contrib/loaders/flash/msp432/msp432p411x.h

   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
   4 *
   5 * Redistribution and use in source and binary forms, with or without
   6 * modification, are permitted provided that the following conditions
   7 * are met:
   8 *
   9 *  Redistributions of source code must retain the above copyright
  10 *  notice, this list of conditions and the following disclaimer.
  11 *
  12 *  Redistributions in binary form must reproduce the above copyright
  13 *  notice, this list of conditions and the following disclaimer in the
  14 *  documentation and/or other materials provided with the
  15 *  distribution.
  16 *
  17 *  Neither the name of Texas Instruments Incorporated nor the names of
  18 *  its contributors may be used to endorse or promote products derived
  19 *  from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 *
  33 ******************************************************************************/
  34
  35 #ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432P411X_H
  36 #define OPENOCD_LOADERS_FLASH_MSP432_MSP432P411X_H
  37
  38 #include <stdint.h>
  39
  40 #ifdef __cplusplus
  41 extern "C" {
  42 #endif
  43
  44 /* Available Peripherals */
  45 #define __MCU_HAS_FLCTL_A__  /* Module FLCTL_A is available */
  46 #define __MCU_HAS_SYSCTL_A__ /* Module SYSCTL_A is available */
  47
  48 /* Device and Peripheral Memory Map */
  49 #define FLASH_BASE        ((uint32_t)0x00000000)     /* Flash memory address */
  50 #define PERIPH_BASE       ((uint32_t)0x40000000)     /* Peripherals address */
  51 #define CS_BASE           (PERIPH_BASE + 0x00010400) /* Address of CS regs. */
  52 #define PCM_BASE          (PERIPH_BASE + 0x00010000) /* Address of PCM regs. */
  53 #define RTC_C_BASE        (PERIPH_BASE + 0x00004400) /* Address of RTC_C regs */
  54 #define TLV_BASE          ((uint32_t)0x00201000)     /* Address of TLV regs. */
  55 #define WDT_A_BASE        (PERIPH_BASE + 0x00004800) /* Address of WDT_A regs */
  56 #define BITBAND_PERI_BASE ((uint32_t)(0x42000000))
  57
  58 /*
  59  * Peripherals with 8-bit or 16-bit register access allow only 8-bit or
  60  * 16-bit bit band access, so cast to 8 bit always
  61  */
  62 #define BITBAND_PERI(x, b) (*((volatile  uint8_t *) (BITBAND_PERI_BASE + \
  63         (((uint32_t)(uint32_t *)&(x)) - PERIPH_BASE)*32 + (b)*4)))
  64
  65 /* Register map for CLock Signal peripheral (CS) */
  66 struct cs {
  67         volatile uint32_t KEY;  /* Key Register */
  68         volatile uint32_t CTL0; /* Control 0 Register */
  69         volatile uint32_t CTL1; /* Control 1 Register */
  70         volatile uint32_t CTL2; /* Control 2 Register */
  71         volatile uint32_t CTL3; /* Control 3 Register */
  72 };
  73
  74 /* Register map for Power Control Module peripheral (PCM) */
  75 struct pcm {
  76         volatile uint32_t CTL0;   /* Control 0 Register */
  77         volatile uint32_t CTL1;   /* Control 1 Register */
  78         volatile uint32_t IE;     /* Interrupt Enable Register */
  79         volatile uint32_t IFG;    /* Interrupt Flag Register */
  80         volatile uint32_t CLRIFG; /* Clear Interrupt Flag Register */
  81 };
  82
  83 /* Register map for Real-Time Clock peripheral (RTC_C) */
  84 struct rtc_c {
  85         volatile uint16_t CTL0;    /* RTCCTL0 Register */
  86         volatile uint16_t CTL13;   /* RTCCTL13 Register */
  87         volatile uint16_t OCAL;    /* RTCOCAL Register */
  88         volatile uint16_t TCMP;    /* RTCTCMP Register */
  89         volatile uint16_t PS0CTL;  /* RTC Prescale Timer 0 Control Register */
  90         volatile uint16_t PS1CTL;  /* RTC Prescale Timer 1 Control Register */
  91         volatile uint16_t PS;      /* Real-Time Clock Prescale Timer Register */
  92         volatile uint16_t IV;      /* Real-Time Clock Interrupt Vector Register */
  93         volatile uint16_t TIM0;    /* RTCTIM0 Register  Hexadecimal Format */
  94         volatile uint16_t TIM1;    /* Real-Time Clock Hour, Day of Week */
  95         volatile uint16_t DATE;    /* RTCDATE - Hexadecimal Format */
  96         volatile uint16_t YEAR;    /* RTCYEAR Register - Hexadecimal Format */
  97         volatile uint16_t AMINHR;  /* RTCMINHR - Hexadecimal Format */
  98         volatile uint16_t ADOWDAY; /* RTCADOWDAY - Hexadecimal Format */
  99         volatile uint16_t BIN2BCD; /* Binary-to-BCD Conversion Register */
 100         volatile uint16_t BCD2BIN; /* BCD-to-Binary Conversion Register */
 101 };
 102
 103 /* Register map for Watchdog Timer peripheral (WDT_A) */
 104 struct wdt_a {
 105         uint16_t RESERVED0[6];
 106         volatile uint16_t CTL; /* Watchdog Timer Control Register */
 107 };
 108
 109 /* Peripheral Declarations */
 110 #define CS    ((struct cs *) CS_BASE)
 111 #define PCM   ((struct pcm *) PCM_BASE)
 112 #define RTC_C ((struct rtc_c *) RTC_C_BASE)
 113 #define WDT_A ((struct wdt_a *) WDT_A_BASE)
 114
 115 /* Peripheral Register Bit Definitions */
 116
 117 /* DCORSEL Bit Mask */
 118 #define CS_CTL0_DCORSEL_MASK  ((uint32_t)0x00070000)
 119 /* Nominal DCO Frequency Range (MHz): 2 to 4 */
 120 #define CS_CTL0_DCORSEL_1     ((uint32_t)0x00010000)
 121 /* Nominal DCO Frequency Range (MHz): 16 to 32 */
 122 #define CS_CTL0_DCORSEL_4     ((uint32_t)0x00040000)
 123 /* CS control key value */
 124 #define CS_KEY_VAL            ((uint32_t)0x0000695A)
 125
 126 /* AMR Bit Mask */
 127 #define PCM_CTL0_AMR_MASK     ((uint32_t)0x0000000F)
 128 /* LPMR Bit Mask */
 129 #define PCM_CTL0_LPMR_MASK    ((uint32_t)0x000000F0)
 130 /* LPM3.5. Core voltage setting 0. */
 131 #define PCM_CTL0_LPMR_10      ((uint32_t)0x000000A0)
 132 /* LPM4.5 */
 133 #define PCM_CTL0_LPMR_12      ((uint32_t)0x000000C0)
 134 /* CPM Bit Offset */
 135 #define PCM_CTL0_CPM_OFS      (8)
 136 /* CPM Bit Mask */
 137 #define PCM_CTL0_CPM_MASK     ((uint32_t)0x00003F00)
 138 /* PCMKEY Bit Mask */
 139 #define PCM_CTL0_KEY_MASK     ((uint32_t)0xFFFF0000)
 140 /* PMR_BUSY Bit Offset */
 141 #define PCM_CTL1_PMR_BUSY_OFS (8)
 142
 143 /* RTCKEY Bit Offset */
 144 #define RTC_C_CTL0_KEY_OFS    (8)
 145 /* RTCKEY Bit Mask */
 146 #define RTC_C_CTL0_KEY_MASK   ((uint16_t)0xFF00)
 147 /* RTCHOLD Bit Offset */
 148 #define RTC_C_CTL13_HOLD_OFS  (6)
 149 /* RTC_C Key Value for RTC_C write access */
 150 #define RTC_C_KEY             ((uint16_t)0xA500)
 151
 152 /* Watchdog timer hold */
 153 #define WDT_A_CTL_HOLD        ((uint16_t)0x0080)
 154 /* WDT Key Value for WDT write access */
 155 #define WDT_A_CTL_PW          ((uint16_t)0x5A00)
 156
 157 /* Address of BSL API table */
 158 #define BSL_API_TABLE_ADDR    ((uint32_t)0x00202000)
 159
 160 #ifdef __cplusplus
 161 }
 162 #endif
 163
 164 #endif /* OPENOCD_LOADERS_FLASH_MSP432_MSP432P411X_H */