contrib/loaders/flash/stm32/stm32h7x.S

   1 /***************************************************************************
   2  *   Copyright (C) 2017 by STMicroelectronics                              *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.                                        *
  17  ***************************************************************************/
  18
  19         .text
  20         .syntax unified
  21         .cpu cortex-m7
  22         .thumb
  23
  24 /*
  25  * Code limitations:
  26  * The workarea must have size multiple of 4 bytes, since R/W
  27  * operations are all at 32 bits.
  28  * The workarea must be big enough to contain 32 bytes of data,
  29  * thus the minimum size is (rp, wp, data) = 4 + 4 + 32 = 40 bytes.
  30  * To benefit from concurrent host write-to-buffer and target
  31  * write-to-flash, the workarea must be way bigger than the minimum.
  32  */
  33
  34 /*
  35  * Params :
  36  * r0 = workarea start, status (out)
  37  * r1 = workarea end
  38  * r2 = target address
  39  * r3 = count (256 bit words)
  40  * r4 = flash reg base
  41  *
  42  * Clobbered:
  43  * r5 - rp
  44  * r6 - wp, status, tmp
  45  * r7 - loop index, tmp
  46  */
  47
  48 #define STM32_FLASH_CR_OFFSET   0x0C    /* offset of CR register in FLASH struct */
  49 #define STM32_FLASH_SR_OFFSET   0x10    /* offset of SR register in FLASH struct */
  50 #define STM32_CR_PROG                   0x00000032      /* PSIZE64 | PG */
  51 #define STM32_SR_BUSY_MASK              0x00000001      /* BSY */
  52 #define STM32_SR_ERROR_MASK             0x03ee0000      /* DBECCERR | SNECCERR | RDSERR | RDPERR | OPERR
  53                                                                                            | INCERR | STRBERR | PGSERR | WRPERR */
  54
  55         .thumb_func
  56         .global _start
  57 _start:
  58         ldr             r5, [r0, #4]            /* read rp */
  59
  60 wait_fifo:
  61         ldr             r6, [r0, #0]            /* read wp */
  62         cbz             r6, exit                        /* abort if wp == 0, status = 0 */
  63         subs    r6, r6, r5                      /* number of bytes available for read in r6 */
  64         ittt    mi                                      /* if wrapped around */
  65         addmi   r6, r1                          /* add size of buffer */
  66         submi   r6, r0
  67         submi   r6, #8
  68         cmp             r6, #32                         /* wait until 32 bytes are available */
  69         bcc             wait_fifo
  70
  71         mov             r6, #STM32_CR_PROG
  72         str             r6, [r4, #STM32_FLASH_CR_OFFSET]
  73
  74         mov             r7, #8                          /* program by 8 words = 32 bytes */
  75 write_flash:
  76         ldr             r6, [r5], #0x04         /* read one word from src, increment ptr */
  77         str             r6, [r2], #0x04         /* write one word to dst, increment ptr */
  78         dsb
  79         cmp             r5, r1                          /* if rp >= end of buffer ... */
  80         it              cs
  81         addcs   r5, r0, #8                      /* ... then wrap at buffer start */
  82         subs    r7, r7, #1                      /* decrement loop index */
  83         bne             write_flash                     /* loop if not done */
  84
  85 busy:
  86         ldr             r6, [r4, #STM32_FLASH_SR_OFFSET]
  87         tst             r6, #STM32_SR_BUSY_MASK
  88         bne             busy                            /* operation in progress, wait ... */
  89
  90         ldr             r7, =STM32_SR_ERROR_MASK
  91         tst             r6, r7
  92         bne             error                           /* fail... */
  93
  94         str             r5, [r0, #4]            /* store rp */
  95         subs    r3, r3, #1                      /* decrement count */
  96         bne             wait_fifo                       /* loop if not done */
  97         b               exit
  98
  99 error:
 100         movs    r7, #0
 101         str             r7, [r0, #4]            /* set rp = 0 on error */
 102
 103 exit:
 104         mov             r0, r6                          /* return status in r0 */
 105         bkpt    #0x00
 106
 107         .pool
 108