0dd1223192ea10310cf0b9dacec5104f878108ba
[openocd.git] / contrib / loaders / flash / stm32f2x.S
1 /***************************************************************************
2 * Copyright (C) 2010 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2011 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
22 ***************************************************************************/
23
24 .text
25 .syntax unified
26 .cpu cortex-m3
27 .thumb
28 .thumb_func
29
30 /*
31 * Params :
32 * r0 = workarea start, status (out)
33 * r1 = workarea end
34 * r2 = target address
35 * r3 = count (16bit words)
36 * r4 = flash base
37 *
38 * Clobbered:
39 * r6 - temp
40 * r7 - rp
41 * r8 - wp, tmp
42 */
43
44 #define STM32_FLASH_CR_OFFSET 0x10 /* offset of CR register in FLASH struct */
45 #define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register in FLASH struct */
46
47 wait_fifo:
48 ldr r8, [r0, #0] /* read wp */
49 cmp r8, #0 /* abort if wp == 0 */
50 beq exit
51 ldr r7, [r0, #4] /* read rp */
52 cmp r7, r8 /* wait until rp != wp */
53 beq wait_fifo
54
55 ldr r6, STM32_PROG16
56 str r6, [r4, #STM32_FLASH_CR_OFFSET]
57 ldrh r6, [r7], #0x02 /* read one half-word from src, increment ptr */
58 strh r6, [r2], #0x02 /* write one half-word from src, increment ptr */
59 dsb
60 busy:
61 ldr r6, [r4, #STM32_FLASH_SR_OFFSET]
62 tst r6, #0x10000 /* BSY (bit16) == 1 => operation in progress */
63 bne busy /* wait more... */
64 tst r6, #0xf0 /* PGSERR | PGPERR | PGAERR | WRPERR */
65 bne error /* fail... */
66
67 cmp r7, r1 /* wrap rp at end of buffer */
68 it cs
69 addcs r7, r0, #8 /* skip loader args */
70 str r7, [r0, #4] /* store rp */
71 subs r3, r3, #1 /* decrement halfword count */
72 cbz r3, exit /* loop if not done */
73 b wait_fifo
74 error:
75 movs r1, #0
76 str r1, [r0, #4] /* set rp = 0 on error */
77 exit:
78 mov r0, r6 /* return status in r0 */
79 bkpt #0x00
80
81 STM32_PROG16: .word 0x101 /* PG | PSIZE_16*/

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