flash: Added support for Freescale Kinetis KE family.
[openocd.git] / contrib / loaders / flash / stm32l4x.S
1 /***************************************************************************
2 * Copyright (C) 2010 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2011 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
7 * *
8 * Copyright (C) 2015 Uwe Bonnes *
9 * bon@elektron.ikp.physik.tu-darmstadt.de *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc. *
24 ***************************************************************************/
25
26 .text
27 .syntax unified
28 .cpu cortex-m4
29 .thumb
30 .thumb_func
31
32 /* To assemble:
33 * arm-none-eabi-gcc -c stm32l4x.S
34 *
35 * To disassemble:
36 * arm-none-eabi-objdump -o stm32l4x.o
37 *
38 * To generate binary file:
39 * arm-none-eabi-objcopy -O binary stm32l4x.o stm32l4_flash_write_code.bin
40 *
41 * To generate include file:
42 * xxd -i stm32l4_flash_write_code.bin
43 */
44
45 /*
46 * Params :
47 * r0 = workarea start, status (out)
48 * r1 = workarea end
49 * r2 = target address
50 * r3 = count (64bit words)
51 * r4 = flash base
52 *
53 * Clobbered:
54 * r5 - rp
55 * r6 - temp
56 * r8 - wp, tmp
57 */
58
59 #define STM32_FLASH_CR_OFFSET 0x14 /* offset of CR register in FLASH struct */
60 #define STM32_FLASH_SR_OFFSET 0x10 /* offset of SR register in FLASH struct */
61
62 wait_fifo:
63 ldr r8, [r0, #0] /* read wp */
64 cmp r8, #0 /* abort if wp == 0 */
65 beq exit
66 ldr r5, [r0, #4] /* read rp */
67 subs r6, r8, r5 /* number of bytes available for read in r6*/
68 cmp r6, #7 /* wait until 8 bytes are available */
69 bcc wait_fifo
70
71 ldr r6, STM32_PROG
72 str r6, [r4, #STM32_FLASH_CR_OFFSET]
73 ldr r6, [r5], #0x04 /* read one word from src, increment ptr */
74 str r6, [r2], #0x04 /* write one word to dst, increment ptr */
75 ldr r6, [r5], #0x04 /* read one word from src, increment ptr */
76 str r6, [r2], #0x04 /* write one word to dst, increment ptr */
77 dsb
78 busy:
79 ldr r6, [r4, #STM32_FLASH_SR_OFFSET]
80 tst r6, #0x10000 /* BSY (bit16) == 1 => operation in progress */
81 bne busy /* wait more... */
82 tst r6, #0xfa /* PGSERR | PGPERR | PGAERR | WRPERR | PROGERR*/
83 bne error /* fail... */
84
85 cmp r5, r1 /* wrap rp at end of buffer */
86 it cs
87 addcs r5, r0, #8 /* skip loader args */
88 str r5, [r0, #4] /* store rp */
89 subs r3, r3, #1 /* decrement dword count */
90 cbz r3, exit /* loop if not done */
91 b wait_fifo
92 error:
93 movs r1, #0
94 str r1, [r0, #4] /* set rp = 0 on error */
95 exit:
96 mov r0, r6 /* return status in r0 */
97 bkpt #0x00
98
99 STM32_PROG: .word 0x1 /* PG */

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