contrib/loaders/reset/espressif/esp32s3/esp32s3_cpu_reset_handler.S

   1 /***************************************************************************
   2  *   Reset stub used by esp32s3 target                                     *
   3  *   Copyright (C) 2020 Espressif Systems (Shanghai) Co. Ltd.              *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18
  19 #define RTC_CNTL_RESET_STATE_REG            0x60008038
  20 #define RTC_CNTL_RESET_STATE_DEF            0x3000
  21 #define RTC_CNTL_CLK_CONF_REG               0x60008074
  22 #define RTC_CNTL_CLK_CONF_DEF               0x1583218
  23 #define RTC_CNTL_STORE4_REG                 0x600080C0
  24 #define RTC_CNTL_STORE5_REG                 0x600080C4
  25 #define WDT_WKEY_VALUE                      0x50D83AA1
  26 #define TIMG0_WDTWPROTECT_REG               0x6001F064
  27 #define TIMG0_WDTCONFIG0_REG                0x6001F048
  28 #define TIMG1_WDTWPROTECT_REG               0x60020064
  29 #define TIMG1_WDTCONFIG0_REG                0x60020048
  30 #define RTC_CNTL_WDTCONFIG0_REG             0x60008094
  31 #define RTC_CNTL_WDTWPROTECT_REG            0x600080AC
  32 #define RTC_CNTL_OPTIONS0_REG               0x60008000
  33 #define RTC_CNTL_OPTIONS0_DEF               0x1C00A000
  34 #define RTC_CNTL_SW_SYS_RST                 0x80000000
  35 #define RTC_CNTL_DIG_PWC_REG                0x60008090
  36 #define RTC_CNTL_SWD_CONF_REG               0x600080B0
  37 #define RTC_CNTL_SWD_CONF_VAL               0x84B00000
  38 #define RTC_CNTL_SWD_WPROTECT_REG           0x600080B4
  39 #define RTC_CNTL_SWD_WKEY_VALUE             0x8F1D312A
  40 #define SYSTEM_CORE_1_CONTROL_0_REG         0x600C0000
  41 #define SYSTEM_CONTROL_CORE_1_RESETING      0x4
  42 #define SYSTEM_CONTROL_CORE_1_CLKGATE_EN    0x2
  43 #define SYSTEM_CORE_1_CONTROL_1_REG         0x600C0004
  44
  45
  46 /* This stub is copied to RTC_SLOW_MEM by OpenOCD, and the CPU starts executing
  47  * it instead of the ROM code (0x40000400). This stub disables watchdogs and
  48  * goes into a loop.
  49  * OpenOCD will then halt the target and perform CPU reset using OCD.
  50  */
  51
  52
  53 /* Has to be at offset 0. This is the entry point of the CPU, once
  54  * RTC_CNTL_PROCPU_STAT_VECTOR_SEL is cleared.
  55  * CPU will come here after the system reset, triggered by RTC_CNTL_SW_SYS_RST.
  56  */
  57     .global     cpu_at_start_handler
  58     .type       cpu_at_start_handler,@function
  59     .align      4
  60 cpu_at_start_handler:
  61     j start
  62
  63
  64 /* Has to be at offset 4. Once the stub code has been uploaded into RTC Slow
  65  * memory, OpenOCD will set the PC to this address, and resume execution.
  66  * The stub will then jump to 'reset' label and perform the reset.
  67  */
  68     .global     cpu_reset_handler
  69     .type       cpu_reset_handler,@function
  70     .align      4
  71 cpu_reset_handler:
  72     j reset
  73
  74     .align 4
  75     .literal_position
  76
  77     .align 4
  78 reset:
  79     /* Use a5 as a zero register */
  80     xor a5, a5, a5
  81     /* Select static reset vector 0 (XCHAL_RESET_VECTOR0_VADDR, 0x50000000) */
  82     movi a4, RTC_CNTL_RESET_STATE_REG
  83     s32i a5, a4, 0
  84     /* Set some clock-related RTC registers to the default values */
  85     movi a4, RTC_CNTL_STORE4_REG
  86     s32i a5, a4, 0
  87     movi a4, RTC_CNTL_STORE5_REG
  88     s32i a5, a4, 0
  89     movi a4, RTC_CNTL_DIG_PWC_REG
  90     s32i a5, a4, 0
  91     movi a4, RTC_CNTL_CLK_CONF_REG
  92     movi a3, RTC_CNTL_CLK_CONF_DEF
  93     s32i a3, a4, 0
  94     /* Reset the digital part of the chip (RTC controller doesn't get reset) */
  95     movi a3, (RTC_CNTL_OPTIONS0_DEF | RTC_CNTL_SW_SYS_RST)
  96     movi a4, RTC_CNTL_OPTIONS0_REG
  97     s32i a3, a4, 0
  98     /* Doesn't reach beyond this instruction */
  99
 100     .align 4
 101 start:
 102     /* If running on the APP CPU, skip directly to the parking loop */
 103     rsr.prid a6
 104     extui a6, a6, 1, 1
 105     bnez a6, parking_loop
 106
 107     /* Use a5 as a zero register */
 108     xor a5, a5, a5
 109     /* Disable the watchdogs */
 110     movi a3, WDT_WKEY_VALUE
 111     movi a4, RTC_CNTL_WDTWPROTECT_REG
 112     s32i.n a3, a4, 0
 113     movi a4, TIMG0_WDTWPROTECT_REG
 114     s32i.n a3, a4, 0
 115     movi a4, TIMG1_WDTWPROTECT_REG
 116     s32i.n a3, a4, 0
 117     movi a4, RTC_CNTL_WDTCONFIG0_REG
 118     s32i.n a5, a4, 0
 119     movi a4, TIMG0_WDTCONFIG0_REG
 120     s32i.n a5, a4, 0
 121     movi a4, TIMG1_WDTCONFIG0_REG
 122     s32i.n a5, a4, 0
 123     movi a4, RTC_CNTL_SWD_WPROTECT_REG
 124     movi a3, RTC_CNTL_SWD_WKEY_VALUE
 125     s32i.n a3, a4, 0
 126     movi a4, RTC_CNTL_SWD_CONF_REG
 127     movi a3, RTC_CNTL_SWD_CONF_VAL
 128     s32i.n a3, a4, 0
 129     /* Clear APP_CPU boot address */
 130     movi a4, SYSTEM_CORE_1_CONTROL_1_REG
 131     s32i.n a5, a4, 0
 132     /* Clear APP_CPU clock gating */
 133     movi a4, SYSTEM_CORE_1_CONTROL_0_REG
 134     movi a3, SYSTEM_CONTROL_CORE_1_CLKGATE_EN
 135     s32i.n a3, a4, 0
 136     /* Set and clear APP_CPU reset */
 137     movi a4, SYSTEM_CORE_1_CONTROL_0_REG
 138     movi a3, SYSTEM_CONTROL_CORE_1_RESETING
 139     s32i.n a3, a4, 0
 140     s32i.n a5, a4, 0
 141     /* Restore the reset vector to ROM */
 142     movi a4, RTC_CNTL_RESET_STATE_REG
 143     movi a3, RTC_CNTL_RESET_STATE_DEF
 144     s32i.n a3, a4, 0
 145
 146
 147 parking_loop:
 148     /* PRO and APP CPU will be in this loop, until OpenOCD
 149      * finds the JTAG taps and puts the CPUs into debug mode.
 150      */
 151     waiti 0
 152     j parking_loop