doc/manual/primer/jtag.txt

   1 /** @page primerjtag OpenOCD JTAG Primer
   2
   3 JTAG is unnecessarily confusing, because JTAG is often confused with
   4 boundary scan, which is just one of its possible functions.
   5
   6 JTAG is simply a communication interface designed to allow communication
   7 to functions contained on devices, for the designed purposes of
   8 initialisation, programming, testing, debugging, and anything else you
   9 want to use it for (as a chip designer).
  10
  11 Think of JTAG as I2C for testing.  It doesn't define what it can do,
  12 just a logical interface that allows a uniform channel for communication.
  13
  14 See @par
  15         http://en.wikipedia.org/wiki/Joint_Test_Action_Group
  16
  17 @image html jtag-state-machine-large.png
  18
  19 The first page (among other things) shows a logical representation
  20 describing how multiple devices are wired up using JTAG.  JTAG does not
  21 specify, data rates or interface levels (3.3V/1.8V, etc) each device can
  22 support different data rates/interface logic levels.  How to wire them
  23 in a compatible way is an exercise for an engineer.
  24
  25 Basically TMS controls which shift register is placed on the device,
  26 between TDI and TDO.  The second diagram shows the state transitions on
  27 TMS which will select different shift registers.
  28
  29 The first thing you need to do is reset the state machine, because when
  30 you connect to a chip you do not know what state the controller is in,you need
  31 to clock TMS as 1, at least 5 times.  This will put you into "Test Logic
  32 Reset" State.  Knowing this, you can, once reset, then track what each
  33 transition on TMS will do, and hence know what state the JTAG state
  34 machine is in.
  35
  36 There are 2 "types" of shift registers.  The Instruction shift register
  37 and the data shift register.  The sizes of these are undefined, and can
  38 change from chip to chip.  The Instruction register is used to select
  39 which Data register/data register function is used, and the data
  40 register is used to read data from that function or write data to it.
  41
  42 Each of the states control what happens to either the data register or
  43 instruction register.
  44
  45 For example, one of the data registers will be known as "bypass" this is
  46 (usually) a single bit which has no function and is used to bypass the
  47 chip.  Assume we have 3 identical chips, wired up like the picture(wikipedia)
  48 and each has a 3 bits instruction register, and there are 2 known
  49 instructions (110 = bypass, 010 = "some other function") if we want to use
  50 "some other function", on the second chip in the line, and not change
  51 the other chips we would do the following transitions.
  52
  53 From Test Logic Reset, TMS goes:
  54
  55   0 1 1 0 0
  56
  57 which puts every chip in the chain into the "Shift IR state"
  58 Then (while holding TMS as 0) TDI goes:
  59
  60   0 1 1  0 1 0  0 1 1
  61
  62 which puts the following values in the instruction shift register for
  63 each chip [110] [010] [110]
  64
  65 The order is reversed, because we shift out the least significant bit
  66 first.  Then we transition TMS:
  67
  68   1 1 1 0 0
  69
  70 which puts us in the "Shift DR state".
  71
  72 Now when we clock data onto TDI (again while holding TMS to 0) , the
  73 data shifts through the data registers, and because of the instruction
  74 registers we selected ("some other function" has 8 bits in its data
  75 register), our total data register in the chain looks like this:
  76
  77   0 00000000 0
  78
  79 The first and last bit are in the "bypassed" chips, so values read from
  80 them are irrelevant and data written to them is ignored.  But we need to
  81 write bits for those registers, because they are in the chain.
  82
  83 If we wanted to write 0xF5 to the data register we would clock out of
  84 TDI (holding TMS to 0):
  85
  86   0 1 0 1 0 1 1 1 1 0
  87
  88 Again, we are clocking the least-significant bit first.  Then we would
  89 clock TMS:
  90
  91   1 1 0
  92
  93 which updates the selected data register with the value 0xF5 and returns
  94 us to run test idle.
  95
  96 If we needed to read the data register before over-writing it with F5,
  97 no sweat, that's already done, because the TDI/TDO are set up as a
  98 circular shift register, so if you write enough bits to fill the shift
  99 register, you will receive the "captured" contents of the data registers
 100 simultaneously on TDO.
 101
 102 That's JTAG in a nutshell.  On top of this, you need to get specs for
 103 target chips and work out what the various instruction registers/data
 104 registers do, so you can actually do something useful.  That's where it
 105 gets interesting.  But in and of itself, JTAG is actually very simple.
 106
 107 @section primerjtag More Reading
 108
 109 A separate primer contains information about @subpage primerjtagbs for
 110 developers that want to extend OpenOCD for such purposes.
 111
 112  */
 113 /** @page primerjtagbs JTAG Boundary Scan Primer
 114
 115 The following page provides an introduction on JTAG that focuses on its
 116 boundary scan capabilities: @par
 117 http://www.engr.udayton.edu/faculty/jloomis/ece446/notes/jtag/jtag1.html
 118
 119 OpenOCD does not presently have clear means of using JTAG for boundary
 120 scan testing purposes; however, some developers have explored the
 121 possibilities.  The page contains information that may be useful to
 122 those wishing to implement boundary scan capabilities in OpenOCD.
 123
 124 @section primerbsdl The BSDL Language
 125
 126 For more information on the Boundary Scan Description Language (BSDL),
 127 the following page provides a good introduction: @par
 128 http://www.radio-electronics.com/info/t_and_m/boundaryscan/bsdl.php
 129
 130 @section primerbsdlvendors Vendor BSDL Files
 131
 132 NXP LPC: @par
 133 http://www.standardics.nxp.com/support/models/lpc2000/
 134
 135 Freescale PowerPC: @par
 136 http://www.freescale.com/webapp/sps/site/overview.jsp?code=DRPPCBSDLFLS
 137
 138 Freescale i.MX1 (too old): @par
 139 http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX1&nodeId=0162468rH311432973ZrDR&fpsp=1&tab=Design_Tools_Tab
 140
 141 Renesas R32C/117: @par
 142 http://sg.renesas.com/fmwk.jsp?cnt=r32c116_7_8_root.jsp&fp=/products/mpumcu/m16c_family/r32c100_series/r32c116_7_8_group/
 143 - The device page does not come with BSDL file; you have to register to
 144   download them. @par
 145   http://www.corelis.com/support/BSDL.htm
 146
 147 TI links theirs right off the generic page for each chip;
 148 this may be the case for other vendors as well.  For example:
 149
 150 - DaVinci DM355 -- http://www.ti.com/litv/zip/sprm262b
 151 - DaVinci DM6446
 152   - 2.1 silicon -- http://www.ti.com/litv/zip/sprm325a
 153   - older silicon -- http://www.ti.com/litv/zip/sprm203
 154 - OMAP 3530
 155   - CBB package -- http://www.ti.com/litv/zip/sprm315b
 156     - 515 ball s-PGBA, POP, 0.4mm pitch
 157   - CUS package -- http://www.ti.com/litv/zip/sprm314a
 158     - 515 ball s-PGBA, POP, 0.5mm pitch
 159   - CBC package -- http://www.ti.com/litv/zip/sprm346
 160     - 423 ball s-PGBA, 0.65mm pitch
 161
 162 Many other files are available in the "Semiconductor Manufacturer's BSDL
 163 files" section of the following site: @par
 164 http://www.freelabs.com/~whitis/electronics/jtag/
 165
 166  */
 167 /** @file
 168 This file contains the @ref primerjtag and @ref primerjtagbs page.
 169  */