ARM: "armv4_5" command prefix becomes "arm"
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{}
24 @item Copyright @copyright{} 2008 Oyvind Harboe @email{}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{}
26 @item Copyright @copyright{} 2009 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developers
64 * JTAG Hardware Dongles:: JTAG Hardware Dongles
65 * About JIM-Tcl:: About JIM-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Interface - Dongle Configuration:: Interface - Dongle Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * TFTP:: TFTP
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on:
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
94 @end menu
96 @node About
97 @unnumbered About
98 @cindex about
100 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
101 University of Applied Sciences Augsburg (@uref{}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
104 around the world.
106 @section What is OpenOCD?
107 @cindex TAP
108 @cindex JTAG
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
112 devices.
114 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
115 with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
116 A @dfn{TAP} is a ``Test Access Port'', a module which processes
117 special instructions and data. TAPs are daisy-chained within and
118 between chips and boards.
120 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
121 based, parallel port based, and other standalone boxes that run
122 OpenOCD internally. @xref{JTAG Hardware Dongles}.
124 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
125 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
126 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
127 debugged via the GDB protocol.
129 @b{Flash Programing:} Flash writing is supported for external CFI
130 compatible NOR flashes (Intel and AMD/Spansion command set) and several
131 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
132 STM32x). Preliminary support for various NAND flash controllers
133 (LPC3180, Orion, S3C24xx, more) controller is included.
135 @section OpenOCD Web Site
137 The OpenOCD web site provides the latest public news from the community:
139 @uref{}
141 @section Latest User's Guide:
143 The user's guide you are now reading may not be the latest one
144 available. A version for more recent code may be available.
145 Its HTML form is published irregularly at:
147 @uref{}
149 PDF form is likewise published at:
151 @uref{}
153 @section OpenOCD User's Forum
155 There is an OpenOCD forum (phpBB) hosted by SparkFun:
157 @uref{}
160 @node Developers
161 @chapter OpenOCD Developer Resources
162 @cindex developers
164 If you are interested in improving the state of OpenOCD's debugging and
165 testing support, new contributions will be welcome. Motivated developers
166 can produce new target, flash or interface drivers, improve the
167 documentation, as well as more conventional bug fixes and enhancements.
169 The resources in this chapter are available for developers wishing to explore
170 or expand the OpenOCD source code.
172 @section OpenOCD GIT Repository
174 During the 0.3.x release cycle, OpenOCD switched from Subversion to
175 a GIT repository hosted at SourceForge. The repository URL is:
177 @uref{git://}
179 You may prefer to use a mirror and the HTTP protocol:
181 @uref{}
183 With standard GIT tools, use @command{git clone} to initialize
184 a local repository, and @command{git pull} to update it.
185 There are also gitweb pages letting you browse the repository
186 with a web browser, or download arbitrary snapshots without
187 needing a GIT client:
189 @uref{}
191 @uref{}
193 The @file{README} file contains the instructions for building the project
194 from the repository or a snapshot.
196 Developers that want to contribute patches to the OpenOCD system are
197 @b{strongly} encouraged to work against mainline.
198 Patches created against older versions may require additional
199 work from their submitter in order to be updated for newer releases.
201 @section Doxygen Developer Manual
203 During the 0.2.x release cycle, the OpenOCD project began
204 providing a Doxygen reference manual. This document contains more
205 technical information about the software internals, development
206 processes, and similar documentation:
208 @uref{}
210 This document is a work-in-progress, but contributions would be welcome
211 to fill in the gaps. All of the source files are provided in-tree,
212 listed in the Doxyfile configuration in the top of the source tree.
214 @section OpenOCD Developer Mailing List
216 The OpenOCD Developer Mailing List provides the primary means of
217 communication between developers:
219 @uref{}
221 Discuss and submit patches to this list.
222 The @file{PATCHES} file contains basic information about how
223 to prepare patches.
226 @node JTAG Hardware Dongles
227 @chapter JTAG Hardware Dongles
228 @cindex dongles
229 @cindex FTDI
230 @cindex wiggler
231 @cindex zy1000
232 @cindex printer port
233 @cindex USB Adapter
234 @cindex RTCK
236 Defined: @b{dongle}: A small device that plugins into a computer and serves as
237 an adapter .... [snip]
239 In the OpenOCD case, this generally refers to @b{a small adapater} one
240 attaches to your computer via USB or the Parallel Printer Port. The
241 execption being the Zylin ZY1000 which is a small box you attach via
242 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
243 require any drivers to be installed on the developer PC. It also has
244 a built in web interface. It supports RTCK/RCLK or adaptive clocking
245 and has a built in relay to power cycle targets remotely.
248 @section Choosing a Dongle
250 There are several things you should keep in mind when choosing a dongle.
252 @enumerate
253 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
254 Does your dongle support it? You might need a level converter.
255 @item @b{Pinout} What pinout does your target board use?
256 Does your dongle support it? You may be able to use jumper
257 wires, or an "octopus" connector, to convert pinouts.
258 @item @b{Connection} Does your computer have the USB, printer, or
259 Ethernet port needed?
260 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
261 @end enumerate
263 @section Stand alone Systems
265 @b{ZY1000} See: @url{} Technically, not a
266 dongle, but a standalone box. The ZY1000 has the advantage that it does
267 not require any drivers installed on the developer PC. It also has
268 a built in web interface. It supports RTCK/RCLK or adaptive clocking
269 and has a built in relay to power cycle targets remotely.
271 @section USB FT2232 Based
273 There are many USB JTAG dongles on the market, many of them are based
274 on a chip from ``Future Technology Devices International'' (FTDI)
275 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
276 See: @url{} for more information.
277 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
278 chips are starting to become available in JTAG adapters.
280 @itemize @bullet
281 @item @b{usbjtag}
282 @* Link @url{}
283 @item @b{jtagkey}
284 @* See: @url{}
285 @item @b{jtagkey2}
286 @* See: @url{}
287 @item @b{oocdlink}
288 @* See: @url{} By Joern Kaipf
289 @item @b{signalyzer}
290 @* See: @url{}
291 @item @b{evb_lm3s811}
292 @* See: @url{} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
293 @item @b{luminary_icdi}
294 @* See: @url{} - Luminary In-Circuit Debug Interface (ICDI) Board, included in the Stellaris LM3S9B90 and LM3S9B92 Evaluation Kits.
295 @item @b{olimex-jtag}
296 @* See: @url{}
297 @item @b{flyswatter}
298 @* See: @url{}
299 @item @b{turtelizer2}
300 @* See:
301 @uref{, Turtelizer 2}, or
302 @url{}
303 @item @b{comstick}
304 @* Link: @url{}
305 @item @b{stm32stick}
306 @* Link @url{}
307 @item @b{axm0432_jtag}
308 @* Axiom AXM-0432 Link @url{}
309 @item @b{cortino}
310 @* Link @url{}
311 @end itemize
313 @section USB JLINK based
314 There are several OEM versions of the Segger @b{JLINK} adapter. It is
315 an example of a micro controller based JTAG adapter, it uses an
316 AT91SAM764 internally.
318 @itemize @bullet
319 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
320 @* Link: @url{}
321 @item @b{SEGGER JLINK}
322 @* Link: @url{}
323 @item @b{IAR J-Link}
324 @* Link: @url{}
325 @end itemize
327 @section USB RLINK based
328 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
330 @itemize @bullet
331 @item @b{Raisonance RLink}
332 @* Link: @url{}
333 @item @b{STM32 Primer}
334 @* Link: @url{}
335 @item @b{STM32 Primer2}
336 @* Link: @url{}
337 @end itemize
339 @section USB Other
340 @itemize @bullet
341 @item @b{USBprog}
342 @* Link: @url{} - which uses an Atmel MEGA32 and a UBN9604
344 @item @b{USB - Presto}
345 @* Link: @url{}
347 @item @b{Versaloon-Link}
348 @* Link: @url{}
350 @item @b{ARM-JTAG-EW}
351 @* Link: @url{}
352 @end itemize
354 @section IBM PC Parallel Printer Port Based
356 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
357 and the MacGraigor Wiggler. There are many clones and variations of
358 these on the market.
360 Note that parallel ports are becoming much less common, so if you
361 have the choice you should probably avoid these adapters in favor
362 of USB-based ones.
364 @itemize @bullet
366 @item @b{Wiggler} - There are many clones of this.
367 @* Link: @url{}
369 @item @b{DLC5} - From XILINX - There are many clones of this
370 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
371 produced, PDF schematics are easily found and it is easy to make.
373 @item @b{Amontec - JTAG Accelerator}
374 @* Link: @url{}
376 @item @b{GW16402}
377 @* Link: @url{}
379 @item @b{Wiggler2}
380 @*@uref{,
381 Improved parallel-port wiggler-style JTAG adapter}
383 @item @b{Wiggler_ntrst_inverted}
384 @* Yet another variation - See the source code, src/jtag/parport.c
386 @item @b{old_amt_wiggler}
387 @* Unknown - probably not on the market today
389 @item @b{arm-jtag}
390 @* Link: Most likely @url{} [another wiggler clone]
392 @item @b{chameleon}
393 @* Link: @url{}
395 @item @b{Triton}
396 @* Unknown.
398 @item @b{Lattice}
399 @* ispDownload from Lattice Semiconductor
400 @url{}
402 @item @b{flashlink}
403 @* From ST Microsystems;
404 @uref{,
405 FlashLINK JTAG programing cable for PSD and uPSD}
407 @end itemize
409 @section Other...
410 @itemize @bullet
412 @item @b{ep93xx}
413 @* An EP93xx based Linux machine using the GPIO pins directly.
415 @item @b{at91rm9200}
416 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
418 @end itemize
420 @node About JIM-Tcl
421 @chapter About JIM-Tcl
422 @cindex JIM Tcl
423 @cindex tcl
425 OpenOCD includes a small ``Tcl Interpreter'' known as JIM-Tcl.
426 This programming language provides a simple and extensible
427 command interpreter.
429 All commands presented in this Guide are extensions to JIM-Tcl.
430 You can use them as simple commands, without needing to learn
431 much of anything about Tcl.
432 Alternatively, can write Tcl programs with them.
434 You can learn more about JIM at its website, @url{}.
436 @itemize @bullet
437 @item @b{JIM vs. Tcl}
438 @* JIM-TCL is a stripped down version of the well known Tcl language,
439 which can be found here: @url{}. JIM-Tcl has far
440 fewer features. JIM-Tcl is a single .C file and a single .H file and
441 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
442 4.2 MB .zip file containing 1540 files.
444 @item @b{Missing Features}
445 @* Our practice has been: Add/clone the real Tcl feature if/when
446 needed. We welcome JIM Tcl improvements, not bloat.
448 @item @b{Scripts}
449 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
450 command interpreter today is a mixture of (newer)
451 JIM-Tcl commands, and (older) the orginal command interpreter.
453 @item @b{Commands}
454 @* At the OpenOCD telnet command line (or via the GDB mon command) one
455 can type a Tcl for() loop, set variables, etc.
456 Some of the commands documented in this guide are implemented
457 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
459 @item @b{Historical Note}
460 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
462 @item @b{Need a crash course in Tcl?}
463 @*@xref{Tcl Crash Course}.
464 @end itemize
466 @node Running
467 @chapter Running
468 @cindex command line options
469 @cindex logfile
470 @cindex directory search
472 The @option{--help} option shows:
473 @verbatim
474 bash$ openocd --help
476 --help | -h display this help
477 --version | -v display OpenOCD version
478 --file | -f use configuration file <name>
479 --search | -s dir to search for config files and scripts
480 --debug | -d set debug level <0-3>
481 --log_output | -l redirect log output to file <name>
482 --command | -c run <command>
483 --pipe | -p use pipes when talking to gdb
484 @end verbatim
486 By default OpenOCD reads the file configuration file @file{openocd.cfg}
487 in the current directory. To specify a different (or multiple)
488 configuration file, you can use the ``-f'' option. For example:
490 @example
491 openocd -f config1.cfg -f config2.cfg -f config3.cfg
492 @end example
494 OpenOCD starts by processing the configuration commands provided
495 on the command line or in @file{openocd.cfg}.
496 @xref{Configuration Stage}.
497 At the end of the configuration stage it verifies the JTAG scan
498 chain defined using those commands; your configuration should
499 ensure that this always succeeds.
500 Normally, OpenOCD then starts running as a daemon.
501 Alternatively, commands may be used to terminate the configuration
502 stage early, perform work (such as updating some flash memory),
503 and then shut down without acting as a daemon.
505 Once OpenOCD starts running as a daemon, it waits for connections from
506 clients (Telnet, GDB, Other) and processes the commands issued through
507 those channels.
509 If you are having problems, you can enable internal debug messages via
510 the ``-d'' option.
512 Also it is possible to interleave JIM-Tcl commands w/config scripts using the
513 @option{-c} command line switch.
515 To enable debug output (when reporting problems or working on OpenOCD
516 itself), use the @option{-d} command line switch. This sets the
517 @option{debug_level} to "3", outputting the most information,
518 including debug messages. The default setting is "2", outputting only
519 informational messages, warnings and errors. You can also change this
520 setting from within a telnet or gdb session using @command{debug_level
521 <n>} (@pxref{debug_level}).
523 You can redirect all output from the daemon to a file using the
524 @option{-l <logfile>} switch.
526 Search paths for config/script files can be added to OpenOCD by using
527 the @option{-s <search>} switch. The current directory and the OpenOCD
528 target library is in the search path by default.
530 For details on the @option{-p} option. @xref{Connecting to GDB}.
532 Note! OpenOCD will launch the GDB & telnet server even if it can not
533 establish a connection with the target. In general, it is possible for
534 the JTAG controller to be unresponsive until the target is set up
535 correctly via e.g. GDB monitor commands in a GDB init script.
537 @node OpenOCD Project Setup
538 @chapter OpenOCD Project Setup
540 To use OpenOCD with your development projects, you need to do more than
541 just connecting the JTAG adapter hardware (dongle) to your development board
542 and then starting the OpenOCD server.
543 You also need to configure that server so that it knows
544 about that adapter and board, and helps your work.
546 @section Hooking up the JTAG Adapter
548 Today's most common case is a dongle with a JTAG cable on one side
549 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
550 and a USB cable on the other.
551 Instead of USB, some cables use Ethernet;
552 older ones may use a PC parallel port, or even a serial port.
554 @enumerate
555 @item @emph{Start with power to your target board turned off},
556 and nothing connected to your JTAG adapter.
557 If you're particularly paranoid, unplug power to the board.
558 It's important to have the ground signal properly set up,
559 unless you are using a JTAG adapter which provides
560 galvanic isolation between the target board and the
561 debugging host.
563 @item @emph{Be sure it's the right kind of JTAG connector.}
564 If your dongle has a 20-pin ARM connector, you need some kind
565 of adapter (or octopus, see below) to hook it up to
566 boards using 14-pin or 10-pin connectors ... or to 20-pin
567 connectors which don't use ARM's pinout.
569 In the same vein, make sure the voltage levels are compatible.
570 Not all JTAG adapters have the level shifters needed to work
571 with 1.2 Volt boards.
573 @item @emph{Be certain the cable is properly oriented} or you might
574 damage your board. In most cases there are only two possible
575 ways to connect the cable.
576 Connect the JTAG cable from your adapter to the board.
577 Be sure it's firmly connected.
579 In the best case, the connector is keyed to physically
580 prevent you from inserting it wrong.
581 This is most often done using a slot on the board's male connector
582 housing, which must match a key on the JTAG cable's female connector.
583 If there's no housing, then you must look carefully and
584 make sure pin 1 on the cable hooks up to pin 1 on the board.
585 Ribbon cables are frequently all grey except for a wire on one
586 edge, which is red. The red wire is pin 1.
588 Sometimes dongles provide cables where one end is an ``octopus'' of
589 color coded single-wire connectors, instead of a connector block.
590 These are great when converting from one JTAG pinout to another,
591 but are tedious to set up.
592 Use these with connector pinout diagrams to help you match up the
593 adapter signals to the right board pins.
595 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
596 A USB, parallel, or serial port connector will go to the host which
597 you are using to run OpenOCD.
598 For Ethernet, consult the documentation and your network administrator.
600 For USB based JTAG adapters you have an easy sanity check at this point:
601 does the host operating system see the JTAG adapter?
603 @item @emph{Connect the adapter's power supply, if needed.}
604 This step is primarily for non-USB adapters,
605 but sometimes USB adapters need extra power.
607 @item @emph{Power up the target board.}
608 Unless you just let the magic smoke escape,
609 you're now ready to set up the OpenOCD server
610 so you can use JTAG to work with that board.
612 @end enumerate
614 Talk with the OpenOCD server using
615 telnet (@code{telnet localhost 4444} on many systems) or GDB.
616 @xref{GDB and OpenOCD}.
618 @section Project Directory
620 There are many ways you can configure OpenOCD and start it up.
622 A simple way to organize them all involves keeping a
623 single directory for your work with a given board.
624 When you start OpenOCD from that directory,
625 it searches there first for configuration files, scripts,
626 and for code you upload to the target board.
627 It is also the natural place to write files,
628 such as log files and data you download from the board.
630 @section Configuration Basics
632 There are two basic ways of configuring OpenOCD, and
633 a variety of ways you can mix them.
634 Think of the difference as just being how you start the server:
636 @itemize
637 @item Many @option{-f file} or @option{-c command} options on the command line
638 @item No options, but a @dfn{user config file}
639 in the current directory named @file{openocd.cfg}
640 @end itemize
642 Here is an example @file{openocd.cfg} file for a setup
643 using a Signalyzer FT2232-based JTAG adapter to talk to
644 a board with an Atmel AT91SAM7X256 microcontroller:
646 @example
647 source [find interface/signalyzer.cfg]
649 # GDB can also flash my flash!
650 gdb_memory_map enable
651 gdb_flash_program enable
653 source [find target/sam7x256.cfg]
654 @end example
656 Here is the command line equivalent of that configuration:
658 @example
659 openocd -f interface/signalyzer.cfg \
660 -c "gdb_memory_map enable" \
661 -c "gdb_flash_program enable" \
662 -f target/sam7x256.cfg
663 @end example
665 You could wrap such long command lines in shell scripts,
666 each supporting a different development task.
667 One might re-flash the board with a specific firmware version.
668 Another might set up a particular debugging or run-time environment.
670 @quotation Important
671 At this writing (October 2009) the command line method has
672 problems with how it treats variables.
673 For example, after @option{-c "set VAR value"}, or doing the
674 same in a script, the variable @var{VAR} will have no value
675 that can be tested in a later script.
676 @end quotation
678 Here we will focus on the simpler solution: one user config
679 file, including basic configuration plus any TCL procedures
680 to simplify your work.
682 @section User Config Files
683 @cindex config file, user
684 @cindex user config file
685 @cindex config file, overview
687 A user configuration file ties together all the parts of a project
688 in one place.
689 One of the following will match your situation best:
691 @itemize
692 @item Ideally almost everything comes from configuration files
693 provided by someone else.
694 For example, OpenOCD distributes a @file{scripts} directory
695 (probably in @file{/usr/share/openocd/scripts} on Linux).
696 Board and tool vendors can provide these too, as can individual
697 user sites; the @option{-s} command line option lets you say
698 where to find these files. (@xref{Running}.)
699 The AT91SAM7X256 example above works this way.
701 Three main types of non-user configuration file each have their
702 own subdirectory in the @file{scripts} directory:
704 @enumerate
705 @item @b{interface} -- one for each kind of JTAG adapter/dongle
706 @item @b{board} -- one for each different board
707 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
708 @end enumerate
710 Best case: include just two files, and they handle everything else.
711 The first is an interface config file.
712 The second is board-specific, and it sets up the JTAG TAPs and
713 their GDB targets (by deferring to some @file{target.cfg} file),
714 declares all flash memory, and leaves you nothing to do except
715 meet your deadline:
717 @example
718 source [find interface/olimex-jtag-tiny.cfg]
719 source [find board/csb337.cfg]
720 @end example
722 Boards with a single microcontroller often won't need more
723 than the target config file, as in the AT91SAM7X256 example.
724 That's because there is no external memory (flash, DDR RAM), and
725 the board differences are encapsulated by application code.
727 @item Maybe you don't know yet what your board looks like to JTAG.
728 Once you know the @file{interface.cfg} file to use, you may
729 need help from OpenOCD to discover what's on the board.
730 Once you find the TAPs, you can just search for appropriate
731 configuration files ... or write your own, from the bottom up.
732 @xref{Autoprobing}.
734 @item You can often reuse some standard config files but
735 need to write a few new ones, probably a @file{board.cfg} file.
736 You will be using commands described later in this User's Guide,
737 and working with the guidelines in the next chapter.
739 For example, there may be configuration files for your JTAG adapter
740 and target chip, but you need a new board-specific config file
741 giving access to your particular flash chips.
742 Or you might need to write another target chip configuration file
743 for a new chip built around the Cortex M3 core.
745 @quotation Note
746 When you write new configuration files, please submit
747 them for inclusion in the next OpenOCD release.
748 For example, a @file{board/newboard.cfg} file will help the
749 next users of that board, and a @file{target/newcpu.cfg}
750 will help support users of any board using that chip.
751 @end quotation
753 @item
754 You may may need to write some C code.
755 It may be as simple as a supporting a new ft2232 or parport
756 based dongle; a bit more involved, like a NAND or NOR flash
757 controller driver; or a big piece of work like supporting
758 a new chip architecture.
759 @end itemize
761 Reuse the existing config files when you can.
762 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
763 You may find a board configuration that's a good example to follow.
765 When you write config files, separate the reusable parts
766 (things every user of that interface, chip, or board needs)
767 from ones specific to your environment and debugging approach.
768 @itemize
770 @item
771 For example, a @code{gdb-attach} event handler that invokes
772 the @command{reset init} command will interfere with debugging
773 early boot code, which performs some of the same actions
774 that the @code{reset-init} event handler does.
776 @item
777 Likewise, the @command{arm9 vector_catch} command (or
778 @cindex vector_catch
779 its siblings @command{xscale vector_catch}
780 and @command{cortex_m3 vector_catch}) can be a timesaver
781 during some debug sessions, but don't make everyone use that either.
782 Keep those kinds of debugging aids in your user config file,
783 along with messaging and tracing setup.
784 (@xref{Software Debug Messages and Tracing}.)
786 @item
787 You might need to override some defaults.
788 For example, you might need to move, shrink, or back up the target's
789 work area if your application needs much SRAM.
791 @item
792 TCP/IP port configuration is another example of something which
793 is environment-specific, and should only appear in
794 a user config file. @xref{TCP/IP Ports}.
795 @end itemize
797 @section Project-Specific Utilities
799 A few project-specific utility
800 routines may well speed up your work.
801 Write them, and keep them in your project's user config file.
803 For example, if you are making a boot loader work on a
804 board, it's nice to be able to debug the ``after it's
805 loaded to RAM'' parts separately from the finicky early
806 code which sets up the DDR RAM controller and clocks.
807 A script like this one, or a more GDB-aware sibling,
808 may help:
810 @example
811 proc ramboot @{ @} @{
812 # Reset, running the target's "reset-init" scripts
813 # to initialize clocks and the DDR RAM controller.
814 # Leave the CPU halted.
815 reset init
817 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
818 load_image u-boot.bin 0x20000000
820 # Start running.
821 resume 0x20000000
822 @}
823 @end example
825 Then once that code is working you will need to make it
826 boot from NOR flash; a different utility would help.
827 Alternatively, some developers write to flash using GDB.
828 (You might use a similar script if you're working with a flash
829 based microcontroller application instead of a boot loader.)
831 @example
832 proc newboot @{ @} @{
833 # Reset, leaving the CPU halted. The "reset-init" event
834 # proc gives faster access to the CPU and to NOR flash;
835 # "reset halt" would be slower.
836 reset init
838 # Write standard version of U-Boot into the first two
839 # sectors of NOR flash ... the standard version should
840 # do the same lowlevel init as "reset-init".
841 flash protect 0 0 1 off
842 flash erase_sector 0 0 1
843 flash write_bank 0 u-boot.bin 0x0
844 flash protect 0 0 1 on
846 # Reboot from scratch using that new boot loader.
847 reset run
848 @}
849 @end example
851 You may need more complicated utility procedures when booting
852 from NAND.
853 That often involves an extra bootloader stage,
854 running from on-chip SRAM to perform DDR RAM setup so it can load
855 the main bootloader code (which won't fit into that SRAM).
857 Other helper scripts might be used to write production system images,
858 involving considerably more than just a three stage bootloader.
860 @section Target Software Changes
862 Sometimes you may want to make some small changes to the software
863 you're developing, to help make JTAG debugging work better.
864 For example, in C or assembly language code you might
865 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
866 handling issues like:
868 @itemize @bullet
870 @item @b{ARM Wait-For-Interrupt}...
871 Many ARM chips synchronize the JTAG clock using the core clock.
872 Low power states which stop that core clock thus prevent JTAG access.
873 Idle loops in tasking environments often enter those low power states
874 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
876 You may want to @emph{disable that instruction} in source code,
877 or otherwise prevent using that state,
878 to ensure you can get JTAG access at any time.
879 For example, the OpenOCD @command{halt} command may not
880 work for an idle processor otherwise.
882 @item @b{Delay after reset}...
883 Not all chips have good support for debugger access
884 right after reset; many LPC2xxx chips have issues here.
885 Similarly, applications that reconfigure pins used for
886 JTAG access as they start will also block debugger access.
888 To work with boards like this, @emph{enable a short delay loop}
889 the first thing after reset, before "real" startup activities.
890 For example, one second's delay is usually more than enough
891 time for a JTAG debugger to attach, so that
892 early code execution can be debugged
893 or firmware can be replaced.
895 @item @b{Debug Communications Channel (DCC)}...
896 Some processors include mechanisms to send messages over JTAG.
897 Many ARM cores support these, as do some cores from other vendors.
898 (OpenOCD may be able to use this DCC internally, speeding up some
899 operations like writing to memory.)
901 Your application may want to deliver various debugging messages
902 over JTAG, by @emph{linking with a small library of code}
903 provided with OpenOCD and using the utilities there to send
904 various kinds of message.
905 @xref{Software Debug Messages and Tracing}.
907 @end itemize
909 @node Config File Guidelines
910 @chapter Config File Guidelines
912 This chapter is aimed at any user who needs to write a config file,
913 including developers and integrators of OpenOCD and any user who
914 needs to get a new board working smoothly.
915 It provides guidelines for creating those files.
917 You should find the following directories under @t{$(INSTALLDIR)/scripts},
918 with files including the ones listed here.
919 Use them as-is where you can; or as models for new files.
920 @itemize @bullet
921 @item @file{interface} ...
922 think JTAG Dongle. Files that configure JTAG adapters go here.
923 @example
924 $ ls interface
925 arm-jtag-ew.cfg hitex_str9-comstick.cfg oocdlink.cfg
926 arm-usb-ocd.cfg icebear.cfg openocd-usb.cfg
927 at91rm9200.cfg jlink.cfg parport.cfg
928 axm0432.cfg jtagkey2.cfg parport_dlc5.cfg
929 calao-usb-a9260-c01.cfg jtagkey.cfg rlink.cfg
930 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg sheevaplug.cfg
931 calao-usb-a9260.cfg luminary.cfg signalyzer.cfg
932 chameleon.cfg luminary-icdi.cfg stm32-stick.cfg
933 cortino.cfg luminary-lm3s811.cfg turtelizer2.cfg
934 dummy.cfg olimex-arm-usb-ocd.cfg usbprog.cfg
935 flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
936 $
937 @end example
938 @item @file{board} ...
939 think Circuit Board, PWA, PCB, they go by many names. Board files
940 contain initialization items that are specific to a board.
941 They reuse target configuration files, since the same
942 microprocessor chips are used on many boards,
943 but support for external parts varies widely. For
944 example, the SDRAM initialization sequence for the board, or the type
945 of external flash and what address it uses. Any initialization
946 sequence to enable that external flash or SDRAM should be found in the
947 board file. Boards may also contain multiple targets: two CPUs; or
948 a CPU and an FPGA.
949 @example
950 $ ls board
951 arm_evaluator7t.cfg keil_mcb1700.cfg
952 at91rm9200-dk.cfg keil_mcb2140.cfg
953 at91sam9g20-ek.cfg linksys_nslu2.cfg
954 atmel_at91sam7s-ek.cfg logicpd_imx27.cfg
955 atmel_at91sam9260-ek.cfg mini2440.cfg
956 atmel_sam3u_ek.cfg olimex_LPC2378STK.cfg
957 crossbow_tech_imote2.cfg olimex_lpc_h2148.cfg
958 csb337.cfg olimex_sam7_ex256.cfg
959 csb732.cfg olimex_sam9_l9260.cfg
960 digi_connectcore_wi-9c.cfg olimex_stm32_h103.cfg
961 dm355evm.cfg omap2420_h4.cfg
962 dm365evm.cfg osk5912.cfg
963 dm6446evm.cfg pic-p32mx.cfg
964 eir.cfg propox_mmnet1001.cfg
965 ek-lm3s1968.cfg pxa255_sst.cfg
966 ek-lm3s3748.cfg sheevaplug.cfg
967 ek-lm3s811.cfg stm3210e_eval.cfg
968 ek-lm3s9b9x.cfg stm32f10x_128k_eval.cfg
969 hammer.cfg str910-eval.cfg
970 hitex_lpc2929.cfg telo.cfg
971 hitex_stm32-performancestick.cfg ti_beagleboard.cfg
972 hitex_str9-comstick.cfg topas910.cfg
973 iar_str912_sk.cfg topasa900.cfg
974 imx27ads.cfg unknown_at91sam9260.cfg
975 imx27lnst.cfg x300t.cfg
976 imx31pdk.cfg zy1000.cfg
977 $
978 @end example
979 @item @file{target} ...
980 think chip. The ``target'' directory represents the JTAG TAPs
981 on a chip
982 which OpenOCD should control, not a board. Two common types of targets
983 are ARM chips and FPGA or CPLD chips.
984 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
985 the target config file defines all of them.
986 @example
987 $ ls target
988 aduc702x.cfg imx27.cfg pxa255.cfg
989 ar71xx.cfg imx31.cfg pxa270.cfg
990 at91eb40a.cfg imx35.cfg readme.txt
991 at91r40008.cfg is5114.cfg sam7se512.cfg
992 at91rm9200.cfg ixp42x.cfg sam7x256.cfg
993 at91sam3u1c.cfg lm3s1968.cfg samsung_s3c2410.cfg
994 at91sam3u1e.cfg lm3s3748.cfg samsung_s3c2440.cfg
995 at91sam3u2c.cfg lm3s6965.cfg samsung_s3c2450.cfg
996 at91sam3u2e.cfg lm3s811.cfg samsung_s3c4510.cfg
997 at91sam3u4c.cfg lm3s9b9x.cfg samsung_s3c6410.cfg
998 at91sam3u4e.cfg lpc1768.cfg sharp_lh79532.cfg
999 at91sam3uXX.cfg lpc2103.cfg smdk6410.cfg
1000 at91sam7sx.cfg lpc2124.cfg smp8634.cfg
1001 at91sam9260.cfg lpc2129.cfg stm32.cfg
1002 c100.cfg lpc2148.cfg str710.cfg
1003 c100config.tcl lpc2294.cfg str730.cfg
1004 c100helper.tcl lpc2378.cfg str750.cfg
1005 c100regs.tcl lpc2478.cfg str912.cfg
1006 cs351x.cfg lpc2900.cfg telo.cfg
1007 davinci.cfg mega128.cfg ti_dm355.cfg
1008 dragonite.cfg netx500.cfg ti_dm365.cfg
1009 epc9301.cfg omap2420.cfg ti_dm6446.cfg
1010 feroceon.cfg omap3530.cfg tmpa900.cfg
1011 icepick.cfg omap5912.cfg tmpa910.cfg
1012 imx21.cfg pic32mx.cfg xba_revA3.cfg
1013 $
1014 @end example
1015 @item @emph{more} ... browse for other library files which may be useful.
1016 For example, there are various generic and CPU-specific utilities.
1017 @end itemize
1019 The @file{openocd.cfg} user config
1020 file may override features in any of the above files by
1021 setting variables before sourcing the target file, or by adding
1022 commands specific to their situation.
1024 @section Interface Config Files
1026 The user config file
1027 should be able to source one of these files with a command like this:
1029 @example
1030 source [find interface/FOOBAR.cfg]
1031 @end example
1033 A preconfigured interface file should exist for every interface in use
1034 today, that said, perhaps some interfaces have only been used by the
1035 sole developer who created it.
1037 A separate chapter gives information about how to set these up.
1038 @xref{Interface - Dongle Configuration}.
1039 Read the OpenOCD source code if you have a new kind of hardware interface
1040 and need to provide a driver for it.
1042 @section Board Config Files
1043 @cindex config file, board
1044 @cindex board config file
1046 The user config file
1047 should be able to source one of these files with a command like this:
1049 @example
1050 source [find board/FOOBAR.cfg]
1051 @end example
1053 The point of a board config file is to package everything
1054 about a given board that user config files need to know.
1055 In summary the board files should contain (if present)
1057 @enumerate
1058 @item One or more @command{source [target/...cfg]} statements
1059 @item NOR flash configuration (@pxref{NOR Configuration})
1060 @item NAND flash configuration (@pxref{NAND Configuration})
1061 @item Target @code{reset} handlers for SDRAM and I/O configuration
1062 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1063 @item All things that are not ``inside a chip''
1064 @end enumerate
1066 Generic things inside target chips belong in target config files,
1067 not board config files. So for example a @code{reset-init} event
1068 handler should know board-specific oscillator and PLL parameters,
1069 which it passes to target-specific utility code.
1071 The most complex task of a board config file is creating such a
1072 @code{reset-init} event handler.
1073 Define those handlers last, after you verify the rest of the board
1074 configuration works.
1076 @subsection Communication Between Config files
1078 In addition to target-specific utility code, another way that
1079 board and target config files communicate is by following a
1080 convention on how to use certain variables.
1082 The full Tcl/Tk language supports ``namespaces'', but JIM-Tcl does not.
1083 Thus the rule we follow in OpenOCD is this: Variables that begin with
1084 a leading underscore are temporary in nature, and can be modified and
1085 used at will within a target configuration file.
1087 Complex board config files can do the things like this,
1088 for a board with three chips:
1090 @example
1091 # Chip #1: PXA270 for network side, big endian
1092 set CHIPNAME network
1093 set ENDIAN big
1094 source [find target/pxa270.cfg]
1095 # on return: _TARGETNAME = network.cpu
1096 # other commands can refer to the "network.cpu" target.
1097 $_TARGETNAME configure .... events for this CPU..
1099 # Chip #2: PXA270 for video side, little endian
1100 set CHIPNAME video
1101 set ENDIAN little
1102 source [find target/pxa270.cfg]
1103 # on return: _TARGETNAME = video.cpu
1104 # other commands can refer to the "video.cpu" target.
1105 $_TARGETNAME configure .... events for this CPU..
1107 # Chip #3: Xilinx FPGA for glue logic
1108 set CHIPNAME xilinx
1109 unset ENDIAN
1110 source [find target/spartan3.cfg]
1111 @end example
1113 That example is oversimplified because it doesn't show any flash memory,
1114 or the @code{reset-init} event handlers to initialize external DRAM
1115 or (assuming it needs it) load a configuration into the FPGA.
1116 Such features are usually needed for low-level work with many boards,
1117 where ``low level'' implies that the board initialization software may
1118 not be working. (That's a common reason to need JTAG tools. Another
1119 is to enable working with microcontroller-based systems, which often
1120 have no debugging support except a JTAG connector.)
1122 Target config files may also export utility functions to board and user
1123 config files. Such functions should use name prefixes, to help avoid
1124 naming collisions.
1126 Board files could also accept input variables from user config files.
1127 For example, there might be a @code{J4_JUMPER} setting used to identify
1128 what kind of flash memory a development board is using, or how to set
1129 up other clocks and peripherals.
1131 @subsection Variable Naming Convention
1132 @cindex variable names
1134 Most boards have only one instance of a chip.
1135 However, it should be easy to create a board with more than
1136 one such chip (as shown above).
1137 Accordingly, we encourage these conventions for naming
1138 variables associated with different @file{target.cfg} files,
1139 to promote consistency and
1140 so that board files can override target defaults.
1142 Inputs to target config files include:
1144 @itemize @bullet
1145 @item @code{CHIPNAME} ...
1146 This gives a name to the overall chip, and is used as part of
1147 tap identifier dotted names.
1148 While the default is normally provided by the chip manufacturer,
1149 board files may need to distinguish between instances of a chip.
1150 @item @code{ENDIAN} ...
1151 By default @option{little} - although chips may hard-wire @option{big}.
1152 Chips that can't change endianness don't need to use this variable.
1153 @item @code{CPUTAPID} ...
1154 When OpenOCD examines the JTAG chain, it can be told verify the
1155 chips against the JTAG IDCODE register.
1156 The target file will hold one or more defaults, but sometimes the
1157 chip in a board will use a different ID (perhaps a newer revision).
1158 @end itemize
1160 Outputs from target config files include:
1162 @itemize @bullet
1163 @item @code{_TARGETNAME} ...
1164 By convention, this variable is created by the target configuration
1165 script. The board configuration file may make use of this variable to
1166 configure things like a ``reset init'' script, or other things
1167 specific to that board and that target.
1168 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1169 @code{_TARGETNAME1}, ... etc.
1170 @end itemize
1172 @subsection The reset-init Event Handler
1173 @cindex event, reset-init
1174 @cindex reset-init handler
1176 Board config files run in the OpenOCD configuration stage;
1177 they can't use TAPs or targets, since they haven't been
1178 fully set up yet.
1179 This means you can't write memory or access chip registers;
1180 you can't even verify that a flash chip is present.
1181 That's done later in event handlers, of which the target @code{reset-init}
1182 handler is one of the most important.
1184 Except on microcontrollers, the basic job of @code{reset-init} event
1185 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1186 Microcontrollers rarely use boot loaders; they run right out of their
1187 on-chip flash and SRAM memory. But they may want to use one of these
1188 handlers too, if just for developer convenience.
1190 @quotation Note
1191 Because this is so very board-specific, and chip-specific, no examples
1192 are included here.
1193 Instead, look at the board config files distributed with OpenOCD.
1194 If you have a boot loader, its source code will help; so will
1195 configuration files for other JTAG tools
1196 (@pxref{Translating Configuration Files}).
1197 @end quotation
1199 Some of this code could probably be shared between different boards.
1200 For example, setting up a DRAM controller often doesn't differ by
1201 much except the bus width (16 bits or 32?) and memory timings, so a
1202 reusable TCL procedure loaded by the @file{target.cfg} file might take
1203 those as parameters.
1204 Similarly with oscillator, PLL, and clock setup;
1205 and disabling the watchdog.
1206 Structure the code cleanly, and provide comments to help
1207 the next developer doing such work.
1208 (@emph{You might be that next person} trying to reuse init code!)
1210 The last thing normally done in a @code{reset-init} handler is probing
1211 whatever flash memory was configured. For most chips that needs to be
1212 done while the associated target is halted, either because JTAG memory
1213 access uses the CPU or to prevent conflicting CPU access.
1215 @subsection JTAG Clock Rate
1217 Before your @code{reset-init} handler has set up
1218 the PLLs and clocking, you may need to run with
1219 a low JTAG clock rate.
1220 @xref{JTAG Speed}.
1221 Then you'd increase that rate after your handler has
1222 made it possible to use the faster JTAG clock.
1223 When the initial low speed is board-specific, for example
1224 because it depends on a board-specific oscillator speed, then
1225 you should probably set it up in the board config file;
1226 if it's target-specific, it belongs in the target config file.
1228 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1229 @uref{} gives details.}
1230 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1231 Consult chip documentation to determine the peak JTAG clock rate,
1232 which might be less than that.
1234 @quotation Warning
1235 On most ARMs, JTAG clock detection is coupled to the core clock, so
1236 software using a @option{wait for interrupt} operation blocks JTAG access.
1237 Adaptive clocking provides a partial workaround, but a more complete
1238 solution just avoids using that instruction with JTAG debuggers.
1239 @end quotation
1241 If the board supports adaptive clocking, use the @command{jtag_rclk}
1242 command, in case your board is used with JTAG adapter which
1243 also supports it. Otherwise use @command{jtag_khz}.
1244 Set the slow rate at the beginning of the reset sequence,
1245 and the faster rate as soon as the clocks are at full speed.
1247 @section Target Config Files
1248 @cindex config file, target
1249 @cindex target config file
1251 Board config files communicate with target config files using
1252 naming conventions as described above, and may source one or
1253 more target config files like this:
1255 @example
1256 source [find target/FOOBAR.cfg]
1257 @end example
1259 The point of a target config file is to package everything
1260 about a given chip that board config files need to know.
1261 In summary the target files should contain
1263 @enumerate
1264 @item Set defaults
1265 @item Add TAPs to the scan chain
1266 @item Add CPU targets (includes GDB support)
1267 @item CPU/Chip/CPU-Core specific features
1268 @item On-Chip flash
1269 @end enumerate
1271 As a rule of thumb, a target file sets up only one chip.
1272 For a microcontroller, that will often include a single TAP,
1273 which is a CPU needing a GDB target, and its on-chip flash.
1275 More complex chips may include multiple TAPs, and the target
1276 config file may need to define them all before OpenOCD
1277 can talk to the chip.
1278 For example, some phone chips have JTAG scan chains that include
1279 an ARM core for operating system use, a DSP,
1280 another ARM core embedded in an image processing engine,
1281 and other processing engines.
1283 @subsection Default Value Boiler Plate Code
1285 All target configuration files should start with code like this,
1286 letting board config files express environment-specific
1287 differences in how things should be set up.
1289 @example
1290 # Boards may override chip names, perhaps based on role,
1291 # but the default should match what the vendor uses
1292 if @{ [info exists CHIPNAME] @} @{
1294 @} else @{
1295 set _CHIPNAME sam7x256
1296 @}
1298 # ONLY use ENDIAN with targets that can change it.
1299 if @{ [info exists ENDIAN] @} @{
1300 set _ENDIAN $ENDIAN
1301 @} else @{
1302 set _ENDIAN little
1303 @}
1305 # TAP identifiers may change as chips mature, for example with
1306 # new revision fields (the "3" here). Pick a good default; you
1307 # can pass several such identifiers to the "jtag newtap" command.
1308 if @{ [info exists CPUTAPID ] @} @{
1310 @} else @{
1311 set _CPUTAPID 0x3f0f0f0f
1312 @}
1313 @end example
1314 @c but 0x3f0f0f0f is for an str73x part ...
1316 @emph{Remember:} Board config files may include multiple target
1317 config files, or the same target file multiple times
1318 (changing at least @code{CHIPNAME}).
1320 Likewise, the target configuration file should define
1321 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1322 use it later on when defining debug targets:
1324 @example
1326 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1327 @end example
1329 @subsection Adding TAPs to the Scan Chain
1330 After the ``defaults'' are set up,
1331 add the TAPs on each chip to the JTAG scan chain.
1332 @xref{TAP Declaration}, and the naming convention
1333 for taps.
1335 In the simplest case the chip has only one TAP,
1336 probably for a CPU or FPGA.
1337 The config file for the Atmel AT91SAM7X256
1338 looks (in part) like this:
1340 @example
1341 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1342 @end example
1344 A board with two such at91sam7 chips would be able
1345 to source such a config file twice, with different
1346 values for @code{CHIPNAME}, so
1347 it adds a different TAP each time.
1349 If there are nonzero @option{-expected-id} values,
1350 OpenOCD attempts to verify the actual tap id against those values.
1351 It will issue error messages if there is mismatch, which
1352 can help to pinpoint problems in OpenOCD configurations.
1354 @example
1355 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1356 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1357 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1358 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1359 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1360 @end example
1362 There are more complex examples too, with chips that have
1363 multiple TAPs. Ones worth looking at include:
1365 @itemize
1366 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1367 plus a JRC to enable them
1368 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1369 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1370 is not currently used)
1371 @end itemize
1373 @subsection Add CPU targets
1375 After adding a TAP for a CPU, you should set it up so that
1376 GDB and other commands can use it.
1377 @xref{CPU Configuration}.
1378 For the at91sam7 example above, the command can look like this;
1379 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1380 to little endian, and this chip doesn't support changing that.
1382 @example
1384 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1385 @end example
1387 Work areas are small RAM areas associated with CPU targets.
1388 They are used by OpenOCD to speed up downloads,
1389 and to download small snippets of code to program flash chips.
1390 If the chip includes a form of ``on-chip-ram'' - and many do - define
1391 a work area if you can.
1392 Again using the at91sam7 as an example, this can look like:
1394 @example
1395 $_TARGETNAME configure -work-area-phys 0x00200000 \
1396 -work-area-size 0x4000 -work-area-backup 0
1397 @end example
1399 @subsection Chip Reset Setup
1401 As a rule, you should put the @command{reset_config} command
1402 into the board file. Most things you think you know about a
1403 chip can be tweaked by the board.
1405 Some chips have specific ways the TRST and SRST signals are
1406 managed. In the unusual case that these are @emph{chip specific}
1407 and can never be changed by board wiring, they could go here.
1409 Some chips need special attention during reset handling if
1410 they're going to be used with JTAG.
1411 An example might be needing to send some commands right
1412 after the target's TAP has been reset, providing a
1413 @code{reset-deassert-post} event handler that writes a chip
1414 register to report that JTAG debugging is being done.
1416 JTAG clocking constraints often change during reset, and in
1417 some cases target config files (rather than board config files)
1418 are the right places to handle some of those issues.
1419 For example, immediately after reset most chips run using a
1420 slower clock than they will use later.
1421 That means that after reset (and potentially, as OpenOCD
1422 first starts up) they must use a slower JTAG clock rate
1423 than they will use later.
1424 @xref{JTAG Speed}.
1426 @quotation Important
1427 When you are debugging code that runs right after chip
1428 reset, getting these issues right is critical.
1429 In particular, if you see intermittent failures when
1430 OpenOCD verifies the scan chain after reset,
1431 look at how you are setting up JTAG clocking.
1432 @end quotation
1434 @subsection ARM Core Specific Hacks
1436 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1437 special high speed download features - enable it.
1439 If present, the MMU, the MPU and the CACHE should be disabled.
1441 Some ARM cores are equipped with trace support, which permits
1442 examination of the instruction and data bus activity. Trace
1443 activity is controlled through an ``Embedded Trace Module'' (ETM)
1444 on one of the core's scan chains. The ETM emits voluminous data
1445 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
1446 If you are using an external trace port,
1447 configure it in your board config file.
1448 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1449 configure it in your target config file.
1451 @example
1452 etm config $_TARGETNAME 16 normal full etb
1453 etb config $_TARGETNAME $_CHIPNAME.etb
1454 @end example
1456 @subsection Internal Flash Configuration
1458 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1460 @b{Never ever} in the ``target configuration file'' define any type of
1461 flash that is external to the chip. (For example a BOOT flash on
1462 Chip Select 0.) Such flash information goes in a board file - not
1463 the TARGET (chip) file.
1465 Examples:
1466 @itemize @bullet
1467 @item at91sam7x256 - has 256K flash YES enable it.
1468 @item str912 - has flash internal YES enable it.
1469 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1470 @item pxa270 - again - CS0 flash - it goes in the board file.
1471 @end itemize
1473 @anchor{Translating Configuration Files}
1474 @section Translating Configuration Files
1475 @cindex translation
1476 If you have a configuration file for another hardware debugger
1477 or toolset (Abatron, BDI2000, BDI3000, CCS,
1478 Lauterbach, Segger, Macraigor, etc.), translating
1479 it into OpenOCD syntax is often quite straightforward. The most tricky
1480 part of creating a configuration script is oftentimes the reset init
1481 sequence where e.g. PLLs, DRAM and the like is set up.
1483 One trick that you can use when translating is to write small
1484 Tcl procedures to translate the syntax into OpenOCD syntax. This
1485 can avoid manual translation errors and make it easier to
1486 convert other scripts later on.
1488 Example of transforming quirky arguments to a simple search and
1489 replace job:
1491 @example
1492 # Lauterbach syntax(?)
1493 #
1494 # Data.Set c15:0x042f %long 0x40000015
1495 #
1496 # OpenOCD syntax when using procedure below.
1497 #
1498 # setc15 0x01 0x00050078
1500 proc setc15 @{regs value@} @{
1501 global TARGETNAME
1503 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
1505 mcr 15 [expr ($regs>>12)&0x7] \
1506 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
1507 [expr ($regs>>8)&0x7] $value
1508 @}
1509 @end example
1513 @node Daemon Configuration
1514 @chapter Daemon Configuration
1515 @cindex initialization
1516 The commands here are commonly found in the openocd.cfg file and are
1517 used to specify what TCP/IP ports are used, and how GDB should be
1518 supported.
1520 @anchor{Configuration Stage}
1521 @section Configuration Stage
1522 @cindex configuration stage
1523 @cindex config command
1525 When the OpenOCD server process starts up, it enters a
1526 @emph{configuration stage} which is the only time that
1527 certain commands, @emph{configuration commands}, may be issued.
1528 In this manual, the definition of a configuration command is
1529 presented as a @emph{Config Command}, not as a @emph{Command}
1530 which may be issued interactively.
1532 Those configuration commands include declaration of TAPs,
1533 flash banks,
1534 the interface used for JTAG communication,
1535 and other basic setup.
1536 The server must leave the configuration stage before it
1537 may access or activate TAPs.
1538 After it leaves this stage, configuration commands may no
1539 longer be issued.
1541 @section Entering the Run Stage
1543 The first thing OpenOCD does after leaving the configuration
1544 stage is to verify that it can talk to the scan chain
1545 (list of TAPs) which has been configured.
1546 It will warn if it doesn't find TAPs it expects to find,
1547 or finds TAPs that aren't supposed to be there.
1548 You should see no errors at this point.
1549 If you see errors, resolve them by correcting the
1550 commands you used to configure the server.
1551 Common errors include using an initial JTAG speed that's too
1552 fast, and not providing the right IDCODE values for the TAPs
1553 on the scan chain.
1555 Once OpenOCD has entered the run stage, a number of commands
1556 become available.
1557 A number of these relate to the debug targets you may have declared.
1558 For example, the @command{mww} command will not be available until
1559 a target has been successfuly instantiated.
1560 If you want to use those commands, you may need to force
1561 entry to the run stage.
1563 @deffn {Config Command} init
1564 This command terminates the configuration stage and
1565 enters the run stage. This helps when you need to have
1566 the startup scripts manage tasks such as resetting the target,
1567 programming flash, etc. To reset the CPU upon startup, add "init" and
1568 "reset" at the end of the config script or at the end of the OpenOCD
1569 command line using the @option{-c} command line switch.
1571 If this command does not appear in any startup/configuration file
1572 OpenOCD executes the command for you after processing all
1573 configuration files and/or command line options.
1575 @b{NOTE:} This command normally occurs at or near the end of your
1576 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1577 targets ready. For example: If your openocd.cfg file needs to
1578 read/write memory on your target, @command{init} must occur before
1579 the memory read/write commands. This includes @command{nand probe}.
1580 @end deffn
1582 @deffn {Overridable Procedure} jtag_init
1583 This is invoked at server startup to verify that it can talk
1584 to the scan chain (list of TAPs) which has been configured.
1586 The default implementation first tries @command{jtag arp_init},
1587 which uses only a lightweight JTAG reset before examining the
1588 scan chain.
1589 If that fails, it tries again, using a harder reset
1590 from the overridable procedure @command{init_reset}.
1592 Implementations must have verified the JTAG scan chain before
1593 they return.
1594 This is done by calling @command{jtag arp_init}
1595 (or @command{jtag arp_init-reset}).
1596 @end deffn
1598 @anchor{TCP/IP Ports}
1599 @section TCP/IP Ports
1600 @cindex TCP port
1601 @cindex server
1602 @cindex port
1603 @cindex security
1604 The OpenOCD server accepts remote commands in several syntaxes.
1605 Each syntax uses a different TCP/IP port, which you may specify
1606 only during configuration (before those ports are opened).
1608 For reasons including security, you may wish to prevent remote
1609 access using one or more of these ports.
1610 In such cases, just specify the relevant port number as zero.
1611 If you disable all access through TCP/IP, you will need to
1612 use the command line @option{-pipe} option.
1614 @deffn {Command} gdb_port (number)
1615 @cindex GDB server
1616 Specify or query the first port used for incoming GDB connections.
1617 The GDB port for the
1618 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1619 When not specified during the configuration stage,
1620 the port @var{number} defaults to 3333.
1621 When specified as zero, this port is not activated.
1622 @end deffn
1624 @deffn {Command} tcl_port (number)
1625 Specify or query the port used for a simplified RPC
1626 connection that can be used by clients to issue TCL commands and get the
1627 output from the Tcl engine.
1628 Intended as a machine interface.
1629 When not specified during the configuration stage,
1630 the port @var{number} defaults to 6666.
1631 When specified as zero, this port is not activated.
1632 @end deffn
1634 @deffn {Command} telnet_port (number)
1635 Specify or query the
1636 port on which to listen for incoming telnet connections.
1637 This port is intended for interaction with one human through TCL commands.
1638 When not specified during the configuration stage,
1639 the port @var{number} defaults to 4444.
1640 When specified as zero, this port is not activated.
1641 @end deffn
1643 @anchor{GDB Configuration}
1644 @section GDB Configuration
1645 @cindex GDB
1646 @cindex GDB configuration
1647 You can reconfigure some GDB behaviors if needed.
1648 The ones listed here are static and global.
1649 @xref{Target Configuration}, about configuring individual targets.
1650 @xref{Target Events}, about configuring target-specific event handling.
1652 @anchor{gdb_breakpoint_override}
1653 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
1654 Force breakpoint type for gdb @command{break} commands.
1655 This option supports GDB GUIs which don't
1656 distinguish hard versus soft breakpoints, if the default OpenOCD and
1657 GDB behaviour is not sufficient. GDB normally uses hardware
1658 breakpoints if the memory map has been set up for flash regions.
1659 @end deffn
1661 @anchor{gdb_flash_program}
1662 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
1663 Set to @option{enable} to cause OpenOCD to program the flash memory when a
1664 vFlash packet is received.
1665 The default behaviour is @option{enable}.
1666 @end deffn
1668 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
1669 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
1670 requested. GDB will then know when to set hardware breakpoints, and program flash
1671 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1672 for flash programming to work.
1673 Default behaviour is @option{enable}.
1674 @xref{gdb_flash_program}.
1675 @end deffn
1677 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
1678 Specifies whether data aborts cause an error to be reported
1679 by GDB memory read packets.
1680 The default behaviour is @option{disable};
1681 use @option{enable} see these errors reported.
1682 @end deffn
1684 @anchor{Event Polling}
1685 @section Event Polling
1687 Hardware debuggers are parts of asynchronous systems,
1688 where significant events can happen at any time.
1689 The OpenOCD server needs to detect some of these events,
1690 so it can report them to through TCL command line
1691 or to GDB.
1693 Examples of such events include:
1695 @itemize
1696 @item One of the targets can stop running ... maybe it triggers
1697 a code breakpoint or data watchpoint, or halts itself.
1698 @item Messages may be sent over ``debug message'' channels ... many
1699 targets support such messages sent over JTAG,
1700 for receipt by the person debugging or tools.
1701 @item Loss of power ... some adapters can detect these events.
1702 @item Resets not issued through JTAG ... such reset sources
1703 can include button presses or other system hardware, sometimes
1704 including the target itself (perhaps through a watchdog).
1705 @item Debug instrumentation sometimes supports event triggering
1706 such as ``trace buffer full'' (so it can quickly be emptied)
1707 or other signals (to correlate with code behavior).
1708 @end itemize
1710 None of those events are signaled through standard JTAG signals.
1711 However, most conventions for JTAG connectors include voltage
1712 level and system reset (SRST) signal detection.
1713 Some connectors also include instrumentation signals, which
1714 can imply events when those signals are inputs.
1716 In general, OpenOCD needs to periodically check for those events,
1717 either by looking at the status of signals on the JTAG connector
1718 or by sending synchronous ``tell me your status'' JTAG requests
1719 to the various active targets.
1720 There is a command to manage and monitor that polling,
1721 which is normally done in the background.
1723 @deffn Command poll [@option{on}|@option{off}]
1724 Poll the current target for its current state.
1725 (Also, @pxref{target curstate}.)
1726 If that target is in debug mode, architecture
1727 specific information about the current state is printed.
1728 An optional parameter
1729 allows background polling to be enabled and disabled.
1731 You could use this from the TCL command shell, or
1732 from GDB using @command{monitor poll} command.
1733 @example
1734 > poll
1735 background polling: on
1736 target state: halted
1737 target halted in ARM state due to debug-request, \
1738 current mode: Supervisor
1739 cpsr: 0x800000d3 pc: 0x11081bfc
1740 MMU: disabled, D-Cache: disabled, I-Cache: enabled
1741 >
1742 @end example
1743 @end deffn
1745 @node Interface - Dongle Configuration
1746 @chapter Interface - Dongle Configuration
1747 @cindex config file, interface
1748 @cindex interface config file
1750 JTAG Adapters/Interfaces/Dongles are normally configured
1751 through commands in an interface configuration
1752 file which is sourced by your @file{openocd.cfg} file, or
1753 through a command line @option{-f interface/....cfg} option.
1755 @example
1756 source [find interface/olimex-jtag-tiny.cfg]
1757 @end example
1759 These commands tell
1760 OpenOCD what type of JTAG adapter you have, and how to talk to it.
1761 A few cases are so simple that you only need to say what driver to use:
1763 @example
1764 # jlink interface
1765 interface jlink
1766 @end example
1768 Most adapters need a bit more configuration than that.
1771 @section Interface Configuration
1773 The interface command tells OpenOCD what type of JTAG dongle you are
1774 using. Depending on the type of dongle, you may need to have one or
1775 more additional commands.
1777 @deffn {Config Command} {interface} name
1778 Use the interface driver @var{name} to connect to the
1779 target.
1780 @end deffn
1782 @deffn Command {interface_list}
1783 List the interface drivers that have been built into
1784 the running copy of OpenOCD.
1785 @end deffn
1787 @deffn Command {jtag interface}
1788 Returns the name of the interface driver being used.
1789 @end deffn
1791 @section Interface Drivers
1793 Each of the interface drivers listed here must be explicitly
1794 enabled when OpenOCD is configured, in order to be made
1795 available at run time.
1797 @deffn {Interface Driver} {amt_jtagaccel}
1798 Amontec Chameleon in its JTAG Accelerator configuration,
1799 connected to a PC's EPP mode parallel port.
1800 This defines some driver-specific commands:
1802 @deffn {Config Command} {parport_port} number
1803 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1804 the number of the @file{/dev/parport} device.
1805 @end deffn
1807 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
1808 Displays status of RTCK option.
1809 Optionally sets that option first.
1810 @end deffn
1811 @end deffn
1813 @deffn {Interface Driver} {arm-jtag-ew}
1814 Olimex ARM-JTAG-EW USB adapter
1815 This has one driver-specific command:
1817 @deffn Command {armjtagew_info}
1818 Logs some status
1819 @end deffn
1820 @end deffn
1822 @deffn {Interface Driver} {at91rm9200}
1823 Supports bitbanged JTAG from the local system,
1824 presuming that system is an Atmel AT91rm9200
1825 and a specific set of GPIOs is used.
1826 @c command: at91rm9200_device NAME
1827 @c chooses among list of bit configs ... only one option
1828 @end deffn
1830 @deffn {Interface Driver} {dummy}
1831 A dummy software-only driver for debugging.
1832 @end deffn
1834 @deffn {Interface Driver} {ep93xx}
1835 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1836 @end deffn
1838 @deffn {Interface Driver} {ft2232}
1839 FTDI FT2232 (USB) based devices over one of the userspace libraries.
1840 These interfaces have several commands, used to configure the driver
1841 before initializing the JTAG scan chain:
1843 @deffn {Config Command} {ft2232_device_desc} description
1844 Provides the USB device description (the @emph{iProduct string})
1845 of the FTDI FT2232 device. If not
1846 specified, the FTDI default value is used. This setting is only valid
1847 if compiled with FTD2XX support.
1848 @end deffn
1850 @deffn {Config Command} {ft2232_serial} serial-number
1851 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
1852 in case the vendor provides unique IDs and more than one FT2232 device
1853 is connected to the host.
1854 If not specified, serial numbers are not considered.
1855 (Note that USB serial numbers can be arbitrary Unicode strings,
1856 and are not restricted to containing only decimal digits.)
1857 @end deffn
1859 @deffn {Config Command} {ft2232_layout} name
1860 Each vendor's FT2232 device can use different GPIO signals
1861 to control output-enables, reset signals, and LEDs.
1862 Currently valid layout @var{name} values include:
1863 @itemize @minus
1864 @item @b{axm0432_jtag} Axiom AXM-0432
1865 @item @b{comstick} Hitex STR9 comstick
1866 @item @b{cortino} Hitex Cortino JTAG interface
1867 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
1868 either for the local Cortex-M3 (SRST only)
1869 or in a passthrough mode (neither SRST nor TRST)
1870 @item @b{luminary_icdi} Luminary In-Circuit Debug Interface (ICDI) Board
1871 @item @b{flyswatter} Tin Can Tools Flyswatter
1872 @item @b{icebear} ICEbear JTAG adapter from Section 5
1873 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
1874 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
1875 @item @b{m5960} American Microsystems M5960
1876 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
1877 @item @b{oocdlink} OOCDLink
1878 @c oocdlink ~= jtagkey_prototype_v1
1879 @item @b{sheevaplug} Marvell Sheevaplug development kit
1880 @item @b{signalyzer} Xverve Signalyzer
1881 @item @b{stm32stick} Hitex STM32 Performance Stick
1882 @item @b{turtelizer2} egnite Software turtelizer2
1883 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
1884 @end itemize
1885 @end deffn
1887 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
1888 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1889 default values are used.
1890 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
1891 @example
1892 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1893 @end example
1894 @end deffn
1896 @deffn {Config Command} {ft2232_latency} ms
1897 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1898 ft2232_read() fails to return the expected number of bytes. This can be caused by
1899 USB communication delays and has proved hard to reproduce and debug. Setting the
1900 FT2232 latency timer to a larger value increases delays for short USB packets but it
1901 also reduces the risk of timeouts before receiving the expected number of bytes.
1902 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1903 @end deffn
1905 For example, the interface config file for a
1906 Turtelizer JTAG Adapter looks something like this:
1908 @example
1909 interface ft2232
1910 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
1911 ft2232_layout turtelizer2
1912 ft2232_vid_pid 0x0403 0xbdc8
1913 @end example
1914 @end deffn
1916 @deffn {Interface Driver} {gw16012}
1917 Gateworks GW16012 JTAG programmer.
1918 This has one driver-specific command:
1920 @deffn {Config Command} {parport_port} number
1921 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1922 the number of the @file{/dev/parport} device.
1923 @end deffn
1924 @end deffn
1926 @deffn {Interface Driver} {jlink}
1927 Segger jlink USB adapter
1928 @c command: jlink_info
1929 @c dumps status
1930 @c command: jlink_hw_jtag (2|3)
1931 @c sets version 2 or 3
1932 @end deffn
1934 @deffn {Interface Driver} {parport}
1935 Supports PC parallel port bit-banging cables:
1936 Wigglers, PLD download cable, and more.
1937 These interfaces have several commands, used to configure the driver
1938 before initializing the JTAG scan chain:
1940 @deffn {Config Command} {parport_cable} name
1941 The layout of the parallel port cable used to connect to the target.
1942 Currently valid cable @var{name} values include:
1944 @itemize @minus
1945 @item @b{altium} Altium Universal JTAG cable.
1946 @item @b{arm-jtag} Same as original wiggler except SRST and
1947 TRST connections reversed and TRST is also inverted.
1948 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
1949 in configuration mode. This is only used to
1950 program the Chameleon itself, not a connected target.
1951 @item @b{dlc5} The Xilinx Parallel cable III.
1952 @item @b{flashlink} The ST Parallel cable.
1953 @item @b{lattice} Lattice ispDOWNLOAD Cable
1954 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
1955 some versions of
1956 Amontec's Chameleon Programmer. The new version available from
1957 the website uses the original Wiggler layout ('@var{wiggler}')
1958 @item @b{triton} The parallel port adapter found on the
1959 ``Karo Triton 1 Development Board''.
1960 This is also the layout used by the HollyGates design
1961 (see @uref{}).
1962 @item @b{wiggler} The original Wiggler layout, also supported by
1963 several clones, such as the Olimex ARM-JTAG
1964 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
1965 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
1966 @end itemize
1967 @end deffn
1969 @deffn {Config Command} {parport_port} number
1970 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1971 the @file{/dev/parport} device
1973 When using PPDEV to access the parallel port, use the number of the parallel port:
1974 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1975 you may encounter a problem.
1976 @end deffn
1978 @deffn Command {parport_toggling_time} [nanoseconds]
1979 Displays how many nanoseconds the hardware needs to toggle TCK;
1980 the parport driver uses this value to obey the
1981 @command{jtag_khz} configuration.
1982 When the optional @var{nanoseconds} parameter is given,
1983 that setting is changed before displaying the current value.
1985 The default setting should work reasonably well on commodity PC hardware.
1986 However, you may want to calibrate for your specific hardware.
1987 @quotation Tip
1988 To measure the toggling time with a logic analyzer or a digital storage
1989 oscilloscope, follow the procedure below:
1990 @example
1991 > parport_toggling_time 1000
1992 > jtag_khz 500
1993 @end example
1994 This sets the maximum JTAG clock speed of the hardware, but
1995 the actual speed probably deviates from the requested 500 kHz.
1996 Now, measure the time between the two closest spaced TCK transitions.
1997 You can use @command{runtest 1000} or something similar to generate a
1998 large set of samples.
1999 Update the setting to match your measurement:
2000 @example
2001 > parport_toggling_time <measured nanoseconds>
2002 @end example
2003 Now the clock speed will be a better match for @command{jtag_khz rate}
2004 commands given in OpenOCD scripts and event handlers.
2006 You can do something similar with many digital multimeters, but note
2007 that you'll probably need to run the clock continuously for several
2008 seconds before it decides what clock rate to show. Adjust the
2009 toggling time up or down until the measured clock rate is a good
2010 match for the jtag_khz rate you specified; be conservative.
2011 @end quotation
2012 @end deffn
2014 @deffn {Config Command} {parport_write_on_exit} (on|off)
2015 This will configure the parallel driver to write a known
2016 cable-specific value to the parallel interface on exiting OpenOCD
2017 @end deffn
2019 For example, the interface configuration file for a
2020 classic ``Wiggler'' cable might look something like this:
2022 @example
2023 interface parport
2024 parport_port 0xc8b8
2025 parport_cable wiggler
2026 @end example
2027 @end deffn
2029 @deffn {Interface Driver} {presto}
2030 ASIX PRESTO USB JTAG programmer.
2031 @c command: presto_serial str
2032 @c sets serial number
2033 @end deffn
2035 @deffn {Interface Driver} {rlink}
2036 Raisonance RLink USB adapter
2037 @end deffn
2039 @deffn {Interface Driver} {usbprog}
2040 usbprog is a freely programmable USB adapter.
2041 @end deffn
2043 @deffn {Interface Driver} {vsllink}
2044 vsllink is part of Versaloon which is a versatile USB programmer.
2046 @quotation Note
2047 This defines quite a few driver-specific commands,
2048 which are not currently documented here.
2049 @end quotation
2050 @end deffn
2052 @deffn {Interface Driver} {ZY1000}
2053 This is the Zylin ZY1000 JTAG debugger.
2055 @quotation Note
2056 This defines some driver-specific commands,
2057 which are not currently documented here.
2058 @end quotation
2060 @deffn Command power [@option{on}|@option{off}]
2061 Turn power switch to target on/off.
2062 No arguments: print status.
2063 @end deffn
2065 @end deffn
2067 @anchor{JTAG Speed}
2068 @section JTAG Speed
2069 JTAG clock setup is part of system setup.
2070 It @emph{does not belong with interface setup} since any interface
2071 only knows a few of the constraints for the JTAG clock speed.
2072 Sometimes the JTAG speed is
2073 changed during the target initialization process: (1) slow at
2074 reset, (2) program the CPU clocks, (3) run fast.
2075 Both the "slow" and "fast" clock rates are functions of the
2076 oscillators used, the chip, the board design, and sometimes
2077 power management software that may be active.
2079 The speed used during reset, and the scan chain verification which
2080 follows reset, can be adjusted using a @code{reset-start}
2081 target event handler.
2082 It can then be reconfigured to a faster speed by a
2083 @code{reset-init} target event handler after it reprograms those
2084 CPU clocks, or manually (if something else, such as a boot loader,
2085 sets up those clocks).
2086 @xref{Target Events}.
2087 When the initial low JTAG speed is a chip characteristic, perhaps
2088 because of a required oscillator speed, provide such a handler
2089 in the target config file.
2090 When that speed is a function of a board-specific characteristic
2091 such as which speed oscillator is used, it belongs in the board
2092 config file instead.
2093 In both cases it's safest to also set the initial JTAG clock rate
2094 to that same slow speed, so that OpenOCD never starts up using a
2095 clock speed that's faster than the scan chain can support.
2097 @example
2098 jtag_rclk 3000
2099 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
2100 @end example
2102 If your system supports adaptive clocking (RTCK), configuring
2103 JTAG to use that is probably the most robust approach.
2104 However, it introduces delays to synchronize clocks; so it
2105 may not be the fastest solution.
2107 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
2108 instead of @command{jtag_khz}.
2110 @deffn {Command} jtag_khz max_speed_kHz
2111 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
2112 JTAG interfaces usually support a limited number of
2113 speeds. The speed actually used won't be faster
2114 than the speed specified.
2116 Chip data sheets generally include a top JTAG clock rate.
2117 The actual rate is often a function of a CPU core clock,
2118 and is normally less than that peak rate.
2119 For example, most ARM cores accept at most one sixth of the CPU clock.
2121 Speed 0 (khz) selects RTCK method.
2122 @xref{FAQ RTCK}.
2123 If your system uses RTCK, you won't need to change the
2124 JTAG clocking after setup.
2125 Not all interfaces, boards, or targets support ``rtck''.
2126 If the interface device can not
2127 support it, an error is returned when you try to use RTCK.
2128 @end deffn
2130 @defun jtag_rclk fallback_speed_kHz
2131 @cindex adaptive clocking
2132 @cindex RTCK
2133 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
2134 If that fails (maybe the interface, board, or target doesn't
2135 support it), falls back to the specified frequency.
2136 @example
2137 # Fall back to 3mhz if RTCK is not supported
2138 jtag_rclk 3000
2139 @end example
2140 @end defun
2142 @node Reset Configuration
2143 @chapter Reset Configuration
2144 @cindex Reset Configuration
2146 Every system configuration may require a different reset
2147 configuration. This can also be quite confusing.
2148 Resets also interact with @var{reset-init} event handlers,
2149 which do things like setting up clocks and DRAM, and
2150 JTAG clock rates. (@xref{JTAG Speed}.)
2151 They can also interact with JTAG routers.
2152 Please see the various board files for examples.
2154 @quotation Note
2155 To maintainers and integrators:
2156 Reset configuration touches several things at once.
2157 Normally the board configuration file
2158 should define it and assume that the JTAG adapter supports
2159 everything that's wired up to the board's JTAG connector.
2161 However, the target configuration file could also make note
2162 of something the silicon vendor has done inside the chip,
2163 which will be true for most (or all) boards using that chip.
2164 And when the JTAG adapter doesn't support everything, the
2165 user configuration file will need to override parts of
2166 the reset configuration provided by other files.
2167 @end quotation
2169 @section Types of Reset
2171 There are many kinds of reset possible through JTAG, but
2172 they may not all work with a given board and adapter.
2173 That's part of why reset configuration can be error prone.
2175 @itemize @bullet
2176 @item
2177 @emph{System Reset} ... the @emph{SRST} hardware signal
2178 resets all chips connected to the JTAG adapter, such as processors,
2179 power management chips, and I/O controllers. Normally resets triggered
2180 with this signal behave exactly like pressing a RESET button.
2181 @item
2182 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
2183 just the TAP controllers connected to the JTAG adapter.
2184 Such resets should not be visible to the rest of the system; resetting a
2185 device's the TAP controller just puts that controller into a known state.
2186 @item
2187 @emph{Emulation Reset} ... many devices can be reset through JTAG
2188 commands. These resets are often distinguishable from system
2189 resets, either explicitly (a "reset reason" register says so)
2190 or implicitly (not all parts of the chip get reset).
2191 @item
2192 @emph{Other Resets} ... system-on-chip devices often support
2193 several other types of reset.
2194 You may need to arrange that a watchdog timer stops
2195 while debugging, preventing a watchdog reset.
2196 There may be individual module resets.
2197 @end itemize
2199 In the best case, OpenOCD can hold SRST, then reset
2200 the TAPs via TRST and send commands through JTAG to halt the
2201 CPU at the reset vector before the 1st instruction is executed.
2202 Then when it finally releases the SRST signal, the system is
2203 halted under debugger control before any code has executed.
2204 This is the behavior required to support the @command{reset halt}
2205 and @command{reset init} commands; after @command{reset init} a
2206 board-specific script might do things like setting up DRAM.
2207 (@xref{Reset Command}.)
2209 @anchor{SRST and TRST Issues}
2210 @section SRST and TRST Issues
2212 Because SRST and TRST are hardware signals, they can have a
2213 variety of system-specific constraints. Some of the most
2214 common issues are:
2216 @itemize @bullet
2218 @item @emph{Signal not available} ... Some boards don't wire
2219 SRST or TRST to the JTAG connector. Some JTAG adapters don't
2220 support such signals even if they are wired up.
2221 Use the @command{reset_config} @var{signals} options to say
2222 when either of those signals is not connected.
2223 When SRST is not available, your code might not be able to rely
2224 on controllers having been fully reset during code startup.
2225 Missing TRST is not a problem, since JTAG level resets can
2226 be triggered using with TMS signaling.
2228 @item @emph{Signals shorted} ... Sometimes a chip, board, or
2229 adapter will connect SRST to TRST, instead of keeping them separate.
2230 Use the @command{reset_config} @var{combination} options to say
2231 when those signals aren't properly independent.
2233 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
2234 delay circuit, reset supervisor, or on-chip features can extend
2235 the effect of a JTAG adapter's reset for some time after the adapter
2236 stops issuing the reset. For example, there may be chip or board
2237 requirements that all reset pulses last for at least a
2238 certain amount of time; and reset buttons commonly have
2239 hardware debouncing.
2240 Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
2241 commands to say when extra delays are needed.
2243 @item @emph{Drive type} ... Reset lines often have a pullup
2244 resistor, letting the JTAG interface treat them as open-drain
2245 signals. But that's not a requirement, so the adapter may need
2246 to use push/pull output drivers.
2247 Also, with weak pullups it may be advisable to drive
2248 signals to both levels (push/pull) to minimize rise times.
2249 Use the @command{reset_config} @var{trst_type} and
2250 @var{srst_type} parameters to say how to drive reset signals.
2252 @item @emph{Special initialization} ... Targets sometimes need
2253 special JTAG initialization sequences to handle chip-specific
2254 issues (not limited to errata).
2255 For example, certain JTAG commands might need to be issued while
2256 the system as a whole is in a reset state (SRST active)
2257 but the JTAG scan chain is usable (TRST inactive).
2258 Many systems treat combined assertion of SRST and TRST as a
2259 trigger for a harder reset than SRST alone.
2260 Such custom reset handling is discussed later in this chapter.
2261 @end itemize
2263 There can also be other issues.
2264 Some devices don't fully conform to the JTAG specifications.
2265 Trivial system-specific differences are common, such as
2266 SRST and TRST using slightly different names.
2267 There are also vendors who distribute key JTAG documentation for
2268 their chips only to developers who have signed a Non-Disclosure
2269 Agreement (NDA).
2271 Sometimes there are chip-specific extensions like a requirement to use
2272 the normally-optional TRST signal (precluding use of JTAG adapters which
2273 don't pass TRST through), or needing extra steps to complete a TAP reset.
2275 In short, SRST and especially TRST handling may be very finicky,
2276 needing to cope with both architecture and board specific constraints.
2278 @section Commands for Handling Resets
2280 @deffn {Command} jtag_nsrst_assert_width milliseconds
2281 Minimum amount of time (in milliseconds) OpenOCD should wait
2282 after asserting nSRST (active-low system reset) before
2283 allowing it to be deasserted.
2284 @end deffn
2286 @deffn {Command} jtag_nsrst_delay milliseconds
2287 How long (in milliseconds) OpenOCD should wait after deasserting
2288 nSRST (active-low system reset) before starting new JTAG operations.
2289 When a board has a reset button connected to SRST line it will
2290 probably have hardware debouncing, implying you should use this.
2291 @end deffn
2293 @deffn {Command} jtag_ntrst_assert_width milliseconds
2294 Minimum amount of time (in milliseconds) OpenOCD should wait
2295 after asserting nTRST (active-low JTAG TAP reset) before
2296 allowing it to be deasserted.
2297 @end deffn
2299 @deffn {Command} jtag_ntrst_delay milliseconds
2300 How long (in milliseconds) OpenOCD should wait after deasserting
2301 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
2302 @end deffn
2304 @deffn {Command} reset_config mode_flag ...
2305 This command displays or modifies the reset configuration
2306 of your combination of JTAG board and target in target
2307 configuration scripts.
2309 Information earlier in this section describes the kind of problems
2310 the command is intended to address (@pxref{SRST and TRST Issues}).
2311 As a rule this command belongs only in board config files,
2312 describing issues like @emph{board doesn't connect TRST};
2313 or in user config files, addressing limitations derived
2314 from a particular combination of interface and board.
2315 (An unlikely example would be using a TRST-only adapter
2316 with a board that only wires up SRST.)
2318 The @var{mode_flag} options can be specified in any order, but only one
2319 of each type -- @var{signals}, @var{combination},
2320 @var{gates},
2321 @var{trst_type},
2322 and @var{srst_type} -- may be specified at a time.
2323 If you don't provide a new value for a given type, its previous
2324 value (perhaps the default) is unchanged.
2325 For example, this means that you don't need to say anything at all about
2326 TRST just to declare that if the JTAG adapter should want to drive SRST,
2327 it must explicitly be driven high (@option{srst_push_pull}).
2329 @itemize
2330 @item
2331 @var{signals} can specify which of the reset signals are connected.
2332 For example, If the JTAG interface provides SRST, but the board doesn't
2333 connect that signal properly, then OpenOCD can't use it.
2334 Possible values are @option{none} (the default), @option{trst_only},
2335 @option{srst_only} and @option{trst_and_srst}.
2337 @quotation Tip
2338 If your board provides SRST and/or TRST through the JTAG connector,
2339 you must declare that so those signals can be used.
2340 @end quotation
2342 @item
2343 The @var{combination} is an optional value specifying broken reset
2344 signal implementations.
2345 The default behaviour if no option given is @option{separate},
2346 indicating everything behaves normally.
2347 @option{srst_pulls_trst} states that the
2348 test logic is reset together with the reset of the system (e.g. Philips
2349 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
2350 the system is reset together with the test logic (only hypothetical, I
2351 haven't seen hardware with such a bug, and can be worked around).
2352 @option{combined} implies both @option{srst_pulls_trst} and
2353 @option{trst_pulls_srst}.
2355 @item
2356 The @var{gates} tokens control flags that describe some cases where
2357 JTAG may be unvailable during reset.
2358 @option{srst_gates_jtag} (default)
2359 indicates that asserting SRST gates the
2360 JTAG clock. This means that no communication can happen on JTAG
2361 while SRST is asserted.
2362 Its converse is @option{srst_nogate}, indicating that JTAG commands
2363 can safely be issued while SRST is active.
2364 @end itemize
2366 The optional @var{trst_type} and @var{srst_type} parameters allow the
2367 driver mode of each reset line to be specified. These values only affect
2368 JTAG interfaces with support for different driver modes, like the Amontec
2369 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
2370 relevant signal (TRST or SRST) is not connected.
2372 @itemize
2373 @item
2374 Possible @var{trst_type} driver modes for the test reset signal (TRST)
2375 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
2376 Most boards connect this signal to a pulldown, so the JTAG TAPs
2377 never leave reset unless they are hooked up to a JTAG adapter.
2379 @item
2380 Possible @var{srst_type} driver modes for the system reset signal (SRST)
2381 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
2382 Most boards connect this signal to a pullup, and allow the
2383 signal to be pulled low by various events including system
2384 powerup and pressing a reset button.
2385 @end itemize
2386 @end deffn
2388 @section Custom Reset Handling
2389 @cindex events
2391 OpenOCD has several ways to help support the various reset
2392 mechanisms provided by chip and board vendors.
2393 The commands shown in the previous section give standard parameters.
2394 There are also @emph{event handlers} associated with TAPs or Targets.
2395 Those handlers are Tcl procedures you can provide, which are invoked
2396 at particular points in the reset sequence.
2398 After configuring those mechanisms, you might still
2399 find your board doesn't start up or reset correctly.
2400 For example, maybe it needs a slightly different sequence
2401 of SRST and/or TRST manipulations, because of quirks that
2402 the @command{reset_config} mechanism doesn't address;
2403 or asserting both might trigger a stronger reset, which
2404 needs special attention.
2406 Experiment with lower level operations, such as @command{jtag_reset}
2407 and the @command{jtag arp_*} operations shown here,
2408 to find a sequence of operations that works.
2409 @xref{JTAG Commands}.
2410 When you find a working sequence, it can be used to override
2411 @command{jtag_init}, which fires during OpenOCD startup
2412 (@pxref{Configuration Stage});
2413 or @command{init_reset}, which fires during reset processing.
2415 You might also want to provide some project-specific reset
2416 schemes. For example, on a multi-target board the standard
2417 @command{reset} command would reset all targets, but you
2418 may need the ability to reset only one target at time and
2419 thus want to avoid using the board-wide SRST signal.
2421 @deffn {Overridable Procedure} init_reset mode
2422 This is invoked near the beginning of the @command{reset} command,
2423 usually to provide as much of a cold (power-up) reset as practical.
2424 By default it is also invoked from @command{jtag_init} if
2425 the scan chain does not respond to pure JTAG operations.
2426 The @var{mode} parameter is the parameter given to the
2427 low level reset command (@option{halt},
2428 @option{init}, or @option{run}), @option{setup},
2429 or potentially some other value.
2431 The default implementation just invokes @command{jtag arp_init-reset}.
2432 Replacements will normally build on low level JTAG
2433 operations such as @command{jtag_reset}.
2434 Operations here must not address individual TAPs
2435 (or their associated targets)
2436 until the JTAG scan chain has first been verified to work.
2438 Implementations must have verified the JTAG scan chain before
2439 they return.
2440 This is done by calling @command{jtag arp_init}
2441 (or @command{jtag arp_init-reset}).
2442 @end deffn
2444 @deffn Command {jtag arp_init}
2445 This validates the scan chain using just the four
2446 standard JTAG signals (TMS, TCK, TDI, TDO).
2447 It starts by issuing a JTAG-only reset.
2448 Then it performs checks to verify that the scan chain configuration
2449 matches the TAPs it can observe.
2450 Those checks include checking IDCODE values for each active TAP,
2451 and verifying the length of their instruction registers using
2452 TAP @code{-ircapture} and @code{-irmask} values.
2453 If these tests all pass, TAP @code{setup} events are
2454 issued to all TAPs with handlers for that event.
2455 @end deffn
2457 @deffn Command {jtag arp_init-reset}
2458 This uses TRST and SRST to try resetting
2459 everything on the JTAG scan chain
2460 (and anything else connected to SRST).
2461 It then invokes the logic of @command{jtag arp_init}.
2462 @end deffn
2465 @node TAP Declaration
2466 @chapter TAP Declaration
2467 @cindex TAP declaration
2468 @cindex TAP configuration
2470 @emph{Test Access Ports} (TAPs) are the core of JTAG.
2471 TAPs serve many roles, including:
2473 @itemize @bullet
2474 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
2475 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
2476 Others do it indirectly, making a CPU do it.
2477 @item @b{Program Download} Using the same CPU support GDB uses,
2478 you can initialize a DRAM controller, download code to DRAM, and then
2479 start running that code.
2480 @item @b{Boundary Scan} Most chips support boundary scan, which
2481 helps test for board assembly problems like solder bridges
2482 and missing connections
2483 @end itemize
2485 OpenOCD must know about the active TAPs on your board(s).
2486 Setting up the TAPs is the core task of your configuration files.
2487 Once those TAPs are set up, you can pass their names to code
2488 which sets up CPUs and exports them as GDB targets,
2489 probes flash memory, performs low-level JTAG operations, and more.
2491 @section Scan Chains
2492 @cindex scan chain
2494 TAPs are part of a hardware @dfn{scan chain},
2495 which is daisy chain of TAPs.
2496 They also need to be added to
2497 OpenOCD's software mirror of that hardware list,
2498 giving each member a name and associating other data with it.
2499 Simple scan chains, with a single TAP, are common in
2500 systems with a single microcontroller or microprocessor.
2501 More complex chips may have several TAPs internally.
2502 Very complex scan chains might have a dozen or more TAPs:
2503 several in one chip, more in the next, and connecting
2504 to other boards with their own chips and TAPs.
2506 You can display the list with the @command{scan_chain} command.
2507 (Don't confuse this with the list displayed by the @command{targets}
2508 command, presented in the next chapter.
2509 That only displays TAPs for CPUs which are configured as
2510 debugging targets.)
2511 Here's what the scan chain might look like for a chip more than one TAP:
2513 @verbatim
2514 TapName Enabled IdCode Expected IrLen IrCap IrMask Instr
2515 -- ------------------ ------- ---------- ---------- ----- ----- ------ -----
2516 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0 0 0x...
2517 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x1 0 0xc
2518 2 omap5912.unknown Y 0x00000000 0x00000000 8 0 0 0xff
2519 @end verbatim
2521 Unfortunately those TAPs can't always be autoconfigured,
2522 because not all devices provide good support for that.
2523 JTAG doesn't require supporting IDCODE instructions, and
2524 chips with JTAG routers may not link TAPs into the chain
2525 until they are told to do so.
2527 The configuration mechanism currently supported by OpenOCD
2528 requires explicit configuration of all TAP devices using
2529 @command{jtag newtap} commands, as detailed later in this chapter.
2530 A command like this would declare one tap and name it @code{chip1.cpu}:
2532 @example
2533 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
2534 @end example
2536 Each target configuration file lists the TAPs provided
2537 by a given chip.
2538 Board configuration files combine all the targets on a board,
2539 and so forth.
2540 Note that @emph{the order in which TAPs are declared is very important.}
2541 It must match the order in the JTAG scan chain, both inside
2542 a single chip and between them.
2543 @xref{FAQ TAP Order}.
2545 For example, the ST Microsystems STR912 chip has
2546 three separate TAPs@footnote{See the ST
2547 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
2548 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
2549 @url{}}.
2550 To configure those taps, @file{target/str912.cfg}
2551 includes commands something like this:
2553 @example
2554 jtag newtap str912 flash ... params ...
2555 jtag newtap str912 cpu ... params ...
2556 jtag newtap str912 bs ... params ...
2557 @end example
2559 Actual config files use a variable instead of literals like
2560 @option{str912}, to support more than one chip of each type.
2561 @xref{Config File Guidelines}.
2563 @deffn Command {jtag names}
2564 Returns the names of all current TAPs in the scan chain.
2565 Use @command{jtag cget} or @command{jtag tapisenabled}
2566 to examine attributes and state of each TAP.
2567 @example
2568 foreach t [jtag names] @{
2569 puts [format "TAP: %s\n" $t]
2570 @}
2571 @end example
2572 @end deffn
2574 @deffn Command {scan_chain}
2575 Displays the TAPs in the scan chain configuration,
2576 and their status.
2577 The set of TAPs listed by this command is fixed by
2578 exiting the OpenOCD configuration stage,
2579 but systems with a JTAG router can
2580 enable or disable TAPs dynamically.
2581 In addition to the enable/disable status, the contents of
2582 each TAP's instruction register can also change.
2583 @end deffn
2585 @c FIXME! "jtag cget" should be able to return all TAP
2586 @c attributes, like "$target_name cget" does for targets.
2588 @c Probably want "jtag eventlist", and a "tap-reset" event
2589 @c (on entry to RESET state).
2591 @section TAP Names
2592 @cindex dotted name
2594 When TAP objects are declared with @command{jtag newtap},
2595 a @dfn{} is created for the TAP, combining the
2596 name of a module (usually a chip) and a label for the TAP.
2597 For example: @code{xilinx.tap}, @code{str912.flash},
2598 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
2599 Many other commands use that to manipulate or
2600 refer to the TAP. For example, CPU configuration uses the
2601 name, as does declaration of NAND or NOR flash banks.
2603 The components of a dotted name should follow ``C'' symbol
2604 name rules: start with an alphabetic character, then numbers
2605 and underscores are OK; while others (including dots!) are not.
2607 @quotation Tip
2608 In older code, JTAG TAPs were numbered from 0..N.
2609 This feature is still present.
2610 However its use is highly discouraged, and
2611 should not be relied on; it will be removed by mid-2010.
2612 Update all of your scripts to use TAP names rather than numbers,
2613 by paying attention to the runtime warnings they trigger.
2614 Using TAP numbers in target configuration scripts prevents
2615 reusing those scripts on boards with multiple targets.
2616 @end quotation
2618 @section TAP Declaration Commands
2620 @c shouldn't this be(come) a {Config Command}?
2621 @anchor{jtag newtap}
2622 @deffn Command {jtag newtap} chipname tapname configparams...
2623 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
2624 and configured according to the various @var{configparams}.
2626 The @var{chipname} is a symbolic name for the chip.
2627 Conventionally target config files use @code{$_CHIPNAME},
2628 defaulting to the model name given by the chip vendor but
2629 overridable.
2631 @cindex TAP naming convention
2632 The @var{tapname} reflects the role of that TAP,
2633 and should follow this convention:
2635 @itemize @bullet
2636 @item @code{bs} -- For boundary scan if this is a seperate TAP;
2637 @item @code{cpu} -- The main CPU of the chip, alternatively
2638 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
2639 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
2640 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
2641 @item @code{flash} -- If the chip has a flash TAP, like the str912;
2642 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
2643 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
2644 @item @code{tap} -- Should be used only FPGA or CPLD like devices
2645 with a single TAP;
2646 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
2647 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
2648 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
2649 a JTAG TAP; that TAP should be named @code{sdma}.
2650 @end itemize
2652 Every TAP requires at least the following @var{configparams}:
2654 @itemize @bullet
2655 @item @code{-irlen} @var{NUMBER}
2656 @*The length in bits of the
2657 instruction register, such as 4 or 5 bits.
2658 @end itemize
2660 A TAP may also provide optional @var{configparams}:
2662 @itemize @bullet
2663 @item @code{-disable} (or @code{-enable})
2664 @*Use the @code{-disable} parameter to flag a TAP which is not
2665 linked in to the scan chain after a reset using either TRST
2666 or the JTAG state machine's @sc{reset} state.
2667 You may use @code{-enable} to highlight the default state
2668 (the TAP is linked in).
2669 @xref{Enabling and Disabling TAPs}.
2670 @item @code{-expected-id} @var{number}
2671 @*A non-zero @var{number} represents a 32-bit IDCODE
2672 which you expect to find when the scan chain is examined.
2673 These codes are not required by all JTAG devices.
2674 @emph{Repeat the option} as many times as required if more than one
2675 ID code could appear (for example, multiple versions).
2676 Specify @var{number} as zero to suppress warnings about IDCODE
2677 values that were found but not included in the list.
2679 Provide this value if at all possible, since it lets OpenOCD
2680 tell when the scan chain it sees isn't right. These values
2681 are provided in vendors' chip documentation, usually a technical
2682 reference manual. Sometimes you may need to probe the JTAG
2683 hardware to find these values.
2684 @xref{Autoprobing}.
2685 @item @code{-ircapture} @var{NUMBER}
2686 @*The bit pattern loaded by the TAP into the JTAG shift register
2687 on entry to the @sc{ircapture} state, such as 0x01.
2688 JTAG requires the two LSBs of this value to be 01.
2689 By default, @code{-ircapture} and @code{-irmask} are set
2690 up to verify that two-bit value. You may provide
2691 additional bits, if you know them, or indicate that
2692 a TAP doesn't conform to the JTAG specification.
2693 @item @code{-irmask} @var{NUMBER}
2694 @*A mask used with @code{-ircapture}
2695 to verify that instruction scans work correctly.
2696 Such scans are not used by OpenOCD except to verify that
2697 there seems to be no problems with JTAG scan chain operations.
2698 @end itemize
2699 @end deffn
2701 @section Other TAP commands
2703 @deffn Command {jtag cget} @option{-event} name
2704 @deffnx Command {jtag configure} @option{-event} name string
2705 At this writing this TAP attribute
2706 mechanism is used only for event handling.
2707 (It is not a direct analogue of the @code{cget}/@code{configure}
2708 mechanism for debugger targets.)
2709 See the next section for information about the available events.
2711 The @code{configure} subcommand assigns an event handler,
2712 a TCL string which is evaluated when the event is triggered.
2713 The @code{cget} subcommand returns that handler.
2714 @end deffn
2716 @anchor{TAP Events}
2717 @section TAP Events
2718 @cindex events
2719 @cindex TAP events
2721 OpenOCD includes two event mechanisms.
2722 The one presented here applies to all JTAG TAPs.
2723 The other applies to debugger targets,
2724 which are associated with certain TAPs.
2726 The TAP events currently defined are:
2728 @itemize @bullet
2729 @item @b{post-reset}
2730 @* The TAP has just completed a JTAG reset.
2731 The tap may still be in the JTAG @sc{reset} state.
2732 Handlers for these events might perform initialization sequences
2733 such as issuing TCK cycles, TMS sequences to ensure
2734 exit from the ARM SWD mode, and more.
2736 Because the scan chain has not yet been verified, handlers for these events
2737 @emph{should not issue commands which scan the JTAG IR or DR registers}
2738 of any particular target.
2739 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
2740 @item @b{setup}
2741 @* The scan chain has been reset and verified.
2742 This handler may enable TAPs as needed.
2743 @item @b{tap-disable}
2744 @* The TAP needs to be disabled. This handler should
2745 implement @command{jtag tapdisable}
2746 by issuing the relevant JTAG commands.
2747 @item @b{tap-enable}
2748 @* The TAP needs to be enabled. This handler should
2749 implement @command{jtag tapenable}
2750 by issuing the relevant JTAG commands.
2751 @end itemize
2753 If you need some action after each JTAG reset, which isn't actually
2754 specific to any TAP (since you can't yet trust the scan chain's
2755 contents to be accurate), you might:
2757 @example
2758 jtag configure CHIP.jrc -event post-reset @{
2759 echo "JTAG Reset done"
2760 ... non-scan jtag operations to be done after reset
2761 @}
2762 @end example
2765 @anchor{Enabling and Disabling TAPs}
2766 @section Enabling and Disabling TAPs
2767 @cindex JTAG Route Controller
2768 @cindex jrc
2770 In some systems, a @dfn{JTAG Route Controller} (JRC)
2771 is used to enable and/or disable specific JTAG TAPs.
2772 Many ARM based chips from Texas Instruments include
2773 an ``ICEpick'' module, which is a JRC.
2774 Such chips include DaVinci and OMAP3 processors.
2776 A given TAP may not be visible until the JRC has been
2777 told to link it into the scan chain; and if the JRC
2778 has been told to unlink that TAP, it will no longer
2779 be visible.
2780 Such routers address problems that JTAG ``bypass mode''
2781 ignores, such as:
2783 @itemize
2784 @item The scan chain can only go as fast as its slowest TAP.
2785 @item Having many TAPs slows instruction scans, since all
2786 TAPs receive new instructions.
2787 @item TAPs in the scan chain must be powered up, which wastes
2788 power and prevents debugging some power management mechanisms.
2789 @end itemize
2791 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
2792 as implied by the existence of JTAG routers.
2793 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
2794 does include a kind of JTAG router functionality.
2796 @c (a) currently the event handlers don't seem to be able to
2797 @c fail in a way that could lead to no-change-of-state.
2799 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
2800 shown below, and is implemented using TAP event handlers.
2801 So for example, when defining a TAP for a CPU connected to
2802 a JTAG router, your @file{target.cfg} file
2803 should define TAP event handlers using
2804 code that looks something like this:
2806 @example
2807 jtag configure CHIP.cpu -event tap-enable @{
2808 ... jtag operations using CHIP.jrc
2809 @}
2810 jtag configure CHIP.cpu -event tap-disable @{
2811 ... jtag operations using CHIP.jrc
2812 @}
2813 @end example
2815 Then you might want that CPU's TAP enabled almost all the time:
2817 @example
2818 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
2819 @end example
2821 Note how that particular setup event handler declaration
2822 uses quotes to evaluate @code{$CHIP} when the event is configured.
2823 Using brackets @{ @} would cause it to be evaluated later,
2824 at runtime, when it might have a different value.
2826 @deffn Command {jtag tapdisable}
2827 If necessary, disables the tap
2828 by sending it a @option{tap-disable} event.
2829 Returns the string "1" if the tap
2830 specified by @var{} is enabled,
2831 and "0" if it is disabled.
2832 @end deffn
2834 @deffn Command {jtag tapenable}
2835 If necessary, enables the tap
2836 by sending it a @option{tap-enable} event.
2837 Returns the string "1" if the tap
2838 specified by @var{} is enabled,
2839 and "0" if it is disabled.
2840 @end deffn
2842 @deffn Command {jtag tapisenabled}
2843 Returns the string "1" if the tap
2844 specified by @var{} is enabled,
2845 and "0" if it is disabled.
2847 @quotation Note
2848 Humans will find the @command{scan_chain} command more helpful
2849 for querying the state of the JTAG taps.
2850 @end quotation
2851 @end deffn
2853 @anchor{Autoprobing}
2854 @section Autoprobing
2855 @cindex autoprobe
2856 @cindex JTAG autoprobe
2858 TAP configuration is the first thing that needs to be done
2859 after interface and reset configuration. Sometimes it's
2860 hard finding out what TAPs exist, or how they are identified.
2861 Vendor documentation is not always easy to find and use.
2863 To help you get past such problems, OpenOCD has a limited
2864 @emph{autoprobing} ability to look at the scan chain, doing
2865 a @dfn{blind interrogation} and then reporting the TAPs it finds.
2866 To use this mechanism, start the OpenOCD server with only data
2867 that configures your JTAG interface, and arranges to come up
2868 with a slow clock (many devices don't support fast JTAG clocks
2869 right when they come out of reset).
2871 For example, your @file{openocd.cfg} file might have:
2873 @example
2874 source [find interface/olimex-arm-usb-tiny-h.cfg]
2875 reset_config trst_and_srst
2876 jtag_rclk 8
2877 @end example
2879 When you start the server without any TAPs configured, it will
2880 attempt to autoconfigure the TAPs. There are two parts to this:
2882 @enumerate
2883 @item @emph{TAP discovery} ...
2884 After a JTAG reset (sometimes a system reset may be needed too),
2885 each TAP's data registers will hold the contents of either the
2886 IDCODE or BYPASS register.
2887 If JTAG communication is working, OpenOCD will see each TAP,
2888 and report what @option{-expected-id} to use with it.
2889 @item @emph{IR Length discovery} ...
2890 Unfortunately JTAG does not provide a reliable way to find out
2891 the value of the @option{-irlen} parameter to use with a TAP
2892 that is discovered.
2893 If OpenOCD can discover the length of a TAP's instruction
2894 register, it will report it.
2895 Otherwise you may need to consult vendor documentation, such
2896 as chip data sheets or BSDL files.
2897 @end enumerate
2899 In many cases your board will have a simple scan chain with just
2900 a single device. Here's what OpenOCD reported with one board
2901 that's a bit more complex:
2903 @example
2904 clock speed 8 kHz
2905 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
2906 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
2907 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
2908 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
2909 AUTO auto0.tap - use "... -irlen 4"
2910 AUTO auto1.tap - use "... -irlen 4"
2911 AUTO auto2.tap - use "... -irlen 6"
2912 no gdb ports allocated as no target has been specified
2913 @end example
2915 Given that information, you should be able to either find some existing
2916 config files to use, or create your own. If you create your own, you
2917 would configure from the bottom up: first a @file{target.cfg} file
2918 with these TAPs, any targets associated with them, and any on-chip
2919 resources; then a @file{board.cfg} with off-chip resources, clocking,
2920 and so forth.
2922 @node CPU Configuration
2923 @chapter CPU Configuration
2924 @cindex GDB target
2926 This chapter discusses how to set up GDB debug targets for CPUs.
2927 You can also access these targets without GDB
2928 (@pxref{Architecture and Core Commands},
2929 and @ref{Target State handling}) and
2930 through various kinds of NAND and NOR flash commands.
2931 If you have multiple CPUs you can have multiple such targets.
2933 We'll start by looking at how to examine the targets you have,
2934 then look at how to add one more target and how to configure it.
2936 @section Target List
2937 @cindex target, current
2938 @cindex target, list
2940 All targets that have been set up are part of a list,
2941 where each member has a name.
2942 That name should normally be the same as the TAP name.
2943 You can display the list with the @command{targets}
2944 (plural!) command.
2945 This display often has only one CPU; here's what it might
2946 look like with more than one:
2947 @verbatim
2948 TargetName Type Endian TapName State
2949 -- ------------------ ---------- ------ ------------------ ------------
2950 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
2951 1 MyTarget cortex_m3 little tap-disabled
2952 @end verbatim
2954 One member of that list is the @dfn{current target}, which
2955 is implicitly referenced by many commands.
2956 It's the one marked with a @code{*} near the target name.
2957 In particular, memory addresses often refer to the address
2958 space seen by that current target.
2959 Commands like @command{mdw} (memory display words)
2960 and @command{flash erase_address} (erase NOR flash blocks)
2961 are examples; and there are many more.
2963 Several commands let you examine the list of targets:
2965 @deffn Command {target count}
2966 @emph{Note: target numbers are deprecated; don't use them.
2967 They will be removed shortly after August 2010, including this command.
2968 Iterate target using @command{target names}, not by counting.}
2970 Returns the number of targets, @math{N}.
2971 The highest numbered target is @math{N - 1}.
2972 @example
2973 set c [target count]
2974 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
2975 # Assuming you have created this function
2976 print_target_details $x
2977 @}
2978 @end example
2979 @end deffn
2981 @deffn Command {target current}
2982 Returns the name of the current target.
2983 @end deffn
2985 @deffn Command {target names}
2986 Lists the names of all current targets in the list.
2987 @example
2988 foreach t [target names] @{
2989 puts [format "Target: %s\n" $t]
2990 @}
2991 @end example
2992 @end deffn
2994 @deffn Command {target number} number
2995 @emph{Note: target numbers are deprecated; don't use them.
2996 They will be removed shortly after August 2010, including this command.}
2998 The list of targets is numbered starting at zero.
2999 This command returns the name of the target at index @var{number}.
3000 @example
3001 set thename [target number $x]
3002 puts [format "Target %d is: %s\n" $x $thename]
3003 @end example
3004 @end deffn
3006 @c yep, "target list" would have been better.
3007 @c plus maybe "target setdefault".
3009 @deffn Command targets [name]
3010 @emph{Note: the name of this command is plural. Other target
3011 command names are singular.}
3013 With no parameter, this command displays a table of all known
3014 targets in a user friendly form.
3016 With a parameter, this command sets the current target to
3017 the given target with the given @var{name}; this is
3018 only relevant on boards which have more than one target.
3019 @end deffn
3021 @section Target CPU Types and Variants
3022 @cindex target type
3023 @cindex CPU type
3024 @cindex CPU variant
3026 Each target has a @dfn{CPU type}, as shown in the output of
3027 the @command{targets} command. You need to specify that type
3028 when calling @command{target create}.
3029 The CPU type indicates more than just the instruction set.
3030 It also indicates how that instruction set is implemented,
3031 what kind of debug support it integrates,
3032 whether it has an MMU (and if so, what kind),
3033 what core-specific commands may be available
3034 (@pxref{Architecture and Core Commands}),
3035 and more.
3037 For some CPU types, OpenOCD also defines @dfn{variants} which
3038 indicate differences that affect their handling.
3039 For example, a particular implementation bug might need to be
3040 worked around in some chip versions.
3042 It's easy to see what target types are supported,
3043 since there's a command to list them.
3044 However, there is currently no way to list what target variants
3045 are supported (other than by reading the OpenOCD source code).
3047 @anchor{target types}
3048 @deffn Command {target types}
3049 Lists all supported target types.
3050 At this writing, the supported CPU types and variants are:
3052 @itemize @bullet
3053 @item @code{arm11} -- this is a generation of ARMv6 cores
3054 @item @code{arm720t} -- this is an ARMv4 core with an MMU
3055 @item @code{arm7tdmi} -- this is an ARMv4 core
3056 @item @code{arm920t} -- this is an ARMv5 core with an MMU
3057 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
3058 @item @code{arm966e} -- this is an ARMv5 core
3059 @item @code{arm9tdmi} -- this is an ARMv4 core
3060 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
3061 (Support for this is preliminary and incomplete.)
3062 @item @code{cortex_a8} -- this is an ARMv7 core with an MMU
3063 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
3064 compact Thumb2 instruction set. It supports one variant:
3065 @itemize @minus
3066 @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
3067 This will cause OpenOCD to use a software reset rather than asserting
3068 SRST, to avoid a issue with clearing the debug registers.
3069 This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
3070 be detected and the normal reset behaviour used.
3071 @end itemize
3072 @item @code{dragonite} -- resembles arm966e
3073 @item @code{fa526} -- resembles arm920 (w/o Thumb)
3074 @item @code{feroceon} -- resembles arm926
3075 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
3076 @itemize @minus
3077 @item @code{ejtag_srst} ... Use this when debugging targets that do not
3078 provide a functional SRST line on the EJTAG connector. This causes
3079 OpenOCD to instead use an EJTAG software reset command to reset the
3080 processor.
3081 You still need to enable @option{srst} on the @command{reset_config}
3082 command to enable OpenOCD hardware reset functionality.
3083 @end itemize
3084 @item @code{xscale} -- this is actually an architecture,
3085 not a CPU type. It is based on the ARMv5 architecture.
3086 There are several variants defined:
3087 @itemize @minus
3088 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
3089 @code{pxa27x} ... instruction register length is 7 bits
3090 @item @code{pxa250}, @code{pxa255},
3091 @code{pxa26x} ... instruction register length is 5 bits
3092 @end itemize
3093 @end itemize
3094 @end deffn
3096 To avoid being confused by the variety of ARM based cores, remember
3097 this key point: @emph{ARM is a technology licencing company}.
3098 (See: @url{}.)
3099 The CPU name used by OpenOCD will reflect the CPU design that was
3100 licenced, not a vendor brand which incorporates that design.
3101 Name prefixes like arm7, arm9, arm11, and cortex
3102 reflect design generations;
3103 while names like ARMv4, ARMv5, ARMv6, and ARMv7
3104 reflect an architecture version implemented by a CPU design.
3106 @anchor{Target Configuration}
3107 @section Target Configuration
3109 Before creating a ``target'', you must have added its TAP to the scan chain.
3110 When you've added that TAP, you will have a @code{}
3111 which is used to set up the CPU support.
3112 The chip-specific configuration file will normally configure its CPU(s)
3113 right after it adds all of the chip's TAPs to the scan chain.
3115 Although you can set up a target in one step, it's often clearer if you
3116 use shorter commands and do it in two steps: create it, then configure
3117 optional parts.
3118 All operations on the target after it's created will use a new
3119 command, created as part of target creation.
3121 The two main things to configure after target creation are
3122 a work area, which usually has target-specific defaults even
3123 if the board setup code overrides them later;
3124 and event handlers (@pxref{Target Events}), which tend
3125 to be much more board-specific.
3126 The key steps you use might look something like this
3128 @example
3129 target create MyTarget cortex_m3 -chain-position mychip.cpu
3130 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
3131 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
3132 $MyTarget configure -event reset-init @{ myboard_reinit @}
3133 @end example
3135 You should specify a working area if you can; typically it uses some
3136 on-chip SRAM.
3137 Such a working area can speed up many things, including bulk
3138 writes to target memory;
3139 flash operations like checking to see if memory needs to be erased;
3140 GDB memory checksumming;
3141 and more.
3143 @quotation Warning
3144 On more complex chips, the work area can become
3145 inaccessible when application code
3146 (such as an operating system)
3147 enables or disables the MMU.
3148 For example, the particular MMU context used to acess the virtual
3149 address will probably matter ... and that context might not have
3150 easy access to other addresses needed.
3151 At this writing, OpenOCD doesn't have much MMU intelligence.
3152 @end quotation
3154 It's often very useful to define a @code{reset-init} event handler.
3155 For systems that are normally used with a boot loader,
3156 common tasks include updating clocks and initializing memory
3157 controllers.
3158 That may be needed to let you write the boot loader into flash,
3159 in order to ``de-brick'' your board; or to load programs into
3160 external DDR memory without having run the boot loader.
3162 @deffn Command {target create} target_name type configparams...
3163 This command creates a GDB debug target that refers to a specific JTAG tap.
3164 It enters that target into a list, and creates a new
3165 command (@command{@var{target_name}}) which is used for various
3166 purposes including additional configuration.
3168 @itemize @bullet
3169 @item @var{target_name} ... is the name of the debug target.
3170 By convention this should be the same as the @emph{}
3171 of the TAP associated with this target, which must be specified here
3172 using the @code{-chain-position @var{}} configparam.
3174 This name is also used to create the target object command,
3175 referred to here as @command{$target_name},
3176 and in other places the target needs to be identified.
3177 @item @var{type} ... specifies the target type. @xref{target types}.
3178 @item @var{configparams} ... all parameters accepted by
3179 @command{$target_name configure} are permitted.
3180 If the target is big-endian, set it here with @code{-endian big}.
3181 If the variant matters, set it here with @code{-variant}.
3183 You @emph{must} set the @code{-chain-position @var{}} here.
3184 @end itemize
3185 @end deffn
3187 @deffn Command {$target_name configure} configparams...
3188 The options accepted by this command may also be
3189 specified as parameters to @command{target create}.
3190 Their values can later be queried one at a time by
3191 using the @command{$target_name cget} command.
3193 @emph{Warning:} changing some of these after setup is dangerous.
3194 For example, moving a target from one TAP to another;
3195 and changing its endianness or variant.
3197 @itemize @bullet
3199 @item @code{-chain-position} @var{} -- names the TAP
3200 used to access this target.
3202 @item @code{-endian} (@option{big}|@option{little}) -- specifies
3203 whether the CPU uses big or little endian conventions
3205 @item @code{-event} @var{event_name} @var{event_body} --
3206 @xref{Target Events}.
3207 Note that this updates a list of named event handlers.
3208 Calling this twice with two different event names assigns
3209 two different handlers, but calling it twice with the
3210 same event name assigns only one handler.
3212 @item @code{-variant} @var{name} -- specifies a variant of the target,
3213 which OpenOCD needs to know about.
3215 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
3216 whether the work area gets backed up; by default,
3217 @emph{it is not backed up.}
3218 When possible, use a working_area that doesn't need to be backed up,
3219 since performing a backup slows down operations.
3220 For example, the beginning of an SRAM block is likely to
3221 be used by most build systems, but the end is often unused.
3223 @item @code{-work-area-size} @var{size} -- specify work are size,
3224 in bytes. The same size applies regardless of whether its physical
3225 or virtual address is being used.
3227 @item @code{-work-area-phys} @var{address} -- set the work area
3228 base @var{address} to be used when no MMU is active.
3230 @item @code{-work-area-virt} @var{address} -- set the work area
3231 base @var{address} to be used when an MMU is active.
3232 @emph{Do not specify a value for this except on targets with an MMU.}
3233 The value should normally correspond to a static mapping for the
3234 @code{-work-area-phys} address, set up by the current operating system.
3236 @end itemize
3237 @end deffn
3239 @section Other $target_name Commands
3240 @cindex object command
3242 The Tcl/Tk language has the concept of object commands,
3243 and OpenOCD adopts that same model for targets.
3245 A good Tk example is a on screen button.
3246 Once a button is created a button
3247 has a name (a path in Tk terms) and that name is useable as a first
3248 class command. For example in Tk, one can create a button and later
3249 configure it like this:
3251 @example
3252 # Create
3253 button .foobar -background red -command @{ foo @}
3254 # Modify
3255 .foobar configure -foreground blue
3256 # Query
3257 set x [.foobar cget -background]
3258 # Report
3259 puts [format "The button is %s" $x]
3260 @end example
3262 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
3263 button, and its object commands are invoked the same way.
3265 @example
3266 str912.cpu mww 0x1234 0x42
3267 omap3530.cpu mww 0x5555 123
3268 @end example
3270 The commands supported by OpenOCD target objects are:
3272 @deffn Command {$target_name arp_examine}
3273 @deffnx Command {$target_name arp_halt}
3274 @deffnx Command {$target_name arp_poll}
3275 @deffnx Command {$target_name arp_reset}
3276 @deffnx Command {$target_name arp_waitstate}
3277 Internal OpenOCD scripts (most notably @file{startup.tcl})
3278 use these to deal with specific reset cases.
3279 They are not otherwise documented here.
3280 @end deffn
3282 @deffn Command {$target_name array2mem} arrayname width address count
3283 @deffnx Command {$target_name mem2array} arrayname width address count
3284 These provide an efficient script-oriented interface to memory.
3285 The @code{array2mem} primitive writes bytes, halfwords, or words;
3286 while @code{mem2array} reads them.
3287 In both cases, the TCL side uses an array, and
3288 the target side uses raw memory.
3290 The efficiency comes from enabling the use of
3291 bulk JTAG data transfer operations.
3292 The script orientation comes from working with data
3293 values that are packaged for use by TCL scripts;
3294 @command{mdw} type primitives only print data they retrieve,
3295 and neither store nor return those values.
3297 @itemize
3298 @item @var{arrayname} ... is the name of an array variable
3299 @item @var{width} ... is 8/16/32 - indicating the memory access size
3300 @item @var{address} ... is the target memory address
3301 @item @var{count} ... is the number of elements to process
3302 @end itemize
3303 @end deffn
3305 @deffn Command {$target_name cget} queryparm
3306 Each configuration parameter accepted by
3307 @command{$target_name configure}
3308 can be individually queried, to return its current value.
3309 The @var{queryparm} is a parameter name
3310 accepted by that command, such as @code{-work-area-phys}.
3311 There are a few special cases:
3313 @itemize @bullet
3314 @item @code{-event} @var{event_name} -- returns the handler for the
3315 event named @var{event_name}.
3316 This is a special case because setting a handler requires
3317 two parameters.
3318 @item @code{-type} -- returns the target type.
3319 This is a special case because this is set using
3320 @command{target create} and can't be changed
3321 using @command{$target_name configure}.
3322 @end itemize
3324 For example, if you wanted to summarize information about
3325 all the targets you might use something like this:
3327 @example
3328 foreach name [target names] @{
3329 set y [$name cget -endian]
3330 set z [$name cget -type]
3331 puts [format "Chip %d is %s, Endian: %s, type: %s" \
3332 $x $name $y $z]
3333 @}
3334 @end example
3335 @end deffn
3337 @anchor{target curstate}
3338 @deffn Command {$target_name curstate}
3339 Displays the current target state:
3340 @code{debug-running},
3341 @code{halted},
3342 @code{reset},
3343 @code{running}, or @code{unknown}.
3344 (Also, @pxref{Event Polling}.)
3345 @end deffn
3347 @deffn Command {$target_name eventlist}
3348 Displays a table listing all event handlers
3349 currently associated with this target.
3350 @xref{Target Events}.
3351 @end deffn
3353 @deffn Command {$target_name invoke-event} event_name
3354 Invokes the handler for the event named @var{event_name}.
3355 (This is primarily intended for use by OpenOCD framework
3356 code, for example by the reset code in @file{startup.tcl}.)
3357 @end deffn
3359 @deffn Command {$target_name mdw} addr [count]
3360 @deffnx Command {$target_name mdh} addr [count]
3361 @deffnx Command {$target_name mdb} addr [count]
3362 Display contents of address @var{addr}, as
3363 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
3364 or 8-bit bytes (@command{mdb}).
3365 If @var{count} is specified, displays that many units.
3366 (If you want to manipulate the data instead of displaying it,
3367 see the @code{mem2array} primitives.)
3368 @end deffn
3370 @deffn Command {$target_name mww} addr word
3371 @deffnx Command {$target_name mwh} addr halfword
3372 @deffnx Command {$target_name mwb} addr byte
3373 Writes the specified @var{word} (32 bits),
3374 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3375 at the specified address @var{addr}.
3376 @end deffn
3378 @anchor{Target Events}
3379 @section Target Events
3380 @cindex target events
3381 @cindex events
3382 At various times, certain things can happen, or you want them to happen.
3383 For example:
3384 @itemize @bullet
3385 @item What should happen when GDB connects? Should your target reset?
3386 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
3387 @item During reset, do you need to write to certain memory locations
3388 to set up system clocks or
3389 to reconfigure the SDRAM?
3390 @end itemize
3392 All of the above items can be addressed by target event handlers.
3393 These are set up by @command{$target_name configure -event} or
3394 @command{target create ... -event}.
3396 The programmer's model matches the @code{-command} option used in Tcl/Tk
3397 buttons and events. The two examples below act the same, but one creates
3398 and invokes a small procedure while the other inlines it.
3400 @example
3401 proc my_attach_proc @{ @} @{
3402 echo "Reset..."
3403 reset halt
3404 @}
3405 mychip.cpu configure -event gdb-attach my_attach_proc
3406 mychip.cpu configure -event gdb-attach @{
3407 echo "Reset..."
3408 reset halt
3409 @}
3410 @end example
3412 The following target events are defined:
3414 @itemize @bullet
3415 @item @b{debug-halted}
3416 @* The target has halted for debug reasons (i.e.: breakpoint)
3417 @item @b{debug-resumed}
3418 @* The target has resumed (i.e.: gdb said run)
3419 @item @b{early-halted}
3420 @* Occurs early in the halt process
3421 @ignore
3422 @item @b{examine-end}
3423 @* Currently not used (goal: when JTAG examine completes)
3424 @item @b{examine-start}
3425 @* Currently not used (goal: when JTAG examine starts)
3426 @end ignore
3427 @item @b{gdb-attach}
3428 @* When GDB connects
3429 @item @b{gdb-detach}
3430 @* When GDB disconnects
3431 @item @b{gdb-end}
3432 @* When the target has halted and GDB is not doing anything (see early halt)
3433 @item @b{gdb-flash-erase-start}
3434 @* Before the GDB flash process tries to erase the flash
3435 @item @b{gdb-flash-erase-end}
3436 @* After the GDB flash process has finished erasing the flash
3437 @item @b{gdb-flash-write-start}
3438 @* Before GDB writes to the flash
3439 @item @b{gdb-flash-write-end}
3440 @* After GDB writes to the flash
3441 @item @b{gdb-start}
3442 @* Before the target steps, gdb is trying to start/resume the target
3443 @item @b{halted}
3444 @* The target has halted
3445 @ignore
3446 @item @b{old-gdb_program_config}
3447 @* DO NOT USE THIS: Used internally
3448 @item @b{old-pre_resume}
3449 @* DO NOT USE THIS: Used internally
3450 @end ignore
3451 @item @b{reset-assert-pre}
3452 @* Issued as part of @command{reset} processing
3453 after @command{reset_init} was triggered
3454 but before SRST alone is re-asserted on the tap.
3455 @item @b{reset-assert-post}
3456 @* Issued as part of @command{reset} processing
3457 when SRST is asserted on the tap.
3458 @item @b{reset-deassert-pre}
3459 @* Issued as part of @command{reset} processing
3460 when SRST is about to be released on the tap.
3461 @item @b{reset-deassert-post}
3462 @* Issued as part of @command{reset} processing
3463 when SRST has been released on the tap.
3464 @item @b{reset-end}
3465 @* Issued as the final step in @command{reset} processing.
3466 @ignore
3467 @item @b{reset-halt-post}
3468 @* Currently not used
3469 @item @b{reset-halt-pre}
3470 @* Currently not used
3471 @end ignore
3472 @item @b{reset-init}
3473 @* Used by @b{reset init} command for board-specific initialization.
3474 This event fires after @emph{reset-deassert-post}.
3476 This is where you would configure PLLs and clocking, set up DRAM so
3477 you can download programs that don't fit in on-chip SRAM, set up pin
3478 multiplexing, and so on.
3479 (You may be able to switch to a fast JTAG clock rate here, after
3480 the target clocks are fully set up.)
3481 @item @b{reset-start}
3482 @* Issued as part of @command{reset} processing
3483 before @command{reset_init} is called.
3485 This is the most robust place to use @command{jtag_rclk}
3486 or @command{jtag_khz} to switch to a low JTAG clock rate,
3487 when reset disables PLLs needed to use a fast clock.
3488 @ignore
3489 @item @b{reset-wait-pos}
3490 @* Currently not used
3491 @item @b{reset-wait-pre}
3492 @* Currently not used
3493 @end ignore
3494 @item @b{resume-start}
3495 @* Before any target is resumed
3496 @item @b{resume-end}
3497 @* After all targets have resumed
3498 @item @b{resume-ok}
3499 @* Success
3500 @item @b{resumed}
3501 @* Target has resumed
3502 @end itemize
3505 @node Flash Commands
3506 @chapter Flash Commands
3508 OpenOCD has different commands for NOR and NAND flash;
3509 the ``flash'' command works with NOR flash, while
3510 the ``nand'' command works with NAND flash.
3511 This partially reflects different hardware technologies:
3512 NOR flash usually supports direct CPU instruction and data bus access,
3513 while data from a NAND flash must be copied to memory before it can be
3514 used. (SPI flash must also be copied to memory before use.)
3515 However, the documentation also uses ``flash'' as a generic term;
3516 for example, ``Put flash configuration in board-specific files''.
3518 Flash Steps:
3519 @enumerate
3520 @item Configure via the command @command{flash bank}
3521 @* Do this in a board-specific configuration file,
3522 passing parameters as needed by the driver.
3523 @item Operate on the flash via @command{flash subcommand}
3524 @* Often commands to manipulate the flash are typed by a human, or run
3525 via a script in some automated way. Common tasks include writing a
3526 boot loader, operating system, or other data.
3527 @item GDB Flashing
3528 @* Flashing via GDB requires the flash be configured via ``flash
3529 bank'', and the GDB flash features be enabled.
3530 @xref{GDB Configuration}.
3531 @end enumerate
3533 Many CPUs have the ablity to ``boot'' from the first flash bank.
3534 This means that misprogramming that bank can ``brick'' a system,
3535 so that it can't boot.
3536 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
3537 board by (re)installing working boot firmware.
3539 @anchor{NOR Configuration}
3540 @section Flash Configuration Commands
3541 @cindex flash configuration
3543 @deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
3544 Configures a flash bank which provides persistent storage
3545 for addresses from @math{base} to @math{base + size - 1}.
3546 These banks will often be visible to GDB through the target's memory map.
3547 In some cases, configuring a flash bank will activate extra commands;
3548 see the driver-specific documentation.
3550 @itemize @bullet
3551 @item @var{driver} ... identifies the controller driver
3552 associated with the flash bank being declared.
3553 This is usually @code{cfi} for external flash, or else
3554 the name of a microcontroller with embedded flash memory.
3555 @xref{Flash Driver List}.
3556 @item @var{base} ... Base address of the flash chip.
3557 @item @var{size} ... Size of the chip, in bytes.
3558 For some drivers, this value is detected from the hardware.
3559 @item @var{chip_width} ... Width of the flash chip, in bytes;
3560 ignored for most microcontroller drivers.
3561 @item @var{bus_width} ... Width of the data bus used to access the
3562 chip, in bytes; ignored for most microcontroller drivers.
3563 @item @var{target} ... Names the target used to issue
3564 commands to the flash controller.
3565 @comment Actually, it's currently a controller-specific parameter...
3566 @item @var{driver_options} ... drivers may support, or require,
3567 additional parameters. See the driver-specific documentation
3568 for more information.
3569 @end itemize
3570 @quotation Note
3571 This command is not available after OpenOCD initialization has completed.
3572 Use it in board specific configuration files, not interactively.
3573 @end quotation
3574 @end deffn
3576 @comment the REAL name for this command is "ocd_flash_banks"
3577 @comment less confusing would be: "flash list" (like "nand list")
3578 @deffn Command {flash banks}
3579 Prints a one-line summary of each device declared
3580 using @command{flash bank}, numbered from zero.
3581 Note that this is the @emph{plural} form;
3582 the @emph{singular} form is a very different command.
3583 @end deffn
3585 @deffn Command {flash probe} num
3586 Identify the flash, or validate the parameters of the configured flash. Operation
3587 depends on the flash type.
3588 The @var{num} parameter is a value shown by @command{flash banks}.
3589 Most flash commands will implicitly @emph{autoprobe} the bank;
3590 flash drivers can distinguish between probing and autoprobing,
3591 but most don't bother.
3592 @end deffn
3594 @section Erasing, Reading, Writing to Flash
3595 @cindex flash erasing
3596 @cindex flash reading
3597 @cindex flash writing
3598 @cindex flash programming
3600 One feature distinguishing NOR flash from NAND or serial flash technologies
3601 is that for read access, it acts exactly like any other addressible memory.
3602 This means you can use normal memory read commands like @command{mdw} or
3603 @command{dump_image} with it, with no special @command{flash} subcommands.
3604 @xref{Memory access}, and @ref{Image access}.
3606 Write access works differently. Flash memory normally needs to be erased
3607 before it's written. Erasing a sector turns all of its bits to ones, and
3608 writing can turn ones into zeroes. This is why there are special commands
3609 for interactive erasing and writing, and why GDB needs to know which parts
3610 of the address space hold NOR flash memory.
3612 @quotation Note
3613 Most of these erase and write commands leverage the fact that NOR flash
3614 chips consume target address space. They implicitly refer to the current
3615 JTAG target, and map from an address in that target's address space
3616 back to a flash bank.
3617 @comment In May 2009, those mappings may fail if any bank associated
3618 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
3619 A few commands use abstract addressing based on bank and sector numbers,
3620 and don't depend on searching the current target and its address space.
3621 Avoid confusing the two command models.
3622 @end quotation
3624 Some flash chips implement software protection against accidental writes,
3625 since such buggy writes could in some cases ``brick'' a system.
3626 For such systems, erasing and writing may require sector protection to be
3627 disabled first.
3628 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
3629 and AT91SAM7 on-chip flash.
3630 @xref{flash protect}.
3632 @anchor{flash erase_sector}
3633 @deffn Command {flash erase_sector} num first last
3634 Erase sectors in bank @var{num}, starting at sector @var{first}
3635 up to and including @var{last}.
3636 Sector numbering starts at 0.
3637 Providing a @var{last} sector of @option{last}
3638 specifies "to the end of the flash bank".
3639 The @var{num} parameter is a value shown by @command{flash banks}.
3640 @end deffn
3642 @deffn Command {flash erase_address} address length
3643 Erase sectors starting at @var{address} for @var{length} bytes.
3644 The flash bank to use is inferred from the @var{address}, and
3645 the specified length must stay within that bank.
3646 As a special case, when @var{length} is zero and @var{address} is
3647 the start of the bank, the whole flash is erased.
3648 @end deffn
3650 @deffn Command {flash fillw} address word length
3651 @deffnx Command {flash fillh} address halfword length
3652 @deffnx Command {flash fillb} address byte length
3653 Fills flash memory with the specified @var{word} (32 bits),
3654 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3655 starting at @var{address} and continuing
3656 for @var{length} units (word/halfword/byte).
3657 No erasure is done before writing; when needed, that must be done
3658 before issuing this command.
3659 Writes are done in blocks of up to 1024 bytes, and each write is
3660 verified by reading back the data and comparing it to what was written.
3661 The flash bank to use is inferred from the @var{address} of
3662 each block, and the specified length must stay within that bank.
3663 @end deffn
3664 @comment no current checks for errors if fill blocks touch multiple banks!
3666 @anchor{flash write_bank}
3667 @deffn Command {flash write_bank} num filename offset
3668 Write the binary @file{filename} to flash bank @var{num},
3669 starting at @var{offset} bytes from the beginning of the bank.
3670 The @var{num} parameter is a value shown by @command{flash banks}.
3671 @end deffn
3673 @anchor{flash write_image}
3674 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
3675 Write the image @file{filename} to the current target's flash bank(s).
3676 A relocation @var{offset} may be specified, in which case it is added
3677 to the base address for each section in the image.
3678 The file [@var{type}] can be specified
3679 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
3680 @option{elf} (ELF file), @option{s19} (Motorola s19).
3681 @option{mem}, or @option{builder}.
3682 The relevant flash sectors will be erased prior to programming
3683 if the @option{erase} parameter is given. If @option{unlock} is
3684 provided, then the flash banks are unlocked before erase and
3685 program. The flash bank to use is inferred from the @var{address} of
3686 each image segment.
3687 @end deffn
3689 @section Other Flash commands
3690 @cindex flash protection
3692 @deffn Command {flash erase_check} num
3693 Check erase state of sectors in flash bank @var{num},
3694 and display that status.
3695 The @var{num} parameter is a value shown by @command{flash banks}.
3696 This is the only operation that
3697 updates the erase state information displayed by @option{flash info}. That means you have
3698 to issue a @command{flash erase_check} command after erasing or programming the device
3699 to get updated information.
3700 (Code execution may have invalidated any state records kept by OpenOCD.)
3701 @end deffn
3703 @deffn Command {flash info} num
3704 Print info about flash bank @var{num}
3705 The @var{num} parameter is a value shown by @command{flash banks}.
3706 The information includes per-sector protect status.
3707 @end deffn
3709 @anchor{flash protect}
3710 @deffn Command {flash protect} num first last (@option{on}|@option{off})
3711 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
3712 in flash bank @var{num}, starting at sector @var{first}
3713 and continuing up to and including @var{last}.
3714 Providing a @var{last} sector of @option{last}
3715 specifies "to the end of the flash bank".
3716 The @var{num} parameter is a value shown by @command{flash banks}.
3717 @end deffn
3719 @deffn Command {flash protect_check} num
3720 Check protection state of sectors in flash bank @var{num}.
3721 The @var{num} parameter is a value shown by @command{flash banks}.
3722 @comment @option{flash erase_sector} using the same syntax.
3723 @end deffn
3725 @anchor{Flash Driver List}
3726 @section Flash Driver List
3727 As noted above, the @command{flash bank} command requires a driver name,
3728 and allows driver-specific options and behaviors.
3729 Some drivers also activate driver-specific commands.
3731 @subsection External Flash
3733 @deffn {Flash Driver} cfi
3734 @cindex Common Flash Interface
3735 @cindex CFI
3736 The ``Common Flash Interface'' (CFI) is the main standard for
3737 external NOR flash chips, each of which connects to a
3738 specific external chip select on the CPU.
3739 Frequently the first such chip is used to boot the system.
3740 Your board's @code{reset-init} handler might need to
3741 configure additional chip selects using other commands (like: @command{mww} to
3742 configure a bus and its timings), or
3743 perhaps configure a GPIO pin that controls the ``write protect'' pin
3744 on the flash chip.
3745 The CFI driver can use a target-specific working area to significantly
3746 speed up operation.
3748 The CFI driver can accept the following optional parameters, in any order:
3750 @itemize
3751 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
3752 like AM29LV010 and similar types.
3753 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
3754 @end itemize
3756 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
3757 wide on a sixteen bit bus:
3759 @example
3760 flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
3761 flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
3762 @end example
3764 To configure one bank of 32 MBytes
3765 built from two sixteen bit (two byte) wide parts wired in parallel
3766 to create a thirty-two bit (four byte) bus with doubled throughput:
3768 @example
3769 flash bank cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
3770 @end example
3772 @c "cfi part_id" disabled
3773 @end deffn
3775 @subsection Internal Flash (Microcontrollers)
3777 @deffn {Flash Driver} aduc702x
3778 The ADUC702x analog microcontrollers from Analog Devices
3779 include internal flash and use ARM7TDMI cores.
3780 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
3781 The setup command only requires the @var{target} argument
3782 since all devices in this family have the same memory layout.
3784 @example
3785 flash bank aduc702x 0 0 0 0 $_TARGETNAME
3786 @end example
3787 @end deffn
3789 @deffn {Flash Driver} at91sam3
3790 @cindex at91sam3
3791 All members of the AT91SAM3 microcontroller family from
3792 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
3793 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
3794 that the driver was orginaly developed and tested using the
3795 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
3796 the family was cribbed from the data sheet. @emph{Note to future
3797 readers/updaters: Please remove this worrysome comment after other
3798 chips are confirmed.}
3800 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
3801 have one flash bank. In all cases the flash banks are at
3802 the following fixed locations:
3804 @example
3805 # Flash bank 0 - all chips
3806 flash bank at91sam3 0x00080000 0 1 1 $_TARGETNAME
3807 # Flash bank 1 - only 256K chips
3808 flash bank at91sam3 0x00100000 0 1 1 $_TARGETNAME
3809 @end example
3811 Internally, the AT91SAM3 flash memory is organized as follows.
3812 Unlike the AT91SAM7 chips, these are not used as parameters
3813 to the @command{flash bank} command:
3815 @itemize
3816 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
3817 @item @emph{Bank Size:} 128K/64K Per flash bank
3818 @item @emph{Sectors:} 16 or 8 per bank
3819 @item @emph{SectorSize:} 8K Per Sector
3820 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
3821 @end itemize
3823 The AT91SAM3 driver adds some additional commands:
3825 @deffn Command {at91sam3 gpnvm}
3826 @deffnx Command {at91sam3 gpnvm clear} number
3827 @deffnx Command {at91sam3 gpnvm set} number
3828 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
3829 With no parameters, @command{show} or @command{show all},
3830 shows the status of all GPNVM bits.
3831 With @command{show} @var{number}, displays that bit.
3833 With @command{set} @var{number} or @command{clear} @var{number},
3834 modifies that GPNVM bit.
3835 @end deffn
3837 @deffn Command {at91sam3 info}
3838 This command attempts to display information about the AT91SAM3
3839 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
3840 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
3841 document id: doc6430A] and decodes the values. @emph{Second} it reads the
3842 various clock configuration registers and attempts to display how it
3843 believes the chip is configured. By default, the SLOWCLK is assumed to
3844 be 32768 Hz, see the command @command{at91sam3 slowclk}.
3845 @end deffn
3847 @deffn Command {at91sam3 slowclk} [value]
3848 This command shows/sets the slow clock frequency used in the
3849 @command{at91sam3 info} command calculations above.
3850 @end deffn
3851 @end deffn
3853 @deffn {Flash Driver} at91sam7
3854 All members of the AT91SAM7 microcontroller family from Atmel include
3855 internal flash and use ARM7TDMI cores. The driver automatically
3856 recognizes a number of these chips using the chip identification
3857 register, and autoconfigures itself.
3859 @example
3860 flash bank at91sam7 0 0 0 0 $_TARGETNAME
3861 @end example
3863 For chips which are not recognized by the controller driver, you must
3864 provide additional parameters in the following order:
3866 @itemize
3867 @item @var{chip_model} ... label used with @command{flash info}
3868 @item @var{banks}
3869 @item @var{sectors_per_bank}
3870 @item @var{pages_per_sector}
3871 @item @var{pages_size}
3872 @item @var{num_nvm_bits}
3873 @item @var{freq_khz} ... required if an external clock is provided,
3874 optional (but recommended) when the oscillator frequency is known
3875 @end itemize
3877 It is recommended that you provide zeroes for all of those values
3878 except the clock frequency, so that everything except that frequency
3879 will be autoconfigured.
3880 Knowing the frequency helps ensure correct timings for flash access.
3882 The flash controller handles erases automatically on a page (128/256 byte)
3883 basis, so explicit erase commands are not necessary for flash programming.
3884 However, there is an ``EraseAll`` command that can erase an entire flash
3885 plane (of up to 256KB), and it will be used automatically when you issue
3886 @command{flash erase_sector} or @command{flash erase_address} commands.
3888 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
3889 Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
3890 bit for the processor. Each processor has a number of such bits,
3891 used for controlling features such as brownout detection (so they
3892 are not truly general purpose).
3893 @quotation Note
3894 This assumes that the first flash bank (number 0) is associated with
3895 the appropriate at91sam7 target.
3896 @end quotation
3897 @end deffn
3898 @end deffn
3900 @deffn {Flash Driver} avr
3901 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
3902 @emph{The current implementation is incomplete.}
3903 @comment - defines mass_erase ... pointless given flash_erase_address
3904 @end deffn
3906 @deffn {Flash Driver} ecosflash
3907 @emph{No idea what this is...}
3908 The @var{ecosflash} driver defines one mandatory parameter,
3909 the name of a modules of target code which is downloaded
3910 and executed.
3911 @end deffn
3913 @deffn {Flash Driver} lpc2000
3914 Most members of the LPC1700 and LPC2000 microcontroller families from NXP
3915 include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
3917 @quotation Note
3918 There are LPC2000 devices which are not supported by the @var{lpc2000}
3919 driver:
3920 The LPC2888 is supported by the @var{lpc288x} driver.
3921 The LPC29xx family is supported by the @var{lpc2900} driver.
3922 @end quotation
3924 The @var{lpc2000} driver defines two mandatory and one optional parameters,
3925 which must appear in the following order:
3927 @itemize
3928 @item @var{variant} ... required, may be
3929 @var{lpc2000_v1} (older LPC21xx and LPC22xx)
3930 @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
3931 or @var{lpc1700} (LPC175x and LPC176x)
3932 @item @var{clock_kHz} ... the frequency, in kiloHertz,
3933 at which the core is running
3934 @item @var{calc_checksum} ... optional (but you probably want to provide this!),
3935 telling the driver to calculate a valid checksum for the exception vector table.
3936 @end itemize
3938 LPC flashes don't require the chip and bus width to be specified.
3940 @example
3941 flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
3942 lpc2000_v2 14765 calc_checksum
3943 @end example
3945 @deffn {Command} {lpc2000 part_id} bank
3946 Displays the four byte part identifier associated with
3947 the specified flash @var{bank}.
3948 @end deffn
3949 @end deffn
3951 @deffn {Flash Driver} lpc288x
3952 The LPC2888 microcontroller from NXP needs slightly different flash
3953 support from its lpc2000 siblings.
3954 The @var{lpc288x} driver defines one mandatory parameter,
3955 the programming clock rate in Hz.
3956 LPC flashes don't require the chip and bus width to be specified.
3958 @example
3959 flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
3960 @end example
3961 @end deffn
3963 @deffn {Flash Driver} lpc2900
3964 This driver supports the LPC29xx ARM968E based microcontroller family
3965 from NXP.
3967 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
3968 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
3969 sector layout are auto-configured by the driver.
3970 The driver has one additional mandatory parameter: The CPU clock rate
3971 (in kHz) at the time the flash operations will take place. Most of the time this
3972 will not be the crystal frequency, but a higher PLL frequency. The
3973 @code{reset-init} event handler in the board script is usually the place where
3974 you start the PLL.
3976 The driver rejects flashless devices (currently the LPC2930).
3978 The EEPROM in LPC2900 devices is not mapped directly into the address space.
3979 It must be handled much more like NAND flash memory, and will therefore be
3980 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
3982 Sector protection in terms of the LPC2900 is handled transparently. Every time a
3983 sector needs to be erased or programmed, it is automatically unprotected.
3984 What is shown as protection status in the @code{flash info} command, is
3985 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
3986 sector from ever being erased or programmed again. As this is an irreversible
3987 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
3988 and not by the standard @code{flash protect} command.
3990 Example for a 125 MHz clock frequency:
3991 @example
3992 flash bank lpc2900 0 0 0 0 $_TARGETNAME 125000
3993 @end example
3995 Some @code{lpc2900}-specific commands are defined. In the following command list,
3996 the @var{bank} parameter is the bank number as obtained by the
3997 @code{flash banks} command.
3999 @deffn Command {lpc2900 signature} bank
4000 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
4001 content. This is a hardware feature of the flash block, hence the calculation is
4002 very fast. You may use this to verify the content of a programmed device against
4003 a known signature.
4004 Example:
4005 @example
4006 lpc2900 signature 0
4007 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
4008 @end example
4009 @end deffn
4011 @deffn Command {lpc2900 read_custom} bank filename
4012 Reads the 912 bytes of customer information from the flash index sector, and
4013 saves it to a file in binary format.
4014 Example:
4015 @example
4016 lpc2900 read_custom 0 /path_to/customer_info.bin
4017 @end example
4018 @end deffn
4020 The index sector of the flash is a @emph{write-only} sector. It cannot be
4021 erased! In order to guard against unintentional write access, all following
4022 commands need to be preceeded by a successful call to the @code{password}
4023 command:
4025 @deffn Command {lpc2900 password} bank password
4026 You need to use this command right before each of the following commands:
4027 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
4028 @code{lpc2900 secure_jtag}.
4030 The password string is fixed to "I_know_what_I_am_doing".
4031 Example:
4032 @example
4033 lpc2900 password 0 I_know_what_I_am_doing
4034 Potentially dangerous operation allowed in next command!
4035 @end example
4036 @end deffn
4038 @deffn Command {lpc2900 write_custom} bank filename type
4039 Writes the content of the file into the customer info space of the flash index
4040 sector. The filetype can be specified with the @var{type} field. Possible values
4041 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
4042 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
4043 contain a single section, and the contained data length must be exactly
4044 912 bytes.
4045 @quotation Attention
4046 This cannot be reverted! Be careful!
4047 @end quotation
4048 Example:
4049 @example
4050 lpc2900 write_custom 0 /path_to/customer_info.bin bin
4051 @end example
4052 @end deffn
4054 @deffn Command {lpc2900 secure_sector} bank first last
4055 Secures the sector range from @var{first} to @var{last} (including) against
4056 further program and erase operations. The sector security will be effective
4057 after the next power cycle.
4058 @quotation Attention
4059 This cannot be reverted! Be careful!
4060 @end quotation
4061 Secured sectors appear as @emph{protected} in the @code{flash info} command.
4062 Example:
4063 @example
4064 lpc2900 secure_sector 0 1 1
4065 flash info 0
4066 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
4067 # 0: 0x00000000 (0x2000 8kB) not protected
4068 # 1: 0x00002000 (0x2000 8kB) protected
4069 # 2: 0x00004000 (0x2000 8kB) not protected
4070 @end example
4071 @end deffn
4073 @deffn Command {lpc2900 secure_jtag} bank
4074 Irreversibly disable the JTAG port. The new JTAG security setting will be
4075 effective after the next power cycle.
4076 @quotation Attention
4077 This cannot be reverted! Be careful!
4078 @end quotation
4079 Examples:
4080 @example
4081 lpc2900 secure_jtag 0
4082 @end example
4083 @end deffn
4084 @end deffn
4086 @deffn {Flash Driver} ocl
4087 @emph{No idea what this is, other than using some arm7/arm9 core.}
4089 @example
4090 flash bank ocl 0 0 0 0 $_TARGETNAME
4091 @end example
4092 @end deffn
4094 @deffn {Flash Driver} pic32mx
4095 The PIC32MX microcontrollers are based on the MIPS 4K cores,
4096 and integrate flash memory.
4097 @emph{The current implementation is incomplete.}
4099 @example
4100 flash bank pix32mx 0 0 0 0 $_TARGETNAME
4101 @end example
4103 @comment numerous *disabled* commands are defined:
4104 @comment - chip_erase ... pointless given flash_erase_address
4105 @comment - lock, unlock ... pointless given protect on/off (yes?)
4106 @comment - pgm_word ... shouldn't bank be deduced from address??
4107 Some pic32mx-specific commands are defined:
4108 @deffn Command {pic32mx pgm_word} address value bank
4109 Programs the specified 32-bit @var{value} at the given @var{address}
4110 in the specified chip @var{bank}.
4111 @end deffn
4112 @end deffn
4114 @deffn {Flash Driver} stellaris
4115 All members of the Stellaris LM3Sxxx microcontroller family from
4116 Texas Instruments
4117 include internal flash and use ARM Cortex M3 cores.
4118 The driver automatically recognizes a number of these chips using
4119 the chip identification register, and autoconfigures itself.
4120 @footnote{Currently there is a @command{stellaris mass_erase} command.
4121 That seems pointless since the same effect can be had using the
4122 standard @command{flash erase_address} command.}
4124 @example
4125 flash bank stellaris 0 0 0 0 $_TARGETNAME
4126 @end example
4127 @end deffn
4129 @deffn {Flash Driver} stm32x
4130 All members of the STM32 microcontroller family from ST Microelectronics
4131 include internal flash and use ARM Cortex M3 cores.
4132 The driver automatically recognizes a number of these chips using
4133 the chip identification register, and autoconfigures itself.
4135 @example
4136 flash bank stm32x 0 0 0 0 $_TARGETNAME
4137 @end example
4139 Some stm32x-specific commands
4140 @footnote{Currently there is a @command{stm32x mass_erase} command.
4141 That seems pointless since the same effect can be had using the
4142 standard @command{flash erase_address} command.}
4143 are defined:
4145 @deffn Command {stm32x lock} num
4146 Locks the entire stm32 device.
4147 The @var{num} parameter is a value shown by @command{flash banks}.
4148 @end deffn
4150 @deffn Command {stm32x unlock} num
4151 Unlocks the entire stm32 device.
4152 The @var{num} parameter is a value shown by @command{flash banks}.
4153 @end deffn
4155 @deffn Command {stm32x options_read} num
4156 Read and display the stm32 option bytes written by
4157 the @command{stm32x options_write} command.
4158 The @var{num} parameter is a value shown by @command{flash banks}.
4159 @end deffn
4161 @deffn Command {stm32x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
4162 Writes the stm32 option byte with the specified values.
4163 The @var{num} parameter is a value shown by @command{flash banks}.
4164 @end deffn
4165 @end deffn
4167 @deffn {Flash Driver} str7x
4168 All members of the STR7 microcontroller family from ST Microelectronics
4169 include internal flash and use ARM7TDMI cores.
4170 The @var{str7x} driver defines one mandatory parameter, @var{variant},
4171 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
4173 @example
4174 flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
4175 @end example
4177 @deffn Command {str7x disable_jtag} bank
4178 Activate the Debug/Readout protection mechanism
4179 for the specified flash bank.
4180 @end deffn
4181 @end deffn
4183 @deffn {Flash Driver} str9x
4184 Most members of the STR9 microcontroller family from ST Microelectronics
4185 include internal flash and use ARM966E cores.
4186 The str9 needs the flash controller to be configured using
4187 the @command{str9x flash_config} command prior to Flash programming.
4189 @example
4190 flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
4191 str9x flash_config 0 4 2 0 0x80000
4192 @end example
4194 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
4195 Configures the str9 flash controller.
4196 The @var{num} parameter is a value shown by @command{flash banks}.
4198 @itemize @bullet
4199 @item @var{bbsr} - Boot Bank Size register
4200 @item @var{nbbsr} - Non Boot Bank Size register
4201 @item @var{bbadr} - Boot Bank Start Address register