1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (OpenOCD)
5 @dircategory Development
7 * OpenOCD: (openocd). Open On-Chip Debugger.
14 Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}
16 Permission is granted to copy, distribute and/or modify this document
17 under the terms of the GNU Free Documentation License, Version 1.2 or
18 any later version published by the Free Software Foundation; with no
19 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
20 Texts. A copy of the license is included in the section entitled ``GNU
21 Free Documentation License''.
26 @title Open On-Chip Debugger (OpenOCD)
27 @subtitle Edition @value{EDITION} for OpenOCD version @value{VERSION}
28 @subtitle @value{UPDATED}
30 @vskip 0pt plus 1filll
36 @node Top, About, , (dir)
39 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
40 (OpenOCD) version @value{VERSION}, @value{UPDATED}.
45 * About:: About OpenOCD.
46 * Developers:: OpenOCD developers
47 * Building:: Building OpenOCD
48 * Running:: Running OpenOCD
49 * Configuration:: OpenOCD Configuration.
50 * Target library:: Target library
51 * Commands:: OpenOCD Commands
52 * Sample Scripts:: Sample Target Scripts
53 * GDB and OpenOCD:: Using GDB and OpenOCD
54 * TCL and OpenOCD:: Using TCL and OpenOCD
55 * Upgrading:: Deprecated/Removed Commands
56 * FAQ:: Frequently Asked Questions
57 * License:: GNU Free Documentation License
65 The Open On-Chip Debugger (OpenOCD) aims to provide debugging, in-system programming
66 and boundary-scan testing for embedded target devices. The targets are interfaced
67 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
68 connection types in the future.
70 OpenOCD currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
71 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
72 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
73 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
75 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
76 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
77 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
83 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
84 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
85 Others interested in improving the state of free and open debug and testing technology
86 are welcome to participate.
88 Other developers have contributed support for additional targets and flashes as well
89 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
91 The main OpenOCD web site is available at @uref{http://openocd.berlios.de/web/}
95 @cindex building OpenOCD
97 You can download the current SVN version with SVN client of your choice from the
98 following repositories:
100 (@uref{svn://svn.berlios.de/openocd/trunk})
104 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
106 Using the SVN command line client, you can use the following command to fetch the
107 latest version (make sure there is no (non-svn) directory called "openocd" in the
111 svn checkout svn://svn.berlios.de/openocd/trunk openocd
114 Building OpenOCD requires a recent version of the GNU autotools.
115 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
116 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
117 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
118 paths, resulting in obscure dependency errors (This is an observation I've gathered
119 from the logs of one user - correct me if I'm wrong).
121 You further need the appropriate driver files, if you want to build support for
122 a FTDI FT2232 based interface:
124 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
125 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
126 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
127 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
130 libftdi is supported under windows. Versions earlier than 0.13 will require patching.
131 see contrib/libftdi for more details.
133 In general, the D2XX driver provides superior performance (several times as fast),
134 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
135 a kernel module, only a user space library.
137 To build OpenOCD (on both Linux and Cygwin), use the following commands:
141 Bootstrap generates the configure script, and prepares building on your system.
145 Configure generates the Makefiles used to build OpenOCD.
149 Make builds OpenOCD, and places the final executable in ./src/.
151 The configure script takes several options, specifying which JTAG interfaces
156 @option{--enable-parport}
158 @option{--enable-parport_ppdev}
160 @option{--enable-parport_giveio}
162 @option{--enable-amtjtagaccel}
164 @option{--enable-ft2232_ftd2xx}
165 @footnote{Using the latest D2XX drivers from FTDI and following their installation
166 instructions, I had to use @option{--enable-ft2232_libftd2xx} for OpenOCD to
169 @option{--enable-ft2232_libftdi}
171 @option{--with-ftd2xx=/path/to/d2xx/}
173 @option{--enable-gw16012}
175 @option{--enable-usbprog}
177 @option{--enable-presto_libftdi}
179 @option{--enable-presto_ftd2xx}
181 @option{--enable-jlink}
184 If you want to access the parallel port using the PPDEV interface you have to specify
185 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
186 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
187 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
189 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
190 absolute path containing no spaces.
192 Linux users should copy the various parts of the D2XX package to the appropriate
193 locations, i.e. /usr/include, /usr/lib.
197 @cindex running OpenOCD
199 @cindex --debug_level
202 OpenOCD runs as a daemon, waiting for connections from clients (Telnet, GDB, Other).
203 Run with @option{--help} or @option{-h} to view the available command line switches.
205 It reads its configuration by default from the file openocd.cfg located in the current
206 working directory. This may be overwritten with the @option{-f <configfile>} command line
207 switch. The @option{-f} command line switch can be specified multiple times, in which case the config files
208 are executed in order.
210 Also it is possible to interleave commands w/config scripts using the @option{-c} command line switch.
212 To enable debug output (when reporting problems or working on OpenOCD itself), use
213 the @option{-d} command line switch. This sets the debug_level to "3", outputting
214 the most information, including debug messages. The default setting is "2", outputting
215 only informational messages, warnings and errors. You can also change this setting
216 from within a telnet or gdb session (@option{debug_level <n>}).
218 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
220 Search paths for config/script files can be added to OpenOCD by using
221 the @option{-s <search>} switch. The current directory and the OpenOCD target library
222 is in the search path by default.
224 Note! OpenOCD will launch the GDB & telnet server even if it can not establish a connection
225 with the target. In general, it is possible for the JTAG controller to be unresponsive until
226 the target is set up correctly via e.g. GDB monitor commands in a GDB init script.
229 @chapter Configuration
230 @cindex configuration
231 OpenOCD runs as a daemon, and reads it current configuration
232 by default from the file openocd.cfg in the current directory. A different configuration
233 file can be specified with the @option{-f <conf.file>} command line switch specified when starting OpenOCD.
235 The configuration file is used to specify on which ports the daemon listens for new
236 connections, the JTAG interface used to connect to the target, the layout of the JTAG
237 chain, the targets that should be debugged, and connected flashes.
239 @section Daemon configuration
242 @item @b{init} This command terminates the configuration stage and enters the normal
243 command mode. This can be useful to add commands to the startup scripts and commands
244 such as resetting the target, programming flash, etc. To reset the CPU upon startup,
245 add "init" and "reset" at the end of the config script or at the end of the
246 OpenOCD command line using the @option{-c} command line switch.
248 @item @b{telnet_port} <@var{number}>
250 Port on which to listen for incoming telnet connections
251 @item @b{gdb_port} <@var{number}>
253 First port on which to listen for incoming GDB connections. The GDB port for the
254 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
255 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
257 Configures what OpenOCD will do when gdb detaches from the daeman.
258 Default behaviour is <@var{resume}>
259 @item @b{gdb_memory_map} <@var{enable|disable}>
260 @cindex gdb_memory_map
261 Set to <@var{enable}> to cause OpenOCD to send the memory configuration to gdb when
262 requested. gdb will then know when to set hardware breakpoints, and program flash
263 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
264 for flash programming to work.
265 Default behaviour is <@var{enable}>
266 @item @b{gdb_flash_program} <@var{enable|disable}>
267 @cindex gdb_flash_program
268 Set to <@var{enable}> to cause OpenOCD to program the flash memory when a
269 vFlash packet is received.
270 Default behaviour is <@var{enable}>
271 at item @b{tcl_port} <@var{number}>
273 Port on which to listen for incoming TCL syntax. This port is intended as
274 a simplified RPC connection that can be used by clients to issue commands
275 and get the output from the TCL engine.
276 @item @b{daemon_startup} <@var{mode}>
277 @cindex daemon_startup
278 @option{mode} can either @option{attach} or @option{reset}
279 This is equivalent to adding "init" and "reset" to the end of the config script.
281 It is available as a command mainly for backwards compatibility.
284 @section JTAG interface configuration
287 @item @b{interface} <@var{name}>
289 Use the interface driver <@var{name}> to connect to the target. Currently supported
293 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
296 @item @b{amt_jtagaccel}
297 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
302 FTDI FT2232 based devices using either the open-source libftdi or the binary only
303 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
304 platform. The libftdi uses libusb, and should be portable to all systems that provide
309 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
313 ASIX PRESTO USB JTAG programmer.
317 usbprog is a freely programmable USB adapter.
321 Gateworks GW16012 JTAG programmer.
325 Segger jlink usb adapter
330 @item @b{jtag_speed} <@var{reset speed}> <@var{post reset speed}>
332 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
333 speed. The actual effect of this option depends on the JTAG interface used. Reset
334 speed is used during reset and post reset speed after reset. post reset speed
335 is optional, in which case the reset speed is used.
338 @item wiggler: maximum speed / @var{number}
339 @item ft2232: 6MHz / (@var{number}+1)
340 @item amt jtagaccel: 8 / 2**@var{number}
341 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
344 Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
345 especially true for synthesized cores (-S).
347 @item @b{jtag_khz} <@var{reset speed kHz}> <@var{post reset speed kHz}>
349 Same as jtag_speed, except that the speed is specified in maximum kHz. If
350 the device can not support the rate asked for, or can not translate from
351 kHz to jtag_speed, then an error is returned. 0 means RTCK. If RTCK
352 is not supported, then an error is reported.
354 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
356 The configuration of the reset signals available on the JTAG interface AND the target.
357 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
358 then OpenOCD can't use it. <@var{signals}> can be @option{none}, @option{trst_only},
359 @option{srst_only} or @option{trst_and_srst}.
361 [@var{combination}] is an optional value specifying broken reset signal implementations.
362 @option{srst_pulls_trst} states that the testlogic is reset together with the reset of
363 the system (e.g. Philips LPC2000, "broken" board layout), @option{trst_pulls_srst} says
364 that the system is reset together with the test logic (only hypothetical, I haven't
365 seen hardware with such a bug, and can be worked around).
366 @option{combined} imples both @option{srst_pulls_trst} and @option{trst_pulls_srst}.
367 The default behaviour if no option given is @option{separate}.
369 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
370 reset lines to be specified. Possible values are @option{trst_push_pull} (default)
371 and @option{trst_open_drain} for the test reset signal, and @option{srst_open_drain}
372 (default) and @option{srst_push_pull} for the system reset. These values only affect
373 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
375 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
377 Describes the devices that form the JTAG daisy chain, with the first device being
378 the one closest to TDO. The parameters are the length of the instruction register
379 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
380 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
381 The IDCODE instruction will in future be used to query devices for their JTAG
382 identification code. This line is the same for all ARM7 and ARM9 devices.
383 Other devices, like CPLDs, require different parameters. An example configuration
384 line for a Xilinx XC9500 CPLD would look like this:
386 jtag_device 8 0x01 0x0e3 0xfe
388 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
389 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
390 The IDCODE instruction is 0xfe.
392 @item @b{jtag_nsrst_delay} <@var{ms}>
393 @cindex jtag_nsrst_delay
394 How long (in milliseconds) OpenOCD should wait after deasserting nSRST before
395 starting new JTAG operations.
396 @item @b{jtag_ntrst_delay} <@var{ms}>
397 @cindex jtag_ntrst_delay
398 How long (in milliseconds) OpenOCD should wait after deasserting nTRST before
399 starting new JTAG operations.
401 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
402 or on-chip features) keep a reset line asserted for some time after the external reset
406 @section parport options
409 @item @b{parport_port} <@var{number}>
411 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
412 the @file{/dev/parport} device
414 When using PPDEV to access the parallel port, use the number of the parallel port:
415 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
416 you may encounter a problem.
417 @item @b{parport_cable} <@var{name}>
418 @cindex parport_cable
419 The layout of the parallel port cable used to connect to the target.
420 Currently supported cables are
424 The original Wiggler layout, also supported by several clones, such
425 as the Olimex ARM-JTAG
426 @item @b{old_amt_wiggler}
427 @cindex old_amt_wiggler
428 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
429 version available from the website uses the original Wiggler layout ('@var{wiggler}')
432 The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to program the Chameleon itself, not a connected target.
435 The Xilinx Parallel cable III.
438 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
439 This is also the layout used by the HollyGates design
440 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
443 The ST Parallel cable.
445 @item @b{parport_write_on_exit} <@var{on|off}>
446 @cindex parport_write_on_exit
447 This will configure the parallel driver to write a known value to the parallel
448 interface on exiting OpenOCD
451 @section amt_jtagaccel options
453 @item @b{parport_port} <@var{number}>
455 Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
456 @file{/dev/parport} device
458 @section ft2232 options
461 @item @b{ft2232_device_desc} <@var{description}>
462 @cindex ft2232_device_desc
463 The USB device description of the FTDI FT2232 device. If not specified, the FTDI
464 default value is used. This setting is only valid if compiled with FTD2XX support.
465 @item @b{ft2232_layout} <@var{name}>
466 @cindex ft2232_layout
467 The layout of the FT2232 GPIO signals used to control output-enables and reset
468 signals. Valid layouts are
471 "USBJTAG-1" layout described in the original OpenOCD diploma thesis
473 Amontec JTAGkey and JTAGkey-tiny
476 @item @b{olimex-jtag}
479 American Microsystems M5960
480 @item @b{evb_lm3s811}
481 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
482 SRST signals on external connector
486 Hitex STM32 Performance Stick
488 Tin Can Tools Flyswatter
489 @item @b{turtelizer2}
490 egnite Software turtelizer2
495 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
496 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
497 default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, eg.
499 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
501 @item @b{ft2232_latency} <@var{ms}>
502 On some systems using ft2232 based JTAG interfaces the FT_Read function call in
503 ft2232_read() fails to return the expected number of bytes. This can be caused by
504 USB communication delays and has proved hard to reproduce and debug. Setting the
505 FT2232 latency timer to a larger value increases delays for short USB packages but it
506 also reduces the risk of timeouts before receiving the expected number of bytes.
507 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
510 @section ep93xx options
511 @cindex ep93xx options
512 Currently, there are no options available for the ep93xx interface.
515 @section Target configuration
518 @item @b{target} <@var{type}> <@var{endianess}> <@var{reset_mode}> <@var{JTAG pos}>
521 Defines a target that should be debugged. Currently supported types are:
535 If you want to use a target board that is not on this list, see Adding a new
538 Endianess may be @option{little} or @option{big}.
540 The reset_mode specifies what should happen to the target when a reset occurs:
544 Immediately request a target halt after reset. This allows targets to be debugged
545 from the very first instruction. This is only possible with targets and JTAG
546 interfaces that correctly implement the reset signals.
549 Similar to @option{reset_halt}, but executes the script file defined to handle the
550 'reset' event for the target. Like @option{reset_halt} this only works with
551 correct reset implementations.
554 Simply let the target run after a reset.
555 @item @b{run_and_halt}
557 Let the target run for some time (default: 1s), and then request halt.
558 @item @b{run_and_init}
560 A combination of @option{reset_init} and @option{run_and_halt}. The target is allowed
561 to run for some time, then halted, and the @option{reset} event script is executed.
564 On JTAG interfaces / targets where system reset and test-logic reset can't be driven
565 completely independent (like the LPC2000 series), or where the JTAG interface is
566 unavailable for some time during startup (like the STR7 series), you can't use
567 @option{reset_halt} or @option{reset_init}.
569 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
570 @cindex target_script
571 Event is one of the following:
572 @option{pre_reset}, @option{reset}, @option{post_reset}, @option{post_halt},
573 @option{pre_resume} or @option{gdb_program_config}.
574 @option{post_reset} and @option{reset} will produce the same results.
576 @item @b{run_and_halt_time} <@var{target#}> <@var{time_in_ms}>
577 @cindex run_and_halt_time
578 The amount of time the debugger should wait after releasing reset before it asserts
579 a debug request. This is used by the @option{run_and_halt} and @option{run_and_init}
581 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
582 <@var{backup}|@var{nobackup}>
584 Specifies a working area for the debugger to use. This may be used to speed-up
585 downloads to target memory and flash operations, or to perform otherwise unavailable
586 operations (some coprocessor operations on ARM7/9 systems, for example). The last
587 parameter decides whether the memory should be preserved (<@var{backup}>) or can simply be overwritten (<@var{nobackup}>). If possible, use
588 a working_area that doesn't need to be backed up, as performing a backup slows down operation.
591 @subsection arm7tdmi options
592 @cindex arm7tdmi options
593 target arm7tdmi <@var{endianess}> <@var{reset_mode}> <@var{jtag#}>
594 The arm7tdmi target definition requires at least one additional argument, specifying
595 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
596 The optional [@var{variant}] parameter has been removed in recent versions.
597 The correct feature set is determined at runtime.
599 @subsection arm720t options
600 @cindex arm720t options
601 ARM720t options are similar to ARM7TDMI options.
603 @subsection arm9tdmi options
604 @cindex arm9tdmi options
605 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
606 @option{arm920t}, @option{arm922t} and @option{arm940t}.
607 This enables the hardware single-stepping support found on these cores.
609 @subsection arm920t options
610 @cindex arm920t options
611 ARM920t options are similar to ARM9TDMI options.
613 @subsection arm966e options
614 @cindex arm966e options
615 ARM966e options are similar to ARM9TDMI options.
617 @subsection cortex_m3 options
618 @cindex cortex_m3 options
619 use variant <@var{variant}> @option{lm3s} when debugging luminary lm3s targets. This will cause
620 openocd to use a software reset rather than asserting SRST to avoid a issue with clearing
621 the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
622 be detected and the normal reset behaviour used.
624 @subsection xscale options
625 @cindex xscale options
626 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
627 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
629 @section Flash configuration
630 @cindex Flash configuration
633 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
634 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
636 Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
637 and <@var{bus_width}> bytes using the selected flash <driver>.
640 @subsection lpc2000 options
641 @cindex lpc2000 options
643 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
644 <@var{clock}> [@var{calc_checksum}]
645 LPC flashes don't require the chip and bus width to be specified. Additional
646 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
647 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
648 of the target this flash belongs to (first is 0), the frequency at which the core
649 is currently running (in kHz - must be an integral number), and the optional keyword
650 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
653 @subsection cfi options
656 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
658 CFI flashes require the number of the target they're connected to as an additional
659 argument. The CFI driver makes use of a working area (specified for the target)
660 to significantly speed up operation.
662 @var{chip_width} and @var{bus_width} are specified in bytes.
664 @subsection at91sam7 options
665 @cindex at91sam7 options
667 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
668 AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
669 reading the chip-id and type.
671 @subsection str7 options
674 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
675 variant can be either STR71x, STR73x or STR75x.
677 @subsection str9 options
680 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
681 The str9 needs the flash controller to be configured prior to Flash programming, eg.
683 str9x flash_config 0 4 2 0 0x80000
685 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
687 @subsection str9 options (str9xpec driver)
689 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
690 Before using the flash commands the turbo mode will need enabling using str9xpec
691 @option{enable_turbo} <@var{num>.}
693 Only use this driver for locking/unlocking the device or configuring the option bytes.
694 Use the standard str9 driver for programming.
696 @subsection stellaris (LM3Sxxx) options
697 @cindex stellaris (LM3Sxxx) options
699 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
700 stellaris flash plugin only require the @var{target#}.
702 @subsection stm32x options
703 @cindex stm32x options
705 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
706 stm32x flash plugin only require the @var{target#}.
709 @chapter Target library
710 @cindex Target library
712 OpenOCD comes with a target configuration script library. These scripts can be
713 used as-is or serve as a starting point.
715 The target library is published together with the openocd executable and
716 the path to the target library is in the OpenOCD script search path.
717 Similarly there are example scripts for configuring the JTAG interface.
719 The command line below uses the example parport configuration scripts
720 that ship with OpenOCD, then configures the str710.cfg target and
721 finally issues the init and reset command. The communication speed
722 is set to 10kHz for reset and 8MHz for post reset.
726 openocd -f interface/parport.cfg -c "jtag_khz 10 8000" -f target/str710.cfg -c "init" -c "reset"
730 To list the target scripts available:
733 $ ls /usr/local/lib/openocd/target
735 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
736 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
737 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
738 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
746 OpenOCD allows user interaction through a GDB server (default: port 3333),
747 a telnet interface (default: port 4444), and a TCL interface (default: port 5555). The command line interpreter
748 is available from both the telnet interface and a GDB session. To issue commands to the
749 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
750 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
753 The TCL interface is used as a simplified RPC mechanism that feeds all the
754 input into the TCL interpreter and returns the output from the evaluation of
760 @item @b{sleep} <@var{msec}>
762 Wait for n milliseconds before resuming. Useful in connection with script files
763 (@var{script} command and @var{target_script} configuration).
767 Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet, Other).
769 @item @b{debug_level} [@var{n}]
771 Display or adjust debug level to n<0-3>
773 @item @b{fast} [@var{enable/disable}]
775 Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
776 downloads and fast memory access will work if the JTAG interface isn't too fast and
777 the core doesn't run at a too low frequency. Note that this option only changes the default
778 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
781 The target specific "dangerous" optimisation tweaking options may come and go
782 as more robust and user friendly ways are found to ensure maximum throughput
783 and robustness with a minimum of configuration.
785 Typically the "fast enable" is specified first on the command line:
788 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
791 @item @b{log_output} <@var{file}>
793 Redirect logging to <file> (default: stderr)
795 @item @b{script} <@var{file}>
797 Execute commands from <file>
801 @subsection Target state handling
803 @item @b{poll} [@option{on}|@option{off}]
805 Poll the target for its current state. If the target is in debug mode, architecture
806 specific information about the current state is printed. An optional parameter
807 allows continuous polling to be enabled and disabled.
809 @item @b{halt} [@option{ms}]
811 Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
812 Default [@option{ms}] is 5 seconds if no arg given.
813 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
814 will stop OpenOCD from waiting.
816 @item @b{wait_halt} [@option{ms}]
818 Wait for the target to enter debug mode. Optional [@option{ms}] is
819 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
822 @item @b{resume} [@var{address}]
824 Resume the target at its current code position, or at an optional address.
825 OpenOCD will wait 5 seconds for the target to resume.
827 @item @b{step} [@var{address}]
829 Single-step the target at its current code position, or at an optional address.
831 @item @b{reset} [@option{run}|@option{halt}|@option{init}|@option{run_and_halt}
832 |@option{run_and_init}]
834 Perform a hard-reset. The optional parameter specifies what should happen after the reset.
835 This optional parameter overrides the setting specified in the configuration file,
836 making the new behaviour the default for the @option{reset} command.
843 Immediately halt the target (works only with certain configurations).
846 Immediately halt the target, and execute the reset script (works only with certain
848 @item @b{run_and_halt}
849 @cindex reset run_and_halt
850 Let the target run for a certain amount of time, then request a halt.
851 @item @b{run_and_init}
852 @cindex reset run_and_init
853 Let the target run for a certain amount of time, then request a halt. Execute the
854 reset script once the target enters debug mode.
858 @subsection Memory access commands
859 These commands allow accesses of a specific size to the memory system:
861 @item @b{mdw} <@var{addr}> [@var{count}]
864 @item @b{mdh} <@var{addr}> [@var{count}]
866 display memory half-words
867 @item @b{mdb} <@var{addr}> [@var{count}]
870 @item @b{mww} <@var{addr}> <@var{value}>
873 @item @b{mwh} <@var{addr}> <@var{value}>
875 write memory half-word
876 @item @b{mwb} <@var{addr}> <@var{value}>
880 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
882 Load image <@var{file}> to target memory at <@var{address}>
883 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
885 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
886 (binary) <@var{file}>.
887 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
889 Verify <@var{file}> against target memory starting at <@var{address}>.
890 This will first attempt comparison using a crc checksum, if this fails it will try a binary compare.
893 @subsection Flash commands
894 @cindex Flash commands
896 @item @b{flash banks}
898 List configured flash banks
899 @item @b{flash info} <@var{num}>
901 Print info about flash bank <@option{num}>
902 @item @b{flash probe} <@var{num}>
904 Identify the flash, or validate the parameters of the configured flash. Operation
905 depends on the flash type.
906 @item @b{flash erase_check} <@var{num}>
907 @cindex flash erase_check
908 Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
909 updates the erase state information displayed by @option{flash info}. That means you have
910 to issue an @option{erase_check} command after erasing or programming the device to get
912 @item @b{flash protect_check} <@var{num}>
913 @cindex flash protect_check
914 Check protection state of sectors in flash bank <num>.
915 @option{flash erase_sector} using the same syntax.
916 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
917 @cindex flash erase_sector
918 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
919 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing may
920 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
922 @item @b{flash erase_address} <@var{address}> <@var{length}>
923 @cindex flash erase_address
924 Erase sectors starting at <@var{address}> for <@var{length}> bytes
925 @item @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
926 @cindex flash write_bank
927 Write the binary <@var{file}> to flash bank <@var{num}>, starting at
928 <@option{offset}> bytes from the beginning of the bank.
929 @item @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
930 @cindex flash write_image
931 Write the image <@var{file}> to the current target's flash bank(s). A relocation
932 [@var{offset}] can be specified and the file [@var{type}] can be specified
933 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
934 (ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
935 if the @option{erase} parameter is given.
936 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
937 @cindex flash protect
938 Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
939 <@var{last}> of @option{flash bank} <@var{num}>.
943 @section Target Specific Commands
944 @cindex Target Specific Commands
946 @subsection AT91SAM7 specific commands
947 @cindex AT91SAM7 specific commands
948 The flash configuration is deduced from the chip identification register. The flash
949 controller handles erases automatically on a page (128/265 byte) basis so erase is
950 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
951 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
952 that can be erased separatly. Only an EraseAll command is supported by the controller
953 for each flash plane and this is called with
955 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
956 bulk erase flash planes first_plane to last_plane.
957 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
958 @cindex at91sam7 gpnvm
959 set or clear a gpnvm bit for the processor
962 @subsection STR9 specific commands
963 @cindex STR9 specific commands
964 These are flash specific commands when using the str9xpec driver.
966 @item @b{str9xpec enable_turbo} <@var{num}>
967 @cindex str9xpec enable_turbo
968 enable turbo mode, simply this will remove the str9 from the chain and talk
969 directly to the embedded flash controller.
970 @item @b{str9xpec disable_turbo} <@var{num}>
971 @cindex str9xpec disable_turbo
972 restore the str9 into jtag chain.
973 @item @b{str9xpec lock} <@var{num}>
974 @cindex str9xpec lock
975 lock str9 device. The str9 will only respond to an unlock command that will
977 @item @b{str9xpec unlock} <@var{num}>
978 @cindex str9xpec unlock
980 @item @b{str9xpec options_read} <@var{num}>
981 @cindex str9xpec options_read
982 read str9 option bytes.
983 @item @b{str9xpec options_write} <@var{num}>
984 @cindex str9xpec options_write
985 write str9 option bytes.
988 @subsection STR9 configuration
989 @cindex STR9 configuration
991 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
992 <@var{BBADR}> <@var{NBBADR}>
993 @cindex str9x flash_config
994 Configure str9 flash controller.
996 eg. str9x flash_config 0 4 2 0 0x80000
998 BBSR - Boot Bank Size register
999 NBBSR - Non Boot Bank Size register
1000 BBADR - Boot Bank Start Address register
1001 NBBADR - Boot Bank Start Address register
1005 @subsection STR9 option byte configuration
1006 @cindex STR9 option byte configuration
1008 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
1009 @cindex str9xpec options_cmap
1010 configure str9 boot bank.
1011 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
1012 @cindex str9xpec options_lvdthd
1013 configure str9 lvd threshold.
1014 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
1015 @cindex str9xpec options_lvdsel
1016 configure str9 lvd source.
1017 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
1018 @cindex str9xpec options_lvdwarn
1019 configure str9 lvd reset warning source.
1022 @subsection STM32x specific commands
1023 @cindex STM32x specific commands
1025 These are flash specific commands when using the stm32x driver.
1027 @item @b{stm32x lock} <@var{num}>
1030 @item @b{stm32x unlock} <@var{num}>
1031 @cindex stm32x unlock
1032 unlock stm32 device.
1033 @item @b{stm32x options_read} <@var{num}>
1034 @cindex stm32x options_read
1035 read stm32 option bytes.
1036 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
1037 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
1038 @cindex stm32x options_write
1039 write stm32 option bytes.
1040 @item @b{stm32x mass_erase} <@var{num}>
1041 @cindex stm32x mass_erase
1042 mass erase flash memory.
1045 @subsection Stellaris specific commands
1046 @cindex Stellaris specific commands
1048 These are flash specific commands when using the Stellaris driver.
1050 @item @b{stellaris mass_erase} <@var{num}>
1051 @cindex stellaris mass_erase
1052 mass erase flash memory.
1056 @section Architecture Specific Commands
1057 @cindex Architecture Specific Commands
1059 @subsection ARMV4/5 specific commands
1060 @cindex ARMV4/5 specific commands
1062 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
1063 or Intel XScale (XScale isn't supported yet).
1065 @item @b{armv4_5 reg}
1067 Display a list of all banked core registers, fetching the current value from every
1068 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
1070 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
1071 @cindex armv4_5 core_mode
1072 Displays the core_mode, optionally changing it to either ARM or Thumb mode.
1073 The target is resumed in the currently set @option{core_mode}.
1076 @subsection ARM7/9 specific commands
1077 @cindex ARM7/9 specific commands
1079 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
1080 ARM920t or ARM926EJ-S.
1082 @item @b{arm7_9 sw_bkpts} <@var{enable}|@var{disable}>
1083 @cindex arm7_9 sw_bkpts
1084 Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
1085 one of the watchpoint registers to implement software breakpoints. Disabling
1086 SW Bkpts frees that register again.
1087 @item @b{arm7_9 force_hw_bkpts} <@var{enable}|@var{disable}>
1088 @cindex arm7_9 force_hw_bkpts
1089 When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
1090 breakpoints are turned into hardware breakpoints.
1091 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
1092 @cindex arm7_9 dbgrq
1093 Enable use of the DBGRQ bit to force entry into debug mode. This should be
1094 safe for all but ARM7TDMI--S cores (like Philips LPC).
1095 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
1096 @cindex arm7_9 fast_memory_access
1097 Allow OpenOCD to read and write memory without checking completion of
1098 the operation. This provides a huge speed increase, especially with USB JTAG
1099 cables (FT2232), but might be unsafe if used with targets running at a very low
1100 speed, like the 32kHz startup clock of an AT91RM9200.
1101 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
1102 @cindex arm7_9 dcc_downloads
1103 Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
1104 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
1105 unsafe, especially with targets running at a very low speed. This command was introduced
1106 with OpenOCD rev. 60.
1109 @subsection ARM720T specific commands
1110 @cindex ARM720T specific commands
1113 @item @b{arm720t cp15} <@var{num}> [@var{value}]
1114 @cindex arm720t cp15
1115 display/modify cp15 register <@option{num}> [@option{value}].
1116 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
1117 @cindex arm720t md<bhw>_phys
1118 Display memory at physical address addr.
1119 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
1120 @cindex arm720t mw<bhw>_phys
1121 Write memory at physical address addr.
1122 @item @b{arm720t virt2phys} <@var{va}>
1123 @cindex arm720t virt2phys
1124 Translate a virtual address to a physical address.
1127 @subsection ARM9TDMI specific commands
1128 @cindex ARM9TDMI specific commands
1131 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
1132 @cindex arm9tdmi vector_catch
1133 Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
1134 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
1135 @option{irq} @option{fiq}.
1137 Can also be used on other arm9 based cores, arm966, arm920t and arm926ejs.
1140 @subsection ARM966E specific commands
1141 @cindex ARM966E specific commands
1144 @item @b{arm966e cp15} <@var{num}> [@var{value}]
1145 @cindex arm966e cp15
1146 display/modify cp15 register <@option{num}> [@option{value}].
1149 @subsection ARM920T specific commands
1150 @cindex ARM920T specific commands
1153 @item @b{arm920t cp15} <@var{num}> [@var{value}]
1154 @cindex arm920t cp15
1155 display/modify cp15 register <@option{num}> [@option{value}].
1156 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
1157 @cindex arm920t cp15i
1158 display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
1159 @item @b{arm920t cache_info}
1160 @cindex arm920t cache_info
1161 Print information about the caches found. This allows you to see if your target
1162 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
1163 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
1164 @cindex arm920t md<bhw>_phys
1165 Display memory at physical address addr.
1166 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
1167 @cindex arm920t mw<bhw>_phys
1168 Write memory at physical address addr.
1169 @item @b{arm920t read_cache} <@var{filename}>
1170 @cindex arm920t read_cache
1171 Dump the content of ICache and DCache to a file.
1172 @item @b{arm920t read_mmu} <@var{filename}>
1173 @cindex arm920t read_mmu
1174 Dump the content of the ITLB and DTLB to a file.
1175 @item @b{arm920t virt2phys} <@var{va}>
1176 @cindex arm920t virt2phys
1177 Translate a virtual address to a physical address.
1180 @subsection ARM926EJS specific commands
1181 @cindex ARM926EJS specific commands
1184 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
1185 @cindex arm926ejs cp15
1186 display/modify cp15 register <@option{num}> [@option{value}].
1187 @item @b{arm926ejs cache_info}
1188 @cindex arm926ejs cache_info
1189 Print information about the caches found.
1190 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
1191 @cindex arm926ejs md<bhw>_phys
1192 Display memory at physical address addr.
1193 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
1194 @cindex arm926ejs mw<bhw>_phys
1195 Write memory at physical address addr.
1196 @item @b{arm926ejs virt2phys} <@var{va}>
1197 @cindex arm926ejs virt2phys
1198 Translate a virtual address to a physical address.
1202 @section Debug commands
1203 @cindex Debug commands
1204 The following commands give direct access to the core, and are most likely
1205 only useful while debugging OpenOCD.
1207 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
1208 @cindex arm7_9 write_xpsr
1209 Immediately write either the current program status register (CPSR) or the saved
1210 program status register (SPSR), without changing the register cache (as displayed
1211 by the @option{reg} and @option{armv4_5 reg} commands).
1212 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
1213 <@var{0=cpsr},@var{1=spsr}>
1214 @cindex arm7_9 write_xpsr_im8
1215 Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
1216 operation (similar to @option{write_xpsr}).
1217 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
1218 @cindex arm7_9 write_core_reg
1219 Write a core register, without changing the register cache (as displayed by the
1220 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
1221 encoding of the [M4:M0] bits of the PSR.
1225 @section JTAG commands
1226 @cindex JTAG commands
1228 @item @b{scan_chain}
1230 Print current scan chain configuration.
1231 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
1234 @item @b{endstate} <@var{tap_state}>
1236 Finish JTAG operations in <@var{tap_state}>.
1237 @item @b{runtest} <@var{num_cycles}>
1239 Move to Run-Test/Idle, and execute <@var{num_cycles}>
1240 @item @b{statemove} [@var{tap_state}]
1242 Move to current endstate or [@var{tap_state}]
1243 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1245 Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1246 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
1248 Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
1249 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
1250 @cindex verify_ircapture
1251 Verify value captured during Capture-IR. Default is enabled.
1252 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1254 Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1255 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1257 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
1261 @section Target Requests
1262 @cindex Target Requests
1263 OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
1264 See libdcc in the contrib dir for more details.
1266 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
1267 @cindex target_request debugmsgs
1268 Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
1271 @node Sample Scripts
1272 @chapter Sample Scripts
1275 This page shows how to use the target library.
1277 The configuration script can be divided in the following section:
1279 @item daemon configuration
1281 @item jtag scan chain
1282 @item target configuration
1283 @item flash configuration
1286 Detailed information about each section can be found at OpenOCD configuration.
1288 @section AT91R40008 example
1289 @cindex AT91R40008 example
1290 To start OpenOCD with a target script for the AT91R40008 CPU and reset
1291 the CPU upon startup of the OpenOCD daemon.
1293 openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
1297 @node GDB and OpenOCD
1298 @chapter GDB and OpenOCD
1299 @cindex GDB and OpenOCD
1300 OpenOCD complies with the remote gdbserver protocol, and as such can be used
1301 to debug remote targets.
1303 @section Connecting to gdb
1304 @cindex Connecting to gdb
1305 A connection is typically started as follows:
1307 target remote localhost:3333
1309 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
1311 To see a list of available OpenOCD commands type @option{monitor help} on the
1314 OpenOCD supports the gdb @option{qSupported} packet, this enables information
1315 to be sent by the gdb server (openocd) to gdb. Typical information includes
1316 packet size and device memory map.
1318 Previous versions of OpenOCD required the following gdb options to increase
1319 the packet size and speed up gdb communication.
1321 set remote memory-write-packet-size 1024
1322 set remote memory-write-packet-size fixed
1323 set remote memory-read-packet-size 1024
1324 set remote memory-read-packet-size fixed
1326 This is now handled in the @option{qSupported} PacketSize.
1328 @section Programming using gdb
1329 @cindex Programming using gdb
1331 By default the target memory map is sent to gdb, this can be disabled by
1332 the following OpenOCD config option:
1334 gdb_memory_map disable
1336 For this to function correctly a valid flash config must also be configured
1337 in OpenOCD. For faster performance you should also configure a valid
1340 Informing gdb of the memory map of the target will enable gdb to protect any
1341 flash area of the target and use hardware breakpoints by default. This means
1342 that the OpenOCD option @option{arm7_9 force_hw_bkpts} is not required when
1345 To view the configured memory map in gdb, use the gdb command @option{info mem}
1346 All other unasigned addresses within gdb are treated as RAM.
1348 GDB 6.8 and higher set any memory area not in the memory map as inaccessible,
1349 this can be changed to the old behaviour by using the following gdb command.
1351 set mem inaccessible-by-default off
1354 If @option{gdb_flash_program enable} is also used, gdb will be able to
1355 program any flash memory using the vFlash interface.
1357 gdb will look at the target memory map when a load command is given, if any
1358 areas to be programmed lie within the target flash area the vFlash packets
1361 If the target needs configuring before gdb programming, a script can be executed.
1363 target_script 0 gdb_program_config config.script
1366 To verify any flash programming the gdb command @option{compare-sections}
1369 @node TCL and OpenOCD
1370 @chapter TCL and OpenOCD
1371 @cindex TCL and OpenOCD
1372 OpenOCD embeds a TCL interpreter (see JIM) for command parsing and scripting
1375 The TCL interpreter can be invoked from the interactive command line, files, and a network port.
1377 The command and file interfaces are fairly straightforward, while the network
1378 port is geared toward intergration with external clients. A small example
1379 of an external TCL script that can connect to openocd is shown below.
1382 # Simple tcl client to connect to openocd
1383 puts "Use empty line to exit"
1384 set fo [socket 127.0.0.1 5555]
1385 puts -nonewline stdout "> "
1387 while {[gets stdin line] >= 0} {
1388 if {$line eq {}} break
1393 puts -nonewline stdout "> "
1399 This script can easily be modified to front various GUIs or be a sub
1400 component of a larger framework for control and interaction.
1403 @chapter Deprecated/Removed Commands
1404 @cindex Deprecated/Removed Commands
1405 Certain OpenOCD commands have been deprecated/removed during the various revisions.
1408 @item @b{load_binary}
1410 use @option{load_image} command with same args
1411 @item @b{dump_binary}
1413 use @option{dump_image} command with same args
1414 @item @b{flash erase}
1416 use @option{flash erase_sector} command with same args
1417 @item @b{flash write}
1419 use @option{flash write_bank} command with same args
1420 @item @b{flash write_binary}
1421 @cindex flash write_binary
1422 use @option{flash write_bank} command with same args
1423 @item @b{arm7_9 fast_writes}
1424 @cindex arm7_9 fast_writes
1425 use @option{arm7_9 fast_memory_access} command with same args
1426 @item @b{flash auto_erase}
1427 @cindex flash auto_erase
1428 use @option{flash write_image} command passing @option{erase} as the first parameter.
1435 @item OpenOCD complains about a missing cygwin1.dll.
1437 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1438 claims to come with all the necessary dlls. When using Cygwin, try launching
1439 OpenOCD from the Cygwin shell.
1441 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1442 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1443 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1445 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1446 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1447 software breakpoints consume one of the two available hardware breakpoints,
1448 and are therefore disabled by default. If your code is running from RAM, you
1449 can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
1450 your code resides in Flash, you can't use software breakpoints, but you can force
1451 OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
1453 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
1454 and works sometimes fine.
1456 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
1457 clock at the time you're programming the flash. If you've specified the crystal's
1458 frequency, make sure the PLL is disabled, if you've specified the full core speed
1459 (e.g. 60MHz), make sure the PLL is enabled.
1461 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
1462 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
1463 out while waiting for end of scan, rtck was disabled".
1465 Make sure your PC's parallel port operates in EPP mode. You might have to try several
1466 settings in your PC BIOS (ECP, EPP, and different versions of those).
1468 @item When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
1469 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
1470 memory read caused data abort".
1472 The errors are non-fatal, and are the result of GDB trying to trace stack frames
1473 beyond the last valid frame. It might be possible to prevent this by setting up
1474 a proper "initial" stack frame, if you happen to know what exactly has to
1475 be done, feel free to add this here.
1477 @item I get the following message in the OpenOCD console (or log file):
1478 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
1480 This warning doesn't indicate any serious problem, as long as you don't want to
1481 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
1482 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
1483 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
1484 independently. With this setup, it's not possible to halt the core right out of
1485 reset, everything else should work fine.
1487 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
1488 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
1489 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
1490 quit with an error message. Is there a stability issue with OpenOCD?
1492 No, this is not a stability issue concerning OpenOCD. Most users have solved
1493 this issue by simply using a self-powered USB hub, which they connect their
1494 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
1495 supply stable enough for the Amontec JTAGkey to be operated.
1497 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
1498 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
1499 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
1500 What does that mean and what might be the reason for this?
1502 First of all, the reason might be the USB power supply. Try using a self-powered
1503 hub instead of a direct connection to your computer. Secondly, the error code 4
1504 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
1505 chip ran into some sort of error - this points us to a USB problem.
1507 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
1508 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
1509 What does that mean and what might be the reason for this?
1511 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
1512 has closed the connection to OpenOCD. This might be a GDB issue.
1514 @item In the configuration file in the section where flash device configurations
1515 are described, there is a parameter for specifying the clock frequency for
1516 LPC2000 internal flash devices (e.g.
1517 @option{flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}),
1518 which must be specified in kilohertz. However, I do have a quartz crystal of a
1519 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
1520 Is it possible to specify real numbers for the clock frequency?
1522 No. The clock frequency specified here must be given as an integral number.
1523 However, this clock frequency is used by the In-Application-Programming (IAP)
1524 routines of the LPC2000 family only, which seems to be very tolerant concerning
1525 the given clock frequency, so a slight difference between the specified clock
1526 frequency and the actual clock frequency will not cause any trouble.
1528 @item Do I have to keep a specific order for the commands in the configuration file?
1530 Well, yes and no. Commands can be given in arbitrary order, yet the devices
1531 listed for the JTAG scan chain must be given in the right order (jtag_device),
1532 with the device closest to the TDO-Pin being listed first. In general,
1533 whenever objects of the same type exist which require an index number, then
1534 these objects must be given in the right order (jtag_devices, targets and flash
1535 banks - a target references a jtag_device and a flash bank references a target).
1537 @item Sometimes my debugging session terminates with an error. When I look into the
1538 log file, I can see these error messages: Error: arm7_9_common.c:561
1539 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP