target: add Espressif ESP32 basic support
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
11
12 @include version.texi
13
14 @copying
15
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
20
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
28
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A
34 copy of the license is included in the section entitled ``GNU Free
35 Documentation License''.
36 @end quotation
37 @end copying
38
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
45
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
50
51 @summarycontents
52 @contents
53
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
57
58 @insertcopying
59 @end ifnottex
60
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
87
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
94 @end menu
95
96 @node About
97 @unnumbered About
98 @cindex about
99
100 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
101 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
104 around the world.
105
106 @section What is OpenOCD?
107 @cindex TAP
108 @cindex JTAG
109
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
112 devices.
113
114 It does so with the assistance of a @dfn{debug adapter}, which is
115 a small hardware module which helps provide the right kind of
116 electrical signaling to the target being debugged. These are
117 required since the debug host (on which OpenOCD runs) won't
118 usually have native support for such signaling, or the connector
119 needed to hook up to the target.
120
121 Such debug adapters support one or more @dfn{transport} protocols,
122 each of which involves different electrical signaling (and uses
123 different messaging protocols on top of that signaling). There
124 are many types of debug adapter, and little uniformity in what
125 they are called. (There are also product naming differences.)
126
127 These adapters are sometimes packaged as discrete dongles, which
128 may generically be called @dfn{hardware interface dongles}.
129 Some development boards also integrate them directly, which may
130 let the development board connect directly to the debug
131 host over USB (and sometimes also to power it over USB).
132
133 For example, a @dfn{JTAG Adapter} supports JTAG
134 signaling, and is used to communicate
135 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
136 A @dfn{TAP} is a ``Test Access Port'', a module which processes
137 special instructions and data. TAPs are daisy-chained within and
138 between chips and boards. JTAG supports debugging and boundary
139 scan operations.
140
141 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
142 signaling to communicate with some newer ARM cores, as well as debug
143 adapters which support both JTAG and SWD transports. SWD supports only
144 debugging, whereas JTAG also supports boundary scan operations.
145
146 For some chips, there are also @dfn{Programming Adapters} supporting
147 special transports used only to write code to flash memory, without
148 support for on-chip debugging or boundary scan.
149 (At this writing, OpenOCD does not support such non-debug adapters.)
150
151
152 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
153 USB-based, parallel port-based, and other standalone boxes that run
154 OpenOCD internally. @xref{Debug Adapter Hardware}.
155
156 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
157 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
158 (Stellaris LM3, STMicroelectronics STM32 and Energy Micro EFM32) and
159 Intel Quark (x10xx) based cores to be debugged via the GDB protocol.
160
161 @b{Flash Programming:} Flash writing is supported for external
162 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
163 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
164 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
165 controllers (LPC3180, Orion, S3C24xx, more) is included.
166
167 @section OpenOCD Web Site
168
169 The OpenOCD web site provides the latest public news from the community:
170
171 @uref{http://openocd.org/}
172
173 @section Latest User's Guide:
174
175 The user's guide you are now reading may not be the latest one
176 available. A version for more recent code may be available.
177 Its HTML form is published regularly at:
178
179 @uref{http://openocd.org/doc/html/index.html}
180
181 PDF form is likewise published at:
182
183 @uref{http://openocd.org/doc/pdf/openocd.pdf}
184
185 @section OpenOCD User's Forum
186
187 There is an OpenOCD forum (phpBB) hosted by SparkFun,
188 which might be helpful to you. Note that if you want
189 anything to come to the attention of developers, you
190 should post it to the OpenOCD Developer Mailing List
191 instead of this forum.
192
193 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
194
195 @section OpenOCD User's Mailing List
196
197 The OpenOCD User Mailing List provides the primary means of
198 communication between users:
199
200 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
201
202 @section OpenOCD IRC
203
204 Support can also be found on irc:
205 @uref{irc://irc.libera.chat/openocd}
206
207 @node Developers
208 @chapter OpenOCD Developer Resources
209 @cindex developers
210
211 If you are interested in improving the state of OpenOCD's debugging and
212 testing support, new contributions will be welcome. Motivated developers
213 can produce new target, flash or interface drivers, improve the
214 documentation, as well as more conventional bug fixes and enhancements.
215
216 The resources in this chapter are available for developers wishing to explore
217 or expand the OpenOCD source code.
218
219 @section OpenOCD Git Repository
220
221 During the 0.3.x release cycle, OpenOCD switched from Subversion to
222 a Git repository hosted at SourceForge. The repository URL is:
223
224 @uref{git://git.code.sf.net/p/openocd/code}
225
226 or via http
227
228 @uref{http://git.code.sf.net/p/openocd/code}
229
230 You may prefer to use a mirror and the HTTP protocol:
231
232 @uref{http://repo.or.cz/r/openocd.git}
233
234 With standard Git tools, use @command{git clone} to initialize
235 a local repository, and @command{git pull} to update it.
236 There are also gitweb pages letting you browse the repository
237 with a web browser, or download arbitrary snapshots without
238 needing a Git client:
239
240 @uref{http://repo.or.cz/w/openocd.git}
241
242 The @file{README} file contains the instructions for building the project
243 from the repository or a snapshot.
244
245 Developers that want to contribute patches to the OpenOCD system are
246 @b{strongly} encouraged to work against mainline.
247 Patches created against older versions may require additional
248 work from their submitter in order to be updated for newer releases.
249
250 @section Doxygen Developer Manual
251
252 During the 0.2.x release cycle, the OpenOCD project began
253 providing a Doxygen reference manual. This document contains more
254 technical information about the software internals, development
255 processes, and similar documentation:
256
257 @uref{http://openocd.org/doc/doxygen/html/index.html}
258
259 This document is a work-in-progress, but contributions would be welcome
260 to fill in the gaps. All of the source files are provided in-tree,
261 listed in the Doxyfile configuration at the top of the source tree.
262
263 @section Gerrit Review System
264
265 All changes in the OpenOCD Git repository go through the web-based Gerrit
266 Code Review System:
267
268 @uref{https://review.openocd.org/}
269
270 After a one-time registration and repository setup, anyone can push commits
271 from their local Git repository directly into Gerrit.
272 All users and developers are encouraged to review, test, discuss and vote
273 for changes in Gerrit. The feedback provides the basis for a maintainer to
274 eventually submit the change to the main Git repository.
275
276 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
277 Developer Manual, contains basic information about how to connect a
278 repository to Gerrit, prepare and push patches. Patch authors are expected to
279 maintain their changes while they're in Gerrit, respond to feedback and if
280 necessary rework and push improved versions of the change.
281
282 @section OpenOCD Developer Mailing List
283
284 The OpenOCD Developer Mailing List provides the primary means of
285 communication between developers:
286
287 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
288
289 @section OpenOCD Bug Tracker
290
291 The OpenOCD Bug Tracker is hosted on SourceForge:
292
293 @uref{http://bugs.openocd.org/}
294
295
296 @node Debug Adapter Hardware
297 @chapter Debug Adapter Hardware
298 @cindex dongles
299 @cindex FTDI
300 @cindex wiggler
301 @cindex printer port
302 @cindex USB Adapter
303 @cindex RTCK
304
305 Defined: @b{dongle}: A small device that plugs into a computer and serves as
306 an adapter .... [snip]
307
308 In the OpenOCD case, this generally refers to @b{a small adapter} that
309 attaches to your computer via USB or the parallel port.
310
311
312 @section Choosing a Dongle
313
314 There are several things you should keep in mind when choosing a dongle.
315
316 @enumerate
317 @item @b{Transport} Does it support the kind of communication that you need?
318 OpenOCD focuses mostly on JTAG. Your version may also support
319 other ways to communicate with target devices.
320 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
321 Does your dongle support it? You might need a level converter.
322 @item @b{Pinout} What pinout does your target board use?
323 Does your dongle support it? You may be able to use jumper
324 wires, or an "octopus" connector, to convert pinouts.
325 @item @b{Connection} Does your computer have the USB, parallel, or
326 Ethernet port needed?
327 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
328 RTCK support (also known as ``adaptive clocking'')?
329 @end enumerate
330
331 @section USB FT2232 Based
332
333 There are many USB JTAG dongles on the market, many of them based
334 on a chip from ``Future Technology Devices International'' (FTDI)
335 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
336 See: @url{http://www.ftdichip.com} for more information.
337 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
338 chips started to become available in JTAG adapters. Around 2012, a new
339 variant appeared - FT232H - this is a single-channel version of FT2232H.
340 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
341 clocking.)
342
343 The FT2232 chips are flexible enough to support some other
344 transport options, such as SWD or the SPI variants used to
345 program some chips. They have two communications channels,
346 and one can be used for a UART adapter at the same time the
347 other one is used to provide a debug adapter.
348
349 Also, some development boards integrate an FT2232 chip to serve as
350 a built-in low-cost debug adapter and USB-to-serial solution.
351
352 @itemize @bullet
353 @item @b{usbjtag}
354 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
355 @item @b{jtagkey}
356 @* See: @url{http://www.amontec.com/jtagkey.shtml}
357 @item @b{jtagkey2}
358 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
359 @item @b{oocdlink}
360 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
361 @item @b{signalyzer}
362 @* See: @url{http://www.signalyzer.com}
363 @item @b{Stellaris Eval Boards}
364 @* See: @url{http://www.ti.com} - The Stellaris eval boards
365 bundle FT2232-based JTAG and SWD support, which can be used to debug
366 the Stellaris chips. Using separate JTAG adapters is optional.
367 These boards can also be used in a "pass through" mode as JTAG adapters
368 to other target boards, disabling the Stellaris chip.
369 @item @b{TI/Luminary ICDI}
370 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
371 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
372 Evaluation Kits. Like the non-detachable FT2232 support on the other
373 Stellaris eval boards, they can be used to debug other target boards.
374 @item @b{olimex-jtag}
375 @* See: @url{http://www.olimex.com}
376 @item @b{Flyswatter/Flyswatter2}
377 @* See: @url{http://www.tincantools.com}
378 @item @b{turtelizer2}
379 @* See:
380 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
381 @url{http://www.ethernut.de}
382 @item @b{comstick}
383 @* Link: @url{http://www.hitex.com/index.php?id=383}
384 @item @b{stm32stick}
385 @* Link @url{http://www.hitex.com/stm32-stick}
386 @item @b{axm0432_jtag}
387 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
388 to be available anymore as of April 2012.
389 @item @b{cortino}
390 @* Link @url{http://www.hitex.com/index.php?id=cortino}
391 @item @b{dlp-usb1232h}
392 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
393 @item @b{digilent-hs1}
394 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
395 @item @b{opendous}
396 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
397 (OpenHardware).
398 @item @b{JTAG-lock-pick Tiny 2}
399 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
400
401 @item @b{GW16042}
402 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
403 FT2232H-based
404
405 @end itemize
406 @section USB-JTAG / Altera USB-Blaster compatibles
407
408 These devices also show up as FTDI devices, but are not
409 protocol-compatible with the FT2232 devices. They are, however,
410 protocol-compatible among themselves. USB-JTAG devices typically consist
411 of a FT245 followed by a CPLD that understands a particular protocol,
412 or emulates this protocol using some other hardware.
413
414 They may appear under different USB VID/PID depending on the particular
415 product. The driver can be configured to search for any VID/PID pair
416 (see the section on driver commands).
417
418 @itemize
419 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
420 @* Link: @url{http://ixo-jtag.sourceforge.net/}
421 @item @b{Altera USB-Blaster}
422 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
423 @end itemize
424
425 @section USB J-Link based
426 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
427 an example of a microcontroller based JTAG adapter, it uses an
428 AT91SAM764 internally.
429
430 @itemize @bullet
431 @item @b{SEGGER J-Link}
432 @* Link: @url{http://www.segger.com/jlink.html}
433 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
434 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
435 @item @b{IAR J-Link}
436 @end itemize
437
438 @section USB RLINK based
439 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
440 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
441 SWD and not JTAG, thus not supported.
442
443 @itemize @bullet
444 @item @b{Raisonance RLink}
445 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
446 @item @b{STM32 Primer}
447 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
448 @item @b{STM32 Primer2}
449 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
450 @end itemize
451
452 @section USB ST-LINK based
453 STMicroelectronics has an adapter called @b{ST-LINK}.
454 They only work with STMicroelectronics chips, notably STM32 and STM8.
455
456 @itemize @bullet
457 @item @b{ST-LINK}
458 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
459 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
460 @item @b{ST-LINK/V2}
461 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
462 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
463 @item @b{STLINK-V3}
464 @* This is available standalone and as part of some kits.
465 @* Link: @url{http://www.st.com/stlink-v3}
466 @end itemize
467
468 For info the original ST-LINK enumerates using the mass storage usb class; however,
469 its implementation is completely broken. The result is this causes issues under Linux.
470 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
471 @itemize @bullet
472 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
473 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
474 @end itemize
475
476 @section USB TI/Stellaris ICDI based
477 Texas Instruments has an adapter called @b{ICDI}.
478 It is not to be confused with the FTDI based adapters that were originally fitted to their
479 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
480
481 @section USB Nuvoton Nu-Link
482 Nuvoton has an adapter called @b{Nu-Link}.
483 It is available either as stand-alone dongle and embedded on development boards.
484 It supports SWD, serial port bridge and mass storage for firmware update.
485 Both Nu-Link v1 and v2 are supported.
486
487 @section USB CMSIS-DAP based
488 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
489 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
490
491 @section USB Other
492 @itemize @bullet
493 @item @b{USBprog}
494 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
495
496 @item @b{USB - Presto}
497 @* Link: @url{http://tools.asix.net/prg_presto.htm}
498
499 @item @b{Versaloon-Link}
500 @* Link: @url{http://www.versaloon.com}
501
502 @item @b{ARM-JTAG-EW}
503 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
504
505 @item @b{Buspirate}
506 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
507
508 @item @b{opendous}
509 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
510
511 @item @b{estick}
512 @* Link: @url{http://code.google.com/p/estick-jtag/}
513
514 @item @b{Keil ULINK v1}
515 @* Link: @url{http://www.keil.com/ulink1/}
516
517 @item @b{TI XDS110 Debug Probe}
518 @* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds110.html}
519 @* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds_software_package_download.html#xds110-support-utilities}
520 @end itemize
521
522 @section IBM PC Parallel Printer Port Based
523
524 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
525 and the Macraigor Wiggler. There are many clones and variations of
526 these on the market.
527
528 Note that parallel ports are becoming much less common, so if you
529 have the choice you should probably avoid these adapters in favor
530 of USB-based ones.
531
532 @itemize @bullet
533
534 @item @b{Wiggler} - There are many clones of this.
535 @* Link: @url{http://www.macraigor.com/wiggler.htm}
536
537 @item @b{DLC5} - From XILINX - There are many clones of this
538 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
539 produced, PDF schematics are easily found and it is easy to make.
540
541 @item @b{Amontec - JTAG Accelerator}
542 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
543
544 @item @b{Wiggler2}
545 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
546
547 @item @b{Wiggler_ntrst_inverted}
548 @* Yet another variation - See the source code, src/jtag/parport.c
549
550 @item @b{old_amt_wiggler}
551 @* Unknown - probably not on the market today
552
553 @item @b{arm-jtag}
554 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
555
556 @item @b{chameleon}
557 @* Link: @url{http://www.amontec.com/chameleon.shtml}
558
559 @item @b{Triton}
560 @* Unknown.
561
562 @item @b{Lattice}
563 @* ispDownload from Lattice Semiconductor
564 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
565
566 @item @b{flashlink}
567 @* From STMicroelectronics;
568 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
569
570 @end itemize
571
572 @section Other...
573 @itemize @bullet
574
575 @item @b{ep93xx}
576 @* An EP93xx based Linux machine using the GPIO pins directly.
577
578 @item @b{at91rm9200}
579 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
580
581 @item @b{bcm2835gpio}
582 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
583
584 @item @b{imx_gpio}
585 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
586
587 @item @b{am335xgpio}
588 @* A Texas Instruments AM335x-based board (e.g. BeagleBone Black) using the GPIO pins of the expansion headers.
589
590 @item @b{jtag_vpi}
591 @* A JTAG driver acting as a client for the JTAG VPI server interface.
592 @* Link: @url{http://github.com/fjullien/jtag_vpi}
593
594 @item @b{vdebug}
595 @* A driver for Cadence virtual Debug Interface to emulated or simulated targets.
596 It implements a client connecting to the vdebug server, which in turn communicates
597 with the emulated or simulated RTL model through a transactor. The current version
598 supports only JTAG as a transport, but other virtual transports, like DAP are planned.
599
600 @item @b{jtag_dpi}
601 @* A JTAG driver acting as a client for the SystemVerilog Direct Programming
602 Interface (DPI) for JTAG devices. DPI allows OpenOCD to connect to the JTAG
603 interface of a hardware model written in SystemVerilog, for example, on an
604 emulation model of target hardware.
605
606 @item @b{xlnx_pcie_xvc}
607 @* A JTAG driver exposing Xilinx Virtual Cable over PCI Express to OpenOCD as JTAG/SWD interface.
608
609 @item @b{linuxgpiod}
610 @* A bitbang JTAG driver using Linux GPIO through library libgpiod.
611
612 @item @b{sysfsgpio}
613 @* A bitbang JTAG driver using Linux legacy sysfs GPIO.
614 This is deprecated from Linux v5.3; prefer using @b{linuxgpiod}.
615
616 @end itemize
617
618 @node About Jim-Tcl
619 @chapter About Jim-Tcl
620 @cindex Jim-Tcl
621 @cindex tcl
622
623 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
624 This programming language provides a simple and extensible
625 command interpreter.
626
627 All commands presented in this Guide are extensions to Jim-Tcl.
628 You can use them as simple commands, without needing to learn
629 much of anything about Tcl.
630 Alternatively, you can write Tcl programs with them.
631
632 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
633 There is an active and responsive community, get on the mailing list
634 if you have any questions. Jim-Tcl maintainers also lurk on the
635 OpenOCD mailing list.
636
637 @itemize @bullet
638 @item @b{Jim vs. Tcl}
639 @* Jim-Tcl is a stripped down version of the well known Tcl language,
640 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
641 fewer features. Jim-Tcl is several dozens of .C files and .H files and
642 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
643 4.2 MB .zip file containing 1540 files.
644
645 @item @b{Missing Features}
646 @* Our practice has been: Add/clone the real Tcl feature if/when
647 needed. We welcome Jim-Tcl improvements, not bloat. Also there
648 are a large number of optional Jim-Tcl features that are not
649 enabled in OpenOCD.
650
651 @item @b{Scripts}
652 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
653 command interpreter today is a mixture of (newer)
654 Jim-Tcl commands, and the (older) original command interpreter.
655
656 @item @b{Commands}
657 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
658 can type a Tcl for() loop, set variables, etc.
659 Some of the commands documented in this guide are implemented
660 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
661
662 @item @b{Historical Note}
663 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
664 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
665 as a Git submodule, which greatly simplified upgrading Jim-Tcl
666 to benefit from new features and bugfixes in Jim-Tcl.
667
668 @item @b{Need a crash course in Tcl?}
669 @*@xref{Tcl Crash Course}.
670 @end itemize
671
672 @node Running
673 @chapter Running
674 @cindex command line options
675 @cindex logfile
676 @cindex directory search
677
678 Properly installing OpenOCD sets up your operating system to grant it access
679 to the debug adapters. On Linux, this usually involves installing a file
680 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
681 that works for many common adapters is shipped with OpenOCD in the
682 @file{contrib} directory. MS-Windows needs
683 complex and confusing driver configuration for every peripheral. Such issues
684 are unique to each operating system, and are not detailed in this User's Guide.
685
686 Then later you will invoke the OpenOCD server, with various options to
687 tell it how each debug session should work.
688 The @option{--help} option shows:
689 @verbatim
690 bash$ openocd --help
691
692 --help | -h display this help
693 --version | -v display OpenOCD version
694 --file | -f use configuration file <name>
695 --search | -s dir to search for config files and scripts
696 --debug | -d set debug level to 3
697 | -d<n> set debug level to <level>
698 --log_output | -l redirect log output to file <name>
699 --command | -c run <command>
700 @end verbatim
701
702 If you don't give any @option{-f} or @option{-c} options,
703 OpenOCD tries to read the configuration file @file{openocd.cfg}.
704 To specify one or more different
705 configuration files, use @option{-f} options. For example:
706
707 @example
708 openocd -f config1.cfg -f config2.cfg -f config3.cfg
709 @end example
710
711 Configuration files and scripts are searched for in
712 @enumerate
713 @item the current directory,
714 @item any search dir specified on the command line using the @option{-s} option,
715 @item any search dir specified using the @command{add_script_search_dir} command,
716 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
717 @item @file{%APPDATA%/OpenOCD} (only on Windows),
718 @item @file{$HOME/Library/Preferences/org.openocd} (only on Darwin),
719 @item @file{$XDG_CONFIG_HOME/openocd} (@env{$XDG_CONFIG_HOME} defaults to @file{$HOME/.config}),
720 @item @file{$HOME/.openocd},
721 @item the site wide script library @file{$pkgdatadir/site} and
722 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
723 @end enumerate
724 The first found file with a matching file name will be used.
725
726 @quotation Note
727 Don't try to use configuration script names or paths which
728 include the "#" character. That character begins Tcl comments.
729 @end quotation
730
731 @section Simple setup, no customization
732
733 In the best case, you can use two scripts from one of the script
734 libraries, hook up your JTAG adapter, and start the server ... and
735 your JTAG setup will just work "out of the box". Always try to
736 start by reusing those scripts, but assume you'll need more
737 customization even if this works. @xref{OpenOCD Project Setup}.
738
739 If you find a script for your JTAG adapter, and for your board or
740 target, you may be able to hook up your JTAG adapter then start
741 the server with some variation of one of the following:
742
743 @example
744 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
745 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
746 @end example
747
748 You might also need to configure which reset signals are present,
749 using @option{-c 'reset_config trst_and_srst'} or something similar.
750 If all goes well you'll see output something like
751
752 @example
753 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
754 For bug reports, read
755 http://openocd.org/doc/doxygen/bugs.html
756 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
757 (mfg: 0x23b, part: 0xba00, ver: 0x3)
758 @end example
759
760 Seeing that "tap/device found" message, and no warnings, means
761 the JTAG communication is working. That's a key milestone, but
762 you'll probably need more project-specific setup.
763
764 @section What OpenOCD does as it starts
765
766 OpenOCD starts by processing the configuration commands provided
767 on the command line or, if there were no @option{-c command} or
768 @option{-f file.cfg} options given, in @file{openocd.cfg}.
769 @xref{configurationstage,,Configuration Stage}.
770 At the end of the configuration stage it verifies the JTAG scan
771 chain defined using those commands; your configuration should
772 ensure that this always succeeds.
773 Normally, OpenOCD then starts running as a server.
774 Alternatively, commands may be used to terminate the configuration
775 stage early, perform work (such as updating some flash memory),
776 and then shut down without acting as a server.
777
778 Once OpenOCD starts running as a server, it waits for connections from
779 clients (Telnet, GDB, RPC) and processes the commands issued through
780 those channels.
781
782 If you are having problems, you can enable internal debug messages via
783 the @option{-d} option.
784
785 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
786 @option{-c} command line switch.
787
788 To enable debug output (when reporting problems or working on OpenOCD
789 itself), use the @option{-d} command line switch. This sets the
790 @option{debug_level} to "3", outputting the most information,
791 including debug messages. The default setting is "2", outputting only
792 informational messages, warnings and errors. You can also change this
793 setting from within a telnet or gdb session using @command{debug_level<n>}
794 (@pxref{debuglevel,,debug_level}).
795
796 You can redirect all output from the server to a file using the
797 @option{-l <logfile>} switch.
798
799 Note! OpenOCD will launch the GDB & telnet server even if it can not
800 establish a connection with the target. In general, it is possible for
801 the JTAG controller to be unresponsive until the target is set up
802 correctly via e.g. GDB monitor commands in a GDB init script.
803
804 @node OpenOCD Project Setup
805 @chapter OpenOCD Project Setup
806
807 To use OpenOCD with your development projects, you need to do more than
808 just connect the JTAG adapter hardware (dongle) to your development board
809 and start the OpenOCD server.
810 You also need to configure your OpenOCD server so that it knows
811 about your adapter and board, and helps your work.
812 You may also want to connect OpenOCD to GDB, possibly
813 using Eclipse or some other GUI.
814
815 @section Hooking up the JTAG Adapter
816
817 Today's most common case is a dongle with a JTAG cable on one side
818 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
819 and a USB cable on the other.
820 Instead of USB, some dongles use Ethernet;
821 older ones may use a PC parallel port, or even a serial port.
822
823 @enumerate
824 @item @emph{Start with power to your target board turned off},
825 and nothing connected to your JTAG adapter.
826 If you're particularly paranoid, unplug power to the board.
827 It's important to have the ground signal properly set up,
828 unless you are using a JTAG adapter which provides
829 galvanic isolation between the target board and the
830 debugging host.
831
832 @item @emph{Be sure it's the right kind of JTAG connector.}
833 If your dongle has a 20-pin ARM connector, you need some kind
834 of adapter (or octopus, see below) to hook it up to
835 boards using 14-pin or 10-pin connectors ... or to 20-pin
836 connectors which don't use ARM's pinout.
837
838 In the same vein, make sure the voltage levels are compatible.
839 Not all JTAG adapters have the level shifters needed to work
840 with 1.2 Volt boards.
841
842 @item @emph{Be certain the cable is properly oriented} or you might
843 damage your board. In most cases there are only two possible
844 ways to connect the cable.
845 Connect the JTAG cable from your adapter to the board.
846 Be sure it's firmly connected.
847
848 In the best case, the connector is keyed to physically
849 prevent you from inserting it wrong.
850 This is most often done using a slot on the board's male connector
851 housing, which must match a key on the JTAG cable's female connector.
852 If there's no housing, then you must look carefully and
853 make sure pin 1 on the cable hooks up to pin 1 on the board.
854 Ribbon cables are frequently all grey except for a wire on one
855 edge, which is red. The red wire is pin 1.
856
857 Sometimes dongles provide cables where one end is an ``octopus'' of
858 color coded single-wire connectors, instead of a connector block.
859 These are great when converting from one JTAG pinout to another,
860 but are tedious to set up.
861 Use these with connector pinout diagrams to help you match up the
862 adapter signals to the right board pins.
863
864 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
865 A USB, parallel, or serial port connector will go to the host which
866 you are using to run OpenOCD.
867 For Ethernet, consult the documentation and your network administrator.
868
869 For USB-based JTAG adapters you have an easy sanity check at this point:
870 does the host operating system see the JTAG adapter? If you're running
871 Linux, try the @command{lsusb} command. If that host is an
872 MS-Windows host, you'll need to install a driver before OpenOCD works.
873
874 @item @emph{Connect the adapter's power supply, if needed.}
875 This step is primarily for non-USB adapters,
876 but sometimes USB adapters need extra power.
877
878 @item @emph{Power up the target board.}
879 Unless you just let the magic smoke escape,
880 you're now ready to set up the OpenOCD server
881 so you can use JTAG to work with that board.
882
883 @end enumerate
884
885 Talk with the OpenOCD server using
886 telnet (@code{telnet localhost 4444} on many systems) or GDB.
887 @xref{GDB and OpenOCD}.
888
889 @section Project Directory
890
891 There are many ways you can configure OpenOCD and start it up.
892
893 A simple way to organize them all involves keeping a
894 single directory for your work with a given board.
895 When you start OpenOCD from that directory,
896 it searches there first for configuration files, scripts,
897 files accessed through semihosting,
898 and for code you upload to the target board.
899 It is also the natural place to write files,
900 such as log files and data you download from the board.
901
902 @section Configuration Basics
903
904 There are two basic ways of configuring OpenOCD, and
905 a variety of ways you can mix them.
906 Think of the difference as just being how you start the server:
907
908 @itemize
909 @item Many @option{-f file} or @option{-c command} options on the command line
910 @item No options, but a @dfn{user config file}
911 in the current directory named @file{openocd.cfg}
912 @end itemize
913
914 Here is an example @file{openocd.cfg} file for a setup
915 using a Signalyzer FT2232-based JTAG adapter to talk to
916 a board with an Atmel AT91SAM7X256 microcontroller:
917
918 @example
919 source [find interface/ftdi/signalyzer.cfg]
920
921 # GDB can also flash my flash!
922 gdb_memory_map enable
923 gdb_flash_program enable
924
925 source [find target/sam7x256.cfg]
926 @end example
927
928 Here is the command line equivalent of that configuration:
929
930 @example
931 openocd -f interface/ftdi/signalyzer.cfg \
932 -c "gdb_memory_map enable" \
933 -c "gdb_flash_program enable" \
934 -f target/sam7x256.cfg
935 @end example
936
937 You could wrap such long command lines in shell scripts,
938 each supporting a different development task.
939 One might re-flash the board with a specific firmware version.
940 Another might set up a particular debugging or run-time environment.
941
942 @quotation Important
943 At this writing (October 2009) the command line method has
944 problems with how it treats variables.
945 For example, after @option{-c "set VAR value"}, or doing the
946 same in a script, the variable @var{VAR} will have no value
947 that can be tested in a later script.
948 @end quotation
949
950 Here we will focus on the simpler solution: one user config
951 file, including basic configuration plus any TCL procedures
952 to simplify your work.
953
954 @section User Config Files
955 @cindex config file, user
956 @cindex user config file
957 @cindex config file, overview
958
959 A user configuration file ties together all the parts of a project
960 in one place.
961 One of the following will match your situation best:
962
963 @itemize
964 @item Ideally almost everything comes from configuration files
965 provided by someone else.
966 For example, OpenOCD distributes a @file{scripts} directory
967 (probably in @file{/usr/share/openocd/scripts} on Linux).
968 Board and tool vendors can provide these too, as can individual
969 user sites; the @option{-s} command line option lets you say
970 where to find these files. (@xref{Running}.)
971 The AT91SAM7X256 example above works this way.
972
973 Three main types of non-user configuration file each have their
974 own subdirectory in the @file{scripts} directory:
975
976 @enumerate
977 @item @b{interface} -- one for each different debug adapter;
978 @item @b{board} -- one for each different board
979 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
980 @end enumerate
981
982 Best case: include just two files, and they handle everything else.
983 The first is an interface config file.
984 The second is board-specific, and it sets up the JTAG TAPs and
985 their GDB targets (by deferring to some @file{target.cfg} file),
986 declares all flash memory, and leaves you nothing to do except
987 meet your deadline:
988
989 @example
990 source [find interface/olimex-jtag-tiny.cfg]
991 source [find board/csb337.cfg]
992 @end example
993
994 Boards with a single microcontroller often won't need more
995 than the target config file, as in the AT91SAM7X256 example.
996 That's because there is no external memory (flash, DDR RAM), and
997 the board differences are encapsulated by application code.
998
999 @item Maybe you don't know yet what your board looks like to JTAG.
1000 Once you know the @file{interface.cfg} file to use, you may
1001 need help from OpenOCD to discover what's on the board.
1002 Once you find the JTAG TAPs, you can just search for appropriate
1003 target and board
1004 configuration files ... or write your own, from the bottom up.
1005 @xref{autoprobing,,Autoprobing}.
1006
1007 @item You can often reuse some standard config files but
1008 need to write a few new ones, probably a @file{board.cfg} file.
1009 You will be using commands described later in this User's Guide,
1010 and working with the guidelines in the next chapter.
1011
1012 For example, there may be configuration files for your JTAG adapter
1013 and target chip, but you need a new board-specific config file
1014 giving access to your particular flash chips.
1015 Or you might need to write another target chip configuration file
1016 for a new chip built around the Cortex-M3 core.
1017
1018 @quotation Note
1019 When you write new configuration files, please submit
1020 them for inclusion in the next OpenOCD release.
1021 For example, a @file{board/newboard.cfg} file will help the
1022 next users of that board, and a @file{target/newcpu.cfg}
1023 will help support users of any board using that chip.
1024 @end quotation
1025
1026 @item
1027 You may need to write some C code.
1028 It may be as simple as supporting a new FT2232 or parport
1029 based adapter; a bit more involved, like a NAND or NOR flash
1030 controller driver; or a big piece of work like supporting
1031 a new chip architecture.
1032 @end itemize
1033
1034 Reuse the existing config files when you can.
1035 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1036 You may find a board configuration that's a good example to follow.
1037
1038 When you write config files, separate the reusable parts
1039 (things every user of that interface, chip, or board needs)
1040 from ones specific to your environment and debugging approach.
1041 @itemize
1042
1043 @item
1044 For example, a @code{gdb-attach} event handler that invokes
1045 the @command{reset init} command will interfere with debugging
1046 early boot code, which performs some of the same actions
1047 that the @code{reset-init} event handler does.
1048
1049 @item
1050 Likewise, the @command{arm9 vector_catch} command (or
1051 @cindex vector_catch
1052 its siblings @command{xscale vector_catch}
1053 and @command{cortex_m vector_catch}) can be a time-saver
1054 during some debug sessions, but don't make everyone use that either.
1055 Keep those kinds of debugging aids in your user config file,
1056 along with messaging and tracing setup.
1057 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1058
1059 @item
1060 You might need to override some defaults.
1061 For example, you might need to move, shrink, or back up the target's
1062 work area if your application needs much SRAM.
1063
1064 @item
1065 TCP/IP port configuration is another example of something which
1066 is environment-specific, and should only appear in
1067 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1068 @end itemize
1069
1070 @section Project-Specific Utilities
1071
1072 A few project-specific utility
1073 routines may well speed up your work.
1074 Write them, and keep them in your project's user config file.
1075
1076 For example, if you are making a boot loader work on a
1077 board, it's nice to be able to debug the ``after it's
1078 loaded to RAM'' parts separately from the finicky early
1079 code which sets up the DDR RAM controller and clocks.
1080 A script like this one, or a more GDB-aware sibling,
1081 may help:
1082
1083 @example
1084 proc ramboot @{ @} @{
1085 # Reset, running the target's "reset-init" scripts
1086 # to initialize clocks and the DDR RAM controller.
1087 # Leave the CPU halted.
1088 reset init
1089
1090 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1091 load_image u-boot.bin 0x20000000
1092
1093 # Start running.
1094 resume 0x20000000
1095 @}
1096 @end example
1097
1098 Then once that code is working you will need to make it
1099 boot from NOR flash; a different utility would help.
1100 Alternatively, some developers write to flash using GDB.
1101 (You might use a similar script if you're working with a flash
1102 based microcontroller application instead of a boot loader.)
1103
1104 @example
1105 proc newboot @{ @} @{
1106 # Reset, leaving the CPU halted. The "reset-init" event
1107 # proc gives faster access to the CPU and to NOR flash;
1108 # "reset halt" would be slower.
1109 reset init
1110
1111 # Write standard version of U-Boot into the first two
1112 # sectors of NOR flash ... the standard version should
1113 # do the same lowlevel init as "reset-init".
1114 flash protect 0 0 1 off
1115 flash erase_sector 0 0 1
1116 flash write_bank 0 u-boot.bin 0x0
1117 flash protect 0 0 1 on
1118
1119 # Reboot from scratch using that new boot loader.
1120 reset run
1121 @}
1122 @end example
1123
1124 You may need more complicated utility procedures when booting
1125 from NAND.
1126 That often involves an extra bootloader stage,
1127 running from on-chip SRAM to perform DDR RAM setup so it can load
1128 the main bootloader code (which won't fit into that SRAM).
1129
1130 Other helper scripts might be used to write production system images,
1131 involving considerably more than just a three stage bootloader.
1132
1133 @section Target Software Changes
1134
1135 Sometimes you may want to make some small changes to the software
1136 you're developing, to help make JTAG debugging work better.
1137 For example, in C or assembly language code you might
1138 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1139 handling issues like:
1140
1141 @itemize @bullet
1142
1143 @item @b{Watchdog Timers}...
1144 Watchdog timers are typically used to automatically reset systems if
1145 some application task doesn't periodically reset the timer. (The
1146 assumption is that the system has locked up if the task can't run.)
1147 When a JTAG debugger halts the system, that task won't be able to run
1148 and reset the timer ... potentially causing resets in the middle of
1149 your debug sessions.
1150
1151 It's rarely a good idea to disable such watchdogs, since their usage
1152 needs to be debugged just like all other parts of your firmware.
1153 That might however be your only option.
1154
1155 Look instead for chip-specific ways to stop the watchdog from counting
1156 while the system is in a debug halt state. It may be simplest to set
1157 that non-counting mode in your debugger startup scripts. You may however
1158 need a different approach when, for example, a motor could be physically
1159 damaged by firmware remaining inactive in a debug halt state. That might
1160 involve a type of firmware mode where that "non-counting" mode is disabled
1161 at the beginning then re-enabled at the end; a watchdog reset might fire
1162 and complicate the debug session, but hardware (or people) would be
1163 protected.@footnote{Note that many systems support a "monitor mode" debug
1164 that is a somewhat cleaner way to address such issues. You can think of
1165 it as only halting part of the system, maybe just one task,
1166 instead of the whole thing.
1167 At this writing, January 2010, OpenOCD based debugging does not support
1168 monitor mode debug, only "halt mode" debug.}
1169
1170 @item @b{ARM Semihosting}...
1171 @cindex ARM semihosting
1172 When linked with a special runtime library provided with many
1173 toolchains@footnote{See chapter 8 "Semihosting" in
1174 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1175 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1176 The CodeSourcery EABI toolchain also includes a semihosting library.},
1177 your target code can use I/O facilities on the debug host. That library
1178 provides a small set of system calls which are handled by OpenOCD.
1179 It can let the debugger provide your system console and a file system,
1180 helping with early debugging or providing a more capable environment
1181 for sometimes-complex tasks like installing system firmware onto
1182 NAND or SPI flash.
1183
1184 @item @b{ARM Wait-For-Interrupt}...
1185 Many ARM chips synchronize the JTAG clock using the core clock.
1186 Low power states which stop that core clock thus prevent JTAG access.
1187 Idle loops in tasking environments often enter those low power states
1188 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1189
1190 You may want to @emph{disable that instruction} in source code,
1191 or otherwise prevent using that state,
1192 to ensure you can get JTAG access at any time.@footnote{As a more
1193 polite alternative, some processors have special debug-oriented
1194 registers which can be used to change various features including
1195 how the low power states are clocked while debugging.
1196 The STM32 DBGMCU_CR register is an example; at the cost of extra
1197 power consumption, JTAG can be used during low power states.}
1198 For example, the OpenOCD @command{halt} command may not
1199 work for an idle processor otherwise.
1200
1201 @item @b{Delay after reset}...
1202 Not all chips have good support for debugger access
1203 right after reset; many LPC2xxx chips have issues here.
1204 Similarly, applications that reconfigure pins used for
1205 JTAG access as they start will also block debugger access.
1206
1207 To work with boards like this, @emph{enable a short delay loop}
1208 the first thing after reset, before "real" startup activities.
1209 For example, one second's delay is usually more than enough
1210 time for a JTAG debugger to attach, so that
1211 early code execution can be debugged
1212 or firmware can be replaced.
1213
1214 @item @b{Debug Communications Channel (DCC)}...
1215 Some processors include mechanisms to send messages over JTAG.
1216 Many ARM cores support these, as do some cores from other vendors.
1217 (OpenOCD may be able to use this DCC internally, speeding up some
1218 operations like writing to memory.)
1219
1220 Your application may want to deliver various debugging messages
1221 over JTAG, by @emph{linking with a small library of code}
1222 provided with OpenOCD and using the utilities there to send
1223 various kinds of message.
1224 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1225
1226 @end itemize
1227
1228 @section Target Hardware Setup
1229
1230 Chip vendors often provide software development boards which
1231 are highly configurable, so that they can support all options
1232 that product boards may require. @emph{Make sure that any
1233 jumpers or switches match the system configuration you are
1234 working with.}
1235
1236 Common issues include:
1237
1238 @itemize @bullet
1239
1240 @item @b{JTAG setup} ...
1241 Boards may support more than one JTAG configuration.
1242 Examples include jumpers controlling pullups versus pulldowns
1243 on the nTRST and/or nSRST signals, and choice of connectors
1244 (e.g. which of two headers on the base board,
1245 or one from a daughtercard).
1246 For some Texas Instruments boards, you may need to jumper the
1247 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1248
1249 @item @b{Boot Modes} ...
1250 Complex chips often support multiple boot modes, controlled
1251 by external jumpers. Make sure this is set up correctly.
1252 For example many i.MX boards from NXP need to be jumpered
1253 to "ATX mode" to start booting using the on-chip ROM, when
1254 using second stage bootloader code stored in a NAND flash chip.
1255
1256 Such explicit configuration is common, and not limited to
1257 booting from NAND. You might also need to set jumpers to
1258 start booting using code loaded from an MMC/SD card; external
1259 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1260 flash; some external host; or various other sources.
1261
1262
1263 @item @b{Memory Addressing} ...
1264 Boards which support multiple boot modes may also have jumpers
1265 to configure memory addressing. One board, for example, jumpers
1266 external chipselect 0 (used for booting) to address either
1267 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1268 or NAND flash. When it's jumpered to address NAND flash, that
1269 board must also be told to start booting from on-chip ROM.
1270
1271 Your @file{board.cfg} file may also need to be told this jumper
1272 configuration, so that it can know whether to declare NOR flash
1273 using @command{flash bank} or instead declare NAND flash with
1274 @command{nand device}; and likewise which probe to perform in
1275 its @code{reset-init} handler.
1276
1277 A closely related issue is bus width. Jumpers might need to
1278 distinguish between 8 bit or 16 bit bus access for the flash
1279 used to start booting.
1280
1281 @item @b{Peripheral Access} ...
1282 Development boards generally provide access to every peripheral
1283 on the chip, sometimes in multiple modes (such as by providing
1284 multiple audio codec chips).
1285 This interacts with software
1286 configuration of pin multiplexing, where for example a
1287 given pin may be routed either to the MMC/SD controller
1288 or the GPIO controller. It also often interacts with
1289 configuration jumpers. One jumper may be used to route
1290 signals to an MMC/SD card slot or an expansion bus (which
1291 might in turn affect booting); others might control which
1292 audio or video codecs are used.
1293
1294 @end itemize
1295
1296 Plus you should of course have @code{reset-init} event handlers
1297 which set up the hardware to match that jumper configuration.
1298 That includes in particular any oscillator or PLL used to clock
1299 the CPU, and any memory controllers needed to access external
1300 memory and peripherals. Without such handlers, you won't be
1301 able to access those resources without working target firmware
1302 which can do that setup ... this can be awkward when you're
1303 trying to debug that target firmware. Even if there's a ROM
1304 bootloader which handles a few issues, it rarely provides full
1305 access to all board-specific capabilities.
1306
1307
1308 @node Config File Guidelines
1309 @chapter Config File Guidelines
1310
1311 This chapter is aimed at any user who needs to write a config file,
1312 including developers and integrators of OpenOCD and any user who
1313 needs to get a new board working smoothly.
1314 It provides guidelines for creating those files.
1315
1316 You should find the following directories under
1317 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1318 them as-is where you can; or as models for new files.
1319 @itemize @bullet
1320 @item @file{interface} ...
1321 These are for debug adapters. Files that specify configuration to use
1322 specific JTAG, SWD and other adapters go here.
1323 @item @file{board} ...
1324 Think Circuit Board, PWA, PCB, they go by many names. Board files
1325 contain initialization items that are specific to a board.
1326
1327 They reuse target configuration files, since the same
1328 microprocessor chips are used on many boards,
1329 but support for external parts varies widely. For
1330 example, the SDRAM initialization sequence for the board, or the type
1331 of external flash and what address it uses. Any initialization
1332 sequence to enable that external flash or SDRAM should be found in the
1333 board file. Boards may also contain multiple targets: two CPUs; or
1334 a CPU and an FPGA.
1335 @item @file{target} ...
1336 Think chip. The ``target'' directory represents the JTAG TAPs
1337 on a chip
1338 which OpenOCD should control, not a board. Two common types of targets
1339 are ARM chips and FPGA or CPLD chips.
1340 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1341 the target config file defines all of them.
1342 @item @emph{more} ... browse for other library files which may be useful.
1343 For example, there are various generic and CPU-specific utilities.
1344 @end itemize
1345
1346 The @file{openocd.cfg} user config
1347 file may override features in any of the above files by
1348 setting variables before sourcing the target file, or by adding
1349 commands specific to their situation.
1350
1351 @section Interface Config Files
1352
1353 The user config file
1354 should be able to source one of these files with a command like this:
1355
1356 @example
1357 source [find interface/FOOBAR.cfg]
1358 @end example
1359
1360 A preconfigured interface file should exist for every debug adapter
1361 in use today with OpenOCD.
1362 That said, perhaps some of these config files
1363 have only been used by the developer who created it.
1364
1365 A separate chapter gives information about how to set these up.
1366 @xref{Debug Adapter Configuration}.
1367 Read the OpenOCD source code (and Developer's Guide)
1368 if you have a new kind of hardware interface
1369 and need to provide a driver for it.
1370
1371 @deffn {Command} {find} 'filename'
1372 Prints full path to @var{filename} according to OpenOCD search rules.
1373 @end deffn
1374
1375 @deffn {Command} {ocd_find} 'filename'
1376 Prints full path to @var{filename} according to OpenOCD search rules. This
1377 is a low level function used by the @command{find}. Usually you want
1378 to use @command{find}, instead.
1379 @end deffn
1380
1381 @section Board Config Files
1382 @cindex config file, board
1383 @cindex board config file
1384
1385 The user config file
1386 should be able to source one of these files with a command like this:
1387
1388 @example
1389 source [find board/FOOBAR.cfg]
1390 @end example
1391
1392 The point of a board config file is to package everything
1393 about a given board that user config files need to know.
1394 In summary the board files should contain (if present)
1395
1396 @enumerate
1397 @item One or more @command{source [find target/...cfg]} statements
1398 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1399 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1400 @item Target @code{reset} handlers for SDRAM and I/O configuration
1401 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1402 @item All things that are not ``inside a chip''
1403 @end enumerate
1404
1405 Generic things inside target chips belong in target config files,
1406 not board config files. So for example a @code{reset-init} event
1407 handler should know board-specific oscillator and PLL parameters,
1408 which it passes to target-specific utility code.
1409
1410 The most complex task of a board config file is creating such a
1411 @code{reset-init} event handler.
1412 Define those handlers last, after you verify the rest of the board
1413 configuration works.
1414
1415 @subsection Communication Between Config files
1416
1417 In addition to target-specific utility code, another way that
1418 board and target config files communicate is by following a
1419 convention on how to use certain variables.
1420
1421 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1422 Thus the rule we follow in OpenOCD is this: Variables that begin with
1423 a leading underscore are temporary in nature, and can be modified and
1424 used at will within a target configuration file.
1425
1426 Complex board config files can do the things like this,
1427 for a board with three chips:
1428
1429 @example
1430 # Chip #1: PXA270 for network side, big endian
1431 set CHIPNAME network
1432 set ENDIAN big
1433 source [find target/pxa270.cfg]
1434 # on return: _TARGETNAME = network.cpu
1435 # other commands can refer to the "network.cpu" target.
1436 $_TARGETNAME configure .... events for this CPU..
1437
1438 # Chip #2: PXA270 for video side, little endian
1439 set CHIPNAME video
1440 set ENDIAN little
1441 source [find target/pxa270.cfg]
1442 # on return: _TARGETNAME = video.cpu
1443 # other commands can refer to the "video.cpu" target.
1444 $_TARGETNAME configure .... events for this CPU..
1445
1446 # Chip #3: Xilinx FPGA for glue logic
1447 set CHIPNAME xilinx
1448 unset ENDIAN
1449 source [find target/spartan3.cfg]
1450 @end example
1451
1452 That example is oversimplified because it doesn't show any flash memory,
1453 or the @code{reset-init} event handlers to initialize external DRAM
1454 or (assuming it needs it) load a configuration into the FPGA.
1455 Such features are usually needed for low-level work with many boards,
1456 where ``low level'' implies that the board initialization software may
1457 not be working. (That's a common reason to need JTAG tools. Another
1458 is to enable working with microcontroller-based systems, which often
1459 have no debugging support except a JTAG connector.)
1460
1461 Target config files may also export utility functions to board and user
1462 config files. Such functions should use name prefixes, to help avoid
1463 naming collisions.
1464
1465 Board files could also accept input variables from user config files.
1466 For example, there might be a @code{J4_JUMPER} setting used to identify
1467 what kind of flash memory a development board is using, or how to set
1468 up other clocks and peripherals.
1469
1470 @subsection Variable Naming Convention
1471 @cindex variable names
1472
1473 Most boards have only one instance of a chip.
1474 However, it should be easy to create a board with more than
1475 one such chip (as shown above).
1476 Accordingly, we encourage these conventions for naming
1477 variables associated with different @file{target.cfg} files,
1478 to promote consistency and
1479 so that board files can override target defaults.
1480
1481 Inputs to target config files include:
1482
1483 @itemize @bullet
1484 @item @code{CHIPNAME} ...
1485 This gives a name to the overall chip, and is used as part of
1486 tap identifier dotted names.
1487 While the default is normally provided by the chip manufacturer,
1488 board files may need to distinguish between instances of a chip.
1489 @item @code{ENDIAN} ...
1490 By default @option{little} - although chips may hard-wire @option{big}.
1491 Chips that can't change endianness don't need to use this variable.
1492 @item @code{CPUTAPID} ...
1493 When OpenOCD examines the JTAG chain, it can be told verify the
1494 chips against the JTAG IDCODE register.
1495 The target file will hold one or more defaults, but sometimes the
1496 chip in a board will use a different ID (perhaps a newer revision).
1497 @end itemize
1498
1499 Outputs from target config files include:
1500
1501 @itemize @bullet
1502 @item @code{_TARGETNAME} ...
1503 By convention, this variable is created by the target configuration
1504 script. The board configuration file may make use of this variable to
1505 configure things like a ``reset init'' script, or other things
1506 specific to that board and that target.
1507 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1508 @code{_TARGETNAME1}, ... etc.
1509 @end itemize
1510
1511 @subsection The reset-init Event Handler
1512 @cindex event, reset-init
1513 @cindex reset-init handler
1514
1515 Board config files run in the OpenOCD configuration stage;
1516 they can't use TAPs or targets, since they haven't been
1517 fully set up yet.
1518 This means you can't write memory or access chip registers;
1519 you can't even verify that a flash chip is present.
1520 That's done later in event handlers, of which the target @code{reset-init}
1521 handler is one of the most important.
1522
1523 Except on microcontrollers, the basic job of @code{reset-init} event
1524 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1525 Microcontrollers rarely use boot loaders; they run right out of their
1526 on-chip flash and SRAM memory. But they may want to use one of these
1527 handlers too, if just for developer convenience.
1528
1529 @quotation Note
1530 Because this is so very board-specific, and chip-specific, no examples
1531 are included here.
1532 Instead, look at the board config files distributed with OpenOCD.
1533 If you have a boot loader, its source code will help; so will
1534 configuration files for other JTAG tools
1535 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1536 @end quotation
1537
1538 Some of this code could probably be shared between different boards.
1539 For example, setting up a DRAM controller often doesn't differ by
1540 much except the bus width (16 bits or 32?) and memory timings, so a
1541 reusable TCL procedure loaded by the @file{target.cfg} file might take
1542 those as parameters.
1543 Similarly with oscillator, PLL, and clock setup;
1544 and disabling the watchdog.
1545 Structure the code cleanly, and provide comments to help
1546 the next developer doing such work.
1547 (@emph{You might be that next person} trying to reuse init code!)
1548
1549 The last thing normally done in a @code{reset-init} handler is probing
1550 whatever flash memory was configured. For most chips that needs to be
1551 done while the associated target is halted, either because JTAG memory
1552 access uses the CPU or to prevent conflicting CPU access.
1553
1554 @subsection JTAG Clock Rate
1555
1556 Before your @code{reset-init} handler has set up
1557 the PLLs and clocking, you may need to run with
1558 a low JTAG clock rate.
1559 @xref{jtagspeed,,JTAG Speed}.
1560 Then you'd increase that rate after your handler has
1561 made it possible to use the faster JTAG clock.
1562 When the initial low speed is board-specific, for example
1563 because it depends on a board-specific oscillator speed, then
1564 you should probably set it up in the board config file;
1565 if it's target-specific, it belongs in the target config file.
1566
1567 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1568 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1569 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1570 Consult chip documentation to determine the peak JTAG clock rate,
1571 which might be less than that.
1572
1573 @quotation Warning
1574 On most ARMs, JTAG clock detection is coupled to the core clock, so
1575 software using a @option{wait for interrupt} operation blocks JTAG access.
1576 Adaptive clocking provides a partial workaround, but a more complete
1577 solution just avoids using that instruction with JTAG debuggers.
1578 @end quotation
1579
1580 If both the chip and the board support adaptive clocking,
1581 use the @command{jtag_rclk}
1582 command, in case your board is used with JTAG adapter which
1583 also supports it. Otherwise use @command{adapter speed}.
1584 Set the slow rate at the beginning of the reset sequence,
1585 and the faster rate as soon as the clocks are at full speed.
1586
1587 @anchor{theinitboardprocedure}
1588 @subsection The init_board procedure
1589 @cindex init_board procedure
1590
1591 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1592 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1593 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1594 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1595 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1596 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1597 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1598 Additionally ``linear'' board config file will most likely fail when target config file uses
1599 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1600 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1601 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1602 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1603
1604 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1605 the original), allowing greater code reuse.
1606
1607 @example
1608 ### board_file.cfg ###
1609
1610 # source target file that does most of the config in init_targets
1611 source [find target/target.cfg]
1612
1613 proc enable_fast_clock @{@} @{
1614 # enables fast on-board clock source
1615 # configures the chip to use it
1616 @}
1617
1618 # initialize only board specifics - reset, clock, adapter frequency
1619 proc init_board @{@} @{
1620 reset_config trst_and_srst trst_pulls_srst
1621
1622 $_TARGETNAME configure -event reset-start @{
1623 adapter speed 100
1624 @}
1625
1626 $_TARGETNAME configure -event reset-init @{
1627 enable_fast_clock
1628 adapter speed 10000
1629 @}
1630 @}
1631 @end example
1632
1633 @section Target Config Files
1634 @cindex config file, target
1635 @cindex target config file
1636
1637 Board config files communicate with target config files using
1638 naming conventions as described above, and may source one or
1639 more target config files like this:
1640
1641 @example
1642 source [find target/FOOBAR.cfg]
1643 @end example
1644
1645 The point of a target config file is to package everything
1646 about a given chip that board config files need to know.
1647 In summary the target files should contain
1648
1649 @enumerate
1650 @item Set defaults
1651 @item Add TAPs to the scan chain
1652 @item Add CPU targets (includes GDB support)
1653 @item CPU/Chip/CPU-Core specific features
1654 @item On-Chip flash
1655 @end enumerate
1656
1657 As a rule of thumb, a target file sets up only one chip.
1658 For a microcontroller, that will often include a single TAP,
1659 which is a CPU needing a GDB target, and its on-chip flash.
1660
1661 More complex chips may include multiple TAPs, and the target
1662 config file may need to define them all before OpenOCD
1663 can talk to the chip.
1664 For example, some phone chips have JTAG scan chains that include
1665 an ARM core for operating system use, a DSP,
1666 another ARM core embedded in an image processing engine,
1667 and other processing engines.
1668
1669 @subsection Default Value Boiler Plate Code
1670
1671 All target configuration files should start with code like this,
1672 letting board config files express environment-specific
1673 differences in how things should be set up.
1674
1675 @example
1676 # Boards may override chip names, perhaps based on role,
1677 # but the default should match what the vendor uses
1678 if @{ [info exists CHIPNAME] @} @{
1679 set _CHIPNAME $CHIPNAME
1680 @} else @{
1681 set _CHIPNAME sam7x256
1682 @}
1683
1684 # ONLY use ENDIAN with targets that can change it.
1685 if @{ [info exists ENDIAN] @} @{
1686 set _ENDIAN $ENDIAN
1687 @} else @{
1688 set _ENDIAN little
1689 @}
1690
1691 # TAP identifiers may change as chips mature, for example with
1692 # new revision fields (the "3" here). Pick a good default; you
1693 # can pass several such identifiers to the "jtag newtap" command.
1694 if @{ [info exists CPUTAPID ] @} @{
1695 set _CPUTAPID $CPUTAPID
1696 @} else @{
1697 set _CPUTAPID 0x3f0f0f0f
1698 @}
1699 @end example
1700 @c but 0x3f0f0f0f is for an str73x part ...
1701
1702 @emph{Remember:} Board config files may include multiple target
1703 config files, or the same target file multiple times
1704 (changing at least @code{CHIPNAME}).
1705
1706 Likewise, the target configuration file should define
1707 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1708 use it later on when defining debug targets:
1709
1710 @example
1711 set _TARGETNAME $_CHIPNAME.cpu
1712 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1713 @end example
1714
1715 @subsection Adding TAPs to the Scan Chain
1716 After the ``defaults'' are set up,
1717 add the TAPs on each chip to the JTAG scan chain.
1718 @xref{TAP Declaration}, and the naming convention
1719 for taps.
1720
1721 In the simplest case the chip has only one TAP,
1722 probably for a CPU or FPGA.
1723 The config file for the Atmel AT91SAM7X256
1724 looks (in part) like this:
1725
1726 @example
1727 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1728 @end example
1729
1730 A board with two such at91sam7 chips would be able
1731 to source such a config file twice, with different
1732 values for @code{CHIPNAME}, so
1733 it adds a different TAP each time.
1734
1735 If there are nonzero @option{-expected-id} values,
1736 OpenOCD attempts to verify the actual tap id against those values.
1737 It will issue error messages if there is mismatch, which
1738 can help to pinpoint problems in OpenOCD configurations.
1739
1740 @example
1741 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1742 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1743 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1744 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1745 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1746 @end example
1747
1748 There are more complex examples too, with chips that have
1749 multiple TAPs. Ones worth looking at include:
1750
1751 @itemize
1752 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1753 plus a JRC to enable them
1754 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1755 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1756 is not currently used)
1757 @end itemize
1758
1759 @subsection Add CPU targets
1760
1761 After adding a TAP for a CPU, you should set it up so that
1762 GDB and other commands can use it.
1763 @xref{CPU Configuration}.
1764 For the at91sam7 example above, the command can look like this;
1765 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1766 to little endian, and this chip doesn't support changing that.
1767
1768 @example
1769 set _TARGETNAME $_CHIPNAME.cpu
1770 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1771 @end example
1772
1773 Work areas are small RAM areas associated with CPU targets.
1774 They are used by OpenOCD to speed up downloads,
1775 and to download small snippets of code to program flash chips.
1776 If the chip includes a form of ``on-chip-ram'' - and many do - define
1777 a work area if you can.
1778 Again using the at91sam7 as an example, this can look like:
1779
1780 @example
1781 $_TARGETNAME configure -work-area-phys 0x00200000 \
1782 -work-area-size 0x4000 -work-area-backup 0
1783 @end example
1784
1785 @anchor{definecputargetsworkinginsmp}
1786 @subsection Define CPU targets working in SMP
1787 @cindex SMP
1788 After setting targets, you can define a list of targets working in SMP.
1789
1790 @example
1791 set _TARGETNAME_1 $_CHIPNAME.cpu1
1792 set _TARGETNAME_2 $_CHIPNAME.cpu2
1793 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1794 -coreid 0 -dbgbase $_DAP_DBG1
1795 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1796 -coreid 1 -dbgbase $_DAP_DBG2
1797 #define 2 targets working in smp.
1798 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1799 @end example
1800 In the above example on cortex_a, 2 cpus are working in SMP.
1801 In SMP only one GDB instance is created and :
1802 @itemize @bullet
1803 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1804 @item halt command triggers the halt of all targets in the list.
1805 @item resume command triggers the write context and the restart of all targets in the list.
1806 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1807 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1808 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1809 @end itemize
1810
1811 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1812 command have been implemented.
1813 @itemize @bullet
1814 @item cortex_a smp on : enable SMP mode, behaviour is as described above.
1815 @item cortex_a smp off : disable SMP mode, the current target is the one
1816 displayed in the GDB session, only this target is now controlled by GDB
1817 session. This behaviour is useful during system boot up.
1818 @item cortex_a smp : display current SMP mode.
1819 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1820 following example.
1821 @end itemize
1822
1823 @example
1824 >cortex_a smp_gdb
1825 gdb coreid 0 -> -1
1826 #0 : coreid 0 is displayed to GDB ,
1827 #-> -1 : next resume triggers a real resume
1828 > cortex_a smp_gdb 1
1829 gdb coreid 0 -> 1
1830 #0 :coreid 0 is displayed to GDB ,
1831 #->1 : next resume displays coreid 1 to GDB
1832 > resume
1833 > cortex_a smp_gdb
1834 gdb coreid 1 -> 1
1835 #1 :coreid 1 is displayed to GDB ,
1836 #->1 : next resume displays coreid 1 to GDB
1837 > cortex_a smp_gdb -1
1838 gdb coreid 1 -> -1
1839 #1 :coreid 1 is displayed to GDB,
1840 #->-1 : next resume triggers a real resume
1841 @end example
1842
1843
1844 @subsection Chip Reset Setup
1845
1846 As a rule, you should put the @command{reset_config} command
1847 into the board file. Most things you think you know about a
1848 chip can be tweaked by the board.
1849
1850 Some chips have specific ways the TRST and SRST signals are
1851 managed. In the unusual case that these are @emph{chip specific}
1852 and can never be changed by board wiring, they could go here.
1853 For example, some chips can't support JTAG debugging without
1854 both signals.
1855
1856 Provide a @code{reset-assert} event handler if you can.
1857 Such a handler uses JTAG operations to reset the target,
1858 letting this target config be used in systems which don't
1859 provide the optional SRST signal, or on systems where you
1860 don't want to reset all targets at once.
1861 Such a handler might write to chip registers to force a reset,
1862 use a JRC to do that (preferable -- the target may be wedged!),
1863 or force a watchdog timer to trigger.
1864 (For Cortex-M targets, this is not necessary. The target
1865 driver knows how to use trigger an NVIC reset when SRST is
1866 not available.)
1867
1868 Some chips need special attention during reset handling if
1869 they're going to be used with JTAG.
1870 An example might be needing to send some commands right
1871 after the target's TAP has been reset, providing a
1872 @code{reset-deassert-post} event handler that writes a chip
1873 register to report that JTAG debugging is being done.
1874 Another would be reconfiguring the watchdog so that it stops
1875 counting while the core is halted in the debugger.
1876
1877 JTAG clocking constraints often change during reset, and in
1878 some cases target config files (rather than board config files)
1879 are the right places to handle some of those issues.
1880 For example, immediately after reset most chips run using a
1881 slower clock than they will use later.
1882 That means that after reset (and potentially, as OpenOCD
1883 first starts up) they must use a slower JTAG clock rate
1884 than they will use later.
1885 @xref{jtagspeed,,JTAG Speed}.
1886
1887 @quotation Important
1888 When you are debugging code that runs right after chip
1889 reset, getting these issues right is critical.
1890 In particular, if you see intermittent failures when
1891 OpenOCD verifies the scan chain after reset,
1892 look at how you are setting up JTAG clocking.
1893 @end quotation
1894
1895 @anchor{theinittargetsprocedure}
1896 @subsection The init_targets procedure
1897 @cindex init_targets procedure
1898
1899 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1900 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1901 procedure called @code{init_targets}, which will be executed when entering run stage
1902 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1903 Such procedure can be overridden by ``next level'' script (which sources the original).
1904 This concept facilitates code reuse when basic target config files provide generic configuration
1905 procedures and @code{init_targets} procedure, which can then be sourced and enhanced or changed in
1906 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1907 because sourcing them executes every initialization commands they provide.
1908
1909 @example
1910 ### generic_file.cfg ###
1911
1912 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1913 # basic initialization procedure ...
1914 @}
1915
1916 proc init_targets @{@} @{
1917 # initializes generic chip with 4kB of flash and 1kB of RAM
1918 setup_my_chip MY_GENERIC_CHIP 4096 1024
1919 @}
1920
1921 ### specific_file.cfg ###
1922
1923 source [find target/generic_file.cfg]
1924
1925 proc init_targets @{@} @{
1926 # initializes specific chip with 128kB of flash and 64kB of RAM
1927 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1928 @}
1929 @end example
1930
1931 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1932 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1933
1934 For an example of this scheme see LPC2000 target config files.
1935
1936 The @code{init_boards} procedure is a similar concept concerning board config files
1937 (@xref{theinitboardprocedure,,The init_board procedure}.)
1938
1939 @anchor{theinittargeteventsprocedure}
1940 @subsection The init_target_events procedure
1941 @cindex init_target_events procedure
1942
1943 A special procedure called @code{init_target_events} is run just after
1944 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1945 procedure}.) and before @code{init_board}
1946 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1947 to set up default target events for the targets that do not have those
1948 events already assigned.
1949
1950 @subsection ARM Core Specific Hacks
1951
1952 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1953 special high speed download features - enable it.
1954
1955 If present, the MMU, the MPU and the CACHE should be disabled.
1956
1957 Some ARM cores are equipped with trace support, which permits
1958 examination of the instruction and data bus activity. Trace
1959 activity is controlled through an ``Embedded Trace Module'' (ETM)
1960 on one of the core's scan chains. The ETM emits voluminous data
1961 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1962 If you are using an external trace port,
1963 configure it in your board config file.
1964 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1965 configure it in your target config file.
1966
1967 @example
1968 etm config $_TARGETNAME 16 normal full etb
1969 etb config $_TARGETNAME $_CHIPNAME.etb
1970 @end example
1971
1972 @subsection Internal Flash Configuration
1973
1974 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1975
1976 @b{Never ever} in the ``target configuration file'' define any type of
1977 flash that is external to the chip. (For example a BOOT flash on
1978 Chip Select 0.) Such flash information goes in a board file - not
1979 the TARGET (chip) file.
1980
1981 Examples:
1982 @itemize @bullet
1983 @item at91sam7x256 - has 256K flash YES enable it.
1984 @item str912 - has flash internal YES enable it.
1985 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1986 @item pxa270 - again - CS0 flash - it goes in the board file.
1987 @end itemize
1988
1989 @anchor{translatingconfigurationfiles}
1990 @section Translating Configuration Files
1991 @cindex translation
1992 If you have a configuration file for another hardware debugger
1993 or toolset (Abatron, BDI2000, BDI3000, CCS,
1994 Lauterbach, SEGGER, Macraigor, etc.), translating
1995 it into OpenOCD syntax is often quite straightforward. The most tricky
1996 part of creating a configuration script is oftentimes the reset init
1997 sequence where e.g. PLLs, DRAM and the like is set up.
1998
1999 One trick that you can use when translating is to write small
2000 Tcl procedures to translate the syntax into OpenOCD syntax. This
2001 can avoid manual translation errors and make it easier to
2002 convert other scripts later on.
2003
2004 Example of transforming quirky arguments to a simple search and
2005 replace job:
2006
2007 @example
2008 # Lauterbach syntax(?)
2009 #
2010 # Data.Set c15:0x042f %long 0x40000015
2011 #
2012 # OpenOCD syntax when using procedure below.
2013 #
2014 # setc15 0x01 0x00050078
2015
2016 proc setc15 @{regs value@} @{
2017 global TARGETNAME
2018
2019 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2020
2021 arm mcr 15 [expr @{($regs >> 12) & 0x7@}] \
2022 [expr @{($regs >> 0) & 0xf@}] [expr @{($regs >> 4) & 0xf@}] \
2023 [expr @{($regs >> 8) & 0x7@}] $value
2024 @}
2025 @end example
2026
2027
2028
2029 @node Server Configuration
2030 @chapter Server Configuration
2031 @cindex initialization
2032 The commands here are commonly found in the openocd.cfg file and are
2033 used to specify what TCP/IP ports are used, and how GDB should be
2034 supported.
2035
2036 @anchor{configurationstage}
2037 @section Configuration Stage
2038 @cindex configuration stage
2039 @cindex config command
2040
2041 When the OpenOCD server process starts up, it enters a
2042 @emph{configuration stage} which is the only time that
2043 certain commands, @emph{configuration commands}, may be issued.
2044 Normally, configuration commands are only available
2045 inside startup scripts.
2046
2047 In this manual, the definition of a configuration command is
2048 presented as a @emph{Config Command}, not as a @emph{Command}
2049 which may be issued interactively.
2050 The runtime @command{help} command also highlights configuration
2051 commands, and those which may be issued at any time.
2052
2053 Those configuration commands include declaration of TAPs,
2054 flash banks,
2055 the interface used for JTAG communication,
2056 and other basic setup.
2057 The server must leave the configuration stage before it
2058 may access or activate TAPs.
2059 After it leaves this stage, configuration commands may no
2060 longer be issued.
2061
2062 @deffn {Command} {command mode} [command_name]
2063 Returns the command modes allowed by a command: 'any', 'config', or
2064 'exec'. If no command is specified, returns the current command
2065 mode. Returns 'unknown' if an unknown command is given. Command can be
2066 multiple tokens. (command valid any time)
2067
2068 In this document, the modes are described as stages, 'config' and
2069 'exec' mode correspond configuration stage and run stage. 'any' means
2070 the command can be executed in either
2071 stages. @xref{configurationstage,,Configuration Stage}, and
2072 @xref{enteringtherunstage,,Entering the Run Stage}.
2073 @end deffn
2074
2075 @anchor{enteringtherunstage}
2076 @section Entering the Run Stage
2077
2078 The first thing OpenOCD does after leaving the configuration
2079 stage is to verify that it can talk to the scan chain
2080 (list of TAPs) which has been configured.
2081 It will warn if it doesn't find TAPs it expects to find,
2082 or finds TAPs that aren't supposed to be there.
2083 You should see no errors at this point.
2084 If you see errors, resolve them by correcting the
2085 commands you used to configure the server.
2086 Common errors include using an initial JTAG speed that's too
2087 fast, and not providing the right IDCODE values for the TAPs
2088 on the scan chain.
2089
2090 Once OpenOCD has entered the run stage, a number of commands
2091 become available.
2092 A number of these relate to the debug targets you may have declared.
2093 For example, the @command{mww} command will not be available until
2094 a target has been successfully instantiated.
2095 If you want to use those commands, you may need to force
2096 entry to the run stage.
2097
2098 @deffn {Config Command} {init}
2099 This command terminates the configuration stage and
2100 enters the run stage. This helps when you need to have
2101 the startup scripts manage tasks such as resetting the target,
2102 programming flash, etc. To reset the CPU upon startup, add "init" and
2103 "reset" at the end of the config script or at the end of the OpenOCD
2104 command line using the @option{-c} command line switch.
2105
2106 If this command does not appear in any startup/configuration file
2107 OpenOCD executes the command for you after processing all
2108 configuration files and/or command line options.
2109
2110 @b{NOTE:} This command normally occurs near the end of your
2111 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2112 targets ready. For example: If your openocd.cfg file needs to
2113 read/write memory on your target, @command{init} must occur before
2114 the memory read/write commands. This includes @command{nand probe}.
2115
2116 @command{init} calls the following internal OpenOCD commands to initialize
2117 corresponding subsystems:
2118 @deffn {Config Command} {target init}
2119 @deffnx {Command} {transport init}
2120 @deffnx {Command} {dap init}
2121 @deffnx {Config Command} {flash init}
2122 @deffnx {Config Command} {nand init}
2123 @deffnx {Config Command} {pld init}
2124 @deffnx {Command} {tpiu init}
2125 @end deffn
2126
2127 At last, @command{init} executes all the commands that are specified in
2128 the TCL list @var{post_init_commands}. The commands are executed in the
2129 same order they occupy in the list. If one of the commands fails, then
2130 the error is propagated and OpenOCD fails too.
2131 @example
2132 lappend post_init_commands @{echo "OpenOCD successfully initialized."@}
2133 lappend post_init_commands @{echo "Have fun with OpenOCD !"@}
2134 @end example
2135 @end deffn
2136
2137 @deffn {Config Command} {noinit}
2138 Prevent OpenOCD from implicit @command{init} call at the end of startup.
2139 Allows issuing configuration commands over telnet or Tcl connection.
2140 When you are done with configuration use @command{init} to enter
2141 the run stage.
2142 @end deffn
2143
2144 @deffn {Overridable Procedure} {jtag_init}
2145 This is invoked at server startup to verify that it can talk
2146 to the scan chain (list of TAPs) which has been configured.
2147
2148 The default implementation first tries @command{jtag arp_init},
2149 which uses only a lightweight JTAG reset before examining the
2150 scan chain.
2151 If that fails, it tries again, using a harder reset
2152 from the overridable procedure @command{init_reset}.
2153
2154 Implementations must have verified the JTAG scan chain before
2155 they return.
2156 This is done by calling @command{jtag arp_init}
2157 (or @command{jtag arp_init-reset}).
2158 @end deffn
2159
2160 @anchor{tcpipports}
2161 @section TCP/IP Ports
2162 @cindex TCP port
2163 @cindex server
2164 @cindex port
2165 @cindex security
2166 The OpenOCD server accepts remote commands in several syntaxes.
2167 Each syntax uses a different TCP/IP port, which you may specify
2168 only during configuration (before those ports are opened).
2169
2170 For reasons including security, you may wish to prevent remote
2171 access using one or more of these ports.
2172 In such cases, just specify the relevant port number as "disabled".
2173 If you disable all access through TCP/IP, you will need to
2174 use the command line @option{-pipe} option.
2175
2176 @anchor{gdb_port}
2177 @deffn {Config Command} {gdb_port} [number]
2178 @cindex GDB server
2179 Normally gdb listens to a TCP/IP port, but GDB can also
2180 communicate via pipes(stdin/out or named pipes). The name
2181 "gdb_port" stuck because it covers probably more than 90% of
2182 the normal use cases.
2183
2184 No arguments reports GDB port. "pipe" means listen to stdin
2185 output to stdout, an integer is base port number, "disabled"
2186 disables the gdb server.
2187
2188 When using "pipe", also use log_output to redirect the log
2189 output to a file so as not to flood the stdin/out pipes.
2190
2191 Any other string is interpreted as named pipe to listen to.
2192 Output pipe is the same name as input pipe, but with 'o' appended,
2193 e.g. /var/gdb, /var/gdbo.
2194
2195 The GDB port for the first target will be the base port, the
2196 second target will listen on gdb_port + 1, and so on.
2197 When not specified during the configuration stage,
2198 the port @var{number} defaults to 3333.
2199 When @var{number} is not a numeric value, incrementing it to compute
2200 the next port number does not work. In this case, specify the proper
2201 @var{number} for each target by using the option @code{-gdb-port} of the
2202 commands @command{target create} or @command{$target_name configure}.
2203 @xref{gdbportoverride,,option -gdb-port}.
2204
2205 Note: when using "gdb_port pipe", increasing the default remote timeout in
2206 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2207 cause initialization to fail with "Unknown remote qXfer reply: OK".
2208 @end deffn
2209
2210 @deffn {Config Command} {tcl_port} [number]
2211 Specify or query the port used for a simplified RPC
2212 connection that can be used by clients to issue TCL commands and get the
2213 output from the Tcl engine.
2214 Intended as a machine interface.
2215 When not specified during the configuration stage,
2216 the port @var{number} defaults to 6666.
2217 When specified as "disabled", this service is not activated.
2218 @end deffn
2219
2220 @deffn {Config Command} {telnet_port} [number]
2221 Specify or query the
2222 port on which to listen for incoming telnet connections.
2223 This port is intended for interaction with one human through TCL commands.
2224 When not specified during the configuration stage,
2225 the port @var{number} defaults to 4444.
2226 When specified as "disabled", this service is not activated.
2227 @end deffn
2228
2229 @anchor{gdbconfiguration}
2230 @section GDB Configuration
2231 @cindex GDB
2232 @cindex GDB configuration
2233 You can reconfigure some GDB behaviors if needed.
2234 The ones listed here are static and global.
2235 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2236 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2237
2238 @anchor{gdbbreakpointoverride}
2239 @deffn {Command} {gdb_breakpoint_override} [@option{hard}|@option{soft}|@option{disable}]
2240 Force breakpoint type for gdb @command{break} commands.
2241 This option supports GDB GUIs which don't
2242 distinguish hard versus soft breakpoints, if the default OpenOCD and
2243 GDB behaviour is not sufficient. GDB normally uses hardware
2244 breakpoints if the memory map has been set up for flash regions.
2245 @end deffn
2246
2247 @anchor{gdbflashprogram}
2248 @deffn {Config Command} {gdb_flash_program} (@option{enable}|@option{disable})
2249 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2250 vFlash packet is received.
2251 The default behaviour is @option{enable}.
2252 @end deffn
2253
2254 @deffn {Config Command} {gdb_memory_map} (@option{enable}|@option{disable})
2255 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2256 requested. GDB will then know when to set hardware breakpoints, and program flash
2257 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2258 for flash programming to work.
2259 Default behaviour is @option{enable}.
2260 @xref{gdbflashprogram,,gdb_flash_program}.
2261 @end deffn
2262
2263 @deffn {Config Command} {gdb_report_data_abort} (@option{enable}|@option{disable})
2264 Specifies whether data aborts cause an error to be reported
2265 by GDB memory read packets.
2266 The default behaviour is @option{disable};
2267 use @option{enable} see these errors reported.
2268 @end deffn
2269
2270 @deffn {Config Command} {gdb_report_register_access_error} (@option{enable}|@option{disable})
2271 Specifies whether register accesses requested by GDB register read/write
2272 packets report errors or not.
2273 The default behaviour is @option{disable};
2274 use @option{enable} see these errors reported.
2275 @end deffn
2276
2277 @deffn {Config Command} {gdb_target_description} (@option{enable}|@option{disable})
2278 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2279 The default behaviour is @option{enable}.
2280 @end deffn
2281
2282 @deffn {Command} {gdb_save_tdesc}
2283 Saves the target description file to the local file system.
2284
2285 The file name is @i{target_name}.xml.
2286 @end deffn
2287
2288 @anchor{eventpolling}
2289 @section Event Polling
2290
2291 Hardware debuggers are parts of asynchronous systems,
2292 where significant events can happen at any time.
2293 The OpenOCD server needs to detect some of these events,
2294 so it can report them to through TCL command line
2295 or to GDB.
2296
2297 Examples of such events include:
2298
2299 @itemize
2300 @item One of the targets can stop running ... maybe it triggers
2301 a code breakpoint or data watchpoint, or halts itself.
2302 @item Messages may be sent over ``debug message'' channels ... many
2303 targets support such messages sent over JTAG,
2304 for receipt by the person debugging or tools.
2305 @item Loss of power ... some adapters can detect these events.
2306 @item Resets not issued through JTAG ... such reset sources
2307 can include button presses or other system hardware, sometimes
2308 including the target itself (perhaps through a watchdog).
2309 @item Debug instrumentation sometimes supports event triggering
2310 such as ``trace buffer full'' (so it can quickly be emptied)
2311 or other signals (to correlate with code behavior).
2312 @end itemize
2313
2314 None of those events are signaled through standard JTAG signals.
2315 However, most conventions for JTAG connectors include voltage
2316 level and system reset (SRST) signal detection.
2317 Some connectors also include instrumentation signals, which
2318 can imply events when those signals are inputs.
2319
2320 In general, OpenOCD needs to periodically check for those events,
2321 either by looking at the status of signals on the JTAG connector
2322 or by sending synchronous ``tell me your status'' JTAG requests
2323 to the various active targets.
2324 There is a command to manage and monitor that polling,
2325 which is normally done in the background.
2326
2327 @deffn {Command} {poll} [@option{on}|@option{off}]
2328 Poll the current target for its current state.
2329 (Also, @pxref{targetcurstate,,target curstate}.)
2330 If that target is in debug mode, architecture
2331 specific information about the current state is printed.
2332 An optional parameter
2333 allows background polling to be enabled and disabled.
2334
2335 You could use this from the TCL command shell, or
2336 from GDB using @command{monitor poll} command.
2337 Leave background polling enabled while you're using GDB.
2338 @example
2339 > poll
2340 background polling: on
2341 target state: halted
2342 target halted in ARM state due to debug-request, \
2343 current mode: Supervisor
2344 cpsr: 0x800000d3 pc: 0x11081bfc
2345 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2346 >
2347 @end example
2348 @end deffn
2349
2350 @node Debug Adapter Configuration
2351 @chapter Debug Adapter Configuration
2352 @cindex config file, interface
2353 @cindex interface config file
2354
2355 Correctly installing OpenOCD includes making your operating system give
2356 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2357 are used to select which one is used, and to configure how it is used.
2358
2359 @quotation Note
2360 Because OpenOCD started out with a focus purely on JTAG, you may find
2361 places where it wrongly presumes JTAG is the only transport protocol
2362 in use. Be aware that recent versions of OpenOCD are removing that
2363 limitation. JTAG remains more functional than most other transports.
2364 Other transports do not support boundary scan operations, or may be
2365 specific to a given chip vendor. Some might be usable only for
2366 programming flash memory, instead of also for debugging.
2367 @end quotation
2368
2369 Debug Adapters/Interfaces/Dongles are normally configured
2370 through commands in an interface configuration
2371 file which is sourced by your @file{openocd.cfg} file, or
2372 through a command line @option{-f interface/....cfg} option.
2373
2374 @example
2375 source [find interface/olimex-jtag-tiny.cfg]
2376 @end example
2377
2378 These commands tell
2379 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2380 A few cases are so simple that you only need to say what driver to use:
2381
2382 @example
2383 # jlink interface
2384 adapter driver jlink
2385 @end example
2386
2387 Most adapters need a bit more configuration than that.
2388
2389
2390 @section Adapter Configuration
2391
2392 The @command{adapter driver} command tells OpenOCD what type of debug adapter you are
2393 using. Depending on the type of adapter, you may need to use one or
2394 more additional commands to further identify or configure the adapter.
2395
2396 @deffn {Config Command} {adapter driver} name
2397 Use the adapter driver @var{name} to connect to the
2398 target.
2399 @end deffn
2400
2401 @deffn {Command} {adapter list}
2402 List the debug adapter drivers that have been built into
2403 the running copy of OpenOCD.
2404 @end deffn
2405 @deffn {Config Command} {adapter transports} transport_name+
2406 Specifies the transports supported by this debug adapter.
2407 The adapter driver builds-in similar knowledge; use this only
2408 when external configuration (such as jumpering) changes what
2409 the hardware can support.
2410 @end deffn
2411
2412
2413
2414 @deffn {Command} {adapter name}
2415 Returns the name of the debug adapter driver being used.
2416 @end deffn
2417
2418 @anchor{adapter_usb_location}
2419 @deffn {Config Command} {adapter usb location} [<bus>-<port>[.<port>]...]
2420 Displays or specifies the physical USB port of the adapter to use. The path
2421 roots at @var{bus} and walks down the physical ports, with each
2422 @var{port} option specifying a deeper level in the bus topology, the last
2423 @var{port} denoting where the target adapter is actually plugged.
2424 The USB bus topology can be queried with the command @emph{lsusb -t} or @emph{dmesg}.
2425
2426 This command is only available if your libusb1 is at least version 1.0.16.
2427 @end deffn
2428
2429 @deffn {Config Command} {adapter serial} serial_string
2430 Specifies the @var{serial_string} of the adapter to use.
2431 If this command is not specified, serial strings are not checked.
2432 Only the following adapter drivers use the serial string from this command:
2433 aice (aice_usb), arm-jtag-ew, cmsis_dap, ft232r, ftdi, hla (stlink, ti-icdi), jlink, kitprog, opendus,
2434 openjtag, osbdm, presto, rlink, st-link, usb_blaster (ublast2), usbprog, vsllink, xds110.
2435 @end deffn
2436
2437 @section Interface Drivers
2438
2439 Each of the interface drivers listed here must be explicitly
2440 enabled when OpenOCD is configured, in order to be made
2441 available at run time.
2442
2443 @deffn {Interface Driver} {amt_jtagaccel}
2444 Amontec Chameleon in its JTAG Accelerator configuration,
2445 connected to a PC's EPP mode parallel port.
2446 This defines some driver-specific commands:
2447
2448 @deffn {Config Command} {parport port} number
2449 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2450 the number of the @file{/dev/parport} device.
2451 @end deffn
2452
2453 @deffn {Config Command} {rtck} [@option{enable}|@option{disable}]
2454 Displays status of RTCK option.
2455 Optionally sets that option first.
2456 @end deffn
2457 @end deffn
2458
2459 @deffn {Interface Driver} {arm-jtag-ew}
2460 Olimex ARM-JTAG-EW USB adapter
2461 This has one driver-specific command:
2462
2463 @deffn {Command} {armjtagew_info}
2464 Logs some status
2465 @end deffn
2466 @end deffn
2467
2468 @deffn {Interface Driver} {at91rm9200}
2469 Supports bitbanged JTAG from the local system,
2470 presuming that system is an Atmel AT91rm9200
2471 and a specific set of GPIOs is used.
2472 @c command: at91rm9200_device NAME
2473 @c chooses among list of bit configs ... only one option
2474 @end deffn
2475
2476 @deffn {Interface Driver} {cmsis-dap}
2477 ARM CMSIS-DAP compliant based adapter v1 (USB HID based)
2478 or v2 (USB bulk).
2479
2480 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2481 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2482 the driver will attempt to auto detect the CMSIS-DAP device.
2483 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2484 @example
2485 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2486 @end example
2487 @end deffn
2488
2489 @deffn {Config Command} {cmsis_dap_backend} [@option{auto}|@option{usb_bulk}|@option{hid}]
2490 Specifies how to communicate with the adapter:
2491
2492 @itemize @minus
2493 @item @option{hid} Use HID generic reports - CMSIS-DAP v1
2494 @item @option{usb_bulk} Use USB bulk - CMSIS-DAP v2
2495 @item @option{auto} First try USB bulk CMSIS-DAP v2, if not found try HID CMSIS-DAP v1.
2496 This is the default if @command{cmsis_dap_backend} is not specified.
2497 @end itemize
2498 @end deffn
2499
2500 @deffn {Config Command} {cmsis_dap_usb interface} [number]
2501 Specifies the @var{number} of the USB interface to use in v2 mode (USB bulk).
2502 In most cases need not to be specified and interfaces are searched by
2503 interface string or for user class interface.
2504 @end deffn
2505
2506 @deffn {Command} {cmsis-dap info}
2507 Display various device information, like hardware version, firmware version, current bus status.
2508 @end deffn
2509
2510 @deffn {Command} {cmsis-dap cmd} number number ...
2511 Execute an arbitrary CMSIS-DAP command. Use for adapter testing or for handling
2512 of an adapter vendor specific command from a Tcl script.
2513
2514 Take given numbers as bytes, assemble a CMSIS-DAP protocol command packet
2515 from them and send it to the adapter. The first 4 bytes of the adapter response
2516 are logged.
2517 See @url{https://arm-software.github.io/CMSIS_5/DAP/html/group__DAP__Commands__gr.html}
2518 @end deffn
2519 @end deffn
2520
2521 @deffn {Interface Driver} {dummy}
2522 A dummy software-only driver for debugging.
2523 @end deffn
2524
2525 @deffn {Interface Driver} {ep93xx}
2526 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2527 @end deffn
2528
2529 @deffn {Interface Driver} {ftdi}
2530 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2531 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2532
2533 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2534 bypassing intermediate libraries like libftdi.
2535
2536 Support for new FTDI based adapters can be added completely through
2537 configuration files, without the need to patch and rebuild OpenOCD.
2538
2539 The driver uses a signal abstraction to enable Tcl configuration files to
2540 define outputs for one or several FTDI GPIO. These outputs can then be
2541 controlled using the @command{ftdi set_signal} command. Special signal names
2542 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2543 will be used for their customary purpose. Inputs can be read using the
2544 @command{ftdi get_signal} command.
2545
2546 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2547 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2548 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2549 required by the protocol, to tell the adapter to drive the data output onto
2550 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2551
2552 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2553 be controlled differently. In order to support tristateable signals such as
2554 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2555 signal. The following output buffer configurations are supported:
2556
2557 @itemize @minus
2558 @item Push-pull with one FTDI output as (non-)inverted data line
2559 @item Open drain with one FTDI output as (non-)inverted output-enable
2560 @item Tristate with one FTDI output as (non-)inverted data line and another
2561 FTDI output as (non-)inverted output-enable
2562 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2563 switching data and direction as necessary
2564 @end itemize
2565
2566 These interfaces have several commands, used to configure the driver
2567 before initializing the JTAG scan chain:
2568
2569 @deffn {Config Command} {ftdi vid_pid} [vid pid]+
2570 The vendor ID and product ID of the adapter. Up to eight
2571 [@var{vid}, @var{pid}] pairs may be given, e.g.
2572 @example
2573 ftdi vid_pid 0x0403 0xcff8 0x15ba 0x0003
2574 @end example
2575 @end deffn
2576
2577 @deffn {Config Command} {ftdi device_desc} description
2578 Provides the USB device description (the @emph{iProduct string})
2579 of the adapter. If not specified, the device description is ignored
2580 during device selection.
2581 @end deffn
2582
2583 @deffn {Config Command} {ftdi channel} channel
2584 Selects the channel of the FTDI device to use for MPSSE operations. Most
2585 adapters use the default, channel 0, but there are exceptions.
2586 @end deffn
2587
2588 @deffn {Config Command} {ftdi layout_init} data direction
2589 Specifies the initial values of the FTDI GPIO data and direction registers.
2590 Each value is a 16-bit number corresponding to the concatenation of the high
2591 and low FTDI GPIO registers. The values should be selected based on the
2592 schematics of the adapter, such that all signals are set to safe levels with
2593 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2594 and initially asserted reset signals.
2595 @end deffn
2596
2597 @deffn {Command} {ftdi layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2598 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2599 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2600 register bitmasks to tell the driver the connection and type of the output
2601 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2602 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2603 used with inverting data inputs and @option{-data} with non-inverting inputs.
2604 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2605 not-output-enable) input to the output buffer is connected. The options
2606 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2607 with the method @command{ftdi get_signal}.
2608
2609 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2610 simple open-collector transistor driver would be specified with @option{-oe}
2611 only. In that case the signal can only be set to drive low or to Hi-Z and the
2612 driver will complain if the signal is set to drive high. Which means that if
2613 it's a reset signal, @command{reset_config} must be specified as
2614 @option{srst_open_drain}, not @option{srst_push_pull}.
2615
2616 A special case is provided when @option{-data} and @option{-oe} is set to the
2617 same bitmask. Then the FTDI pin is considered being connected straight to the
2618 target without any buffer. The FTDI pin is then switched between output and
2619 input as necessary to provide the full set of low, high and Hi-Z
2620 characteristics. In all other cases, the pins specified in a signal definition
2621 are always driven by the FTDI.
2622
2623 If @option{-alias} or @option{-nalias} is used, the signal is created
2624 identical (or with data inverted) to an already specified signal
2625 @var{name}.
2626 @end deffn
2627
2628 @deffn {Command} {ftdi set_signal} name @option{0}|@option{1}|@option{z}
2629 Set a previously defined signal to the specified level.
2630 @itemize @minus
2631 @item @option{0}, drive low
2632 @item @option{1}, drive high
2633 @item @option{z}, set to high-impedance
2634 @end itemize
2635 @end deffn
2636
2637 @deffn {Command} {ftdi get_signal} name
2638 Get the value of a previously defined signal.
2639 @end deffn
2640
2641 @deffn {Command} {ftdi tdo_sample_edge} @option{rising}|@option{falling}
2642 Configure TCK edge at which the adapter samples the value of the TDO signal
2643
2644 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2645 peculiar at high JTAG clock speeds. However, FTDI chips offer a possibility to sample
2646 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2647 stability at higher JTAG clocks.
2648 @itemize @minus
2649 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2650 @item @option{falling}, sample TDO on falling edge of TCK
2651 @end itemize
2652 @end deffn
2653
2654 For example adapter definitions, see the configuration files shipped in the
2655 @file{interface/ftdi} directory.
2656
2657 @end deffn
2658
2659 @deffn {Interface Driver} {ft232r}
2660 This driver is implementing synchronous bitbang mode of an FTDI FT232R,
2661 FT230X, FT231X and similar USB UART bridge ICs by reusing RS232 signals as GPIO.
2662 It currently doesn't support using CBUS pins as GPIO.
2663
2664 List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
2665 @itemize @minus
2666 @item RXD(5) - TDI
2667 @item TXD(1) - TCK
2668 @item RTS(3) - TDO
2669 @item CTS(11) - TMS
2670 @item DTR(2) - TRST
2671 @item DCD(10) - SRST
2672 @end itemize
2673
2674 User can change default pinout by supplying configuration
2675 commands with GPIO numbers or RS232 signal names.
2676 GPIO numbers correspond to bit numbers in FTDI GPIO register.
2677 They differ from physical pin numbers.
2678 For details see actual FTDI chip datasheets.
2679 Every JTAG line must be configured to unique GPIO number
2680 different than any other JTAG line, even those lines
2681 that are sometimes not used like TRST or SRST.
2682
2683 FT232R
2684 @itemize @minus
2685 @item bit 7 - RI
2686 @item bit 6 - DCD
2687 @item bit 5 - DSR
2688 @item bit 4 - DTR
2689 @item bit 3 - CTS
2690 @item bit 2 - RTS
2691 @item bit 1 - RXD
2692 @item bit 0 - TXD
2693 @end itemize
2694
2695 These interfaces have several commands, used to configure the driver
2696 before initializing the JTAG scan chain:
2697
2698 @deffn {Config Command} {ft232r vid_pid} @var{vid} @var{pid}
2699 The vendor ID and product ID of the adapter. If not specified, default
2700 0x0403:0x6001 is used.
2701 @end deffn
2702
2703 @deffn {Config Command} {ft232r jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
2704 Set four JTAG GPIO numbers at once.
2705 If not specified, default 0 3 1 2 or TXD CTS RXD RTS is used.
2706 @end deffn
2707
2708 @deffn {Config Command} {ft232r tck_num} @var{tck}
2709 Set TCK GPIO number. If not specified, default 0 or TXD is used.
2710 @end deffn
2711
2712 @deffn {Config Command} {ft232r tms_num} @var{tms}
2713 Set TMS GPIO number. If not specified, default 3 or CTS is used.
2714 @end deffn
2715
2716 @deffn {Config Command} {ft232r tdi_num} @var{tdi}
2717 Set TDI GPIO number. If not specified, default 1 or RXD is used.
2718 @end deffn
2719
2720 @deffn {Config Command} {ft232r tdo_num} @var{tdo}
2721 Set TDO GPIO number. If not specified, default 2 or RTS is used.
2722 @end deffn
2723
2724 @deffn {Config Command} {ft232r trst_num} @var{trst}
2725 Set TRST GPIO number. If not specified, default 4 or DTR is used.
2726 @end deffn
2727
2728 @deffn {Config Command} {ft232r srst_num} @var{srst}
2729 Set SRST GPIO number. If not specified, default 6 or DCD is used.
2730 @end deffn
2731
2732 @deffn {Config Command} {ft232r restore_serial} @var{word}
2733 Restore serial port after JTAG. This USB bitmode control word
2734 (16-bit) will be sent before quit. Lower byte should
2735 set GPIO direction register to a "sane" state:
2736 0x15 for TXD RTS DTR as outputs (1), others as inputs (0). Higher
2737 byte is usually 0 to disable bitbang mode.
2738 When kernel driver reattaches, serial port should continue to work.
2739 Value 0xFFFF disables sending control word and serial port,
2740 then kernel driver will not reattach.
2741 If not specified, default 0xFFFF is used.
2742 @end deffn
2743
2744 @end deffn
2745
2746 @deffn {Interface Driver} {remote_bitbang}
2747 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2748 with a remote process and sends ASCII encoded bitbang requests to that process
2749 instead of directly driving JTAG.
2750
2751 The remote_bitbang driver is useful for debugging software running on
2752 processors which are being simulated.
2753
2754 @deffn {Config Command} {remote_bitbang port} number
2755 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2756 sockets instead of TCP.
2757 @end deffn
2758
2759 @deffn {Config Command} {remote_bitbang host} hostname
2760 Specifies the hostname of the remote process to connect to using TCP, or the
2761 name of the UNIX socket to use if remote_bitbang port is 0.
2762 @end deffn
2763
2764 For example, to connect remotely via TCP to the host foobar you might have
2765 something like:
2766
2767 @example
2768 adapter driver remote_bitbang
2769 remote_bitbang port 3335
2770 remote_bitbang host foobar
2771 @end example
2772
2773 To connect to another process running locally via UNIX sockets with socket
2774 named mysocket:
2775
2776 @example
2777 adapter driver remote_bitbang
2778 remote_bitbang port 0
2779 remote_bitbang host mysocket
2780 @end example
2781 @end deffn
2782
2783 @deffn {Interface Driver} {usb_blaster}
2784 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2785 for FTDI chips. These interfaces have several commands, used to
2786 configure the driver before initializing the JTAG scan chain:
2787
2788 @deffn {Config Command} {usb_blaster vid_pid} vid pid
2789 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2790 default values are used.
2791 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2792 Altera USB-Blaster (default):
2793 @example
2794 usb_blaster vid_pid 0x09FB 0x6001
2795 @end example
2796 The following VID/PID is for Kolja Waschk's USB JTAG:
2797 @example
2798 usb_blaster vid_pid 0x16C0 0x06AD
2799 @end example
2800 @end deffn
2801
2802 @deffn {Command} {usb_blaster pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2803 Sets the state or function of the unused GPIO pins on USB-Blasters
2804 (pins 6 and 8 on the female JTAG header). These pins can be used as
2805 SRST and/or TRST provided the appropriate connections are made on the
2806 target board.
2807
2808 For example, to use pin 6 as SRST:
2809 @example
2810 usb_blaster pin pin6 s
2811 reset_config srst_only
2812 @end example
2813 @end deffn
2814
2815 @deffn {Config Command} {usb_blaster lowlevel_driver} (@option{ftdi}|@option{ublast2})
2816 Chooses the low level access method for the adapter. If not specified,
2817 @option{ftdi} is selected unless it wasn't enabled during the
2818 configure stage. USB-Blaster II needs @option{ublast2}.
2819 @end deffn
2820
2821 @deffn {Config Command} {usb_blaster firmware} @var{path}
2822 This command specifies @var{path} to access USB-Blaster II firmware
2823 image. To be used with USB-Blaster II only.
2824 @end deffn
2825
2826 @end deffn
2827
2828 @deffn {Interface Driver} {gw16012}
2829 Gateworks GW16012 JTAG programmer.
2830 This has one driver-specific command:
2831
2832 @deffn {Config Command} {parport port} [port_number]
2833 Display either the address of the I/O port
2834 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2835 If a parameter is provided, first switch to use that port.
2836 This is a write-once setting.
2837 @end deffn
2838 @end deffn
2839
2840 @deffn {Interface Driver} {jlink}
2841 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2842 transports.
2843
2844 @quotation Compatibility Note
2845 SEGGER released many firmware versions for the many hardware versions they
2846 produced. OpenOCD was extensively tested and intended to run on all of them,
2847 but some combinations were reported as incompatible. As a general
2848 recommendation, it is advisable to use the latest firmware version
2849 available for each hardware version. However the current V8 is a moving
2850 target, and SEGGER firmware versions released after the OpenOCD was
2851 released may not be compatible. In such cases it is recommended to
2852 revert to the last known functional version. For 0.5.0, this is from
2853 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2854 version is from "May 3 2012 18:36:22", packed with 4.46f.
2855 @end quotation
2856
2857 @deffn {Command} {jlink hwstatus}
2858 Display various hardware related information, for example target voltage and pin
2859 states.
2860 @end deffn
2861 @deffn {Command} {jlink freemem}
2862 Display free device internal memory.
2863 @end deffn
2864 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2865 Set the JTAG command version to be used. Without argument, show the actual JTAG
2866 command version.
2867 @end deffn
2868 @deffn {Command} {jlink config}
2869 Display the device configuration.
2870 @end deffn
2871 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2872 Set the target power state on JTAG-pin 19. Without argument, show the target
2873 power state.
2874 @end deffn
2875 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2876 Set the MAC address of the device. Without argument, show the MAC address.
2877 @end deffn
2878 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2879 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2880 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2881 IP configuration.
2882 @end deffn
2883 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2884 Set the USB address of the device. This will also change the USB Product ID
2885 (PID) of the device. Without argument, show the USB address.
2886 @end deffn
2887 @deffn {Command} {jlink config reset}
2888 Reset the current configuration.
2889 @end deffn
2890 @deffn {Command} {jlink config write}
2891 Write the current configuration to the internal persistent storage.
2892 @end deffn
2893 @deffn {Command} {jlink emucom write} <channel> <data>
2894 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2895 pairs.
2896
2897 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2898 the EMUCOM channel 0x10:
2899 @example
2900 > jlink emucom write 0x10 aa0b23
2901 @end example
2902 @end deffn
2903 @deffn {Command} {jlink emucom read} <channel> <length>
2904 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2905 pairs.
2906
2907 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2908 @example
2909 > jlink emucom read 0x0 4
2910 77a90000
2911 @end example
2912 @end deffn
2913 @deffn {Config Command} {jlink usb} <@option{0} to @option{3}>
2914 Set the USB address of the interface, in case more than one adapter is connected
2915 to the host. If not specified, USB addresses are not considered. Device
2916 selection via USB address is not always unambiguous. It is recommended to use
2917 the serial number instead, if possible.
2918
2919 As a configuration command, it can be used only before 'init'.
2920 @end deffn
2921 @end deffn
2922
2923 @deffn {Interface Driver} {kitprog}
2924 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2925 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2926 families, but it is possible to use it with some other devices. If you are using
2927 this adapter with a PSoC or a PRoC, you may need to add
2928 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2929 configuration script.
2930
2931 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2932 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2933 be used with this driver, and must either be used with the cmsis-dap driver or
2934 switched back to KitProg mode. See the Cypress KitProg User Guide for
2935 instructions on how to switch KitProg modes.
2936
2937 Known limitations:
2938 @itemize @bullet
2939 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2940 and 2.7 MHz.
2941 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2942 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2943 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2944 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2945 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2946 SWD sequence must be sent after every target reset in order to re-establish
2947 communications with the target.
2948 @item Due in part to the limitation above, KitProg devices with firmware below
2949 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
2950 communicate with PSoC 5LP devices. This is because, assuming debug is not
2951 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
2952 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
2953 could only be sent with an acquisition sequence.
2954 @end itemize
2955
2956 @deffn {Config Command} {kitprog_init_acquire_psoc}
2957 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
2958 Please be aware that the acquisition sequence hard-resets the target.
2959 @end deffn
2960
2961 @deffn {Command} {kitprog acquire_psoc}
2962 Run a PSoC acquisition sequence immediately. Typically, this should not be used
2963 outside of the target-specific configuration scripts since it hard-resets the
2964 target as a side-effect.
2965 This is necessary for "reset halt" on some PSoC 4 series devices.
2966 @end deffn
2967
2968 @deffn {Command} {kitprog info}
2969 Display various adapter information, such as the hardware version, firmware
2970 version, and target voltage.
2971 @end deffn
2972 @end deffn
2973
2974 @deffn {Interface Driver} {parport}
2975 Supports PC parallel port bit-banging cables:
2976 Wigglers, PLD download cable, and more.
2977 These interfaces have several commands, used to configure the driver
2978 before initializing the JTAG scan chain:
2979
2980 @deffn {Config Command} {parport cable} name
2981 Set the layout of the parallel port cable used to connect to the target.
2982 This is a write-once setting.
2983 Currently valid cable @var{name} values include:
2984
2985 @itemize @minus
2986 @item @b{altium} Altium Universal JTAG cable.
2987 @item @b{arm-jtag} Same as original wiggler except SRST and
2988 TRST connections reversed and TRST is also inverted.
2989 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2990 in configuration mode. This is only used to
2991 program the Chameleon itself, not a connected target.
2992 @item @b{dlc5} The Xilinx Parallel cable III.
2993 @item @b{flashlink} The ST Parallel cable.
2994 @item @b{lattice} Lattice ispDOWNLOAD Cable
2995 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2996 some versions of
2997 Amontec's Chameleon Programmer. The new version available from
2998 the website uses the original Wiggler layout ('@var{wiggler}')
2999 @item @b{triton} The parallel port adapter found on the
3000 ``Karo Triton 1 Development Board''.
3001 This is also the layout used by the HollyGates design
3002 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
3003 @item @b{wiggler} The original Wiggler layout, also supported by
3004 several clones, such as the Olimex ARM-JTAG
3005 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
3006 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
3007 @end itemize
3008 @end deffn
3009
3010 @deffn {Config Command} {parport port} [port_number]
3011 Display either the address of the I/O port
3012 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
3013 If a parameter is provided, first switch to use that port.
3014 This is a write-once setting.
3015
3016 When using PPDEV to access the parallel port, use the number of the parallel port:
3017 @option{parport port 0} (the default). If @option{parport port 0x378} is specified
3018 you may encounter a problem.
3019 @end deffn
3020
3021 @deffn {Config Command} {parport toggling_time} [nanoseconds]
3022 Displays how many nanoseconds the hardware needs to toggle TCK;
3023 the parport driver uses this value to obey the
3024 @command{adapter speed} configuration.
3025 When the optional @var{nanoseconds} parameter is given,
3026 that setting is changed before displaying the current value.
3027
3028 The default setting should work reasonably well on commodity PC hardware.
3029 However, you may want to calibrate for your specific hardware.
3030 @quotation Tip
3031 To measure the toggling time with a logic analyzer or a digital storage
3032 oscilloscope, follow the procedure below:
3033 @example
3034 > parport toggling_time 1000
3035 > adapter speed 500
3036 @end example
3037 This sets the maximum JTAG clock speed of the hardware, but
3038 the actual speed probably deviates from the requested 500 kHz.
3039 Now, measure the time between the two closest spaced TCK transitions.
3040 You can use @command{runtest 1000} or something similar to generate a
3041 large set of samples.
3042 Update the setting to match your measurement:
3043 @example
3044 > parport toggling_time <measured nanoseconds>
3045 @end example
3046 Now the clock speed will be a better match for @command{adapter speed}
3047 command given in OpenOCD scripts and event handlers.
3048
3049 You can do something similar with many digital multimeters, but note
3050 that you'll probably need to run the clock continuously for several
3051 seconds before it decides what clock rate to show. Adjust the
3052 toggling time up or down until the measured clock rate is a good
3053 match with the rate you specified in the @command{adapter speed} command;
3054 be conservative.
3055 @end quotation
3056 @end deffn
3057
3058 @deffn {Config Command} {parport write_on_exit} (@option{on}|@option{off})
3059 This will configure the parallel driver to write a known
3060 cable-specific value to the parallel interface on exiting OpenOCD.
3061 @end deffn
3062
3063 For example, the interface configuration file for a
3064 classic ``Wiggler'' cable on LPT2 might look something like this:
3065
3066 @example
3067 adapter driver parport
3068 parport port 0x278
3069 parport cable wiggler
3070 @end example
3071 @end deffn
3072
3073 @deffn {Interface Driver} {presto}
3074 ASIX PRESTO USB JTAG programmer.
3075 @end deffn
3076
3077 @deffn {Interface Driver} {rlink}
3078 Raisonance RLink USB adapter
3079 @end deffn
3080
3081 @deffn {Interface Driver} {usbprog}
3082 usbprog is a freely programmable USB adapter.
3083 @end deffn
3084
3085 @deffn {Interface Driver} {vsllink}
3086 vsllink is part of Versaloon which is a versatile USB programmer.
3087
3088 @quotation Note
3089 This defines quite a few driver-specific commands,
3090 which are not currently documented here.
3091 @end quotation
3092 @end deffn
3093
3094 @anchor{hla_interface}
3095 @deffn {Interface Driver} {hla}
3096 This is a driver that supports multiple High Level Adapters.
3097 This type of adapter does not expose some of the lower level api's
3098 that OpenOCD would normally use to access the target.
3099
3100 Currently supported adapters include the STMicroelectronics ST-LINK, TI ICDI
3101 and Nuvoton Nu-Link.
3102 ST-LINK firmware version >= V2.J21.S4 recommended due to issues with earlier
3103 versions of firmware where serial number is reset after first use. Suggest
3104 using ST firmware update utility to upgrade ST-LINK firmware even if current
3105 version reported is V2.J21.S4.
3106
3107 @deffn {Config Command} {hla_device_desc} description
3108 Currently Not Supported.
3109 @end deffn
3110
3111 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi}|@option{nulink})
3112 Specifies the adapter layout to use.
3113 @end deffn
3114
3115 @deffn {Config Command} {hla_vid_pid} [vid pid]+
3116 Pairs of vendor IDs and product IDs of the device.
3117 @end deffn
3118
3119 @deffn {Config Command} {hla_stlink_backend} (usb | tcp [port])
3120 @emph{ST-Link only:} Choose between 'exclusive' USB communication (the default backend) or
3121 'shared' mode using ST-Link TCP server (the default port is 7184).
3122
3123 @emph{Note:} ST-Link TCP server is a binary application provided by ST
3124 available from @url{https://www.st.com/en/development-tools/st-link-server.html,
3125 ST-LINK server software module}.
3126 @end deffn
3127
3128 @deffn {Command} {hla_command} command
3129 Execute a custom adapter-specific command. The @var{command} string is
3130 passed as is to the underlying adapter layout handler.
3131 @end deffn
3132 @end deffn
3133
3134 @anchor{st_link_dap_interface}
3135 @deffn {Interface Driver} {st-link}
3136 This is a driver that supports STMicroelectronics adapters ST-LINK/V2
3137 (from firmware V2J24) and STLINK-V3, thanks to a new API that provides
3138 directly access the arm ADIv5 DAP.
3139
3140 The new API provide access to multiple AP on the same DAP, but the
3141 maximum number of the AP port is limited by the specific firmware version
3142 (e.g. firmware V2J29 has 3 as maximum AP number, while V2J32 has 8).
3143 An error is returned for any AP number above the maximum allowed value.
3144
3145 @emph{Note:} Either these same adapters and their older versions are
3146 also supported by @ref{hla_interface, the hla interface driver}.
3147
3148 @deffn {Config Command} {st-link backend} (usb | tcp [port])
3149 Choose between 'exclusive' USB communication (the default backend) or
3150 'shared' mode using ST-Link TCP server (the default port is 7184).
3151
3152 @emph{Note:} ST-Link TCP server is a binary application provided by ST
3153 available from @url{https://www.st.com/en/development-tools/st-link-server.html,
3154 ST-LINK server software module}.
3155
3156 @emph{Note:} ST-Link TCP server does not support the SWIM transport.
3157 @end deffn
3158
3159 @deffn {Config Command} {st-link vid_pid} [vid pid]+
3160 Pairs of vendor IDs and product IDs of the device.
3161 @end deffn
3162
3163 @deffn {Command} {st-link cmd} rx_n (tx_byte)+
3164 Sends an arbitrary command composed by the sequence of bytes @var{tx_byte}
3165 and receives @var{rx_n} bytes.
3166
3167 For example, the command to read the target's supply voltage is one byte 0xf7 followed
3168 by 15 bytes zero. It returns 8 bytes, where the first 4 bytes represent the ADC sampling
3169 of the reference voltage 1.2V and the last 4 bytes represent the ADC sampling of half
3170 the target's supply voltage.
3171 @example
3172 > st-link cmd 8 0xf7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3173 0xf1 0x05 0x00 0x00 0x0b 0x08 0x00 0x00
3174 @end example
3175 The result can be converted to Volts (ignoring the most significant bytes, always zero)
3176 @example
3177 > set a [st-link cmd 8 0xf7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
3178 > set n [expr @{[lindex $a 4] + 256 * [lindex $a 5]@}]
3179 > set d [expr @{[lindex $a 0] + 256 * [lindex $a 1]@}]
3180 > echo [expr @{2 * 1.2 * $n / $d@}]
3181 3.24891518738
3182 @end example
3183 @end deffn
3184 @end deffn
3185
3186 @deffn {Interface Driver} {opendous}
3187 opendous-jtag is a freely programmable USB adapter.
3188 @end deffn
3189
3190 @deffn {Interface Driver} {ulink}
3191 This is the Keil ULINK v1 JTAG debugger.
3192 @end deffn
3193
3194 @deffn {Interface Driver} {xds110}
3195 The XDS110 is included as the embedded debug probe on many Texas Instruments
3196 LaunchPad evaluation boards. The XDS110 is also available as a stand-alone USB
3197 debug probe with the added capability to supply power to the target board. The
3198 following commands are supported by the XDS110 driver:
3199
3200 @deffn {Config Command} {xds110 supply} voltage_in_millivolts
3201 Available only on the XDS110 stand-alone probe. Sets the voltage level of the
3202 XDS110 power supply. A value of 0 leaves the supply off. Otherwise, the supply
3203 can be set to any value in the range 1800 to 3600 millivolts.
3204 @end deffn
3205
3206 @deffn {Command} {xds110 info}
3207 Displays information about the connected XDS110 debug probe (e.g. firmware
3208 version).
3209 @end deffn
3210 @end deffn
3211
3212 @deffn {Interface Driver} {xlnx_pcie_xvc}
3213 This driver supports the Xilinx Virtual Cable (XVC) over PCI Express.
3214 It is commonly found in Xilinx based PCI Express designs. It allows debugging
3215 fabric based JTAG/SWD devices such as Cortex-M1/M3 microcontrollers. Access to this is
3216 exposed via extended capability registers in the PCI Express configuration space.
3217
3218 For more information see Xilinx PG245 (Section on From_PCIE_to_JTAG mode).
3219
3220 @deffn {Config Command} {xlnx_pcie_xvc config} device
3221 Specifies the PCI Express device via parameter @var{device} to use.
3222
3223 The correct value for @var{device} can be obtained by looking at the output
3224 of lscpi -D (first column) for the corresponding device.
3225
3226 The string will be of the format "DDDD:BB:SS.F" such as "0000:65:00.1".
3227
3228 @end deffn
3229 @end deffn
3230
3231 @deffn {Interface Driver} {bcm2835gpio}
3232 This SoC is present in Raspberry Pi which is a cheap single-board computer
3233 exposing some GPIOs on its expansion header.
3234
3235 The driver accesses memory-mapped GPIO peripheral registers directly
3236 for maximum performance, but the only possible race condition is for
3237 the pins' modes/muxing (which is highly unlikely), so it should be
3238 able to coexist nicely with both sysfs bitbanging and various
3239 peripherals' kernel drivers. The driver restores the previous
3240 configuration on exit.
3241
3242 GPIO numbers >= 32 can't be used for performance reasons.
3243
3244 See @file{interface/raspberrypi-native.cfg} for a sample config and
3245 pinout.
3246
3247 @deffn {Config Command} {bcm2835gpio jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
3248 Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order).
3249 Must be specified to enable JTAG transport. These pins can also be specified
3250 individually.
3251 @end deffn
3252
3253 @deffn {Config Command} {bcm2835gpio tck_num} @var{tck}
3254 Set TCK GPIO number. Must be specified to enable JTAG transport. Can also be
3255 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3256 @end deffn
3257
3258 @deffn {Config Command} {bcm2835gpio tms_num} @var{tms}
3259 Set TMS GPIO number. Must be specified to enable JTAG transport. Can also be
3260 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3261 @end deffn
3262
3263 @deffn {Config Command} {bcm2835gpio tdo_num} @var{tdo}
3264 Set TDO GPIO number. Must be specified to enable JTAG transport. Can also be
3265 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3266 @end deffn
3267
3268 @deffn {Config Command} {bcm2835gpio tdi_num} @var{tdi}
3269 Set TDI GPIO number. Must be specified to enable JTAG transport. Can also be
3270 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3271 @end deffn
3272
3273 @deffn {Config Command} {bcm2835gpio swd_nums} @var{swclk} @var{swdio}
3274 Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be
3275 specified to enable SWD transport. These pins can also be specified individually.
3276 @end deffn
3277
3278 @deffn {Config Command} {bcm2835gpio swclk_num} @var{swclk}
3279 Set SWCLK GPIO number. Must be specified to enable SWD transport. Can also be
3280 specified using the configuration command @command{bcm2835gpio swd_nums}.
3281 @end deffn
3282
3283 @deffn {Config Command} {bcm2835gpio swdio_num} @var{swdio}
3284 Set SWDIO GPIO number. Must be specified to enable SWD transport. Can also be
3285 specified using the configuration command @command{bcm2835gpio swd_nums}.
3286 @end deffn
3287
3288 @deffn {Config Command} {bcm2835gpio swdio_dir_num} @var{swdio} @var{dir}
3289 Set SWDIO direction control pin GPIO number. If specified, this pin can be used
3290 to control the direction of an external buffer on the SWDIO pin (set=output
3291 mode, clear=input mode). If not specified, this feature is disabled.
3292 @end deffn
3293
3294 @deffn {Config Command} {bcm2835gpio srst_num} @var{srst}
3295 Set SRST GPIO number. Must be specified to enable SRST.
3296 @end deffn
3297
3298 @deffn {Config Command} {bcm2835gpio trst_num} @var{trst}
3299 Set TRST GPIO number. Must be specified to enable TRST.
3300 @end deffn
3301
3302 @deffn {Config Command} {bcm2835gpio speed_coeffs} @var{speed_coeff} @var{speed_offset}
3303 Set SPEED_COEFF and SPEED_OFFSET for delay calculations. If unspecified,
3304 speed_coeff defaults to 113714, and speed_offset defaults to 28.
3305 @end deffn
3306
3307 @deffn {Config Command} {bcm2835gpio peripheral_base} @var{base}
3308 Set the peripheral base register address to access GPIOs. For the RPi1, use
3309 0x20000000. For RPi2 and RPi3, use 0x3F000000. For RPi4, use 0xFE000000. A full
3310 list can be found in the
3311 @uref{https://www.raspberrypi.org/documentation/hardware/raspberrypi/peripheral_addresses.md, official guide}.
3312 @end deffn
3313
3314 @end deffn
3315
3316 @deffn {Interface Driver} {imx_gpio}
3317 i.MX SoC is present in many community boards. Wandboard is an example
3318 of the one which is most popular.
3319
3320 This driver is mostly the same as bcm2835gpio.
3321
3322 See @file{interface/imx-native.cfg} for a sample config and
3323 pinout.
3324
3325 @end deffn
3326
3327
3328 @deffn {Interface Driver} {am335xgpio} The AM335x SoC is present in BeagleBone
3329 Black and BeagleBone Green single-board computers which expose some of the GPIOs
3330 on the two expansion headers.
3331
3332 For maximum performance the driver accesses memory-mapped GPIO peripheral
3333 registers directly. The memory mapping requires read and write permission to
3334 kernel memory; if /dev/gpiomem exists it will be used, otherwise /dev/mem will
3335 be used. The driver restores the GPIO state on exit.
3336
3337 All four GPIO ports are available. GPIOs numbered 0 to 31 are mapped to GPIO port
3338 0, GPIO numbers 32 to 63 are mapped to GPIO port 1 and so on.
3339
3340 See @file{interface/beaglebone-swd-native.cfg} for a sample configuration file.
3341
3342 @deffn {Config Command} {am335xgpio jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
3343 Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order).
3344 Must be specified to enable JTAG transport. These pins can also be specified
3345 individually.
3346 @end deffn
3347
3348 @deffn {Config Command} {am335xgpio tck_num} @var{tck}
3349 Set TCK GPIO number. Must be specified to enable JTAG transport. Can also be
3350 specified using the configuration command @command{am335xgpio jtag_nums}.
3351 @end deffn
3352
3353 @deffn {Config Command} {am335xgpio tms_num} @var{tms}
3354 Set TMS GPIO number. Must be specified to enable JTAG transport. Can also be
3355 specified using the configuration command @command{am335xgpio jtag_nums}.
3356 @end deffn
3357
3358 @deffn {Config Command} {am335xgpio tdo_num} @var{tdo}
3359 Set TDO GPIO number. Must be specified to enable JTAG transport. Can also be
3360 specified using the configuration command @command{am335xgpio jtag_nums}.
3361 @end deffn
3362
3363 @deffn {Config Command} {am335xgpio tdi_num} @var{tdi}
3364 Set TDI GPIO number. Must be specified to enable JTAG transport. Can also be
3365 specified using the configuration command @command{am335xgpio jtag_nums}.
3366 @end deffn
3367
3368 @deffn {Config Command} {am335xgpio swd_nums} @var{swclk} @var{swdio}
3369 Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be
3370 specified to enable SWD transport. These pins can also be specified individually.
3371 @end deffn
3372
3373 @deffn {Config Command} {am335xgpio swclk_num} @var{swclk}
3374 Set SWCLK GPIO number. Must be specified to enable SWD transport. Can also be
3375 specified using the configuration command @command{am335xgpio swd_nums}.
3376 @end deffn
3377
3378 @deffn {Config Command} {am335xgpio swdio_num} @var{swdio}
3379 Set SWDIO GPIO number. Must be specified to enable SWD transport. Can also be
3380 specified using the configuration command @command{am335xgpio swd_nums}.
3381 @end deffn
3382
3383 @deffn {Config Command} {am335xgpio swdio_dir_num} @var{swdio_dir}
3384 Set SWDIO direction control pin GPIO number. If specified, this pin can be used
3385 to control the direction of an external buffer on the SWDIO pin. The direction
3386 control state can be set with the command @command{am335xgpio
3387 swdio_dir_output_state}. If not specified this feature is disabled.
3388 @end deffn
3389
3390 @deffn {Config Command} {am335xgpio swdio_dir_output_state} @var{output_state}
3391 Set the state required for an external SWDIO buffer to be an output. Valid
3392 values are @option{on} (default) and @option{off}.
3393 @end deffn
3394
3395 @deffn {Config Command} {am335xgpio srst_num} @var{srst}
3396 Set SRST GPIO number. Must be specified to enable SRST.
3397 @end deffn
3398
3399 @deffn {Config Command} {am335xgpio trst_num} @var{trst}
3400 Set TRST GPIO number. Must be specified to enable TRST.
3401 @end deffn
3402
3403 @deffn {Config Command} {am335xgpio led_num} @var{led}
3404 Set activity LED GPIO number. If not specified an activity LED is not enabled.
3405 @end deffn
3406
3407 @deffn {Config Command} {am335xgpio led_on_state} @var{on_state}
3408 Set required logic level for the LED to be on. Valid values are @option{on}
3409 (default) and @option{off}.
3410 @end deffn
3411
3412 @deffn {Config Command} {am335xgpio speed_coeffs} @var{speed_coeff} @var{speed_offset}
3413 Set SPEED_COEFF and SPEED_OFFSET for delay calculations. If unspecified
3414 speed_coeff defaults to 600000 and speed_offset defaults to 575.
3415 @end deffn
3416
3417 @end deffn
3418
3419
3420 @deffn {Interface Driver} {linuxgpiod}
3421 Linux provides userspace access to GPIO through libgpiod since Linux kernel version v4.6.
3422 The driver emulates either JTAG or SWD transport through bitbanging.
3423
3424 See @file{interface/dln-2-gpiod.cfg} for a sample config.
3425
3426 @deffn {Config Command} {linuxgpiod gpiochip} @var{chip}
3427 Set the GPIO chip number for all GPIOs used by linuxgpiod. If GPIOs use
3428 different GPIO chips then the individual GPIO configuration commands (i.e., not
3429 @command{linuxgpiod jtag_nums} or @command{linuxgpiod swd_nums}) can be used to
3430 set chip numbers independently for each GPIO.
3431 @end deffn
3432
3433 @deffn {Config Command} {linuxgpiod jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
3434 Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order). Must
3435 be specified to enable JTAG transport. These pins can also be specified
3436 individually.
3437 @end deffn
3438
3439 @deffn {Config Command} {linuxgpiod tck_num} [@var{chip}] @var{tck}
3440 Set TCK GPIO number, and optionally TCK chip number. Must be specified to enable
3441 JTAG transport. Can also be specified using the configuration command
3442 @command{linuxgpiod jtag_nums}.
3443 @end deffn
3444
3445 @deffn {Config Command} {linuxgpiod tms_num} [@var{chip}] @var{tms}
3446 Set TMS GPIO number, and optionally TMS chip number. Must be specified to enable
3447 JTAG transport. Can also be specified using the configuration command
3448 @command{linuxgpiod jtag_nums}.
3449 @end deffn
3450
3451 @deffn {Config Command} {linuxgpiod tdo_num} [@var{chip}] @var{tdo}
3452 Set TDO GPIO number, and optionally TDO chip number. Must be specified to enable
3453 JTAG transport. Can also be specified using the configuration command
3454 @command{linuxgpiod jtag_nums}.
3455 @end deffn
3456
3457 @deffn {Config Command} {linuxgpiod tdi_num} [@var{chip}] @var{tdi}
3458 Set TDI GPIO number, and optionally TDI chip number. Must be specified to enable
3459 JTAG transport. Can also be specified using the configuration command
3460 @command{linuxgpiod jtag_nums}.
3461 @end deffn
3462
3463 @deffn {Config Command} {linuxgpiod trst_num} [@var{chip}] @var{trst}
3464 Set TRST GPIO number, and optionally TRST chip number. Must be specified to
3465 enable TRST.
3466 @end deffn
3467
3468 @deffn {Config Command} {linuxgpiod swd_nums} @var{swclk} @var{swdio}
3469 Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be
3470 specified to enable SWD transport. These pins can also be specified
3471 individually.
3472 @end deffn
3473
3474 @deffn {Config Command} {linuxgpiod swclk_num} [@var{chip}] @var{swclk}
3475 Set SWCLK GPIO number, and optionally SWCLK chip number. Must be specified to
3476 enable SWD transport. Can also be specified using the configuration command
3477 @command{linuxgpiod swd_nums}.
3478 @end deffn
3479
3480 @deffn {Config Command} {linuxgpiod swdio_num} [@var{chip}] @var{swdio}
3481 Set SWDIO GPIO number, and optionally SWDIO chip number. Must be specified to
3482 enable SWD transport. Can also be specified using the configuration command
3483 @command{linuxgpiod swd_nums}.
3484 @end deffn
3485
3486 @deffn {Config Command} {linuxgpiod swdio_dir_num} [@var{chip}] @var{swdio_dir}
3487 Set SWDIO direction control GPIO number, and optionally SWDIO direction control
3488 chip number. If specified, this GPIO can be used to control the direction of an
3489 external buffer connected to the SWDIO GPIO (set=output mode, clear=input mode).
3490 @end deffn
3491
3492 @deffn {Config Command} {linuxgpiod srst_num} [@var{chip}] @var{srst}
3493 Set SRST GPIO number, and optionally SRST chip number. Must be specified to
3494 enable SRST.
3495 @end deffn
3496
3497 @deffn {Config Command} {linuxgpiod led_num} [@var{chip}] @var{led}
3498 Set activity LED GPIO number, and optionally activity LED chip number. If not
3499 specified an activity LED is not enabled.
3500 @end deffn
3501
3502 @end deffn
3503
3504
3505 @deffn {Interface Driver} {sysfsgpio}
3506 Linux legacy userspace access to GPIO through sysfs is deprecated from Linux kernel version v5.3.
3507 Prefer using @b{linuxgpiod}, instead.
3508
3509 See @file{interface/sysfsgpio-raspberrypi.cfg} for a sample config.
3510 @end deffn
3511
3512
3513 @deffn {Interface Driver} {openjtag}
3514 OpenJTAG compatible USB adapter.
3515 This defines some driver-specific commands:
3516
3517 @deffn {Config Command} {openjtag variant} variant
3518 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
3519 Currently valid @var{variant} values include:
3520
3521 @itemize @minus
3522 @item @b{standard} Standard variant (default).
3523 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3524 (see @uref{http://www.cypress.com/?rID=82870}).
3525 @end itemize
3526 @end deffn
3527
3528 @deffn {Config Command} {openjtag device_desc} string
3529 The USB device description string of the adapter.
3530 This value is only used with the standard variant.
3531 @end deffn
3532 @end deffn
3533
3534
3535 @deffn {Interface Driver} {vdebug}
3536 Cadence Virtual Debug Interface driver.
3537
3538 @deffn {Config Command} {vdebug server} host:port
3539 Specifies the host and TCP port number where the vdebug server runs.
3540 @end deffn
3541
3542 @deffn {Config Command} {vdebug batching} value
3543 Specifies the batching method for the vdebug request. Possible values are
3544 0 for no batching
3545 1 or wr to batch write transactions together (default)
3546 2 or rw to batch both read and write transactions
3547 @end deffn
3548
3549 @deffn {Config Command} {vdebug polling} min max
3550 Takes two values, representing the polling interval in ms. Lower values mean faster
3551 debugger responsiveness, but lower emulation performance. The minimum should be
3552 around 10, maximum should not exceed 1000, which is the default gdb and keepalive
3553 timeout value.
3554 @end deffn
3555
3556 @deffn {Config Command} {vdebug bfm_path} path clk_period
3557 Specifies the hierarchical path and input clk period of the vdebug BFM in the design.
3558 The hierarchical path uses Verilog notation top.inst.inst
3559 The clock period must include the unit, for instance 40ns.
3560 @end deffn
3561
3562 @deffn {Config Command} {vdebug mem_path} path base size
3563 Specifies the hierarchical path to the design memory instance for backdoor access.
3564 Up to 4 memories can be specified. The hierarchical path uses Verilog notation.
3565 The base specifies start address in the design address space, size its size in bytes.
3566 Both values can use hexadecimal notation with prefix 0x.
3567 @end deffn
3568 @end deffn
3569
3570 @deffn {Interface Driver} {jtag_dpi}
3571 SystemVerilog Direct Programming Interface (DPI) compatible driver for
3572 JTAG devices in emulation. The driver acts as a client for the SystemVerilog
3573 DPI server interface.
3574
3575 @deffn {Config Command} {jtag_dpi set_port} port
3576 Specifies the TCP/IP port number of the SystemVerilog DPI server interface.
3577 @end deffn
3578
3579 @deffn {Config Command} {jtag_dpi set_address} address
3580 Specifies the TCP/IP address of the SystemVerilog DPI server interface.
3581 @end deffn
3582 @end deffn
3583
3584
3585 @deffn {Interface Driver} {buspirate}
3586
3587 This driver is for the Bus Pirate (see @url{http://dangerousprototypes.com/docs/Bus_Pirate}) and compatible devices.
3588 It uses a simple data protocol over a serial port connection.
3589
3590 Most hardware development boards have a UART, a real serial port, or a virtual USB serial device, so this driver
3591 allows you to start building your own JTAG adapter without the complexity of a custom USB connection.
3592
3593 @deffn {Config Command} {buspirate port} serial_port
3594 Specify the serial port's filename. For example:
3595 @example
3596 buspirate port /dev/ttyUSB0
3597 @end example
3598 @end deffn
3599
3600 @deffn {Config Command} {buspirate speed} (normal|fast)
3601 Set the communication speed to 115k (normal) or 1M (fast). For example:
3602 @example
3603 buspirate speed normal
3604 @end example
3605 @end deffn
3606
3607 @deffn {Config Command} {buspirate mode} (normal|open-drain)
3608 Set the Bus Pirate output mode.
3609 @itemize @minus
3610 @item In normal mode (push/pull), do not enable the pull-ups, and do not connect I/O header pin VPU to JTAG VREF.
3611 @item In open drain mode, you will then need to enable the pull-ups.
3612 @end itemize
3613 For example:
3614 @example
3615 buspirate mode normal
3616 @end example
3617 @end deffn
3618
3619 @deffn {Config Command} {buspirate pullup} (0|1)
3620 Whether to connect (1) or not (0) the I/O header pin VPU (JTAG VREF)
3621 to the pull-up/pull-down resistors on MOSI (JTAG TDI), CLK (JTAG TCK), MISO (JTAG TDO) and CS (JTAG TMS).
3622 For example:
3623 @example
3624 buspirate pullup 0
3625 @end example
3626 @end deffn
3627
3628 @deffn {Config Command} {buspirate vreg} (0|1)
3629 Whether to enable (1) or disable (0) the built-in voltage regulator,
3630 which can be used to supply power to a test circuit through
3631 I/O header pins +3V3 and +5V. For example:
3632 @example
3633 buspirate vreg 0
3634 @end example
3635 @end deffn
3636
3637 @deffn {Command} {buspirate led} (0|1)
3638 Turns the Bus Pirate's LED on (1) or off (0). For example:
3639 @end deffn
3640 @example
3641 buspirate led 1
3642 @end example
3643
3644 @end deffn
3645
3646
3647 @section Transport Configuration
3648 @cindex Transport
3649 As noted earlier, depending on the version of OpenOCD you use,
3650 and the debug adapter you are using,
3651 several transports may be available to
3652 communicate with debug targets (or perhaps to program flash memory).
3653 @deffn {Command} {transport list}
3654 displays the names of the transports supported by this
3655 version of OpenOCD.
3656 @end deffn
3657
3658 @deffn {Command} {transport select} @option{transport_name}
3659 Select which of the supported transports to use in this OpenOCD session.
3660
3661 When invoked with @option{transport_name}, attempts to select the named
3662 transport. The transport must be supported by the debug adapter
3663 hardware and by the version of OpenOCD you are using (including the
3664 adapter's driver).
3665
3666 If no transport has been selected and no @option{transport_name} is
3667 provided, @command{transport select} auto-selects the first transport
3668 supported by the debug adapter.
3669
3670 @command{transport select} always returns the name of the session's selected
3671 transport, if any.
3672 @end deffn
3673
3674 @subsection JTAG Transport
3675 @cindex JTAG
3676 JTAG is the original transport supported by OpenOCD, and most
3677 of the OpenOCD commands support it.
3678 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3679 each of which must be explicitly declared.
3680 JTAG supports both debugging and boundary scan testing.
3681 Flash programming support is built on top of debug support.
3682
3683 JTAG transport is selected with the command @command{transport select
3684 jtag}. Unless your adapter uses either @ref{hla_interface,the hla interface
3685 driver} (in which case the command is @command{transport select hla_jtag})
3686 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3687 the command is @command{transport select dapdirect_jtag}).
3688
3689 @subsection SWD Transport
3690 @cindex SWD
3691 @cindex Serial Wire Debug
3692 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3693 Debug Access Point (DAP, which must be explicitly declared.
3694 (SWD uses fewer signal wires than JTAG.)
3695 SWD is debug-oriented, and does not support boundary scan testing.
3696 Flash programming support is built on top of debug support.
3697 (Some processors support both JTAG and SWD.)
3698
3699 SWD transport is selected with the command @command{transport select
3700 swd}. Unless your adapter uses either @ref{hla_interface,the hla interface
3701 driver} (in which case the command is @command{transport select hla_swd})
3702 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3703 the command is @command{transport select dapdirect_swd}).
3704
3705 @deffn {Config Command} {swd newdap} ...
3706 Declares a single DAP which uses SWD transport.
3707 Parameters are currently the same as "jtag newtap" but this is
3708 expected to change.
3709 @end deffn
3710
3711 @cindex SWD multi-drop
3712 The newer SWD devices (SW-DP v2 or SWJ-DP v2) support the multi-drop extension
3713 of SWD protocol: two or more devices can be connected to one SWD adapter.
3714 SWD transport works in multi-drop mode if @ref{dap_create,DAP} is configured
3715 with both @code{-dp-id} and @code{-instance-id} parameters regardless how many
3716 DAPs are created.
3717
3718 Not all adapters and adapter drivers support SWD multi-drop. Only the following
3719 adapter drivers are SWD multi-drop capable:
3720 cmsis_dap (use an adapter with CMSIS-DAP version 2.0), ftdi, all bitbang based.
3721
3722 @subsection SPI Transport
3723 @cindex SPI
3724 @cindex Serial Peripheral Interface
3725 The Serial Peripheral Interface (SPI) is a general purpose transport
3726 which uses four wire signaling. Some processors use it as part of a
3727 solution for flash programming.
3728
3729 @anchor{swimtransport}
3730 @subsection SWIM Transport
3731 @cindex SWIM
3732 @cindex Single Wire Interface Module
3733 The Single Wire Interface Module (SWIM) is a low-pin-count debug protocol used
3734 by the STMicroelectronics MCU family STM8 and documented in the
3735 @uref{https://www.st.com/resource/en/user_manual/cd00173911.pdf, User Manual UM470}.
3736
3737 SWIM does not support boundary scan testing nor multiple cores.
3738
3739 The SWIM transport is selected with the command @command{transport select swim}.
3740
3741 The concept of TAPs does not fit in the protocol since SWIM does not implement
3742 a scan chain. Nevertheless, the current SW model of OpenOCD requires defining a
3743 virtual SWIM TAP through the command @command{swim newtap basename tap_type}.
3744 The TAP definition must precede the target definition command
3745 @command{target create target_name stm8 -chain-position basename.tap_type}.
3746
3747 @anchor{jtagspeed}
3748 @section JTAG Speed
3749 JTAG clock setup is part of system setup.
3750 It @emph{does not belong with interface setup} since any interface
3751 only knows a few of the constraints for the JTAG clock speed.
3752 Sometimes the JTAG speed is
3753 changed during the target initialization process: (1) slow at
3754 reset, (2) program the CPU clocks, (3) run fast.
3755 Both the "slow" and "fast" clock rates are functions of the
3756 oscillators used, the chip, the board design, and sometimes
3757 power management software that may be active.
3758
3759 The speed used during reset, and the scan chain verification which
3760 follows reset, can be adjusted using a @code{reset-start}
3761 target event handler.
3762 It can then be reconfigured to a faster speed by a
3763 @code{reset-init} target event handler after it reprograms those
3764 CPU clocks, or manually (if something else, such as a boot loader,
3765 sets up those clocks).
3766 @xref{targetevents,,Target Events}.
3767 When the initial low JTAG speed is a chip characteristic, perhaps
3768 because of a required oscillator speed, provide such a handler
3769 in the target config file.
3770 When that speed is a function of a board-specific characteristic
3771 such as which speed oscillator is used, it belongs in the board
3772 config file instead.
3773 In both cases it's safest to also set the initial JTAG clock rate
3774 to that same slow speed, so that OpenOCD never starts up using a
3775 clock speed that's faster than the scan chain can support.
3776
3777 @example
3778 jtag_rclk 3000
3779 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3780 @end example
3781
3782 If your system supports adaptive clocking (RTCK), configuring
3783 JTAG to use that is probably the most robust approach.
3784 However, it introduces delays to synchronize clocks; so it
3785 may not be the fastest solution.
3786
3787 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3788 instead of @command{adapter speed}, but only for (ARM) cores and boards
3789 which support adaptive clocking.
3790
3791 @deffn {Command} {adapter speed} max_speed_kHz
3792 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3793 JTAG interfaces usually support a limited number of
3794 speeds. The speed actually used won't be faster
3795 than the speed specified.
3796
3797 Chip data sheets generally include a top JTAG clock rate.
3798 The actual rate is often a function of a CPU core clock,
3799 and is normally less than that peak rate.
3800 For example, most ARM cores accept at most one sixth of the CPU clock.
3801
3802 Speed 0 (khz) selects RTCK method.
3803 @xref{faqrtck,,FAQ RTCK}.
3804 If your system uses RTCK, you won't need to change the
3805 JTAG clocking after setup.
3806 Not all interfaces, boards, or targets support ``rtck''.
3807 If the interface device can not
3808 support it, an error is returned when you try to use RTCK.
3809 @end deffn
3810
3811 @defun jtag_rclk fallback_speed_kHz
3812 @cindex adaptive clocking
3813 @cindex RTCK
3814 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3815 If that fails (maybe the interface, board, or target doesn't
3816 support it), falls back to the specified frequency.
3817 @example
3818 # Fall back to 3mhz if RTCK is not supported
3819 jtag_rclk 3000
3820 @end example
3821 @end defun
3822
3823 @node Reset Configuration
3824 @chapter Reset Configuration
3825 @cindex Reset Configuration
3826
3827 Every system configuration may require a different reset
3828 configuration. This can also be quite confusing.
3829 Resets also interact with @var{reset-init} event handlers,
3830 which do things like setting up clocks and DRAM, and
3831 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3832 They can also interact with JTAG routers.
3833 Please see the various board files for examples.
3834
3835 @quotation Note
3836 To maintainers and integrators:
3837 Reset configuration touches several things at once.
3838 Normally the board configuration file
3839 should define it and assume that the JTAG adapter supports
3840 everything that's wired up to the board's JTAG connector.
3841
3842 However, the target configuration file could also make note
3843 of something the silicon vendor has done inside the chip,
3844 which will be true for most (or all) boards using that chip.
3845 And when the JTAG adapter doesn't support everything, the
3846 user configuration file will need to override parts of
3847 the reset configuration provided by other files.
3848 @end quotation
3849
3850 @section Types of Reset
3851
3852 There are many kinds of reset possible through JTAG, but
3853 they may not all work with a given board and adapter.
3854 That's part of why reset configuration can be error prone.
3855
3856 @itemize @bullet
3857 @item
3858 @emph{System Reset} ... the @emph{SRST} hardware signal
3859 resets all chips connected to the JTAG adapter, such as processors,
3860 power management chips, and I/O controllers. Normally resets triggered
3861 with this signal behave exactly like pressing a RESET button.
3862 @item
3863 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3864 just the TAP controllers connected to the JTAG adapter.
3865 Such resets should not be visible to the rest of the system; resetting a
3866 device's TAP controller just puts that controller into a known state.
3867 @item
3868 @emph{Emulation Reset} ... many devices can be reset through JTAG
3869 commands. These resets are often distinguishable from system
3870 resets, either explicitly (a "reset reason" register says so)
3871 or implicitly (not all parts of the chip get reset).
3872 @item
3873 @emph{Other Resets} ... system-on-chip devices often support
3874 several other types of reset.
3875 You may need to arrange that a watchdog timer stops
3876 while debugging, preventing a watchdog reset.
3877 There may be individual module resets.
3878 @end itemize
3879
3880 In the best case, OpenOCD can hold SRST, then reset
3881 the TAPs via TRST and send commands through JTAG to halt the
3882 CPU at the reset vector before the 1st instruction is executed.
3883 Then when it finally releases the SRST signal, the system is
3884 halted under debugger control before any code has executed.
3885 This is the behavior required to support the @command{reset halt}
3886 and @command{reset init} commands; after @command{reset init} a
3887 board-specific script might do things like setting up DRAM.
3888 (@xref{resetcommand,,Reset Command}.)
3889
3890 @anchor{srstandtrstissues}
3891 @section SRST and TRST Issues
3892
3893 Because SRST and TRST are hardware signals, they can have a
3894 variety of system-specific constraints. Some of the most
3895 common issues are:
3896
3897 @itemize @bullet
3898
3899 @item @emph{Signal not available} ... Some boards don't wire
3900 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3901 support such signals even if they are wired up.
3902 Use the @command{reset_config} @var{signals} options to say
3903 when either of those signals is not connected.
3904 When SRST is not available, your code might not be able to rely
3905 on controllers having been fully reset during code startup.
3906 Missing TRST is not a problem, since JTAG-level resets can
3907 be triggered using with TMS signaling.
3908
3909 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3910 adapter will connect SRST to TRST, instead of keeping them separate.
3911 Use the @command{reset_config} @var{combination} options to say
3912 when those signals aren't properly independent.
3913
3914 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3915 delay circuit, reset supervisor, or on-chip features can extend
3916 the effect of a JTAG adapter's reset for some time after the adapter
3917 stops issuing the reset. For example, there may be chip or board
3918 requirements that all reset pulses last for at least a
3919 certain amount of time; and reset buttons commonly have
3920 hardware debouncing.
3921 Use the @command{adapter srst delay} and @command{jtag_ntrst_delay}
3922 commands to say when extra delays are needed.
3923
3924 @item @emph{Drive type} ... Reset lines often have a pullup
3925 resistor, letting the JTAG interface treat them as open-drain
3926 signals. But that's not a requirement, so the adapter may need
3927 to use push/pull output drivers.
3928 Also, with weak pullups it may be advisable to drive
3929 signals to both levels (push/pull) to minimize rise times.
3930 Use the @command{reset_config} @var{trst_type} and
3931 @var{srst_type} parameters to say how to drive reset signals.
3932
3933 @item @emph{Special initialization} ... Targets sometimes need
3934 special JTAG initialization sequences to handle chip-specific
3935 issues (not limited to errata).
3936 For example, certain JTAG commands might need to be issued while
3937 the system as a whole is in a reset state (SRST active)
3938 but the JTAG scan chain is usable (TRST inactive).
3939 Many systems treat combined assertion of SRST and TRST as a
3940 trigger for a harder reset than SRST alone.
3941 Such custom reset handling is discussed later in this chapter.
3942 @end itemize
3943
3944 There can also be other issues.
3945 Some devices don't fully conform to the JTAG specifications.
3946 Trivial system-specific differences are common, such as
3947 SRST and TRST using slightly different names.
3948 There are also vendors who distribute key JTAG documentation for
3949 their chips only to developers who have signed a Non-Disclosure
3950 Agreement (NDA).
3951
3952 Sometimes there are chip-specific extensions like a requirement to use
3953 the normally-optional TRST signal (precluding use of JTAG adapters which
3954 don't pass TRST through), or needing extra steps to complete a TAP reset.
3955
3956 In short, SRST and especially TRST handling may be very finicky,
3957 needing to cope with both architecture and board specific constraints.
3958
3959 @section Commands for Handling Resets
3960
3961 @deffn {Command} {adapter srst pulse_width} milliseconds
3962 Minimum amount of time (in milliseconds) OpenOCD should wait
3963 after asserting nSRST (active-low system reset) before
3964 allowing it to be deasserted.
3965 @end deffn
3966
3967 @deffn {Command} {adapter srst delay} milliseconds
3968 How long (in milliseconds) OpenOCD should wait after deasserting
3969 nSRST (active-low system reset) before starting new JTAG operations.
3970 When a board has a reset button connected to SRST line it will
3971 probably have hardware debouncing, implying you should use this.
3972 @end deffn
3973
3974 @deffn {Command} {jtag_ntrst_assert_width} milliseconds
3975 Minimum amount of time (in milliseconds) OpenOCD should wait
3976 after asserting nTRST (active-low JTAG TAP reset) before
3977 allowing it to be deasserted.
3978 @end deffn
3979
3980 @deffn {Command} {jtag_ntrst_delay} milliseconds
3981 How long (in milliseconds) OpenOCD should wait after deasserting
3982 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3983 @end deffn
3984
3985 @anchor{reset_config}
3986 @deffn {Command} {reset_config} mode_flag ...
3987 This command displays or modifies the reset configuration
3988 of your combination of JTAG board and target in target
3989 configuration scripts.
3990
3991 Information earlier in this section describes the kind of problems
3992 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3993 As a rule this command belongs only in board config files,
3994 describing issues like @emph{board doesn't connect TRST};
3995 or in user config files, addressing limitations derived
3996 from a particular combination of interface and board.
3997 (An unlikely example would be using a TRST-only adapter
3998 with a board that only wires up SRST.)
3999
4000 The @var{mode_flag} options can be specified in any order, but only one
4001 of each type -- @var{signals}, @var{combination}, @var{gates},
4002 @var{trst_type}, @var{srst_type} and @var{connect_type}
4003 -- may be specified at a time.
4004 If you don't provide a new value for a given type, its previous
4005 value (perhaps the default) is unchanged.
4006 For example, this means that you don't need to say anything at all about
4007 TRST just to declare that if the JTAG adapter should want to drive SRST,
4008 it must explicitly be driven high (@option{srst_push_pull}).
4009
4010 @itemize
4011 @item
4012 @var{signals} can specify which of the reset signals are connected.
4013 For example, If the JTAG interface provides SRST, but the board doesn't
4014 connect that signal properly, then OpenOCD can't use it.
4015 Possible values are @option{none} (the default), @option{trst_only},
4016 @option{srst_only} and @option{trst_and_srst}.
4017
4018 @quotation Tip
4019 If your board provides SRST and/or TRST through the JTAG connector,
4020 you must declare that so those signals can be used.
4021 @end quotation
4022
4023 @item
4024 The @var{combination} is an optional value specifying broken reset
4025 signal implementations.
4026 The default behaviour if no option given is @option{separate},
4027 indicating everything behaves normally.
4028 @option{srst_pulls_trst} states that the
4029 test logic is reset together with the reset of the system (e.g. NXP
4030 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
4031 the system is reset together with the test logic (only hypothetical, I
4032 haven't seen hardware with such a bug, and can be worked around).
4033 @option{combined} implies both @option{srst_pulls_trst} and
4034 @option{trst_pulls_srst}.
4035
4036 @item
4037 The @var{gates} tokens control flags that describe some cases where
4038 JTAG may be unavailable during reset.
4039 @option{srst_gates_jtag} (default)
4040 indicates that asserting SRST gates the
4041 JTAG clock. This means that no communication can happen on JTAG
4042 while SRST is asserted.
4043 Its converse is @option{srst_nogate}, indicating that JTAG commands
4044 can safely be issued while SRST is active.
4045
4046 @item
4047 The @var{connect_type} tokens control flags that describe some cases where
4048 SRST is asserted while connecting to the target. @option{srst_nogate}
4049 is required to use this option.
4050 @option{connect_deassert_srst} (default)
4051 indicates that SRST will not be asserted while connecting to the target.
4052 Its converse is @option{connect_assert_srst}, indicating that SRST will
4053 be asserted before any target connection.
4054 Only some targets support this feature, STM32 and STR9 are examples.
4055 This feature is useful if you are unable to connect to your target due
4056 to incorrect options byte config or illegal program execution.
4057 @end itemize
4058
4059 The optional @var{trst_type} and @var{srst_type} parameters allow the
4060 driver mode of each reset line to be specified. These values only affect
4061 JTAG interfaces with support for different driver modes, like the Amontec
4062 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
4063 relevant signal (TRST or SRST) is not connected.
4064
4065 @itemize
4066 @item
4067 Possible @var{trst_type} driver modes for the test reset signal (TRST)
4068 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
4069 Most boards connect this signal to a pulldown, so the JTAG TAPs
4070 never leave reset unless they are hooked up to a JTAG adapter.
4071
4072 @item
4073 Possible @var{srst_type} driver modes for the system reset signal (SRST)
4074 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
4075 Most boards connect this signal to a pullup, and allow the
4076 signal to be pulled low by various events including system
4077 power-up and pressing a reset button.
4078 @end itemize
4079 @end deffn
4080
4081 @section Custom Reset Handling
4082 @cindex events
4083
4084 OpenOCD has several ways to help support the various reset
4085 mechanisms provided by chip and board vendors.
4086 The commands shown in the previous section give standard parameters.
4087 There are also @emph{event handlers} associated with TAPs or Targets.
4088 Those handlers are Tcl procedures you can provide, which are invoked
4089 at particular points in the reset sequence.
4090
4091 @emph{When SRST is not an option} you must set
4092 up a @code{reset-assert} event handler for your target.
4093 For example, some JTAG adapters don't include the SRST signal;
4094 and some boards have multiple targets, and you won't always
4095 want to reset everything at once.
4096
4097 After configuring those mechanisms, you might still
4098 find your board doesn't start up or reset correctly.
4099 For example, maybe it needs a slightly different sequence
4100 of SRST and/or TRST manipulations, because of quirks that
4101 the @command{reset_config} mechanism doesn't address;
4102 or asserting both might trigger a stronger reset, which
4103 needs special attention.
4104
4105 Experiment with lower level operations, such as
4106 @command{adapter assert}, @command{adapter deassert}
4107 and the @command{jtag arp_*} operations shown here,
4108 to find a sequence of operations that works.
4109 @xref{JTAG Commands}.
4110 When you find a working sequence, it can be used to override
4111 @command{jtag_init}, which fires during OpenOCD startup
4112 (@pxref{configurationstage,,Configuration Stage});
4113 or @command{init_reset}, which fires during reset processing.
4114
4115 You might also want to provide some project-specific reset
4116 schemes. For example, on a multi-target board the standard
4117 @command{reset} command would reset all targets, but you
4118 may need the ability to reset only one target at time and
4119 thus want to avoid using the board-wide SRST signal.
4120
4121 @deffn {Overridable Procedure} {init_reset} mode
4122 This is invoked near the beginning of the @command{reset} command,
4123 usually to provide as much of a cold (power-up) reset as practical.
4124 By default it is also invoked from @command{jtag_init} if
4125 the scan chain does not respond to pure JTAG operations.
4126 The @var{mode} parameter is the parameter given to the
4127 low level reset command (@option{halt},
4128 @option{init}, or @option{run}), @option{setup},
4129 or potentially some other value.
4130
4131 The default implementation just invokes @command{jtag arp_init-reset}.
4132 Replacements will normally build on low level JTAG
4133 operations such as @command{adapter assert} and @command{adapter deassert}.
4134 Operations here must not address individual TAPs
4135 (or their associated targets)
4136 until the JTAG scan chain has first been verified to work.
4137
4138 Implementations must have verified the JTAG scan chain before
4139 they return.
4140 This is done by calling @command{jtag arp_init}
4141 (or @command{jtag arp_init-reset}).
4142 @end deffn
4143
4144 @deffn {Command} {jtag arp_init}
4145 This validates the scan chain using just the four
4146 standard JTAG signals (TMS, TCK, TDI, TDO).
4147 It starts by issuing a JTAG-only reset.
4148 Then it performs checks to verify that the scan chain configuration
4149 matches the TAPs it can observe.
4150 Those checks include checking IDCODE values for each active TAP,
4151 and verifying the length of their instruction registers using
4152 TAP @code{-ircapture} and @code{-irmask} values.
4153 If these tests all pass, TAP @code{setup} events are
4154 issued to all TAPs with handlers for that event.
4155 @end deffn
4156
4157 @deffn {Command} {jtag arp_init-reset}
4158 This uses TRST and SRST to try resetting
4159 everything on the JTAG scan chain
4160 (and anything else connected to SRST).
4161 It then invokes the logic of @command{jtag arp_init}.
4162 @end deffn
4163
4164
4165 @node TAP Declaration
4166 @chapter TAP Declaration
4167 @cindex TAP declaration
4168 @cindex TAP configuration
4169
4170 @emph{Test Access Ports} (TAPs) are the core of JTAG.
4171 TAPs serve many roles, including: