docs: add initial target rtos support info
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * TFTP:: TFTP
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on:
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
94 @end menu
96 @node About
97 @unnumbered About
98 @cindex about
100 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
101 University of Applied Sciences Augsburg (@uref{}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
104 around the world.
106 @section What is OpenOCD?
107 @cindex TAP
108 @cindex JTAG
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
112 devices.
114 It does so with the assistance of a @dfn{debug adapter}, which is
115 a small hardware module which helps provide the right kind of
116 electrical signaling to the target being debugged. These are
117 required since the debug host (on which OpenOCD runs) won't
118 usually have native support for such signaling, or the connector
119 needed to hook up to the target.
121 Such debug adapters support one or more @dfn{transport} protocols,
122 each of which involves different electrical signaling (and uses
123 different messaging protocols on top of that signaling). There
124 are many types of debug adapter, and little uniformity in what
125 they are called. (There are also product naming differences.)
127 These adapters are sometimes packaged as discrete dongles, which
128 may generically be called @dfn{hardware interface dongles}.
129 Some development boards also integrate them directly, which may
130 let the development board can be directly connected to the debug
131 host over USB (and sometimes also to power it over USB).
133 For example, a @dfn{JTAG Adapter} supports JTAG
134 signaling, and is used to communicate
135 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
136 A @dfn{TAP} is a ``Test Access Port'', a module which processes
137 special instructions and data. TAPs are daisy-chained within and
138 between chips and boards. JTAG supports debugging and boundary
139 scan operations.
141 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
142 signaling to communicate with some newer ARM cores, as well as debug
143 adapters which support both JTAG and SWD transports. SWD only supports
144 debugging, whereas JTAG also supports boundary scan operations.
146 For some chips, there are also @dfn{Programming Adapters} supporting
147 special transports used only to write code to flash memory, without
148 support for on-chip debugging or boundary scan.
149 (At this writing, OpenOCD does not support such non-debug adapters.)
152 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
153 based, parallel port based, and other standalone boxes that run
154 OpenOCD internally. @xref{Debug Adapter Hardware}.
156 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
157 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
158 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
159 debugged via the GDB protocol.
161 @b{Flash Programing:} Flash writing is supported for external CFI
162 compatible NOR flashes (Intel and AMD/Spansion command set) and several
163 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
164 STM32x). Preliminary support for various NAND flash controllers
165 (LPC3180, Orion, S3C24xx, more) controller is included.
167 @section OpenOCD Web Site
169 The OpenOCD web site provides the latest public news from the community:
171 @uref{}
173 @section Latest User's Guide:
175 The user's guide you are now reading may not be the latest one
176 available. A version for more recent code may be available.
177 Its HTML form is published irregularly at:
179 @uref{}
181 PDF form is likewise published at:
183 @uref{}
185 @section OpenOCD User's Forum
187 There is an OpenOCD forum (phpBB) hosted by SparkFun,
188 which might be helpful to you. Note that if you want
189 anything to come to the attention of developers, you
190 should post it to the OpenOCD Developer Mailing List
191 instead of this forum.
193 @uref{}
196 @node Developers
197 @chapter OpenOCD Developer Resources
198 @cindex developers
200 If you are interested in improving the state of OpenOCD's debugging and
201 testing support, new contributions will be welcome. Motivated developers
202 can produce new target, flash or interface drivers, improve the
203 documentation, as well as more conventional bug fixes and enhancements.
205 The resources in this chapter are available for developers wishing to explore
206 or expand the OpenOCD source code.
208 @section OpenOCD GIT Repository
210 During the 0.3.x release cycle, OpenOCD switched from Subversion to
211 a GIT repository hosted at SourceForge. The repository URL is:
213 @uref{git://}
215 You may prefer to use a mirror and the HTTP protocol:
217 @uref{}
219 With standard GIT tools, use @command{git clone} to initialize
220 a local repository, and @command{git pull} to update it.
221 There are also gitweb pages letting you browse the repository
222 with a web browser, or download arbitrary snapshots without
223 needing a GIT client:
225 @uref{}
227 @uref{}
229 The @file{README} file contains the instructions for building the project
230 from the repository or a snapshot.
232 Developers that want to contribute patches to the OpenOCD system are
233 @b{strongly} encouraged to work against mainline.
234 Patches created against older versions may require additional
235 work from their submitter in order to be updated for newer releases.
237 @section Doxygen Developer Manual
239 During the 0.2.x release cycle, the OpenOCD project began
240 providing a Doxygen reference manual. This document contains more
241 technical information about the software internals, development
242 processes, and similar documentation:
244 @uref{}
246 This document is a work-in-progress, but contributions would be welcome
247 to fill in the gaps. All of the source files are provided in-tree,
248 listed in the Doxyfile configuration in the top of the source tree.
250 @section OpenOCD Developer Mailing List
252 The OpenOCD Developer Mailing List provides the primary means of
253 communication between developers:
255 @uref{}
257 Discuss and submit patches to this list.
258 The @file{HACKING} file contains basic information about how
259 to prepare patches.
261 @section OpenOCD Bug Database
263 During the 0.4.x release cycle the OpenOCD project team began
264 using Trac for its bug database:
266 @uref{}
269 @node Debug Adapter Hardware
270 @chapter Debug Adapter Hardware
271 @cindex dongles
272 @cindex FTDI
273 @cindex wiggler
274 @cindex zy1000
275 @cindex printer port
276 @cindex USB Adapter
277 @cindex RTCK
279 Defined: @b{dongle}: A small device that plugins into a computer and serves as
280 an adapter .... [snip]
282 In the OpenOCD case, this generally refers to @b{a small adapter} that
283 attaches to your computer via USB or the Parallel Printer Port. One
284 exception is the Zylin ZY1000, packaged as a small box you attach via
285 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
286 require any drivers to be installed on the developer PC. It also has
287 a built in web interface. It supports RTCK/RCLK or adaptive clocking
288 and has a built in relay to power cycle targets remotely.
291 @section Choosing a Dongle
293 There are several things you should keep in mind when choosing a dongle.
295 @enumerate
296 @item @b{Transport} Does it support the kind of communication that you need?
297 OpenOCD focusses mostly on JTAG. Your version may also support
298 other ways to communicate with target devices.
299 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
300 Does your dongle support it? You might need a level converter.
301 @item @b{Pinout} What pinout does your target board use?
302 Does your dongle support it? You may be able to use jumper
303 wires, or an "octopus" connector, to convert pinouts.
304 @item @b{Connection} Does your computer have the USB, printer, or
305 Ethernet port needed?
306 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
307 RTCK support? Also known as ``adaptive clocking''
308 @end enumerate
310 @section Stand alone Systems
312 @b{ZY1000} See: @url{} Technically, not a
313 dongle, but a standalone box. The ZY1000 has the advantage that it does
314 not require any drivers installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built in relay to power cycle targets remotely.
318 @section USB FT2232 Based
320 There are many USB JTAG dongles on the market, many of them are based
321 on a chip from ``Future Technology Devices International'' (FTDI)
322 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
323 See: @url{} for more information.
324 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
325 chips are starting to become available in JTAG adapters. (Adapters
326 using those high speed FT2232H chips may support adaptive clocking.)
328 The FT2232 chips are flexible enough to support some other
329 transport options, such as SWD or the SPI variants used to
330 program some chips. They have two communications channels,
331 and one can be used for a UART adapter at the same time the
332 other one is used to provide a debug adapter.
334 Also, some development boards integrate an FT2232 chip to serve as
335 a built-in low cost debug adapter and usb-to-serial solution.
337 @itemize @bullet
338 @item @b{usbjtag}
339 @* Link @url{}
340 @item @b{jtagkey}
341 @* See: @url{}
342 @item @b{jtagkey2}
343 @* See: @url{}
344 @item @b{oocdlink}
345 @* See: @url{} By Joern Kaipf
346 @item @b{signalyzer}
347 @* See: @url{}
348 @item @b{Stellaris Eval Boards}
349 @* See: @url{} - The Stellaris eval boards
350 bundle FT2232-based JTAG and SWD support, which can be used to debug
351 the Stellaris chips. Using separate JTAG adapters is optional.
352 These boards can also be used in a "pass through" mode as JTAG adapters
353 to other target boards, disabling the Stellaris chip.
354 @item @b{Luminary ICDI}
355 @* See: @url{} - Luminary In-Circuit Debug
356 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
357 Evaluation Kits. Like the non-detachable FT2232 support on the other
358 Stellaris eval boards, they can be used to debug other target boards.
359 @item @b{olimex-jtag}
360 @* See: @url{}
361 @item @b{Flyswatter/Flyswatter2}
362 @* See: @url{}
363 @item @b{turtelizer2}
364 @* See:
365 @uref{, Turtelizer 2}, or
366 @url{}
367 @item @b{comstick}
368 @* Link: @url{}
369 @item @b{stm32stick}
370 @* Link @url{}
371 @item @b{axm0432_jtag}
372 @* Axiom AXM-0432 Link @url{} - NOTE: This JTAG does not appear
373 to be available anymore as of April 2012.
374 @item @b{cortino}
375 @* Link @url{}
376 @item @b{dlp-usb1232h}
377 @* Link @url{}
378 @item @b{digilent-hs1}
379 @* Link @url{}
380 @end itemize
382 @section USB-JTAG / Altera USB-Blaster compatibles
384 These devices also show up as FTDI devices, but are not
385 protocol-compatible with the FT2232 devices. They are, however,
386 protocol-compatible among themselves. USB-JTAG devices typically consist
387 of a FT245 followed by a CPLD that understands a particular protocol,
388 or emulate this protocol using some other hardware.
390 They may appear under different USB VID/PID depending on the particular
391 product. The driver can be configured to search for any VID/PID pair
392 (see the section on driver commands).
394 @itemize
395 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
396 @* Link: @url{}
397 @item @b{Altera USB-Blaster}
398 @* Link: @url{}
399 @end itemize
401 @section USB JLINK based
402 There are several OEM versions of the Segger @b{JLINK} adapter. It is
403 an example of a micro controller based JTAG adapter, it uses an
404 AT91SAM764 internally.
406 @itemize @bullet
407 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
408 @* Link: @url{}
409 @item @b{SEGGER JLINK}
410 @* Link: @url{}
411 @item @b{IAR J-Link}
412 @* Link: @url{}
413 @end itemize
415 @section USB RLINK based
416 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
418 @itemize @bullet
419 @item @b{Raisonance RLink}
420 @* Link: @url{}
421 @item @b{STM32 Primer}
422 @* Link: @url{}
423 @item @b{STM32 Primer2}
424 @* Link: @url{}
425 @end itemize
427 @section USB ST-LINK based
428 ST Micro has an adapter called @b{ST-LINK}.
429 They only work with ST Micro chips, notably STM32 and STM8.
431 @itemize @bullet
432 @item @b{ST-LINK}
433 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
434 @* Link: @url{}
435 @item @b{ST-LINK/V2}
436 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
437 @* Link: @url{}
438 @end itemize
440 For info the original ST-LINK enumerates using the mass storage usb class, however
441 it's implementation is completely broken. The result is this causes issues under linux.
442 The simplest solution is to get linux to ignore the ST-LINK using one of the following methods:
443 @itemize @bullet
444 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
445 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
446 @end itemize
448 @section USB Other
449 @itemize @bullet
450 @item @b{USBprog}
451 @* Link: @url{} - which uses an Atmel MEGA32 and a UBN9604
453 @item @b{USB - Presto}
454 @* Link: @url{}
456 @item @b{Versaloon-Link}
457 @* Link: @url{}
459 @item @b{ARM-JTAG-EW}
460 @* Link: @url{}
462 @item @b{Buspirate}
463 @* Link: @url{}
465 @item @b{opendous}
466 @* Link: @url{}
468 @item @b{estick}
469 @* Link: @url{}
470 @end itemize
472 @section IBM PC Parallel Printer Port Based
474 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
475 and the Macraigor Wiggler. There are many clones and variations of
476 these on the market.
478 Note that parallel ports are becoming much less common, so if you
479 have the choice you should probably avoid these adapters in favor
480 of USB-based ones.
482 @itemize @bullet
484 @item @b{Wiggler} - There are many clones of this.
485 @* Link: @url{}
487 @item @b{DLC5} - From XILINX - There are many clones of this
488 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
489 produced, PDF schematics are easily found and it is easy to make.
491 @item @b{Amontec - JTAG Accelerator}
492 @* Link: @url{}
494 @item @b{GW16402}
495 @* Link: @url{}
497 @item @b{Wiggler2}
498 @* Link: @url{}
500 @item @b{Wiggler_ntrst_inverted}
501 @* Yet another variation - See the source code, src/jtag/parport.c
503 @item @b{old_amt_wiggler}
504 @* Unknown - probably not on the market today
506 @item @b{arm-jtag}
507 @* Link: Most likely @url{} [another wiggler clone]
509 @item @b{chameleon}
510 @* Link: @url{}
512 @item @b{Triton}
513 @* Unknown.
515 @item @b{Lattice}
516 @* ispDownload from Lattice Semiconductor
517 @url{}
519 @item @b{flashlink}
520 @* From ST Microsystems;
521 @* Link: @url{}
523 @end itemize
525 @section Other...
526 @itemize @bullet
528 @item @b{ep93xx}
529 @* An EP93xx based Linux machine using the GPIO pins directly.
531 @item @b{at91rm9200}
532 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
534 @end itemize
536 @node About Jim-Tcl
537 @chapter About Jim-Tcl
538 @cindex Jim-Tcl
539 @cindex tcl
541 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
542 This programming language provides a simple and extensible
543 command interpreter.
545 All commands presented in this Guide are extensions to Jim-Tcl.
546 You can use them as simple commands, without needing to learn
547 much of anything about Tcl.
548 Alternatively, can write Tcl programs with them.
550 You can learn more about Jim at its website, @url{}.
551 There is an active and responsive community, get on the mailing list
552 if you have any questions. Jim-Tcl maintainers also lurk on the
553 OpenOCD mailing list.
555 @itemize @bullet
556 @item @b{Jim vs. Tcl}
557 @* Jim-Tcl is a stripped down version of the well known Tcl language,
558 which can be found here: @url{}. Jim-Tcl has far
559 fewer features. Jim-Tcl is several dozens of .C files and .H files and
560 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
561 4.2 MB .zip file containing 1540 files.
563 @item @b{Missing Features}
564 @* Our practice has been: Add/clone the real Tcl feature if/when
565 needed. We welcome Jim-Tcl improvements, not bloat. Also there
566 are a large number of optional Jim-Tcl features that are not
567 enabled in OpenOCD.
569 @item @b{Scripts}
570 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
571 command interpreter today is a mixture of (newer)
572 Jim-Tcl commands, and (older) the orginal command interpreter.
574 @item @b{Commands}
575 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
576 can type a Tcl for() loop, set variables, etc.
577 Some of the commands documented in this guide are implemented
578 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
580 @item @b{Historical Note}
581 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
582 before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
583 as a git submodule, which greatly simplified upgrading Jim Tcl
584 to benefit from new features and bugfixes in Jim Tcl.
586 @item @b{Need a crash course in Tcl?}
587 @*@xref{Tcl Crash Course}.
588 @end itemize
590 @node Running
591 @chapter Running
592 @cindex command line options
593 @cindex logfile
594 @cindex directory search
596 Properly installing OpenOCD sets up your operating system to grant it access
597 to the debug adapters. On Linux, this usually involves installing a file
598 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
599 complex and confusing driver configuration for every peripheral. Such issues
600 are unique to each operating system, and are not detailed in this User's Guide.
602 Then later you will invoke the OpenOCD server, with various options to
603 tell it how each debug session should work.
604 The @option{--help} option shows:
605 @verbatim
606 bash$ openocd --help
608 --help | -h display this help
609 --version | -v display OpenOCD version
610 --file | -f use configuration file <name>
611 --search | -s dir to search for config files and scripts
612 --debug | -d set debug level <0-3>
613 --log_output | -l redirect log output to file <name>
614 --command | -c run <command>
615 @end verbatim
617 If you don't give any @option{-f} or @option{-c} options,
618 OpenOCD tries to read the configuration file @file{openocd.cfg}.
619 To specify one or more different
620 configuration files, use @option{-f} options. For example:
622 @example
623 openocd -f config1.cfg -f config2.cfg -f config3.cfg
624 @end example
626 Configuration files and scripts are searched for in
627 @enumerate
628 @item the current directory,
629 @item any search dir specified on the command line using the @option{-s} option,
630 @item any search dir specified using the @command{add_script_search_dir} command,
631 @item @file{$HOME/.openocd} (not on Windows),
632 @item the site wide script library @file{$pkgdatadir/site} and
633 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
634 @end enumerate
635 The first found file with a matching file name will be used.
637 @quotation Note
638 Don't try to use configuration script names or paths which
639 include the "#" character. That character begins Tcl comments.
640 @end quotation
642 @section Simple setup, no customization
644 In the best case, you can use two scripts from one of the script
645 libraries, hook up your JTAG adapter, and start the server ... and
646 your JTAG setup will just work "out of the box". Always try to
647 start by reusing those scripts, but assume you'll need more
648 customization even if this works. @xref{OpenOCD Project Setup}.
650 If you find a script for your JTAG adapter, and for your board or
651 target, you may be able to hook up your JTAG adapter then start
652 the server like:
654 @example
655 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
656 @end example
658 You might also need to configure which reset signals are present,
659 using @option{-c 'reset_config trst_and_srst'} or something similar.
660 If all goes well you'll see output something like
662 @example
663 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
664 For bug reports, read
666 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
667 (mfg: 0x23b, part: 0xba00, ver: 0x3)
668 @end example
670 Seeing that "tap/device found" message, and no warnings, means
671 the JTAG communication is working. That's a key milestone, but
672 you'll probably need more project-specific setup.
674 @section What OpenOCD does as it starts
676 OpenOCD starts by processing the configuration commands provided
677 on the command line or, if there were no @option{-c command} or
678 @option{-f file.cfg} options given, in @file{openocd.cfg}.
679 @xref{Configuration Stage}.
680 At the end of the configuration stage it verifies the JTAG scan
681 chain defined using those commands; your configuration should
682 ensure that this always succeeds.
683 Normally, OpenOCD then starts running as a daemon.
684 Alternatively, commands may be used to terminate the configuration
685 stage early, perform work (such as updating some flash memory),
686 and then shut down without acting as a daemon.
688 Once OpenOCD starts running as a daemon, it waits for connections from
689 clients (Telnet, GDB, Other) and processes the commands issued through
690 those channels.
692 If you are having problems, you can enable internal debug messages via
693 the @option{-d} option.
695 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
696 @option{-c} command line switch.
698 To enable debug output (when reporting problems or working on OpenOCD
699 itself), use the @option{-d} command line switch. This sets the
700 @option{debug_level} to "3", outputting the most information,
701 including debug messages. The default setting is "2", outputting only
702 informational messages, warnings and errors. You can also change this
703 setting from within a telnet or gdb session using @command{debug_level
704 <n>} (@pxref{debug_level}).
706 You can redirect all output from the daemon to a file using the
707 @option{-l <logfile>} switch.
709 Note! OpenOCD will launch the GDB & telnet server even if it can not
710 establish a connection with the target. In general, it is possible for
711 the JTAG controller to be unresponsive until the target is set up
712 correctly via e.g. GDB monitor commands in a GDB init script.
714 @node OpenOCD Project Setup
715 @chapter OpenOCD Project Setup
717 To use OpenOCD with your development projects, you need to do more than
718 just connecting the JTAG adapter hardware (dongle) to your development board
719 and then starting the OpenOCD server.
720 You also need to configure that server so that it knows
721 about that adapter and board, and helps your work.
722 You may also want to connect OpenOCD to GDB, possibly
723 using Eclipse or some other GUI.
725 @section Hooking up the JTAG Adapter
727 Today's most common case is a dongle with a JTAG cable on one side
728 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
729 and a USB cable on the other.
730 Instead of USB, some cables use Ethernet;
731 older ones may use a PC parallel port, or even a serial port.
733 @enumerate
734 @item @emph{Start with power to your target board turned off},
735 and nothing connected to your JTAG adapter.
736 If you're particularly paranoid, unplug power to the board.
737 It's important to have the ground signal properly set up,
738 unless you are using a JTAG adapter which provides
739 galvanic isolation between the target board and the
740 debugging host.
742 @item @emph{Be sure it's the right kind of JTAG connector.}
743 If your dongle has a 20-pin ARM connector, you need some kind
744 of adapter (or octopus, see below) to hook it up to
745 boards using 14-pin or 10-pin connectors ... or to 20-pin
746 connectors which don't use ARM's pinout.
748 In the same vein, make sure the voltage levels are compatible.
749 Not all JTAG adapters have the level shifters needed to work
750 with 1.2 Volt boards.
752 @item @emph{Be certain the cable is properly oriented} or you might
753 damage your board. In most cases there are only two possible
754 ways to connect the cable.
755 Connect the JTAG cable from your adapter to the board.
756 Be sure it's firmly connected.
758 In the best case, the connector is keyed to physically
759 prevent you from inserting it wrong.
760 This is most often done using a slot on the board's male connector
761 housing, which must match a key on the JTAG cable's female connector.
762 If there's no housing, then you must look carefully and
763 make sure pin 1 on the cable hooks up to pin 1 on the board.
764 Ribbon cables are frequently all grey except for a wire on one
765 edge, which is red. The red wire is pin 1.
767 Sometimes dongles provide cables where one end is an ``octopus'' of
768 color coded single-wire connectors, instead of a connector block.
769 These are great when converting from one JTAG pinout to another,
770 but are tedious to set up.
771 Use these with connector pinout diagrams to help you match up the
772 adapter signals to the right board pins.
774 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
775 A USB, parallel, or serial port connector will go to the host which
776 you are using to run OpenOCD.
777 For Ethernet, consult the documentation and your network administrator.
779 For USB based JTAG adapters you have an easy sanity check at this point:
780 does the host operating system see the JTAG adapter? If that host is an
781 MS-Windows host, you'll need to install a driver before OpenOCD works.
783 @item @emph{Connect the adapter's power supply, if needed.}
784 This step is primarily for non-USB adapters,
785 but sometimes USB adapters need extra power.
787 @item @emph{Power up the target board.}
788 Unless you just let the magic smoke escape,
789 you're now ready to set up the OpenOCD server
790 so you can use JTAG to work with that board.
792 @end enumerate
794 Talk with the OpenOCD server using
795 telnet (@code{telnet localhost 4444} on many systems) or GDB.
796 @xref{GDB and OpenOCD}.
798 @section Project Directory
800 There are many ways you can configure OpenOCD and start it up.
802 A simple way to organize them all involves keeping a
803 single directory for your work with a given board.
804 When you start OpenOCD from that directory,
805 it searches there first for configuration files, scripts,
806 files accessed through semihosting,
807 and for code you upload to the target board.
808 It is also the natural place to write files,
809 such as log files and data you download from the board.
811 @section Configuration Basics
813 There are two basic ways of configuring OpenOCD, and
814 a variety of ways you can mix them.
815 Think of the difference as just being how you start the server:
817 @itemize
818 @item Many @option{-f file} or @option{-c command} options on the command line
819 @item No options, but a @dfn{user config file}
820 in the current directory named @file{openocd.cfg}
821 @end itemize
823 Here is an example @file{openocd.cfg} file for a setup
824 using a Signalyzer FT2232-based JTAG adapter to talk to
825 a board with an Atmel AT91SAM7X256 microcontroller:
827 @example
828 source [find interface/signalyzer.cfg]
830 # GDB can also flash my flash!
831 gdb_memory_map enable
832 gdb_flash_program enable
834 source [find target/sam7x256.cfg]
835 @end example
837 Here is the command line equivalent of that configuration:
839 @example
840 openocd -f interface/signalyzer.cfg \
841 -c "gdb_memory_map enable" \
842 -c "gdb_flash_program enable" \
843 -f target/sam7x256.cfg
844 @end example
846 You could wrap such long command lines in shell scripts,
847 each supporting a different development task.
848 One might re-flash the board with a specific firmware version.
849 Another might set up a particular debugging or run-time environment.
851 @quotation Important
852 At this writing (October 2009) the command line method has
853 problems with how it treats variables.
854 For example, after @option{-c "set VAR value"}, or doing the
855 same in a script, the variable @var{VAR} will have no value
856 that can be tested in a later script.
857 @end quotation
859 Here we will focus on the simpler solution: one user config
860 file, including basic configuration plus any TCL procedures
861 to simplify your work.
863 @section User Config Files
864 @cindex config file, user
865 @cindex user config file
866 @cindex config file, overview
868 A user configuration file ties together all the parts of a project
869 in one place.
870 One of the following will match your situation best:
872 @itemize
873 @item Ideally almost everything comes from configuration files
874 provided by someone else.
875 For example, OpenOCD distributes a @file{scripts} directory
876 (probably in @file{/usr/share/openocd/scripts} on Linux).
877 Board and tool vendors can provide these too, as can individual
878 user sites; the @option{-s} command line option lets you say
879 where to find these files. (@xref{Running}.)
880 The AT91SAM7X256 example above works this way.
882 Three main types of non-user configuration file each have their
883 own subdirectory in the @file{scripts} directory:
885 @enumerate
886 @item @b{interface} -- one for each different debug adapter;
887 @item @b{board} -- one for each different board
888 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
889 @end enumerate
891 Best case: include just two files, and they handle everything else.
892 The first is an interface config file.
893 The second is board-specific, and it sets up the JTAG TAPs and
894 their GDB targets (by deferring to some @file{target.cfg} file),
895 declares all flash memory, and leaves you nothing to do except
896 meet your deadline:
898 @example
899 source [find interface/olimex-jtag-tiny.cfg]
900 source [find board/csb337.cfg]
901 @end example
903 Boards with a single microcontroller often won't need more
904 than the target config file, as in the AT91SAM7X256 example.
905 That's because there is no external memory (flash, DDR RAM), and
906 the board differences are encapsulated by application code.
908 @item Maybe you don't know yet what your board looks like to JTAG.
909 Once you know the @file{interface.cfg} file to use, you may
910 need help from OpenOCD to discover what's on the board.
911 Once you find the JTAG TAPs, you can just search for appropriate
912 target and board
913 configuration files ... or write your own, from the bottom up.
914 @xref{Autoprobing}.
916 @item You can often reuse some standard config files but
917 need to write a few new ones, probably a @file{board.cfg} file.
918 You will be using commands described later in this User's Guide,
919 and working with the guidelines in the next chapter.
921 For example, there may be configuration files for your JTAG adapter
922 and target chip, but you need a new board-specific config file
923 giving access to your particular flash chips.
924 Or you might need to write another target chip configuration file
925 for a new chip built around the Cortex M3 core.
927 @quotation Note
928 When you write new configuration files, please submit
929 them for inclusion in the next OpenOCD release.
930 For example, a @file{board/newboard.cfg} file will help the
931 next users of that board, and a @file{target/newcpu.cfg}
932 will help support users of any board using that chip.
933 @end quotation
935 @item
936 You may may need to write some C code.
937 It may be as simple as a supporting a new ft2232 or parport
938 based adapter; a bit more involved, like a NAND or NOR flash
939 controller driver; or a big piece of work like supporting
940 a new chip architecture.
941 @end itemize
943 Reuse the existing config files when you can.
944 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
945 You may find a board configuration that's a good example to follow.
947 When you write config files, separate the reusable parts
948 (things every user of that interface, chip, or board needs)
949 from ones specific to your environment and debugging approach.
950 @itemize
952 @item
953 For example, a @code{gdb-attach} event handler that invokes
954 the @command{reset init} command will interfere with debugging
955 early boot code, which performs some of the same actions
956 that the @code{reset-init} event handler does.
958 @item
959 Likewise, the @command{arm9 vector_catch} command (or
960 @cindex vector_catch
961 its siblings @command{xscale vector_catch}
962 and @command{cortex_m3 vector_catch}) can be a timesaver
963 during some debug sessions, but don't make everyone use that either.
964 Keep those kinds of debugging aids in your user config file,
965 along with messaging and tracing setup.
966 (@xref{Software Debug Messages and Tracing}.)
968 @item
969 You might need to override some defaults.
970 For example, you might need to move, shrink, or back up the target's
971 work area if your application needs much SRAM.
973 @item
974 TCP/IP port configuration is another example of something which
975 is environment-specific, and should only appear in
976 a user config file. @xref{TCP/IP Ports}.
977 @end itemize
979 @section Project-Specific Utilities
981 A few project-specific utility
982 routines may well speed up your work.
983 Write them, and keep them in your project's user config file.
985 For example, if you are making a boot loader work on a
986 board, it's nice to be able to debug the ``after it's
987 loaded to RAM'' parts separately from the finicky early
988 code which sets up the DDR RAM controller and clocks.
989 A script like this one, or a more GDB-aware sibling,
990 may help:
992 @example
993 proc ramboot @{ @} @{
994 # Reset, running the target's "reset-init" scripts
995 # to initialize clocks and the DDR RAM controller.
996 # Leave the CPU halted.
997 reset init
999 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1000 load_image u-boot.bin 0x20000000
1002 # Start running.
1003 resume 0x20000000
1004 @}
1005 @end example
1007 Then once that code is working you will need to make it
1008 boot from NOR flash; a different utility would help.
1009 Alternatively, some developers write to flash using GDB.
1010 (You might use a similar script if you're working with a flash
1011 based microcontroller application instead of a boot loader.)
1013 @example
1014 proc newboot @{ @} @{
1015 # Reset, leaving the CPU halted. The "reset-init" event
1016 # proc gives faster access to the CPU and to NOR flash;
1017 # "reset halt" would be slower.
1018 reset init
1020 # Write standard version of U-Boot into the first two
1021 # sectors of NOR flash ... the standard version should
1022 # do the same lowlevel init as "reset-init".
1023 flash protect 0 0 1 off
1024 flash erase_sector 0 0 1
1025 flash write_bank 0 u-boot.bin 0x0
1026 flash protect 0 0 1 on
1028 # Reboot from scratch using that new boot loader.
1029 reset run
1030 @}
1031 @end example
1033 You may need more complicated utility procedures when booting
1034 from NAND.
1035 That often involves an extra bootloader stage,
1036 running from on-chip SRAM to perform DDR RAM setup so it can load
1037 the main bootloader code (which won't fit into that SRAM).
1039 Other helper scripts might be used to write production system images,
1040 involving considerably more than just a three stage bootloader.
1042 @section Target Software Changes
1044 Sometimes you may want to make some small changes to the software
1045 you're developing, to help make JTAG debugging work better.
1046 For example, in C or assembly language code you might
1047 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1048 handling issues like:
1050 @itemize @bullet
1052 @item @b{Watchdog Timers}...
1053 Watchog timers are typically used to automatically reset systems if
1054 some application task doesn't periodically reset the timer. (The
1055 assumption is that the system has locked up if the task can't run.)
1056 When a JTAG debugger halts the system, that task won't be able to run
1057 and reset the timer ... potentially causing resets in the middle of
1058 your debug sessions.
1060 It's rarely a good idea to disable such watchdogs, since their usage
1061 needs to be debugged just like all other parts of your firmware.
1062 That might however be your only option.
1064 Look instead for chip-specific ways to stop the watchdog from counting
1065 while the system is in a debug halt state. It may be simplest to set
1066 that non-counting mode in your debugger startup scripts. You may however
1067 need a different approach when, for example, a motor could be physically
1068 damaged by firmware remaining inactive in a debug halt state. That might
1069 involve a type of firmware mode where that "non-counting" mode is disabled
1070 at the beginning then re-enabled at the end; a watchdog reset might fire
1071 and complicate the debug session, but hardware (or people) would be
1072 protected.@footnote{Note that many systems support a "monitor mode" debug
1073 that is a somewhat cleaner way to address such issues. You can think of
1074 it as only halting part of the system, maybe just one task,
1075 instead of the whole thing.
1076 At this writing, January 2010, OpenOCD based debugging does not support
1077 monitor mode debug, only "halt mode" debug.}
1079 @item @b{ARM Semihosting}...
1080 @cindex ARM semihosting
1081 When linked with a special runtime library provided with many
1082 toolchains@footnote{See chapter 8 "Semihosting" in
1083 @uref{,
1084 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1085 The CodeSourcery EABI toolchain also includes a semihosting library.},
1086 your target code can use I/O facilities on the debug host. That library
1087 provides a small set of system calls which are handled by OpenOCD.
1088 It can let the debugger provide your system console and a file system,
1089 helping with early debugging or providing a more capable environment
1090 for sometimes-complex tasks like installing system firmware onto
1091 NAND or SPI flash.
1093 @item @b{ARM Wait-For-Interrupt}...
1094 Many ARM chips synchronize the JTAG clock using the core clock.
1095 Low power states which stop that core clock thus prevent JTAG access.
1096 Idle loops in tasking environments often enter those low power states
1097 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1099 You may want to @emph{disable that instruction} in source code,
1100 or otherwise prevent using that state,
1101 to ensure you can get JTAG access at any time.@footnote{As a more
1102 polite alternative, some processors have special debug-oriented
1103 registers which can be used to change various features including
1104 how the low power states are clocked while debugging.
1105 The STM32 DBGMCU_CR register is an example; at the cost of extra
1106 power consumption, JTAG can be used during low power states.}
1107 For example, the OpenOCD @command{halt} command may not
1108 work for an idle processor otherwise.
1110 @item @b{Delay after reset}...
1111 Not all chips have good support for debugger access
1112 right after reset; many LPC2xxx chips have issues here.
1113 Similarly, applications that reconfigure pins used for
1114 JTAG access as they start will also block debugger access.
1116 To work with boards like this, @emph{enable a short delay loop}
1117 the first thing after reset, before "real" startup activities.
1118 For example, one second's delay is usually more than enough
1119 time for a JTAG debugger to attach, so that
1120 early code execution can be debugged
1121 or firmware can be replaced.
1123 @item @b{Debug Communications Channel (DCC)}...
1124 Some processors include mechanisms to send messages over JTAG.
1125 Many ARM cores support these, as do some cores from other vendors.
1126 (OpenOCD may be able to use this DCC internally, speeding up some
1127 operations like writing to memory.)
1129 Your application may want to deliver various debugging messages
1130 over JTAG, by @emph{linking with a small library of code}
1131 provided with OpenOCD and using the utilities there to send
1132 various kinds of message.
1133 @xref{Software Debug Messages and Tracing}.
1135 @end itemize
1137 @section Target Hardware Setup
1139 Chip vendors often provide software development boards which
1140 are highly configurable, so that they can support all options
1141 that product boards may require. @emph{Make sure that any
1142 jumpers or switches match the system configuration you are
1143 working with.}
1145 Common issues include:
1147 @itemize @bullet
1149 @item @b{JTAG setup} ...
1150 Boards may support more than one JTAG configuration.
1151 Examples include jumpers controlling pullups versus pulldowns
1152 on the nTRST and/or nSRST signals, and choice of connectors
1153 (e.g. which of two headers on the base board,
1154 or one from a daughtercard).
1155 For some Texas Instruments boards, you may need to jumper the
1156 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1158 @item @b{Boot Modes} ...
1159 Complex chips often support multiple boot modes, controlled
1160 by external jumpers. Make sure this is set up correctly.
1161 For example many i.MX boards from NXP need to be jumpered
1162 to "ATX mode" to start booting using the on-chip ROM, when
1163 using second stage bootloader code stored in a NAND flash chip.
1165 Such explicit configuration is common, and not limited to
1166 booting from NAND. You might also need to set jumpers to
1167 start booting using code loaded from an MMC/SD card; external
1168 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1169 flash; some external host; or various other sources.
1172 @item @b{Memory Addressing} ...
1173 Boards which support multiple boot modes may also have jumpers
1174 to configure memory addressing. One board, for example, jumpers
1175 external chipselect 0 (used for booting) to address either
1176 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1177 or NAND flash. When it's jumpered to address NAND flash, that
1178 board must also be told to start booting from on-chip ROM.
1180 Your @file{board.cfg} file may also need to be told this jumper
1181 configuration, so that it can know whether to declare NOR flash
1182 using @command{flash bank} or instead declare NAND flash with
1183 @command{nand device}; and likewise which probe to perform in
1184 its @code{reset-init} handler.
1186 A closely related issue is bus width. Jumpers might need to
1187 distinguish between 8 bit or 16 bit bus access for the flash
1188 used to start booting.
1190 @item @b{Peripheral Access} ...
1191 Development boards generally provide access to every peripheral
1192 on the chip, sometimes in multiple modes (such as by providing
1193 multiple audio codec chips).
1194 This interacts with software
1195 configuration of pin multiplexing, where for example a
1196 given pin may be routed either to the MMC/SD controller
1197 or the GPIO controller. It also often interacts with
1198 configuration jumpers. One jumper may be used to route
1199 signals to an MMC/SD card slot or an expansion bus (which
1200 might in turn affect booting); others might control which
1201 audio or video codecs are used.
1203 @end itemize
1205 Plus you should of course have @code{reset-init} event handlers
1206 which set up the hardware to match that jumper configuration.
1207 That includes in particular any oscillator or PLL used to clock
1208 the CPU, and any memory controllers needed to access external
1209 memory and peripherals. Without such handlers, you won't be
1210 able to access those resources without working target firmware
1211 which can do that setup ... this can be awkward when you're
1212 trying to debug that target firmware. Even if there's a ROM
1213 bootloader which handles a few issues, it rarely provides full
1214 access to all board-specific capabilities.
1217 @node Config File Guidelines
1218 @chapter Config File Guidelines
1220 This chapter is aimed at any user who needs to write a config file,
1221 including developers and integrators of OpenOCD and any user who
1222 needs to get a new board working smoothly.
1223 It provides guidelines for creating those files.
1225 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1226 with files including the ones listed here.
1227 Use them as-is where you can; or as models for new files.
1228 @itemize @bullet
1229 @item @file{interface} ...
1230 These are for debug adapters.
1231 Files that configure JTAG adapters go here.
1232 @example
1233 $ ls interface
1234 arm-jtag-ew.cfg hitex_str9-comstick.cfg oocdlink.cfg
1235 arm-usb-ocd.cfg icebear.cfg openocd-usb.cfg
1236 at91rm9200.cfg jlink.cfg parport.cfg
1237 axm0432.cfg jtagkey2.cfg parport_dlc5.cfg
1238 calao-usb-a9260-c01.cfg jtagkey.cfg rlink.cfg
1239 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg sheevaplug.cfg
1240 calao-usb-a9260.cfg luminary.cfg signalyzer.cfg
1241 chameleon.cfg luminary-icdi.cfg stm32-stick.cfg
1242 cortino.cfg luminary-lm3s811.cfg turtelizer2.cfg
1243 dummy.cfg olimex-arm-usb-ocd.cfg usbprog.cfg
1244 flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
1245 $
1246 @end example
1247 @item @file{board} ...
1248 think Circuit Board, PWA, PCB, they go by many names. Board files
1249 contain initialization items that are specific to a board.
1250 They reuse target configuration files, since the same
1251 microprocessor chips are used on many boards,
1252 but support for external parts varies widely. For
1253 example, the SDRAM initialization sequence for the board, or the type
1254 of external flash and what address it uses. Any initialization
1255 sequence to enable that external flash or SDRAM should be found in the
1256 board file. Boards may also contain multiple targets: two CPUs; or
1257 a CPU and an FPGA.
1258 @example
1259 $ ls board
1260 arm_evaluator7t.cfg keil_mcb1700.cfg
1261 at91rm9200-dk.cfg keil_mcb2140.cfg
1262 at91sam9g20-ek.cfg linksys_nslu2.cfg
1263 atmel_at91sam7s-ek.cfg logicpd_imx27.cfg
1264 atmel_at91sam9260-ek.cfg mini2440.cfg
1265 atmel_sam3u_ek.cfg olimex_LPC2378STK.cfg
1266 crossbow_tech_imote2.cfg olimex_lpc_h2148.cfg
1267 csb337.cfg olimex_sam7_ex256.cfg
1268 csb732.cfg olimex_sam9_l9260.cfg
1269 digi_connectcore_wi-9c.cfg olimex_stm32_h103.cfg
1270 dm355evm.cfg omap2420_h4.cfg
1271 dm365evm.cfg osk5912.cfg
1272 dm6446evm.cfg pic-p32mx.cfg
1273 eir.cfg propox_mmnet1001.cfg
1274 ek-lm3s1968.cfg pxa255_sst.cfg
1275 ek-lm3s3748.cfg sheevaplug.cfg
1276 ek-lm3s811.cfg stm3210e_eval.cfg
1277 ek-lm3s9b9x.cfg stm32f10x_128k_eval.cfg
1278 hammer.cfg str910-eval.cfg
1279 hitex_lpc2929.cfg telo.cfg
1280 hitex_stm32-performancestick.cfg ti_beagleboard.cfg
1281 hitex_str9-comstick.cfg topas910.cfg
1282 iar_str912_sk.cfg topasa900.cfg
1283 imx27ads.cfg unknown_at91sam9260.cfg
1284 imx27lnst.cfg x300t.cfg
1285 imx31pdk.cfg zy1000.cfg
1286 $
1287 @end example
1288 @item @file{target} ...
1289 think chip. The ``target'' directory represents the JTAG TAPs
1290 on a chip
1291 which OpenOCD should control, not a board. Two common types of targets
1292 are ARM chips and FPGA or CPLD chips.
1293 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1294 the target config file defines all of them.
1295 @example
1296 $ ls target
1297 aduc702x.cfg imx27.cfg pxa255.cfg
1298 ar71xx.cfg imx31.cfg pxa270.cfg
1299 at91eb40a.cfg imx35.cfg readme.txt
1300 at91r40008.cfg is5114.cfg sam7se512.cfg
1301 at91rm9200.cfg ixp42x.cfg sam7x256.cfg
1302 at91sam3u1c.cfg lm3s1968.cfg samsung_s3c2410.cfg
1303 at91sam3u1e.cfg lm3s3748.cfg samsung_s3c2440.cfg
1304 at91sam3u2c.cfg lm3s6965.cfg samsung_s3c2450.cfg
1305 at91sam3u2e.cfg lm3s811.cfg samsung_s3c4510.cfg
1306 at91sam3u4c.cfg lm3s9b9x.cfg samsung_s3c6410.cfg
1307 at91sam3u4e.cfg lpc1768.cfg sharp_lh79532.cfg
1308 at91sam3uXX.cfg lpc2103.cfg smdk6410.cfg
1309 at91sam7sx.cfg lpc2124.cfg smp8634.cfg
1310 at91sam9260.cfg lpc2129.cfg stm32f1x.cfg
1311 c100.cfg lpc2148.cfg str710.cfg
1312 c100config.tcl lpc2294.cfg str730.cfg
1313 c100helper.tcl lpc2378.cfg str750.cfg
1314 c100regs.tcl lpc2478.cfg str912.cfg
1315 cs351x.cfg lpc2900.cfg telo.cfg
1316 davinci.cfg mega128.cfg ti_dm355.cfg
1317 dragonite.cfg netx500.cfg ti_dm365.cfg
1318 epc9301.cfg omap2420.cfg ti_dm6446.cfg
1319 feroceon.cfg omap3530.cfg tmpa900.cfg
1320 icepick.cfg omap5912.cfg tmpa910.cfg
1321 imx21.cfg pic32mx.cfg xba_revA3.cfg
1322 $
1323 @end example
1324 @item @emph{more} ... browse for other library files which may be useful.
1325 For example, there are various generic and CPU-specific utilities.
1326 @end itemize
1328 The @file{openocd.cfg} user config
1329 file may override features in any of the above files by
1330 setting variables before sourcing the target file, or by adding
1331 commands specific to their situation.
1333 @section Interface Config Files
1335 The user config file
1336 should be able to source one of these files with a command like this:
1338 @example
1339 source [find interface/FOOBAR.cfg]
1340 @end example
1342 A preconfigured interface file should exist for every debug adapter
1343 in use today with OpenOCD.
1344 That said, perhaps some of these config files
1345 have only been used by the developer who created it.
1347 A separate chapter gives information about how to set these up.
1348 @xref{Debug Adapter Configuration}.
1349 Read the OpenOCD source code (and Developer's Guide)
1350 if you have a new kind of hardware interface
1351 and need to provide a driver for it.
1353 @section Board Config Files
1354 @cindex config file, board
1355 @cindex board config file
1357 The user config file
1358 should be able to source one of these files with a command like this:
1360 @example
1361 source [find board/FOOBAR.cfg]
1362 @end example
1364 The point of a board config file is to package everything
1365 about a given board that user config files need to know.
1366 In summary the board files should contain (if present)
1368 @enumerate
1369 @item One or more @command{source [target/...cfg]} statements
1370 @item NOR flash configuration (@pxref{NOR Configuration})
1371 @item NAND flash configuration (@pxref{NAND Configuration})
1372 @item Target @code{reset} handlers for SDRAM and I/O configuration
1373 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1374 @item All things that are not ``inside a chip''
1375 @end enumerate
1377 Generic things inside target chips belong in target config files,
1378 not board config files. So for example a @code{reset-init} event
1379 handler should know board-specific oscillator and PLL parameters,
1380 which it passes to target-specific utility code.
1382 The most complex task of a board config file is creating such a
1383 @code{reset-init} event handler.
1384 Define those handlers last, after you verify the rest of the board
1385 configuration works.
1387 @subsection Communication Between Config files
1389 In addition to target-specific utility code, another way that
1390 board and target config files communicate is by following a
1391 convention on how to use certain variables.
1393 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1394 Thus the rule we follow in OpenOCD is this: Variables that begin with
1395 a leading underscore are temporary in nature, and can be modified and
1396 used at will within a target configuration file.
1398 Complex board config files can do the things like this,
1399 for a board with three chips:
1401 @example
1402 # Chip #1: PXA270 for network side, big endian
1403 set CHIPNAME network
1404 set ENDIAN big
1405 source [find target/pxa270.cfg]
1406 # on return: _TARGETNAME = network.cpu
1407 # other commands can refer to the "network.cpu" target.
1408 $_TARGETNAME configure .... events for this CPU..
1410 # Chip #2: PXA270 for video side, little endian
1411 set CHIPNAME video
1412 set ENDIAN little
1413 source [find target/pxa270.cfg]
1414 # on return: _TARGETNAME = video.cpu
1415 # other commands can refer to the "video.cpu" target.
1416 $_TARGETNAME configure .... events for this CPU..
1418 # Chip #3: Xilinx FPGA for glue logic
1419 set CHIPNAME xilinx
1420 unset ENDIAN
1421 source [find target/spartan3.cfg]
1422 @end example
1424 That example is oversimplified because it doesn't show any flash memory,
1425 or the @code{reset-init} event handlers to initialize external DRAM
1426 or (assuming it needs it) load a configuration into the FPGA.
1427 Such features are usually needed for low-level work with many boards,
1428 where ``low level'' implies that the board initialization software may
1429 not be working. (That's a common reason to need JTAG tools. Another
1430 is to enable working with microcontroller-based systems, which often
1431 have no debugging support except a JTAG connector.)
1433 Target config files may also export utility functions to board and user
1434 config files. Such functions should use name prefixes, to help avoid
1435 naming collisions.
1437 Board files could also accept input variables from user config files.
1438 For example, there might be a @code{J4_JUMPER} setting used to identify
1439 what kind of flash memory a development board is using, or how to set
1440 up other clocks and peripherals.
1442 @subsection Variable Naming Convention
1443 @cindex variable names
1445 Most boards have only one instance of a chip.
1446 However, it should be easy to create a board with more than
1447 one such chip (as shown above).
1448 Accordingly, we encourage these conventions for naming
1449 variables associated with different @file{target.cfg} files,
1450 to promote consistency and
1451 so that board files can override target defaults.
1453 Inputs to target config files include:
1455 @itemize @bullet
1456 @item @code{CHIPNAME} ...
1457 This gives a name to the overall chip, and is used as part of
1458 tap identifier dotted names.
1459 While the default is normally provided by the chip manufacturer,
1460 board files may need to distinguish between instances of a chip.
1461 @item @code{ENDIAN} ...
1462 By default @option{little} - although chips may hard-wire @option{big}.
1463 Chips that can't change endianness don't need to use this variable.
1464 @item @code{CPUTAPID} ...
1465 When OpenOCD examines the JTAG chain, it can be told verify the
1466 chips against the JTAG IDCODE register.
1467 The target file will hold one or more defaults, but sometimes the
1468 chip in a board will use a different ID (perhaps a newer revision).
1469 @end itemize
1471 Outputs from target config files include:
1473 @itemize @bullet
1474 @item @code{_TARGETNAME} ...
1475 By convention, this variable is created by the target configuration
1476 script. The board configuration file may make use of this variable to
1477 configure things like a ``reset init'' script, or other things
1478 specific to that board and that target.
1479 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1480 @code{_TARGETNAME1}, ... etc.
1481 @end itemize
1483 @subsection The reset-init Event Handler
1484 @cindex event, reset-init
1485 @cindex reset-init handler
1487 Board config files run in the OpenOCD configuration stage;
1488 they can't use TAPs or targets, since they haven't been
1489 fully set up yet.
1490 This means you can't write memory or access chip registers;
1491 you can't even verify that a flash chip is present.
1492 That's done later in event handlers, of which the target @code{reset-init}
1493 handler is one of the most important.
1495 Except on microcontrollers, the basic job of @code{reset-init} event
1496 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1497 Microcontrollers rarely use boot loaders; they run right out of their
1498 on-chip flash and SRAM memory. But they may want to use one of these
1499 handlers too, if just for developer convenience.
1501 @quotation Note
1502 Because this is so very board-specific, and chip-specific, no examples
1503 are included here.
1504 Instead, look at the board config files distributed with OpenOCD.
1505 If you have a boot loader, its source code will help; so will
1506 configuration files for other JTAG tools
1507 (@pxref{Translating Configuration Files}).
1508 @end quotation
1510 Some of this code could probably be shared between different boards.
1511 For example, setting up a DRAM controller often doesn't differ by
1512 much except the bus width (16 bits or 32?) and memory timings, so a
1513 reusable TCL procedure loaded by the @file{target.cfg} file might take
1514 those as parameters.
1515 Similarly with oscillator, PLL, and clock setup;
1516 and disabling the watchdog.
1517 Structure the code cleanly, and provide comments to help
1518 the next developer doing such work.
1519 (@emph{You might be that next person} trying to reuse init code!)
1521 The last thing normally done in a @code{reset-init} handler is probing
1522 whatever flash memory was configured. For most chips that needs to be
1523 done while the associated target is halted, either because JTAG memory
1524 access uses the CPU or to prevent conflicting CPU access.
1526 @subsection JTAG Clock Rate
1528 Before your @code{reset-init} handler has set up
1529 the PLLs and clocking, you may need to run with
1530 a low JTAG clock rate.
1531 @xref{JTAG Speed}.
1532 Then you'd increase that rate after your handler has
1533 made it possible to use the faster JTAG clock.
1534 When the initial low speed is board-specific, for example
1535 because it depends on a board-specific oscillator speed, then
1536 you should probably set it up in the board config file;
1537 if it's target-specific, it belongs in the target config file.
1539 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1540 @uref{} gives details.}
1541 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1542 Consult chip documentation to determine the peak JTAG clock rate,
1543 which might be less than that.
1545 @quotation Warning
1546 On most ARMs, JTAG clock detection is coupled to the core clock, so
1547 software using a @option{wait for interrupt} operation blocks JTAG access.
1548 Adaptive clocking provides a partial workaround, but a more complete
1549 solution just avoids using that instruction with JTAG debuggers.
1550 @end quotation
1552 If both the chip and the board support adaptive clocking,
1553 use the @command{jtag_rclk}
1554 command, in case your board is used with JTAG adapter which
1555 also supports it. Otherwise use @command{adapter_khz}.
1556 Set the slow rate at the beginning of the reset sequence,
1557 and the faster rate as soon as the clocks are at full speed.
1559 @anchor{The init_board procedure}
1560 @subsection The init_board procedure
1561 @cindex init_board procedure
1563 The concept of @code{init_board} procedure is very similar to @code{init_targets} (@xref{The init_targets procedure}.)
1564 - it's a replacement of ``linear'' configuration scripts. This procedure is meant to be executed when OpenOCD enters run
1565 stage (@xref{Entering the Run Stage},) after @code{init_targets}. The idea to have spearate @code{init_targets} and
1566 @code{init_board} procedures is to allow the first one to configure everything target specific (internal flash,
1567 internal RAM, etc.) and the second one to configure everything board specific (reset signals, chip frequency,
1568 reset-init event handler, external memory, etc.). Additionally ``linear'' board config file will most likely fail when
1569 target config file uses @code{init_targets} scheme (``linear'' script is executed before @code{init} and
1570 @code{init_targets} - after), so separating these two configuration stages is very convenient, as the easiest way to
1571 overcome this problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1572 need to override @code{init_targets} defined in target config files when they only need to to add some specifics.
1574 Just as @code{init_targets}, the @code{init_board} procedure can be overriden by ``next level'' script (which sources
1575 the original), allowing greater code reuse.
1577 @example
1578 ### board_file.cfg ###
1580 # source target file that does most of the config in init_targets
1581 source [find target/target.cfg]
1583 proc enable_fast_clock @{@} @{
1584 # enables fast on-board clock source
1585 # configures the chip to use it
1586 @}
1588 # initialize only board specifics - reset, clock, adapter frequency
1589 proc init_board @{@} @{
1590 reset_config trst_and_srst trst_pulls_srst
1592 $_TARGETNAME configure -event reset-init @{
1593 adapter_khz 1
1594 enable_fast_clock
1595 adapter_khz 10000
1596 @}
1597 @}
1598 @end example
1600 @section Target Config Files
1601 @cindex config file, target
1602 @cindex target config file
1604 Board config files communicate with target config files using
1605 naming conventions as described above, and may source one or
1606 more target config files like this:
1608 @example
1609 source [find target/FOOBAR.cfg]
1610 @end example
1612 The point of a target config file is to package everything
1613 about a given chip that board config files need to know.
1614 In summary the target files should contain
1616 @enumerate
1617 @item Set defaults
1618 @item Add TAPs to the scan chain
1619 @item Add CPU targets (includes GDB support)
1620 @item CPU/Chip/CPU-Core specific features
1621 @item On-Chip flash
1622 @end enumerate
1624 As a rule of thumb, a target file sets up only one chip.
1625 For a microcontroller, that will often include a single TAP,
1626 which is a CPU needing a GDB target, and its on-chip flash.
1628 More complex chips may include multiple TAPs, and the target
1629 config file may need to define them all before OpenOCD
1630 can talk to the chip.
1631 For example, some phone chips have JTAG scan chains that include
1632 an ARM core for operating system use, a DSP,
1633 another ARM core embedded in an image processing engine,
1634 and other processing engines.
1636 @subsection Default Value Boiler Plate Code
1638 All target configuration files should start with code like this,
1639 letting board config files express environment-specific
1640 differences in how things should be set up.
1642 @example
1643 # Boards may override chip names, perhaps based on role,
1644 # but the default should match what the vendor uses
1645 if @{ [info exists CHIPNAME] @} @{
1647 @} else @{
1648 set _CHIPNAME sam7x256
1649 @}
1651 # ONLY use ENDIAN with targets that can change it.
1652 if @{ [info exists ENDIAN] @} @{
1653 set _ENDIAN $ENDIAN
1654 @} else @{
1655 set _ENDIAN little
1656 @}
1658 # TAP identifiers may change as chips mature, for example with
1659 # new revision fields (the "3" here). Pick a good default; you
1660 # can pass several such identifiers to the "jtag newtap" command.
1661 if @{ [info exists CPUTAPID ] @} @{
1663 @} else @{
1664 set _CPUTAPID 0x3f0f0f0f
1665 @}
1666 @end example
1667 @c but 0x3f0f0f0f is for an str73x part ...
1669 @emph{Remember:} Board config files may include multiple target
1670 config files, or the same target file multiple times
1671 (changing at least @code{CHIPNAME}).
1673 Likewise, the target configuration file should define
1674 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1675 use it later on when defining debug targets:
1677 @example
1679 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1680 @end example
1682 @subsection Adding TAPs to the Scan Chain
1683 After the ``defaults'' are set up,
1684 add the TAPs on each chip to the JTAG scan chain.
1685 @xref{TAP Declaration}, and the naming convention
1686 for taps.
1688 In the simplest case the chip has only one TAP,
1689 probably for a CPU or FPGA.
1690 The config file for the Atmel AT91SAM7X256
1691 looks (in part) like this:
1693 @example
1694 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1695 @end example
1697 A board with two such at91sam7 chips would be able
1698 to source such a config file twice, with different
1699 values for @code{CHIPNAME}, so
1700 it adds a different TAP each time.
1702 If there are nonzero @option{-expected-id} values,
1703 OpenOCD attempts to verify the actual tap id against those values.
1704 It will issue error messages if there is mismatch, which
1705 can help to pinpoint problems in OpenOCD configurations.
1707 @example
1708 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1709 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1710 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1711 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1712 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1713 @end example
1715 There are more complex examples too, with chips that have
1716 multiple TAPs. Ones worth looking at include:
1718 @itemize
1719 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1720 plus a JRC to enable them
1721 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1722 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1723 is not currently used)
1724 @end itemize
1726 @subsection Add CPU targets
1728 After adding a TAP for a CPU, you should set it up so that
1729 GDB and other commands can use it.
1730 @xref{CPU Configuration}.
1731 For the at91sam7 example above, the command can look like this;
1732 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1733 to little endian, and this chip doesn't support changing that.
1735 @example
1737 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1738 @end example
1740 Work areas are small RAM areas associated with CPU targets.
1741 They are used by OpenOCD to speed up downloads,
1742 and to download small snippets of code to program flash chips.
1743 If the chip includes a form of ``on-chip-ram'' - and many do - define
1744 a work area if you can.
1745 Again using the at91sam7 as an example, this can look like:
1747 @example
1748 $_TARGETNAME configure -work-area-phys 0x00200000 \
1749 -work-area-size 0x4000 -work-area-backup 0
1750 @end example
1752 @anchor{Define CPU targets working in SMP}
1753 @subsection Define CPU targets working in SMP
1754 @cindex SMP
1755 After setting targets, you can define a list of targets working in SMP.
1757 @example
1758 set _TARGETNAME_1 $_CHIPNAME.cpu1
1759 set _TARGETNAME_2 $_CHIPNAME.cpu2
1760 target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap \
1761 -coreid 0 -dbgbase $_DAP_DBG1
1762 target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap \
1763 -coreid 1 -dbgbase $_DAP_DBG2
1764 #define 2 targets working in smp.
1765 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1766 @end example
1767 In the above example on cortex_a8, 2 cpus are working in SMP.
1768 In SMP only one GDB instance is created and :
1769 @itemize @bullet
1770 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1771 @item halt command triggers the halt of all targets in the list.
1772 @item resume command triggers the write context and the restart of all targets in the list.
1773 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1774 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1775 displayed by the GDB session @pxref{Using openocd SMP with GDB}.
1776 @end itemize
1778 The SMP behaviour can be disabled/enabled dynamically. On cortex_a8 following
1779 command have been implemented.
1780 @itemize @bullet
1781 @item cortex_a8 smp_on : enable SMP mode, behaviour is as described above.
1782 @item cortex_a8 smp_off : disable SMP mode, the current target is the one
1783 displayed in the GDB session, only this target is now controlled by GDB
1784 session. This behaviour is useful during system boot up.
1785 @item cortex_a8 smp_gdb : display/fix the core id displayed in GDB session see
1786 following example.
1787 @end itemize
1789 @example
1790 >cortex_a8 smp_gdb
1791 gdb coreid 0 -> -1
1792 #0 : coreid 0 is displayed to GDB ,
1793 #-> -1 : next resume triggers a real resume
1794 > cortex_a8 smp_gdb 1
1795 gdb coreid 0 -> 1
1796 #0 :coreid 0 is displayed to GDB ,
1797 #->1 : next resume displays coreid 1 to GDB
1798 > resume
1799 > cortex_a8 smp_gdb
1800 gdb coreid 1 -> 1
1801 #1 :coreid 1 is displayed to GDB ,
1802 #->1 : next resume displays coreid 1 to GDB
1803 > cortex_a8 smp_gdb -1
1804 gdb coreid 1 -> -1
1805 #1 :coreid 1 is displayed to GDB,
1806 #->-1 : next resume triggers a real resume
1807 @end example
1810 @subsection Chip Reset Setup
1812 As a rule, you should put the @command{reset_config} command
1813 into the board file. Most things you think you know about a
1814 chip can be tweaked by the board.
1816 Some chips have specific ways the TRST and SRST signals are
1817 managed. In the unusual case that these are @emph{chip specific}
1818 and can never be changed by board wiring, they could go here.
1819 For example, some chips can't support JTAG debugging without
1820 both signals.
1822 Provide a @code{reset-assert} event handler if you can.
1823 Such a handler uses JTAG operations to reset the target,
1824 letting this target config be used in systems which don't
1825 provide the optional SRST signal, or on systems where you
1826 don't want to reset all targets at once.
1827 Such a handler might write to chip registers to force a reset,
1828 use a JRC to do that (preferable -- the target may be wedged!),
1829 or force a watchdog timer to trigger.
1830 (For Cortex-M3 targets, this is not necessary. The target
1831 driver knows how to use trigger an NVIC reset when SRST is
1832 not available.)
1834 Some chips need special attention during reset handling if
1835 they're going to be used with JTAG.
1836 An example might be needing to send some commands right
1837 after the target's TAP has been reset, providing a
1838 @code{reset-deassert-post} event handler that writes a chip
1839 register to report that JTAG debugging is being done.
1840 Another would be reconfiguring the watchdog so that it stops
1841 counting while the core is halted in the debugger.
1843 JTAG clocking constraints often change during reset, and in
1844 some cases target config files (rather than board config files)
1845 are the right places to handle some of those issues.
1846 For example, immediately after reset most chips run using a
1847 slower clock than they will use later.
1848 That means that after reset (and potentially, as OpenOCD
1849 first starts up) they must use a slower JTAG clock rate
1850 than they will use later.
1851 @xref{JTAG Speed}.
1853 @quotation Important
1854 When you are debugging code that runs right after chip
1855 reset, getting these issues right is critical.
1856 In particular, if you see intermittent failures when
1857 OpenOCD verifies the scan chain after reset,
1858 look at how you are setting up JTAG clocking.
1859 @end quotation
1861 @anchor{The init_targets procedure}
1862 @subsection The init_targets procedure
1863 @cindex init_targets procedure
1865 Target config files can either be ``linear'' (script executed line-by-line when parsed in configuration stage,
1866 @xref{Configuration Stage},) or they can contain a special procedure called @code{init_targets}, which will be executed
1867 when entering run stage (after parsing all config files or after @code{init} command, @xref{Entering the Run Stage}.)
1868 Such procedure can be overriden by ``next level'' script (which sources the original). This concept faciliates code
1869 reuse when basic target config files provide generic configuration procedures and @code{init_targets} procedure, which
1870 can then be sourced and enchanced or changed in a ``more specific'' target config file. This is not possible with
1871 ``linear'' config scripts, because sourcing them executes every initialization commands they provide.
1873 @example
1874 ### generic_file.cfg ###
1876 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1877 # basic initialization procedure ...
1878 @}
1880 proc init_targets @{@} @{
1881 # initializes generic chip with 4kB of flash and 1kB of RAM
1882 setup_my_chip MY_GENERIC_CHIP 4096 1024
1883 @}
1885 ### specific_file.cfg ###
1887 source [find target/generic_file.cfg]
1889 proc init_targets @{@} @{
1890 # initializes specific chip with 128kB of flash and 64kB of RAM
1891 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1892 @}
1893 @end example
1895 The easiest way to convert ``linear'' config files to @code{init_targets} version is to enclose every line of ``code''
1896 (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1898 For an example of this scheme see LPC2000 target config files.
1900 The @code{init_boards} procedure is a similar concept concerning board config files (@xref{The init_board procedure}.)
1902 @subsection ARM Core Specific Hacks
1904 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1905 special high speed download features - enable it.
1907 If present, the MMU, the MPU and the CACHE should be disabled.
1909 Some ARM cores are equipped with trace support, which permits
1910 examination of the instruction and data bus activity. Trace
1911 activity is controlled through an ``Embedded Trace Module'' (ETM)
1912 on one of the core's scan chains. The ETM emits voluminous data
1913 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
1914 If you are using an external trace port,
1915 configure it in your board config file.
1916 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1917 configure it in your target config file.
1919 @example
1920 etm config $_TARGETNAME 16 normal full etb
1921 etb config $_TARGETNAME $_CHIPNAME.etb
1922 @end example
1924 @subsection Internal Flash Configuration
1926 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1928 @b{Never ever} in the ``target configuration file'' define any type of
1929 flash that is external to the chip. (For example a BOOT flash on
1930 Chip Select 0.) Such flash information goes in a board file - not
1931 the TARGET (chip) file.
1933 Examples:
1934 @itemize @bullet
1935 @item at91sam7x256 - has 256K flash YES enable it.
1936 @item str912 - has flash internal YES enable it.
1937 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1938 @item pxa270 - again - CS0 flash - it goes in the board file.
1939 @end itemize
1941 @anchor{Translating Configuration Files}
1942 @section Translating Configuration Files
1943 @cindex translation
1944 If you have a configuration file for another hardware debugger
1945 or toolset (Abatron, BDI2000, BDI3000, CCS,
1946 Lauterbach, Segger, Macraigor, etc.), translating
1947 it into OpenOCD syntax is often quite straightforward. The most tricky
1948 part of creating a configuration script is oftentimes the reset init
1949 sequence where e.g. PLLs, DRAM and the like is set up.
1951 One trick that you can use when translating is to write small
1952 Tcl procedures to translate the syntax into OpenOCD syntax. This
1953 can avoid manual translation errors and make it easier to
1954 convert other scripts later on.
1956 Example of transforming quirky arguments to a simple search and
1957 replace job:
1959 @example
1960 # Lauterbach syntax(?)
1961 #
1962 # Data.Set c15:0x042f %long 0x40000015
1963 #
1964 # OpenOCD syntax when using procedure below.
1965 #
1966 # setc15 0x01 0x00050078
1968 proc setc15 @{regs value@} @{
1969 global TARGETNAME
1971 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
1973 arm mcr 15 [expr ($regs>>12)&0x7] \
1974 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
1975 [expr ($regs>>8)&0x7] $value
1976 @}
1977 @end example
1981 @node Daemon Configuration
1982 @chapter Daemon Configuration
1983 @cindex initialization
1984 The commands here are commonly found in the openocd.cfg file and are
1985 used to specify what TCP/IP ports are used, and how GDB should be
1986 supported.
1988 @anchor{Configuration Stage}
1989 @section Configuration Stage
1990 @cindex configuration stage
1991 @cindex config command
1993 When the OpenOCD server process starts up, it enters a
1994 @emph{configuration stage} which is the only time that
1995 certain commands, @emph{configuration commands}, may be issued.
1996 Normally, configuration commands are only available
1997 inside startup scripts.
1999 In this manual, the definition of a configuration command is
2000 presented as a @emph{Config Command}, not as a @emph{Command}
2001 which may be issued interactively.
2002 The runtime @command{help} command also highlights configuration
2003 commands, and those which may be issued at any time.
2005 Those configuration commands include declaration of TAPs,
2006 flash banks,
2007 the interface used for JTAG communication,
2008 and other basic setup.
2009 The server must leave the configuration stage before it
2010 may access or activate TAPs.
2011 After it leaves this stage, configuration commands may no
2012 longer be issued.
2014 @anchor{Entering the Run Stage}
2015 @section Entering the Run Stage
2017 The first thing OpenOCD does after leaving the configuration
2018 stage is to verify that it can talk to the scan chain
2019 (list of TAPs) which has been configured.
2020 It will warn if it doesn't find TAPs it expects to find,
2021 or finds TAPs that aren't supposed to be there.
2022 You should see no errors at this point.
2023 If you see errors, resolve them by correcting the
2024 commands you used to configure the server.
2025 Common errors include using an initial JTAG speed that's too
2026 fast, and not providing the right IDCODE values for the TAPs
2027 on the scan chain.
2029 Once OpenOCD has entered the run stage, a number of commands
2030 become available.
2031 A number of these relate to the debug targets you may have declared.
2032 For example, the @command{mww} command will not be available until
2033 a target has been successfuly instantiated.
2034 If you want to use those commands, you may need to force
2035 entry to the run stage.
2037 @deffn {Config Command} init
2038 This command terminates the configuration stage and
2039 enters the run stage. This helps when you need to have
2040 the startup scripts manage tasks such as resetting the target,
2041 programming flash, etc. To reset the CPU upon startup, add "init" and
2042 "reset" at the end of the config script or at the end of the OpenOCD
2043 command line using the @option{-c} command line switch.
2045 If this command does not appear in any startup/configuration file
2046 OpenOCD executes the command for you after processing all
2047 configuration files and/or command line options.
2049 @b{NOTE:} This command normally occurs at or near the end of your
2050 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2051 targets ready. For example: If your openocd.cfg file needs to
2052 read/write memory on your target, @command{init} must occur before
2053 the memory read/write commands. This includes @command{nand probe}.
2054 @end deffn
2056 @deffn {Overridable Procedure} jtag_init
2057 This is invoked at server startup to verify that it can talk
2058 to the scan chain (list of TAPs) which has been configured.
2060 The default implementation first tries @command{jtag arp_init},
2061 which uses only a lightweight JTAG reset before examining the
2062 scan chain.
2063 If that fails, it tries again, using a harder reset
2064 from the overridable procedure @command{init_reset}.
2066 Implementations must have verified the JTAG scan chain before
2067 they return.
2068 This is done by calling @command{jtag arp_init}
2069 (or @command{jtag arp_init-reset}).
2070 @end deffn
2072 @anchor{TCP/IP Ports}
2073 @section TCP/IP Ports
2074 @cindex TCP port
2075 @cindex server
2076 @cindex port
2077 @cindex security
2078 The OpenOCD server accepts remote commands in several syntaxes.
2079 Each syntax uses a different TCP/IP port, which you may specify
2080 only during configuration (before those ports are opened).
2082 For reasons including security, you may wish to prevent remote
2083 access using one or more of these ports.
2084 In such cases, just specify the relevant port number as zero.
2085 If you disable all access through TCP/IP, you will need to
2086 use the command line @option{-pipe} option.
2088 @deffn {Command} gdb_port [number]
2089 @cindex GDB server
2090 Normally gdb listens to a TCP/IP port, but GDB can also
2091 communicate via pipes(stdin/out or named pipes). The name
2092 "gdb_port" stuck because it covers probably more than 90% of
2093 the normal use cases.
2095 No arguments reports GDB port. "pipe" means listen to stdin
2096 output to stdout, an integer is base port number, "disable"
2097 disables the gdb server.
2099 When using "pipe", also use log_output to redirect the log
2100 output to a file so as not to flood the stdin/out pipes.
2102 The -p/--pipe option is deprecated and a warning is printed
2103 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2105 Any other string is interpreted as named pipe to listen to.
2106 Output pipe is the same name as input pipe, but with 'o' appended,
2107 e.g. /var/gdb, /var/gdbo.
2109 The GDB port for the first target will be the base port, the
2110 second target will listen on gdb_port + 1, and so on.
2111 When not specified during the configuration stage,
2112 the port @var{number} defaults to 3333.
2113 @end deffn
2115 @deffn {Command} tcl_port [number]
2116 Specify or query the port used for a simplified RPC
2117 connection that can be used by clients to issue TCL commands and get the
2118 output from the Tcl engine.
2119 Intended as a machine interface.
2120 When not specified during the configuration stage,
2121 the port @var{number} defaults to 6666.
2123 @end deffn
2125 @deffn {Command} telnet_port [number]
2126 Specify or query the
2127 port on which to listen for incoming telnet connections.
2128 This port is intended for interaction with one human through TCL commands.
2129 When not specified during the configuration stage,
2130 the port @var{number} defaults to 4444.
2131 When specified as zero, this port is not activated.
2132 @end deffn
2134 @anchor{GDB Configuration}
2135 @section GDB Configuration
2136 @cindex GDB
2137 @cindex GDB configuration
2138 You can reconfigure some GDB behaviors if needed.
2139 The ones listed here are static and global.
2140 @xref{Target Configuration}, about configuring individual targets.
2141 @xref{Target Events}, about configuring target-specific event handling.
2143 @anchor{gdb_breakpoint_override}
2144 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2145 Force breakpoint type for gdb @command{break} commands.
2146 This option supports GDB GUIs which don't
2147 distinguish hard versus soft breakpoints, if the default OpenOCD and
2148 GDB behaviour is not sufficient. GDB normally uses hardware
2149 breakpoints if the memory map has been set up for flash regions.
2150 @end deffn
2152 @anchor{gdb_flash_program}
2153 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2154 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2155 vFlash packet is received.
2156 The default behaviour is @option{enable}.
2157 @end deffn
2159 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2160 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2161 requested. GDB will then know when to set hardware breakpoints, and program flash
2162 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2163 for flash programming to work.
2164 Default behaviour is @option{enable}.
2165 @xref{gdb_flash_program}.
2166 @end deffn
2168 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2169 Specifies whether data aborts cause an error to be reported
2170 by GDB memory read packets.
2171 The default behaviour is @option{disable};
2172 use @option{enable} see these errors reported.
2173 @end deffn
2175 @anchor{Event Polling}
2176 @section Event Polling
2178 Hardware debuggers are parts of asynchronous systems,
2179 where significant events can happen at any time.
2180 The OpenOCD server needs to detect some of these events,
2181 so it can report them to through TCL command line
2182 or to GDB.
2184 Examples of such events include:
2186 @itemize
2187 @item One of the targets can stop running ... maybe it triggers
2188 a code breakpoint or data watchpoint, or halts itself.
2189 @item Messages may be sent over ``debug message'' channels ... many
2190 targets support such messages sent over JTAG,
2191 for receipt by the person debugging or tools.
2192 @item Loss of power ... some adapters can detect these events.
2193 @item Resets not issued through JTAG ... such reset sources
2194 can include button presses or other system hardware, sometimes
2195 including the target itself (perhaps through a watchdog).
2196 @item Debug instrumentation sometimes supports event triggering
2197 such as ``trace buffer full'' (so it can quickly be emptied)
2198 or other signals (to correlate with code behavior).
2199 @end itemize
2201 None of those events are signaled through standard JTAG signals.
2202 However, most conventions for JTAG connectors include voltage
2203 level and system reset (SRST) signal detection.
2204 Some connectors also include instrumentation signals, which
2205 can imply events when those signals are inputs.
2207 In general, OpenOCD needs to periodically check for those events,
2208 either by looking at the status of signals on the JTAG connector
2209 or by sending synchronous ``tell me your status'' JTAG requests
2210 to the various active targets.
2211 There is a command to manage and monitor that polling,
2212 which is normally done in the background.
2214 @deffn Command poll [@option{on}|@option{off}]
2215 Poll the current target for its current state.
2216 (Also, @pxref{target curstate}.)
2217 If that target is in debug mode, architecture
2218 specific information about the current state is printed.
2219 An optional parameter
2220 allows background polling to be enabled and disabled.
2222 You could use this from the TCL command shell, or
2223 from GDB using @command{monitor poll} command.
2224 Leave background polling enabled while you're using GDB.
2225 @example
2226 > poll
2227 background polling: on
2228 target state: halted
2229 target halted in ARM state due to debug-request, \
2230 current mode: Supervisor
2231 cpsr: 0x800000d3 pc: 0x11081bfc
2232 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2233 >
2234 @end example
2235 @end deffn
2237 @node Debug Adapter Configuration
2238 @chapter Debug Adapter Configuration
2239 @cindex config file, interface
2240 @cindex interface config file
2242 Correctly installing OpenOCD includes making your operating system give
2243 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2244 are used to select which one is used, and to configure how it is used.
2246 @quotation Note
2247 Because OpenOCD started out with a focus purely on JTAG, you may find
2248 places where it wrongly presumes JTAG is the only transport protocol
2249 in use. Be aware that recent versions of OpenOCD are removing that
2250 limitation. JTAG remains more functional than most other transports.
2251 Other transports do not support boundary scan operations, or may be
2252 specific to a given chip vendor. Some might be usable only for
2253 programming flash memory, instead of also for debugging.
2254 @end quotation
2256 Debug Adapters/Interfaces/Dongles are normally configured
2257 through commands in an interface configuration
2258 file which is sourced by your @file{openocd.cfg} file, or
2259 through a command line @option{-f interface/....cfg} option.
2261 @example
2262 source [find interface/olimex-jtag-tiny.cfg]
2263 @end example
2265 These commands tell
2266 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2267 A few cases are so simple that you only need to say what driver to use:
2269 @example
2270 # jlink interface
2271 interface jlink
2272 @end example
2274 Most adapters need a bit more configuration than that.
2277 @section Interface Configuration
2279 The interface command tells OpenOCD what type of debug adapter you are
2280 using. Depending on the type of adapter, you may need to use one or
2281 more additional commands to further identify or configure the adapter.
2283 @deffn {Config Command} {interface} name
2284 Use the interface driver @var{name} to connect to the
2285 target.
2286 @end deffn
2288 @deffn Command {interface_list}
2289 List the debug adapter drivers that have been built into
2290 the running copy of OpenOCD.
2291 @end deffn
2292 @deffn Command {interface transports} transport_name+
2293 Specifies the transports supported by this debug adapter.
2294 The adapter driver builds-in similar knowledge; use this only
2295 when external configuration (such as jumpering) changes what
2296 the hardware can support.
2297 @end deffn
2301 @deffn Command {adapter_name}
2302 Returns the name of the debug adapter driver being used.
2303 @end deffn
2305 @section Interface Drivers
2307 Each of the interface drivers listed here must be explicitly
2308 enabled when OpenOCD is configured, in order to be made
2309 available at run time.
2311 @deffn {Interface Driver} {amt_jtagaccel}
2312 Amontec Chameleon in its JTAG Accelerator configuration,
2313 connected to a PC's EPP mode parallel port.
2314 This defines some driver-specific commands:
2316 @deffn {Config Command} {parport_port} number
2317 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2318 the number of the @file{/dev/parport} device.
2319 @end deffn
2321 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2322 Displays status of RTCK option.
2323 Optionally sets that option first.
2324 @end deffn
2325 @end deffn
2327 @deffn {Interface Driver} {arm-jtag-ew}
2328 Olimex ARM-JTAG-EW USB adapter
2329 This has one driver-specific command:
2331 @deffn Command {armjtagew_info}
2332 Logs some status
2333 @end deffn
2334 @end deffn
2336 @deffn {Interface Driver} {at91rm9200}
2337 Supports bitbanged JTAG from the local system,
2338 presuming that system is an Atmel AT91rm9200
2339 and a specific set of GPIOs is used.
2340 @c command: at91rm9200_device NAME
2341 @c chooses among list of bit configs ... only one option
2342 @end deffn
2344 @deffn {Interface Driver} {dummy}
2345 A dummy software-only driver for debugging.
2346 @end deffn
2348 @deffn {Interface Driver} {ep93xx}
2349 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2350 @end deffn
2352 @deffn {Interface Driver} {ft2232}
2353 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2354 These interfaces have several commands, used to configure the driver
2355 before initializing the JTAG scan chain:
2357 @deffn {Config Command} {ft2232_device_desc} description
2358 Provides the USB device description (the @emph{iProduct string})
2359 of the FTDI FT2232 device. If not
2360 specified, the FTDI default value is used. This setting is only valid
2361 if compiled with FTD2XX support.
2362 @end deffn
2364 @deffn {Config Command} {ft2232_serial} serial-number
2365 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2366 in case the vendor provides unique IDs and more than one FT2232 device
2367 is connected to the host.
2368 If not specified, serial numbers are not considered.
2369 (Note that USB serial numbers can be arbitrary Unicode strings,
2370 and are not restricted to containing only decimal digits.)
2371 @end deffn
2373 @deffn {Config Command} {ft2232_layout} name
2374 Each vendor's FT2232 device can use different GPIO signals
2375 to control output-enables, reset signals, and LEDs.
2376 Currently valid layout @var{name} values include:
2377 @itemize @minus
2378 @item @b{axm0432_jtag} Axiom AXM-0432
2379 @item @b{comstick} Hitex STR9 comstick
2380 @item @b{cortino} Hitex Cortino JTAG interface
2381 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
2382 either for the local Cortex-M3 (SRST only)
2383 or in a passthrough mode (neither SRST nor TRST)
2384 This layout can not support the SWO trace mechanism, and should be
2385 used only for older boards (before rev C).
2386 @item @b{luminary_icdi} This layout should be used with most Luminary
2387 eval boards, including Rev C LM3S811 eval boards and the eponymous
2388 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2389 to debug some other target. It can support the SWO trace mechanism.
2390 @item @b{flyswatter} Tin Can Tools Flyswatter
2391 @item @b{icebear} ICEbear JTAG adapter from Section 5
2392 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2393 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2394 @item @b{m5960} American Microsystems M5960
2395 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2396 @item @b{oocdlink} OOCDLink
2397 @c oocdlink ~= jtagkey_prototype_v1
2398 @item @b{redbee-econotag} Integrated with a Redbee development board.
2399 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2400 @item @b{sheevaplug} Marvell Sheevaplug development kit
2401 @item @b{signalyzer} Xverve Signalyzer
2402 @item @b{stm32stick} Hitex STM32 Performance Stick
2403 @item @b{turtelizer2} egnite Software turtelizer2
2404 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2405 @end itemize
2406 @end deffn
2408 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2409 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2410 default values are used.
2411 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2412 @example
2413 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2414 @end example
2415 @end deffn
2417 @deffn {Config Command} {ft2232_latency} ms
2418 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2419 ft2232_read() fails to return the expected number of bytes. This can be caused by
2420 USB communication delays and has proved hard to reproduce and debug. Setting the
2421 FT2232 latency timer to a larger value increases delays for short USB packets but it
2422 also reduces the risk of timeouts before receiving the expected number of bytes.
2423 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2424 @end deffn
2426 For example, the interface config file for a
2427 Turtelizer JTAG Adapter looks something like this:
2429 @example
2430 interface ft2232
2431 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2432 ft2232_layout turtelizer2
2433 ft2232_vid_pid 0x0403 0xbdc8
2434 @end example
2435 @end deffn
2437 @deffn {Interface Driver} {remote_bitbang}
2438 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2439 with a remote process and sends ASCII encoded bitbang requests to that process
2440 instead of directly driving JTAG.
2442 The remote_bitbang driver is useful for debugging software running on
2443 processors which are being simulated.
2445 @deffn {Config Command} {remote_bitbang_port} number
2446 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2447 sockets instead of TCP.
2448 @end deffn
2450 @deffn {Config Command} {remote_bitbang_host} hostname
2451 Specifies the hostname of the remote process to connect to using TCP, or the
2452 name of the UNIX socket to use if remote_bitbang_port is 0.
2453 @end deffn
2455 For example, to connect remotely via TCP to the host foobar you might have
2456 something like:
2458 @example
2459 interface remote_bitbang
2460 remote_bitbang_port 3335
2461 remote_bitbang_host foobar
2462 @end example
2464 To connect to another process running locally via UNIX sockets with socket
2465 named mysocket:
2467 @example
2468 interface remote_bitbang
2469 remote_bitbang_port 0
2470 remote_bitbang_host mysocket
2471 @end example
2472 @end deffn
2474 @deffn {Interface Driver} {usb_blaster}
2475 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2476 for FTDI chips. These interfaces have several commands, used to
2477 configure the driver before initializing the JTAG scan chain:
2479 @deffn {Config Command} {usb_blaster_device_desc} description
2480 Provides the USB device description (the @emph{iProduct string})
2481 of the FTDI FT245 device. If not
2482 specified, the FTDI default value is used. This setting is only valid
2483 if compiled with FTD2XX support.
2484 @end deffn
2486 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2487 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2488 default values are used.
2489 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2490 Altera USB-Blaster (default):
2491 @example
2492 usb_blaster_vid_pid 0x09FB 0x6001
2493 @end example
2494 The following VID/PID is for Kolja Waschk's USB JTAG:
2495 @example
2496 usb_blaster_vid_pid 0x16C0 0x06AD
2497 @end example
2498 @end deffn
2500 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2501 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2502 female JTAG header). These pins can be used as SRST and/or TRST provided the
2503 appropriate connections are made on the target board.
2505 For example, to use pin 6 as SRST (as with an AVR board):
2506 @example
2507 $_TARGETNAME configure -event reset-assert \
2508 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2509 @end example
2510 @end deffn
2512 @end deffn
2514 @deffn {Interface Driver} {gw16012}
2515 Gateworks GW16012 JTAG programmer.
2516 This has one driver-specific command:
2518 @deffn {Config Command} {parport_port} [port_number]
2519 Display either the address of the I/O port
2520 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2521 If a parameter is provided, first switch to use that port.
2522 This is a write-once setting.
2523 @end deffn
2524 @end deffn
2526 @deffn {Interface Driver} {jlink}
2527 Segger jlink USB adapter
2528 @c command: jlink caps
2529 @c dumps jlink capabilities
2530 @c command: jlink config
2531 @c access J-Link configurationif no argument this will dump the config
2532 @c command: jlink config kickstart [val]
2533 @c set Kickstart power on JTAG-pin 19.
2534 @c command: jlink config mac_address [ff:ff:ff:ff:ff:ff]
2535 @c set the MAC Address
2536 @c command: jlink config ip [A.B.C.D[/E] [F.G.H.I]]
2537 @c set the ip address of the J-Link Pro, "
2538 @c where A.B.C.D is the ip,
2539 @c E the bit of the subnet mask
2540 @c F.G.H.I the subnet mask
2541 @c command: jlink config reset
2542 @c reset the current config
2543 @c command: jlink config save
2544 @c save the current config
2545 @c command: jlink config usb_address [0x00 to 0x03 or 0xff]
2546 @c set the USB-Address,
2547 @c This will change the product id
2548 @c command: jlink info
2549 @c dumps status
2550 @c command: jlink hw_jtag (2|3)
2551 @c sets version 2 or 3
2552 @c command: jlink pid
2553 @c set the pid of the interface we want to use
2554 @end deffn
2556 @deffn {Interface Driver} {parport}
2557 Supports PC parallel port bit-banging cables:
2558 Wigglers, PLD download cable, and more.
2559 These interfaces have several commands, used to configure the driver
2560 before initializing the JTAG scan chain:
2562 @deffn {Config Command} {parport_cable} name
2563 Set the layout of the parallel port cable used to connect to the target.
2564 This is a write-once setting.
2565 Currently valid cable @var{name} values include:
2567 @itemize @minus
2568 @item @b{altium} Altium Universal JTAG cable.
2569 @item @b{arm-jtag} Same as original wiggler except SRST and
2570 TRST connections reversed and TRST is also inverted.
2571 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2572 in configuration mode. This is only used to
2573 program the Chameleon itself, not a connected target.
2574 @item @b{dlc5} The Xilinx Parallel cable III.
2575 @item @b{flashlink} The ST Parallel cable.
2576 @item @b{lattice} Lattice ispDOWNLOAD Cable
2577 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2578 some versions of
2579 Amontec's Chameleon Programmer. The new version available from
2580 the website uses the original Wiggler layout ('@var{wiggler}')
2581 @item @b{triton} The parallel port adapter found on the
2582 ``Karo Triton 1 Development Board''.
2583 This is also the layout used by the HollyGates design
2584 (see @uref{}).
2585 @item @b{wiggler} The original Wiggler layout, also supported by
2586 several clones, such as the Olimex ARM-JTAG
2587 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2588 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2589 @end itemize
2590 @end deffn
2592 @deffn {Config Command} {parport_port} [port_number]
2593 Display either the address of the I/O port
2594 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2595 If a parameter is provided, first switch to use that port.
2596 This is a write-once setting.
2598 When using PPDEV to access the parallel port, use the number of the parallel port:
2599 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2600 you may encounter a problem.
2601 @end deffn
2603 @deffn Command {parport_toggling_time} [nanoseconds]
2604 Displays how many nanoseconds the hardware needs to toggle TCK;
2605 the parport driver uses this value to obey the
2606 @command{adapter_khz} configuration.
2607 When the optional @var{nanoseconds} parameter is given,
2608 that setting is changed before displaying the current value.
2610 The default setting should work reasonably well on commodity PC hardware.
2611 However, you may want to calibrate for your specific hardware.
2612 @quotation Tip
2613 To measure the toggling time with a logic analyzer or a digital storage
2614 oscilloscope, follow the procedure below:
2615 @example
2616 > parport_toggling_time 1000
2617 > adapter_khz 500
2618 @end example
2619 This sets the maximum JTAG clock speed of the hardware, but
2620 the actual speed probably deviates from the requested 500 kHz.
2621 Now, measure the time between the two closest spaced TCK transitions.
2622 You can use @command{runtest 1000} or something similar to generate a
2623 large set of samples.
2624 Update the setting to match your measurement:
2625 @example
2626 > parport_toggling_time <measured nanoseconds>
2627 @end example
2628 Now the clock speed will be a better match for @command{adapter_khz rate}
2629 commands given in OpenOCD scripts and event handlers.
2631 You can do something similar with many digital multimeters, but note
2632 that you'll probably need to run the clock continuously for several
2633 seconds before it decides what clock rate to show. Adjust the
2634 toggling time up or down until the measured clock rate is a good
2635 match for the adapter_khz rate you specified; be conservative.
2636 @end quotation
2637 @end deffn
2639 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2640 This will configure the parallel driver to write a known
2641 cable-specific value to the parallel interface on exiting OpenOCD.
2642 @end deffn
2644 For example, the interface configuration file for a
2645 classic ``Wiggler'' cable on LPT2 might look something like this:
2647 @example
2648 interface parport
2649 parport_port 0x278
2650 parport_cable wiggler
2651 @end example
2652 @end deffn
2654 @deffn {Interface Driver} {presto}
2655 ASIX PRESTO USB JTAG programmer.
2656 @deffn {Config Command} {presto_serial} serial_string
2657 Configures the USB serial number of the Presto device to use.
2658 @end deffn
2659 @end deffn
2661 @deffn {Interface Driver} {rlink}
2662 Raisonance RLink USB adapter
2663 @end deffn
2665 @deffn {Interface Driver} {usbprog}
2666 usbprog is a freely programmable USB adapter.
2667 @end deffn
2669 @deffn {Interface Driver} {vsllink}
2670 vsllink is part of Versaloon which is a versatile USB programmer.
2672 @quotation Note
2673 This defines quite a few driver-specific commands,
2674 which are not currently documented here.
2675 @end quotation
2676 @end deffn
2678 @deffn {Interface Driver} {stlink}
2679 ST Micro ST-LINK adapter.
2681 @deffn {Config Command} {stlink_device_desc} description
2682 Currently Not Supported.
2683 @end deffn
2685 @deffn {Config Command} {stlink_serial} serial
2686 Currently Not Supported.
2687 @end deffn
2689 @deffn {Config Command} {stlink_layout} (@option{sg}|@option{usb})
2690 Specifies the stlink layout to use.
2691 @end deffn
2693 @deffn {Config Command} {stlink_vid_pid} vid pid
2694 The vendor ID and product ID of the STLINK device.
2695 @end deffn
2697 @deffn {Config Command} {stlink_api} api_level
2698 Manually sets the stlink api used, valid options are 1 or 2.
2699 @end deffn
2700 @end deffn
2702 @deffn {Interface Driver} {opendous}
2703 opendous-jtag is a freely programmable USB adapter.
2704 @end deffn
2706 @deffn {Interface Driver} {ZY1000}
2707 This is the Zylin ZY1000 JTAG debugger.
2708 @end deffn
2710 @quotation Note
2711 This defines some driver-specific commands,
2712 which are not currently documented here.
2713 @end quotation
2715 @deffn Command power [@option{on}|@option{off}]
2716 Turn power switch to target on/off.
2717 No arguments: print status.
2718 @end deffn
2720 @section Transport Configuration
2721 @cindex Transport
2722 As noted earlier, depending on the version of OpenOCD you use,
2723 and the debug adapter you are using,
2724 several transports may be available to
2725 communicate with debug targets (or perhaps to program flash memory).
2726 @deffn Command {transport list}
2727 displays the names of the transports supported by this
2728 version of OpenOCD.
2729 @end deffn
2731 @deffn Command {transport select} transport_name
2732 Select which of the supported transports to use in this OpenOCD session.
2733 The transport must be supported by the debug adapter hardware and by the
2734 version of OPenOCD you are using (including the adapter's driver).
2735 No arguments: returns name of session's selected transport.
2736 @end deffn
2738 @subsection JTAG Transport
2739 @cindex JTAG
2740 JTAG is the original transport supported by OpenOCD, and most
2741 of the OpenOCD commands support it.
2742 JTAG transports expose a chain of one or more Test Access Points (TAPs),
2743 each of which must be explicitly declared.
2744 JTAG supports both debugging and boundary scan testing.
2745 Flash programming support is built on top of debug support.
2746 @subsection SWD Transport
2747 @cindex SWD
2748 @cindex Serial Wire Debug
2749 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
2750 Debug Access Point (DAP, which must be explicitly declared.
2751 (SWD uses fewer signal wires than JTAG.)
2752 SWD is debug-oriented, and does not support boundary scan testing.
2753 Flash programming support is built on top of debug support.
2754 (Some processors support both JTAG and SWD.)
2755 @deffn Command {swd newdap} ...
2756 Declares a single DAP which uses SWD transport.
2757 Parameters are currently the same as "jtag newtap" but this is
2758 expected to change.
2759 @end deffn
2760 @deffn Command {swd wcr trn prescale}
2761 Updates TRN (turnaraound delay) and prescaling.fields of the
2762 Wire Control Register (WCR).
2763 No parameters: displays current settings.
2764 @end deffn
2766 @subsection SPI Transport
2767 @cindex SPI
2768 @cindex Serial Peripheral Interface
2769 The Serial Peripheral Interface (SPI) is a general purpose transport
2770 which uses four wire signaling. Some processors use it as part of a
2771 solution for flash programming.
2773 @anchor{JTAG Speed}
2774 @section JTAG Speed
2775 JTAG clock setup is part of system setup.
2776 It @emph{does not belong with interface setup} since any interface
2777 only knows a few of the constraints for the JTAG clock speed.
2778 Sometimes the JTAG speed is
2779 changed during the target initialization process: (1) slow at
2780 reset, (2) program the CPU clocks, (3) run fast.
2781 Both the "slow" and "fast" clock rates are functions of the
2782 oscillators used, the chip, the board design, and sometimes
2783 power management software that may be active.
2785 The speed used during reset, and the scan chain verification which
2786 follows reset, can be adjusted using a @code{reset-start}
2787 target event handler.
2788 It can then be reconfigured to a faster speed by a
2789 @code{reset-init} target event handler after it reprograms those
2790 CPU clocks, or manually (if something else, such as a boot loader,
2791 sets up those clocks).
2792 @xref{Target Events}.
2793 When the initial low JTAG speed is a chip characteristic, perhaps
2794 because of a required oscillator speed, provide such a handler
2795 in the target config file.
2796 When that speed is a function of a board-specific characteristic
2797 such as which speed oscillator is used, it belongs in the board
2798 config file instead.
2799 In both cases it's safest to also set the initial JTAG clock rate
2800 to that same slow speed, so that OpenOCD never starts up using a
2801 clock speed that's faster than the scan chain can support.
2803 @example
2804 jtag_rclk 3000
2805 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
2806 @end example
2808 If your system supports adaptive clocking (RTCK), configuring
2809 JTAG to use that is probably the most robust approach.
2810 However, it introduces delays to synchronize clocks; so it
2811 may not be the fastest solution.
2813 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
2814 instead of @command{adapter_khz}, but only for (ARM) cores and boards
2815 which support adaptive clocking.
2817 @deffn {Command} adapter_khz max_speed_kHz
2818 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
2819 JTAG interfaces usually support a limited number of
2820 speeds. The speed actually used won't be faster
2821 than the speed specified.
2823 Chip data sheets generally include a top JTAG clock rate.
2824 The actual rate is often a function of a CPU core clock,
2825 and is normally less than that peak rate.
2826 For example, most ARM cores accept at most one sixth of the CPU clock.
2828 Speed 0 (khz) selects RTCK method.
2829 @xref{FAQ RTCK}.
2830 If your system uses RTCK, you won't need to change the
2831 JTAG clocking after setup.
2832 Not all interfaces, boards, or targets support ``rtck''.
2833 If the interface device can not
2834 support it, an error is returned when you try to use RTCK.
2835 @end deffn
2837 @defun jtag_rclk fallback_speed_kHz
2838 @cindex adaptive clocking
2839 @cindex RTCK
2840 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
2841 If that fails (maybe the interface, board, or target doesn't
2842 support it), falls back to the specified frequency.
2843 @example
2844 # Fall back to 3mhz if RTCK is not supported
2845 jtag_rclk 3000
2846 @end example
2847 @end defun
2849 @node Reset Configuration
2850 @chapter Reset Configuration
2851 @cindex Reset Configuration
2853 Every system configuration may require a different reset
2854 configuration. This can also be quite confusing.
2855 Resets also interact with @var{reset-init} event handlers,
2856 which do things like setting up clocks and DRAM, and
2857 JTAG clock rates. (@xref{JTAG Speed}.)
2858 They can also interact with JTAG routers.
2859 Please see the various board files for examples.
2861 @quotation Note
2862 To maintainers and integrators:
2863 Reset configuration touches several things at once.
2864 Normally the board configuration file
2865 should define it and assume that the JTAG adapter supports
2866 everything that's wired up to the board's JTAG connector.
2868 However, the target configuration file could also make note
2869 of something the silicon vendor has done inside the chip,
2870 which will be true for most (or all) boards using that chip.
2871 And when the JTAG adapter doesn't support everything, the
2872 user configuration file will need to override parts of
2873 the reset configuration provided by other files.
2874 @end quotation
2876 @section Types of Reset
2878 There are many kinds of reset possible through JTAG, but
2879 they may not all work with a given board and adapter.
2880 That's part of why reset configuration can be error prone.
2882 @itemize @bullet
2883 @item
2884 @emph{System Reset} ... the @emph{SRST} hardware signal
2885 resets all chips connected to the JTAG adapter, such as processors,
2886 power management chips, and I/O controllers. Normally resets triggered
2887 with this signal behave exactly like pressing a RESET button.
2888 @item
2889 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
2890 just the TAP controllers connected to the JTAG adapter.
2891 Such resets should not be visible to the rest of the system; resetting a
2892 device's TAP controller just puts that controller into a known state.
2893 @item
2894 @emph{Emulation Reset} ... many devices can be reset through JTAG
2895 commands. These resets are often distinguishable from system
2896 resets, either explicitly (a "reset reason" register says so)
2897 or implicitly (not all parts of the chip get reset).
2898 @item
2899 @emph{Other Resets} ... system-on-chip devices often support
2900 several other types of reset.
2901 You may need to arrange that a watchdog timer stops
2902 while debugging, preventing a watchdog reset.
2903 There may be individual module resets.
2904 @end itemize
2906 In the best case, OpenOCD can hold SRST, then reset
2907 the TAPs via TRST and send commands through JTAG to halt the
2908 CPU at the reset vector before the 1st instruction is executed.
2909 Then when it finally releases the SRST signal, the system is
2910 halted under debugger control before any code has executed.
2911 This is the behavior required to support the @command{reset halt}
2912 and @command{reset init} commands; after @command{reset init} a
2913 board-specific script might do things like setting up DRAM.
2914 (@xref{Reset Command}.)
2916 @anchor{SRST and TRST Issues}
2917 @section SRST and TRST Issues
2919 Because SRST and TRST are hardware signals, they can have a
2920 variety of system-specific constraints. Some of the most
2921 common issues are:
2923 @itemize @bullet
2925 @item @emph{Signal not available} ... Some boards don't wire
2926 SRST or TRST to the JTAG connector. Some JTAG adapters don't
2927 support such signals even if they are wired up.
2928 Use the @command{reset_config} @var{signals} options to say
2929 when either of those signals is not connected.
2930 When SRST is not available, your code might not be able to rely
2931 on controllers having been fully reset during code startup.
2932 Missing TRST is not a problem, since JTAG-level resets can
2933 be triggered using with TMS signaling.
2935 @item @emph{Signals shorted} ... Sometimes a chip, board, or
2936 adapter will connect SRST to TRST, instead of keeping them separate.
2937 Use the @command{reset_config} @var{combination} options to say
2938 when those signals aren't properly independent.
2940 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
2941 delay circuit, reset supervisor, or on-chip features can extend
2942 the effect of a JTAG adapter's reset for some time after the adapter
2943 stops issuing the reset. For example, there may be chip or board
2944 requirements that all reset pulses last for at least a
2945 certain amount of time; and reset buttons commonly have
2946 hardware debouncing.
2947 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
2948 commands to say when extra delays are needed.
2950 @item @emph{Drive type} ... Reset lines often have a pullup
2951 resistor, letting the JTAG interface treat them as open-drain
2952 signals. But that's not a requirement, so the adapter may need
2953 to use push/pull output drivers.
2954 Also, with weak pullups it may be advisable to drive
2955 signals to both levels (push/pull) to minimize rise times.
2956 Use the @command{reset_config} @var{trst_type} and
2957 @var{srst_type} parameters to say how to drive reset signals.
2959 @item @emph{Special initialization} ... Targets sometimes need
2960 special JTAG initialization sequences to handle chip-specific
2961 issues (not limited to errata).
2962 For example, certain JTAG commands might need to be issued while
2963 the system as a whole is in a reset state (SRST active)
2964 but the JTAG scan chain is usable (TRST inactive).
2965 Many systems treat combined assertion of SRST and TRST as a
2966 trigger for a harder reset than SRST alone.
2967 Such custom reset handling is discussed later in this chapter.
2968 @end itemize
2970 There can also be other issues.
2971 Some devices don't fully conform to the JTAG specifications.
2972 Trivial system-specific differences are common, such as
2973 SRST and TRST using slightly different names.
2974 There are also vendors who distribute key JTAG documentation for
2975 their chips only to developers who have signed a Non-Disclosure
2976 Agreement (NDA).
2978 Sometimes there are chip-specific extensions like a requirement to use
2979 the normally-optional TRST signal (precluding use of JTAG adapters which
2980 don't pass TRST through), or needing extra steps to complete a TAP reset.
2982 In short, SRST and especially TRST handling may be very finicky,
2983 needing to cope with both architecture and board specific constraints.
2985 @section Commands for Handling Resets
2987 @deffn {Command} adapter_nsrst_assert_width milliseconds
2988 Minimum amount of time (in milliseconds) OpenOCD should wait
2989 after asserting nSRST (active-low system reset) before
2990 allowing it to be deasserted.
2991 @end deffn
2993 @deffn {Command} adapter_nsrst_delay milliseconds
2994 How long (in milliseconds) OpenOCD should wait after deasserting
2995 nSRST (active-low system reset) before starting new JTAG operations.
2996 When a board has a reset button connected to SRST line it will
2997 probably have hardware debouncing, implying you should use this.
2998 @end deffn
3000 @deffn {Command} jtag_ntrst_assert_width milliseconds
3001 Minimum amount of time (in milliseconds) OpenOCD should wait
3002 after asserting nTRST (active-low JTAG TAP reset) before
3003 allowing it to be deasserted.
3004 @end deffn
3006 @deffn {Command} jtag_ntrst_delay milliseconds
3007 How long (in milliseconds) OpenOCD should wait after deasserting
3008 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3009 @end deffn
3011 @deffn {Command} reset_config mode_flag ...
3012 This command displays or modifies the reset configuration
3013 of your combination of JTAG board and target in target
3014 configuration scripts.
3016 Information earlier in this section describes the kind of problems
3017 the command is intended to address (@pxref{SRST and TRST Issues}).
3018 As a rule this command belongs only in board config files,
3019 describing issues like @emph{board doesn't connect TRST};
3020 or in user config files, addressing limitations derived
3021 from a particular combination of interface and board.
3022 (An unlikely example would be using a TRST-only adapter
3023 with a board that only wires up SRST.)
3025 The @var{mode_flag} options can be specified in any order, but only one
3026 of each type -- @var{signals}, @var{combination},
3027 @var{gates},
3028 @var{trst_type},
3029 and @var{srst_type} -- may be specified at a time.
3030 If you don't provide a new value for a given type, its previous
3031 value (perhaps the default) is unchanged.
3032 For example, this means that you don't need to say anything at all about
3033 TRST just to declare that if the JTAG adapter should want to drive SRST,
3034 it must explicitly be driven high (@option{srst_push_pull}).
3036 @itemize
3037 @item
3038 @var{signals} can specify which of the reset signals are connected.
3039 For example, If the JTAG interface provides SRST, but the board doesn't
3040 connect that signal properly, then OpenOCD can't use it.
3041 Possible values are @option{none} (the default), @option{trst_only},
3042 @option{srst_only} and @option{trst_and_srst}.
3044 @quotation Tip
3045 If your board provides SRST and/or TRST through the JTAG connector,
3046 you must declare that so those signals can be used.
3047 @end quotation
3049 @item
3050 The @var{combination} is an optional value specifying broken reset
3051 signal implementations.
3052 The default behaviour if no option given is @option{separate},
3053 indicating everything behaves normally.
3054 @option{srst_pulls_trst} states that the
3055 test logic is reset together with the reset of the system (e.g. NXP
3056 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3057 the system is reset together with the test logic (only hypothetical, I
3058 haven't seen hardware with such a bug, and can be worked around).
3059 @option{combined} implies both @option{srst_pulls_trst} and
3060 @option{trst_pulls_srst}.
3062 @item
3063 The @var{gates} tokens control flags that describe some cases where
3064 JTAG may be unvailable during reset.
3065 @option{srst_gates_jtag} (default)
3066 indicates that asserting SRST gates the
3067 JTAG clock. This means that no communication can happen on JTAG
3068 while SRST is asserted.
3069 Its converse is @option{srst_nogate}, indicating that JTAG commands
3070 can safely be issued while SRST is active.
3071 @end itemize
3073 The optional @var{trst_type} and @var{srst_type} parameters allow the
3074 driver mode of each reset line to be specified. These values only affect
3075 JTAG interfaces with support for different driver modes, like the Amontec
3076 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3077 relevant signal (TRST or SRST) is not connected.
3079 @itemize
3080 @item
3081 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3082 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3083 Most boards connect this signal to a pulldown, so the JTAG TAPs
3084 never leave reset unless they are hooked up to a JTAG adapter.
3086 @item
3087 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3088 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3089 Most boards connect this signal to a pullup, and allow the
3090 signal to be pulled low by various events including system
3091 powerup and pressing a reset button.
3092 @end itemize
3093 @end deffn
3095 @section Custom Reset Handling
3096 @cindex events
3098 OpenOCD has several ways to help support the various reset
3099 mechanisms provided by chip and board vendors.
3100 The commands shown in the previous section give standard parameters.
3101 There are also @emph{event handlers} associated with TAPs or Targets.
3102 Those handlers are Tcl procedures you can provide, which are invoked
3103 at particular points in the reset sequence.
3105 @emph{When SRST is not an option} you must set
3106 up a @code{reset-assert} event handler for your target.
3107 For example, some JTAG adapters don't include the SRST signal;
3108 and some boards have multiple targets, and you won't always
3109 want to reset everything at once.
3111 After configuring those mechanisms, you might still
3112 find your board doesn't start up or reset correctly.
3113 For example, maybe it needs a slightly different sequence
3114 of SRST and/or TRST manipulations, because of quirks that
3115 the @command{reset_config} mechanism doesn't address;
3116 or asserting both might trigger a stronger reset, which
3117 needs special attention.
3119 Experiment with lower level operations, such as @command{jtag_reset}
3120 and the @command{jtag arp_*} operations shown here,
3121 to find a sequence of operations that works.
3122 @xref{JTAG Commands}.
3123 When you find a working sequence, it can be used to override
3124 @command{jtag_init}, which fires during OpenOCD startup
3125 (@pxref{Configuration Stage});
3126 or @command{init_reset}, which fires during reset processing.
3128 You might also want to provide some project-specific reset
3129 schemes. For example, on a multi-target board the standard
3130 @command{reset} command would reset all targets, but you
3131 may need the ability to reset only one target at time and
3132 thus want to avoid using the board-wide SRST signal.
3134 @deffn {Overridable Procedure} init_reset mode
3135 This is invoked near the beginning of the @command{reset} command,
3136 usually to provide as much of a cold (power-up) reset as practical.
3137 By default it is also invoked from @command{jtag_init} if
3138 the scan chain does not respond to pure JTAG operations.
3139 The @var{mode} parameter is the parameter given to the
3140 low level reset command (@option{halt},
3141 @option{init}, or @option{run}), @option{setup},
3142 or potentially some other value.
3144 The default implementation just invokes @command{jtag arp_init-reset}.
3145 Replacements will normally build on low level JTAG
3146 operations such as @command{jtag_reset}.
3147 Operations here must not address individual TAPs
3148 (or their associated targets)
3149 until the JTAG scan chain has first been verified to work.
3151 Implementations must have verified the JTAG scan chain before
3152 they return.
3153 This is done by calling @command{jtag arp_init}
3154 (or @command{jtag arp_init-reset}).
3155 @end deffn
3157 @deffn Command {jtag arp_init}
3158 This validates the scan chain using just the four
3159 standard JTAG signals (TMS, TCK, TDI, TDO).
3160 It starts by issuing a JTAG-only reset.
3161 Then it performs checks to verify that the scan chain configuration
3162 matches the TAPs it can observe.
3163 Those checks include checking IDCODE values for each active TAP,
3164 and verifying the length of their instruction registers using
3165 TAP @code{-ircapture} and @code{-irmask} values.
3166 If these tests all pass, TAP @code{setup} events are
3167 issued to all TAPs with handlers for that event.
3168 @end deffn
3170 @deffn Command {jtag arp_init-reset}
3171 This uses TRST and SRST to try resetting
3172 everything on the JTAG scan chain
3173 (and anything else connected to SRST).
3174 It then invokes the logic of @command{jtag arp_init}.
3175 @end deffn
3178 @node TAP Declaration
3179 @chapter TAP Declaration
3180 @cindex TAP declaration
3181 @cindex TAP configuration
3183 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3184 TAPs serve many roles, including:
3186 @itemize @bullet
3187 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
3188 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
3189 Others do it indirectly, making a CPU do it.
3190 @item @b{Program Download} Using the same CPU support GDB uses,
3191 you can initialize a DRAM controller, download code to DRAM, and then
3192 start running that code.
3193 @item @b{Boundary Scan} Most chips support boundary scan, which
3194 helps test for board assembly problems like solder bridges
3195 and missing connections
3196 @end itemize
3198 OpenOCD must know about the active TAPs on your board(s).
3199 Setting up the TAPs is the core task of your configuration files.
3200 Once those TAPs are set up, you can pass their names to code
3201 which sets up CPUs and exports them as GDB targets,
3202 probes flash memory, performs low-level JTAG operations, and more.
3204 @section Scan Chains
3205 @cindex scan chain
3207 TAPs are part of a hardware @dfn{scan chain},
3208 which is daisy chain of TAPs.
3209 They also need to be added to
3210 OpenOCD's software mirror of that hardware list,
3211 giving each member a name and associating other data with it.
3212 Simple scan chains, with a single TAP, are common in
3213 systems with a single microcontroller or microprocessor.
3214 More complex chips may have several TAPs internally.
3215 Very complex scan chains might have a dozen or more TAPs:
3216 several in one chip, more in the next, and connecting
3217 to other boards with their own chips and TAPs.
3219 You can display the list with the @command{scan_chain} command.
3220 (Don't confuse this with the list displayed by the @command{targets}
3221 command, presented in the next chapter.
3222 That only displays TAPs for CPUs which are configured as
3223 debugging targets.)
3224 Here's what the scan chain might look like for a chip more than one TAP:
3226 @verbatim
3227 TapName Enabled IdCode Expected IrLen IrCap IrMask
3228 -- ------------------ ------- ---------- ---------- ----- ----- ------
3229 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3230 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3231 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3232 @end verbatim
3234 OpenOCD can detect some of that information, but not all
3235 of it. @xref{Autoprobing}.
3236 Unfortunately those TAPs can't always be autoconfigured,
3237 because not all devices provide good support for that.
3238 JTAG doesn't require supporting IDCODE instructions, and
3239 chips with JTAG routers may not link TAPs into the chain
3240 until they are told to do so.
3242 The configuration mechanism currently supported by OpenOCD
3243 requires explicit configuration of all TAP devices using
3244 @command{jtag newtap} commands, as detailed later in this chapter.
3245 A command like this would declare one tap and name it @code{chip1.cpu}:
3247 @example
3248 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3249 @end example
3251 Each target configuration file lists the TAPs provided
3252 by a given chip.
3253 Board configuration files combine all the targets on a board,
3254 and so forth.
3255 Note that @emph{the order in which TAPs are declared is very important.}
3256 It must match the order in the JTAG scan chain, both inside
3257 a single chip and between them.
3258 @xref{FAQ TAP Order}.
3260 For example, the ST Microsystems STR912 chip has
3261 three separate TAPs@footnote{See the ST
3262 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3263 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3264 @url{}}.
3265 To configure those taps, @file{target/str912.cfg}
3266 includes commands something like this:
3268 @example
3269 jtag newtap str912 flash ... params ...
3270 jtag newtap str912 cpu ... params ...
3271 jtag newtap str912 bs ... params ...
3272 @end example
3274 Actual config files use a variable instead of literals like
3275 @option{str912}, to support more than one chip of each type.
3276 @xref{Config File Guidelines}.
3278 @deffn Command {jtag names}
3279 Returns the names of all current TAPs in the scan chain.
3280 Use @command{jtag cget} or @command{jtag tapisenabled}
3281 to examine attributes and state of each TAP.
3282 @example
3283 foreach t [jtag names] @{
3284 puts [format "TAP: %s\n" $t]
3285 @}
3286 @end example
3287 @end deffn
3289 @deffn Command {scan_chain}
3290 Displays the TAPs in the scan chain configuration,
3291 and their status.
3292 The set of TAPs listed by this command is fixed by
3293 exiting the OpenOCD configuration stage,
3294 but systems with a JTAG router can
3295 enable or disable TAPs dynamically.
3296 @end deffn
3298 @c FIXME! "jtag cget" should be able to return all TAP
3299 @c attributes, like "$target_name cget" does for targets.
3301 @c Probably want "jtag eventlist", and a "tap-reset" event
3302 @c (on entry to RESET state).
3304 @section TAP Names
3305 @cindex dotted name
3307 When TAP objects are declared with @command{jtag newtap},
3308 a @dfn{} is created for the TAP, combining the
3309 name of a module (usually a chip) and a label for the TAP.
3310 For example: @code{xilinx.tap}, @code{str912.flash},
3311 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3312 Many other commands use that to manipulate or
3313 refer to the TAP. For example, CPU configuration uses the
3314 name, as does declaration of NAND or NOR flash banks.
3316 The components of a dotted name should follow ``C'' symbol
3317 name rules: start with an alphabetic character, then numbers
3318 and underscores are OK; while others (including dots!) are not.
3320 @quotation Tip
3321 In older code, JTAG TAPs were numbered from 0..N.
3322 This feature is still present.
3323 However its use is highly discouraged, and
3324 should not be relied on; it will be removed by mid-2010.
3325 Update all of your scripts to use TAP names rather than numbers,
3326 by paying attention to the runtime warnings they trigger.
3327 Using TAP numbers in target configuration scripts prevents
3328 reusing those scripts on boards with multiple targets.
3329 @end quotation
3331 @section TAP Declaration Commands
3333 @c shouldn't this be(come) a {Config Command}?
3334 @anchor{jtag newtap}
3335 @deffn Command {jtag newtap} chipname tapname configparams...
3336 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3337 and configured according to the various @var{configparams}.
3339 The @var{chipname} is a symbolic name for the chip.
3340 Conventionally target config files use @code{$_CHIPNAME},
3341 defaulting to the model name given by the chip vendor but
3342 overridable.
3344 @cindex TAP naming convention
3345 The @var{tapname} reflects the role of that TAP,
3346 and should follow this convention:
3348 @itemize @bullet
3349 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3350 @item @code{cpu} -- The main CPU of the chip, alternatively
3351 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3352 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3353 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3354 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3355 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3356 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3357 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3358 with a single TAP;
3359 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3360 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3361 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3362 a JTAG TAP; that TAP should be named @code{sdma}.
3363 @end itemize
3365 Every TAP requires at least the following @var{configparams}:
3367 @itemize @bullet
3368 @item @code{-irlen} @var{NUMBER}
3369 @*The length in bits of the
3370 instruction register, such as 4 or 5 bits.
3371 @end itemize
3373 A TAP may also provide optional @var{configparams}:
3375 @itemize @bullet
3376 @item @code{-disable} (or @code{-enable})
3377 @*Use the @code{-disable} parameter to flag a TAP which is not
3378 linked in to the scan chain after a reset using either TRST
3379 or the JTAG state machine's @sc{reset} state.
3380 You may use @code{-enable} to highlight the default state
3381 (the TAP is linked in).
3382 @xref{Enabling and Disabling TAPs}.
3383 @item @code{-expected-id} @var{number}
3384 @*A non-zero @var{number} represents a 32-bit IDCODE
3385 which you expect to find when the scan chain is examined.
3386 These codes are not required by all JTAG devices.
3387 @emph{Repeat the option} as many times as required if more than one
3388 ID code could appear (for example, multiple versions).
3389 Specify @var{number} as zero to suppress warnings about IDCODE
3390 values that were found but not included in the list.
3392 Provide this value if at all possible, since it lets OpenOCD
3393 tell when the scan chain it sees isn't right. These values
3394 are provided in vendors' chip documentation, usually a technical
3395 reference manual. Sometimes you may need to probe the JTAG
3396 hardware to find these values.
3397 @xref{Autoprobing}.
3398 @item @code{-ignore-version}
3399 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3400 option. When vendors put out multiple versions of a chip, or use the same
3401 JTAG-level ID for several largely-compatible chips, it may be more practical
3402 to ignore the version field than to update config files to handle all of
3403 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3404 @item @code{-ircapture} @var{NUMBER}
3405 @*The bit pattern loaded by the TAP into the JTAG shift register
3406 on entry to the @sc{ircapture} state, such as 0x01.
3407 JTAG requires the two LSBs of this value to be 01.
3408 By default, @code{-ircapture} and @code{-irmask} are set
3409 up to verify that two-bit value. You may provide
3410 additional bits, if you know them, or indicate that
3411 a TAP doesn't conform to the JTAG specification.
3412 @item @code{-irmask} @var{NUMBER}
3413 @*A mask used with @code{-ircapture}
3414 to verify that instruction scans work correctly.
3415 Such scans are not used by OpenOCD except to verify that
3416 there seems to be no problems with JTAG scan chain operations.
3417 @end itemize
3418 @end deffn
3420 @section Other TAP commands
3422 @deffn Command {jtag cget} @option{-event} name
3423 @deffnx Command {jtag configure} @option{-event} name string
3424 At this writing this TAP attribute
3425 mechanism is used only for event handling.
3426 (It is not a direct analogue of the @code{cget}/@code{configure}
3427 mechanism for debugger targets.)
3428 See the next section for information about the available events.
3430 The @code{configure} subcommand assigns an event handler,
3431 a TCL string which is evaluated when the event is triggered.
3432 The @code{cget} subcommand returns that handler.
3433 @end deffn
3435 @anchor{TAP Events}
3436 @section TAP Events
3437 @cindex events
3438 @cindex TAP events
3440 OpenOCD includes two event mechanisms.
3441 The one presented here applies to all JTAG TAPs.
3442 The other applies to debugger targets,
3443 which are associated with certain TAPs.
3445 The TAP events currently defined are:
3447 @itemize @bullet
3448 @item @b{post-reset}
3449 @* The TAP has just completed a JTAG reset.
3450 The tap may still be in the JTAG @sc{reset} state.
3451 Handlers for these events might perform initialization sequences
3452 such as issuing TCK cycles, TMS sequences to ensure
3453 exit from the ARM SWD mode, and more.
3455 Because the scan chain has not yet been verified, handlers for these events
3456 @emph{should not issue commands which scan the JTAG IR or DR registers}
3457 of any particular target.
3458 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3459 @item @b{setup}
3460 @* The scan chain has been reset and verified.
3461 This handler may enable TAPs as needed.
3462 @item @b{tap-disable}
3463 @* The TAP needs to be disabled. This handler should
3464 implement @command{jtag tapdisable}
3465 by issuing the relevant JTAG commands.
3466 @item @b{tap-enable}
3467 @* The TAP needs to be enabled. This handler should
3468 implement @command{jtag tapenable}
3469 by issuing the relevant JTAG commands.
3470 @end itemize
3472 If you need some action after each JTAG reset, which isn't actually
3473 specific to any TAP (since you can't yet trust the scan chain's
3474 contents to be accurate), you might:
3476 @example
3477 jtag configure CHIP.jrc -event post-reset @{
3478 echo "JTAG Reset done"
3479 ... non-scan jtag operations to be done after reset
3480 @}
3481 @end example
3484 @anchor{Enabling and Disabling TAPs}
3485 @section Enabling and Disabling TAPs
3486 @cindex JTAG Route Controller
3487 @cindex jrc
3489 In some systems, a @dfn{JTAG Route Controller} (JRC)
3490 is used to enable and/or disable specific JTAG TAPs.
3491 Many ARM based chips from Texas Instruments include
3492 an ``ICEpick'' module, which is a JRC.
3493 Such chips include DaVinci and OMAP3 processors.
3495 A given TAP may not be visible until the JRC has been
3496 told to link it into the scan chain; and if the JRC
3497 has been told to unlink that TAP, it will no longer
3498 be visible.
3499 Such routers address problems that JTAG ``bypass mode''
3500 ignores, such as:
3502 @itemize
3503 @item The scan chain can only go as fast as its slowest TAP.
3504 @item Having many TAPs slows instruction scans, since all
3505 TAPs receive new instructions.
3506 @item TAPs in the scan chain must be powered up, which wastes
3507 power and prevents debugging some power management mechanisms.
3508 @end itemize
3510 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3511 as implied by the existence of JTAG routers.
3512 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3513 does include a kind of JTAG router functionality.
3515 @c (a) currently the event handlers don't seem to be able to
3516 @c fail in a way that could lead to no-change-of-state.
3518 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3519 shown below, and is implemented using TAP event handlers.
3520 So for example, when defining a TAP for a CPU connected to
3521 a JTAG router, your @file{target.cfg} file
3522 should define TAP event handlers using
3523 code that looks something like this:
3525 @example
3526 jtag configure CHIP.cpu -event tap-enable @{
3527 ... jtag operations using CHIP.jrc
3528 @}
3529 jtag configure CHIP.cpu -event tap-disable @{
3530 ... jtag operations using CHIP.jrc
3531 @}
3532 @end example
3534 Then you might want that CPU's TAP enabled almost all the time:
3536 @example
3537 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3538 @end example
3540 Note how that particular setup event handler declaration
3541 uses quotes to evaluate @code{$CHIP} when the event is configured.
3542 Using brackets @{ @} would cause it to be evaluated later,
3543 at runtime, when it might have a different value.
3545 @deffn Command {jtag tapdisable}
3546 If necessary, disables the tap
3547 by sending it a @option{tap-disable} event.
3548 Returns the string "1" if the tap
3549 specified by @var{} is enabled,
3550 and "0" if it is disabled.
3551 @end deffn
3553 @deffn Command {jtag tapenable}
3554 If necessary, enables the tap
3555 by sending it a @option{tap-enable} event.
3556 Returns the string "1" if the tap
3557 specified by @var{} is enabled,
3558 and "0" if it is disabled.
3559 @end deffn
3561 @deffn Command {jtag tapisenabled}
3562 Returns the string "1" if the tap
3563 specified by @var{} is enabled,
3564 and "0" if it is disabled.
3566 @quotation Note
3567 Humans will find the @command{scan_chain} command more helpful
3568 for querying the state of the JTAG taps.
3569 @end quotation
3570 @end deffn
3572 @anchor{Autoprobing}
3573 @section Autoprobing
3574 @cindex autoprobe
3575 @cindex JTAG autoprobe
3577 TAP configuration is the first thing that needs to be done
3578 after interface and reset configuration. Sometimes it's
3579 hard finding out what TAPs exist, or how they are identified.
3580 Vendor documentation is not always easy to find and use.
3582 To help you get past such problems, OpenOCD has a limited
3583 @emph{autoprobing} ability to look at the scan chain, doing
3584 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3585 To use this mechanism, start the OpenOCD server with only data
3586 that configures your JTAG interface, and arranges to come up
3587 with a slow clock (many devices don't support fast JTAG clocks
3588 right when they come out of reset).
3590 For example, your @file{openocd.cfg} file might have:
3592 @example
3593 source [find interface/olimex-arm-usb-tiny-h.cfg]
3594 reset_config trst_and_srst
3595 jtag_rclk 8
3596 @end example
3598 When you start the server without any TAPs configured, it will
3599 attempt to autoconfigure the TAPs. There are two parts to this:
3601 @enumerate
3602 @item @emph{TAP discovery} ...
3603 After a JTAG reset (sometimes a system reset may be needed too),
3604 each TAP's data registers will hold the contents of either the
3605 IDCODE or BYPASS register.
3606 If JTAG communication is working, OpenOCD will see each TAP,
3607 and report what @option{-expected-id} to use with it.
3608 @item @emph{IR Length discovery} ...
3609 Unfortunately JTAG does not provide a reliable way to find out
3610 the value of the @option{-irlen} parameter to use with a TAP
3611 that is discovered.
3612 If OpenOCD can discover the length of a TAP's instruction
3613 register, it will report it.
3614 Otherwise you may need to consult vendor documentation, such
3615 as chip data sheets or BSDL files.
3616 @end enumerate
3618 In many cases your board will have a simple scan chain with just
3619 a single device. Here's what OpenOCD reported with one board
3620 that's a bit more complex:
3622 @example
3623 clock speed 8 kHz
3624 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3625 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3626 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3627 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3628 AUTO auto0.tap - use "... -irlen 4"
3629 AUTO auto1.tap - use "... -irlen 4"
3630 AUTO auto2.tap - use "... -irlen 6"
3631 no gdb ports allocated as no target has been specified
3632 @end example
3634 Given that information, you should be able to either find some existing
3635 config files to use, or create your own. If you create your own, you
3636 would configure from the bottom up: first a @file{target.cfg} file
3637 with these TAPs, any targets associated with them, and any on-chip
3638 resources; then a @file{board.cfg} with off-chip resources, clocking,
3639 and so forth.
3641 @node CPU Configuration
3642 @chapter CPU Configuration
3643 @cindex GDB target
3645 This chapter discusses how to set up GDB debug targets for CPUs.
3646 You can also access these targets without GDB
3647 (@pxref{Architecture and Core Commands},
3648 and @ref{Target State handling}) and
3649 through various kinds of NAND and NOR flash commands.
3650 If you have multiple CPUs you can have multiple such targets.
3652 We'll start by looking at how to examine the targets you have,
3653 then look at how to add one more target and how to configure it.
3655 @section Target List
3656 @cindex target, current
3657 @cindex target, list
3659 All targets that have been set up are part of a list,
3660 where each member has a name.
3661 That name should normally be the same as the TAP name.
3662 You can display the list with the @command{targets}
3663 (plural!) command.
3664 This display often has only one CPU; here's what it might
3665 look like with more than one:
3666 @verbatim
3667 TargetName Type Endian TapName State
3668 -- ------------------ ---------- ------ ------------------ ------------
3669 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
3670 1 MyTarget cortex_m3 little tap-disabled
3671 @end verbatim
3673 One member of that list is the @dfn{current target}, which
3674 is implicitly referenced by many commands.
3675 It's the one marked with a @code{*} near the target name.
3676 In particular, memory addresses often refer to the address
3677 space seen by that current target.
3678 Commands like @command{mdw} (memory display words)
3679 and @command{flash erase_address} (erase NOR flash blocks)
3680 are examples; and there are many more.
3682 Several commands let you examine the list of targets:
3684 @deffn Command {target count}
3685 @emph{Note: target numbers are deprecated; don't use them.
3686 They will be removed shortly after August 2010, including this command.
3687 Iterate target using @command{target names}, not by counting.}
3689 Returns the number of targets, @math{N}.
3690 The highest numbered target is @math{N - 1}.
3691 @example
3692 set c [target count]
3693 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
3694 # Assuming you have created this function
3695 print_target_details $x
3696 @}
3697 @end example
3698 @end deffn
3700 @deffn Command {target current}
3701 Returns the name of the current target.
3702 @end deffn
3704 @deffn Command {target names}
3705 Lists the names of all current targets in the list.
3706 @example
3707 foreach t [target names] @{
3708 puts [format "Target: %s\n" $t]
3709 @}
3710 @end example
3711 @end deffn
3713 @deffn Command {target number} number
3714 @emph{Note: target numbers are deprecated; don't use them.
3715 They will be removed shortly after August 2010, including this command.}
3717 The list of targets is numbered starting at zero.
3718 This command returns the name of the target at index @var{number}.
3719 @example
3720 set thename [target number $x]
3721 puts [format "Target %d is: %s\n" $x $thename]
3722 @end example
3723 @end deffn
3725 @c yep, "target list" would have been better.
3726 @c plus maybe "target setdefault".
3728 @deffn Command targets [name]
3729 @emph{Note: the name of this command is plural. Other target
3730 command names are singular.}
3732 With no parameter, this command displays a table of all known
3733 targets in a user friendly form.
3735 With a parameter, this command sets the current target to
3736 the given target with the given @var{name}; this is
3737 only relevant on boards which have more than one target.
3738 @end deffn
3740 @section Target CPU Types and Variants
3741 @cindex target type
3742 @cindex CPU type
3743 @cindex CPU variant
3745 Each target has a @dfn{CPU type}, as shown in the output of
3746 the @command{targets} command. You need to specify that type
3747 when calling @command{target create}.
3748 The CPU type indicates more than just the instruction set.
3749 It also indicates how that instruction set is implemented,
3750 what kind of debug support it integrates,
3751 whether it has an MMU (and if so, what kind),
3752 what core-specific commands may be available
3753 (@pxref{Architecture and Core Commands}),
3754 and more.
3756 For some CPU types, OpenOCD also defines @dfn{variants} which
3757 indicate differences that affect their handling.
3758 For example, a particular implementation bug might need to be
3759 worked around in some chip versions.
3761 It's easy to see what target types are supported,
3762 since there's a command to list them.
3763 However, there is currently no way to list what target variants
3764 are supported (other than by reading the OpenOCD source code).
3766 @anchor{target types}
3767 @deffn Command {target types}
3768 Lists all supported target types.
3769 At this writing, the supported CPU types and variants are:
3771 @itemize @bullet
3772 @item @code{arm11} -- this is a generation of ARMv6 cores
3773 @item @code{arm720t} -- this is an ARMv4 core with an MMU
3774 @item @code{arm7tdmi} -- this is an ARMv4 core
3775 @item @code{arm920t} -- this is an ARMv4 core with an MMU
3776 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
3777 @item @code{arm966e} -- this is an ARMv5 core
3778 @item @code{arm9tdmi} -- this is an ARMv4 core
3779 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
3780 (Support for this is preliminary and incomplete.)
3781 @item @code{cortex_a8} -- this is an ARMv7 core with an MMU
3782 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
3783 compact Thumb2 instruction set.
3784 @item @code{dragonite} -- resembles arm966e
3785 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
3786 (Support for this is still incomplete.)
3787 @item @code{fa526} -- resembles arm920 (w/o Thumb)
3788 @item @code{feroceon} -- resembles arm926
3789 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
3790 @item @code{xscale} -- this is actually an architecture,
3791 not a CPU type. It is based on the ARMv5 architecture.
3792 There are several variants defined:
3793 @itemize @minus
3794 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
3795 @code{pxa27x} ... instruction register length is 7 bits
3796 @item @code{pxa250}, @code{pxa255},
3797 @code{pxa26x} ... instruction register length is 5 bits
3798 @item @code{pxa3xx} ... instruction register length is 11 bits
3799 @end itemize
3800 @end itemize
3801 @end deffn
3803 To avoid being confused by the variety of ARM based cores, remember
3804 this key point: @emph{ARM is a technology licencing company}.
3805 (See: @url{}.)
3806 The CPU name used by OpenOCD will reflect the CPU design that was
3807 licenced, not a vendor brand which incorporates that design.
3808 Name prefixes like arm7, arm9, arm11, and cortex
3809 reflect design generations;
3810 while names like ARMv4, ARMv5, ARMv6, and ARMv7
3811 reflect an architecture version implemented by a CPU design.
3813 @anchor{Target Configuration}
3814 @section Target Configuration
3816 Before creating a ``target'', you must have added its TAP to the scan chain.
3817 When you've added that TAP, you will have a @code{}
3818 which is used to set up the CPU support.
3819 The chip-specific configuration file will normally configure its CPU(s)
3820 right after it adds all of the chip's TAPs to the scan chain.
3822 Although you can set up a target in one step, it's often clearer if you
3823 use shorter commands and do it in two steps: create it, then configure
3824 optional parts.
3825 All operations on the target after it's created will use a new
3826 command, created as part of target creation.
3828 The two main things to configure after target creation are
3829 a work area, which usually has target-specific defaults even
3830 if the board setup code overrides them later;
3831 and event handlers (@pxref{Target Events}), which tend
3832 to be much more board-specific.
3833 The key steps you use might look something like this
3835 @example
3836 target create MyTarget cortex_m3 -chain-position mychip.cpu
3837 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
3838 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
3839 $MyTarget configure -event reset-init @{ myboard_reinit @}
3840 @end example
3842 You should specify a working area if you can; typically it uses some
3843 on-chip SRAM.
3844 Such a working area can speed up many things, including bulk
3845 writes to target memory;
3846 flash operations like checking to see if memory needs to be erased;
3847 GDB memory checksumming;
3848 and more.
3850 @quotation Warning
3851 On more complex chips, the work area can become
3852 inaccessible when application code
3853 (such as an operating system)
3854 enables or disables the MMU.
3855 For example, the particular MMU context used to acess the virtual
3856 address will probably matter ... and that context might not have
3857 easy access to other addresses needed.
3858 At this writing, OpenOCD doesn't have much MMU intelligence.
3859 @end quotation
3861 It's often very useful to define a @code{reset-init} event handler.
3862 For systems that are normally used with a boot loader,
3863 common tasks include updating clocks and initializing memory
3864 controllers.
3865 That may be needed to let you write the boot loader into flash,
3866 in order to ``de-brick'' your board; or to load programs into
3867 external DDR memory without having run the boot loader.
3869 @deffn Command {target create} target_name type configparams...
3870 This command creates a GDB debug target that refers to a specific JTAG tap.
3871 It enters that target into a list, and creates a new
3872 command (@command{@var{target_name}}) which is used for various
3873 purposes including additional configuration.
3875 @itemize @bullet
3876 @item @var{target_name} ... is the name of the debug target.
3877 By convention this should be the same as the @emph{}
3878 of the TAP associated with this target, which must be specified here
3879 using the @code{-chain-position @var{}} configparam.
3881 This name is also used to create the target object command,
3882 referred to here as @command{$target_name},
3883 and in other places the target needs to be identified.
3884 @item @var{type} ... specifies the target type. @xref{target types}.
3885 @item @var{configparams} ... all parameters accepted by
3886 @command{$target_name configure} are permitted.
3887 If the target is big-endian, set it here with @code{-endian big}.
3888 If the variant matters, set it here with @code{-variant}.
3890 You @emph{must} set the @code{-chain-position @var{}} here.
3891 @end itemize
3892 @end deffn
3894 @deffn Command {$target_name configure} configparams...
3895 The options accepted by this command may also be
3896 specified as parameters to @command{target create}.
3897 Their values can later be queried one at a time by
3898 using the @command{$target_name cget} command.
3900 @emph{Warning:} changing some of these after setup is dangerous.
3901 For example, moving a target from one TAP to another;
3902 and changing its endianness or variant.
3904 @itemize @bullet
3906 @item @code{-chain-position} @var{} -- names the TAP
3907 used to access this target.
3909 @item @code{-endian} (@option{big}|@option{little}) -- specifies
3910 whether the CPU uses big or little endian conventions
3912 @item @code{-event} @var{event_name} @var{event_body} --
3913 @xref{Target Events}.
3914 Note that this updates a list of named event handlers.
3915 Calling this twice with two different event names assigns
3916 two different handlers, but calling it twice with the
3917 same event name assigns only one handler.
3919 @item @code{-variant} @var{name} -- specifies a variant of the target,
3920 which OpenOCD needs to know about.
3922 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
3923 whether the work area gets backed up; by default,
3924 @emph{it is not backed up.}
3925 When possible, use a working_area that doesn't need to be backed up,
3926 since performing a backup slows down operations.
3927 For example, the beginning of an SRAM block is likely to
3928 be used by most build systems, but the end is often unused.
3930 @item @code{-work-area-size} @var{size} -- specify work are size,
3931 in bytes. The same size applies regardless of whether its physical
3932 or virtual address is being used.
3934 @item @code{-work-area-phys} @var{address} -- set the work area
3935 base @var{address} to be used when no MMU is active.
3937 @item @code{-work-area-virt} @var{address} -- set the work area
3938 base @var{address} to be used when an MMU is active.
3939 @emph{Do not specify a value for this except on targets with an MMU.}
3940 The value should normally correspond to a static mapping for the
3941 @code{-work-area-phys} address, set up by the current operating system.
3943 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
3944 @var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{threadx}|
3945 @option{freertos}|@option{linux}.
3947 @end itemize
3948 @end deffn
3950 @section Other $target_name Commands
3951 @cindex object command
3953 The Tcl/Tk language has the concept of object commands,
3954 and OpenOCD adopts that same model for targets.
3956 A good Tk example is a on screen button.
3957 Once a button is created a button
3958 has a name (a path in Tk terms) and that name is useable as a first
3959 class command. For example in Tk, one can create a button and later
3960 configure it like this:
3962 @example
3963 # Create
3964 button .foobar -background red -command @{ foo @}
3965 # Modify
3966 .foobar configure -foreground blue
3967 # Query
3968 set x [.foobar cget -background]
3969 # Report
3970 puts [format "The button is %s" $x]
3971 @end example
3973 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
3974 button, and its object commands are invoked the same way.
3976 @example
3977 str912.cpu mww 0x1234 0x42
3978 omap3530.cpu mww 0x5555 123
3979 @end example
3981 The commands supported by OpenOCD target objects are:
3983 @deffn Command {$target_name arp_examine}
3984 @deffnx Command {$target_name arp_halt}
3985 @deffnx Command {$target_name arp_poll}
3986 @deffnx Command {$target_name arp_reset}
3987 @deffnx Command {$target_name arp_waitstate}
3988 Internal OpenOCD scripts (most notably @file{startup.tcl})
3989 use these to deal with specific reset cases.
3990 They are not otherwise documented here.
3991 @end deffn
3993 @deffn Command {$target_name array2mem} arrayname width address count
3994 @deffnx Command {$target_name mem2array} arrayname width address count
3995 These provide an efficient script-oriented interface to memory.
3996 The @code{array2mem} primitive writes bytes, halfwords, or words;
3997 while @code{mem2array} reads them.
3998 In both cases, the TCL side uses an array, and
3999 the target side uses raw memory.
4001 The efficiency comes from enabling the use of
4002 bulk JTAG data transfer operations.
4003 The script orientation comes from working with data
4004 values that are packaged for use by TCL scripts;
4005 @command{mdw} type primitives only print data they retrieve,
4006 and neither store nor return those values.
4008 @itemize
4009 @item @var{arrayname} ... is the name of an array variable
4010 @item @var{width} ... is 8/16/32 - indicating the memory access size
4011 @item @var{address} ... is the target memory address
4012 @item @var{count} ... is the number of elements to process
4013 @end itemize
4014 @end deffn
4016 @deffn Command {$target_name cget} queryparm
4017 Each configuration parameter accepted by
4018 @command{$target_name configure}
4019 can be individually queried, to return its current value.
4020 The @var{queryparm} is a parameter name
4021 accepted by that command, such as @code{-work-area-phys}.
4022 There are a few special cases:
4024 @itemize @bullet
4025 @item @code{-event} @var{event_name} -- returns the handler for the
4026 event named @var{event_name}.
4027 This is a special case because setting a handler requires
4028 two parameters.
4029 @item @code{-type} -- returns the target type.
4030 This is a special case because this is set using
4031 @command{target create} and can't be changed
4032 using @command{$target_name configure}.
4033 @end itemize
4035 For example, if you wanted to summarize information about
4036 all the targets you might use something like this:
4038 @example
4039 foreach name [target names] @{
4040 set y [$name cget -endian]
4041 set z [$name cget -type]
4042 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4043 $x $name $y $z]
4044 @}
4045 @end example
4046 @end deffn
4048 @anchor{target curstate}
4049 @deffn Command {$target_name curstate}
4050 Displays the current target state:
4051 @code{debug-running},
4052 @code{halted},
4053 @code{reset},
4054 @code{running}, or @code{unknown}.
4055 (Also, @pxref{Event Polling}.)
4056 @end deffn
4058 @deffn Command {$target_name eventlist}
4059 Displays a table listing all event handlers
4060 currently associated with this target.
4061 @xref{Target Events}.
4062 @end deffn
4064 @deffn Command {$target_name invoke-event} event_name
4065 Invokes the handler for the event named @var{event_name}.
4066 (This is primarily intended for use by OpenOCD framework
4067 code, for example by the reset code in @file{startup.tcl}.)
4068 @end deffn
4070 @deffn Command {$target_name mdw} addr [count]
4071 @deffnx Command {$target_name mdh} addr [count]
4072 @deffnx Command {$target_name mdb} addr [count]
4073 Display contents of address @var{addr}, as
4074 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4075 or 8-bit bytes (@command{mdb}).
4076 If @var{count} is specified, displays that many units.
4077 (If you want to manipulate the data instead of displaying it,
4078 see the @code{mem2array} primitives.)
4079 @end deffn
4081 @deffn Command {$target_name mww} addr word
4082 @deffnx Command {$target_name mwh} addr halfword
4083 @deffnx Command {$target_name mwb} addr byte
4084 Writes the specified @var{word} (32 bits),
4085 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4086 at the specified address @var{addr}.
4087 @end deffn
4089 @anchor{Target Events}
4090 @section Target Events
4091 @cindex target events
4092 @cindex events
4093 At various times, certain things can happen, or you want them to happen.
4094 For example:
4095 @itemize @bullet
4096 @item What should happen when GDB connects? Should your target reset?
4097 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4098 @item Is using SRST appropriate (and possible) on your system?
4099 Or instead of that, do you need to issue JTAG commands to trigger reset?
4100 SRST usually resets everything on the scan chain, which can be inappropriate.
4101 @item During reset, do you need to write to certain memory locations
4102 to set up system clocks or
4103 to reconfigure the SDRAM?
4104 How about configuring the watchdog timer, or other peripherals,
4105 to stop running while you hold the core stopped for debugging?
4106 @end itemize
4108 All of the above items can be addressed by target event handlers.
4109 These are set up by @command{$target_name configure -event} or
4110 @command{target create ... -event}.
4112 The programmer's model matches the @code{-command} option used in Tcl/Tk
4113 buttons and events. The two examples below act the same, but one creates
4114 and invokes a small procedure while the other inlines it.
4116 @example
4117 proc my_attach_proc @{ @} @{
4118 echo "Reset..."
4119 reset halt
4120 @}
4121 mychip.cpu configure -event gdb-attach my_attach_proc
4122 mychip.cpu configure -event gdb-attach @{
4123 echo "Reset..."
4124 # To make flash probe and gdb load to flash work we need a reset init.
4125 reset init
4126 @}
4127 @end example
4129 The following target events are defined:
4131 @itemize @bullet
4132 @item @b{debug-halted}
4133 @* The target has halted for debug reasons (i.e.: breakpoint)
4134 @item @b{debug-resumed}
4135 @* The target has resumed (i.e.: gdb said run)
4136 @item @b{early-halted}
4137 @* Occurs early in the halt process
4138 @ignore
4139 @item @b{examine-end}
4140 @* Currently not used (goal: when JTAG examine completes)
4141 @item @b{examine-start}
4142 @* Currently not used (goal: when JTAG examine starts)
4143 @end ignore
4144 @item @b{gdb-attach}
4145 @* When GDB connects. This is before any communication with the target, so this
4146 can be used to set up the target so it is possible to probe flash. Probing flash
4147 is necessary during gdb connect if gdb load is to write the image to flash. Another
4148 use of the flash memory map is for GDB to automatically hardware/software breakpoints
4149 depending on whether the breakpoint is in RAM or read only memory.
4150 @item @b{gdb-detach}
4151 @* When GDB disconnects
4152 @item @b{gdb-end}
4153 @* When the target has halted and GDB is not doing anything (see early halt)
4154 @item @b{gdb-flash-erase-start}
4155 @* Before the GDB flash process tries to erase the flash
4156 @item @b{gdb-flash-erase-end}
4157 @* After the GDB flash process has finished erasing the flash
4158 @item @b{gdb-flash-write-start}
4159 @* Before GDB writes to the flash
4160 @item @b{gdb-flash-write-end}
4161 @* After GDB writes to the flash
4162 @item @b{gdb-start}
4163 @* Before the target steps, gdb is trying to start/resume the target
4164 @item @b{halted}
4165 @* The target has halted
4166 @ignore
4167 @item @b{old-gdb_program_config}
4168 @* DO NOT USE THIS: Used internally
4169 @item @b{old-pre_resume}
4170 @* DO NOT USE THIS: Used internally
4171 @end ignore
4172 @item @b{reset-assert-pre}
4173 @* Issued as part of @command{reset} processing
4174 after @command{reset_init} was triggered
4175 but before either SRST alone is re-asserted on the scan chain,
4176 or @code{reset-assert} is triggered.
4177 @item @b{reset-assert}
4178 @* Issued as part of @command{reset} processing
4179 after @command{reset-assert-pre} was triggered.
4180 When such a handler is present, cores which support this event will use
4181 it instead of asserting SRST.
4182 This support is essential for debugging with JTAG interfaces which
4183 don't include an SRST line (JTAG doesn't require SRST), and for
4184 selective reset on scan chains that have multiple targets.
4185 @item @b{reset-assert-post}
4186 @* Issued as part of @command{reset} processing
4187 after @code{reset-assert} has been triggered.
4188 or the target asserted SRST on the entire scan chain.