cfg: add revb ek-lm3s811 board config
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * TFTP:: TFTP
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on:
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
94 @end menu
96 @node About
97 @unnumbered About
98 @cindex about
100 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
101 University of Applied Sciences Augsburg (@uref{}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
104 around the world.
106 @section What is OpenOCD?
107 @cindex TAP
108 @cindex JTAG
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
112 devices.
114 It does so with the assistance of a @dfn{debug adapter}, which is
115 a small hardware module which helps provide the right kind of
116 electrical signaling to the target being debugged. These are
117 required since the debug host (on which OpenOCD runs) won't
118 usually have native support for such signaling, or the connector
119 needed to hook up to the target.
121 Such debug adapters support one or more @dfn{transport} protocols,
122 each of which involves different electrical signaling (and uses
123 different messaging protocols on top of that signaling). There
124 are many types of debug adapter, and little uniformity in what
125 they are called. (There are also product naming differences.)
127 These adapters are sometimes packaged as discrete dongles, which
128 may generically be called @dfn{hardware interface dongles}.
129 Some development boards also integrate them directly, which may
130 let the development board can be directly connected to the debug
131 host over USB (and sometimes also to power it over USB).
133 For example, a @dfn{JTAG Adapter} supports JTAG
134 signaling, and is used to communicate
135 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
136 A @dfn{TAP} is a ``Test Access Port'', a module which processes
137 special instructions and data. TAPs are daisy-chained within and
138 between chips and boards. JTAG supports debugging and boundary
139 scan operations.
141 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
142 signaling to communicate with some newer ARM cores, as well as debug
143 adapters which support both JTAG and SWD transports. SWD only supports
144 debugging, whereas JTAG also supports boundary scan operations.
146 For some chips, there are also @dfn{Programming Adapters} supporting
147 special transports used only to write code to flash memory, without
148 support for on-chip debugging or boundary scan.
149 (At this writing, OpenOCD does not support such non-debug adapters.)
152 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
153 based, parallel port based, and other standalone boxes that run
154 OpenOCD internally. @xref{Debug Adapter Hardware}.
156 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
157 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
158 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
159 debugged via the GDB protocol.
161 @b{Flash Programing:} Flash writing is supported for external CFI
162 compatible NOR flashes (Intel and AMD/Spansion command set) and several
163 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
164 STM32x). Preliminary support for various NAND flash controllers
165 (LPC3180, Orion, S3C24xx, more) controller is included.
167 @section OpenOCD Web Site
169 The OpenOCD web site provides the latest public news from the community:
171 @uref{}
173 @section Latest User's Guide:
175 The user's guide you are now reading may not be the latest one
176 available. A version for more recent code may be available.
177 Its HTML form is published irregularly at:
179 @uref{}
181 PDF form is likewise published at:
183 @uref{}
185 @section OpenOCD User's Forum
187 There is an OpenOCD forum (phpBB) hosted by SparkFun,
188 which might be helpful to you. Note that if you want
189 anything to come to the attention of developers, you
190 should post it to the OpenOCD Developer Mailing List
191 instead of this forum.
193 @uref{}
196 @node Developers
197 @chapter OpenOCD Developer Resources
198 @cindex developers
200 If you are interested in improving the state of OpenOCD's debugging and
201 testing support, new contributions will be welcome. Motivated developers
202 can produce new target, flash or interface drivers, improve the
203 documentation, as well as more conventional bug fixes and enhancements.
205 The resources in this chapter are available for developers wishing to explore
206 or expand the OpenOCD source code.
208 @section OpenOCD GIT Repository
210 During the 0.3.x release cycle, OpenOCD switched from Subversion to
211 a GIT repository hosted at SourceForge. The repository URL is:
213 @uref{git://}
215 You may prefer to use a mirror and the HTTP protocol:
217 @uref{}
219 With standard GIT tools, use @command{git clone} to initialize
220 a local repository, and @command{git pull} to update it.
221 There are also gitweb pages letting you browse the repository
222 with a web browser, or download arbitrary snapshots without
223 needing a GIT client:
225 @uref{}
227 @uref{}
229 The @file{README} file contains the instructions for building the project
230 from the repository or a snapshot.
232 Developers that want to contribute patches to the OpenOCD system are
233 @b{strongly} encouraged to work against mainline.
234 Patches created against older versions may require additional
235 work from their submitter in order to be updated for newer releases.
237 @section Doxygen Developer Manual
239 During the 0.2.x release cycle, the OpenOCD project began
240 providing a Doxygen reference manual. This document contains more
241 technical information about the software internals, development
242 processes, and similar documentation:
244 @uref{}
246 This document is a work-in-progress, but contributions would be welcome
247 to fill in the gaps. All of the source files are provided in-tree,
248 listed in the Doxyfile configuration in the top of the source tree.
250 @section OpenOCD Developer Mailing List
252 The OpenOCD Developer Mailing List provides the primary means of
253 communication between developers:
255 @uref{}
257 Discuss and submit patches to this list.
258 The @file{HACKING} file contains basic information about how
259 to prepare patches.
261 @section OpenOCD Bug Database
263 During the 0.4.x release cycle the OpenOCD project team began
264 using Trac for its bug database:
266 @uref{}
269 @node Debug Adapter Hardware
270 @chapter Debug Adapter Hardware
271 @cindex dongles
272 @cindex FTDI
273 @cindex wiggler
274 @cindex zy1000
275 @cindex printer port
276 @cindex USB Adapter
277 @cindex RTCK
279 Defined: @b{dongle}: A small device that plugins into a computer and serves as
280 an adapter .... [snip]
282 In the OpenOCD case, this generally refers to @b{a small adapter} that
283 attaches to your computer via USB or the Parallel Printer Port. One
284 exception is the Zylin ZY1000, packaged as a small box you attach via
285 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
286 require any drivers to be installed on the developer PC. It also has
287 a built in web interface. It supports RTCK/RCLK or adaptive clocking
288 and has a built in relay to power cycle targets remotely.
291 @section Choosing a Dongle
293 There are several things you should keep in mind when choosing a dongle.
295 @enumerate
296 @item @b{Transport} Does it support the kind of communication that you need?
297 OpenOCD focusses mostly on JTAG. Your version may also support
298 other ways to communicate with target devices.
299 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
300 Does your dongle support it? You might need a level converter.
301 @item @b{Pinout} What pinout does your target board use?
302 Does your dongle support it? You may be able to use jumper
303 wires, or an "octopus" connector, to convert pinouts.
304 @item @b{Connection} Does your computer have the USB, printer, or
305 Ethernet port needed?
306 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
307 RTCK support? Also known as ``adaptive clocking''
308 @end enumerate
310 @section Stand alone Systems
312 @b{ZY1000} See: @url{} Technically, not a
313 dongle, but a standalone box. The ZY1000 has the advantage that it does
314 not require any drivers installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built in relay to power cycle targets remotely.
318 @section USB FT2232 Based
320 There are many USB JTAG dongles on the market, many of them are based
321 on a chip from ``Future Technology Devices International'' (FTDI)
322 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
323 See: @url{} for more information.
324 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
325 chips are starting to become available in JTAG adapters. (Adapters
326 using those high speed FT2232H chips may support adaptive clocking.)
328 The FT2232 chips are flexible enough to support some other
329 transport options, such as SWD or the SPI variants used to
330 program some chips. They have two communications channels,
331 and one can be used for a UART adapter at the same time the
332 other one is used to provide a debug adapter.
334 Also, some development boards integrate an FT2232 chip to serve as
335 a built-in low cost debug adapter and usb-to-serial solution.
337 @itemize @bullet
338 @item @b{usbjtag}
339 @* Link @url{}
340 @item @b{jtagkey}
341 @* See: @url{}
342 @item @b{jtagkey2}
343 @* See: @url{}
344 @item @b{oocdlink}
345 @* See: @url{} By Joern Kaipf
346 @item @b{signalyzer}
347 @* See: @url{}
348 @item @b{Stellaris Eval Boards}
349 @* See: @url{} - The Stellaris eval boards
350 bundle FT2232-based JTAG and SWD support, which can be used to debug
351 the Stellaris chips. Using separate JTAG adapters is optional.
352 These boards can also be used in a "pass through" mode as JTAG adapters
353 to other target boards, disabling the Stellaris chip.
354 @item @b{Luminary ICDI}
355 @* See: @url{} - Luminary In-Circuit Debug
356 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
357 Evaluation Kits. Like the non-detachable FT2232 support on the other
358 Stellaris eval boards, they can be used to debug other target boards.
359 @item @b{olimex-jtag}
360 @* See: @url{}
361 @item @b{flyswatter}
362 @* See: @url{}
363 @item @b{turtelizer2}
364 @* See:
365 @uref{, Turtelizer 2}, or
366 @url{}
367 @item @b{comstick}
368 @* Link: @url{}
369 @item @b{stm32stick}
370 @* Link @url{}
371 @item @b{axm0432_jtag}
372 @* Axiom AXM-0432 Link @url{}
373 @item @b{cortino}
374 @* Link @url{}
375 @item @b{dlp-usb1232h}
376 @* Link @url{}
377 @end itemize
379 @section USB-JTAG / Altera USB-Blaster compatibles
381 These devices also show up as FTDI devices, but are not
382 protocol-compatible with the FT2232 devices. They are, however,
383 protocol-compatible among themselves. USB-JTAG devices typically consist
384 of a FT245 followed by a CPLD that understands a particular protocol,
385 or emulate this protocol using some other hardware.
387 They may appear under different USB VID/PID depending on the particular
388 product. The driver can be configured to search for any VID/PID pair
389 (see the section on driver commands).
391 @itemize
392 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
393 @* Link: @url{}
394 @item @b{Altera USB-Blaster}
395 @* Link: @url{}
396 @end itemize
398 @section USB JLINK based
399 There are several OEM versions of the Segger @b{JLINK} adapter. It is
400 an example of a micro controller based JTAG adapter, it uses an
401 AT91SAM764 internally.
403 @itemize @bullet
404 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
405 @* Link: @url{}
406 @item @b{SEGGER JLINK}
407 @* Link: @url{}
408 @item @b{IAR J-Link}
409 @* Link: @url{}
410 @end itemize
412 @section USB RLINK based
413 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
415 @itemize @bullet
416 @item @b{Raisonance RLink}
417 @* Link: @url{}
418 @item @b{STM32 Primer}
419 @* Link: @url{}
420 @item @b{STM32 Primer2}
421 @* Link: @url{}
422 @end itemize
424 @section USB ST-LINK based
425 ST Micro has an adapter called @b{ST-LINK}.
426 They only works with ST Micro chips, notably STM32 and STM8.
428 @itemize @bullet
429 @item @b{ST-LINK}
430 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
431 @* Link: @url{}
432 @item @b{ST-LINK/V2}
433 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
434 @* Link: @url{}
435 @end itemize
437 For info the original ST-LINK enumerates using the mass storage usb class, however
438 it's implementation is completely broken. The result is this causes issues under linux.
439 The simplest solution is to get linux to ignore the ST-LINK using one of the following method's:
440 @itemize @bullet
441 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
442 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
443 @end itemize
445 @section USB Other
446 @itemize @bullet
447 @item @b{USBprog}
448 @* Link: @url{} - which uses an Atmel MEGA32 and a UBN9604
450 @item @b{USB - Presto}
451 @* Link: @url{}
453 @item @b{Versaloon-Link}
454 @* Link: @url{}
456 @item @b{ARM-JTAG-EW}
457 @* Link: @url{}
459 @item @b{Buspirate}
460 @* Link: @url{}
461 @end itemize
463 @section IBM PC Parallel Printer Port Based
465 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
466 and the MacGraigor Wiggler. There are many clones and variations of
467 these on the market.
469 Note that parallel ports are becoming much less common, so if you
470 have the choice you should probably avoid these adapters in favor
471 of USB-based ones.
473 @itemize @bullet
475 @item @b{Wiggler} - There are many clones of this.
476 @* Link: @url{}
478 @item @b{DLC5} - From XILINX - There are many clones of this
479 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
480 produced, PDF schematics are easily found and it is easy to make.
482 @item @b{Amontec - JTAG Accelerator}
483 @* Link: @url{}
485 @item @b{GW16402}
486 @* Link: @url{}
488 @item @b{Wiggler2}
489 @*@uref{,
490 Improved parallel-port wiggler-style JTAG adapter}
492 @item @b{Wiggler_ntrst_inverted}
493 @* Yet another variation - See the source code, src/jtag/parport.c
495 @item @b{old_amt_wiggler}
496 @* Unknown - probably not on the market today
498 @item @b{arm-jtag}
499 @* Link: Most likely @url{} [another wiggler clone]
501 @item @b{chameleon}
502 @* Link: @url{}
504 @item @b{Triton}
505 @* Unknown.
507 @item @b{Lattice}
508 @* ispDownload from Lattice Semiconductor
509 @url{}
511 @item @b{flashlink}
512 @* From ST Microsystems;
513 @uref{,
514 FlashLINK JTAG programing cable for PSD and uPSD}
516 @end itemize
518 @section Other...
519 @itemize @bullet
521 @item @b{ep93xx}
522 @* An EP93xx based Linux machine using the GPIO pins directly.
524 @item @b{at91rm9200}
525 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
527 @end itemize
529 @node About Jim-Tcl
530 @chapter About Jim-Tcl
531 @cindex Jim-Tcl
532 @cindex tcl
534 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
535 This programming language provides a simple and extensible
536 command interpreter.
538 All commands presented in this Guide are extensions to Jim-Tcl.
539 You can use them as simple commands, without needing to learn
540 much of anything about Tcl.
541 Alternatively, can write Tcl programs with them.
543 You can learn more about Jim at its website, @url{}.
544 There is an active and responsive community, get on the mailing list
545 if you have any questions. Jim-Tcl maintainers also lurk on the
546 OpenOCD mailing list.
548 @itemize @bullet
549 @item @b{Jim vs. Tcl}
550 @* Jim-Tcl is a stripped down version of the well known Tcl language,
551 which can be found here: @url{}. Jim-Tcl has far
552 fewer features. Jim-Tcl is several dozens of .C files and .H files and
553 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
554 4.2 MB .zip file containing 1540 files.
556 @item @b{Missing Features}
557 @* Our practice has been: Add/clone the real Tcl feature if/when
558 needed. We welcome Jim-Tcl improvements, not bloat. Also there
559 are a large number of optional Jim-Tcl features that are not
560 enabled in OpenOCD.
562 @item @b{Scripts}
563 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
564 command interpreter today is a mixture of (newer)
565 Jim-Tcl commands, and (older) the orginal command interpreter.
567 @item @b{Commands}
568 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
569 can type a Tcl for() loop, set variables, etc.
570 Some of the commands documented in this guide are implemented
571 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
573 @item @b{Historical Note}
574 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
575 before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
576 as a git submodule, which greatly simplified upgrading Jim Tcl
577 to benefit from new features and bugfixes in Jim Tcl.
579 @item @b{Need a crash course in Tcl?}
580 @*@xref{Tcl Crash Course}.
581 @end itemize
583 @node Running
584 @chapter Running
585 @cindex command line options
586 @cindex logfile
587 @cindex directory search
589 Properly installing OpenOCD sets up your operating system to grant it access
590 to the debug adapters. On Linux, this usually involves installing a file
591 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
592 complex and confusing driver configuration for every peripheral. Such issues
593 are unique to each operating system, and are not detailed in this User's Guide.
595 Then later you will invoke the OpenOCD server, with various options to
596 tell it how each debug session should work.
597 The @option{--help} option shows:
598 @verbatim
599 bash$ openocd --help
601 --help | -h display this help
602 --version | -v display OpenOCD version
603 --file | -f use configuration file <name>
604 --search | -s dir to search for config files and scripts
605 --debug | -d set debug level <0-3>
606 --log_output | -l redirect log output to file <name>
607 --command | -c run <command>
608 @end verbatim
610 If you don't give any @option{-f} or @option{-c} options,
611 OpenOCD tries to read the configuration file @file{openocd.cfg}.
612 To specify one or more different
613 configuration files, use @option{-f} options. For example:
615 @example
616 openocd -f config1.cfg -f config2.cfg -f config3.cfg
617 @end example
619 Configuration files and scripts are searched for in
620 @enumerate
621 @item the current directory,
622 @item any search dir specified on the command line using the @option{-s} option,
623 @item any search dir specified using the @command{add_script_search_dir} command,
624 @item @file{$HOME/.openocd} (not on Windows),
625 @item the site wide script library @file{$pkgdatadir/site} and
626 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
627 @end enumerate
628 The first found file with a matching file name will be used.
630 @quotation Note
631 Don't try to use configuration script names or paths which
632 include the "#" character. That character begins Tcl comments.
633 @end quotation
635 @section Simple setup, no customization
637 In the best case, you can use two scripts from one of the script
638 libraries, hook up your JTAG adapter, and start the server ... and
639 your JTAG setup will just work "out of the box". Always try to
640 start by reusing those scripts, but assume you'll need more
641 customization even if this works. @xref{OpenOCD Project Setup}.
643 If you find a script for your JTAG adapter, and for your board or
644 target, you may be able to hook up your JTAG adapter then start
645 the server like:
647 @example
648 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
649 @end example
651 You might also need to configure which reset signals are present,
652 using @option{-c 'reset_config trst_and_srst'} or something similar.
653 If all goes well you'll see output something like
655 @example
656 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
657 For bug reports, read
659 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
660 (mfg: 0x23b, part: 0xba00, ver: 0x3)
661 @end example
663 Seeing that "tap/device found" message, and no warnings, means
664 the JTAG communication is working. That's a key milestone, but
665 you'll probably need more project-specific setup.
667 @section What OpenOCD does as it starts
669 OpenOCD starts by processing the configuration commands provided
670 on the command line or, if there were no @option{-c command} or
671 @option{-f file.cfg} options given, in @file{openocd.cfg}.
672 @xref{Configuration Stage}.
673 At the end of the configuration stage it verifies the JTAG scan
674 chain defined using those commands; your configuration should
675 ensure that this always succeeds.
676 Normally, OpenOCD then starts running as a daemon.
677 Alternatively, commands may be used to terminate the configuration
678 stage early, perform work (such as updating some flash memory),
679 and then shut down without acting as a daemon.
681 Once OpenOCD starts running as a daemon, it waits for connections from
682 clients (Telnet, GDB, Other) and processes the commands issued through
683 those channels.
685 If you are having problems, you can enable internal debug messages via
686 the @option{-d} option.
688 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
689 @option{-c} command line switch.
691 To enable debug output (when reporting problems or working on OpenOCD
692 itself), use the @option{-d} command line switch. This sets the
693 @option{debug_level} to "3", outputting the most information,
694 including debug messages. The default setting is "2", outputting only
695 informational messages, warnings and errors. You can also change this
696 setting from within a telnet or gdb session using @command{debug_level
697 <n>} (@pxref{debug_level}).
699 You can redirect all output from the daemon to a file using the
700 @option{-l <logfile>} switch.
702 Note! OpenOCD will launch the GDB & telnet server even if it can not
703 establish a connection with the target. In general, it is possible for
704 the JTAG controller to be unresponsive until the target is set up
705 correctly via e.g. GDB monitor commands in a GDB init script.
707 @node OpenOCD Project Setup
708 @chapter OpenOCD Project Setup
710 To use OpenOCD with your development projects, you need to do more than
711 just connecting the JTAG adapter hardware (dongle) to your development board
712 and then starting the OpenOCD server.
713 You also need to configure that server so that it knows
714 about that adapter and board, and helps your work.
715 You may also want to connect OpenOCD to GDB, possibly
716 using Eclipse or some other GUI.
718 @section Hooking up the JTAG Adapter
720 Today's most common case is a dongle with a JTAG cable on one side
721 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
722 and a USB cable on the other.
723 Instead of USB, some cables use Ethernet;
724 older ones may use a PC parallel port, or even a serial port.
726 @enumerate
727 @item @emph{Start with power to your target board turned off},
728 and nothing connected to your JTAG adapter.
729 If you're particularly paranoid, unplug power to the board.
730 It's important to have the ground signal properly set up,
731 unless you are using a JTAG adapter which provides
732 galvanic isolation between the target board and the
733 debugging host.
735 @item @emph{Be sure it's the right kind of JTAG connector.}
736 If your dongle has a 20-pin ARM connector, you need some kind
737 of adapter (or octopus, see below) to hook it up to
738 boards using 14-pin or 10-pin connectors ... or to 20-pin
739 connectors which don't use ARM's pinout.
741 In the same vein, make sure the voltage levels are compatible.
742 Not all JTAG adapters have the level shifters needed to work
743 with 1.2 Volt boards.
745 @item @emph{Be certain the cable is properly oriented} or you might
746 damage your board. In most cases there are only two possible
747 ways to connect the cable.
748 Connect the JTAG cable from your adapter to the board.
749 Be sure it's firmly connected.
751 In the best case, the connector is keyed to physically
752 prevent you from inserting it wrong.
753 This is most often done using a slot on the board's male connector
754 housing, which must match a key on the JTAG cable's female connector.
755 If there's no housing, then you must look carefully and
756 make sure pin 1 on the cable hooks up to pin 1 on the board.
757 Ribbon cables are frequently all grey except for a wire on one
758 edge, which is red. The red wire is pin 1.
760 Sometimes dongles provide cables where one end is an ``octopus'' of
761 color coded single-wire connectors, instead of a connector block.
762 These are great when converting from one JTAG pinout to another,
763 but are tedious to set up.
764 Use these with connector pinout diagrams to help you match up the
765 adapter signals to the right board pins.
767 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
768 A USB, parallel, or serial port connector will go to the host which
769 you are using to run OpenOCD.
770 For Ethernet, consult the documentation and your network administrator.
772 For USB based JTAG adapters you have an easy sanity check at this point:
773 does the host operating system see the JTAG adapter? If that host is an
774 MS-Windows host, you'll need to install a driver before OpenOCD works.
776 @item @emph{Connect the adapter's power supply, if needed.}
777 This step is primarily for non-USB adapters,
778 but sometimes USB adapters need extra power.
780 @item @emph{Power up the target board.}
781 Unless you just let the magic smoke escape,
782 you're now ready to set up the OpenOCD server
783 so you can use JTAG to work with that board.
785 @end enumerate
787 Talk with the OpenOCD server using
788 telnet (@code{telnet localhost 4444} on many systems) or GDB.
789 @xref{GDB and OpenOCD}.
791 @section Project Directory
793 There are many ways you can configure OpenOCD and start it up.
795 A simple way to organize them all involves keeping a
796 single directory for your work with a given board.
797 When you start OpenOCD from that directory,
798 it searches there first for configuration files, scripts,
799 files accessed through semihosting,
800 and for code you upload to the target board.
801 It is also the natural place to write files,
802 such as log files and data you download from the board.
804 @section Configuration Basics
806 There are two basic ways of configuring OpenOCD, and
807 a variety of ways you can mix them.
808 Think of the difference as just being how you start the server:
810 @itemize
811 @item Many @option{-f file} or @option{-c command} options on the command line
812 @item No options, but a @dfn{user config file}
813 in the current directory named @file{openocd.cfg}
814 @end itemize
816 Here is an example @file{openocd.cfg} file for a setup
817 using a Signalyzer FT2232-based JTAG adapter to talk to
818 a board with an Atmel AT91SAM7X256 microcontroller:
820 @example
821 source [find interface/signalyzer.cfg]
823 # GDB can also flash my flash!
824 gdb_memory_map enable
825 gdb_flash_program enable
827 source [find target/sam7x256.cfg]
828 @end example
830 Here is the command line equivalent of that configuration:
832 @example
833 openocd -f interface/signalyzer.cfg \
834 -c "gdb_memory_map enable" \
835 -c "gdb_flash_program enable" \
836 -f target/sam7x256.cfg
837 @end example
839 You could wrap such long command lines in shell scripts,
840 each supporting a different development task.
841 One might re-flash the board with a specific firmware version.
842 Another might set up a particular debugging or run-time environment.
844 @quotation Important
845 At this writing (October 2009) the command line method has
846 problems with how it treats variables.
847 For example, after @option{-c "set VAR value"}, or doing the
848 same in a script, the variable @var{VAR} will have no value
849 that can be tested in a later script.
850 @end quotation
852 Here we will focus on the simpler solution: one user config
853 file, including basic configuration plus any TCL procedures
854 to simplify your work.
856 @section User Config Files
857 @cindex config file, user
858 @cindex user config file
859 @cindex config file, overview
861 A user configuration file ties together all the parts of a project
862 in one place.
863 One of the following will match your situation best:
865 @itemize
866 @item Ideally almost everything comes from configuration files
867 provided by someone else.
868 For example, OpenOCD distributes a @file{scripts} directory
869 (probably in @file{/usr/share/openocd/scripts} on Linux).
870 Board and tool vendors can provide these too, as can individual
871 user sites; the @option{-s} command line option lets you say
872 where to find these files. (@xref{Running}.)
873 The AT91SAM7X256 example above works this way.
875 Three main types of non-user configuration file each have their
876 own subdirectory in the @file{scripts} directory:
878 @enumerate
879 @item @b{interface} -- one for each different debug adapter;
880 @item @b{board} -- one for each different board
881 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
882 @end enumerate
884 Best case: include just two files, and they handle everything else.
885 The first is an interface config file.
886 The second is board-specific, and it sets up the JTAG TAPs and
887 their GDB targets (by deferring to some @file{target.cfg} file),
888 declares all flash memory, and leaves you nothing to do except
889 meet your deadline:
891 @example
892 source [find interface/olimex-jtag-tiny.cfg]
893 source [find board/csb337.cfg]
894 @end example
896 Boards with a single microcontroller often won't need more
897 than the target config file, as in the AT91SAM7X256 example.
898 That's because there is no external memory (flash, DDR RAM), and
899 the board differences are encapsulated by application code.
901 @item Maybe you don't know yet what your board looks like to JTAG.
902 Once you know the @file{interface.cfg} file to use, you may
903 need help from OpenOCD to discover what's on the board.
904 Once you find the JTAG TAPs, you can just search for appropriate
905 target and board
906 configuration files ... or write your own, from the bottom up.
907 @xref{Autoprobing}.
909 @item You can often reuse some standard config files but
910 need to write a few new ones, probably a @file{board.cfg} file.
911 You will be using commands described later in this User's Guide,
912 and working with the guidelines in the next chapter.
914 For example, there may be configuration files for your JTAG adapter
915 and target chip, but you need a new board-specific config file
916 giving access to your particular flash chips.
917 Or you might need to write another target chip configuration file
918 for a new chip built around the Cortex M3 core.
920 @quotation Note
921 When you write new configuration files, please submit
922 them for inclusion in the next OpenOCD release.
923 For example, a @file{board/newboard.cfg} file will help the
924 next users of that board, and a @file{target/newcpu.cfg}
925 will help support users of any board using that chip.
926 @end quotation
928 @item
929 You may may need to write some C code.
930 It may be as simple as a supporting a new ft2232 or parport
931 based adapter; a bit more involved, like a NAND or NOR flash
932 controller driver; or a big piece of work like supporting
933 a new chip architecture.
934 @end itemize
936 Reuse the existing config files when you can.
937 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
938 You may find a board configuration that's a good example to follow.
940 When you write config files, separate the reusable parts
941 (things every user of that interface, chip, or board needs)
942 from ones specific to your environment and debugging approach.
943 @itemize
945 @item
946 For example, a @code{gdb-attach} event handler that invokes
947 the @command{reset init} command will interfere with debugging
948 early boot code, which performs some of the same actions
949 that the @code{reset-init} event handler does.
951 @item
952 Likewise, the @command{arm9 vector_catch} command (or
953 @cindex vector_catch
954 its siblings @command{xscale vector_catch}
955 and @command{cortex_m3 vector_catch}) can be a timesaver
956 during some debug sessions, but don't make everyone use that either.
957 Keep those kinds of debugging aids in your user config file,
958 along with messaging and tracing setup.
959 (@xref{Software Debug Messages and Tracing}.)
961 @item
962 You might need to override some defaults.
963 For example, you might need to move, shrink, or back up the target's
964 work area if your application needs much SRAM.
966 @item
967 TCP/IP port configuration is another example of something which
968 is environment-specific, and should only appear in
969 a user config file. @xref{TCP/IP Ports}.
970 @end itemize
972 @section Project-Specific Utilities
974 A few project-specific utility
975 routines may well speed up your work.
976 Write them, and keep them in your project's user config file.
978 For example, if you are making a boot loader work on a
979 board, it's nice to be able to debug the ``after it's
980 loaded to RAM'' parts separately from the finicky early
981 code which sets up the DDR RAM controller and clocks.
982 A script like this one, or a more GDB-aware sibling,
983 may help:
985 @example
986 proc ramboot @{ @} @{
987 # Reset, running the target's "reset-init" scripts
988 # to initialize clocks and the DDR RAM controller.
989 # Leave the CPU halted.
990 reset init
992 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
993 load_image u-boot.bin 0x20000000
995 # Start running.
996 resume 0x20000000
997 @}
998 @end example
1000 Then once that code is working you will need to make it
1001 boot from NOR flash; a different utility would help.
1002 Alternatively, some developers write to flash using GDB.
1003 (You might use a similar script if you're working with a flash
1004 based microcontroller application instead of a boot loader.)
1006 @example
1007 proc newboot @{ @} @{
1008 # Reset, leaving the CPU halted. The "reset-init" event
1009 # proc gives faster access to the CPU and to NOR flash;
1010 # "reset halt" would be slower.
1011 reset init
1013 # Write standard version of U-Boot into the first two
1014 # sectors of NOR flash ... the standard version should
1015 # do the same lowlevel init as "reset-init".
1016 flash protect 0 0 1 off
1017 flash erase_sector 0 0 1
1018 flash write_bank 0 u-boot.bin 0x0
1019 flash protect 0 0 1 on
1021 # Reboot from scratch using that new boot loader.
1022 reset run
1023 @}
1024 @end example
1026 You may need more complicated utility procedures when booting
1027 from NAND.
1028 That often involves an extra bootloader stage,
1029 running from on-chip SRAM to perform DDR RAM setup so it can load
1030 the main bootloader code (which won't fit into that SRAM).
1032 Other helper scripts might be used to write production system images,
1033 involving considerably more than just a three stage bootloader.
1035 @section Target Software Changes
1037 Sometimes you may want to make some small changes to the software
1038 you're developing, to help make JTAG debugging work better.
1039 For example, in C or assembly language code you might
1040 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1041 handling issues like:
1043 @itemize @bullet
1045 @item @b{Watchdog Timers}...
1046 Watchog timers are typically used to automatically reset systems if
1047 some application task doesn't periodically reset the timer. (The
1048 assumption is that the system has locked up if the task can't run.)
1049 When a JTAG debugger halts the system, that task won't be able to run
1050 and reset the timer ... potentially causing resets in the middle of
1051 your debug sessions.
1053 It's rarely a good idea to disable such watchdogs, since their usage
1054 needs to be debugged just like all other parts of your firmware.
1055 That might however be your only option.
1057 Look instead for chip-specific ways to stop the watchdog from counting
1058 while the system is in a debug halt state. It may be simplest to set
1059 that non-counting mode in your debugger startup scripts. You may however
1060 need a different approach when, for example, a motor could be physically
1061 damaged by firmware remaining inactive in a debug halt state. That might
1062 involve a type of firmware mode where that "non-counting" mode is disabled
1063 at the beginning then re-enabled at the end; a watchdog reset might fire
1064 and complicate the debug session, but hardware (or people) would be
1065 protected.@footnote{Note that many systems support a "monitor mode" debug
1066 that is a somewhat cleaner way to address such issues. You can think of
1067 it as only halting part of the system, maybe just one task,
1068 instead of the whole thing.
1069 At this writing, January 2010, OpenOCD based debugging does not support
1070 monitor mode debug, only "halt mode" debug.}
1072 @item @b{ARM Semihosting}...
1073 @cindex ARM semihosting
1074 When linked with a special runtime library provided with many
1075 toolchains@footnote{See chapter 8 "Semihosting" in
1076 @uref{,
1077 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1078 The CodeSourcery EABI toolchain also includes a semihosting library.},
1079 your target code can use I/O facilities on the debug host. That library
1080 provides a small set of system calls which are handled by OpenOCD.
1081 It can let the debugger provide your system console and a file system,
1082 helping with early debugging or providing a more capable environment
1083 for sometimes-complex tasks like installing system firmware onto
1084 NAND or SPI flash.
1086 @item @b{ARM Wait-For-Interrupt}...
1087 Many ARM chips synchronize the JTAG clock using the core clock.
1088 Low power states which stop that core clock thus prevent JTAG access.
1089 Idle loops in tasking environments often enter those low power states
1090 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1092 You may want to @emph{disable that instruction} in source code,
1093 or otherwise prevent using that state,
1094 to ensure you can get JTAG access at any time.@footnote{As a more
1095 polite alternative, some processors have special debug-oriented
1096 registers which can be used to change various features including
1097 how the low power states are clocked while debugging.
1098 The STM32 DBGMCU_CR register is an example; at the cost of extra
1099 power consumption, JTAG can be used during low power states.}
1100 For example, the OpenOCD @command{halt} command may not
1101 work for an idle processor otherwise.
1103 @item @b{Delay after reset}...
1104 Not all chips have good support for debugger access
1105 right after reset; many LPC2xxx chips have issues here.
1106 Similarly, applications that reconfigure pins used for
1107 JTAG access as they start will also block debugger access.
1109 To work with boards like this, @emph{enable a short delay loop}
1110 the first thing after reset, before "real" startup activities.
1111 For example, one second's delay is usually more than enough
1112 time for a JTAG debugger to attach, so that
1113 early code execution can be debugged
1114 or firmware can be replaced.
1116 @item @b{Debug Communications Channel (DCC)}...
1117 Some processors include mechanisms to send messages over JTAG.
1118 Many ARM cores support these, as do some cores from other vendors.
1119 (OpenOCD may be able to use this DCC internally, speeding up some
1120 operations like writing to memory.)
1122 Your application may want to deliver various debugging messages
1123 over JTAG, by @emph{linking with a small library of code}
1124 provided with OpenOCD and using the utilities there to send
1125 various kinds of message.
1126 @xref{Software Debug Messages and Tracing}.
1128 @end itemize
1130 @section Target Hardware Setup
1132 Chip vendors often provide software development boards which
1133 are highly configurable, so that they can support all options
1134 that product boards may require. @emph{Make sure that any
1135 jumpers or switches match the system configuration you are
1136 working with.}
1138 Common issues include:
1140 @itemize @bullet
1142 @item @b{JTAG setup} ...
1143 Boards may support more than one JTAG configuration.
1144 Examples include jumpers controlling pullups versus pulldowns
1145 on the nTRST and/or nSRST signals, and choice of connectors
1146 (e.g. which of two headers on the base board,
1147 or one from a daughtercard).
1148 For some Texas Instruments boards, you may need to jumper the
1149 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1151 @item @b{Boot Modes} ...
1152 Complex chips often support multiple boot modes, controlled
1153 by external jumpers. Make sure this is set up correctly.
1154 For example many i.MX boards from NXP need to be jumpered
1155 to "ATX mode" to start booting using the on-chip ROM, when
1156 using second stage bootloader code stored in a NAND flash chip.
1158 Such explicit configuration is common, and not limited to
1159 booting from NAND. You might also need to set jumpers to
1160 start booting using code loaded from an MMC/SD card; external
1161 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1162 flash; some external host; or various other sources.
1165 @item @b{Memory Addressing} ...
1166 Boards which support multiple boot modes may also have jumpers
1167 to configure memory addressing. One board, for example, jumpers
1168 external chipselect 0 (used for booting) to address either
1169 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1170 or NAND flash. When it's jumpered to address NAND flash, that
1171 board must also be told to start booting from on-chip ROM.
1173 Your @file{board.cfg} file may also need to be told this jumper
1174 configuration, so that it can know whether to declare NOR flash
1175 using @command{flash bank} or instead declare NAND flash with
1176 @command{nand device}; and likewise which probe to perform in
1177 its @code{reset-init} handler.
1179 A closely related issue is bus width. Jumpers might need to
1180 distinguish between 8 bit or 16 bit bus access for the flash
1181 used to start booting.
1183 @item @b{Peripheral Access} ...
1184 Development boards generally provide access to every peripheral
1185 on the chip, sometimes in multiple modes (such as by providing
1186 multiple audio codec chips).
1187 This interacts with software
1188 configuration of pin multiplexing, where for example a
1189 given pin may be routed either to the MMC/SD controller
1190 or the GPIO controller. It also often interacts with
1191 configuration jumpers. One jumper may be used to route
1192 signals to an MMC/SD card slot or an expansion bus (which
1193 might in turn affect booting); others might control which
1194 audio or video codecs are used.
1196 @end itemize
1198 Plus you should of course have @code{reset-init} event handlers
1199 which set up the hardware to match that jumper configuration.
1200 That includes in particular any oscillator or PLL used to clock
1201 the CPU, and any memory controllers needed to access external
1202 memory and peripherals. Without such handlers, you won't be
1203 able to access those resources without working target firmware
1204 which can do that setup ... this can be awkward when you're
1205 trying to debug that target firmware. Even if there's a ROM
1206 bootloader which handles a few issues, it rarely provides full
1207 access to all board-specific capabilities.
1210 @node Config File Guidelines
1211 @chapter Config File Guidelines
1213 This chapter is aimed at any user who needs to write a config file,
1214 including developers and integrators of OpenOCD and any user who
1215 needs to get a new board working smoothly.
1216 It provides guidelines for creating those files.
1218 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1219 with files including the ones listed here.
1220 Use them as-is where you can; or as models for new files.
1221 @itemize @bullet
1222 @item @file{interface} ...
1223 These are for debug adapters.
1224 Files that configure JTAG adapters go here.
1225 @example
1226 $ ls interface
1227 arm-jtag-ew.cfg hitex_str9-comstick.cfg oocdlink.cfg
1228 arm-usb-ocd.cfg icebear.cfg openocd-usb.cfg
1229 at91rm9200.cfg jlink.cfg parport.cfg
1230 axm0432.cfg jtagkey2.cfg parport_dlc5.cfg
1231 calao-usb-a9260-c01.cfg jtagkey.cfg rlink.cfg
1232 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg sheevaplug.cfg
1233 calao-usb-a9260.cfg luminary.cfg signalyzer.cfg
1234 chameleon.cfg luminary-icdi.cfg stm32-stick.cfg
1235 cortino.cfg luminary-lm3s811.cfg turtelizer2.cfg
1236 dummy.cfg olimex-arm-usb-ocd.cfg usbprog.cfg
1237 flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
1238 $
1239 @end example
1240 @item @file{board} ...
1241 think Circuit Board, PWA, PCB, they go by many names. Board files
1242 contain initialization items that are specific to a board.
1243 They reuse target configuration files, since the same
1244 microprocessor chips are used on many boards,
1245 but support for external parts varies widely. For
1246 example, the SDRAM initialization sequence for the board, or the type
1247 of external flash and what address it uses. Any initialization
1248 sequence to enable that external flash or SDRAM should be found in the
1249 board file. Boards may also contain multiple targets: two CPUs; or
1250 a CPU and an FPGA.
1251 @example
1252 $ ls board
1253 arm_evaluator7t.cfg keil_mcb1700.cfg
1254 at91rm9200-dk.cfg keil_mcb2140.cfg
1255 at91sam9g20-ek.cfg linksys_nslu2.cfg
1256 atmel_at91sam7s-ek.cfg logicpd_imx27.cfg
1257 atmel_at91sam9260-ek.cfg mini2440.cfg
1258 atmel_sam3u_ek.cfg olimex_LPC2378STK.cfg
1259 crossbow_tech_imote2.cfg olimex_lpc_h2148.cfg
1260 csb337.cfg olimex_sam7_ex256.cfg
1261 csb732.cfg olimex_sam9_l9260.cfg
1262 digi_connectcore_wi-9c.cfg olimex_stm32_h103.cfg
1263 dm355evm.cfg omap2420_h4.cfg
1264 dm365evm.cfg osk5912.cfg
1265 dm6446evm.cfg pic-p32mx.cfg
1266 eir.cfg propox_mmnet1001.cfg
1267 ek-lm3s1968.cfg pxa255_sst.cfg
1268 ek-lm3s3748.cfg sheevaplug.cfg
1269 ek-lm3s811.cfg stm3210e_eval.cfg
1270 ek-lm3s9b9x.cfg stm32f10x_128k_eval.cfg
1271 hammer.cfg str910-eval.cfg
1272 hitex_lpc2929.cfg telo.cfg
1273 hitex_stm32-performancestick.cfg ti_beagleboard.cfg
1274 hitex_str9-comstick.cfg topas910.cfg
1275 iar_str912_sk.cfg topasa900.cfg
1276 imx27ads.cfg unknown_at91sam9260.cfg
1277 imx27lnst.cfg x300t.cfg
1278 imx31pdk.cfg zy1000.cfg
1279 $
1280 @end example
1281 @item @file{target} ...
1282 think chip. The ``target'' directory represents the JTAG TAPs
1283 on a chip
1284 which OpenOCD should control, not a board. Two common types of targets
1285 are ARM chips and FPGA or CPLD chips.
1286 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1287 the target config file defines all of them.
1288 @example
1289 $ ls target
1290 aduc702x.cfg imx27.cfg pxa255.cfg
1291 ar71xx.cfg imx31.cfg pxa270.cfg
1292 at91eb40a.cfg imx35.cfg readme.txt
1293 at91r40008.cfg is5114.cfg sam7se512.cfg
1294 at91rm9200.cfg ixp42x.cfg sam7x256.cfg
1295 at91sam3u1c.cfg lm3s1968.cfg samsung_s3c2410.cfg
1296 at91sam3u1e.cfg lm3s3748.cfg samsung_s3c2440.cfg
1297 at91sam3u2c.cfg lm3s6965.cfg samsung_s3c2450.cfg
1298 at91sam3u2e.cfg lm3s811.cfg samsung_s3c4510.cfg
1299 at91sam3u4c.cfg lm3s9b9x.cfg samsung_s3c6410.cfg
1300 at91sam3u4e.cfg lpc1768.cfg sharp_lh79532.cfg
1301 at91sam3uXX.cfg lpc2103.cfg smdk6410.cfg
1302 at91sam7sx.cfg lpc2124.cfg smp8634.cfg
1303 at91sam9260.cfg lpc2129.cfg stm32f1x.cfg
1304 c100.cfg lpc2148.cfg str710.cfg
1305 c100config.tcl lpc2294.cfg str730.cfg
1306 c100helper.tcl lpc2378.cfg str750.cfg
1307 c100regs.tcl lpc2478.cfg str912.cfg
1308 cs351x.cfg lpc2900.cfg telo.cfg
1309 davinci.cfg mega128.cfg ti_dm355.cfg
1310 dragonite.cfg netx500.cfg ti_dm365.cfg
1311 epc9301.cfg omap2420.cfg ti_dm6446.cfg
1312 feroceon.cfg omap3530.cfg tmpa900.cfg
1313 icepick.cfg omap5912.cfg tmpa910.cfg
1314 imx21.cfg pic32mx.cfg xba_revA3.cfg
1315 $
1316 @end example
1317 @item @emph{more} ... browse for other library files which may be useful.
1318 For example, there are various generic and CPU-specific utilities.
1319 @end itemize
1321 The @file{openocd.cfg} user config
1322 file may override features in any of the above files by
1323 setting variables before sourcing the target file, or by adding
1324 commands specific to their situation.
1326 @section Interface Config Files
1328 The user config file
1329 should be able to source one of these files with a command like this:
1331 @example
1332 source [find interface/FOOBAR.cfg]
1333 @end example
1335 A preconfigured interface file should exist for every debug adapter
1336 in use today with OpenOCD.
1337 That said, perhaps some of these config files
1338 have only been used by the developer who created it.
1340 A separate chapter gives information about how to set these up.
1341 @xref{Debug Adapter Configuration}.
1342 Read the OpenOCD source code (and Developer's GUide)
1343 if you have a new kind of hardware interface
1344 and need to provide a driver for it.
1346 @section Board Config Files
1347 @cindex config file, board
1348 @cindex board config file
1350 The user config file
1351 should be able to source one of these files with a command like this:
1353 @example
1354 source [find board/FOOBAR.cfg]
1355 @end example
1357 The point of a board config file is to package everything
1358 about a given board that user config files need to know.
1359 In summary the board files should contain (if present)
1361 @enumerate
1362 @item One or more @command{source [target/...cfg]} statements
1363 @item NOR flash configuration (@pxref{NOR Configuration})
1364 @item NAND flash configuration (@pxref{NAND Configuration})
1365 @item Target @code{reset} handlers for SDRAM and I/O configuration
1366 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1367 @item All things that are not ``inside a chip''
1368 @end enumerate
1370 Generic things inside target chips belong in target config files,
1371 not board config files. So for example a @code{reset-init} event
1372 handler should know board-specific oscillator and PLL parameters,
1373 which it passes to target-specific utility code.
1375 The most complex task of a board config file is creating such a
1376 @code{reset-init} event handler.
1377 Define those handlers last, after you verify the rest of the board
1378 configuration works.
1380 @subsection Communication Between Config files
1382 In addition to target-specific utility code, another way that
1383 board and target config files communicate is by following a
1384 convention on how to use certain variables.
1386 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1387 Thus the rule we follow in OpenOCD is this: Variables that begin with
1388 a leading underscore are temporary in nature, and can be modified and
1389 used at will within a target configuration file.
1391 Complex board config files can do the things like this,
1392 for a board with three chips:
1394 @example
1395 # Chip #1: PXA270 for network side, big endian
1396 set CHIPNAME network
1397 set ENDIAN big
1398 source [find target/pxa270.cfg]
1399 # on return: _TARGETNAME = network.cpu
1400 # other commands can refer to the "network.cpu" target.
1401 $_TARGETNAME configure .... events for this CPU..
1403 # Chip #2: PXA270 for video side, little endian
1404 set CHIPNAME video
1405 set ENDIAN little
1406 source [find target/pxa270.cfg]
1407 # on return: _TARGETNAME = video.cpu
1408 # other commands can refer to the "video.cpu" target.
1409 $_TARGETNAME configure .... events for this CPU..
1411 # Chip #3: Xilinx FPGA for glue logic
1412 set CHIPNAME xilinx
1413 unset ENDIAN
1414 source [find target/spartan3.cfg]
1415 @end example
1417 That example is oversimplified because it doesn't show any flash memory,
1418 or the @code{reset-init} event handlers to initialize external DRAM
1419 or (assuming it needs it) load a configuration into the FPGA.
1420 Such features are usually needed for low-level work with many boards,
1421 where ``low level'' implies that the board initialization software may
1422 not be working. (That's a common reason to need JTAG tools. Another
1423 is to enable working with microcontroller-based systems, which often
1424 have no debugging support except a JTAG connector.)
1426 Target config files may also export utility functions to board and user
1427 config files. Such functions should use name prefixes, to help avoid
1428 naming collisions.
1430 Board files could also accept input variables from user config files.
1431 For example, there might be a @code{J4_JUMPER} setting used to identify
1432 what kind of flash memory a development board is using, or how to set
1433 up other clocks and peripherals.
1435 @subsection Variable Naming Convention
1436 @cindex variable names
1438 Most boards have only one instance of a chip.
1439 However, it should be easy to create a board with more than
1440 one such chip (as shown above).
1441 Accordingly, we encourage these conventions for naming
1442 variables associated with different @file{target.cfg} files,
1443 to promote consistency and
1444 so that board files can override target defaults.
1446 Inputs to target config files include:
1448 @itemize @bullet
1449 @item @code{CHIPNAME} ...
1450 This gives a name to the overall chip, and is used as part of
1451 tap identifier dotted names.
1452 While the default is normally provided by the chip manufacturer,
1453 board files may need to distinguish between instances of a chip.
1454 @item @code{ENDIAN} ...
1455 By default @option{little} - although chips may hard-wire @option{big}.
1456 Chips that can't change endianness don't need to use this variable.
1457 @item @code{CPUTAPID} ...
1458 When OpenOCD examines the JTAG chain, it can be told verify the
1459 chips against the JTAG IDCODE register.
1460 The target file will hold one or more defaults, but sometimes the
1461 chip in a board will use a different ID (perhaps a newer revision).
1462 @end itemize
1464 Outputs from target config files include:
1466 @itemize @bullet
1467 @item @code{_TARGETNAME} ...
1468 By convention, this variable is created by the target configuration
1469 script. The board configuration file may make use of this variable to
1470 configure things like a ``reset init'' script, or other things
1471 specific to that board and that target.
1472 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1473 @code{_TARGETNAME1}, ... etc.
1474 @end itemize
1476 @subsection The reset-init Event Handler
1477 @cindex event, reset-init
1478 @cindex reset-init handler
1480 Board config files run in the OpenOCD configuration stage;
1481 they can't use TAPs or targets, since they haven't been
1482 fully set up yet.
1483 This means you can't write memory or access chip registers;
1484 you can't even verify that a flash chip is present.
1485 That's done later in event handlers, of which the target @code{reset-init}
1486 handler is one of the most important.
1488 Except on microcontrollers, the basic job of @code{reset-init} event
1489 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1490 Microcontrollers rarely use boot loaders; they run right out of their
1491 on-chip flash and SRAM memory. But they may want to use one of these
1492 handlers too, if just for developer convenience.
1494 @quotation Note
1495 Because this is so very board-specific, and chip-specific, no examples
1496 are included here.
1497 Instead, look at the board config files distributed with OpenOCD.
1498 If you have a boot loader, its source code will help; so will
1499 configuration files for other JTAG tools
1500 (@pxref{Translating Configuration Files}).
1501 @end quotation
1503 Some of this code could probably be shared between different boards.
1504 For example, setting up a DRAM controller often doesn't differ by
1505 much except the bus width (16 bits or 32?) and memory timings, so a
1506 reusable TCL procedure loaded by the @file{target.cfg} file might take
1507 those as parameters.
1508 Similarly with oscillator, PLL, and clock setup;
1509 and disabling the watchdog.
1510 Structure the code cleanly, and provide comments to help
1511 the next developer doing such work.
1512 (@emph{You might be that next person} trying to reuse init code!)
1514 The last thing normally done in a @code{reset-init} handler is probing
1515 whatever flash memory was configured. For most chips that needs to be
1516 done while the associated target is halted, either because JTAG memory
1517 access uses the CPU or to prevent conflicting CPU access.
1519 @subsection JTAG Clock Rate
1521 Before your @code{reset-init} handler has set up
1522 the PLLs and clocking, you may need to run with
1523 a low JTAG clock rate.
1524 @xref{JTAG Speed}.
1525 Then you'd increase that rate after your handler has
1526 made it possible to use the faster JTAG clock.
1527 When the initial low speed is board-specific, for example
1528 because it depends on a board-specific oscillator speed, then
1529 you should probably set it up in the board config file;
1530 if it's target-specific, it belongs in the target config file.
1532 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1533 @uref{} gives details.}
1534 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1535 Consult chip documentation to determine the peak JTAG clock rate,
1536 which might be less than that.
1538 @quotation Warning
1539 On most ARMs, JTAG clock detection is coupled to the core clock, so
1540 software using a @option{wait for interrupt} operation blocks JTAG access.
1541 Adaptive clocking provides a partial workaround, but a more complete
1542 solution just avoids using that instruction with JTAG debuggers.
1543 @end quotation
1545 If both the chip and the board support adaptive clocking,
1546 use the @command{jtag_rclk}
1547 command, in case your board is used with JTAG adapter which
1548 also supports it. Otherwise use @command{adapter_khz}.
1549 Set the slow rate at the beginning of the reset sequence,
1550 and the faster rate as soon as the clocks are at full speed.
1552 @section Target Config Files
1553 @cindex config file, target
1554 @cindex target config file
1556 Board config files communicate with target config files using
1557 naming conventions as described above, and may source one or
1558 more target config files like this:
1560 @example
1561 source [find target/FOOBAR.cfg]
1562 @end example
1564 The point of a target config file is to package everything
1565 about a given chip that board config files need to know.
1566 In summary the target files should contain
1568 @enumerate
1569 @item Set defaults
1570 @item Add TAPs to the scan chain
1571 @item Add CPU targets (includes GDB support)
1572 @item CPU/Chip/CPU-Core specific features
1573 @item On-Chip flash
1574 @end enumerate
1576 As a rule of thumb, a target file sets up only one chip.
1577 For a microcontroller, that will often include a single TAP,
1578 which is a CPU needing a GDB target, and its on-chip flash.
1580 More complex chips may include multiple TAPs, and the target
1581 config file may need to define them all before OpenOCD
1582 can talk to the chip.
1583 For example, some phone chips have JTAG scan chains that include
1584 an ARM core for operating system use, a DSP,
1585 another ARM core embedded in an image processing engine,
1586 and other processing engines.
1588 @subsection Default Value Boiler Plate Code
1590 All target configuration files should start with code like this,
1591 letting board config files express environment-specific
1592 differences in how things should be set up.
1594 @example
1595 # Boards may override chip names, perhaps based on role,
1596 # but the default should match what the vendor uses
1597 if @{ [info exists CHIPNAME] @} @{
1599 @} else @{
1600 set _CHIPNAME sam7x256
1601 @}
1603 # ONLY use ENDIAN with targets that can change it.
1604 if @{ [info exists ENDIAN] @} @{
1605 set _ENDIAN $ENDIAN
1606 @} else @{
1607 set _ENDIAN little
1608 @}
1610 # TAP identifiers may change as chips mature, for example with
1611 # new revision fields (the "3" here). Pick a good default; you
1612 # can pass several such identifiers to the "jtag newtap" command.
1613 if @{ [info exists CPUTAPID ] @} @{
1615 @} else @{
1616 set _CPUTAPID 0x3f0f0f0f
1617 @}
1618 @end example
1619 @c but 0x3f0f0f0f is for an str73x part ...
1621 @emph{Remember:} Board config files may include multiple target
1622 config files, or the same target file multiple times
1623 (changing at least @code{CHIPNAME}).
1625 Likewise, the target configuration file should define
1626 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1627 use it later on when defining debug targets:
1629 @example
1631 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1632 @end example
1634 @subsection Adding TAPs to the Scan Chain
1635 After the ``defaults'' are set up,
1636 add the TAPs on each chip to the JTAG scan chain.
1637 @xref{TAP Declaration}, and the naming convention
1638 for taps.
1640 In the simplest case the chip has only one TAP,
1641 probably for a CPU or FPGA.
1642 The config file for the Atmel AT91SAM7X256
1643 looks (in part) like this:
1645 @example
1646 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1647 @end example
1649 A board with two such at91sam7 chips would be able
1650 to source such a config file twice, with different
1651 values for @code{CHIPNAME}, so
1652 it adds a different TAP each time.
1654 If there are nonzero @option{-expected-id} values,
1655 OpenOCD attempts to verify the actual tap id against those values.
1656 It will issue error messages if there is mismatch, which
1657 can help to pinpoint problems in OpenOCD configurations.
1659 @example
1660 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1661 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1662 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1663 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1664 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1665 @end example
1667 There are more complex examples too, with chips that have
1668 multiple TAPs. Ones worth looking at include:
1670 @itemize
1671 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1672 plus a JRC to enable them
1673 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1674 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1675 is not currently used)
1676 @end itemize
1678 @subsection Add CPU targets
1680 After adding a TAP for a CPU, you should set it up so that
1681 GDB and other commands can use it.
1682 @xref{CPU Configuration}.
1683 For the at91sam7 example above, the command can look like this;
1684 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1685 to little endian, and this chip doesn't support changing that.
1687 @example
1689 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1690 @end example
1692 Work areas are small RAM areas associated with CPU targets.
1693 They are used by OpenOCD to speed up downloads,
1694 and to download small snippets of code to program flash chips.
1695 If the chip includes a form of ``on-chip-ram'' - and many do - define
1696 a work area if you can.
1697 Again using the at91sam7 as an example, this can look like:
1699 @example
1700 $_TARGETNAME configure -work-area-phys 0x00200000 \
1701 -work-area-size 0x4000 -work-area-backup 0
1702 @end example
1704 @anchor{Define CPU targets working in SMP}
1705 @subsection Define CPU targets working in SMP
1706 @cindex SMP
1707 After setting targets, you can define a list of targets working in SMP.
1709 @example
1710 set _TARGETNAME_1 $_CHIPNAME.cpu1
1711 set _TARGETNAME_2 $_CHIPNAME.cpu2
1712 target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap \
1713 -coreid 0 -dbgbase $_DAP_DBG1
1714 target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap \
1715 -coreid 1 -dbgbase $_DAP_DBG2
1716 #define 2 targets working in smp.
1717 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1718 @end example
1719 In the above example on cortex_a8, 2 cpus are working in SMP.
1720 In SMP only one GDB instance is created and :
1721 @itemize @bullet
1722 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1723 @item halt command triggers the halt of all targets in the list.
1724 @item resume command triggers the write context and the restart of all targets in the list.
1725 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1726 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1727 displayed by the GDB session @pxref{Using openocd SMP with GDB}.
1728 @end itemize
1730 The SMP behaviour can be disabled/enabled dynamically. On cortex_a8 following
1731 command have been implemented.
1732 @itemize @bullet
1733 @item cortex_a8 smp_on : enable SMP mode, behaviour is as described above.
1734 @item cortex_a8 smp_off : disable SMP mode, the current target is the one
1735 displayed in the GDB session, only this target is now controlled by GDB
1736 session. This behaviour is useful during system boot up.
1737 @item cortex_a8 smp_gdb : display/fix the core id displayed in GDB session see
1738 following example.
1739 @end itemize
1741 @example
1742 >cortex_a8 smp_gdb
1743 gdb coreid 0 -> -1
1744 #0 : coreid 0 is displayed to GDB ,
1745 #-> -1 : next resume triggers a real resume
1746 > cortex_a8 smp_gdb 1
1747 gdb coreid 0 -> 1
1748 #0 :coreid 0 is displayed to GDB ,
1749 #->1 : next resume displays coreid 1 to GDB
1750 > resume
1751 > cortex_a8 smp_gdb
1752 gdb coreid 1 -> 1
1753 #1 :coreid 1 is displayed to GDB ,
1754 #->1 : next resume displays coreid 1 to GDB
1755 > cortex_a8 smp_gdb -1
1756 gdb coreid 1 -> -1
1757 #1 :coreid 1 is displayed to GDB,
1758 #->-1 : next resume triggers a real resume
1759 @end example
1762 @subsection Chip Reset Setup
1764 As a rule, you should put the @command{reset_config} command
1765 into the board file. Most things you think you know about a
1766 chip can be tweaked by the board.
1768 Some chips have specific ways the TRST and SRST signals are
1769 managed. In the unusual case that these are @emph{chip specific}
1770 and can never be changed by board wiring, they could go here.
1771 For example, some chips can't support JTAG debugging without
1772 both signals.
1774 Provide a @code{reset-assert} event handler if you can.
1775 Such a handler uses JTAG operations to reset the target,
1776 letting this target config be used in systems which don't
1777 provide the optional SRST signal, or on systems where you
1778 don't want to reset all targets at once.
1779 Such a handler might write to chip registers to force a reset,
1780 use a JRC to do that (preferable -- the target may be wedged!),
1781 or force a watchdog timer to trigger.
1782 (For Cortex-M3 targets, this is not necessary. The target
1783 driver knows how to use trigger an NVIC reset when SRST is
1784 not available.)
1786 Some chips need special attention during reset handling if
1787 they're going to be used with JTAG.
1788 An example might be needing to send some commands right
1789 after the target's TAP has been reset, providing a
1790 @code{reset-deassert-post} event handler that writes a chip
1791 register to report that JTAG debugging is being done.
1792 Another would be reconfiguring the watchdog so that it stops
1793 counting while the core is halted in the debugger.
1795 JTAG clocking constraints often change during reset, and in
1796 some cases target config files (rather than board config files)
1797 are the right places to handle some of those issues.
1798 For example, immediately after reset most chips run using a
1799 slower clock than they will use later.
1800 That means that after reset (and potentially, as OpenOCD
1801 first starts up) they must use a slower JTAG clock rate
1802 than they will use later.
1803 @xref{JTAG Speed}.
1805 @quotation Important
1806 When you are debugging code that runs right after chip
1807 reset, getting these issues right is critical.
1808 In particular, if you see intermittent failures when
1809 OpenOCD verifies the scan chain after reset,
1810 look at how you are setting up JTAG clocking.
1811 @end quotation
1813 @anchor{The init_targets procedure}
1814 @subsection The init_targets procedure
1815 @cindex init_targets procedure
1817 Target config files can either be ``linear'' (script executed line-by-line when parsed in configuration stage,
1818 @xref{Configuration Stage}) or they can contain a special procedure called @code{init_targets}, which will be executed
1819 when entering run stage (after parsing all config files or after @code{init} command, @xref{Entering the Run Stage}).
1820 Such procedure can be overriden by ``next level'' script (which sources the original). This concept faciliates code
1821 reuse when basic target config files provide generic configuration procedures and @code{init_targets} procedure, which
1822 can then be sourced and enchanced or changed in a ``more specific'' target config file. This is not possible with
1823 ``linear'' config scripts, because sourcing them executes every initialization commands they provide.
1825 @example
1826 ### generic_file.cfg ###
1828 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1829 # basic initialization procedure ...
1830 @}
1832 proc init_targets @{@} @{
1833 # initializes generic chip with 4kB of flash and 1kB of RAM
1834 setup_my_chip MY_GENERIC_CHIP 4096 1024
1835 @}
1837 ### specific_file.cfg ###
1839 source [find target/generic_file.cfg]
1841 proc init_targets @{@} @{
1842 # initializes specific chip with 128kB of flash and 64kB of RAM
1843 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1844 @}
1845 @end example
1847 The easiest way to convert ``linear'' config files to @code{init_targets} version is to enclose every line of ``code''
1848 (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1850 For an example of this scheme see LPC2000 target config files.
1852 @subsection ARM Core Specific Hacks
1854 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1855 special high speed download features - enable it.
1857 If present, the MMU, the MPU and the CACHE should be disabled.
1859 Some ARM cores are equipped with trace support, which permits
1860 examination of the instruction and data bus activity. Trace
1861 activity is controlled through an ``Embedded Trace Module'' (ETM)
1862 on one of the core's scan chains. The ETM emits voluminous data
1863 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
1864 If you are using an external trace port,
1865 configure it in your board config file.
1866 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1867 configure it in your target config file.
1869 @example
1870 etm config $_TARGETNAME 16 normal full etb
1871 etb config $_TARGETNAME $_CHIPNAME.etb
1872 @end example
1874 @subsection Internal Flash Configuration
1876 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1878 @b{Never ever} in the ``target configuration file'' define any type of
1879 flash that is external to the chip. (For example a BOOT flash on
1880 Chip Select 0.) Such flash information goes in a board file - not
1881 the TARGET (chip) file.
1883 Examples:
1884 @itemize @bullet
1885 @item at91sam7x256 - has 256K flash YES enable it.
1886 @item str912 - has flash internal YES enable it.
1887 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1888 @item pxa270 - again - CS0 flash - it goes in the board file.
1889 @end itemize
1891 @anchor{Translating Configuration Files}
1892 @section Translating Configuration Files
1893 @cindex translation
1894 If you have a configuration file for another hardware debugger
1895 or toolset (Abatron, BDI2000, BDI3000, CCS,
1896 Lauterbach, Segger, Macraigor, etc.), translating
1897 it into OpenOCD syntax is often quite straightforward. The most tricky
1898 part of creating a configuration script is oftentimes the reset init
1899 sequence where e.g. PLLs, DRAM and the like is set up.
1901 One trick that you can use when translating is to write small
1902 Tcl procedures to translate the syntax into OpenOCD syntax. This
1903 can avoid manual translation errors and make it easier to
1904 convert other scripts later on.
1906 Example of transforming quirky arguments to a simple search and
1907 replace job:
1909 @example
1910 # Lauterbach syntax(?)
1911 #
1912 # Data.Set c15:0x042f %long 0x40000015
1913 #
1914 # OpenOCD syntax when using procedure below.
1915 #
1916 # setc15 0x01 0x00050078
1918 proc setc15 @{regs value@} @{
1919 global TARGETNAME
1921 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
1923 arm mcr 15 [expr ($regs>>12)&0x7] \
1924 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
1925 [expr ($regs>>8)&0x7] $value
1926 @}
1927 @end example
1931 @node Daemon Configuration
1932 @chapter Daemon Configuration
1933 @cindex initialization
1934 The commands here are commonly found in the openocd.cfg file and are
1935 used to specify what TCP/IP ports are used, and how GDB should be
1936 supported.
1938 @anchor{Configuration Stage}
1939 @section Configuration Stage
1940 @cindex configuration stage
1941 @cindex config command
1943 When the OpenOCD server process starts up, it enters a
1944 @emph{configuration stage} which is the only time that
1945 certain commands, @emph{configuration commands}, may be issued.
1946 Normally, configuration commands are only available
1947 inside startup scripts.
1949 In this manual, the definition of a configuration command is
1950 presented as a @emph{Config Command}, not as a @emph{Command}
1951 which may be issued interactively.
1952 The runtime @command{help} command also highlights configuration
1953 commands, and those which may be issued at any time.
1955 Those configuration commands include declaration of TAPs,
1956 flash banks,
1957 the interface used for JTAG communication,
1958 and other basic setup.
1959 The server must leave the configuration stage before it
1960 may access or activate TAPs.
1961 After it leaves this stage, configuration commands may no
1962 longer be issued.
1964 @anchor{Entering the Run Stage}
1965 @section Entering the Run Stage
1967 The first thing OpenOCD does after leaving the configuration
1968 stage is to verify that it can talk to the scan chain
1969 (list of TAPs) which has been configured.
1970 It will warn if it doesn't find TAPs it expects to find,
1971 or finds TAPs that aren't supposed to be there.
1972 You should see no errors at this point.
1973 If you see errors, resolve them by correcting the
1974 commands you used to configure the server.
1975 Common errors include using an initial JTAG speed that's too
1976 fast, and not providing the right IDCODE values for the TAPs
1977 on the scan chain.
1979 Once OpenOCD has entered the run stage, a number of commands
1980 become available.
1981 A number of these relate to the debug targets you may have declared.
1982 For example, the @command{mww} command will not be available until
1983 a target has been successfuly instantiated.
1984 If you want to use those commands, you may need to force
1985 entry to the run stage.
1987 @deffn {Config Command} init
1988 This command terminates the configuration stage and
1989 enters the run stage. This helps when you need to have
1990 the startup scripts manage tasks such as resetting the target,
1991 programming flash, etc. To reset the CPU upon startup, add "init" and
1992 "reset" at the end of the config script or at the end of the OpenOCD
1993 command line using the @option{-c} command line switch.
1995 If this command does not appear in any startup/configuration file
1996 OpenOCD executes the command for you after processing all
1997 configuration files and/or command line options.
1999 @b{NOTE:} This command normally occurs at or near the end of your
2000 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2001 targets ready. For example: If your openocd.cfg file needs to
2002 read/write memory on your target, @command{init} must occur before
2003 the memory read/write commands. This includes @command{nand probe}.
2004 @end deffn
2006 @deffn {Overridable Procedure} jtag_init
2007 This is invoked at server startup to verify that it can talk
2008 to the scan chain (list of TAPs) which has been configured.
2010 The default implementation first tries @command{jtag arp_init},
2011 which uses only a lightweight JTAG reset before examining the
2012 scan chain.
2013 If that fails, it tries again, using a harder reset
2014 from the overridable procedure @command{init_reset}.
2016 Implementations must have verified the JTAG scan chain before
2017 they return.
2018 This is done by calling @command{jtag arp_init}
2019 (or @command{jtag arp_init-reset}).
2020 @end deffn
2022 @anchor{TCP/IP Ports}
2023 @section TCP/IP Ports
2024 @cindex TCP port
2025 @cindex server
2026 @cindex port
2027 @cindex security
2028 The OpenOCD server accepts remote commands in several syntaxes.
2029 Each syntax uses a different TCP/IP port, which you may specify
2030 only during configuration (before those ports are opened).
2032 For reasons including security, you may wish to prevent remote
2033 access using one or more of these ports.
2034 In such cases, just specify the relevant port number as zero.
2035 If you disable all access through TCP/IP, you will need to
2036 use the command line @option{-pipe} option.
2038 @deffn {Command} gdb_port [number]
2039 @cindex GDB server
2040 Normally gdb listens to a TCP/IP port, but GDB can also
2041 communicate via pipes(stdin/out or named pipes). The name
2042 "gdb_port" stuck because it covers probably more than 90% of
2043 the normal use cases.
2045 No arguments reports GDB port. "pipe" means listen to stdin
2046 output to stdout, an integer is base port number, "disable"
2047 disables the gdb server.
2049 When using "pipe", also use log_output to redirect the log
2050 output to a file so as not to flood the stdin/out pipes.
2052 The -p/--pipe option is deprecated and a warning is printed
2053 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2055 Any other string is interpreted as named pipe to listen to.
2056 Output pipe is the same name as input pipe, but with 'o' appended,
2057 e.g. /var/gdb, /var/gdbo.
2059 The GDB port for the first target will be the base port, the
2060 second target will listen on gdb_port + 1, and so on.
2061 When not specified during the configuration stage,
2062 the port @var{number} defaults to 3333.
2063 @end deffn
2065 @deffn {Command} tcl_port [number]
2066 Specify or query the port used for a simplified RPC
2067 connection that can be used by clients to issue TCL commands and get the
2068 output from the Tcl engine.
2069 Intended as a machine interface.
2070 When not specified during the configuration stage,
2071 the port @var{number} defaults to 6666.
2073 @end deffn
2075 @deffn {Command} telnet_port [number]
2076 Specify or query the
2077 port on which to listen for incoming telnet connections.
2078 This port is intended for interaction with one human through TCL commands.
2079 When not specified during the configuration stage,
2080 the port @var{number} defaults to 4444.
2081 When specified as zero, this port is not activated.
2082 @end deffn
2084 @anchor{GDB Configuration}
2085 @section GDB Configuration
2086 @cindex GDB
2087 @cindex GDB configuration
2088 You can reconfigure some GDB behaviors if needed.
2089 The ones listed here are static and global.
2090 @xref{Target Configuration}, about configuring individual targets.
2091 @xref{Target Events}, about configuring target-specific event handling.
2093 @anchor{gdb_breakpoint_override}
2094 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2095 Force breakpoint type for gdb @command{break} commands.
2096 This option supports GDB GUIs which don't
2097 distinguish hard versus soft breakpoints, if the default OpenOCD and
2098 GDB behaviour is not sufficient. GDB normally uses hardware
2099 breakpoints if the memory map has been set up for flash regions.
2100 @end deffn
2102 @anchor{gdb_flash_program}
2103 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2104 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2105 vFlash packet is received.
2106 The default behaviour is @option{enable}.
2107 @end deffn
2109 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2110 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2111 requested. GDB will then know when to set hardware breakpoints, and program flash
2112 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2113 for flash programming to work.
2114 Default behaviour is @option{enable}.
2115 @xref{gdb_flash_program}.
2116 @end deffn
2118 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2119 Specifies whether data aborts cause an error to be reported
2120 by GDB memory read packets.
2121 The default behaviour is @option{disable};
2122 use @option{enable} see these errors reported.
2123 @end deffn
2125 @anchor{Event Polling}
2126 @section Event Polling
2128 Hardware debuggers are parts of asynchronous systems,
2129 where significant events can happen at any time.
2130 The OpenOCD server needs to detect some of these events,
2131 so it can report them to through TCL command line
2132 or to GDB.
2134 Examples of such events include:
2136 @itemize
2137 @item One of the targets can stop running ... maybe it triggers
2138 a code breakpoint or data watchpoint, or halts itself.
2139 @item Messages may be sent over ``debug message'' channels ... many
2140 targets support such messages sent over JTAG,
2141 for receipt by the person debugging or tools.
2142 @item Loss of power ... some adapters can detect these events.
2143 @item Resets not issued through JTAG ... such reset sources
2144 can include button presses or other system hardware, sometimes
2145 including the target itself (perhaps through a watchdog).
2146 @item Debug instrumentation sometimes supports event triggering
2147 such as ``trace buffer full'' (so it can quickly be emptied)
2148 or other signals (to correlate with code behavior).
2149 @end itemize
2151 None of those events are signaled through standard JTAG signals.
2152 However, most conventions for JTAG connectors include voltage
2153 level and system reset (SRST) signal detection.
2154 Some connectors also include instrumentation signals, which
2155 can imply events when those signals are inputs.
2157 In general, OpenOCD needs to periodically check for those events,
2158 either by looking at the status of signals on the JTAG connector
2159 or by sending synchronous ``tell me your status'' JTAG requests
2160 to the various active targets.
2161 There is a command to manage and monitor that polling,
2162 which is normally done in the background.
2164 @deffn Command poll [@option{on}|@option{off}]
2165 Poll the current target for its current state.
2166 (Also, @pxref{target curstate}.)
2167 If that target is in debug mode, architecture
2168 specific information about the current state is printed.
2169 An optional parameter
2170 allows background polling to be enabled and disabled.
2172 You could use this from the TCL command shell, or
2173 from GDB using @command{monitor poll} command.
2174 Leave background polling enabled while you're using GDB.
2175 @example
2176 > poll
2177 background polling: on
2178 target state: halted
2179 target halted in ARM state due to debug-request, \
2180 current mode: Supervisor
2181 cpsr: 0x800000d3 pc: 0x11081bfc
2182 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2183 >
2184 @end example
2185 @end deffn
2187 @node Debug Adapter Configuration
2188 @chapter Debug Adapter Configuration
2189 @cindex config file, interface
2190 @cindex interface config file
2192 Correctly installing OpenOCD includes making your operating system give
2193 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2194 are used to select which one is used, and to configure how it is used.
2196 @quotation Note
2197 Because OpenOCD started out with a focus purely on JTAG, you may find
2198 places where it wrongly presumes JTAG is the only transport protocol
2199 in use. Be aware that recent versions of OpenOCD are removing that
2200 limitation. JTAG remains more functional than most other transports.
2201 Other transports do not support boundary scan operations, or may be
2202 specific to a given chip vendor. Some might be usable only for
2203 programming flash memory, instead of also for debugging.
2204 @end quotation
2206 Debug Adapters/Interfaces/Dongles are normally configured
2207 through commands in an interface configuration
2208 file which is sourced by your @file{openocd.cfg} file, or
2209 through a command line @option{-f interface/....cfg} option.
2211 @example
2212 source [find interface/olimex-jtag-tiny.cfg]
2213 @end example
2215 These commands tell
2216 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2217 A few cases are so simple that you only need to say what driver to use:
2219 @example
2220 # jlink interface
2221 interface jlink
2222 @end example
2224 Most adapters need a bit more configuration than that.
2227 @section Interface Configuration
2229 The interface command tells OpenOCD what type of debug adapter you are
2230 using. Depending on the type of adapter, you may need to use one or
2231 more additional commands to further identify or configure the adapter.
2233 @deffn {Config Command} {interface} name
2234 Use the interface driver @var{name} to connect to the
2235 target.
2236 @end deffn
2238 @deffn Command {interface_list}
2239 List the debug adapter drivers that have been built into
2240 the running copy of OpenOCD.
2241 @end deffn
2242 @deffn Command {interface transports} transport_name+
2243 Specifies the transports supported by this debug adapter.
2244 The adapter driver builds-in similar knowledge; use this only
2245 when external configuration (such as jumpering) changes what
2246 the hardware can support.
2247 @end deffn
2251 @deffn Command {adapter_name}
2252 Returns the name of the debug adapter driver being used.
2253 @end deffn
2255 @section Interface Drivers
2257 Each of the interface drivers listed here must be explicitly
2258 enabled when OpenOCD is configured, in order to be made
2259 available at run time.
2261 @deffn {Interface Driver} {amt_jtagaccel}
2262 Amontec Chameleon in its JTAG Accelerator configuration,
2263 connected to a PC's EPP mode parallel port.
2264 This defines some driver-specific commands:
2266 @deffn {Config Command} {parport_port} number
2267 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2268 the number of the @file{/dev/parport} device.
2269 @end deffn
2271 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2272 Displays status of RTCK option.
2273 Optionally sets that option first.
2274 @end deffn
2275 @end deffn
2277 @deffn {Interface Driver} {arm-jtag-ew}
2278 Olimex ARM-JTAG-EW USB adapter
2279 This has one driver-specific command:
2281 @deffn Command {armjtagew_info}
2282 Logs some status
2283 @end deffn
2284 @end deffn
2286 @deffn {Interface Driver} {at91rm9200}
2287 Supports bitbanged JTAG from the local system,
2288 presuming that system is an Atmel AT91rm9200
2289 and a specific set of GPIOs is used.
2290 @c command: at91rm9200_device NAME
2291 @c chooses among list of bit configs ... only one option
2292 @end deffn
2294 @deffn {Interface Driver} {dummy}
2295 A dummy software-only driver for debugging.
2296 @end deffn
2298 @deffn {Interface Driver} {ep93xx}
2299 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2300 @end deffn
2302 @deffn {Interface Driver} {ft2232}
2303 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2304 These interfaces have several commands, used to configure the driver
2305 before initializing the JTAG scan chain:
2307 @deffn {Config Command} {ft2232_device_desc} description
2308 Provides the USB device description (the @emph{iProduct string})
2309 of the FTDI FT2232 device. If not
2310 specified, the FTDI default value is used. This setting is only valid
2311 if compiled with FTD2XX support.
2312 @end deffn
2314 @deffn {Config Command} {ft2232_serial} serial-number
2315 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2316 in case the vendor provides unique IDs and more than one FT2232 device
2317 is connected to the host.
2318 If not specified, serial numbers are not considered.
2319 (Note that USB serial numbers can be arbitrary Unicode strings,
2320 and are not restricted to containing only decimal digits.)
2321 @end deffn
2323 @deffn {Config Command} {ft2232_layout} name
2324 Each vendor's FT2232 device can use different GPIO signals
2325 to control output-enables, reset signals, and LEDs.
2326 Currently valid layout @var{name} values include:
2327 @itemize @minus
2328 @item @b{axm0432_jtag} Axiom AXM-0432
2329 @item @b{comstick} Hitex STR9 comstick
2330 @item @b{cortino} Hitex Cortino JTAG interface
2331 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
2332 either for the local Cortex-M3 (SRST only)
2333 or in a passthrough mode (neither SRST nor TRST)
2334 This layout can not support the SWO trace mechanism, and should be
2335 used only for older boards (before rev C).
2336 @item @b{luminary_icdi} This layout should be used with most Luminary
2337 eval boards, including Rev C LM3S811 eval boards and the eponymous
2338 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2339 to debug some other target. It can support the SWO trace mechanism.
2340 @item @b{flyswatter} Tin Can Tools Flyswatter
2341 @item @b{icebear} ICEbear JTAG adapter from Section 5
2342 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2343 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2344 @item @b{m5960} American Microsystems M5960
2345 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2346 @item @b{oocdlink} OOCDLink
2347 @c oocdlink ~= jtagkey_prototype_v1
2348 @item @b{redbee-econotag} Integrated with a Redbee development board.
2349 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2350 @item @b{sheevaplug} Marvell Sheevaplug development kit
2351 @item @b{signalyzer} Xverve Signalyzer
2352 @item @b{stm32stick} Hitex STM32 Performance Stick
2353 @item @b{turtelizer2} egnite Software turtelizer2
2354 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2355 @end itemize
2356 @end deffn
2358 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2359 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2360 default values are used.
2361 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2362 @example
2363 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2364 @end example
2365 @end deffn
2367 @deffn {Config Command} {ft2232_latency} ms
2368 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2369 ft2232_read() fails to return the expected number of bytes. This can be caused by
2370 USB communication delays and has proved hard to reproduce and debug. Setting the
2371 FT2232 latency timer to a larger value increases delays for short USB packets but it
2372 also reduces the risk of timeouts before receiving the expected number of bytes.
2373 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2374 @end deffn
2376 For example, the interface config file for a
2377 Turtelizer JTAG Adapter looks something like this:
2379 @example
2380 interface ft2232
2381 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2382 ft2232_layout turtelizer2
2383 ft2232_vid_pid 0x0403 0xbdc8
2384 @end example
2385 @end deffn
2387 @deffn {Interface Driver} {remote_bitbang}
2388 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2389 with a remote process and sends ASCII encoded bitbang requests to that process
2390 instead of directly driving JTAG.
2392 The remote_bitbang driver is useful for debugging software running on
2393 processors which are being simulated.
2395 @deffn {Config Command} {remote_bitbang_port} number
2396 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2397 sockets instead of TCP.
2398 @end deffn
2400 @deffn {Config Command} {remote_bitbang_host} hostname
2401 Specifies the hostname of the remote process to connect to using TCP, or the
2402 name of the UNIX socket to use if remote_bitbang_port is 0.
2403 @end deffn
2405 For example, to connect remotely via TCP to the host foobar you might have
2406 something like:
2408 @example
2409 interface remote_bitbang
2410 remote_bitbang_port 3335
2411 remote_bitbang_host foobar
2412 @end example
2414 To connect to another process running locally via UNIX sockets with socket
2415 named mysocket:
2417 @example
2418 interface remote_bitbang
2419 remote_bitbang_port 0
2420 remote_bitbang_host mysocket
2421 @end example
2422 @end deffn
2424 @deffn {Interface Driver} {usb_blaster}
2425 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2426 for FTDI chips. These interfaces have several commands, used to
2427 configure the driver before initializing the JTAG scan chain:
2429 @deffn {Config Command} {usb_blaster_device_desc} description
2430 Provides the USB device description (the @emph{iProduct string})
2431 of the FTDI FT245 device. If not
2432 specified, the FTDI default value is used. This setting is only valid
2433 if compiled with FTD2XX support.
2434 @end deffn
2436 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2437 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2438 default values are used.
2439 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2440 Altera USB-Blaster (default):
2441 @example
2442 usb_blaster_vid_pid 0x09FB 0x6001
2443 @end example
2444 The following VID/PID is for Kolja Waschk's USB JTAG:
2445 @example
2446 usb_blaster_vid_pid 0x16C0 0x06AD
2447 @end example
2448 @end deffn
2450 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2451 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2452 female JTAG header). These pins can be used as SRST and/or TRST provided the
2453 appropriate connections are made on the target board.
2455 For example, to use pin 6 as SRST (as with an AVR board):
2456 @example
2457 $_TARGETNAME configure -event reset-assert \
2458 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2459 @end example
2460 @end deffn
2462 @end deffn
2464 @deffn {Interface Driver} {gw16012}
2465 Gateworks GW16012 JTAG programmer.
2466 This has one driver-specific command:
2468 @deffn {Config Command} {parport_port} [port_number]
2469 Display either the address of the I/O port
2470 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2471 If a parameter is provided, first switch to use that port.
2472 This is a write-once setting.
2473 @end deffn
2474 @end deffn
2476 @deffn {Interface Driver} {jlink}
2477 Segger jlink USB adapter
2478 @c command: jlink caps
2479 @c dumps jlink capabilities
2480 @c command: jlink config
2481 @c access J-Link configurationif no argument this will dump the config
2482 @c command: jlink config kickstart [val]
2483 @c set Kickstart power on JTAG-pin 19.
2484 @c command: jlink config mac_address [ff:ff:ff:ff:ff:ff]
2485 @c set the MAC Address
2486 @c command: jlink config ip [A.B.C.D[/E] [F.G.H.I]]
2487 @c set the ip address of the J-Link Pro, "
2488 @c where A.B.C.D is the ip,
2489 @c E the bit of the subnet mask
2490 @c F.G.H.I the subnet mask
2491 @c command: jlink config reset
2492 @c reset the current config
2493 @c command: jlink config save
2494 @c save the current config
2495 @c command: jlink config usb_address [0x00 to 0x03 or 0xff]
2496 @c set the USB-Address,
2497 @c This will change the product id
2498 @c command: jlink info
2499 @c dumps status
2500 @c command: jlink hw_jtag (2|3)
2501 @c sets version 2 or 3
2502 @c command: jlink pid
2503 @c set the pid of the interface we want to use
2504 @end deffn
2506 @deffn {Interface Driver} {parport}
2507 Supports PC parallel port bit-banging cables:
2508 Wigglers, PLD download cable, and more.
2509 These interfaces have several commands, used to configure the driver
2510 before initializing the JTAG scan chain:
2512 @deffn {Config Command} {parport_cable} name
2513 Set the layout of the parallel port cable used to connect to the target.
2514 This is a write-once setting.
2515 Currently valid cable @var{name} values include:
2517 @itemize @minus
2518 @item @b{altium} Altium Universal JTAG cable.
2519 @item @b{arm-jtag} Same as original wiggler except SRST and
2520 TRST connections reversed and TRST is also inverted.
2521 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2522 in configuration mode. This is only used to
2523 program the Chameleon itself, not a connected target.
2524 @item @b{dlc5} The Xilinx Parallel cable III.
2525 @item @b{flashlink} The ST Parallel cable.
2526 @item @b{lattice} Lattice ispDOWNLOAD Cable
2527 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2528 some versions of
2529 Amontec's Chameleon Programmer. The new version available from
2530 the website uses the original Wiggler layout ('@var{wiggler}')
2531 @item @b{triton} The parallel port adapter found on the
2532 ``Karo Triton 1 Development Board''.
2533 This is also the layout used by the HollyGates design
2534 (see @uref{}).
2535 @item @b{wiggler} The original Wiggler layout, also supported by
2536 several clones, such as the Olimex ARM-JTAG
2537 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2538 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2539 @end itemize
2540 @end deffn
2542 @deffn {Config Command} {parport_port} [port_number]
2543 Display either the address of the I/O port
2544 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2545 If a parameter is provided, first switch to use that port.
2546 This is a write-once setting.
2548 When using PPDEV to access the parallel port, use the number of the parallel port:
2549 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2550 you may encounter a problem.
2551 @end deffn
2553 @deffn Command {parport_toggling_time} [nanoseconds]
2554 Displays how many nanoseconds the hardware needs to toggle TCK;
2555 the parport driver uses this value to obey the
2556 @command{adapter_khz} configuration.
2557 When the optional @var{nanoseconds} parameter is given,
2558 that setting is changed before displaying the current value.
2560 The default setting should work reasonably well on commodity PC hardware.
2561 However, you may want to calibrate for your specific hardware.
2562 @quotation Tip
2563 To measure the toggling time with a logic analyzer or a digital storage
2564 oscilloscope, follow the procedure below:
2565 @example
2566 > parport_toggling_time 1000
2567 > adapter_khz 500
2568 @end example
2569 This sets the maximum JTAG clock speed of the hardware, but
2570 the actual speed probably deviates from the requested 500 kHz.
2571 Now, measure the time between the two closest spaced TCK transitions.
2572 You can use @command{runtest 1000} or something similar to generate a
2573 large set of samples.
2574 Update the setting to match your measurement:
2575 @example
2576 > parport_toggling_time <measured nanoseconds>
2577 @end example
2578 Now the clock speed will be a better match for @command{adapter_khz rate}
2579 commands given in OpenOCD scripts and event handlers.
2581 You can do something similar with many digital multimeters, but note
2582 that you'll probably need to run the clock continuously for several
2583 seconds before it decides what clock rate to show. Adjust the
2584 toggling time up or down until the measured clock rate is a good
2585 match for the adapter_khz rate you specified; be conservative.
2586 @end quotation
2587 @end deffn
2589 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2590 This will configure the parallel driver to write a known
2591 cable-specific value to the parallel interface on exiting OpenOCD.
2592 @end deffn
2594 For example, the interface configuration file for a
2595 classic ``Wiggler'' cable on LPT2 might look something like this:
2597 @example
2598 interface parport
2599 parport_port 0x278
2600 parport_cable wiggler
2601 @end example
2602 @end deffn
2604 @deffn {Interface Driver} {presto}
2605 ASIX PRESTO USB JTAG programmer.
2606 @deffn {Config Command} {presto_serial} serial_string
2607 Configures the USB serial number of the Presto device to use.
2608 @end deffn
2609 @end deffn
2611 @deffn {Interface Driver} {rlink}
2612 Raisonance RLink USB adapter
2613 @end deffn
2615 @deffn {Interface Driver} {usbprog}
2616 usbprog is a freely programmable USB adapter.
2617 @end deffn
2619 @deffn {Interface Driver} {vsllink}
2620 vsllink is part of Versaloon which is a versatile USB programmer.
2622 @quotation Note
2623 This defines quite a few driver-specific commands,
2624 which are not currently documented here.
2625 @end quotation
2626 @end deffn
2628 @deffn {Interface Driver} {stlink}
2629 ST Micro ST-LINK adapter.
2630 @end deffn
2632 @deffn {Interface Driver} {ZY1000}
2633 This is the Zylin ZY1000 JTAG debugger.
2634 @end deffn
2636 @quotation Note
2637 This defines some driver-specific commands,
2638 which are not currently documented here.
2639 @end quotation
2641 @deffn Command power [@option{on}|@option{off}]
2642 Turn power switch to target on/off.
2643 No arguments: print status.
2644 @end deffn
2646 @section Transport Configuration
2647 @cindex Transport
2648 As noted earlier, depending on the version of OpenOCD you use,
2649 and the debug adapter you are using,
2650 several transports may be available to
2651 communicate with debug targets (or perhaps to program flash memory).
2652 @deffn Command {transport list}
2653 displays the names of the transports supported by this
2654 version of OpenOCD.
2655 @end deffn
2657 @deffn Command {transport select} transport_name
2658 Select which of the supported transports to use in this OpenOCD session.
2659 The transport must be supported by the debug adapter hardware and by the
2660 version of OPenOCD you are using (including the adapter's driver).
2661 No arguments: returns name of session's selected transport.
2662 @end deffn
2664 @subsection JTAG Transport
2665 @cindex JTAG
2666 JTAG is the original transport supported by OpenOCD, and most
2667 of the OpenOCD commands support it.
2668 JTAG transports expose a chain of one or more Test Access Points (TAPs),
2669 each of which must be explicitly declared.
2670 JTAG supports both debugging and boundary scan testing.
2671 Flash programming support is built on top of debug support.
2672 @subsection SWD Transport
2673 @cindex SWD
2674 @cindex Serial Wire Debug
2675 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
2676 Debug Access Point (DAP, which must be explicitly declared.
2677 (SWD uses fewer signal wires than JTAG.)
2678 SWD is debug-oriented, and does not support boundary scan testing.
2679 Flash programming support is built on top of debug support.
2680 (Some processors support both JTAG and SWD.)
2681 @deffn Command {swd newdap} ...
2682 Declares a single DAP which uses SWD transport.
2683 Parameters are currently the same as "jtag newtap" but this is
2684 expected to change.
2685 @end deffn
2686 @deffn Command {swd wcr trn prescale}
2687 Updates TRN (turnaraound delay) and prescaling.fields of the
2688 Wire Control Register (WCR).
2689 No parameters: displays current settings.
2690 @end deffn
2692 @subsection SPI Transport
2693 @cindex SPI
2694 @cindex Serial Peripheral Interface
2695 The Serial Peripheral Interface (SPI) is a general purpose transport
2696 which uses four wire signaling. Some processors use it as part of a
2697 solution for flash programming.
2699 @anchor{JTAG Speed}
2700 @section JTAG Speed
2701 JTAG clock setup is part of system setup.
2702 It @emph{does not belong with interface setup} since any interface
2703 only knows a few of the constraints for the JTAG clock speed.
2704 Sometimes the JTAG speed is
2705 changed during the target initialization process: (1) slow at
2706 reset, (2) program the CPU clocks, (3) run fast.
2707 Both the "slow" and "fast" clock rates are functions of the
2708 oscillators used, the chip, the board design, and sometimes
2709 power management software that may be active.
2711 The speed used during reset, and the scan chain verification which
2712 follows reset, can be adjusted using a @code{reset-start}
2713 target event handler.
2714 It can then be reconfigured to a faster speed by a
2715 @code{reset-init} target event handler after it reprograms those
2716 CPU clocks, or manually (if something else, such as a boot loader,
2717 sets up those clocks).
2718 @xref{Target Events}.
2719 When the initial low JTAG speed is a chip characteristic, perhaps
2720 because of a required oscillator speed, provide such a handler
2721 in the target config file.
2722 When that speed is a function of a board-specific characteristic
2723 such as which speed oscillator is used, it belongs in the board
2724 config file instead.
2725 In both cases it's safest to also set the initial JTAG clock rate
2726 to that same slow speed, so that OpenOCD never starts up using a
2727 clock speed that's faster than the scan chain can support.
2729 @example
2730 jtag_rclk 3000
2731 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
2732 @end example
2734 If your system supports adaptive clocking (RTCK), configuring
2735 JTAG to use that is probably the most robust approach.
2736 However, it introduces delays to synchronize clocks; so it
2737 may not be the fastest solution.
2739 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
2740 instead of @command{adapter_khz}, but only for (ARM) cores and boards
2741 which support adaptive clocking.
2743 @deffn {Command} adapter_khz max_speed_kHz
2744 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
2745 JTAG interfaces usually support a limited number of
2746 speeds. The speed actually used won't be faster
2747 than the speed specified.
2749 Chip data sheets generally include a top JTAG clock rate.
2750 The actual rate is often a function of a CPU core clock,
2751 and is normally less than that peak rate.
2752 For example, most ARM cores accept at most one sixth of the CPU clock.
2754 Speed 0 (khz) selects RTCK method.
2755 @xref{FAQ RTCK}.
2756 If your system uses RTCK, you won't need to change the
2757 JTAG clocking after setup.
2758 Not all interfaces, boards, or targets support ``rtck''.
2759 If the interface device can not
2760 support it, an error is returned when you try to use RTCK.
2761 @end deffn
2763 @defun jtag_rclk fallback_speed_kHz
2764 @cindex adaptive clocking
2765 @cindex RTCK
2766 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
2767 If that fails (maybe the interface, board, or target doesn't
2768 support it), falls back to the specified frequency.
2769 @example
2770 # Fall back to 3mhz if RTCK is not supported
2771 jtag_rclk 3000
2772 @end example
2773 @end defun
2775 @node Reset Configuration
2776 @chapter Reset Configuration
2777 @cindex Reset Configuration
2779 Every system configuration may require a different reset
2780 configuration. This can also be quite confusing.
2781 Resets also interact with @var{reset-init} event handlers,
2782 which do things like setting up clocks and DRAM, and
2783 JTAG clock rates. (@xref{JTAG Speed}.)
2784 They can also interact with JTAG routers.
2785 Please see the various board files for examples.
2787 @quotation Note
2788 To maintainers and integrators:
2789 Reset configuration touches several things at once.
2790 Normally the board configuration file
2791 should define it and assume that the JTAG adapter supports
2792 everything that's wired up to the board's JTAG connector.
2794 However, the target configuration file could also make note
2795 of something the silicon vendor has done inside the chip,
2796 which will be true for most (or all) boards using that chip.
2797 And when the JTAG adapter doesn't support everything, the
2798 user configuration file will need to override parts of
2799 the reset configuration provided by other files.
2800 @end quotation
2802 @section Types of Reset
2804 There are many kinds of reset possible through JTAG, but
2805 they may not all work with a given board and adapter.
2806 That's part of why reset configuration can be error prone.
2808 @itemize @bullet
2809 @item
2810 @emph{System Reset} ... the @emph{SRST} hardware signal
2811 resets all chips connected to the JTAG adapter, such as processors,
2812 power management chips, and I/O controllers. Normally resets triggered
2813 with this signal behave exactly like pressing a RESET button.
2814 @item
2815 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
2816 just the TAP controllers connected to the JTAG adapter.
2817 Such resets should not be visible to the rest of the system; resetting a
2818 device's TAP controller just puts that controller into a known state.
2819 @item
2820 @emph{Emulation Reset} ... many devices can be reset through JTAG
2821 commands. These resets are often distinguishable from system
2822 resets, either explicitly (a "reset reason" register says so)
2823 or implicitly (not all parts of the chip get reset).
2824 @item
2825 @emph{Other Resets} ... system-on-chip devices often support
2826 several other types of reset.
2827 You may need to arrange that a watchdog timer stops
2828 while debugging, preventing a watchdog reset.
2829 There may be individual module resets.
2830 @end itemize
2832 In the best case, OpenOCD can hold SRST, then reset
2833 the TAPs via TRST and send commands through JTAG to halt the
2834 CPU at the reset vector before the 1st instruction is executed.
2835 Then when it finally releases the SRST signal, the system is
2836 halted under debugger control before any code has executed.
2837 This is the behavior required to support the @command{reset halt}
2838 and @command{reset init} commands; after @command{reset init} a
2839 board-specific script might do things like setting up DRAM.
2840 (@xref{Reset Command}.)
2842 @anchor{SRST and TRST Issues}
2843 @section SRST and TRST Issues
2845 Because SRST and TRST are hardware signals, they can have a
2846 variety of system-specific constraints. Some of the most
2847 common issues are:
2849 @itemize @bullet
2851 @item @emph{Signal not available} ... Some boards don't wire
2852 SRST or TRST to the JTAG connector. Some JTAG adapters don't
2853 support such signals even if they are wired up.
2854 Use the @command{reset_config} @var{signals} options to say
2855 when either of those signals is not connected.
2856 When SRST is not available, your code might not be able to rely
2857 on controllers having been fully reset during code startup.
2858 Missing TRST is not a problem, since JTAG-level resets can
2859 be triggered using with TMS signaling.
2861 @item @emph{Signals shorted} ... Sometimes a chip, board, or
2862 adapter will connect SRST to TRST, instead of keeping them separate.
2863 Use the @command{reset_config} @var{combination} options to say
2864 when those signals aren't properly independent.
2866 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
2867 delay circuit, reset supervisor, or on-chip features can extend
2868 the effect of a JTAG adapter's reset for some time after the adapter
2869 stops issuing the reset. For example, there may be chip or board
2870 requirements that all reset pulses last for at least a
2871 certain amount of time; and reset buttons commonly have
2872 hardware debouncing.
2873 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
2874 commands to say when extra delays are needed.
2876 @item @emph{Drive type} ... Reset lines often have a pullup
2877 resistor, letting the JTAG interface treat them as open-drain
2878 signals. But that's not a requirement, so the adapter may need
2879 to use push/pull output drivers.
2880 Also, with weak pullups it may be advisable to drive
2881 signals to both levels (push/pull) to minimize rise times.
2882 Use the @command{reset_config} @var{trst_type} and
2883 @var{srst_type} parameters to say how to drive reset signals.
2885 @item @emph{Special initialization} ... Targets sometimes need
2886 special JTAG initialization sequences to handle chip-specific
2887 issues (not limited to errata).
2888 For example, certain JTAG commands might need to be issued while
2889 the system as a whole is in a reset state (SRST active)
2890 but the JTAG scan chain is usable (TRST inactive).
2891 Many systems treat combined assertion of SRST and TRST as a
2892 trigger for a harder reset than SRST alone.
2893 Such custom reset handling is discussed later in this chapter.
2894 @end itemize
2896 There can also be other issues.
2897 Some devices don't fully conform to the JTAG specifications.
2898 Trivial system-specific differences are common, such as
2899 SRST and TRST using slightly different names.
2900 There are also vendors who distribute key JTAG documentation for
2901 their chips only to developers who have signed a Non-Disclosure
2902 Agreement (NDA).
2904 Sometimes there are chip-specific extensions like a requirement to use
2905 the normally-optional TRST signal (precluding use of JTAG adapters which
2906 don't pass TRST through), or needing extra steps to complete a TAP reset.
2908 In short, SRST and especially TRST handling may be very finicky,
2909 needing to cope with both architecture and board specific constraints.
2911 @section Commands for Handling Resets
2913 @deffn {Command} adapter_nsrst_assert_width milliseconds
2914 Minimum amount of time (in milliseconds) OpenOCD should wait
2915 after asserting nSRST (active-low system reset) before
2916 allowing it to be deasserted.
2917 @end deffn
2919 @deffn {Command} adapter_nsrst_delay milliseconds
2920 How long (in milliseconds) OpenOCD should wait after deasserting
2921 nSRST (active-low system reset) before starting new JTAG operations.
2922 When a board has a reset button connected to SRST line it will
2923 probably have hardware debouncing, implying you should use this.
2924 @end deffn
2926 @deffn {Command} jtag_ntrst_assert_width milliseconds
2927 Minimum amount of time (in milliseconds) OpenOCD should wait
2928 after asserting nTRST (active-low JTAG TAP reset) before
2929 allowing it to be deasserted.
2930 @end deffn
2932 @deffn {Command} jtag_ntrst_delay milliseconds
2933 How long (in milliseconds) OpenOCD should wait after deasserting
2934 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
2935 @end deffn
2937 @deffn {Command} reset_config mode_flag ...
2938 This command displays or modifies the reset configuration
2939 of your combination of JTAG board and target in target
2940 configuration scripts.
2942 Information earlier in this section describes the kind of problems
2943 the command is intended to address (@pxref{SRST and TRST Issues}).
2944 As a rule this command belongs only in board config files,
2945 describing issues like @emph{board doesn't connect TRST};
2946 or in user config files, addressing limitations derived
2947 from a particular combination of interface and board.
2948 (An unlikely example would be using a TRST-only adapter
2949 with a board that only wires up SRST.)
2951 The @var{mode_flag} options can be specified in any order, but only one
2952 of each type -- @var{signals}, @var{combination},
2953 @var{gates},
2954 @var{trst_type},
2955 and @var{srst_type} -- may be specified at a time.
2956 If you don't provide a new value for a given type, its previous
2957 value (perhaps the default) is unchanged.
2958 For example, this means that you don't need to say anything at all about
2959 TRST just to declare that if the JTAG adapter should want to drive SRST,
2960 it must explicitly be driven high (@option{srst_push_pull}).
2962 @itemize
2963 @item
2964 @var{signals} can specify which of the reset signals are connected.
2965 For example, If the JTAG interface provides SRST, but the board doesn't
2966 connect that signal properly, then OpenOCD can't use it.
2967 Possible values are @option{none} (the default), @option{trst_only},
2968 @option{srst_only} and @option{trst_and_srst}.
2970 @quotation Tip
2971 If your board provides SRST and/or TRST through the JTAG connector,
2972 you must declare that so those signals can be used.
2973 @end quotation
2975 @item
2976 The @var{combination} is an optional value specifying broken reset
2977 signal implementations.
2978 The default behaviour if no option given is @option{separate},
2979 indicating everything behaves normally.
2980 @option{srst_pulls_trst} states that the
2981 test logic is reset together with the reset of the system (e.g. NXP
2982 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
2983 the system is reset together with the test logic (only hypothetical, I
2984 haven't seen hardware with such a bug, and can be worked around).
2985 @option{combined} implies both @option{srst_pulls_trst} and
2986 @option{trst_pulls_srst}.
2988 @item
2989 The @var{gates} tokens control flags that describe some cases where
2990 JTAG may be unvailable during reset.
2991 @option{srst_gates_jtag} (default)
2992 indicates that asserting SRST gates the
2993 JTAG clock. This means that no communication can happen on JTAG
2994 while SRST is asserted.
2995 Its converse is @option{srst_nogate}, indicating that JTAG commands
2996 can safely be issued while SRST is active.
2997 @end itemize
2999 The optional @var{trst_type} and @var{srst_type} parameters allow the
3000 driver mode of each reset line to be specified. These values only affect
3001 JTAG interfaces with support for different driver modes, like the Amontec
3002 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3003 relevant signal (TRST or SRST) is not connected.
3005 @itemize
3006 @item
3007 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3008 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3009 Most boards connect this signal to a pulldown, so the JTAG TAPs
3010 never leave reset unless they are hooked up to a JTAG adapter.
3012 @item
3013 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3014 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3015 Most boards connect this signal to a pullup, and allow the
3016 signal to be pulled low by various events including system
3017 powerup and pressing a reset button.
3018 @end itemize
3019 @end deffn
3021 @section Custom Reset Handling
3022 @cindex events
3024 OpenOCD has several ways to help support the various reset
3025 mechanisms provided by chip and board vendors.
3026 The commands shown in the previous section give standard parameters.
3027 There are also @emph{event handlers} associated with TAPs or Targets.
3028 Those handlers are Tcl procedures you can provide, which are invoked
3029 at particular points in the reset sequence.
3031 @emph{When SRST is not an option} you must set
3032 up a @code{reset-assert} event handler for your target.
3033 For example, some JTAG adapters don't include the SRST signal;
3034 and some boards have multiple targets, and you won't always
3035 want to reset everything at once.
3037 After configuring those mechanisms, you might still
3038 find your board doesn't start up or reset correctly.
3039 For example, maybe it needs a slightly different sequence
3040 of SRST and/or TRST manipulations, because of quirks that
3041 the @command{reset_config} mechanism doesn't address;
3042 or asserting both might trigger a stronger reset, which
3043 needs special attention.
3045 Experiment with lower level operations, such as @command{jtag_reset}
3046 and the @command{jtag arp_*} operations shown here,
3047 to find a sequence of operations that works.
3048 @xref{JTAG Commands}.
3049 When you find a working sequence, it can be used to override
3050 @command{jtag_init}, which fires during OpenOCD startup
3051 (@pxref{Configuration Stage});
3052 or @command{init_reset}, which fires during reset processing.
3054 You might also want to provide some project-specific reset
3055 schemes. For example, on a multi-target board the standard
3056 @command{reset} command would reset all targets, but you
3057 may need the ability to reset only one target at time and
3058 thus want to avoid using the board-wide SRST signal.
3060 @deffn {Overridable Procedure} init_reset mode
3061 This is invoked near the beginning of the @command{reset} command,
3062 usually to provide as much of a cold (power-up) reset as practical.
3063 By default it is also invoked from @command{jtag_init} if
3064 the scan chain does not respond to pure JTAG operations.
3065 The @var{mode} parameter is the parameter given to the
3066 low level reset command (@option{halt},
3067 @option{init}, or @option{run}), @option{setup},
3068 or potentially some other value.
3070 The default implementation just invokes @command{jtag arp_init-reset}.
3071 Replacements will normally build on low level JTAG
3072 operations such as @command{jtag_reset}.
3073 Operations here must not address individual TAPs
3074 (or their associated targets)
3075 until the JTAG scan chain has first been verified to work.
3077 Implementations must have verified the JTAG scan chain before
3078 they return.
3079 This is done by calling @command{jtag arp_init}
3080 (or @command{jtag arp_init-reset}).
3081 @end deffn
3083 @deffn Command {jtag arp_init}
3084 This validates the scan chain using just the four
3085 standard JTAG signals (TMS, TCK, TDI, TDO).
3086 It starts by issuing a JTAG-only reset.
3087 Then it performs checks to verify that the scan chain configuration
3088 matches the TAPs it can observe.
3089 Those checks include checking IDCODE values for each active TAP,
3090 and verifying the length of their instruction registers using
3091 TAP @code{-ircapture} and @code{-irmask} values.
3092 If these tests all pass, TAP @code{setup} events are
3093 issued to all TAPs with handlers for that event.
3094 @end deffn
3096 @deffn Command {jtag arp_init-reset}
3097 This uses TRST and SRST to try resetting
3098 everything on the JTAG scan chain
3099 (and anything else connected to SRST).
3100 It then invokes the logic of @command{jtag arp_init}.
3101 @end deffn
3104 @node TAP Declaration
3105 @chapter TAP Declaration
3106 @cindex TAP declaration
3107 @cindex TAP configuration
3109 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3110 TAPs serve many roles, including:
3112 @itemize @bullet
3113 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
3114 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
3115 Others do it indirectly, making a CPU do it.
3116 @item @b{Program Download} Using the same CPU support GDB uses,
3117 you can initialize a DRAM controller, download code to DRAM, and then
3118 start running that code.
3119 @item @b{Boundary Scan} Most chips support boundary scan, which
3120 helps test for board assembly problems like solder bridges
3121 and missing connections
3122 @end itemize
3124 OpenOCD must know about the active TAPs on your board(s).
3125 Setting up the TAPs is the core task of your configuration files.
3126 Once those TAPs are set up, you can pass their names to code
3127 which sets up CPUs and exports them as GDB targets,
3128 probes flash memory, performs low-level JTAG operations, and more.
3130 @section Scan Chains
3131 @cindex scan chain
3133 TAPs are part of a hardware @dfn{scan chain},
3134 which is daisy chain of TAPs.
3135 They also need to be added to
3136 OpenOCD's software mirror of that hardware list,
3137 giving each member a name and associating other data with it.
3138 Simple scan chains, with a single TAP, are common in
3139 systems with a single microcontroller or microprocessor.
3140 More complex chips may have several TAPs internally.
3141 Very complex scan chains might have a dozen or more TAPs:
3142 several in one chip, more in the next, and connecting
3143 to other boards with their own chips and TAPs.
3145 You can display the list with the @command{scan_chain} command.
3146 (Don't confuse this with the list displayed by the @command{targets}
3147 command, presented in the next chapter.
3148 That only displays TAPs for CPUs which are configured as
3149 debugging targets.)
3150 Here's what the scan chain might look like for a chip more than one TAP:
3152 @verbatim
3153 TapName Enabled IdCode Expected IrLen IrCap IrMask
3154 -- ------------------ ------- ---------- ---------- ----- ----- ------
3155 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3156 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3157 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3158 @end verbatim
3160 OpenOCD can detect some of that information, but not all
3161 of it. @xref{Autoprobing}.
3162 Unfortunately those TAPs can't always be autoconfigured,
3163 because not all devices provide good support for that.
3164 JTAG doesn't require supporting IDCODE instructions, and
3165 chips with JTAG routers may not link TAPs into the chain
3166 until they are told to do so.
3168 The configuration mechanism currently supported by OpenOCD
3169 requires explicit configuration of all TAP devices using
3170 @command{jtag newtap} commands, as detailed later in this chapter.
3171 A command like this would declare one tap and name it @code{chip1.cpu}:
3173 @example
3174 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3175 @end example
3177 Each target configuration file lists the TAPs provided
3178 by a given chip.
3179 Board configuration files combine all the targets on a board,
3180 and so forth.
3181 Note that @emph{the order in which TAPs are declared is very important.}
3182 It must match the order in the JTAG scan chain, both inside
3183 a single chip and between them.
3184 @xref{FAQ TAP Order}.
3186 For example, the ST Microsystems STR912 chip has
3187 three separate TAPs@footnote{See the ST
3188 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3189 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3190 @url{}}.
3191 To configure those taps, @file{target/str912.cfg}
3192 includes commands something like this:
3194 @example
3195 jtag newtap str912 flash ... params ...
3196 jtag newtap str912 cpu ... params ...
3197 jtag newtap str912 bs ... params ...
3198 @end example
3200 Actual config files use a variable instead of literals like
3201 @option{str912}, to support more than one chip of each type.
3202 @xref{Config File Guidelines}.
3204 @deffn Command {jtag names}
3205 Returns the names of all current TAPs in the scan chain.
3206 Use @command{jtag cget} or @command{jtag tapisenabled}
3207 to examine attributes and state of each TAP.
3208 @example
3209 foreach t [jtag names] @{
3210 puts [format "TAP: %s\n" $t]
3211 @}
3212 @end example
3213 @end deffn
3215 @deffn Command {scan_chain}
3216 Displays the TAPs in the scan chain configuration,
3217 and their status.
3218 The set of TAPs listed by this command is fixed by
3219 exiting the OpenOCD configuration stage,
3220 but systems with a JTAG router can
3221 enable or disable TAPs dynamically.
3222 @end deffn
3224 @c FIXME! "jtag cget" should be able to return all TAP
3225 @c attributes, like "$target_name cget" does for targets.
3227 @c Probably want "jtag eventlist", and a "tap-reset" event
3228 @c (on entry to RESET state).
3230 @section TAP Names
3231 @cindex dotted name
3233 When TAP objects are declared with @command{jtag newtap},
3234 a @dfn{} is created for the TAP, combining the
3235 name of a module (usually a chip) and a label for the TAP.
3236 For example: @code{xilinx.tap}, @code{str912.flash},
3237 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3238 Many other commands use that to manipulate or
3239 refer to the TAP. For example, CPU configuration uses the
3240 name, as does declaration of NAND or NOR flash banks.
3242 The components of a dotted name should follow ``C'' symbol
3243 name rules: start with an alphabetic character, then numbers
3244 and underscores are OK; while others (including dots!) are not.
3246 @quotation Tip
3247 In older code, JTAG TAPs were numbered from 0..N.
3248 This feature is still present.
3249 However its use is highly discouraged, and
3250 should not be relied on; it will be removed by mid-2010.
3251 Update all of your scripts to use TAP names rather than numbers,
3252 by paying attention to the runtime warnings they trigger.
3253 Using TAP numbers in target configuration scripts prevents
3254 reusing those scripts on boards with multiple targets.
3255 @end quotation
3257 @section TAP Declaration Commands
3259 @c shouldn't this be(come) a {Config Command}?
3260 @anchor{jtag newtap}
3261 @deffn Command {jtag newtap} chipname tapname configparams...
3262 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3263 and configured according to the various @var{configparams}.
3265 The @var{chipname} is a symbolic name for the chip.
3266 Conventionally target config files use @code{$_CHIPNAME},
3267 defaulting to the model name given by the chip vendor but
3268 overridable.
3270 @cindex TAP naming convention
3271 The @var{tapname} reflects the role of that TAP,
3272 and should follow this convention:
3274 @itemize @bullet
3275 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3276 @item @code{cpu} -- The main CPU of the chip, alternatively
3277 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3278 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3279 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3280 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3281 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3282 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3283 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3284 with a single TAP;
3285 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3286 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3287 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3288 a JTAG TAP; that TAP should be named @code{sdma}.
3289 @end itemize
3291 Every TAP requires at least the following @var{configparams}:
3293 @itemize @bullet
3294 @item @code{-irlen} @var{NUMBER}
3295 @*The length in bits of the
3296 instruction register, such as 4 or 5 bits.
3297 @end itemize
3299 A TAP may also provide optional @var{configparams}:
3301 @itemize @bullet
3302 @item @code{-disable} (or @code{-enable})
3303 @*Use the @code{-disable} parameter to flag a TAP which is not
3304 linked in to the scan chain after a reset using either TRST
3305 or the JTAG state machine's @sc{reset} state.
3306 You may use @code{-enable} to highlight the default state
3307 (the TAP is linked in).
3308 @xref{Enabling and Disabling TAPs}.
3309 @item @code{-expected-id} @var{number}
3310 @*A non-zero @var{number} represents a 32-bit IDCODE
3311 which you expect to find when the scan chain is examined.
3312 These codes are not required by all JTAG devices.
3313 @emph{Repeat the option} as many times as required if more than one
3314 ID code could appear (for example, multiple versions).
3315 Specify @var{number} as zero to suppress warnings about IDCODE
3316 values that were found but not included in the list.
3318 Provide this value if at all possible, since it lets OpenOCD
3319 tell when the scan chain it sees isn't right. These values
3320 are provided in vendors' chip documentation, usually a technical
3321 reference manual. Sometimes you may need to probe the JTAG
3322 hardware to find these values.
3323 @xref{Autoprobing}.
3324 @item @code{-ignore-version}
3325 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3326 option. When vendors put out multiple versions of a chip, or use the same
3327 JTAG-level ID for several largely-compatible chips, it may be more practical
3328 to ignore the version field than to update config files to handle all of
3329 the various chip IDs.
3330 @item @code{-ircapture} @var{NUMBER}
3331 @*The bit pattern loaded by the TAP into the JTAG shift register
3332 on entry to the @sc{ircapture} state, such as 0x01.
3333 JTAG requires the two LSBs of this value to be 01.
3334 By default, @code{-ircapture} and @code{-irmask} are set
3335 up to verify that two-bit value. You may provide
3336 additional bits, if you know them, or indicate that
3337 a TAP doesn't conform to the JTAG specification.
3338 @item @code{-irmask} @var{NUMBER}
3339 @*A mask used with @code{-ircapture}
3340 to verify that instruction scans work correctly.
3341 Such scans are not used by OpenOCD except to verify that
3342 there seems to be no problems with JTAG scan chain operations.
3343 @end itemize
3344 @end deffn
3346 @section Other TAP commands
3348 @deffn Command {jtag cget} @option{-event} name
3349 @deffnx Command {jtag configure} @option{-event} name string
3350 At this writing this TAP attribute
3351 mechanism is used only for event handling.
3352 (It is not a direct analogue of the @code{cget}/@code{configure}
3353 mechanism for debugger targets.)
3354 See the next section for information about the available events.
3356 The @code{configure} subcommand assigns an event handler,
3357 a TCL string which is evaluated when the event is triggered.
3358 The @code{cget} subcommand returns that handler.
3359 @end deffn
3361 @anchor{TAP Events}
3362 @section TAP Events
3363 @cindex events
3364 @cindex TAP events
3366 OpenOCD includes two event mechanisms.
3367 The one presented here applies to all JTAG TAPs.
3368 The other applies to debugger targets,
3369 which are associated with certain TAPs.
3371 The TAP events currently defined are:
3373 @itemize @bullet
3374 @item @b{post-reset}
3375 @* The TAP has just completed a JTAG reset.
3376 The tap may still be in the JTAG @sc{reset} state.
3377 Handlers for these events might perform initialization sequences
3378 such as issuing TCK cycles, TMS sequences to ensure
3379 exit from the ARM SWD mode, and more.
3381 Because the scan chain has not yet been verified, handlers for these events
3382 @emph{should not issue commands which scan the JTAG IR or DR registers}
3383 of any particular target.
3384 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3385 @item @b{setup}
3386 @* The scan chain has been reset and verified.
3387 This handler may enable TAPs as needed.
3388 @item @b{tap-disable}
3389 @* The TAP needs to be disabled. This handler should
3390 implement @command{jtag tapdisable}
3391 by issuing the relevant JTAG commands.
3392 @item @b{tap-enable}
3393 @* The TAP needs to be enabled. This handler should
3394 implement @command{jtag tapenable}
3395 by issuing the relevant JTAG commands.
3396 @end itemize
3398 If you need some action after each JTAG reset, which isn't actually
3399 specific to any TAP (since you can't yet trust the scan chain's
3400 contents to be accurate), you might:
3402 @example
3403 jtag configure CHIP.jrc -event post-reset @{
3404 echo "JTAG Reset done"
3405 ... non-scan jtag operations to be done after reset
3406 @}
3407 @end example
3410 @anchor{Enabling and Disabling TAPs}
3411 @section Enabling and Disabling TAPs
3412 @cindex JTAG Route Controller
3413 @cindex jrc
3415 In some systems, a @dfn{JTAG Route Controller} (JRC)
3416 is used to enable and/or disable specific JTAG TAPs.
3417 Many ARM based chips from Texas Instruments include
3418 an ``ICEpick'' module, which is a JRC.
3419 Such chips include DaVinci and OMAP3 processors.
3421 A given TAP may not be visible until the JRC has been
3422 told to link it into the scan chain; and if the JRC
3423 has been told to unlink that TAP, it will no longer
3424 be visible.
3425 Such routers address problems that JTAG ``bypass mode''
3426 ignores, such as:
3428 @itemize
3429 @item The scan chain can only go as fast as its slowest TAP.
3430 @item Having many TAPs slows instruction scans, since all
3431 TAPs receive new instructions.
3432 @item TAPs in the scan chain must be powered up, which wastes
3433 power and prevents debugging some power management mechanisms.
3434 @end itemize
3436 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3437 as implied by the existence of JTAG routers.
3438 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3439 does include a kind of JTAG router functionality.
3441 @c (a) currently the event handlers don't seem to be able to
3442 @c fail in a way that could lead to no-change-of-state.
3444 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3445 shown below, and is implemented using TAP event handlers.
3446 So for example, when defining a TAP for a CPU connected to
3447 a JTAG router, your @file{target.cfg} file
3448 should define TAP event handlers using
3449 code that looks something like this:
3451 @example
3452 jtag configure CHIP.cpu -event tap-enable @{
3453 ... jtag operations using CHIP.jrc
3454 @}
3455 jtag configure CHIP.cpu -event tap-disable @{
3456 ... jtag operations using CHIP.jrc
3457 @}
3458 @end example
3460 Then you might want that CPU's TAP enabled almost all the time:
3462 @example
3463 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3464 @end example
3466 Note how that particular setup event handler declaration
3467 uses quotes to evaluate @code{$CHIP} when the event is configured.
3468 Using brackets @{ @} would cause it to be evaluated later,
3469 at runtime, when it might have a different value.
3471 @deffn Command {jtag tapdisable}
3472 If necessary, disables the tap
3473 by sending it a @option{tap-disable} event.
3474 Returns the string "1" if the tap
3475 specified by @var{} is enabled,
3476 and "0" if it is disabled.
3477 @end deffn
3479 @deffn Command {jtag tapenable}
3480 If necessary, enables the tap
3481 by sending it a @option{tap-enable} event.
3482 Returns the string "1" if the tap
3483 specified by @var{} is enabled,
3484 and "0" if it is disabled.
3485 @end deffn
3487 @deffn Command {jtag tapisenabled}
3488 Returns the string "1" if the tap
3489 specified by @var{} is enabled,
3490 and "0" if it is disabled.
3492 @quotation Note
3493 Humans will find the @command{scan_chain} command more helpful
3494 for querying the state of the JTAG taps.
3495 @end quotation
3496 @end deffn
3498 @anchor{Autoprobing}
3499 @section Autoprobing
3500 @cindex autoprobe
3501 @cindex JTAG autoprobe
3503 TAP configuration is the first thing that needs to be done
3504 after interface and reset configuration. Sometimes it's
3505 hard finding out what TAPs exist, or how they are identified.
3506 Vendor documentation is not always easy to find and use.
3508 To help you get past such problems, OpenOCD has a limited
3509 @emph{autoprobing} ability to look at the scan chain, doing
3510 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3511 To use this mechanism, start the OpenOCD server with only data
3512 that configures your JTAG interface, and arranges to come up
3513 with a slow clock (many devices don't support fast JTAG clocks
3514 right when they come out of reset).
3516 For example, your @file{openocd.cfg} file might have:
3518 @example
3519 source [find interface/olimex-arm-usb-tiny-h.cfg]
3520 reset_config trst_and_srst
3521 jtag_rclk 8
3522 @end example
3524 When you start the server without any TAPs configured, it will
3525 attempt to autoconfigure the TAPs. There are two parts to this:
3527 @enumerate
3528 @item @emph{TAP discovery} ...
3529 After a JTAG reset (sometimes a system reset may be needed too),
3530 each TAP's data registers will hold the contents of either the
3531 IDCODE or BYPASS register.
3532 If JTAG communication is working, OpenOCD will see each TAP,
3533 and report what @option{-expected-id} to use with it.
3534 @item @emph{IR Length discovery} ...
3535 Unfortunately JTAG does not provide a reliable way to find out
3536 the value of the @option{-irlen} parameter to use with a TAP
3537 that is discovered.
3538 If OpenOCD can discover the length of a TAP's instruction
3539 register, it will report it.
3540 Otherwise you may need to consult vendor documentation, such
3541 as chip data sheets or BSDL files.
3542 @end enumerate
3544 In many cases your board will have a simple scan chain with just
3545 a single device. Here's what OpenOCD reported with one board
3546 that's a bit more complex:
3548 @example
3549 clock speed 8 kHz
3550 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3551 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3552 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3553 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3554 AUTO auto0.tap - use "... -irlen 4"
3555 AUTO auto1.tap - use "... -irlen 4"
3556 AUTO auto2.tap - use "... -irlen 6"
3557 no gdb ports allocated as no target has been specified
3558 @end example
3560 Given that information, you should be able to either find some existing
3561 config files to use, or create your own. If you create your own, you
3562 would configure from the bottom up: first a @file{target.cfg} file
3563 with these TAPs, any targets associated with them, and any on-chip
3564 resources; then a @file{board.cfg} with off-chip resources, clocking,
3565 and so forth.
3567 @node CPU Configuration
3568 @chapter CPU Configuration
3569 @cindex GDB target
3571 This chapter discusses how to set up GDB debug targets for CPUs.
3572 You can also access these targets without GDB
3573 (@pxref{Architecture and Core Commands},
3574 and @ref{Target State handling}) and
3575 through various kinds of NAND and NOR flash commands.
3576 If you have multiple CPUs you can have multiple such targets.
3578 We'll start by looking at how to examine the targets you have,
3579 then look at how to add one more target and how to configure it.
3581 @section Target List
3582 @cindex target, current
3583 @cindex target, list
3585 All targets that have been set up are part of a list,
3586 where each member has a name.
3587 That name should normally be the same as the TAP name.
3588 You can display the list with the @command{targets}
3589 (plural!) command.
3590 This display often has only one CPU; here's what it might
3591 look like with more than one:
3592 @verbatim
3593 TargetName Type Endian TapName State
3594 -- ------------------ ---------- ------ ------------------ ------------
3595 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
3596 1 MyTarget cortex_m3 little tap-disabled
3597 @end verbatim
3599 One member of that list is the @dfn{current target}, which
3600 is implicitly referenced by many commands.
3601 It's the one marked with a @code{*} near the target name.
3602 In particular, memory addresses often refer to the address
3603 space seen by that current target.
3604 Commands like @command{mdw} (memory display words)
3605 and @command{flash erase_address} (erase NOR flash blocks)
3606 are examples; and there are many more.
3608 Several commands let you examine the list of targets:
3610 @deffn Command {target count}
3611 @emph{Note: target numbers are deprecated; don't use them.
3612 They will be removed shortly after August 2010, including this command.
3613 Iterate target using @command{target names}, not by counting.}
3615 Returns the number of targets, @math{N}.
3616 The highest numbered target is @math{N - 1}.
3617 @example
3618 set c [target count]
3619 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
3620 # Assuming you have created this function
3621 print_target_details $x
3622 @}
3623 @end example
3624 @end deffn
3626 @deffn Command {target current}
3627 Returns the name of the current target.
3628 @end deffn
3630 @deffn Command {target names}
3631 Lists the names of all current targets in the list.
3632 @example
3633 foreach t [target names] @{
3634 puts [format "Target: %s\n" $t]
3635 @}
3636 @end example
3637 @end deffn
3639 @deffn Command {target number} number
3640 @emph{Note: target numbers are deprecated; don't use them.
3641 They will be removed shortly after August 2010, including this command.}
3643 The list of targets is numbered starting at zero.
3644 This command returns the name of the target at index @var{number}.
3645 @example
3646 set thename [target number $x]
3647 puts [format "Target %d is: %s\n" $x $thename]
3648 @end example
3649 @end deffn
3651 @c yep, "target list" would have been better.
3652 @c plus maybe "target setdefault".
3654 @deffn Command targets [name]
3655 @emph{Note: the name of this command is plural. Other target
3656 command names are singular.}
3658 With no parameter, this command displays a table of all known
3659 targets in a user friendly form.
3661 With a parameter, this command sets the current target to
3662 the given target with the given @var{name}; this is
3663 only relevant on boards which have more than one target.
3664 @end deffn
3666 @section Target CPU Types and Variants
3667 @cindex target type
3668 @cindex CPU type
3669 @cindex CPU variant
3671 Each target has a @dfn{CPU type}, as shown in the output of
3672 the @command{targets} command. You need to specify that type
3673 when calling @command{target create}.
3674 The CPU type indicates more than just the instruction set.
3675 It also indicates how that instruction set is implemented,
3676 what kind of debug support it integrates,
3677 whether it has an MMU (and if so, what kind),
3678 what core-specific commands may be available
3679 (@pxref{Architecture and Core Commands}),
3680 and more.
3682 For some CPU types, OpenOCD also defines @dfn{variants} which
3683 indicate differences that affect their handling.
3684 For example, a particular implementation bug might need to be
3685 worked around in some chip versions.
3687 It's easy to see what target types are supported,
3688 since there's a command to list them.
3689 However, there is currently no way to list what target variants
3690 are supported (other than by reading the OpenOCD source code).
3692 @anchor{target types}
3693 @deffn Command {target types}
3694 Lists all supported target types.
3695 At this writing, the supported CPU types and variants are:
3697 @itemize @bullet
3698 @item @code{arm11} -- this is a generation of ARMv6 cores
3699 @item @code{arm720t} -- this is an ARMv4 core with an MMU
3700 @item @code{arm7tdmi} -- this is an ARMv4 core
3701 @item @code{arm920t} -- this is an ARMv4 core with an MMU
3702 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
3703 @item @code{arm966e} -- this is an ARMv5 core
3704 @item @code{arm9tdmi} -- this is an ARMv4 core
3705 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
3706 (Support for this is preliminary and incomplete.)
3707 @item @code{cortex_a8} -- this is an ARMv7 core with an MMU
3708 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
3709 compact Thumb2 instruction set.
3710 @item @code{dragonite} -- resembles arm966e
3711 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
3712 (Support for this is still incomplete.)
3713 @item @code{fa526} -- resembles arm920 (w/o Thumb)
3714 @item @code{feroceon} -- resembles arm926
3715 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
3716 @item @code{xscale} -- this is actually an architecture,
3717 not a CPU type. It is based on the ARMv5 architecture.
3718 There are several variants defined:
3719 @itemize @minus
3720 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
3721 @code{pxa27x} ... instruction register length is 7 bits
3722 @item @code{pxa250}, @code{pxa255},
3723 @code{pxa26x} ... instruction register length is 5 bits
3724 @item @code{pxa3xx} ... instruction register length is 11 bits
3725 @end itemize
3726 @end itemize
3727 @end deffn
3729 To avoid being confused by the variety of ARM based cores, remember
3730 this key point: @emph{ARM is a technology licencing company}.
3731 (See: @url{}.)
3732 The CPU name used by OpenOCD will reflect the CPU design that was
3733 licenced, not a vendor brand which incorporates that design.
3734 Name prefixes like arm7, arm9, arm11, and cortex
3735 reflect design generations;
3736 while names like ARMv4, ARMv5, ARMv6, and ARMv7
3737 reflect an architecture version implemented by a CPU design.
3739 @anchor{Target Configuration}
3740 @section Target Configuration
3742 Before creating a ``target'', you must have added its TAP to the scan chain.
3743 When you've added that TAP, you will have a @code{}
3744 which is used to set up the CPU support.
3745 The chip-specific configuration file will normally configure its CPU(s)
3746 right after it adds all of the chip's TAPs to the scan chain.
3748 Although you can set up a target in one step, it's often clearer if you
3749 use shorter commands and do it in two steps: create it, then configure
3750 optional parts.
3751 All operations on the target after it's created will use a new
3752 command, created as part of target creation.
3754 The two main things to configure after target creation are
3755 a work area, which usually has target-specific defaults even
3756 if the board setup code overrides them later;
3757 and event handlers (@pxref{Target Events}), which tend
3758 to be much more board-specific.
3759 The key steps you use might look something like this
3761 @example
3762 target create MyTarget cortex_m3 -chain-position mychip.cpu
3763 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
3764 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
3765 $MyTarget configure -event reset-init @{ myboard_reinit @}
3766 @end example
3768 You should specify a working area if you can; typically it uses some
3769 on-chip SRAM.
3770 Such a working area can speed up many things, including bulk
3771 writes to target memory;
3772 flash operations like checking to see if memory needs to be erased;
3773 GDB memory checksumming;
3774 and more.
3776 @quotation Warning
3777 On more complex chips, the work area can become
3778 inaccessible when application code
3779 (such as an operating system)
3780 enables or disables the MMU.
3781 For example, the particular MMU context used to acess the virtual
3782 address will probably matter ... and that context might not have
3783 easy access to other addresses needed.
3784 At this writing, OpenOCD doesn't have much MMU intelligence.
3785 @end quotation
3787 It's often very useful to define a @code{reset-init} event handler.
3788 For systems that are normally used with a boot loader,
3789 common tasks include updating clocks and initializing memory
3790 controllers.
3791 That may be needed to let you write the boot loader into flash,
3792 in order to ``de-brick'' your board; or to load programs into
3793 external DDR memory without having run the boot loader.
3795 @deffn Command {target create} target_name type configparams...
3796 This command creates a GDB debug target that refers to a specific JTAG tap.
3797 It enters that target into a list, and creates a new
3798 command (@command{@var{target_name}}) which is used for various
3799 purposes including additional configuration.
3801 @itemize @bullet
3802 @item @var{target_name} ... is the name of the debug target.
3803 By convention this should be the same as the @emph{}
3804 of the TAP associated with this target, which must be specified here
3805 using the @code{-chain-position @var{}} configparam.
3807 This name is also used to create the target object command,
3808 referred to here as @command{$target_name},
3809 and in other places the target needs to be identified.
3810 @item @var{type} ... specifies the target type. @xref{target types}.
3811 @item @var{configparams} ... all parameters accepted by
3812 @command{$target_name configure} are permitted.
3813 If the target is big-endian, set it here with @code{-endian big}.
3814 If the variant matters, set it here with @code{-variant}.
3816 You @emph{must} set the @code{-chain-position @var{}} here.
3817 @end itemize
3818 @end deffn
3820 @deffn Command {$target_name configure} configparams...
3821 The options accepted by this command may also be
3822 specified as parameters to @command{target create}.
3823 Their values can later be queried one at a time by
3824 using the @command{$target_name cget} command.
3826 @emph{Warning:} changing some of these after setup is dangerous.
3827 For example, moving a target from one TAP to another;
3828 and changing its endianness or variant.
3830 @itemize @bullet
3832 @item @code{-chain-position} @var{} -- names the TAP
3833 used to access this target.
3835 @item @code{-endian} (@option{big}|@option{little}) -- specifies
3836 whether the CPU uses big or little endian conventions
3838 @item @code{-event} @var{event_name} @var{event_body} --
3839 @xref{Target Events}.
3840 Note that this updates a list of named event handlers.
3841 Calling this twice with two different event names assigns
3842 two different handlers, but calling it twice with the
3843 same event name assigns only one handler.
3845 @item @code{-variant} @var{name} -- specifies a variant of the target,
3846 which OpenOCD needs to know about.
3848 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
3849 whether the work area gets backed up; by default,
3850 @emph{it is not backed up.}
3851 When possible, use a working_area that doesn't need to be backed up,
3852 since performing a backup slows down operations.
3853 For example, the beginning of an SRAM block is likely to
3854 be used by most build systems, but the end is often unused.
3856 @item @code{-work-area-size} @var{size} -- specify work are size,
3857 in bytes. The same size applies regardless of whether its physical
3858 or virtual address is being used.
3860 @item @code{-work-area-phys} @var{address} -- set the work area
3861 base @var{address} to be used when no MMU is active.
3863 @item @code{-work-area-virt} @var{address} -- set the work area
3864 base @var{address} to be used when an MMU is active.
3865 @emph{Do not specify a value for this except on targets with an MMU.}
3866 The value should normally correspond to a static mapping for the
3867 @code{-work-area-phys} address, set up by the current operating system.
3869 @end itemize
3870 @end deffn
3872 @section Other $target_name Commands
3873 @cindex object command
3875 The Tcl/Tk language has the concept of object commands,
3876 and OpenOCD adopts that same model for targets.
3878 A good Tk example is a on screen button.
3879 Once a button is created a button
3880 has a name (a path in Tk terms) and that name is useable as a first
3881 class command. For example in Tk, one can create a button and later
3882 configure it like this:
3884 @example
3885 # Create
3886 button .foobar -background red -command @{ foo @}
3887 # Modify
3888 .foobar configure -foreground blue
3889 # Query
3890 set x [.foobar cget -background]
3891 # Report
3892 puts [format "The button is %s" $x]
3893 @end example
3895 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
3896 button, and its object commands are invoked the same way.
3898 @example
3899 str912.cpu mww 0x1234 0x42
3900 omap3530.cpu mww 0x5555 123
3901 @end example
3903 The commands supported by OpenOCD target objects are:
3905 @deffn Command {$target_name arp_examine}
3906 @deffnx Command {$target_name arp_halt}
3907 @deffnx Command {$target_name arp_poll}
3908 @deffnx Command {$target_name arp_reset}
3909 @deffnx Command {$target_name arp_waitstate}
3910 Internal OpenOCD scripts (most notably @file{startup.tcl})
3911 use these to deal with specific reset cases.
3912 They are not otherwise documented here.
3913 @end deffn
3915 @deffn Command {$target_name array2mem} arrayname width address count
3916 @deffnx Command {$target_name mem2array} arrayname width address count
3917 These provide an efficient script-oriented interface to memory.
3918 The @code{array2mem} primitive writes bytes, halfwords, or words;
3919 while @code{mem2array} reads them.
3920 In both cases, the TCL side uses an array, and
3921 the target side uses raw memory.
3923 The efficiency comes from enabling the use of
3924 bulk JTAG data transfer operations.
3925 The script orientation comes from working with data
3926 values that are packaged for use by TCL scripts;
3927 @command{mdw} type primitives only print data they retrieve,
3928 and neither store nor return those values.
3930 @itemize
3931 @item @var{arrayname} ... is the name of an array variable
3932 @item @var{width} ... is 8/16/32 - indicating the memory access size
3933 @item @var{address} ... is the target memory address
3934 @item @var{count} ... is the number of elements to process
3935 @end itemize
3936 @end deffn
3938 @deffn Command {$target_name cget} queryparm
3939 Each configuration parameter accepted by
3940 @command{$target_name configure}
3941 can be individually queried, to return its current value.
3942 The @var{queryparm} is a parameter name
3943 accepted by that command, such as @code{-work-area-phys}.
3944 There are a few special cases:
3946 @itemize @bullet
3947 @item @code{-event} @var{event_name} -- returns the handler for the
3948 event named @var{event_name}.
3949 This is a special case because setting a handler requires
3950 two parameters.
3951 @item @code{-type} -- returns the target type.
3952 This is a special case because this is set using
3953 @command{target create} and can't be changed
3954 using @command{$target_name configure}.
3955 @end itemize
3957 For example, if you wanted to summarize information about
3958 all the targets you might use something like this:
3960 @example
3961 foreach name [target names] @{
3962 set y [$name cget -endian]
3963 set z [$name cget -type]
3964 puts [format "Chip %d is %s, Endian: %s, type: %s" \
3965 $x $name $y $z]
3966 @}
3967 @end example
3968 @end deffn
3970 @anchor{target curstate}
3971 @deffn Command {$target_name curstate}
3972 Displays the current target state:
3973 @code{debug-running},
3974 @code{halted},
3975 @code{reset},
3976 @code{running}, or @code{unknown}.
3977 (Also, @pxref{Event Polling}.)
3978 @end deffn
3980 @deffn Command {$target_name eventlist}
3981 Displays a table listing all event handlers
3982 currently associated with this target.
3983 @xref{Target Events}.
3984 @end deffn
3986 @deffn Command {$target_name invoke-event} event_name
3987 Invokes the handler for the event named @var{event_name}.
3988 (This is primarily intended for use by OpenOCD framework
3989 code, for example by the reset code in @file{startup.tcl}.)
3990 @end deffn
3992 @deffn Command {$target_name mdw} addr [count]
3993 @deffnx Command {$target_name mdh} addr [count]
3994 @deffnx Command {$target_name mdb} addr [count]
3995 Display contents of address @var{addr}, as
3996 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
3997 or 8-bit bytes (@command{mdb}).
3998 If @var{count} is specified, displays that many units.
3999 (If you want to manipulate the data instead of displaying it,
4000 see the @code{mem2array} primitives.)
4001 @end deffn
4003 @deffn Command {$target_name mww} addr word
4004 @deffnx Command {$target_name mwh} addr halfword
4005 @deffnx Command {$target_name mwb} addr byte
4006 Writes the specified @var{word} (32 bits),
4007 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4008 at the specified address @var{addr}.
4009 @end deffn
4011 @anchor{Target Events}
4012 @section Target Events
4013 @cindex target events
4014 @cindex events
4015 At various times, certain things can happen, or you want them to happen.
4016 For example:
4017 @itemize @bullet
4018 @item What should happen when GDB connects? Should your target reset?
4019 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4020 @item Is using SRST appropriate (and possible) on your system?
4021 Or instead of that, do you need to issue JTAG commands to trigger reset?
4022 SRST usually resets everything on the scan chain, which can be inappropriate.
4023 @item During reset, do you need to write to certain memory locations
4024 to set up system clocks or
4025 to reconfigure the SDRAM?
4026 How about configuring the watchdog timer, or other peripherals,
4027 to stop running while you hold the core stopped for debugging?
4028 @end itemize
4030 All of the above items can be addressed by target event handlers.
4031 These are set up by @command{$target_name configure -event} or
4032 @command{target create ... -event}.
4034 The programmer's model matches the @code{-command} option used in Tcl/Tk
4035 buttons and events. The two examples below act the same, but one creates
4036 and invokes a small procedure while the other inlines it.
4038 @example
4039 proc my_attach_proc @{ @} @{
4040 echo "Reset..."
4041 reset halt
4042 @}
4043 mychip.cpu configure -event gdb-attach my_attach_proc
4044 mychip.cpu configure -event gdb-attach @{
4045 echo "Reset..."
4046 # To make flash probe and gdb load to flash work we need a reset init.
4047 reset init
4048 @}
4049 @end example
4051 The following target events are defined:
4053 @itemize @bullet
4054 @item @b{debug-halted}
4055 @* The target has halted for debug reasons (i.e.: breakpoint)
4056 @item @b{debug-resumed}
4057 @* The target has resumed (i.e.: gdb said run)
4058 @item @b{early-halted}
4059 @* Occurs early in the halt process
4060 @ignore
4061 @item @b{examine-end}
4062 @* Currently not used (goal: when JTAG examine completes)
4063 @item @b{examine-start}
4064 @* Currently not used (goal: when JTAG examine starts)
4065 @end ignore
4066 @item @b{gdb-attach}
4067 @* When GDB connects. This is before any communication with the target, so this
4068 can be used to set up the target so it is possible to probe flash. Probing flash
4069 is necessary during gdb connect if gdb load is to write the image to flash. Another
4070 use of the flash memory map is for GDB to automatically hardware/software breakpoints
4071 depending on whether the breakpoint is in RAM or read only memory.
4072 @item @b{gdb-detach}
4073 @* When GDB disconnects
4074 @item @b{gdb-end}
4075 @* When the target has halted and GDB is not doing anything (see early halt)
4076 @item @b{gdb-flash-erase-start}
4077 @* Before the GDB flash process tries to erase the flash
4078 @item @b{gdb-flash-erase-end}
4079 @* After the GDB flash process has finished erasing the flash
4080 @item @b{gdb-flash-write-start}
4081 @* Before GDB writes to the flash
4082 @item @b{gdb-flash-write-end}
4083 @* After GDB writes to the flash
4084 @item @b{gdb-start}
4085 @* Before the target steps, gdb is trying to start/resume the target
4086 @item @b{halted}
4087 @* The target has halted
4088 @ignore
4089 @item @b{old-gdb_program_config}
4090 @* DO NOT USE THIS: Used internally
4091 @item @b{old-pre_resume}
4092 @* DO NOT USE THIS: Used internally
4093 @end ignore
4094 @item @b{reset-assert-pre}
4095 @* Issued as part of @command{reset} processing
4096 after @command{reset_init} was triggered
4097 but before either SRST alone is re-asserted on the scan chain,
4098 or @code{reset-assert} is triggered.
4099 @item @b{reset-assert}
4100 @* Issued as part of @command{reset} processing
4101 after @command{reset-assert-pre} was triggered.
4102 When such a handler is present, cores which support this event will use
4103 it instead of asserting SRST.
4104 This support is essential for debugging with JTAG interfaces which
4105 don't include an SRST line (JTAG doesn't require SRST), and for
4106 selective reset on scan chains that have multiple targets.
4107 @item @b{reset-assert-post}
4108 @* Issued as part of @command{reset} processing
4109 after @code{reset-assert} has been triggered.
4110 or the target asserted SRST on the entire scan chain.
4111 @item @b{reset-deassert-pre}
4112 @* Issued as part of @command{reset} processing
4113 after @code{reset-assert-post} has been triggered.
4114 @item @b{reset-deassert-post}
4115 @* Issued as part of @command{reset} processing
4116 after @code{reset-deassert-pre} has been triggered
4117 and (if the target is using it) after SRST has been
4118 released on the scan chain.
4119 @item @b{reset-end}
4120 @* Issued as the final step in @command{reset} processing.
4121 @ignore
4122 @item @b{reset-halt-post}
4123 @* Currently not used
4124 @item @b{reset-halt-pre}
4125 @* Currently not used
4126 @end ignore
4127 @item @b{reset-init}
4128 @* Used by @b{reset init} command for board-specific initialization.
4129 This event fires after @emph{reset-deassert-post}.
4131 This is where you would configure PLLs and clocking, set up DRAM so
4132 you can download programs that don't fit in on-chip SRAM, set up pin
4133 multiplexing, and so on.
4134 (You may be able to switch to a fast JTAG clock rate here, after
4135 the target clocks are fully set up.)
4136 @item @b{reset-start}
4137 @* Issued as part of @command{reset} processing
4138 before @command{reset_init} is called.
4140 This is the most robust place to use @command{jtag_rclk}
4141 or @command{adapter_khz} to switch to a low JTAG clock rate,
4142 when reset disables PLLs needed to use a fast clock.
4143 @ignore
4144 @item @b{reset-wait-pos}
4145 @* Currently not used
4146 @item @b{reset-wait-pre}
4147 @* Currently not used
4148 @end ignore
4149 @item @b{resume-start}
4150 @* Before any target is resumed
4151 @item @b{resume-end}
4152 @* After all targets have resumed
4153 @item @b{resume-ok}
4154 @* Success
4155 @item @b{resumed}
4156 @* Target has resumed
4157 @end itemize
4160 @node Flash Commands
4161 @chapter Flash Commands
4163 OpenOCD has different commands for NOR and NAND flash;
4164 the ``flash'' command works with NOR flash, while
4165 the ``nand'' command works with NAND flash.
4166 This partially reflects different hardware technologies:
4167 NOR flash usually supports direct CPU instruction and data bus access,
4168 while data from a NAND flash must be copied to memory before it can be
4169 used. (SPI flash must also be copied to memory before use.)
4170 However, the documentation also uses ``flash'' as a generic term;
4171 for example, ``Put flash configuration in board-specific files''.
4173 Flash Steps:
4174 @enumerate
4175 @item Configure via the command @command{flash bank}
4176 @* Do this in a board-specific configuration file,
4177 passing parameters as needed by the driver.
4178 @item Operate on the flash via @command{flash subcommand}
4179 @* Often commands to manipulate the flash are typed by a human, or run
4180 via a script in some automated way. Common tasks include writing a
4181 boot loader, operating system, or other data.
4182 @item GDB Flashing
4183 @* Flashing via GDB requires the flash be configured via ``flash
4184 bank'', and the GDB flash features be enabled.
4185 @xref{GDB Configuration}.
4186 @end enumerate
4188 Many CPUs have the ablity to ``boot'' from the first flash bank.
4189 This means that misprogramming that bank can ``brick'' a system,
4190 so that it can't boot.