Remove obsolete tip referring to 2010 removal of TAP numbers.
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * NAND Flash Commands:: NAND Flash Commands
77 * PLD/FPGA Commands:: PLD/FPGA Commands
78 * General Commands:: General Commands
79 * Architecture and Core Commands:: Architecture and Core Commands
80 * JTAG Commands:: JTAG Commands
81 * Boundary Scan Commands:: Boundary Scan Commands
82 * Utility Commands:: Utility Commands
83 * TFTP:: TFTP
84 * GDB and OpenOCD:: Using GDB and OpenOCD
85 * Tcl Scripting API:: Tcl Scripting API
86 * FAQ:: Frequently Asked Questions
87 * Tcl Crash Course:: Tcl Crash Course
88 * License:: GNU Free Documentation License
90 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
91 @comment case issue with ``Index.html'' and ``index.html''
92 @comment Occurs when creating ``--html --no-split'' output
93 @comment This fix is based on:
94 * OpenOCD Concept Index:: Concept Index
95 * Command and Driver Index:: Command and Driver Index
96 @end menu
98 @node About
99 @unnumbered About
100 @cindex about
102 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
103 at the University of Applied Sciences Augsburg (@uref{}).
104 Since that time, the project has grown into an active open-source project,
105 supported by a diverse community of software and hardware developers from
106 around the world.
108 @section What is OpenOCD?
109 @cindex TAP
110 @cindex JTAG
112 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
113 in-system programming and boundary-scan testing for embedded target
114 devices.
116 It does so with the assistance of a @dfn{debug adapter}, which is
117 a small hardware module which helps provide the right kind of
118 electrical signaling to the target being debugged. These are
119 required since the debug host (on which OpenOCD runs) won't
120 usually have native support for such signaling, or the connector
121 needed to hook up to the target.
123 Such debug adapters support one or more @dfn{transport} protocols,
124 each of which involves different electrical signaling (and uses
125 different messaging protocols on top of that signaling). There
126 are many types of debug adapter, and little uniformity in what
127 they are called. (There are also product naming differences.)
129 These adapters are sometimes packaged as discrete dongles, which
130 may generically be called @dfn{hardware interface dongles}.
131 Some development boards also integrate them directly, which may
132 let the development board connect directly to the debug
133 host over USB (and sometimes also to power it over USB).
135 For example, a @dfn{JTAG Adapter} supports JTAG
136 signaling, and is used to communicate
137 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
138 A @dfn{TAP} is a ``Test Access Port'', a module which processes
139 special instructions and data. TAPs are daisy-chained within and
140 between chips and boards. JTAG supports debugging and boundary
141 scan operations.
143 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
144 signaling to communicate with some newer ARM cores, as well as debug
145 adapters which support both JTAG and SWD transports. SWD supports only
146 debugging, whereas JTAG also supports boundary scan operations.
148 For some chips, there are also @dfn{Programming Adapters} supporting
149 special transports used only to write code to flash memory, without
150 support for on-chip debugging or boundary scan.
151 (At this writing, OpenOCD does not support such non-debug adapters.)
154 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
155 USB-based, parallel port-based, and other standalone boxes that run
156 OpenOCD internally. @xref{Debug Adapter Hardware}.
158 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
159 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
160 Cortex-M3 (Stellaris LM3, ST STM32 and Energy Micro EFM32) based cores to be
161 debugged via the GDB protocol.
163 @b{Flash Programming:} Flash writing is supported for external
164 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
165 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
166 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
167 controllers (LPC3180, Orion, S3C24xx, more) is included.
169 @section OpenOCD Web Site
171 The OpenOCD web site provides the latest public news from the community:
173 @uref{}
175 @section Latest User's Guide:
177 The user's guide you are now reading may not be the latest one
178 available. A version for more recent code may be available.
179 Its HTML form is published regularly at:
181 @uref{}
183 PDF form is likewise published at:
185 @uref{}
187 @section OpenOCD User's Forum
189 There is an OpenOCD forum (phpBB) hosted by SparkFun,
190 which might be helpful to you. Note that if you want
191 anything to come to the attention of developers, you
192 should post it to the OpenOCD Developer Mailing List
193 instead of this forum.
195 @uref{}
197 @section OpenOCD User's Mailing List
199 The OpenOCD User Mailing List provides the primary means of
200 communication between users:
202 @uref{}
204 @section OpenOCD IRC
206 Support can also be found on irc:
207 @uref{irc://}
209 @node Developers
210 @chapter OpenOCD Developer Resources
211 @cindex developers
213 If you are interested in improving the state of OpenOCD's debugging and
214 testing support, new contributions will be welcome. Motivated developers
215 can produce new target, flash or interface drivers, improve the
216 documentation, as well as more conventional bug fixes and enhancements.
218 The resources in this chapter are available for developers wishing to explore
219 or expand the OpenOCD source code.
221 @section OpenOCD Git Repository
223 During the 0.3.x release cycle, OpenOCD switched from Subversion to
224 a Git repository hosted at SourceForge. The repository URL is:
226 @uref{git://}
228 or via http
230 @uref{}
232 You may prefer to use a mirror and the HTTP protocol:
234 @uref{}
236 With standard Git tools, use @command{git clone} to initialize
237 a local repository, and @command{git pull} to update it.
238 There are also gitweb pages letting you browse the repository
239 with a web browser, or download arbitrary snapshots without
240 needing a Git client:
242 @uref{}
244 The @file{README} file contains the instructions for building the project
245 from the repository or a snapshot.
247 Developers that want to contribute patches to the OpenOCD system are
248 @b{strongly} encouraged to work against mainline.
249 Patches created against older versions may require additional
250 work from their submitter in order to be updated for newer releases.
252 @section Doxygen Developer Manual
254 During the 0.2.x release cycle, the OpenOCD project began
255 providing a Doxygen reference manual. This document contains more
256 technical information about the software internals, development
257 processes, and similar documentation:
259 @uref{}
261 This document is a work-in-progress, but contributions would be welcome
262 to fill in the gaps. All of the source files are provided in-tree,
263 listed in the Doxyfile configuration at the top of the source tree.
265 @section OpenOCD Developer Mailing List
267 The OpenOCD Developer Mailing List provides the primary means of
268 communication between developers:
270 @uref{}
272 Discuss and submit patches to this list.
273 The @file{HACKING} file contains basic information about how
274 to prepare patches.
276 @section OpenOCD Bug Database
278 During the 0.4.x release cycle the OpenOCD project team began
279 using Trac for its bug database:
281 @uref{}
284 @node Debug Adapter Hardware
285 @chapter Debug Adapter Hardware
286 @cindex dongles
287 @cindex FTDI
288 @cindex wiggler
289 @cindex zy1000
290 @cindex printer port
291 @cindex USB Adapter
292 @cindex RTCK
294 Defined: @b{dongle}: A small device that plugs into a computer and serves as
295 an adapter .... [snip]
297 In the OpenOCD case, this generally refers to @b{a small adapter} that
298 attaches to your computer via USB or the parallel port. One
299 exception is the Ultimate Solutions ZY1000, packaged as a small box you
300 attach via an ethernet cable. The ZY1000 has the advantage that it does not
301 require any drivers to be installed on the developer PC. It also has
302 a built in web interface. It supports RTCK/RCLK or adaptive clocking
303 and has a built-in relay to power cycle targets remotely.
306 @section Choosing a Dongle
308 There are several things you should keep in mind when choosing a dongle.
310 @enumerate
311 @item @b{Transport} Does it support the kind of communication that you need?
312 OpenOCD focusses mostly on JTAG. Your version may also support
313 other ways to communicate with target devices.
314 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
315 Does your dongle support it? You might need a level converter.
316 @item @b{Pinout} What pinout does your target board use?
317 Does your dongle support it? You may be able to use jumper
318 wires, or an "octopus" connector, to convert pinouts.
319 @item @b{Connection} Does your computer have the USB, parallel, or
320 Ethernet port needed?
321 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
322 RTCK support (also known as ``adaptive clocking'')?
323 @end enumerate
325 @section Stand-alone JTAG Probe
327 The ZY1000 from Ultimate Solutions is technically not a dongle but a
328 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
329 running on the developer's host computer.
330 Once installed on a network using DHCP or a static IP assignment, users can
331 access the ZY1000 probe locally or remotely from any host with access to the
332 IP address assigned to the probe.
333 The ZY1000 provides an intuitive web interface with direct access to the
334 OpenOCD debugger.
335 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
336 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
337 the target.
338 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
339 to power cycle the target remotely.
341 For more information, visit:
343 @b{ZY1000} See: @url{}
345 @section USB FT2232 Based
347 There are many USB JTAG dongles on the market, many of them based
348 on a chip from ``Future Technology Devices International'' (FTDI)
349 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
350 See: @url{} for more information.
351 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
352 chips started to become available in JTAG adapters. Around 2012, a new
353 variant appeared - FT232H - this is a single-channel version of FT2232H.
354 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
355 clocking.)
357 The FT2232 chips are flexible enough to support some other
358 transport options, such as SWD or the SPI variants used to
359 program some chips. They have two communications channels,
360 and one can be used for a UART adapter at the same time the
361 other one is used to provide a debug adapter.
363 Also, some development boards integrate an FT2232 chip to serve as
364 a built-in low-cost debug adapter and USB-to-serial solution.
366 @itemize @bullet
367 @item @b{usbjtag}
368 @* Link @url{}
369 @item @b{jtagkey}
370 @* See: @url{}
371 @item @b{jtagkey2}
372 @* See: @url{}
373 @item @b{oocdlink}
374 @* See: @url{} By Joern Kaipf
375 @item @b{signalyzer}
376 @* See: @url{}
377 @item @b{Stellaris Eval Boards}
378 @* See: @url{} - The Stellaris eval boards
379 bundle FT2232-based JTAG and SWD support, which can be used to debug
380 the Stellaris chips. Using separate JTAG adapters is optional.
381 These boards can also be used in a "pass through" mode as JTAG adapters
382 to other target boards, disabling the Stellaris chip.
383 @item @b{TI/Luminary ICDI}
384 @* See: @url{} - TI/Luminary In-Circuit Debug
385 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
386 Evaluation Kits. Like the non-detachable FT2232 support on the other
387 Stellaris eval boards, they can be used to debug other target boards.
388 @item @b{olimex-jtag}
389 @* See: @url{}
390 @item @b{Flyswatter/Flyswatter2}
391 @* See: @url{}
392 @item @b{turtelizer2}
393 @* See:
394 @uref{, Turtelizer 2}, or
395 @url{}
396 @item @b{comstick}
397 @* Link: @url{}
398 @item @b{stm32stick}
399 @* Link @url{}
400 @item @b{axm0432_jtag}
401 @* Axiom AXM-0432 Link @url{} - NOTE: This JTAG does not appear
402 to be available anymore as of April 2012.
403 @item @b{cortino}
404 @* Link @url{}
405 @item @b{dlp-usb1232h}
406 @* Link @url{}
407 @item @b{digilent-hs1}
408 @* Link @url{}
409 @item @b{opendous}
410 @* Link @url{} FT2232H-based
411 (OpenHardware).
412 @item @b{JTAG-lock-pick Tiny 2}
413 @* Link @url{} FT232H-based
415 @item @b{GW16042}
416 @* Link: @url{}
417 FT2232H-based
419 @end itemize
420 @section USB-JTAG / Altera USB-Blaster compatibles
422 These devices also show up as FTDI devices, but are not
423 protocol-compatible with the FT2232 devices. They are, however,
424 protocol-compatible among themselves. USB-JTAG devices typically consist
425 of a FT245 followed by a CPLD that understands a particular protocol,
426 or emulates this protocol using some other hardware.
428 They may appear under different USB VID/PID depending on the particular
429 product. The driver can be configured to search for any VID/PID pair
430 (see the section on driver commands).
432 @itemize
433 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
434 @* Link: @url{}
435 @item @b{Altera USB-Blaster}
436 @* Link: @url{}
437 @end itemize
439 @section USB JLINK based
440 There are several OEM versions of the Segger @b{JLINK} adapter. It is
441 an example of a micro controller based JTAG adapter, it uses an
442 AT91SAM764 internally.
444 @itemize @bullet
445 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
446 @* Link: @url{}
447 @item @b{SEGGER JLINK}
448 @* Link: @url{}
449 @item @b{IAR J-Link}
450 @* Link: @url{}
451 @end itemize
453 @section USB RLINK based
454 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
455 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
456 SWD and not JTAG, thus not supported.
458 @itemize @bullet
459 @item @b{Raisonance RLink}
460 @* Link: @url{}
461 @item @b{STM32 Primer}
462 @* Link: @url{}
463 @item @b{STM32 Primer2}
464 @* Link: @url{}
465 @end itemize
467 @section USB ST-LINK based
468 ST Micro has an adapter called @b{ST-LINK}.
469 They only work with ST Micro chips, notably STM32 and STM8.
471 @itemize @bullet
472 @item @b{ST-LINK}
473 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
474 @* Link: @url{}
475 @item @b{ST-LINK/V2}
476 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
477 @* Link: @url{}
478 @end itemize
480 For info the original ST-LINK enumerates using the mass storage usb class; however,
481 its implementation is completely broken. The result is this causes issues under Linux.
482 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
483 @itemize @bullet
484 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
485 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
486 @end itemize
488 @section USB TI/Stellaris ICDI based
489 Texas Instruments has an adapter called @b{ICDI}.
490 It is not to be confused with the FTDI based adapters that were originally fitted to their
491 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
493 @section USB CMSIS-DAP based
494 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
495 debuggers to ARM Cortex based targets @url{}.
497 @section USB Other
498 @itemize @bullet
499 @item @b{USBprog}
500 @* Link: @url{} - which uses an Atmel MEGA32 and a UBN9604
502 @item @b{USB - Presto}
503 @* Link: @url{}
505 @item @b{Versaloon-Link}
506 @* Link: @url{}
508 @item @b{ARM-JTAG-EW}
509 @* Link: @url{}
511 @item @b{Buspirate}
512 @* Link: @url{}
514 @item @b{opendous}
515 @* Link: @url{} - which uses an AT90USB162
517 @item @b{estick}
518 @* Link: @url{}
520 @item @b{Keil ULINK v1}
521 @* Link: @url{}
522 @end itemize
524 @section IBM PC Parallel Printer Port Based
526 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
527 and the Macraigor Wiggler. There are many clones and variations of
528 these on the market.
530 Note that parallel ports are becoming much less common, so if you
531 have the choice you should probably avoid these adapters in favor
532 of USB-based ones.
534 @itemize @bullet
536 @item @b{Wiggler} - There are many clones of this.
537 @* Link: @url{}
539 @item @b{DLC5} - From XILINX - There are many clones of this
540 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
541 produced, PDF schematics are easily found and it is easy to make.
543 @item @b{Amontec - JTAG Accelerator}
544 @* Link: @url{}
546 @item @b{Wiggler2}
547 @* Link: @url{}
549 @item @b{Wiggler_ntrst_inverted}
550 @* Yet another variation - See the source code, src/jtag/parport.c
552 @item @b{old_amt_wiggler}
553 @* Unknown - probably not on the market today
555 @item @b{arm-jtag}
556 @* Link: Most likely @url{} [another wiggler clone]
558 @item @b{chameleon}
559 @* Link: @url{}
561 @item @b{Triton}
562 @* Unknown.
564 @item @b{Lattice}
565 @* ispDownload from Lattice Semiconductor
566 @url{}
568 @item @b{flashlink}
569 @* From ST Microsystems;
570 @* Link: @url{}
572 @end itemize
574 @section Other...
575 @itemize @bullet
577 @item @b{ep93xx}
578 @* An EP93xx based Linux machine using the GPIO pins directly.
580 @item @b{at91rm9200}
581 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
583 @item @b{bcm2835gpio}
584 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
586 @item @b{jtag_vpi}
587 @* A JTAG driver acting as a client for the JTAG VPI server interface.
588 @* Link: @url{}
590 @end itemize
592 @node About Jim-Tcl
593 @chapter About Jim-Tcl
594 @cindex Jim-Tcl
595 @cindex tcl
597 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
598 This programming language provides a simple and extensible
599 command interpreter.
601 All commands presented in this Guide are extensions to Jim-Tcl.
602 You can use them as simple commands, without needing to learn
603 much of anything about Tcl.
604 Alternatively, you can write Tcl programs with them.
606 You can learn more about Jim at its website, @url{}.
607 There is an active and responsive community, get on the mailing list
608 if you have any questions. Jim-Tcl maintainers also lurk on the
609 OpenOCD mailing list.
611 @itemize @bullet
612 @item @b{Jim vs. Tcl}
613 @* Jim-Tcl is a stripped down version of the well known Tcl language,
614 which can be found here: @url{}. Jim-Tcl has far
615 fewer features. Jim-Tcl is several dozens of .C files and .H files and
616 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
617 4.2 MB .zip file containing 1540 files.
619 @item @b{Missing Features}
620 @* Our practice has been: Add/clone the real Tcl feature if/when
621 needed. We welcome Jim-Tcl improvements, not bloat. Also there
622 are a large number of optional Jim-Tcl features that are not
623 enabled in OpenOCD.
625 @item @b{Scripts}
626 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
627 command interpreter today is a mixture of (newer)
628 Jim-Tcl commands, and the (older) original command interpreter.
630 @item @b{Commands}
631 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
632 can type a Tcl for() loop, set variables, etc.
633 Some of the commands documented in this guide are implemented
634 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
636 @item @b{Historical Note}
637 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
638 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
639 as a Git submodule, which greatly simplified upgrading Jim-Tcl
640 to benefit from new features and bugfixes in Jim-Tcl.
642 @item @b{Need a crash course in Tcl?}
643 @*@xref{Tcl Crash Course}.
644 @end itemize
646 @node Running
647 @chapter Running
648 @cindex command line options
649 @cindex logfile
650 @cindex directory search
652 Properly installing OpenOCD sets up your operating system to grant it access
653 to the debug adapters. On Linux, this usually involves installing a file
654 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
655 complex and confusing driver configuration for every peripheral. Such issues
656 are unique to each operating system, and are not detailed in this User's Guide.
658 Then later you will invoke the OpenOCD server, with various options to
659 tell it how each debug session should work.
660 The @option{--help} option shows:
661 @verbatim
662 bash$ openocd --help
664 --help | -h display this help
665 --version | -v display OpenOCD version
666 --file | -f use configuration file <name>
667 --search | -s dir to search for config files and scripts
668 --debug | -d set debug level <0-3>
669 --log_output | -l redirect log output to file <name>
670 --command | -c run <command>
671 @end verbatim
673 If you don't give any @option{-f} or @option{-c} options,
674 OpenOCD tries to read the configuration file @file{openocd.cfg}.
675 To specify one or more different
676 configuration files, use @option{-f} options. For example:
678 @example
679 openocd -f config1.cfg -f config2.cfg -f config3.cfg
680 @end example
682 Configuration files and scripts are searched for in
683 @enumerate
684 @item the current directory,
685 @item any search dir specified on the command line using the @option{-s} option,
686 @item any search dir specified using the @command{add_script_search_dir} command,
687 @item @file{$HOME/.openocd} (not on Windows),
688 @item the site wide script library @file{$pkgdatadir/site} and
689 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
690 @end enumerate
691 The first found file with a matching file name will be used.
693 @quotation Note
694 Don't try to use configuration script names or paths which
695 include the "#" character. That character begins Tcl comments.
696 @end quotation
698 @section Simple setup, no customization
700 In the best case, you can use two scripts from one of the script
701 libraries, hook up your JTAG adapter, and start the server ... and
702 your JTAG setup will just work "out of the box". Always try to
703 start by reusing those scripts, but assume you'll need more
704 customization even if this works. @xref{OpenOCD Project Setup}.
706 If you find a script for your JTAG adapter, and for your board or
707 target, you may be able to hook up your JTAG adapter then start
708 the server with some variation of one of the following:
710 @example
711 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
712 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
713 @end example
715 You might also need to configure which reset signals are present,
716 using @option{-c 'reset_config trst_and_srst'} or something similar.
717 If all goes well you'll see output something like
719 @example
720 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
721 For bug reports, read
723 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
724 (mfg: 0x23b, part: 0xba00, ver: 0x3)
725 @end example
727 Seeing that "tap/device found" message, and no warnings, means
728 the JTAG communication is working. That's a key milestone, but
729 you'll probably need more project-specific setup.
731 @section What OpenOCD does as it starts
733 OpenOCD starts by processing the configuration commands provided
734 on the command line or, if there were no @option{-c command} or
735 @option{-f file.cfg} options given, in @file{openocd.cfg}.
736 @xref{configurationstage,,Configuration Stage}.
737 At the end of the configuration stage it verifies the JTAG scan
738 chain defined using those commands; your configuration should
739 ensure that this always succeeds.
740 Normally, OpenOCD then starts running as a daemon.
741 Alternatively, commands may be used to terminate the configuration
742 stage early, perform work (such as updating some flash memory),
743 and then shut down without acting as a daemon.
745 Once OpenOCD starts running as a daemon, it waits for connections from
746 clients (Telnet, GDB, Other) and processes the commands issued through
747 those channels.
749 If you are having problems, you can enable internal debug messages via
750 the @option{-d} option.
752 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
753 @option{-c} command line switch.
755 To enable debug output (when reporting problems or working on OpenOCD
756 itself), use the @option{-d} command line switch. This sets the
757 @option{debug_level} to "3", outputting the most information,
758 including debug messages. The default setting is "2", outputting only
759 informational messages, warnings and errors. You can also change this
760 setting from within a telnet or gdb session using @command{debug_level<n>}
761 (@pxref{debuglevel,,debug_level}).
763 You can redirect all output from the daemon to a file using the
764 @option{-l <logfile>} switch.
766 Note! OpenOCD will launch the GDB & telnet server even if it can not
767 establish a connection with the target. In general, it is possible for
768 the JTAG controller to be unresponsive until the target is set up
769 correctly via e.g. GDB monitor commands in a GDB init script.
771 @node OpenOCD Project Setup
772 @chapter OpenOCD Project Setup
774 To use OpenOCD with your development projects, you need to do more than
775 just connect the JTAG adapter hardware (dongle) to your development board
776 and start the OpenOCD server.
777 You also need to configure your OpenOCD server so that it knows
778 about your adapter and board, and helps your work.
779 You may also want to connect OpenOCD to GDB, possibly
780 using Eclipse or some other GUI.
782 @section Hooking up the JTAG Adapter
784 Today's most common case is a dongle with a JTAG cable on one side
785 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
786 and a USB cable on the other.
787 Instead of USB, some cables use Ethernet;
788 older ones may use a PC parallel port, or even a serial port.
790 @enumerate
791 @item @emph{Start with power to your target board turned off},
792 and nothing connected to your JTAG adapter.
793 If you're particularly paranoid, unplug power to the board.
794 It's important to have the ground signal properly set up,
795 unless you are using a JTAG adapter which provides
796 galvanic isolation between the target board and the
797 debugging host.
799 @item @emph{Be sure it's the right kind of JTAG connector.}
800 If your dongle has a 20-pin ARM connector, you need some kind
801 of adapter (or octopus, see below) to hook it up to
802 boards using 14-pin or 10-pin connectors ... or to 20-pin
803 connectors which don't use ARM's pinout.
805 In the same vein, make sure the voltage levels are compatible.
806 Not all JTAG adapters have the level shifters needed to work
807 with 1.2 Volt boards.
809 @item @emph{Be certain the cable is properly oriented} or you might
810 damage your board. In most cases there are only two possible
811 ways to connect the cable.
812 Connect the JTAG cable from your adapter to the board.
813 Be sure it's firmly connected.
815 In the best case, the connector is keyed to physically
816 prevent you from inserting it wrong.
817 This is most often done using a slot on the board's male connector
818 housing, which must match a key on the JTAG cable's female connector.
819 If there's no housing, then you must look carefully and
820 make sure pin 1 on the cable hooks up to pin 1 on the board.
821 Ribbon cables are frequently all grey except for a wire on one
822 edge, which is red. The red wire is pin 1.
824 Sometimes dongles provide cables where one end is an ``octopus'' of
825 color coded single-wire connectors, instead of a connector block.
826 These are great when converting from one JTAG pinout to another,
827 but are tedious to set up.
828 Use these with connector pinout diagrams to help you match up the
829 adapter signals to the right board pins.
831 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
832 A USB, parallel, or serial port connector will go to the host which
833 you are using to run OpenOCD.
834 For Ethernet, consult the documentation and your network administrator.
836 For USB-based JTAG adapters you have an easy sanity check at this point:
837 does the host operating system see the JTAG adapter? If you're running
838 Linux, try the @command{lsusb} command. If that host is an
839 MS-Windows host, you'll need to install a driver before OpenOCD works.
841 @item @emph{Connect the adapter's power supply, if needed.}
842 This step is primarily for non-USB adapters,
843 but sometimes USB adapters need extra power.
845 @item @emph{Power up the target board.}
846 Unless you just let the magic smoke escape,
847 you're now ready to set up the OpenOCD server
848 so you can use JTAG to work with that board.
850 @end enumerate
852 Talk with the OpenOCD server using
853 telnet (@code{telnet localhost 4444} on many systems) or GDB.
854 @xref{GDB and OpenOCD}.
856 @section Project Directory
858 There are many ways you can configure OpenOCD and start it up.
860 A simple way to organize them all involves keeping a
861 single directory for your work with a given board.
862 When you start OpenOCD from that directory,
863 it searches there first for configuration files, scripts,
864 files accessed through semihosting,
865 and for code you upload to the target board.
866 It is also the natural place to write files,
867 such as log files and data you download from the board.
869 @section Configuration Basics
871 There are two basic ways of configuring OpenOCD, and
872 a variety of ways you can mix them.
873 Think of the difference as just being how you start the server:
875 @itemize
876 @item Many @option{-f file} or @option{-c command} options on the command line
877 @item No options, but a @dfn{user config file}
878 in the current directory named @file{openocd.cfg}
879 @end itemize
881 Here is an example @file{openocd.cfg} file for a setup
882 using a Signalyzer FT2232-based JTAG adapter to talk to
883 a board with an Atmel AT91SAM7X256 microcontroller:
885 @example
886 source [find interface/signalyzer.cfg]
888 # GDB can also flash my flash!
889 gdb_memory_map enable
890 gdb_flash_program enable
892 source [find target/sam7x256.cfg]
893 @end example
895 Here is the command line equivalent of that configuration:
897 @example
898 openocd -f interface/signalyzer.cfg \
899 -c "gdb_memory_map enable" \
900 -c "gdb_flash_program enable" \
901 -f target/sam7x256.cfg
902 @end example
904 You could wrap such long command lines in shell scripts,
905 each supporting a different development task.
906 One might re-flash the board with a specific firmware version.
907 Another might set up a particular debugging or run-time environment.
909 @quotation Important
910 At this writing (October 2009) the command line method has
911 problems with how it treats variables.
912 For example, after @option{-c "set VAR value"}, or doing the
913 same in a script, the variable @var{VAR} will have no value
914 that can be tested in a later script.
915 @end quotation
917 Here we will focus on the simpler solution: one user config
918 file, including basic configuration plus any TCL procedures
919 to simplify your work.
921 @section User Config Files
922 @cindex config file, user
923 @cindex user config file
924 @cindex config file, overview
926 A user configuration file ties together all the parts of a project
927 in one place.
928 One of the following will match your situation best:
930 @itemize
931 @item Ideally almost everything comes from configuration files
932 provided by someone else.
933 For example, OpenOCD distributes a @file{scripts} directory
934 (probably in @file{/usr/share/openocd/scripts} on Linux).
935 Board and tool vendors can provide these too, as can individual
936 user sites; the @option{-s} command line option lets you say
937 where to find these files. (@xref{Running}.)
938 The AT91SAM7X256 example above works this way.
940 Three main types of non-user configuration file each have their
941 own subdirectory in the @file{scripts} directory:
943 @enumerate
944 @item @b{interface} -- one for each different debug adapter;
945 @item @b{board} -- one for each different board
946 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
947 @end enumerate
949 Best case: include just two files, and they handle everything else.
950 The first is an interface config file.
951 The second is board-specific, and it sets up the JTAG TAPs and
952 their GDB targets (by deferring to some @file{target.cfg} file),
953 declares all flash memory, and leaves you nothing to do except
954 meet your deadline:
956 @example
957 source [find interface/olimex-jtag-tiny.cfg]
958 source [find board/csb337.cfg]
959 @end example
961 Boards with a single microcontroller often won't need more
962 than the target config file, as in the AT91SAM7X256 example.
963 That's because there is no external memory (flash, DDR RAM), and
964 the board differences are encapsulated by application code.
966 @item Maybe you don't know yet what your board looks like to JTAG.
967 Once you know the @file{interface.cfg} file to use, you may
968 need help from OpenOCD to discover what's on the board.
969 Once you find the JTAG TAPs, you can just search for appropriate
970 target and board
971 configuration files ... or write your own, from the bottom up.
972 @xref{autoprobing,,Autoprobing}.
974 @item You can often reuse some standard config files but
975 need to write a few new ones, probably a @file{board.cfg} file.
976 You will be using commands described later in this User's Guide,
977 and working with the guidelines in the next chapter.
979 For example, there may be configuration files for your JTAG adapter
980 and target chip, but you need a new board-specific config file
981 giving access to your particular flash chips.
982 Or you might need to write another target chip configuration file
983 for a new chip built around the Cortex M3 core.
985 @quotation Note
986 When you write new configuration files, please submit
987 them for inclusion in the next OpenOCD release.
988 For example, a @file{board/newboard.cfg} file will help the
989 next users of that board, and a @file{target/newcpu.cfg}
990 will help support users of any board using that chip.
991 @end quotation
993 @item
994 You may may need to write some C code.
995 It may be as simple as supporting a new FT2232 or parport
996 based adapter; a bit more involved, like a NAND or NOR flash
997 controller driver; or a big piece of work like supporting
998 a new chip architecture.
999 @end itemize
1001 Reuse the existing config files when you can.
1002 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1003 You may find a board configuration that's a good example to follow.
1005 When you write config files, separate the reusable parts
1006 (things every user of that interface, chip, or board needs)
1007 from ones specific to your environment and debugging approach.
1008 @itemize
1010 @item
1011 For example, a @code{gdb-attach} event handler that invokes
1012 the @command{reset init} command will interfere with debugging
1013 early boot code, which performs some of the same actions
1014 that the @code{reset-init} event handler does.
1016 @item
1017 Likewise, the @command{arm9 vector_catch} command (or
1018 @cindex vector_catch
1019 its siblings @command{xscale vector_catch}
1020 and @command{cortex_m vector_catch}) can be a timesaver
1021 during some debug sessions, but don't make everyone use that either.
1022 Keep those kinds of debugging aids in your user config file,
1023 along with messaging and tracing setup.
1024 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1026 @item
1027 You might need to override some defaults.
1028 For example, you might need to move, shrink, or back up the target's
1029 work area if your application needs much SRAM.
1031 @item
1032 TCP/IP port configuration is another example of something which
1033 is environment-specific, and should only appear in
1034 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1035 @end itemize
1037 @section Project-Specific Utilities
1039 A few project-specific utility
1040 routines may well speed up your work.
1041 Write them, and keep them in your project's user config file.
1043 For example, if you are making a boot loader work on a
1044 board, it's nice to be able to debug the ``after it's
1045 loaded to RAM'' parts separately from the finicky early
1046 code which sets up the DDR RAM controller and clocks.
1047 A script like this one, or a more GDB-aware sibling,
1048 may help:
1050 @example
1051 proc ramboot @{ @} @{
1052 # Reset, running the target's "reset-init" scripts
1053 # to initialize clocks and the DDR RAM controller.
1054 # Leave the CPU halted.
1055 reset init
1057 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1058 load_image u-boot.bin 0x20000000
1060 # Start running.
1061 resume 0x20000000
1062 @}
1063 @end example
1065 Then once that code is working you will need to make it
1066 boot from NOR flash; a different utility would help.
1067 Alternatively, some developers write to flash using GDB.
1068 (You might use a similar script if you're working with a flash
1069 based microcontroller application instead of a boot loader.)
1071 @example
1072 proc newboot @{ @} @{
1073 # Reset, leaving the CPU halted. The "reset-init" event
1074 # proc gives faster access to the CPU and to NOR flash;
1075 # "reset halt" would be slower.
1076 reset init
1078 # Write standard version of U-Boot into the first two
1079 # sectors of NOR flash ... the standard version should
1080 # do the same lowlevel init as "reset-init".
1081 flash protect 0 0 1 off
1082 flash erase_sector 0 0 1
1083 flash write_bank 0 u-boot.bin 0x0
1084 flash protect 0 0 1 on
1086 # Reboot from scratch using that new boot loader.
1087 reset run
1088 @}
1089 @end example
1091 You may need more complicated utility procedures when booting
1092 from NAND.
1093 That often involves an extra bootloader stage,
1094 running from on-chip SRAM to perform DDR RAM setup so it can load
1095 the main bootloader code (which won't fit into that SRAM).
1097 Other helper scripts might be used to write production system images,
1098 involving considerably more than just a three stage bootloader.
1100 @section Target Software Changes
1102 Sometimes you may want to make some small changes to the software
1103 you're developing, to help make JTAG debugging work better.
1104 For example, in C or assembly language code you might
1105 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1106 handling issues like:
1108 @itemize @bullet
1110 @item @b{Watchdog Timers}...
1111 Watchog timers are typically used to automatically reset systems if
1112 some application task doesn't periodically reset the timer. (The
1113 assumption is that the system has locked up if the task can't run.)
1114 When a JTAG debugger halts the system, that task won't be able to run
1115 and reset the timer ... potentially causing resets in the middle of
1116 your debug sessions.
1118 It's rarely a good idea to disable such watchdogs, since their usage
1119 needs to be debugged just like all other parts of your firmware.
1120 That might however be your only option.
1122 Look instead for chip-specific ways to stop the watchdog from counting
1123 while the system is in a debug halt state. It may be simplest to set
1124 that non-counting mode in your debugger startup scripts. You may however
1125 need a different approach when, for example, a motor could be physically
1126 damaged by firmware remaining inactive in a debug halt state. That might
1127 involve a type of firmware mode where that "non-counting" mode is disabled
1128 at the beginning then re-enabled at the end; a watchdog reset might fire
1129 and complicate the debug session, but hardware (or people) would be
1130 protected.@footnote{Note that many systems support a "monitor mode" debug
1131 that is a somewhat cleaner way to address such issues. You can think of
1132 it as only halting part of the system, maybe just one task,
1133 instead of the whole thing.
1134 At this writing, January 2010, OpenOCD based debugging does not support
1135 monitor mode debug, only "halt mode" debug.}
1137 @item @b{ARM Semihosting}...
1138 @cindex ARM semihosting
1139 When linked with a special runtime library provided with many
1140 toolchains@footnote{See chapter 8 "Semihosting" in
1141 @uref{,
1142 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1143 The CodeSourcery EABI toolchain also includes a semihosting library.},
1144 your target code can use I/O facilities on the debug host. That library
1145 provides a small set of system calls which are handled by OpenOCD.
1146 It can let the debugger provide your system console and a file system,
1147 helping with early debugging or providing a more capable environment
1148 for sometimes-complex tasks like installing system firmware onto
1149 NAND or SPI flash.
1151 @item @b{ARM Wait-For-Interrupt}...
1152 Many ARM chips synchronize the JTAG clock using the core clock.
1153 Low power states which stop that core clock thus prevent JTAG access.
1154 Idle loops in tasking environments often enter those low power states
1155 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1157 You may want to @emph{disable that instruction} in source code,
1158 or otherwise prevent using that state,
1159 to ensure you can get JTAG access at any time.@footnote{As a more
1160 polite alternative, some processors have special debug-oriented
1161 registers which can be used to change various features including
1162 how the low power states are clocked while debugging.
1163 The STM32 DBGMCU_CR register is an example; at the cost of extra
1164 power consumption, JTAG can be used during low power states.}
1165 For example, the OpenOCD @command{halt} command may not
1166 work for an idle processor otherwise.
1168 @item @b{Delay after reset}...
1169 Not all chips have good support for debugger access
1170 right after reset; many LPC2xxx chips have issues here.
1171 Similarly, applications that reconfigure pins used for
1172 JTAG access as they start will also block debugger access.
1174 To work with boards like this, @emph{enable a short delay loop}
1175 the first thing after reset, before "real" startup activities.
1176 For example, one second's delay is usually more than enough
1177 time for a JTAG debugger to attach, so that
1178 early code execution can be debugged
1179 or firmware can be replaced.
1181 @item @b{Debug Communications Channel (DCC)}...
1182 Some processors include mechanisms to send messages over JTAG.
1183 Many ARM cores support these, as do some cores from other vendors.
1184 (OpenOCD may be able to use this DCC internally, speeding up some
1185 operations like writing to memory.)
1187 Your application may want to deliver various debugging messages
1188 over JTAG, by @emph{linking with a small library of code}
1189 provided with OpenOCD and using the utilities there to send
1190 various kinds of message.
1191 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1193 @end itemize
1195 @section Target Hardware Setup
1197 Chip vendors often provide software development boards which
1198 are highly configurable, so that they can support all options
1199 that product boards may require. @emph{Make sure that any
1200 jumpers or switches match the system configuration you are
1201 working with.}
1203 Common issues include:
1205 @itemize @bullet
1207 @item @b{JTAG setup} ...
1208 Boards may support more than one JTAG configuration.
1209 Examples include jumpers controlling pullups versus pulldowns
1210 on the nTRST and/or nSRST signals, and choice of connectors
1211 (e.g. which of two headers on the base board,
1212 or one from a daughtercard).
1213 For some Texas Instruments boards, you may need to jumper the
1214 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1216 @item @b{Boot Modes} ...
1217 Complex chips often support multiple boot modes, controlled
1218 by external jumpers. Make sure this is set up correctly.
1219 For example many i.MX boards from NXP need to be jumpered
1220 to "ATX mode" to start booting using the on-chip ROM, when
1221 using second stage bootloader code stored in a NAND flash chip.
1223 Such explicit configuration is common, and not limited to
1224 booting from NAND. You might also need to set jumpers to
1225 start booting using code loaded from an MMC/SD card; external
1226 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1227 flash; some external host; or various other sources.
1230 @item @b{Memory Addressing} ...
1231 Boards which support multiple boot modes may also have jumpers
1232 to configure memory addressing. One board, for example, jumpers
1233 external chipselect 0 (used for booting) to address either
1234 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1235 or NAND flash. When it's jumpered to address NAND flash, that
1236 board must also be told to start booting from on-chip ROM.
1238 Your @file{board.cfg} file may also need to be told this jumper
1239 configuration, so that it can know whether to declare NOR flash
1240 using @command{flash bank} or instead declare NAND flash with
1241 @command{nand device}; and likewise which probe to perform in
1242 its @code{reset-init} handler.
1244 A closely related issue is bus width. Jumpers might need to
1245 distinguish between 8 bit or 16 bit bus access for the flash
1246 used to start booting.
1248 @item @b{Peripheral Access} ...
1249 Development boards generally provide access to every peripheral
1250 on the chip, sometimes in multiple modes (such as by providing
1251 multiple audio codec chips).
1252 This interacts with software
1253 configuration of pin multiplexing, where for example a
1254 given pin may be routed either to the MMC/SD controller
1255 or the GPIO controller. It also often interacts with
1256 configuration jumpers. One jumper may be used to route
1257 signals to an MMC/SD card slot or an expansion bus (which
1258 might in turn affect booting); others might control which
1259 audio or video codecs are used.
1261 @end itemize
1263 Plus you should of course have @code{reset-init} event handlers
1264 which set up the hardware to match that jumper configuration.
1265 That includes in particular any oscillator or PLL used to clock
1266 the CPU, and any memory controllers needed to access external
1267 memory and peripherals. Without such handlers, you won't be
1268 able to access those resources without working target firmware
1269 which can do that setup ... this can be awkward when you're
1270 trying to debug that target firmware. Even if there's a ROM
1271 bootloader which handles a few issues, it rarely provides full
1272 access to all board-specific capabilities.
1275 @node Config File Guidelines
1276 @chapter Config File Guidelines
1278 This chapter is aimed at any user who needs to write a config file,
1279 including developers and integrators of OpenOCD and any user who
1280 needs to get a new board working smoothly.
1281 It provides guidelines for creating those files.
1283 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1284 with files including the ones listed here.
1285 Use them as-is where you can; or as models for new files.
1286 @itemize @bullet
1287 @item @file{interface} ...
1288 These are for debug adapters.
1289 Files that configure JTAG adapters go here.
1290 @example
1291 $ ls interface -R
1292 interface/:
1293 altera-usb-blaster.cfg hilscher_nxhx50_re.cfg openocd-usb-hs.cfg
1294 arm-jtag-ew.cfg hitex_str9-comstick.cfg openrd.cfg
1295 at91rm9200.cfg icebear.cfg osbdm.cfg
1296 axm0432.cfg jlink.cfg parport.cfg
1297 busblaster.cfg jtagkey2.cfg parport_dlc5.cfg
1298 buspirate.cfg jtagkey2p.cfg redbee-econotag.cfg
1299 calao-usb-a9260-c01.cfg jtagkey.cfg redbee-usb.cfg
1300 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg rlink.cfg
1301 calao-usb-a9260.cfg jtag-lock-pick_tiny_2.cfg sheevaplug.cfg
1302 chameleon.cfg kt-link.cfg signalyzer.cfg
1303 cortino.cfg lisa-l.cfg signalyzer-h2.cfg
1304 digilent-hs1.cfg luminary.cfg signalyzer-h4.cfg
1305 dlp-usb1232h.cfg luminary-icdi.cfg signalyzer-lite.cfg
1306 dummy.cfg luminary-lm3s811.cfg stlink-v1.cfg
1307 estick.cfg minimodule.cfg stlink-v2.cfg
1308 flashlink.cfg neodb.cfg stm32-stick.cfg
1309 flossjtag.cfg ngxtech.cfg sysfsgpio-raspberrypi.cfg
1310 flossjtag-noeeprom.cfg olimex-arm-usb-ocd.cfg ti-icdi.cfg
1311 flyswatter2.cfg olimex-arm-usb-ocd-h.cfg turtelizer2.cfg
1312 flyswatter.cfg olimex-arm-usb-tiny-h.cfg ulink.cfg
1313 ftdi olimex-jtag-tiny.cfg usb-jtag.cfg
1314 hilscher_nxhx10_etm.cfg oocdlink.cfg usbprog.cfg
1315 hilscher_nxhx500_etm.cfg opendous.cfg vpaclink.cfg
1316 hilscher_nxhx500_re.cfg opendous_ftdi.cfg vsllink.cfg
1317 hilscher_nxhx50_etm.cfg openocd-usb.cfg xds100v2.cfg
1319 interface/ftdi:
1320 axm0432.cfg hitex_str9-comstick.cfg olimex-jtag-tiny.cfg
1321 calao-usb-a9260-c01.cfg icebear.cfg oocdlink.cfg
1322 calao-usb-a9260-c02.cfg jtagkey2.cfg opendous_ftdi.cfg
1323 cortino.cfg jtagkey2p.cfg openocd-usb.cfg
1324 dlp-usb1232h.cfg jtagkey.cfg openocd-usb-hs.cfg
1325 dp_busblaster.cfg jtag-lock-pick_tiny_2.cfg openrd.cfg
1326 flossjtag.cfg kt-link.cfg redbee-econotag.cfg
1327 flossjtag-noeeprom.cfg lisa-l.cfg redbee-usb.cfg
1328 flyswatter2.cfg luminary.cfg sheevaplug.cfg
1329 flyswatter.cfg luminary-icdi.cfg signalyzer.cfg
1330 gw16042.cfg luminary-lm3s811.cfg signalyzer-lite.cfg
1331 hilscher_nxhx10_etm.cfg minimodule.cfg stm32-stick.cfg
1332 hilscher_nxhx500_etm.cfg neodb.cfg turtelizer2-revB.cfg
1333 hilscher_nxhx500_re.cfg ngxtech.cfg turtelizer2-revC.cfg
1334 hilscher_nxhx50_etm.cfg olimex-arm-usb-ocd.cfg vpaclink.cfg
1335 hilscher_nxhx50_re.cfg olimex-arm-usb-ocd-h.cfg xds100v2.cfg
1336 hitex_lpc1768stick.cfg olimex-arm-usb-tiny-h.cfg
1337 $
1338 @end example
1339 @item @file{board} ...
1340 think Circuit Board, PWA, PCB, they go by many names. Board files
1341 contain initialization items that are specific to a board.
1342 They reuse target configuration files, since the same
1343 microprocessor chips are used on many boards,
1344 but support for external parts varies widely. For
1345 example, the SDRAM initialization sequence for the board, or the type
1346 of external flash and what address it uses. Any initialization
1347 sequence to enable that external flash or SDRAM should be found in the
1348 board file. Boards may also contain multiple targets: two CPUs; or
1349 a CPU and an FPGA.
1350 @example
1351 $ ls board
1352 actux3.cfg lpc1850_spifi_generic.cfg
1353 am3517evm.cfg lpc4350_spifi_generic.cfg
1354 arm_evaluator7t.cfg lubbock.cfg
1355 at91cap7a-stk-sdram.cfg mcb1700.cfg
1356 at91eb40a.cfg microchip_explorer16.cfg
1357 at91rm9200-dk.cfg mini2440.cfg
1358 at91rm9200-ek.cfg mini6410.cfg
1359 at91sam9261-ek.cfg netgear-dg834v3.cfg
1360 at91sam9263-ek.cfg olimex_LPC2378STK.cfg
1361 at91sam9g20-ek.cfg olimex_lpc_h2148.cfg
1362 atmel_at91sam7s-ek.cfg olimex_sam7_ex256.cfg
1363 atmel_at91sam9260-ek.cfg olimex_sam9_l9260.cfg
1364 atmel_at91sam9rl-ek.cfg olimex_stm32_h103.cfg
1365 atmel_sam3n_ek.cfg olimex_stm32_h107.cfg
1366 atmel_sam3s_ek.cfg olimex_stm32_p107.cfg
1367 atmel_sam3u_ek.cfg omap2420_h4.cfg
1368 atmel_sam3x_ek.cfg open-bldc.cfg
1369 atmel_sam4s_ek.cfg openrd.cfg
1370 balloon3-cpu.cfg osk5912.cfg
1371 colibri.cfg phone_se_j100i.cfg
1372 crossbow_tech_imote2.cfg phytec_lpc3250.cfg
1373 csb337.cfg pic-p32mx.cfg
1374 csb732.cfg propox_mmnet1001.cfg
1375 da850evm.cfg pxa255_sst.cfg
1376 digi_connectcore_wi-9c.cfg redbee.cfg
1377 diolan_lpc4350-db1.cfg rsc-w910.cfg
1378 dm355evm.cfg sheevaplug.cfg
1379 dm365evm.cfg smdk6410.cfg
1380 dm6446evm.cfg spear300evb.cfg
1381 efikamx.cfg spear300evb_mod.cfg
1382 eir.cfg spear310evb20.cfg
1383 ek-lm3s1968.cfg spear310evb20_mod.cfg
1384 ek-lm3s3748.cfg spear320cpu.cfg
1385 ek-lm3s6965.cfg spear320cpu_mod.cfg
1386 ek-lm3s811.cfg steval_pcc010.cfg
1387 ek-lm3s811-revb.cfg stm320518_eval_stlink.cfg
1388 ek-lm3s8962.cfg stm32100b_eval.cfg
1389 ek-lm3s9b9x.cfg stm3210b_eval.cfg
1390 ek-lm3s9d92.cfg stm3210c_eval.cfg
1391 ek-lm4f120xl.cfg stm3210e_eval.cfg
1392 ek-lm4f232.cfg stm3220g_eval.cfg
1393 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1394 ethernut3.cfg stm3241g_eval.cfg
1395 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1396 hammer.cfg stm32f0discovery.cfg
1397 hilscher_nxdb500sys.cfg stm32f3discovery.cfg
1398 hilscher_nxeb500hmi.cfg stm32f4discovery.cfg
1399 hilscher_nxhx10.cfg stm32ldiscovery.cfg
1400 hilscher_nxhx500.cfg stm32vldiscovery.cfg
1401 hilscher_nxhx50.cfg str910-eval.cfg
1402 hilscher_nxsb100.cfg telo.cfg
1403 hitex_lpc1768stick.cfg ti_am335xevm.cfg
1404 hitex_lpc2929.cfg ti_beagleboard.cfg
1405 hitex_stm32-performancestick.cfg ti_beagleboard_xm.cfg
1406 hitex_str9-comstick.cfg ti_beaglebone.cfg
1407 iar_lpc1768.cfg ti_blaze.cfg
1408 iar_str912_sk.cfg ti_pandaboard.cfg
1409 icnova_imx53_sodimm.cfg ti_pandaboard_es.cfg
1410 icnova_sam9g45_sodimm.cfg topas910.cfg
1411 imx27ads.cfg topasa900.cfg
1412 imx27lnst.cfg twr-k60f120m.cfg
1413 imx28evk.cfg twr-k60n512.cfg
1414 imx31pdk.cfg tx25_stk5.cfg
1415 imx35pdk.cfg tx27_stk5.cfg
1416 imx53loco.cfg unknown_at91sam9260.cfg
1417 keil_mcb1700.cfg uptech_2410.cfg
1418 keil_mcb2140.cfg verdex.cfg
1419 kwikstik.cfg voipac.cfg
1420 linksys_nslu2.cfg voltcraft_dso-3062c.cfg
1421 lisa-l.cfg x300t.cfg
1422 logicpd_imx27.cfg zy1000.cfg
1423 $
1424 @end example
1425 @item @file{target} ...
1426 think chip. The ``target'' directory represents the JTAG TAPs
1427 on a chip
1428 which OpenOCD should control, not a board. Two common types of targets
1429 are ARM chips and FPGA or CPLD chips.
1430 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1431 the target config file defines all of them.
1432 @example
1433 $ ls target
1434 aduc702x.cfg lpc1763.cfg
1435 am335x.cfg lpc1764.cfg
1436 amdm37x.cfg lpc1765.cfg
1437 ar71xx.cfg lpc1766.cfg
1438 at32ap7000.cfg lpc1767.cfg
1439 at91r40008.cfg lpc1768.cfg
1440 at91rm9200.cfg lpc1769.cfg
1441 at91sam3ax_4x.cfg lpc1788.cfg
1442 at91sam3ax_8x.cfg lpc17xx.cfg
1443 at91sam3ax_xx.cfg lpc1850.cfg
1444 at91sam3nXX.cfg lpc2103.cfg
1445 at91sam3sXX.cfg lpc2124.cfg
1446 at91sam3u1c.cfg lpc2129.cfg
1447 at91sam3u1e.cfg lpc2148.cfg
1448 at91sam3u2c.cfg lpc2294.cfg
1449 at91sam3u2e.cfg lpc2378.cfg
1450 at91sam3u4c.cfg lpc2460.cfg
1451 at91sam3u4e.cfg lpc2478.cfg
1452 at91sam3uxx.cfg lpc2900.cfg
1453 at91sam3XXX.cfg lpc2xxx.cfg
1454 at91sam4sd32x.cfg lpc3131.cfg
1455 at91sam4sXX.cfg lpc3250.cfg
1456 at91sam4XXX.cfg lpc4350.cfg
1457 at91sam7se512.cfg lpc4350.cfg.orig
1458 at91sam7sx.cfg mc13224v.cfg
1459 at91sam7x256.cfg nuc910.cfg
1460 at91sam7x512.cfg omap2420.cfg
1461 at91sam9260.cfg omap3530.cfg
1462 at91sam9260_ext_RAM_ext_flash.cfg omap4430.cfg
1463 at91sam9261.cfg omap4460.cfg
1464 at91sam9263.cfg omap5912.cfg
1465 at91sam9.cfg omapl138.cfg
1466 at91sam9g10.cfg pic32mx.cfg
1467 at91sam9g20.cfg pxa255.cfg
1468 at91sam9g45.cfg pxa270.cfg
1469 at91sam9rl.cfg pxa3xx.cfg
1470 atmega128.cfg readme.txt
1471 avr32.cfg samsung_s3c2410.cfg
1472 c100.cfg samsung_s3c2440.cfg
1473 c100config.tcl samsung_s3c2450.cfg
1474 c100helper.tcl samsung_s3c4510.cfg
1475 c100regs.tcl samsung_s3c6410.cfg
1476 cs351x.cfg sharp_lh79532.cfg
1477 davinci.cfg smp8634.cfg
1478 dragonite.cfg spear3xx.cfg
1479 dsp56321.cfg stellaris.cfg
1480 dsp568013.cfg stellaris_icdi.cfg
1481 dsp568037.cfg stm32f0x_stlink.cfg
1482 efm32_stlink.cfg stm32f1x.cfg
1483 epc9301.cfg stm32f1x_stlink.cfg
1484 faux.cfg stm32f2x.cfg
1485 feroceon.cfg stm32f2x_stlink.cfg
1486 fm3.cfg stm32f3x.cfg
1487 hilscher_netx10.cfg stm32f3x_stlink.cfg
1488 hilscher_netx500.cfg stm32f4x.cfg
1489 hilscher_netx50.cfg stm32f4x_stlink.cfg
1490 icepick.cfg stm32l.cfg
1491 imx21.cfg stm32lx_dual_bank.cfg
1492 imx25.cfg stm32lx_stlink.cfg
1493 imx27.cfg stm32_stlink.cfg
1494 imx28.cfg stm32w108_stlink.cfg
1495 imx31.cfg stm32xl.cfg
1496 imx35.cfg str710.cfg
1497 imx51.cfg str730.cfg
1498 imx53.cfg str750.cfg
1499 imx6.cfg str912.cfg
1500 imx.cfg swj-dp.tcl
1501 is5114.cfg test_reset_syntax_error.cfg
1502 ixp42x.cfg test_syntax_error.cfg
1503 k40.cfg ti-ar7.cfg
1504 k60.cfg ti_calypso.cfg
1505 lpc1751.cfg ti_dm355.cfg
1506 lpc1752.cfg ti_dm365.cfg
1507 lpc1754.cfg ti_dm6446.cfg
1508 lpc1756.cfg tmpa900.cfg
1509 lpc1758.cfg tmpa910.cfg
1510 lpc1759.cfg u8500.cfg
1511 @end example
1512 @item @emph{more} ... browse for other library files which may be useful.
1513 For example, there are various generic and CPU-specific utilities.
1514 @end itemize
1516 The @file{openocd.cfg} user config
1517 file may override features in any of the above files by
1518 setting variables before sourcing the target file, or by adding
1519 commands specific to their situation.
1521 @section Interface Config Files
1523 The user config file
1524 should be able to source one of these files with a command like this:
1526 @example
1527 source [find interface/FOOBAR.cfg]
1528 @end example
1530 A preconfigured interface file should exist for every debug adapter
1531 in use today with OpenOCD.
1532 That said, perhaps some of these config files
1533 have only been used by the developer who created it.
1535 A separate chapter gives information about how to set these up.
1536 @xref{Debug Adapter Configuration}.
1537 Read the OpenOCD source code (and Developer's Guide)
1538 if you have a new kind of hardware interface
1539 and need to provide a driver for it.
1541 @section Board Config Files
1542 @cindex config file, board
1543 @cindex board config file
1545 The user config file
1546 should be able to source one of these files with a command like this:
1548 @example
1549 source [find board/FOOBAR.cfg]
1550 @end example
1552 The point of a board config file is to package everything
1553 about a given board that user config files need to know.
1554 In summary the board files should contain (if present)
1556 @enumerate
1557 @item One or more @command{source [find target/...cfg]} statements
1558 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1559 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1560 @item Target @code{reset} handlers for SDRAM and I/O configuration
1561 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1562 @item All things that are not ``inside a chip''
1563 @end enumerate
1565 Generic things inside target chips belong in target config files,
1566 not board config files. So for example a @code{reset-init} event
1567 handler should know board-specific oscillator and PLL parameters,
1568 which it passes to target-specific utility code.
1570 The most complex task of a board config file is creating such a
1571 @code{reset-init} event handler.
1572 Define those handlers last, after you verify the rest of the board
1573 configuration works.
1575 @subsection Communication Between Config files
1577 In addition to target-specific utility code, another way that
1578 board and target config files communicate is by following a
1579 convention on how to use certain variables.
1581 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1582 Thus the rule we follow in OpenOCD is this: Variables that begin with
1583 a leading underscore are temporary in nature, and can be modified and
1584 used at will within a target configuration file.
1586 Complex board config files can do the things like this,
1587 for a board with three chips:
1589 @example
1590 # Chip #1: PXA270 for network side, big endian
1591 set CHIPNAME network
1592 set ENDIAN big
1593 source [find target/pxa270.cfg]
1594 # on return: _TARGETNAME = network.cpu
1595 # other commands can refer to the "network.cpu" target.
1596 $_TARGETNAME configure .... events for this CPU..
1598 # Chip #2: PXA270 for video side, little endian
1599 set CHIPNAME video
1600 set ENDIAN little
1601 source [find target/pxa270.cfg]
1602 # on return: _TARGETNAME = video.cpu
1603 # other commands can refer to the "video.cpu" target.
1604 $_TARGETNAME configure .... events for this CPU..
1606 # Chip #3: Xilinx FPGA for glue logic
1607 set CHIPNAME xilinx
1608 unset ENDIAN
1609 source [find target/spartan3.cfg]
1610 @end example
1612 That example is oversimplified because it doesn't show any flash memory,
1613 or the @code{reset-init} event handlers to initialize external DRAM
1614 or (assuming it needs it) load a configuration into the FPGA.
1615 Such features are usually needed for low-level work with many boards,
1616 where ``low level'' implies that the board initialization software may
1617 not be working. (That's a common reason to need JTAG tools. Another
1618 is to enable working with microcontroller-based systems, which often
1619 have no debugging support except a JTAG connector.)
1621 Target config files may also export utility functions to board and user
1622 config files. Such functions should use name prefixes, to help avoid
1623 naming collisions.
1625 Board files could also accept input variables from user config files.
1626 For example, there might be a @code{J4_JUMPER} setting used to identify
1627 what kind of flash memory a development board is using, or how to set
1628 up other clocks and peripherals.
1630 @subsection Variable Naming Convention
1631 @cindex variable names
1633 Most boards have only one instance of a chip.
1634 However, it should be easy to create a board with more than
1635 one such chip (as shown above).
1636 Accordingly, we encourage these conventions for naming
1637 variables associated with different @file{target.cfg} files,
1638 to promote consistency and
1639 so that board files can override target defaults.
1641 Inputs to target config files include:
1643 @itemize @bullet
1644 @item @code{CHIPNAME} ...
1645 This gives a name to the overall chip, and is used as part of
1646 tap identifier dotted names.
1647 While the default is normally provided by the chip manufacturer,
1648 board files may need to distinguish between instances of a chip.
1649 @item @code{ENDIAN} ...
1650 By default @option{little} - although chips may hard-wire @option{big}.
1651 Chips that can't change endianness don't need to use this variable.
1652 @item @code{CPUTAPID} ...
1653 When OpenOCD examines the JTAG chain, it can be told verify the
1654 chips against the JTAG IDCODE register.
1655 The target file will hold one or more defaults, but sometimes the
1656 chip in a board will use a different ID (perhaps a newer revision).
1657 @end itemize
1659 Outputs from target config files include:
1661 @itemize @bullet
1662 @item @code{_TARGETNAME} ...
1663 By convention, this variable is created by the target configuration
1664 script. The board configuration file may make use of this variable to
1665 configure things like a ``reset init'' script, or other things
1666 specific to that board and that target.
1667 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1668 @code{_TARGETNAME1}, ... etc.
1669 @end itemize
1671 @subsection The reset-init Event Handler
1672 @cindex event, reset-init
1673 @cindex reset-init handler
1675 Board config files run in the OpenOCD configuration stage;
1676 they can't use TAPs or targets, since they haven't been
1677 fully set up yet.
1678 This means you can't write memory or access chip registers;
1679 you can't even verify that a flash chip is present.
1680 That's done later in event handlers, of which the target @code{reset-init}
1681 handler is one of the most important.
1683 Except on microcontrollers, the basic job of @code{reset-init} event
1684 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1685 Microcontrollers rarely use boot loaders; they run right out of their
1686 on-chip flash and SRAM memory. But they may want to use one of these
1687 handlers too, if just for developer convenience.
1689 @quotation Note
1690 Because this is so very board-specific, and chip-specific, no examples
1691 are included here.
1692 Instead, look at the board config files distributed with OpenOCD.
1693 If you have a boot loader, its source code will help; so will
1694 configuration files for other JTAG tools
1695 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1696 @end quotation
1698 Some of this code could probably be shared between different boards.
1699 For example, setting up a DRAM controller often doesn't differ by
1700 much except the bus width (16 bits or 32?) and memory timings, so a
1701 reusable TCL procedure loaded by the @file{target.cfg} file might take
1702 those as parameters.
1703 Similarly with oscillator, PLL, and clock setup;
1704 and disabling the watchdog.
1705 Structure the code cleanly, and provide comments to help
1706 the next developer doing such work.
1707 (@emph{You might be that next person} trying to reuse init code!)
1709 The last thing normally done in a @code{reset-init} handler is probing
1710 whatever flash memory was configured. For most chips that needs to be
1711 done while the associated target is halted, either because JTAG memory
1712 access uses the CPU or to prevent conflicting CPU access.
1714 @subsection JTAG Clock Rate
1716 Before your @code{reset-init} handler has set up
1717 the PLLs and clocking, you may need to run with
1718 a low JTAG clock rate.
1719 @xref{jtagspeed,,JTAG Speed}.
1720 Then you'd increase that rate after your handler has
1721 made it possible to use the faster JTAG clock.
1722 When the initial low speed is board-specific, for example
1723 because it depends on a board-specific oscillator speed, then
1724 you should probably set it up in the board config file;
1725 if it's target-specific, it belongs in the target config file.
1727 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1728 @uref{} gives details.}
1729 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1730 Consult chip documentation to determine the peak JTAG clock rate,
1731 which might be less than that.
1733 @quotation Warning
1734 On most ARMs, JTAG clock detection is coupled to the core clock, so
1735 software using a @option{wait for interrupt} operation blocks JTAG access.
1736 Adaptive clocking provides a partial workaround, but a more complete
1737 solution just avoids using that instruction with JTAG debuggers.
1738 @end quotation
1740 If both the chip and the board support adaptive clocking,
1741 use the @command{jtag_rclk}
1742 command, in case your board is used with JTAG adapter which
1743 also supports it. Otherwise use @command{adapter_khz}.
1744 Set the slow rate at the beginning of the reset sequence,
1745 and the faster rate as soon as the clocks are at full speed.
1747 @anchor{theinitboardprocedure}
1748 @subsection The init_board procedure
1749 @cindex init_board procedure
1751 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1752 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1753 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1754 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1755 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1756 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1757 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1758 Additionally ``linear'' board config file will most likely fail when target config file uses
1759 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1760 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1761 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1762 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1764 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1765 the original), allowing greater code reuse.
1767 @example
1768 ### board_file.cfg ###
1770 # source target file that does most of the config in init_targets
1771 source [find target/target.cfg]
1773 proc enable_fast_clock @{@} @{
1774 # enables fast on-board clock source
1775 # configures the chip to use it
1776 @}
1778 # initialize only board specifics - reset, clock, adapter frequency
1779 proc init_board @{@} @{
1780 reset_config trst_and_srst trst_pulls_srst
1782 $_TARGETNAME configure -event reset-init @{
1783 adapter_khz 1
1784 enable_fast_clock
1785 adapter_khz 10000
1786 @}
1787 @}
1788 @end example
1790 @section Target Config Files
1791 @cindex config file, target
1792 @cindex target config file
1794 Board config files communicate with target config files using
1795 naming conventions as described above, and may source one or
1796 more target config files like this:
1798 @example
1799 source [find target/FOOBAR.cfg]
1800 @end example
1802 The point of a target config file is to package everything
1803 about a given chip that board config files need to know.
1804 In summary the target files should contain
1806 @enumerate
1807 @item Set defaults
1808 @item Add TAPs to the scan chain
1809 @item Add CPU targets (includes GDB support)
1810 @item CPU/Chip/CPU-Core specific features
1811 @item On-Chip flash
1812 @end enumerate
1814 As a rule of thumb, a target file sets up only one chip.
1815 For a microcontroller, that will often include a single TAP,
1816 which is a CPU needing a GDB target, and its on-chip flash.
1818 More complex chips may include multiple TAPs, and the target
1819 config file may need to define them all before OpenOCD
1820 can talk to the chip.
1821 For example, some phone chips have JTAG scan chains that include
1822 an ARM core for operating system use, a DSP,
1823 another ARM core embedded in an image processing engine,
1824 and other processing engines.
1826 @subsection Default Value Boiler Plate Code
1828 All target configuration files should start with code like this,
1829 letting board config files express environment-specific
1830 differences in how things should be set up.
1832 @example
1833 # Boards may override chip names, perhaps based on role,
1834 # but the default should match what the vendor uses
1835 if @{ [info exists CHIPNAME] @} @{
1837 @} else @{
1838 set _CHIPNAME sam7x256
1839 @}
1841 # ONLY use ENDIAN with targets that can change it.
1842 if @{ [info exists ENDIAN] @} @{
1843 set _ENDIAN $ENDIAN
1844 @} else @{
1845 set _ENDIAN little
1846 @}
1848 # TAP identifiers may change as chips mature, for example with
1849 # new revision fields (the "3" here). Pick a good default; you
1850 # can pass several such identifiers to the "jtag newtap" command.
1851 if @{ [info exists CPUTAPID ] @} @{
1853 @} else @{
1854 set _CPUTAPID 0x3f0f0f0f
1855 @}
1856 @end example
1857 @c but 0x3f0f0f0f is for an str73x part ...
1859 @emph{Remember:} Board config files may include multiple target
1860 config files, or the same target file multiple times
1861 (changing at least @code{CHIPNAME}).
1863 Likewise, the target configuration file should define
1864 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1865 use it later on when defining debug targets:
1867 @example
1869 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1870 @end example
1872 @subsection Adding TAPs to the Scan Chain
1873 After the ``defaults'' are set up,
1874 add the TAPs on each chip to the JTAG scan chain.
1875 @xref{TAP Declaration}, and the naming convention
1876 for taps.
1878 In the simplest case the chip has only one TAP,
1879 probably for a CPU or FPGA.
1880 The config file for the Atmel AT91SAM7X256
1881 looks (in part) like this:
1883 @example
1884 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1885 @end example
1887 A board with two such at91sam7 chips would be able
1888 to source such a config file twice, with different
1889 values for @code{CHIPNAME}, so
1890 it adds a different TAP each time.
1892 If there are nonzero @option{-expected-id} values,
1893 OpenOCD attempts to verify the actual tap id against those values.
1894 It will issue error messages if there is mismatch, which
1895 can help to pinpoint problems in OpenOCD configurations.
1897 @example
1898 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1899 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1900 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1901 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1902 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1903 @end example
1905 There are more complex examples too, with chips that have
1906 multiple TAPs. Ones worth looking at include:
1908 @itemize
1909 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1910 plus a JRC to enable them
1911 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1912 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1913 is not currently used)
1914 @end itemize
1916 @subsection Add CPU targets
1918 After adding a TAP for a CPU, you should set it up so that
1919 GDB and other commands can use it.
1920 @xref{CPU Configuration}.
1921 For the at91sam7 example above, the command can look like this;
1922 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1923 to little endian, and this chip doesn't support changing that.
1925 @example
1927 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1928 @end example
1930 Work areas are small RAM areas associated with CPU targets.
1931 They are used by OpenOCD to speed up downloads,
1932 and to download small snippets of code to program flash chips.
1933 If the chip includes a form of ``on-chip-ram'' - and many do - define
1934 a work area if you can.
1935 Again using the at91sam7 as an example, this can look like:
1937 @example
1938 $_TARGETNAME configure -work-area-phys 0x00200000 \
1939 -work-area-size 0x4000 -work-area-backup 0
1940 @end example
1942 @anchor{definecputargetsworkinginsmp}
1943 @subsection Define CPU targets working in SMP
1944 @cindex SMP
1945 After setting targets, you can define a list of targets working in SMP.
1947 @example
1948 set _TARGETNAME_1 $_CHIPNAME.cpu1
1949 set _TARGETNAME_2 $_CHIPNAME.cpu2
1950 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1951 -coreid 0 -dbgbase $_DAP_DBG1
1952 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1953 -coreid 1 -dbgbase $_DAP_DBG2
1954 #define 2 targets working in smp.
1955 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1956 @end example
1957 In the above example on cortex_a, 2 cpus are working in SMP.
1958 In SMP only one GDB instance is created and :
1959 @itemize @bullet
1960 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1961 @item halt command triggers the halt of all targets in the list.
1962 @item resume command triggers the write context and the restart of all targets in the list.
1963 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1964 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1965 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1966 @end itemize
1968 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1969 command have been implemented.
1970 @itemize @bullet
1971 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1972 @item cortex_a smp_off : disable SMP mode, the current target is the one
1973 displayed in the GDB session, only this target is now controlled by GDB
1974 session. This behaviour is useful during system boot up.
1975 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1976 following example.
1977 @end itemize
1979 @example
1980 >cortex_a smp_gdb
1981 gdb coreid 0 -> -1
1982 #0 : coreid 0 is displayed to GDB ,
1983 #-> -1 : next resume triggers a real resume
1984 > cortex_a smp_gdb 1
1985 gdb coreid 0 -> 1
1986 #0 :coreid 0 is displayed to GDB ,
1987 #->1 : next resume displays coreid 1 to GDB
1988 > resume
1989 > cortex_a smp_gdb
1990 gdb coreid 1 -> 1
1991 #1 :coreid 1 is displayed to GDB ,
1992 #->1 : next resume displays coreid 1 to GDB
1993 > cortex_a smp_gdb -1
1994 gdb coreid 1 -> -1
1995 #1 :coreid 1 is displayed to GDB,
1996 #->-1 : next resume triggers a real resume
1997 @end example
2000 @subsection Chip Reset Setup
2002 As a rule, you should put the @command{reset_config} command
2003 into the board file. Most things you think you know about a
2004 chip can be tweaked by the board.
2006 Some chips have specific ways the TRST and SRST signals are
2007 managed. In the unusual case that these are @emph{chip specific}
2008 and can never be changed by board wiring, they could go here.
2009 For example, some chips can't support JTAG debugging without
2010 both signals.
2012 Provide a @code{reset-assert} event handler if you can.
2013 Such a handler uses JTAG operations to reset the target,
2014 letting this target config be used in systems which don't
2015 provide the optional SRST signal, or on systems where you
2016 don't want to reset all targets at once.
2017 Such a handler might write to chip registers to force a reset,
2018 use a JRC to do that (preferable -- the target may be wedged!),
2019 or force a watchdog timer to trigger.
2020 (For Cortex-M targets, this is not necessary. The target
2021 driver knows how to use trigger an NVIC reset when SRST is
2022 not available.)
2024 Some chips need special attention during reset handling if
2025 they're going to be used with JTAG.
2026 An example might be needing to send some commands right
2027 after the target's TAP has been reset, providing a
2028 @code{reset-deassert-post} event handler that writes a chip
2029 register to report that JTAG debugging is being done.
2030 Another would be reconfiguring the watchdog so that it stops
2031 counting while the core is halted in the debugger.
2033 JTAG clocking constraints often change during reset, and in
2034 some cases target config files (rather than board config files)
2035 are the right places to handle some of those issues.
2036 For example, immediately after reset most chips run using a
2037 slower clock than they will use later.
2038 That means that after reset (and potentially, as OpenOCD
2039 first starts up) they must use a slower JTAG clock rate
2040 than they will use later.
2041 @xref{jtagspeed,,JTAG Speed}.
2043 @quotation Important
2044 When you are debugging code that runs right after chip
2045 reset, getting these issues right is critical.
2046 In particular, if you see intermittent failures when
2047 OpenOCD verifies the scan chain after reset,
2048 look at how you are setting up JTAG clocking.
2049 @end quotation
2051 @anchor{theinittargetsprocedure}
2052 @subsection The init_targets procedure
2053 @cindex init_targets procedure
2055 Target config files can either be ``linear'' (script executed line-by-line when parsed in
2056 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
2057 procedure called @code{init_targets}, which will be executed when entering run stage
2058 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
2059 Such procedure can be overriden by ``next level'' script (which sources the original).
2060 This concept faciliates code reuse when basic target config files provide generic configuration
2061 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
2062 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
2063 because sourcing them executes every initialization commands they provide.
2065 @example
2066 ### generic_file.cfg ###
2068 proc setup_my_chip @{chip_name flash_size ram_size@} @{
2069 # basic initialization procedure ...
2070 @}
2072 proc init_targets @{@} @{
2073 # initializes generic chip with 4kB of flash and 1kB of RAM
2074 setup_my_chip MY_GENERIC_CHIP 4096 1024
2075 @}
2077 ### specific_file.cfg ###
2079 source [find target/generic_file.cfg]
2081 proc init_targets @{@} @{
2082 # initializes specific chip with 128kB of flash and 64kB of RAM
2083 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
2084 @}
2085 @end example
2087 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
2088 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
2090 For an example of this scheme see LPC2000 target config files.
2092 The @code{init_boards} procedure is a similar concept concerning board config files
2093 (@xref{theinitboardprocedure,,The init_board procedure}.)
2095 @subsection ARM Core Specific Hacks
2097 If the chip has a DCC, enable it. If the chip is an ARM9 with some
2098 special high speed download features - enable it.
2100 If present, the MMU, the MPU and the CACHE should be disabled.
2102 Some ARM cores are equipped with trace support, which permits
2103 examination of the instruction and data bus activity. Trace
2104 activity is controlled through an ``Embedded Trace Module'' (ETM)
2105 on one of the core's scan chains. The ETM emits voluminous data
2106 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
2107 If you are using an external trace port,
2108 configure it in your board config file.
2109 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2110 configure it in your target config file.
2112 @example
2113 etm config $_TARGETNAME 16 normal full etb
2114 etb config $_TARGETNAME $_CHIPNAME.etb
2115 @end example
2117 @subsection Internal Flash Configuration
2119 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2121 @b{Never ever} in the ``target configuration file'' define any type of
2122 flash that is external to the chip. (For example a BOOT flash on
2123 Chip Select 0.) Such flash information goes in a board file - not
2124 the TARGET (chip) file.
2126 Examples:
2127 @itemize @bullet
2128 @item at91sam7x256 - has 256K flash YES enable it.
2129 @item str912 - has flash internal YES enable it.
2130 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2131 @item pxa270 - again - CS0 flash - it goes in the board file.
2132 @end itemize
2134 @anchor{translatingconfigurationfiles}
2135 @section Translating Configuration Files
2136 @cindex translation
2137 If you have a configuration file for another hardware debugger
2138 or toolset (Abatron, BDI2000, BDI3000, CCS,
2139 Lauterbach, Segger, Macraigor, etc.), translating
2140 it into OpenOCD syntax is often quite straightforward. The most tricky
2141 part of creating a configuration script is oftentimes the reset init
2142 sequence where e.g. PLLs, DRAM and the like is set up.
2144 One trick that you can use when translating is to write small
2145 Tcl procedures to translate the syntax into OpenOCD syntax. This
2146 can avoid manual translation errors and make it easier to
2147 convert other scripts later on.
2149 Example of transforming quirky arguments to a simple search and
2150 replace job:
2152 @example
2153 # Lauterbach syntax(?)
2154 #
2155 # Data.Set c15:0x042f %long 0x40000015
2156 #
2157 # OpenOCD syntax when using procedure below.
2158 #
2159 # setc15 0x01 0x00050078
2161 proc setc15 @{regs value@} @{
2162 global TARGETNAME
2164 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2166 arm mcr 15 [expr ($regs>>12)&0x7] \
2167 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2168 [expr ($regs>>8)&0x7] $value
2169 @}
2170 @end example
2174 @node Daemon Configuration
2175 @chapter Daemon Configuration
2176 @cindex initialization
2177 The commands here are commonly found in the openocd.cfg file and are
2178 used to specify what TCP/IP ports are used, and how GDB should be
2179 supported.
2181 @anchor{configurationstage}
2182 @section Configuration Stage
2183 @cindex configuration stage
2184 @cindex config command
2186 When the OpenOCD server process starts up, it enters a
2187 @emph{configuration stage} which is the only time that
2188 certain commands, @emph{configuration commands}, may be issued.
2189 Normally, configuration commands are only available
2190 inside startup scripts.
2192 In this manual, the definition of a configuration command is
2193 presented as a @emph{Config Command}, not as a @emph{Command}
2194 which may be issued interactively.
2195 The runtime @command{help} command also highlights configuration
2196 commands, and those which may be issued at any time.
2198 Those configuration commands include declaration of TAPs,
2199 flash banks,
2200 the interface used for JTAG communication,
2201 and other basic setup.
2202 The server must leave the configuration stage before it
2203 may access or activate TAPs.
2204 After it leaves this stage, configuration commands may no
2205 longer be issued.
2207 @anchor{enteringtherunstage}
2208 @section Entering the Run Stage
2210 The first thing OpenOCD does after leaving the configuration
2211 stage is to verify that it can talk to the scan chain
2212 (list of TAPs) which has been configured.
2213 It will warn if it doesn't find TAPs it expects to find,
2214 or finds TAPs that aren't supposed to be there.
2215 You should see no errors at this point.
2216 If you see errors, resolve them by correcting the
2217 commands you used to configure the server.
2218 Common errors include using an initial JTAG speed that's too
2219 fast, and not providing the right IDCODE values for the TAPs
2220 on the scan chain.
2222 Once OpenOCD has entered the run stage, a number of commands
2223 become available.
2224 A number of these relate to the debug targets you may have declared.
2225 For example, the @command{mww} command will not be available until
2226 a target has been successfuly instantiated.
2227 If you want to use those commands, you may need to force
2228 entry to the run stage.
2230 @deffn {Config Command} init
2231 This command terminates the configuration stage and
2232 enters the run stage. This helps when you need to have
2233 the startup scripts manage tasks such as resetting the target,
2234 programming flash, etc. To reset the CPU upon startup, add "init" and
2235 "reset" at the end of the config script or at the end of the OpenOCD
2236 command line using the @option{-c} command line switch.
2238 If this command does not appear in any startup/configuration file
2239 OpenOCD executes the command for you after processing all
2240 configuration files and/or command line options.
2242 @b{NOTE:} This command normally occurs at or near the end of your
2243 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2244 targets ready. For example: If your openocd.cfg file needs to
2245 read/write memory on your target, @command{init} must occur before
2246 the memory read/write commands. This includes @command{nand probe}.
2247 @end deffn
2249 @deffn {Overridable Procedure} jtag_init
2250 This is invoked at server startup to verify that it can talk
2251 to the scan chain (list of TAPs) which has been configured.
2253 The default implementation first tries @command{jtag arp_init},
2254 which uses only a lightweight JTAG reset before examining the
2255 scan chain.
2256 If that fails, it tries again, using a harder reset
2257 from the overridable procedure @command{init_reset}.
2259 Implementations must have verified the JTAG scan chain before
2260 they return.
2261 This is done by calling @command{jtag arp_init}
2262 (or @command{jtag arp_init-reset}).
2263 @end deffn
2265 @anchor{tcpipports}
2266 @section TCP/IP Ports
2267 @cindex TCP port
2268 @cindex server
2269 @cindex port
2270 @cindex security
2271 The OpenOCD server accepts remote commands in several syntaxes.
2272 Each syntax uses a different TCP/IP port, which you may specify
2273 only during configuration (before those ports are opened).
2275 For reasons including security, you may wish to prevent remote
2276 access using one or more of these ports.
2277 In such cases, just specify the relevant port number as zero.
2278 If you disable all access through TCP/IP, you will need to
2279 use the command line @option{-pipe} option.
2281 @deffn {Command} gdb_port [number]
2282 @cindex GDB server
2283 Normally gdb listens to a TCP/IP port, but GDB can also
2284 communicate via pipes(stdin/out or named pipes). The name
2285 "gdb_port" stuck because it covers probably more than 90% of
2286 the normal use cases.
2288 No arguments reports GDB port. "pipe" means listen to stdin
2289 output to stdout, an integer is base port number, "disable"
2290 disables the gdb server.
2292 When using "pipe", also use log_output to redirect the log
2293 output to a file so as not to flood the stdin/out pipes.
2295 The -p/--pipe option is deprecated and a warning is printed
2296 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2298 Any other string is interpreted as named pipe to listen to.
2299 Output pipe is the same name as input pipe, but with 'o' appended,
2300 e.g. /var/gdb, /var/gdbo.
2302 The GDB port for the first target will be the base port, the
2303 second target will listen on gdb_port + 1, and so on.
2304 When not specified during the configuration stage,
2305 the port @var{number} defaults to 3333.
2306 @end deffn
2308 @deffn {Command} tcl_port [number]
2309 Specify or query the port used for a simplified RPC
2310 connection that can be used by clients to issue TCL commands and get the
2311 output from the Tcl engine.
2312 Intended as a machine interface.
2313 When not specified during the configuration stage,
2314 the port @var{number} defaults to 6666.
2316 @end deffn
2318 @deffn {Command} telnet_port [number]
2319 Specify or query the
2320 port on which to listen for incoming telnet connections.
2321 This port is intended for interaction with one human through TCL commands.
2322 When not specified during the configuration stage,
2323 the port @var{number} defaults to 4444.
2324 When specified as zero, this port is not activated.
2325 @end deffn
2327 @anchor{gdbconfiguration}
2328 @section GDB Configuration
2329 @cindex GDB
2330 @cindex GDB configuration
2331 You can reconfigure some GDB behaviors if needed.
2332 The ones listed here are static and global.
2333 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2334 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2336 @anchor{gdbbreakpointoverride}
2337 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2338 Force breakpoint type for gdb @command{break} commands.
2339 This option supports GDB GUIs which don't
2340 distinguish hard versus soft breakpoints, if the default OpenOCD and
2341 GDB behaviour is not sufficient. GDB normally uses hardware
2342 breakpoints if the memory map has been set up for flash regions.
2343 @end deffn
2345 @anchor{gdbflashprogram}
2346 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2347 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2348 vFlash packet is received.
2349 The default behaviour is @option{enable}.
2350 @end deffn
2352 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2353 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2354 requested. GDB will then know when to set hardware breakpoints, and program flash
2355 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2356 for flash programming to work.
2357 Default behaviour is @option{enable}.
2358 @xref{gdbflashprogram,,gdb_flash_program}.
2359 @end deffn
2361 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2362 Specifies whether data aborts cause an error to be reported
2363 by GDB memory read packets.
2364 The default behaviour is @option{disable};
2365 use @option{enable} see these errors reported.
2366 @end deffn
2368 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2369 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2370 The default behaviour is @option{disable}.
2371 @end deffn
2373 @deffn {Command} gdb_save_tdesc
2374 Saves the target descripton file to the local file system.
2376 The file name is @i{target_name}.xml.
2377 @end deffn
2379 @anchor{eventpolling}
2380 @section Event Polling
2382 Hardware debuggers are parts of asynchronous systems,
2383 where significant events can happen at any time.
2384 The OpenOCD server needs to detect some of these events,
2385 so it can report them to through TCL command line
2386 or to GDB.
2388 Examples of such events include:
2390 @itemize
2391 @item One of the targets can stop running ... maybe it triggers
2392 a code breakpoint or data watchpoint, or halts itself.
2393 @item Messages may be sent over ``debug message'' channels ... many
2394 targets support such messages sent over JTAG,
2395 for receipt by the person debugging or tools.
2396 @item Loss of power ... some adapters can detect these events.
2397 @item Resets not issued through JTAG ... such reset sources
2398 can include button presses or other system hardware, sometimes
2399 including the target itself (perhaps through a watchdog).
2400 @item Debug instrumentation sometimes supports event triggering
2401 such as ``trace buffer full'' (so it can quickly be emptied)
2402 or other signals (to correlate with code behavior).
2403 @end itemize
2405 None of those events are signaled through standard JTAG signals.
2406 However, most conventions for JTAG connectors include voltage
2407 level and system reset (SRST) signal detection.
2408 Some connectors also include instrumentation signals, which
2409 can imply events when those signals are inputs.
2411 In general, OpenOCD needs to periodically check for those events,
2412 either by looking at the status of signals on the JTAG connector
2413 or by sending synchronous ``tell me your status'' JTAG requests
2414 to the various active targets.
2415 There is a command to manage and monitor that polling,
2416 which is normally done in the background.
2418 @deffn Command poll [@option{on}|@option{off}]
2419 Poll the current target for its current state.
2420 (Also, @pxref{targetcurstate,,target curstate}.)
2421 If that target is in debug mode, architecture
2422 specific information about the current state is printed.
2423 An optional parameter
2424 allows background polling to be enabled and disabled.
2426 You could use this from the TCL command shell, or
2427 from GDB using @command{monitor poll} command.
2428 Leave background polling enabled while you're using GDB.
2429 @example
2430 > poll
2431 background polling: on
2432 target state: halted
2433 target halted in ARM state due to debug-request, \
2434 current mode: Supervisor
2435 cpsr: 0x800000d3 pc: 0x11081bfc
2436 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2437 >
2438 @end example
2439 @end deffn
2441 @node Debug Adapter Configuration
2442 @chapter Debug Adapter Configuration
2443 @cindex config file, interface
2444 @cindex interface config file
2446 Correctly installing OpenOCD includes making your operating system give
2447 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2448 are used to select which one is used, and to configure how it is used.
2450 @quotation Note
2451 Because OpenOCD started out with a focus purely on JTAG, you may find
2452 places where it wrongly presumes JTAG is the only transport protocol
2453 in use. Be aware that recent versions of OpenOCD are removing that
2454 limitation. JTAG remains more functional than most other transports.
2455 Other transports do not support boundary scan operations, or may be
2456 specific to a given chip vendor. Some might be usable only for
2457 programming flash memory, instead of also for debugging.
2458 @end quotation
2460 Debug Adapters/Interfaces/Dongles are normally configured
2461 through commands in an interface configuration
2462 file which is sourced by your @file{openocd.cfg} file, or
2463 through a command line @option{-f interface/....cfg} option.
2465 @example
2466 source [find interface/olimex-jtag-tiny.cfg]
2467 @end example
2469 These commands tell
2470 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2471 A few cases are so simple that you only need to say what driver to use:
2473 @example
2474 # jlink interface
2475 interface jlink
2476 @end example
2478 Most adapters need a bit more configuration than that.
2481 @section Interface Configuration
2483 The interface command tells OpenOCD what type of debug adapter you are
2484 using. Depending on the type of adapter, you may need to use one or
2485 more additional commands to further identify or configure the adapter.
2487 @deffn {Config Command} {interface} name
2488 Use the interface driver @var{name} to connect to the
2489 target.
2490 @end deffn
2492 @deffn Command {interface_list}
2493 List the debug adapter drivers that have been built into
2494 the running copy of OpenOCD.
2495 @end deffn
2496 @deffn Command {interface transports} transport_name+
2497 Specifies the transports supported by this debug adapter.
2498 The adapter driver builds-in similar knowledge; use this only
2499 when external configuration (such as jumpering) changes what
2500 the hardware can support.
2501 @end deffn
2505 @deffn Command {adapter_name}
2506 Returns the name of the debug adapter driver being used.
2507 @end deffn
2509 @section Interface Drivers
2511 Each of the interface drivers listed here must be explicitly
2512 enabled when OpenOCD is configured, in order to be made
2513 available at run time.
2515 @deffn {Interface Driver} {amt_jtagaccel}
2516 Amontec Chameleon in its JTAG Accelerator configuration,
2517 connected to a PC's EPP mode parallel port.
2518 This defines some driver-specific commands:
2520 @deffn {Config Command} {parport_port} number
2521 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2522 the number of the @file{/dev/parport} device.
2523 @end deffn
2525 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2526 Displays status of RTCK option.
2527 Optionally sets that option first.
2528 @end deffn
2529 @end deffn
2531 @deffn {Interface Driver} {arm-jtag-ew}
2532 Olimex ARM-JTAG-EW USB adapter
2533 This has one driver-specific command:
2535 @deffn Command {armjtagew_info}
2536 Logs some status
2537 @end deffn
2538 @end deffn
2540 @deffn {Interface Driver} {at91rm9200}
2541 Supports bitbanged JTAG from the local system,
2542 presuming that system is an Atmel AT91rm9200
2543 and a specific set of GPIOs is used.
2544 @c command: at91rm9200_device NAME
2545 @c chooses among list of bit configs ... only one option
2546 @end deffn
2548 @deffn {Interface Driver} {cmsis-dap}
2549 CMSIS-DAP compliant based adapter.
2551 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2552 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2553 known default values are used.
2554 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2555 @example
2556 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2557 @end example
2558 @end deffn
2560 @deffn {Command} {cmsis-dap info}
2561 Display various device information, like hardware version, firmware version, current bus status.
2562 @end deffn
2563 @end deffn
2565 @deffn {Interface Driver} {dummy}
2566 A dummy software-only driver for debugging.
2567 @end deffn
2569 @deffn {Interface Driver} {ep93xx}
2570 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2571 @end deffn
2573 @deffn {Interface Driver} {ft2232}
2574 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2576 Note that this driver has several flaws and the @command{ftdi} driver is
2577 recommended as its replacement.
2579 These interfaces have several commands, used to configure the driver
2580 before initializing the JTAG scan chain:
2582 @deffn {Config Command} {ft2232_device_desc} description
2583 Provides the USB device description (the @emph{iProduct string})
2584 of the FTDI FT2232 device. If not
2585 specified, the FTDI default value is used. This setting is only valid
2586 if compiled with FTD2XX support.
2587 @end deffn
2589 @deffn {Config Command} {ft2232_serial} serial-number
2590 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2591 in case the vendor provides unique IDs and more than one FT2232 device
2592 is connected to the host.
2593 If not specified, serial numbers are not considered.
2594 (Note that USB serial numbers can be arbitrary Unicode strings,
2595 and are not restricted to containing only decimal digits.)
2596 @end deffn
2598 @deffn {Config Command} {ft2232_layout} name
2599 Each vendor's FT2232 device can use different GPIO signals
2600 to control output-enables, reset signals, and LEDs.
2601 Currently valid layout @var{name} values include:
2602 @itemize @minus
2603 @item @b{axm0432_jtag} Axiom AXM-0432
2604 @item @b{comstick} Hitex STR9 comstick
2605 @item @b{cortino} Hitex Cortino JTAG interface
2606 @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
2607 either for the local Cortex-M3 (SRST only)
2608 or in a passthrough mode (neither SRST nor TRST)
2609 This layout can not support the SWO trace mechanism, and should be
2610 used only for older boards (before rev C).
2611 @item @b{luminary_icdi} This layout should be used with most TI/Luminary
2612 eval boards, including Rev C LM3S811 eval boards and the eponymous
2613 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2614 to debug some other target. It can support the SWO trace mechanism.
2615 @item @b{flyswatter} Tin Can Tools Flyswatter
2616 @item @b{icebear} ICEbear JTAG adapter from Section 5
2617 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2618 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2619 @item @b{m5960} American Microsystems M5960
2620 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2621 @item @b{oocdlink} OOCDLink
2622 @c oocdlink ~= jtagkey_prototype_v1
2623 @item @b{redbee-econotag} Integrated with a Redbee development board.
2624 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2625 @item @b{sheevaplug} Marvell Sheevaplug development kit
2626 @item @b{signalyzer} Xverve Signalyzer
2627 @item @b{stm32stick} Hitex STM32 Performance Stick
2628 @item @b{turtelizer2} egnite Software turtelizer2
2629 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2630 @end itemize
2631 @end deffn
2633 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2634 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2635 default values are used.
2636 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2637 @example
2638 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2639 @end example
2640 @end deffn
2642 @deffn {Config Command} {ft2232_latency} ms
2643 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2644 ft2232_read() fails to return the expected number of bytes. This can be caused by
2645 USB communication delays and has proved hard to reproduce and debug. Setting the
2646 FT2232 latency timer to a larger value increases delays for short USB packets but it
2647 also reduces the risk of timeouts before receiving the expected number of bytes.
2648 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2649 @end deffn
2651 @deffn {Config Command} {ft2232_channel} channel
2652 Used to select the channel of the ft2232 chip to use (between 1 and 4).
2653 The default value is 1.
2654 @end deffn
2656 For example, the interface config file for a
2657 Turtelizer JTAG Adapter looks something like this:
2659 @example
2660 interface ft2232
2661 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2662 ft2232_layout turtelizer2
2663 ft2232_vid_pid 0x0403 0xbdc8
2664 @end example
2665 @end deffn
2667 @deffn {Interface Driver} {ftdi}
2668 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2669 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2670 It is a complete rewrite to address a large number of problems with the ft2232
2671 interface driver.
2673 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2674 bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
2675 consistently faster than the ft2232 driver, sometimes several times faster.
2677 A major improvement of this driver is that support for new FTDI based adapters
2678 can be added competely through configuration files, without the need to patch
2679 and rebuild OpenOCD.
2681 The driver uses a signal abstraction to enable Tcl configuration files to
2682 define outputs for one or several FTDI GPIO. These outputs can then be
2683 controlled using the @command{ftdi_set_signal} command. Special signal names
2684 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2685 will be used for their customary purpose.
2687 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2688 be controlled differently. In order to support tristateable signals such as
2689 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2690 signal. The following output buffer configurations are supported:
2692 @itemize @minus
2693 @item Push-pull with one FTDI output as (non-)inverted data line
2694 @item Open drain with one FTDI output as (non-)inverted output-enable
2695 @item Tristate with one FTDI output as (non-)inverted data line and another
2696 FTDI output as (non-)inverted output-enable
2697 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2698 switching data and direction as necessary
2699 @end itemize
2701 These interfaces have several commands, used to configure the driver
2702 before initializing the JTAG scan chain:
2704 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2705 The vendor ID and product ID of the adapter. If not specified, the FTDI
2706 default values are used.
2707 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2708 @example
2709 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2710 @end example
2711 @end deffn
2713 @deffn {Config Command} {ftdi_device_desc} description
2714 Provides the USB device description (the @emph{iProduct string})
2715 of the adapter. If not specified, the device description is ignored
2716 during device selection.
2717 @end deffn
2719 @deffn {Config Command} {ftdi_serial} serial-number
2720 Specifies the @var{serial-number} of the adapter to use,
2721 in case the vendor provides unique IDs and more than one adapter
2722 is connected to the host.
2723 If not specified, serial numbers are not considered.
2724 (Note that USB serial numbers can be arbitrary Unicode strings,
2725 and are not restricted to containing only decimal digits.)
2726 @end deffn
2728 @deffn {Config Command} {ftdi_channel} channel
2729 Selects the channel of the FTDI device to use for MPSSE operations. Most
2730 adapters use the default, channel 0, but there are exceptions.
2731 @end deffn
2733 @deffn {Config Command} {ftdi_layout_init} data direction
2734 Specifies the initial values of the FTDI GPIO data and direction registers.
2735 Each value is a 16-bit number corresponding to the concatenation of the high
2736 and low FTDI GPIO registers. The values should be selected based on the
2737 schematics of the adapter, such that all signals are set to safe levels with
2738 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2739 and initially asserted reset signals.
2740 @end deffn
2742 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask]
2743 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2744 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2745 register bitmasks to tell the driver the connection and type of the output
2746 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2747 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2748 used with inverting data inputs and @option{-data} with non-inverting inputs.
2749 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2750 not-output-enable) input to the output buffer is connected.
2752 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2753 simple open-collector transistor driver would be specified with @option{-oe}
2754 only. In that case the signal can only be set to drive low or to Hi-Z and the
2755 driver will complain if the signal is set to drive high. Which means that if
2756 it's a reset signal, @command{reset_config} must be specified as
2757 @option{srst_open_drain}, not @option{srst_push_pull}.
2759 A special case is provided when @option{-data} and @option{-oe} is set to the
2760 same bitmask. Then the FTDI pin is considered being connected straight to the
2761 target without any buffer. The FTDI pin is then switched between output and
2762 input as necessary to provide the full set of low, high and Hi-Z
2763 characteristics. In all other cases, the pins specified in a signal definition
2764 are always driven by the FTDI.
2765 @end deffn
2767 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2768 Set a previously defined signal to the specified level.
2769 @itemize @minus
2770 @item @option{0}, drive low
2771 @item @option{1}, drive high
2772 @item @option{z}, set to high-impedance
2773 @end itemize
2774 @end deffn
2776 For example adapter definitions, see the configuration files shipped in the
2777 @file{interface/ftdi} directory.
2778 @end deffn
2780 @deffn {Interface Driver} {remote_bitbang}
2781 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2782 with a remote process and sends ASCII encoded bitbang requests to that process
2783 instead of directly driving JTAG.
2785 The remote_bitbang driver is useful for debugging software running on
2786 processors which are being simulated.
2788 @deffn {Config Command} {remote_bitbang_port} number
2789 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2790 sockets instead of TCP.
2791 @end deffn
2793 @deffn {Config Command} {remote_bitbang_host} hostname
2794 Specifies the hostname of the remote process to connect to using TCP, or the
2795 name of the UNIX socket to use if remote_bitbang_port is 0.
2796 @end deffn
2798 For example, to connect remotely via TCP to the host foobar you might have
2799 something like:
2801 @example
2802 interface remote_bitbang
2803 remote_bitbang_port 3335
2804 remote_bitbang_host foobar
2805 @end example
2807 To connect to another process running locally via UNIX sockets with socket
2808 named mysocket:
2810 @example
2811 interface remote_bitbang
2812 remote_bitbang_port 0
2813 remote_bitbang_host mysocket
2814 @end example
2815 @end deffn
2817 @deffn {Interface Driver} {usb_blaster}
2818 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2819 for FTDI chips. These interfaces have several commands, used to
2820 configure the driver before initializing the JTAG scan chain:
2822 @deffn {Config Command} {usb_blaster_device_desc} description
2823 Provides the USB device description (the @emph{iProduct string})
2824 of the FTDI FT245 device. If not
2825 specified, the FTDI default value is used. This setting is only valid
2826 if compiled with FTD2XX support.
2827 @end deffn
2829 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2830 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2831 default values are used.
2832 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2833 Altera USB-Blaster (default):
2834 @example
2835 usb_blaster_vid_pid 0x09FB 0x6001
2836 @end example
2837 The following VID/PID is for Kolja Waschk's USB JTAG:
2838 @example
2839 usb_blaster_vid_pid 0x16C0 0x06AD
2840 @end example
2841 @end deffn
2843 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2844 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2845 female JTAG header). These pins can be used as SRST and/or TRST provided the
2846 appropriate connections are made on the target board.
2848 For example, to use pin 6 as SRST (as with an AVR board):
2849 @example
2850 $_TARGETNAME configure -event reset-assert \
2851 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2852 @end example
2853 @end deffn
2855 @end deffn
2857 @deffn {Interface Driver} {gw16012}
2858 Gateworks GW16012 JTAG programmer.
2859 This has one driver-specific command:
2861 @deffn {Config Command} {parport_port} [port_number]
2862 Display either the address of the I/O port
2863 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2864 If a parameter is provided, first switch to use that port.
2865 This is a write-once setting.
2866 @end deffn
2867 @end deffn
2869 @deffn {Interface Driver} {jlink}
2870 Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
2872 @quotation Compatibility Note
2873 Segger released many firmware versions for the many harware versions they
2874 produced. OpenOCD was extensively tested and intended to run on all of them,
2875 but some combinations were reported as incompatible. As a general
2876 recommendation, it is advisable to use the latest firmware version
2877 available for each hardware version. However the current V8 is a moving
2878 target, and Segger firmware versions released after the OpenOCD was
2879 released may not be compatible. In such cases it is recommended to
2880 revert to the last known functional version. For 0.5.0, this is from
2881 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2882 version is from "May 3 2012 18:36:22", packed with 4.46f.
2883 @end quotation
2885 @deffn {Command} {jlink caps}
2886 Display the device firmware capabilities.
2887 @end deffn
2888 @deffn {Command} {jlink info}
2889 Display various device information, like hardware version, firmware version, current bus status.
2890 @end deffn
2891 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2892 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2893 @end deffn
2894 @deffn {Command} {jlink config}
2895 Display the J-Link configuration.
2896 @end deffn
2897 @deffn {Command} {jlink config kickstart} [val]
2898 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2899 @end deffn
2900 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2901 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2902 @end deffn
2903 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2904 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2905 E the bit of the subnet mask and
2906 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2907 @end deffn
2908 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2909 Set the USB address; this will also change the product id. Without argument, show the USB address.
2910 @end deffn
2911 @deffn {Command} {jlink config reset}
2912 Reset the current configuration.
2913 @end deffn
2914 @deffn {Command} {jlink config save}
2915 Save the current configuration to the internal persistent storage.
2916 @end deffn
2917 @deffn {Config} {jlink pid} val
2918 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2919 @end deffn
2920 @end deffn
2922 @deffn {Interface Driver} {parport}
2923 Supports PC parallel port bit-banging cables:
2924 Wigglers, PLD download cable, and more.
2925 These interfaces have several commands, used to configure the driver
2926 before initializing the JTAG scan chain:
2928 @deffn {Config Command} {parport_cable} name
2929 Set the layout of the parallel port cable used to connect to the target.
2930 This is a write-once setting.
2931 Currently valid cable @var{name} values include:
2933 @itemize @minus
2934 @item @b{altium} Altium Universal JTAG cable.
2935 @item @b{arm-jtag} Same as original wiggler except SRST and
2936 TRST connections reversed and TRST is also inverted.
2937 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2938 in configuration mode. This is only used to
2939 program the Chameleon itself, not a connected target.
2940 @item @b{dlc5} The Xilinx Parallel cable III.
2941 @item @b{flashlink} The ST Parallel cable.
2942 @item @b{lattice} Lattice ispDOWNLOAD Cable
2943 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2944 some versions of
2945 Amontec's Chameleon Programmer. The new version available from
2946 the website uses the original Wiggler layout ('@var{wiggler}')
2947 @item @b{triton} The parallel port adapter found on the
2948 ``Karo Triton 1 Development Board''.
2949 This is also the layout used by the HollyGates design
2950 (see @uref{}).
2951 @item @b{wiggler} The original Wiggler layout, also supported by
2952 several clones, such as the Olimex ARM-JTAG
2953 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2954 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2955 @end itemize
2956 @end deffn
2958 @deffn {Config Command} {parport_port} [port_number]
2959 Display either the address of the I/O port
2960 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2961 If a parameter is provided, first switch to use that port.
2962 This is a write-once setting.
2964 When using PPDEV to access the parallel port, use the number of the parallel port:
2965 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2966 you may encounter a problem.
2967 @end deffn
2969 @deffn Command {parport_toggling_time} [nanoseconds]
2970 Displays how many nanoseconds the hardware needs to toggle TCK;
2971 the parport driver uses this value to obey the
2972 @command{adapter_khz} configuration.
2973 When the optional @var{nanoseconds} parameter is given,
2974 that setting is changed before displaying the current value.
2976 The default setting should work reasonably well on commodity PC hardware.
2977 However, you may want to calibrate for your specific hardware.
2978 @quotation Tip
2979 To measure the toggling time with a logic analyzer or a digital storage
2980 oscilloscope, follow the procedure below:
2981 @example
2982 > parport_toggling_time 1000
2983 > adapter_khz 500
2984 @end example
2985 This sets the maximum JTAG clock speed of the hardware, but
2986 the actual speed probably deviates from the requested 500 kHz.
2987 Now, measure the time between the two closest spaced TCK transitions.
2988 You can use @command{runtest 1000} or something similar to generate a
2989 large set of samples.
2990 Update the setting to match your measurement:
2991 @example
2992 > parport_toggling_time <measured nanoseconds>
2993 @end example
2994 Now the clock speed will be a better match for @command{adapter_khz rate}
2995 commands given in OpenOCD scripts and event handlers.
2997 You can do something similar with many digital multimeters, but note
2998 that you'll probably need to run the clock continuously for several
2999 seconds before it decides what clock rate to show. Adjust the
3000 toggling time up or down until the measured clock rate is a good
3001 match for the adapter_khz rate you specified; be conservative.
3002 @end quotation
3003 @end deffn
3005 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
3006 This will configure the parallel driver to write a known
3007 cable-specific value to the parallel interface on exiting OpenOCD.
3008 @end deffn
3010 For example, the interface configuration file for a
3011 classic ``Wiggler'' cable on LPT2 might look something like this:
3013 @example
3014 interface parport
3015 parport_port 0x278
3016 parport_cable wiggler
3017 @end example
3018 @end deffn
3020 @deffn {Interface Driver} {presto}
3021 ASIX PRESTO USB JTAG programmer.
3022 @deffn {Config Command} {presto_serial} serial_string
3023 Configures the USB serial number of the Presto device to use.
3024 @end deffn
3025 @end deffn
3027 @deffn {Interface Driver} {rlink}
3028 Raisonance RLink USB adapter
3029 @end deffn
3031 @deffn {Interface Driver} {usbprog}
3032 usbprog is a freely programmable USB adapter.
3033 @end deffn
3035 @deffn {Interface Driver} {vsllink}
3036 vsllink is part of Versaloon which is a versatile USB programmer.
3038 @quotation Note
3039 This defines quite a few driver-specific commands,
3040 which are not currently documented here.
3041 @end quotation
3042 @end deffn
3044 @deffn {Interface Driver} {hla}
3045 This is a driver that supports multiple High Level Adapters.
3046 This type of adapter does not expose some of the lower level api's
3047 that OpenOCD would normally use to access the target.
3049 Currently supported adapters include the ST STLINK and TI ICDI.
3051 @deffn {Config Command} {hla_device_desc} description
3052 Currently Not Supported.
3053 @end deffn
3055 @deffn {Config Command} {hla_serial} serial
3056 Currently Not Supported.
3057 @end deffn
3059 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
3060 Specifies the adapter layout to use.
3061 @end deffn
3063 @deffn {Config Command} {hla_vid_pid} vid pid
3064 The vendor ID and product ID of the device.
3065 @end deffn
3067 @deffn {Config Command} {trace} source_clock_hz [output_file_path]
3068 Enable SWO tracing (if supported). The source clock rate for the
3069 trace port must be specified, this is typically the CPU clock rate. If
3070 the optional output file is specified then raw trace data is appended
3071 to the file, and the file is created if it does not exist.
3072 @end deffn
3073 @end deffn
3075 @deffn {Interface Driver} {opendous}
3076 opendous-jtag is a freely programmable USB adapter.
3077 @end deffn
3079 @deffn {Interface Driver} {ulink}
3080 This is the Keil ULINK v1 JTAG debugger.
3081 @end deffn
3083 @deffn {Interface Driver} {ZY1000}
3084 This is the Zylin ZY1000 JTAG debugger.
3085 @end deffn
3087 @quotation Note
3088 This defines some driver-specific commands,
3089 which are not currently documented here.
3090 @end quotation
3092 @deffn Command power [@option{on}|@option{off}]
3093 Turn power switch to target on/off.
3094 No arguments: print status.
3095 @end deffn
3097 @deffn {Interface Driver} {bcm2835gpio}
3098 This SoC is present in Raspberry Pi which is a cheap single-board computer
3099 exposing some GPIOs on its expansion header.
3101 The driver accesses memory-mapped GPIO peripheral registers directly
3102 for maximum performance, but the only possible race condition is for
3103 the pins' modes/muxing (which is highly unlikely), so it should be
3104 able to coexist nicely with both sysfs bitbanging and various
3105 peripherals' kernel drivers. The driver restores the previous
3106 configuration on exit.
3108 See @file{interface/raspberrypi-native.cfg} for a sample config and
3109 pinout.
3111 @end deffn
3113 @section Transport Configuration
3114 @cindex Transport
3115 As noted earlier, depending on the version of OpenOCD you use,
3116 and the debug adapter you are using,
3117 several transports may be available to
3118 communicate with debug targets (or perhaps to program flash memory).
3119 @deffn Command {transport list}
3120 displays the names of the transports supported by this
3121 version of OpenOCD.
3122 @end deffn
3124 @deffn Command {transport select} transport_name
3125 Select which of the supported transports to use in this OpenOCD session.
3126 The transport must be supported by the debug adapter hardware and by the
3127 version of OpenOCD you are using (including the adapter's driver).
3128 No arguments: returns name of session's selected transport.
3129 @end deffn
3131 @subsection JTAG Transport
3132 @cindex JTAG
3133 JTAG is the original transport supported by OpenOCD, and most
3134 of the OpenOCD commands support it.
3135 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3136 each of which must be explicitly declared.
3137 JTAG supports both debugging and boundary scan testing.
3138 Flash programming support is built on top of debug support.
3139 @subsection SWD Transport
3140 @cindex SWD
3141 @cindex Serial Wire Debug
3142 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3143 Debug Access Point (DAP, which must be explicitly declared.
3144 (SWD uses fewer signal wires than JTAG.)
3145 SWD is debug-oriented, and does not support boundary scan testing.
3146 Flash programming support is built on top of debug support.
3147 (Some processors support both JTAG and SWD.)
3148 @deffn Command {swd newdap} ...
3149 Declares a single DAP which uses SWD transport.
3150 Parameters are currently the same as "jtag newtap" but this is
3151 expected to change.
3152 @end deffn
3153 @deffn Command {swd wcr trn prescale}
3154 Updates TRN (turnaraound delay) and prescaling.fields of the
3155 Wire Control Register (WCR).
3156 No parameters: displays current settings.
3157 @end deffn
3159 @subsection CMSIS-DAP Transport
3160 @cindex CMSIS-DAP
3161 CMSIS-DAP is an ARM-specific transport that is used to connect to
3162 compilant debuggers.
3164 @subsection SPI Transport
3165 @cindex SPI
3166 @cindex Serial Peripheral Interface
3167 The Serial Peripheral Interface (SPI) is a general purpose transport
3168 which uses four wire signaling. Some processors use it as part of a
3169 solution for flash programming.
3171 @anchor{jtagspeed}
3172 @section JTAG Speed
3173 JTAG clock setup is part of system setup.
3174 It @emph{does not belong with interface setup} since any interface
3175 only knows a few of the constraints for the JTAG clock speed.
3176 Sometimes the JTAG speed is
3177 changed during the target initialization process: (1) slow at
3178 reset, (2) program the CPU clocks, (3) run fast.
3179 Both the "slow" and "fast" clock rates are functions of the
3180 oscillators used, the chip, the board design, and sometimes
3181 power management software that may be active.
3183 The speed used during reset, and the scan chain verification which
3184 follows reset, can be adjusted using a @code{reset-start}
3185 target event handler.
3186 It can then be reconfigured to a faster speed by a
3187 @code{reset-init} target event handler after it reprograms those
3188 CPU clocks, or manually (if something else, such as a boot loader,
3189 sets up those clocks).
3190 @xref{targetevents,,Target Events}.
3191 When the initial low JTAG speed is a chip characteristic, perhaps
3192 because of a required oscillator speed, provide such a handler
3193 in the target config file.
3194 When that speed is a function of a board-specific characteristic
3195 such as which speed oscillator is used, it belongs in the board
3196 config file instead.
3197 In both cases it's safest to also set the initial JTAG clock rate
3198 to that same slow speed, so that OpenOCD never starts up using a
3199 clock speed that's faster than the scan chain can support.
3201 @example
3202 jtag_rclk 3000
3203 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3204 @end example
3206 If your system supports adaptive clocking (RTCK), configuring
3207 JTAG to use that is probably the most robust approach.
3208 However, it introduces delays to synchronize clocks; so it
3209 may not be the fastest solution.
3211 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3212 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3213 which support adaptive clocking.
3215 @deffn {Command} adapter_khz max_speed_kHz
3216 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3217 JTAG interfaces usually support a limited number of
3218 speeds. The speed actually used won't be faster
3219 than the speed specified.
3221 Chip data sheets generally include a top JTAG clock rate.
3222 The actual rate is often a function of a CPU core clock,
3223 and is normally less than that peak rate.
3224 For example, most ARM cores accept at most one sixth of the CPU clock.
3226 Speed 0 (khz) selects RTCK method.
3227 @xref{faqrtck,,FAQ RTCK}.
3228 If your system uses RTCK, you won't need to change the
3229 JTAG clocking after setup.
3230 Not all interfaces, boards, or targets support ``rtck''.
3231 If the interface device can not
3232 support it, an error is returned when you try to use RTCK.
3233 @end deffn
3235 @defun jtag_rclk fallback_speed_kHz
3236 @cindex adaptive clocking
3237 @cindex RTCK
3238 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3239 If that fails (maybe the interface, board, or target doesn't
3240 support it), falls back to the specified frequency.
3241 @example
3242 # Fall back to 3mhz if RTCK is not supported
3243 jtag_rclk 3000
3244 @end example
3245 @end defun
3247 @node Reset Configuration
3248 @chapter Reset Configuration
3249 @cindex Reset Configuration
3251 Every system configuration may require a different reset
3252 configuration. This can also be quite confusing.
3253 Resets also interact with @var{reset-init} event handlers,
3254 which do things like setting up clocks and DRAM, and
3255 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3256 They can also interact with JTAG routers.
3257 Please see the various board files for examples.
3259 @quotation Note
3260 To maintainers and integrators:
3261 Reset configuration touches several things at once.
3262 Normally the board configuration file
3263 should define it and assume that the JTAG adapter supports
3264 everything that's wired up to the board's JTAG connector.
3266 However, the target configuration file could also make note
3267 of something the silicon vendor has done inside the chip,
3268 which will be true for most (or all) boards using that chip.
3269 And when the JTAG adapter doesn't support everything, the
3270 user configuration file will need to override parts of
3271 the reset configuration provided by other files.
3272 @end quotation
3274 @section Types of Reset
3276 There are many kinds of reset possible through JTAG, but
3277 they may not all work with a given board and adapter.
3278 That's part of why reset configuration can be error prone.
3280 @itemize @bullet
3281 @item
3282 @emph{System Reset} ... the @emph{SRST} hardware signal
3283 resets all chips connected to the JTAG adapter, such as processors,
3284 power management chips, and I/O controllers. Normally resets triggered
3285 with this signal behave exactly like pressing a RESET button.
3286 @item
3287 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3288 just the TAP controllers connected to the JTAG adapter.
3289 Such resets should not be visible to the rest of the system; resetting a
3290 device's TAP controller just puts that controller into a known state.
3291 @item
3292 @emph{Emulation Reset} ... many devices can be reset through JTAG
3293 commands. These resets are often distinguishable from system
3294 resets, either explicitly (a "reset reason" register says so)
3295 or implicitly (not all parts of the chip get reset).
3296 @item
3297 @emph{Other Resets} ... system-on-chip devices often support
3298 several other types of reset.
3299 You may need to arrange that a watchdog timer stops
3300 while debugging, preventing a watchdog reset.
3301 There may be individual module resets.
3302 @end itemize
3304 In the best case, OpenOCD can hold SRST, then reset
3305 the TAPs via TRST and send commands through JTAG to halt the
3306 CPU at the reset vector before the 1st instruction is executed.
3307 Then when it finally releases the SRST signal, the system is
3308 halted under debugger control before any code has executed.
3309 This is the behavior required to support the @command{reset halt}
3310 and @command{reset init} commands; after @command{reset init} a
3311 board-specific script might do things like setting up DRAM.
3312 (@xref{resetcommand,,Reset Command}.)
3314 @anchor{srstandtrstissues}
3315 @section SRST and TRST Issues
3317 Because SRST and TRST are hardware signals, they can have a
3318 variety of system-specific constraints. Some of the most
3319 common issues are:
3321 @itemize @bullet
3323 @item @emph{Signal not available} ... Some boards don't wire
3324 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3325 support such signals even if they are wired up.
3326 Use the @command{reset_config} @var{signals} options to say
3327 when either of those signals is not connected.
3328 When SRST is not available, your code might not be able to rely
3329 on controllers having been fully reset during code startup.
3330 Missing TRST is not a problem, since JTAG-level resets can
3331 be triggered using with TMS signaling.
3333 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3334 adapter will connect SRST to TRST, instead of keeping them separate.
3335 Use the @command{reset_config} @var{combination} options to say
3336 when those signals aren't properly independent.
3338 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3339 delay circuit, reset supervisor, or on-chip features can extend
3340 the effect of a JTAG adapter's reset for some time after the adapter
3341 stops issuing the reset. For example, there may be chip or board
3342 requirements that all reset pulses last for at least a
3343 certain amount of time; and reset buttons commonly have
3344 hardware debouncing.
3345 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3346 commands to say when extra delays are needed.
3348 @item @emph{Drive type} ... Reset lines often have a pullup
3349 resistor, letting the JTAG interface treat them as open-drain
3350 signals. But that's not a requirement, so the adapter may need
3351 to use push/pull output drivers.
3352 Also, with weak pullups it may be advisable to drive
3353 signals to both levels (push/pull) to minimize rise times.
3354 Use the @command{reset_config} @var{trst_type} and
3355 @var{srst_type} parameters to say how to drive reset signals.
3357 @item @emph{Special initialization} ... Targets sometimes need
3358 special JTAG initialization sequences to handle chip-specific
3359 issues (not limited to errata).
3360 For example, certain JTAG commands might need to be issued while
3361 the system as a whole is in a reset state (SRST active)
3362 but the JTAG scan chain is usable (TRST inactive).
3363 Many systems treat combined assertion of SRST and TRST as a
3364 trigger for a harder reset than SRST alone.
3365 Such custom reset handling is discussed later in this chapter.
3366 @end itemize
3368 There can also be other issues.
3369 Some devices don't fully conform to the JTAG specifications.
3370 Trivial system-specific differences are common, such as
3371 SRST and TRST using slightly different names.
3372 There are also vendors who distribute key JTAG documentation for
3373 their chips only to developers who have signed a Non-Disclosure
3374 Agreement (NDA).
3376 Sometimes there are chip-specific extensions like a requirement to use
3377 the normally-optional TRST signal (precluding use of JTAG adapters which
3378 don't pass TRST through), or needing extra steps to complete a TAP reset.
3380 In short, SRST and especially TRST handling may be very finicky,
3381 needing to cope with both architecture and board specific constraints.
3383 @section Commands for Handling Resets
3385 @deffn {Command} adapter_nsrst_assert_width milliseconds
3386 Minimum amount of time (in milliseconds) OpenOCD should wait
3387 after asserting nSRST (active-low system reset) before
3388 allowing it to be deasserted.
3389 @end deffn
3391 @deffn {Command} adapter_nsrst_delay milliseconds
3392 How long (in milliseconds) OpenOCD should wait after deasserting
3393 nSRST (active-low system reset) before starting new JTAG operations.
3394 When a board has a reset button connected to SRST line it will
3395 probably have hardware debouncing, implying you should use this.
3396 @end deffn
3398 @deffn {Command} jtag_ntrst_assert_width milliseconds
3399 Minimum amount of time (in milliseconds) OpenOCD should wait
3400 after asserting nTRST (active-low JTAG TAP reset) before
3401 allowing it to be deasserted.
3402 @end deffn
3404 @deffn {Command} jtag_ntrst_delay milliseconds
3405 How long (in milliseconds) OpenOCD should wait after deasserting
3406 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3407 @end deffn
3409 @deffn {Command} reset_config mode_flag ...
3410 This command displays or modifies the reset configuration
3411 of your combination of JTAG board and target in target
3412 configuration scripts.
3414 Information earlier in this section describes the kind of problems
3415 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3416 As a rule this command belongs only in board config files,
3417 describing issues like @emph{board doesn't connect TRST};
3418 or in user config files, addressing limitations derived
3419 from a particular combination of interface and board.
3420 (An unlikely example would be using a TRST-only adapter
3421 with a board that only wires up SRST.)
3423 The @var{mode_flag} options can be specified in any order, but only one
3424 of each type -- @var{signals}, @var{combination}, @var{gates},
3425 @var{trst_type}, @var{srst_type} and @var{connect_type}
3426 -- may be specified at a time.
3427 If you don't provide a new value for a given type, its previous
3428 value (perhaps the default) is unchanged.
3429 For example, this means that you don't need to say anything at all about
3430 TRST just to declare that if the JTAG adapter should want to drive SRST,
3431 it must explicitly be driven high (@option{srst_push_pull}).
3433 @itemize
3434 @item
3435 @var{signals} can specify which of the reset signals are connected.
3436 For example, If the JTAG interface provides SRST, but the board doesn't
3437 connect that signal properly, then OpenOCD can't use it.
3438 Possible values are @option{none} (the default), @option{trst_only},
3439 @option{srst_only} and @option{trst_and_srst}.
3441 @quotation Tip
3442 If your board provides SRST and/or TRST through the JTAG connector,
3443 you must declare that so those signals can be used.
3444 @end quotation
3446 @item
3447 The @var{combination} is an optional value specifying broken reset
3448 signal implementations.
3449 The default behaviour if no option given is @option{separate},
3450 indicating everything behaves normally.
3451 @option{srst_pulls_trst} states that the
3452 test logic is reset together with the reset of the system (e.g. NXP
3453 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3454 the system is reset together with the test logic (only hypothetical, I
3455 haven't seen hardware with such a bug, and can be worked around).
3456 @option{combined} implies both @option{srst_pulls_trst} and
3457 @option{trst_pulls_srst}.
3459 @item
3460 The @var{gates} tokens control flags that describe some cases where
3461 JTAG may be unvailable during reset.
3462 @option{srst_gates_jtag} (default)
3463 indicates that asserting SRST gates the
3464 JTAG clock. This means that no communication can happen on JTAG
3465 while SRST is asserted.
3466 Its converse is @option{srst_nogate}, indicating that JTAG commands
3467 can safely be issued while SRST is active.
3469 @item
3470 The @var{connect_type} tokens control flags that describe some cases where
3471 SRST is asserted while connecting to the target. @option{srst_nogate}
3472 is required to use this option.
3473 @option{connect_deassert_srst} (default)
3474 indicates that SRST will not be asserted while connecting to the target.
3475 Its converse is @option{connect_assert_srst}, indicating that SRST will
3476 be asserted before any target connection.
3477 Only some targets support this feature, STM32 and STR9 are examples.
3478 This feature is useful if you are unable to connect to your target due
3479 to incorrect options byte config or illegal program execution.
3480 @end itemize
3482 The optional @var{trst_type} and @var{srst_type} parameters allow the
3483 driver mode of each reset line to be specified. These values only affect
3484 JTAG interfaces with support for different driver modes, like the Amontec
3485 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3486 relevant signal (TRST or SRST) is not connected.
3488 @itemize
3489 @item
3490 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3491 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3492 Most boards connect this signal to a pulldown, so the JTAG TAPs
3493 never leave reset unless they are hooked up to a JTAG adapter.
3495 @item
3496 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3497 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3498 Most boards connect this signal to a pullup, and allow the
3499 signal to be pulled low by various events including system
3500 powerup and pressing a reset button.
3501 @end itemize
3502 @end deffn
3504 @section Custom Reset Handling
3505 @cindex events
3507 OpenOCD has several ways to help support the various reset
3508 mechanisms provided by chip and board vendors.
3509 The commands shown in the previous section give standard parameters.
3510 There are also @emph{event handlers} associated with TAPs or Targets.
3511 Those handlers are Tcl procedures you can provide, which are invoked
3512 at particular points in the reset sequence.
3514 @emph{When SRST is not an option} you must set
3515 up a @code{reset-assert} event handler for your target.
3516 For example, some JTAG adapters don't include the SRST signal;
3517 and some boards have multiple targets, and you won't always
3518 want to reset everything at once.
3520 After configuring those mechanisms, you might still
3521 find your board doesn't start up or reset correctly.
3522 For example, maybe it needs a slightly different sequence
3523 of SRST and/or TRST manipulations, because of quirks that
3524 the @command{reset_config} mechanism doesn't address;
3525 or asserting both might trigger a stronger reset, which
3526 needs special attention.
3528 Experiment with lower level operations, such as @command{jtag_reset}
3529 and the @command{jtag arp_*} operations shown here,
3530 to find a sequence of operations that works.
3531 @xref{JTAG Commands}.
3532 When you find a working sequence, it can be used to override
3533 @command{jtag_init}, which fires during OpenOCD startup
3534 (@pxref{configurationstage,,Configuration Stage});
3535 or @command{init_reset}, which fires during reset processing.
3537 You might also want to provide some project-specific reset
3538 schemes. For example, on a multi-target board the standard
3539 @command{reset} command would reset all targets, but you
3540 may need the ability to reset only one target at time and
3541 thus want to avoid using the board-wide SRST signal.
3543 @deffn {Overridable Procedure} init_reset mode
3544 This is invoked near the beginning of the @command{reset} command,
3545 usually to provide as much of a cold (power-up) reset as practical.
3546 By default it is also invoked from @command{jtag_init} if
3547 the scan chain does not respond to pure JTAG operations.
3548 The @var{mode} parameter is the parameter given to the
3549 low level reset command (@option{halt},
3550 @option{init}, or @option{run}), @option{setup},
3551 or potentially some other value.
3553 The default implementation just invokes @command{jtag arp_init-reset}.
3554 Replacements will normally build on low level JTAG
3555 operations such as @command{jtag_reset}.
3556 Operations here must not address individual TAPs
3557 (or their associated targets)
3558 until the JTAG scan chain has first been verified to work.
3560 Implementations must have verified the JTAG scan chain before
3561 they return.
3562 This is done by calling @command{jtag arp_init}
3563 (or @command{jtag arp_init-reset}).
3564 @end deffn
3566 @deffn Command {jtag arp_init}
3567 This validates the scan chain using just the four
3568 standard JTAG signals (TMS, TCK, TDI, TDO).
3569 It starts by issuing a JTAG-only reset.
3570 Then it performs checks to verify that the scan chain configuration
3571 matches the TAPs it can observe.
3572 Those checks include checking IDCODE values for each active TAP,
3573 and verifying the length of their instruction registers using
3574 TAP @code{-ircapture} and @code{-irmask} values.
3575 If these tests all pass, TAP @code{setup} events are
3576 issued to all TAPs with handlers for that event.
3577 @end deffn
3579 @deffn Command {jtag arp_init-reset}
3580 This uses TRST and SRST to try resetting
3581 everything on the JTAG scan chain
3582 (and anything else connected to SRST).
3583 It then invokes the logic of @command{jtag arp_init}.
3584 @end deffn
3587 @node TAP Declaration
3588 @chapter TAP Declaration
3589 @cindex TAP declaration
3590 @cindex TAP configuration
3592 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3593 TAPs serve many roles, including:
3595 @itemize @bullet
3596 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3597 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3598 Others do it indirectly, making a CPU do it.
3599 @item @b{Program Download} Using the same CPU support GDB uses,
3600 you can initialize a DRAM controller, download code to DRAM, and then
3601 start running that code.
3602 @item @b{Boundary Scan} Most chips support boundary scan, which
3603 helps test for board assembly problems like solder bridges
3604 and missing connections.
3605 @end itemize
3607 OpenOCD must know about the active TAPs on your board(s).
3608 Setting up the TAPs is the core task of your configuration files.
3609 Once those TAPs are set up, you can pass their names to code
3610 which sets up CPUs and exports them as GDB targets,
3611 probes flash memory, performs low-level JTAG operations, and more.
3613 @section Scan Chains
3614 @cindex scan chain
3616 TAPs are part of a hardware @dfn{scan chain},
3617 which is a daisy chain of TAPs.
3618 They also need to be added to
3619 OpenOCD's software mirror of that hardware list,
3620 giving each member a name and associating other data with it.
3621 Simple scan chains, with a single TAP, are common in
3622 systems with a single microcontroller or microprocessor.
3623 More complex chips may have several TAPs internally.
3624 Very complex scan chains might have a dozen or more TAPs:
3625 several in one chip, more in the next, and connecting
3626 to other boards with their own chips and TAPs.
3628 You can display the list with the @command{scan_chain} command.
3629 (Don't confuse this with the list displayed by the @command{targets}
3630 command, presented in the next chapter.
3631 That only displays TAPs for CPUs which are configured as
3632 debugging targets.)
3633 Here's what the scan chain might look like for a chip more than one TAP:
3635 @verbatim
3636 TapName Enabled IdCode Expected IrLen IrCap IrMask
3637 -- ------------------ ------- ---------- ---------- ----- ----- ------
3638 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3639 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3640 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3641 @end verbatim
3643 OpenOCD can detect some of that information, but not all
3644 of it. @xref{autoprobing,,Autoprobing}.
3645 Unfortunately, those TAPs can't always be autoconfigured,
3646 because not all devices provide good support for that.
3647 JTAG doesn't require supporting IDCODE instructions, and
3648 chips with JTAG routers may not link TAPs into the chain
3649 until they are told to do so.
3651 The configuration mechanism currently supported by OpenOCD
3652 requires explicit configuration of all TAP devices using
3653 @command{jtag newtap} commands, as detailed later in this chapter.
3654 A command like this would declare one tap and name it @code{chip1.cpu}:
3656 @example
3657 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3658 @end example
3660 Each target configuration file lists the TAPs provided
3661 by a given chip.
3662 Board configuration files combine all the targets on a board,
3663 and so forth.
3664 Note that @emph{the order in which TAPs are declared is very important.}
3665 That declaration order must match the order in the JTAG scan chain,
3666 both inside a single chip and between them.
3667 @xref{faqtaporder,,FAQ TAP Order}.
3669 For example, the ST Microsystems STR912 chip has
3670 three separate TAPs@footnote{See the ST
3671 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3672 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3673 @url{}}.
3674 To configure those taps, @file{target/str912.cfg}
3675 includes commands something like this:
3677 @example
3678 jtag newtap str912 flash ... params ...
3679 jtag newtap str912 cpu ... params ...
3680 jtag newtap str912 bs ... params ...
3681 @end example
3683 Actual config files typically use a variable such as @code{$_CHIPNAME}
3684 instead of literals like @option{str912}, to support more than one chip
3685 of each type. @xref{Config File Guidelines}.
3687 @deffn Command {jtag names}
3688 Returns the names of all current TAPs in the scan chain.
3689 Use @command{jtag cget} or @command{jtag tapisenabled}
3690 to examine attributes and state of each TAP.
3691 @example
3692 foreach t [jtag names] @{
3693 puts [format "TAP: %s\n" $t]
3694 @}
3695 @end example
3696 @end deffn
3698 @deffn Command {scan_chain}
3699 Displays the TAPs in the scan chain configuration,
3700 and their status.
3701 The set of TAPs listed by this command is fixed by
3702 exiting the OpenOCD configuration stage,
3703 but systems with a JTAG router can
3704 enable or disable TAPs dynamically.
3705 @end deffn
3707 @c FIXME! "jtag cget" should be able to return all TAP
3708 @c attributes, like "$target_name cget" does for targets.
3710 @c Probably want "jtag eventlist", and a "tap-reset" event
3711 @c (on entry to RESET state).
3713 @section TAP Names
3714 @cindex dotted name
3716 When TAP objects are declared with @command{jtag newtap},
3717 a @dfn{} is created for the TAP, combining the
3718 name of a module (usually a chip) and a label for the TAP.
3719 For example: @code{xilinx.tap}, @code{str912.flash},
3720 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3721 Many other commands use that to manipulate or
3722 refer to the TAP. For example, CPU configuration uses the
3723 name, as does declaration of NAND or NOR flash banks.
3725 The components of a dotted name should follow ``C'' symbol
3726 name rules: start with an alphabetic character, then numbers
3727 and underscores are OK; while others (including dots!) are not.
3729 @section TAP Declaration Commands
3731 @c shouldn't this be(come) a {Config Command}?
3732 @deffn Command {jtag newtap} chipname tapname configparams...
3733 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3734 and configured according to the various @var{configparams}.
3736 The @var{chipname} is a symbolic name for the chip.
3737 Conventionally target config files use @code{$_CHIPNAME},
3738 defaulting to the model name given by the chip vendor but
3739 overridable.
3741 @cindex TAP naming convention
3742 The @var{tapname} reflects the role of that TAP,
3743 and should follow this convention:
3745 @itemize @bullet
3746 @item @code{bs} -- For boundary scan if this is a separate TAP;
3747 @item @code{cpu} -- The main CPU of the chip, alternatively
3748 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3749 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3750 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3751 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3752 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3753 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3754 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3755 with a single TAP;
3756 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3757 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3758 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3759 a JTAG TAP; that TAP should be named @code{sdma}.
3760 @end itemize
3762 Every TAP requires at least the following @var{configparams}:
3764 @itemize @bullet
3765 @item @code{-irlen} @var{NUMBER}
3766 @*The length in bits of the
3767 instruction register, such as 4 or 5 bits.
3768 @end itemize
3770 A TAP may also provide optional @var{configparams}:
3772 @itemize @bullet
3773 @item @code{-disable} (or @code{-enable})
3774 @*Use the @code{-disable} parameter to flag a TAP which is not
3775 linked into the scan chain after a reset using either TRST
3776 or the JTAG state machine's @sc{reset} state.
3777 You may use @code{-enable} to highlight the default state
3778 (the TAP is linked in).
3779 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3780 @item @code{-expected-id} @var{NUMBER}
3781 @*A non-zero @var{number} represents a 32-bit IDCODE
3782 which you expect to find when the scan chain is examined.
3783 These codes are not required by all JTAG devices.
3784 @emph{Repeat the option} as many times as required if more than one
3785 ID code could appear (for example, multiple versions).
3786 Specify @var{number} as zero to suppress warnings about IDCODE
3787 values that were found but not included in the list.
3789 Provide this value if at all possible, since it lets OpenOCD
3790 tell when the scan chain it sees isn't right. These values
3791 are provided in vendors' chip documentation, usually a technical
3792 reference manual. Sometimes you may need to probe the JTAG
3793 hardware to find these values.
3794 @xref{autoprobing,,Autoprobing}.
3795 @item @code{-ignore-version}
3796 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3797 option. When vendors put out multiple versions of a chip, or use the same
3798 JTAG-level ID for several largely-compatible chips, it may be more practical
3799 to ignore the version field than to update config files to handle all of
3800 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3801 @item @code{-ircapture} @var{NUMBER}
3802 @*The bit pattern loaded by the TAP into the JTAG shift register
3803 on entry to the @sc{ircapture} state, such as 0x01.
3804 JTAG requires the two LSBs of this value to be 01.
3805 By default, @code{-ircapture} and @code{-irmask} are set
3806 up to verify that two-bit value. You may provide
3807 additional bits if you know them, or indicate that
3808 a TAP doesn't conform to the JTAG specification.
3809 @item @code{-irmask} @var{NUMBER}
3810 @*A mask used with @code{-ircapture}
3811 to verify that instruction scans work correctly.
3812 Such scans are not used by OpenOCD except to verify that
3813 there seems to be no problems with JTAG scan chain operations.
3814 @end itemize
3815 @end deffn
3817 @section Other TAP commands
3819 @deffn Command {jtag cget} @option{-event} event_name
3820 @deffnx Command {jtag configure} @option{-event} event_name handler
3821 At this writing this TAP attribute
3822 mechanism is used only for event handling.
3823 (It is not a direct analogue of the @code{cget}/@code{configure}
3824 mechanism for debugger targets.)
3825 See the next section for information about the available events.
3827 The @code{configure} subcommand assigns an event handler,
3828 a TCL string which is evaluated when the event is triggered.
3829 The @code{cget} subcommand returns that handler.
3830 @end deffn
3832 @section TAP Events
3833 @cindex events
3834 @cindex TAP events
3836 OpenOCD includes two event mechanisms.
3837 The one presented here applies to all JTAG TAPs.
3838 The other applies to debugger targets,
3839 which are associated with certain TAPs.
3841 The TAP events currently defined are:
3843 @itemize @bullet
3844 @item @b{post-reset}
3845 @* The TAP has just completed a JTAG reset.
3846 The tap may still be in the JTAG @sc{reset} state.
3847 Handlers for these events might perform initialization sequences
3848 such as issuing TCK cycles, TMS sequences to ensure
3849 exit from the ARM SWD mode, and more.
3851 Because the scan chain has not yet been verified, handlers for these events
3852 @emph{should not issue commands which scan the JTAG IR or DR registers}
3853 of any particular target.
3854 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3855 @item @b{setup}
3856 @* The scan chain has been reset and verified.
3857 This handler may enable TAPs as needed.
3858 @item @b{tap-disable}
3859 @* The TAP needs to be disabled. This handler should
3860 implement @command{jtag tapdisable}
3861 by issuing the relevant JTAG commands.
3862 @item @b{tap-enable}
3863 @* The TAP needs to be enabled. This handler should
3864 implement @command{jtag tapenable}
3865 by issuing the relevant JTAG commands.
3866 @end itemize
3868 If you need some action after each JTAG reset which isn't actually
3869 specific to any TAP (since you can't yet trust the scan chain's
3870 contents to be accurate), you might:
3872 @example
3873 jtag configure CHIP.jrc -event post-reset @{
3874 echo "JTAG Reset done"
3875 ... non-scan jtag operations to be done after reset
3876 @}
3877 @end example
3880 @anchor{enablinganddisablingtaps}
3881 @section Enabling and Disabling TAPs
3882 @cindex JTAG Route Controller
3883 @cindex jrc
3885 In some systems, a @dfn{JTAG Route Controller} (JRC)
3886 is used to enable and/or disable specific JTAG TAPs.
3887 Many ARM-based chips from Texas Instruments include
3888 an ``ICEPick'' module, which is a JRC.
3889 Such chips include DaVinci and OMAP3 processors.
3891 A given TAP may not be visible until the JRC has been
3892 told to link it into the scan chain; and if the JRC
3893 has been told to unlink that TAP, it will no longer
3894 be visible.
3895 Such routers address problems that JTAG ``bypass mode''
3896 ignores, such as:
3898 @itemize
3899 @item The scan chain can only go as fast as its slowest TAP.
3900 @item Having many TAPs slows instruction scans, since all
3901 TAPs receive new instructions.
3902 @item TAPs in the scan chain must be powered up, which wastes
3903 power and prevents debugging some power management mechanisms.
3904 @end itemize
3906 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3907 as implied by the existence of JTAG routers.
3908 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3909 does include a kind of JTAG router functionality.
3911 @c (a) currently the event handlers don't seem to be able to
3912 @c fail in a way that could lead to no-change-of-state.
3914 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3915 shown below, and is implemented using TAP event handlers.
3916 So for example, when defining a TAP for a CPU connected to
3917 a JTAG router, your @file{target.cfg} file
3918 should define TAP event handlers using
3919 code that looks something like this:
3921 @example
3922 jtag configure CHIP.cpu -event tap-enable @{
3923 ... jtag operations using CHIP.jrc
3924 @}
3925 jtag configure CHIP.cpu -event tap-disable @{
3926 ... jtag operations using CHIP.jrc
3927 @}
3928 @end example
3930 Then you might want that CPU's TAP enabled almost all the time:
3932 @example
3933 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3934 @end example
3936 Note how that particular setup event handler declaration
3937 uses quotes to evaluate @code{$CHIP} when the event is configured.
3938 Using brackets @{ @} would cause it to be evaluated later,
3939 at runtime, when it might have a different value.
3941 @deffn Command {jtag tapdisable}
3942 If necessary, disables the tap
3943 by sending it a @option{tap-disable} event.
3944 Returns the string "1" if the tap
3945 specified by @var{} is enabled,
3946 and "0" if it is disabled.
3947 @end deffn
3949 @deffn Command {jtag tapenable}
3950 If necessary, enables the tap
3951 by sending it a @option{tap-enable} event.
3952 Returns the string "1" if the tap
3953 specified by @var{} is enabled,
3954 and "0" if it is disabled.
3955 @end deffn
3957 @deffn Command {jtag tapisenabled}
3958 Returns the string "1" if the tap
3959 specified by @var{} is enabled,
3960 and "0" if it is disabled.
3962 @quotation Note
3963 Humans will find the @command{scan_chain} command more helpful
3964 for querying the state of the JTAG taps.
3965 @end quotation
3966 @end deffn
3968 @anchor{autoprobing}
3969 @section Autoprobing
3970 @cindex autoprobe
3971 @cindex JTAG autoprobe
3973 TAP configuration is the first thing that needs to be done
3974 after interface and reset configuration. Sometimes it's
3975 hard finding out what TAPs exist, or how they are identified.
3976 Vendor documentation is not always easy to find and use.
3978 To help you get past such problems, OpenOCD has a limited
3979 @emph{autoprobing} ability to look at the scan chain, doing
3980 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3981 To use this mechanism, start the OpenOCD server with only data
3982 that configures your JTAG interface, and arranges to come up
3983 with a slow clock (many devices don't support fast JTAG clocks
3984 right when they come out of reset).
3986 For example, your @file{openocd.cfg} file might have:
3988 @example
3989 source [find interface/olimex-arm-usb-tiny-h.cfg]
3990 reset_config trst_and_srst
3991 jtag_rclk 8
3992 @end example
3994 When you start the server without any TAPs configured, it will
3995 attempt to autoconfigure the TAPs. There are two parts to this:
3997 @enumerate
3998 @item @emph{TAP discovery} ...
3999 After a JTAG reset (sometimes a system reset may be needed too),
4000 each TAP's data registers will hold the contents of either the
4001 IDCODE or BYPASS register.
4002 If JTAG communication is working, OpenOCD will see each TAP,
4003 and report what @option{-expected-id} to use with it.
4004 @item @emph{IR Length discovery} ...
4005 Unfortunately JTAG does not provide a reliable way to find out
4006 the value of the @option{-irlen} parameter to use with a TAP
4007 that is discovered.
4008 If OpenOCD can discover the length of a TAP's instruction
4009 register, it will report it.
4010 Otherwise you may need to consult vendor documentation, such
4011 as chip data sheets or BSDL files.
4012 @end enumerate
4014 In many cases your board will have a simple scan chain with just
4015 a single device. Here's what OpenOCD reported with one board
4016 that's a bit more complex:
4018 @example
4019 clock speed 8 kHz
4020 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4021 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4022 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4023 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4024 AUTO auto0.tap - use "... -irlen 4"
4025 AUTO auto1.tap - use "... -irlen 4"
4026 AUTO auto2.tap - use "... -irlen 6"
4027 no gdb ports allocated as no target has been specified
4028 @end example
4030 Given that information, you should be able to either find some existing
4031 config files to use, or create your own. If you create your own, you
4032 would configure from the bottom up: first a @file{target.cfg} file
4033 with these TAPs, any targets associated with them, and any on-chip
4034 resources; then a @file{board.cfg} with off-chip resources, clocking,
4035 and so forth.
4037 @node CPU Configuration
4038 @chapter CPU Configuration
4039 @cindex GDB target
4041 This chapter discusses how to set up GDB debug targets for CPUs.
4042 You can also access these targets without GDB
4043 (@pxref{Architecture and Core Commands},
4044 and @ref{targetstatehandling,,Target State handling}) and
4045 through various kinds of NAND and NOR flash commands.
4046 If you have multiple CPUs you can have multiple such targets.
4048 We'll start by looking at how to examine the targets you have,
4049 then look at how to add one more target and how to configure it.
4051 @section Target List
4052 @cindex target, current
4053 @cindex target, list
4055 All targets that have been set up are part of a list,
4056 where each member has a name.
4057 That name should normally be the same as the TAP name.
4058 You can display the list with the @command{targets}
4059 (plural!) command.
4060 This display often has only one CPU; here's what it might
4061 look like with more than one:
4062 @verbatim
4063 TargetName Type Endian TapName State
4064 -- ------------------ ---------- ------ ------------------ ------------
4065 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4066 1 MyTarget cortex_m little tap-disabled
4067 @end verbatim
4069 One member of that list is the @dfn{current target}, which
4070 is implicitly referenced by many commands.
4071 It's the one marked with a @code{*} near the target name.
4072 In particular, memory addresses often refer to the address
4073 space seen by that current target.
4074 Commands like @command{mdw} (memory display words)
4075 and @command{flash erase_address} (erase NOR flash blocks)
4076 are examples; and there are many more.
4078 Several commands let you examine the list of targets:
4080 @deffn Command {target count}
4081 @emph{Note: target numbers are deprecated; don't use them.
4082 They will be removed shortly after August 2010, including this command.
4083 Iterate target using @command{target names}, not by counting.}
4085 Returns the number of targets, @math{N}.
4086 The highest numbered target is @math{N - 1}.
4087 @example
4088 set c [target count]
4089 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
4090 # Assuming you have created this function
4091 print_target_details $x
4092 @}
4093 @end example
4094 @end deffn
4096 @deffn Command {target current}
4097 Returns the name of the current target.
4098 @end deffn
4100 @deffn Command {target names}
4101 Lists the names of all current targets in the list.
4102 @example
4103 foreach t [target names] @{
4104 puts [format "Target: %s\n" $t]
4105 @}
4106 @end example
4107 @end deffn
4109 @deffn Command {target number} number
4110 @emph{Note: target numbers are deprecated; don't use them.
4111 They will be removed shortly after August 2010, including this command.}
4113 The list of targets is numbered starting at zero.
4114 This command returns the name of the target at index @var{number}.
4115 @example
4116 set thename [target number $x]
4117 puts [format "Target %d is: %s\n" $x $thename]
4118 @end example
4119 @end deffn
4121 @c yep, "target list" would have been better.
4122 @c plus maybe "target setdefault".
4124 @deffn Command targets [name]
4125 @emph{Note: the name of this command is plural. Other target
4126 command names are singular.}
4128 With no parameter, this command displays a table of all known
4129 targets in a user friendly form.
4131 With a parameter, this command sets the current target to
4132 the given target with the given @var{name}; this is
4133 only relevant on boards which have more than one target.
4134 @end deffn
4136 @section Target CPU Types and Variants
4137 @cindex target type
4138 @cindex CPU type
4139 @cindex CPU variant
4141 Each target has a @dfn{CPU type}, as shown in the output of
4142 the @command{targets} command. You need to specify that type
4143 when calling @command{target create}.
4144 The CPU type indicates more than just the instruction set.
4145 It also indicates how that instruction set is implemented,
4146 what kind of debug support it integrates,
4147 whether it has an MMU (and if so, what kind),
4148 what core-specific commands may be available
4149 (@pxref{Architecture and Core Commands}),
4150 and more.
4152 For some CPU types, OpenOCD also defines @dfn{variants} which
4153 indicate differences that affect their handling.
4154 For example, a particular implementation bug might need to be
4155 worked around in some chip versions.
4157 It's easy to see what target types are supported,
4158 since there's a command to list them.
4159 However, there is currently no way to list what target variants
4160 are supported (other than by reading the OpenOCD source code).
4162 @anchor{targettypes}
4163 @deffn Command {target types}
4164 Lists all supported target types.
4165 At this writing, the supported CPU types and variants are:
4167 @itemize @bullet
4168 @item @code{arm11} -- this is a generation of ARMv6 cores
4169 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4170 @item @code{arm7tdmi} -- this is an ARMv4 core
4171 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4172 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4173 @item @code{arm966e} -- this is an ARMv5 core
4174 @item @code{arm9tdmi} -- this is an ARMv4 core