[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * NAND Flash Commands:: NAND Flash Commands
77 * PLD/FPGA Commands:: PLD/FPGA Commands
78 * General Commands:: General Commands
79 * Architecture and Core Commands:: Architecture and Core Commands
80 * JTAG Commands:: JTAG Commands
81 * Boundary Scan Commands:: Boundary Scan Commands
82 * TFTP:: TFTP
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
95 @end menu
97 @node About
98 @unnumbered About
99 @cindex about
101 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
102 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
105 around the world.
107 @section What is OpenOCD?
108 @cindex TAP
109 @cindex JTAG
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
113 devices.
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board can be directly connected to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
140 scan operations.
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD only supports
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
154 based, parallel port based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
159 Cortex-M3 (Stellaris LM3, ST STM32 and Energy Micro EFM32) based cores to be
160 debugged via the GDB protocol.
162 @b{Flash Programing:} Flash writing is supported for external CFI
163 compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) controller is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{http://openocd.sourceforge.net/}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{http://openocd.sourceforge.net/doc/html/index.html}
182 PDF form is likewise published at:
184 @uref{http://openocd.sourceforge.net/doc/pdf/openocd.pdf}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
203 @section OpenOCD IRC
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
208 @node Developers
209 @chapter OpenOCD Developer Resources
210 @cindex developers
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD GIT Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a GIT repository hosted at SourceForge. The repository URL is:
225 @uref{git://git.code.sf.net/p/openocd/code}
227 or via http
229 @uref{http://git.code.sf.net/p/openocd/code}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{http://repo.or.cz/r/openocd.git}
235 With standard GIT tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a GIT client:
241 @uref{http://repo.or.cz/w/openocd.git}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{http://openocd.sourceforge.net/doc/doxygen/html/index.html}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration in the top of the source tree.
264 @section OpenOCD Developer Mailing List
266 The OpenOCD Developer Mailing List provides the primary means of
267 communication between developers:
269 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
271 Discuss and submit patches to this list.
272 The @file{HACKING} file contains basic information about how
273 to prepare patches.
275 @section OpenOCD Bug Database
277 During the 0.4.x release cycle the OpenOCD project team began
278 using Trac for its bug database:
280 @uref{https://sourceforge.net/apps/trac/openocd}
283 @node Debug Adapter Hardware
284 @chapter Debug Adapter Hardware
285 @cindex dongles
286 @cindex FTDI
287 @cindex wiggler
288 @cindex zy1000
289 @cindex printer port
290 @cindex USB Adapter
291 @cindex RTCK
293 Defined: @b{dongle}: A small device that plugins into a computer and serves as
294 an adapter .... [snip]
296 In the OpenOCD case, this generally refers to @b{a small adapter} that
297 attaches to your computer via USB or the Parallel Printer Port. One
298 exception is the Zylin ZY1000, packaged as a small box you attach via
299 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
300 require any drivers to be installed on the developer PC. It also has
301 a built in web interface. It supports RTCK/RCLK or adaptive clocking
302 and has a built in relay to power cycle targets remotely.
305 @section Choosing a Dongle
307 There are several things you should keep in mind when choosing a dongle.
309 @enumerate
310 @item @b{Transport} Does it support the kind of communication that you need?
311 OpenOCD focusses mostly on JTAG. Your version may also support
312 other ways to communicate with target devices.
313 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
314 Does your dongle support it? You might need a level converter.
315 @item @b{Pinout} What pinout does your target board use?
316 Does your dongle support it? You may be able to use jumper
317 wires, or an "octopus" connector, to convert pinouts.
318 @item @b{Connection} Does your computer have the USB, printer, or
319 Ethernet port needed?
320 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
321 RTCK support? Also known as ``adaptive clocking''
322 @end enumerate
324 @section Stand-alone JTAG Probe
326 The ZY1000 from Ultimate Solutions is technically not a dongle but a
327 stand-alone JTAG probe that unlikemost dongles doesn’t require any drivers
328 running on the developers host computer.
329 Once installed on a network using DHCP or a static IP assignment, users can
330 access the ZY1000 probe locally or remotely from any host with access to the
331 IP address assigned to the probe.
332 The ZY1000 provides an intuitive web interface with direct access to the
333 OpenOCD debugger.
334 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
335 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
336 the target.
337 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
338 to power cycle the target remotely.
340 For more information, visit:
342 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/33-zylin-zy1000-jtag-probe}
344 @section USB FT2232 Based
346 There are many USB JTAG dongles on the market, many of them are based
347 on a chip from ``Future Technology Devices International'' (FTDI)
348 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
349 See: @url{http://www.ftdichip.com} for more information.
350 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
351 chips are starting to become available in JTAG adapters. Around 2012 a new
352 variant appeared - FT232H - this is a single-channel version of FT2232H.
353 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
354 clocking.)
356 The FT2232 chips are flexible enough to support some other
357 transport options, such as SWD or the SPI variants used to
358 program some chips. They have two communications channels,
359 and one can be used for a UART adapter at the same time the
360 other one is used to provide a debug adapter.
362 Also, some development boards integrate an FT2232 chip to serve as
363 a built-in low cost debug adapter and usb-to-serial solution.
365 @itemize @bullet
366 @item @b{usbjtag}
367 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
368 @item @b{jtagkey}
369 @* See: @url{http://www.amontec.com/jtagkey.shtml}
370 @item @b{jtagkey2}
371 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
372 @item @b{oocdlink}
373 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
374 @item @b{signalyzer}
375 @* See: @url{http://www.signalyzer.com}
376 @item @b{Stellaris Eval Boards}
377 @* See: @url{http://www.ti.com} - The Stellaris eval boards
378 bundle FT2232-based JTAG and SWD support, which can be used to debug
379 the Stellaris chips. Using separate JTAG adapters is optional.
380 These boards can also be used in a "pass through" mode as JTAG adapters
381 to other target boards, disabling the Stellaris chip.
382 @item @b{TI/Luminary ICDI}
383 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
384 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
385 Evaluation Kits. Like the non-detachable FT2232 support on the other
386 Stellaris eval boards, they can be used to debug other target boards.
387 @item @b{olimex-jtag}
388 @* See: @url{http://www.olimex.com}
389 @item @b{Flyswatter/Flyswatter2}
390 @* See: @url{http://www.tincantools.com}
391 @item @b{turtelizer2}
392 @* See:
393 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
394 @url{http://www.ethernut.de}
395 @item @b{comstick}
396 @* Link: @url{http://www.hitex.com/index.php?id=383}
397 @item @b{stm32stick}
398 @* Link @url{http://www.hitex.com/stm32-stick}
399 @item @b{axm0432_jtag}
400 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
401 to be available anymore as of April 2012.
402 @item @b{cortino}
403 @* Link @url{http://www.hitex.com/index.php?id=cortino}
404 @item @b{dlp-usb1232h}
405 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
406 @item @b{digilent-hs1}
407 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
408 @item @b{opendous}
409 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
410 (OpenHardware).
411 @item @b{JTAG-lock-pick Tiny 2}
412 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
414 @item @b{GW16042}
415 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
416 FT2232H-based
418 @end itemize
419 @section USB-JTAG / Altera USB-Blaster compatibles
421 These devices also show up as FTDI devices, but are not
422 protocol-compatible with the FT2232 devices. They are, however,
423 protocol-compatible among themselves. USB-JTAG devices typically consist
424 of a FT245 followed by a CPLD that understands a particular protocol,
425 or emulate this protocol using some other hardware.
427 They may appear under different USB VID/PID depending on the particular
428 product. The driver can be configured to search for any VID/PID pair
429 (see the section on driver commands).
431 @itemize
432 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
433 @* Link: @url{http://ixo-jtag.sourceforge.net/}
434 @item @b{Altera USB-Blaster}
435 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
436 @end itemize
438 @section USB JLINK based
439 There are several OEM versions of the Segger @b{JLINK} adapter. It is
440 an example of a micro controller based JTAG adapter, it uses an
441 AT91SAM764 internally.
443 @itemize @bullet
444 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
445 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
446 @item @b{SEGGER JLINK}
447 @* Link: @url{http://www.segger.com/jlink.html}
448 @item @b{IAR J-Link}
449 @* Link: @url{http://www.iar.com/en/products/hardware-debug-probes/iar-j-link/}
450 @end itemize
452 @section USB RLINK based
453 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
454 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
455 SWD and not JTAG, thus not supported.
457 @itemize @bullet
458 @item @b{Raisonance RLink}
459 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
460 @item @b{STM32 Primer}
461 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
462 @item @b{STM32 Primer2}
463 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
464 @end itemize
466 @section USB ST-LINK based
467 ST Micro has an adapter called @b{ST-LINK}.
468 They only work with ST Micro chips, notably STM32 and STM8.
470 @itemize @bullet
471 @item @b{ST-LINK}
472 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
473 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
474 @item @b{ST-LINK/V2}
475 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
476 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
477 @end itemize
479 For info the original ST-LINK enumerates using the mass storage usb class, however
480 it's implementation is completely broken. The result is this causes issues under linux.
481 The simplest solution is to get linux to ignore the ST-LINK using one of the following methods:
482 @itemize @bullet
483 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
484 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
485 @end itemize
487 @section USB TI/Stellaris ICDI based
488 Texas Instruments has an adapter called @b{ICDI}.
489 It is not to be confused with the FTDI based adapters that were originally fitted to their
490 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
492 @section USB Other
493 @itemize @bullet
494 @item @b{USBprog}
495 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
497 @item @b{USB - Presto}
498 @* Link: @url{http://tools.asix.net/prg_presto.htm}
500 @item @b{Versaloon-Link}
501 @* Link: @url{http://www.versaloon.com}
503 @item @b{ARM-JTAG-EW}
504 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
506 @item @b{Buspirate}
507 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
509 @item @b{opendous}
510 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
512 @item @b{estick}
513 @* Link: @url{http://code.google.com/p/estick-jtag/}
515 @item @b{Keil ULINK v1}
516 @* Link: @url{http://www.keil.com/ulink1/}
517 @end itemize
519 @section IBM PC Parallel Printer Port Based
521 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
522 and the Macraigor Wiggler. There are many clones and variations of
523 these on the market.
525 Note that parallel ports are becoming much less common, so if you
526 have the choice you should probably avoid these adapters in favor
527 of USB-based ones.
529 @itemize @bullet
531 @item @b{Wiggler} - There are many clones of this.
532 @* Link: @url{http://www.macraigor.com/wiggler.htm}
534 @item @b{DLC5} - From XILINX - There are many clones of this
535 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
536 produced, PDF schematics are easily found and it is easy to make.
538 @item @b{Amontec - JTAG Accelerator}
539 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
541 @item @b{Wiggler2}
542 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
544 @item @b{Wiggler_ntrst_inverted}
545 @* Yet another variation - See the source code, src/jtag/parport.c
547 @item @b{old_amt_wiggler}
548 @* Unknown - probably not on the market today
550 @item @b{arm-jtag}
551 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
553 @item @b{chameleon}
554 @* Link: @url{http://www.amontec.com/chameleon.shtml}
556 @item @b{Triton}
557 @* Unknown.
559 @item @b{Lattice}
560 @* ispDownload from Lattice Semiconductor
561 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
563 @item @b{flashlink}
564 @* From ST Microsystems;
565 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
567 @end itemize
569 @section Other...
570 @itemize @bullet
572 @item @b{ep93xx}
573 @* An EP93xx based Linux machine using the GPIO pins directly.
575 @item @b{at91rm9200}
576 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
578 @item @b{bcm2835gpio}
579 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
581 @item @b{jtag_vpi}
582 @* A JTAG driver acting as a client for the JTAG VPI server interface.
583 @* Link: @url{http://github.com/fjullien/jtag_vpi}
585 @end itemize
587 @node About Jim-Tcl
588 @chapter About Jim-Tcl
589 @cindex Jim-Tcl
590 @cindex tcl
592 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
593 This programming language provides a simple and extensible
594 command interpreter.
596 All commands presented in this Guide are extensions to Jim-Tcl.
597 You can use them as simple commands, without needing to learn
598 much of anything about Tcl.
599 Alternatively, can write Tcl programs with them.
601 You can learn more about Jim at its website, @url{http://jim.berlios.de}.
602 There is an active and responsive community, get on the mailing list
603 if you have any questions. Jim-Tcl maintainers also lurk on the
604 OpenOCD mailing list.
606 @itemize @bullet
607 @item @b{Jim vs. Tcl}
608 @* Jim-Tcl is a stripped down version of the well known Tcl language,
609 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
610 fewer features. Jim-Tcl is several dozens of .C files and .H files and
611 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
612 4.2 MB .zip file containing 1540 files.
614 @item @b{Missing Features}
615 @* Our practice has been: Add/clone the real Tcl feature if/when
616 needed. We welcome Jim-Tcl improvements, not bloat. Also there
617 are a large number of optional Jim-Tcl features that are not
618 enabled in OpenOCD.
620 @item @b{Scripts}
621 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
622 command interpreter today is a mixture of (newer)
623 Jim-Tcl commands, and (older) the orginal command interpreter.
625 @item @b{Commands}
626 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
627 can type a Tcl for() loop, set variables, etc.
628 Some of the commands documented in this guide are implemented
629 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
631 @item @b{Historical Note}
632 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
633 before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
634 as a git submodule, which greatly simplified upgrading Jim Tcl
635 to benefit from new features and bugfixes in Jim Tcl.
637 @item @b{Need a crash course in Tcl?}
638 @*@xref{Tcl Crash Course}.
639 @end itemize
641 @node Running
642 @chapter Running
643 @cindex command line options
644 @cindex logfile
645 @cindex directory search
647 Properly installing OpenOCD sets up your operating system to grant it access
648 to the debug adapters. On Linux, this usually involves installing a file
649 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
650 complex and confusing driver configuration for every peripheral. Such issues
651 are unique to each operating system, and are not detailed in this User's Guide.
653 Then later you will invoke the OpenOCD server, with various options to
654 tell it how each debug session should work.
655 The @option{--help} option shows:
656 @verbatim
657 bash$ openocd --help
659 --help | -h display this help
660 --version | -v display OpenOCD version
661 --file | -f use configuration file <name>
662 --search | -s dir to search for config files and scripts
663 --debug | -d set debug level <0-3>
664 --log_output | -l redirect log output to file <name>
665 --command | -c run <command>
666 @end verbatim
668 If you don't give any @option{-f} or @option{-c} options,
669 OpenOCD tries to read the configuration file @file{openocd.cfg}.
670 To specify one or more different
671 configuration files, use @option{-f} options. For example:
673 @example
674 openocd -f config1.cfg -f config2.cfg -f config3.cfg
675 @end example
677 Configuration files and scripts are searched for in
678 @enumerate
679 @item the current directory,
680 @item any search dir specified on the command line using the @option{-s} option,
681 @item any search dir specified using the @command{add_script_search_dir} command,
682 @item @file{$HOME/.openocd} (not on Windows),
683 @item the site wide script library @file{$pkgdatadir/site} and
684 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
685 @end enumerate
686 The first found file with a matching file name will be used.
688 @quotation Note
689 Don't try to use configuration script names or paths which
690 include the "#" character. That character begins Tcl comments.
691 @end quotation
693 @section Simple setup, no customization
695 In the best case, you can use two scripts from one of the script
696 libraries, hook up your JTAG adapter, and start the server ... and
697 your JTAG setup will just work "out of the box". Always try to
698 start by reusing those scripts, but assume you'll need more
699 customization even if this works. @xref{OpenOCD Project Setup}.
701 If you find a script for your JTAG adapter, and for your board or
702 target, you may be able to hook up your JTAG adapter then start
703 the server like:
705 @example
706 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
707 @end example
709 You might also need to configure which reset signals are present,
710 using @option{-c 'reset_config trst_and_srst'} or something similar.
711 If all goes well you'll see output something like
713 @example
714 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
715 For bug reports, read
716 http://openocd.sourceforge.net/doc/doxygen/bugs.html
717 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
718 (mfg: 0x23b, part: 0xba00, ver: 0x3)
719 @end example
721 Seeing that "tap/device found" message, and no warnings, means
722 the JTAG communication is working. That's a key milestone, but
723 you'll probably need more project-specific setup.
725 @section What OpenOCD does as it starts
727 OpenOCD starts by processing the configuration commands provided
728 on the command line or, if there were no @option{-c command} or
729 @option{-f file.cfg} options given, in @file{openocd.cfg}.
730 @xref{configurationstage,,Configuration Stage}.
731 At the end of the configuration stage it verifies the JTAG scan
732 chain defined using those commands; your configuration should
733 ensure that this always succeeds.
734 Normally, OpenOCD then starts running as a daemon.
735 Alternatively, commands may be used to terminate the configuration
736 stage early, perform work (such as updating some flash memory),
737 and then shut down without acting as a daemon.
739 Once OpenOCD starts running as a daemon, it waits for connections from
740 clients (Telnet, GDB, Other) and processes the commands issued through
741 those channels.
743 If you are having problems, you can enable internal debug messages via
744 the @option{-d} option.
746 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
747 @option{-c} command line switch.
749 To enable debug output (when reporting problems or working on OpenOCD
750 itself), use the @option{-d} command line switch. This sets the
751 @option{debug_level} to "3", outputting the most information,
752 including debug messages. The default setting is "2", outputting only
753 informational messages, warnings and errors. You can also change this
754 setting from within a telnet or gdb session using @command{debug_level<n>}
755 (@pxref{debuglevel,,debug_level}).
757 You can redirect all output from the daemon to a file using the
758 @option{-l <logfile>} switch.
760 Note! OpenOCD will launch the GDB & telnet server even if it can not
761 establish a connection with the target. In general, it is possible for
762 the JTAG controller to be unresponsive until the target is set up
763 correctly via e.g. GDB monitor commands in a GDB init script.
765 @node OpenOCD Project Setup
766 @chapter OpenOCD Project Setup
768 To use OpenOCD with your development projects, you need to do more than
769 just connecting the JTAG adapter hardware (dongle) to your development board
770 and then starting the OpenOCD server.
771 You also need to configure that server so that it knows
772 about that adapter and board, and helps your work.
773 You may also want to connect OpenOCD to GDB, possibly
774 using Eclipse or some other GUI.
776 @section Hooking up the JTAG Adapter
778 Today's most common case is a dongle with a JTAG cable on one side
779 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
780 and a USB cable on the other.
781 Instead of USB, some cables use Ethernet;
782 older ones may use a PC parallel port, or even a serial port.
784 @enumerate
785 @item @emph{Start with power to your target board turned off},
786 and nothing connected to your JTAG adapter.
787 If you're particularly paranoid, unplug power to the board.
788 It's important to have the ground signal properly set up,
789 unless you are using a JTAG adapter which provides
790 galvanic isolation between the target board and the
791 debugging host.
793 @item @emph{Be sure it's the right kind of JTAG connector.}
794 If your dongle has a 20-pin ARM connector, you need some kind
795 of adapter (or octopus, see below) to hook it up to
796 boards using 14-pin or 10-pin connectors ... or to 20-pin
797 connectors which don't use ARM's pinout.
799 In the same vein, make sure the voltage levels are compatible.
800 Not all JTAG adapters have the level shifters needed to work
801 with 1.2 Volt boards.
803 @item @emph{Be certain the cable is properly oriented} or you might
804 damage your board. In most cases there are only two possible
805 ways to connect the cable.
806 Connect the JTAG cable from your adapter to the board.
807 Be sure it's firmly connected.
809 In the best case, the connector is keyed to physically
810 prevent you from inserting it wrong.
811 This is most often done using a slot on the board's male connector
812 housing, which must match a key on the JTAG cable's female connector.
813 If there's no housing, then you must look carefully and
814 make sure pin 1 on the cable hooks up to pin 1 on the board.
815 Ribbon cables are frequently all grey except for a wire on one
816 edge, which is red. The red wire is pin 1.
818 Sometimes dongles provide cables where one end is an ``octopus'' of
819 color coded single-wire connectors, instead of a connector block.
820 These are great when converting from one JTAG pinout to another,
821 but are tedious to set up.
822 Use these with connector pinout diagrams to help you match up the
823 adapter signals to the right board pins.
825 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
826 A USB, parallel, or serial port connector will go to the host which
827 you are using to run OpenOCD.
828 For Ethernet, consult the documentation and your network administrator.
830 For USB based JTAG adapters you have an easy sanity check at this point:
831 does the host operating system see the JTAG adapter? If that host is an
832 MS-Windows host, you'll need to install a driver before OpenOCD works.
834 @item @emph{Connect the adapter's power supply, if needed.}
835 This step is primarily for non-USB adapters,
836 but sometimes USB adapters need extra power.
838 @item @emph{Power up the target board.}
839 Unless you just let the magic smoke escape,
840 you're now ready to set up the OpenOCD server
841 so you can use JTAG to work with that board.
843 @end enumerate
845 Talk with the OpenOCD server using
846 telnet (@code{telnet localhost 4444} on many systems) or GDB.
847 @xref{GDB and OpenOCD}.
849 @section Project Directory
851 There are many ways you can configure OpenOCD and start it up.
853 A simple way to organize them all involves keeping a
854 single directory for your work with a given board.
855 When you start OpenOCD from that directory,
856 it searches there first for configuration files, scripts,
857 files accessed through semihosting,
858 and for code you upload to the target board.
859 It is also the natural place to write files,
860 such as log files and data you download from the board.
862 @section Configuration Basics
864 There are two basic ways of configuring OpenOCD, and
865 a variety of ways you can mix them.
866 Think of the difference as just being how you start the server:
868 @itemize
869 @item Many @option{-f file} or @option{-c command} options on the command line
870 @item No options, but a @dfn{user config file}
871 in the current directory named @file{openocd.cfg}
872 @end itemize
874 Here is an example @file{openocd.cfg} file for a setup
875 using a Signalyzer FT2232-based JTAG adapter to talk to
876 a board with an Atmel AT91SAM7X256 microcontroller:
878 @example
879 source [find interface/signalyzer.cfg]
881 # GDB can also flash my flash!
882 gdb_memory_map enable
883 gdb_flash_program enable
885 source [find target/sam7x256.cfg]
886 @end example
888 Here is the command line equivalent of that configuration:
890 @example
891 openocd -f interface/signalyzer.cfg \
892 -c "gdb_memory_map enable" \
893 -c "gdb_flash_program enable" \
894 -f target/sam7x256.cfg
895 @end example
897 You could wrap such long command lines in shell scripts,
898 each supporting a different development task.
899 One might re-flash the board with a specific firmware version.
900 Another might set up a particular debugging or run-time environment.
902 @quotation Important
903 At this writing (October 2009) the command line method has
904 problems with how it treats variables.
905 For example, after @option{-c "set VAR value"}, or doing the
906 same in a script, the variable @var{VAR} will have no value
907 that can be tested in a later script.
908 @end quotation
910 Here we will focus on the simpler solution: one user config
911 file, including basic configuration plus any TCL procedures
912 to simplify your work.
914 @section User Config Files
915 @cindex config file, user
916 @cindex user config file
917 @cindex config file, overview
919 A user configuration file ties together all the parts of a project
920 in one place.
921 One of the following will match your situation best:
923 @itemize
924 @item Ideally almost everything comes from configuration files
925 provided by someone else.
926 For example, OpenOCD distributes a @file{scripts} directory
927 (probably in @file{/usr/share/openocd/scripts} on Linux).
928 Board and tool vendors can provide these too, as can individual
929 user sites; the @option{-s} command line option lets you say
930 where to find these files. (@xref{Running}.)
931 The AT91SAM7X256 example above works this way.
933 Three main types of non-user configuration file each have their
934 own subdirectory in the @file{scripts} directory:
936 @enumerate
937 @item @b{interface} -- one for each different debug adapter;
938 @item @b{board} -- one for each different board
939 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
940 @end enumerate
942 Best case: include just two files, and they handle everything else.
943 The first is an interface config file.
944 The second is board-specific, and it sets up the JTAG TAPs and
945 their GDB targets (by deferring to some @file{target.cfg} file),
946 declares all flash memory, and leaves you nothing to do except
947 meet your deadline:
949 @example
950 source [find interface/olimex-jtag-tiny.cfg]
951 source [find board/csb337.cfg]
952 @end example
954 Boards with a single microcontroller often won't need more
955 than the target config file, as in the AT91SAM7X256 example.
956 That's because there is no external memory (flash, DDR RAM), and
957 the board differences are encapsulated by application code.
959 @item Maybe you don't know yet what your board looks like to JTAG.
960 Once you know the @file{interface.cfg} file to use, you may
961 need help from OpenOCD to discover what's on the board.
962 Once you find the JTAG TAPs, you can just search for appropriate
963 target and board
964 configuration files ... or write your own, from the bottom up.
965 @xref{autoprobing,,Autoprobing}.
967 @item You can often reuse some standard config files but
968 need to write a few new ones, probably a @file{board.cfg} file.
969 You will be using commands described later in this User's Guide,
970 and working with the guidelines in the next chapter.
972 For example, there may be configuration files for your JTAG adapter
973 and target chip, but you need a new board-specific config file
974 giving access to your particular flash chips.
975 Or you might need to write another target chip configuration file
976 for a new chip built around the Cortex M3 core.
978 @quotation Note
979 When you write new configuration files, please submit
980 them for inclusion in the next OpenOCD release.
981 For example, a @file{board/newboard.cfg} file will help the
982 next users of that board, and a @file{target/newcpu.cfg}
983 will help support users of any board using that chip.
984 @end quotation
986 @item
987 You may may need to write some C code.
988 It may be as simple as a supporting a new ft2232 or parport
989 based adapter; a bit more involved, like a NAND or NOR flash
990 controller driver; or a big piece of work like supporting
991 a new chip architecture.
992 @end itemize
994 Reuse the existing config files when you can.
995 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
996 You may find a board configuration that's a good example to follow.
998 When you write config files, separate the reusable parts
999 (things every user of that interface, chip, or board needs)
1000 from ones specific to your environment and debugging approach.
1001 @itemize
1003 @item
1004 For example, a @code{gdb-attach} event handler that invokes
1005 the @command{reset init} command will interfere with debugging
1006 early boot code, which performs some of the same actions
1007 that the @code{reset-init} event handler does.
1009 @item
1010 Likewise, the @command{arm9 vector_catch} command (or
1011 @cindex vector_catch
1012 its siblings @command{xscale vector_catch}
1013 and @command{cortex_m vector_catch}) can be a timesaver
1014 during some debug sessions, but don't make everyone use that either.
1015 Keep those kinds of debugging aids in your user config file,
1016 along with messaging and tracing setup.
1017 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1019 @item
1020 You might need to override some defaults.
1021 For example, you might need to move, shrink, or back up the target's
1022 work area if your application needs much SRAM.
1024 @item
1025 TCP/IP port configuration is another example of something which
1026 is environment-specific, and should only appear in
1027 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1028 @end itemize
1030 @section Project-Specific Utilities
1032 A few project-specific utility
1033 routines may well speed up your work.
1034 Write them, and keep them in your project's user config file.
1036 For example, if you are making a boot loader work on a
1037 board, it's nice to be able to debug the ``after it's
1038 loaded to RAM'' parts separately from the finicky early
1039 code which sets up the DDR RAM controller and clocks.
1040 A script like this one, or a more GDB-aware sibling,
1041 may help:
1043 @example
1044 proc ramboot @{ @} @{
1045 # Reset, running the target's "reset-init" scripts
1046 # to initialize clocks and the DDR RAM controller.
1047 # Leave the CPU halted.
1048 reset init
1050 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1051 load_image u-boot.bin 0x20000000
1053 # Start running.
1054 resume 0x20000000
1055 @}
1056 @end example
1058 Then once that code is working you will need to make it
1059 boot from NOR flash; a different utility would help.
1060 Alternatively, some developers write to flash using GDB.
1061 (You might use a similar script if you're working with a flash
1062 based microcontroller application instead of a boot loader.)
1064 @example
1065 proc newboot @{ @} @{
1066 # Reset, leaving the CPU halted. The "reset-init" event
1067 # proc gives faster access to the CPU and to NOR flash;
1068 # "reset halt" would be slower.
1069 reset init
1071 # Write standard version of U-Boot into the first two
1072 # sectors of NOR flash ... the standard version should
1073 # do the same lowlevel init as "reset-init".
1074 flash protect 0 0 1 off
1075 flash erase_sector 0 0 1
1076 flash write_bank 0 u-boot.bin 0x0
1077 flash protect 0 0 1 on
1079 # Reboot from scratch using that new boot loader.
1080 reset run
1081 @}
1082 @end example
1084 You may need more complicated utility procedures when booting
1085 from NAND.
1086 That often involves an extra bootloader stage,
1087 running from on-chip SRAM to perform DDR RAM setup so it can load
1088 the main bootloader code (which won't fit into that SRAM).
1090 Other helper scripts might be used to write production system images,
1091 involving considerably more than just a three stage bootloader.
1093 @section Target Software Changes
1095 Sometimes you may want to make some small changes to the software
1096 you're developing, to help make JTAG debugging work better.
1097 For example, in C or assembly language code you might
1098 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1099 handling issues like:
1101 @itemize @bullet
1103 @item @b{Watchdog Timers}...
1104 Watchog timers are typically used to automatically reset systems if
1105 some application task doesn't periodically reset the timer. (The
1106 assumption is that the system has locked up if the task can't run.)
1107 When a JTAG debugger halts the system, that task won't be able to run
1108 and reset the timer ... potentially causing resets in the middle of
1109 your debug sessions.
1111 It's rarely a good idea to disable such watchdogs, since their usage
1112 needs to be debugged just like all other parts of your firmware.
1113 That might however be your only option.
1115 Look instead for chip-specific ways to stop the watchdog from counting
1116 while the system is in a debug halt state. It may be simplest to set
1117 that non-counting mode in your debugger startup scripts. You may however
1118 need a different approach when, for example, a motor could be physically
1119 damaged by firmware remaining inactive in a debug halt state. That might
1120 involve a type of firmware mode where that "non-counting" mode is disabled
1121 at the beginning then re-enabled at the end; a watchdog reset might fire
1122 and complicate the debug session, but hardware (or people) would be
1123 protected.@footnote{Note that many systems support a "monitor mode" debug
1124 that is a somewhat cleaner way to address such issues. You can think of
1125 it as only halting part of the system, maybe just one task,
1126 instead of the whole thing.
1127 At this writing, January 2010, OpenOCD based debugging does not support
1128 monitor mode debug, only "halt mode" debug.}
1130 @item @b{ARM Semihosting}...
1131 @cindex ARM semihosting
1132 When linked with a special runtime library provided with many
1133 toolchains@footnote{See chapter 8 "Semihosting" in
1134 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1135 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1136 The CodeSourcery EABI toolchain also includes a semihosting library.},
1137 your target code can use I/O facilities on the debug host. That library
1138 provides a small set of system calls which are handled by OpenOCD.
1139 It can let the debugger provide your system console and a file system,
1140 helping with early debugging or providing a more capable environment
1141 for sometimes-complex tasks like installing system firmware onto
1142 NAND or SPI flash.
1144 @item @b{ARM Wait-For-Interrupt}...
1145 Many ARM chips synchronize the JTAG clock using the core clock.
1146 Low power states which stop that core clock thus prevent JTAG access.
1147 Idle loops in tasking environments often enter those low power states
1148 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1150 You may want to @emph{disable that instruction} in source code,
1151 or otherwise prevent using that state,
1152 to ensure you can get JTAG access at any time.@footnote{As a more
1153 polite alternative, some processors have special debug-oriented
1154 registers which can be used to change various features including
1155 how the low power states are clocked while debugging.
1156 The STM32 DBGMCU_CR register is an example; at the cost of extra
1157 power consumption, JTAG can be used during low power states.}
1158 For example, the OpenOCD @command{halt} command may not
1159 work for an idle processor otherwise.
1161 @item @b{Delay after reset}...
1162 Not all chips have good support for debugger access
1163 right after reset; many LPC2xxx chips have issues here.
1164 Similarly, applications that reconfigure pins used for
1165 JTAG access as they start will also block debugger access.
1167 To work with boards like this, @emph{enable a short delay loop}
1168 the first thing after reset, before "real" startup activities.
1169 For example, one second's delay is usually more than enough
1170 time for a JTAG debugger to attach, so that
1171 early code execution can be debugged
1172 or firmware can be replaced.
1174 @item @b{Debug Communications Channel (DCC)}...
1175 Some processors include mechanisms to send messages over JTAG.
1176 Many ARM cores support these, as do some cores from other vendors.
1177 (OpenOCD may be able to use this DCC internally, speeding up some
1178 operations like writing to memory.)
1180 Your application may want to deliver various debugging messages
1181 over JTAG, by @emph{linking with a small library of code}
1182 provided with OpenOCD and using the utilities there to send
1183 various kinds of message.
1184 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1186 @end itemize
1188 @section Target Hardware Setup
1190 Chip vendors often provide software development boards which
1191 are highly configurable, so that they can support all options
1192 that product boards may require. @emph{Make sure that any
1193 jumpers or switches match the system configuration you are
1194 working with.}
1196 Common issues include:
1198 @itemize @bullet
1200 @item @b{JTAG setup} ...
1201 Boards may support more than one JTAG configuration.
1202 Examples include jumpers controlling pullups versus pulldowns
1203 on the nTRST and/or nSRST signals, and choice of connectors
1204 (e.g. which of two headers on the base board,
1205 or one from a daughtercard).
1206 For some Texas Instruments boards, you may need to jumper the
1207 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1209 @item @b{Boot Modes} ...
1210 Complex chips often support multiple boot modes, controlled
1211 by external jumpers. Make sure this is set up correctly.
1212 For example many i.MX boards from NXP need to be jumpered
1213 to "ATX mode" to start booting using the on-chip ROM, when
1214 using second stage bootloader code stored in a NAND flash chip.
1216 Such explicit configuration is common, and not limited to
1217 booting from NAND. You might also need to set jumpers to
1218 start booting using code loaded from an MMC/SD card; external
1219 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1220 flash; some external host; or various other sources.
1223 @item @b{Memory Addressing} ...
1224 Boards which support multiple boot modes may also have jumpers
1225 to configure memory addressing. One board, for example, jumpers
1226 external chipselect 0 (used for booting) to address either
1227 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1228 or NAND flash. When it's jumpered to address NAND flash, that
1229 board must also be told to start booting from on-chip ROM.
1231 Your @file{board.cfg} file may also need to be told this jumper
1232 configuration, so that it can know whether to declare NOR flash
1233 using @command{flash bank} or instead declare NAND flash with
1234 @command{nand device}; and likewise which probe to perform in
1235 its @code{reset-init} handler.
1237 A closely related issue is bus width. Jumpers might need to
1238 distinguish between 8 bit or 16 bit bus access for the flash
1239 used to start booting.
1241 @item @b{Peripheral Access} ...
1242 Development boards generally provide access to every peripheral
1243 on the chip, sometimes in multiple modes (such as by providing
1244 multiple audio codec chips).
1245 This interacts with software
1246 configuration of pin multiplexing, where for example a
1247 given pin may be routed either to the MMC/SD controller
1248 or the GPIO controller. It also often interacts with
1249 configuration jumpers. One jumper may be used to route
1250 signals to an MMC/SD card slot or an expansion bus (which
1251 might in turn affect booting); others might control which
1252 audio or video codecs are used.
1254 @end itemize
1256 Plus you should of course have @code{reset-init} event handlers
1257 which set up the hardware to match that jumper configuration.
1258 That includes in particular any oscillator or PLL used to clock
1259 the CPU, and any memory controllers needed to access external
1260 memory and peripherals. Without such handlers, you won't be
1261 able to access those resources without working target firmware
1262 which can do that setup ... this can be awkward when you're
1263 trying to debug that target firmware. Even if there's a ROM
1264 bootloader which handles a few issues, it rarely provides full
1265 access to all board-specific capabilities.
1268 @node Config File Guidelines
1269 @chapter Config File Guidelines
1271 This chapter is aimed at any user who needs to write a config file,
1272 including developers and integrators of OpenOCD and any user who
1273 needs to get a new board working smoothly.
1274 It provides guidelines for creating those files.
1276 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1277 with files including the ones listed here.
1278 Use them as-is where you can; or as models for new files.
1279 @itemize @bullet
1280 @item @file{interface} ...
1281 These are for debug adapters.
1282 Files that configure JTAG adapters go here.
1283 @example
1284 $ ls interface -R
1285 interface/:
1286 altera-usb-blaster.cfg hilscher_nxhx50_re.cfg openocd-usb-hs.cfg
1287 arm-jtag-ew.cfg hitex_str9-comstick.cfg openrd.cfg
1288 at91rm9200.cfg icebear.cfg osbdm.cfg
1289 axm0432.cfg jlink.cfg parport.cfg
1290 busblaster.cfg jtagkey2.cfg parport_dlc5.cfg
1291 buspirate.cfg jtagkey2p.cfg redbee-econotag.cfg
1292 calao-usb-a9260-c01.cfg jtagkey.cfg redbee-usb.cfg
1293 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg rlink.cfg
1294 calao-usb-a9260.cfg jtag-lock-pick_tiny_2.cfg sheevaplug.cfg
1295 chameleon.cfg kt-link.cfg signalyzer.cfg
1296 cortino.cfg lisa-l.cfg signalyzer-h2.cfg
1297 digilent-hs1.cfg luminary.cfg signalyzer-h4.cfg
1298 dlp-usb1232h.cfg luminary-icdi.cfg signalyzer-lite.cfg
1299 dummy.cfg luminary-lm3s811.cfg stlink-v1.cfg
1300 estick.cfg minimodule.cfg stlink-v2.cfg
1301 flashlink.cfg neodb.cfg stm32-stick.cfg
1302 flossjtag.cfg ngxtech.cfg sysfsgpio-raspberrypi.cfg
1303 flossjtag-noeeprom.cfg olimex-arm-usb-ocd.cfg ti-icdi.cfg
1304 flyswatter2.cfg olimex-arm-usb-ocd-h.cfg turtelizer2.cfg
1305 flyswatter.cfg olimex-arm-usb-tiny-h.cfg ulink.cfg
1306 ftdi olimex-jtag-tiny.cfg usb-jtag.cfg
1307 hilscher_nxhx10_etm.cfg oocdlink.cfg usbprog.cfg
1308 hilscher_nxhx500_etm.cfg opendous.cfg vpaclink.cfg
1309 hilscher_nxhx500_re.cfg opendous_ftdi.cfg vsllink.cfg
1310 hilscher_nxhx50_etm.cfg openocd-usb.cfg xds100v2.cfg
1312 interface/ftdi:
1313 axm0432.cfg hitex_str9-comstick.cfg olimex-jtag-tiny.cfg
1314 calao-usb-a9260-c01.cfg icebear.cfg oocdlink.cfg
1315 calao-usb-a9260-c02.cfg jtagkey2.cfg opendous_ftdi.cfg
1316 cortino.cfg jtagkey2p.cfg openocd-usb.cfg
1317 dlp-usb1232h.cfg jtagkey.cfg openocd-usb-hs.cfg
1318 dp_busblaster.cfg jtag-lock-pick_tiny_2.cfg openrd.cfg
1319 flossjtag.cfg kt-link.cfg redbee-econotag.cfg
1320 flossjtag-noeeprom.cfg lisa-l.cfg redbee-usb.cfg
1321 flyswatter2.cfg luminary.cfg sheevaplug.cfg
1322 flyswatter.cfg luminary-icdi.cfg signalyzer.cfg
1323 gw16042.cfg luminary-lm3s811.cfg signalyzer-lite.cfg
1324 hilscher_nxhx10_etm.cfg minimodule.cfg stm32-stick.cfg
1325 hilscher_nxhx500_etm.cfg neodb.cfg turtelizer2-revB.cfg
1326 hilscher_nxhx500_re.cfg ngxtech.cfg turtelizer2-revC.cfg
1327 hilscher_nxhx50_etm.cfg olimex-arm-usb-ocd.cfg vpaclink.cfg
1328 hilscher_nxhx50_re.cfg olimex-arm-usb-ocd-h.cfg xds100v2.cfg
1329 hitex_lpc1768stick.cfg olimex-arm-usb-tiny-h.cfg
1330 $
1331 @end example
1332 @item @file{board} ...
1333 think Circuit Board, PWA, PCB, they go by many names. Board files
1334 contain initialization items that are specific to a board.
1335 They reuse target configuration files, since the same
1336 microprocessor chips are used on many boards,
1337 but support for external parts varies widely. For
1338 example, the SDRAM initialization sequence for the board, or the type
1339 of external flash and what address it uses. Any initialization
1340 sequence to enable that external flash or SDRAM should be found in the
1341 board file. Boards may also contain multiple targets: two CPUs; or
1342 a CPU and an FPGA.
1343 @example
1344 $ ls board
1345 actux3.cfg lpc1850_spifi_generic.cfg
1346 am3517evm.cfg lpc4350_spifi_generic.cfg
1347 arm_evaluator7t.cfg lubbock.cfg
1348 at91cap7a-stk-sdram.cfg mcb1700.cfg
1349 at91eb40a.cfg microchip_explorer16.cfg
1350 at91rm9200-dk.cfg mini2440.cfg
1351 at91rm9200-ek.cfg mini6410.cfg
1352 at91sam9261-ek.cfg netgear-dg834v3.cfg
1353 at91sam9263-ek.cfg olimex_LPC2378STK.cfg
1354 at91sam9g20-ek.cfg olimex_lpc_h2148.cfg
1355 atmel_at91sam7s-ek.cfg olimex_sam7_ex256.cfg
1356 atmel_at91sam9260-ek.cfg olimex_sam9_l9260.cfg
1357 atmel_at91sam9rl-ek.cfg olimex_stm32_h103.cfg
1358 atmel_sam3n_ek.cfg olimex_stm32_h107.cfg
1359 atmel_sam3s_ek.cfg olimex_stm32_p107.cfg
1360 atmel_sam3u_ek.cfg omap2420_h4.cfg
1361 atmel_sam3x_ek.cfg open-bldc.cfg
1362 atmel_sam4s_ek.cfg openrd.cfg
1363 balloon3-cpu.cfg osk5912.cfg
1364 colibri.cfg phone_se_j100i.cfg
1365 crossbow_tech_imote2.cfg phytec_lpc3250.cfg
1366 csb337.cfg pic-p32mx.cfg
1367 csb732.cfg propox_mmnet1001.cfg
1368 da850evm.cfg pxa255_sst.cfg
1369 digi_connectcore_wi-9c.cfg redbee.cfg
1370 diolan_lpc4350-db1.cfg rsc-w910.cfg
1371 dm355evm.cfg sheevaplug.cfg
1372 dm365evm.cfg smdk6410.cfg
1373 dm6446evm.cfg spear300evb.cfg
1374 efikamx.cfg spear300evb_mod.cfg
1375 eir.cfg spear310evb20.cfg
1376 ek-lm3s1968.cfg spear310evb20_mod.cfg
1377 ek-lm3s3748.cfg spear320cpu.cfg
1378 ek-lm3s6965.cfg spear320cpu_mod.cfg
1379 ek-lm3s811.cfg steval_pcc010.cfg
1380 ek-lm3s811-revb.cfg stm320518_eval_stlink.cfg
1381 ek-lm3s8962.cfg stm32100b_eval.cfg
1382 ek-lm3s9b9x.cfg stm3210b_eval.cfg
1383 ek-lm3s9d92.cfg stm3210c_eval.cfg
1384 ek-lm4f120xl.cfg stm3210e_eval.cfg
1385 ek-lm4f232.cfg stm3220g_eval.cfg
1386 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1387 ethernut3.cfg stm3241g_eval.cfg
1388 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1389 hammer.cfg stm32f0discovery.cfg
1390 hilscher_nxdb500sys.cfg stm32f3discovery.cfg
1391 hilscher_nxeb500hmi.cfg stm32f4discovery.cfg
1392 hilscher_nxhx10.cfg stm32ldiscovery.cfg
1393 hilscher_nxhx500.cfg stm32vldiscovery.cfg
1394 hilscher_nxhx50.cfg str910-eval.cfg
1395 hilscher_nxsb100.cfg telo.cfg
1396 hitex_lpc1768stick.cfg ti_am335xevm.cfg
1397 hitex_lpc2929.cfg ti_beagleboard.cfg
1398 hitex_stm32-performancestick.cfg ti_beagleboard_xm.cfg
1399 hitex_str9-comstick.cfg ti_beaglebone.cfg
1400 iar_lpc1768.cfg ti_blaze.cfg
1401 iar_str912_sk.cfg ti_pandaboard.cfg
1402 icnova_imx53_sodimm.cfg ti_pandaboard_es.cfg
1403 icnova_sam9g45_sodimm.cfg topas910.cfg
1404 imx27ads.cfg topasa900.cfg
1405 imx27lnst.cfg twr-k60f120m.cfg
1406 imx28evk.cfg twr-k60n512.cfg
1407 imx31pdk.cfg tx25_stk5.cfg
1408 imx35pdk.cfg tx27_stk5.cfg
1409 imx53loco.cfg unknown_at91sam9260.cfg
1410 keil_mcb1700.cfg uptech_2410.cfg
1411 keil_mcb2140.cfg verdex.cfg
1412 kwikstik.cfg voipac.cfg
1413 linksys_nslu2.cfg voltcraft_dso-3062c.cfg
1414 lisa-l.cfg x300t.cfg
1415 logicpd_imx27.cfg zy1000.cfg
1416 $
1417 @end example
1418 @item @file{target} ...
1419 think chip. The ``target'' directory represents the JTAG TAPs
1420 on a chip
1421 which OpenOCD should control, not a board. Two common types of targets
1422 are ARM chips and FPGA or CPLD chips.
1423 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1424 the target config file defines all of them.
1425 @example
1426 $ ls target
1427 aduc702x.cfg lpc1763.cfg
1428 am335x.cfg lpc1764.cfg
1429 amdm37x.cfg lpc1765.cfg
1430 ar71xx.cfg lpc1766.cfg
1431 at32ap7000.cfg lpc1767.cfg
1432 at91r40008.cfg lpc1768.cfg
1433 at91rm9200.cfg lpc1769.cfg
1434 at91sam3ax_4x.cfg lpc1788.cfg
1435 at91sam3ax_8x.cfg lpc17xx.cfg
1436 at91sam3ax_xx.cfg lpc1850.cfg
1437 at91sam3nXX.cfg lpc2103.cfg
1438 at91sam3sXX.cfg lpc2124.cfg
1439 at91sam3u1c.cfg lpc2129.cfg
1440 at91sam3u1e.cfg lpc2148.cfg
1441 at91sam3u2c.cfg lpc2294.cfg
1442 at91sam3u2e.cfg lpc2378.cfg
1443 at91sam3u4c.cfg lpc2460.cfg
1444 at91sam3u4e.cfg lpc2478.cfg
1445 at91sam3uxx.cfg lpc2900.cfg
1446 at91sam3XXX.cfg lpc2xxx.cfg
1447 at91sam4sd32x.cfg lpc3131.cfg
1448 at91sam4sXX.cfg lpc3250.cfg
1449 at91sam4XXX.cfg lpc4350.cfg
1450 at91sam7se512.cfg lpc4350.cfg.orig
1451 at91sam7sx.cfg mc13224v.cfg
1452 at91sam7x256.cfg nuc910.cfg
1453 at91sam7x512.cfg omap2420.cfg
1454 at91sam9260.cfg omap3530.cfg
1455 at91sam9260_ext_RAM_ext_flash.cfg omap4430.cfg
1456 at91sam9261.cfg omap4460.cfg
1457 at91sam9263.cfg omap5912.cfg
1458 at91sam9.cfg omapl138.cfg
1459 at91sam9g10.cfg pic32mx.cfg
1460 at91sam9g20.cfg pxa255.cfg
1461 at91sam9g45.cfg pxa270.cfg
1462 at91sam9rl.cfg pxa3xx.cfg
1463 atmega128.cfg readme.txt
1464 avr32.cfg samsung_s3c2410.cfg
1465 c100.cfg samsung_s3c2440.cfg
1466 c100config.tcl samsung_s3c2450.cfg
1467 c100helper.tcl samsung_s3c4510.cfg
1468 c100regs.tcl samsung_s3c6410.cfg
1469 cs351x.cfg sharp_lh79532.cfg
1470 davinci.cfg smp8634.cfg
1471 dragonite.cfg spear3xx.cfg
1472 dsp56321.cfg stellaris.cfg
1473 dsp568013.cfg stellaris_icdi.cfg
1474 dsp568037.cfg stm32f0x_stlink.cfg
1475 efm32_stlink.cfg stm32f1x.cfg
1476 epc9301.cfg stm32f1x_stlink.cfg
1477 faux.cfg stm32f2x.cfg
1478 feroceon.cfg stm32f2x_stlink.cfg
1479 fm3.cfg stm32f3x.cfg
1480 hilscher_netx10.cfg stm32f3x_stlink.cfg
1481 hilscher_netx500.cfg stm32f4x.cfg
1482 hilscher_netx50.cfg stm32f4x_stlink.cfg
1483 icepick.cfg stm32l.cfg
1484 imx21.cfg stm32lx_dual_bank.cfg
1485 imx25.cfg stm32lx_stlink.cfg
1486 imx27.cfg stm32_stlink.cfg
1487 imx28.cfg stm32w108_stlink.cfg
1488 imx31.cfg stm32xl.cfg
1489 imx35.cfg str710.cfg
1490 imx51.cfg str730.cfg
1491 imx53.cfg str750.cfg
1492 imx6.cfg str912.cfg
1493 imx.cfg swj-dp.tcl
1494 is5114.cfg test_reset_syntax_error.cfg
1495 ixp42x.cfg test_syntax_error.cfg
1496 k40.cfg ti-ar7.cfg
1497 k60.cfg ti_calypso.cfg
1498 lpc1751.cfg ti_dm355.cfg
1499 lpc1752.cfg ti_dm365.cfg
1500 lpc1754.cfg ti_dm6446.cfg
1501 lpc1756.cfg tmpa900.cfg
1502 lpc1758.cfg tmpa910.cfg
1503 lpc1759.cfg u8500.cfg
1504 @end example
1505 @item @emph{more} ... browse for other library files which may be useful.
1506 For example, there are various generic and CPU-specific utilities.
1507 @end itemize
1509 The @file{openocd.cfg} user config
1510 file may override features in any of the above files by
1511 setting variables before sourcing the target file, or by adding
1512 commands specific to their situation.
1514 @section Interface Config Files
1516 The user config file
1517 should be able to source one of these files with a command like this:
1519 @example
1520 source [find interface/FOOBAR.cfg]
1521 @end example
1523 A preconfigured interface file should exist for every debug adapter
1524 in use today with OpenOCD.
1525 That said, perhaps some of these config files
1526 have only been used by the developer who created it.
1528 A separate chapter gives information about how to set these up.
1529 @xref{Debug Adapter Configuration}.
1530 Read the OpenOCD source code (and Developer's Guide)
1531 if you have a new kind of hardware interface
1532 and need to provide a driver for it.
1534 @section Board Config Files
1535 @cindex config file, board
1536 @cindex board config file
1538 The user config file
1539 should be able to source one of these files with a command like this:
1541 @example
1542 source [find board/FOOBAR.cfg]
1543 @end example
1545 The point of a board config file is to package everything
1546 about a given board that user config files need to know.
1547 In summary the board files should contain (if present)
1549 @enumerate
1550 @item One or more @command{source [target/...cfg]} statements
1551 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1552 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1553 @item Target @code{reset} handlers for SDRAM and I/O configuration
1554 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1555 @item All things that are not ``inside a chip''
1556 @end enumerate
1558 Generic things inside target chips belong in target config files,
1559 not board config files. So for example a @code{reset-init} event
1560 handler should know board-specific oscillator and PLL parameters,
1561 which it passes to target-specific utility code.
1563 The most complex task of a board config file is creating such a
1564 @code{reset-init} event handler.
1565 Define those handlers last, after you verify the rest of the board
1566 configuration works.
1568 @subsection Communication Between Config files
1570 In addition to target-specific utility code, another way that
1571 board and target config files communicate is by following a
1572 convention on how to use certain variables.
1574 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1575 Thus the rule we follow in OpenOCD is this: Variables that begin with
1576 a leading underscore are temporary in nature, and can be modified and
1577 used at will within a target configuration file.
1579 Complex board config files can do the things like this,
1580 for a board with three chips:
1582 @example
1583 # Chip #1: PXA270 for network side, big endian
1584 set CHIPNAME network
1585 set ENDIAN big
1586 source [find target/pxa270.cfg]
1587 # on return: _TARGETNAME = network.cpu
1588 # other commands can refer to the "network.cpu" target.
1589 $_TARGETNAME configure .... events for this CPU..
1591 # Chip #2: PXA270 for video side, little endian
1592 set CHIPNAME video
1593 set ENDIAN little
1594 source [find target/pxa270.cfg]
1595 # on return: _TARGETNAME = video.cpu
1596 # other commands can refer to the "video.cpu" target.
1597 $_TARGETNAME configure .... events for this CPU..
1599 # Chip #3: Xilinx FPGA for glue logic
1600 set CHIPNAME xilinx
1601 unset ENDIAN
1602 source [find target/spartan3.cfg]
1603 @end example
1605 That example is oversimplified because it doesn't show any flash memory,
1606 or the @code{reset-init} event handlers to initialize external DRAM
1607 or (assuming it needs it) load a configuration into the FPGA.
1608 Such features are usually needed for low-level work with many boards,
1609 where ``low level'' implies that the board initialization software may
1610 not be working. (That's a common reason to need JTAG tools. Another
1611 is to enable working with microcontroller-based systems, which often
1612 have no debugging support except a JTAG connector.)
1614 Target config files may also export utility functions to board and user
1615 config files. Such functions should use name prefixes, to help avoid
1616 naming collisions.
1618 Board files could also accept input variables from user config files.
1619 For example, there might be a @code{J4_JUMPER} setting used to identify
1620 what kind of flash memory a development board is using, or how to set
1621 up other clocks and peripherals.
1623 @subsection Variable Naming Convention
1624 @cindex variable names
1626 Most boards have only one instance of a chip.
1627 However, it should be easy to create a board with more than
1628 one such chip (as shown above).
1629 Accordingly, we encourage these conventions for naming
1630 variables associated with different @file{target.cfg} files,
1631 to promote consistency and
1632 so that board files can override target defaults.
1634 Inputs to target config files include:
1636 @itemize @bullet
1637 @item @code{CHIPNAME} ...
1638 This gives a name to the overall chip, and is used as part of
1639 tap identifier dotted names.
1640 While the default is normally provided by the chip manufacturer,
1641 board files may need to distinguish between instances of a chip.
1642 @item @code{ENDIAN} ...
1643 By default @option{little} - although chips may hard-wire @option{big}.
1644 Chips that can't change endianness don't need to use this variable.
1645 @item @code{CPUTAPID} ...
1646 When OpenOCD examines the JTAG chain, it can be told verify the
1647 chips against the JTAG IDCODE register.
1648 The target file will hold one or more defaults, but sometimes the
1649 chip in a board will use a different ID (perhaps a newer revision).
1650 @end itemize
1652 Outputs from target config files include:
1654 @itemize @bullet
1655 @item @code{_TARGETNAME} ...
1656 By convention, this variable is created by the target configuration
1657 script. The board configuration file may make use of this variable to
1658 configure things like a ``reset init'' script, or other things
1659 specific to that board and that target.
1660 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1661 @code{_TARGETNAME1}, ... etc.
1662 @end itemize
1664 @subsection The reset-init Event Handler
1665 @cindex event, reset-init
1666 @cindex reset-init handler
1668 Board config files run in the OpenOCD configuration stage;
1669 they can't use TAPs or targets, since they haven't been
1670 fully set up yet.
1671 This means you can't write memory or access chip registers;
1672 you can't even verify that a flash chip is present.
1673 That's done later in event handlers, of which the target @code{reset-init}
1674 handler is one of the most important.
1676 Except on microcontrollers, the basic job of @code{reset-init} event
1677 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1678 Microcontrollers rarely use boot loaders; they run right out of their
1679 on-chip flash and SRAM memory. But they may want to use one of these
1680 handlers too, if just for developer convenience.
1682 @quotation Note
1683 Because this is so very board-specific, and chip-specific, no examples
1684 are included here.
1685 Instead, look at the board config files distributed with OpenOCD.
1686 If you have a boot loader, its source code will help; so will
1687 configuration files for other JTAG tools
1688 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1689 @end quotation
1691 Some of this code could probably be shared between different boards.
1692 For example, setting up a DRAM controller often doesn't differ by
1693 much except the bus width (16 bits or 32?) and memory timings, so a
1694 reusable TCL procedure loaded by the @file{target.cfg} file might take
1695 those as parameters.
1696 Similarly with oscillator, PLL, and clock setup;
1697 and disabling the watchdog.
1698 Structure the code cleanly, and provide comments to help
1699 the next developer doing such work.
1700 (@emph{You might be that next person} trying to reuse init code!)
1702 The last thing normally done in a @code{reset-init} handler is probing
1703 whatever flash memory was configured. For most chips that needs to be
1704 done while the associated target is halted, either because JTAG memory
1705 access uses the CPU or to prevent conflicting CPU access.
1707 @subsection JTAG Clock Rate
1709 Before your @code{reset-init} handler has set up
1710 the PLLs and clocking, you may need to run with
1711 a low JTAG clock rate.
1712 @xref{jtagspeed,,JTAG Speed}.
1713 Then you'd increase that rate after your handler has
1714 made it possible to use the faster JTAG clock.
1715 When the initial low speed is board-specific, for example
1716 because it depends on a board-specific oscillator speed, then
1717 you should probably set it up in the board config file;
1718 if it's target-specific, it belongs in the target config file.
1720 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1721 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1722 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1723 Consult chip documentation to determine the peak JTAG clock rate,
1724 which might be less than that.
1726 @quotation Warning
1727 On most ARMs, JTAG clock detection is coupled to the core clock, so
1728 software using a @option{wait for interrupt} operation blocks JTAG access.
1729 Adaptive clocking provides a partial workaround, but a more complete
1730 solution just avoids using that instruction with JTAG debuggers.
1731 @end quotation
1733 If both the chip and the board support adaptive clocking,
1734 use the @command{jtag_rclk}
1735 command, in case your board is used with JTAG adapter which
1736 also supports it. Otherwise use @command{adapter_khz}.
1737 Set the slow rate at the beginning of the reset sequence,
1738 and the faster rate as soon as the clocks are at full speed.
1740 @anchor{theinitboardprocedure}
1741 @subsection The init_board procedure
1742 @cindex init_board procedure
1744 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1745 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1746 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1747 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1748 spearate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1749 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1750 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1751 Additionally ``linear'' board config file will most likely fail when target config file uses
1752 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1753 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1754 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1755 need to override @code{init_targets} defined in target config files when they only need to to add some specifics.
1757 Just as @code{init_targets}, the @code{init_board} procedure can be overriden by ``next level'' script (which sources
1758 the original), allowing greater code reuse.
1760 @example
1761 ### board_file.cfg ###
1763 # source target file that does most of the config in init_targets
1764 source [find target/target.cfg]
1766 proc enable_fast_clock @{@} @{
1767 # enables fast on-board clock source
1768 # configures the chip to use it
1769 @}
1771 # initialize only board specifics - reset, clock, adapter frequency
1772 proc init_board @{@} @{
1773 reset_config trst_and_srst trst_pulls_srst
1775 $_TARGETNAME configure -event reset-init @{
1776 adapter_khz 1
1777 enable_fast_clock
1778 adapter_khz 10000
1779 @}
1780 @}
1781 @end example
1783 @section Target Config Files
1784 @cindex config file, target
1785 @cindex target config file
1787 Board config files communicate with target config files using
1788 naming conventions as described above, and may source one or
1789 more target config files like this:
1791 @example
1792 source [find target/FOOBAR.cfg]
1793 @end example
1795 The point of a target config file is to package everything
1796 about a given chip that board config files need to know.
1797 In summary the target files should contain
1799 @enumerate
1800 @item Set defaults
1801 @item Add TAPs to the scan chain
1802 @item Add CPU targets (includes GDB support)
1803 @item CPU/Chip/CPU-Core specific features
1804 @item On-Chip flash
1805 @end enumerate
1807 As a rule of thumb, a target file sets up only one chip.
1808 For a microcontroller, that will often include a single TAP,
1809 which is a CPU needing a GDB target, and its on-chip flash.
1811 More complex chips may include multiple TAPs, and the target
1812 config file may need to define them all before OpenOCD
1813 can talk to the chip.
1814 For example, some phone chips have JTAG scan chains that include
1815 an ARM core for operating system use, a DSP,
1816 another ARM core embedded in an image processing engine,
1817 and other processing engines.
1819 @subsection Default Value Boiler Plate Code
1821 All target configuration files should start with code like this,
1822 letting board config files express environment-specific
1823 differences in how things should be set up.
1825 @example
1826 # Boards may override chip names, perhaps based on role,
1827 # but the default should match what the vendor uses
1828 if @{ [info exists CHIPNAME] @} @{
1830 @} else @{
1831 set _CHIPNAME sam7x256
1832 @}
1834 # ONLY use ENDIAN with targets that can change it.
1835 if @{ [info exists ENDIAN] @} @{
1836 set _ENDIAN $ENDIAN
1837 @} else @{
1838 set _ENDIAN little
1839 @}
1841 # TAP identifiers may change as chips mature, for example with
1842 # new revision fields (the "3" here). Pick a good default; you
1843 # can pass several such identifiers to the "jtag newtap" command.
1844 if @{ [info exists CPUTAPID ] @} @{
1846 @} else @{
1847 set _CPUTAPID 0x3f0f0f0f
1848 @}
1849 @end example
1850 @c but 0x3f0f0f0f is for an str73x part ...
1852 @emph{Remember:} Board config files may include multiple target
1853 config files, or the same target file multiple times
1854 (changing at least @code{CHIPNAME}).
1856 Likewise, the target configuration file should define
1857 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1858 use it later on when defining debug targets:
1860 @example
1862 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1863 @end example
1865 @subsection Adding TAPs to the Scan Chain
1866 After the ``defaults'' are set up,
1867 add the TAPs on each chip to the JTAG scan chain.
1868 @xref{TAP Declaration}, and the naming convention
1869 for taps.
1871 In the simplest case the chip has only one TAP,
1872 probably for a CPU or FPGA.
1873 The config file for the Atmel AT91SAM7X256
1874 looks (in part) like this:
1876 @example
1877 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1878 @end example
1880 A board with two such at91sam7 chips would be able
1881 to source such a config file twice, with different
1882 values for @code{CHIPNAME}, so
1883 it adds a different TAP each time.
1885 If there are nonzero @option{-expected-id} values,
1886 OpenOCD attempts to verify the actual tap id against those values.
1887 It will issue error messages if there is mismatch, which
1888 can help to pinpoint problems in OpenOCD configurations.
1890 @example
1891 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1892 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1893 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1894 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1895 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1896 @end example
1898 There are more complex examples too, with chips that have
1899 multiple TAPs. Ones worth looking at include:
1901 @itemize
1902 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1903 plus a JRC to enable them
1904 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1905 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1906 is not currently used)
1907 @end itemize
1909 @subsection Add CPU targets
1911 After adding a TAP for a CPU, you should set it up so that
1912 GDB and other commands can use it.
1913 @xref{CPU Configuration}.
1914 For the at91sam7 example above, the command can look like this;
1915 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1916 to little endian, and this chip doesn't support changing that.
1918 @example
1920 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1921 @end example
1923 Work areas are small RAM areas associated with CPU targets.
1924 They are used by OpenOCD to speed up downloads,
1925 and to download small snippets of code to program flash chips.
1926 If the chip includes a form of ``on-chip-ram'' - and many do - define
1927 a work area if you can.
1928 Again using the at91sam7 as an example, this can look like:
1930 @example
1931 $_TARGETNAME configure -work-area-phys 0x00200000 \
1932 -work-area-size 0x4000 -work-area-backup 0
1933 @end example
1935 @anchor{definecputargetsworkinginsmp}
1936 @subsection Define CPU targets working in SMP
1937 @cindex SMP
1938 After setting targets, you can define a list of targets working in SMP.
1940 @example
1941 set _TARGETNAME_1 $_CHIPNAME.cpu1
1942 set _TARGETNAME_2 $_CHIPNAME.cpu2
1943 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1944 -coreid 0 -dbgbase $_DAP_DBG1
1945 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1946 -coreid 1 -dbgbase $_DAP_DBG2
1947 #define 2 targets working in smp.
1948 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1949 @end example
1950 In the above example on cortex_a, 2 cpus are working in SMP.
1951 In SMP only one GDB instance is created and :
1952 @itemize @bullet
1953 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1954 @item halt command triggers the halt of all targets in the list.
1955 @item resume command triggers the write context and the restart of all targets in the list.
1956 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1957 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1958 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1959 @end itemize
1961 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1962 command have been implemented.
1963 @itemize @bullet
1964 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1965 @item cortex_a smp_off : disable SMP mode, the current target is the one
1966 displayed in the GDB session, only this target is now controlled by GDB
1967 session. This behaviour is useful during system boot up.
1968 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1969 following example.
1970 @end itemize
1972 @example
1973 >cortex_a smp_gdb
1974 gdb coreid 0 -> -1
1975 #0 : coreid 0 is displayed to GDB ,
1976 #-> -1 : next resume triggers a real resume
1977 > cortex_a smp_gdb 1
1978 gdb coreid 0 -> 1
1979 #0 :coreid 0 is displayed to GDB ,
1980 #->1 : next resume displays coreid 1 to GDB
1981 > resume
1982 > cortex_a smp_gdb
1983 gdb coreid 1 -> 1
1984 #1 :coreid 1 is displayed to GDB ,
1985 #->1 : next resume displays coreid 1 to GDB
1986 > cortex_a smp_gdb -1
1987 gdb coreid 1 -> -1
1988 #1 :coreid 1 is displayed to GDB,
1989 #->-1 : next resume triggers a real resume
1990 @end example
1993 @subsection Chip Reset Setup
1995 As a rule, you should put the @command{reset_config} command
1996 into the board file. Most things you think you know about a
1997 chip can be tweaked by the board.
1999 Some chips have specific ways the TRST and SRST signals are
2000 managed. In the unusual case that these are @emph{chip specific}
2001 and can never be changed by board wiring, they could go here.
2002 For example, some chips can't support JTAG debugging without
2003 both signals.
2005 Provide a @code{reset-assert} event handler if you can.
2006 Such a handler uses JTAG operations to reset the target,
2007 letting this target config be used in systems which don't
2008 provide the optional SRST signal, or on systems where you
2009 don't want to reset all targets at once.
2010 Such a handler might write to chip registers to force a reset,
2011 use a JRC to do that (preferable -- the target may be wedged!),
2012 or force a watchdog timer to trigger.
2013 (For Cortex-M targets, this is not necessary. The target
2014 driver knows how to use trigger an NVIC reset when SRST is
2015 not available.)
2017 Some chips need special attention during reset handling if
2018 they're going to be used with JTAG.
2019 An example might be needing to send some commands right
2020 after the target's TAP has been reset, providing a
2021 @code{reset-deassert-post} event handler that writes a chip
2022 register to report that JTAG debugging is being done.
2023 Another would be reconfiguring the watchdog so that it stops
2024 counting while the core is halted in the debugger.
2026 JTAG clocking constraints often change during reset, and in
2027 some cases target config files (rather than board config files)
2028 are the right places to handle some of those issues.
2029 For example, immediately after reset most chips run using a
2030 slower clock than they will use later.
2031 That means that after reset (and potentially, as OpenOCD
2032 first starts up) they must use a slower JTAG clock rate
2033 than they will use later.
2034 @xref{jtagspeed,,JTAG Speed}.
2036 @quotation Important
2037 When you are debugging code that runs right after chip
2038 reset, getting these issues right is critical.
2039 In particular, if you see intermittent failures when
2040 OpenOCD verifies the scan chain after reset,
2041 look at how you are setting up JTAG clocking.
2042 @end quotation
2044 @anchor{theinittargetsprocedure}
2045 @subsection The init_targets procedure
2046 @cindex init_targets procedure
2048 Target config files can either be ``linear'' (script executed line-by-line when parsed in
2049 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
2050 procedure called @code{init_targets}, which will be executed when entering run stage
2051 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
2052 Such procedure can be overriden by ``next level'' script (which sources the original).
2053 This concept faciliates code reuse when basic target config files provide generic configuration
2054 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
2055 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
2056 because sourcing them executes every initialization commands they provide.
2058 @example
2059 ### generic_file.cfg ###
2061 proc setup_my_chip @{chip_name flash_size ram_size@} @{
2062 # basic initialization procedure ...
2063 @}
2065 proc init_targets @{@} @{
2066 # initializes generic chip with 4kB of flash and 1kB of RAM
2067 setup_my_chip MY_GENERIC_CHIP 4096 1024
2068 @}
2070 ### specific_file.cfg ###
2072 source [find target/generic_file.cfg]
2074 proc init_targets @{@} @{
2075 # initializes specific chip with 128kB of flash and 64kB of RAM
2076 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
2077 @}
2078 @end example
2080 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
2081 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
2083 For an example of this scheme see LPC2000 target config files.
2085 The @code{init_boards} procedure is a similar concept concerning board config files
2086 (@xref{theinitboardprocedure,,The init_board procedure}.)
2088 @subsection ARM Core Specific Hacks
2090 If the chip has a DCC, enable it. If the chip is an ARM9 with some
2091 special high speed download features - enable it.
2093 If present, the MMU, the MPU and the CACHE should be disabled.
2095 Some ARM cores are equipped with trace support, which permits
2096 examination of the instruction and data bus activity. Trace
2097 activity is controlled through an ``Embedded Trace Module'' (ETM)
2098 on one of the core's scan chains. The ETM emits voluminous data
2099 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
2100 If you are using an external trace port,
2101 configure it in your board config file.
2102 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2103 configure it in your target config file.
2105 @example
2106 etm config $_TARGETNAME 16 normal full etb
2107 etb config $_TARGETNAME $_CHIPNAME.etb
2108 @end example
2110 @subsection Internal Flash Configuration
2112 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2114 @b{Never ever} in the ``target configuration file'' define any type of
2115 flash that is external to the chip. (For example a BOOT flash on
2116 Chip Select 0.) Such flash information goes in a board file - not
2117 the TARGET (chip) file.
2119 Examples:
2120 @itemize @bullet
2121 @item at91sam7x256 - has 256K flash YES enable it.
2122 @item str912 - has flash internal YES enable it.
2123 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2124 @item pxa270 - again - CS0 flash - it goes in the board file.
2125 @end itemize
2127 @anchor{translatingconfigurationfiles}
2128 @section Translating Configuration Files
2129 @cindex translation
2130 If you have a configuration file for another hardware debugger
2131 or toolset (Abatron, BDI2000, BDI3000, CCS,
2132 Lauterbach, Segger, Macraigor, etc.), translating
2133 it into OpenOCD syntax is often quite straightforward. The most tricky
2134 part of creating a configuration script is oftentimes the reset init
2135 sequence where e.g. PLLs, DRAM and the like is set up.
2137 One trick that you can use when translating is to write small
2138 Tcl procedures to translate the syntax into OpenOCD syntax. This
2139 can avoid manual translation errors and make it easier to
2140 convert other scripts later on.
2142 Example of transforming quirky arguments to a simple search and
2143 replace job:
2145 @example
2146 # Lauterbach syntax(?)
2147 #
2148 # Data.Set c15:0x042f %long 0x40000015
2149 #
2150 # OpenOCD syntax when using procedure below.
2151 #
2152 # setc15 0x01 0x00050078
2154 proc setc15 @{regs value@} @{
2155 global TARGETNAME
2157 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2159 arm mcr 15 [expr ($regs>>12)&0x7] \
2160 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2161 [expr ($regs>>8)&0x7] $value
2162 @}
2163 @end example
2167 @node Daemon Configuration
2168 @chapter Daemon Configuration
2169 @cindex initialization
2170 The commands here are commonly found in the openocd.cfg file and are
2171 used to specify what TCP/IP ports are used, and how GDB should be
2172 supported.
2174 @anchor{configurationstage}
2175 @section Configuration Stage
2176 @cindex configuration stage
2177 @cindex config command
2179 When the OpenOCD server process starts up, it enters a
2180 @emph{configuration stage} which is the only time that
2181 certain commands, @emph{configuration commands}, may be issued.
2182 Normally, configuration commands are only available
2183 inside startup scripts.
2185 In this manual, the definition of a configuration command is
2186 presented as a @emph{Config Command}, not as a @emph{Command}
2187 which may be issued interactively.
2188 The runtime @command{help} command also highlights configuration
2189 commands, and those which may be issued at any time.
2191 Those configuration commands include declaration of TAPs,
2192 flash banks,
2193 the interface used for JTAG communication,
2194 and other basic setup.
2195 The server must leave the configuration stage before it
2196 may access or activate TAPs.
2197 After it leaves this stage, configuration commands may no
2198 longer be issued.
2200 @anchor{enteringtherunstage}
2201 @section Entering the Run Stage
2203 The first thing OpenOCD does after leaving the configuration
2204 stage is to verify that it can talk to the scan chain
2205 (list of TAPs) which has been configured.
2206 It will warn if it doesn't find TAPs it expects to find,
2207 or finds TAPs that aren't supposed to be there.
2208 You should see no errors at this point.
2209 If you see errors, resolve them by correcting the
2210 commands you used to configure the server.
2211 Common errors include using an initial JTAG speed that's too
2212 fast, and not providing the right IDCODE values for the TAPs
2213 on the scan chain.
2215 Once OpenOCD has entered the run stage, a number of commands
2216 become available.
2217 A number of these relate to the debug targets you may have declared.
2218 For example, the @command{mww} command will not be available until
2219 a target has been successfuly instantiated.
2220 If you want to use those commands, you may need to force
2221 entry to the run stage.
2223 @deffn {Config Command} init
2224 This command terminates the configuration stage and
2225 enters the run stage. This helps when you need to have
2226 the startup scripts manage tasks such as resetting the target,
2227 programming flash, etc. To reset the CPU upon startup, add "init" and
2228 "reset" at the end of the config script or at the end of the OpenOCD
2229 command line using the @option{-c} command line switch.
2231 If this command does not appear in any startup/configuration file
2232 OpenOCD executes the command for you after processing all
2233 configuration files and/or command line options.
2235 @b{NOTE:} This command normally occurs at or near the end of your
2236 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2237 targets ready. For example: If your openocd.cfg file needs to
2238 read/write memory on your target, @command{init} must occur before
2239 the memory read/write commands. This includes @command{nand probe}.
2240 @end deffn
2242 @deffn {Overridable Procedure} jtag_init
2243 This is invoked at server startup to verify that it can talk
2244 to the scan chain (list of TAPs) which has been configured.
2246 The default implementation first tries @command{jtag arp_init},
2247 which uses only a lightweight JTAG reset before examining the
2248 scan chain.
2249 If that fails, it tries again, using a harder reset
2250 from the overridable procedure @command{init_reset}.
2252 Implementations must have verified the JTAG scan chain before
2253 they return.
2254 This is done by calling @command{jtag arp_init}
2255 (or @command{jtag arp_init-reset}).
2256 @end deffn
2258 @anchor{tcpipports}
2259 @section TCP/IP Ports
2260 @cindex TCP port
2261 @cindex server
2262 @cindex port
2263 @cindex security
2264 The OpenOCD server accepts remote commands in several syntaxes.
2265 Each syntax uses a different TCP/IP port, which you may specify
2266 only during configuration (before those ports are opened).
2268 For reasons including security, you may wish to prevent remote
2269 access using one or more of these ports.
2270 In such cases, just specify the relevant port number as zero.
2271 If you disable all access through TCP/IP, you will need to
2272 use the command line @option{-pipe} option.
2274 @deffn {Command} gdb_port [number]
2275 @cindex GDB server
2276 Normally gdb listens to a TCP/IP port, but GDB can also
2277 communicate via pipes(stdin/out or named pipes). The name
2278 "gdb_port" stuck because it covers probably more than 90% of
2279 the normal use cases.
2281 No arguments reports GDB port. "pipe" means listen to stdin
2282 output to stdout, an integer is base port number, "disable"
2283 disables the gdb server.
2285 When using "pipe", also use log_output to redirect the log
2286 output to a file so as not to flood the stdin/out pipes.
2288 The -p/--pipe option is deprecated and a warning is printed
2289 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2291 Any other string is interpreted as named pipe to listen to.
2292 Output pipe is the same name as input pipe, but with 'o' appended,
2293 e.g. /var/gdb, /var/gdbo.
2295 The GDB port for the first target will be the base port, the
2296 second target will listen on gdb_port + 1, and so on.
2297 When not specified during the configuration stage,
2298 the port @var{number} defaults to 3333.
2299 @end deffn
2301 @deffn {Command} tcl_port [number]
2302 Specify or query the port used for a simplified RPC
2303 connection that can be used by clients to issue TCL commands and get the
2304 output from the Tcl engine.
2305 Intended as a machine interface.
2306 When not specified during the configuration stage,
2307 the port @var{number} defaults to 6666.
2309 @end deffn
2311 @deffn {Command} telnet_port [number]
2312 Specify or query the
2313 port on which to listen for incoming telnet connections.
2314 This port is intended for interaction with one human through TCL commands.
2315 When not specified during the configuration stage,
2316 the port @var{number} defaults to 4444.
2317 When specified as zero, this port is not activated.
2318 @end deffn
2320 @anchor{gdbconfiguration}
2321 @section GDB Configuration
2322 @cindex GDB
2323 @cindex GDB configuration
2324 You can reconfigure some GDB behaviors if needed.
2325 The ones listed here are static and global.
2326 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2327 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2329 @anchor{gdbbreakpointoverride}
2330 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2331 Force breakpoint type for gdb @command{break} commands.
2332 This option supports GDB GUIs which don't
2333 distinguish hard versus soft breakpoints, if the default OpenOCD and
2334 GDB behaviour is not sufficient. GDB normally uses hardware
2335 breakpoints if the memory map has been set up for flash regions.
2336 @end deffn
2338 @anchor{gdbflashprogram}
2339 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2340 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2341 vFlash packet is received.
2342 The default behaviour is @option{enable}.
2343 @end deffn
2345 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2346 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2347 requested. GDB will then know when to set hardware breakpoints, and program flash
2348 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2349 for flash programming to work.
2350 Default behaviour is @option{enable}.
2351 @xref{gdbflashprogram,,gdb_flash_program}.
2352 @end deffn
2354 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2355 Specifies whether data aborts cause an error to be reported
2356 by GDB memory read packets.
2357 The default behaviour is @option{disable};
2358 use @option{enable} see these errors reported.
2359 @end deffn
2361 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2362 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2363 The default behaviour is @option{disable}.
2364 @end deffn
2366 @deffn {Command} gdb_save_tdesc
2367 Saves the target descripton file to the local file system.
2369 The file name is @i{target_name}.xml.
2370 @end deffn
2372 @anchor{eventpolling}
2373 @section Event Polling
2375 Hardware debuggers are parts of asynchronous systems,
2376 where significant events can happen at any time.
2377 The OpenOCD server needs to detect some of these events,
2378 so it can report them to through TCL command line
2379 or to GDB.
2381 Examples of such events include:
2383 @itemize
2384 @item One of the targets can stop running ... maybe it triggers
2385 a code breakpoint or data watchpoint, or halts itself.
2386 @item Messages may be sent over ``debug message'' channels ... many
2387 targets support such messages sent over JTAG,
2388 for receipt by the person debugging or tools.
2389 @item Loss of power ... some adapters can detect these events.
2390 @item Resets not issued through JTAG ... such reset sources
2391 can include button presses or other system hardware, sometimes
2392 including the target itself (perhaps through a watchdog).
2393 @item Debug instrumentation sometimes supports event triggering
2394 such as ``trace buffer full'' (so it can quickly be emptied)
2395 or other signals (to correlate with code behavior).
2396 @end itemize
2398 None of those events are signaled through standard JTAG signals.
2399 However, most conventions for JTAG connectors include voltage
2400 level and system reset (SRST) signal detection.
2401 Some connectors also include instrumentation signals, which
2402 can imply events when those signals are inputs.
2404 In general, OpenOCD needs to periodically check for those events,
2405 either by looking at the status of signals on the JTAG connector
2406 or by sending synchronous ``tell me your status'' JTAG requests
2407 to the various active targets.
2408 There is a command to manage and monitor that polling,
2409 which is normally done in the background.
2411 @deffn Command poll [@option{on}|@option{off}]
2412 Poll the current target for its current state.
2413 (Also, @pxref{targetcurstate,,target curstate}.)
2414 If that target is in debug mode, architecture
2415 specific information about the current state is printed.
2416 An optional parameter
2417 allows background polling to be enabled and disabled.
2419 You could use this from the TCL command shell, or
2420 from GDB using @command{monitor poll} command.
2421 Leave background polling enabled while you're using GDB.
2422 @example
2423 > poll
2424 background polling: on
2425 target state: halted
2426 target halted in ARM state due to debug-request, \
2427 current mode: Supervisor
2428 cpsr: 0x800000d3 pc: 0x11081bfc
2429 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2430 >
2431 @end example
2432 @end deffn
2434 @node Debug Adapter Configuration
2435 @chapter Debug Adapter Configuration
2436 @cindex config file, interface
2437 @cindex interface config file
2439 Correctly installing OpenOCD includes making your operating system give
2440 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2441 are used to select which one is used, and to configure how it is used.
2443 @quotation Note
2444 Because OpenOCD started out with a focus purely on JTAG, you may find
2445 places where it wrongly presumes JTAG is the only transport protocol
2446 in use. Be aware that recent versions of OpenOCD are removing that
2447 limitation. JTAG remains more functional than most other transports.
2448 Other transports do not support boundary scan operations, or may be
2449 specific to a given chip vendor. Some might be usable only for
2450 programming flash memory, instead of also for debugging.
2451 @end quotation
2453 Debug Adapters/Interfaces/Dongles are normally configured
2454 through commands in an interface configuration
2455 file which is sourced by your @file{openocd.cfg} file, or
2456 through a command line @option{-f interface/....cfg} option.
2458 @example
2459 source [find interface/olimex-jtag-tiny.cfg]
2460 @end example
2462 These commands tell
2463 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2464 A few cases are so simple that you only need to say what driver to use:
2466 @example
2467 # jlink interface
2468 interface jlink
2469 @end example
2471 Most adapters need a bit more configuration than that.
2474 @section Interface Configuration
2476 The interface command tells OpenOCD what type of debug adapter you are
2477 using. Depending on the type of adapter, you may need to use one or
2478 more additional commands to further identify or configure the adapter.
2480 @deffn {Config Command} {interface} name
2481 Use the interface driver @var{name} to connect to the
2482 target.
2483 @end deffn
2485 @deffn Command {interface_list}
2486 List the debug adapter drivers that have been built into
2487 the running copy of OpenOCD.
2488 @end deffn
2489 @deffn Command {interface transports} transport_name+
2490 Specifies the transports supported by this debug adapter.
2491 The adapter driver builds-in similar knowledge; use this only
2492 when external configuration (such as jumpering) changes what
2493 the hardware can support.
2494 @end deffn
2498 @deffn Command {adapter_name}
2499 Returns the name of the debug adapter driver being used.
2500 @end deffn
2502 @section Interface Drivers
2504 Each of the interface drivers listed here must be explicitly
2505 enabled when OpenOCD is configured, in order to be made
2506 available at run time.
2508 @deffn {Interface Driver} {amt_jtagaccel}
2509 Amontec Chameleon in its JTAG Accelerator configuration,
2510 connected to a PC's EPP mode parallel port.
2511 This defines some driver-specific commands:
2513 @deffn {Config Command} {parport_port} number
2514 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2515 the number of the @file{/dev/parport} device.
2516 @end deffn
2518 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2519 Displays status of RTCK option.
2520 Optionally sets that option first.
2521 @end deffn
2522 @end deffn
2524 @deffn {Interface Driver} {arm-jtag-ew}
2525 Olimex ARM-JTAG-EW USB adapter
2526 This has one driver-specific command:
2528 @deffn Command {armjtagew_info}
2529 Logs some status
2530 @end deffn
2531 @end deffn
2533 @deffn {Interface Driver} {at91rm9200}
2534 Supports bitbanged JTAG from the local system,
2535 presuming that system is an Atmel AT91rm9200
2536 and a specific set of GPIOs is used.
2537 @c command: at91rm9200_device NAME
2538 @c chooses among list of bit configs ... only one option
2539 @end deffn
2541 @deffn {Interface Driver} {dummy}
2542 A dummy software-only driver for debugging.
2543 @end deffn
2545 @deffn {Interface Driver} {ep93xx}
2546 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2547 @end deffn
2549 @deffn {Interface Driver} {ft2232}
2550 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2552 Note that this driver has several flaws and the @command{ftdi} driver is
2553 recommended as its replacement.
2555 These interfaces have several commands, used to configure the driver
2556 before initializing the JTAG scan chain:
2558 @deffn {Config Command} {ft2232_device_desc} description
2559 Provides the USB device description (the @emph{iProduct string})
2560 of the FTDI FT2232 device. If not
2561 specified, the FTDI default value is used. This setting is only valid
2562 if compiled with FTD2XX support.
2563 @end deffn
2565 @deffn {Config Command} {ft2232_serial} serial-number
2566 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2567 in case the vendor provides unique IDs and more than one FT2232 device
2568 is connected to the host.
2569 If not specified, serial numbers are not considered.
2570 (Note that USB serial numbers can be arbitrary Unicode strings,
2571 and are not restricted to containing only decimal digits.)
2572 @end deffn
2574 @deffn {Config Command} {ft2232_layout} name
2575 Each vendor's FT2232 device can use different GPIO signals
2576 to control output-enables, reset signals, and LEDs.
2577 Currently valid layout @var{name} values include:
2578 @itemize @minus
2579 @item @b{axm0432_jtag} Axiom AXM-0432
2580 @item @b{comstick} Hitex STR9 comstick
2581 @item @b{cortino} Hitex Cortino JTAG interface
2582 @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
2583 either for the local Cortex-M3 (SRST only)
2584 or in a passthrough mode (neither SRST nor TRST)
2585 This layout can not support the SWO trace mechanism, and should be
2586 used only for older boards (before rev C).
2587 @item @b{luminary_icdi} This layout should be used with most TI/Luminary
2588 eval boards, including Rev C LM3S811 eval boards and the eponymous
2589 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2590 to debug some other target. It can support the SWO trace mechanism.
2591 @item @b{flyswatter} Tin Can Tools Flyswatter
2592 @item @b{icebear} ICEbear JTAG adapter from Section 5
2593 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2594 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2595 @item @b{m5960} American Microsystems M5960
2596 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2597 @item @b{oocdlink} OOCDLink
2598 @c oocdlink ~= jtagkey_prototype_v1
2599 @item @b{redbee-econotag} Integrated with a Redbee development board.
2600 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2601 @item @b{sheevaplug} Marvell Sheevaplug development kit
2602 @item @b{signalyzer} Xverve Signalyzer
2603 @item @b{stm32stick} Hitex STM32 Performance Stick
2604 @item @b{turtelizer2} egnite Software turtelizer2
2605 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2606 @end itemize
2607 @end deffn
2609 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2610 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2611 default values are used.
2612 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2613 @example
2614 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2615 @end example
2616 @end deffn
2618 @deffn {Config Command} {ft2232_latency} ms
2619 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2620 ft2232_read() fails to return the expected number of bytes. This can be caused by
2621 USB communication delays and has proved hard to reproduce and debug. Setting the
2622 FT2232 latency timer to a larger value increases delays for short USB packets but it
2623 also reduces the risk of timeouts before receiving the expected number of bytes.
2624 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2625 @end deffn
2627 @deffn {Config Command} {ft2232_channel} channel
2628 Used to select the channel of the ft2232 chip to use (between 1 and 4).
2629 The default value is 1.
2630 @end deffn
2632 For example, the interface config file for a
2633 Turtelizer JTAG Adapter looks something like this:
2635 @example
2636 interface ft2232
2637 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2638 ft2232_layout turtelizer2
2639 ft2232_vid_pid 0x0403 0xbdc8
2640 @end example
2641 @end deffn
2643 @deffn {Interface Driver} {ftdi}
2644 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2645 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2646 It is a complete rewrite to address a large number of problems with the ft2232
2647 interface driver.
2649 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2650 bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
2651 consistently faster than the ft2232 driver, sometimes several times faster.
2653 A major improvement of this driver is that support for new FTDI based adapters
2654 can be added competely through configuration files, without the need to patch
2655 and rebuild OpenOCD.
2657 The driver uses a signal abstraction to enable Tcl configuration files to
2658 define outputs for one or several FTDI GPIO. These outputs can then be
2659 controlled using the @command{ftdi_set_signal} command. Special signal names
2660 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2661 will be used for their customary purpose.
2663 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2664 be controlled differently. In order to support tristateable signals such as
2665 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2666 signal. The following output buffer configurations are supported:
2668 @itemize @minus
2669 @item Push-pull with one FTDI output as (non-)inverted data line
2670 @item Open drain with one FTDI output as (non-)inverted output-enable
2671 @item Tristate with one FTDI output as (non-)inverted data line and another
2672 FTDI output as (non-)inverted output-enable
2673 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2674 switching data and direction as necessary
2675 @end itemize
2677 These interfaces have several commands, used to configure the driver
2678 before initializing the JTAG scan chain:
2680 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2681 The vendor ID and product ID of the adapter. If not specified, the FTDI
2682 default values are used.
2683 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2684 @example
2685 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2686 @end example
2687 @end deffn
2689 @deffn {Config Command} {ftdi_device_desc} description
2690 Provides the USB device description (the @emph{iProduct string})
2691 of the adapter. If not specified, the device description is ignored
2692 during device selection.
2693 @end deffn
2695 @deffn {Config Command} {ftdi_serial} serial-number
2696 Specifies the @var{serial-number} of the adapter to use,
2697 in case the vendor provides unique IDs and more than one adapter
2698 is connected to the host.
2699 If not specified, serial numbers are not considered.
2700 (Note that USB serial numbers can be arbitrary Unicode strings,
2701 and are not restricted to containing only decimal digits.)
2702 @end deffn
2704 @deffn {Config Command} {ftdi_channel} channel
2705 Selects the channel of the FTDI device to use for MPSSE operations. Most
2706 adapters use the default, channel 0, but there are exceptions.
2707 @end deffn
2709 @deffn {Config Command} {ftdi_layout_init} data direction
2710 Specifies the initial values of the FTDI GPIO data and direction registers.
2711 Each value is a 16-bit number corresponding to the concatenation of the high
2712 and low FTDI GPIO registers. The values should be selected based on the
2713 schematics of the adapter, such that all signals are set to safe levels with
2714 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2715 and initially asserted reset signals.
2716 @end deffn
2718 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask]
2719 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2720 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2721 register bitmasks to tell the driver the connection and type of the output
2722 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2723 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2724 used with inverting data inputs and @option{-data} with non-inverting inputs.
2725 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2726 not-output-enable) input to the output buffer is connected.
2728 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2729 simple open-collector transistor driver would be specified with @option{-oe}
2730 only. In that case the signal can only be set to drive low or to Hi-Z and the
2731 driver will complain if the signal is set to drive high. Which means that if
2732 it's a reset signal, @command{reset_config} must be specified as
2733 @option{srst_open_drain}, not @option{srst_push_pull}.
2735 A special case is provided when @option{-data} and @option{-oe} is set to the
2736 same bitmask. Then the FTDI pin is considered being connected straight to the
2737 target without any buffer. The FTDI pin is then switched between output and
2738 input as necessary to provide the full set of low, high and Hi-Z
2739 characteristics. In all other cases, the pins specified in a signal definition
2740 are always driven by the FTDI.
2741 @end deffn
2743 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2744 Set a previously defined signal to the specified level.
2745 @itemize @minus
2746 @item @option{0}, drive low
2747 @item @option{1}, drive high
2748 @item @option{z}, set to high-impedance
2749 @end itemize
2750 @end deffn
2752 For example adapter definitions, see the configuration files shipped in the
2753 @file{interface/ftdi} directory.
2754 @end deffn
2756 @deffn {Interface Driver} {remote_bitbang}
2757 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2758 with a remote process and sends ASCII encoded bitbang requests to that process
2759 instead of directly driving JTAG.
2761 The remote_bitbang driver is useful for debugging software running on
2762 processors which are being simulated.
2764 @deffn {Config Command} {remote_bitbang_port} number
2765 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2766 sockets instead of TCP.
2767 @end deffn
2769 @deffn {Config Command} {remote_bitbang_host} hostname
2770 Specifies the hostname of the remote process to connect to using TCP, or the
2771 name of the UNIX socket to use if remote_bitbang_port is 0.
2772 @end deffn
2774 For example, to connect remotely via TCP to the host foobar you might have
2775 something like:
2777 @example
2778 interface remote_bitbang
2779 remote_bitbang_port 3335
2780 remote_bitbang_host foobar
2781 @end example
2783 To connect to another process running locally via UNIX sockets with socket
2784 named mysocket:
2786 @example
2787 interface remote_bitbang
2788 remote_bitbang_port 0
2789 remote_bitbang_host mysocket
2790 @end example
2791 @end deffn
2793 @deffn {Interface Driver} {usb_blaster}
2794 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2795 for FTDI chips. These interfaces have several commands, used to
2796 configure the driver before initializing the JTAG scan chain:
2798 @deffn {Config Command} {usb_blaster_device_desc} description
2799 Provides the USB device description (the @emph{iProduct string})
2800 of the FTDI FT245 device. If not
2801 specified, the FTDI default value is used. This setting is only valid
2802 if compiled with FTD2XX support.
2803 @end deffn
2805 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2806 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2807 default values are used.
2808 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2809 Altera USB-Blaster (default):
2810 @example
2811 usb_blaster_vid_pid 0x09FB 0x6001
2812 @end example
2813 The following VID/PID is for Kolja Waschk's USB JTAG:
2814 @example
2815 usb_blaster_vid_pid 0x16C0 0x06AD
2816 @end example
2817 @end deffn
2819 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2820 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2821 female JTAG header). These pins can be used as SRST and/or TRST provided the
2822 appropriate connections are made on the target board.
2824 For example, to use pin 6 as SRST (as with an AVR board):
2825 @example
2826 $_TARGETNAME configure -event reset-assert \
2827 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2828 @end example
2829 @end deffn
2831 @end deffn
2833 @deffn {Interface Driver} {gw16012}
2834 Gateworks GW16012 JTAG programmer.
2835 This has one driver-specific command:
2837 @deffn {Config Command} {parport_port} [port_number]
2838 Display either the address of the I/O port
2839 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2840 If a parameter is provided, first switch to use that port.
2841 This is a write-once setting.
2842 @end deffn
2843 @end deffn
2845 @deffn {Interface Driver} {jlink}
2846 Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
2848 @quotation Compatibility Note
2849 Segger released many firmware versions for the many harware versions they
2850 produced. OpenOCD was extensively tested and intended to run on all of them,
2851 but some combinations were reported as incompatible. As a general
2852 recommendation, it is advisable to use the latest firmware version
2853 available for each hardware version. However the current V8 is a moving
2854 target, and Segger firmware versions released after the OpenOCD was
2855 released may not be compatible. In such cases it is recommended to
2856 revert to the last known functional version. For 0.5.0, this is from
2857 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2858 version is from "May 3 2012 18:36:22", packed with 4.46f.
2859 @end quotation
2861 @deffn {Command} {jlink caps}
2862 Display the device firmware capabilities.
2863 @end deffn
2864 @deffn {Command} {jlink info}
2865 Display various device information, like hardware version, firmware version, current bus status.
2866 @end deffn
2867 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2868 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2869 @end deffn
2870 @deffn {Command} {jlink config}
2871 Display the J-Link configuration.
2872 @end deffn
2873 @deffn {Command} {jlink config kickstart} [val]
2874 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2875 @end deffn
2876 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2877 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2878 @end deffn
2879 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2880 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2881 E the bit of the subnet mask and
2882 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2883 @end deffn
2884 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2885 Set the USB address; this will also change the product id. Without argument, show the USB address.
2886 @end deffn
2887 @deffn {Command} {jlink config reset}
2888 Reset the current configuration.
2889 @end deffn
2890 @deffn {Command} {jlink config save}
2891 Save the current configuration to the internal persistent storage.
2892 @end deffn
2893 @deffn {Config} {jlink pid} val
2894 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2895 @end deffn
2896 @end deffn
2898 @deffn {Interface Driver} {parport}
2899 Supports PC parallel port bit-banging cables:
2900 Wigglers, PLD download cable, and more.
2901 These interfaces have several commands, used to configure the driver
2902 before initializing the JTAG scan chain:
2904 @deffn {Config Command} {parport_cable} name
2905 Set the layout of the parallel port cable used to connect to the target.
2906 This is a write-once setting.
2907 Currently valid cable @var{name} values include:
2909 @itemize @minus
2910 @item @b{altium} Altium Universal JTAG cable.
2911 @item @b{arm-jtag} Same as original wiggler except SRST and
2912 TRST connections reversed and TRST is also inverted.
2913 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2914 in configuration mode. This is only used to
2915 program the Chameleon itself, not a connected target.
2916 @item @b{dlc5} The Xilinx Parallel cable III.
2917 @item @b{flashlink} The ST Parallel cable.
2918 @item @b{lattice} Lattice ispDOWNLOAD Cable
2919 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2920 some versions of
2921 Amontec's Chameleon Programmer. The new version available from
2922 the website uses the original Wiggler layout ('@var{wiggler}')
2923 @item @b{triton} The parallel port adapter found on the
2924 ``Karo Triton 1 Development Board''.
2925 This is also the layout used by the HollyGates design
2926 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2927 @item @b{wiggler} The original Wiggler layout, also supported by
2928 several clones, such as the Olimex ARM-JTAG
2929 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2930 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2931 @end itemize
2932 @end deffn
2934 @deffn {Config Command} {parport_port} [port_number]
2935 Display either the address of the I/O port
2936 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2937 If a parameter is provided, first switch to use that port.
2938 This is a write-once setting.
2940 When using PPDEV to access the parallel port, use the number of the parallel port:
2941 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2942 you may encounter a problem.
2943 @end deffn
2945 @deffn Command {parport_toggling_time} [nanoseconds]
2946 Displays how many nanoseconds the hardware needs to toggle TCK;
2947 the parport driver uses this value to obey the
2948 @command{adapter_khz} configuration.
2949 When the optional @var{nanoseconds} parameter is given,
2950 that setting is changed before displaying the current value.
2952 The default setting should work reasonably well on commodity PC hardware.
2953 However, you may want to calibrate for your specific hardware.
2954 @quotation Tip
2955 To measure the toggling time with a logic analyzer or a digital storage
2956 oscilloscope, follow the procedure below:
2957 @example
2958 > parport_toggling_time 1000
2959 > adapter_khz 500
2960 @end example
2961 This sets the maximum JTAG clock speed of the hardware, but
2962 the actual speed probably deviates from the requested 500 kHz.
2963 Now, measure the time between the two closest spaced TCK transitions.
2964 You can use @command{runtest 1000} or something similar to generate a
2965 large set of samples.
2966 Update the setting to match your measurement:
2967 @example
2968 > parport_toggling_time <measured nanoseconds>
2969 @end example
2970 Now the clock speed will be a better match for @command{adapter_khz rate}
2971 commands given in OpenOCD scripts and event handlers.
2973 You can do something similar with many digital multimeters, but note
2974 that you'll probably need to run the clock continuously for several
2975 seconds before it decides what clock rate to show. Adjust the
2976 toggling time up or down until the measured clock rate is a good
2977 match for the adapter_khz rate you specified; be conservative.
2978 @end quotation
2979 @end deffn
2981 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2982 This will configure the parallel driver to write a known
2983 cable-specific value to the parallel interface on exiting OpenOCD.
2984 @end deffn
2986 For example, the interface configuration file for a
2987 classic ``Wiggler'' cable on LPT2 might look something like this:
2989 @example
2990 interface parport
2991 parport_port 0x278
2992 parport_cable wiggler
2993 @end example
2994 @end deffn
2996 @deffn {Interface Driver} {presto}
2997 ASIX PRESTO USB JTAG programmer.
2998 @deffn {Config Command} {presto_serial} serial_string
2999 Configures the USB serial number of the Presto device to use.
3000 @end deffn
3001 @end deffn
3003 @deffn {Interface Driver} {rlink}
3004 Raisonance RLink USB adapter
3005 @end deffn
3007 @deffn {Interface Driver} {usbprog}
3008 usbprog is a freely programmable USB adapter.
3009 @end deffn
3011 @deffn {Interface Driver} {vsllink}
3012 vsllink is part of Versaloon which is a versatile USB programmer.
3014 @quotation Note
3015 This defines quite a few driver-specific commands,
3016 which are not currently documented here.
3017 @end quotation
3018 @end deffn
3020 @deffn {Interface Driver} {hla}
3021 This is a driver that supports multiple High Level Adapters.
3022 This type of adapter does not expose some of the lower level api's
3023 that OpenOCD would normally use to access the target.
3025 Currently supported adapters include the ST STLINK and TI ICDI.
3027 @deffn {Config Command} {hla_device_desc} description
3028 Currently Not Supported.
3029 @end deffn
3031 @deffn {Config Command} {hla_serial} serial
3032 Currently Not Supported.
3033 @end deffn
3035 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
3036 Specifies the adapter layout to use.
3037 @end deffn
3039 @deffn {Config Command} {hla_vid_pid} vid pid
3040 The vendor ID and product ID of the device.
3041 @end deffn
3043 @deffn {Config Command} {stlink_api} api_level
3044 Manually sets the stlink api used, valid options are 1 or 2. (@b{STLINK Only}).
3045 @end deffn
3047 @deffn {Config Command} {trace} output_file_path source_clock_hz
3048 Enable SWO tracing (if supported), trace data is appended to the specified
3049 output file and the file is created if it does not exist. The source clock
3050 rate for the trace port must be specified, this is typically the CPU clock
3051 rate.
3052 @end deffn
3053 @end deffn
3055 @deffn {Interface Driver} {opendous}
3056 opendous-jtag is a freely programmable USB adapter.
3057 @end deffn
3059 @deffn {Interface Driver} {ulink}
3060 This is the Keil ULINK v1 JTAG debugger.
3061 @end deffn
3063 @deffn {Interface Driver} {ZY1000}
3064 This is the Zylin ZY1000 JTAG debugger.
3065 @end deffn
3067 @quotation Note
3068 This defines some driver-specific commands,
3069 which are not currently documented here.
3070 @end quotation
3072 @deffn Command power [@option{on}|@option{off}]
3073 Turn power switch to target on/off.
3074 No arguments: print status.
3075 @end deffn
3077 @deffn {Interface Driver} {bcm2835gpio}
3078 This SoC is present in Raspberry Pi which is a cheap single-board computer
3079 exposing some GPIOs on its expansion header.
3081 The driver accesses memory-mapped GPIO peripheral registers directly
3082 for maximum performance, but the only possible race condition is for
3083 the pins' modes/muxing (which is highly unlikely), so it should be
3084 able to coexist nicely with both sysfs bitbanging and various
3085 peripherals' kernel drivers. The driver restores the previous
3086 configuration on exit.
3088 See @file{interface/raspberrypi-native.cfg} for a sample config and
3089 pinout.
3091 @end deffn
3093 @section Transport Configuration
3094 @cindex Transport
3095 As noted earlier, depending on the version of OpenOCD you use,
3096 and the debug adapter you are using,
3097 several transports may be available to
3098 communicate with debug targets (or perhaps to program flash memory).
3099 @deffn Command {transport list}
3100 displays the names of the transports supported by this
3101 version of OpenOCD.
3102 @end deffn
3104 @deffn Command {transport select} transport_name
3105 Select which of the supported transports to use in this OpenOCD session.
3106 The transport must be supported by the debug adapter hardware and by the
3107 version of OpenOCD you are using (including the adapter's driver).
3108 No arguments: returns name of session's selected transport.
3109 @end deffn
3111 @subsection JTAG Transport
3112 @cindex JTAG
3113 JTAG is the original transport supported by OpenOCD, and most
3114 of the OpenOCD commands support it.
3115 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3116 each of which must be explicitly declared.
3117 JTAG supports both debugging and boundary scan testing.
3118 Flash programming support is built on top of debug support.
3119 @subsection SWD Transport
3120 @cindex SWD
3121 @cindex Serial Wire Debug
3122 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3123 Debug Access Point (DAP, which must be explicitly declared.
3124 (SWD uses fewer signal wires than JTAG.)
3125 SWD is debug-oriented, and does not support boundary scan testing.
3126 Flash programming support is built on top of debug support.
3127 (Some processors support both JTAG and SWD.)
3128 @deffn Command {swd newdap} ...
3129 Declares a single DAP which uses SWD transport.
3130 Parameters are currently the same as "jtag newtap" but this is
3131 expected to change.
3132 @end deffn
3133 @deffn Command {swd wcr trn prescale}
3134 Updates TRN (turnaraound delay) and prescaling.fields of the
3135 Wire Control Register (WCR).
3136 No parameters: displays current settings.
3137 @end deffn
3139 @subsection SPI Transport
3140 @cindex SPI
3141 @cindex Serial Peripheral Interface
3142 The Serial Peripheral Interface (SPI) is a general purpose transport
3143 which uses four wire signaling. Some processors use it as part of a
3144 solution for flash programming.
3146 @anchor{jtagspeed}
3147 @section JTAG Speed
3148 JTAG clock setup is part of system setup.
3149 It @emph{does not belong with interface setup} since any interface
3150 only knows a few of the constraints for the JTAG clock speed.
3151 Sometimes the JTAG speed is
3152 changed during the target initialization process: (1) slow at
3153 reset, (2) program the CPU clocks, (3) run fast.
3154 Both the "slow" and "fast" clock rates are functions of the
3155 oscillators used, the chip, the board design, and sometimes
3156 power management software that may be active.
3158 The speed used during reset, and the scan chain verification which
3159 follows reset, can be adjusted using a @code{reset-start}
3160 target event handler.
3161 It can then be reconfigured to a faster speed by a
3162 @code{reset-init} target event handler after it reprograms those
3163 CPU clocks, or manually (if something else, such as a boot loader,
3164 sets up those clocks).
3165 @xref{targetevents,,Target Events}.
3166 When the initial low JTAG speed is a chip characteristic, perhaps
3167 because of a required oscillator speed, provide such a handler
3168 in the target config file.
3169 When that speed is a function of a board-specific characteristic
3170 such as which speed oscillator is used, it belongs in the board
3171 config file instead.
3172 In both cases it's safest to also set the initial JTAG clock rate
3173 to that same slow speed, so that OpenOCD never starts up using a
3174 clock speed that's faster than the scan chain can support.
3176 @example
3177 jtag_rclk 3000
3178 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3179 @end example
3181 If your system supports adaptive clocking (RTCK), configuring
3182 JTAG to use that is probably the most robust approach.
3183 However, it introduces delays to synchronize clocks; so it
3184 may not be the fastest solution.
3186 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3187 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3188 which support adaptive clocking.
3190 @deffn {Command} adapter_khz max_speed_kHz
3191 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3192 JTAG interfaces usually support a limited number of
3193 speeds. The speed actually used won't be faster
3194 than the speed specified.
3196 Chip data sheets generally include a top JTAG clock rate.
3197 The actual rate is often a function of a CPU core clock,
3198 and is normally less than that peak rate.
3199 For example, most ARM cores accept at most one sixth of the CPU clock.
3201 Speed 0 (khz) selects RTCK method.
3202 @xref{faqrtck,,FAQ RTCK}.
3203 If your system uses RTCK, you won't need to change the
3204 JTAG clocking after setup.
3205 Not all interfaces, boards, or targets support ``rtck''.
3206 If the interface device can not
3207 support it, an error is returned when you try to use RTCK.
3208 @end deffn
3210 @defun jtag_rclk fallback_speed_kHz
3211 @cindex adaptive clocking
3212 @cindex RTCK
3213 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3214 If that fails (maybe the interface, board, or target doesn't
3215 support it), falls back to the specified frequency.
3216 @example
3217 # Fall back to 3mhz if RTCK is not supported
3218 jtag_rclk 3000
3219 @end example
3220 @end defun
3222 @node Reset Configuration
3223 @chapter Reset Configuration
3224 @cindex Reset Configuration
3226 Every system configuration may require a different reset
3227 configuration. This can also be quite confusing.
3228 Resets also interact with @var{reset-init} event handlers,
3229 which do things like setting up clocks and DRAM, and
3230 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3231 They can also interact with JTAG routers.
3232 Please see the various board files for examples.
3234 @quotation Note
3235 To maintainers and integrators:
3236 Reset configuration touches several things at once.
3237 Normally the board configuration file
3238 should define it and assume that the JTAG adapter supports
3239 everything that's wired up to the board's JTAG connector.
3241 However, the target configuration file could also make note
3242 of something the silicon vendor has done inside the chip,
3243 which will be true for most (or all) boards using that chip.
3244 And when the JTAG adapter doesn't support everything, the
3245 user configuration file will need to override parts of
3246 the reset configuration provided by other files.
3247 @end quotation
3249 @section Types of Reset
3251 There are many kinds of reset possible through JTAG, but
3252 they may not all work with a given board and adapter.
3253 That's part of why reset configuration can be error prone.
3255 @itemize @bullet
3256 @item
3257 @emph{System Reset} ... the @emph{SRST} hardware signal
3258 resets all chips connected to the JTAG adapter, such as processors,
3259 power management chips, and I/O controllers. Normally resets triggered
3260 with this signal behave exactly like pressing a RESET button.
3261 @item
3262 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3263 just the TAP controllers connected to the JTAG adapter.
3264 Such resets should not be visible to the rest of the system; resetting a
3265 device's TAP controller just puts that controller into a known state.
3266 @item
3267 @emph{Emulation Reset} ... many devices can be reset through JTAG
3268 commands. These resets are often distinguishable from system
3269 resets, either explicitly (a "reset reason" register says so)
3270 or implicitly (not all parts of the chip get reset).
3271 @item
3272 @emph{Other Resets} ... system-on-chip devices often support
3273 several other types of reset.
3274 You may need to arrange that a watchdog timer stops
3275 while debugging, preventing a watchdog reset.
3276 There may be individual module resets.
3277 @end itemize
3279 In the best case, OpenOCD can hold SRST, then reset
3280 the TAPs via TRST and send commands through JTAG to halt the
3281 CPU at the reset vector before the 1st instruction is executed.
3282 Then when it finally releases the SRST signal, the system is
3283 halted under debugger control before any code has executed.
3284 This is the behavior required to support the @command{reset halt}
3285 and @command{reset init} commands; after @command{reset init} a
3286 board-specific script might do things like setting up DRAM.
3287 (@xref{resetcommand,,Reset Command}.)
3289 @anchor{srstandtrstissues}
3290 @section SRST and TRST Issues
3292 Because SRST and TRST are hardware signals, they can have a
3293 variety of system-specific constraints. Some of the most
3294 common issues are:
3296 @itemize @bullet
3298 @item @emph{Signal not available} ... Some boards don't wire
3299 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3300 support such signals even if they are wired up.
3301 Use the @command{reset_config} @var{signals} options to say
3302 when either of those signals is not connected.
3303 When SRST is not available, your code might not be able to rely
3304 on controllers having been fully reset during code startup.
3305 Missing TRST is not a problem, since JTAG-level resets can
3306 be triggered using with TMS signaling.
3308 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3309 adapter will connect SRST to TRST, instead of keeping them separate.
3310 Use the @command{reset_config} @var{combination} options to say
3311 when those signals aren't properly independent.
3313 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3314 delay circuit, reset supervisor, or on-chip features can extend
3315 the effect of a JTAG adapter's reset for some time after the adapter
3316 stops issuing the reset. For example, there may be chip or board
3317 requirements that all reset pulses last for at least a
3318 certain amount of time; and reset buttons commonly have
3319 hardware debouncing.
3320 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3321 commands to say when extra delays are needed.
3323 @item @emph{Drive type} ... Reset lines often have a pullup
3324 resistor, letting the JTAG interface treat them as open-drain
3325 signals. But that's not a requirement, so the adapter may need
3326 to use push/pull output drivers.
3327 Also, with weak pullups it may be advisable to drive
3328 signals to both levels (push/pull) to minimize rise times.
3329 Use the @command{reset_config} @var{trst_type} and
3330 @var{srst_type} parameters to say how to drive reset signals.
3332 @item @emph{Special initialization} ... Targets sometimes need
3333 special JTAG initialization sequences to handle chip-specific
3334 issues (not limited to errata).
3335 For example, certain JTAG commands might need to be issued while
3336 the system as a whole is in a reset state (SRST active)
3337 but the JTAG scan chain is usable (TRST inactive).
3338 Many systems treat combined assertion of SRST and TRST as a
3339 trigger for a harder reset than SRST alone.
3340 Such custom reset handling is discussed later in this chapter.
3341 @end itemize
3343 There can also be other issues.
3344 Some devices don't fully conform to the JTAG specifications.
3345 Trivial system-specific differences are common, such as
3346 SRST and TRST using slightly different names.
3347 There are also vendors who distribute key JTAG documentation for
3348 their chips only to developers who have signed a Non-Disclosure
3349 Agreement (NDA).
3351 Sometimes there are chip-specific extensions like a requirement to use
3352 the normally-optional TRST signal (precluding use of JTAG adapters which
3353 don't pass TRST through), or needing extra steps to complete a TAP reset.
3355 In short, SRST and especially TRST handling may be very finicky,
3356 needing to cope with both architecture and board specific constraints.
3358 @section Commands for Handling Resets
3360 @deffn {Command} adapter_nsrst_assert_width milliseconds
3361 Minimum amount of time (in milliseconds) OpenOCD should wait
3362 after asserting nSRST (active-low system reset) before
3363 allowing it to be deasserted.
3364 @end deffn
3366 @deffn {Command} adapter_nsrst_delay milliseconds
3367 How long (in milliseconds) OpenOCD should wait after deasserting
3368 nSRST (active-low system reset) before starting new JTAG operations.
3369 When a board has a reset button connected to SRST line it will
3370 probably have hardware debouncing, implying you should use this.
3371 @end deffn
3373 @deffn {Command} jtag_ntrst_assert_width milliseconds
3374 Minimum amount of time (in milliseconds) OpenOCD should wait
3375 after asserting nTRST (active-low JTAG TAP reset) before
3376 allowing it to be deasserted.
3377 @end deffn
3379 @deffn {Command} jtag_ntrst_delay milliseconds
3380 How long (in milliseconds) OpenOCD should wait after deasserting
3381 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3382 @end deffn
3384 @deffn {Command} reset_config mode_flag ...
3385 This command displays or modifies the reset configuration
3386 of your combination of JTAG board and target in target
3387 configuration scripts.
3389 Information earlier in this section describes the kind of problems
3390 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3391 As a rule this command belongs only in board config files,
3392 describing issues like @emph{board doesn't connect TRST};
3393 or in user config files, addressing limitations derived
3394 from a particular combination of interface and board.
3395 (An unlikely example would be using a TRST-only adapter
3396 with a board that only wires up SRST.)
3398 The @var{mode_flag} options can be specified in any order, but only one
3399 of each type -- @var{signals}, @var{combination}, @var{gates},
3400 @var{trst_type}, @var{srst_type} and @var{connect_type}
3401 -- may be specified at a time.
3402 If you don't provide a new value for a given type, its previous
3403 value (perhaps the default) is unchanged.
3404 For example, this means that you don't need to say anything at all about
3405 TRST just to declare that if the JTAG adapter should want to drive SRST,
3406 it must explicitly be driven high (@option{srst_push_pull}).
3408 @itemize
3409 @item
3410 @var{signals} can specify which of the reset signals are connected.
3411 For example, If the JTAG interface provides SRST, but the board doesn't
3412 connect that signal properly, then OpenOCD can't use it.
3413 Possible values are @option{none} (the default), @option{trst_only},
3414 @option{srst_only} and @option{trst_and_srst}.
3416 @quotation Tip
3417 If your board provides SRST and/or TRST through the JTAG connector,
3418 you must declare that so those signals can be used.
3419 @end quotation
3421 @item
3422 The @var{combination} is an optional value specifying broken reset
3423 signal implementations.
3424 The default behaviour if no option given is @option{separate},
3425 indicating everything behaves normally.
3426 @option{srst_pulls_trst} states that the
3427 test logic is reset together with the reset of the system (e.g. NXP
3428 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3429 the system is reset together with the test logic (only hypothetical, I
3430 haven't seen hardware with such a bug, and can be worked around).
3431 @option{combined} implies both @option{srst_pulls_trst} and
3432 @option{trst_pulls_srst}.
3434 @item
3435 The @var{gates} tokens control flags that describe some cases where
3436 JTAG may be unvailable during reset.
3437 @option{srst_gates_jtag} (default)
3438 indicates that asserting SRST gates the
3439 JTAG clock. This means that no communication can happen on JTAG
3440 while SRST is asserted.
3441 Its converse is @option{srst_nogate}, indicating that JTAG commands
3442 can safely be issued while SRST is active.
3444 @item
3445 The @var{connect_type} tokens control flags that describe some cases where
3446 SRST is asserted while connecting to the target. @option{srst_nogate}
3447 is required to use this option.
3448 @option{connect_deassert_srst} (default)
3449 indicates that SRST will not be asserted while connecting to the target.
3450 Its converse is @option{connect_assert_srst}, indicating that SRST will
3451 be asserted before any target connection.
3452 Only some targets support this feature, STM32 and STR9 are examples.
3453 This feature is useful if you are unable to connect to your target due
3454 to incorrect options byte config or illegal program execution.
3455 @end itemize
3457 The optional @var{trst_type} and @var{srst_type} parameters allow the
3458 driver mode of each reset line to be specified. These values only affect
3459 JTAG interfaces with support for different driver modes, like the Amontec
3460 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3461 relevant signal (TRST or SRST) is not connected.
3463 @itemize
3464 @item
3465 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3466 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3467 Most boards connect this signal to a pulldown, so the JTAG TAPs
3468 never leave reset unless they are hooked up to a JTAG adapter.
3470 @item
3471 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3472 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3473 Most boards connect this signal to a pullup, and allow the
3474 signal to be pulled low by various events including system
3475 powerup and pressing a reset button.
3476 @end itemize
3477 @end deffn
3479 @section Custom Reset Handling
3480 @cindex events
3482 OpenOCD has several ways to help support the various reset
3483 mechanisms provided by chip and board vendors.
3484 The commands shown in the previous section give standard parameters.
3485 There are also @emph{event handlers} associated with TAPs or Targets.
3486 Those handlers are Tcl procedures you can provide, which are invoked
3487 at particular points in the reset sequence.
3489 @emph{When SRST is not an option} you must set
3490 up a @code{reset-assert} event handler for your target.
3491 For example, some JTAG adapters don't include the SRST signal;
3492 and some boards have multiple targets, and you won't always
3493 want to reset everything at once.
3495 After configuring those mechanisms, you might still
3496 find your board doesn't start up or reset correctly.
3497 For example, maybe it needs a slightly different sequence
3498 of SRST and/or TRST manipulations, because of quirks that
3499 the @command{reset_config} mechanism doesn't address;
3500 or asserting both might trigger a stronger reset, which
3501 needs special attention.
3503 Experiment with lower level operations, such as @command{jtag_reset}
3504 and the @command{jtag arp_*} operations shown here,
3505 to find a sequence of operations that works.
3506 @xref{JTAG Commands}.
3507 When you find a working sequence, it can be used to override
3508 @command{jtag_init}, which fires during OpenOCD startup
3509 (@pxref{configurationstage,,Configuration Stage});
3510 or @command{init_reset}, which fires during reset processing.
3512 You might also want to provide some project-specific reset
3513 schemes. For example, on a multi-target board the standard
3514 @command{reset} command would reset all targets, but you
3515 may need the ability to reset only one target at time and
3516 thus want to avoid using the board-wide SRST signal.
3518 @deffn {Overridable Procedure} init_reset mode
3519 This is invoked near the beginning of the @command{reset} command,
3520 usually to provide as much of a cold (power-up) reset as practical.
3521 By default it is also invoked from @command{jtag_init} if
3522 the scan chain does not respond to pure JTAG operations.
3523 The @var{mode} parameter is the parameter given to the
3524 low level reset command (@option{halt},
3525 @option{init}, or @option{run}), @option{setup},
3526 or potentially some other value.
3528 The default implementation just invokes @command{jtag arp_init-reset}.
3529 Replacements will normally build on low level JTAG
3530 operations such as @command{jtag_reset}.
3531 Operations here must not address individual TAPs
3532 (or their associated targets)
3533 until the JTAG scan chain has first been verified to work.
3535 Implementations must have verified the JTAG scan chain before
3536 they return.
3537 This is done by calling @command{jtag arp_init}
3538 (or @command{jtag arp_init-reset}).
3539 @end deffn
3541 @deffn Command {jtag arp_init}
3542 This validates the scan chain using just the four
3543 standard JTAG signals (TMS, TCK, TDI, TDO).
3544 It starts by issuing a JTAG-only reset.
3545 Then it performs checks to verify that the scan chain configuration
3546 matches the TAPs it can observe.
3547 Those checks include checking IDCODE values for each active TAP,
3548 and verifying the length of their instruction registers using
3549 TAP @code{-ircapture} and @code{-irmask} values.
3550 If these tests all pass, TAP @code{setup} events are
3551 issued to all TAPs with handlers for that event.
3552 @end deffn
3554 @deffn Command {jtag arp_init-reset}
3555 This uses TRST and SRST to try resetting
3556 everything on the JTAG scan chain
3557 (and anything else connected to SRST).
3558 It then invokes the logic of @command{jtag arp_init}.
3559 @end deffn
3562 @node TAP Declaration
3563 @chapter TAP Declaration
3564 @cindex TAP declaration
3565 @cindex TAP configuration
3567 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3568 TAPs serve many roles, including:
3570 @itemize @bullet
3571 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
3572 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
3573 Others do it indirectly, making a CPU do it.
3574 @item @b{Program Download} Using the same CPU support GDB uses,
3575 you can initialize a DRAM controller, download code to DRAM, and then
3576 start running that code.
3577 @item @b{Boundary Scan} Most chips support boundary scan, which
3578 helps test for board assembly problems like solder bridges
3579 and missing connections
3580 @end itemize
3582 OpenOCD must know about the active TAPs on your board(s).
3583 Setting up the TAPs is the core task of your configuration files.
3584 Once those TAPs are set up, you can pass their names to code
3585 which sets up CPUs and exports them as GDB targets,
3586 probes flash memory, performs low-level JTAG operations, and more.
3588 @section Scan Chains
3589 @cindex scan chain
3591 TAPs are part of a hardware @dfn{scan chain},
3592 which is daisy chain of TAPs.
3593 They also need to be added to
3594 OpenOCD's software mirror of that hardware list,
3595 giving each member a name and associating other data with it.
3596 Simple scan chains, with a single TAP, are common in
3597 systems with a single microcontroller or microprocessor.
3598 More complex chips may have several TAPs internally.
3599 Very complex scan chains might have a dozen or more TAPs:
3600 several in one chip, more in the next, and connecting
3601 to other boards with their own chips and TAPs.
3603 You can display the list with the @command{scan_chain} command.
3604 (Don't confuse this with the list displayed by the @command{targets}
3605 command, presented in the next chapter.
3606 That only displays TAPs for CPUs which are configured as
3607 debugging targets.)
3608 Here's what the scan chain might look like for a chip more than one TAP:
3610 @verbatim
3611 TapName Enabled IdCode Expected IrLen IrCap IrMask
3612 -- ------------------ ------- ---------- ---------- ----- ----- ------
3613 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3614 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3615 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3616 @end verbatim
3618 OpenOCD can detect some of that information, but not all
3619 of it. @xref{autoprobing,,Autoprobing}.
3620 Unfortunately those TAPs can't always be autoconfigured,
3621 because not all devices provide good support for that.
3622 JTAG doesn't require supporting IDCODE instructions, and
3623 chips with JTAG routers may not link TAPs into the chain
3624 until they are told to do so.
3626 The configuration mechanism currently supported by OpenOCD
3627 requires explicit configuration of all TAP devices using
3628 @command{jtag newtap} commands, as detailed later in this chapter.
3629 A command like this would declare one tap and name it @code{chip1.cpu}:
3631 @example
3632 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3633 @end example
3635 Each target configuration file lists the TAPs provided
3636 by a given chip.
3637 Board configuration files combine all the targets on a board,
3638 and so forth.
3639 Note that @emph{the order in which TAPs are declared is very important.}
3640 It must match the order in the JTAG scan chain, both inside
3641 a single chip and between them.
3642 @xref{faqtaporder,,FAQ TAP Order}.
3644 For example, the ST Microsystems STR912 chip has
3645 three separate TAPs@footnote{See the ST
3646 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3647 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3648 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3649 To configure those taps, @file{target/str912.cfg}
3650 includes commands something like this:
3652 @example
3653 jtag newtap str912 flash ... params ...
3654 jtag newtap str912 cpu ... params ...
3655 jtag newtap str912 bs ... params ...
3656 @end example
3658 Actual config files use a variable instead of literals like
3659 @option{str912}, to support more than one chip of each type.
3660 @xref{Config File Guidelines}.
3662 @deffn Command {jtag names}
3663 Returns the names of all current TAPs in the scan chain.
3664 Use @command{jtag cget} or @command{jtag tapisenabled}
3665 to examine attributes and state of each TAP.
3666 @example
3667 foreach t [jtag names] @{
3668 puts [format "TAP: %s\n" $t]
3669 @}
3670 @end example
3671 @end deffn
3673 @deffn Command {scan_chain}
3674 Displays the TAPs in the scan chain configuration,
3675 and their status.
3676 The set of TAPs listed by this command is fixed by
3677 exiting the OpenOCD configuration stage,
3678 but systems with a JTAG router can
3679 enable or disable TAPs dynamically.
3680 @end deffn
3682 @c FIXME! "jtag cget" should be able to return all TAP
3683 @c attributes, like "$target_name cget" does for targets.
3685 @c Probably want "jtag eventlist", and a "tap-reset" event
3686 @c (on entry to RESET state).
3688 @section TAP Names
3689 @cindex dotted name
3691 When TAP objects are declared with @command{jtag newtap},
3692 a @dfn{dotted.name} is created for the TAP, combining the
3693 name of a module (usually a chip) and a label for the TAP.
3694 For example: @code{xilinx.tap}, @code{str912.flash},
3695 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3696 Many other commands use that dotted.name to manipulate or
3697 refer to the TAP. For example, CPU configuration uses the
3698 name, as does declaration of NAND or NOR flash banks.
3700 The components of a dotted name should follow ``C'' symbol
3701 name rules: start with an alphabetic character, then numbers
3702 and underscores are OK; while others (including dots!) are not.
3704 @quotation Tip
3705 In older code, JTAG TAPs were numbered from 0..N.
3706 This feature is still present.
3707 However its use is highly discouraged, and
3708 should not be relied on; it will be removed by mid-2010.
3709 Update all of your scripts to use TAP names rather than numbers,
3710 by paying attention to the runtime warnings they trigger.
3711 Using TAP numbers in target configuration scripts prevents
3712 reusing those scripts on boards with multiple targets.
3713 @end quotation
3715 @section TAP Declaration Commands
3717 @c shouldn't this be(come) a {Config Command}?
3718 @deffn Command {jtag newtap} chipname tapname configparams...
3719 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3720 and configured according to the various @var{configparams}.
3722 The @var{chipname} is a symbolic name for the chip.
3723 Conventionally target config files use @code{$_CHIPNAME},
3724 defaulting to the model name given by the chip vendor but
3725 overridable.
3727 @cindex TAP naming convention
3728 The @var{tapname} reflects the role of that TAP,
3729 and should follow this convention:
3731 @itemize @bullet
3732 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3733 @item @code{cpu} -- The main CPU of the chip, alternatively
3734 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3735 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3736 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3737 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3738 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3739 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3740 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3741 with a single TAP;
3742 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3743 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3744 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3745 a JTAG TAP; that TAP should be named @code{sdma}.
3746 @end itemize
3748 Every TAP requires at least the following @var{configparams}:
3750 @itemize @bullet
3751 @item @code{-irlen} @var{NUMBER}
3752 @*The length in bits of the
3753 instruction register, such as 4 or 5 bits.
3754 @end itemize
3756 A TAP may also provide optional @var{configparams}:
3758 @itemize @bullet
3759 @item @code{-disable} (or @code{-enable})
3760 @*Use the @code{-disable} parameter to flag a TAP which is not
3761 linked in to the scan chain after a reset using either TRST
3762 or the JTAG state machine's @sc{reset} state.
3763 You may use @code{-enable} to highlight the default state
3764 (the TAP is linked in).
3765 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3766 @item @code{-expected-id} @var{number}
3767 @*A non-zero @var{number} represents a 32-bit IDCODE
3768 which you expect to find when the scan chain is examined.
3769 These codes are not required by all JTAG devices.
3770 @emph{Repeat the option} as many times as required if more than one
3771 ID code could appear (for example, multiple versions).
3772 Specify @var{number} as zero to suppress warnings about IDCODE
3773 values that were found but not included in the list.
3775 Provide this value if at all possible, since it lets OpenOCD
3776 tell when the scan chain it sees isn't right. These values
3777 are provided in vendors' chip documentation, usually a technical
3778 reference manual. Sometimes you may need to probe the JTAG
3779 hardware to find these values.
3780 @xref{autoprobing,,Autoprobing}.
3781 @item @code{-ignore-version}
3782 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3783 option. When vendors put out multiple versions of a chip, or use the same
3784 JTAG-level ID for several largely-compatible chips, it may be more practical
3785 to ignore the version field than to update config files to handle all of
3786 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3787 @item @code{-ircapture} @var{NUMBER}
3788 @*The bit pattern loaded by the TAP into the JTAG shift register
3789 on entry to the @sc{ircapture} state, such as 0x01.
3790 JTAG requires the two LSBs of this value to be 01.
3791 By default, @code{-ircapture} and @code{-irmask} are set
3792 up to verify that two-bit value. You may provide
3793 additional bits, if you know them, or indicate that
3794 a TAP doesn't conform to the JTAG specification.
3795 @item @code{-irmask} @var{NUMBER}
3796 @*A mask used with @code{-ircapture}
3797 to verify that instruction scans work correctly.
3798 Such scans are not used by OpenOCD except to verify that
3799 there seems to be no problems with JTAG scan chain operations.
3800 @end itemize
3801 @end deffn
3803 @section Other TAP commands
3805 @deffn Command {jtag cget} dotted.name @option{-event} name
3806 @deffnx Command {jtag configure} dotted.name @option{-event} name string
3807 At this writing this TAP attribute
3808 mechanism is used only for event handling.
3809 (It is not a direct analogue of the @code{cget}/@code{configure}
3810 mechanism for debugger targets.)
3811 See the next section for information about the available events.
3813 The @code{configure} subcommand assigns an event handler,
3814 a TCL string which is evaluated when the event is triggered.
3815 The @code{cget} subcommand returns that handler.
3816 @end deffn
3818 @section TAP Events
3819 @cindex events
3820 @cindex TAP events
3822 OpenOCD includes two event mechanisms.
3823 The one presented here applies to all JTAG TAPs.
3824 The other applies to debugger targets,
3825 which are associated with certain TAPs.
3827 The TAP events currently defined are:
3829 @itemize @bullet
3830 @item @b{post-reset}
3831 @* The TAP has just completed a JTAG reset.
3832 The tap may still be in the JTAG @sc{reset} state.
3833 Handlers for these events might perform initialization sequences
3834 such as issuing TCK cycles, TMS sequences to ensure
3835 exit from the ARM SWD mode, and more.
3837 Because the scan chain has not yet been verified, handlers for these events
3838 @emph{should not issue commands which scan the JTAG IR or DR registers}
3839 of any particular target.
3840 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3841 @item @b{setup}
3842 @* The scan chain has been reset and verified.
3843 This handler may enable TAPs as needed.
3844 @item @b{tap-disable}
3845 @* The TAP needs to be disabled. This handler should
3846 implement @command{jtag tapdisable}
3847 by issuing the relevant JTAG commands.
3848 @item @b{tap-enable}
3849 @* The TAP needs to be enabled. This handler should
3850 implement @command{jtag tapenable}
3851 by issuing the relevant JTAG commands.
3852 @end itemize
3854 If you need some action after each JTAG reset, which isn't actually
3855 specific to any TAP (since you can't yet trust the scan chain's
3856 contents to be accurate), you might:
3858 @example
3859 jtag configure CHIP.jrc -event post-reset @{
3860 echo "JTAG Reset done"
3861 ... non-scan jtag operations to be done after reset
3862 @}
3863 @end example
3866 @anchor{enablinganddisablingtaps}
3867 @section Enabling and Disabling TAPs
3868 @cindex JTAG Route Controller
3869 @cindex jrc
3871 In some systems, a @dfn{JTAG Route Controller} (JRC)
3872 is used to enable and/or disable specific JTAG TAPs.
3873 Many ARM based chips from Texas Instruments include
3874 an ``ICEpick'' module, which is a JRC.
3875 Such chips include DaVinci and OMAP3 processors.
3877 A given TAP may not be visible until the JRC has been
3878 told to link it into the scan chain; and if the JRC
3879 has been told to unlink that TAP, it will no longer
3880 be visible.
3881 Such routers address problems that JTAG ``bypass mode''
3882 ignores, such as:
3884 @itemize
3885 @item The scan chain can only go as fast as its slowest TAP.
3886 @item Having many TAPs slows instruction scans, since all
3887 TAPs receive new instructions.
3888 @item TAPs in the scan chain must be powered up, which wastes
3889 power and prevents debugging some power management mechanisms.
3890 @end itemize
3892 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3893 as implied by the existence of JTAG routers.
3894 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3895 does include a kind of JTAG router functionality.
3897 @c (a) currently the event handlers don't seem to be able to
3898 @c fail in a way that could lead to no-change-of-state.
3900 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3901 shown below, and is implemented using TAP event handlers.
3902 So for example, when defining a TAP for a CPU connected to
3903 a JTAG router, your @file{target.cfg} file
3904 should define TAP event handlers using
3905 code that looks something like this:
3907 @example
3908 jtag configure CHIP.cpu -event tap-enable @{
3909 ... jtag operations using CHIP.jrc
3910 @}
3911 jtag configure CHIP.cpu -event tap-disable @{
3912 ... jtag operations using CHIP.jrc
3913 @}
3914 @end example
3916 Then you might want that CPU's TAP enabled almost all the time:
3918 @example
3919 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3920 @end example
3922 Note how that particular setup event handler declaration
3923 uses quotes to evaluate @code{$CHIP} when the event is configured.
3924 Using brackets @{ @} would cause it to be evaluated later,
3925 at runtime, when it might have a different value.
3927 @deffn Command {jtag tapdisable} dotted.name
3928 If necessary, disables the tap
3929 by sending it a @option{tap-disable} event.
3930 Returns the string "1" if the tap
3931 specified by @var{dotted.name} is enabled,
3932 and "0" if it is disabled.
3933 @end deffn
3935 @deffn Command {jtag tapenable} dotted.name
3936 If necessary, enables the tap
3937 by sending it a @option{tap-enable} event.
3938 Returns the string "1" if the tap
3939 specified by @var{dotted.name} is enabled,
3940 and "0" if it is disabled.
3941 @end deffn
3943 @deffn Command {jtag tapisenabled} dotted.name
3944 Returns the string "1" if the tap
3945 specified by @var{dotted.name} is enabled,
3946 and "0" if it is disabled.
3948 @quotation Note
3949 Humans will find the @command{scan_chain} command more helpful
3950 for querying the state of the JTAG taps.
3951 @end quotation
3952 @end deffn
3954 @anchor{autoprobing}
3955 @section Autoprobing
3956 @cindex autoprobe
3957 @cindex JTAG autoprobe
3959 TAP configuration is the first thing that needs to be done
3960 after interface and reset configuration. Sometimes it's
3961 hard finding out what TAPs exist, or how they are identified.
3962 Vendor documentation is not always easy to find and use.
3964 To help you get past such problems, OpenOCD has a limited
3965 @emph{autoprobing} ability to look at the scan chain, doing
3966 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3967 To use this mechanism, start the OpenOCD server with only data
3968 that configures your JTAG interface, and arranges to come up
3969 with a slow clock (many devices don't support fast JTAG clocks
3970 right when they come out of reset).
3972 For example, your @file{openocd.cfg} file might have:
3974 @example
3975 source [find interface/olimex-arm-usb-tiny-h.cfg]
3976 reset_config trst_and_srst
3977 jtag_rclk 8
3978 @end example
3980 When you start the server without any TAPs configured, it will
3981 attempt to autoconfigure the TAPs. There are two parts to this:
3983 @enumerate
3984 @item @emph{TAP discovery} ...
3985 After a JTAG reset (sometimes a system reset may be needed too),
3986 each TAP's data registers will hold the contents of either the
3987 IDCODE or BYPASS register.
3988 If JTAG communication is working, OpenOCD will see each TAP,
3989 and report what @option{-expected-id} to use with it.
3990 @item @emph{IR Length discovery} ...
3991 Unfortunately JTAG does not provide a reliable way to find out
3992 the value of the @option{-irlen} parameter to use with a TAP
3993 that is discovered.
3994 If OpenOCD can discover the length of a TAP's instruction
3995 register, it will report it.
3996 Otherwise you may need to consult vendor documentation, such
3997 as chip data sheets or BSDL files.
3998 @end enumerate
4000 In many cases your board will have a simple scan chain with just
4001 a single device. Here's what OpenOCD reported with one board
4002 that's a bit more complex:
4004 @example
4005 clock speed 8 kHz
4006 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4007 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4008 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4009 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4010 AUTO auto0.tap - use "... -irlen 4"
4011 AUTO auto1.tap - use "... -irlen 4"
4012 AUTO auto2.tap - use "... -irlen 6"
4013 no gdb ports allocated as no target has been specified
4014 @end example
4016 Given that information, you should be able to either find some existing
4017 config files to use, or create your own. If you create your own, you
4018 would configure from the bottom up: first a @file{target.cfg} file
4019 with these TAPs, any targets associated with them, and any on-chip
4020 resources; then a @file{board.cfg} with off-chip resources, clocking,
4021 and so forth.
4023 @node CPU Configuration
4024 @chapter CPU Configuration
4025 @cindex GDB target
4027 This chapter discusses how to set up GDB debug targets for CPUs.
4028 You can also access these targets without GDB
4029 (@pxref{Architecture and Core Commands},
4030 and @ref{targetstatehandling,,Target State handling}) and
4031 through various kinds of NAND and NOR flash commands.
4032 If you have multiple CPUs you can have multiple such targets.
4034 We'll start by looking at how to examine the targets you have,
4035 then look at how to add one more target and how to configure it.
4037 @section Target List
4038 @cindex target, current
4039 @cindex target, list
4041 All targets that have been set up are part of a list,
4042 where each member has a name.
4043 That name should normally be the same as the TAP name.
4044 You can display the list with the @command{targets}
4045 (plural!) command.
4046 This display often has only one CPU; here's what it might
4047 look like with more than one:
4048 @verbatim
4049 TargetName Type Endian TapName State
4050 -- ------------------ ---------- ------ ------------------ ------------
4051 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4052 1 MyTarget cortex_m little mychip.foo tap-disabled
4053 @end verbatim
4055 One member of that list is the @dfn{current target}, which
4056 is implicitly referenced by many commands.
4057 It's the one marked with a @code{*} near the target name.
4058 In particular, memory addresses often refer to the address
4059 space seen by that current target.
4060 Commands like @command{mdw} (memory display words)
4061 and @command{flash erase_address} (erase NOR flash blocks)
4062 are examples; and there are many more.
4064 Several commands let you examine the list of targets:
4066 @deffn Command {target count}
4067 @emph{Note: target numbers are deprecated; don't use them.
4068 They will be removed shortly after August 2010, including this command.
4069 Iterate target using @command{target names}, not by counting.}
4071 Returns the number of targets, @math{N}.
4072 The highest numbered target is @math{N - 1}.
4073 @example
4074 set c [target count]
4075 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
4076 # Assuming you have created this function
4077 print_target_details $x
4078 @}
4079 @end example
4080 @end deffn
4082 @deffn Command {target current}
4083 Returns the name of the current target.
4084 @end deffn
4086 @deffn Command {target names}
4087 Lists the names of all current targets in the list.
4088 @example
4089 foreach t [target names] @{
4090 puts [format "Target: %s\n" $t]
4091 @}
4092 @end example
4093 @end deffn
4095 @deffn Command {target number} number
4096 @emph{Note: target numbers are deprecated; don't use them.
4097 They will be removed shortly after August 2010, including this command.}
4099 The list of targets is numbered starting at zero.
4100 This command returns the name of the target at index @var{number}.
4101 @example
4102 set thename [target number $x]
4103 puts [format "Target %d is: %s\n" $x $thename]
4104 @end example
4105 @end deffn
4107 @c yep, "target list" would have been better.
4108 @c plus maybe "target setdefault".
4110 @deffn Command targets [name]
4111 @emph{Note: the name of this command is plural. Other target
4112 command names are singular.}
4114 With no parameter, this command displays a table of all known
4115 targets in a user friendly form.
4117 With a parameter, this command sets the current target to
4118 the given target with the given @var{name}; this is
4119 only relevant on boards which have more than one target.
4120 @end deffn
4122 @section Target CPU Types and Variants
4123 @cindex target type
4124 @cindex CPU type
4125 @cindex CPU variant
4127 Each target has a @dfn{CPU type}, as shown in the output of
4128 the @command{targets} command. You need to specify that type
4129 when calling @command{target create}.
4130 The CPU type indicates more than just the instruction set.
4131 It also indicates how that instruction set is implemented,
4132 what kind of debug support it integrates,
4133 whether it has an MMU (and if so, what kind),
4134 what core-specific commands may be available
4135 (@pxref{Architecture and Core Commands}),
4136 and more.
4138 For some CPU types, OpenOCD also defines @dfn{variants} which
4139 indicate differences that affect their handling.
4140 For example, a particular implementation bug might need to be
4141 worked around in some chip versions.
4143 It's easy to see what target types are supported,
4144 since there's a command to list them.
4145 However, there is currently no way to list what target variants
4146 are supported (other than by reading the OpenOCD source code).
4148 @anchor{targettypes}
4149 @deffn Command {target types}
4150 Lists all supported target types.
4151 At this writing, the supported CPU types and variants are:
4153 @itemize @bullet
4154 @item @code{arm11} -- this is a generation of ARMv6 cores
4155 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4156 @item @code{arm7tdmi} -- this is an ARMv4 core
4157 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4158 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4159 @item @code{arm966e} -- this is an ARMv5 core
4160 @item @code{arm9tdmi} -- this is an ARMv4 core
4161 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4162 (Support for this is preliminary and incomplete.)
4163 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4164 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4165 compact Thumb2 instruction set.
4166 @item @code{dragonite} -- resembles arm966e
4167 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4168 (Support for this is still incomplete.)
4169 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4170 @item @code{feroceon} -- resembles arm926
4171 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
4172 @item @code{xscale} -- this is actually an architecture,
4173 not a CPU type. It is based on the ARMv5 architecture.
4174 There are several variants defined:
4175 @itemize @minus
4176 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
4177 @code{pxa27x} ... instruction register length is 7 bits
4178 @item @code{pxa250}, @code{pxa255},
4179 @code{pxa26x} ... instruction register length is 5 bits
4180 @item @code{pxa3xx} ... instruction register length is 11 bits
4181 @end itemize
4182 @end itemize
4183 @end deffn
4185 To avoid being confused by the variety of ARM based cores, remember
4186 this key point: @emph{ARM is a technology licencing company}.
4187 (See: @url{http://www.arm.com}.)
4188 The CPU name used by OpenOCD will reflect the CPU design that was
4189 licenced, not a vendor brand which incorporates that design.
4190 Name prefixes like arm7, arm9, arm11, and cortex
4191 reflect design generations;
4192 while names like ARMv4, ARMv5, ARMv6, and ARMv7
4193 reflect an architecture version implemented by a CPU design.
4195 @anchor{targetconfiguration}
4196 @section Target Configuration
4198 Before creating a ``target'', you must have added its TAP to the scan chain.
4199 When you've added that TAP, you will have a @code{dotted.name}
4200 which is used to set up the CPU support.
4201 The chip-specific configuration file will normally configure its CPU(s)
4202 right after it adds all of the chip's TAPs to the scan chain.
4204 Although you can set up a target in one step, it's often clearer if you
4205 use shorter commands and do it in two steps: create it, then configure
4206 optional parts.
4207 All operations on the target after it's created will use a new
4208 command, created as part of target creation.
4210 The two main things to configure after target creation are
4211 a work area, which usually has target-specific defaults even
4212 if the board setup code overrides them later;
4213 and event handlers (@pxref{targetevents,,Target Events}), which tend
4214 to be much more board-specific.
4215 The key steps you use might look something like this
4217 @example
4218 target create MyTarget cortex_m -chain-position mychip.cpu
4219 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4220 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4221 $MyTarget configure -event reset-init @{ myboard_reinit @}
4222 @end example
4224 You should specify a working area if you can; typically it uses some
4225 on-chip SRAM.
4226 Such a working area can speed up many things, including bulk
4227 writes to target memory;
4228 flash operations like checking to see if memory needs to be erased;
4229 GDB memory checksumming;
4230 and more.
4232 @quotation Warning
4233 On more complex chips, the work area can become
4234 inaccessible when application code
4235 (such as an operating system)
4236 enables or disables the MMU.
4237 For example, the particular MMU context used to acess the virtual
4238 address will probably matter ... and that context might not have
4239 easy access to other addresses needed.
4240 At this writing, OpenOCD doesn't have much MMU intelligence.
4241 @end quotation
4243 It's often very useful to define a @code{reset-init} event handler.
4244 For systems that are normally used with a boot loader,
4245 common tasks include updating clocks and initializing memory
4246 controllers.
4247 That may be needed to let you write the boot loader into flash,
4248 in order to ``de-brick'' your board; or to load programs into
4249 external DDR memory without having run the boot loader.
4251 @deffn Command {target create} target_name type configparams...
4252 This command creates a GDB debug target that refers to a specific JTAG tap.
4253 It enters that target into a list, and creates a new
4254 command (@command{@var{target_name}}) which is used for various
4255 purposes including additional configuration.
4257 @itemize @bullet
4258 @item @var{target_name} ... is the name of the debug target.
4259 By convention this should be the same as the @emph{dotted.name}
4260 of the TAP associated with this target, which must be specified here
4261 using the @code{-chain-position @var{dotted.name}} configparam.
4263 This name is also used to create the target object command,
4264 referred to here as @command{$target_name},
4265 and in other places the target needs to be identified.
4266 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4267 @item @var{configparams} ... all parameters accepted by
4268 @command{$target_name configure} are permitted.
4269 If the target is big-endian, set it here with @code{-endian big}.
4270 If the variant matters, set it here with @code{-variant}.
4272 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
4273 @end itemize
4274 @end deffn
4276 @deffn Command {$target_name configure} configparams...
4277 The options accepted by this command may also be
4278 specified as parameters to @command{target create}.
4279 Their values can later be queried one at a time by
4280 using the @command{$target_name cget} command.
4282 @emph{Warning:} changing some of these after setup is dangerous.
4283 For example, moving a target from one TAP to another;
4284 and changing its endianness or variant.
4286 @itemize @bullet
4288 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4289 used to access this target.
4291 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4292 whether the CPU uses big or little endian conventions
4294 @item @code{-event} @var{event_name} @var{event_body} --
4295 @xref{targetevents,,Target Events}.
4296 Note that this updates a list of named event handlers.
4297 Calling this twice with two different event names assigns
4298 two different handlers, but calling it twice with the
4299 same event name assigns only one handler.
4301 @item @code{-variant} @var{name} -- specifies a variant of the target,
4302 which OpenOCD needs to know about.
4304 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4305 whether the work area gets backed up; by default,
4306 @emph{it is not backed up.}
4307 When possible, use a working_area that doesn't need to be backed up,
4308 since performing a backup slows down operations.
4309 For example, the beginning of an SRAM block is likely to
4310 be used by most build systems, but the end is often unused.
4312 @item @code{-work-area-size} @var{size} -- specify work are size,
4313 in bytes. The same size applies regardless of whether its physical
4314 or virtual address is being used.
4316 @item @code{-work-area-phys} @var{address} -- set the work area
4317 base @var{address} to be used when no MMU is active.
4319 @item @code{-work-area-virt} @var{address} -- set the work area
4320 base @var{address} to be used when an MMU is active.
4321 @emph{Do not specify a value for this except on targets with an MMU.}
4322 The value should normally correspond to a static mapping for the
4323 @code{-work-area-phys} address, set up by the current operating system.
4325 @anchor{rtostype}
4326 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4327 @var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}|
4328 @option{FreeRTOS}|@option{linux}|@option{ChibiOS}|@option{embKernel}
4329 @xref{gdbrtossupport,,RTOS Support}.
4331 @end itemize
4332 @end deffn
4334 @section Other $target_name Commands
4335 @cindex object command
4337 The Tcl/Tk language has the concept of object commands,
4338 and OpenOCD adopts that same model for targets.
4340 A good Tk example is a on screen button.
4341 Once a button is created a button
4342 has a name (a path in Tk terms) and that name is useable as a first
4343 class command. For example in Tk, one can create a button and later
4344 configure it like this:
4346 @example
4347 # Create
4348 button .foobar -background red -command @{ foo @}
4349 # Modify
4350 .foobar configure -foreground blue
4351 # Query
4352 set x [.foobar cget -background]
4353 # Report
4354 puts [format "The button is %s" $x]
4355 @end example
4357 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4358 button, and its object commands are invoked the same way.
4360 @example
4361 str912.cpu mww 0x1234 0x42
4362 omap3530.cpu mww 0x5555 123
4363 @end example
4365 The commands supported by OpenOCD target objects are:
4367 @deffn Command {$target_name arp_examine}
4368 @deffnx Command {$target_name arp_halt}
4369 @deffnx Command {$target_name arp_poll}
4370 @deffnx Command {$target_name arp_reset}
4371 @deffnx Command {$target_name arp_waitstate}
4372 Internal OpenOCD scripts (most notably @file{startup.tcl})
4373 use these to deal with specific reset cases.
4374 They are not otherwise documented here.
4375 @end deffn
4377 @deffn Command {$target_name array2mem} arrayname width address count
4378 @deffnx Command {$target_name mem2array} arrayname width address count
4379 These provide an efficient script-oriented interface to memory.
4380 The @code{array2mem} primitive writes bytes, halfwords, or words;
4381 while @code{mem2array} reads them.
4382 In both cases, the TCL side uses an array, and
4383 the target side uses raw memory.
4385 The efficiency comes from enabling the use of
4386 bulk JTAG data transfer operations.
4387 The script orientation comes from working with data
4388 values that are packaged for use by TCL scripts;
4389 @command{mdw} type primitives only print data they retrieve,
4390 and neither store nor return those values.
4392 @itemize
4393 @item @var{arrayname} ... is the name of an array variable
4394 @item @var{width} ... is 8/16/32 - indicating the memory access size
4395 @item @var{address} ... is the target memory address
4396 @item @var{count} ... is the number of elements to process
4397 @end itemize
4398 @end deffn
4400 @deffn Command {$target_name cget} queryparm
4401 Each configuration parameter accepted by
4402 @command{$target_name configure}
4403 can be individually queried, to return its current value.
4404 The @var{queryparm} is a parameter name
4405 accepted by that command, such as @code{-work-area-phys}.
4406 There are a few special cases:
4408 @itemize @bullet
4409 @item @code{-event} @var{event_name} -- returns the handler for the
4410 event named @var{event_name}.
4411 This is a special case because setting a handler requires
4412 two parameters.
4413 @item @code{-type} -- returns the target type.
4414 This is a special case because this is set using
4415 @command{target create} and can't be changed
4416 using @command{$target_name configure}.
4417 @end itemize
4419 For example, if you wanted to summarize information about
4420 all the targets you might use something like this:
4422 @example
4423 foreach name [target names] @{
4424 set y [$name cget -endian]
4425 set z [$name cget -type]
4426 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4427 $x $name $y $z]
4428 @}
4429 @end example
4430 @end deffn
4432 @anchor{targetcurstate}
4433 @deffn Command {$target_name curstate}
4434 Displays the current target state:
4435 @code{debug-running},
4436 @code{halted},
4437 @code{reset},
4438 @code{running}, or @code{unknown}.
4439 (Also, @pxref{eventpolling,,Event Polling}.)
4440 @end deffn
4442 @deffn Command {$target_name eventlist}
4443 Displays a table listing all event handlers
4444 currently associated with this target.
4445 @xref{targetevents,,Target Events}.
4446 @end deffn
4448 @deffn Command {$target_name invoke-event} event_name
4449 Invokes the handler for the event named @var{event_name}.
4450 (This is primarily intended for use by OpenOCD framework
4451 code, for example by the reset code in @file{startup.tcl}.)
4452 @end deffn
4454 @deffn Command {$target_name mdw} addr [count]
4455 @deffnx Command {$target_name mdh} addr [count]
4456 @deffnx Command {$target_name mdb} addr [count]
4457 Display contents of address @var{addr}, as
4458 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4459 or 8-bit bytes (@command{mdb}).
4460 If @var{count} is specified, displays that many units.
4461 (If you want to manipulate the data instead of displaying it,
4462 see the @code{mem2array} primitives.)
4463 @end deffn
4465 @deffn Command {$target_name mww} addr word
4466 @deffnx Command {$target_name mwh} addr halfword
4467 @deffnx Command {$target_name mwb} addr byte
4468 Writes the specified @var{word} (32 bits),
4469 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4470 at the specified address @var{addr}.
4471 @end deffn
4473 @anchor{targetevents}
4474 @section Target Events
4475 @cindex target events
4476 @cindex events
4477 At various times, certain things can happen, or you want them to happen.
4478 For example:
4479 @itemize @bullet
4480 @item What should happen when GDB connects? Should your target reset?
4481 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4482 @item Is using SRST appropriate (and possible) on your system?
4483 Or instead of that, do you need to issue JTAG commands to trigger reset?
4484 SRST usually resets everything on the scan chain, which can be inappropriate.
4485 @item During reset, do you need to write to certain memory locations
4486 to set up system clocks or
4487 to reconfigure the SDRAM?
4488 How about configuring the watchdog timer, or other peripherals,
4489 to stop running while you hold the core stopped for debugging?
4490 @end itemize
4492 All of the above items can be addressed by target event handlers.
4493 These are set up by @command{$target_name configure -event} or
4494 @command{target create ... -event}.
4496 The programmer's model matches the @code{-command} option used in Tcl/Tk
4497 buttons and events. The two examples below act the same, but one creates
4498 and invokes a small procedure while the other inlines it.
4500 @example
4501 proc my_attach_proc @{ @} @{
4502 echo "Reset..."
4503 reset halt
4504 @}
4505 mychip.cpu configure -event gdb-attach my_attach_proc
4506 mychip.cpu configure -event gdb-attach @{
4507 echo "Reset..."
4508 # To make flash probe and gdb load to flash work we need a reset init.
4509 reset init
4510 @}
4511 @end example
4513 The following target events are defined:
4515 @itemize @bullet
4516 @item @b{debug-halted}
4517 @* The target has halted for debug reasons (i.e.: breakpoint)
4518 @item @b{debug-resumed}
4519 @* The target has resumed (i.e.: gdb said run)
4520 @item @b{early-halted}
4521 @* Occurs early in the halt process
4522 @item @b{examine-start}
4523 @* Before target examine is called.
4524 @item @b{examine-end}
4525 @* After target examine is called with no errors.
4526 @item @b{gdb-attach}
4527 @* When GDB connects. This is before any communication with the target, so this
4528 can be used to set up the target so it is possible to probe flash. Probing flash
4529 is necessary during gdb connect if gdb load is to write the image to flash. Another
4530 use of the flash memory map is for GDB to automatically hardware/software breakpoints
4531 depending on whether the breakpoint is in RAM or read only memory.
4532 @item @b{gdb-detach}
4533 @* When GDB disconnects
4534 @item @b{gdb-end}
4535 @* When the target has halted and GDB is not doing anything (see early halt)
4536 @item @b{gdb-flash-erase-start}
4537 @* Before the GDB flash process tries to erase the flash
4538 @item @b{gdb-flash-erase-end}
4539 @* After the GDB flash process has finished erasing the flash
4540 @item @b{gdb-flash-write-start}
4541 @* Before GDB writes to the flash
4542 @item @b{gdb-flash-write-end}
4543 @* After GDB writes to the flash
4544 @item @b{gdb-start}
4545 @* Before the target steps, gdb is trying to start/resume the target
4546 @item @b{halted}
4547 @* The target has halted
4548 @item @b{reset-assert-pre}
4549 @* Issued as part of @command{reset} processing
4550 after @command{reset_init} was triggered
4551 but before either SRST alone is re-asserted on the scan chain,
4552 or @code{reset-assert} is triggered.
4553 @item @b{reset-assert}
4554 @* Issued as part of @command{reset} processing
4555 after @command{reset-assert-pre} was triggered.
4556 When such a handler is present, cores which support this event will use
4557 it instead of asserting SRST.
4558 This support is essential for debugging with JTAG interfaces which
4559 don't include an SRST line (JTAG doesn't require SRST), and for
4560 selective reset on scan chains that have multiple targets.
4561 @item @b{reset-assert-post}
4562 @* Issued as part of @command{reset} processing
4563 after @code{reset-assert} has been triggered.
4564 or the target asserted SRST on the entire scan chain.
4565 @item @b{reset-deassert-pre}
4566 @* Issued as part of @command{reset} processing
4567 after @code{reset-assert-post} has been triggered.
4568 @item @b{reset-deassert-post}
4569 @* Issued as part of @command{reset} processing
4570 after @code{reset-deassert-pre} has been triggered
4571 and (if the target is using it) after SRST has been
4572 released on the scan chain.
4573 @item @b{reset-end}
4574 @* Issued as the final step in @command{reset} processing.
4575 @ignore
4576 @item @b{reset-halt-post}
4577 @* Currently not used
4578 @item @b{reset-halt-pre}
4579 @* Currently not used
4580 @end ignore
4581 @item @b{reset-init}
4582 @* Used by @b{reset init} command for board-specific initialization.
4583 This event fires after @emph{reset-deassert-post}.
4585 This is where you would configure PLLs and clocking, set up DRAM so
4586 you can download programs that don't fit in on-chip SRAM, set up pin
4587 multiplexing, and so on.
4588 (You may be able to switch to a fast JTAG clock rate here, after
4589 the target clocks are fully set up.)
4590 @item @b{reset-start}
4591 @* Issued as part of @command{reset} processing
4592 before @command{reset_init} is called.
4594 This is the most robust place to use @command{jtag_rclk}
4595 or @command{adapter_khz} to switch to a low JTAG clock rate,
4596 when reset disables PLLs needed to use a fast clock.
4597 @ignore
4598 @item @b{reset-wait-pos}
4599 @* Currently not used
4600 @item @b{reset-wait-pre}
4601 @* Currently not used
4602 @end ignore
4603 @item @b{resume-start}
4604 @* Before any target is resumed
4605 @item @b{resume-end}
4606 @* After all targets have resumed
4607 @item @b{resumed}
4608 @* Target has resumed
4609 @end itemize
4611 @node Flash Commands
4612 @chapter Flash Commands
4614 OpenOCD has different commands for NOR and NAND flash;
4615 the ``flash'' command works with NOR flash, while
4616 the ``nand'' command works with NAND flash.
4617 This partially reflects different hardware technologies:
4618 NOR flash usually supports direct CPU instruction and data bus access,
4619 while data from a NAND flash must be copied to memory before it can be
4620 used. (SPI flash must also be copied to memory before use.)
4621 However, the documentation also uses ``flash'' as a generic term;
4622 for example, ``Put flash configuration in board-specific files''.
4624 Flash Steps:
4625 @enumerate
4626 @item Configure via the command @command{flash bank}
4627 @* Do this in a board-specific configuration file,
4628 passing parameters as needed by the driver.
4629 @item Operate on the flash via @command{flash subcommand}
4630 @* Often commands to manipulate the flash are typed by a human, or run
4631 via a script in some automated way. Common tasks include writing a
4632 boot loader, operating system, or other data.
4633 @item GDB Flashing
4634 @* Flashing via GDB requires the flash be configured via ``flash
4635 bank'', and the GDB flash features be enabled.
4636 @xref{gdbconfiguration,,GDB Configuration}.
4637 @end enumerate
4639 Many CPUs have the ablity to ``boot'' from the first flash bank.
4640 This means that misprogramming that bank can ``brick'' a system,
4641 so that it can't boot.
4642 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4643 board by (re)installing working boot firmware.
4645 @anchor{norconfiguration}
4646 @section Flash Configuration Commands
4647 @cindex flash configuration
4649 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4650 Configures a flash bank which provides persistent storage
4651 for addresses from @math{base} to @math{base + size - 1}.
4652 These banks will often be visible to GDB through the target's memory map.
4653 In some cases, configuring a flash bank will activate extra commands;
4654 see the driver-specific documentation.
4656 @itemize @bullet
4657 @item @var{name} ... may be used to reference the flash bank
4658 in other flash commands. A number is also available.
4659 @item @var{driver} ... identifies the controller driver
4660 associated with the flash bank being declared.
4661 This is usually @code{cfi} for external flash, or else
4662 the name of a microcontroller with embedded flash memory.
4663 @xref{flashdriverlist,,Flash Driver List}.
4664 @item @var{base} ... Base address of the flash chip.
4665 @item @var{size} ... Size of the chip, in bytes.
4666 For some drivers, this value is detected from the hardware.
4667 @item @var{chip_width} ... Width of the flash chip, in bytes;
4668 ignored for most microcontroller drivers.
4669 @item @var{bus_width} ... Width of the data bus used to access the
4670 chip, in bytes; ignored for most microcontroller drivers.
4671 @item @var{target} ... Names the target used to issue
4672 commands to the flash controller.
4673 @comment Actually, it's currently a controller-specific parameter...
4674 @item @var{driver_options} ... drivers may support, or require,
4675 additional parameters. See the driver-specific documentation
4676 for more information.
4677 @end itemize
4678 @quotation Note
4679 This command is not available after OpenOCD initialization has completed.
4680 Use it in board specific configuration files, not interactively.
4681 @end quotation
4682 @end deffn
4684 @comment the REAL name for this command is "ocd_flash_banks"
4685 @comment less confusing would be: "flash list" (like "nand list")
4686 @deffn Command {flash banks}
4687 Prints a one-line summary of each device that was
4688 declared using @command{flash bank}, numbered from zero.
4689 Note that this is the @emph{plural} form;
4690 the @emph{singular} form is a very different command.
4691 @end deffn
4693 @deffn Command {flash list}
4694 Retrieves a list of associative arrays for each device that was
4695 declared using @command{flash bank}, numbered from zero.
4696 This returned list can be manipulated easily from within scripts.
4697 @end deffn
4699 @deffn Command {flash probe} num
4700 Identify the flash, or validate the parameters of the configured flash. Operation
4701 depends on the flash type.
4702 The @var{num} parameter is a value shown by @command{flash banks}.
4703 Most flash commands will implicitly @emph{autoprobe} the bank;
4704 flash drivers can distinguish between probing and autoprobing,
4705 but most don't bother.
4706 @end deffn
4708 @section Erasing, Reading, Writing to Flash
4709 @cindex flash erasing
4710 @cindex flash reading
4711 @cindex flash writing
4712 @cindex flash programming
4713 @anchor{flashprogrammingcommands}
4715 One feature distinguishing NOR flash from NAND or serial flash technologies
4716 is that for read access, it acts exactly like any other addressible memory.
4717 This means you can use normal memory read commands like @command{mdw} or
4718 @command{dump_image} with it, with no special @command{flash} subcommands.
4719 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
4721 Write access works differently. Flash memory normally needs to be erased
4722 before it's written. Erasing a sector turns all of its bits to ones, and
4723 writing can turn ones into zeroes. This is why there are special commands
4724 for interactive erasing and writing, and why GDB needs to know which parts
4725 of the address space hold NOR flash memory.
4727 @quotation Note
4728 Most of these erase and write commands leverage the fact that NOR flash
4729 chips consume target address space. They implicitly refer to the current
4730 JTAG target, and map from an address in that target's address space
4731 back to a flash bank.
4732 @comment In May 2009, those mappings may fail if any bank associated
4733 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
4734 A few commands use abstract addressing based on bank and sector numbers,
4735 and don't depend on searching the current target and its address space.
4736 Avoid confusing the two command models.
4737 @end quotation
4739 Some flash chips implement software protection against accidental writes,
4740 since such buggy writes could in some cases ``brick'' a system.
4741 For such systems, erasing and writing may require sector protection to be
4742 disabled first.
4743 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4744 and AT91SAM7 on-chip flash.
4745 @xref{flashprotect,,flash protect}.
4747 @deffn Command {flash erase_sector} num first last
4748 Erase sectors in bank @var{num}, starting at sector @var{first}
4749 up to and including @var{last}.
4750 Sector numbering starts at 0.
4751 Providing a @var{last} sector of @option{last}
4752 specifies "to the end of the flash bank".
4753 The @var{num} parameter is a value shown by @command{flash banks}.
4754 @end deffn
4756 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4757 Erase sectors starting at @var{address} for @var{length} bytes.
4758 Unless @option{pad} is specified, @math{address} must begin a
4759 flash sector, and @math{address + length - 1} must end a sector.
4760 Specifying @option{pad} erases extra data at the beginning and/or
4761 end of the specified region, as needed to erase only full sectors.
4762 The flash bank to use is inferred from the @var{address}, and
4763 the specified length must stay within that bank.
4764 As a special case, when @var{length} is zero and @var{address} is
4765 the start of the bank, the whole flash is erased.
4766 If @option{unlock} is specified, then the flash is unprotected
4767 before erase starts.
4768 @end deffn
4770 @deffn Command {flash fillw} address word length
4771 @deffnx Command {flash fillh} address halfword length
4772 @deffnx Command {flash fillb} address byte length
4773 Fills flash memory with the specified @var{word} (32 bits),
4774 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4775 starting at @var{address} and continuing
4776 for @var{length} units (word/halfword/byte).
4777 No erasure is done before writing; when needed, that must be done
4778 before issuing this command.
4779 Writes are done in blocks of up to 1024 bytes, and each write is
4780 verified by reading back the data and comparing it to what was written.
4781 The flash bank to use is inferred from the @var{address} of
4782 each block, and the specified length must stay within that bank.
4783 @end deffn
4784 @comment no current checks for errors if fill blocks touch multiple banks!
4786 @deffn Command {flash write_bank} num filename offset
4787 Write the binary @file{filename} to flash bank @var{num},
4788 starting at @var{offset} bytes from the beginning of the bank.
4789 The @var{num} parameter is a value shown by @command{flash banks}.
4790 @end deffn
4792 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4793 Write the image @file{filename} to the current target's flash bank(s).
4794 A relocation @var{offset} may be specified, in which case it is added
4795 to the base address for each section in the image.
4796 The file [@var{type}] can be specified
4797 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4798 @option{elf} (ELF file), @option{s19} (Motorola s19).
4799 @option{mem}, or @option{builder}.
4800 The relevant flash sectors will be erased prior to programming
4801 if the @option{erase} parameter is given. If @option{unlock} is
4802 provided, then the flash banks are unlocked before erase and
4803 program. The flash bank to use is inferred from the address of
4804 each image section.
4806 @quotation Warning
4807 Be careful using the @option{erase} flag when the flash is holding
4808 data you want to preserve.
4809 Portions of the flash outside those described in the image's
4810 sections might be erased with no notice.
4811 @itemize
4812 @item
4813 When a section of the image being written does not fill out all the
4814 sectors it uses, the unwritten parts of those sectors are necessarily
4815 also erased, because sectors can't be partially erased.
4816 @item
4817 Data stored in sector "holes" between image sections are also affected.
4818 For example, "@command{flash write_image erase ...}" of an image with
4819 one byte at the beginning of a flash bank and one byte at the end
4820 erases the entire bank -- not just the two sectors being written.
4821 @end itemize
4822 Also, when flash protection is important, you must re-apply it after
4823 it has been removed by the @option{unlock} flag.
4824 @end quotation
4826 @end deffn
4828 @section Other Flash commands
4829 @cindex flash protection
4831 @deffn Command {flash erase_check} num
4832 Check erase state of sectors in flash bank @var{num},
4833 and display that status.
4834 The @var{num} parameter is a value shown by @command{flash banks}.
4835 @end deffn
4837 @deffn Command {flash info} num
4838 Print info about flash bank @var{num}
4839 The @var{num} parameter is a value shown by @command{flash banks}.
4840 This command will first query the hardware, it does not print cached
4841 and possibly stale information.
4842 @end deffn
4844 @anchor{flashprotect}
4845 @deffn Command {flash protect} num first last (@option{on}|@option{off})
4846 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
4847 in flash bank @var{num}, starting at sector @var{first}
4848 and continuing up to and including @var{last}.
4849 Providing a @var{last} sector of @option{last}
4850 specifies "to the end of the flash bank".
4851 The @var{num} parameter is a value shown by @command{flash banks}.
4852 @end deffn
4854 @anchor{program}
4855 @deffn Command {program} filename [verify] [reset] [offset]
4856 This is a helper script that simplifies using OpenOCD as a standalone
4857 programmer. The only required parameter is @option{filename}, the others are optional.
4858 @xref{Flash Programming}.
4859 @end deffn
4861 @anchor{flashdriverlist}
4862 @section Flash Driver List
4863 As noted above, the @command{flash bank} command requires a driver name,
4864 and allows driver-specific options and behaviors.
4865 Some drivers also activate driver-specific commands.
4867 @subsection External Flash
4869 @deffn {Flash Driver} cfi
4870 @cindex Common Flash Interface
4871 @cindex CFI
4872 The ``Common Flash Interface'' (CFI) is the main standard for
4873 external NOR flash chips, each of which connects to a
4874 specific external chip select on the CPU.
4875 Frequently the first such chip is used to boot the system.
4876 Your board's @code{reset-init} handler might need to
4877 configure additional chip selects using other commands (like: @command{mww} to
4878 configure a bus and its timings), or
4879 perhaps configure a GPIO pin that controls the ``write protect'' pin
4880 on the flash chip.
4881 The CFI driver can use a target-specific working area to significantly
4882 speed up operation.
4884 The CFI driver can accept the following optional parameters, in any order:
4886 @itemize
4887 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
4888 like AM29LV010 and similar types.
4889 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
4890 @end itemize
4892 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
4893 wide on a sixteen bit bus:
4895 @example
4896 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
4897 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
4898 @end example
4900 To configure one bank of 32 MBytes
4901 built from two sixteen bit (two byte) wide parts wired in parallel
4902 to create a thirty-two bit (four byte) bus with doubled throughput:
4904 @example
4905 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
4906 @end example
4908 @c "cfi part_id" disabled
4909 @end deffn
4911 @deffn {Flash Driver} lpcspifi
4912 @cindex NXP SPI Flash Interface
4913 @cindex SPIFI
4914 @cindex lpcspifi
4915 NXP's LPC43xx and LPC18xx families include a proprietary SPI
4916 Flash Interface (SPIFI) peripheral that can drive and provide
4917 memory mapped access to external SPI flash devices.
4919 The lpcspifi driver initializes this interface and provides
4920 program and erase functionality for these serial flash devices.
4921 Use of this driver @b{requires} a working area of at least 1kB
4922 to be configured on the target device; more than this will
4923 significantly reduce flash programming times.
4925 The setup command only requires the @var{base} parameter. All
4926 other parameters are ignored, and the flash size and layout
4927 are configured by the driver.
4929 @example
4930 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
4931 @end example
4933 @end deffn
4935 @deffn {Flash Driver} stmsmi
4936 @cindex STMicroelectronics Serial Memory Interface
4937 @cindex SMI
4938 @cindex stmsmi
4939 Some devices form STMicroelectronics (e.g. STR75x MCU family,
4940 SPEAr MPU family) include a proprietary
4941 ``Serial Memory Interface'' (SMI) controller able to drive external
4942 SPI flash devices.
4943 Depending on specific device and board configuration, up to 4 external
4944 flash devices can be connected.
4946 SMI makes the flash content directly accessible in the CPU address
4947 space; each external device is mapped in a memory bank.
4948 CPU can directly read data, execute code and boot from SMI banks.
4949 Normal OpenOCD commands like @command{mdw} can be used to display
4950 the flash content.
4952 The setup command only requires the @var{base} parameter in order
4953 to identify the memory bank.
4954 All other parameters are ignored. Additional information, like
4955 flash size, are detected automatically.
4957 @example
4958 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
4959 @end example
4961 @end deffn
4963 @subsection Internal Flash (Microcontrollers)
4965 @deffn {Flash Driver} aduc702x
4966 The ADUC702x analog microcontrollers from Analog Devices
4967 include internal flash and use ARM7TDMI cores.
4968 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
4969 The setup command only requires the @var{target} argument
4970 since all devices in this family have the same memory layout.
4972 @example
4973 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
4974 @end example
4975 @end deffn
4977 @anchor{at91sam3}
4978 @deffn {Flash Driver} at91sam3
4979 @cindex at91sam3
4980 All members of the AT91SAM3 microcontroller family from
4981 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
4982 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
4983 that the driver was orginaly developed and tested using the
4984 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
4985 the family was cribbed from the data sheet. @emph{Note to future
4986 readers/updaters: Please remove this worrysome comment after other
4987 chips are confirmed.}
4989 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
4990 have one flash bank. In all cases the flash banks are at
4991 the following fixed locations:
4993 @example
4994 # Flash bank 0 - all chips
4995 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
4996 # Flash bank 1 - only 256K chips
4997 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
4998 @end example
5000 Internally, the AT91SAM3 flash memory is organized as follows.
5001 Unlike the AT91SAM7 chips, these are not used as parameters
5002 to the @command{flash bank} command:
5004 @itemize
5005 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
5006 @item @emph{Bank Size:} 128K/64K Per flash bank
5007 @item @emph{Sectors:} 16 or 8 per bank
5008 @item @emph{SectorSize:} 8K Per Sector
5009 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
5010 @end itemize
5012 The AT91SAM3 driver adds some additional commands:
5014 @deffn Command {at91sam3 gpnvm}
5015 @deffnx Command {at91sam3 gpnvm clear} number
5016 @deffnx Command {at91sam3 gpnvm set} number
5017 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
5018 With no parameters, @command{show} or @command{show all},
5019 shows the status of all GPNVM bits.
5020 With @command{show} @var{number}, displays that bit.
5022 With @command{set} @var{number} or @command{clear} @var{number},
5023 modifies that GPNVM bit.
5024 @end deffn
5026 @deffn Command {at91sam3 info}
5027 This command attempts to display information about the AT91SAM3
5028 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
5029 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
5030 document id: doc6430A] and decodes the values. @emph{Second} it reads the
5031 various clock configuration registers and attempts to display how it
5032 believes the chip is configured. By default, the SLOWCLK is assumed to
5033 be 32768 Hz, see the command @command{at91sam3 slowclk}.
5034 @end deffn
5036 @deffn Command {at91sam3 slowclk} [value]
5037 This command shows/sets the slow clock frequency used in the
5038 @command{at91sam3 info} command calculations above.
5039 @end deffn
5040 @end deffn
5042 @deffn {Flash Driver} at91sam4
5043 @cindex at91sam4
5044 All members of the AT91SAM4 microcontroller family from
5045 Atmel include internal flash and use ARM's Cortex-M4 core.
5046 This driver uses the same cmd names/syntax as @xref{at91sam3}.
5047 @end deffn
5049 @deffn {Flash Driver} at91sam7
5050 All members of the AT91SAM7 microcontroller family from Atmel include
5051 internal flash and use ARM7TDMI cores. The driver automatically
5052 recognizes a number of these chips using the chip identification
5053 register, and autoconfigures itself.
5055 @example
5056 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
5057 @end example
5059 For chips which are not recognized by the controller driver, you must
5060 provide additional parameters in the following order:
5062 @itemize
5063 @item @var{chip_model} ... label used with @command{flash info}
5064 @item @var{banks}
5065 @item @var{sectors_per_bank}
5066 @item @var{pages_per_sector}