pipes: add documentation for pipes
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About JIM-Tcl:: About JIM-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * TFTP:: TFTP
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
94 @end menu
96 @node About
97 @unnumbered About
98 @cindex about
100 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
101 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
104 around the world.
106 @section What is OpenOCD?
107 @cindex TAP
108 @cindex JTAG
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
112 devices.
114 It does so with the assistance of a @dfn{debug adapter}, which is
115 a small hardware module which helps provide the right kind of
116 electrical signaling to the target being debugged. These are
117 required since the debug host (on which OpenOCD runs) won't
118 usually have native support for such signaling, or the connector
119 needed to hook up to the target.
121 Such debug adapters support one or more @dfn{transport} protocols,
122 each of which involves different electrical signaling (and uses
123 different messaging protocols on top of that signaling). There
124 are many types of debug adapter, and little uniformity in what
125 they are called. (There are also product naming differences.)
127 These adapters are sometimes packaged as discrete dongles. which
128 may generically be called @dfn{hardware interface dongles}.
129 Some development boards also integrate them directly, which may
130 let the development board can be directly connected to the debug
131 host over USB (and sometimes also to power it over USB).
133 For example, a @dfn{JTAG Adapter} supports JTAG
134 signaling, and is used to communicate
135 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
136 A @dfn{TAP} is a ``Test Access Port'', a module which processes
137 special instructions and data. TAPs are daisy-chained within and
138 between chips and boards. JTAG supports debugging and boundary
139 scan operations.
141 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
142 signaling to communicate with some newer ARM cores, as well as debug
143 adapters which support both JTAG and SWD transports. SWD only supports
144 debugging, whereas JTAG also supports boundary scan operations.
146 For some chips, there are also @dfn{Programming Adapters} supporting
147 special transports used only to write code to flash memory, without
148 support for on-chip debugging or boundary scan.
149 (At this writing, OpenOCD does not support such non-debug adapters.)
152 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
153 based, parallel port based, and other standalone boxes that run
154 OpenOCD internally. @xref{Debug Adapter Hardware}.
156 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
157 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
158 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
159 debugged via the GDB protocol.
161 @b{Flash Programing:} Flash writing is supported for external CFI
162 compatible NOR flashes (Intel and AMD/Spansion command set) and several
163 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
164 STM32x). Preliminary support for various NAND flash controllers
165 (LPC3180, Orion, S3C24xx, more) controller is included.
167 @section OpenOCD Web Site
169 The OpenOCD web site provides the latest public news from the community:
171 @uref{http://openocd.berlios.de/web/}
173 @section Latest User's Guide:
175 The user's guide you are now reading may not be the latest one
176 available. A version for more recent code may be available.
177 Its HTML form is published irregularly at:
179 @uref{http://openocd.berlios.de/doc/html/index.html}
181 PDF form is likewise published at:
183 @uref{http://openocd.berlios.de/doc/pdf/openocd.pdf}
185 @section OpenOCD User's Forum
187 There is an OpenOCD forum (phpBB) hosted by SparkFun,
188 which might be helpful to you. Note that if you want
189 anything to come to the attention of developers, you
190 should post it to the OpenOCD Developer Mailing List
191 instead of this forum.
193 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @node Developers
197 @chapter OpenOCD Developer Resources
198 @cindex developers
200 If you are interested in improving the state of OpenOCD's debugging and
201 testing support, new contributions will be welcome. Motivated developers
202 can produce new target, flash or interface drivers, improve the
203 documentation, as well as more conventional bug fixes and enhancements.
205 The resources in this chapter are available for developers wishing to explore
206 or expand the OpenOCD source code.
208 @section OpenOCD GIT Repository
210 During the 0.3.x release cycle, OpenOCD switched from Subversion to
211 a GIT repository hosted at SourceForge. The repository URL is:
213 @uref{git://openocd.git.sourceforge.net/gitroot/openocd/openocd}
215 You may prefer to use a mirror and the HTTP protocol:
217 @uref{http://repo.or.cz/r/openocd.git}
219 With standard GIT tools, use @command{git clone} to initialize
220 a local repository, and @command{git pull} to update it.
221 There are also gitweb pages letting you browse the repository
222 with a web browser, or download arbitrary snapshots without
223 needing a GIT client:
225 @uref{http://openocd.git.sourceforge.net/git/gitweb.cgi?p=openocd/openocd}
227 @uref{http://repo.or.cz/w/openocd.git}
229 The @file{README} file contains the instructions for building the project
230 from the repository or a snapshot.
232 Developers that want to contribute patches to the OpenOCD system are
233 @b{strongly} encouraged to work against mainline.
234 Patches created against older versions may require additional
235 work from their submitter in order to be updated for newer releases.
237 @section Doxygen Developer Manual
239 During the 0.2.x release cycle, the OpenOCD project began
240 providing a Doxygen reference manual. This document contains more
241 technical information about the software internals, development
242 processes, and similar documentation:
244 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
246 This document is a work-in-progress, but contributions would be welcome
247 to fill in the gaps. All of the source files are provided in-tree,
248 listed in the Doxyfile configuration in the top of the source tree.
250 @section OpenOCD Developer Mailing List
252 The OpenOCD Developer Mailing List provides the primary means of
253 communication between developers:
255 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
257 Discuss and submit patches to this list.
258 The @file{PATCHES.txt} file contains basic information about how
259 to prepare patches.
261 @section OpenOCD Bug Database
263 During the 0.4.x release cycle the OpenOCD project team began
264 using Trac for its bug database:
266 @uref{https://sourceforge.net/apps/trac/openocd}
269 @node Debug Adapter Hardware
270 @chapter Debug Adapter Hardware
271 @cindex dongles
272 @cindex FTDI
273 @cindex wiggler
274 @cindex zy1000
275 @cindex printer port
276 @cindex USB Adapter
277 @cindex RTCK
279 Defined: @b{dongle}: A small device that plugins into a computer and serves as
280 an adapter .... [snip]
282 In the OpenOCD case, this generally refers to @b{a small adapter} that
283 attaches to your computer via USB or the Parallel Printer Port. One
284 exception is the Zylin ZY1000, packaged as a small box you attach via
285 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
286 require any drivers to be installed on the developer PC. It also has
287 a built in web interface. It supports RTCK/RCLK or adaptive clocking
288 and has a built in relay to power cycle targets remotely.
291 @section Choosing a Dongle
293 There are several things you should keep in mind when choosing a dongle.
295 @enumerate
296 @item @b{Transport} Does it support the kind of communication that you need?
297 OpenOCD focusses mostly on JTAG. Your version may also support
298 other ways to communicate with target devices.
299 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
300 Does your dongle support it? You might need a level converter.
301 @item @b{Pinout} What pinout does your target board use?
302 Does your dongle support it? You may be able to use jumper
303 wires, or an "octopus" connector, to convert pinouts.
304 @item @b{Connection} Does your computer have the USB, printer, or
305 Ethernet port needed?
306 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
307 RTCK support? Also known as ``adaptive clocking''
308 @end enumerate
310 @section Stand alone Systems
312 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
313 dongle, but a standalone box. The ZY1000 has the advantage that it does
314 not require any drivers installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built in relay to power cycle targets remotely.
318 @section USB FT2232 Based
320 There are many USB JTAG dongles on the market, many of them are based
321 on a chip from ``Future Technology Devices International'' (FTDI)
322 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
323 See: @url{http://www.ftdichip.com} for more information.
324 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
325 chips are starting to become available in JTAG adapters. (Adapters
326 using those high speed FT2232H chips may support adaptive clocking.)
328 The FT2232 chips are flexible enough to support some other
329 transport options, such as SWD or the SPI variants used to
330 program some chips. They have two communications channels,
331 and one can be used for a UART adapter at the same time the
332 other one is used to provide a debug adapter.
334 Also, some development boards integrate an FT2232 chip to serve as
335 a built-in low cost debug adapter and usb-to-serial solution.
337 @itemize @bullet
338 @item @b{usbjtag}
339 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
340 @item @b{jtagkey}
341 @* See: @url{http://www.amontec.com/jtagkey.shtml}
342 @item @b{jtagkey2}
343 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
344 @item @b{oocdlink}
345 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
346 @item @b{signalyzer}
347 @* See: @url{http://www.signalyzer.com}
348 @item @b{Stellaris Eval Boards}
349 @* See: @url{http://www.luminarymicro.com} - The Stellaris eval boards
350 bundle FT2232-based JTAG and SWD support, which can be used to debug
351 the Stellaris chips. Using separate JTAG adapters is optional.
352 These boards can also be used in a "pass through" mode as JTAG adapters
353 to other target boards, disabling the Stellaris chip.
354 @item @b{Luminary ICDI}
355 @* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug
356 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
357 Evaluation Kits. Like the non-detachable FT2232 support on the other
358 Stellaris eval boards, they can be used to debug other target boards.
359 @item @b{olimex-jtag}
360 @* See: @url{http://www.olimex.com}
361 @item @b{flyswatter}
362 @* See: @url{http://www.tincantools.com}
363 @item @b{turtelizer2}
364 @* See:
365 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
366 @url{http://www.ethernut.de}
367 @item @b{comstick}
368 @* Link: @url{http://www.hitex.com/index.php?id=383}
369 @item @b{stm32stick}
370 @* Link @url{http://www.hitex.com/stm32-stick}
371 @item @b{axm0432_jtag}
372 @* Axiom AXM-0432 Link @url{http://www.axman.com}
373 @item @b{cortino}
374 @* Link @url{http://www.hitex.com/index.php?id=cortino}
375 @end itemize
377 @section USB-JTAG / Altera USB-Blaster compatibles
379 These devices also show up as FTDI devices, but are not
380 protocol-compatible with the FT2232 devices. They are, however,
381 protocol-compatible among themselves. USB-JTAG devices typically consist
382 of a FT245 followed by a CPLD that understands a particular protocol,
383 or emulate this protocol using some other hardware.
385 They may appear under different USB VID/PID depending on the particular
386 product. The driver can be configured to search for any VID/PID pair
387 (see the section on driver commands).
389 @itemize
390 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
391 @* Link: @url{http://www.ixo.de/info/usb_jtag/}
392 @item @b{Altera USB-Blaster}
393 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
394 @end itemize
396 @section USB JLINK based
397 There are several OEM versions of the Segger @b{JLINK} adapter. It is
398 an example of a micro controller based JTAG adapter, it uses an
399 AT91SAM764 internally.
401 @itemize @bullet
402 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
403 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
404 @item @b{SEGGER JLINK}
405 @* Link: @url{http://www.segger.com/jlink.html}
406 @item @b{IAR J-Link}
407 @* Link: @url{http://www.iar.com/website1/}
408 @end itemize
410 @section USB RLINK based
411 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
413 @itemize @bullet
414 @item @b{Raisonance RLink}
415 @* Link: @url{http://www.raisonance.com/products/RLink.php}
416 @item @b{STM32 Primer}
417 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
418 @item @b{STM32 Primer2}
419 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
420 @end itemize
422 @section USB Other
423 @itemize @bullet
424 @item @b{USBprog}
425 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
427 @item @b{USB - Presto}
428 @* Link: @url{http://tools.asix.net/prg_presto.htm}
430 @item @b{Versaloon-Link}
431 @* Link: @url{http://www.simonqian.com/en/Versaloon}
433 @item @b{ARM-JTAG-EW}
434 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
436 @item @b{Buspirate}
437 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
438 @end itemize
440 @section IBM PC Parallel Printer Port Based
442 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
443 and the MacGraigor Wiggler. There are many clones and variations of
444 these on the market.
446 Note that parallel ports are becoming much less common, so if you
447 have the choice you should probably avoid these adapters in favor
448 of USB-based ones.
450 @itemize @bullet
452 @item @b{Wiggler} - There are many clones of this.
453 @* Link: @url{http://www.macraigor.com/wiggler.htm}
455 @item @b{DLC5} - From XILINX - There are many clones of this
456 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
457 produced, PDF schematics are easily found and it is easy to make.
459 @item @b{Amontec - JTAG Accelerator}
460 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
462 @item @b{GW16402}
463 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
465 @item @b{Wiggler2}
466 @*@uref{http://www.ccac.rwth-aachen.de/@/~michaels/@/index.php/hardware/@/armjtag,
467 Improved parallel-port wiggler-style JTAG adapter}
469 @item @b{Wiggler_ntrst_inverted}
470 @* Yet another variation - See the source code, src/jtag/parport.c
472 @item @b{old_amt_wiggler}
473 @* Unknown - probably not on the market today
475 @item @b{arm-jtag}
476 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
478 @item @b{chameleon}
479 @* Link: @url{http://www.amontec.com/chameleon.shtml}
481 @item @b{Triton}
482 @* Unknown.
484 @item @b{Lattice}
485 @* ispDownload from Lattice Semiconductor
486 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
488 @item @b{flashlink}
489 @* From ST Microsystems;
490 @uref{http://www.st.com/stonline/@/products/literature/um/7889.pdf,
491 FlashLINK JTAG programing cable for PSD and uPSD}
493 @end itemize
495 @section Other...
496 @itemize @bullet
498 @item @b{ep93xx}
499 @* An EP93xx based Linux machine using the GPIO pins directly.
501 @item @b{at91rm9200}
502 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
504 @end itemize
506 @node About JIM-Tcl
507 @chapter About JIM-Tcl
508 @cindex JIM Tcl
509 @cindex tcl
511 OpenOCD includes a small ``Tcl Interpreter'' known as JIM-Tcl.
512 This programming language provides a simple and extensible
513 command interpreter.
515 All commands presented in this Guide are extensions to JIM-Tcl.
516 You can use them as simple commands, without needing to learn
517 much of anything about Tcl.
518 Alternatively, can write Tcl programs with them.
520 You can learn more about JIM at its website, @url{http://jim.berlios.de}.
522 @itemize @bullet
523 @item @b{JIM vs. Tcl}
524 @* JIM-TCL is a stripped down version of the well known Tcl language,
525 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
526 fewer features. JIM-Tcl is a single .C file and a single .H file and
527 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
528 4.2 MB .zip file containing 1540 files.
530 @item @b{Missing Features}
531 @* Our practice has been: Add/clone the real Tcl feature if/when
532 needed. We welcome JIM Tcl improvements, not bloat.
534 @item @b{Scripts}
535 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
536 command interpreter today is a mixture of (newer)
537 JIM-Tcl commands, and (older) the orginal command interpreter.
539 @item @b{Commands}
540 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
541 can type a Tcl for() loop, set variables, etc.
542 Some of the commands documented in this guide are implemented
543 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
545 @item @b{Historical Note}
546 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
548 @item @b{Need a crash course in Tcl?}
549 @*@xref{Tcl Crash Course}.
550 @end itemize
552 @node Running
553 @chapter Running
554 @cindex command line options
555 @cindex logfile
556 @cindex directory search
558 Properly installing OpenOCD sets up your operating system to grant it access
559 to the debug adapters. On Linux, this usually involves installing a file
560 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
561 complex and confusing driver configuration for every peripheral. Such issues
562 are unique to each operating system, and are not detailed in this User's Guide.
564 Then later you will invoke the OpenOCD server, with various options to
565 tell it how each debug session should work.
566 The @option{--help} option shows:
567 @verbatim
568 bash$ openocd --help
570 --help | -h display this help
571 --version | -v display OpenOCD version
572 --file | -f use configuration file <name>
573 --search | -s dir to search for config files and scripts
574 --debug | -d set debug level <0-3>
575 --log_output | -l redirect log output to file <name>
576 --command | -c run <command>
577 @end verbatim
579 If you don't give any @option{-f} or @option{-c} options,
580 OpenOCD tries to read the configuration file @file{openocd.cfg}.
581 To specify one or more different
582 configuration files, use @option{-f} options. For example:
584 @example
585 openocd -f config1.cfg -f config2.cfg -f config3.cfg
586 @end example
588 Configuration files and scripts are searched for in
589 @enumerate
590 @item the current directory,
591 @item any search dir specified on the command line using the @option{-s} option,
592 @item any search dir specified using the @command{add_script_search_dir} command,
593 @item @file{$HOME/.openocd} (not on Windows),
594 @item the site wide script library @file{$pkgdatadir/site} and
595 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
596 @end enumerate
597 The first found file with a matching file name will be used.
599 @quotation Note
600 Don't try to use configuration script names or paths which
601 include the "#" character. That character begins Tcl comments.
602 @end quotation
604 @section Simple setup, no customization
606 In the best case, you can use two scripts from one of the script
607 libraries, hook up your JTAG adapter, and start the server ... and
608 your JTAG setup will just work "out of the box". Always try to
609 start by reusing those scripts, but assume you'll need more
610 customization even if this works. @xref{OpenOCD Project Setup}.
612 If you find a script for your JTAG adapter, and for your board or
613 target, you may be able to hook up your JTAG adapter then start
614 the server like:
616 @example
617 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
618 @end example
620 You might also need to configure which reset signals are present,
621 using @option{-c 'reset_config trst_and_srst'} or something similar.
622 If all goes well you'll see output something like
624 @example
625 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
626 For bug reports, read
627 http://openocd.berlios.de/doc/doxygen/bugs.html
628 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
629 (mfg: 0x23b, part: 0xba00, ver: 0x3)
630 @end example
632 Seeing that "tap/device found" message, and no warnings, means
633 the JTAG communication is working. That's a key milestone, but
634 you'll probably need more project-specific setup.
636 @section What OpenOCD does as it starts
638 OpenOCD starts by processing the configuration commands provided
639 on the command line or, if there were no @option{-c command} or
640 @option{-f file.cfg} options given, in @file{openocd.cfg}.
641 @xref{Configuration Stage}.
642 At the end of the configuration stage it verifies the JTAG scan
643 chain defined using those commands; your configuration should
644 ensure that this always succeeds.
645 Normally, OpenOCD then starts running as a daemon.
646 Alternatively, commands may be used to terminate the configuration
647 stage early, perform work (such as updating some flash memory),
648 and then shut down without acting as a daemon.
650 Once OpenOCD starts running as a daemon, it waits for connections from
651 clients (Telnet, GDB, Other) and processes the commands issued through
652 those channels.
654 If you are having problems, you can enable internal debug messages via
655 the @option{-d} option.
657 Also it is possible to interleave JIM-Tcl commands w/config scripts using the
658 @option{-c} command line switch.
660 To enable debug output (when reporting problems or working on OpenOCD
661 itself), use the @option{-d} command line switch. This sets the
662 @option{debug_level} to "3", outputting the most information,
663 including debug messages. The default setting is "2", outputting only
664 informational messages, warnings and errors. You can also change this
665 setting from within a telnet or gdb session using @command{debug_level
666 <n>} (@pxref{debug_level}).
668 You can redirect all output from the daemon to a file using the
669 @option{-l <logfile>} switch.
671 For details on the @option{-p} option. @xref{Connecting to GDB}.
673 Note! OpenOCD will launch the GDB & telnet server even if it can not
674 establish a connection with the target. In general, it is possible for
675 the JTAG controller to be unresponsive until the target is set up
676 correctly via e.g. GDB monitor commands in a GDB init script.
678 @node OpenOCD Project Setup
679 @chapter OpenOCD Project Setup
681 To use OpenOCD with your development projects, you need to do more than
682 just connecting the JTAG adapter hardware (dongle) to your development board
683 and then starting the OpenOCD server.
684 You also need to configure that server so that it knows
685 about that adapter and board, and helps your work.
686 You may also want to connect OpenOCD to GDB, possibly
687 using Eclipse or some other GUI.
689 @section Hooking up the JTAG Adapter
691 Today's most common case is a dongle with a JTAG cable on one side
692 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
693 and a USB cable on the other.
694 Instead of USB, some cables use Ethernet;
695 older ones may use a PC parallel port, or even a serial port.
697 @enumerate
698 @item @emph{Start with power to your target board turned off},
699 and nothing connected to your JTAG adapter.
700 If you're particularly paranoid, unplug power to the board.
701 It's important to have the ground signal properly set up,
702 unless you are using a JTAG adapter which provides
703 galvanic isolation between the target board and the
704 debugging host.
706 @item @emph{Be sure it's the right kind of JTAG connector.}
707 If your dongle has a 20-pin ARM connector, you need some kind
708 of adapter (or octopus, see below) to hook it up to
709 boards using 14-pin or 10-pin connectors ... or to 20-pin
710 connectors which don't use ARM's pinout.
712 In the same vein, make sure the voltage levels are compatible.
713 Not all JTAG adapters have the level shifters needed to work
714 with 1.2 Volt boards.
716 @item @emph{Be certain the cable is properly oriented} or you might
717 damage your board. In most cases there are only two possible
718 ways to connect the cable.
719 Connect the JTAG cable from your adapter to the board.
720 Be sure it's firmly connected.
722 In the best case, the connector is keyed to physically
723 prevent you from inserting it wrong.
724 This is most often done using a slot on the board's male connector
725 housing, which must match a key on the JTAG cable's female connector.
726 If there's no housing, then you must look carefully and
727 make sure pin 1 on the cable hooks up to pin 1 on the board.
728 Ribbon cables are frequently all grey except for a wire on one
729 edge, which is red. The red wire is pin 1.
731 Sometimes dongles provide cables where one end is an ``octopus'' of
732 color coded single-wire connectors, instead of a connector block.
733 These are great when converting from one JTAG pinout to another,
734 but are tedious to set up.
735 Use these with connector pinout diagrams to help you match up the
736 adapter signals to the right board pins.
738 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
739 A USB, parallel, or serial port connector will go to the host which
740 you are using to run OpenOCD.
741 For Ethernet, consult the documentation and your network administrator.
743 For USB based JTAG adapters you have an easy sanity check at this point:
744 does the host operating system see the JTAG adapter? If that host is an
745 MS-Windows host, you'll need to install a driver before OpenOCD works.
747 @item @emph{Connect the adapter's power supply, if needed.}
748 This step is primarily for non-USB adapters,
749 but sometimes USB adapters need extra power.
751 @item @emph{Power up the target board.}
752 Unless you just let the magic smoke escape,
753 you're now ready to set up the OpenOCD server
754 so you can use JTAG to work with that board.
756 @end enumerate
758 Talk with the OpenOCD server using
759 telnet (@code{telnet localhost 4444} on many systems) or GDB.
760 @xref{GDB and OpenOCD}.
762 @section Project Directory
764 There are many ways you can configure OpenOCD and start it up.
766 A simple way to organize them all involves keeping a
767 single directory for your work with a given board.
768 When you start OpenOCD from that directory,
769 it searches there first for configuration files, scripts,
770 files accessed through semihosting,
771 and for code you upload to the target board.
772 It is also the natural place to write files,
773 such as log files and data you download from the board.
775 @section Configuration Basics
777 There are two basic ways of configuring OpenOCD, and
778 a variety of ways you can mix them.
779 Think of the difference as just being how you start the server:
781 @itemize
782 @item Many @option{-f file} or @option{-c command} options on the command line
783 @item No options, but a @dfn{user config file}
784 in the current directory named @file{openocd.cfg}
785 @end itemize
787 Here is an example @file{openocd.cfg} file for a setup
788 using a Signalyzer FT2232-based JTAG adapter to talk to
789 a board with an Atmel AT91SAM7X256 microcontroller:
791 @example
792 source [find interface/signalyzer.cfg]
794 # GDB can also flash my flash!
795 gdb_memory_map enable
796 gdb_flash_program enable
798 source [find target/sam7x256.cfg]
799 @end example
801 Here is the command line equivalent of that configuration:
803 @example
804 openocd -f interface/signalyzer.cfg \
805 -c "gdb_memory_map enable" \
806 -c "gdb_flash_program enable" \
807 -f target/sam7x256.cfg
808 @end example
810 You could wrap such long command lines in shell scripts,
811 each supporting a different development task.
812 One might re-flash the board with a specific firmware version.
813 Another might set up a particular debugging or run-time environment.
815 @quotation Important
816 At this writing (October 2009) the command line method has
817 problems with how it treats variables.
818 For example, after @option{-c "set VAR value"}, or doing the
819 same in a script, the variable @var{VAR} will have no value
820 that can be tested in a later script.
821 @end quotation
823 Here we will focus on the simpler solution: one user config
824 file, including basic configuration plus any TCL procedures
825 to simplify your work.
827 @section User Config Files
828 @cindex config file, user
829 @cindex user config file
830 @cindex config file, overview
832 A user configuration file ties together all the parts of a project
833 in one place.
834 One of the following will match your situation best:
836 @itemize
837 @item Ideally almost everything comes from configuration files
838 provided by someone else.
839 For example, OpenOCD distributes a @file{scripts} directory
840 (probably in @file{/usr/share/openocd/scripts} on Linux).
841 Board and tool vendors can provide these too, as can individual
842 user sites; the @option{-s} command line option lets you say
843 where to find these files. (@xref{Running}.)
844 The AT91SAM7X256 example above works this way.
846 Three main types of non-user configuration file each have their
847 own subdirectory in the @file{scripts} directory:
849 @enumerate
850 @item @b{interface} -- one for each different debug adapter;
851 @item @b{board} -- one for each different board
852 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
853 @end enumerate
855 Best case: include just two files, and they handle everything else.
856 The first is an interface config file.
857 The second is board-specific, and it sets up the JTAG TAPs and
858 their GDB targets (by deferring to some @file{target.cfg} file),
859 declares all flash memory, and leaves you nothing to do except
860 meet your deadline:
862 @example
863 source [find interface/olimex-jtag-tiny.cfg]
864 source [find board/csb337.cfg]
865 @end example
867 Boards with a single microcontroller often won't need more
868 than the target config file, as in the AT91SAM7X256 example.
869 That's because there is no external memory (flash, DDR RAM), and
870 the board differences are encapsulated by application code.
872 @item Maybe you don't know yet what your board looks like to JTAG.
873 Once you know the @file{interface.cfg} file to use, you may
874 need help from OpenOCD to discover what's on the board.
875 Once you find the JTAG TAPs, you can just search for appropriate
876 target and board
877 configuration files ... or write your own, from the bottom up.
878 @xref{Autoprobing}.
880 @item You can often reuse some standard config files but
881 need to write a few new ones, probably a @file{board.cfg} file.
882 You will be using commands described later in this User's Guide,
883 and working with the guidelines in the next chapter.
885 For example, there may be configuration files for your JTAG adapter
886 and target chip, but you need a new board-specific config file
887 giving access to your particular flash chips.
888 Or you might need to write another target chip configuration file
889 for a new chip built around the Cortex M3 core.
891 @quotation Note
892 When you write new configuration files, please submit
893 them for inclusion in the next OpenOCD release.
894 For example, a @file{board/newboard.cfg} file will help the
895 next users of that board, and a @file{target/newcpu.cfg}
896 will help support users of any board using that chip.
897 @end quotation
899 @item
900 You may may need to write some C code.
901 It may be as simple as a supporting a new ft2232 or parport
902 based adapter; a bit more involved, like a NAND or NOR flash
903 controller driver; or a big piece of work like supporting
904 a new chip architecture.
905 @end itemize
907 Reuse the existing config files when you can.
908 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
909 You may find a board configuration that's a good example to follow.
911 When you write config files, separate the reusable parts
912 (things every user of that interface, chip, or board needs)
913 from ones specific to your environment and debugging approach.
914 @itemize
916 @item
917 For example, a @code{gdb-attach} event handler that invokes
918 the @command{reset init} command will interfere with debugging
919 early boot code, which performs some of the same actions
920 that the @code{reset-init} event handler does.
922 @item
923 Likewise, the @command{arm9 vector_catch} command (or
924 @cindex vector_catch
925 its siblings @command{xscale vector_catch}
926 and @command{cortex_m3 vector_catch}) can be a timesaver
927 during some debug sessions, but don't make everyone use that either.
928 Keep those kinds of debugging aids in your user config file,
929 along with messaging and tracing setup.
930 (@xref{Software Debug Messages and Tracing}.)
932 @item
933 You might need to override some defaults.
934 For example, you might need to move, shrink, or back up the target's
935 work area if your application needs much SRAM.
937 @item
938 TCP/IP port configuration is another example of something which
939 is environment-specific, and should only appear in
940 a user config file. @xref{TCP/IP Ports}.
941 @end itemize
943 @section Project-Specific Utilities
945 A few project-specific utility
946 routines may well speed up your work.
947 Write them, and keep them in your project's user config file.
949 For example, if you are making a boot loader work on a
950 board, it's nice to be able to debug the ``after it's
951 loaded to RAM'' parts separately from the finicky early
952 code which sets up the DDR RAM controller and clocks.
953 A script like this one, or a more GDB-aware sibling,
954 may help:
956 @example
957 proc ramboot @{ @} @{
958 # Reset, running the target's "reset-init" scripts
959 # to initialize clocks and the DDR RAM controller.
960 # Leave the CPU halted.
961 reset init
963 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
964 load_image u-boot.bin 0x20000000
966 # Start running.
967 resume 0x20000000
968 @}
969 @end example
971 Then once that code is working you will need to make it
972 boot from NOR flash; a different utility would help.
973 Alternatively, some developers write to flash using GDB.
974 (You might use a similar script if you're working with a flash
975 based microcontroller application instead of a boot loader.)
977 @example
978 proc newboot @{ @} @{
979 # Reset, leaving the CPU halted. The "reset-init" event
980 # proc gives faster access to the CPU and to NOR flash;
981 # "reset halt" would be slower.
982 reset init
984 # Write standard version of U-Boot into the first two
985 # sectors of NOR flash ... the standard version should
986 # do the same lowlevel init as "reset-init".
987 flash protect 0 0 1 off
988 flash erase_sector 0 0 1
989 flash write_bank 0 u-boot.bin 0x0
990 flash protect 0 0 1 on
992 # Reboot from scratch using that new boot loader.
993 reset run
994 @}
995 @end example
997 You may need more complicated utility procedures when booting
998 from NAND.
999 That often involves an extra bootloader stage,
1000 running from on-chip SRAM to perform DDR RAM setup so it can load
1001 the main bootloader code (which won't fit into that SRAM).
1003 Other helper scripts might be used to write production system images,
1004 involving considerably more than just a three stage bootloader.
1006 @section Target Software Changes
1008 Sometimes you may want to make some small changes to the software
1009 you're developing, to help make JTAG debugging work better.
1010 For example, in C or assembly language code you might
1011 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1012 handling issues like:
1014 @itemize @bullet
1016 @item @b{Watchdog Timers}...
1017 Watchog timers are typically used to automatically reset systems if
1018 some application task doesn't periodically reset the timer. (The
1019 assumption is that the system has locked up if the task can't run.)
1020 When a JTAG debugger halts the system, that task won't be able to run
1021 and reset the timer ... potentially causing resets in the middle of
1022 your debug sessions.
1024 It's rarely a good idea to disable such watchdogs, since their usage
1025 needs to be debugged just like all other parts of your firmware.
1026 That might however be your only option.
1028 Look instead for chip-specific ways to stop the watchdog from counting
1029 while the system is in a debug halt state. It may be simplest to set
1030 that non-counting mode in your debugger startup scripts. You may however
1031 need a different approach when, for example, a motor could be physically
1032 damaged by firmware remaining inactive in a debug halt state. That might
1033 involve a type of firmware mode where that "non-counting" mode is disabled
1034 at the beginning then re-enabled at the end; a watchdog reset might fire
1035 and complicate the debug session, but hardware (or people) would be
1036 protected.@footnote{Note that many systems support a "monitor mode" debug
1037 that is a somewhat cleaner way to address such issues. You can think of
1038 it as only halting part of the system, maybe just one task,
1039 instead of the whole thing.
1040 At this writing, January 2010, OpenOCD based debugging does not support
1041 monitor mode debug, only "halt mode" debug.}
1043 @item @b{ARM Semihosting}...
1044 @cindex ARM semihosting
1045 When linked with a special runtime library provided with many
1046 toolchains@footnote{See chapter 8 "Semihosting" in
1047 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1048 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1049 The CodeSourcery EABI toolchain also includes a semihosting library.},
1050 your target code can use I/O facilities on the debug host. That library
1051 provides a small set of system calls which are handled by OpenOCD.
1052 It can let the debugger provide your system console and a file system,
1053 helping with early debugging or providing a more capable environment
1054 for sometimes-complex tasks like installing system firmware onto
1055 NAND or SPI flash.
1057 @item @b{ARM Wait-For-Interrupt}...
1058 Many ARM chips synchronize the JTAG clock using the core clock.
1059 Low power states which stop that core clock thus prevent JTAG access.
1060 Idle loops in tasking environments often enter those low power states
1061 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1063 You may want to @emph{disable that instruction} in source code,
1064 or otherwise prevent using that state,
1065 to ensure you can get JTAG access at any time.@footnote{As a more
1066 polite alternative, some processors have special debug-oriented
1067 registers which can be used to change various features including
1068 how the low power states are clocked while debugging.
1069 The STM32 DBGMCU_CR register is an example; at the cost of extra
1070 power consumption, JTAG can be used during low power states.}
1071 For example, the OpenOCD @command{halt} command may not
1072 work for an idle processor otherwise.
1074 @item @b{Delay after reset}...
1075 Not all chips have good support for debugger access
1076 right after reset; many LPC2xxx chips have issues here.
1077 Similarly, applications that reconfigure pins used for
1078 JTAG access as they start will also block debugger access.
1080 To work with boards like this, @emph{enable a short delay loop}
1081 the first thing after reset, before "real" startup activities.
1082 For example, one second's delay is usually more than enough
1083 time for a JTAG debugger to attach, so that
1084 early code execution can be debugged
1085 or firmware can be replaced.
1087 @item @b{Debug Communications Channel (DCC)}...
1088 Some processors include mechanisms to send messages over JTAG.
1089 Many ARM cores support these, as do some cores from other vendors.
1090 (OpenOCD may be able to use this DCC internally, speeding up some
1091 operations like writing to memory.)
1093 Your application may want to deliver various debugging messages
1094 over JTAG, by @emph{linking with a small library of code}
1095 provided with OpenOCD and using the utilities there to send
1096 various kinds of message.
1097 @xref{Software Debug Messages and Tracing}.
1099 @end itemize
1101 @section Target Hardware Setup
1103 Chip vendors often provide software development boards which
1104 are highly configurable, so that they can support all options
1105 that product boards may require. @emph{Make sure that any
1106 jumpers or switches match the system configuration you are
1107 working with.}
1109 Common issues include:
1111 @itemize @bullet
1113 @item @b{JTAG setup} ...
1114 Boards may support more than one JTAG configuration.
1115 Examples include jumpers controlling pullups versus pulldowns
1116 on the nTRST and/or nSRST signals, and choice of connectors
1117 (e.g. which of two headers on the base board,
1118 or one from a daughtercard).
1119 For some Texas Instruments boards, you may need to jumper the
1120 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1122 @item @b{Boot Modes} ...
1123 Complex chips often support multiple boot modes, controlled
1124 by external jumpers. Make sure this is set up correctly.
1125 For example many i.MX boards from NXP need to be jumpered
1126 to "ATX mode" to start booting using the on-chip ROM, when
1127 using second stage bootloader code stored in a NAND flash chip.
1129 Such explicit configuration is common, and not limited to
1130 booting from NAND. You might also need to set jumpers to
1131 start booting using code loaded from an MMC/SD card; external
1132 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1133 flash; some external host; or various other sources.
1136 @item @b{Memory Addressing} ...
1137 Boards which support multiple boot modes may also have jumpers
1138 to configure memory addressing. One board, for example, jumpers
1139 external chipselect 0 (used for booting) to address either
1140 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1141 or NAND flash. When it's jumpered to address NAND flash, that
1142 board must also be told to start booting from on-chip ROM.
1144 Your @file{board.cfg} file may also need to be told this jumper
1145 configuration, so that it can know whether to declare NOR flash
1146 using @command{flash bank} or instead declare NAND flash with
1147 @command{nand device}; and likewise which probe to perform in
1148 its @code{reset-init} handler.
1150 A closely related issue is bus width. Jumpers might need to
1151 distinguish between 8 bit or 16 bit bus access for the flash
1152 used to start booting.
1154 @item @b{Peripheral Access} ...
1155 Development boards generally provide access to every peripheral
1156 on the chip, sometimes in multiple modes (such as by providing
1157 multiple audio codec chips).
1158 This interacts with software
1159 configuration of pin multiplexing, where for example a
1160 given pin may be routed either to the MMC/SD controller
1161 or the GPIO controller. It also often interacts with
1162 configuration jumpers. One jumper may be used to route
1163 signals to an MMC/SD card slot or an expansion bus (which
1164 might in turn affect booting); others might control which
1165 audio or video codecs are used.
1167 @end itemize
1169 Plus you should of course have @code{reset-init} event handlers
1170 which set up the hardware to match that jumper configuration.
1171 That includes in particular any oscillator or PLL used to clock
1172 the CPU, and any memory controllers needed to access external
1173 memory and peripherals. Without such handlers, you won't be
1174 able to access those resources without working target firmware
1175 which can do that setup ... this can be awkward when you're
1176 trying to debug that target firmware. Even if there's a ROM
1177 bootloader which handles a few issues, it rarely provides full
1178 access to all board-specific capabilities.
1181 @node Config File Guidelines
1182 @chapter Config File Guidelines
1184 This chapter is aimed at any user who needs to write a config file,
1185 including developers and integrators of OpenOCD and any user who
1186 needs to get a new board working smoothly.
1187 It provides guidelines for creating those files.
1189 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1190 with files including the ones listed here.
1191 Use them as-is where you can; or as models for new files.
1192 @itemize @bullet
1193 @item @file{interface} ...
1194 These are for debug adapters.
1195 Files that configure JTAG adapters go here.
1196 @example
1197 $ ls interface
1198 arm-jtag-ew.cfg hitex_str9-comstick.cfg oocdlink.cfg
1199 arm-usb-ocd.cfg icebear.cfg openocd-usb.cfg
1200 at91rm9200.cfg jlink.cfg parport.cfg
1201 axm0432.cfg jtagkey2.cfg parport_dlc5.cfg
1202 calao-usb-a9260-c01.cfg jtagkey.cfg rlink.cfg
1203 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg sheevaplug.cfg
1204 calao-usb-a9260.cfg luminary.cfg signalyzer.cfg
1205 chameleon.cfg luminary-icdi.cfg stm32-stick.cfg
1206 cortino.cfg luminary-lm3s811.cfg turtelizer2.cfg
1207 dummy.cfg olimex-arm-usb-ocd.cfg usbprog.cfg
1208 flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
1209 $
1210 @end example
1211 @item @file{board} ...
1212 think Circuit Board, PWA, PCB, they go by many names. Board files
1213 contain initialization items that are specific to a board.
1214 They reuse target configuration files, since the same
1215 microprocessor chips are used on many boards,
1216 but support for external parts varies widely. For
1217 example, the SDRAM initialization sequence for the board, or the type
1218 of external flash and what address it uses. Any initialization
1219 sequence to enable that external flash or SDRAM should be found in the
1220 board file. Boards may also contain multiple targets: two CPUs; or
1221 a CPU and an FPGA.
1222 @example
1223 $ ls board
1224 arm_evaluator7t.cfg keil_mcb1700.cfg
1225 at91rm9200-dk.cfg keil_mcb2140.cfg
1226 at91sam9g20-ek.cfg linksys_nslu2.cfg
1227 atmel_at91sam7s-ek.cfg logicpd_imx27.cfg
1228 atmel_at91sam9260-ek.cfg mini2440.cfg
1229 atmel_sam3u_ek.cfg olimex_LPC2378STK.cfg
1230 crossbow_tech_imote2.cfg olimex_lpc_h2148.cfg
1231 csb337.cfg olimex_sam7_ex256.cfg
1232 csb732.cfg olimex_sam9_l9260.cfg
1233 digi_connectcore_wi-9c.cfg olimex_stm32_h103.cfg
1234 dm355evm.cfg omap2420_h4.cfg
1235 dm365evm.cfg osk5912.cfg
1236 dm6446evm.cfg pic-p32mx.cfg
1237 eir.cfg propox_mmnet1001.cfg
1238 ek-lm3s1968.cfg pxa255_sst.cfg
1239 ek-lm3s3748.cfg sheevaplug.cfg
1240 ek-lm3s811.cfg stm3210e_eval.cfg
1241 ek-lm3s9b9x.cfg stm32f10x_128k_eval.cfg
1242 hammer.cfg str910-eval.cfg
1243 hitex_lpc2929.cfg telo.cfg
1244 hitex_stm32-performancestick.cfg ti_beagleboard.cfg
1245 hitex_str9-comstick.cfg topas910.cfg
1246 iar_str912_sk.cfg topasa900.cfg
1247 imx27ads.cfg unknown_at91sam9260.cfg
1248 imx27lnst.cfg x300t.cfg
1249 imx31pdk.cfg zy1000.cfg
1250 $
1251 @end example
1252 @item @file{target} ...
1253 think chip. The ``target'' directory represents the JTAG TAPs
1254 on a chip
1255 which OpenOCD should control, not a board. Two common types of targets
1256 are ARM chips and FPGA or CPLD chips.
1257 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1258 the target config file defines all of them.
1259 @example
1260 $ ls target
1261 aduc702x.cfg imx27.cfg pxa255.cfg
1262 ar71xx.cfg imx31.cfg pxa270.cfg
1263 at91eb40a.cfg imx35.cfg readme.txt
1264 at91r40008.cfg is5114.cfg sam7se512.cfg
1265 at91rm9200.cfg ixp42x.cfg sam7x256.cfg
1266 at91sam3u1c.cfg lm3s1968.cfg samsung_s3c2410.cfg
1267 at91sam3u1e.cfg lm3s3748.cfg samsung_s3c2440.cfg
1268 at91sam3u2c.cfg lm3s6965.cfg samsung_s3c2450.cfg
1269 at91sam3u2e.cfg lm3s811.cfg samsung_s3c4510.cfg
1270 at91sam3u4c.cfg lm3s9b9x.cfg samsung_s3c6410.cfg
1271 at91sam3u4e.cfg lpc1768.cfg sharp_lh79532.cfg
1272 at91sam3uXX.cfg lpc2103.cfg smdk6410.cfg
1273 at91sam7sx.cfg lpc2124.cfg smp8634.cfg
1274 at91sam9260.cfg lpc2129.cfg stm32.cfg
1275 c100.cfg lpc2148.cfg str710.cfg
1276 c100config.tcl lpc2294.cfg str730.cfg
1277 c100helper.tcl lpc2378.cfg str750.cfg
1278 c100regs.tcl lpc2478.cfg str912.cfg
1279 cs351x.cfg lpc2900.cfg telo.cfg
1280 davinci.cfg mega128.cfg ti_dm355.cfg
1281 dragonite.cfg netx500.cfg ti_dm365.cfg
1282 epc9301.cfg omap2420.cfg ti_dm6446.cfg
1283 feroceon.cfg omap3530.cfg tmpa900.cfg
1284 icepick.cfg omap5912.cfg tmpa910.cfg
1285 imx21.cfg pic32mx.cfg xba_revA3.cfg
1286 $
1287 @end example
1288 @item @emph{more} ... browse for other library files which may be useful.
1289 For example, there are various generic and CPU-specific utilities.
1290 @end itemize
1292 The @file{openocd.cfg} user config
1293 file may override features in any of the above files by
1294 setting variables before sourcing the target file, or by adding
1295 commands specific to their situation.
1297 @section Interface Config Files
1299 The user config file
1300 should be able to source one of these files with a command like this:
1302 @example
1303 source [find interface/FOOBAR.cfg]
1304 @end example
1306 A preconfigured interface file should exist for every debug adapter
1307 in use today with OpenOCD.
1308 That said, perhaps some of these config files
1309 have only been used by the developer who created it.
1311 A separate chapter gives information about how to set these up.
1312 @xref{Debug Adapter Configuration}.
1313 Read the OpenOCD source code (and Developer's GUide)
1314 if you have a new kind of hardware interface
1315 and need to provide a driver for it.
1317 @section Board Config Files
1318 @cindex config file, board
1319 @cindex board config file
1321 The user config file
1322 should be able to source one of these files with a command like this:
1324 @example
1325 source [find board/FOOBAR.cfg]
1326 @end example
1328 The point of a board config file is to package everything
1329 about a given board that user config files need to know.
1330 In summary the board files should contain (if present)
1332 @enumerate
1333 @item One or more @command{source [target/...cfg]} statements
1334 @item NOR flash configuration (@pxref{NOR Configuration})
1335 @item NAND flash configuration (@pxref{NAND Configuration})
1336 @item Target @code{reset} handlers for SDRAM and I/O configuration
1337 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1338 @item All things that are not ``inside a chip''
1339 @end enumerate
1341 Generic things inside target chips belong in target config files,
1342 not board config files. So for example a @code{reset-init} event
1343 handler should know board-specific oscillator and PLL parameters,
1344 which it passes to target-specific utility code.
1346 The most complex task of a board config file is creating such a
1347 @code{reset-init} event handler.
1348 Define those handlers last, after you verify the rest of the board
1349 configuration works.
1351 @subsection Communication Between Config files
1353 In addition to target-specific utility code, another way that
1354 board and target config files communicate is by following a
1355 convention on how to use certain variables.
1357 The full Tcl/Tk language supports ``namespaces'', but JIM-Tcl does not.
1358 Thus the rule we follow in OpenOCD is this: Variables that begin with
1359 a leading underscore are temporary in nature, and can be modified and
1360 used at will within a target configuration file.
1362 Complex board config files can do the things like this,
1363 for a board with three chips:
1365 @example
1366 # Chip #1: PXA270 for network side, big endian
1367 set CHIPNAME network
1368 set ENDIAN big
1369 source [find target/pxa270.cfg]
1370 # on return: _TARGETNAME = network.cpu
1371 # other commands can refer to the "network.cpu" target.
1372 $_TARGETNAME configure .... events for this CPU..
1374 # Chip #2: PXA270 for video side, little endian
1375 set CHIPNAME video
1376 set ENDIAN little
1377 source [find target/pxa270.cfg]
1378 # on return: _TARGETNAME = video.cpu
1379 # other commands can refer to the "video.cpu" target.
1380 $_TARGETNAME configure .... events for this CPU..
1382 # Chip #3: Xilinx FPGA for glue logic
1383 set CHIPNAME xilinx
1384 unset ENDIAN
1385 source [find target/spartan3.cfg]
1386 @end example
1388 That example is oversimplified because it doesn't show any flash memory,
1389 or the @code{reset-init} event handlers to initialize external DRAM
1390 or (assuming it needs it) load a configuration into the FPGA.
1391 Such features are usually needed for low-level work with many boards,
1392 where ``low level'' implies that the board initialization software may
1393 not be working. (That's a common reason to need JTAG tools. Another
1394 is to enable working with microcontroller-based systems, which often
1395 have no debugging support except a JTAG connector.)
1397 Target config files may also export utility functions to board and user
1398 config files. Such functions should use name prefixes, to help avoid
1399 naming collisions.
1401 Board files could also accept input variables from user config files.
1402 For example, there might be a @code{J4_JUMPER} setting used to identify
1403 what kind of flash memory a development board is using, or how to set
1404 up other clocks and peripherals.
1406 @subsection Variable Naming Convention
1407 @cindex variable names
1409 Most boards have only one instance of a chip.
1410 However, it should be easy to create a board with more than
1411 one such chip (as shown above).
1412 Accordingly, we encourage these conventions for naming
1413 variables associated with different @file{target.cfg} files,
1414 to promote consistency and
1415 so that board files can override target defaults.
1417 Inputs to target config files include:
1419 @itemize @bullet
1420 @item @code{CHIPNAME} ...
1421 This gives a name to the overall chip, and is used as part of
1422 tap identifier dotted names.
1423 While the default is normally provided by the chip manufacturer,
1424 board files may need to distinguish between instances of a chip.
1425 @item @code{ENDIAN} ...
1426 By default @option{little} - although chips may hard-wire @option{big}.
1427 Chips that can't change endianness don't need to use this variable.
1428 @item @code{CPUTAPID} ...
1429 When OpenOCD examines the JTAG chain, it can be told verify the
1430 chips against the JTAG IDCODE register.
1431 The target file will hold one or more defaults, but sometimes the
1432 chip in a board will use a different ID (perhaps a newer revision).
1433 @end itemize
1435 Outputs from target config files include:
1437 @itemize @bullet
1438 @item @code{_TARGETNAME} ...
1439 By convention, this variable is created by the target configuration
1440 script. The board configuration file may make use of this variable to
1441 configure things like a ``reset init'' script, or other things
1442 specific to that board and that target.
1443 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1444 @code{_TARGETNAME1}, ... etc.
1445 @end itemize
1447 @subsection The reset-init Event Handler
1448 @cindex event, reset-init
1449 @cindex reset-init handler
1451 Board config files run in the OpenOCD configuration stage;
1452 they can't use TAPs or targets, since they haven't been
1453 fully set up yet.
1454 This means you can't write memory or access chip registers;
1455 you can't even verify that a flash chip is present.
1456 That's done later in event handlers, of which the target @code{reset-init}
1457 handler is one of the most important.
1459 Except on microcontrollers, the basic job of @code{reset-init} event
1460 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1461 Microcontrollers rarely use boot loaders; they run right out of their
1462 on-chip flash and SRAM memory. But they may want to use one of these
1463 handlers too, if just for developer convenience.
1465 @quotation Note
1466 Because this is so very board-specific, and chip-specific, no examples
1467 are included here.
1468 Instead, look at the board config files distributed with OpenOCD.
1469 If you have a boot loader, its source code will help; so will
1470 configuration files for other JTAG tools
1471 (@pxref{Translating Configuration Files}).
1472 @end quotation
1474 Some of this code could probably be shared between different boards.
1475 For example, setting up a DRAM controller often doesn't differ by
1476 much except the bus width (16 bits or 32?) and memory timings, so a
1477 reusable TCL procedure loaded by the @file{target.cfg} file might take
1478 those as parameters.
1479 Similarly with oscillator, PLL, and clock setup;
1480 and disabling the watchdog.
1481 Structure the code cleanly, and provide comments to help
1482 the next developer doing such work.
1483 (@emph{You might be that next person} trying to reuse init code!)
1485 The last thing normally done in a @code{reset-init} handler is probing
1486 whatever flash memory was configured. For most chips that needs to be
1487 done while the associated target is halted, either because JTAG memory
1488 access uses the CPU or to prevent conflicting CPU access.
1490 @subsection JTAG Clock Rate
1492 Before your @code{reset-init} handler has set up
1493 the PLLs and clocking, you may need to run with
1494 a low JTAG clock rate.
1495 @xref{JTAG Speed}.
1496 Then you'd increase that rate after your handler has
1497 made it possible to use the faster JTAG clock.
1498 When the initial low speed is board-specific, for example
1499 because it depends on a board-specific oscillator speed, then
1500 you should probably set it up in the board config file;
1501 if it's target-specific, it belongs in the target config file.
1503 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1504 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1505 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1506 Consult chip documentation to determine the peak JTAG clock rate,
1507 which might be less than that.
1509 @quotation Warning
1510 On most ARMs, JTAG clock detection is coupled to the core clock, so
1511 software using a @option{wait for interrupt} operation blocks JTAG access.
1512 Adaptive clocking provides a partial workaround, but a more complete
1513 solution just avoids using that instruction with JTAG debuggers.
1514 @end quotation
1516 If both the chip and the board support adaptive clocking,
1517 use the @command{jtag_rclk}
1518 command, in case your board is used with JTAG adapter which
1519 also supports it. Otherwise use @command{adapter_khz}.
1520 Set the slow rate at the beginning of the reset sequence,
1521 and the faster rate as soon as the clocks are at full speed.
1523 @section Target Config Files
1524 @cindex config file, target
1525 @cindex target config file
1527 Board config files communicate with target config files using
1528 naming conventions as described above, and may source one or
1529 more target config files like this:
1531 @example
1532 source [find target/FOOBAR.cfg]
1533 @end example
1535 The point of a target config file is to package everything
1536 about a given chip that board config files need to know.
1537 In summary the target files should contain
1539 @enumerate
1540 @item Set defaults
1541 @item Add TAPs to the scan chain
1542 @item Add CPU targets (includes GDB support)
1543 @item CPU/Chip/CPU-Core specific features
1544 @item On-Chip flash
1545 @end enumerate
1547 As a rule of thumb, a target file sets up only one chip.
1548 For a microcontroller, that will often include a single TAP,
1549 which is a CPU needing a GDB target, and its on-chip flash.
1551 More complex chips may include multiple TAPs, and the target
1552 config file may need to define them all before OpenOCD
1553 can talk to the chip.
1554 For example, some phone chips have JTAG scan chains that include
1555 an ARM core for operating system use, a DSP,
1556 another ARM core embedded in an image processing engine,
1557 and other processing engines.
1559 @subsection Default Value Boiler Plate Code
1561 All target configuration files should start with code like this,
1562 letting board config files express environment-specific
1563 differences in how things should be set up.
1565 @example
1566 # Boards may override chip names, perhaps based on role,
1567 # but the default should match what the vendor uses
1568 if @{ [info exists CHIPNAME] @} @{
1570 @} else @{
1571 set _CHIPNAME sam7x256
1572 @}
1574 # ONLY use ENDIAN with targets that can change it.
1575 if @{ [info exists ENDIAN] @} @{
1576 set _ENDIAN $ENDIAN
1577 @} else @{
1578 set _ENDIAN little
1579 @}
1581 # TAP identifiers may change as chips mature, for example with
1582 # new revision fields (the "3" here). Pick a good default; you
1583 # can pass several such identifiers to the "jtag newtap" command.
1584 if @{ [info exists CPUTAPID ] @} @{
1586 @} else @{
1587 set _CPUTAPID 0x3f0f0f0f
1588 @}
1589 @end example
1590 @c but 0x3f0f0f0f is for an str73x part ...
1592 @emph{Remember:} Board config files may include multiple target
1593 config files, or the same target file multiple times
1594 (changing at least @code{CHIPNAME}).
1596 Likewise, the target configuration file should define
1597 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1598 use it later on when defining debug targets:
1600 @example
1602 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1603 @end example
1605 @subsection Adding TAPs to the Scan Chain
1606 After the ``defaults'' are set up,
1607 add the TAPs on each chip to the JTAG scan chain.
1608 @xref{TAP Declaration}, and the naming convention
1609 for taps.
1611 In the simplest case the chip has only one TAP,
1612 probably for a CPU or FPGA.
1613 The config file for the Atmel AT91SAM7X256
1614 looks (in part) like this:
1616 @example
1617 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1618 @end example
1620 A board with two such at91sam7 chips would be able
1621 to source such a config file twice, with different
1622 values for @code{CHIPNAME}, so
1623 it adds a different TAP each time.
1625 If there are nonzero @option{-expected-id} values,
1626 OpenOCD attempts to verify the actual tap id against those values.
1627 It will issue error messages if there is mismatch, which
1628 can help to pinpoint problems in OpenOCD configurations.
1630 @example
1631 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1632 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1633 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1634 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1635 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1636 @end example
1638 There are more complex examples too, with chips that have
1639 multiple TAPs. Ones worth looking at include:
1641 @itemize
1642 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1643 plus a JRC to enable them
1644 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1645 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1646 is not currently used)
1647 @end itemize
1649 @subsection Add CPU targets
1651 After adding a TAP for a CPU, you should set it up so that
1652 GDB and other commands can use it.
1653 @xref{CPU Configuration}.
1654 For the at91sam7 example above, the command can look like this;
1655 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1656 to little endian, and this chip doesn't support changing that.
1658 @example
1660 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1661 @end example
1663 Work areas are small RAM areas associated with CPU targets.
1664 They are used by OpenOCD to speed up downloads,
1665 and to download small snippets of code to program flash chips.
1666 If the chip includes a form of ``on-chip-ram'' - and many do - define
1667 a work area if you can.
1668 Again using the at91sam7 as an example, this can look like:
1670 @example
1671 $_TARGETNAME configure -work-area-phys 0x00200000 \
1672 -work-area-size 0x4000 -work-area-backup 0
1673 @end example
1675 @subsection Chip Reset Setup
1677 As a rule, you should put the @command{reset_config} command
1678 into the board file. Most things you think you know about a
1679 chip can be tweaked by the board.
1681 Some chips have specific ways the TRST and SRST signals are
1682 managed. In the unusual case that these are @emph{chip specific}
1683 and can never be changed by board wiring, they could go here.
1684 For example, some chips can't support JTAG debugging without
1685 both signals.
1687 Provide a @code{reset-assert} event handler if you can.
1688 Such a handler uses JTAG operations to reset the target,
1689 letting this target config be used in systems which don't
1690 provide the optional SRST signal, or on systems where you
1691 don't want to reset all targets at once.
1692 Such a handler might write to chip registers to force a reset,
1693 use a JRC to do that (preferable -- the target may be wedged!),
1694 or force a watchdog timer to trigger.
1695 (For Cortex-M3 targets, this is not necessary. The target
1696 driver knows how to use trigger an NVIC reset when SRST is
1697 not available.)
1699 Some chips need special attention during reset handling if
1700 they're going to be used with JTAG.
1701 An example might be needing to send some commands right
1702 after the target's TAP has been reset, providing a
1703 @code{reset-deassert-post} event handler that writes a chip
1704 register to report that JTAG debugging is being done.
1705 Another would be reconfiguring the watchdog so that it stops
1706 counting while the core is halted in the debugger.
1708 JTAG clocking constraints often change during reset, and in
1709 some cases target config files (rather than board config files)
1710 are the right places to handle some of those issues.
1711 For example, immediately after reset most chips run using a
1712 slower clock than they will use later.
1713 That means that after reset (and potentially, as OpenOCD
1714 first starts up) they must use a slower JTAG clock rate
1715 than they will use later.
1716 @xref{JTAG Speed}.
1718 @quotation Important
1719 When you are debugging code that runs right after chip
1720 reset, getting these issues right is critical.
1721 In particular, if you see intermittent failures when
1722 OpenOCD verifies the scan chain after reset,
1723 look at how you are setting up JTAG clocking.
1724 @end quotation
1726 @subsection ARM Core Specific Hacks
1728 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1729 special high speed download features - enable it.
1731 If present, the MMU, the MPU and the CACHE should be disabled.
1733 Some ARM cores are equipped with trace support, which permits
1734 examination of the instruction and data bus activity. Trace
1735 activity is controlled through an ``Embedded Trace Module'' (ETM)
1736 on one of the core's scan chains. The ETM emits voluminous data
1737 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
1738 If you are using an external trace port,
1739 configure it in your board config file.
1740 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1741 configure it in your target config file.
1743 @example
1744 etm config $_TARGETNAME 16 normal full etb
1745 etb config $_TARGETNAME $_CHIPNAME.etb
1746 @end example
1748 @subsection Internal Flash Configuration
1750 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1752 @b{Never ever} in the ``target configuration file'' define any type of
1753 flash that is external to the chip. (For example a BOOT flash on
1754 Chip Select 0.) Such flash information goes in a board file - not
1755 the TARGET (chip) file.
1757 Examples:
1758 @itemize @bullet
1759 @item at91sam7x256 - has 256K flash YES enable it.
1760 @item str912 - has flash internal YES enable it.
1761 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1762 @item pxa270 - again - CS0 flash - it goes in the board file.
1763 @end itemize
1765 @anchor{Translating Configuration Files}
1766 @section Translating Configuration Files
1767 @cindex translation
1768 If you have a configuration file for another hardware debugger
1769 or toolset (Abatron, BDI2000, BDI3000, CCS,
1770 Lauterbach, Segger, Macraigor, etc.), translating
1771 it into OpenOCD syntax is often quite straightforward. The most tricky
1772 part of creating a configuration script is oftentimes the reset init
1773 sequence where e.g. PLLs, DRAM and the like is set up.
1775 One trick that you can use when translating is to write small
1776 Tcl procedures to translate the syntax into OpenOCD syntax. This
1777 can avoid manual translation errors and make it easier to
1778 convert other scripts later on.
1780 Example of transforming quirky arguments to a simple search and
1781 replace job:
1783 @example
1784 # Lauterbach syntax(?)
1785 #
1786 # Data.Set c15:0x042f %long 0x40000015
1787 #
1788 # OpenOCD syntax when using procedure below.
1789 #
1790 # setc15 0x01 0x00050078
1792 proc setc15 @{regs value@} @{
1793 global TARGETNAME
1795 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
1797 arm mcr 15 [expr ($regs>>12)&0x7] \
1798 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
1799 [expr ($regs>>8)&0x7] $value
1800 @}
1801 @end example
1805 @node Daemon Configuration
1806 @chapter Daemon Configuration
1807 @cindex initialization
1808 The commands here are commonly found in the openocd.cfg file and are
1809 used to specify what TCP/IP ports are used, and how GDB should be
1810 supported.
1812 @anchor{Configuration Stage}
1813 @section Configuration Stage
1814 @cindex configuration stage
1815 @cindex config command
1817 When the OpenOCD server process starts up, it enters a
1818 @emph{configuration stage} which is the only time that
1819 certain commands, @emph{configuration commands}, may be issued.
1820 Normally, configuration commands are only available
1821 inside startup scripts.
1823 In this manual, the definition of a configuration command is
1824 presented as a @emph{Config Command}, not as a @emph{Command}
1825 which may be issued interactively.
1826 The runtime @command{help} command also highlights configuration
1827 commands, and those which may be issued at any time.
1829 Those configuration commands include declaration of TAPs,
1830 flash banks,
1831 the interface used for JTAG communication,
1832 and other basic setup.
1833 The server must leave the configuration stage before it
1834 may access or activate TAPs.
1835 After it leaves this stage, configuration commands may no
1836 longer be issued.
1838 @section Entering the Run Stage
1840 The first thing OpenOCD does after leaving the configuration
1841 stage is to verify that it can talk to the scan chain
1842 (list of TAPs) which has been configured.
1843 It will warn if it doesn't find TAPs it expects to find,
1844 or finds TAPs that aren't supposed to be there.
1845 You should see no errors at this point.
1846 If you see errors, resolve them by correcting the
1847 commands you used to configure the server.
1848 Common errors include using an initial JTAG speed that's too
1849 fast, and not providing the right IDCODE values for the TAPs
1850 on the scan chain.
1852 Once OpenOCD has entered the run stage, a number of commands
1853 become available.
1854 A number of these relate to the debug targets you may have declared.
1855 For example, the @command{mww} command will not be available until
1856 a target has been successfuly instantiated.
1857 If you want to use those commands, you may need to force
1858 entry to the run stage.
1860 @deffn {Config Command} init
1861 This command terminates the configuration stage and
1862 enters the run stage. This helps when you need to have
1863 the startup scripts manage tasks such as resetting the target,
1864 programming flash, etc. To reset the CPU upon startup, add "init" and
1865 "reset" at the end of the config script or at the end of the OpenOCD
1866 command line using the @option{-c} command line switch.
1868 If this command does not appear in any startup/configuration file
1869 OpenOCD executes the command for you after processing all
1870 configuration files and/or command line options.
1872 @b{NOTE:} This command normally occurs at or near the end of your
1873 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1874 targets ready. For example: If your openocd.cfg file needs to
1875 read/write memory on your target, @command{init} must occur before
1876 the memory read/write commands. This includes @command{nand probe}.
1877 @end deffn
1879 @deffn {Overridable Procedure} jtag_init
1880 This is invoked at server startup to verify that it can talk
1881 to the scan chain (list of TAPs) which has been configured.
1883 The default implementation first tries @command{jtag arp_init},
1884 which uses only a lightweight JTAG reset before examining the
1885 scan chain.
1886 If that fails, it tries again, using a harder reset
1887 from the overridable procedure @command{init_reset}.
1889 Implementations must have verified the JTAG scan chain before
1890 they return.
1891 This is done by calling @command{jtag arp_init}
1892 (or @command{jtag arp_init-reset}).
1893 @end deffn
1895 @anchor{TCP/IP Ports}
1896 @section TCP/IP Ports
1897 @cindex TCP port
1898 @cindex server
1899 @cindex port
1900 @cindex security
1901 The OpenOCD server accepts remote commands in several syntaxes.
1902 Each syntax uses a different TCP/IP port, which you may specify
1903 only during configuration (before those ports are opened).
1905 For reasons including security, you may wish to prevent remote
1906 access using one or more of these ports.
1907 In such cases, just specify the relevant port number as zero.
1908 If you disable all access through TCP/IP, you will need to
1909 use the command line @option{-pipe} option.
1911 @deffn {Command} gdb_port [number]
1912 @cindex GDB server
1913 Normally gdb listens to a TCP/IP port, but GDB can also
1914 communicate via pipes(stdin/out or named pipes). The name
1915 "gdb_port" stuck because it covers probably more than 90% of
1916 the normal use cases.
1918 No arguments reports GDB port. "pipe" means listen to stdin
1919 output to stdout, an integer is base port number, "disable"
1920 disables the gdb server.
1922 When using "pipe", also use log_output to redirect the log
1923 output to a file so as not to flood the stdin/out pipes.
1925 The -p/--pipe option is deprecated and a warning is printed
1926 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
1928 Any other string is interpreted as named pipe to listen to.
1929 Output pipe is the same name as input pipe, but with 'o' appended,
1930 e.g. /var/gdb, /var/gdbo.
1932 The GDB port for the first target will be the base port, the
1933 second target will listen on gdb_port + 1, and so on.
1934 When not specified during the configuration stage,
1935 the port @var{number} defaults to 3333.
1936 @end deffn
1938 @deffn {Command} tcl_port [number]
1939 Specify or query the port used for a simplified RPC
1940 connection that can be used by clients to issue TCL commands and get the
1941 output from the Tcl engine.
1942 Intended as a machine interface.
1943 When not specified during the configuration stage,
1944 the port @var{number} defaults to 6666.
1946 @end deffn
1948 @deffn {Command} telnet_port [number]
1949 Specify or query the
1950 port on which to listen for incoming telnet connections.
1951 This port is intended for interaction with one human through TCL commands.
1952 When not specified during the configuration stage,
1953 the port @var{number} defaults to 4444.
1954 When specified as zero, this port is not activated.
1955 @end deffn
1957 @anchor{GDB Configuration}
1958 @section GDB Configuration
1959 @cindex GDB
1960 @cindex GDB configuration
1961 You can reconfigure some GDB behaviors if needed.
1962 The ones listed here are static and global.
1963 @xref{Target Configuration}, about configuring individual targets.
1964 @xref{Target Events}, about configuring target-specific event handling.
1966 @anchor{gdb_breakpoint_override}
1967 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
1968 Force breakpoint type for gdb @command{break} commands.
1969 This option supports GDB GUIs which don't
1970 distinguish hard versus soft breakpoints, if the default OpenOCD and
1971 GDB behaviour is not sufficient. GDB normally uses hardware
1972 breakpoints if the memory map has been set up for flash regions.
1973 @end deffn
1975 @anchor{gdb_flash_program}
1976 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
1977 Set to @option{enable} to cause OpenOCD to program the flash memory when a
1978 vFlash packet is received.
1979 The default behaviour is @option{enable}.
1980 @end deffn
1982 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
1983 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
1984 requested. GDB will then know when to set hardware breakpoints, and program flash
1985 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1986 for flash programming to work.
1987 Default behaviour is @option{enable}.
1988 @xref{gdb_flash_program}.
1989 @end deffn
1991 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
1992 Specifies whether data aborts cause an error to be reported
1993 by GDB memory read packets.
1994 The default behaviour is @option{disable};
1995 use @option{enable} see these errors reported.
1996 @end deffn
1998 @anchor{Event Polling}
1999 @section Event Polling
2001 Hardware debuggers are parts of asynchronous systems,
2002 where significant events can happen at any time.
2003 The OpenOCD server needs to detect some of these events,
2004 so it can report them to through TCL command line
2005 or to GDB.
2007 Examples of such events include:
2009 @itemize
2010 @item One of the targets can stop running ... maybe it triggers
2011 a code breakpoint or data watchpoint, or halts itself.
2012 @item Messages may be sent over ``debug message'' channels ... many
2013 targets support such messages sent over JTAG,
2014 for receipt by the person debugging or tools.
2015 @item Loss of power ... some adapters can detect these events.
2016 @item Resets not issued through JTAG ... such reset sources
2017 can include button presses or other system hardware, sometimes
2018 including the target itself (perhaps through a watchdog).
2019 @item Debug instrumentation sometimes supports event triggering
2020 such as ``trace buffer full'' (so it can quickly be emptied)
2021 or other signals (to correlate with code behavior).
2022 @end itemize
2024 None of those events are signaled through standard JTAG signals.
2025 However, most conventions for JTAG connectors include voltage
2026 level and system reset (SRST) signal detection.
2027 Some connectors also include instrumentation signals, which
2028 can imply events when those signals are inputs.
2030 In general, OpenOCD needs to periodically check for those events,
2031 either by looking at the status of signals on the JTAG connector
2032 or by sending synchronous ``tell me your status'' JTAG requests
2033 to the various active targets.
2034 There is a command to manage and monitor that polling,
2035 which is normally done in the background.
2037 @deffn Command poll [@option{on}|@option{off}]
2038 Poll the current target for its current state.
2039 (Also, @pxref{target curstate}.)
2040 If that target is in debug mode, architecture
2041 specific information about the current state is printed.
2042 An optional parameter
2043 allows background polling to be enabled and disabled.
2045 You could use this from the TCL command shell, or
2046 from GDB using @command{monitor poll} command.
2047 Leave background polling enabled while you're using GDB.
2048 @example
2049 > poll
2050 background polling: on
2051 target state: halted
2052 target halted in ARM state due to debug-request, \
2053 current mode: Supervisor
2054 cpsr: 0x800000d3 pc: 0x11081bfc
2055 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2056 >
2057 @end example
2058 @end deffn
2060 @node Debug Adapter Configuration
2061 @chapter Debug Adapter Configuration
2062 @cindex config file, interface
2063 @cindex interface config file
2065 Correctly installing OpenOCD includes making your operating system give
2066 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2067 are used to select which one is used, and to configure how it is used.
2069 @quotation Note
2070 Because OpenOCD started out with a focus purely on JTAG, you may find
2071 places where it wrongly presumes JTAG is the only transport protocol
2072 in use. Be aware that recent versions of OpenOCD are removing that
2073 limitation. JTAG remains more functional than most other transports.
2074 Other transports do not support boundary scan operations, or may be
2075 specific to a given chip vendor. Some might be usable only for
2076 programming flash memory, instead of also for debugging.
2077 @end quotation
2079 Debug Adapters/Interfaces/Dongles are normally configured
2080 through commands in an interface configuration
2081 file which is sourced by your @file{openocd.cfg} file, or
2082 through a command line @option{-f interface/....cfg} option.
2084 @example
2085 source [find interface/olimex-jtag-tiny.cfg]
2086 @end example
2088 These commands tell
2089 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2090 A few cases are so simple that you only need to say what driver to use:
2092 @example
2093 # jlink interface
2094 interface jlink
2095 @end example
2097 Most adapters need a bit more configuration than that.
2100 @section Interface Configuration
2102 The interface command tells OpenOCD what type of debug adapter you are
2103 using. Depending on the type of adapter, you may need to use one or
2104 more additional commands to further identify or configure the adapter.
2106 @deffn {Config Command} {interface} name
2107 Use the interface driver @var{name} to connect to the
2108 target.
2109 @end deffn
2111 @deffn Command {interface_list}
2112 List the debug adapter drivers that have been built into
2113 the running copy of OpenOCD.
2114 @end deffn
2115 @deffn Command {interface transports} transport_name+
2116 Specifies the transports supported by this debug adapter.
2117 The adapter driver builds-in similar knowledge; use this only
2118 when external configuration (such as jumpering) changes what
2119 the hardware can support.
2120 @end deffn
2124 @deffn Command {adapter_name}
2125 Returns the name of the debug adapter driver being used.
2126 @end deffn
2128 @section Interface Drivers
2130 Each of the interface drivers listed here must be explicitly
2131 enabled when OpenOCD is configured, in order to be made
2132 available at run time.
2134 @deffn {Interface Driver} {amt_jtagaccel}
2135 Amontec Chameleon in its JTAG Accelerator configuration,
2136 connected to a PC's EPP mode parallel port.
2137 This defines some driver-specific commands:
2139 @deffn {Config Command} {parport_port} number
2140 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2141 the number of the @file{/dev/parport} device.
2142 @end deffn
2144 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2145 Displays status of RTCK option.
2146 Optionally sets that option first.
2147 @end deffn
2148 @end deffn
2150 @deffn {Interface Driver} {arm-jtag-ew}
2151 Olimex ARM-JTAG-EW USB adapter
2152 This has one driver-specific command:
2154 @deffn Command {armjtagew_info}
2155 Logs some status
2156 @end deffn
2157 @end deffn
2159 @deffn {Interface Driver} {at91rm9200}
2160 Supports bitbanged JTAG from the local system,
2161 presuming that system is an Atmel AT91rm9200
2162 and a specific set of GPIOs is used.
2163 @c command: at91rm9200_device NAME
2164 @c chooses among list of bit configs ... only one option
2165 @end deffn
2167 @deffn {Interface Driver} {dummy}
2168 A dummy software-only driver for debugging.
2169 @end deffn
2171 @deffn {Interface Driver} {ep93xx}
2172 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2173 @end deffn
2175 @deffn {Interface Driver} {ft2232}
2176 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2177 These interfaces have several commands, used to configure the driver
2178 before initializing the JTAG scan chain:
2180 @deffn {Config Command} {ft2232_device_desc} description
2181 Provides the USB device description (the @emph{iProduct string})
2182 of the FTDI FT2232 device. If not
2183 specified, the FTDI default value is used. This setting is only valid
2184 if compiled with FTD2XX support.
2185 @end deffn
2187 @deffn {Config Command} {ft2232_serial} serial-number
2188 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2189 in case the vendor provides unique IDs and more than one FT2232 device
2190 is connected to the host.
2191 If not specified, serial numbers are not considered.
2192 (Note that USB serial numbers can be arbitrary Unicode strings,
2193 and are not restricted to containing only decimal digits.)
2194 @end deffn
2196 @deffn {Config Command} {ft2232_layout} name
2197 Each vendor's FT2232 device can use different GPIO signals
2198 to control output-enables, reset signals, and LEDs.
2199 Currently valid layout @var{name} values include:
2200 @itemize @minus
2201 @item @b{axm0432_jtag} Axiom AXM-0432
2202 @item @b{comstick} Hitex STR9 comstick
2203 @item @b{cortino} Hitex Cortino JTAG interface
2204 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
2205 either for the local Cortex-M3 (SRST only)
2206 or in a passthrough mode (neither SRST nor TRST)
2207 This layout can not support the SWO trace mechanism, and should be
2208 used only for older boards (before rev C).
2209 @item @b{luminary_icdi} This layout should be used with most Luminary
2210 eval boards, including Rev C LM3S811 eval boards and the eponymous
2211 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2212 to debug some other target. It can support the SWO trace mechanism.
2213 @item @b{flyswatter} Tin Can Tools Flyswatter
2214 @item @b{icebear} ICEbear JTAG adapter from Section 5
2215 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2216 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2217 @item @b{m5960} American Microsystems M5960
2218 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2219 @item @b{oocdlink} OOCDLink
2220 @c oocdlink ~= jtagkey_prototype_v1
2221 @item @b{redbee-econotag} Integrated with a Redbee development board.
2222 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2223 @item @b{sheevaplug} Marvell Sheevaplug development kit
2224 @item @b{signalyzer} Xverve Signalyzer
2225 @item @b{stm32stick} Hitex STM32 Performance Stick
2226 @item @b{turtelizer2} egnite Software turtelizer2
2227 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2228 @end itemize
2229 @end deffn
2231 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2232 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2233 default values are used.
2234 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2235 @example
2236 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2237 @end example
2238 @end deffn
2240 @deffn {Config Command} {ft2232_latency} ms
2241 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2242 ft2232_read() fails to return the expected number of bytes. This can be caused by
2243 USB communication delays and has proved hard to reproduce and debug. Setting the
2244 FT2232 latency timer to a larger value increases delays for short USB packets but it
2245 also reduces the risk of timeouts before receiving the expected number of bytes.
2246 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2247 @end deffn
2249 For example, the interface config file for a
2250 Turtelizer JTAG Adapter looks something like this:
2252 @example
2253 interface ft2232
2254 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2255 ft2232_layout turtelizer2
2256 ft2232_vid_pid 0x0403 0xbdc8
2257 @end example
2258 @end deffn
2260 @deffn {Interface Driver} {usb_blaster}
2261 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2262 for FTDI chips. These interfaces have several commands, used to
2263 configure the driver before initializing the JTAG scan chain:
2265 @deffn {Config Command} {usb_blaster_device_desc} description
2266 Provides the USB device description (the @emph{iProduct string})
2267 of the FTDI FT245 device. If not
2268 specified, the FTDI default value is used. This setting is only valid
2269 if compiled with FTD2XX support.
2270 @end deffn
2272 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2273 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2274 default values are used.
2275 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2276 Altera USB-Blaster (default):
2277 @example
2278 usb_blaster_vid_pid 0x09FB 0x6001
2279 @end example
2280 The following VID/PID is for Kolja Waschk's USB JTAG:
2281 @example
2282 usb_blaster_vid_pid 0x16C0 0x06AD
2283 @end example
2284 @end deffn
2286 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2287 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2288 female JTAG header). These pins can be used as SRST and/or TRST provided the
2289 appropriate connections are made on the target board.
2291 For example, to use pin 6 as SRST (as with an AVR board):
2292 @example
2293 $_TARGETNAME configure -event reset-assert \
2294 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2295 @end example
2296 @end deffn
2298 @end deffn
2300 @deffn {Interface Driver} {gw16012}
2301 Gateworks GW16012 JTAG programmer.
2302 This has one driver-specific command:
2304 @deffn {Config Command} {parport_port} [port_number]
2305 Display either the address of the I/O port
2306 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2307 If a parameter is provided, first switch to use that port.
2308 This is a write-once setting.
2309 @end deffn
2310 @end deffn
2312 @deffn {Interface Driver} {jlink}
2313 Segger jlink USB adapter
2314 @c command: jlink_info
2315 @c dumps status
2316 @c command: jlink_hw_jtag (2|3)
2317 @c sets version 2 or 3
2318 @end deffn
2320 @deffn {Interface Driver} {parport}
2321 Supports PC parallel port bit-banging cables:
2322 Wigglers, PLD download cable, and more.
2323 These interfaces have several commands, used to configure the driver
2324 before initializing the JTAG scan chain:
2326 @deffn {Config Command} {parport_cable} name
2327 Set the layout of the parallel port cable used to connect to the target.
2328 This is a write-once setting.
2329 Currently valid cable @var{name} values include:
2331 @itemize @minus
2332 @item @b{altium} Altium Universal JTAG cable.
2333 @item @b{arm-jtag} Same as original wiggler except SRST and
2334 TRST connections reversed and TRST is also inverted.
2335 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2336 in configuration mode. This is only used to
2337 program the Chameleon itself, not a connected target.
2338 @item @b{dlc5} The Xilinx Parallel cable III.
2339 @item @b{flashlink} The ST Parallel cable.
2340 @item @b{lattice} Lattice ispDOWNLOAD Cable
2341 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2342 some versions of
2343 Amontec's Chameleon Programmer. The new version available from
2344 the website uses the original Wiggler layout ('@var{wiggler}')
2345 @item @b{triton} The parallel port adapter found on the
2346 ``Karo Triton 1 Development Board''.
2347 This is also the layout used by the HollyGates design
2348 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2349 @item @b{wiggler} The original Wiggler layout, also supported by
2350 several clones, such as the Olimex ARM-JTAG
2351 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2352 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2353 @end itemize
2354 @end deffn
2356 @deffn {Config Command} {parport_port} [port_number]
2357 Display either the address of the I/O port
2358 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2359 If a parameter is provided, first switch to use that port.
2360 This is a write-once setting.
2362 When using PPDEV to access the parallel port, use the number of the parallel port:
2363 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2364 you may encounter a problem.
2365 @end deffn
2367 @deffn Command {parport_toggling_time} [nanoseconds]
2368 Displays how many nanoseconds the hardware needs to toggle TCK;
2369 the parport driver uses this value to obey the
2370 @command{adapter_khz} configuration.
2371 When the optional @var{nanoseconds} parameter is given,
2372 that setting is changed before displaying the current value.
2374 The default setting should work reasonably well on commodity PC hardware.
2375 However, you may want to calibrate for your specific hardware.
2376 @quotation Tip
2377 To measure the toggling time with a logic analyzer or a digital storage
2378 oscilloscope, follow the procedure below:
2379 @example
2380 > parport_toggling_time 1000
2381 > adapter_khz 500
2382 @end example
2383 This sets the maximum JTAG clock speed of the hardware, but
2384 the actual speed probably deviates from the requested 500 kHz.
2385 Now, measure the time between the two closest spaced TCK transitions.
2386 You can use @command{runtest 1000} or something similar to generate a
2387 large set of samples.
2388 Update the setting to match your measurement:
2389 @example
2390 > parport_toggling_time <measured nanoseconds>
2391 @end example
2392 Now the clock speed will be a better match for @command{adapter_khz rate}
2393 commands given in OpenOCD scripts and event handlers.
2395 You can do something similar with many digital multimeters, but note
2396 that you'll probably need to run the clock continuously for several
2397 seconds before it decides what clock rate to show. Adjust the
2398 toggling time up or down until the measured clock rate is a good
2399 match for the adapter_khz rate you specified; be conservative.
2400 @end quotation
2401 @end deffn
2403 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2404 This will configure the parallel driver to write a known
2405 cable-specific value to the parallel interface on exiting OpenOCD.
2406 @end deffn
2408 For example, the interface configuration file for a
2409 classic ``Wiggler'' cable on LPT2 might look something like this:
2411 @example
2412 interface parport
2413 parport_port 0x278
2414 parport_cable wiggler
2415 @end example
2416 @end deffn
2418 @deffn {Interface Driver} {presto}
2419 ASIX PRESTO USB JTAG programmer.
2420 @deffn {Config Command} {presto_serial} serial_string
2421 Configures the USB serial number of the Presto device to use.
2422 @end deffn
2423 @end deffn
2425 @deffn {Interface Driver} {rlink}
2426 Raisonance RLink USB adapter
2427 @end deffn
2429 @deffn {Interface Driver} {usbprog}
2430 usbprog is a freely programmable USB adapter.
2431 @end deffn
2433 @deffn {Interface Driver} {vsllink}
2434 vsllink is part of Versaloon which is a versatile USB programmer.
2436 @quotation Note
2437 This defines quite a few driver-specific commands,
2438 which are not currently documented here.
2439 @end quotation
2440 @end deffn
2442 @deffn {Interface Driver} {ZY1000}
2443 This is the Zylin ZY1000 JTAG debugger.
2444 @end deffn
2446 @quotation Note
2447 This defines some driver-specific commands,
2448 which are not currently documented here.
2449 @end quotation
2451 @deffn Command power [@option{on}|@option{off}]
2452 Turn power switch to target on/off.
2453 No arguments: print status.
2454 @end deffn
2456 @section Transport Configuration
2457 As noted earlier, depending on the version of OpenOCD you use,
2458 and the debug adapter you are using,
2459 several transports may be available to
2460 communicate with debug targets (or perhaps to program flash memory).
2461 @deffn Command {transport list}
2462 displays the names of the transports supported by this
2463 version of OpenOCD.
2464 @end deffn
2466 @deffn Command {transport select} transport_name
2467 Select which of the supported transports to use in this OpenOCD session.
2468 The transport must be supported by the debug adapter hardware and by the
2469 version of OPenOCD you are using (including the adapter's driver).
2470 No arguments: returns name of session's selected transport.
2471 @end deffn
2473 @subsection JTAG Transport
2474 JTAG is the original transport supported by OpenOCD, and most
2475 of the OpenOCD commands support it.
2476 JTAG transports expose a chain of one or more Test Access Points (TAPs),
2477 each of which must be explicitly declared.
2478 JTAG supports both debugging and boundary scan testing.
2479 Flash programming support is built on top of debug support.
2480 @subsection SWD Transport
2481 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
2482 Debug Access Point (DAP, which must be explicitly declared.
2483 (SWD uses fewer signal wires than JTAG.)
2484 SWD is debug-oriented, and does not support boundary scan testing.
2485 Flash programming support is built on top of debug support.
2486 (Some processors support both JTAG and SWD.)
2487 @subsection SPI Transport
2488 The Serial Peripheral Interface (SPI) is a general purpose transport
2489 which uses four wire signaling. Some processors use it as part of a
2490 solution for flash programming.
2492 @anchor{JTAG Speed}
2493 @section JTAG Speed
2494 JTAG clock setup is part of system setup.
2495 It @emph{does not belong with interface setup} since any interface
2496 only knows a few of the constraints for the JTAG clock speed.
2497 Sometimes the JTAG speed is
2498 changed during the target initialization process: (1) slow at
2499 reset, (2) program the CPU clocks, (3) run fast.
2500 Both the "slow" and "fast" clock rates are functions of the
2501 oscillators used, the chip, the board design, and sometimes
2502 power management software that may be active.
2504 The speed used during reset, and the scan chain verification which
2505 follows reset, can be adjusted using a @code{reset-start}
2506 target event handler.
2507 It can then be reconfigured to a faster speed by a
2508 @code{reset-init} target event handler after it reprograms those
2509 CPU clocks, or manually (if something else, such as a boot loader,
2510 sets up those clocks).
2511 @xref{Target Events}.
2512 When the initial low JTAG speed is a chip characteristic, perhaps
2513 because of a required oscillator speed, provide such a handler
2514 in the target config file.
2515 When that speed is a function of a board-specific characteristic
2516 such as which speed oscillator is used, it belongs in the board
2517 config file instead.
2518 In both cases it's safest to also set the initial JTAG clock rate
2519 to that same slow speed, so that OpenOCD never starts up using a
2520 clock speed that's faster than the scan chain can support.
2522 @example
2523 jtag_rclk 3000
2524 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
2525 @end example
2527 If your system supports adaptive clocking (RTCK), configuring
2528 JTAG to use that is probably the most robust approach.
2529 However, it introduces delays to synchronize clocks; so it
2530 may not be the fastest solution.
2532 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
2533 instead of @command{adapter_khz}, but only for (ARM) cores and boards
2534 which support adaptive clocking.
2536 @deffn {Command} adapter_khz max_speed_kHz
2537 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
2538 JTAG interfaces usually support a limited number of
2539 speeds. The speed actually used won't be faster
2540 than the speed specified.
2542 Chip data sheets generally include a top JTAG clock rate.
2543 The actual rate is often a function of a CPU core clock,
2544 and is normally less than that peak rate.
2545 For example, most ARM cores accept at most one sixth of the CPU clock.
2547 Speed 0 (khz) selects RTCK method.
2548 @xref{FAQ RTCK}.
2549 If your system uses RTCK, you won't need to change the
2550 JTAG clocking after setup.
2551 Not all interfaces, boards, or targets support ``rtck''.
2552 If the interface device can not
2553 support it, an error is returned when you try to use RTCK.
2554 @end deffn
2556 @defun jtag_rclk fallback_speed_kHz
2557 @cindex adaptive clocking
2558 @cindex RTCK
2559 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
2560 If that fails (maybe the interface, board, or target doesn't
2561 support it), falls back to the specified frequency.
2562 @example
2563 # Fall back to 3mhz if RTCK is not supported
2564 jtag_rclk 3000
2565 @end example
2566 @end defun
2568 @node Reset Configuration
2569 @chapter Reset Configuration
2570 @cindex Reset Configuration
2572 Every system configuration may require a different reset
2573 configuration. This can also be quite confusing.
2574 Resets also interact with @var{reset-init} event handlers,
2575 which do things like setting up clocks and DRAM, and
2576 JTAG clock rates. (@xref{JTAG Speed}.)
2577 They can also interact with JTAG routers.
2578 Please see the various board files for examples.
2580 @quotation Note
2581 To maintainers and integrators:
2582 Reset configuration touches several things at once.
2583 Normally the board configuration file
2584 should define it and assume that the JTAG adapter supports
2585 everything that's wired up to the board's JTAG connector.
2587 However, the target configuration file could also make note
2588 of something the silicon vendor has done inside the chip,
2589 which will be true for most (or all) boards using that chip.
2590 And when the JTAG adapter doesn't support everything, the
2591 user configuration file will need to override parts of
2592 the reset configuration provided by other files.
2593 @end quotation
2595 @section Types of Reset
2597 There are many kinds of reset possible through JTAG, but
2598 they may not all work with a given board and adapter.
2599 That's part of why reset configuration can be error prone.
2601 @itemize @bullet
2602 @item
2603 @emph{System Reset} ... the @emph{SRST} hardware signal
2604 resets all chips connected to the JTAG adapter, such as processors,
2605 power management chips, and I/O controllers. Normally resets triggered
2606 with this signal behave exactly like pressing a RESET button.
2607 @item
2608 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
2609 just the TAP controllers connected to the JTAG adapter.
2610 Such resets should not be visible to the rest of the system; resetting a
2611 device's the TAP controller just puts that controller into a known state.
2612 @item
2613 @emph{Emulation Reset} ... many devices can be reset through JTAG
2614 commands. These resets are often distinguishable from system
2615 resets, either explicitly (a "reset reason" register says so)
2616 or implicitly (not all parts of the chip get reset).
2617 @item
2618 @emph{Other Resets} ... system-on-chip devices often support
2619 several other types of reset.
2620 You may need to arrange that a watchdog timer stops
2621 while debugging, preventing a watchdog reset.
2622 There may be individual module resets.
2623 @end itemize
2625 In the best case, OpenOCD can hold SRST, then reset
2626 the TAPs via TRST and send commands through JTAG to halt the
2627 CPU at the reset vector before the 1st instruction is executed.
2628 Then when it finally releases the SRST signal, the system is
2629 halted under debugger control before any code has executed.
2630 This is the behavior required to support the @command{reset halt}
2631 and @command{reset init} commands; after @command{reset init} a
2632 board-specific script might do things like setting up DRAM.
2633 (@xref{Reset Command}.)
2635 @anchor{SRST and TRST Issues}
2636 @section SRST and TRST Issues
2638 Because SRST and TRST are hardware signals, they can have a
2639 variety of system-specific constraints. Some of the most
2640 common issues are:
2642 @itemize @bullet
2644 @item @emph{Signal not available} ... Some boards don't wire
2645 SRST or TRST to the JTAG connector. Some JTAG adapters don't
2646 support such signals even if they are wired up.
2647 Use the @command{reset_config} @var{signals} options to say
2648 when either of those signals is not connected.
2649 When SRST is not available, your code might not be able to rely
2650 on controllers having been fully reset during code startup.
2651 Missing TRST is not a problem, since JTAG level resets can
2652 be triggered using with TMS signaling.
2654 @item @emph{Signals shorted} ... Sometimes a chip, board, or
2655 adapter will connect SRST to TRST, instead of keeping them separate.
2656 Use the @command{reset_config} @var{combination} options to say
2657 when those signals aren't properly independent.
2659 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
2660 delay circuit, reset supervisor, or on-chip features can extend
2661 the effect of a JTAG adapter's reset for some time after the adapter
2662 stops issuing the reset. For example, there may be chip or board
2663 requirements that all reset pulses last for at least a
2664 certain amount of time; and reset buttons commonly have
2665 hardware debouncing.
2666 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
2667 commands to say when extra delays are needed.
2669 @item @emph{Drive type} ... Reset lines often have a pullup
2670 resistor, letting the JTAG interface treat them as open-drain
2671 signals. But that's not a requirement, so the adapter may need
2672 to use push/pull output drivers.
2673 Also, with weak pullups it may be advisable to drive
2674 signals to both levels (push/pull) to minimize rise times.
2675 Use the @command{reset_config} @var{trst_type} and
2676 @var{srst_type} parameters to say how to drive reset signals.
2678 @item @emph{Special initialization} ... Targets sometimes need
2679 special JTAG initialization sequences to handle chip-specific
2680 issues (not limited to errata).
2681 For example, certain JTAG commands might need to be issued while
2682 the system as a whole is in a reset state (SRST active)
2683 but the JTAG scan chain is usable (TRST inactive).
2684 Many systems treat combined assertion of SRST and TRST as a
2685 trigger for a harder reset than SRST alone.
2686 Such custom reset handling is discussed later in this chapter.
2687 @end itemize
2689 There can also be other issues.
2690 Some devices don't fully conform to the JTAG specifications.
2691 Trivial system-specific differences are common, such as
2692 SRST and TRST using slightly different names.
2693 There are also vendors who distribute key JTAG documentation for
2694 their chips only to developers who have signed a Non-Disclosure
2695 Agreement (NDA).
2697 Sometimes there are chip-specific extensions like a requirement to use
2698 the normally-optional TRST signal (precluding use of JTAG adapters which
2699 don't pass TRST through), or needing extra steps to complete a TAP reset.
2701 In short, SRST and especially TRST handling may be very finicky,
2702 needing to cope with both architecture and board specific constraints.
2704 @section Commands for Handling Resets
2706 @deffn {Command} adapter_nsrst_assert_width milliseconds
2707 Minimum amount of time (in milliseconds) OpenOCD should wait
2708 after asserting nSRST (active-low system reset) before
2709 allowing it to be deasserted.
2710 @end deffn
2712 @deffn {Command} adapter_nsrst_delay milliseconds
2713 How long (in milliseconds) OpenOCD should wait after deasserting
2714 nSRST (active-low system reset) before starting new JTAG operations.
2715 When a board has a reset button connected to SRST line it will
2716 probably have hardware debouncing, implying you should use this.
2717 @end deffn
2719 @deffn {Command} jtag_ntrst_assert_width milliseconds
2720 Minimum amount of time (in milliseconds) OpenOCD should wait
2721 after asserting nTRST (active-low JTAG TAP reset) before
2722 allowing it to be deasserted.
2723 @end deffn
2725 @deffn {Command} jtag_ntrst_delay milliseconds
2726 How long (in milliseconds) OpenOCD should wait after deasserting
2727 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
2728 @end deffn
2730 @deffn {Command} reset_config mode_flag ...
2731 This command displays or modifies the reset configuration
2732 of your combination of JTAG board and target in target
2733 configuration scripts.
2735 Information earlier in this section describes the kind of problems
2736 the command is intended to address (@pxref{SRST and TRST Issues}).
2737 As a rule this command belongs only in board config files,
2738 describing issues like @emph{board doesn't connect TRST};
2739 or in user config files, addressing limitations derived
2740 from a particular combination of interface and board.
2741 (An unlikely example would be using a TRST-only adapter
2742 with a board that only wires up SRST.)
2744 The @var{mode_flag} options can be specified in any order, but only one
2745 of each type -- @var{signals}, @var{combination},
2746 @var{gates},
2747 @var{trst_type},
2748 and @var{srst_type} -- may be specified at a time.
2749 If you don't provide a new value for a given type, its previous
2750 value (perhaps the default) is unchanged.
2751 For example, this means that you don't need to say anything at all about
2752 TRST just to declare that if the JTAG adapter should want to drive SRST,
2753 it must explicitly be driven high (@option{srst_push_pull}).
2755 @itemize
2756 @item
2757 @var{signals} can specify which of the reset signals are connected.
2758 For example, If the JTAG interface provides SRST, but the board doesn't
2759 connect that signal properly, then OpenOCD can't use it.
2760 Possible values are @option{none} (the default), @option{trst_only},
2761 @option{srst_only} and @option{trst_and_srst}.
2763 @quotation Tip
2764 If your board provides SRST and/or TRST through the JTAG connector,
2765 you must declare that so those signals can be used.
2766 @end quotation
2768 @item
2769 The @var{combination} is an optional value specifying broken reset
2770 signal implementations.
2771 The default behaviour if no option given is @option{separate},
2772 indicating everything behaves normally.
2773 @option{srst_pulls_trst} states that the
2774 test logic is reset together with the reset of the system (e.g. NXP
2775 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
2776 the system is reset together with the test logic (only hypothetical, I
2777 haven't seen hardware with such a bug, and can be worked around).
2778 @option{combined} implies both @option{srst_pulls_trst} and
2779 @option{trst_pulls_srst}.
2781 @item
2782 The @var{gates} tokens control flags that describe some cases where
2783 JTAG may be unvailable during reset.
2784 @option{srst_gates_jtag} (default)
2785 indicates that asserting SRST gates the
2786 JTAG clock. This means that no communication can happen on JTAG
2787 while SRST is asserted.
2788 Its converse is @option{srst_nogate}, indicating that JTAG commands
2789 can safely be issued while SRST is active.
2790 @end itemize
2792 The optional @var{trst_type} and @var{srst_type} parameters allow the
2793 driver mode of each reset line to be specified. These values only affect
2794 JTAG interfaces with support for different driver modes, like the Amontec
2795 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
2796 relevant signal (TRST or SRST) is not connected.
2798 @itemize
2799 @item
2800 Possible @var{trst_type} driver modes for the test reset signal (TRST)
2801 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
2802 Most boards connect this signal to a pulldown, so the JTAG TAPs
2803 never leave reset unless they are hooked up to a JTAG adapter.
2805 @item
2806 Possible @var{srst_type} driver modes for the system reset signal (SRST)
2807 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
2808 Most boards connect this signal to a pullup, and allow the
2809 signal to be pulled low by various events including system
2810 powerup and pressing a reset button.
2811 @end itemize
2812 @end deffn
2814 @section Custom Reset Handling
2815 @cindex events
2817 OpenOCD has several ways to help support the various reset
2818 mechanisms provided by chip and board vendors.
2819 The commands shown in the previous section give standard parameters.
2820 There are also @emph{event handlers} associated with TAPs or Targets.
2821 Those handlers are Tcl procedures you can provide, which are invoked
2822 at particular points in the reset sequence.
2824 @emph{When SRST is not an option} you must set
2825 up a @code{reset-assert} event handler for your target.
2826 For example, some JTAG adapters don't include the SRST signal;
2827 and some boards have multiple targets, and you won't always
2828 want to reset everything at once.
2830 After configuring those mechanisms, you might still
2831 find your board doesn't start up or reset correctly.
2832 For example, maybe it needs a slightly different sequence
2833 of SRST and/or TRST manipulations, because of quirks that
2834 the @command{reset_config} mechanism doesn't address;
2835 or asserting both might trigger a stronger reset, which
2836 needs special attention.
2838 Experiment with lower level operations, such as @command{jtag_reset}
2839 and the @command{jtag arp_*} operations shown here,
2840 to find a sequence of operations that works.
2841 @xref{JTAG Commands}.
2842 When you find a working sequence, it can be used to override
2843 @command{jtag_init}, which fires during OpenOCD startup
2844 (@pxref{Configuration Stage});
2845 or @command{init_reset}, which fires during reset processing.
2847 You might also want to provide some project-specific reset
2848 schemes. For example, on a multi-target board the standard
2849 @command{reset} command would reset all targets, but you
2850 may need the ability to reset only one target at time and
2851 thus want to avoid using the board-wide SRST signal.
2853 @deffn {Overridable Procedure} init_reset mode
2854 This is invoked near the beginning of the @command{reset} command,
2855 usually to provide as much of a cold (power-up) reset as practical.
2856 By default it is also invoked from @command{jtag_init} if
2857 the scan chain does not respond to pure JTAG operations.
2858 The @var{mode} parameter is the parameter given to the
2859 low level reset command (@option{halt},
2860 @option{init}, or @option{run}), @option{setup},
2861 or potentially some other value.
2863 The default implementation just invokes @command{jtag arp_init-reset}.
2864 Replacements will normally build on low level JTAG
2865 operations such as @command{jtag_reset}.
2866 Operations here must not address individual TAPs
2867 (or their associated targets)
2868 until the JTAG scan chain has first been verified to work.
2870 Implementations must have verified the JTAG scan chain before
2871 they return.
2872 This is done by calling @command{jtag arp_init}
2873 (or @command{jtag arp_init-reset}).
2874 @end deffn
2876 @deffn Command {jtag arp_init}
2877 This validates the scan chain using just the four
2878 standard JTAG signals (TMS, TCK, TDI, TDO).
2879 It starts by issuing a JTAG-only reset.
2880 Then it performs checks to verify that the scan chain configuration
2881 matches the TAPs it can observe.
2882 Those checks include checking IDCODE values for each active TAP,
2883 and verifying the length of their instruction registers using
2884 TAP @code{-ircapture} and @code{-irmask} values.
2885 If these tests all pass, TAP @code{setup} events are
2886 issued to all TAPs with handlers for that event.
2887 @end deffn
2889 @deffn Command {jtag arp_init-reset}
2890 This uses TRST and SRST to try resetting
2891 everything on the JTAG scan chain
2892 (and anything else connected to SRST).
2893 It then invokes the logic of @command{jtag arp_init}.
2894 @end deffn
2897 @node TAP Declaration
2898 @chapter TAP Declaration
2899 @cindex TAP declaration
2900 @cindex TAP configuration
2902 @emph{Test Access Ports} (TAPs) are the core of JTAG.
2903 TAPs serve many roles, including:
2905 @itemize @bullet
2906 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
2907 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
2908 Others do it indirectly, making a CPU do it.
2909 @item @b{Program Download} Using the same CPU support GDB uses,
2910 you can initialize a DRAM controller, download code to DRAM, and then
2911 start running that code.
2912 @item @b{Boundary Scan} Most chips support boundary scan, which
2913 helps test for board assembly problems like solder bridges
2914 and missing connections
2915 @end itemize
2917 OpenOCD must know about the active TAPs on your board(s).
2918 Setting up the TAPs is the core task of your configuration files.
2919 Once those TAPs are set up, you can pass their names to code
2920 which sets up CPUs and exports them as GDB targets,
2921 probes flash memory, performs low-level JTAG operations, and more.
2923 @section Scan Chains
2924 @cindex scan chain
2926 TAPs are part of a hardware @dfn{scan chain},
2927 which is daisy chain of TAPs.
2928 They also need to be added to
2929 OpenOCD's software mirror of that hardware list,
2930 giving each member a name and associating other data with it.
2931 Simple scan chains, with a single TAP, are common in
2932 systems with a single microcontroller or microprocessor.
2933 More complex chips may have several TAPs internally.
2934 Very complex scan chains might have a dozen or more TAPs:
2935 several in one chip, more in the next, and connecting
2936 to other boards with their own chips and TAPs.
2938 You can display the list with the @command{scan_chain} command.
2939 (Don't confuse this with the list displayed by the @command{targets}
2940 command, presented in the next chapter.
2941 That only displays TAPs for CPUs which are configured as
2942 debugging targets.)
2943 Here's what the scan chain might look like for a chip more than one TAP:
2945 @verbatim
2946 TapName Enabled IdCode Expected IrLen IrCap IrMask
2947 -- ------------------ ------- ---------- ---------- ----- ----- ------
2948 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
2949 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
2950 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
2951 @end verbatim
2953 OpenOCD can detect some of that information, but not all
2954 of it. @xref{Autoprobing}.
2955 Unfortunately those TAPs can't always be autoconfigured,
2956 because not all devices provide good support for that.
2957 JTAG doesn't require supporting IDCODE instructions, and
2958 chips with JTAG routers may not link TAPs into the chain
2959 until they are told to do so.
2961 The configuration mechanism currently supported by OpenOCD
2962 requires explicit configuration of all TAP devices using
2963 @command{jtag newtap} commands, as detailed later in this chapter.
2964 A command like this would declare one tap and name it @code{chip1.cpu}:
2966 @example
2967 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
2968 @end example
2970 Each target configuration file lists the TAPs provided
2971 by a given chip.
2972 Board configuration files combine all the targets on a board,
2973 and so forth.
2974 Note that @emph{the order in which TAPs are declared is very important.}
2975 It must match the order in the JTAG scan chain, both inside
2976 a single chip and between them.
2977 @xref{FAQ TAP Order}.
2979 For example, the ST Microsystems STR912 chip has
2980 three separate TAPs@footnote{See the ST
2981 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
2982 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
2983 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
2984 To configure those taps, @file{target/str912.cfg}
2985 includes commands something like this:
2987 @example
2988 jtag newtap str912 flash ... params ...
2989 jtag newtap str912 cpu ... params ...
2990 jtag newtap str912 bs ... params ...
2991 @end example
2993 Actual config files use a variable instead of literals like
2994 @option{str912}, to support more than one chip of each type.
2995 @xref{Config File Guidelines}.
2997 @deffn Command {jtag names}
2998 Returns the names of all current TAPs in the scan chain.
2999 Use @command{jtag cget} or @command{jtag tapisenabled}
3000 to examine attributes and state of each TAP.
3001 @example
3002 foreach t [jtag names] @{
3003 puts [format "TAP: %s\n" $t]
3004 @}
3005 @end example
3006 @end deffn
3008 @deffn Command {scan_chain}
3009 Displays the TAPs in the scan chain configuration,
3010 and their status.
3011 The set of TAPs listed by this command is fixed by
3012 exiting the OpenOCD configuration stage,
3013 but systems with a JTAG router can
3014 enable or disable TAPs dynamically.
3015 @end deffn
3017 @c FIXME! "jtag cget" should be able to return all TAP
3018 @c attributes, like "$target_name cget" does for targets.
3020 @c Probably want "jtag eventlist", and a "tap-reset" event
3021 @c (on entry to RESET state).
3023 @section TAP Names
3024 @cindex dotted name
3026 When TAP objects are declared with @command{jtag newtap},
3027 a @dfn{dotted.name} is created for the TAP, combining the
3028 name of a module (usually a chip) and a label for the TAP.
3029 For example: @code{xilinx.tap}, @code{str912.flash},
3030 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3031 Many other commands use that dotted.name to manipulate or
3032 refer to the TAP. For example, CPU configuration uses the
3033 name, as does declaration of NAND or NOR flash banks.
3035 The components of a dotted name should follow ``C'' symbol
3036 name rules: start with an alphabetic character, then numbers
3037 and underscores are OK; while others (including dots!) are not.
3039 @quotation Tip
3040 In older code, JTAG TAPs were numbered from 0..N.
3041 This feature is still present.
3042 However its use is highly discouraged, and
3043 should not be relied on; it will be removed by mid-2010.
3044 Update all of your scripts to use TAP names rather than numbers,
3045 by paying attention to the runtime warnings they trigger.
3046 Using TAP numbers in target configuration scripts prevents
3047 reusing those scripts on boards with multiple targets.
3048 @end quotation
3050 @section TAP Declaration Commands
3052 @c shouldn't this be(come) a {Config Command}?
3053 @anchor{jtag newtap}
3054 @deffn Command {jtag newtap} chipname tapname configparams...
3055 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3056 and configured according to the various @var{configparams}.
3058 The @var{chipname} is a symbolic name for the chip.
3059 Conventionally target config files use @code{$_CHIPNAME},
3060 defaulting to the model name given by the chip vendor but
3061 overridable.
3063 @cindex TAP naming convention
3064 The @var{tapname} reflects the role of that TAP,
3065 and should follow this convention:
3067 @itemize @bullet
3068 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3069 @item @code{cpu} -- The main CPU of the chip, alternatively
3070 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3071 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3072 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3073 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3074 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3075 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3076 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3077 with a single TAP;
3078 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3079 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3080 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3081 a JTAG TAP; that TAP should be named @code{sdma}.
3082 @end itemize
3084 Every TAP requires at least the following @var{configparams}:
3086 @itemize @bullet
3087 @item @code{-irlen} @var{NUMBER}
3088 @*The length in bits of the
3089 instruction register, such as 4 or 5 bits.
3090 @end itemize
3092 A TAP may also provide optional @var{configparams}:
3094 @itemize @bullet
3095 @item @code{-disable} (or @code{-enable})
3096 @*Use the @code{-disable} parameter to flag a TAP which is not
3097 linked in to the scan chain after a reset using either TRST
3098 or the JTAG state machine's @sc{reset} state.
3099 You may use @code{-enable} to highlight the default state
3100 (the TAP is linked in).
3101 @xref{Enabling and Disabling TAPs}.
3102 @item @code{-expected-id} @var{number}
3103 @*A non-zero @var{number} represents a 32-bit IDCODE
3104 which you expect to find when the scan chain is examined.
3105 These codes are not required by all JTAG devices.
3106 @emph{Repeat the option} as many times as required if more than one
3107 ID code could appear (for example, multiple versions).
3108 Specify @var{number} as zero to suppress warnings about IDCODE
3109 values that were found but not included in the list.
3111 Provide this value if at all possible, since it lets OpenOCD
3112 tell when the scan chain it sees isn't right. These values
3113 are provided in vendors' chip documentation, usually a technical
3114 reference manual. Sometimes you may need to probe the JTAG
3115 hardware to find these values.
3116 @xref{Autoprobing}.
3117 @item @code{-ignore-version}
3118 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3119 option. When vendors put out multiple versions of a chip, or use the same
3120 JTAG-level ID for several largely-compatible chips, it may be more practical
3121 to ignore the version field than to update config files to handle all of
3122 the various chip IDs.
3123 @item @code{-ircapture} @var{NUMBER}
3124 @*The bit pattern loaded by the TAP into the JTAG shift register
3125 on entry to the @sc{ircapture} state, such as 0x01.
3126 JTAG requires the two LSBs of this value to be 01.
3127 By default, @code{-ircapture} and @code{-irmask} are set
3128 up to verify that two-bit value. You may provide
3129 additional bits, if you know them, or indicate that
3130 a TAP doesn't conform to the JTAG specification.
3131 @item @code{-irmask} @var{NUMBER}
3132 @*A mask used with @code{-ircapture}
3133 to verify that instruction scans work correctly.
3134 Such scans are not used by OpenOCD except to verify that
3135 there seems to be no problems with JTAG scan chain operations.
3136 @end itemize
3137 @end deffn
3139 @section Other TAP commands
3141 @deffn Command {jtag cget} dotted.name @option{-event} name
3142 @deffnx Command {jtag configure} dotted.name @option{-event} name string
3143 At this writing this TAP attribute
3144 mechanism is used only for event handling.
3145 (It is not a direct analogue of the @code{cget}/@code{configure}
3146 mechanism for debugger targets.)
3147 See the next section for information about the available events.
3149 The @code{configure} subcommand assigns an event handler,
3150 a TCL string which is evaluated when the event is triggered.
3151 The @code{cget} subcommand returns that handler.
3152 @end deffn
3154 @anchor{TAP Events}
3155 @section TAP Events
3156 @cindex events
3157 @cindex TAP events
3159 OpenOCD includes two event mechanisms.
3160 The one presented here applies to all JTAG TAPs.
3161 The other applies to debugger targets,
3162 which are associated with certain TAPs.
3164 The TAP events currently defined are:
3166 @itemize @bullet
3167 @item @b{post-reset}
3168 @* The TAP has just completed a JTAG reset.
3169 The tap may still be in the JTAG @sc{reset} state.
3170 Handlers for these events might perform initialization sequences
3171 such as issuing TCK cycles, TMS sequences to ensure
3172 exit from the ARM SWD mode, and more.
3174 Because the scan chain has not yet been verified, handlers for these events
3175 @emph{should not issue commands which scan the JTAG IR or DR registers}
3176 of any particular target.
3177 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3178 @item @b{setup}
3179 @* The scan chain has been reset and verified.
3180 This handler may enable TAPs as needed.
3181 @item @b{tap-disable}
3182 @* The TAP needs to be disabled. This handler should
3183 implement @command{jtag tapdisable}
3184 by issuing the relevant JTAG commands.
3185 @item @b{tap-enable}
3186 @* The TAP needs to be enabled. This handler should
3187 implement @command{jtag tapenable}
3188 by issuing the relevant JTAG commands.
3189 @end itemize
3191 If you need some action after each JTAG reset, which isn't actually
3192 specific to any TAP (since you can't yet trust the scan chain's
3193 contents to be accurate), you might:
3195 @example
3196 jtag configure CHIP.jrc -event post-reset @{
3197 echo "JTAG Reset done"
3198 ... non-scan jtag operations to be done after reset
3199 @}
3200 @end example
3203 @anchor{Enabling and Disabling TAPs}
3204 @section Enabling and Disabling TAPs
3205 @cindex JTAG Route Controller
3206 @cindex jrc
3208 In some systems, a @dfn{JTAG Route Controller} (JRC)
3209 is used to enable and/or disable specific JTAG TAPs.
3210 Many ARM based chips from Texas Instruments include
3211 an ``ICEpick'' module, which is a JRC.
3212 Such chips include DaVinci and OMAP3 processors.
3214 A given TAP may not be visible until the JRC has been
3215 told to link it into the scan chain; and if the JRC
3216 has been told to unlink that TAP, it will no longer
3217 be visible.
3218 Such routers address problems that JTAG ``bypass mode''
3219 ignores, such as:
3221 @itemize
3222 @item The scan chain can only go as fast as its slowest TAP.
3223 @item Having many TAPs slows instruction scans, since all
3224 TAPs receive new instructions.
3225 @item TAPs in the scan chain must be powered up, which wastes
3226 power and prevents debugging some power management mechanisms.
3227 @end itemize
3229 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3230 as implied by the existence of JTAG routers.
3231 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3232 does include a kind of JTAG router functionality.
3234 @c (a) currently the event handlers don't seem to be able to
3235 @c fail in a way that could lead to no-change-of-state.
3237 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3238 shown below, and is implemented using TAP event handlers.
3239 So for example, when defining a TAP for a CPU connected to
3240 a JTAG router, your @file{target.cfg} file
3241 should define TAP event handlers using
3242 code that looks something like this:
3244 @example
3245 jtag configure CHIP.cpu -event tap-enable @{
3246 ... jtag operations using CHIP.jrc
3247 @}
3248 jtag configure CHIP.cpu -event tap-disable @{
3249 ... jtag operations using CHIP.jrc
3250 @}
3251 @end example
3253 Then you might want that CPU's TAP enabled almost all the time:
3255 @example
3256 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3257 @end example
3259 Note how that particular setup event handler declaration
3260 uses quotes to evaluate @code{$CHIP} when the event is configured.
3261 Using brackets @{ @} would cause it to be evaluated later,
3262 at runtime, when it might have a different value.
3264 @deffn Command {jtag tapdisable} dotted.name
3265 If necessary, disables the tap
3266 by sending it a @option{tap-disable} event.
3267 Returns the string "1" if the tap
3268 specified by @var{dotted.name} is enabled,
3269 and "0" if it is disabled.
3270 @end deffn
3272 @deffn Command {jtag tapenable} dotted.name
3273 If necessary, enables the tap
3274 by sending it a @option{tap-enable} event.
3275 Returns the string "1" if the tap
3276 specified by @var{dotted.name} is enabled,
3277 and "0" if it is disabled.
3278 @end deffn
3280 @deffn Command {jtag tapisenabled} dotted.name
3281 Returns the string "1" if the tap
3282 specified by @var{dotted.name} is enabled,
3283 and "0" if it is disabled.
3285 @quotation Note
3286 Humans will find the @command{scan_chain} command more helpful
3287 for querying the state of the JTAG taps.
3288 @end quotation
3289 @end deffn
3291 @anchor{Autoprobing}
3292 @section Autoprobing
3293 @cindex autoprobe
3294 @cindex JTAG autoprobe
3296 TAP configuration is the first thing that needs to be done
3297 after interface and reset configuration. Sometimes it's
3298 hard finding out what TAPs exist, or how they are identified.
3299 Vendor documentation is not always easy to find and use.
3301 To help you get past such problems, OpenOCD has a limited
3302 @emph{autoprobing} ability to look at the scan chain, doing
3303 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3304 To use this mechanism, start the OpenOCD server with only data
3305 that configures your JTAG interface, and arranges to come up
3306 with a slow clock (many devices don't support fast JTAG clocks
3307 right when they come out of reset).
3309 For example, your @file{openocd.cfg} file might have:
3311 @example
3312 source [find interface/olimex-arm-usb-tiny-h.cfg]
3313 reset_config trst_and_srst
3314 jtag_rclk 8
3315 @end example
3317 When you start the server without any TAPs configured, it will
3318 attempt to autoconfigure the TAPs. There are two parts to this:
3320 @enumerate
3321 @item @emph{TAP discovery} ...
3322 After a JTAG reset (sometimes a system reset may be needed too),
3323 each TAP's data registers will hold the contents of either the
3324 IDCODE or BYPASS register.
3325 If JTAG communication is working, OpenOCD will see each TAP,
3326 and report what @option{-expected-id} to use with it.
3327 @item @emph{IR Length discovery} ...
3328 Unfortunately JTAG does not provide a reliable way to find out
3329 the value of the @option{-irlen} parameter to use with a TAP
3330 that is discovered.
3331 If OpenOCD can discover the length of a TAP's instruction
3332 register, it will report it.
3333 Otherwise you may need to consult vendor documentation, such
3334 as chip data sheets or BSDL files.
3335 @end enumerate
3337 In many cases your board will have a simple scan chain with just
3338 a single device. Here's what OpenOCD reported with one board
3339 that's a bit more complex:
3341 @example
3342 clock speed 8 kHz
3343 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3344 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3345 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3346 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3347 AUTO auto0.tap - use "... -irlen 4"
3348 AUTO auto1.tap - use "... -irlen 4"
3349 AUTO auto2.tap - use "... -irlen 6"
3350 no gdb ports allocated as no target has been specified
3351 @end example
3353 Given that information, you should be able to either find some existing
3354 config files to use, or create your own. If you create your own, you
3355 would configure from the bottom up: first a @file{target.cfg} file
3356 with these TAPs, any targets associated with them, and any on-chip
3357 resources; then a @file{board.cfg} with off-chip resources, clocking,
3358 and so forth.
3360 @node CPU Configuration
3361 @chapter CPU Configuration
3362 @cindex GDB target
3364 This chapter discusses how to set up GDB debug targets for CPUs.
3365 You can also access these targets without GDB
3366 (@pxref{Architecture and Core Commands},
3367 and @ref{Target State handling}) and
3368 through various kinds of NAND and NOR flash commands.
3369 If you have multiple CPUs you can have multiple such targets.
3371 We'll start by looking at how to examine the targets you have,
3372 then look at how to add one more target and how to configure it.
3374 @section Target List
3375 @cindex target, current
3376 @cindex target, list
3378 All targets that have been set up are part of a list,
3379 where each member has a name.
3380 That name should normally be the same as the TAP name.
3381 You can display the list with the @command{targets}
3382 (plural!) command.
3383 This display often has only one CPU; here's what it might
3384 look like with more than one:
3385 @verbatim
3386 TargetName Type Endian TapName State
3387 -- ------------------ ---------- ------ ------------------ ------------
3388 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
3389 1 MyTarget cortex_m3 little mychip.foo tap-disabled
3390 @end verbatim
3392 One member of that list is the @dfn{current target}, which
3393 is implicitly referenced by many commands.
3394 It's the one marked with a @code{*} near the target name.
3395 In particular, memory addresses often refer to the address
3396 space seen by that current target.
3397 Commands like @command{mdw} (memory display words)
3398 and @command{flash erase_address} (erase NOR flash blocks)
3399 are examples; and there are many more.
3401 Several commands let you examine the list of targets:
3403 @deffn Command {target count}
3404 @emph{Note: target numbers are deprecated; don't use them.
3405 They will be removed shortly after August 2010, including this command.
3406 Iterate target using @command{target names}, not by counting.}
3408 Returns the number of targets, @math{N}.
3409 The highest numbered target is @math{N - 1}.
3410 @example
3411 set c [target count]
3412 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
3413 # Assuming you have created this function
3414 print_target_details $x
3415 @}
3416 @end example
3417 @end deffn
3419 @deffn Command {target current}
3420 Returns the name of the current target.
3421 @end deffn
3423 @deffn Command {target names}
3424 Lists the names of all current targets in the list.
3425 @example
3426 foreach t [target names] @{
3427 puts [format "Target: %s\n" $t]
3428 @}
3429 @end example
3430 @end deffn
3432 @deffn Command {target number} number
3433 @emph{Note: target numbers are deprecated; don't use them.
3434 They will be removed shortly after August 2010, including this command.}
3436 The list of targets is numbered starting at zero.
3437 This command returns the name of the target at index @var{number}.
3438 @example
3439 set thename [target number $x]
3440 puts [format "Target %d is: %s\n" $x $thename]
3441 @end example
3442 @end deffn
3444 @c yep, "target list" would have been better.
3445 @c plus maybe "target setdefault".
3447 @deffn Command targets [name]
3448 @emph{Note: the name of this command is plural. Other target
3449 command names are singular.}
3451 With no parameter, this command displays a table of all known
3452 targets in a user friendly form.
3454 With a parameter, this command sets the current target to
3455 the given target with the given @var{name}; this is
3456 only relevant on boards which have more than one target.
3457 @end deffn
3459 @section Target CPU Types and Variants
3460 @cindex target type
3461 @cindex CPU type
3462 @cindex CPU variant
3464 Each target has a @dfn{CPU type}, as shown in the output of
3465 the @command{targets} command. You need to specify that type
3466 when calling @command{target create}.
3467 The CPU type indicates more than just the instruction set.
3468 It also indicates how that instruction set is implemented,
3469 what kind of debug support it integrates,
3470 whether it has an MMU (and if so, what kind),
3471 what core-specific commands may be available
3472 (@pxref{Architecture and Core Commands}),
3473 and more.
3475 For some CPU types, OpenOCD also defines @dfn{variants} which
3476 indicate differences that affect their handling.
3477 For example, a particular implementation bug might need to be
3478 worked around in some chip versions.
3480 It's easy to see what target types are supported,
3481 since there's a command to list them.
3482 However, there is currently no way to list what target variants
3483 are supported (other than by reading the OpenOCD source code).
3485 @anchor{target types}
3486 @deffn Command {target types}
3487 Lists all supported target types.
3488 At this writing, the supported CPU types and variants are:
3490 @itemize @bullet
3491 @item @code{arm11} -- this is a generation of ARMv6 cores
3492 @item @code{arm720t} -- this is an ARMv4 core with an MMU
3493 @item @code{arm7tdmi} -- this is an ARMv4 core
3494 @item @code{arm920t} -- this is an ARMv4 core with an MMU
3495 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
3496 @item @code{arm966e} -- this is an ARMv5 core
3497 @item @code{arm9tdmi} -- this is an ARMv4 core
3498 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
3499 (Support for this is preliminary and incomplete.)
3500 @item @code{cortex_a8} -- this is an ARMv7 core with an MMU
3501 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
3502 compact Thumb2 instruction set. It supports one variant:
3503 @itemize @minus
3504 @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
3505 This will cause OpenOCD to use a software reset rather than asserting
3506 SRST, to avoid a issue with clearing the debug registers.
3507 This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
3508 be detected and the normal reset behaviour used.
3509 @end itemize
3510 @item @code{dragonite} -- resembles arm966e
3511 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
3512 (Support for this is still incomplete.)
3513 @item @code{fa526} -- resembles arm920 (w/o Thumb)
3514 @item @code{feroceon} -- resembles arm926
3515 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
3516 @item @code{xscale} -- this is actually an architecture,
3517 not a CPU type. It is based on the ARMv5 architecture.
3518 There are several variants defined:
3519 @itemize @minus
3520 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
3521 @code{pxa27x} ... instruction register length is 7 bits
3522 @item @code{pxa250}, @code{pxa255},
3523 @code{pxa26x} ... instruction register length is 5 bits
3524 @item @code{pxa3xx} ... instruction register length is 11 bits
3525 @end itemize
3526 @end itemize
3527 @end deffn
3529 To avoid being confused by the variety of ARM based cores, remember
3530 this key point: @emph{ARM is a technology licencing company}.
3531 (See: @url{http://www.arm.com}.)
3532 The CPU name used by OpenOCD will reflect the CPU design that was
3533 licenced, not a vendor brand which incorporates that design.
3534 Name prefixes like arm7, arm9, arm11, and cortex
3535 reflect design generations;
3536 while names like ARMv4, ARMv5, ARMv6, and ARMv7
3537 reflect an architecture version implemented by a CPU design.
3539 @anchor{Target Configuration}
3540 @section Target Configuration
3542 Before creating a ``target'', you must have added its TAP to the scan chain.
3543 When you've added that TAP, you will have a @code{dotted.name}
3544 which is used to set up the CPU support.
3545 The chip-specific configuration file will normally configure its CPU(s)
3546 right after it adds all of the chip's TAPs to the scan chain.
3548 Although you can set up a target in one step, it's often clearer if you
3549 use shorter commands and do it in two steps: create it, then configure
3550 optional parts.
3551 All operations on the target after it's created will use a new
3552 command, created as part of target creation.
3554 The two main things to configure after target creation are
3555 a work area, which usually has target-specific defaults even
3556 if the board setup code overrides them later;
3557 and event handlers (@pxref{Target Events}), which tend
3558 to be much more board-specific.
3559 The key steps you use might look something like this
3561 @example
3562 target create MyTarget cortex_m3 -chain-position mychip.cpu
3563 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
3564 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
3565 $MyTarget configure -event reset-init @{ myboard_reinit @}
3566 @end example
3568 You should specify a working area if you can; typically it uses some
3569 on-chip SRAM.
3570 Such a working area can speed up many things, including bulk
3571 writes to target memory;
3572 flash operations like checking to see if memory needs to be erased;
3573 GDB memory checksumming;
3574 and more.
3576 @quotation Warning
3577 On more complex chips, the work area can become
3578 inaccessible when application code
3579 (such as an operating system)
3580 enables or disables the MMU.
3581 For example, the particular MMU context used to acess the virtual
3582 address will probably matter ... and that context might not have
3583 easy access to other addresses needed.
3584 At this writing, OpenOCD doesn't have much MMU intelligence.
3585 @end quotation
3587 It's often very useful to define a @code{reset-init} event handler.
3588 For systems that are normally used with a boot loader,
3589 common tasks include updating clocks and initializing memory
3590 controllers.
3591 That may be needed to let you write the boot loader into flash,
3592 in order to ``de-brick'' your board; or to load programs into
3593 external DDR memory without having run the boot loader.
3595 @deffn Command {target create} target_name type configparams...
3596 This command creates a GDB debug target that refers to a specific JTAG tap.
3597 It enters that target into a list, and creates a new
3598 command (@command{@var{target_name}}) which is used for various
3599 purposes including additional configuration.
3601 @itemize @bullet
3602 @item @var{target_name} ... is the name of the debug target.
3603 By convention this should be the same as the @emph{dotted.name}
3604 of the TAP associated with this target, which must be specified here
3605 using the @code{-chain-position @var{dotted.name}} configparam.
3607 This name is also used to create the target object command,
3608 referred to here as @command{$target_name},
3609 and in other places the target needs to be identified.
3610 @item @var{type} ... specifies the target type. @xref{target types}.
3611 @item @var{configparams} ... all parameters accepted by
3612 @command{$target_name configure} are permitted.
3613 If the target is big-endian, set it here with @code{-endian big}.
3614 If the variant matters, set it here with @code{-variant}.
3616 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
3617 @end itemize
3618 @end deffn
3620 @deffn Command {$target_name configure} configparams...
3621 The options accepted by this command may also be
3622 specified as parameters to @command{target create}.
3623 Their values can later be queried one at a time by
3624 using the @command{$target_name cget} command.
3626 @emph{Warning:} changing some of these after setup is dangerous.
3627 For example, moving a target from one TAP to another;
3628 and changing its endianness or variant.
3630 @itemize @bullet
3632 @item @code{-chain-position} @var{dotted.name} -- names the TAP
3633 used to access this target.
3635 @item @code{-endian} (@option{big}|@option{little}) -- specifies
3636 whether the CPU uses big or little endian conventions
3638 @item @code{-event} @var{event_name} @var{event_body} --
3639 @xref{Target Events}.
3640 Note that this updates a list of named event handlers.
3641 Calling this twice with two different event names assigns
3642 two different handlers, but calling it twice with the
3643 same event name assigns only one handler.
3645 @item @code{-variant} @var{name} -- specifies a variant of the target,
3646 which OpenOCD needs to know about.
3648 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
3649 whether the work area gets backed up; by default,
3650 @emph{it is not backed up.}
3651 When possible, use a working_area that doesn't need to be backed up,
3652 since performing a backup slows down operations.
3653 For example, the beginning of an SRAM block is likely to
3654 be used by most build systems, but the end is often unused.
3656 @item @code{-work-area-size} @var{size} -- specify work are size,
3657 in bytes. The same size applies regardless of whether its physical
3658 or virtual address is being used.
3660 @item @code{-work-area-phys} @var{address} -- set the work area
3661 base @var{address} to be used when no MMU is active.
3663 @item @code{-work-area-virt} @var{address} -- set the work area
3664 base @var{address} to be used when an MMU is active.
3665 @emph{Do not specify a value for this except on targets with an MMU.}
3666 The value should normally correspond to a static mapping for the
3667 @code{-work-area-phys} address, set up by the current operating system.
3669 @end itemize
3670 @end deffn
3672 @section Other $target_name Commands
3673 @cindex object command
3675 The Tcl/Tk language has the concept of object commands,
3676 and OpenOCD adopts that same model for targets.
3678 A good Tk example is a on screen button.
3679 Once a button is created a button
3680 has a name (a path in Tk terms) and that name is useable as a first
3681 class command. For example in Tk, one can create a button and later
3682 configure it like this:
3684 @example
3685 # Create
3686 button .foobar -background red -command @{ foo @}
3687 # Modify
3688 .foobar configure -foreground blue
3689 # Query
3690 set x [.foobar cget -background]
3691 # Report
3692 puts [format "The button is %s" $x]
3693 @end example
3695 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
3696 button, and its object commands are invoked the same way.
3698 @example
3699 str912.cpu mww 0x1234 0x42
3700 omap3530.cpu mww 0x5555 123
3701 @end example
3703 The commands supported by OpenOCD target objects are:
3705 @deffn Command {$target_name arp_examine}
3706 @deffnx Command {$target_name arp_halt}
3707 @deffnx Command {$target_name arp_poll}
3708 @deffnx Command {$target_name arp_reset}
3709 @deffnx Command {$target_name arp_waitstate}
3710 Internal OpenOCD scripts (most notably @file{startup.tcl})
3711 use these to deal with specific reset cases.
3712 They are not otherwise documented here.
3713 @end deffn
3715 @deffn Command {$target_name array2mem} arrayname width address count
3716 @deffnx Command {$target_name mem2array} arrayname width address count
3717 These provide an efficient script-oriented interface to memory.
3718 The @code{array2mem} primitive writes bytes, halfwords, or words;
3719 while @code{mem2array} reads them.
3720 In both cases, the TCL side uses an array, and
3721 the target side uses raw memory.
3723 The efficiency comes from enabling the use of
3724 bulk JTAG data transfer operations.
3725 The script orientation comes from working with data
3726 values that are packaged for use by TCL scripts;
3727 @command{mdw} type primitives only print data they retrieve,
3728 and neither store nor return those values.
3730 @itemize
3731 @item @var{arrayname} ... is the name of an array variable
3732 @item @var{width} ... is 8/16/32 - indicating the memory access size
3733 @item @var{address} ... is the target memory address
3734 @item @var{count} ... is the number of elements to process
3735 @end itemize
3736 @end deffn
3738 @deffn Command {$target_name cget} queryparm
3739 Each configuration parameter accepted by
3740 @command{$target_name configure}
3741 can be individually queried, to return its current value.
3742 The @var{queryparm} is a parameter name
3743 accepted by that command, such as @code{-work-area-phys}.
3744 There are a few special cases:
3746 @itemize @bullet
3747 @item @code{-event} @var{event_name} -- returns the handler for the
3748 event named @var{event_name}.
3749 This is a special case because setting a handler requires
3750 two parameters.
3751 @item @code{-type} -- returns the target type.
3752 This is a special case because this is set using
3753 @command{target create} and can't be changed
3754 using @command{$target_name configure}.
3755 @end itemize
3757 For example, if you wanted to summarize information about
3758 all the targets you might use something like this:
3760 @example
3761 foreach name [target names] @{
3762 set y [$name cget -endian]
3763 set z [$name cget -type]
3764 puts [format "Chip %d is %s, Endian: %s, type: %s" \
3765 $x $name $y $z]
3766 @}
3767 @end example
3768 @end deffn
3770 @anchor{target curstate}
3771 @deffn Command {$target_name curstate}
3772 Displays the current target state:
3773 @code{debug-running},
3774 @code{halted},
3775 @code{reset},
3776 @code{running}, or @code{unknown}.
3777 (Also, @pxref{Event Polling}.)
3778 @end deffn
3780 @deffn Command {$target_name eventlist}
3781 Displays a table listing all event handlers
3782 currently associated with this target.
3783 @xref{Target Events}.
3784 @end deffn
3786 @deffn Command {$target_name invoke-event} event_name
3787 Invokes the handler for the event named @var{event_name}.
3788 (This is primarily intended for use by OpenOCD framework
3789 code, for example by the reset code in @file{startup.tcl}.)
3790 @end deffn
3792 @deffn Command {$target_name mdw} addr [count]
3793 @deffnx Command {$target_name mdh} addr [count]
3794 @deffnx Command {$target_name mdb} addr [count]
3795 Display contents of address @var{addr}, as
3796 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
3797 or 8-bit bytes (@command{mdb}).
3798 If @var{count} is specified, displays that many units.
3799 (If you want to manipulate the data instead of displaying it,
3800 see the @code{mem2array} primitives.)
3801 @end deffn
3803 @deffn Command {$target_name mww} addr word
3804 @deffnx Command {$target_name mwh} addr halfword
3805 @deffnx Command {$target_name mwb} addr byte
3806 Writes the specified @var{word} (32 bits),
3807 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3808 at the specified address @var{addr}.
3809 @end deffn
3811 @anchor{Target Events}
3812 @section Target Events
3813 @cindex target events
3814 @cindex events
3815 At various times, certain things can happen, or you want them to happen.
3816 For example:
3817 @itemize @bullet
3818 @item What should happen when GDB connects? Should your target reset?
3819 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
3820 @item Is using SRST appropriate (and possible) on your system?
3821 Or instead of that, do you need to issue JTAG commands to trigger reset?
3822 SRST usually resets everything on the scan chain, which can be inappropriate.
3823 @item During reset, do you need to write to certain memory locations
3824 to set up system clocks or
3825 to reconfigure the SDRAM?
3826 How about configuring the watchdog timer, or other peripherals,
3827 to stop running while you hold the core stopped for debugging?
3828 @end itemize
3830 All of the above items can be addressed by target event handlers.
3831 These are set up by @command{$target_name configure -event} or
3832 @command{target create ... -event}.
3834 The programmer's model matches the @code{-command} option used in Tcl/Tk
3835 buttons and events. The two examples below act the same, but one creates
3836 and invokes a small procedure while the other inlines it.
3838 @example
3839 proc my_attach_proc @{ @} @{
3840 echo "Reset..."
3841 reset halt
3842 @}
3843 mychip.cpu configure -event gdb-attach my_attach_proc
3844 mychip.cpu configure -event gdb-attach @{
3845 echo "Reset..."
3846 # To make flash probe and gdb load to flash work we need a reset init.
3847 reset init
3848 @}
3849 @end example
3851 The following target events are defined:
3853 @itemize @bullet
3854 @item @b{debug-halted}
3855 @* The target has halted for debug reasons (i.e.: breakpoint)
3856 @item @b{debug-resumed}
3857 @* The target has resumed (i.e.: gdb said run)
3858 @item @b{early-halted}
3859 @* Occurs early in the halt process
3860 @ignore
3861 @item @b{examine-end}
3862 @* Currently not used (goal: when JTAG examine completes)
3863 @item @b{examine-start}
3864 @* Currently not used (goal: when JTAG examine starts)
3865 @end ignore
3866 @item @b{gdb-attach}
3867 @* When GDB connects. This is before any communication with the target, so this
3868 can be used to set up the target so it is possible to probe flash. Probing flash
3869 is necessary during gdb connect if gdb load is to write the image to flash. Another
3870 use of the flash memory map is for GDB to automatically hardware/software breakpoints
3871 depending on whether the breakpoint is in RAM or read only memory.
3872 @item @b{gdb-detach}
3873 @* When GDB disconnects
3874 @item @b{gdb-end}
3875 @* When the target has halted and GDB is not doing anything (see early halt)
3876 @item @b{gdb-flash-erase-start}
3877 @* Before the GDB flash process tries to erase the flash
3878 @item @b{gdb-flash-erase-end}
3879 @* After the GDB flash process has finished erasing the flash
3880 @item @b{gdb-flash-write-start}
3881 @* Before GDB writes to the flash
3882 @item @b{gdb-flash-write-end}
3883 @* After GDB writes to the flash
3884 @item @b{gdb-start}
3885 @* Before the target steps, gdb is trying to start/resume the target
3886 @item @b{halted}
3887 @* The target has halted
3888 @ignore
3889 @item @b{old-gdb_program_config}
3890 @* DO NOT USE THIS: Used internally
3891 @item @b{old-pre_resume}
3892 @* DO NOT USE THIS: Used internally
3893 @end ignore
3894 @item @b{reset-assert-pre}
3895 @* Issued as part of @command{reset} processing
3896 after @command{reset_init} was triggered
3897 but before either SRST alone is re-asserted on the scan chain,
3898 or @code{reset-assert} is triggered.
3899 @item @b{reset-assert}
3900 @* Issued as part of @command{reset} processing
3901 after @command{reset-assert-pre} was triggered.
3902 When such a handler is present, cores which support this event will use
3903 it instead of asserting SRST.
3904 This support is essential for debugging with JTAG interfaces which
3905 don't include an SRST line (JTAG doesn't require SRST), and for
3906 selective reset on scan chains that have multiple targets.
3907 @item @b{reset-assert-post}
3908 @* Issued as part of @command{reset} processing
3909 after @code{reset-assert} has been triggered.
3910 or the target asserted SRST on the entire scan chain.
3911 @item @b{reset-deassert-pre}
3912 @* Issued as part of @command{reset} processing
3913 after @code{reset-assert-post} has been triggered.
3914 @item @b{reset-deassert-post}
3915 @* Issued as part of @command{reset} processing
3916 after @code{reset-deassert-pre} has been triggered
3917 and (if the target is using it) after SRST has been
3918 released on the scan chain.
3919 @item @b{reset-end}
3920 @* Issued as the final step in @command{reset} processing.
3921 @ignore
3922 @item @b{reset-halt-post}
3923 @* Currently not used
3924 @item @b{reset-halt-pre}
3925 @* Currently not used
3926 @end ignore
3927 @item @b{reset-init}
3928 @* Used by @b{reset init} command for board-specific initialization.
3929 This event fires after @emph{reset-deassert-post}.
3931 This is where you would configure PLLs and clocking, set up DRAM so
3932 you can download programs that don't fit in on-chip SRAM, set up pin
3933 multiplexing, and so on.
3934 (You may be able to switch to a fast JTAG clock rate here, after
3935 the target clocks are fully set up.)
3936 @item @b{reset-start}
3937 @* Issued as part of @command{reset} processing
3938 before @command{reset_init} is called.
3940 This is the most robust place to use @command{jtag_rclk}
3941 or @command{adapter_khz} to switch to a low JTAG clock rate,
3942 when reset disables PLLs needed to use a fast clock.
3943 @ignore
3944 @item @b{reset-wait-pos}
3945 @* Currently not used
3946 @item @b{reset-wait-pre}
3947 @* Currently not used
3948 @end ignore
3949 @item @b{resume-start}
3950 @* Before any target is resumed
3951 @item @b{resume-end}
3952 @* After all targets have resumed
3953 @item @b{resume-ok}
3954 @* Success
3955 @item @b{resumed}
3956 @* Target has resumed
3957 @end itemize
3960 @node Flash Commands
3961 @chapter Flash Commands
3963 OpenOCD has different commands for NOR and NAND flash;
3964 the ``flash'' command works with NOR flash, while
3965 the ``nand'' command works with NAND flash.
3966 This partially reflects different hardware technologies:
3967 NOR flash usually supports direct CPU instruction and data bus access,
3968 while data from a NAND flash must be copied to memory before it can be
3969 used. (SPI flash must also be copied to memory before use.)
3970 However, the documentation also uses ``flash'' as a generic term;
3971 for example, ``Put flash configuration in board-specific files''.
3973 Flash Steps:
3974 @enumerate
3975 @item Configure via the command @command{flash bank}
3976 @* Do this in a board-specific configuration file,
3977 passing parameters as needed by the driver.
3978 @item Operate on the flash via @command{flash subcommand}
3979 @* Often commands to manipulate the flash are typed by a human, or run
3980 via a script in some automated way. Common tasks include writing a
3981 boot loader, operating system, or other data.
3982 @item GDB Flashing
3983 @* Flashing via GDB requires the flash be configured via ``flash
3984 bank'', and the GDB flash features be enabled.
3985 @xref{GDB Configuration}.
3986 @end enumerate
3988 Many CPUs have the ablity to ``boot'' from the first flash bank.
3989 This means that misprogramming that bank can ``brick'' a system,
3990 so that it can't boot.
3991 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
3992 board by (re)installing working boot firmware.
3994 @anchor{NOR Configuration}
3995 @section Flash Configuration Commands
3996 @cindex flash configuration
3998 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
3999 Configures a flash bank which provides persistent storage
4000 for addresses from @math{base} to @math{base + size - 1}.
4001 These banks will often be visible to GDB through the target's memory map.
4002 In some cases, configuring a flash bank will activate extra commands;
4003 see the driver-specific documentation.
4005 @itemize @bullet
4006 @item @var{name} ... may be used to reference the flash bank
4007 in other flash commands. A number is also available.
4008 @item @var{driver} ... identifies the controller driver
4009 associated with the flash bank being declared.
4010 This is usually @code{cfi} for external flash, or else
4011 the name of a microcontroller with embedded flash memory.
4012 @xref{Flash Driver List}.
4013 @item @var{base} ... Base address of the flash chip.
4014 @item @var{size} ... Size of the chip, in bytes.
4015 For some drivers, this value is detected from the hardware.
4016 @item @var{chip_width} ... Width of the flash chip, in bytes;
4017 ignored for most microcontroller drivers.
4018 @item @var{bus_width} ... Width of the data bus used to access the
4019 chip, in bytes; ignored for most microcontroller drivers.
4020 @item @var{target} ... Names the target used to issue
4021 commands to the flash controller.
4022 @comment Actually, it's currently a controller-specific parameter...
4023 @item @var{driver_options} ... drivers may support, or require,
4024 additional parameters. See the driver-specific documentation
4025 for more information.
4026 @end itemize
4027 @quotation Note
4028 This command is not available after OpenOCD initialization has completed.
4029 Use it in board specific configuration files, not interactively.
4030 @end quotation
4031 @end deffn
4033 @comment the REAL name for this command is "ocd_flash_banks"
4034 @comment less confusing would be: "flash list" (like "nand list")
4035 @deffn Command {flash banks}
4036 Prints a one-line summary of each device that was
4037 declared using @command{flash bank}, numbered from zero.
4038 Note that this is the @emph{plural} form;
4039 the @emph{singular} form is a very different command.
4040 @end deffn
4042 @deffn Command {flash list}
4043 Retrieves a list of associative arrays for each device that was
4044 declared using @command{flash bank}, numbered from zero.
4045 This returned list can be manipulated easily from within scripts.
4046 @end deffn
4048 @deffn Command {flash probe} num
4049 Identify the flash, or validate the parameters of the configured flash. Operation
4050 depends on the flash type.
4051 The @var{num} parameter is a value shown by @command{flash banks}.
4052 Most flash commands will implicitly @emph{autoprobe} the bank;
4053 flash drivers can distinguish between probing and autoprobing,
4054 but most don't bother.
4055 @end deffn
4057 @section Erasing, Reading, Writing to Flash
4058 @cindex flash erasing
4059 @cindex flash reading
4060 @cindex flash writing
4061 @cindex flash programming
4063 One feature distinguishing NOR flash from NAND or serial flash technologies
4064 is that for read access, it acts exactly like any other addressible memory.
4065 This means you can use normal memory read commands like @command{mdw} or
4066 @command{dump_image} with it, with no special @command{flash} subcommands.
4067 @xref{Memory access}, and @ref{Image access}.
4069 Write access works differently. Flash memory normally needs to be erased
4070 before it's written. Erasing a sector turns all of its bits to ones, and
4071 writing can turn ones into zeroes. This is why there are special commands
4072 for interactive erasing and writing, and why GDB needs to know which parts
4073 of the address space hold NOR flash memory.
4075 @quotation Note
4076 Most of these erase and write commands leverage the fact that NOR flash
4077 chips consume target address space. They implicitly refer to the current
4078 JTAG target, and map from an address in that target's address space
4079 back to a flash bank.
4080 @comment In May 2009, those mappings may fail if any bank associated
4081 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
4082 A few commands use abstract addressing based on bank and sector numbers,
4083 and don't depend on searching the current target and its address space.
4084 Avoid confusing the two command models.
4085 @end quotation
4087 Some flash chips implement software protection against accidental writes,
4088 since such buggy writes could in some cases ``brick'' a system.
4089 For such systems, erasing and writing may require sector protection to be
4090 disabled first.
4091 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4092 and AT91SAM7 on-chip flash.
4093 @xref{flash protect}.
4095 @anchor{flash erase_sector}
4096 @deffn Command {flash erase_sector} num first last
4097 Erase sectors in bank @var{num}, starting at sector @var{first}
4098 up to and including @var{last}.
4099 Sector numbering starts at 0.
4100 Providing a @var{last} sector of @option{last}
4101 specifies "to the end of the flash bank".
4102 The @var{num} parameter is a value shown by @command{flash banks}.
4103 @end deffn
4105 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4106 Erase sectors starting at @var{address} for @var{length} bytes.
4107 Unless @option{pad} is specified, @math{address} must begin a
4108 flash sector, and @math{address + length - 1} must end a sector.
4109 Specifying @option{pad} erases extra data at the beginning and/or
4110 end of the specified region, as needed to erase only full sectors.
4111 The flash bank to use is inferred from the @var{address}, and
4112 the specified length must stay within that bank.
4113 As a special case, when @var{length} is zero and @var{address} is
4114 the start of the bank, the whole flash is erased.
4115 If @option{unlock} is specified, then the flash is unprotected
4116 before erase starts.
4117 @end deffn
4119 @deffn Command {flash fillw} address word length
4120 @deffnx Command {flash fillh} address halfword length
4121 @deffnx Command {flash fillb} address byte length
4122 Fills flash memory with the specified @var{word} (32 bits),
4123 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4124 starting at @var{address} and continuing
4125 for @var{length} units (word/halfword/byte).
4126 No erasure is done before writing; when needed, that must be done
4127 before issuing this command.
4128 Writes are done in blocks of up to 1024 bytes, and each write is
4129 verified by reading back the data and comparing it to what was written.
4130 The flash bank to use is inferred from the @var{address} of
4131 each block, and the specified length must stay within that bank.
4132 @end deffn
4133 @comment no current checks for errors if fill blocks touch multiple banks!
4135 @anchor{flash write_bank}
4136 @deffn Command {flash write_bank} num filename offset
4137 Write the binary @file{filename} to flash bank @var{num},
4138 starting at @var{offset} bytes from the beginning of the bank.
4139 The @var{num} parameter is a value shown by @command{flash banks}.
4140 @end deffn
4142 @anchor{flash write_image}
4143 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4144 Write the image @file{filename} to the current target's flash bank(s).
4145 A relocation @var{offset} may be specified, in which case it is added
4146 to the base address for each section in the image.
4147 The file [@var{type}] can be specified
4148 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4149 @option{elf} (ELF file), @option{s19} (Motorola s19).
4150 @option{mem}, or @option{builder}.
4151 The relevant flash sectors will be erased prior to programming
4152 if the @option{erase} parameter is given. If @option{unlock} is
4153 provided, then the flash banks are unlocked before erase and
4154 program. The flash bank to use is inferred from the address of
4155 each image section.
4157 @quotation Warning
4158 Be careful using the @option{erase} flag when the flash is holding
4159 data you want to preserve.
4160 Portions of the flash outside those described in the image's
4161 sections might be erased with no notice.
4162 @itemize
4163 @item
4164 When a section of the image being written does not fill out all the
4165 sectors it uses, the unwritten parts of those sectors are necessarily
4166 also erased, because sectors can't be partially erased.
4167 @item
4168 Data stored in sector "holes" between image sections are also affected.
4169 For example, "@command{flash write_image erase ...}" of an image with
4170 one byte at the beginning of a flash bank and one byte at the end
4171 erases the entire bank -- not just the two sectors being written.
4172 @end itemize
4173 Also, when flash protection is important, you must re-apply it after
4174 it has been removed by the @option{unlock} flag.
4175 @end quotation
4177 @end deffn
4179 @section Other Flash commands
4180 @cindex flash protection
4182 @deffn Command {flash erase_check} num
4183 Check erase state of sectors in flash bank @var{num},
4184 and display that status.