[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
82 * TFTP:: TFTP
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
95 @end menu
97 @node About
98 @unnumbered About
99 @cindex about
101 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
102 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
105 around the world.
107 @section What is OpenOCD?
108 @cindex TAP
109 @cindex JTAG
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
113 devices.
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board connect directly to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
140 scan operations.
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD supports only
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
154 USB-based, parallel port-based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
159 (Stellaris LM3, ST STM32 and Energy Micro EFM32) and Intel Quark (x10xx)
160 based cores to be debugged via the GDB protocol.
162 @b{Flash Programming:} Flash writing is supported for external
163 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{http://openocd.org/}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{http://openocd.org/doc/html/index.html}
182 PDF form is likewise published at:
184 @uref{http://openocd.org/doc/pdf/openocd.pdf}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
203 @section OpenOCD IRC
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
208 @node Developers
209 @chapter OpenOCD Developer Resources
210 @cindex developers
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD Git Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a Git repository hosted at SourceForge. The repository URL is:
225 @uref{git://git.code.sf.net/p/openocd/code}
227 or via http
229 @uref{http://git.code.sf.net/p/openocd/code}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{http://repo.or.cz/r/openocd.git}
235 With standard Git tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a Git client:
241 @uref{http://repo.or.cz/w/openocd.git}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{http://openocd.org/doc/doxygen/html/index.html}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration at the top of the source tree.
264 @section Gerrit Review System
266 All changes in the OpenOCD Git repository go through the web-based Gerrit
267 Code Review System:
269 @uref{http://openocd.zylin.com/}
271 After a one-time registration and repository setup, anyone can push commits
272 from their local Git repository directly into Gerrit.
273 All users and developers are encouraged to review, test, discuss and vote
274 for changes in Gerrit. The feedback provides the basis for a maintainer to
275 eventually submit the change to the main Git repository.
277 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
278 Developer Manual, contains basic information about how to connect a
279 repository to Gerrit, prepare and push patches. Patch authors are expected to
280 maintain their changes while they're in Gerrit, respond to feedback and if
281 necessary rework and push improved versions of the change.
283 @section OpenOCD Developer Mailing List
285 The OpenOCD Developer Mailing List provides the primary means of
286 communication between developers:
288 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
290 @section OpenOCD Bug Tracker
292 The OpenOCD Bug Tracker is hosted on SourceForge:
294 @uref{http://bugs.openocd.org/}
297 @node Debug Adapter Hardware
298 @chapter Debug Adapter Hardware
299 @cindex dongles
300 @cindex FTDI
301 @cindex wiggler
302 @cindex zy1000
303 @cindex printer port
304 @cindex USB Adapter
305 @cindex RTCK
307 Defined: @b{dongle}: A small device that plugs into a computer and serves as
308 an adapter .... [snip]
310 In the OpenOCD case, this generally refers to @b{a small adapter} that
311 attaches to your computer via USB or the parallel port. One
312 exception is the Ultimate Solutions ZY1000, packaged as a small box you
313 attach via an ethernet cable. The ZY1000 has the advantage that it does not
314 require any drivers to be installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built-in relay to power cycle targets remotely.
319 @section Choosing a Dongle
321 There are several things you should keep in mind when choosing a dongle.
323 @enumerate
324 @item @b{Transport} Does it support the kind of communication that you need?
325 OpenOCD focusses mostly on JTAG. Your version may also support
326 other ways to communicate with target devices.
327 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
328 Does your dongle support it? You might need a level converter.
329 @item @b{Pinout} What pinout does your target board use?
330 Does your dongle support it? You may be able to use jumper
331 wires, or an "octopus" connector, to convert pinouts.
332 @item @b{Connection} Does your computer have the USB, parallel, or
333 Ethernet port needed?
334 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
335 RTCK support (also known as ``adaptive clocking'')?
336 @end enumerate
338 @section Stand-alone JTAG Probe
340 The ZY1000 from Ultimate Solutions is technically not a dongle but a
341 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
342 running on the developer's host computer.
343 Once installed on a network using DHCP or a static IP assignment, users can
344 access the ZY1000 probe locally or remotely from any host with access to the
345 IP address assigned to the probe.
346 The ZY1000 provides an intuitive web interface with direct access to the
347 OpenOCD debugger.
348 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
349 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
350 the target.
351 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
352 to power cycle the target remotely.
354 For more information, visit:
356 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/210-zylin-zy1000-main}
358 @section USB FT2232 Based
360 There are many USB JTAG dongles on the market, many of them based
361 on a chip from ``Future Technology Devices International'' (FTDI)
362 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
363 See: @url{http://www.ftdichip.com} for more information.
364 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
365 chips started to become available in JTAG adapters. Around 2012, a new
366 variant appeared - FT232H - this is a single-channel version of FT2232H.
367 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
368 clocking.)
370 The FT2232 chips are flexible enough to support some other
371 transport options, such as SWD or the SPI variants used to
372 program some chips. They have two communications channels,
373 and one can be used for a UART adapter at the same time the
374 other one is used to provide a debug adapter.
376 Also, some development boards integrate an FT2232 chip to serve as
377 a built-in low-cost debug adapter and USB-to-serial solution.
379 @itemize @bullet
380 @item @b{usbjtag}
381 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
382 @item @b{jtagkey}
383 @* See: @url{http://www.amontec.com/jtagkey.shtml}
384 @item @b{jtagkey2}
385 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
386 @item @b{oocdlink}
387 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
388 @item @b{signalyzer}
389 @* See: @url{http://www.signalyzer.com}
390 @item @b{Stellaris Eval Boards}
391 @* See: @url{http://www.ti.com} - The Stellaris eval boards
392 bundle FT2232-based JTAG and SWD support, which can be used to debug
393 the Stellaris chips. Using separate JTAG adapters is optional.
394 These boards can also be used in a "pass through" mode as JTAG adapters
395 to other target boards, disabling the Stellaris chip.
396 @item @b{TI/Luminary ICDI}
397 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
398 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
399 Evaluation Kits. Like the non-detachable FT2232 support on the other
400 Stellaris eval boards, they can be used to debug other target boards.
401 @item @b{olimex-jtag}
402 @* See: @url{http://www.olimex.com}
403 @item @b{Flyswatter/Flyswatter2}
404 @* See: @url{http://www.tincantools.com}
405 @item @b{turtelizer2}
406 @* See:
407 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
408 @url{http://www.ethernut.de}
409 @item @b{comstick}
410 @* Link: @url{http://www.hitex.com/index.php?id=383}
411 @item @b{stm32stick}
412 @* Link @url{http://www.hitex.com/stm32-stick}
413 @item @b{axm0432_jtag}
414 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
415 to be available anymore as of April 2012.
416 @item @b{cortino}
417 @* Link @url{http://www.hitex.com/index.php?id=cortino}
418 @item @b{dlp-usb1232h}
419 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
420 @item @b{digilent-hs1}
421 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
422 @item @b{opendous}
423 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
424 (OpenHardware).
425 @item @b{JTAG-lock-pick Tiny 2}
426 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
428 @item @b{GW16042}
429 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
430 FT2232H-based
432 @end itemize
433 @section USB-JTAG / Altera USB-Blaster compatibles
435 These devices also show up as FTDI devices, but are not
436 protocol-compatible with the FT2232 devices. They are, however,
437 protocol-compatible among themselves. USB-JTAG devices typically consist
438 of a FT245 followed by a CPLD that understands a particular protocol,
439 or emulates this protocol using some other hardware.
441 They may appear under different USB VID/PID depending on the particular
442 product. The driver can be configured to search for any VID/PID pair
443 (see the section on driver commands).
445 @itemize
446 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
447 @* Link: @url{http://ixo-jtag.sourceforge.net/}
448 @item @b{Altera USB-Blaster}
449 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
450 @end itemize
452 @section USB JLINK based
453 There are several OEM versions of the Segger @b{JLINK} adapter. It is
454 an example of a micro controller based JTAG adapter, it uses an
455 AT91SAM764 internally.
457 @itemize @bullet
458 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
459 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
460 @item @b{SEGGER JLINK}
461 @* Link: @url{http://www.segger.com/jlink.html}
462 @item @b{IAR J-Link}
463 @* Link: @url{http://www.iar.com/en/products/hardware-debug-probes/iar-j-link/}
464 @end itemize
466 @section USB RLINK based
467 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
468 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
469 SWD and not JTAG, thus not supported.
471 @itemize @bullet
472 @item @b{Raisonance RLink}
473 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
474 @item @b{STM32 Primer}
475 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
476 @item @b{STM32 Primer2}
477 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
478 @end itemize
480 @section USB ST-LINK based
481 ST Micro has an adapter called @b{ST-LINK}.
482 They only work with ST Micro chips, notably STM32 and STM8.
484 @itemize @bullet
485 @item @b{ST-LINK}
486 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
487 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
488 @item @b{ST-LINK/V2}
489 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
490 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
491 @end itemize
493 For info the original ST-LINK enumerates using the mass storage usb class; however,
494 its implementation is completely broken. The result is this causes issues under Linux.
495 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
496 @itemize @bullet
497 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
498 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
499 @end itemize
501 @section USB TI/Stellaris ICDI based
502 Texas Instruments has an adapter called @b{ICDI}.
503 It is not to be confused with the FTDI based adapters that were originally fitted to their
504 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
506 @section USB CMSIS-DAP based
507 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
508 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
510 @section USB Other
511 @itemize @bullet
512 @item @b{USBprog}
513 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
515 @item @b{USB - Presto}
516 @* Link: @url{http://tools.asix.net/prg_presto.htm}
518 @item @b{Versaloon-Link}
519 @* Link: @url{http://www.versaloon.com}
521 @item @b{ARM-JTAG-EW}
522 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
524 @item @b{Buspirate}
525 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
527 @item @b{opendous}
528 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
530 @item @b{estick}
531 @* Link: @url{http://code.google.com/p/estick-jtag/}
533 @item @b{Keil ULINK v1}
534 @* Link: @url{http://www.keil.com/ulink1/}
535 @end itemize
537 @section IBM PC Parallel Printer Port Based
539 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
540 and the Macraigor Wiggler. There are many clones and variations of
541 these on the market.
543 Note that parallel ports are becoming much less common, so if you
544 have the choice you should probably avoid these adapters in favor
545 of USB-based ones.
547 @itemize @bullet
549 @item @b{Wiggler} - There are many clones of this.
550 @* Link: @url{http://www.macraigor.com/wiggler.htm}
552 @item @b{DLC5} - From XILINX - There are many clones of this
553 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
554 produced, PDF schematics are easily found and it is easy to make.
556 @item @b{Amontec - JTAG Accelerator}
557 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
559 @item @b{Wiggler2}
560 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
562 @item @b{Wiggler_ntrst_inverted}
563 @* Yet another variation - See the source code, src/jtag/parport.c
565 @item @b{old_amt_wiggler}
566 @* Unknown - probably not on the market today
568 @item @b{arm-jtag}
569 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
571 @item @b{chameleon}
572 @* Link: @url{http://www.amontec.com/chameleon.shtml}
574 @item @b{Triton}
575 @* Unknown.
577 @item @b{Lattice}
578 @* ispDownload from Lattice Semiconductor
579 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
581 @item @b{flashlink}
582 @* From ST Microsystems;
583 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
585 @end itemize
587 @section Other...
588 @itemize @bullet
590 @item @b{ep93xx}
591 @* An EP93xx based Linux machine using the GPIO pins directly.
593 @item @b{at91rm9200}
594 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
596 @item @b{bcm2835gpio}
597 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
599 @item @b{jtag_vpi}
600 @* A JTAG driver acting as a client for the JTAG VPI server interface.
601 @* Link: @url{http://github.com/fjullien/jtag_vpi}
603 @end itemize
605 @node About Jim-Tcl
606 @chapter About Jim-Tcl
607 @cindex Jim-Tcl
608 @cindex tcl
610 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
611 This programming language provides a simple and extensible
612 command interpreter.
614 All commands presented in this Guide are extensions to Jim-Tcl.
615 You can use them as simple commands, without needing to learn
616 much of anything about Tcl.
617 Alternatively, you can write Tcl programs with them.
619 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
620 There is an active and responsive community, get on the mailing list
621 if you have any questions. Jim-Tcl maintainers also lurk on the
622 OpenOCD mailing list.
624 @itemize @bullet
625 @item @b{Jim vs. Tcl}
626 @* Jim-Tcl is a stripped down version of the well known Tcl language,
627 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
628 fewer features. Jim-Tcl is several dozens of .C files and .H files and
629 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
630 4.2 MB .zip file containing 1540 files.
632 @item @b{Missing Features}
633 @* Our practice has been: Add/clone the real Tcl feature if/when
634 needed. We welcome Jim-Tcl improvements, not bloat. Also there
635 are a large number of optional Jim-Tcl features that are not
636 enabled in OpenOCD.
638 @item @b{Scripts}
639 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
640 command interpreter today is a mixture of (newer)
641 Jim-Tcl commands, and the (older) original command interpreter.
643 @item @b{Commands}
644 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
645 can type a Tcl for() loop, set variables, etc.
646 Some of the commands documented in this guide are implemented
647 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
649 @item @b{Historical Note}
650 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
651 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
652 as a Git submodule, which greatly simplified upgrading Jim-Tcl
653 to benefit from new features and bugfixes in Jim-Tcl.
655 @item @b{Need a crash course in Tcl?}
656 @*@xref{Tcl Crash Course}.
657 @end itemize
659 @node Running
660 @chapter Running
661 @cindex command line options
662 @cindex logfile
663 @cindex directory search
665 Properly installing OpenOCD sets up your operating system to grant it access
666 to the debug adapters. On Linux, this usually involves installing a file
667 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
668 that works for many common adapters is shipped with OpenOCD in the
669 @file{contrib} directory. MS-Windows needs
670 complex and confusing driver configuration for every peripheral. Such issues
671 are unique to each operating system, and are not detailed in this User's Guide.
673 Then later you will invoke the OpenOCD server, with various options to
674 tell it how each debug session should work.
675 The @option{--help} option shows:
676 @verbatim
677 bash$ openocd --help
679 --help | -h display this help
680 --version | -v display OpenOCD version
681 --file | -f use configuration file <name>
682 --search | -s dir to search for config files and scripts
683 --debug | -d set debug level <0-3>
684 --log_output | -l redirect log output to file <name>
685 --command | -c run <command>
686 @end verbatim
688 If you don't give any @option{-f} or @option{-c} options,
689 OpenOCD tries to read the configuration file @file{openocd.cfg}.
690 To specify one or more different
691 configuration files, use @option{-f} options. For example:
693 @example
694 openocd -f config1.cfg -f config2.cfg -f config3.cfg
695 @end example
697 Configuration files and scripts are searched for in
698 @enumerate
699 @item the current directory,
700 @item any search dir specified on the command line using the @option{-s} option,
701 @item any search dir specified using the @command{add_script_search_dir} command,
702 @item @file{$HOME/.openocd} (not on Windows),
703 @item the site wide script library @file{$pkgdatadir/site} and
704 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
705 @end enumerate
706 The first found file with a matching file name will be used.
708 @quotation Note
709 Don't try to use configuration script names or paths which
710 include the "#" character. That character begins Tcl comments.
711 @end quotation
713 @section Simple setup, no customization
715 In the best case, you can use two scripts from one of the script
716 libraries, hook up your JTAG adapter, and start the server ... and
717 your JTAG setup will just work "out of the box". Always try to
718 start by reusing those scripts, but assume you'll need more
719 customization even if this works. @xref{OpenOCD Project Setup}.
721 If you find a script for your JTAG adapter, and for your board or
722 target, you may be able to hook up your JTAG adapter then start
723 the server with some variation of one of the following:
725 @example
726 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
727 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
728 @end example
730 You might also need to configure which reset signals are present,
731 using @option{-c 'reset_config trst_and_srst'} or something similar.
732 If all goes well you'll see output something like
734 @example
735 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
736 For bug reports, read
737 http://openocd.org/doc/doxygen/bugs.html
738 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
739 (mfg: 0x23b, part: 0xba00, ver: 0x3)
740 @end example
742 Seeing that "tap/device found" message, and no warnings, means
743 the JTAG communication is working. That's a key milestone, but
744 you'll probably need more project-specific setup.
746 @section What OpenOCD does as it starts
748 OpenOCD starts by processing the configuration commands provided
749 on the command line or, if there were no @option{-c command} or
750 @option{-f file.cfg} options given, in @file{openocd.cfg}.
751 @xref{configurationstage,,Configuration Stage}.
752 At the end of the configuration stage it verifies the JTAG scan
753 chain defined using those commands; your configuration should
754 ensure that this always succeeds.
755 Normally, OpenOCD then starts running as a daemon.
756 Alternatively, commands may be used to terminate the configuration
757 stage early, perform work (such as updating some flash memory),
758 and then shut down without acting as a daemon.
760 Once OpenOCD starts running as a daemon, it waits for connections from
761 clients (Telnet, GDB, Other) and processes the commands issued through
762 those channels.
764 If you are having problems, you can enable internal debug messages via
765 the @option{-d} option.
767 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
768 @option{-c} command line switch.
770 To enable debug output (when reporting problems or working on OpenOCD
771 itself), use the @option{-d} command line switch. This sets the
772 @option{debug_level} to "3", outputting the most information,
773 including debug messages. The default setting is "2", outputting only
774 informational messages, warnings and errors. You can also change this
775 setting from within a telnet or gdb session using @command{debug_level<n>}
776 (@pxref{debuglevel,,debug_level}).
778 You can redirect all output from the daemon to a file using the
779 @option{-l <logfile>} switch.
781 Note! OpenOCD will launch the GDB & telnet server even if it can not
782 establish a connection with the target. In general, it is possible for
783 the JTAG controller to be unresponsive until the target is set up
784 correctly via e.g. GDB monitor commands in a GDB init script.
786 @node OpenOCD Project Setup
787 @chapter OpenOCD Project Setup
789 To use OpenOCD with your development projects, you need to do more than
790 just connect the JTAG adapter hardware (dongle) to your development board
791 and start the OpenOCD server.
792 You also need to configure your OpenOCD server so that it knows
793 about your adapter and board, and helps your work.
794 You may also want to connect OpenOCD to GDB, possibly
795 using Eclipse or some other GUI.
797 @section Hooking up the JTAG Adapter
799 Today's most common case is a dongle with a JTAG cable on one side
800 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
801 and a USB cable on the other.
802 Instead of USB, some cables use Ethernet;
803 older ones may use a PC parallel port, or even a serial port.
805 @enumerate
806 @item @emph{Start with power to your target board turned off},
807 and nothing connected to your JTAG adapter.
808 If you're particularly paranoid, unplug power to the board.
809 It's important to have the ground signal properly set up,
810 unless you are using a JTAG adapter which provides
811 galvanic isolation between the target board and the
812 debugging host.
814 @item @emph{Be sure it's the right kind of JTAG connector.}
815 If your dongle has a 20-pin ARM connector, you need some kind
816 of adapter (or octopus, see below) to hook it up to
817 boards using 14-pin or 10-pin connectors ... or to 20-pin
818 connectors which don't use ARM's pinout.
820 In the same vein, make sure the voltage levels are compatible.
821 Not all JTAG adapters have the level shifters needed to work
822 with 1.2 Volt boards.
824 @item @emph{Be certain the cable is properly oriented} or you might
825 damage your board. In most cases there are only two possible
826 ways to connect the cable.
827 Connect the JTAG cable from your adapter to the board.
828 Be sure it's firmly connected.
830 In the best case, the connector is keyed to physically
831 prevent you from inserting it wrong.
832 This is most often done using a slot on the board's male connector
833 housing, which must match a key on the JTAG cable's female connector.
834 If there's no housing, then you must look carefully and
835 make sure pin 1 on the cable hooks up to pin 1 on the board.
836 Ribbon cables are frequently all grey except for a wire on one
837 edge, which is red. The red wire is pin 1.
839 Sometimes dongles provide cables where one end is an ``octopus'' of
840 color coded single-wire connectors, instead of a connector block.
841 These are great when converting from one JTAG pinout to another,
842 but are tedious to set up.
843 Use these with connector pinout diagrams to help you match up the
844 adapter signals to the right board pins.
846 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
847 A USB, parallel, or serial port connector will go to the host which
848 you are using to run OpenOCD.
849 For Ethernet, consult the documentation and your network administrator.
851 For USB-based JTAG adapters you have an easy sanity check at this point:
852 does the host operating system see the JTAG adapter? If you're running
853 Linux, try the @command{lsusb} command. If that host is an
854 MS-Windows host, you'll need to install a driver before OpenOCD works.
856 @item @emph{Connect the adapter's power supply, if needed.}
857 This step is primarily for non-USB adapters,
858 but sometimes USB adapters need extra power.
860 @item @emph{Power up the target board.}
861 Unless you just let the magic smoke escape,
862 you're now ready to set up the OpenOCD server
863 so you can use JTAG to work with that board.
865 @end enumerate
867 Talk with the OpenOCD server using
868 telnet (@code{telnet localhost 4444} on many systems) or GDB.
869 @xref{GDB and OpenOCD}.
871 @section Project Directory
873 There are many ways you can configure OpenOCD and start it up.
875 A simple way to organize them all involves keeping a
876 single directory for your work with a given board.
877 When you start OpenOCD from that directory,
878 it searches there first for configuration files, scripts,
879 files accessed through semihosting,
880 and for code you upload to the target board.
881 It is also the natural place to write files,
882 such as log files and data you download from the board.
884 @section Configuration Basics
886 There are two basic ways of configuring OpenOCD, and
887 a variety of ways you can mix them.
888 Think of the difference as just being how you start the server:
890 @itemize
891 @item Many @option{-f file} or @option{-c command} options on the command line
892 @item No options, but a @dfn{user config file}
893 in the current directory named @file{openocd.cfg}
894 @end itemize
896 Here is an example @file{openocd.cfg} file for a setup
897 using a Signalyzer FT2232-based JTAG adapter to talk to
898 a board with an Atmel AT91SAM7X256 microcontroller:
900 @example
901 source [find interface/signalyzer.cfg]
903 # GDB can also flash my flash!
904 gdb_memory_map enable
905 gdb_flash_program enable
907 source [find target/sam7x256.cfg]
908 @end example
910 Here is the command line equivalent of that configuration:
912 @example
913 openocd -f interface/signalyzer.cfg \
914 -c "gdb_memory_map enable" \
915 -c "gdb_flash_program enable" \
916 -f target/sam7x256.cfg
917 @end example
919 You could wrap such long command lines in shell scripts,
920 each supporting a different development task.
921 One might re-flash the board with a specific firmware version.
922 Another might set up a particular debugging or run-time environment.
924 @quotation Important
925 At this writing (October 2009) the command line method has
926 problems with how it treats variables.
927 For example, after @option{-c "set VAR value"}, or doing the
928 same in a script, the variable @var{VAR} will have no value
929 that can be tested in a later script.
930 @end quotation
932 Here we will focus on the simpler solution: one user config
933 file, including basic configuration plus any TCL procedures
934 to simplify your work.
936 @section User Config Files
937 @cindex config file, user
938 @cindex user config file
939 @cindex config file, overview
941 A user configuration file ties together all the parts of a project
942 in one place.
943 One of the following will match your situation best:
945 @itemize
946 @item Ideally almost everything comes from configuration files
947 provided by someone else.
948 For example, OpenOCD distributes a @file{scripts} directory
949 (probably in @file{/usr/share/openocd/scripts} on Linux).
950 Board and tool vendors can provide these too, as can individual
951 user sites; the @option{-s} command line option lets you say
952 where to find these files. (@xref{Running}.)
953 The AT91SAM7X256 example above works this way.
955 Three main types of non-user configuration file each have their
956 own subdirectory in the @file{scripts} directory:
958 @enumerate
959 @item @b{interface} -- one for each different debug adapter;
960 @item @b{board} -- one for each different board
961 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
962 @end enumerate
964 Best case: include just two files, and they handle everything else.
965 The first is an interface config file.
966 The second is board-specific, and it sets up the JTAG TAPs and
967 their GDB targets (by deferring to some @file{target.cfg} file),
968 declares all flash memory, and leaves you nothing to do except
969 meet your deadline:
971 @example
972 source [find interface/olimex-jtag-tiny.cfg]
973 source [find board/csb337.cfg]
974 @end example
976 Boards with a single microcontroller often won't need more
977 than the target config file, as in the AT91SAM7X256 example.
978 That's because there is no external memory (flash, DDR RAM), and
979 the board differences are encapsulated by application code.
981 @item Maybe you don't know yet what your board looks like to JTAG.
982 Once you know the @file{interface.cfg} file to use, you may
983 need help from OpenOCD to discover what's on the board.
984 Once you find the JTAG TAPs, you can just search for appropriate
985 target and board
986 configuration files ... or write your own, from the bottom up.
987 @xref{autoprobing,,Autoprobing}.
989 @item You can often reuse some standard config files but
990 need to write a few new ones, probably a @file{board.cfg} file.
991 You will be using commands described later in this User's Guide,
992 and working with the guidelines in the next chapter.
994 For example, there may be configuration files for your JTAG adapter
995 and target chip, but you need a new board-specific config file
996 giving access to your particular flash chips.
997 Or you might need to write another target chip configuration file
998 for a new chip built around the Cortex M3 core.
1000 @quotation Note
1001 When you write new configuration files, please submit
1002 them for inclusion in the next OpenOCD release.
1003 For example, a @file{board/newboard.cfg} file will help the
1004 next users of that board, and a @file{target/newcpu.cfg}
1005 will help support users of any board using that chip.
1006 @end quotation
1008 @item
1009 You may may need to write some C code.
1010 It may be as simple as supporting a new FT2232 or parport
1011 based adapter; a bit more involved, like a NAND or NOR flash
1012 controller driver; or a big piece of work like supporting
1013 a new chip architecture.
1014 @end itemize
1016 Reuse the existing config files when you can.
1017 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1018 You may find a board configuration that's a good example to follow.
1020 When you write config files, separate the reusable parts
1021 (things every user of that interface, chip, or board needs)
1022 from ones specific to your environment and debugging approach.
1023 @itemize
1025 @item
1026 For example, a @code{gdb-attach} event handler that invokes
1027 the @command{reset init} command will interfere with debugging
1028 early boot code, which performs some of the same actions
1029 that the @code{reset-init} event handler does.
1031 @item
1032 Likewise, the @command{arm9 vector_catch} command (or
1033 @cindex vector_catch
1034 its siblings @command{xscale vector_catch}
1035 and @command{cortex_m vector_catch}) can be a timesaver
1036 during some debug sessions, but don't make everyone use that either.
1037 Keep those kinds of debugging aids in your user config file,
1038 along with messaging and tracing setup.
1039 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1041 @item
1042 You might need to override some defaults.
1043 For example, you might need to move, shrink, or back up the target's
1044 work area if your application needs much SRAM.
1046 @item
1047 TCP/IP port configuration is another example of something which
1048 is environment-specific, and should only appear in
1049 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1050 @end itemize
1052 @section Project-Specific Utilities
1054 A few project-specific utility
1055 routines may well speed up your work.
1056 Write them, and keep them in your project's user config file.
1058 For example, if you are making a boot loader work on a
1059 board, it's nice to be able to debug the ``after it's
1060 loaded to RAM'' parts separately from the finicky early
1061 code which sets up the DDR RAM controller and clocks.
1062 A script like this one, or a more GDB-aware sibling,
1063 may help:
1065 @example
1066 proc ramboot @{ @} @{
1067 # Reset, running the target's "reset-init" scripts
1068 # to initialize clocks and the DDR RAM controller.
1069 # Leave the CPU halted.
1070 reset init
1072 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1073 load_image u-boot.bin 0x20000000
1075 # Start running.
1076 resume 0x20000000
1077 @}
1078 @end example
1080 Then once that code is working you will need to make it
1081 boot from NOR flash; a different utility would help.
1082 Alternatively, some developers write to flash using GDB.
1083 (You might use a similar script if you're working with a flash
1084 based microcontroller application instead of a boot loader.)
1086 @example
1087 proc newboot @{ @} @{
1088 # Reset, leaving the CPU halted. The "reset-init" event
1089 # proc gives faster access to the CPU and to NOR flash;
1090 # "reset halt" would be slower.
1091 reset init
1093 # Write standard version of U-Boot into the first two
1094 # sectors of NOR flash ... the standard version should
1095 # do the same lowlevel init as "reset-init".
1096 flash protect 0 0 1 off
1097 flash erase_sector 0 0 1
1098 flash write_bank 0 u-boot.bin 0x0
1099 flash protect 0 0 1 on
1101 # Reboot from scratch using that new boot loader.
1102 reset run
1103 @}
1104 @end example
1106 You may need more complicated utility procedures when booting
1107 from NAND.
1108 That often involves an extra bootloader stage,
1109 running from on-chip SRAM to perform DDR RAM setup so it can load
1110 the main bootloader code (which won't fit into that SRAM).
1112 Other helper scripts might be used to write production system images,
1113 involving considerably more than just a three stage bootloader.
1115 @section Target Software Changes
1117 Sometimes you may want to make some small changes to the software
1118 you're developing, to help make JTAG debugging work better.
1119 For example, in C or assembly language code you might
1120 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1121 handling issues like:
1123 @itemize @bullet
1125 @item @b{Watchdog Timers}...
1126 Watchog timers are typically used to automatically reset systems if
1127 some application task doesn't periodically reset the timer. (The
1128 assumption is that the system has locked up if the task can't run.)
1129 When a JTAG debugger halts the system, that task won't be able to run
1130 and reset the timer ... potentially causing resets in the middle of
1131 your debug sessions.
1133 It's rarely a good idea to disable such watchdogs, since their usage
1134 needs to be debugged just like all other parts of your firmware.
1135 That might however be your only option.
1137 Look instead for chip-specific ways to stop the watchdog from counting
1138 while the system is in a debug halt state. It may be simplest to set
1139 that non-counting mode in your debugger startup scripts. You may however
1140 need a different approach when, for example, a motor could be physically
1141 damaged by firmware remaining inactive in a debug halt state. That might
1142 involve a type of firmware mode where that "non-counting" mode is disabled
1143 at the beginning then re-enabled at the end; a watchdog reset might fire
1144 and complicate the debug session, but hardware (or people) would be
1145 protected.@footnote{Note that many systems support a "monitor mode" debug
1146 that is a somewhat cleaner way to address such issues. You can think of
1147 it as only halting part of the system, maybe just one task,
1148 instead of the whole thing.
1149 At this writing, January 2010, OpenOCD based debugging does not support
1150 monitor mode debug, only "halt mode" debug.}
1152 @item @b{ARM Semihosting}...
1153 @cindex ARM semihosting
1154 When linked with a special runtime library provided with many
1155 toolchains@footnote{See chapter 8 "Semihosting" in
1156 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1157 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1158 The CodeSourcery EABI toolchain also includes a semihosting library.},
1159 your target code can use I/O facilities on the debug host. That library
1160 provides a small set of system calls which are handled by OpenOCD.
1161 It can let the debugger provide your system console and a file system,
1162 helping with early debugging or providing a more capable environment
1163 for sometimes-complex tasks like installing system firmware onto
1164 NAND or SPI flash.
1166 @item @b{ARM Wait-For-Interrupt}...
1167 Many ARM chips synchronize the JTAG clock using the core clock.
1168 Low power states which stop that core clock thus prevent JTAG access.
1169 Idle loops in tasking environments often enter those low power states
1170 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1172 You may want to @emph{disable that instruction} in source code,
1173 or otherwise prevent using that state,
1174 to ensure you can get JTAG access at any time.@footnote{As a more
1175 polite alternative, some processors have special debug-oriented
1176 registers which can be used to change various features including
1177 how the low power states are clocked while debugging.
1178 The STM32 DBGMCU_CR register is an example; at the cost of extra
1179 power consumption, JTAG can be used during low power states.}
1180 For example, the OpenOCD @command{halt} command may not
1181 work for an idle processor otherwise.
1183 @item @b{Delay after reset}...
1184 Not all chips have good support for debugger access
1185 right after reset; many LPC2xxx chips have issues here.
1186 Similarly, applications that reconfigure pins used for
1187 JTAG access as they start will also block debugger access.
1189 To work with boards like this, @emph{enable a short delay loop}
1190 the first thing after reset, before "real" startup activities.
1191 For example, one second's delay is usually more than enough
1192 time for a JTAG debugger to attach, so that
1193 early code execution can be debugged
1194 or firmware can be replaced.
1196 @item @b{Debug Communications Channel (DCC)}...
1197 Some processors include mechanisms to send messages over JTAG.
1198 Many ARM cores support these, as do some cores from other vendors.
1199 (OpenOCD may be able to use this DCC internally, speeding up some
1200 operations like writing to memory.)
1202 Your application may want to deliver various debugging messages
1203 over JTAG, by @emph{linking with a small library of code}
1204 provided with OpenOCD and using the utilities there to send
1205 various kinds of message.
1206 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1208 @end itemize
1210 @section Target Hardware Setup
1212 Chip vendors often provide software development boards which
1213 are highly configurable, so that they can support all options
1214 that product boards may require. @emph{Make sure that any
1215 jumpers or switches match the system configuration you are
1216 working with.}
1218 Common issues include:
1220 @itemize @bullet
1222 @item @b{JTAG setup} ...
1223 Boards may support more than one JTAG configuration.
1224 Examples include jumpers controlling pullups versus pulldowns
1225 on the nTRST and/or nSRST signals, and choice of connectors
1226 (e.g. which of two headers on the base board,
1227 or one from a daughtercard).
1228 For some Texas Instruments boards, you may need to jumper the
1229 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1231 @item @b{Boot Modes} ...
1232 Complex chips often support multiple boot modes, controlled
1233 by external jumpers. Make sure this is set up correctly.
1234 For example many i.MX boards from NXP need to be jumpered
1235 to "ATX mode" to start booting using the on-chip ROM, when
1236 using second stage bootloader code stored in a NAND flash chip.
1238 Such explicit configuration is common, and not limited to
1239 booting from NAND. You might also need to set jumpers to
1240 start booting using code loaded from an MMC/SD card; external
1241 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1242 flash; some external host; or various other sources.
1245 @item @b{Memory Addressing} ...
1246 Boards which support multiple boot modes may also have jumpers
1247 to configure memory addressing. One board, for example, jumpers
1248 external chipselect 0 (used for booting) to address either
1249 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1250 or NAND flash. When it's jumpered to address NAND flash, that
1251 board must also be told to start booting from on-chip ROM.
1253 Your @file{board.cfg} file may also need to be told this jumper
1254 configuration, so that it can know whether to declare NOR flash
1255 using @command{flash bank} or instead declare NAND flash with
1256 @command{nand device}; and likewise which probe to perform in
1257 its @code{reset-init} handler.
1259 A closely related issue is bus width. Jumpers might need to
1260 distinguish between 8 bit or 16 bit bus access for the flash
1261 used to start booting.
1263 @item @b{Peripheral Access} ...
1264 Development boards generally provide access to every peripheral
1265 on the chip, sometimes in multiple modes (such as by providing
1266 multiple audio codec chips).
1267 This interacts with software
1268 configuration of pin multiplexing, where for example a
1269 given pin may be routed either to the MMC/SD controller
1270 or the GPIO controller. It also often interacts with
1271 configuration jumpers. One jumper may be used to route
1272 signals to an MMC/SD card slot or an expansion bus (which
1273 might in turn affect booting); others might control which
1274 audio or video codecs are used.
1276 @end itemize
1278 Plus you should of course have @code{reset-init} event handlers
1279 which set up the hardware to match that jumper configuration.
1280 That includes in particular any oscillator or PLL used to clock
1281 the CPU, and any memory controllers needed to access external
1282 memory and peripherals. Without such handlers, you won't be
1283 able to access those resources without working target firmware
1284 which can do that setup ... this can be awkward when you're
1285 trying to debug that target firmware. Even if there's a ROM
1286 bootloader which handles a few issues, it rarely provides full
1287 access to all board-specific capabilities.
1290 @node Config File Guidelines
1291 @chapter Config File Guidelines
1293 This chapter is aimed at any user who needs to write a config file,
1294 including developers and integrators of OpenOCD and any user who
1295 needs to get a new board working smoothly.
1296 It provides guidelines for creating those files.
1298 You should find the following directories under
1299 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1300 them as-is where you can; or as models for new files.
1301 @itemize @bullet
1302 @item @file{interface} ...
1303 These are for debug adapters. Files that specify configuration to use
1304 specific JTAG, SWD and other adapters go here.
1305 @item @file{board} ...
1306 Think Circuit Board, PWA, PCB, they go by many names. Board files
1307 contain initialization items that are specific to a board.
1309 They reuse target configuration files, since the same
1310 microprocessor chips are used on many boards,
1311 but support for external parts varies widely. For
1312 example, the SDRAM initialization sequence for the board, or the type
1313 of external flash and what address it uses. Any initialization
1314 sequence to enable that external flash or SDRAM should be found in the
1315 board file. Boards may also contain multiple targets: two CPUs; or
1316 a CPU and an FPGA.
1317 @item @file{target} ...
1318 Think chip. The ``target'' directory represents the JTAG TAPs
1319 on a chip
1320 which OpenOCD should control, not a board. Two common types of targets
1321 are ARM chips and FPGA or CPLD chips.
1322 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1323 the target config file defines all of them.
1324 @item @emph{more} ... browse for other library files which may be useful.
1325 For example, there are various generic and CPU-specific utilities.
1326 @end itemize
1328 The @file{openocd.cfg} user config
1329 file may override features in any of the above files by
1330 setting variables before sourcing the target file, or by adding
1331 commands specific to their situation.
1333 @section Interface Config Files
1335 The user config file
1336 should be able to source one of these files with a command like this:
1338 @example
1339 source [find interface/FOOBAR.cfg]
1340 @end example
1342 A preconfigured interface file should exist for every debug adapter
1343 in use today with OpenOCD.
1344 That said, perhaps some of these config files
1345 have only been used by the developer who created it.
1347 A separate chapter gives information about how to set these up.
1348 @xref{Debug Adapter Configuration}.
1349 Read the OpenOCD source code (and Developer's Guide)
1350 if you have a new kind of hardware interface
1351 and need to provide a driver for it.
1353 @section Board Config Files
1354 @cindex config file, board
1355 @cindex board config file
1357 The user config file
1358 should be able to source one of these files with a command like this:
1360 @example
1361 source [find board/FOOBAR.cfg]
1362 @end example
1364 The point of a board config file is to package everything
1365 about a given board that user config files need to know.
1366 In summary the board files should contain (if present)
1368 @enumerate
1369 @item One or more @command{source [find target/...cfg]} statements
1370 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1371 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1372 @item Target @code{reset} handlers for SDRAM and I/O configuration
1373 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1374 @item All things that are not ``inside a chip''
1375 @end enumerate
1377 Generic things inside target chips belong in target config files,
1378 not board config files. So for example a @code{reset-init} event
1379 handler should know board-specific oscillator and PLL parameters,
1380 which it passes to target-specific utility code.
1382 The most complex task of a board config file is creating such a
1383 @code{reset-init} event handler.
1384 Define those handlers last, after you verify the rest of the board
1385 configuration works.
1387 @subsection Communication Between Config files
1389 In addition to target-specific utility code, another way that
1390 board and target config files communicate is by following a
1391 convention on how to use certain variables.
1393 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1394 Thus the rule we follow in OpenOCD is this: Variables that begin with
1395 a leading underscore are temporary in nature, and can be modified and
1396 used at will within a target configuration file.
1398 Complex board config files can do the things like this,
1399 for a board with three chips:
1401 @example
1402 # Chip #1: PXA270 for network side, big endian
1403 set CHIPNAME network
1404 set ENDIAN big
1405 source [find target/pxa270.cfg]
1406 # on return: _TARGETNAME = network.cpu
1407 # other commands can refer to the "network.cpu" target.
1408 $_TARGETNAME configure .... events for this CPU..
1410 # Chip #2: PXA270 for video side, little endian
1411 set CHIPNAME video
1412 set ENDIAN little
1413 source [find target/pxa270.cfg]
1414 # on return: _TARGETNAME = video.cpu
1415 # other commands can refer to the "video.cpu" target.
1416 $_TARGETNAME configure .... events for this CPU..
1418 # Chip #3: Xilinx FPGA for glue logic
1419 set CHIPNAME xilinx
1420 unset ENDIAN
1421 source [find target/spartan3.cfg]
1422 @end example
1424 That example is oversimplified because it doesn't show any flash memory,
1425 or the @code{reset-init} event handlers to initialize external DRAM
1426 or (assuming it needs it) load a configuration into the FPGA.
1427 Such features are usually needed for low-level work with many boards,
1428 where ``low level'' implies that the board initialization software may
1429 not be working. (That's a common reason to need JTAG tools. Another
1430 is to enable working with microcontroller-based systems, which often
1431 have no debugging support except a JTAG connector.)
1433 Target config files may also export utility functions to board and user
1434 config files. Such functions should use name prefixes, to help avoid
1435 naming collisions.
1437 Board files could also accept input variables from user config files.
1438 For example, there might be a @code{J4_JUMPER} setting used to identify
1439 what kind of flash memory a development board is using, or how to set
1440 up other clocks and peripherals.
1442 @subsection Variable Naming Convention
1443 @cindex variable names
1445 Most boards have only one instance of a chip.
1446 However, it should be easy to create a board with more than
1447 one such chip (as shown above).
1448 Accordingly, we encourage these conventions for naming
1449 variables associated with different @file{target.cfg} files,
1450 to promote consistency and
1451 so that board files can override target defaults.
1453 Inputs to target config files include:
1455 @itemize @bullet
1456 @item @code{CHIPNAME} ...
1457 This gives a name to the overall chip, and is used as part of
1458 tap identifier dotted names.
1459 While the default is normally provided by the chip manufacturer,
1460 board files may need to distinguish between instances of a chip.
1461 @item @code{ENDIAN} ...
1462 By default @option{little} - although chips may hard-wire @option{big}.
1463 Chips that can't change endianness don't need to use this variable.
1464 @item @code{CPUTAPID} ...
1465 When OpenOCD examines the JTAG chain, it can be told verify the
1466 chips against the JTAG IDCODE register.
1467 The target file will hold one or more defaults, but sometimes the
1468 chip in a board will use a different ID (perhaps a newer revision).
1469 @end itemize
1471 Outputs from target config files include:
1473 @itemize @bullet
1474 @item @code{_TARGETNAME} ...
1475 By convention, this variable is created by the target configuration
1476 script. The board configuration file may make use of this variable to
1477 configure things like a ``reset init'' script, or other things
1478 specific to that board and that target.
1479 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1480 @code{_TARGETNAME1}, ... etc.
1481 @end itemize
1483 @subsection The reset-init Event Handler
1484 @cindex event, reset-init
1485 @cindex reset-init handler
1487 Board config files run in the OpenOCD configuration stage;
1488 they can't use TAPs or targets, since they haven't been
1489 fully set up yet.
1490 This means you can't write memory or access chip registers;
1491 you can't even verify that a flash chip is present.
1492 That's done later in event handlers, of which the target @code{reset-init}
1493 handler is one of the most important.
1495 Except on microcontrollers, the basic job of @code{reset-init} event
1496 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1497 Microcontrollers rarely use boot loaders; they run right out of their
1498 on-chip flash and SRAM memory. But they may want to use one of these
1499 handlers too, if just for developer convenience.
1501 @quotation Note
1502 Because this is so very board-specific, and chip-specific, no examples
1503 are included here.
1504 Instead, look at the board config files distributed with OpenOCD.
1505 If you have a boot loader, its source code will help; so will
1506 configuration files for other JTAG tools
1507 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1508 @end quotation
1510 Some of this code could probably be shared between different boards.
1511 For example, setting up a DRAM controller often doesn't differ by
1512 much except the bus width (16 bits or 32?) and memory timings, so a
1513 reusable TCL procedure loaded by the @file{target.cfg} file might take
1514 those as parameters.
1515 Similarly with oscillator, PLL, and clock setup;
1516 and disabling the watchdog.
1517 Structure the code cleanly, and provide comments to help
1518 the next developer doing such work.
1519 (@emph{You might be that next person} trying to reuse init code!)
1521 The last thing normally done in a @code{reset-init} handler is probing
1522 whatever flash memory was configured. For most chips that needs to be
1523 done while the associated target is halted, either because JTAG memory
1524 access uses the CPU or to prevent conflicting CPU access.
1526 @subsection JTAG Clock Rate
1528 Before your @code{reset-init} handler has set up
1529 the PLLs and clocking, you may need to run with
1530 a low JTAG clock rate.
1531 @xref{jtagspeed,,JTAG Speed}.
1532 Then you'd increase that rate after your handler has
1533 made it possible to use the faster JTAG clock.
1534 When the initial low speed is board-specific, for example
1535 because it depends on a board-specific oscillator speed, then
1536 you should probably set it up in the board config file;
1537 if it's target-specific, it belongs in the target config file.
1539 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1540 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1541 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1542 Consult chip documentation to determine the peak JTAG clock rate,
1543 which might be less than that.
1545 @quotation Warning
1546 On most ARMs, JTAG clock detection is coupled to the core clock, so
1547 software using a @option{wait for interrupt} operation blocks JTAG access.
1548 Adaptive clocking provides a partial workaround, but a more complete
1549 solution just avoids using that instruction with JTAG debuggers.
1550 @end quotation
1552 If both the chip and the board support adaptive clocking,
1553 use the @command{jtag_rclk}
1554 command, in case your board is used with JTAG adapter which
1555 also supports it. Otherwise use @command{adapter_khz}.
1556 Set the slow rate at the beginning of the reset sequence,
1557 and the faster rate as soon as the clocks are at full speed.
1559 @anchor{theinitboardprocedure}
1560 @subsection The init_board procedure
1561 @cindex init_board procedure
1563 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1564 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1565 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1566 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1567 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1568 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1569 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1570 Additionally ``linear'' board config file will most likely fail when target config file uses
1571 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1572 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1573 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1574 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1576 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1577 the original), allowing greater code reuse.
1579 @example
1580 ### board_file.cfg ###
1582 # source target file that does most of the config in init_targets
1583 source [find target/target.cfg]
1585 proc enable_fast_clock @{@} @{
1586 # enables fast on-board clock source
1587 # configures the chip to use it
1588 @}
1590 # initialize only board specifics - reset, clock, adapter frequency
1591 proc init_board @{@} @{
1592 reset_config trst_and_srst trst_pulls_srst
1594 $_TARGETNAME configure -event reset-init @{
1595 adapter_khz 1
1596 enable_fast_clock
1597 adapter_khz 10000
1598 @}
1599 @}
1600 @end example
1602 @section Target Config Files
1603 @cindex config file, target
1604 @cindex target config file
1606 Board config files communicate with target config files using
1607 naming conventions as described above, and may source one or
1608 more target config files like this:
1610 @example
1611 source [find target/FOOBAR.cfg]
1612 @end example
1614 The point of a target config file is to package everything
1615 about a given chip that board config files need to know.
1616 In summary the target files should contain
1618 @enumerate
1619 @item Set defaults
1620 @item Add TAPs to the scan chain
1621 @item Add CPU targets (includes GDB support)
1622 @item CPU/Chip/CPU-Core specific features
1623 @item On-Chip flash
1624 @end enumerate
1626 As a rule of thumb, a target file sets up only one chip.
1627 For a microcontroller, that will often include a single TAP,
1628 which is a CPU needing a GDB target, and its on-chip flash.
1630 More complex chips may include multiple TAPs, and the target
1631 config file may need to define them all before OpenOCD
1632 can talk to the chip.
1633 For example, some phone chips have JTAG scan chains that include
1634 an ARM core for operating system use, a DSP,
1635 another ARM core embedded in an image processing engine,
1636 and other processing engines.
1638 @subsection Default Value Boiler Plate Code
1640 All target configuration files should start with code like this,
1641 letting board config files express environment-specific
1642 differences in how things should be set up.
1644 @example
1645 # Boards may override chip names, perhaps based on role,
1646 # but the default should match what the vendor uses
1647 if @{ [info exists CHIPNAME] @} @{
1649 @} else @{
1650 set _CHIPNAME sam7x256
1651 @}
1653 # ONLY use ENDIAN with targets that can change it.
1654 if @{ [info exists ENDIAN] @} @{
1655 set _ENDIAN $ENDIAN
1656 @} else @{
1657 set _ENDIAN little
1658 @}
1660 # TAP identifiers may change as chips mature, for example with
1661 # new revision fields (the "3" here). Pick a good default; you
1662 # can pass several such identifiers to the "jtag newtap" command.
1663 if @{ [info exists CPUTAPID ] @} @{
1665 @} else @{
1666 set _CPUTAPID 0x3f0f0f0f
1667 @}
1668 @end example
1669 @c but 0x3f0f0f0f is for an str73x part ...
1671 @emph{Remember:} Board config files may include multiple target
1672 config files, or the same target file multiple times
1673 (changing at least @code{CHIPNAME}).
1675 Likewise, the target configuration file should define
1676 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1677 use it later on when defining debug targets:
1679 @example
1681 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1682 @end example
1684 @subsection Adding TAPs to the Scan Chain
1685 After the ``defaults'' are set up,
1686 add the TAPs on each chip to the JTAG scan chain.
1687 @xref{TAP Declaration}, and the naming convention
1688 for taps.
1690 In the simplest case the chip has only one TAP,
1691 probably for a CPU or FPGA.
1692 The config file for the Atmel AT91SAM7X256
1693 looks (in part) like this:
1695 @example
1696 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1697 @end example
1699 A board with two such at91sam7 chips would be able
1700 to source such a config file twice, with different
1701 values for @code{CHIPNAME}, so
1702 it adds a different TAP each time.
1704 If there are nonzero @option{-expected-id} values,
1705 OpenOCD attempts to verify the actual tap id against those values.
1706 It will issue error messages if there is mismatch, which
1707 can help to pinpoint problems in OpenOCD configurations.
1709 @example
1710 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1711 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1712 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1713 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1714 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1715 @end example
1717 There are more complex examples too, with chips that have
1718 multiple TAPs. Ones worth looking at include:
1720 @itemize
1721 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1722 plus a JRC to enable them
1723 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1724 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1725 is not currently used)
1726 @end itemize
1728 @subsection Add CPU targets
1730 After adding a TAP for a CPU, you should set it up so that
1731 GDB and other commands can use it.
1732 @xref{CPU Configuration}.
1733 For the at91sam7 example above, the command can look like this;
1734 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1735 to little endian, and this chip doesn't support changing that.
1737 @example
1739 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1740 @end example
1742 Work areas are small RAM areas associated with CPU targets.
1743 They are used by OpenOCD to speed up downloads,
1744 and to download small snippets of code to program flash chips.
1745 If the chip includes a form of ``on-chip-ram'' - and many do - define
1746 a work area if you can.
1747 Again using the at91sam7 as an example, this can look like:
1749 @example
1750 $_TARGETNAME configure -work-area-phys 0x00200000 \
1751 -work-area-size 0x4000 -work-area-backup 0
1752 @end example
1754 @anchor{definecputargetsworkinginsmp}
1755 @subsection Define CPU targets working in SMP
1756 @cindex SMP
1757 After setting targets, you can define a list of targets working in SMP.
1759 @example
1760 set _TARGETNAME_1 $_CHIPNAME.cpu1
1761 set _TARGETNAME_2 $_CHIPNAME.cpu2
1762 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1763 -coreid 0 -dbgbase $_DAP_DBG1
1764 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1765 -coreid 1 -dbgbase $_DAP_DBG2
1766 #define 2 targets working in smp.
1767 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1768 @end example
1769 In the above example on cortex_a, 2 cpus are working in SMP.
1770 In SMP only one GDB instance is created and :
1771 @itemize @bullet
1772 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1773 @item halt command triggers the halt of all targets in the list.
1774 @item resume command triggers the write context and the restart of all targets in the list.
1775 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1776 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1777 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1778 @end itemize
1780 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1781 command have been implemented.
1782 @itemize @bullet
1783 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1784 @item cortex_a smp_off : disable SMP mode, the current target is the one
1785 displayed in the GDB session, only this target is now controlled by GDB
1786 session. This behaviour is useful during system boot up.
1787 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1788 following example.
1789 @end itemize
1791 @example
1792 >cortex_a smp_gdb
1793 gdb coreid 0 -> -1
1794 #0 : coreid 0 is displayed to GDB ,
1795 #-> -1 : next resume triggers a real resume
1796 > cortex_a smp_gdb 1
1797 gdb coreid 0 -> 1
1798 #0 :coreid 0 is displayed to GDB ,
1799 #->1 : next resume displays coreid 1 to GDB
1800 > resume
1801 > cortex_a smp_gdb
1802 gdb coreid 1 -> 1
1803 #1 :coreid 1 is displayed to GDB ,
1804 #->1 : next resume displays coreid 1 to GDB
1805 > cortex_a smp_gdb -1
1806 gdb coreid 1 -> -1
1807 #1 :coreid 1 is displayed to GDB,
1808 #->-1 : next resume triggers a real resume
1809 @end example
1812 @subsection Chip Reset Setup
1814 As a rule, you should put the @command{reset_config} command
1815 into the board file. Most things you think you know about a
1816 chip can be tweaked by the board.
1818 Some chips have specific ways the TRST and SRST signals are
1819 managed. In the unusual case that these are @emph{chip specific}
1820 and can never be changed by board wiring, they could go here.
1821 For example, some chips can't support JTAG debugging without
1822 both signals.
1824 Provide a @code{reset-assert} event handler if you can.
1825 Such a handler uses JTAG operations to reset the target,
1826 letting this target config be used in systems which don't
1827 provide the optional SRST signal, or on systems where you
1828 don't want to reset all targets at once.
1829 Such a handler might write to chip registers to force a reset,
1830 use a JRC to do that (preferable -- the target may be wedged!),
1831 or force a watchdog timer to trigger.
1832 (For Cortex-M targets, this is not necessary. The target
1833 driver knows how to use trigger an NVIC reset when SRST is
1834 not available.)
1836 Some chips need special attention during reset handling if
1837 they're going to be used with JTAG.
1838 An example might be needing to send some commands right
1839 after the target's TAP has been reset, providing a
1840 @code{reset-deassert-post} event handler that writes a chip
1841 register to report that JTAG debugging is being done.
1842 Another would be reconfiguring the watchdog so that it stops
1843 counting while the core is halted in the debugger.
1845 JTAG clocking constraints often change during reset, and in
1846 some cases target config files (rather than board config files)
1847 are the right places to handle some of those issues.
1848 For example, immediately after reset most chips run using a
1849 slower clock than they will use later.
1850 That means that after reset (and potentially, as OpenOCD
1851 first starts up) they must use a slower JTAG clock rate
1852 than they will use later.
1853 @xref{jtagspeed,,JTAG Speed}.
1855 @quotation Important
1856 When you are debugging code that runs right after chip
1857 reset, getting these issues right is critical.
1858 In particular, if you see intermittent failures when
1859 OpenOCD verifies the scan chain after reset,
1860 look at how you are setting up JTAG clocking.
1861 @end quotation
1863 @anchor{theinittargetsprocedure}
1864 @subsection The init_targets procedure
1865 @cindex init_targets procedure
1867 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1868 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1869 procedure called @code{init_targets}, which will be executed when entering run stage
1870 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1871 Such procedure can be overriden by ``next level'' script (which sources the original).
1872 This concept faciliates code reuse when basic target config files provide generic configuration
1873 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
1874 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1875 because sourcing them executes every initialization commands they provide.
1877 @example
1878 ### generic_file.cfg ###
1880 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1881 # basic initialization procedure ...
1882 @}
1884 proc init_targets @{@} @{
1885 # initializes generic chip with 4kB of flash and 1kB of RAM
1886 setup_my_chip MY_GENERIC_CHIP 4096 1024
1887 @}
1889 ### specific_file.cfg ###
1891 source [find target/generic_file.cfg]
1893 proc init_targets @{@} @{
1894 # initializes specific chip with 128kB of flash and 64kB of RAM
1895 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1896 @}
1897 @end example
1899 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1900 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1902 For an example of this scheme see LPC2000 target config files.
1904 The @code{init_boards} procedure is a similar concept concerning board config files
1905 (@xref{theinitboardprocedure,,The init_board procedure}.)
1907 @anchor{theinittargeteventsprocedure}
1908 @subsection The init_target_events procedure
1909 @cindex init_target_events procedure
1911 A special procedure called @code{init_target_events} is run just after
1912 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1913 procedure}.) and before @code{init_board}
1914 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1915 to set up default target events for the targets that do not have those
1916 events already assigned.
1918 @subsection ARM Core Specific Hacks
1920 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1921 special high speed download features - enable it.
1923 If present, the MMU, the MPU and the CACHE should be disabled.
1925 Some ARM cores are equipped with trace support, which permits
1926 examination of the instruction and data bus activity. Trace
1927 activity is controlled through an ``Embedded Trace Module'' (ETM)
1928 on one of the core's scan chains. The ETM emits voluminous data
1929 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1930 If you are using an external trace port,
1931 configure it in your board config file.
1932 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1933 configure it in your target config file.
1935 @example
1936 etm config $_TARGETNAME 16 normal full etb
1937 etb config $_TARGETNAME $_CHIPNAME.etb
1938 @end example
1940 @subsection Internal Flash Configuration
1942 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1944 @b{Never ever} in the ``target configuration file'' define any type of
1945 flash that is external to the chip. (For example a BOOT flash on
1946 Chip Select 0.) Such flash information goes in a board file - not
1947 the TARGET (chip) file.
1949 Examples:
1950 @itemize @bullet
1951 @item at91sam7x256 - has 256K flash YES enable it.
1952 @item str912 - has flash internal YES enable it.
1953 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1954 @item pxa270 - again - CS0 flash - it goes in the board file.
1955 @end itemize
1957 @anchor{translatingconfigurationfiles}
1958 @section Translating Configuration Files
1959 @cindex translation
1960 If you have a configuration file for another hardware debugger
1961 or toolset (Abatron, BDI2000, BDI3000, CCS,
1962 Lauterbach, Segger, Macraigor, etc.), translating
1963 it into OpenOCD syntax is often quite straightforward. The most tricky
1964 part of creating a configuration script is oftentimes the reset init
1965 sequence where e.g. PLLs, DRAM and the like is set up.
1967 One trick that you can use when translating is to write small
1968 Tcl procedures to translate the syntax into OpenOCD syntax. This
1969 can avoid manual translation errors and make it easier to
1970 convert other scripts later on.
1972 Example of transforming quirky arguments to a simple search and
1973 replace job:
1975 @example
1976 # Lauterbach syntax(?)
1977 #
1978 # Data.Set c15:0x042f %long 0x40000015
1979 #
1980 # OpenOCD syntax when using procedure below.
1981 #
1982 # setc15 0x01 0x00050078
1984 proc setc15 @{regs value@} @{
1985 global TARGETNAME
1987 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
1989 arm mcr 15 [expr ($regs>>12)&0x7] \
1990 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
1991 [expr ($regs>>8)&0x7] $value
1992 @}
1993 @end example
1997 @node Daemon Configuration
1998 @chapter Daemon Configuration
1999 @cindex initialization
2000 The commands here are commonly found in the openocd.cfg file and are
2001 used to specify what TCP/IP ports are used, and how GDB should be
2002 supported.
2004 @anchor{configurationstage}
2005 @section Configuration Stage
2006 @cindex configuration stage
2007 @cindex config command
2009 When the OpenOCD server process starts up, it enters a
2010 @emph{configuration stage} which is the only time that
2011 certain commands, @emph{configuration commands}, may be issued.
2012 Normally, configuration commands are only available
2013 inside startup scripts.
2015 In this manual, the definition of a configuration command is
2016 presented as a @emph{Config Command}, not as a @emph{Command}
2017 which may be issued interactively.
2018 The runtime @command{help} command also highlights configuration
2019 commands, and those which may be issued at any time.
2021 Those configuration commands include declaration of TAPs,
2022 flash banks,
2023 the interface used for JTAG communication,
2024 and other basic setup.
2025 The server must leave the configuration stage before it
2026 may access or activate TAPs.
2027 After it leaves this stage, configuration commands may no
2028 longer be issued.
2030 @anchor{enteringtherunstage}
2031 @section Entering the Run Stage
2033 The first thing OpenOCD does after leaving the configuration
2034 stage is to verify that it can talk to the scan chain
2035 (list of TAPs) which has been configured.
2036 It will warn if it doesn't find TAPs it expects to find,
2037 or finds TAPs that aren't supposed to be there.
2038 You should see no errors at this point.
2039 If you see errors, resolve them by correcting the
2040 commands you used to configure the server.
2041 Common errors include using an initial JTAG speed that's too
2042 fast, and not providing the right IDCODE values for the TAPs
2043 on the scan chain.
2045 Once OpenOCD has entered the run stage, a number of commands
2046 become available.
2047 A number of these relate to the debug targets you may have declared.
2048 For example, the @command{mww} command will not be available until
2049 a target has been successfuly instantiated.
2050 If you want to use those commands, you may need to force
2051 entry to the run stage.
2053 @deffn {Config Command} init
2054 This command terminates the configuration stage and
2055 enters the run stage. This helps when you need to have
2056 the startup scripts manage tasks such as resetting the target,
2057 programming flash, etc. To reset the CPU upon startup, add "init" and
2058 "reset" at the end of the config script or at the end of the OpenOCD
2059 command line using the @option{-c} command line switch.
2061 If this command does not appear in any startup/configuration file
2062 OpenOCD executes the command for you after processing all
2063 configuration files and/or command line options.
2065 @b{NOTE:} This command normally occurs at or near the end of your
2066 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2067 targets ready. For example: If your openocd.cfg file needs to
2068 read/write memory on your target, @command{init} must occur before
2069 the memory read/write commands. This includes @command{nand probe}.
2070 @end deffn
2072 @deffn {Overridable Procedure} jtag_init
2073 This is invoked at server startup to verify that it can talk
2074 to the scan chain (list of TAPs) which has been configured.
2076 The default implementation first tries @command{jtag arp_init},
2077 which uses only a lightweight JTAG reset before examining the
2078 scan chain.
2079 If that fails, it tries again, using a harder reset
2080 from the overridable procedure @command{init_reset}.
2082 Implementations must have verified the JTAG scan chain before
2083 they return.
2084 This is done by calling @command{jtag arp_init}
2085 (or @command{jtag arp_init-reset}).
2086 @end deffn
2088 @anchor{tcpipports}
2089 @section TCP/IP Ports
2090 @cindex TCP port
2091 @cindex server
2092 @cindex port
2093 @cindex security
2094 The OpenOCD server accepts remote commands in several syntaxes.
2095 Each syntax uses a different TCP/IP port, which you may specify
2096 only during configuration (before those ports are opened).
2098 For reasons including security, you may wish to prevent remote
2099 access using one or more of these ports.
2100 In such cases, just specify the relevant port number as zero.
2101 If you disable all access through TCP/IP, you will need to
2102 use the command line @option{-pipe} option.
2104 @deffn {Command} gdb_port [number]
2105 @cindex GDB server
2106 Normally gdb listens to a TCP/IP port, but GDB can also
2107 communicate via pipes(stdin/out or named pipes). The name
2108 "gdb_port" stuck because it covers probably more than 90% of
2109 the normal use cases.
2111 No arguments reports GDB port. "pipe" means listen to stdin
2112 output to stdout, an integer is base port number, "disable"
2113 disables the gdb server.
2115 When using "pipe", also use log_output to redirect the log
2116 output to a file so as not to flood the stdin/out pipes.
2118 The -p/--pipe option is deprecated and a warning is printed
2119 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2121 Any other string is interpreted as named pipe to listen to.
2122 Output pipe is the same name as input pipe, but with 'o' appended,
2123 e.g. /var/gdb, /var/gdbo.
2125 The GDB port for the first target will be the base port, the
2126 second target will listen on gdb_port + 1, and so on.
2127 When not specified during the configuration stage,
2128 the port @var{number} defaults to 3333.
2129 @end deffn
2131 @deffn {Command} tcl_port [number]
2132 Specify or query the port used for a simplified RPC
2133 connection that can be used by clients to issue TCL commands and get the
2134 output from the Tcl engine.
2135 Intended as a machine interface.
2136 When not specified during the configuration stage,
2137 the port @var{number} defaults to 6666.
2139 @end deffn
2141 @deffn {Command} telnet_port [number]
2142 Specify or query the
2143 port on which to listen for incoming telnet connections.
2144 This port is intended for interaction with one human through TCL commands.
2145 When not specified during the configuration stage,
2146 the port @var{number} defaults to 4444.
2147 When specified as zero, this port is not activated.
2148 @end deffn
2150 @anchor{gdbconfiguration}
2151 @section GDB Configuration
2152 @cindex GDB
2153 @cindex GDB configuration
2154 You can reconfigure some GDB behaviors if needed.
2155 The ones listed here are static and global.
2156 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2157 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2159 @anchor{gdbbreakpointoverride}
2160 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2161 Force breakpoint type for gdb @command{break} commands.
2162 This option supports GDB GUIs which don't
2163 distinguish hard versus soft breakpoints, if the default OpenOCD and
2164 GDB behaviour is not sufficient. GDB normally uses hardware
2165 breakpoints if the memory map has been set up for flash regions.
2166 @end deffn
2168 @anchor{gdbflashprogram}
2169 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2170 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2171 vFlash packet is received.
2172 The default behaviour is @option{enable}.
2173 @end deffn
2175 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2176 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2177 requested. GDB will then know when to set hardware breakpoints, and program flash
2178 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2179 for flash programming to work.
2180 Default behaviour is @option{enable}.
2181 @xref{gdbflashprogram,,gdb_flash_program}.
2182 @end deffn
2184 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2185 Specifies whether data aborts cause an error to be reported
2186 by GDB memory read packets.
2187 The default behaviour is @option{disable};
2188 use @option{enable} see these errors reported.
2189 @end deffn
2191 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2192 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2193 The default behaviour is @option{disable}.
2194 @end deffn
2196 @deffn {Command} gdb_save_tdesc
2197 Saves the target descripton file to the local file system.
2199 The file name is @i{target_name}.xml.
2200 @end deffn
2202 @anchor{eventpolling}
2203 @section Event Polling
2205 Hardware debuggers are parts of asynchronous systems,
2206 where significant events can happen at any time.
2207 The OpenOCD server needs to detect some of these events,
2208 so it can report them to through TCL command line
2209 or to GDB.
2211 Examples of such events include:
2213 @itemize
2214 @item One of the targets can stop running ... maybe it triggers
2215 a code breakpoint or data watchpoint, or halts itself.
2216 @item Messages may be sent over ``debug message'' channels ... many
2217 targets support such messages sent over JTAG,
2218 for receipt by the person debugging or tools.
2219 @item Loss of power ... some adapters can detect these events.
2220 @item Resets not issued through JTAG ... such reset sources
2221 can include button presses or other system hardware, sometimes
2222 including the target itself (perhaps through a watchdog).
2223 @item Debug instrumentation sometimes supports event triggering
2224 such as ``trace buffer full'' (so it can quickly be emptied)
2225 or other signals (to correlate with code behavior).
2226 @end itemize
2228 None of those events are signaled through standard JTAG signals.
2229 However, most conventions for JTAG connectors include voltage
2230 level and system reset (SRST) signal detection.
2231 Some connectors also include instrumentation signals, which
2232 can imply events when those signals are inputs.
2234 In general, OpenOCD needs to periodically check for those events,
2235 either by looking at the status of signals on the JTAG connector
2236 or by sending synchronous ``tell me your status'' JTAG requests
2237 to the various active targets.
2238 There is a command to manage and monitor that polling,
2239 which is normally done in the background.
2241 @deffn Command poll [@option{on}|@option{off}]
2242 Poll the current target for its current state.
2243 (Also, @pxref{targetcurstate,,target curstate}.)
2244 If that target is in debug mode, architecture
2245 specific information about the current state is printed.
2246 An optional parameter
2247 allows background polling to be enabled and disabled.
2249 You could use this from the TCL command shell, or
2250 from GDB using @command{monitor poll} command.
2251 Leave background polling enabled while you're using GDB.
2252 @example
2253 > poll
2254 background polling: on
2255 target state: halted
2256 target halted in ARM state due to debug-request, \
2257 current mode: Supervisor
2258 cpsr: 0x800000d3 pc: 0x11081bfc
2259 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2260 >
2261 @end example
2262 @end deffn
2264 @node Debug Adapter Configuration
2265 @chapter Debug Adapter Configuration
2266 @cindex config file, interface
2267 @cindex interface config file
2269 Correctly installing OpenOCD includes making your operating system give
2270 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2271 are used to select which one is used, and to configure how it is used.
2273 @quotation Note
2274 Because OpenOCD started out with a focus purely on JTAG, you may find
2275 places where it wrongly presumes JTAG is the only transport protocol
2276 in use. Be aware that recent versions of OpenOCD are removing that
2277 limitation. JTAG remains more functional than most other transports.
2278 Other transports do not support boundary scan operations, or may be
2279 specific to a given chip vendor. Some might be usable only for
2280 programming flash memory, instead of also for debugging.
2281 @end quotation
2283 Debug Adapters/Interfaces/Dongles are normally configured
2284 through commands in an interface configuration
2285 file which is sourced by your @file{openocd.cfg} file, or
2286 through a command line @option{-f interface/....cfg} option.
2288 @example
2289 source [find interface/olimex-jtag-tiny.cfg]
2290 @end example
2292 These commands tell
2293 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2294 A few cases are so simple that you only need to say what driver to use:
2296 @example
2297 # jlink interface
2298 interface jlink
2299 @end example
2301 Most adapters need a bit more configuration than that.
2304 @section Interface Configuration
2306 The interface command tells OpenOCD what type of debug adapter you are
2307 using. Depending on the type of adapter, you may need to use one or
2308 more additional commands to further identify or configure the adapter.
2310 @deffn {Config Command} {interface} name
2311 Use the interface driver @var{name} to connect to the
2312 target.
2313 @end deffn
2315 @deffn Command {interface_list}
2316 List the debug adapter drivers that have been built into
2317 the running copy of OpenOCD.
2318 @end deffn
2319 @deffn Command {interface transports} transport_name+
2320 Specifies the transports supported by this debug adapter.
2321 The adapter driver builds-in similar knowledge; use this only
2322 when external configuration (such as jumpering) changes what
2323 the hardware can support.
2324 @end deffn
2328 @deffn Command {adapter_name}
2329 Returns the name of the debug adapter driver being used.
2330 @end deffn
2332 @section Interface Drivers
2334 Each of the interface drivers listed here must be explicitly
2335 enabled when OpenOCD is configured, in order to be made
2336 available at run time.
2338 @deffn {Interface Driver} {amt_jtagaccel}
2339 Amontec Chameleon in its JTAG Accelerator configuration,
2340 connected to a PC's EPP mode parallel port.
2341 This defines some driver-specific commands:
2343 @deffn {Config Command} {parport_port} number
2344 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2345 the number of the @file{/dev/parport} device.
2346 @end deffn
2348 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2349 Displays status of RTCK option.
2350 Optionally sets that option first.
2351 @end deffn
2352 @end deffn
2354 @deffn {Interface Driver} {arm-jtag-ew}
2355 Olimex ARM-JTAG-EW USB adapter
2356 This has one driver-specific command:
2358 @deffn Command {armjtagew_info}
2359 Logs some status
2360 @end deffn
2361 @end deffn
2363 @deffn {Interface Driver} {at91rm9200}
2364 Supports bitbanged JTAG from the local system,
2365 presuming that system is an Atmel AT91rm9200
2366 and a specific set of GPIOs is used.
2367 @c command: at91rm9200_device NAME
2368 @c chooses among list of bit configs ... only one option
2369 @end deffn
2371 @deffn {Interface Driver} {cmsis-dap}
2372 ARM CMSIS-DAP compliant based adapter.
2374 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2375 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2376 the driver will attempt to auto detect the CMSIS-DAP device.
2377 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2378 @example
2379 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2380 @end example
2381 @end deffn
2383 @deffn {Config Command} {cmsis_dap_serial} [serial]
2384 Specifies the @var{serial} of the CMSIS-DAP device to use.
2385 If not specified, serial numbers are not considered.
2386 @end deffn
2388 @deffn {Command} {cmsis-dap info}
2389 Display various device information, like hardware version, firmware version, current bus status.
2390 @end deffn
2391 @end deffn
2393 @deffn {Interface Driver} {dummy}
2394 A dummy software-only driver for debugging.
2395 @end deffn
2397 @deffn {Interface Driver} {ep93xx}
2398 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2399 @end deffn
2401 @deffn {Interface Driver} {ft2232}
2402 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2404 Note that this driver has several flaws and the @command{ftdi} driver is
2405 recommended as its replacement.
2407 These interfaces have several commands, used to configure the driver
2408 before initializing the JTAG scan chain:
2410 @deffn {Config Command} {ft2232_device_desc} description
2411 Provides the USB device description (the @emph{iProduct string})
2412 of the FTDI FT2232 device. If not
2413 specified, the FTDI default value is used. This setting is only valid
2414 if compiled with FTD2XX support.
2415 @end deffn
2417 @deffn {Config Command} {ft2232_serial} serial-number
2418 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2419 in case the vendor provides unique IDs and more than one FT2232 device
2420 is connected to the host.
2421 If not specified, serial numbers are not considered.
2422 (Note that USB serial numbers can be arbitrary Unicode strings,
2423 and are not restricted to containing only decimal digits.)
2424 @end deffn
2426 @deffn {Config Command} {ft2232_layout} name
2427 Each vendor's FT2232 device can use different GPIO signals
2428 to control output-enables, reset signals, and LEDs.
2429 Currently valid layout @var{name} values include:
2430 @itemize @minus
2431 @item @b{axm0432_jtag} Axiom AXM-0432
2432 @item @b{comstick} Hitex STR9 comstick
2433 @item @b{cortino} Hitex Cortino JTAG interface
2434 @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
2435 either for the local Cortex-M3 (SRST only)
2436 or in a passthrough mode (neither SRST nor TRST)
2437 This layout can not support the SWO trace mechanism, and should be
2438 used only for older boards (before rev C).
2439 @item @b{luminary_icdi} This layout should be used with most TI/Luminary
2440 eval boards, including Rev C LM3S811 eval boards and the eponymous
2441 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2442 to debug some other target. It can support the SWO trace mechanism.
2443 @item @b{flyswatter} Tin Can Tools Flyswatter
2444 @item @b{icebear} ICEbear JTAG adapter from Section 5
2445 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2446 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2447 @item @b{m5960} American Microsystems M5960
2448 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2449 @item @b{oocdlink} OOCDLink
2450 @c oocdlink ~= jtagkey_prototype_v1
2451 @item @b{redbee-econotag} Integrated with a Redbee development board.
2452 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2453 @item @b{sheevaplug} Marvell Sheevaplug development kit
2454 @item @b{signalyzer} Xverve Signalyzer
2455 @item @b{stm32stick} Hitex STM32 Performance Stick
2456 @item @b{turtelizer2} egnite Software turtelizer2
2457 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2458 @end itemize
2459 @end deffn
2461 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2462 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2463 default values are used.
2464 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2465 @example
2466 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2467 @end example
2468 @end deffn
2470 @deffn {Config Command} {ft2232_latency} ms
2471 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2472 ft2232_read() fails to return the expected number of bytes. This can be caused by
2473 USB communication delays and has proved hard to reproduce and debug. Setting the
2474 FT2232 latency timer to a larger value increases delays for short USB packets but it
2475 also reduces the risk of timeouts before receiving the expected number of bytes.
2476 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2477 @end deffn
2479 @deffn {Config Command} {ft2232_channel} channel
2480 Used to select the channel of the ft2232 chip to use (between 1 and 4).
2481 The default value is 1.
2482 @end deffn
2484 For example, the interface config file for a
2485 Turtelizer JTAG Adapter looks something like this:
2487 @example
2488 interface ft2232
2489 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2490 ft2232_layout turtelizer2
2491 ft2232_vid_pid 0x0403 0xbdc8
2492 @end example
2493 @end deffn
2495 @deffn {Interface Driver} {ftdi}
2496 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2497 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2498 It is a complete rewrite to address a large number of problems with the ft2232
2499 interface driver.
2501 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2502 bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
2503 consistently faster than the ft2232 driver, sometimes several times faster.
2505 A major improvement of this driver is that support for new FTDI based adapters
2506 can be added competely through configuration files, without the need to patch
2507 and rebuild OpenOCD.
2509 The driver uses a signal abstraction to enable Tcl configuration files to
2510 define outputs for one or several FTDI GPIO. These outputs can then be
2511 controlled using the @command{ftdi_set_signal} command. Special signal names
2512 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2513 will be used for their customary purpose.
2515 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2516 be controlled differently. In order to support tristateable signals such as
2517 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2518 signal. The following output buffer configurations are supported:
2520 @itemize @minus
2521 @item Push-pull with one FTDI output as (non-)inverted data line
2522 @item Open drain with one FTDI output as (non-)inverted output-enable
2523 @item Tristate with one FTDI output as (non-)inverted data line and another
2524 FTDI output as (non-)inverted output-enable
2525 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2526 switching data and direction as necessary
2527 @end itemize
2529 These interfaces have several commands, used to configure the driver
2530 before initializing the JTAG scan chain:
2532 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2533 The vendor ID and product ID of the adapter. If not specified, the FTDI
2534 default values are used.
2535 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2536 @example
2537 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2538 @end example
2539 @end deffn
2541 @deffn {Config Command} {ftdi_device_desc} description
2542 Provides the USB device description (the @emph{iProduct string})
2543 of the adapter. If not specified, the device description is ignored
2544 during device selection.
2545 @end deffn
2547 @deffn {Config Command} {ftdi_serial} serial-number
2548 Specifies the @var{serial-number} of the adapter to use,
2549 in case the vendor provides unique IDs and more than one adapter
2550 is connected to the host.
2551 If not specified, serial numbers are not considered.
2552 (Note that USB serial numbers can be arbitrary Unicode strings,
2553 and are not restricted to containing only decimal digits.)
2554 @end deffn
2556 @deffn {Config Command} {ftdi_channel} channel
2557 Selects the channel of the FTDI device to use for MPSSE operations. Most
2558 adapters use the default, channel 0, but there are exceptions.
2559 @end deffn
2561 @deffn {Config Command} {ftdi_layout_init} data direction
2562 Specifies the initial values of the FTDI GPIO data and direction registers.
2563 Each value is a 16-bit number corresponding to the concatenation of the high
2564 and low FTDI GPIO registers. The values should be selected based on the
2565 schematics of the adapter, such that all signals are set to safe levels with
2566 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2567 and initially asserted reset signals.
2568 @end deffn
2570 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2571 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2572 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2573 register bitmasks to tell the driver the connection and type of the output
2574 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2575 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2576 used with inverting data inputs and @option{-data} with non-inverting inputs.
2577 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2578 not-output-enable) input to the output buffer is connected.
2580 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2581 simple open-collector transistor driver would be specified with @option{-oe}
2582 only. In that case the signal can only be set to drive low or to Hi-Z and the
2583 driver will complain if the signal is set to drive high. Which means that if
2584 it's a reset signal, @command{reset_config} must be specified as
2585 @option{srst_open_drain}, not @option{srst_push_pull}.
2587 A special case is provided when @option{-data} and @option{-oe} is set to the
2588 same bitmask. Then the FTDI pin is considered being connected straight to the
2589 target without any buffer. The FTDI pin is then switched between output and
2590 input as necessary to provide the full set of low, high and Hi-Z
2591 characteristics. In all other cases, the pins specified in a signal definition
2592 are always driven by the FTDI.
2594 If @option{-alias} or @option{-nalias} is used, the signal is created
2595 identical (or with data inverted) to an already specified signal
2596 @var{name}.
2597 @end deffn
2599 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2600 Set a previously defined signal to the specified level.
2601 @itemize @minus
2602 @item @option{0}, drive low
2603 @item @option{1}, drive high
2604 @item @option{z}, set to high-impedance
2605 @end itemize
2606 @end deffn
2608 For example adapter definitions, see the configuration files shipped in the
2609 @file{interface/ftdi} directory.
2610 @end deffn
2612 @deffn {Interface Driver} {remote_bitbang}
2613 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2614 with a remote process and sends ASCII encoded bitbang requests to that process
2615 instead of directly driving JTAG.
2617 The remote_bitbang driver is useful for debugging software running on
2618 processors which are being simulated.
2620 @deffn {Config Command} {remote_bitbang_port} number
2621 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2622 sockets instead of TCP.
2623 @end deffn
2625 @deffn {Config Command} {remote_bitbang_host} hostname
2626 Specifies the hostname of the remote process to connect to using TCP, or the
2627 name of the UNIX socket to use if remote_bitbang_port is 0.
2628 @end deffn
2630 For example, to connect remotely via TCP to the host foobar you might have
2631 something like:
2633 @example
2634 interface remote_bitbang
2635 remote_bitbang_port 3335
2636 remote_bitbang_host foobar
2637 @end example
2639 To connect to another process running locally via UNIX sockets with socket
2640 named mysocket:
2642 @example
2643 interface remote_bitbang
2644 remote_bitbang_port 0
2645 remote_bitbang_host mysocket
2646 @end example
2647 @end deffn
2649 @deffn {Interface Driver} {usb_blaster}
2650 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2651 for FTDI chips. These interfaces have several commands, used to
2652 configure the driver before initializing the JTAG scan chain:
2654 @deffn {Config Command} {usb_blaster_device_desc} description
2655 Provides the USB device description (the @emph{iProduct string})
2656 of the FTDI FT245 device. If not
2657 specified, the FTDI default value is used. This setting is only valid
2658 if compiled with FTD2XX support.
2659 @end deffn
2661 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2662 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2663 default values are used.
2664 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2665 Altera USB-Blaster (default):
2666 @example
2667 usb_blaster_vid_pid 0x09FB 0x6001
2668 @end example
2669 The following VID/PID is for Kolja Waschk's USB JTAG:
2670 @example
2671 usb_blaster_vid_pid 0x16C0 0x06AD
2672 @end example
2673 @end deffn
2675 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2676 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2677 female JTAG header). These pins can be used as SRST and/or TRST provided the
2678 appropriate connections are made on the target board.
2680 For example, to use pin 6 as SRST (as with an AVR board):
2681 @example
2682 $_TARGETNAME configure -event reset-assert \
2683 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2684 @end example
2685 @end deffn
2687 @end deffn
2689 @deffn {Interface Driver} {gw16012}
2690 Gateworks GW16012 JTAG programmer.
2691 This has one driver-specific command:
2693 @deffn {Config Command} {parport_port} [port_number]
2694 Display either the address of the I/O port
2695 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2696 If a parameter is provided, first switch to use that port.
2697 This is a write-once setting.
2698 @end deffn
2699 @end deffn
2701 @deffn {Interface Driver} {jlink}
2702 Segger J-Link family of USB adapters. It currently supports JTAG and SWD transports.
2704 @quotation Compatibility Note
2705 Segger released many firmware versions for the many harware versions they
2706 produced. OpenOCD was extensively tested and intended to run on all of them,
2707 but some combinations were reported as incompatible. As a general
2708 recommendation, it is advisable to use the latest firmware version
2709 available for each hardware version. However the current V8 is a moving
2710 target, and Segger firmware versions released after the OpenOCD was
2711 released may not be compatible. In such cases it is recommended to
2712 revert to the last known functional version. For 0.5.0, this is from
2713 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2714 version is from "May 3 2012 18:36:22", packed with 4.46f.
2715 @end quotation
2717 @deffn {Command} {jlink caps}
2718 Display the device firmware capabilities.
2719 @end deffn
2720 @deffn {Command} {jlink info}
2721 Display various device information, like hardware version, firmware version, current bus status.
2722 @end deffn
2723 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2724 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2725 @end deffn
2726 @deffn {Command} {jlink config}
2727 Display the J-Link configuration.
2728 @end deffn
2729 @deffn {Command} {jlink config kickstart} [val]
2730 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2731 @end deffn
2732 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2733 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2734 @end deffn
2735 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2736 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2737 E the bit of the subnet mask and
2738 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2739 @end deffn
2740 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2741 Set the USB address; this will also change the product id. Without argument, show the USB address.
2742 @end deffn
2743 @deffn {Command} {jlink config reset}
2744 Reset the current configuration.
2745 @end deffn
2746 @deffn {Command} {jlink config save}
2747 Save the current configuration to the internal persistent storage.
2748 @end deffn
2749 @deffn {Config} {jlink pid} val
2750 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2751 @end deffn
2752 @deffn {Config} {jlink serial} serial-number
2753 Set the @var{serial-number} of the interface, in case more than one adapter is connected to the host.
2754 If not specified, serial numbers are not considered.
2756 Note that there may be leading zeros in the @var{serial-number} string
2757 that will not show in the Segger software, but must be specified here.
2758 Debug level 3 output contains serial numbers if there is a mismatch.
2760 As a configuration command, it can be used only before 'init'.
2761 @end deffn
2762 @end deffn
2764 @deffn {Interface Driver} {parport}
2765 Supports PC parallel port bit-banging cables:
2766 Wigglers, PLD download cable, and more.
2767 These interfaces have several commands, used to configure the driver
2768 before initializing the JTAG scan chain:
2770 @deffn {Config Command} {parport_cable} name
2771 Set the layout of the parallel port cable used to connect to the target.
2772 This is a write-once setting.
2773 Currently valid cable @var{name} values include:
2775 @itemize @minus
2776 @item @b{altium} Altium Universal JTAG cable.
2777 @item @b{arm-jtag} Same as original wiggler except SRST and
2778 TRST connections reversed and TRST is also inverted.
2779 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2780 in configuration mode. This is only used to
2781 program the Chameleon itself, not a connected target.
2782 @item @b{dlc5} The Xilinx Parallel cable III.
2783 @item @b{flashlink} The ST Parallel cable.
2784 @item @b{lattice} Lattice ispDOWNLOAD Cable
2785 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2786 some versions of
2787 Amontec's Chameleon Programmer. The new version available from
2788 the website uses the original Wiggler layout ('@var{wiggler}')
2789 @item @b{triton} The parallel port adapter found on the
2790 ``Karo Triton 1 Development Board''.
2791 This is also the layout used by the HollyGates design
2792 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2793 @item @b{wiggler} The original Wiggler layout, also supported by
2794 several clones, such as the Olimex ARM-JTAG
2795 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2796 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2797 @end itemize
2798 @end deffn
2800 @deffn {Config Command} {parport_port} [port_number]
2801 Display either the address of the I/O port
2802 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2803 If a parameter is provided, first switch to use that port.
2804 This is a write-once setting.
2806 When using PPDEV to access the parallel port, use the number of the parallel port:
2807 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2808 you may encounter a problem.
2809 @end deffn
2811 @deffn Command {parport_toggling_time} [nanoseconds]
2812 Displays how many nanoseconds the hardware needs to toggle TCK;
2813 the parport driver uses this value to obey the
2814 @command{adapter_khz} configuration.
2815 When the optional @var{nanoseconds} parameter is given,
2816 that setting is changed before displaying the current value.
2818 The default setting should work reasonably well on commodity PC hardware.
2819 However, you may want to calibrate for your specific hardware.
2820 @quotation Tip
2821 To measure the toggling time with a logic analyzer or a digital storage
2822 oscilloscope, follow the procedure below:
2823 @example
2824 > parport_toggling_time 1000
2825 > adapter_khz 500
2826 @end example
2827 This sets the maximum JTAG clock speed of the hardware, but
2828 the actual speed probably deviates from the requested 500 kHz.
2829 Now, measure the time between the two closest spaced TCK transitions.
2830 You can use @command{runtest 1000} or something similar to generate a
2831 large set of samples.
2832 Update the setting to match your measurement:
2833 @example
2834 > parport_toggling_time <measured nanoseconds>
2835 @end example
2836 Now the clock speed will be a better match for @command{adapter_khz rate}
2837 commands given in OpenOCD scripts and event handlers.
2839 You can do something similar with many digital multimeters, but note
2840 that you'll probably need to run the clock continuously for several
2841 seconds before it decides what clock rate to show. Adjust the
2842 toggling time up or down until the measured clock rate is a good
2843 match for the adapter_khz rate you specified; be conservative.
2844 @end quotation
2845 @end deffn
2847 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2848 This will configure the parallel driver to write a known
2849 cable-specific value to the parallel interface on exiting OpenOCD.
2850 @end deffn
2852 For example, the interface configuration file for a
2853 classic ``Wiggler'' cable on LPT2 might look something like this:
2855 @example
2856 interface parport
2857 parport_port 0x278
2858 parport_cable wiggler
2859 @end example
2860 @end deffn
2862 @deffn {Interface Driver} {presto}
2863 ASIX PRESTO USB JTAG programmer.
2864 @deffn {Config Command} {presto_serial} serial_string
2865 Configures the USB serial number of the Presto device to use.
2866 @end deffn
2867 @end deffn
2869 @deffn {Interface Driver} {rlink}
2870 Raisonance RLink USB adapter
2871 @end deffn
2873 @deffn {Interface Driver} {usbprog}
2874 usbprog is a freely programmable USB adapter.
2875 @end deffn
2877 @deffn {Interface Driver} {vsllink}
2878 vsllink is part of Versaloon which is a versatile USB programmer.
2880 @quotation Note
2881 This defines quite a few driver-specific commands,
2882 which are not currently documented here.
2883 @end quotation
2884 @end deffn
2886 @anchor{hla_interface}
2887 @deffn {Interface Driver} {hla}
2888 This is a driver that supports multiple High Level Adapters.
2889 This type of adapter does not expose some of the lower level api's
2890 that OpenOCD would normally use to access the target.
2892 Currently supported adapters include the ST STLINK and TI ICDI.
2893 STLINK firmware version >= V2.J21.S4 recommended due to issues with earlier
2894 versions of firmware where serial number is reset after first use. Suggest
2895 using ST firmware update utility to upgrade STLINK firmware even if current
2896 version reported is V2.J21.S4.
2898 @deffn {Config Command} {hla_device_desc} description
2899 Currently Not Supported.
2900 @end deffn
2902 @deffn {Config Command} {hla_serial} serial
2903 Specifies the serial number of the adapter.
2904 @end deffn
2906 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
2907 Specifies the adapter layout to use.
2908 @end deffn
2910 @deffn {Config Command} {hla_vid_pid} vid pid
2911 The vendor ID and product ID of the device.
2912 @end deffn
2914 @deffn {Command} {hla_command} command
2915 Execute a custom adapter-specific command. The @var{command} string is
2916 passed as is to the underlying adapter layout handler.
2917 @end deffn
2918 @end deffn
2920 @deffn {Interface Driver} {opendous}
2921 opendous-jtag is a freely programmable USB adapter.
2922 @end deffn
2924 @deffn {Interface Driver} {ulink}
2925 This is the Keil ULINK v1 JTAG debugger.
2926 @end deffn
2928 @deffn {Interface Driver} {ZY1000}
2929 This is the Zylin ZY1000 JTAG debugger.
2930 @end deffn
2932 @quotation Note
2933 This defines some driver-specific commands,
2934 which are not currently documented here.
2935 @end quotation
2937 @deffn Command power [@option{on}|@option{off}]
2938 Turn power switch to target on/off.
2939 No arguments: print status.
2940 @end deffn
2942 @deffn {Interface Driver} {bcm2835gpio}
2943 This SoC is present in Raspberry Pi which is a cheap single-board computer
2944 exposing some GPIOs on its expansion header.
2946 The driver accesses memory-mapped GPIO peripheral registers directly
2947 for maximum performance, but the only possible race condition is for
2948 the pins' modes/muxing (which is highly unlikely), so it should be
2949 able to coexist nicely with both sysfs bitbanging and various
2950 peripherals' kernel drivers. The driver restores the previous
2951 configuration on exit.
2953 See @file{interface/raspberrypi-native.cfg} for a sample config and
2954 pinout.
2956 @end deffn
2958 @section Transport Configuration
2959 @cindex Transport
2960 As noted earlier, depending on the version of OpenOCD you use,
2961 and the debug adapter you are using,
2962 several transports may be available to
2963 communicate with debug targets (or perhaps to program flash memory).
2964 @deffn Command {transport list}
2965 displays the names of the transports supported by this
2966 version of OpenOCD.
2967 @end deffn
2969 @deffn Command {transport select} @option{transport_name}
2970 Select which of the supported transports to use in this OpenOCD session.
2972 When invoked with @option{transport_name}, attempts to select the named
2973 transport. The transport must be supported by the debug adapter
2974 hardware and by the version of OpenOCD you are using (including the
2975 adapter's driver).
2977 If no transport has been selected and no @option{transport_name} is
2978 provided, @command{transport select} auto-selects the first transport
2979 supported by the debug adapter.
2981 @command{transport select} always returns the name of the session's selected
2982 transport, if any.
2983 @end deffn
2985 @subsection JTAG Transport
2986 @cindex JTAG
2987 JTAG is the original transport supported by OpenOCD, and most
2988 of the OpenOCD commands support it.
2989 JTAG transports expose a chain of one or more Test Access Points (TAPs),
2990 each of which must be explicitly declared.
2991 JTAG supports both debugging and boundary scan testing.
2992 Flash programming support is built on top of debug support.
2994 JTAG transport is selected with the command @command{transport select
2995 jtag}. Unless your adapter uses @ref{hla_interface,the hla interface
2996 driver}, in which case the command is @command{transport select
2997 hla_jtag}.
2999 @subsection SWD Transport
3000 @cindex SWD
3001 @cindex Serial Wire Debug
3002 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3003 Debug Access Point (DAP, which must be explicitly declared.
3004 (SWD uses fewer signal wires than JTAG.)
3005 SWD is debug-oriented, and does not support boundary scan testing.
3006 Flash programming support is built on top of debug support.
3007 (Some processors support both JTAG and SWD.)
3009 SWD transport is selected with the command @command{transport select
3010 swd}. Unless your adapter uses @ref{hla_interface,the hla interface
3011 driver}, in which case the command is @command{transport select
3012 hla_swd}.
3014 @deffn Command {swd newdap} ...
3015 Declares a single DAP which uses SWD transport.
3016 Parameters are currently the same as "jtag newtap" but this is
3017 expected to change.
3018 @end deffn
3019 @deffn Command {swd wcr trn prescale}
3020 Updates TRN (turnaraound delay) and prescaling.fields of the
3021 Wire Control Register (WCR).
3022 No parameters: displays current settings.
3023 @end deffn
3025 @subsection SPI Transport
3026 @cindex SPI
3027 @cindex Serial Peripheral Interface
3028 The Serial Peripheral Interface (SPI) is a general purpose transport
3029 which uses four wire signaling. Some processors use it as part of a
3030 solution for flash programming.
3032 @anchor{jtagspeed}
3033 @section JTAG Speed
3034 JTAG clock setup is part of system setup.
3035 It @emph{does not belong with interface setup} since any interface
3036 only knows a few of the constraints for the JTAG clock speed.
3037 Sometimes the JTAG speed is
3038 changed during the target initialization process: (1) slow at
3039 reset, (2) program the CPU clocks, (3) run fast.
3040 Both the "slow" and "fast" clock rates are functions of the
3041 oscillators used, the chip, the board design, and sometimes
3042 power management software that may be active.
3044 The speed used during reset, and the scan chain verification which
3045 follows reset, can be adjusted using a @code{reset-start}
3046 target event handler.
3047 It can then be reconfigured to a faster speed by a
3048 @code{reset-init} target event handler after it reprograms those
3049 CPU clocks, or manually (if something else, such as a boot loader,
3050 sets up those clocks).
3051 @xref{targetevents,,Target Events}.
3052 When the initial low JTAG speed is a chip characteristic, perhaps
3053 because of a required oscillator speed, provide such a handler
3054 in the target config file.
3055 When that speed is a function of a board-specific characteristic
3056 such as which speed oscillator is used, it belongs in the board
3057 config file instead.
3058 In both cases it's safest to also set the initial JTAG clock rate
3059 to that same slow speed, so that OpenOCD never starts up using a
3060 clock speed that's faster than the scan chain can support.
3062 @example
3063 jtag_rclk 3000
3064 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3065 @end example
3067 If your system supports adaptive clocking (RTCK), configuring
3068 JTAG to use that is probably the most robust approach.
3069 However, it introduces delays to synchronize clocks; so it
3070 may not be the fastest solution.
3072 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3073 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3074 which support adaptive clocking.
3076 @deffn {Command} adapter_khz max_speed_kHz
3077 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3078 JTAG interfaces usually support a limited number of
3079 speeds. The speed actually used won't be faster
3080 than the speed specified.
3082 Chip data sheets generally include a top JTAG clock rate.
3083 The actual rate is often a function of a CPU core clock,
3084 and is normally less than that peak rate.
3085 For example, most ARM cores accept at most one sixth of the CPU clock.
3087 Speed 0 (khz) selects RTCK method.
3088 @xref{faqrtck,,FAQ RTCK}.
3089 If your system uses RTCK, you won't need to change the
3090 JTAG clocking after setup.
3091 Not all interfaces, boards, or targets support ``rtck''.
3092 If the interface device can not
3093 support it, an error is returned when you try to use RTCK.
3094 @end deffn
3096 @defun jtag_rclk fallback_speed_kHz
3097 @cindex adaptive clocking
3098 @cindex RTCK
3099 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3100 If that fails (maybe the interface, board, or target doesn't
3101 support it), falls back to the specified frequency.
3102 @example
3103 # Fall back to 3mhz if RTCK is not supported
3104 jtag_rclk 3000
3105 @end example
3106 @end defun
3108 @node Reset Configuration
3109 @chapter Reset Configuration
3110 @cindex Reset Configuration
3112 Every system configuration may require a different reset
3113 configuration. This can also be quite confusing.
3114 Resets also interact with @var{reset-init} event handlers,
3115 which do things like setting up clocks and DRAM, and
3116 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3117 They can also interact with JTAG routers.
3118 Please see the various board files for examples.
3120 @quotation Note
3121 To maintainers and integrators:
3122 Reset configuration touches several things at once.
3123 Normally the board configuration file
3124 should define it and assume that the JTAG adapter supports
3125 everything that's wired up to the board's JTAG connector.
3127 However, the target configuration file could also make note
3128 of something the silicon vendor has done inside the chip,
3129 which will be true for most (or all) boards using that chip.
3130 And when the JTAG adapter doesn't support everything, the
3131 user configuration file will need to override parts of
3132 the reset configuration provided by other files.
3133 @end quotation
3135 @section Types of Reset
3137 There are many kinds of reset possible through JTAG, but
3138 they may not all work with a given board and adapter.
3139 That's part of why reset configuration can be error prone.
3141 @itemize @bullet
3142 @item
3143 @emph{System Reset} ... the @emph{SRST} hardware signal
3144 resets all chips connected to the JTAG adapter, such as processors,
3145 power management chips, and I/O controllers. Normally resets triggered
3146 with this signal behave exactly like pressing a RESET button.
3147 @item
3148 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3149 just the TAP controllers connected to the JTAG adapter.
3150 Such resets should not be visible to the rest of the system; resetting a
3151 device's TAP controller just puts that controller into a known state.
3152 @item
3153 @emph{Emulation Reset} ... many devices can be reset through JTAG
3154 commands. These resets are often distinguishable from system
3155 resets, either explicitly (a "reset reason" register says so)
3156 or implicitly (not all parts of the chip get reset).
3157 @item
3158 @emph{Other Resets} ... system-on-chip devices often support
3159 several other types of reset.
3160 You may need to arrange that a watchdog timer stops
3161 while debugging, preventing a watchdog reset.
3162 There may be individual module resets.
3163 @end itemize
3165 In the best case, OpenOCD can hold SRST, then reset
3166 the TAPs via TRST and send commands through JTAG to halt the
3167 CPU at the reset vector before the 1st instruction is executed.
3168 Then when it finally releases the SRST signal, the system is
3169 halted under debugger control before any code has executed.
3170 This is the behavior required to support the @command{reset halt}
3171 and @command{reset init} commands; after @command{reset init} a
3172 board-specific script might do things like setting up DRAM.
3173 (@xref{resetcommand,,Reset Command}.)
3175 @anchor{srstandtrstissues}
3176 @section SRST and TRST Issues
3178 Because SRST and TRST are hardware signals, they can have a
3179 variety of system-specific constraints. Some of the most
3180 common issues are:
3182 @itemize @bullet
3184 @item @emph{Signal not available} ... Some boards don't wire
3185 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3186 support such signals even if they are wired up.
3187 Use the @command{reset_config} @var{signals} options to say
3188 when either of those signals is not connected.
3189 When SRST is not available, your code might not be able to rely
3190 on controllers having been fully reset during code startup.
3191 Missing TRST is not a problem, since JTAG-level resets can
3192 be triggered using with TMS signaling.
3194 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3195 adapter will connect SRST to TRST, instead of keeping them separate.
3196 Use the @command{reset_config} @var{combination} options to say
3197 when those signals aren't properly independent.
3199 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3200 delay circuit, reset supervisor, or on-chip features can extend
3201 the effect of a JTAG adapter's reset for some time after the adapter
3202 stops issuing the reset. For example, there may be chip or board
3203 requirements that all reset pulses last for at least a
3204 certain amount of time; and reset buttons commonly have
3205 hardware debouncing.
3206 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3207 commands to say when extra delays are needed.
3209 @item @emph{Drive type} ... Reset lines often have a pullup
3210 resistor, letting the JTAG interface treat them as open-drain
3211 signals. But that's not a requirement, so the adapter may need
3212 to use push/pull output drivers.
3213 Also, with weak pullups it may be advisable to drive
3214 signals to both levels (push/pull) to minimize rise times.
3215 Use the @command{reset_config} @var{trst_type} and
3216 @var{srst_type} parameters to say how to drive reset signals.
3218 @item @emph{Special initialization} ... Targets sometimes need
3219 special JTAG initialization sequences to handle chip-specific
3220 issues (not limited to errata).
3221 For example, certain JTAG commands might need to be issued while
3222 the system as a whole is in a reset state (SRST active)
3223 but the JTAG scan chain is usable (TRST inactive).
3224 Many systems treat combined assertion of SRST and TRST as a
3225 trigger for a harder reset than SRST alone.
3226 Such custom reset handling is discussed later in this chapter.
3227 @end itemize
3229 There can also be other issues.
3230 Some devices don't fully conform to the JTAG specifications.
3231 Trivial system-specific differences are common, such as
3232 SRST and TRST using slightly different names.
3233 There are also vendors who distribute key JTAG documentation for
3234 their chips only to developers who have signed a Non-Disclosure
3235 Agreement (NDA).
3237 Sometimes there are chip-specific extensions like a requirement to use
3238 the normally-optional TRST signal (precluding use of JTAG adapters which
3239 don't pass TRST through), or needing extra steps to complete a TAP reset.
3241 In short, SRST and especially TRST handling may be very finicky,
3242 needing to cope with both architecture and board specific constraints.
3244 @section Commands for Handling Resets
3246 @deffn {Command} adapter_nsrst_assert_width milliseconds
3247 Minimum amount of time (in milliseconds) OpenOCD should wait
3248 after asserting nSRST (active-low system reset) before
3249 allowing it to be deasserted.
3250 @end deffn
3252 @deffn {Command} adapter_nsrst_delay milliseconds
3253 How long (in milliseconds) OpenOCD should wait after deasserting
3254 nSRST (active-low system reset) before starting new JTAG operations.
3255 When a board has a reset button connected to SRST line it will
3256 probably have hardware debouncing, implying you should use this.
3257 @end deffn
3259 @deffn {Command} jtag_ntrst_assert_width milliseconds
3260 Minimum amount of time (in milliseconds) OpenOCD should wait
3261 after asserting nTRST (active-low JTAG TAP reset) before
3262 allowing it to be deasserted.
3263 @end deffn
3265 @deffn {Command} jtag_ntrst_delay milliseconds
3266 How long (in milliseconds) OpenOCD should wait after deasserting
3267 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3268 @end deffn
3270 @deffn {Command} reset_config mode_flag ...
3271 This command displays or modifies the reset configuration
3272 of your combination of JTAG board and target in target
3273 configuration scripts.
3275 Information earlier in this section describes the kind of problems
3276 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3277 As a rule this command belongs only in board config files,
3278 describing issues like @emph{board doesn't connect TRST};
3279 or in user config files, addressing limitations derived
3280 from a particular combination of interface and board.
3281 (An unlikely example would be using a TRST-only adapter
3282 with a board that only wires up SRST.)
3284 The @var{mode_flag} options can be specified in any order, but only one
3285 of each type -- @var{signals}, @var{combination}, @var{gates},
3286 @var{trst_type}, @var{srst_type} and @var{connect_type}
3287 -- may be specified at a time.
3288 If you don't provide a new value for a given type, its previous
3289 value (perhaps the default) is unchanged.
3290 For example, this means that you don't need to say anything at all about
3291 TRST just to declare that if the JTAG adapter should want to drive SRST,
3292 it must explicitly be driven high (@option{srst_push_pull}).
3294 @itemize
3295 @item
3296 @var{signals} can specify which of the reset signals are connected.
3297 For example, If the JTAG interface provides SRST, but the board doesn't
3298 connect that signal properly, then OpenOCD can't use it.
3299 Possible values are @option{none} (the default), @option{trst_only},
3300 @option{srst_only} and @option{trst_and_srst}.
3302 @quotation Tip
3303 If your board provides SRST and/or TRST through the JTAG connector,
3304 you must declare that so those signals can be used.
3305 @end quotation
3307 @item
3308 The @var{combination} is an optional value specifying broken reset
3309 signal implementations.
3310 The default behaviour if no option given is @option{separate},
3311 indicating everything behaves normally.
3312 @option{srst_pulls_trst} states that the
3313 test logic is reset together with the reset of the system (e.g. NXP
3314 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3315 the system is reset together with the test logic (only hypothetical, I
3316 haven't seen hardware with such a bug, and can be worked around).
3317 @option{combined} implies both @option{srst_pulls_trst} and
3318 @option{trst_pulls_srst}.
3320 @item
3321 The @var{gates} tokens control flags that describe some cases where
3322 JTAG may be unvailable during reset.
3323 @option{srst_gates_jtag} (default)
3324 indicates that asserting SRST gates the
3325 JTAG clock. This means that no communication can happen on JTAG
3326 while SRST is asserted.
3327 Its converse is @option{srst_nogate}, indicating that JTAG commands
3328 can safely be issued while SRST is active.
3330 @item
3331 The @var{connect_type} tokens control flags that describe some cases where
3332 SRST is asserted while connecting to the target. @option{srst_nogate}
3333 is required to use this option.
3334 @option{connect_deassert_srst} (default)
3335 indicates that SRST will not be asserted while connecting to the target.
3336 Its converse is @option{connect_assert_srst}, indicating that SRST will
3337 be asserted before any target connection.
3338 Only some targets support this feature, STM32 and STR9 are examples.
3339 This feature is useful if you are unable to connect to your target due
3340 to incorrect options byte config or illegal program execution.
3341 @end itemize
3343 The optional @var{trst_type} and @var{srst_type} parameters allow the
3344 driver mode of each reset line to be specified. These values only affect
3345 JTAG interfaces with support for different driver modes, like the Amontec
3346 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3347 relevant signal (TRST or SRST) is not connected.
3349 @itemize
3350 @item
3351 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3352 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3353 Most boards connect this signal to a pulldown, so the JTAG TAPs
3354 never leave reset unless they are hooked up to a JTAG adapter.
3356 @item
3357 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3358 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3359 Most boards connect this signal to a pullup, and allow the
3360 signal to be pulled low by various events including system
3361 powerup and pressing a reset button.
3362 @end itemize
3363 @end deffn
3365 @section Custom Reset Handling
3366 @cindex events
3368 OpenOCD has several ways to help support the various reset
3369 mechanisms provided by chip and board vendors.
3370 The commands shown in the previous section give standard parameters.
3371 There are also @emph{event handlers} associated with TAPs or Targets.
3372 Those handlers are Tcl procedures you can provide, which are invoked
3373 at particular points in the reset sequence.
3375 @emph{When SRST is not an option} you must set
3376 up a @code{reset-assert} event handler for your target.
3377 For example, some JTAG adapters don't include the SRST signal;
3378 and some boards have multiple targets, and you won't always
3379 want to reset everything at once.
3381 After configuring those mechanisms, you might still
3382 find your board doesn't start up or reset correctly.
3383 For example, maybe it needs a slightly different sequence
3384 of SRST and/or TRST manipulations, because of quirks that
3385 the @command{reset_config} mechanism doesn't address;
3386 or asserting both might trigger a stronger reset, which
3387 needs special attention.
3389 Experiment with lower level operations, such as @command{jtag_reset}
3390 and the @command{jtag arp_*} operations shown here,
3391 to find a sequence of operations that works.
3392 @xref{JTAG Commands}.
3393 When you find a working sequence, it can be used to override
3394 @command{jtag_init}, which fires during OpenOCD startup
3395 (@pxref{configurationstage,,Configuration Stage});
3396 or @command{init_reset}, which fires during reset processing.
3398 You might also want to provide some project-specific reset
3399 schemes. For example, on a multi-target board the standard
3400 @command{reset} command would reset all targets, but you
3401 may need the ability to reset only one target at time and
3402 thus want to avoid using the board-wide SRST signal.
3404 @deffn {Overridable Procedure} init_reset mode
3405 This is invoked near the beginning of the @command{reset} command,
3406 usually to provide as much of a cold (power-up) reset as practical.
3407 By default it is also invoked from @command{jtag_init} if
3408 the scan chain does not respond to pure JTAG operations.
3409 The @var{mode} parameter is the parameter given to the
3410 low level reset command (@option{halt},
3411 @option{init}, or @option{run}), @option{setup},
3412 or potentially some other value.
3414 The default implementation just invokes @command{jtag arp_init-reset}.
3415 Replacements will normally build on low level JTAG
3416 operations such as @command{jtag_reset}.
3417 Operations here must not address individual TAPs
3418 (or their associated targets)
3419 until the JTAG scan chain has first been verified to work.
3421 Implementations must have verified the JTAG scan chain before
3422 they return.
3423 This is done by calling @command{jtag arp_init}
3424 (or @command{jtag arp_init-reset}).
3425 @end deffn
3427 @deffn Command {jtag arp_init}
3428 This validates the scan chain using just the four
3429 standard JTAG signals (TMS, TCK, TDI, TDO).
3430 It starts by issuing a JTAG-only reset.
3431 Then it performs checks to verify that the scan chain configuration
3432 matches the TAPs it can observe.
3433 Those checks include checking IDCODE values for each active TAP,
3434 and verifying the length of their instruction registers using
3435 TAP @code{-ircapture} and @code{-irmask} values.
3436 If these tests all pass, TAP @code{setup} events are
3437 issued to all TAPs with handlers for that event.
3438 @end deffn
3440 @deffn Command {jtag arp_init-reset}
3441 This uses TRST and SRST to try resetting
3442 everything on the JTAG scan chain
3443 (and anything else connected to SRST).
3444 It then invokes the logic of @command{jtag arp_init}.
3445 @end deffn
3448 @node TAP Declaration
3449 @chapter TAP Declaration
3450 @cindex TAP declaration
3451 @cindex TAP configuration
3453 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3454 TAPs serve many roles, including:
3456 @itemize @bullet
3457 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3458 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3459 Others do it indirectly, making a CPU do it.
3460 @item @b{Program Download} Using the same CPU support GDB uses,
3461 you can initialize a DRAM controller, download code to DRAM, and then
3462 start running that code.
3463 @item @b{Boundary Scan} Most chips support boundary scan, which
3464 helps test for board assembly problems like solder bridges
3465 and missing connections.
3466 @end itemize
3468 OpenOCD must know about the active TAPs on your board(s).
3469 Setting up the TAPs is the core task of your configuration files.
3470 Once those TAPs are set up, you can pass their names to code
3471 which sets up CPUs and exports them as GDB targets,
3472 probes flash memory, performs low-level JTAG operations, and more.
3474 @section Scan Chains
3475 @cindex scan chain
3477 TAPs are part of a hardware @dfn{scan chain},
3478 which is a daisy chain of TAPs.
3479 They also need to be added to
3480 OpenOCD's software mirror of that hardware list,
3481 giving each member a name and associating other data with it.
3482 Simple scan chains, with a single TAP, are common in
3483 systems with a single microcontroller or microprocessor.
3484 More complex chips may have several TAPs internally.
3485 Very complex scan chains might have a dozen or more TAPs:
3486 several in one chip, more in the next, and connecting
3487 to other boards with their own chips and TAPs.
3489 You can display the list with the @command{scan_chain} command.
3490 (Don't confuse this with the list displayed by the @command{targets}
3491 command, presented in the next chapter.
3492 That only displays TAPs for CPUs which are configured as
3493 debugging targets.)
3494 Here's what the scan chain might look like for a chip more than one TAP:
3496 @verbatim
3497 TapName Enabled IdCode Expected IrLen IrCap IrMask
3498 -- ------------------ ------- ---------- ---------- ----- ----- ------
3499 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3500 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3501 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3502 @end verbatim
3504 OpenOCD can detect some of that information, but not all
3505 of it. @xref{autoprobing,,Autoprobing}.
3506 Unfortunately, those TAPs can't always be autoconfigured,
3507 because not all devices provide good support for that.
3508 JTAG doesn't require supporting IDCODE instructions, and
3509 chips with JTAG routers may not link TAPs into the chain
3510 until they are told to do so.
3512 The configuration mechanism currently supported by OpenOCD
3513 requires explicit configuration of all TAP devices using
3514 @command{jtag newtap} commands, as detailed later in this chapter.
3515 A command like this would declare one tap and name it @code{chip1.cpu}:
3517 @example
3518 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3519 @end example
3521 Each target configuration file lists the TAPs provided
3522 by a given chip.
3523 Board configuration files combine all the targets on a board,
3524 and so forth.
3525 Note that @emph{the order in which TAPs are declared is very important.}
3526 That declaration order must match the order in the JTAG scan chain,
3527 both inside a single chip and between them.
3528 @xref{faqtaporder,,FAQ TAP Order}.
3530 For example, the ST Microsystems STR912 chip has
3531 three separate TAPs@footnote{See the ST
3532 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3533 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3534 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3535 To configure those taps, @file{target/str912.cfg}
3536 includes commands something like this:
3538 @example
3539 jtag newtap str912 flash ... params ...
3540 jtag newtap str912 cpu ... params ...
3541 jtag newtap str912 bs ... params ...
3542 @end example
3544 Actual config files typically use a variable such as @code{$_CHIPNAME}
3545 instead of literals like @option{str912}, to support more than one chip
3546 of each type. @xref{Config File Guidelines}.
3548 @deffn Command {jtag names}
3549 Returns the names of all current TAPs in the scan chain.
3550 Use @command{jtag cget} or @command{jtag tapisenabled}
3551 to examine attributes and state of each TAP.
3552 @example
3553 foreach t [jtag names] @{
3554 puts [format "TAP: %s\n" $t]
3555 @}
3556 @end example
3557 @end deffn
3559 @deffn Command {scan_chain}
3560 Displays the TAPs in the scan chain configuration,
3561 and their status.
3562 The set of TAPs listed by this command is fixed by
3563 exiting the OpenOCD configuration stage,
3564 but systems with a JTAG router can
3565 enable or disable TAPs dynamically.
3566 @end deffn
3568 @c FIXME! "jtag cget" should be able to return all TAP
3569 @c attributes, like "$target_name cget" does for targets.
3571 @c Probably want "jtag eventlist", and a "tap-reset" event
3572 @c (on entry to RESET state).
3574 @section TAP Names
3575 @cindex dotted name
3577 When TAP objects are declared with @command{jtag newtap},
3578 a @dfn{dotted.name} is created for the TAP, combining the
3579 name of a module (usually a chip) and a label for the TAP.
3580 For example: @code{xilinx.tap}, @code{str912.flash},
3581 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3582 Many other commands use that dotted.name to manipulate or
3583 refer to the TAP. For example, CPU configuration uses the
3584 name, as does declaration of NAND or NOR flash banks.
3586 The components of a dotted name should follow ``C'' symbol
3587 name rules: start with an alphabetic character, then numbers
3588 and underscores are OK; while others (including dots!) are not.
3590 @section TAP Declaration Commands
3592 @c shouldn't this be(come) a {Config Command}?
3593 @deffn Command {jtag newtap} chipname tapname configparams...
3594 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3595 and configured according to the various @var{configparams}.
3597 The @var{chipname} is a symbolic name for the chip.
3598 Conventionally target config files use @code{$_CHIPNAME},
3599 defaulting to the model name given by the chip vendor but
3600 overridable.
3602 @cindex TAP naming convention
3603 The @var{tapname} reflects the role of that TAP,
3604 and should follow this convention:
3606 @itemize @bullet
3607 @item @code{bs} -- For boundary scan if this is a separate TAP;
3608 @item @code{cpu} -- The main CPU of the chip, alternatively
3609 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3610 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3611 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3612 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3613 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3614 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3615 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3616 with a single TAP;
3617 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3618 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3619 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3620 a JTAG TAP; that TAP should be named @code{sdma}.
3621 @end itemize
3623 Every TAP requires at least the following @var{configparams}:
3625 @itemize @bullet
3626 @item @code{-irlen} @var{NUMBER}
3627 @*The length in bits of the
3628 instruction register, such as 4 or 5 bits.
3629 @end itemize
3631 A TAP may also provide optional @var{configparams}:
3633 @itemize @bullet
3634 @item @code{-disable} (or @code{-enable})
3635 @*Use the @code{-disable} parameter to flag a TAP which is not
3636 linked into the scan chain after a reset using either TRST
3637 or the JTAG state machine's @sc{reset} state.
3638 You may use @code{-enable} to highlight the default state
3639 (the TAP is linked in).
3640 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3641 @item @code{-expected-id} @var{NUMBER}
3642 @*A non-zero @var{number} represents a 32-bit IDCODE
3643 which you expect to find when the scan chain is examined.
3644 These codes are not required by all JTAG devices.
3645 @emph{Repeat the option} as many times as required if more than one
3646 ID code could appear (for example, multiple versions).
3647 Specify @var{number} as zero to suppress warnings about IDCODE
3648 values that were found but not included in the list.
3650 Provide this value if at all possible, since it lets OpenOCD
3651 tell when the scan chain it sees isn't right. These values
3652 are provided in vendors' chip documentation, usually a technical
3653 reference manual. Sometimes you may need to probe the JTAG
3654 hardware to find these values.
3655 @xref{autoprobing,,Autoprobing}.
3656 @item @code{-ignore-version}
3657 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3658 option. When vendors put out multiple versions of a chip, or use the same
3659 JTAG-level ID for several largely-compatible chips, it may be more practical
3660 to ignore the version field than to update config files to handle all of
3661 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3662 @item @code{-ircapture} @var{NUMBER}
3663 @*The bit pattern loaded by the TAP into the JTAG shift register
3664 on entry to the @sc{ircapture} state, such as 0x01.
3665 JTAG requires the two LSBs of this value to be 01.
3666 By default, @code{-ircapture} and @code{-irmask} are set
3667 up to verify that two-bit value. You may provide
3668 additional bits if you know them, or indicate that
3669 a TAP doesn't conform to the JTAG specification.
3670 @item @code{-irmask} @var{NUMBER}
3671 @*A mask used with @code{-ircapture}
3672 to verify that instruction scans work correctly.
3673 Such scans are not used by OpenOCD except to verify that
3674 there seems to be no problems with JTAG scan chain operations.
3675 @end itemize
3676 @end deffn
3678 @section Other TAP commands
3680 @deffn Command {jtag cget} dotted.name @option{-event} event_name
3681 @deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
3682 At this writing this TAP attribute
3683 mechanism is used only for event handling.
3684 (It is not a direct analogue of the @code{cget}/@code{configure}
3685 mechanism for debugger targets.)
3686 See the next section for information about the available events.
3688 The @code{configure} subcommand assigns an event handler,
3689 a TCL string which is evaluated when the event is triggered.
3690 The @code{cget} subcommand returns that handler.
3691 @end deffn
3693 @section TAP Events
3694 @cindex events
3695 @cindex TAP events
3697 OpenOCD includes two event mechanisms.
3698 The one presented here applies to all JTAG TAPs.
3699 The other applies to debugger targets,
3700 which are associated with certain TAPs.
3702 The TAP events currently defined are:
3704 @itemize @bullet
3705 @item @b{post-reset}
3706 @* The TAP has just completed a JTAG reset.
3707 The tap may still be in the JTAG @sc{reset} state.
3708 Handlers for these events might perform initialization sequences
3709 such as issuing TCK cycles, TMS sequences to ensure
3710 exit from the ARM SWD mode, and more.
3712 Because the scan chain has not yet been verified, handlers for these events
3713 @emph{should not issue commands which scan the JTAG IR or DR registers}
3714 of any particular target.
3715 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3716 @item @b{setup}
3717 @* The scan chain has been reset and verified.
3718 This handler may enable TAPs as needed.
3719 @item @b{tap-disable}
3720 @* The TAP needs to be disabled. This handler should
3721 implement @command{jtag tapdisable}
3722 by issuing the relevant JTAG commands.
3723 @item @b{tap-enable}
3724 @* The TAP needs to be enabled. This handler should
3725 implement @command{jtag tapenable}
3726 by issuing the relevant JTAG commands.
3727 @end itemize
3729 If you need some action after each JTAG reset which isn't actually
3730 specific to any TAP (since you can't yet trust the scan chain's
3731 contents to be accurate), you might:
3733 @example
3734 jtag configure CHIP.jrc -event post-reset @{
3735 echo "JTAG Reset done"
3736 ... non-scan jtag operations to be done after reset
3737 @}
3738 @end example
3741 @anchor{enablinganddisablingtaps}
3742 @section Enabling and Disabling TAPs
3743 @cindex JTAG Route Controller
3744 @cindex jrc
3746 In some systems, a @dfn{JTAG Route Controller} (JRC)
3747 is used to enable and/or disable specific JTAG TAPs.
3748 Many ARM-based chips from Texas Instruments include
3749 an ``ICEPick'' module, which is a JRC.
3750 Such chips include DaVinci and OMAP3 processors.
3752 A given TAP may not be visible until the JRC has been
3753 told to link it into the scan chain; and if the JRC
3754 has been told to unlink that TAP, it will no longer
3755 be visible.
3756 Such routers address problems that JTAG ``bypass mode''
3757 ignores, such as:
3759 @itemize
3760 @item The scan chain can only go as fast as its slowest TAP.
3761 @item Having many TAPs slows instruction scans, since all
3762 TAPs receive new instructions.
3763 @item TAPs in the scan chain must be powered up, which wastes
3764 power and prevents debugging some power management mechanisms.
3765 @end itemize
3767 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3768 as implied by the existence of JTAG routers.
3769 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3770 does include a kind of JTAG router functionality.
3772 @c (a) currently the event handlers don't seem to be able to
3773 @c fail in a way that could lead to no-change-of-state.
3775 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3776 shown below, and is implemented using TAP event handlers.
3777 So for example, when defining a TAP for a CPU connected to
3778 a JTAG router, your @file{target.cfg} file
3779 should define TAP event handlers using
3780 code that looks something like this:
3782 @example
3783 jtag configure CHIP.cpu -event tap-enable @{
3784 ... jtag operations using CHIP.jrc
3785 @}
3786 jtag configure CHIP.cpu -event tap-disable @{
3787 ... jtag operations using CHIP.jrc
3788 @}
3789 @end example
3791 Then you might want that CPU's TAP enabled almost all the time:
3793 @example
3794 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3795 @end example
3797 Note how that particular setup event handler declaration
3798 uses quotes to evaluate @code{$CHIP} when the event is configured.
3799 Using brackets @{ @} would cause it to be evaluated later,
3800 at runtime, when it might have a different value.
3802 @deffn Command {jtag tapdisable} dotted.name
3803 If necessary, disables the tap
3804 by sending it a @option{tap-disable} event.
3805 Returns the string "1" if the tap
3806 specified by @var{dotted.name} is enabled,
3807 and "0" if it is disabled.
3808 @end deffn
3810 @deffn Command {jtag tapenable} dotted.name
3811 If necessary, enables the tap
3812 by sending it a @option{tap-enable} event.
3813 Returns the string "1" if the tap
3814 specified by @var{dotted.name} is enabled,
3815 and "0" if it is disabled.
3816 @end deffn
3818 @deffn Command {jtag tapisenabled} dotted.name
3819 Returns the string "1" if the tap
3820 specified by @var{dotted.name} is enabled,
3821 and "0" if it is disabled.
3823 @quotation Note
3824 Humans will find the @command{scan_chain} command more helpful
3825 for querying the state of the JTAG taps.
3826 @end quotation
3827 @end deffn
3829 @anchor{autoprobing}
3830 @section Autoprobing
3831 @cindex autoprobe
3832 @cindex JTAG autoprobe
3834 TAP configuration is the first thing that needs to be done
3835 after interface and reset configuration. Sometimes it's
3836 hard finding out what TAPs exist, or how they are identified.
3837 Vendor documentation is not always easy to find and use.
3839 To help you get past such problems, OpenOCD has a limited
3840 @emph{autoprobing} ability to look at the scan chain, doing
3841 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3842 To use this mechanism, start the OpenOCD server with only data
3843 that configures your JTAG interface, and arranges to come up
3844 with a slow clock (many devices don't support fast JTAG clocks
3845 right when they come out of reset).
3847 For example, your @file{openocd.cfg} file might have:
3849 @example
3850 source [find interface/olimex-arm-usb-tiny-h.cfg]
3851 reset_config trst_and_srst
3852 jtag_rclk 8
3853 @end example
3855 When you start the server without any TAPs configured, it will
3856 attempt to autoconfigure the TAPs. There are two parts to this:
3858 @enumerate
3859 @item @emph{TAP discovery} ...
3860 After a JTAG reset (sometimes a system reset may be needed too),
3861 each TAP's data registers will hold the contents of either the
3862 IDCODE or BYPASS register.
3863 If JTAG communication is working, OpenOCD will see each TAP,
3864 and report what @option{-expected-id} to use with it.
3865 @item @emph{IR Length discovery} ...
3866 Unfortunately JTAG does not provide a reliable way to find out
3867 the value of the @option{-irlen} parameter to use with a TAP
3868 that is discovered.
3869 If OpenOCD can discover the length of a TAP's instruction
3870 register, it will report it.
3871 Otherwise you may need to consult vendor documentation, such
3872 as chip data sheets or BSDL files.
3873 @end enumerate
3875 In many cases your board will have a simple scan chain with just
3876 a single device. Here's what OpenOCD reported with one board
3877 that's a bit more complex:
3879 @example
3880 clock speed 8 kHz
3881 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3882 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3883 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3884 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3885 AUTO auto0.tap - use "... -irlen 4"
3886 AUTO auto1.tap - use "... -irlen 4"
3887 AUTO auto2.tap - use "... -irlen 6"
3888 no gdb ports allocated as no target has been specified
3889 @end example
3891 Given that information, you should be able to either find some existing
3892 config files to use, or create your own. If you create your own, you
3893 would configure from the bottom up: first a @file{target.cfg} file
3894 with these TAPs, any targets associated with them, and any on-chip
3895 resources; then a @file{board.cfg} with off-chip resources, clocking,
3896 and so forth.
3898 @node CPU Configuration
3899 @chapter CPU Configuration
3900 @cindex GDB target
3902 This chapter discusses how to set up GDB debug targets for CPUs.
3903 You can also access these targets without GDB
3904 (@pxref{Architecture and Core Commands},
3905 and @ref{targetstatehandling,,Target State handling}) and
3906 through various kinds of NAND and NOR flash commands.
3907 If you have multiple CPUs you can have multiple such targets.
3909 We'll start by looking at how to examine the targets you have,
3910 then look at how to add one more target and how to configure it.
3912 @section Target List
3913 @cindex target, current
3914 @cindex target, list
3916 All targets that have been set up are part of a list,
3917 where each member has a name.
3918 That name should normally be the same as the TAP name.
3919 You can display the list with the @command{targets}
3920 (plural!) command.
3921 This display often has only one CPU; here's what it might
3922 look like with more than one:
3923 @verbatim
3924 TargetName Type Endian TapName State
3925 -- ------------------ ---------- ------ ------------------ ------------
3926 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
3927 1 MyTarget cortex_m little mychip.foo tap-disabled
3928 @end verbatim
3930 One member of that list is the @dfn{current target}, which
3931 is implicitly referenced by many commands.
3932 It's the one marked with a @code{*} near the target name.
3933 In particular, memory addresses often refer to the address
3934 space seen by that current target.
3935 Commands like @command{mdw} (memory display words)
3936 and @command{flash erase_address} (erase NOR flash blocks)
3937 are examples; and there are many more.
3939 Several commands let you examine the list of targets:
3941 @deffn Command {target current}
3942 Returns the name of the current target.
3943 @end deffn
3945 @deffn Command {target names}
3946 Lists the names of all current targets in the list.
3947 @example
3948 foreach t [target names] @{
3949 puts [format "Target: %s\n" $t]
3950 @}
3951 @end example
3952 @end deffn
3954 @c yep, "target list" would have been better.
3955 @c plus maybe "target setdefault".
3957 @deffn Command targets [name]
3958 @emph{Note: the name of this command is plural. Other target
3959 command names are singular.}
3961 With no parameter, this command displays a table of all known
3962 targets in a user friendly form.
3964 With a parameter, this command sets the current target to
3965 the given target with the given @var{name}; this is
3966 only relevant on boards which have more than one target.
3967 @end deffn
3969 @section Target CPU Types
3970 @cindex target type
3971 @cindex CPU type
3973 Each target has a @dfn{CPU type}, as shown in the output of
3974 the @command{targets} command. You need to specify that type
3975 when calling @command{target create}.
3976 The CPU type indicates more than just the instruction set.
3977 It also indicates how that instruction set is implemented,
3978 what kind of debug support it integrates,
3979 whether it has an MMU (and if so, what kind),
3980 what core-specific commands may be available
3981 (@pxref{Architecture and Core Commands}),
3982 and more.
3984 It's easy to see what target types are supported,
3985 since there's a command to list them.
3987 @anchor{targettypes}
3988 @deffn Command {target types}
3989 Lists all supported target types.
3990 At this writing, the supported CPU types are:
3992 @itemize @bullet
3993 @item @code{arm11} -- this is a generation of ARMv6 cores
3994 @item @code{arm720t} -- this is an ARMv4 core with an MMU
3995 @item @code{arm7tdmi} -- this is an ARMv4 core
3996 @item @code{arm920t} -- this is an ARMv4 core with an MMU
3997 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
3998 @item @code{arm966e} -- this is an ARMv5 core
3999 @item @code{arm9tdmi} -- this is an ARMv4 core
4000 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4001 (Support for this is preliminary and incomplete.)
4002 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4003 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4004 compact Thumb2 instruction set.
4005 @item @code{dragonite} -- resembles arm966e
4006 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4007 (Support for this is still incomplete.)
4008 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4009 @item @code{feroceon} -- resembles arm926
4010 @item @code{mips_m4k} -- a MIPS core
4011 @item @code{xscale} -- this is actually an architecture,
4012 not a CPU type. It is based on the ARMv5 architecture.
4013 @item @code{openrisc} -- this is an OpenRISC 1000 core.
4014 The current implementation supports three JTAG TAP cores:
4015 @itemize @minus
4016 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag})
4017 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4018 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4019 @end itemize
4020 And two debug interfaces cores:
4021 @itemize @minus
4022 @item @code{Advanced debug interface} (See: @url{http://opencores.org/project,adv_debug_sys})
4023 @item @code{SoC Debug Interface} (See: @url{http://opencores.org/project,dbg_interface})
4024 @end itemize
4025 @end itemize
4026 @end deffn
4028 To avoid being confused by the variety of ARM based cores, remember
4029 this key point: @emph{ARM is a technology licencing company}.
4030 (See: @url{http://www.arm.com}.)
4031 The CPU name used by OpenOCD will reflect the CPU design that was
4032 licenced, not a vendor brand which incorporates that design.
4033 Name prefixes like arm7, arm9, arm11, and cortex
4034 reflect design generations;
4035 while names like ARMv4, ARMv5, ARMv6, and ARMv7
4036 reflect an architecture version implemented by a CPU design.
4038 @anchor{targetconfiguration}
4039 @section Target Configuration
4041 Before creating a ``target'', you must have added its TAP to the scan chain.
4042 When you've added that TAP, you will have a @code{dotted.name}
4043 which is used to set up the CPU support.
4044 The chip-specific configuration file will normally configure its CPU(s)
4045 right after it adds all of the chip's TAPs to the scan chain.
4047 Although you can set up a target in one step, it's often clearer if you
4048 use shorter commands and do it in two steps: create it, then configure
4049 optional parts.
4050 All operations on the target after it's created will use a new
4051 command, created as part of target creation.
4053 The two main things to configure after target creation are
4054 a work area, which usually has target-specific defaults even
4055 if the board setup code overrides them later;
4056 and event handlers (@pxref{targetevents,,Target Events}), which tend
4057 to be much more board-specific.
4058 The key steps you use might look something like this
4060 @example
4061 target create MyTarget cortex_m -chain-position mychip.cpu
4062 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4063 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4064 $MyTarget configure -event reset-init @{ myboard_reinit @}
4065 @end example
4067 You should specify a working area if you can; typically it uses some
4068 on-chip SRAM.
4069 Such a working area can speed up many things, including bulk
4070 writes to target memory;
4071 flash operations like checking to see if memory needs to be erased;
4072 GDB memory checksumming;
4073 and more.
4075 @quotation Warning
4076 On more complex chips, the work area can become
4077 inaccessible when application code
4078 (such as an operating system)
4079 enables or disables the MMU.
4080 For example, the particular MMU context used to acess the virtual
4081 address will probably matter ... and that context might not have
4082 easy access to other addresses needed.
4083 At this writing, OpenOCD doesn't have much MMU intelligence.
4084 @end quotation
4086 It's often very useful to define a @code{reset-init} event handler.
4087 For systems that are normally used with a boot loader,
4088 common tasks include updating clocks and initializing memory
4089 controllers.
4090 That may be needed to let you write the boot loader into flash,
4091 in order to ``de-brick'' your board; or to load programs into
4092 external DDR memory without having run the boot loader.
4094 @deffn Command {target create} target_name type configparams...
4095 This command creates a GDB debug target that refers to a specific JTAG tap.
4096 It enters that target into a list, and creates a new
4097 command (@command{@var{target_name}}) which is used for various
4098 purposes including additional configuration.
4100 @itemize @bullet
4101 @item @var{target_name} ... is the name of the debug target.
4102 By convention this should be the same as the @emph{dotted.name}
4103 of the TAP associated with this target, which must be specified here
4104 using the @code{-chain-position @var{dotted.name}} configparam.
4106 This name is also used to create the target object command,
4107 referred to here as @command{$target_name},
4108 and in other places the target needs to be identified.
4109 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4110 @item @var{configparams} ... all parameters accepted by
4111 @command{$target_name configure} are permitted.
4112 If the target is big-endian, set it here with @code{-endian big}.
4114 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
4115 @end itemize
4116 @end deffn
4118 @deffn Command {$target_name configure} configparams...
4119 The options accepted by this command may also be
4120 specified as parameters to @command{target create}.
4121 Their values can later be queried one at a time by
4122 using the @command{$target_name cget} command.
4124 @emph{Warning:} changing some of these after setup is dangerous.
4125 For example, moving a target from one TAP to another;
4126 and changing its endianness.
4128 @itemize @bullet
4130 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4131 used to access this target.
4133 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4134 whether the CPU uses big or little endian conventions
4136 @item @code{-event} @var{event_name} @var{event_body} --
4137 @xref{targetevents,,Target Events}.
4138 Note that this updates a list of named event handlers.
4139 Calling this twice with two different event names assigns
4140 two different handlers, but calling it twice with the
4141 same event name assigns only one handler.
4143 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4144 whether the work area gets backed up; by default,
4145 @emph{it is not backed up.}
4146 When possible, use a working_area that doesn't need to be backed up,
4147 since performing a backup slows down operations.
4148 For example, the beginning of an SRAM block is likely to
4149 be used by most build systems, but the end is often unused.
4151 @item @code{-work-area-size} @var{size} -- specify work are size,
4152 in bytes. The same size applies regardless of whether its physical
4153 or virtual address is being used.
4155 @item @code{-work-area-phys} @var{address} -- set the work area
4156 base @var{address} to be used when no MMU is active.
4158 @item @code{-work-area-virt} @var{address} -- set the work area
4159 base @var{address} to be used when an MMU is active.
4160 @emph{Do not specify a value for this except on targets with an MMU.}
4161 The value should normally correspond to a static mapping for the
4162 @code{-work-area-phys} address, set up by the current operating system.
4164 @anchor{rtostype}
4165 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4166 @var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}|
4167 @option{FreeRTOS}|@option{linux}|@option{ChibiOS}|@option{embKernel}|@option{mqx}
4168 @xref{gdbrtossupport,,RTOS Support}.
4170 @end itemize
4171 @end deffn
4173 @section Other $target_name Commands
4174 @cindex object command
4176 The Tcl/Tk language has the concept of object commands,
4177 and OpenOCD adopts that same model for targets.
4179 A good Tk example is a on screen button.
4180 Once a button is created a button
4181 has a name (a path in Tk terms) and that name is useable as a first
4182 class command. For example in Tk, one can create a button and later
4183 configure it like this:
4185 @example
4186 # Create
4187 button .foobar -background red -command @{ foo @}
4188 # Modify
4189 .foobar configure -foreground blue
4190 # Query
4191 set x [.foobar cget -background]
4192 # Report
4193 puts [format "The button is %s" $x]
4194 @end example
4196 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4197 button, and its object commands are invoked the same way.
4199 @example
4200 str912.cpu mww 0x1234 0x42
4201 omap3530.cpu mww 0x5555 123
4202 @end example
4204 The commands supported by OpenOCD target objects are:
4206 @deffn Command {$target_name arp_examine}
4207 @deffnx Command {$target_name arp_halt}
4208 @deffnx Command {$target_name arp_poll}
4209 @deffnx Command {$target_name arp_reset}
4210 @deffnx Command {$target_name arp_waitstate}
4211 Internal OpenOCD scripts (most notably @file{startup.tcl})
4212 use these to deal with specific reset cases.
4213 They are not otherwise documented here.
4214 @end deffn
4216 @deffn Command {$target_name array2mem} arrayname width address count
4217 @deffnx Command {$target_name mem2array} arrayname width address count
4218 These provide an efficient script-oriented interface to memory.
4219 The @code{array2mem} primitive writes bytes, halfwords, or words;
4220 while @code{mem2array} reads them.
4221 In both cases, the TCL side uses an array, and
4222 the target side uses raw memory.
4224 The efficiency comes from enabling the use of
4225 bulk JTAG data transfer operations.
4226 The script orientation comes from working with data
4227 values that are packaged for use by TCL scripts;
4228 @command{mdw} type primitives only print data they retrieve,
4229 and neither store nor return those values.
4231 @itemize
4232 @item @var{arrayname} ... is the name of an array variable
4233 @item @var{width} ... is 8/16/32 - indicating the memory access size
4234 @item @var{address} ... is the target memory address
4235 @item @var{count} ... is the number of elements to process
4236 @end itemize
4237 @end deffn
4239 @deffn Command {$target_name cget} queryparm
4240 Each configuration parameter accepted by
4241 @command{$target_name configure}
4242 can be individually queried, to return its current value.
4243 The @var{queryparm} is a parameter name
4244 accepted by that command, such as @code{-work-area-phys}.
4245 There are a few special cases:
4247 @itemize @bullet
4248 @item @code{-event} @var{event_name} -- returns the handler for the
4249 event named @var{event_name}.
4250 This is a special case because setting a handler requires
4251 two parameters.
4252 @item @code{-type} -- returns the target type.
4253 This is a special case because this is set using
4254 @command{target create} and can't be changed
4255 using @command{$target_name configure}.
4256 @end itemize
4258 For example, if you wanted to summarize information about
4259 all the targets you might use something like this:
4261 @example
4262 foreach name [target names] @{
4263 set y [$name cget -endian]
4264 set z [$name cget -type]
4265 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4266 $x $name $y $z]
4267 @}
4268 @end example
4269 @end deffn
4271 @anchor{targetcurstate}
4272 @deffn Command {$target_name curstate}
4273 Displays the current target state:
4274 @code{debug-running},
4275 @code{halted},
4276 @code{reset},
4277 @code{running}, or @code{unknown}.
4278 (Also, @pxref{eventpolling,,Event Polling}.)
4279 @end deffn
4281 @deffn Command {$target_name eventlist}
4282 Displays a table listing all event handlers
4283 currently associated with this target.
4284 @xref{targetevents,,Target Events}.
4285 @end deffn
4287 @deffn Command {$target_name invoke-event} event_name
4288 Invokes the handler for the event named @var{event_name}.
4289 (This is primarily intended for use by OpenOCD framework
4290 code, for example by the reset code in @file{startup.tcl}.)
4291 @end deffn
4293 @deffn Command {$target_name mdw} addr [count]
4294 @deffnx Command {$target_name mdh} addr [count]
4295 @deffnx Command {$target_name mdb} addr [count]
4296 Display contents of address @var{addr}, as
4297 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4298 or 8-bit bytes (@command{mdb}).
4299 If @var{count} is specified, displays that many units.
4300 (If you want to manipulate the data instead of displaying it,
4301 see the @code{mem2array} primitives.)
4302 @end deffn
4304 @deffn Command {$target_name mww} addr word
4305 @deffnx Command {$target_name mwh} addr halfword
4306 @deffnx Command {$target_name mwb} addr byte
4307 Writes the specified @var{word} (32 bits),
4308 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4309 at the specified address @var{addr}.
4310 @end deffn
4312 @anchor{targetevents}
4313 @section Target Events
4314 @cindex target events
4315 @cindex events
4316 At various times, certain things can happen, or you want them to happen.
4317 For example:
4318 @itemize @bullet
4319 @item What should happen when GDB connects? Should your target reset?
4320 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4321 @item Is using SRST appropriate (and possible) on your system?
4322 Or instead of that, do you need to issue JTAG commands to trigger reset?
4323 SRST usually resets everything on the scan chain, which can be inappropriate.
4324 @item During reset, do you need to write to certain memory locations
4325 to set up system clocks or
4326 to reconfigure the SDRAM?
4327 How about configuring the watchdog timer, or other peripherals,
4328 to stop running while you hold the core stopped for debugging?
4329 @end itemize
4331 All of the above items can be addressed by target event handlers.
4332 These are set up by @command{$target_name configure -event} or
4333 @command{target create ... -event}.
4335 The programmer's model matches the @code{-command} option used in Tcl/Tk
4336 buttons and events. The two examples below act the same, but one creates
4337 and invokes a small procedure while the other inlines it.
4339 @example
4340 proc my_attach_proc @{ @} @{
4341 echo "Reset..."
4342 reset halt
4343 @}
4344 mychip.cpu configure -event gdb-attach my_attach_proc
4345 mychip.cpu configure -event gdb-attach @{
4346 echo "Reset..."
4347 # To make flash probe and gdb load to flash work
4348 # we need a reset init.
4349 reset init
4350 @}
4351 @end example
4353 The following target events are defined:
4355 @itemize @bullet
4356 @item @b{debug-halted}
4357 @* The target has halted for debug reasons (i.e.: breakpoint)
4358 @item @b{debug-resumed}
4359 @* The target has resumed (i.e.: gdb said run)
4360 @item @b{early-halted}
4361 @* Occurs early in the halt process
4362 @item @b{examine-start}
4363 @* Before target examine is called.
4364 @item @b{examine-end}
4365 @* After target examine is called with no errors.
4366 @item @b{gdb-attach}
4367 @* When GDB connects. This is before any communication with the target, so this
4368 can be used to set up the target so it is possible to probe flash. Probing flash
4369 is necessary during gdb connect if gdb load is to write the image to flash. Another
4370 use of the flash memory map is for GDB to automatically hardware/software breakpoints
4371 depending on whether the breakpoint is in RAM or read only memory.
4372 @item @b{gdb-detach}
4373 @* When GDB disconnects
4374 @item @b{gdb-end}
4375 @* When the target has halted and GDB is not doing anything (see early halt)
4376 @item @b{gdb-flash-erase-start}
4377 @* Before the GDB flash process tries to erase the flash (default is
4378 @code{reset init})
4379 @item @b{gdb-flash-erase-end}
4380 @* After the GDB flash process has finished erasing the flash
4381 @item @b{gdb-flash-write-start}
4382 @* Before GDB writes to the flash
4383 @item @b{gdb-flash-write-end}
4384 @* After GDB writes to the flash (default is @code{reset halt})
4385 @item @b{gdb-start}
4386 @* Before the target steps, gdb is trying to start/resume the target
4387 @item @b{halted}
4388 @* The target has halted
4389 @item @b{reset-assert-pre}
4390 @* Issued as part of @command{reset} processing
4391 after @command{reset_init} was triggered
4392 but before either SRST alone is re-asserted on the scan chain,
4393 or @code{reset-assert} is triggered.
4394 @item @b{reset-assert}
4395 @* Issued as part of @command{reset} processing
4396 after @command{reset-assert-pre} was triggered.
4397 When such a handler is present, cores which support this event will use
4398 it instead of asserting SRST.
4399 This support is essential for debugging with JTAG interfaces which
4400 don't include an SRST line (JTAG doesn't require SRST), and for
4401 selective reset on scan chains that have multiple targets.
4402 @item @b{reset-assert-post}
4403 @* Issued as part of @command{reset} processing
4404 after @code{reset-assert} has been triggered.
4405 or the target asserted SRST on the entire scan chain.
4406 @item @b{reset-deassert-pre}
4407 @* Issued as part of @command{reset} processing
4408 after @code{reset-assert-post} has been triggered.
4409 @item @b{reset-deassert-post}
4410 @* Issued as part of @command{reset} processing
4411 after @code{reset-deassert-pre} has been triggered
4412 and (if the target is using it) after SRST has been
4413 released on the scan chain.
4414 @item @b{reset-end}
4415 @* Issued as the final step in @command{reset} processing.
4416 @ignore
4417 @item @b{reset-halt-post}
4418 @* Currently not used
4419 @item @b{reset-halt-pre}
4420 @* Currently not used
4421 @end ignore
4422 @item @b{reset-init}
4423 @* Used by @b{reset init} command for board-specific initialization.
4424 This event fires after @emph{reset-deassert-post}.
4426 This is where you would configure PLLs and clocking, set up DRAM so
4427 you can download programs that don't fit in on-chip SRAM, set up pin
4428 multiplexing, and so on.
4429 (You may be able to switch to a fast JTAG clock rate here, after
4430 the target clocks are fully set up.)
4431 @item @b{reset-start}
4432 @* Issued as part of @command{reset} processing
4433 before @command{reset_init} is called.
4435 This is the most robust place to use @command{jtag_rclk}
4436 or @command{adapter_khz} to switch to a low JTAG clock rate,
4437 when reset disables PLLs needed to use a fast clock.
4438 @ignore
4439 @item @b{reset-wait-pos}
4440 @* Currently not used
4441 @item @b{reset-wait-pre}
4442 @* Currently not used
4443 @end ignore
4444 @item @b{resume-start}
4445 @* Before any target is resumed
4446 @item @b{resume-end}
4447 @* After all targets have resumed
4448 @item @b{resumed}
4449 @* Target has resumed
4450 @item @b{trace-config}
4451 @* After target hardware trace configuration was changed
4452 @end itemize
4454 @node Flash Commands
4455 @chapter Flash Commands
4457 OpenOCD has different commands for NOR and NAND flash;
4458 the ``flash'' command works with NOR flash, while
4459 the ``nand'' command works with NAND flash.
4460 This partially reflects different hardware technologies:
4461 NOR flash usually supports direct CPU instruction and data bus access,
4462 while data from a NAND flash must be copied to memory before it can be
4463 used. (SPI flash must also be copied to memory before use.)
4464 However, the documentation also uses ``flash'' as a generic term;
4465 for example, ``Put flash configuration in board-specific files''.
4467 Flash Steps:
4468 @enumerate
4469 @item Configure via the command @command{flash bank}
4470 @* Do this in a board-specific configuration file,
4471 passing parameters as needed by the driver.
4472 @item Operate on the flash via @command{flash subcommand}
4473 @* Often commands to manipulate the flash are typed by a human, or run
4474 via a script in some automated way. Common tasks include writing a
4475 boot loader, operating system, or other data.
4476 @item GDB Flashing
4477 @* Flashing via GDB requires the flash be configured via ``flash
4478 bank'', and the GDB flash features be enabled.
4479 @xref{gdbconfiguration,,GDB Configuration}.
4480 @end enumerate
4482 Many CPUs have the ablity to ``boot'' from the first flash bank.
4483 This means that misprogramming that bank can ``brick'' a system,
4484 so that it can't boot.
4485 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4486 board by (re)installing working boot firmware.
4488 @anchor{norconfiguration}
4489 @section Flash Configuration Commands
4490 @cindex flash configuration
4492 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4493 Configures a flash bank which provides persistent storage
4494 for addresses from @math{base} to @math{base + size - 1}.
4495 These banks will often be visible to GDB through the target's memory map.
4496 In some cases, configuring a flash bank will activate extra commands;
4497 see the driver-specific documentation.
4499 @itemize @bullet
4500 @item @var{name} ... may be used to reference the flash bank
4501 in other flash commands. A number is also available.
4502 @item @var{driver} ... identifies the controller driver
4503 associated with the flash bank being declared.
4504 This is usually @code{cfi} for external flash, or else
4505 the name of a microcontroller with embedded flash memory.
4506 @xref{flashdriverlist,,Flash Driver List}.
4507 @item @var{base} ... Base address of the flash chip.
4508 @item @var{size} ... Size of the chip, in bytes.
4509 For some drivers, this value is detected from the hardware.
4510 @item @var{chip_width} ... Width of the flash chip, in bytes;
4511 ignored for most microcontroller drivers.
4512 @item @var{bus_width} ... Width of the data bus used to access the
4513 chip, in bytes; ignored for most microcontroller drivers.
4514 @item @var{target} ... Names the target used to issue
4515 commands to the flash controller.
4516 @comment Actually, it's currently a controller-specific parameter...
4517 @item @var{driver_options} ... drivers may support, or require,
4518 additional parameters. See the driver-specific documentation
4519 for more information.
4520 @end itemize
4521 @quotation Note
4522 This command is not available after OpenOCD initialization has completed.
4523 Use it in board specific configuration files, not interactively.
4524 @end quotation
4525 @end deffn
4527 @comment the REAL name for this command is "ocd_flash_banks"
4528 @comment less confusing would be: "flash list" (like "nand list")
4529 @deffn Command {flash banks}
4530 Prints a one-line summary of each device that was
4531 declared using @command{flash bank}, numbered from zero.
4532 Note that this is the @emph{plural} form;
4533 the @emph{singular} form is a very different command.
4534 @end deffn
4536 @deffn Command {flash list}
4537 Retrieves a list of associative arrays for each device that was
4538 declared using @command{flash bank}, numbered from zero.
4539 This returned list can be manipulated easily from within scripts.
4540 @end deffn
4542 @deffn Command {flash probe} num
4543 Identify the flash, or validate the parameters of the configured flash. Operation
4544 depends on the flash type.
4545 The @var{num} parameter is a value shown by @command{flash banks}.
4546 Most flash commands will implicitly @emph{autoprobe} the bank;
4547 flash drivers can distinguish between probing and autoprobing,
4548 but most don't bother.
4549 @end deffn
4551 @section Erasing, Reading, Writing to Flash
4552 @cindex flash erasing
4553 @cindex flash reading
4554 @cindex flash writing
4555 @cindex flash programming
4556 @anchor{flashprogrammingcommands}
4558 One feature distinguishing NOR flash from NAND or serial flash technologies
4559 is that for read access, it acts exactly like any other addressible memory.
4560 This means you can use normal memory read commands like @command{mdw} or
4561 @command{dump_image} with it, with no special @command{flash} subcommands.
4562 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
4564 Write access works differently. Flash memory normally needs to be erased
4565 before it's written. Erasing a sector turns all of its bits to ones, and
4566 writing can turn ones into zeroes. This is why there are special commands
4567 for interactive erasing and writing, and why GDB needs to know which parts
4568 of the address space hold NOR flash memory.
4570 @quotation Note
4571 Most of these erase and write commands leverage the fact that NOR flash
4572 chips consume target address space. They implicitly refer to the current
4573 JTAG target, and map from an address in that target's address space
4574 back to a flash bank.
4575 @comment In May 2009, those mappings may fail if any bank associated
4576 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
4577 A few commands use abstract addressing based on bank and sector numbers,
4578 and don't depend on searching the current target and its address space.
4579 Avoid confusing the two command models.
4580 @end quotation
4582 Some flash chips implement software protection against accidental writes,
4583 since such buggy writes could in some cases ``brick'' a system.
4584 For such systems, erasing and writing may require sector protection to be
4585 disabled first.
4586 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4587 and AT91SAM7 on-chip flash.
4588 @xref{flashprotect,,flash protect}.
4590 @deffn Command {flash erase_sector} num first last
4591 Erase sectors in bank @var{num}, starting at sector @var{first}
4592 up to and including @var{last}.
4593 Sector numbering starts at 0.
4594 Providing a @var{last} sector of @option{last}
4595 specifies "to the end of the flash bank".
4596 The @var{num} parameter is a value shown by @command{flash banks}.
4597 @end deffn
4599 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4600 Erase sectors starting at @var{address} for @var{length} bytes.
4601 Unless @option{pad} is specified, @math{address} must begin a
4602 flash sector, and @math{address + length - 1} must end a sector.
4603 Specifying @option{pad} erases extra data at the beginning and/or
4604 end of the specified region, as needed to erase only full sectors.
4605 The flash bank to use is inferred from the @var{address}, and
4606 the specified length must stay within that bank.
4607 As a special case, when @var{length} is zero and @var{address} is
4608 the start of the bank, the whole flash is erased.
4609 If @option{unlock} is specified, then the flash is unprotected
4610 before erase starts.
4611 @end deffn
4613 @deffn Command {flash fillw} address word length
4614 @deffnx Command {flash fillh} address halfword length
4615 @deffnx Command {flash fillb} address byte length
4616 Fills flash memory with the specified @var{word} (32 bits),
4617 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4618 starting at @var{address} and continuing
4619 for @var{length} units (word/halfword/byte).
4620 No erasure is done before writing; when needed, that must be done
4621 before issuing this command.
4622 Writes are done in blocks of up to 1024 bytes, and each write is
4623 verified by reading back the data and comparing it to what was written.
4624 The flash bank to use is inferred from the @var{address} of
4625 each block, and the specified length must stay within that bank.
4626 @end deffn
4627 @comment no current checks for errors if fill blocks touch multiple banks!
4629 @deffn Command {flash write_bank} num filename offset
4630 Write the binary @file{filename} to flash bank @var{num},
4631 starting at @var{offset} bytes from the beginning of the bank.
4632 The @var{num} parameter is a value shown by @command{flash banks}.
4633 @end deffn
4635 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4636 Write the image @file{filename} to the current target's flash bank(s).
4637 Only loadable sections from the image are written.
4638 A relocation @var{offset} may be specified, in which case it is added
4639 to the base address for each section in the image.
4640 The file [@var{type}] can be specified
4641 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4642 @option{elf} (ELF file), @option{s19} (Motorola s19).
4643 @option{mem}, or @option{builder}.
4644 The relevant flash sectors will be erased prior to programming
4645 if the @option{erase} parameter is given. If @option{unlock} is
4646 provided, then the flash banks are unlocked before erase and
4647 program. The flash bank to use is inferred from the address of
4648 each image section.
4650 @quotation Warning
4651 Be careful using the @option{erase} flag when the flash is holding
4652 data you want to preserve.
4653 Portions of the flash outside those described in the image's
4654 sections might be erased with no notice.
4655 @itemize
4656 @item
4657 When a section of the image being written does not fill out all the
4658 sectors it uses, the unwritten parts of those sectors are necessarily
4659 also erased, because sectors can't be partially erased.
4660 @item
4661 Data stored in sector "holes" between image sections are also affected.
4662 For example, "@command{flash write_image erase ...}" of an image with
4663 one byte at the beginning of a flash bank and one byte at the end
4664 erases the entire bank -- not just the two sectors being written.
4665 @end itemize
4666 Also, when flash protection is important, you must re-apply it after
4667 it has been removed by the @option{unlock} flag.
4668 @end quotation
4670 @end deffn
4672 @section Other Flash commands
4673 @cindex flash protection
4675 @deffn Command {flash erase_check} num
4676 Check erase state of sectors in flash bank @var{num},
4677 and display that status.
4678 The @var{num} parameter is a value shown by @command{flash banks}.
4679 @end deffn
4681 @deffn Command {flash info} num
4682 Print info about flash bank @var{num}
4683 The @var{num} parameter is a value shown by @command{flash banks}.
4684 This command will first query the hardware, it does not print cached
4685 and possibly stale information.
4686 @end deffn
4688 @anchor{flashprotect}
4689 @deffn Command {flash protect} num first last (@option{on}|@option{off})
4690 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
4691 in flash bank @var{num}, starting at sector @var{first}
4692 and continuing up to and including @var{last}.
4693 Providing a @var{last} sector of @option{last}
4694 specifies "to the end of the flash bank".
4695 The @var{num} parameter is a value shown by @command{flash banks}.
4696 @end deffn
4698 @deffn Command {flash padded_value} num value
4699 Sets the default value used for padding any image sections, This should
4700 normally match the flash bank erased value. If not specified by this
4701 comamnd or the flash driver then it defaults to 0xff.
4702 @end deffn
4704 @anchor{program}
4705 @deffn Command {program} filename [verify] [reset] [exit] [offset]
4706 This is a helper script that simplifies using OpenOCD as a standalone
4707 programmer. The only required parameter is @option{filename}, the others are optional.
4708 @xref{Flash Programming}.
4709 @end deffn
4711 @anchor{flashdriverlist}
4712 @section Flash Driver List
4713 As noted above, the @command{flash bank} command requires a driver name,
4714 and allows driver-specific options and behaviors.
4715 Some drivers also activate driver-specific commands.
4717 @deffn {Flash Driver} virtual
4718 This is a special driver that maps a previously defined bank to another
4719 address. All bank settings will be copied from the master physical bank.
4721 The @var{virtual} driver defines one mandatory parameters,
4723 @itemize
4724 @item @var{master_bank} The bank that this virtual address refers to.
4725 @end itemize
4727 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
4728 the flash bank defined at address 0x1fc00000. Any cmds executed on
4729 the virtual banks are actually performed on the physical banks.
4730 @example
4731 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
4732 flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
4733 flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
4734 @end example
4735 @end deffn
4737 @subsection External Flash
4739 @deffn {Flash Driver} cfi
4740 @cindex Common Flash Interface
4741 @cindex CFI
4742 The ``Common Flash Interface'' (CFI) is the main standard for
4743 external NOR flash chips, each of which connects to a
4744 specific external chip select on the CPU.
4745 Frequently the first such chip is used to boot the system.
4746 Your board's @code{reset-init} handler might need to
4747 configure additional chip selects using other commands (like: @command{mww} to
4748 configure a bus and its timings), or
4749 perhaps configure a GPIO pin that controls the ``write protect'' pin
4750 on the flash chip.
4751 The CFI driver can use a target-specific working area to significantly
4752 speed up operation.
4754 The CFI driver can accept the following optional parameters, in any order:
4756 @itemize
4757 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
4758 like AM29LV010 and similar types.
4759 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
4760 @end itemize
4762 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
4763 wide on a sixteen bit bus:
4765 @example
4766 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
4767 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
4768 @end example
4770 To configure one bank of 32 MBytes
4771 built from two sixteen bit (two byte) wide parts wired in parallel
4772 to create a thirty-two bit (four byte) bus with doubled throughput:
4774 @example
4775 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
4776 @end example
4778 @c "cfi part_id" disabled
4779 @end deffn
4781 @deffn {Flash Driver} lpcspifi
4782 @cindex NXP SPI Flash Interface
4783 @cindex SPIFI
4784 @cindex lpcspifi
4785 NXP's LPC43xx and LPC18xx families include a proprietary SPI
4786 Flash Interface (SPIFI) peripheral that can drive and provide
4787 memory mapped access to external SPI flash devices.
4789 The lpcspifi driver initializes this interface and provides
4790 program and erase functionality for these serial flash devices.
4791 Use of this driver @b{requires} a working area of at least 1kB
4792 to be configured on the target device; more than this will
4793 significantly reduce flash programming times.
4795 The setup command only requires the @var{base} parameter. All
4796 other parameters are ignored, and the flash size and layout
4797 are configured by the driver.
4799 @example
4800 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
4801 @end example
4803 @end deffn
4805 @deffn {Flash Driver} stmsmi
4806 @cindex STMicroelectronics Serial Memory Interface
4807 @cindex SMI
4808 @cindex stmsmi
4809 Some devices form STMicroelectronics (e.g. STR75x MCU family,
4810 SPEAr MPU family) include a proprietary
4811 ``Serial Memory Interface'' (SMI) controller able to drive external
4812 SPI flash devices.
4813 Depending on specific device and board configuration, up to 4 external
4814 flash devices can be connected.
4816 SMI makes the flash content directly accessible in the CPU address
4817 space; each external device is mapped in a memory bank.
4818 CPU can directly read data, execute code and boot from SMI banks.
4819 Normal OpenOCD commands like @command{mdw} can be used to display
4820 the flash content.
4822 The setup command only requires the @var{base} parameter in order
4823 to identify the memory bank.
4824 All other parameters are ignored. Additional information, like
4825 flash size, are detected automatically.
4827 @example
4828 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
4829 @end example
4831 @end deffn
4833 @deffn {Flash Driver} mrvlqspi
4834 This driver supports QSPI flash controller of Marvell's Wireless
4835 Microcontroller platform.
4837 The flash size is autodetected based on the table of known JEDEC IDs
4838 hardcoded in the OpenOCD sources.
4840 @example
4841 flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
4842 @end example
4844 @end deffn
4846 @subsection Internal Flash (Microcontrollers)
4848 @deffn {Flash Driver} aduc702x
4849 The ADUC702x analog microcontrollers from Analog Devices
4850 include internal flash and use ARM7TDMI cores.
4851 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
4852 The setup command only requires the @var{target} argument
4853 since all devices in this family have the same memory layout.
4855 @example
4856 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
4857 @end example
4858 @end deffn
4860 @anchor{at91samd}
4861 @deffn {Flash Driver} at91samd
4862 @cindex at91samd
4864 @deffn Command {at91samd chip-erase}
4865 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
4866 used to erase a chip back to its factory state and does not require the
4867 processor to be halted.
4868 @end deffn
4870 @deffn Command {at91samd set-security}
4871 Secures the Flash via the Set Security Bit (SSB) command. This prevents access
4872 to the Flash and can only be undone by using the chip-erase command which
4873 erases the Flash contents and turns off the security bit. Warning: at this
4874 time, openocd will not be able to communicate with a secured chip and it is
4875 therefore not possible to chip-erase it without using another tool.
4877 @example
4878 at91samd set-security enable
4879 @end example
4880 @end deffn
4882 @deffn Command {at91samd eeprom}
4883 Shows or sets the EEPROM emulation size configuration, stored in the User Row
4884 of the Flash. When setting, the EEPROM size must be specified in bytes and it
4885 must be one of the permitted sizes according to the datasheet. Settings are
4886 written immediately but only take effect on MCU reset. EEPROM emulation
4887 requires additional firmware support and the minumum EEPROM size may not be
4888 the same as the minimum that the hardware supports. Set the EEPROM size to 0
4889 in order to disable this feature.
4891 @example
4892 at91samd eeprom
4893 at91samd eeprom 1024
4894 @end example
4895 @end deffn
4897 @deffn Command {at91samd bootloader}
4898 Shows or sets the bootloader size configuration, stored in the User Row of the
4899 Flash. This is called the BOOTPROT region. When setting, the bootloader size
4900 must be specified in bytes and it must be one of the permitted sizes according
4901 to the datasheet. Settings are written immediately but only take effect on
4902 MCU reset. Setting the bootloader size to 0 disables bootloader protection.
4904 @example
4905 at91samd bootloader
4906 at91samd bootloader 16384
4907 @end example
4908 @end deffn
4910 @end deffn
4912 @anchor{at91sam3}
4913 @deffn {Flash Driver} at91sam3
4914 @cindex at91sam3
4915 All members of the AT91SAM3 microcontroller family from
4916 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
4917 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
4918 that the driver was orginaly developed and tested using the
4919 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
4920 the family was cribbed from the data sheet. @emph{Note to future
4921 readers/updaters: Please remove this worrysome comment after other
4922 chips are confirmed.}
4924 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
4925 have one flash bank. In all cases the flash banks are at
4926 the following fixed locations:
4928 @example
4929 # Flash bank 0 - all chips
4930 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
4931 # Flash bank 1 - only 256K chips
4932 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
4933 @end example
4935 Internally, the AT91SAM3 flash memory is organized as follows.
4936 Unlike the AT91SAM7 chips, these are not used as parameters
4937 to the @command{flash bank} command:
4939 @itemize
4940 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
4941 @item @emph{Bank Size:} 128K/64K Per flash bank
4942 @item @emph{Sectors:} 16 or 8 per bank
4943 @item @emph{SectorSize:} 8K Per Sector
4944 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
4945 @end itemize
4947 The AT91SAM3 driver adds some additional commands:
4949 @deffn Command {at91sam3 gpnvm}
4950 @deffnx Command {at91sam3 gpnvm clear} number
4951 @deffnx Command {at91sam3 gpnvm set} number
4952 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
4953 With no parameters, @command{show} or @command{show all},
4954 shows the status of all GPNVM bits.
4955 With @command{show} @var{number}, displays that bit.
4957 With @command{set} @var{number} or @command{clear} @var{number},
4958 modifies that GPNVM bit.
4959 @end deffn
4961 @deffn Command {at91sam3 info}
4962 This command attempts to display information about the AT91SAM3
4963 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
4964 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
4965 document id: doc6430A] and decodes the values. @emph{Second} it reads the
4966 various clock configuration registers and attempts to display how it
4967 believes the chip is configured. By default, the SLOWCLK is assumed to
4968 be 32768 Hz, see the command @command{at91sam3 slowclk}.
4969 @end deffn
4971 @deffn Command {at91sam3 slowclk} [value]
4972 This command shows/sets the slow clock frequency used in the
4973 @command{at91sam3 info} command calculations above.
4974 @end deffn
4975 @end deffn
4977 @deffn {Flash Driver} at91sam4
4978 @cindex at91sam4
4979 All members of the AT91SAM4 microcontroller family from
4980 Atmel include internal flash and use ARM's Cortex-M4 core.
4981 This driver uses the same cmd names/syntax as @xref{at91sam3}.
4982 @end deffn
4984 @deffn {Flash Driver} at91sam4l
4985 @cindex at91sam4l
4986 All members of the AT91SAM4L microcontroller family from
4987 Atmel include internal flash and use ARM's Cortex-M4 core.
4988 This driver uses the same cmd names/syntax as @xref{at91sam3}.
4990 The AT91SAM4L driver adds some additional commands:
4991 @deffn Command {at91sam4l smap_reset_deassert}
4992 This command releases internal reset held by SMAP
4993 and prepares reset vector catch in case of reset halt.
4994 Command is used internally in event event reset-deassert-post.
4995 @end deffn
4996 @end deffn
4998 @deffn {Flash Driver} at91sam7
4999 All members of the AT91SAM7 microcontroller family from Atmel include
5000 internal flash and use ARM7TDMI cores. The driver automatically
5001 recognizes a number of these chips using the chip identification
5002 register, and autoconfigures itself.
5004 @example
5005 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
5006 @end example
5008 For chips which are not recognized by the controller driver, you must
5009 provide additional parameters in the following order:
5011 @itemize
5012 @item @var{chip_model} ... label used with @command{flash info}
5013 @item @var{banks}
5014 @item @var{sectors_per_bank}
5015 @item @var{pages_per_sector}
5016 @item @var{pages_size}
5017 @item @var{num_nvm_bits}
5018 @item @var{freq_khz} ... required if an external clock is provided,
5019 optional (but recommended) when the oscillator frequency is known
5020 @end itemize
5022 It is recommended that you provide zeroes for all of those values
5023 except the clock frequency, so that everything except that frequency
5024 will be autoconfigured.
5025 Knowing the frequency helps ensure correct timings for flash access.
5027 The flash controller handles erases automatically on a page (128/256 byte)
5028 basis, so explicit erase commands are not necessary for flash programming.
5029 However, there is an ``EraseAll`` command that can erase an entire flash
5030 plane (of up to 256KB), and it will be used automatically when you issue
5031 @command{flash erase_sector} or @command{flash erase_address} commands.
5033 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
5034 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
5035 bit for the processor. Each processor has a number of such bits,
5036 used for controlling features such as brownout detection (so they
5037 are not truly general purpose).
5038 @quotation Note
5039 This assumes that the first flash bank (number 0) is associated with
5040 the appropriate at91sam7 target.
5041 @end quotation
5042 @end deffn
5043 @end deffn
5045 @deffn {Flash Driver} avr
5046 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
5047 @emph{The current implementation is incomplete.}
5048 @comment - defines mass_erase ... pointless given flash_erase_address
5049 @end deffn
5051 @deffn {Flash Driver} efm32
5052 All members of the EFM32 microcontroller family from Energy Micro include
5053 internal flash and use ARM Cortex M3 cores. The driver automatically recognizes
5054 a number of these chips using the chip identification register, and
5055 autoconfigures itself.
5056 @example
5057 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
5058 @end example
5059 @emph{The current implementation is incomplete. Unprotecting flash pages is not
5060 supported.}
5061 @end deffn
5063 @deffn {Flash Driver} lpc2000
5064 This is the driver to support internal flash of all members of the
5065 LPC11(x)00 and LPC1300 microcontroller families and most members of
5066 the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000 and LPC54100
5067 microcontroller families from NXP.
5069 @quotation Note
5070 There are LPC2000 devices which are not supported by the @var{lpc2000}
5071 driver:
5072 The LPC2888 is supported by the @var{lpc288x} driver.
5073 The LPC29xx family is supported by the @var{lpc2900} driver.
5074 @end quotation