5977c40944f871d53c665dee0a075697532f005f
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
11
12 @include version.texi
13
14 @copying
15
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
20
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
28
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
38
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
45
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
50
51 @summarycontents
52 @contents
53
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
57
58 @insertcopying
59 @end ifnottex
60
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
82 * TFTP:: TFTP
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
88
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
95 @end menu
96
97 @node About
98 @unnumbered About
99 @cindex about
100
101 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
102 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
105 around the world.
106
107 @section What is OpenOCD?
108 @cindex TAP
109 @cindex JTAG
110
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
113 devices.
114
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
121
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
127
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board connect directly to the debug
132 host over USB (and sometimes also to power it over USB).
133
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
140 scan operations.
141
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD supports only
145 debugging, whereas JTAG also supports boundary scan operations.
146
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
151
152
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
154 USB-based, parallel port-based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
156
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
159 (Stellaris LM3, ST STM32 and Energy Micro EFM32) and Intel Quark (x10xx)
160 based cores to be debugged via the GDB protocol.
161
162 @b{Flash Programming:} Flash writing is supported for external
163 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) is included.
167
168 @section OpenOCD Web Site
169
170 The OpenOCD web site provides the latest public news from the community:
171
172 @uref{http://openocd.org/}
173
174 @section Latest User's Guide:
175
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
179
180 @uref{http://openocd.org/doc/html/index.html}
181
182 PDF form is likewise published at:
183
184 @uref{http://openocd.org/doc/pdf/openocd.pdf}
185
186 @section OpenOCD User's Forum
187
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
193
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
195
196 @section OpenOCD User's Mailing List
197
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
200
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
202
203 @section OpenOCD IRC
204
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
207
208 @node Developers
209 @chapter OpenOCD Developer Resources
210 @cindex developers
211
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
216
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
219
220 @section OpenOCD Git Repository
221
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a Git repository hosted at SourceForge. The repository URL is:
224
225 @uref{git://git.code.sf.net/p/openocd/code}
226
227 or via http
228
229 @uref{http://git.code.sf.net/p/openocd/code}
230
231 You may prefer to use a mirror and the HTTP protocol:
232
233 @uref{http://repo.or.cz/r/openocd.git}
234
235 With standard Git tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a Git client:
240
241 @uref{http://repo.or.cz/w/openocd.git}
242
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
245
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
250
251 @section Doxygen Developer Manual
252
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
257
258 @uref{http://openocd.org/doc/doxygen/html/index.html}
259
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration at the top of the source tree.
263
264 @section Gerrit Review System
265
266 All changes in the OpenOCD Git repository go through the web-based Gerrit
267 Code Review System:
268
269 @uref{http://openocd.zylin.com/}
270
271 After a one-time registration and repository setup, anyone can push commits
272 from their local Git repository directly into Gerrit.
273 All users and developers are encouraged to review, test, discuss and vote
274 for changes in Gerrit. The feedback provides the basis for a maintainer to
275 eventually submit the change to the main Git repository.
276
277 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
278 Developer Manual, contains basic information about how to connect a
279 repository to Gerrit, prepare and push patches. Patch authors are expected to
280 maintain their changes while they're in Gerrit, respond to feedback and if
281 necessary rework and push improved versions of the change.
282
283 @section OpenOCD Developer Mailing List
284
285 The OpenOCD Developer Mailing List provides the primary means of
286 communication between developers:
287
288 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
289
290 @section OpenOCD Bug Tracker
291
292 The OpenOCD Bug Tracker is hosted on SourceForge:
293
294 @uref{http://bugs.openocd.org/}
295
296
297 @node Debug Adapter Hardware
298 @chapter Debug Adapter Hardware
299 @cindex dongles
300 @cindex FTDI
301 @cindex wiggler
302 @cindex zy1000
303 @cindex printer port
304 @cindex USB Adapter
305 @cindex RTCK
306
307 Defined: @b{dongle}: A small device that plugs into a computer and serves as
308 an adapter .... [snip]
309
310 In the OpenOCD case, this generally refers to @b{a small adapter} that
311 attaches to your computer via USB or the parallel port. One
312 exception is the Ultimate Solutions ZY1000, packaged as a small box you
313 attach via an ethernet cable. The ZY1000 has the advantage that it does not
314 require any drivers to be installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built-in relay to power cycle targets remotely.
317
318
319 @section Choosing a Dongle
320
321 There are several things you should keep in mind when choosing a dongle.
322
323 @enumerate
324 @item @b{Transport} Does it support the kind of communication that you need?
325 OpenOCD focusses mostly on JTAG. Your version may also support
326 other ways to communicate with target devices.
327 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
328 Does your dongle support it? You might need a level converter.
329 @item @b{Pinout} What pinout does your target board use?
330 Does your dongle support it? You may be able to use jumper
331 wires, or an "octopus" connector, to convert pinouts.
332 @item @b{Connection} Does your computer have the USB, parallel, or
333 Ethernet port needed?
334 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
335 RTCK support (also known as ``adaptive clocking'')?
336 @end enumerate
337
338 @section Stand-alone JTAG Probe
339
340 The ZY1000 from Ultimate Solutions is technically not a dongle but a
341 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
342 running on the developer's host computer.
343 Once installed on a network using DHCP or a static IP assignment, users can
344 access the ZY1000 probe locally or remotely from any host with access to the
345 IP address assigned to the probe.
346 The ZY1000 provides an intuitive web interface with direct access to the
347 OpenOCD debugger.
348 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
349 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
350 the target.
351 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
352 to power cycle the target remotely.
353
354 For more information, visit:
355
356 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/210-zylin-zy1000-main}
357
358 @section USB FT2232 Based
359
360 There are many USB JTAG dongles on the market, many of them based
361 on a chip from ``Future Technology Devices International'' (FTDI)
362 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
363 See: @url{http://www.ftdichip.com} for more information.
364 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
365 chips started to become available in JTAG adapters. Around 2012, a new
366 variant appeared - FT232H - this is a single-channel version of FT2232H.
367 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
368 clocking.)
369
370 The FT2232 chips are flexible enough to support some other
371 transport options, such as SWD or the SPI variants used to
372 program some chips. They have two communications channels,
373 and one can be used for a UART adapter at the same time the
374 other one is used to provide a debug adapter.
375
376 Also, some development boards integrate an FT2232 chip to serve as
377 a built-in low-cost debug adapter and USB-to-serial solution.
378
379 @itemize @bullet
380 @item @b{usbjtag}
381 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
382 @item @b{jtagkey}
383 @* See: @url{http://www.amontec.com/jtagkey.shtml}
384 @item @b{jtagkey2}
385 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
386 @item @b{oocdlink}
387 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
388 @item @b{signalyzer}
389 @* See: @url{http://www.signalyzer.com}
390 @item @b{Stellaris Eval Boards}
391 @* See: @url{http://www.ti.com} - The Stellaris eval boards
392 bundle FT2232-based JTAG and SWD support, which can be used to debug
393 the Stellaris chips. Using separate JTAG adapters is optional.
394 These boards can also be used in a "pass through" mode as JTAG adapters
395 to other target boards, disabling the Stellaris chip.
396 @item @b{TI/Luminary ICDI}
397 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
398 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
399 Evaluation Kits. Like the non-detachable FT2232 support on the other
400 Stellaris eval boards, they can be used to debug other target boards.
401 @item @b{olimex-jtag}
402 @* See: @url{http://www.olimex.com}
403 @item @b{Flyswatter/Flyswatter2}
404 @* See: @url{http://www.tincantools.com}
405 @item @b{turtelizer2}
406 @* See:
407 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
408 @url{http://www.ethernut.de}
409 @item @b{comstick}
410 @* Link: @url{http://www.hitex.com/index.php?id=383}
411 @item @b{stm32stick}
412 @* Link @url{http://www.hitex.com/stm32-stick}
413 @item @b{axm0432_jtag}
414 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
415 to be available anymore as of April 2012.
416 @item @b{cortino}
417 @* Link @url{http://www.hitex.com/index.php?id=cortino}
418 @item @b{dlp-usb1232h}
419 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
420 @item @b{digilent-hs1}
421 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
422 @item @b{opendous}
423 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
424 (OpenHardware).
425 @item @b{JTAG-lock-pick Tiny 2}
426 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
427
428 @item @b{GW16042}
429 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
430 FT2232H-based
431
432 @end itemize
433 @section USB-JTAG / Altera USB-Blaster compatibles
434
435 These devices also show up as FTDI devices, but are not
436 protocol-compatible with the FT2232 devices. They are, however,
437 protocol-compatible among themselves. USB-JTAG devices typically consist
438 of a FT245 followed by a CPLD that understands a particular protocol,
439 or emulates this protocol using some other hardware.
440
441 They may appear under different USB VID/PID depending on the particular
442 product. The driver can be configured to search for any VID/PID pair
443 (see the section on driver commands).
444
445 @itemize
446 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
447 @* Link: @url{http://ixo-jtag.sourceforge.net/}
448 @item @b{Altera USB-Blaster}
449 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
450 @end itemize
451
452 @section USB J-Link based
453 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
454 an example of a microcontroller based JTAG adapter, it uses an
455 AT91SAM764 internally.
456
457 @itemize @bullet
458 @item @b{SEGGER J-Link}
459 @* Link: @url{http://www.segger.com/jlink.html}
460 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
461 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
462 @item @b{IAR J-Link}
463 @end itemize
464
465 @section USB RLINK based
466 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
467 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
468 SWD and not JTAG, thus not supported.
469
470 @itemize @bullet
471 @item @b{Raisonance RLink}
472 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
473 @item @b{STM32 Primer}
474 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
475 @item @b{STM32 Primer2}
476 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
477 @end itemize
478
479 @section USB ST-LINK based
480 ST Micro has an adapter called @b{ST-LINK}.
481 They only work with ST Micro chips, notably STM32 and STM8.
482
483 @itemize @bullet
484 @item @b{ST-LINK}
485 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
486 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
487 @item @b{ST-LINK/V2}
488 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
489 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
490 @end itemize
491
492 For info the original ST-LINK enumerates using the mass storage usb class; however,
493 its implementation is completely broken. The result is this causes issues under Linux.
494 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
495 @itemize @bullet
496 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
497 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
498 @end itemize
499
500 @section USB TI/Stellaris ICDI based
501 Texas Instruments has an adapter called @b{ICDI}.
502 It is not to be confused with the FTDI based adapters that were originally fitted to their
503 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
504
505 @section USB CMSIS-DAP based
506 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
507 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
508
509 @section USB Other
510 @itemize @bullet
511 @item @b{USBprog}
512 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
513
514 @item @b{USB - Presto}
515 @* Link: @url{http://tools.asix.net/prg_presto.htm}
516
517 @item @b{Versaloon-Link}
518 @* Link: @url{http://www.versaloon.com}
519
520 @item @b{ARM-JTAG-EW}
521 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
522
523 @item @b{Buspirate}
524 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
525
526 @item @b{opendous}
527 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
528
529 @item @b{estick}
530 @* Link: @url{http://code.google.com/p/estick-jtag/}
531
532 @item @b{Keil ULINK v1}
533 @* Link: @url{http://www.keil.com/ulink1/}
534 @end itemize
535
536 @section IBM PC Parallel Printer Port Based
537
538 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
539 and the Macraigor Wiggler. There are many clones and variations of
540 these on the market.
541
542 Note that parallel ports are becoming much less common, so if you
543 have the choice you should probably avoid these adapters in favor
544 of USB-based ones.
545
546 @itemize @bullet
547
548 @item @b{Wiggler} - There are many clones of this.
549 @* Link: @url{http://www.macraigor.com/wiggler.htm}
550
551 @item @b{DLC5} - From XILINX - There are many clones of this
552 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
553 produced, PDF schematics are easily found and it is easy to make.
554
555 @item @b{Amontec - JTAG Accelerator}
556 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
557
558 @item @b{Wiggler2}
559 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
560
561 @item @b{Wiggler_ntrst_inverted}
562 @* Yet another variation - See the source code, src/jtag/parport.c
563
564 @item @b{old_amt_wiggler}
565 @* Unknown - probably not on the market today
566
567 @item @b{arm-jtag}
568 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
569
570 @item @b{chameleon}
571 @* Link: @url{http://www.amontec.com/chameleon.shtml}
572
573 @item @b{Triton}
574 @* Unknown.
575
576 @item @b{Lattice}
577 @* ispDownload from Lattice Semiconductor
578 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
579
580 @item @b{flashlink}
581 @* From ST Microsystems;
582 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
583
584 @end itemize
585
586 @section Other...
587 @itemize @bullet
588
589 @item @b{ep93xx}
590 @* An EP93xx based Linux machine using the GPIO pins directly.
591
592 @item @b{at91rm9200}
593 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
594
595 @item @b{bcm2835gpio}
596 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
597
598 @item @b{jtag_vpi}
599 @* A JTAG driver acting as a client for the JTAG VPI server interface.
600 @* Link: @url{http://github.com/fjullien/jtag_vpi}
601
602 @end itemize
603
604 @node About Jim-Tcl
605 @chapter About Jim-Tcl
606 @cindex Jim-Tcl
607 @cindex tcl
608
609 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
610 This programming language provides a simple and extensible
611 command interpreter.
612
613 All commands presented in this Guide are extensions to Jim-Tcl.
614 You can use them as simple commands, without needing to learn
615 much of anything about Tcl.
616 Alternatively, you can write Tcl programs with them.
617
618 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
619 There is an active and responsive community, get on the mailing list
620 if you have any questions. Jim-Tcl maintainers also lurk on the
621 OpenOCD mailing list.
622
623 @itemize @bullet
624 @item @b{Jim vs. Tcl}
625 @* Jim-Tcl is a stripped down version of the well known Tcl language,
626 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
627 fewer features. Jim-Tcl is several dozens of .C files and .H files and
628 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
629 4.2 MB .zip file containing 1540 files.
630
631 @item @b{Missing Features}
632 @* Our practice has been: Add/clone the real Tcl feature if/when
633 needed. We welcome Jim-Tcl improvements, not bloat. Also there
634 are a large number of optional Jim-Tcl features that are not
635 enabled in OpenOCD.
636
637 @item @b{Scripts}
638 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
639 command interpreter today is a mixture of (newer)
640 Jim-Tcl commands, and the (older) original command interpreter.
641
642 @item @b{Commands}
643 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
644 can type a Tcl for() loop, set variables, etc.
645 Some of the commands documented in this guide are implemented
646 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
647
648 @item @b{Historical Note}
649 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
650 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
651 as a Git submodule, which greatly simplified upgrading Jim-Tcl
652 to benefit from new features and bugfixes in Jim-Tcl.
653
654 @item @b{Need a crash course in Tcl?}
655 @*@xref{Tcl Crash Course}.
656 @end itemize
657
658 @node Running
659 @chapter Running
660 @cindex command line options
661 @cindex logfile
662 @cindex directory search
663
664 Properly installing OpenOCD sets up your operating system to grant it access
665 to the debug adapters. On Linux, this usually involves installing a file
666 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
667 that works for many common adapters is shipped with OpenOCD in the
668 @file{contrib} directory. MS-Windows needs
669 complex and confusing driver configuration for every peripheral. Such issues
670 are unique to each operating system, and are not detailed in this User's Guide.
671
672 Then later you will invoke the OpenOCD server, with various options to
673 tell it how each debug session should work.
674 The @option{--help} option shows:
675 @verbatim
676 bash$ openocd --help
677
678 --help | -h display this help
679 --version | -v display OpenOCD version
680 --file | -f use configuration file <name>
681 --search | -s dir to search for config files and scripts
682 --debug | -d set debug level <0-3>
683 --log_output | -l redirect log output to file <name>
684 --command | -c run <command>
685 @end verbatim
686
687 If you don't give any @option{-f} or @option{-c} options,
688 OpenOCD tries to read the configuration file @file{openocd.cfg}.
689 To specify one or more different
690 configuration files, use @option{-f} options. For example:
691
692 @example
693 openocd -f config1.cfg -f config2.cfg -f config3.cfg
694 @end example
695
696 Configuration files and scripts are searched for in
697 @enumerate
698 @item the current directory,
699 @item any search dir specified on the command line using the @option{-s} option,
700 @item any search dir specified using the @command{add_script_search_dir} command,
701 @item @file{$HOME/.openocd} (not on Windows),
702 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
703 @item the site wide script library @file{$pkgdatadir/site} and
704 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
705 @end enumerate
706 The first found file with a matching file name will be used.
707
708 @quotation Note
709 Don't try to use configuration script names or paths which
710 include the "#" character. That character begins Tcl comments.
711 @end quotation
712
713 @section Simple setup, no customization
714
715 In the best case, you can use two scripts from one of the script
716 libraries, hook up your JTAG adapter, and start the server ... and
717 your JTAG setup will just work "out of the box". Always try to
718 start by reusing those scripts, but assume you'll need more
719 customization even if this works. @xref{OpenOCD Project Setup}.
720
721 If you find a script for your JTAG adapter, and for your board or
722 target, you may be able to hook up your JTAG adapter then start
723 the server with some variation of one of the following:
724
725 @example
726 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
727 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
728 @end example
729
730 You might also need to configure which reset signals are present,
731 using @option{-c 'reset_config trst_and_srst'} or something similar.
732 If all goes well you'll see output something like
733
734 @example
735 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
736 For bug reports, read
737 http://openocd.org/doc/doxygen/bugs.html
738 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
739 (mfg: 0x23b, part: 0xba00, ver: 0x3)
740 @end example
741
742 Seeing that "tap/device found" message, and no warnings, means
743 the JTAG communication is working. That's a key milestone, but
744 you'll probably need more project-specific setup.
745
746 @section What OpenOCD does as it starts
747
748 OpenOCD starts by processing the configuration commands provided
749 on the command line or, if there were no @option{-c command} or
750 @option{-f file.cfg} options given, in @file{openocd.cfg}.
751 @xref{configurationstage,,Configuration Stage}.
752 At the end of the configuration stage it verifies the JTAG scan
753 chain defined using those commands; your configuration should
754 ensure that this always succeeds.
755 Normally, OpenOCD then starts running as a server.
756 Alternatively, commands may be used to terminate the configuration
757 stage early, perform work (such as updating some flash memory),
758 and then shut down without acting as a server.
759
760 Once OpenOCD starts running as a server, it waits for connections from
761 clients (Telnet, GDB, RPC) and processes the commands issued through
762 those channels.
763
764 If you are having problems, you can enable internal debug messages via
765 the @option{-d} option.
766
767 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
768 @option{-c} command line switch.
769
770 To enable debug output (when reporting problems or working on OpenOCD
771 itself), use the @option{-d} command line switch. This sets the
772 @option{debug_level} to "3", outputting the most information,
773 including debug messages. The default setting is "2", outputting only
774 informational messages, warnings and errors. You can also change this
775 setting from within a telnet or gdb session using @command{debug_level<n>}
776 (@pxref{debuglevel,,debug_level}).
777
778 You can redirect all output from the server to a file using the
779 @option{-l <logfile>} switch.
780
781 Note! OpenOCD will launch the GDB & telnet server even if it can not
782 establish a connection with the target. In general, it is possible for
783 the JTAG controller to be unresponsive until the target is set up
784 correctly via e.g. GDB monitor commands in a GDB init script.
785
786 @node OpenOCD Project Setup
787 @chapter OpenOCD Project Setup
788
789 To use OpenOCD with your development projects, you need to do more than
790 just connect the JTAG adapter hardware (dongle) to your development board
791 and start the OpenOCD server.
792 You also need to configure your OpenOCD server so that it knows
793 about your adapter and board, and helps your work.
794 You may also want to connect OpenOCD to GDB, possibly
795 using Eclipse or some other GUI.
796
797 @section Hooking up the JTAG Adapter
798
799 Today's most common case is a dongle with a JTAG cable on one side
800 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
801 and a USB cable on the other.
802 Instead of USB, some cables use Ethernet;
803 older ones may use a PC parallel port, or even a serial port.
804
805 @enumerate
806 @item @emph{Start with power to your target board turned off},
807 and nothing connected to your JTAG adapter.
808 If you're particularly paranoid, unplug power to the board.
809 It's important to have the ground signal properly set up,
810 unless you are using a JTAG adapter which provides
811 galvanic isolation between the target board and the
812 debugging host.
813
814 @item @emph{Be sure it's the right kind of JTAG connector.}
815 If your dongle has a 20-pin ARM connector, you need some kind
816 of adapter (or octopus, see below) to hook it up to
817 boards using 14-pin or 10-pin connectors ... or to 20-pin
818 connectors which don't use ARM's pinout.
819
820 In the same vein, make sure the voltage levels are compatible.
821 Not all JTAG adapters have the level shifters needed to work
822 with 1.2 Volt boards.
823
824 @item @emph{Be certain the cable is properly oriented} or you might
825 damage your board. In most cases there are only two possible
826 ways to connect the cable.
827 Connect the JTAG cable from your adapter to the board.
828 Be sure it's firmly connected.
829
830 In the best case, the connector is keyed to physically
831 prevent you from inserting it wrong.
832 This is most often done using a slot on the board's male connector
833 housing, which must match a key on the JTAG cable's female connector.
834 If there's no housing, then you must look carefully and
835 make sure pin 1 on the cable hooks up to pin 1 on the board.
836 Ribbon cables are frequently all grey except for a wire on one
837 edge, which is red. The red wire is pin 1.
838
839 Sometimes dongles provide cables where one end is an ``octopus'' of
840 color coded single-wire connectors, instead of a connector block.
841 These are great when converting from one JTAG pinout to another,
842 but are tedious to set up.
843 Use these with connector pinout diagrams to help you match up the
844 adapter signals to the right board pins.
845
846 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
847 A USB, parallel, or serial port connector will go to the host which
848 you are using to run OpenOCD.
849 For Ethernet, consult the documentation and your network administrator.
850
851 For USB-based JTAG adapters you have an easy sanity check at this point:
852 does the host operating system see the JTAG adapter? If you're running
853 Linux, try the @command{lsusb} command. If that host is an
854 MS-Windows host, you'll need to install a driver before OpenOCD works.
855
856 @item @emph{Connect the adapter's power supply, if needed.}
857 This step is primarily for non-USB adapters,
858 but sometimes USB adapters need extra power.
859
860 @item @emph{Power up the target board.}
861 Unless you just let the magic smoke escape,
862 you're now ready to set up the OpenOCD server
863 so you can use JTAG to work with that board.
864
865 @end enumerate
866
867 Talk with the OpenOCD server using
868 telnet (@code{telnet localhost 4444} on many systems) or GDB.
869 @xref{GDB and OpenOCD}.
870
871 @section Project Directory
872
873 There are many ways you can configure OpenOCD and start it up.
874
875 A simple way to organize them all involves keeping a
876 single directory for your work with a given board.
877 When you start OpenOCD from that directory,
878 it searches there first for configuration files, scripts,
879 files accessed through semihosting,
880 and for code you upload to the target board.
881 It is also the natural place to write files,
882 such as log files and data you download from the board.
883
884 @section Configuration Basics
885
886 There are two basic ways of configuring OpenOCD, and
887 a variety of ways you can mix them.
888 Think of the difference as just being how you start the server:
889
890 @itemize
891 @item Many @option{-f file} or @option{-c command} options on the command line
892 @item No options, but a @dfn{user config file}
893 in the current directory named @file{openocd.cfg}
894 @end itemize
895
896 Here is an example @file{openocd.cfg} file for a setup
897 using a Signalyzer FT2232-based JTAG adapter to talk to
898 a board with an Atmel AT91SAM7X256 microcontroller:
899
900 @example
901 source [find interface/ftdi/signalyzer.cfg]
902
903 # GDB can also flash my flash!
904 gdb_memory_map enable
905 gdb_flash_program enable
906
907 source [find target/sam7x256.cfg]
908 @end example
909
910 Here is the command line equivalent of that configuration:
911
912 @example
913 openocd -f interface/ftdi/signalyzer.cfg \
914 -c "gdb_memory_map enable" \
915 -c "gdb_flash_program enable" \
916 -f target/sam7x256.cfg
917 @end example
918
919 You could wrap such long command lines in shell scripts,
920 each supporting a different development task.
921 One might re-flash the board with a specific firmware version.
922 Another might set up a particular debugging or run-time environment.
923
924 @quotation Important
925 At this writing (October 2009) the command line method has
926 problems with how it treats variables.
927 For example, after @option{-c "set VAR value"}, or doing the
928 same in a script, the variable @var{VAR} will have no value
929 that can be tested in a later script.
930 @end quotation
931
932 Here we will focus on the simpler solution: one user config
933 file, including basic configuration plus any TCL procedures
934 to simplify your work.
935
936 @section User Config Files
937 @cindex config file, user
938 @cindex user config file
939 @cindex config file, overview
940
941 A user configuration file ties together all the parts of a project
942 in one place.
943 One of the following will match your situation best:
944
945 @itemize
946 @item Ideally almost everything comes from configuration files
947 provided by someone else.
948 For example, OpenOCD distributes a @file{scripts} directory
949 (probably in @file{/usr/share/openocd/scripts} on Linux).
950 Board and tool vendors can provide these too, as can individual
951 user sites; the @option{-s} command line option lets you say
952 where to find these files. (@xref{Running}.)
953 The AT91SAM7X256 example above works this way.
954
955 Three main types of non-user configuration file each have their
956 own subdirectory in the @file{scripts} directory:
957
958 @enumerate
959 @item @b{interface} -- one for each different debug adapter;
960 @item @b{board} -- one for each different board
961 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
962 @end enumerate
963
964 Best case: include just two files, and they handle everything else.
965 The first is an interface config file.
966 The second is board-specific, and it sets up the JTAG TAPs and
967 their GDB targets (by deferring to some @file{target.cfg} file),
968 declares all flash memory, and leaves you nothing to do except
969 meet your deadline:
970
971 @example
972 source [find interface/olimex-jtag-tiny.cfg]
973 source [find board/csb337.cfg]
974 @end example
975
976 Boards with a single microcontroller often won't need more
977 than the target config file, as in the AT91SAM7X256 example.
978 That's because there is no external memory (flash, DDR RAM), and
979 the board differences are encapsulated by application code.
980
981 @item Maybe you don't know yet what your board looks like to JTAG.
982 Once you know the @file{interface.cfg} file to use, you may
983 need help from OpenOCD to discover what's on the board.
984 Once you find the JTAG TAPs, you can just search for appropriate
985 target and board
986 configuration files ... or write your own, from the bottom up.
987 @xref{autoprobing,,Autoprobing}.
988
989 @item You can often reuse some standard config files but
990 need to write a few new ones, probably a @file{board.cfg} file.
991 You will be using commands described later in this User's Guide,
992 and working with the guidelines in the next chapter.
993
994 For example, there may be configuration files for your JTAG adapter
995 and target chip, but you need a new board-specific config file
996 giving access to your particular flash chips.
997 Or you might need to write another target chip configuration file
998 for a new chip built around the Cortex-M3 core.
999
1000 @quotation Note
1001 When you write new configuration files, please submit
1002 them for inclusion in the next OpenOCD release.
1003 For example, a @file{board/newboard.cfg} file will help the
1004 next users of that board, and a @file{target/newcpu.cfg}
1005 will help support users of any board using that chip.
1006 @end quotation
1007
1008 @item
1009 You may may need to write some C code.
1010 It may be as simple as supporting a new FT2232 or parport
1011 based adapter; a bit more involved, like a NAND or NOR flash
1012 controller driver; or a big piece of work like supporting
1013 a new chip architecture.
1014 @end itemize
1015
1016 Reuse the existing config files when you can.
1017 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1018 You may find a board configuration that's a good example to follow.
1019
1020 When you write config files, separate the reusable parts
1021 (things every user of that interface, chip, or board needs)
1022 from ones specific to your environment and debugging approach.
1023 @itemize
1024
1025 @item
1026 For example, a @code{gdb-attach} event handler that invokes
1027 the @command{reset init} command will interfere with debugging
1028 early boot code, which performs some of the same actions
1029 that the @code{reset-init} event handler does.
1030
1031 @item
1032 Likewise, the @command{arm9 vector_catch} command (or
1033 @cindex vector_catch
1034 its siblings @command{xscale vector_catch}
1035 and @command{cortex_m vector_catch}) can be a timesaver
1036 during some debug sessions, but don't make everyone use that either.
1037 Keep those kinds of debugging aids in your user config file,
1038 along with messaging and tracing setup.
1039 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1040
1041 @item
1042 You might need to override some defaults.
1043 For example, you might need to move, shrink, or back up the target's
1044 work area if your application needs much SRAM.
1045
1046 @item
1047 TCP/IP port configuration is another example of something which
1048 is environment-specific, and should only appear in
1049 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1050 @end itemize
1051
1052 @section Project-Specific Utilities
1053
1054 A few project-specific utility
1055 routines may well speed up your work.
1056 Write them, and keep them in your project's user config file.
1057
1058 For example, if you are making a boot loader work on a
1059 board, it's nice to be able to debug the ``after it's
1060 loaded to RAM'' parts separately from the finicky early
1061 code which sets up the DDR RAM controller and clocks.
1062 A script like this one, or a more GDB-aware sibling,
1063 may help:
1064
1065 @example
1066 proc ramboot @{ @} @{
1067 # Reset, running the target's "reset-init" scripts
1068 # to initialize clocks and the DDR RAM controller.
1069 # Leave the CPU halted.
1070 reset init
1071
1072 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1073 load_image u-boot.bin 0x20000000
1074
1075 # Start running.
1076 resume 0x20000000
1077 @}
1078 @end example
1079
1080 Then once that code is working you will need to make it
1081 boot from NOR flash; a different utility would help.
1082 Alternatively, some developers write to flash using GDB.
1083 (You might use a similar script if you're working with a flash
1084 based microcontroller application instead of a boot loader.)
1085
1086 @example
1087 proc newboot @{ @} @{
1088 # Reset, leaving the CPU halted. The "reset-init" event
1089 # proc gives faster access to the CPU and to NOR flash;
1090 # "reset halt" would be slower.
1091 reset init
1092
1093 # Write standard version of U-Boot into the first two
1094 # sectors of NOR flash ... the standard version should
1095 # do the same lowlevel init as "reset-init".
1096 flash protect 0 0 1 off
1097 flash erase_sector 0 0 1
1098 flash write_bank 0 u-boot.bin 0x0
1099 flash protect 0 0 1 on
1100
1101 # Reboot from scratch using that new boot loader.
1102 reset run
1103 @}
1104 @end example
1105
1106 You may need more complicated utility procedures when booting
1107 from NAND.
1108 That often involves an extra bootloader stage,
1109 running from on-chip SRAM to perform DDR RAM setup so it can load
1110 the main bootloader code (which won't fit into that SRAM).
1111
1112 Other helper scripts might be used to write production system images,
1113 involving considerably more than just a three stage bootloader.
1114
1115 @section Target Software Changes
1116
1117 Sometimes you may want to make some small changes to the software
1118 you're developing, to help make JTAG debugging work better.
1119 For example, in C or assembly language code you might
1120 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1121 handling issues like:
1122
1123 @itemize @bullet
1124
1125 @item @b{Watchdog Timers}...
1126 Watchog timers are typically used to automatically reset systems if
1127 some application task doesn't periodically reset the timer. (The
1128 assumption is that the system has locked up if the task can't run.)
1129 When a JTAG debugger halts the system, that task won't be able to run
1130 and reset the timer ... potentially causing resets in the middle of
1131 your debug sessions.
1132
1133 It's rarely a good idea to disable such watchdogs, since their usage
1134 needs to be debugged just like all other parts of your firmware.
1135 That might however be your only option.
1136
1137 Look instead for chip-specific ways to stop the watchdog from counting
1138 while the system is in a debug halt state. It may be simplest to set
1139 that non-counting mode in your debugger startup scripts. You may however
1140 need a different approach when, for example, a motor could be physically
1141 damaged by firmware remaining inactive in a debug halt state. That might
1142 involve a type of firmware mode where that "non-counting" mode is disabled
1143 at the beginning then re-enabled at the end; a watchdog reset might fire
1144 and complicate the debug session, but hardware (or people) would be
1145 protected.@footnote{Note that many systems support a "monitor mode" debug
1146 that is a somewhat cleaner way to address such issues. You can think of
1147 it as only halting part of the system, maybe just one task,
1148 instead of the whole thing.
1149 At this writing, January 2010, OpenOCD based debugging does not support
1150 monitor mode debug, only "halt mode" debug.}
1151
1152 @item @b{ARM Semihosting}...
1153 @cindex ARM semihosting
1154 When linked with a special runtime library provided with many
1155 toolchains@footnote{See chapter 8 "Semihosting" in
1156 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1157 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1158 The CodeSourcery EABI toolchain also includes a semihosting library.},
1159 your target code can use I/O facilities on the debug host. That library
1160 provides a small set of system calls which are handled by OpenOCD.
1161 It can let the debugger provide your system console and a file system,
1162 helping with early debugging or providing a more capable environment
1163 for sometimes-complex tasks like installing system firmware onto
1164 NAND or SPI flash.
1165
1166 @item @b{ARM Wait-For-Interrupt}...
1167 Many ARM chips synchronize the JTAG clock using the core clock.
1168 Low power states which stop that core clock thus prevent JTAG access.
1169 Idle loops in tasking environments often enter those low power states
1170 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1171
1172 You may want to @emph{disable that instruction} in source code,
1173 or otherwise prevent using that state,
1174 to ensure you can get JTAG access at any time.@footnote{As a more
1175 polite alternative, some processors have special debug-oriented
1176 registers which can be used to change various features including
1177 how the low power states are clocked while debugging.
1178 The STM32 DBGMCU_CR register is an example; at the cost of extra
1179 power consumption, JTAG can be used during low power states.}
1180 For example, the OpenOCD @command{halt} command may not
1181 work for an idle processor otherwise.
1182
1183 @item @b{Delay after reset}...
1184 Not all chips have good support for debugger access
1185 right after reset; many LPC2xxx chips have issues here.
1186 Similarly, applications that reconfigure pins used for
1187 JTAG access as they start will also block debugger access.
1188
1189 To work with boards like this, @emph{enable a short delay loop}
1190 the first thing after reset, before "real" startup activities.
1191 For example, one second's delay is usually more than enough
1192 time for a JTAG debugger to attach, so that
1193 early code execution can be debugged
1194 or firmware can be replaced.
1195
1196 @item @b{Debug Communications Channel (DCC)}...
1197 Some processors include mechanisms to send messages over JTAG.
1198 Many ARM cores support these, as do some cores from other vendors.
1199 (OpenOCD may be able to use this DCC internally, speeding up some
1200 operations like writing to memory.)
1201
1202 Your application may want to deliver various debugging messages
1203 over JTAG, by @emph{linking with a small library of code}
1204 provided with OpenOCD and using the utilities there to send
1205 various kinds of message.
1206 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1207
1208 @end itemize
1209
1210 @section Target Hardware Setup
1211
1212 Chip vendors often provide software development boards which
1213 are highly configurable, so that they can support all options
1214 that product boards may require. @emph{Make sure that any
1215 jumpers or switches match the system configuration you are
1216 working with.}
1217
1218 Common issues include:
1219
1220 @itemize @bullet
1221
1222 @item @b{JTAG setup} ...
1223 Boards may support more than one JTAG configuration.
1224 Examples include jumpers controlling pullups versus pulldowns
1225 on the nTRST and/or nSRST signals, and choice of connectors
1226 (e.g. which of two headers on the base board,
1227 or one from a daughtercard).
1228 For some Texas Instruments boards, you may need to jumper the
1229 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1230
1231 @item @b{Boot Modes} ...
1232 Complex chips often support multiple boot modes, controlled
1233 by external jumpers. Make sure this is set up correctly.
1234 For example many i.MX boards from NXP need to be jumpered
1235 to "ATX mode" to start booting using the on-chip ROM, when
1236 using second stage bootloader code stored in a NAND flash chip.
1237
1238 Such explicit configuration is common, and not limited to
1239 booting from NAND. You might also need to set jumpers to
1240 start booting using code loaded from an MMC/SD card; external
1241 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1242 flash; some external host; or various other sources.
1243
1244
1245 @item @b{Memory Addressing} ...
1246 Boards which support multiple boot modes may also have jumpers
1247 to configure memory addressing. One board, for example, jumpers
1248 external chipselect 0 (used for booting) to address either
1249 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1250 or NAND flash. When it's jumpered to address NAND flash, that
1251 board must also be told to start booting from on-chip ROM.
1252
1253 Your @file{board.cfg} file may also need to be told this jumper
1254 configuration, so that it can know whether to declare NOR flash
1255 using @command{flash bank} or instead declare NAND flash with
1256 @command{nand device}; and likewise which probe to perform in
1257 its @code{reset-init} handler.
1258
1259 A closely related issue is bus width. Jumpers might need to
1260 distinguish between 8 bit or 16 bit bus access for the flash
1261 used to start booting.
1262
1263 @item @b{Peripheral Access} ...
1264 Development boards generally provide access to every peripheral
1265 on the chip, sometimes in multiple modes (such as by providing
1266 multiple audio codec chips).
1267 This interacts with software
1268 configuration of pin multiplexing, where for example a
1269 given pin may be routed either to the MMC/SD controller
1270 or the GPIO controller. It also often interacts with
1271 configuration jumpers. One jumper may be used to route
1272 signals to an MMC/SD card slot or an expansion bus (which
1273 might in turn affect booting); others might control which
1274 audio or video codecs are used.
1275
1276 @end itemize
1277
1278 Plus you should of course have @code{reset-init} event handlers
1279 which set up the hardware to match that jumper configuration.
1280 That includes in particular any oscillator or PLL used to clock
1281 the CPU, and any memory controllers needed to access external
1282 memory and peripherals. Without such handlers, you won't be
1283 able to access those resources without working target firmware
1284 which can do that setup ... this can be awkward when you're
1285 trying to debug that target firmware. Even if there's a ROM
1286 bootloader which handles a few issues, it rarely provides full
1287 access to all board-specific capabilities.
1288
1289
1290 @node Config File Guidelines
1291 @chapter Config File Guidelines
1292
1293 This chapter is aimed at any user who needs to write a config file,
1294 including developers and integrators of OpenOCD and any user who
1295 needs to get a new board working smoothly.
1296 It provides guidelines for creating those files.
1297
1298 You should find the following directories under
1299 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1300 them as-is where you can; or as models for new files.
1301 @itemize @bullet
1302 @item @file{interface} ...
1303 These are for debug adapters. Files that specify configuration to use
1304 specific JTAG, SWD and other adapters go here.
1305 @item @file{board} ...
1306 Think Circuit Board, PWA, PCB, they go by many names. Board files
1307 contain initialization items that are specific to a board.
1308
1309 They reuse target configuration files, since the same
1310 microprocessor chips are used on many boards,
1311 but support for external parts varies widely. For
1312 example, the SDRAM initialization sequence for the board, or the type
1313 of external flash and what address it uses. Any initialization
1314 sequence to enable that external flash or SDRAM should be found in the
1315 board file. Boards may also contain multiple targets: two CPUs; or
1316 a CPU and an FPGA.
1317 @item @file{target} ...
1318 Think chip. The ``target'' directory represents the JTAG TAPs
1319 on a chip
1320 which OpenOCD should control, not a board. Two common types of targets
1321 are ARM chips and FPGA or CPLD chips.
1322 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1323 the target config file defines all of them.
1324 @item @emph{more} ... browse for other library files which may be useful.
1325 For example, there are various generic and CPU-specific utilities.
1326 @end itemize
1327
1328 The @file{openocd.cfg} user config
1329 file may override features in any of the above files by
1330 setting variables before sourcing the target file, or by adding
1331 commands specific to their situation.
1332
1333 @section Interface Config Files
1334
1335 The user config file
1336 should be able to source one of these files with a command like this:
1337
1338 @example
1339 source [find interface/FOOBAR.cfg]
1340 @end example
1341
1342 A preconfigured interface file should exist for every debug adapter
1343 in use today with OpenOCD.
1344 That said, perhaps some of these config files
1345 have only been used by the developer who created it.
1346
1347 A separate chapter gives information about how to set these up.
1348 @xref{Debug Adapter Configuration}.
1349 Read the OpenOCD source code (and Developer's Guide)
1350 if you have a new kind of hardware interface
1351 and need to provide a driver for it.
1352
1353 @section Board Config Files
1354 @cindex config file, board
1355 @cindex board config file
1356
1357 The user config file
1358 should be able to source one of these files with a command like this:
1359
1360 @example
1361 source [find board/FOOBAR.cfg]
1362 @end example
1363
1364 The point of a board config file is to package everything
1365 about a given board that user config files need to know.
1366 In summary the board files should contain (if present)
1367
1368 @enumerate
1369 @item One or more @command{source [find target/...cfg]} statements
1370 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1371 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1372 @item Target @code{reset} handlers for SDRAM and I/O configuration
1373 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1374 @item All things that are not ``inside a chip''
1375 @end enumerate
1376
1377 Generic things inside target chips belong in target config files,
1378 not board config files. So for example a @code{reset-init} event
1379 handler should know board-specific oscillator and PLL parameters,
1380 which it passes to target-specific utility code.
1381
1382 The most complex task of a board config file is creating such a
1383 @code{reset-init} event handler.
1384 Define those handlers last, after you verify the rest of the board
1385 configuration works.
1386
1387 @subsection Communication Between Config files
1388
1389 In addition to target-specific utility code, another way that
1390 board and target config files communicate is by following a
1391 convention on how to use certain variables.
1392
1393 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1394 Thus the rule we follow in OpenOCD is this: Variables that begin with
1395 a leading underscore are temporary in nature, and can be modified and
1396 used at will within a target configuration file.
1397
1398 Complex board config files can do the things like this,
1399 for a board with three chips:
1400
1401 @example
1402 # Chip #1: PXA270 for network side, big endian
1403 set CHIPNAME network
1404 set ENDIAN big
1405 source [find target/pxa270.cfg]
1406 # on return: _TARGETNAME = network.cpu
1407 # other commands can refer to the "network.cpu" target.
1408 $_TARGETNAME configure .... events for this CPU..
1409
1410 # Chip #2: PXA270 for video side, little endian
1411 set CHIPNAME video
1412 set ENDIAN little
1413 source [find target/pxa270.cfg]
1414 # on return: _TARGETNAME = video.cpu
1415 # other commands can refer to the "video.cpu" target.
1416 $_TARGETNAME configure .... events for this CPU..
1417
1418 # Chip #3: Xilinx FPGA for glue logic
1419 set CHIPNAME xilinx
1420 unset ENDIAN
1421 source [find target/spartan3.cfg]
1422 @end example
1423
1424 That example is oversimplified because it doesn't show any flash memory,
1425 or the @code{reset-init} event handlers to initialize external DRAM
1426 or (assuming it needs it) load a configuration into the FPGA.
1427 Such features are usually needed for low-level work with many boards,
1428 where ``low level'' implies that the board initialization software may
1429 not be working. (That's a common reason to need JTAG tools. Another
1430 is to enable working with microcontroller-based systems, which often
1431 have no debugging support except a JTAG connector.)
1432
1433 Target config files may also export utility functions to board and user
1434 config files. Such functions should use name prefixes, to help avoid
1435 naming collisions.
1436
1437 Board files could also accept input variables from user config files.
1438 For example, there might be a @code{J4_JUMPER} setting used to identify
1439 what kind of flash memory a development board is using, or how to set
1440 up other clocks and peripherals.
1441
1442 @subsection Variable Naming Convention
1443 @cindex variable names
1444
1445 Most boards have only one instance of a chip.
1446 However, it should be easy to create a board with more than
1447 one such chip (as shown above).
1448 Accordingly, we encourage these conventions for naming
1449 variables associated with different @file{target.cfg} files,
1450 to promote consistency and
1451 so that board files can override target defaults.
1452
1453 Inputs to target config files include:
1454
1455 @itemize @bullet
1456 @item @code{CHIPNAME} ...
1457 This gives a name to the overall chip, and is used as part of
1458 tap identifier dotted names.
1459 While the default is normally provided by the chip manufacturer,
1460 board files may need to distinguish between instances of a chip.
1461 @item @code{ENDIAN} ...
1462 By default @option{little} - although chips may hard-wire @option{big}.
1463 Chips that can't change endianness don't need to use this variable.
1464 @item @code{CPUTAPID} ...
1465 When OpenOCD examines the JTAG chain, it can be told verify the
1466 chips against the JTAG IDCODE register.
1467 The target file will hold one or more defaults, but sometimes the
1468 chip in a board will use a different ID (perhaps a newer revision).
1469 @end itemize
1470
1471 Outputs from target config files include:
1472
1473 @itemize @bullet
1474 @item @code{_TARGETNAME} ...
1475 By convention, this variable is created by the target configuration
1476 script. The board configuration file may make use of this variable to
1477 configure things like a ``reset init'' script, or other things
1478 specific to that board and that target.
1479 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1480 @code{_TARGETNAME1}, ... etc.
1481 @end itemize
1482
1483 @subsection The reset-init Event Handler
1484 @cindex event, reset-init
1485 @cindex reset-init handler
1486
1487 Board config files run in the OpenOCD configuration stage;
1488 they can't use TAPs or targets, since they haven't been
1489 fully set up yet.
1490 This means you can't write memory or access chip registers;
1491 you can't even verify that a flash chip is present.
1492 That's done later in event handlers, of which the target @code{reset-init}
1493 handler is one of the most important.
1494
1495 Except on microcontrollers, the basic job of @code{reset-init} event
1496 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1497 Microcontrollers rarely use boot loaders; they run right out of their
1498 on-chip flash and SRAM memory. But they may want to use one of these
1499 handlers too, if just for developer convenience.
1500
1501 @quotation Note
1502 Because this is so very board-specific, and chip-specific, no examples
1503 are included here.
1504 Instead, look at the board config files distributed with OpenOCD.
1505 If you have a boot loader, its source code will help; so will
1506 configuration files for other JTAG tools
1507 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1508 @end quotation
1509
1510 Some of this code could probably be shared between different boards.
1511 For example, setting up a DRAM controller often doesn't differ by
1512 much except the bus width (16 bits or 32?) and memory timings, so a
1513 reusable TCL procedure loaded by the @file{target.cfg} file might take
1514 those as parameters.
1515 Similarly with oscillator, PLL, and clock setup;
1516 and disabling the watchdog.
1517 Structure the code cleanly, and provide comments to help
1518 the next developer doing such work.
1519 (@emph{You might be that next person} trying to reuse init code!)
1520
1521 The last thing normally done in a @code{reset-init} handler is probing
1522 whatever flash memory was configured. For most chips that needs to be
1523 done while the associated target is halted, either because JTAG memory
1524 access uses the CPU or to prevent conflicting CPU access.
1525
1526 @subsection JTAG Clock Rate
1527
1528 Before your @code{reset-init} handler has set up
1529 the PLLs and clocking, you may need to run with
1530 a low JTAG clock rate.
1531 @xref{jtagspeed,,JTAG Speed}.
1532 Then you'd increase that rate after your handler has
1533 made it possible to use the faster JTAG clock.
1534 When the initial low speed is board-specific, for example
1535 because it depends on a board-specific oscillator speed, then
1536 you should probably set it up in the board config file;
1537 if it's target-specific, it belongs in the target config file.
1538
1539 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1540 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1541 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1542 Consult chip documentation to determine the peak JTAG clock rate,
1543 which might be less than that.
1544
1545 @quotation Warning
1546 On most ARMs, JTAG clock detection is coupled to the core clock, so
1547 software using a @option{wait for interrupt} operation blocks JTAG access.
1548 Adaptive clocking provides a partial workaround, but a more complete
1549 solution just avoids using that instruction with JTAG debuggers.
1550 @end quotation
1551
1552 If both the chip and the board support adaptive clocking,
1553 use the @command{jtag_rclk}
1554 command, in case your board is used with JTAG adapter which
1555 also supports it. Otherwise use @command{adapter_khz}.
1556 Set the slow rate at the beginning of the reset sequence,
1557 and the faster rate as soon as the clocks are at full speed.
1558
1559 @anchor{theinitboardprocedure}
1560 @subsection The init_board procedure
1561 @cindex init_board procedure
1562
1563 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1564 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1565 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1566 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1567 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1568 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1569 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1570 Additionally ``linear'' board config file will most likely fail when target config file uses
1571 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1572 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1573 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1574 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1575
1576 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1577 the original), allowing greater code reuse.
1578
1579 @example
1580 ### board_file.cfg ###
1581
1582 # source target file that does most of the config in init_targets
1583 source [find target/target.cfg]
1584
1585 proc enable_fast_clock @{@} @{
1586 # enables fast on-board clock source
1587 # configures the chip to use it
1588 @}
1589
1590 # initialize only board specifics - reset, clock, adapter frequency
1591 proc init_board @{@} @{
1592 reset_config trst_and_srst trst_pulls_srst
1593
1594 $_TARGETNAME configure -event reset-init @{
1595 adapter_khz 1
1596 enable_fast_clock
1597 adapter_khz 10000
1598 @}
1599 @}
1600 @end example
1601
1602 @section Target Config Files
1603 @cindex config file, target
1604 @cindex target config file
1605
1606 Board config files communicate with target config files using
1607 naming conventions as described above, and may source one or
1608 more target config files like this:
1609
1610 @example
1611 source [find target/FOOBAR.cfg]
1612 @end example
1613
1614 The point of a target config file is to package everything
1615 about a given chip that board config files need to know.
1616 In summary the target files should contain
1617
1618 @enumerate
1619 @item Set defaults
1620 @item Add TAPs to the scan chain
1621 @item Add CPU targets (includes GDB support)
1622 @item CPU/Chip/CPU-Core specific features
1623 @item On-Chip flash
1624 @end enumerate
1625
1626 As a rule of thumb, a target file sets up only one chip.
1627 For a microcontroller, that will often include a single TAP,
1628 which is a CPU needing a GDB target, and its on-chip flash.
1629
1630 More complex chips may include multiple TAPs, and the target
1631 config file may need to define them all before OpenOCD
1632 can talk to the chip.
1633 For example, some phone chips have JTAG scan chains that include
1634 an ARM core for operating system use, a DSP,
1635 another ARM core embedded in an image processing engine,
1636 and other processing engines.
1637
1638 @subsection Default Value Boiler Plate Code
1639
1640 All target configuration files should start with code like this,
1641 letting board config files express environment-specific
1642 differences in how things should be set up.
1643
1644 @example
1645 # Boards may override chip names, perhaps based on role,
1646 # but the default should match what the vendor uses
1647 if @{ [info exists CHIPNAME] @} @{
1648 set _CHIPNAME $CHIPNAME
1649 @} else @{
1650 set _CHIPNAME sam7x256
1651 @}
1652
1653 # ONLY use ENDIAN with targets that can change it.
1654 if @{ [info exists ENDIAN] @} @{
1655 set _ENDIAN $ENDIAN
1656 @} else @{
1657 set _ENDIAN little
1658 @}
1659
1660 # TAP identifiers may change as chips mature, for example with
1661 # new revision fields (the "3" here). Pick a good default; you
1662 # can pass several such identifiers to the "jtag newtap" command.
1663 if @{ [info exists CPUTAPID ] @} @{
1664 set _CPUTAPID $CPUTAPID
1665 @} else @{
1666 set _CPUTAPID 0x3f0f0f0f
1667 @}
1668 @end example
1669 @c but 0x3f0f0f0f is for an str73x part ...
1670
1671 @emph{Remember:} Board config files may include multiple target
1672 config files, or the same target file multiple times
1673 (changing at least @code{CHIPNAME}).
1674
1675 Likewise, the target configuration file should define
1676 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1677 use it later on when defining debug targets:
1678
1679 @example
1680 set _TARGETNAME $_CHIPNAME.cpu
1681 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1682 @end example
1683
1684 @subsection Adding TAPs to the Scan Chain
1685 After the ``defaults'' are set up,
1686 add the TAPs on each chip to the JTAG scan chain.
1687 @xref{TAP Declaration}, and the naming convention
1688 for taps.
1689
1690 In the simplest case the chip has only one TAP,
1691 probably for a CPU or FPGA.
1692 The config file for the Atmel AT91SAM7X256
1693 looks (in part) like this:
1694
1695 @example
1696 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1697 @end example
1698
1699 A board with two such at91sam7 chips would be able
1700 to source such a config file twice, with different
1701 values for @code{CHIPNAME}, so
1702 it adds a different TAP each time.
1703
1704 If there are nonzero @option{-expected-id} values,
1705 OpenOCD attempts to verify the actual tap id against those values.
1706 It will issue error messages if there is mismatch, which
1707 can help to pinpoint problems in OpenOCD configurations.
1708
1709 @example
1710 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1711 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1712 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1713 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1714 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1715 @end example
1716
1717 There are more complex examples too, with chips that have
1718 multiple TAPs. Ones worth looking at include:
1719
1720 @itemize
1721 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1722 plus a JRC to enable them
1723 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1724 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1725 is not currently used)
1726 @end itemize
1727
1728 @subsection Add CPU targets
1729
1730 After adding a TAP for a CPU, you should set it up so that
1731 GDB and other commands can use it.
1732 @xref{CPU Configuration}.
1733 For the at91sam7 example above, the command can look like this;
1734 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1735 to little endian, and this chip doesn't support changing that.
1736
1737 @example
1738 set _TARGETNAME $_CHIPNAME.cpu
1739 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1740 @end example
1741
1742 Work areas are small RAM areas associated with CPU targets.
1743 They are used by OpenOCD to speed up downloads,
1744 and to download small snippets of code to program flash chips.
1745 If the chip includes a form of ``on-chip-ram'' - and many do - define
1746 a work area if you can.
1747 Again using the at91sam7 as an example, this can look like:
1748
1749 @example
1750 $_TARGETNAME configure -work-area-phys 0x00200000 \
1751 -work-area-size 0x4000 -work-area-backup 0
1752 @end example
1753
1754 @anchor{definecputargetsworkinginsmp}
1755 @subsection Define CPU targets working in SMP
1756 @cindex SMP
1757 After setting targets, you can define a list of targets working in SMP.
1758
1759 @example
1760 set _TARGETNAME_1 $_CHIPNAME.cpu1
1761 set _TARGETNAME_2 $_CHIPNAME.cpu2
1762 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1763 -coreid 0 -dbgbase $_DAP_DBG1
1764 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1765 -coreid 1 -dbgbase $_DAP_DBG2
1766 #define 2 targets working in smp.
1767 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1768 @end example
1769 In the above example on cortex_a, 2 cpus are working in SMP.
1770 In SMP only one GDB instance is created and :
1771 @itemize @bullet
1772 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1773 @item halt command triggers the halt of all targets in the list.
1774 @item resume command triggers the write context and the restart of all targets in the list.
1775 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1776 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1777 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1778 @end itemize
1779
1780 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1781 command have been implemented.
1782 @itemize @bullet
1783 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1784 @item cortex_a smp_off : disable SMP mode, the current target is the one
1785 displayed in the GDB session, only this target is now controlled by GDB
1786 session. This behaviour is useful during system boot up.
1787 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1788 following example.
1789 @end itemize
1790
1791 @example
1792 >cortex_a smp_gdb
1793 gdb coreid 0 -> -1
1794 #0 : coreid 0 is displayed to GDB ,
1795 #-> -1 : next resume triggers a real resume
1796 > cortex_a smp_gdb 1
1797 gdb coreid 0 -> 1
1798 #0 :coreid 0 is displayed to GDB ,
1799 #->1 : next resume displays coreid 1 to GDB
1800 > resume
1801 > cortex_a smp_gdb
1802 gdb coreid 1 -> 1
1803 #1 :coreid 1 is displayed to GDB ,
1804 #->1 : next resume displays coreid 1 to GDB
1805 > cortex_a smp_gdb -1
1806 gdb coreid 1 -> -1
1807 #1 :coreid 1 is displayed to GDB,
1808 #->-1 : next resume triggers a real resume
1809 @end example
1810
1811
1812 @subsection Chip Reset Setup
1813
1814 As a rule, you should put the @command{reset_config} command
1815 into the board file. Most things you think you know about a
1816 chip can be tweaked by the board.
1817
1818 Some chips have specific ways the TRST and SRST signals are
1819 managed. In the unusual case that these are @emph{chip specific}
1820 and can never be changed by board wiring, they could go here.
1821 For example, some chips can't support JTAG debugging without
1822 both signals.
1823
1824 Provide a @code{reset-assert} event handler if you can.
1825 Such a handler uses JTAG operations to reset the target,
1826 letting this target config be used in systems which don't
1827 provide the optional SRST signal, or on systems where you
1828 don't want to reset all targets at once.
1829 Such a handler might write to chip registers to force a reset,
1830 use a JRC to do that (preferable -- the target may be wedged!),
1831 or force a watchdog timer to trigger.
1832 (For Cortex-M targets, this is not necessary. The target
1833 driver knows how to use trigger an NVIC reset when SRST is
1834 not available.)
1835
1836 Some chips need special attention during reset handling if
1837 they're going to be used with JTAG.
1838 An example might be needing to send some commands right
1839 after the target's TAP has been reset, providing a
1840 @code{reset-deassert-post} event handler that writes a chip
1841 register to report that JTAG debugging is being done.
1842 Another would be reconfiguring the watchdog so that it stops
1843 counting while the core is halted in the debugger.
1844
1845 JTAG clocking constraints often change during reset, and in
1846 some cases target config files (rather than board config files)
1847 are the right places to handle some of those issues.
1848 For example, immediately after reset most chips run using a
1849 slower clock than they will use later.
1850 That means that after reset (and potentially, as OpenOCD
1851 first starts up) they must use a slower JTAG clock rate
1852 than they will use later.
1853 @xref{jtagspeed,,JTAG Speed}.
1854
1855 @quotation Important
1856 When you are debugging code that runs right after chip
1857 reset, getting these issues right is critical.
1858 In particular, if you see intermittent failures when
1859 OpenOCD verifies the scan chain after reset,
1860 look at how you are setting up JTAG clocking.
1861 @end quotation
1862
1863 @anchor{theinittargetsprocedure}
1864 @subsection The init_targets procedure
1865 @cindex init_targets procedure
1866
1867 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1868 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1869 procedure called @code{init_targets}, which will be executed when entering run stage
1870 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1871 Such procedure can be overriden by ``next level'' script (which sources the original).
1872 This concept faciliates code reuse when basic target config files provide generic configuration
1873 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
1874 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1875 because sourcing them executes every initialization commands they provide.
1876
1877 @example
1878 ### generic_file.cfg ###
1879
1880 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1881 # basic initialization procedure ...
1882 @}
1883
1884 proc init_targets @{@} @{
1885 # initializes generic chip with 4kB of flash and 1kB of RAM
1886 setup_my_chip MY_GENERIC_CHIP 4096 1024
1887 @}
1888
1889 ### specific_file.cfg ###
1890
1891 source [find target/generic_file.cfg]
1892
1893 proc init_targets @{@} @{
1894 # initializes specific chip with 128kB of flash and 64kB of RAM
1895 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1896 @}
1897 @end example
1898
1899 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1900 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1901
1902 For an example of this scheme see LPC2000 target config files.
1903
1904 The @code{init_boards} procedure is a similar concept concerning board config files
1905 (@xref{theinitboardprocedure,,The init_board procedure}.)
1906
1907 @anchor{theinittargeteventsprocedure}
1908 @subsection The init_target_events procedure
1909 @cindex init_target_events procedure
1910
1911 A special procedure called @code{init_target_events} is run just after
1912 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1913 procedure}.) and before @code{init_board}
1914 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1915 to set up default target events for the targets that do not have those
1916 events already assigned.
1917
1918 @subsection ARM Core Specific Hacks
1919
1920 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1921 special high speed download features - enable it.
1922
1923 If present, the MMU, the MPU and the CACHE should be disabled.
1924
1925 Some ARM cores are equipped with trace support, which permits
1926 examination of the instruction and data bus activity. Trace
1927 activity is controlled through an ``Embedded Trace Module'' (ETM)
1928 on one of the core's scan chains. The ETM emits voluminous data
1929 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1930 If you are using an external trace port,
1931 configure it in your board config file.
1932 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1933 configure it in your target config file.
1934
1935 @example
1936 etm config $_TARGETNAME 16 normal full etb
1937 etb config $_TARGETNAME $_CHIPNAME.etb
1938 @end example
1939
1940 @subsection Internal Flash Configuration
1941
1942 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1943
1944 @b{Never ever} in the ``target configuration file'' define any type of
1945 flash that is external to the chip. (For example a BOOT flash on
1946 Chip Select 0.) Such flash information goes in a board file - not
1947 the TARGET (chip) file.
1948
1949 Examples:
1950 @itemize @bullet
1951 @item at91sam7x256 - has 256K flash YES enable it.
1952 @item str912 - has flash internal YES enable it.
1953 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1954 @item pxa270 - again - CS0 flash - it goes in the board file.
1955 @end itemize
1956
1957 @anchor{translatingconfigurationfiles}
1958 @section Translating Configuration Files
1959 @cindex translation
1960 If you have a configuration file for another hardware debugger
1961 or toolset (Abatron, BDI2000, BDI3000, CCS,
1962 Lauterbach, SEGGER, Macraigor, etc.), translating
1963 it into OpenOCD syntax is often quite straightforward. The most tricky
1964 part of creating a configuration script is oftentimes the reset init
1965 sequence where e.g. PLLs, DRAM and the like is set up.
1966
1967 One trick that you can use when translating is to write small
1968 Tcl procedures to translate the syntax into OpenOCD syntax. This
1969 can avoid manual translation errors and make it easier to
1970 convert other scripts later on.
1971
1972 Example of transforming quirky arguments to a simple search and
1973 replace job:
1974
1975 @example
1976 # Lauterbach syntax(?)
1977 #
1978 # Data.Set c15:0x042f %long 0x40000015
1979 #
1980 # OpenOCD syntax when using procedure below.
1981 #
1982 # setc15 0x01 0x00050078
1983
1984 proc setc15 @{regs value@} @{
1985 global TARGETNAME
1986
1987 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
1988
1989 arm mcr 15 [expr ($regs>>12)&0x7] \
1990 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
1991 [expr ($regs>>8)&0x7] $value
1992 @}
1993 @end example
1994
1995
1996
1997 @node Server Configuration
1998 @chapter Server Configuration
1999 @cindex initialization
2000 The commands here are commonly found in the openocd.cfg file and are
2001 used to specify what TCP/IP ports are used, and how GDB should be
2002 supported.
2003
2004 @anchor{configurationstage}
2005 @section Configuration Stage
2006 @cindex configuration stage
2007 @cindex config command
2008
2009 When the OpenOCD server process starts up, it enters a
2010 @emph{configuration stage} which is the only time that
2011 certain commands, @emph{configuration commands}, may be issued.
2012 Normally, configuration commands are only available
2013 inside startup scripts.
2014
2015 In this manual, the definition of a configuration command is
2016 presented as a @emph{Config Command}, not as a @emph{Command}
2017 which may be issued interactively.
2018 The runtime @command{help} command also highlights configuration
2019 commands, and those which may be issued at any time.
2020
2021 Those configuration commands include declaration of TAPs,
2022 flash banks,
2023 the interface used for JTAG communication,
2024 and other basic setup.
2025 The server must leave the configuration stage before it
2026 may access or activate TAPs.
2027 After it leaves this stage, configuration commands may no
2028 longer be issued.
2029
2030 @anchor{enteringtherunstage}
2031 @section Entering the Run Stage
2032
2033 The first thing OpenOCD does after leaving the configuration
2034 stage is to verify that it can talk to the scan chain
2035 (list of TAPs) which has been configured.
2036 It will warn if it doesn't find TAPs it expects to find,
2037 or finds TAPs that aren't supposed to be there.
2038 You should see no errors at this point.
2039 If you see errors, resolve them by correcting the
2040 commands you used to configure the server.
2041 Common errors include using an initial JTAG speed that's too
2042 fast, and not providing the right IDCODE values for the TAPs
2043 on the scan chain.
2044
2045 Once OpenOCD has entered the run stage, a number of commands
2046 become available.
2047 A number of these relate to the debug targets you may have declared.
2048 For example, the @command{mww} command will not be available until
2049 a target has been successfuly instantiated.
2050 If you want to use those commands, you may need to force
2051 entry to the run stage.
2052
2053 @deffn {Config Command} init
2054 This command terminates the configuration stage and
2055 enters the run stage. This helps when you need to have
2056 the startup scripts manage tasks such as resetting the target,
2057 programming flash, etc. To reset the CPU upon startup, add "init" and
2058 "reset" at the end of the config script or at the end of the OpenOCD
2059 command line using the @option{-c} command line switch.
2060
2061 If this command does not appear in any startup/configuration file
2062 OpenOCD executes the command for you after processing all
2063 configuration files and/or command line options.
2064
2065 @b{NOTE:} This command normally occurs at or near the end of your
2066 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2067 targets ready. For example: If your openocd.cfg file needs to
2068 read/write memory on your target, @command{init} must occur before
2069 the memory read/write commands. This includes @command{nand probe}.
2070 @end deffn
2071
2072 @deffn {Overridable Procedure} jtag_init
2073 This is invoked at server startup to verify that it can talk
2074 to the scan chain (list of TAPs) which has been configured.
2075
2076 The default implementation first tries @command{jtag arp_init},
2077 which uses only a lightweight JTAG reset before examining the
2078 scan chain.
2079 If that fails, it tries again, using a harder reset
2080 from the overridable procedure @command{init_reset}.
2081
2082 Implementations must have verified the JTAG scan chain before
2083 they return.
2084 This is done by calling @command{jtag arp_init}
2085 (or @command{jtag arp_init-reset}).
2086 @end deffn
2087
2088 @anchor{tcpipports}
2089 @section TCP/IP Ports
2090 @cindex TCP port
2091 @cindex server
2092 @cindex port
2093 @cindex security
2094 The OpenOCD server accepts remote commands in several syntaxes.
2095 Each syntax uses a different TCP/IP port, which you may specify
2096 only during configuration (before those ports are opened).
2097
2098 For reasons including security, you may wish to prevent remote
2099 access using one or more of these ports.
2100 In such cases, just specify the relevant port number as "disabled".
2101 If you disable all access through TCP/IP, you will need to
2102 use the command line @option{-pipe} option.
2103
2104 @deffn {Command} gdb_port [number]
2105 @cindex GDB server
2106 Normally gdb listens to a TCP/IP port, but GDB can also
2107 communicate via pipes(stdin/out or named pipes). The name
2108 "gdb_port" stuck because it covers probably more than 90% of
2109 the normal use cases.
2110
2111 No arguments reports GDB port. "pipe" means listen to stdin
2112 output to stdout, an integer is base port number, "disabled"
2113 disables the gdb server.
2114
2115 When using "pipe", also use log_output to redirect the log
2116 output to a file so as not to flood the stdin/out pipes.
2117
2118 The -p/--pipe option is deprecated and a warning is printed
2119 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2120
2121 Any other string is interpreted as named pipe to listen to.
2122 Output pipe is the same name as input pipe, but with 'o' appended,
2123 e.g. /var/gdb, /var/gdbo.
2124
2125 The GDB port for the first target will be the base port, the
2126 second target will listen on gdb_port + 1, and so on.
2127 When not specified during the configuration stage,
2128 the port @var{number} defaults to 3333.
2129
2130 Note: when using "gdb_port pipe", increasing the default remote timeout in
2131 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2132 cause initialization to fail with "Unknown remote qXfer reply: OK".
2133
2134 @end deffn
2135
2136 @deffn {Command} tcl_port [number]
2137 Specify or query the port used for a simplified RPC
2138 connection that can be used by clients to issue TCL commands and get the
2139 output from the Tcl engine.
2140 Intended as a machine interface.
2141 When not specified during the configuration stage,
2142 the port @var{number} defaults to 6666.
2143 When specified as "disabled", this service is not activated.
2144 @end deffn
2145
2146 @deffn {Command} telnet_port [number]
2147 Specify or query the
2148 port on which to listen for incoming telnet connections.
2149 This port is intended for interaction with one human through TCL commands.
2150 When not specified during the configuration stage,
2151 the port @var{number} defaults to 4444.
2152 When specified as "disabled", this service is not activated.
2153 @end deffn
2154
2155 @anchor{gdbconfiguration}
2156 @section GDB Configuration
2157 @cindex GDB
2158 @cindex GDB configuration
2159 You can reconfigure some GDB behaviors if needed.
2160 The ones listed here are static and global.
2161 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2162 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2163
2164 @anchor{gdbbreakpointoverride}
2165 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2166 Force breakpoint type for gdb @command{break} commands.
2167 This option supports GDB GUIs which don't
2168 distinguish hard versus soft breakpoints, if the default OpenOCD and
2169 GDB behaviour is not sufficient. GDB normally uses hardware
2170 breakpoints if the memory map has been set up for flash regions.
2171 @end deffn
2172
2173 @anchor{gdbflashprogram}
2174 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2175 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2176 vFlash packet is received.
2177 The default behaviour is @option{enable}.
2178 @end deffn
2179
2180 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2181 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2182 requested. GDB will then know when to set hardware breakpoints, and program flash
2183 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2184 for flash programming to work.
2185 Default behaviour is @option{enable}.
2186 @xref{gdbflashprogram,,gdb_flash_program}.
2187 @end deffn
2188
2189 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2190 Specifies whether data aborts cause an error to be reported
2191 by GDB memory read packets.
2192 The default behaviour is @option{disable};
2193 use @option{enable} see these errors reported.
2194 @end deffn
2195
2196 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2197 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2198 The default behaviour is @option{enable}.
2199 @end deffn
2200
2201 @deffn {Command} gdb_save_tdesc
2202 Saves the target descripton file to the local file system.
2203
2204 The file name is @i{target_name}.xml.
2205 @end deffn
2206
2207 @anchor{eventpolling}
2208 @section Event Polling
2209
2210 Hardware debuggers are parts of asynchronous systems,
2211 where significant events can happen at any time.
2212 The OpenOCD server needs to detect some of these events,
2213 so it can report them to through TCL command line
2214 or to GDB.
2215
2216 Examples of such events include:
2217
2218 @itemize
2219 @item One of the targets can stop running ... maybe it triggers
2220 a code breakpoint or data watchpoint, or halts itself.
2221 @item Messages may be sent over ``debug message'' channels ... many
2222 targets support such messages sent over JTAG,
2223 for receipt by the person debugging or tools.
2224 @item Loss of power ... some adapters can detect these events.
2225 @item Resets not issued through JTAG ... such reset sources
2226 can include button presses or other system hardware, sometimes
2227 including the target itself (perhaps through a watchdog).
2228 @item Debug instrumentation sometimes supports event triggering
2229 such as ``trace buffer full'' (so it can quickly be emptied)
2230 or other signals (to correlate with code behavior).
2231 @end itemize
2232
2233 None of those events are signaled through standard JTAG signals.
2234 However, most conventions for JTAG connectors include voltage
2235 level and system reset (SRST) signal detection.
2236 Some connectors also include instrumentation signals, which
2237 can imply events when those signals are inputs.
2238
2239 In general, OpenOCD needs to periodically check for those events,
2240 either by looking at the status of signals on the JTAG connector
2241 or by sending synchronous ``tell me your status'' JTAG requests
2242 to the various active targets.
2243 There is a command to manage and monitor that polling,
2244 which is normally done in the background.
2245
2246 @deffn Command poll [@option{on}|@option{off}]
2247 Poll the current target for its current state.
2248 (Also, @pxref{targetcurstate,,target curstate}.)
2249 If that target is in debug mode, architecture
2250 specific information about the current state is printed.
2251 An optional parameter
2252 allows background polling to be enabled and disabled.
2253
2254 You could use this from the TCL command shell, or
2255 from GDB using @command{monitor poll} command.
2256 Leave background polling enabled while you're using GDB.
2257 @example
2258 > poll
2259 background polling: on
2260 target state: halted
2261 target halted in ARM state due to debug-request, \
2262 current mode: Supervisor
2263 cpsr: 0x800000d3 pc: 0x11081bfc
2264 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2265 >
2266 @end example
2267 @end deffn
2268
2269 @node Debug Adapter Configuration
2270 @chapter Debug Adapter Configuration
2271 @cindex config file, interface
2272 @cindex interface config file
2273
2274 Correctly installing OpenOCD includes making your operating system give
2275 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2276 are used to select which one is used, and to configure how it is used.
2277
2278 @quotation Note
2279 Because OpenOCD started out with a focus purely on JTAG, you may find
2280 places where it wrongly presumes JTAG is the only transport protocol
2281 in use. Be aware that recent versions of OpenOCD are removing that
2282 limitation. JTAG remains more functional than most other transports.
2283 Other transports do not support boundary scan operations, or may be
2284 specific to a given chip vendor. Some might be usable only for
2285 programming flash memory, instead of also for debugging.
2286 @end quotation
2287
2288 Debug Adapters/Interfaces/Dongles are normally configured
2289 through commands in an interface configuration
2290 file which is sourced by your @file{openocd.cfg} file, or
2291 through a command line @option{-f interface/....cfg} option.
2292
2293 @example
2294 source [find interface/olimex-jtag-tiny.cfg]
2295 @end example
2296
2297 These commands tell
2298 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2299 A few cases are so simple that you only need to say what driver to use:
2300
2301 @example
2302 # jlink interface
2303 interface jlink
2304 @end example
2305
2306 Most adapters need a bit more configuration than that.
2307
2308
2309 @section Interface Configuration
2310
2311 The interface command tells OpenOCD what type of debug adapter you are
2312 using. Depending on the type of adapter, you may need to use one or
2313 more additional commands to further identify or configure the adapter.
2314
2315 @deffn {Config Command} {interface} name
2316 Use the interface driver @var{name} to connect to the
2317 target.
2318 @end deffn
2319
2320 @deffn Command {interface_list}
2321 List the debug adapter drivers that have been built into
2322 the running copy of OpenOCD.
2323 @end deffn
2324 @deffn Command {interface transports} transport_name+
2325 Specifies the transports supported by this debug adapter.
2326 The adapter driver builds-in similar knowledge; use this only
2327 when external configuration (such as jumpering) changes what
2328 the hardware can support.
2329 @end deffn
2330
2331
2332
2333 @deffn Command {adapter_name}
2334 Returns the name of the debug adapter driver being used.
2335 @end deffn
2336
2337 @section Interface Drivers
2338
2339 Each of the interface drivers listed here must be explicitly
2340 enabled when OpenOCD is configured, in order to be made
2341 available at run time.
2342
2343 @deffn {Interface Driver} {amt_jtagaccel}
2344 Amontec Chameleon in its JTAG Accelerator configuration,
2345 connected to a PC's EPP mode parallel port.
2346 This defines some driver-specific commands:
2347
2348 @deffn {Config Command} {parport_port} number
2349 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2350 the number of the @file{/dev/parport} device.
2351 @end deffn
2352
2353 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2354 Displays status of RTCK option.
2355 Optionally sets that option first.
2356 @end deffn
2357 @end deffn
2358
2359 @deffn {Interface Driver} {arm-jtag-ew}
2360 Olimex ARM-JTAG-EW USB adapter
2361 This has one driver-specific command:
2362
2363 @deffn Command {armjtagew_info}
2364 Logs some status
2365 @end deffn
2366 @end deffn
2367
2368 @deffn {Interface Driver} {at91rm9200}
2369 Supports bitbanged JTAG from the local system,
2370 presuming that system is an Atmel AT91rm9200
2371 and a specific set of GPIOs is used.
2372 @c command: at91rm9200_device NAME
2373 @c chooses among list of bit configs ... only one option
2374 @end deffn
2375
2376 @deffn {Interface Driver} {cmsis-dap}
2377 ARM CMSIS-DAP compliant based adapter.
2378
2379 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2380 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2381 the driver will attempt to auto detect the CMSIS-DAP device.
2382 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2383 @example
2384 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2385 @end example
2386 @end deffn
2387
2388 @deffn {Config Command} {cmsis_dap_serial} [serial]
2389 Specifies the @var{serial} of the CMSIS-DAP device to use.
2390 If not specified, serial numbers are not considered.
2391 @end deffn
2392
2393 @deffn {Command} {cmsis-dap info}
2394 Display various device information, like hardware version, firmware version, current bus status.
2395 @end deffn
2396 @end deffn
2397
2398 @deffn {Interface Driver} {dummy}
2399 A dummy software-only driver for debugging.
2400 @end deffn
2401
2402 @deffn {Interface Driver} {ep93xx}
2403 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2404 @end deffn
2405
2406 @deffn {Interface Driver} {ftdi}
2407 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2408 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2409
2410 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2411 bypassing intermediate libraries like libftdi or D2XX.
2412
2413 Support for new FTDI based adapters can be added competely through
2414 configuration files, without the need to patch and rebuild OpenOCD.
2415
2416 The driver uses a signal abstraction to enable Tcl configuration files to
2417 define outputs for one or several FTDI GPIO. These outputs can then be
2418 controlled using the @command{ftdi_set_signal} command. Special signal names
2419 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2420 will be used for their customary purpose. Inputs can be read using the
2421 @command{ftdi_get_signal} command.
2422
2423 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2424 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2425 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2426 required by the protocol, to tell the adapter to drive the data output onto
2427 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2428
2429 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2430 be controlled differently. In order to support tristateable signals such as
2431 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2432 signal. The following output buffer configurations are supported:
2433
2434 @itemize @minus
2435 @item Push-pull with one FTDI output as (non-)inverted data line
2436 @item Open drain with one FTDI output as (non-)inverted output-enable
2437 @item Tristate with one FTDI output as (non-)inverted data line and another
2438 FTDI output as (non-)inverted output-enable
2439 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2440 switching data and direction as necessary
2441 @end itemize
2442
2443 These interfaces have several commands, used to configure the driver
2444 before initializing the JTAG scan chain:
2445
2446 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2447 The vendor ID and product ID of the adapter. Up to eight
2448 [@var{vid}, @var{pid}] pairs may be given, e.g.
2449 @example
2450 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2451 @end example
2452 @end deffn
2453
2454 @deffn {Config Command} {ftdi_device_desc} description
2455 Provides the USB device description (the @emph{iProduct string})
2456 of the adapter. If not specified, the device description is ignored
2457 during device selection.
2458 @end deffn
2459
2460 @deffn {Config Command} {ftdi_serial} serial-number
2461 Specifies the @var{serial-number} of the adapter to use,
2462 in case the vendor provides unique IDs and more than one adapter
2463 is connected to the host.
2464 If not specified, serial numbers are not considered.
2465 (Note that USB serial numbers can be arbitrary Unicode strings,
2466 and are not restricted to containing only decimal digits.)
2467 @end deffn
2468
2469 @deffn {Config Command} {ftdi_location} <bus>:<port>[,<port>]...
2470 Specifies the physical USB port of the adapter to use. The path
2471 roots at @var{bus} and walks down the physical ports, with each
2472 @var{port} option specifying a deeper level in the bus topology, the last
2473 @var{port} denoting where the target adapter is actually plugged.
2474 The USB bus topology can be queried with the command @emph{lsusb -t}.
2475
2476 This command is only available if your libusb1 is at least version 1.0.16.
2477 @end deffn
2478
2479 @deffn {Config Command} {ftdi_channel} channel
2480 Selects the channel of the FTDI device to use for MPSSE operations. Most
2481 adapters use the default, channel 0, but there are exceptions.
2482 @end deffn
2483
2484 @deffn {Config Command} {ftdi_layout_init} data direction
2485 Specifies the initial values of the FTDI GPIO data and direction registers.
2486 Each value is a 16-bit number corresponding to the concatenation of the high
2487 and low FTDI GPIO registers. The values should be selected based on the
2488 schematics of the adapter, such that all signals are set to safe levels with
2489 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2490 and initially asserted reset signals.
2491 @end deffn
2492
2493 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2494 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2495 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2496 register bitmasks to tell the driver the connection and type of the output
2497 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2498 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2499 used with inverting data inputs and @option{-data} with non-inverting inputs.
2500 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2501 not-output-enable) input to the output buffer is connected. The options
2502 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2503 with the method @command{ftdi_get_signal}.
2504
2505 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2506 simple open-collector transistor driver would be specified with @option{-oe}
2507 only. In that case the signal can only be set to drive low or to Hi-Z and the
2508 driver will complain if the signal is set to drive high. Which means that if
2509 it's a reset signal, @command{reset_config} must be specified as
2510 @option{srst_open_drain}, not @option{srst_push_pull}.
2511
2512 A special case is provided when @option{-data} and @option{-oe} is set to the
2513 same bitmask. Then the FTDI pin is considered being connected straight to the
2514 target without any buffer. The FTDI pin is then switched between output and
2515 input as necessary to provide the full set of low, high and Hi-Z
2516 characteristics. In all other cases, the pins specified in a signal definition
2517 are always driven by the FTDI.
2518
2519 If @option{-alias} or @option{-nalias} is used, the signal is created
2520 identical (or with data inverted) to an already specified signal
2521 @var{name}.
2522 @end deffn
2523
2524 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2525 Set a previously defined signal to the specified level.
2526 @itemize @minus
2527 @item @option{0}, drive low
2528 @item @option{1}, drive high
2529 @item @option{z}, set to high-impedance
2530 @end itemize
2531 @end deffn
2532
2533 @deffn {Command} {ftdi_get_signal} name
2534 Get the value of a previously defined signal.
2535 @end deffn
2536
2537 @deffn {Command} {ftdi_tdo_sample_edge} @option{rising}|@option{falling}
2538 Configure TCK edge at which the adapter samples the value of the TDO signal
2539
2540 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2541 peculiar at high JTAG clock speeds. However, FTDI chips offer a possiblity to sample
2542 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2543 stability at higher JTAG clocks.
2544 @itemize @minus
2545 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2546 @item @option{falling}, sample TDO on falling edge of TCK
2547 @end itemize
2548 @end deffn
2549
2550 For example adapter definitions, see the configuration files shipped in the
2551 @file{interface/ftdi} directory.
2552
2553 @end deffn
2554
2555 @deffn {Interface Driver} {remote_bitbang}
2556 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2557 with a remote process and sends ASCII encoded bitbang requests to that process
2558 instead of directly driving JTAG.
2559
2560 The remote_bitbang driver is useful for debugging software running on
2561 processors which are being simulated.
2562
2563 @deffn {Config Command} {remote_bitbang_port} number
2564 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2565 sockets instead of TCP.
2566 @end deffn
2567
2568 @deffn {Config Command} {remote_bitbang_host} hostname
2569 Specifies the hostname of the remote process to connect to using TCP, or the
2570 name of the UNIX socket to use if remote_bitbang_port is 0.
2571 @end deffn
2572
2573 For example, to connect remotely via TCP to the host foobar you might have
2574 something like:
2575
2576 @example
2577 interface remote_bitbang
2578 remote_bitbang_port 3335
2579 remote_bitbang_host foobar
2580 @end example
2581
2582 To connect to another process running locally via UNIX sockets with socket
2583 named mysocket:
2584
2585 @example
2586 interface remote_bitbang
2587 remote_bitbang_port 0
2588 remote_bitbang_host mysocket
2589 @end example
2590 @end deffn
2591
2592 @deffn {Interface Driver} {usb_blaster}
2593 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2594 for FTDI chips. These interfaces have several commands, used to
2595 configure the driver before initializing the JTAG scan chain:
2596
2597 @deffn {Config Command} {usb_blaster_device_desc} description
2598 Provides the USB device description (the @emph{iProduct string})
2599 of the FTDI FT245 device. If not
2600 specified, the FTDI default value is used. This setting is only valid
2601 if compiled with FTD2XX support.
2602 @end deffn
2603
2604 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2605 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2606 default values are used.
2607 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2608 Altera USB-Blaster (default):
2609 @example
2610 usb_blaster_vid_pid 0x09FB 0x6001
2611 @end example
2612 The following VID/PID is for Kolja Waschk's USB JTAG:
2613 @example
2614 usb_blaster_vid_pid 0x16C0 0x06AD
2615 @end example
2616 @end deffn
2617
2618 @deffn {Command} {usb_blaster_pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2619 Sets the state or function of the unused GPIO pins on USB-Blasters
2620 (pins 6 and 8 on the female JTAG header). These pins can be used as
2621 SRST and/or TRST provided the appropriate connections are made on the
2622 target board.
2623
2624 For example, to use pin 6 as SRST:
2625 @example
2626 usb_blaster_pin pin6 s
2627 reset_config srst_only
2628 @end example
2629 @end deffn
2630
2631 @deffn {Command} {usb_blaster_lowlevel_driver} (@option{ftdi}|@option{ublast2})
2632 Chooses the low level access method for the adapter. If not specified,
2633 @option{ftdi} is selected unless it wasn't enabled during the
2634 configure stage. USB-Blaster II needs @option{ublast2}.
2635 @end deffn
2636
2637 @deffn {Command} {usb_blaster_firmware} @var{path}
2638 This command specifies @var{path} to access USB-Blaster II firmware
2639 image. To be used with USB-Blaster II only.
2640 @end deffn
2641
2642 @end deffn
2643
2644 @deffn {Interface Driver} {gw16012}
2645 Gateworks GW16012 JTAG programmer.
2646 This has one driver-specific command:
2647
2648 @deffn {Config Command} {parport_port} [port_number]
2649 Display either the address of the I/O port
2650 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2651 If a parameter is provided, first switch to use that port.
2652 This is a write-once setting.
2653 @end deffn
2654 @end deffn
2655
2656 @deffn {Interface Driver} {jlink}
2657 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2658 transports.
2659
2660 @quotation Compatibility Note
2661 SEGGER released many firmware versions for the many harware versions they
2662 produced. OpenOCD was extensively tested and intended to run on all of them,
2663 but some combinations were reported as incompatible. As a general
2664 recommendation, it is advisable to use the latest firmware version
2665 available for each hardware version. However the current V8 is a moving
2666 target, and SEGGER firmware versions released after the OpenOCD was
2667 released may not be compatible. In such cases it is recommended to
2668 revert to the last known functional version. For 0.5.0, this is from
2669 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2670 version is from "May 3 2012 18:36:22", packed with 4.46f.
2671 @end quotation
2672
2673 @deffn {Command} {jlink hwstatus}
2674 Display various hardware related information, for example target voltage and pin
2675 states.
2676 @end deffn
2677 @deffn {Command} {jlink freemem}
2678 Display free device internal memory.
2679 @end deffn
2680 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2681 Set the JTAG command version to be used. Without argument, show the actual JTAG
2682 command version.
2683 @end deffn
2684 @deffn {Command} {jlink config}
2685 Display the device configuration.
2686 @end deffn
2687 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2688 Set the target power state on JTAG-pin 19. Without argument, show the target
2689 power state.
2690 @end deffn
2691 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2692 Set the MAC address of the device. Without argument, show the MAC address.
2693 @end deffn
2694 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2695 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2696 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2697 IP configuration.
2698 @end deffn
2699 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2700 Set the USB address of the device. This will also change the USB Product ID
2701 (PID) of the device. Without argument, show the USB address.
2702 @end deffn
2703 @deffn {Command} {jlink config reset}
2704 Reset the current configuration.
2705 @end deffn
2706 @deffn {Command} {jlink config write}
2707 Write the current configuration to the internal persistent storage.
2708 @end deffn
2709 @deffn {Command} {jlink emucom write <channel> <data>}
2710 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2711 pairs.
2712
2713 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2714 the EMUCOM channel 0x10:
2715 @example
2716 > jlink emucom write 0x10 aa0b23
2717 @end example
2718 @end deffn
2719 @deffn {Command} {jlink emucom read <channel> <length>}
2720 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2721 pairs.
2722
2723 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2724 @example
2725 > jlink emucom read 0x0 4
2726 77a90000
2727 @end example
2728 @end deffn
2729 @deffn {Config} {jlink usb} <@option{0} to @option{3}>
2730 Set the USB address of the interface, in case more than one adapter is connected
2731 to the host. If not specified, USB addresses are not considered. Device
2732 selection via USB address is deprecated and the serial number should be used
2733 instead.
2734
2735 As a configuration command, it can be used only before 'init'.
2736 @end deffn
2737 @deffn {Config} {jlink serial} <serial number>
2738 Set the serial number of the interface, in case more than one adapter is
2739 connected to the host. If not specified, serial numbers are not considered.
2740
2741 As a configuration command, it can be used only before 'init'.
2742 @end deffn
2743 @end deffn
2744
2745 @deffn {Interface Driver} {parport}
2746 Supports PC parallel port bit-banging cables:
2747 Wigglers, PLD download cable, and more.
2748 These interfaces have several commands, used to configure the driver
2749 before initializing the JTAG scan chain:
2750
2751 @deffn {Config Command} {parport_cable} name
2752 Set the layout of the parallel port cable used to connect to the target.
2753 This is a write-once setting.
2754 Currently valid cable @var{name} values include:
2755
2756 @itemize @minus
2757 @item @b{altium} Altium Universal JTAG cable.
2758 @item @b{arm-jtag} Same as original wiggler except SRST and
2759 TRST connections reversed and TRST is also inverted.
2760 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2761 in configuration mode. This is only used to
2762 program the Chameleon itself, not a connected target.
2763 @item @b{dlc5} The Xilinx Parallel cable III.
2764 @item @b{flashlink} The ST Parallel cable.
2765 @item @b{lattice} Lattice ispDOWNLOAD Cable
2766 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2767 some versions of
2768 Amontec's Chameleon Programmer. The new version available from
2769 the website uses the original Wiggler layout ('@var{wiggler}')
2770 @item @b{triton} The parallel port adapter found on the
2771 ``Karo Triton 1 Development Board''.
2772 This is also the layout used by the HollyGates design
2773 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2774 @item @b{wiggler} The original Wiggler layout, also supported by
2775 several clones, such as the Olimex ARM-JTAG
2776 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2777 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2778 @end itemize
2779 @end deffn
2780
2781 @deffn {Config Command} {parport_port} [port_number]
2782 Display either the address of the I/O port
2783 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2784 If a parameter is provided, first switch to use that port.
2785 This is a write-once setting.
2786
2787 When using PPDEV to access the parallel port, use the number of the parallel port:
2788 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2789 you may encounter a problem.
2790 @end deffn
2791
2792 @deffn Command {parport_toggling_time} [nanoseconds]
2793 Displays how many nanoseconds the hardware needs to toggle TCK;
2794 the parport driver uses this value to obey the
2795 @command{adapter_khz} configuration.
2796 When the optional @var{nanoseconds} parameter is given,
2797 that setting is changed before displaying the current value.
2798
2799 The default setting should work reasonably well on commodity PC hardware.
2800 However, you may want to calibrate for your specific hardware.
2801 @quotation Tip
2802 To measure the toggling time with a logic analyzer or a digital storage
2803 oscilloscope, follow the procedure below:
2804 @example
2805 > parport_toggling_time 1000
2806 > adapter_khz 500
2807 @end example
2808 This sets the maximum JTAG clock speed of the hardware, but
2809 the actual speed probably deviates from the requested 500 kHz.
2810 Now, measure the time between the two closest spaced TCK transitions.
2811 You can use @command{runtest 1000} or something similar to generate a
2812 large set of samples.
2813 Update the setting to match your measurement:
2814 @example
2815 > parport_toggling_time <measured nanoseconds>
2816 @end example
2817 Now the clock speed will be a better match for @command{adapter_khz rate}
2818 commands given in OpenOCD scripts and event handlers.
2819
2820 You can do something similar with many digital multimeters, but note
2821 that you'll probably need to run the clock continuously for several
2822 seconds before it decides what clock rate to show. Adjust the
2823 toggling time up or down until the measured clock rate is a good
2824 match for the adapter_khz rate you specified; be conservative.
2825 @end quotation
2826 @end deffn
2827
2828 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2829 This will configure the parallel driver to write a known
2830 cable-specific value to the parallel interface on exiting OpenOCD.
2831 @end deffn
2832
2833 For example, the interface configuration file for a
2834 classic ``Wiggler'' cable on LPT2 might look something like this:
2835
2836 @example
2837 interface parport
2838 parport_port 0x278
2839 parport_cable wiggler
2840 @end example
2841 @end deffn
2842
2843 @deffn {Interface Driver} {presto}
2844 ASIX PRESTO USB JTAG programmer.
2845 @deffn {Config Command} {presto_serial} serial_string
2846 Configures the USB serial number of the Presto device to use.
2847 @end deffn
2848 @end deffn
2849
2850 @deffn {Interface Driver} {rlink}
2851 Raisonance RLink USB adapter
2852 @end deffn
2853
2854 @deffn {Interface Driver} {usbprog}
2855 usbprog is a freely programmable USB adapter.
2856 @end deffn
2857
2858 @deffn {Interface Driver} {vsllink}
2859 vsllink is part of Versaloon which is a versatile USB programmer.
2860
2861 @quotation Note
2862 This defines quite a few driver-specific commands,
2863 which are not currently documented here.
2864 @end quotation
2865 @end deffn
2866
2867 @anchor{hla_interface}
2868 @deffn {Interface Driver} {hla}
2869 This is a driver that supports multiple High Level Adapters.
2870 This type of adapter does not expose some of the lower level api's
2871 that OpenOCD would normally use to access the target.
2872
2873 Currently supported adapters include the ST STLINK and TI ICDI.
2874 STLINK firmware version >= V2.J21.S4 recommended due to issues with earlier
2875 versions of firmware where serial number is reset after first use. Suggest
2876 using ST firmware update utility to upgrade STLINK firmware even if current
2877 version reported is V2.J21.S4.
2878
2879 @deffn {Config Command} {hla_device_desc} description
2880 Currently Not Supported.
2881 @end deffn
2882
2883 @deffn {Config Command} {hla_serial} serial
2884 Specifies the serial number of the adapter.
2885 @end deffn
2886
2887 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
2888 Specifies the adapter layout to use.
2889 @end deffn
2890
2891 @deffn {Config Command} {hla_vid_pid} vid pid
2892 The vendor ID and product ID of the device.
2893 @end deffn
2894
2895 @deffn {Command} {hla_command} command
2896 Execute a custom adapter-specific command. The @var{command} string is
2897 passed as is to the underlying adapter layout handler.
2898 @end deffn
2899 @end deffn
2900
2901 @deffn {Interface Driver} {opendous}
2902 opendous-jtag is a freely programmable USB adapter.
2903 @end deffn
2904
2905 @deffn {Interface Driver} {ulink}
2906 This is the Keil ULINK v1 JTAG debugger.
2907 @end deffn
2908
2909 @deffn {Interface Driver} {ZY1000}
2910 This is the Zylin ZY1000 JTAG debugger.
2911 @end deffn
2912
2913 @quotation Note
2914 This defines some driver-specific commands,
2915 which are not currently documented here.
2916 @end quotation
2917
2918 @deffn Command power [@option{on}|@option{off}]
2919 Turn power switch to target on/off.
2920 No arguments: print status.
2921 @end deffn
2922
2923 @deffn {Interface Driver} {bcm2835gpio}
2924 This SoC is present in Raspberry Pi which is a cheap single-board computer
2925 exposing some GPIOs on its expansion header.
2926
2927 The driver accesses memory-mapped GPIO peripheral registers directly
2928 for maximum performance, but the only possible race condition is for
2929 the pins' modes/muxing (which is highly unlikely), so it should be
2930 able to coexist nicely with both sysfs bitbanging and various
2931 peripherals' kernel drivers. The driver restores the previous
2932 configuration on exit.
2933
2934 See @file{interface/raspberrypi-native.cfg} for a sample config and
2935 pinout.
2936
2937 @end deffn
2938
2939 @deffn {Interface Driver} {openjtag}
2940 OpenJTAG compatible USB adapter.
2941 This defines some driver-specific commands:
2942
2943 @deffn {Config Command} {openjtag_variant} variant
2944 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
2945 Currently valid @var{variant} values include:
2946
2947 @itemize @minus
2948 @item @b{standard} Standard variant (default).
2949 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
2950 (see @uref{http://www.cypress.com/?rID=82870}).
2951 @end itemize
2952 @end deffn
2953
2954 @deffn {Config Command} {openjtag_device_desc} string
2955 The USB device description string of the adapter.
2956 This value is only used with the standard variant.
2957 @end deffn
2958 @end deffn
2959
2960 @section Transport Configuration
2961 @cindex Transport
2962 As noted earlier, depending on the version of OpenOCD you use,
2963 and the debug adapter you are using,
2964 several transports may be available to
2965 communicate with debug targets (or perhaps to program flash memory).
2966 @deffn Command {transport list}
2967 displays the names of the transports supported by this
2968 version of OpenOCD.
2969 @end deffn
2970
2971 @deffn Command {transport select} @option{transport_name}
2972 Select which of the supported transports to use in this OpenOCD session.
2973
2974 When invoked with @option{transport_name}, attempts to select the named
2975 transport. The transport must be supported by the debug adapter
2976 hardware and by the version of OpenOCD you are using (including the
2977 adapter's driver).
2978
2979 If no transport has been selected and no @option{transport_name} is
2980 provided, @command{transport select} auto-selects the first transport
2981 supported by the debug adapter.
2982
2983 @command{transport select} always returns the name of the session's selected
2984 transport, if any.
2985 @end deffn
2986
2987 @subsection JTAG Transport
2988 @cindex JTAG
2989 JTAG is the original transport supported by OpenOCD, and most
2990 of the OpenOCD commands support it.
2991 JTAG transports expose a chain of one or more Test Access Points (TAPs),
2992 each of which must be explicitly declared.
2993 JTAG supports both debugging and boundary scan testing.
2994 Flash programming support is built on top of debug support.
2995
2996 JTAG transport is selected with the command @command{transport select
2997 jtag}. Unless your adapter uses @ref{hla_interface,the hla interface
2998 driver}, in which case the command is @command{transport select
2999 hla_jtag}.
3000
3001 @subsection SWD Transport
3002 @cindex SWD
3003 @cindex Serial Wire Debug
3004 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3005 Debug Access Point (DAP, which must be explicitly declared.
3006 (SWD uses fewer signal wires than JTAG.)
3007 SWD is debug-oriented, and does not support boundary scan testing.
3008 Flash programming support is built on top of debug support.
3009 (Some processors support both JTAG and SWD.)
3010
3011 SWD transport is selected with the command @command{transport select
3012 swd}. Unless your adapter uses @ref{hla_interface,the hla interface
3013 driver}, in which case the command is @command{transport select
3014 hla_swd}.
3015
3016 @deffn Command {swd newdap} ...
3017 Declares a single DAP which uses SWD transport.
3018 Parameters are currently the same as "jtag newtap" but this is
3019 expected to change.
3020 @end deffn
3021 @deffn Command {swd wcr trn prescale}
3022 Updates TRN (turnaraound delay) and prescaling.fields of the
3023 Wire Control Register (WCR).
3024 No parameters: displays current settings.
3025 @end deffn
3026
3027 @subsection SPI Transport
3028 @cindex SPI
3029 @cindex Serial Peripheral Interface
3030 The Serial Peripheral Interface (SPI) is a general purpose transport
3031 which uses four wire signaling. Some processors use it as part of a
3032 solution for flash programming.
3033
3034 @anchor{jtagspeed}
3035 @section JTAG Speed
3036 JTAG clock setup is part of system setup.
3037 It @emph{does not belong with interface setup} since any interface
3038 only knows a few of the constraints for the JTAG clock speed.
3039 Sometimes the JTAG speed is
3040 changed during the target initialization process: (1) slow at
3041 reset, (2) program the CPU clocks, (3) run fast.
3042 Both the "slow" and "fast" clock rates are functions of the
3043 oscillators used, the chip, the board design, and sometimes
3044 power management software that may be active.
3045
3046 The speed used during reset, and the scan chain verification which
3047 follows reset, can be adjusted using a @code{reset-start}
3048 target event handler.
3049 It can then be reconfigured to a faster speed by a
3050 @code{reset-init} target event handler after it reprograms those
3051 CPU clocks, or manually (if something else, such as a boot loader,
3052 sets up those clocks).
3053 @xref{targetevents,,Target Events}.
3054 When the initial low JTAG speed is a chip characteristic, perhaps
3055 because of a required oscillator speed, provide such a handler
3056 in the target config file.
3057 When that speed is a function of a board-specific characteristic
3058 such as which speed oscillator is used, it belongs in the board
3059 config file instead.
3060 In both cases it's safest to also set the initial JTAG clock rate
3061 to that same slow speed, so that OpenOCD never starts up using a
3062 clock speed that's faster than the scan chain can support.
3063
3064 @example
3065 jtag_rclk 3000
3066 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3067 @end example
3068
3069 If your system supports adaptive clocking (RTCK), configuring
3070 JTAG to use that is probably the most robust approach.
3071 However, it introduces delays to synchronize clocks; so it
3072 may not be the fastest solution.
3073
3074 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3075 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3076 which support adaptive clocking.
3077
3078 @deffn {Command} adapter_khz max_speed_kHz
3079 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3080 JTAG interfaces usually support a limited number of
3081 speeds. The speed actually used won't be faster
3082 than the speed specified.
3083
3084 Chip data sheets generally include a top JTAG clock rate.
3085 The actual rate is often a function of a CPU core clock,
3086 and is normally less than that peak rate.
3087 For example, most ARM cores accept at most one sixth of the CPU clock.
3088
3089 Speed 0 (khz) selects RTCK method.
3090 @xref{faqrtck,,FAQ RTCK}.
3091 If your system uses RTCK, you won't need to change the
3092 JTAG clocking after setup.
3093 Not all interfaces, boards, or targets support ``rtck''.
3094 If the interface device can not
3095 support it, an error is returned when you try to use RTCK.
3096 @end deffn
3097
3098 @defun jtag_rclk fallback_speed_kHz
3099 @cindex adaptive clocking
3100 @cindex RTCK
3101 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3102 If that fails (maybe the interface, board, or target doesn't
3103 support it), falls back to the specified frequency.
3104 @example
3105 # Fall back to 3mhz if RTCK is not supported
3106 jtag_rclk 3000
3107 @end example
3108 @end defun
3109
3110 @node Reset Configuration
3111 @chapter Reset Configuration
3112 @cindex Reset Configuration
3113
3114 Every system configuration may require a different reset
3115 configuration. This can also be quite confusing.
3116 Resets also interact with @var{reset-init} event handlers,
3117 which do things like setting up clocks and DRAM, and
3118 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3119 They can also interact with JTAG routers.
3120 Please see the various board files for examples.
3121
3122 @quotation Note
3123 To maintainers and integrators:
3124 Reset configuration touches several things at once.
3125 Normally the board configuration file
3126 should define it and assume that the JTAG adapter supports
3127 everything that's wired up to the board's JTAG connector.
3128
3129 However, the target configuration file could also make note
3130 of something the silicon vendor has done inside the chip,
3131 which will be true for most (or all) boards using that chip.
3132 And when the JTAG adapter doesn't support everything, the
3133 user configuration file will need to override parts of
3134 the reset configuration provided by other files.
3135 @end quotation
3136
3137 @section Types of Reset
3138
3139 There are many kinds of reset possible through JTAG, but
3140 they may not all work with a given board and adapter.
3141 That's part of why reset configuration can be error prone.
3142
3143 @itemize @bullet
3144 @item
3145 @emph{System Reset} ... the @emph{SRST} hardware signal
3146 resets all chips connected to the JTAG adapter, such as processors,
3147 power management chips, and I/O controllers. Normally resets triggered
3148 with this signal behave exactly like pressing a RESET button.
3149 @item
3150 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3151 just the TAP controllers connected to the JTAG adapter.
3152 Such resets should not be visible to the rest of the system; resetting a
3153 device's TAP controller just puts that controller into a known state.
3154 @item
3155 @emph{Emulation Reset} ... many devices can be reset through JTAG
3156 commands. These resets are often distinguishable from system
3157 resets, either explicitly (a "reset reason" register says so)
3158 or implicitly (not all parts of the chip get reset).
3159 @item
3160 @emph{Other Resets} ... system-on-chip devices often support
3161 several other types of reset.
3162 You may need to arrange that a watchdog timer stops
3163 while debugging, preventing a watchdog reset.
3164 There may be individual module resets.
3165 @end itemize
3166
3167 In the best case, OpenOCD can hold SRST, then reset
3168 the TAPs via TRST and send commands through JTAG to halt the
3169 CPU at the reset vector before the 1st instruction is executed.
3170 Then when it finally releases the SRST signal, the system is
3171 halted under debugger control before any code has executed.
3172 This is the behavior required to support the @command{reset halt}
3173 and @command{reset init} commands; after @command{reset init} a
3174 board-specific script might do things like setting up DRAM.
3175 (@xref{resetcommand,,Reset Command}.)
3176
3177 @anchor{srstandtrstissues}
3178 @section SRST and TRST Issues
3179
3180 Because SRST and TRST are hardware signals, they can have a
3181 variety of system-specific constraints. Some of the most
3182 common issues are:
3183
3184 @itemize @bullet
3185
3186 @item @emph{Signal not available} ... Some boards don't wire
3187 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3188 support such signals even if they are wired up.
3189 Use the @command{reset_config} @var{signals} options to say
3190 when either of those signals is not connected.
3191 When SRST is not available, your code might not be able to rely
3192 on controllers having been fully reset during code startup.
3193 Missing TRST is not a problem, since JTAG-level resets can
3194 be triggered using with TMS signaling.
3195
3196 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3197 adapter will connect SRST to TRST, instead of keeping them separate.
3198 Use the @command{reset_config} @var{combination} options to say
3199 when those signals aren't properly independent.
3200
3201 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3202 delay circuit, reset supervisor, or on-chip features can extend
3203 the effect of a JTAG adapter's reset for some time after the adapter
3204 stops issuing the reset. For example, there may be chip or board
3205 requirements that all reset pulses last for at least a
3206 certain amount of time; and reset buttons commonly have
3207 hardware debouncing.
3208 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3209 commands to say when extra delays are needed.
3210
3211 @item @emph{Drive type} ... Reset lines often have a pullup
3212 resistor, letting the JTAG interface treat them as open-drain
3213 signals. But that's not a requirement, so the adapter may need
3214 to use push/pull output drivers.
3215 Also, with weak pullups it may be advisable to drive
3216 signals to both levels (push/pull) to minimize rise times.
3217 Use the @command{reset_config} @var{trst_type} and
3218 @var{srst_type} parameters to say how to drive reset signals.
3219
3220 @item @emph{Special initialization} ... Targets sometimes need
3221 special JTAG initialization sequences to handle chip-specific
3222 issues (not limited to errata).
3223 For example, certain JTAG commands might need to be issued while
3224 the system as a whole is in a reset state (SRST active)
3225 but the JTAG scan chain is usable (TRST inactive).
3226 Many systems treat combined assertion of SRST and TRST as a
3227 trigger for a harder reset than SRST alone.
3228 Such custom reset handling is discussed later in this chapter.
3229 @end itemize
3230
3231 There can also be other issues.
3232 Some devices don't fully conform to the JTAG specifications.
3233 Trivial system-specific differences are common, such as
3234 SRST and TRST using slightly different names.
3235 There are also vendors who distribute key JTAG documentation for
3236 their chips only to developers who have signed a Non-Disclosure
3237 Agreement (NDA).
3238
3239 Sometimes there are chip-specific extensions like a requirement to use
3240 the normally-optional TRST signal (precluding use of JTAG adapters which
3241 don't pass TRST through), or needing extra steps to complete a TAP reset.
3242
3243 In short, SRST and especially TRST handling may be very finicky,
3244 needing to cope with both architecture and board specific constraints.
3245
3246 @section Commands for Handling Resets
3247
3248 @deffn {Command} adapter_nsrst_assert_width milliseconds
3249 Minimum amount of time (in milliseconds) OpenOCD should wait
3250 after asserting nSRST (active-low system reset) before
3251 allowing it to be deasserted.
3252 @end deffn
3253
3254 @deffn {Command} adapter_nsrst_delay milliseconds
3255 How long (in milliseconds) OpenOCD should wait after deasserting
3256 nSRST (active-low system reset) before starting new JTAG operations.
3257 When a board has a reset button connected to SRST line it will
3258 probably have hardware debouncing, implying you should use this.
3259 @end deffn
3260
3261 @deffn {Command} jtag_ntrst_assert_width milliseconds
3262 Minimum amount of time (in milliseconds) OpenOCD should wait
3263 after asserting nTRST (active-low JTAG TAP reset) before
3264 allowing it to be deasserted.
3265 @end deffn
3266
3267 @deffn {Command} jtag_ntrst_delay milliseconds
3268 How long (in milliseconds) OpenOCD should wait after deasserting
3269 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3270 @end deffn
3271
3272 @deffn {Command} reset_config mode_flag ...
3273 This command displays or modifies the reset configuration
3274 of your combination of JTAG board and target in target
3275 configuration scripts.
3276
3277 Information earlier in this section describes the kind of problems
3278 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3279 As a rule this command belongs only in board config files,
3280 describing issues like @emph{board doesn't connect TRST};
3281 or in user config files, addressing limitations derived
3282 from a particular combination of interface and board.
3283 (An unlikely example would be using a TRST-only adapter
3284 with a board that only wires up SRST.)
3285
3286 The @var{mode_flag} options can be specified in any order, but only one
3287 of each type -- @var{signals}, @var{combination}, @var{gates},
3288 @var{trst_type}, @var{srst_type} and @var{connect_type}
3289 -- may be specified at a time.
3290 If you don't provide a new value for a given type, its previous
3291 value (perhaps the default) is unchanged.
3292 For example, this means that you don't need to say anything at all about
3293 TRST just to declare that if the JTAG adapter should want to drive SRST,
3294 it must explicitly be driven high (@option{srst_push_pull}).
3295
3296 @itemize
3297 @item
3298 @var{signals} can specify which of the reset signals are connected.
3299 For example, If the JTAG interface provides SRST, but the board doesn't
3300 connect that signal properly, then OpenOCD can't use it.
3301 Possible values are @option{none} (the default), @option{trst_only},
3302 @option{srst_only} and @option{trst_and_srst}.
3303
3304 @quotation Tip
3305 If your board provides SRST and/or TRST through the JTAG connector,
3306 you must declare that so those signals can be used.
3307 @end quotation
3308
3309 @item
3310 The @var{combination} is an optional value specifying broken reset
3311 signal implementations.
3312 The default behaviour if no option given is @option{separate},
3313 indicating everything behaves normally.
3314 @option{srst_pulls_trst} states that the
3315 test logic is reset together with the reset of the system (e.g. NXP
3316 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3317 the system is reset together with the test logic (only hypothetical, I
3318 haven't seen hardware with such a bug, and can be worked around).
3319 @option{combined} implies both @option{srst_pulls_trst} and
3320 @option{trst_pulls_srst}.
3321
3322 @item
3323 The @var{gates} tokens control flags that describe some cases where
3324 JTAG may be unvailable during reset.
3325 @option{srst_gates_jtag} (default)
3326 indicates that asserting SRST gates the
3327 JTAG clock. This means that no communication can happen on JTAG
3328 while SRST is asserted.
3329 Its converse is @option{srst_nogate}, indicating that JTAG commands
3330 can safely be issued while SRST is active.
3331
3332 @item
3333 The @var{connect_type} tokens control flags that describe some cases where
3334 SRST is asserted while connecting to the target. @option{srst_nogate}
3335 is required to use this option.
3336 @option{connect_deassert_srst} (default)
3337 indicates that SRST will not be asserted while connecting to the target.
3338 Its converse is @option{connect_assert_srst}, indicating that SRST will
3339 be asserted before any target connection.
3340 Only some targets support this feature, STM32 and STR9 are examples.
3341 This feature is useful if you are unable to connect to your target due
3342 to incorrect options byte config or illegal program execution.
3343 @end itemize
3344
3345 The optional @var{trst_type} and @var{srst_type} parameters allow the
3346 driver mode of each reset line to be specified. These values only affect
3347 JTAG interfaces with support for different driver modes, like the Amontec
3348 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3349 relevant signal (TRST or SRST) is not connected.
3350
3351 @itemize
3352 @item
3353 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3354 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3355 Most boards connect this signal to a pulldown, so the JTAG TAPs
3356 never leave reset unless they are hooked up to a JTAG adapter.
3357
3358 @item
3359 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3360 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3361 Most boards connect this signal to a pullup, and allow the
3362 signal to be pulled low by various events including system
3363 powerup and pressing a reset button.
3364 @end itemize
3365 @end deffn
3366
3367 @section Custom Reset Handling
3368 @cindex events
3369
3370 OpenOCD has several ways to help support the various reset
3371 mechanisms provided by chip and board vendors.
3372 The commands shown in the previous section give standard parameters.
3373 There are also @emph{event handlers} associated with TAPs or Targets.
3374 Those handlers are Tcl procedures you can provide, which are invoked
3375 at particular points in the reset sequence.
3376
3377 @emph{When SRST is not an option} you must set
3378 up a @code{reset-assert} event handler for your target.
3379 For example, some JTAG adapters don't include the SRST signal;
3380 and some boards have multiple targets, and you won't always
3381 want to reset everything at once.
3382
3383 After configuring those mechanisms, you might still
3384 find your board doesn't start up or reset correctly.
3385 For example, maybe it needs a slightly different sequence
3386 of SRST and/or TRST manipulations, because of quirks that
3387 the @command{reset_config} mechanism doesn't address;
3388 or asserting both might trigger a stronger reset, which
3389 needs special attention.
3390
3391 Experiment with lower level operations, such as @command{jtag_reset}
3392 and the @command{jtag arp_*} operations shown here,
3393 to find a sequence of operations that works.
3394 @xref{JTAG Commands}.
3395 When you find a working sequence, it can be used to override
3396 @command{jtag_init}, which fires during OpenOCD startup
3397 (@pxref{configurationstage,,Configuration Stage});
3398 or @command{init_reset}, which fires during reset processing.
3399
3400 You might also want to provide some project-specific reset
3401 schemes. For example, on a multi-target board the standard
3402 @command{reset} command would reset all targets, but you
3403 may need the ability to reset only one target at time and
3404 thus want to avoid using the board-wide SRST signal.
3405
3406 @deffn {Overridable Procedure} init_reset mode
3407 This is invoked near the beginning of the @command{reset} command,
3408 usually to provide as much of a cold (power-up) reset as practical.
3409 By default it is also invoked from @command{jtag_init} if
3410 the scan chain does not respond to pure JTAG operations.
3411 The @var{mode} parameter is the parameter given to the
3412 low level reset command (@option{halt},
3413 @option{init}, or @option{run}), @option{setup},
3414 or potentially some other value.
3415
3416 The default implementation just invokes @command{jtag arp_init-reset}.
3417 Replacements will normally build on low level JTAG
3418 operations such as @command{jtag_reset}.
3419 Operations here must not address individual TAPs
3420 (or their associated targets)
3421 until the JTAG scan chain has first been verified to work.
3422
3423 Implementations must have verified the JTAG scan chain before
3424 they return.
3425 This is done by calling @command{jtag arp_init}
3426 (or @command{jtag arp_init-reset}).
3427 @end deffn
3428
3429 @deffn Command {jtag arp_init}
3430 This validates the scan chain using just the four
3431 standard JTAG signals (TMS, TCK, TDI, TDO).
3432 It starts by issuing a JTAG-only reset.
3433 Then it performs checks to verify that the scan chain configuration
3434 matches the TAPs it can observe.
3435 Those checks include checking IDCODE values for each active TAP,
3436 and verifying the length of their instruction registers using
3437 TAP @code{-ircapture} and @code{-irmask} values.
3438 If these tests all pass, TAP @code{setup} events are
3439 issued to all TAPs with handlers for that event.
3440 @end deffn
3441
3442 @deffn Command {jtag arp_init-reset}
3443 This uses TRST and SRST to try resetting
3444 everything on the JTAG scan chain
3445 (and anything else connected to SRST).
3446 It then invokes the logic of @command{jtag arp_init}.
3447 @end deffn
3448
3449
3450 @node TAP Declaration
3451 @chapter TAP Declaration
3452 @cindex TAP declaration
3453 @cindex TAP configuration
3454
3455 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3456 TAPs serve many roles, including:
3457
3458 @itemize @bullet
3459 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3460 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3461 Others do it indirectly, making a CPU do it.
3462 @item @b{Program Download} Using the same CPU support GDB uses,
3463 you can initialize a DRAM controller, download code to DRAM, and then
3464 start running that code.
3465 @item @b{Boundary Scan} Most chips support boundary scan, which
3466 helps test for board assembly problems like solder bridges
3467 and missing connections.
3468 @end itemize
3469
3470 OpenOCD must know about the active TAPs on your board(s).
3471 Setting up the TAPs is the core task of your configuration files.
3472 Once those TAPs are set up, you can pass their names to code
3473 which sets up CPUs and exports them as GDB targets,
3474 probes flash memory, performs low-level JTAG operations, and more.
3475
3476 @section Scan Chains
3477 @cindex scan chain
3478
3479 TAPs are part of a hardware @dfn{scan chain},
3480 which is a daisy chain of TAPs.
3481 They also need to be added to
3482 OpenOCD's software mirror of that hardware list,
3483 giving each member a name and associating other data with it.
3484 Simple scan chains, with a single TAP, are common in
3485 systems with a single microcontroller or microprocessor.
3486 More complex chips may have several TAPs internally.
3487 Very complex scan chains might have a dozen or more TAPs:
3488 several in one chip, more in the next, and connecting
3489 to other boards with their own chips and TAPs.
3490
3491 You can display the list with the @command{scan_chain} command.
3492 (Don't confuse this with the list displayed by the @command{targets}
3493 command, presented in the next chapter.
3494 That only displays TAPs for CPUs which are configured as
3495 debugging targets.)
3496 Here's what the scan chain might look like for a chip more than one TAP:
3497
3498 @verbatim
3499 TapName Enabled IdCode Expected IrLen IrCap IrMask
3500 -- ------------------ ------- ---------- ---------- ----- ----- ------
3501 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3502 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3503 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3504 @end verbatim
3505
3506 OpenOCD can detect some of that information, but not all
3507 of it. @xref{autoprobing,,Autoprobing}.
3508 Unfortunately, those TAPs can't always be autoconfigured,
3509 because not all devices provide good support for that.
3510 JTAG doesn't require supporting IDCODE instructions, and
3511 chips with JTAG routers may not link TAPs into the chain
3512 until they are told to do so.
3513
3514 The configuration mechanism currently supported by OpenOCD
3515 requires explicit configuration of all TAP devices using
3516 @command{jtag newtap} commands, as detailed later in this chapter.
3517 A command like this would declare one tap and name it @code{chip1.cpu}:
3518
3519 @example
3520 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3521 @end example
3522
3523 Each target configuration file lists the TAPs provided
3524 by a given chip.
3525 Board configuration files combine all the targets on a board,
3526 and so forth.
3527 Note that @emph{the order in which TAPs are declared is very important.}
3528 That declaration order must match the order in the JTAG scan chain,
3529 both inside a single chip and between them.
3530 @xref{faqtaporder,,FAQ TAP Order}.
3531
3532 For example, the ST Microsystems STR912 chip has
3533 three separate TAPs@footnote{See the ST
3534 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3535 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3536 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3537 To configure those taps, @file{target/str912.cfg}
3538 includes commands something like this:
3539
3540 @example
3541 jtag newtap str912 flash ... params ...
3542 jtag newtap str912 cpu ... params ...
3543 jtag newtap str912 bs ... params ...
3544 @end example
3545
3546 Actual config files typically use a variable such as @code{$_CHIPNAME}
3547 instead of literals like @option{str912}, to support more than one chip
3548 of each type. @xref{Config File Guidelines}.
3549
3550 @deffn Command {jtag names}
3551 Returns the names of all current TAPs in the scan chain.
3552 Use @command{jtag cget} or @command{jtag tapisenabled}
3553 to examine attributes and state of each TAP.
3554 @example
3555 foreach t [jtag names] @{
3556 puts [format "TAP: %s\n" $t]
3557 @}
3558 @end example
3559 @end deffn
3560
3561 @deffn Command {scan_chain}
3562 Displays the TAPs in the scan chain configuration,
3563 and their status.
3564 The set of TAPs listed by this command is fixed by
3565 exiting the OpenOCD configuration stage,
3566 but systems with a JTAG router can
3567 enable or disable TAPs dynamically.
3568 @end deffn
3569
3570 @c FIXME! "jtag cget" should be able to return all TAP
3571 @c attributes, like "$target_name cget" does for targets.
3572
3573 @c Probably want "jtag eventlist", and a "tap-reset" event
3574 @c (on entry to RESET state).
3575
3576 @section TAP Names
3577 @cindex dotted name
3578
3579 When TAP objects are declared with @command{jtag newtap},
3580 a @dfn{dotted.name} is created for the TAP, combining the
3581 name of a module (usually a chip) and a label for the TAP.
3582 For example: @code{xilinx.tap}, @code{str912.flash},
3583 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3584 Many other commands use that dotted.name to manipulate or
3585 refer to the TAP. For example, CPU configuration uses the
3586 name, as does declaration of NAND or NOR flash banks.
3587
3588 The components of a dotted name should follow ``C'' symbol
3589 name rules: start with an alphabetic character, then numbers
3590 and underscores are OK; while others (including dots!) are not.
3591
3592 @section TAP Declaration Commands
3593
3594 @c shouldn't this be(come) a {Config Command}?
3595 @deffn Command {jtag newtap} chipname tapname configparams...
3596 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3597 and configured according to the various @var{configparams}.
3598
3599 The @var{chipname} is a symbolic name for the chip.
3600 Conventionally target config files use @code{$_CHIPNAME},
3601 defaulting to the model name given by the chip vendor but
3602 overridable.
3603
3604 @cindex TAP naming convention
3605 The @var{tapname} reflects the role of that TAP,
3606 and should follow this convention:
3607
3608 @itemize @bullet
3609 @item @code{bs} -- For boundary scan if this is a separate TAP;
3610 @item @code{cpu} -- The main CPU of the chip, alternatively
3611 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3612 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3613 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3614 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3615 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3616 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3617 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3618 with a single TAP;
3619 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3620 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3621 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3622 a JTAG TAP; that TAP should be named @code{sdma}.
3623 @end itemize
3624
3625 Every TAP requires at least the following @var{configparams}:
3626
3627 @itemize @bullet
3628 @item @code{-irlen} @var{NUMBER}
3629 @*The length in bits of the
3630 instruction register, such as 4 or 5 bits.
3631 @end itemize
3632
3633 A TAP may also provide optional @var{configparams}:
3634
3635 @itemize @bullet
3636 @item @code{-disable} (or @code{-enable})
3637 @*Use the @code{-disable} parameter to flag a TAP which is not
3638 linked into the scan chain after a reset using either TRST
3639 or the JTAG state machine's @sc{reset} state.
3640 You may use @code{-enable} to highlight the default state
3641 (the TAP is linked in).
3642 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3643 @item @code{-expected-id} @var{NUMBER}
3644 @*A non-zero @var{number} represents a 32-bit IDCODE
3645 which you expect to find when the scan chain is examined.
3646 These codes are not required by all JTAG devices.
3647 @emph{Repeat the option} as many times as required if more than one
3648 ID code could appear (for example, multiple versions).
3649 Specify @var{number} as zero to suppress warnings about IDCODE
3650 values that were found but not included in the list.
3651
3652 Provide this value if at all possible, since it lets OpenOCD
3653 tell when the scan chain it sees isn't right. These values
3654 are provided in vendors' chip documentation, usually a technical
3655 reference manual. Sometimes you may need to probe the JTAG
3656 hardware to find these values.
3657 @xref{autoprobing,,Autoprobing}.
3658 @item @code{-ignore-version}
3659 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3660 option. When vendors put out multiple versions of a chip, or use the same
3661 JTAG-level ID for several largely-compatible chips, it may be more practical
3662 to ignore the version field than to update config files to handle all of
3663 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3664 @item @code{-ircapture} @var{NUMBER}
3665 @*The bit pattern loaded by the TAP into the JTAG shift register
3666 on entry to the @sc{ircapture} state, such as 0x01.
3667 JTAG requires the two LSBs of this value to be 01.
3668 By default, @code{-ircapture} and @code{-irmask} are set
3669 up to verify that two-bit value. You may provide
3670 additional bits if you know them, or indicate that
3671 a TAP doesn't conform to the JTAG specification.
3672 @item @code{-irmask} @var{NUMBER}
3673 @*A mask used with @code{-ircapture}
3674 to verify that instruction scans work correctly.
3675 Such scans are not used by OpenOCD except to verify that
3676 there seems to be no problems with JTAG scan chain operations.
3677 @end itemize
3678 @end deffn
3679
3680 @section Other TAP commands
3681
3682 @deffn Command {jtag cget} dotted.name @option{-event} event_name
3683 @deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
3684 At this writing this TAP attribute
3685 mechanism is used only for event handling.
3686 (It is not a direct analogue of the @code{cget}/@code{configure}
3687 mechanism for debugger targets.)
3688 See the next section for information about the available events.
3689
3690 The @code{configure} subcommand assigns an event handler,
3691 a TCL string which is evaluated when the event is triggered.
3692 The @code{cget} subcommand returns that handler.
3693 @end deffn
3694
3695 @section TAP Events
3696 @cindex events
3697 @cindex TAP events
3698
3699 OpenOCD includes two event mechanisms.
3700 The one presented here applies to all JTAG TAPs.
3701 The other applies to debugger targets,
3702 which are associated with certain TAPs.
3703
3704 The TAP events currently defined are:
3705
3706 @itemize @bullet
3707 @item @b{post-reset}
3708 @* The TAP has just completed a JTAG reset.
3709 The tap may still be in the JTAG @sc{reset} state.
3710 Handlers for these events might perform initialization sequences
3711 such as issuing TCK cycles, TMS sequences to ensure
3712 exit from the ARM SWD mode, and more.
3713
3714 Because the scan chain has not yet been verified, handlers for these events
3715 @emph{should not issue commands which scan the JTAG IR or DR registers}
3716 of any particular target.
3717 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3718 @item @b{setup}
3719 @* The scan chain has been reset and verified.
3720 This handler may enable TAPs as needed.
3721 @item @b{tap-disable}
3722 @* The TAP needs to be disabled. This handler should
3723 implement @command{jtag tapdisable}
3724 by issuing the relevant JTAG commands.
3725 @item @b{tap-enable}
3726 @* The TAP needs to be enabled. This handler should
3727 implement @command{jtag tapenable}
3728 by issuing the relevant JTAG commands.
3729 @end itemize
3730
3731 If you need some action after each JTAG reset which isn't actually
3732 specific to any TAP (since you can't yet trust the scan chain's
3733 contents to be accurate), you might:
3734
3735 @example
3736 jtag configure CHIP.jrc -event post-reset @{
3737 echo "JTAG Reset done"
3738 ... non-scan jtag operations to be done after reset
3739 @}
3740 @end example
3741
3742
3743 @anchor{enablinganddisablingtaps}
3744 @section Enabling and Disabling TAPs
3745 @cindex JTAG Route Controller
3746 @cindex jrc
3747
3748 In some systems, a @dfn{JTAG Route Controller} (JRC)
3749 is used to enable and/or disable specific JTAG TAPs.
3750 Many ARM-based chips from Texas Instruments include
3751 an ``ICEPick'' module, which is a JRC.
3752 Such chips include DaVinci and OMAP3 processors.
3753
3754 A given TAP may not be visible until the JRC has been
3755 told to link it into the scan chain; and if the JRC
3756 has been told to unlink that TAP, it will no longer
3757 be visible.
3758 Such routers address problems that JTAG ``bypass mode''
3759 ignores, such as:
3760
3761 @itemize
3762 @item The scan chain can only go as fast as its slowest TAP.
3763 @item Having many TAPs slows instruction scans, since all
3764 TAPs receive new instructions.
3765 @item TAPs in the scan chain must be powered up, which wastes
3766 power and prevents debugging some power management mechanisms.
3767 @end itemize
3768
3769 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3770 as implied by the existence of JTAG routers.
3771 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3772 does include a kind of JTAG router functionality.
3773
3774 @c (a) currently the event handlers don't seem to be able to
3775 @c fail in a way that could lead to no-change-of-state.
3776
3777 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3778 shown below, and is implemented using TAP event handlers.
3779 So for example, when defining a TAP for a CPU connected to
3780 a JTAG router, your @file{target.cfg} file
3781 should define TAP event handlers using
3782 code that looks something like this:
3783
3784 @example
3785 jtag configure CHIP.cpu -event tap-enable @{
3786 ... jtag operations using CHIP.jrc
3787 @}
3788 jtag configure CHIP.cpu -event tap-disable @{
3789 ... jtag operations using CHIP.jrc
3790 @}
3791 @end example
3792
3793 Then you might want that CPU's TAP enabled almost all the time:
3794
3795 @example
3796 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3797 @end example
3798
3799 Note how that particular setup event handler declaration
3800 uses quotes to evaluate @code{$CHIP} when the event is configured.
3801 Using brackets @{ @} would cause it to be evaluated later,
3802 at runtime, when it might have a different value.
3803
3804 @deffn Command {jtag tapdisable} dotted.name
3805 If necessary, disables the tap
3806 by sending it a @option{tap-disable} event.
3807 Returns the string "1" if the tap
3808 specified by @var{dotted.name} is enabled,
3809 and "0" if it is disabled.
3810 @end deffn
3811
3812 @deffn Command {jtag tapenable} dotted.name
3813 If necessary, enables the tap
3814 by sending it a @option{tap-enable} event.
3815 Returns the string "1" if the tap
3816 specified by @var{dotted.name} is enabled,
3817 and "0" if it is disabled.
3818 @end deffn
3819
3820 @deffn Command {jtag tapisenabled} dotted.name
3821 Returns the string "1" if the tap
3822 specified by @var{dotted.name} is enabled,
3823 and "0" if it is disabled.
3824
3825 @quotation Note
3826 Humans will find the @command{scan_chain} command more helpful
3827 for querying the state of the JTAG taps.
3828 @end quotation
3829 @end deffn
3830
3831 @anchor{autoprobing}
3832 @section Autoprobing
3833 @cindex autoprobe
3834 @cindex JTAG autoprobe
3835
3836 TAP configuration is the first thing that needs to be done
3837 after interface and reset configuration. Sometimes it's
3838 hard finding out what TAPs exist, or how they are identified.
3839 Vendor documentation is not always easy to find and use.
3840
3841 To help you get past such problems, OpenOCD has a limited
3842 @emph{autoprobing} ability to look at the scan chain, doing
3843 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3844 To use this mechanism, start the OpenOCD server with only data
3845 that configures your JTAG interface, and arranges to come up
3846 with a slow clock (many devices don't support fast JTAG clocks
3847 right when they come out of reset).
3848
3849 For example, your @file{openocd.cfg} file might have:
3850
3851 @example
3852 source [find interface/olimex-arm-usb-tiny-h.cfg]
3853 reset_config trst_and_srst
3854 jtag_rclk 8
3855 @end example
3856
3857 When you start the server without any TAPs configured, it will
3858 attempt to autoconfigure the TAPs. There are two parts to this:
3859
3860 @enumerate
3861 @item @emph{TAP discovery} ...
3862 After a JTAG reset (sometimes a system reset may be needed too),
3863 each TAP's data registers will hold the contents of either the
3864 IDCODE or BYPASS register.
3865 If JTAG communication is working, OpenOCD will see each TAP,
3866 and report what @option{-expected-id} to use with it.
3867 @item @emph{IR Length discovery} ...
3868 Unfortunately JTAG does not provide a reliable way to find out
3869 the value of the @option{-irlen} parameter to use with a TAP
3870 that is discovered.
3871 If OpenOCD can discover the length of a TAP's instruction
3872 register, it will report it.
3873 Otherwise you may need to consult vendor documentation, such
3874 as chip data sheets or BSDL files.
3875 @end enumerate
3876
3877 In many cases your board will have a simple scan chain with just
3878 a single device. Here's what OpenOCD reported with one board
3879 that's a bit more complex:
3880
3881 @example
3882 clock speed 8 kHz
3883 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3884 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3885 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3886 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3887 AUTO auto0.tap - use "... -irlen 4"
3888 AUTO auto1.tap - use "... -irlen 4"
3889 AUTO auto2.tap - use "... -irlen 6"
3890 no gdb ports allocated as no target has been specified
3891 @end example
3892
3893 Given that information, you should be able to either find some existing
3894 config files to use, or create your own. If you create your own, you
3895 would configure from the bottom up: first a @file{target.cfg} file
3896 with these TAPs, any targets associated with them, and any on-chip
3897 resources; then a @file{board.cfg} with off-chip resources, clocking,
3898 and so forth.
3899
3900 @node CPU Configuration
3901 @chapter CPU Configuration
3902 @cindex GDB target
3903
3904 This chapter discusses how to set up GDB debug targets for CPUs.
3905 You can also access these targets without GDB
3906 (@pxref{Architecture and Core Commands},
3907 and @ref{targetstatehandling,,Target State handling}) and
3908 through various kinds of NAND and NOR flash commands.
3909 If you have multiple CPUs you can have multiple such targets.
3910
3911 We'll start by looking at how to examine the targets you have,
3912 then look at how to add one more target and how to configure it.
3913
3914 @section Target List
3915 @cindex target, current
3916 @cindex target, list
3917
3918 All targets that have been set up are part of a list,
3919 where each member has a name.
3920 That name should normally be the same as the TAP name.
3921 You can display the list with the @command{targets}
3922 (plural!) command.
3923 This display often has only one CPU; here's what it might
3924 look like with more than one:
3925 @verbatim
3926 TargetName Type Endian TapName State
3927 -- ------------------ ---------- ------ ------------------ ------------
3928 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
3929 1 MyTarget cortex_m little mychip.foo tap-disabled
3930 @end verbatim
3931
3932 One member of that list is the @dfn{current target}, which
3933 is implicitly referenced by many commands.
3934 It's the one marked with a @code{*} near the target name.
3935 In particular, memory addresses often refer to the address
3936 space seen by that current target.
3937 Commands like @command{mdw} (memory display words)
3938 and @command{flash erase_address} (erase NOR flash blocks)
3939 are examples; and there are many more.
3940
3941 Several commands let you examine the list of targets:
3942
3943 @deffn Command {target current}
3944 Returns the name of the current target.
3945 @end deffn
3946
3947 @deffn Command {target names}
3948 Lists the names of all current targets in the list.
3949 @example
3950 foreach t [target names] @{
3951 puts [format "Target: %s\n" $t]
3952 @}
3953 @end example
3954 @end deffn
3955
3956 @c yep, "target list" would have been better.
3957 @c plus maybe "target setdefault".
3958
3959 @deffn Command targets [name]
3960 @emph{Note: the name of this command is plural. Other target
3961 command names are singular.}
3962
3963 With no parameter, this command displays a table of all known
3964 targets in a user friendly form.
3965
3966 With a parameter, this command sets the current target to
3967 the given target with the given @var{name}; this is
3968 only relevant on boards which have more than one target.
3969 @end deffn
3970
3971 @section Target CPU Types
3972 @cindex target type
3973 @cindex CPU type
3974
3975 Each target has a @dfn{CPU type}, as shown in the output of
3976 the @command{targets} command. You need to specify that type
3977 when calling @command{target create}.
3978 The CPU type indicates more than just the instruction set.
3979 It also indicates how that instruction set is implemented,
3980 what kind of debug support it integrates,
3981 whether it has an MMU (and if so, what kind),
3982 what core-specific commands may be available
3983 (@pxref{Architecture and Core Commands}),
3984 and more.
3985
3986 It's easy to see what target types are supported,
3987 since there's a command to list them.
3988
3989 @anchor{targettypes}
3990 @deffn Command {target types}
3991 Lists all supported target types.
3992 At this writing, the supported CPU types are:
3993
3994 @itemize @bullet
3995 @item @code{arm11} -- this is a generation of ARMv6 cores
3996 @item @code{arm720t} -- this is an ARMv4 core with an MMU
3997 @item @code{arm7tdmi} -- this is an ARMv4 core
3998 @item @code{arm920t} -- this is an ARMv4 core with an MMU
3999 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4000 @item @code{arm966e} -- this is an ARMv5 core
4001 @item @code{arm9tdmi} -- this is an ARMv4 core
4002 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4003 (Support for this is preliminary and incomplete.)
4004 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4005 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4006 compact Thumb2 instruction set.
4007 @item @code{dragonite} -- resembles arm966e
4008 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4009 (Support for this is still incomplete.)
4010 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4011 @item @code{feroceon} -- resembles arm926
4012 @item @code{mips_m4k} -- a MIPS core
4013 @item @code{xscale} -- this is actually an architecture,
4014 not a CPU type. It is based on the ARMv5 architecture.
4015 @item @code{openrisc} -- this is an OpenRISC 1000 core.
4016 The current implementation supports three JTAG TAP cores:
4017 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4018 allowing access to physical memory addresses independently of CPU cores.
4019 @itemize @minus
4020 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag})
4021 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4022 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4023 @end itemize
4024 And two debug interfaces cores:
4025 @itemize @minus
4026 @item @code{Advanced debug interface} (See: @url{http://opencores.org/project,adv_debug_sys})
4027 @item @code{SoC Debug Interface} (See: @url{http://opencores.org/project,dbg_interface})
4028 @end itemize
4029 @end itemize
4030 @end deffn
4031
4032 To avoid being confused by the variety of ARM based cores, remember
4033 this key point: @emph{ARM is a technology licencing company}.
4034 (See: @url{http://www.arm.com}.)
4035 The CPU name used by OpenOCD will reflect the CPU design that was
4036 licenced, not a vendor brand which incorporates that design.
4037 Name prefixes like arm7, arm9, arm11, and cortex
4038 reflect design generations;
4039 while names like ARMv4, ARMv5, ARMv6, and ARMv7
4040 reflect an architecture version implemented by a CPU design.
4041
4042 @anchor{targetconfiguration}
4043 @section Target Configuration
4044
4045 Before creating a ``target'', you must have added its TAP to the scan chain.
4046 When you've added that TAP, you will have a @code{dotted.name}
4047 which is used to set up the CPU support.
4048 The chip-specific configuration file will normally configure its CPU(s)
4049 right after it adds all of the chip's TAPs to the scan chain.
4050
4051 Although you can set up a target in one step, it's often clearer if you
4052 use shorter commands and do it in two steps: create it, then configure
4053 optional parts.
4054 All operations on the target after it's created will use a new
4055 command, created as part of target creation.
4056
4057 The two main things to configure after target creation are
4058 a work area, which usually has target-specific defaults even
4059 if the board setup code overrides them later;
4060 and event handlers (@pxref{targetevents,,Target Events}), which tend
4061 to be much more board-specific.
4062 The key steps you use might look something like this
4063
4064 @example
4065 target create MyTarget cortex_m -chain-position mychip.cpu
4066 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4067 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4068 $MyTarget configure -event reset-init @{ myboard_reinit @}
4069 @end example
4070
4071 You should specify a working area if you can; typically it uses some
4072 on-chip SRAM.
4073 Such a working area can speed up many things, including bulk
4074 writes to target memory;
4075 flash operations like checking to see if memory needs to be erased;
4076 GDB memory checksumming;
4077 and more.
4078
4079 @quotation Warning
4080 On more complex chips, the work area can become
4081 inaccessible when application code
4082 (such as an operating system)
4083 enables or disables the MMU.
4084 For example, the particular MMU context used to acess the virtual
4085 address will probably matter ... and that context might not have
4086 easy access to other addresses needed.
4087 At this writing, OpenOCD doesn't have much MMU intelligence.
4088 @end quotation
4089
4090 It's often very useful to define a @code{reset-init} event handler.
4091 For systems that are normally used with a boot loader,
4092 common tasks include updating clocks and initializing memory
4093 controllers.
4094 That may be needed to let you write the boot loader into flash,
4095 in order to ``de-brick'' your board; or to load programs into
4096 external DDR memory without having run the boot loader.
4097
4098 @deffn Command {target create} target_name type configparams...
4099 This command creates a GDB debug target that refers to a specific JTAG tap.
4100 It enters that target into a list, and creates a new
4101 command (@command{@var{target_name}}) which is used for various
4102 purposes including additional configuration.
4103
4104 @itemize @bullet
4105 @item @var{target_name} ... is the name of the debug target.
4106 By convention this should be the same as the @emph{dotted.name}
4107 of the TAP associated with this target, which must be specified here
4108 using the @code{-chain-position @var{dotted.name}} configparam.
4109
4110 This name is also used to create the target object command,
4111 referred to here as @command{$target_name},
4112 and in other places the target needs to be identified.
4113 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4114 @item @var{configparams} ... all parameters accepted by
4115 @command{$target_name configure} are permitted.
4116 If the target is big-endian, set it here with @code{-endian big}.
4117
4118 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
4119 @end itemize
4120 @end deffn
4121
4122 @deffn Command {$target_name configure} configparams...
4123 The options accepted by this command may also be
4124 specified as parameters to @command{target create}.
4125 Their values can later be queried one at a time by
4126 using the @command{$target_name cget} command.
4127
4128 @emph{Warning:} changing some of these after setup is dangerous.
4129 For example, moving a target from one TAP to another;
4130 and changing its endianness.
4131
4132 @itemize @bullet
4133
4134 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4135 used to access this target.
4136
4137 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4138 whether the CPU uses big or little endian conventions
4139
4140 @item @code{-event} @var{event_name} @var{event_body} --
4141 @xref{targetevents,,Target Events}.
4142 Note that this updates a list of named event handlers.
4143 Calling this twice with two different event names assigns
4144 two different handlers, but calling it twice with the
4145 same event name assigns only one handler.
4146
4147 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4148 whether the work area gets backed up; by default,
4149 @emph{it is not backed up.}
4150 When possible, use a working_area that doesn't need to be backed up,
4151 since performing a backup slows down operations.
4152 For example, the beginning of an SRAM block is likely to
4153 be used by most build systems, but the end is often unused.
4154
4155 @item @code{-work-area-size} @var{size} -- specify work are size,
4156 in bytes. The same size applies regardless of whether its physical
4157 or virtual address is being used.
4158
4159 @item @code{-work-area-phys} @var{address} -- set the work area
4160 base @var{address} to be used when no MMU is active.
4161
4162 @item @code{-work-area-virt} @var{address} -- set the work area
4163 base @var{address} to be used when an MMU is active.
4164 @emph{Do not specify a value for this except on targets with an MMU.}
4165 The value should normally correspond to a static mapping for the
4166 @code{-work-area-phys} address, set up by the current operating system.
4167
4168 @anchor{rtostype}
4169 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4170 @var{rtos_type} can be one of @option{auto}, @option{eCos},
4171 @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
4172 @option{embKernel}, @option{mqx}, @option{uCOS-III}
4173 @xref{gdbrtossupport,,RTOS Support}.
4174
4175 @item @code{-defer-examine} -- skip target examination at initial JTAG chain
4176 scan and after a reset. A manual call to arp_examine is required to
4177 access the target for debugging.
4178
4179 @item @code{-ap-num} @var{ap_number} -- set DAP access port for target,
4180 @var{ap_number} is the numeric index of the DAP AP the target is connected to.
4181 Use this option with systems where multiple, independent cores are connected
4182 to separate access ports of the same DAP.
4183 @end itemize
4184 @end deffn
4185
4186 @section Other $target_name Commands
4187 @cindex object command
4188
4189 The Tcl/Tk language has the concept of object commands,
4190 and OpenOCD adopts that same model for targets.
4191
4192 A good Tk example is a on screen button.
4193 Once a button is created a button
4194 has a name (a path in Tk terms) and that name is useable as a first
4195 class command. For example in Tk, one can create a button and later
4196 configure it like this:
4197
4198 @example
4199 # Create
4200 button .foobar -background red -command @{ foo @}
4201 # Modify
4202 .foobar configure -foreground blue
4203 # Query
4204 set x [.foobar cget -background]
4205 # Report
4206 puts [format "The button is %s" $x]
4207 @end example
4208
4209 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4210 button, and its object commands are invoked the same way.
4211
4212 @example
4213 str912.cpu mww 0x1234 0x42
4214 omap3530.cpu mww 0x5555 123
4215 @end example
4216
4217 The commands supported by OpenOCD target objects are:
4218
4219 @deffn Command {$target_name arp_examine} @option{allow-defer}
4220 @deffnx Command {$target_name arp_halt}
4221 @deffnx Command {$target_name arp_poll}
4222 @deffnx Command {$target_name arp_reset}
4223 @deffnx Command {$target_name arp_waitstate}
4224 Internal OpenOCD scripts (most notably @file{startup.tcl})
4225 use these to deal with specific reset cases.
4226 They are not otherwise documented here.
4227 @end deffn
4228
4229 @deffn Command {$target_name array2mem} arrayname width address count
4230 @deffnx Command {$target_name mem2array} arrayname width address count
4231 These provide an efficient script-oriented interface to memory.
4232 The @code{array2mem} primitive writes bytes, halfwords, or words;
4233 while @code{mem2array} reads them.
4234 In both cases, the TCL side uses an array, and
4235 the target side uses raw memory.
4236
4237 The efficiency comes from enabling the use of
4238 bulk JTAG data transfer operations.
4239 The script orientation comes from working with data
4240 values that are packaged for use by TCL scripts;
4241 @command{mdw} type primitives only print data they retrieve,
4242 and neither store nor return those values.
4243
4244 @itemize
4245 @item @var{arrayname} ... is the name of an array variable
4246 @item @var{width} ... is 8/16/32 - indicating the memory access size
4247 @item @var{address} ... is the target memory address
4248 @item @var{count} ... is the number of elements to process
4249 @end itemize
4250 @end deffn
4251
4252 @deffn Command {$target_name cget} queryparm
4253 Each configuration parameter accepted by
4254 @command{$target_name configure}
4255 can be individually queried, to return its current value.
4256 The @var{queryparm} is a parameter name
4257 accepted by that command, such as @code{-work-area-phys}.
4258 There are a few special cases:
4259
4260 @itemize @bullet
4261 @item @code{-event} @var{event_name} -- returns the handler for the
4262 event named @var{event_name}.
4263 This is a special case because setting a handler requires
4264 two parameters.
4265 @item @code{-type} -- returns the target type.
4266 This is a special case because this is set using
4267 @command{target create} and can't be changed
4268 using @command{$target_name configure}.
4269 @end itemize
4270
4271 For example, if you wanted to summarize information about
4272 all the targets you might use something like this:
4273
4274 @example
4275 foreach name [target names] @{
4276 set y [$name cget -endian]
4277 set z [$name cget -type]
4278 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4279 $x $name $y $z]
4280 @}
4281 @end example
4282 @end deffn
4283
4284 @anchor{targetcurstate}
4285 @deffn Command {$target_name curstate}
4286 Displays the current target state:
4287 @code{debug-running},
4288 @code{halted},
4289 @code{reset},
4290 @code{running}, or @code{unknown}.
4291 (Also, @pxref{eventpolling,,Event Polling}.)
4292 @end deffn
4293
4294 @deffn Command {$target_name eventlist}
4295 Displays a table listing all event handlers
4296 currently associated with this target.
4297 @xref{targetevents,,Target Events}.
4298 @end deffn
4299
4300 @deffn Command {$target_name invoke-event} event_name
4301 Invokes the handler for the event named @var{event_name}.
4302 (This is primarily intended for use by OpenOCD framework
4303 code, for example by the reset code in @file{startup.tcl}.)
4304 @end deffn
4305
4306 @deffn Command {$target_name mdw} addr [count]
4307 @deffnx Command {$target_name mdh} addr [count]
4308 @deffnx Command {$target_name mdb} addr [count]
4309 Display contents of address @var{addr}, as
4310 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4311 or 8-bit bytes (@command{mdb}).
4312 If @var{count} is specified, displays that many units.
4313 (If you want to manipulate the data instead of displaying it,
4314 see the @code{mem2array} primitives.)
4315 @end deffn
4316
4317 @deffn Command {$target_name mww} addr word
4318 @deffnx Command {$target_name mwh} addr halfword
4319 @deffnx Command {$target_name mwb} addr byte
4320 Writes the specified @var{word} (32 bits),
4321 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4322 at the specified address @var{addr}.
4323 @end deffn
4324
4325 @anchor{targetevents}
4326 @section Target Events
4327 @cindex target events
4328 @cindex events
4329 At various times, certain things can happen, or you want them to happen.
4330 For example:
4331 @itemize @bullet
4332 @item What should happen when GDB connects? Should your target reset?
4333 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4334 @item Is using SRST appropriate (and possible) on your system?
4335 Or instead of that, do you need to issue JTAG commands to trigger reset?
4336 SRST usually resets everything on the scan chain, which can be inappropriate.
4337 @item During reset, do you need to write to certain memory locations
4338 to set up system clocks or
4339 to reconfigure the SDRAM?
4340 How about configuring the watchdog timer, or other peripherals,
4341 to stop running while you hold the core stopped for debugging?
4342 @end itemize
4343
4344 All of the above items can be addressed by target event handlers.
4345 These are set up by @command{$target_name configure -event} or
4346 @command{target create ... -event}.
4347
4348 The programmer's model matches the @code{-command} option used in Tcl/Tk
4349 buttons and events. The two examples below act the same, but one creates
4350 and invokes a small procedure while the other inlines it.
4351
4352 @example
4353 proc my_attach_proc @{ @} @{
4354 echo "Reset..."
4355 reset halt
4356 @}
4357 mychip.cpu configure -event gdb-attach my_attach_proc
4358 mychip.cpu configure -event gdb-attach @{
4359 echo "Reset..."
4360 # To make flash probe and gdb load to flash work
4361 # we need a reset init.
4362 reset init
4363 @}
4364 @end example
4365
4366 The following target events are defined:
4367
4368 @itemize @bullet
4369 @item @b{debug-halted}
4370 @* The target has halted for debug reasons (i.e.: breakpoint)
4371 @item @b{debug-resumed}
4372 @* The target has resumed (i.e.: gdb said run)
4373 @item @b{early-halted}
4374 @* Occurs early in the halt process
4375 @item @b{examine-start}
4376 @* Before target examine is called.
4377 @item @b{examine-end}
4378 @* After target examine is called with no errors.
4379 @item @b{gdb-attach}
4380 @* When GDB connects. This is before any communication with the target, so this
4381 can be used to set up the target so it is possible to probe flash. Probing flash
4382 is necessary during gdb connect if gdb load is to write the image to flash. Another
4383 use of the flash memory map is for GDB to automatically hardware/software breakpoints
4384 depending on whether the breakpoint is in RAM or read only memory.
4385 @item @b{gdb-detach}
4386 @* When GDB disconnects
4387 @item @b{gdb-end}
4388 @* When the target has halted and GDB is not doing anything (see early halt)
4389 @item @b{gdb-flash-erase-start}
4390 @* Before the GDB flash process tries to erase the flash (default is
4391 @code{reset init})
4392 @item @b{gdb-flash-erase-end}
4393 @* After the GDB flash process has finished erasing the flash
4394 @item @b{gdb-flash-write-start}
4395 @* Before GDB writes to the flash
4396 @item @b{gdb-flash-write-end}
4397 @* After GDB writes to the flash (default is @code{reset halt})
4398 @item @b{gdb-start}
4399 @* Before the target steps, gdb is trying to start/resume the target
4400 @item @b{halted}
4401 @* The target has halted
4402 @item @b{reset-assert-pre}
4403 @* Issued as part of @command{reset} processing
4404 after @command{reset_init} was triggered
4405 but before either SRST alone is re-asserted on the scan chain,
4406 or @code{reset-assert} is triggered.
4407 @item @b{reset-assert}
4408 @* Issued as part of @command{reset} processing
4409 after @command{reset-assert-pre} was triggered.
4410 When such a handler is present, cores which support this event will use
4411 it instead of asserting SRST.
4412 This support is essential for debugging with JTAG interfaces which
4413 don't include an SRST line (JTAG doesn't require SRST), and for
4414 selective reset on scan chains that have multiple targets.
4415 @item @b{reset-assert-post}
4416 @* Issued as part of @command{reset} processing
4417 after @code{reset-assert} has been triggered.
4418 or the target asserted SRST on the entire scan chain.
4419 @item @b{reset-deassert-pre}
4420 @* Issued as part of @command{reset} processing
4421 after @code{reset-assert-post} has been triggered.
4422 @item @b{reset-deassert-post}
4423 @* Issued as part of @command{reset} processing
4424 after @code{reset-deassert-pre} has been triggered
4425 and (if the target is using it) after SRST has been
4426 released on the scan chain.
4427 @item @b{reset-end}
4428 @* Issued as the final step in @command{reset} processing.
4429 @ignore
4430 @item @b{reset-halt-post}
4431 @* Currently not used
4432 @item @b{reset-halt-pre}
4433 @* Currently not used
4434 @end ignore
4435 @item @b{reset-init}
4436 @* Used by @b{reset init} command for board-specific initialization.
4437 This event fires after @emph{reset-deassert-post}.
4438
4439 This is where you would configure PLLs and clocking, set up DRAM so
4440 you can download programs that don't fit in on-chip SRAM, set up pin
4441 multiplexing, and so on.
4442 (You may be able to switch to a fast JTAG clock rate here, after
4443 the target clocks are fully set up.)
4444 @item @b{reset-start}
4445 @* Issued as part of @command{reset} processing
4446 before @command{reset_init} is called.
4447
4448 This is the most robust place to use @command{jtag_rclk}
4449 or @command{adapter_khz} to switch to a low JTAG clock rate,
4450 when reset disables PLLs needed to use a fast clock.
4451 @ignore
4452 @item @b{reset-wait-pos}
4453 @* Currently not used
4454 @item @b{reset-wait-pre}
4455 @* Currently not used
4456 @end ignore
4457 @item @b{resume-start}
4458 @* Before any target is resumed
4459 @item @b{resume-end}
4460 @* After all targets have resumed
4461 @item @b{resumed}
4462 @* Target has resumed
4463 @item @b{trace-config}
4464 @* After target hardware trace configuration was changed
4465 @end itemize
4466
4467 @node Flash Commands
4468 @chapter Flash Commands
4469
4470 OpenOCD has different commands for NOR and NAND flash;
4471 the ``flash'' command works with NOR flash, while
4472 the ``nand'' command works with NAND flash.
4473 This partially reflects different hardware technologies:
4474 NOR flash usually supports direct CPU instruction and data bus access,
4475 while data from a NAND flash must be copied to memory before it can be
4476 used. (SPI flash must also be copied to memory before use.)
4477 However, the documentation also uses ``flash'' as a generic term;
4478 for example, ``Put flash configuration in board-specific files''.
4479
4480 Flash Steps:
4481 @enumerate
4482 @item Configure via the command @command{flash bank}
4483 @* Do this in a board-specific configuration file,
4484 passing parameters as needed by the driver.
4485 @item Operate on the flash via @command{flash subcommand}
4486 @* Often commands to manipulate the flash are typed by a human, or run
4487 via a script in some automated way. Common tasks include writing a
4488 boot loader, operating system, or other data.
4489 @item GDB Flashing
4490 @* Flashing via GDB requires the flash be configured via ``flash
4491 bank'', and the GDB flash features be enabled.
4492 @xref{gdbconfiguration,,GDB Configuration}.
4493 @end enumerate
4494
4495 Many CPUs have the ablity to ``boot'' from the first flash bank.
4496 This means that misprogramming that bank can ``brick'' a system,
4497 so that it can't boot.
4498 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4499 board by (re)installing working boot firmware.
4500
4501 @anchor{norconfiguration}
4502 @section Flash Configuration Commands
4503 @cindex flash configuration
4504
4505 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4506 Configures a flash bank which provides persistent storage
4507 for addresses from @math{base} to @math{base + size - 1}.
4508 These banks will often be visible to GDB through the target's memory map.
4509 In some cases, configuring a flash bank will activate extra commands;
4510 see the driver-specific documentation.
4511
4512 @itemize @bullet
4513 @item @var{name} ... may be used to reference the flash bank
4514 in other flash commands. A number is also available.
4515 @item @var{driver} ... identifies the controller driver
4516 associated with the flash bank being declared.
4517 This is usually @code{cfi} for external flash, or else
4518 the name of a microcontroller with embedded flash memory.
4519 @xref{flashdriverlist,,Flash Driver List}.
4520 @item @var{base} ... Base address of the flash chip.
4521 @item @var{size} ... Size of the chip, in bytes.
4522 For some drivers, this value is detected from the hardware.
4523 @item @var{chip_width} ... Width of the flash chip, in bytes;
4524 ignored for most microcontroller drivers.
4525 @item @var{bus_width} ... Width of the data bus used to access the
4526 chip, in bytes; ignored for most microcontroller drivers.
4527 @item @var{target} ... Names the target used to issue
4528 commands to the flash controller.
4529 @comment Actually, it's currently a controller-specific parameter...
4530 @item @var{driver_options} ... drivers may support, or require,
4531 additional parameters. See the driver-specific documentation
4532 for more information.
4533 @end itemize
4534 @quotation Note
4535 This command is not available after OpenOCD initialization has completed.
4536 Use it in board specific configuration files, not interactively.
4537 @end quotation
4538 @end deffn
4539
4540 @comment the REAL name for this command is "ocd_flash_banks"
4541 @comment less confusing would be: "flash list" (like "nand list")
4542 @deffn Command {flash banks}
4543 Prints a one-line summary of each device that was
4544 declared using @command{flash bank}, numbered from zero.
4545 Note that this is the @emph{plural} form;
4546 the @emph{singular} form is a very different command.
4547 @end deffn
4548
4549 @deffn Command {flash list}
4550 Retrieves a list of associative arrays for each device that was
4551 declared using @command{flash bank}, numbered from zero.
4552 This returned list can be manipulated easily from within scripts.
4553 @end deffn
4554
4555 @deffn Command {flash probe} num
4556 Identify the flash, or validate the parameters of the configured flash. Operation
4557 depends on the flash type.
4558 The @var{num} parameter is a value shown by @command{flash banks}.
4559 Most flash commands will implicitly @emph{autoprobe} the bank;
4560 flash drivers can distinguish between probing and autoprobing,
4561 but most don't bother.
4562 @end deffn
4563
4564 @section Erasing, Reading, Writing to Flash
4565 @cindex flash erasing
4566 @cindex flash reading
4567 @cindex flash writing
4568 @cindex flash programming
4569 @anchor{flashprogrammingcommands}
4570
4571 One feature distinguishing NOR flash from NAND or serial flash technologies
4572 is that for read access, it acts exactly like any other addressible memory.
4573 This means you can use normal memory read commands like @command{mdw} or
4574 @command{dump_image} with it, with no special @command{flash} subcommands.
4575 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
4576
4577 Write access works differently. Flash memory normally needs to be erased
4578 before it's written. Erasing a sector turns all of its bits to ones, and
4579 writing can turn ones into zeroes. This is why there are special commands
4580 for interactive erasing and writing, and why GDB needs to know which parts
4581 of the address space hold NOR flash memory.
4582
4583 @quotation Note
4584 Most of these erase and write commands leverage the fact that NOR flash
4585 chips consume target address space. They implicitly refer to the current
4586 JTAG target, and map from an address in that target's address space
4587 back to a flash bank.
4588 @comment In May 2009, those mappings may fail if any bank associated
4589 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
4590 A few commands use abstract addressing based on bank and sector numbers,
4591 and don't depend on searching the current target and its address space.
4592 Avoid confusing the two command models.
4593 @end quotation
4594
4595 Some flash chips implement software protection against accidental writes,
4596 since such buggy writes could in some cases ``brick'' a system.
4597 For such systems, erasing and writing may require sector protection to be
4598 disabled first.
4599 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4600 and AT91SAM7 on-chip flash.
4601 @xref{flashprotect,,flash protect}.
4602
4603 @deffn Command {flash erase_sector} num first last
4604 Erase sectors in bank @var{num}, starting at sector @var{first}
4605 up to and including @var{last}.
4606 Sector numbering starts at 0.
4607 Providing a @var{last} sector of @option{last}
4608 specifies "to the end of the flash bank".
4609 The @var{num} parameter is a value shown by @command{flash banks}.
4610 @end deffn
4611
4612 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4613 Erase sectors starting at @var{address} for @var{length} bytes.
4614 Unless @option{pad} is specified, @math{address} must begin a
4615 flash sector, and @math{address + length - 1} must end a sector.
4616 Specifying @option{pad} erases extra data at the beginning and/or
4617 end of the specified region, as needed to erase only full sectors.
4618 The flash bank to use is inferred from the @var{address}, and
4619 the specified length must stay within that bank.
4620 As a special case, when @var{length} is zero and @var{address} is
4621 the start of the bank, the whole flash is erased.
4622 If @option{unlock} is specified, then the flash is unprotected
4623 before erase starts.
4624 @end deffn
4625
4626 @deffn Command {flash fillw} address word length
4627 @deffnx Command {flash fillh} address halfword length
4628 @deffnx Command {flash fillb} address byte length
4629 Fills flash memory with the specified @var{word} (32 bits),
4630 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4631 starting at @var{address} and continuing
4632 for @var{length} units (word/halfword/byte).
4633 No erasure is done before writing; when needed, that must be done
4634 before issuing this command.
4635 Writes are done in blocks of up to 1024 bytes, and each write is
4636 verified by reading back the data and comparing it to what was written.
4637 The flash bank to use is inferred from the @var{address} of
4638 each block, and the specified length must stay within that bank.
4639 @end deffn
4640 @comment no current checks for errors if fill blocks touch multiple banks!
4641
4642 @deffn Command {flash write_bank} num filename offset
4643 Write the binary @file{filename} to flash bank @var{num},
4644 starting at @var{offset} bytes from the beginning of the bank.
4645 The @var{num} parameter is a value shown by @command{flash banks}.
4646 @end deffn
4647
4648 @deffn Command {flash read_bank} num filename offset length
4649 Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
4650 and write the contents to the binary @file{filename}.
4651 The @var{num} parameter is a value shown by @command{flash banks}.
4652 @end deffn
4653
4654 @deffn Command {flash verify_bank} num filename offset
4655 Compare the contents of the binary file @var{filename} with the contents of the
4656 flash @var{num} starting at @var{offset}. Fails if the contents do not match.
4657 The @var{num} parameter is a value shown by @command{flash banks}.
4658 @end deffn
4659
4660 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4661 Write the image @file{filename} to the current target's flash bank(s).
4662 Only loadable sections from the image are written.
4663 A relocation @var{offset} may be specified, in which case it is added
4664 to the base address for each section in the image.
4665 The file [@var{type}] can be specified
4666 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4667 @option{elf} (ELF file), @option{s19} (Motorola s19).
4668 @option{mem}, or @option{builder}.
4669 The relevant flash sectors will be erased prior to programming
4670 if the @option{erase} parameter is given. If @option{unlock} is
4671 provided, then the flash banks are unlocked before erase and
4672 program. The flash bank to use is inferred from the address of
4673 each image section.
4674
4675 @quotation Warning
4676 Be careful using the @option{erase} flag when the flash is holding
4677 data you want to preserve.
4678 Portions of the flash outside those described in the image's
4679 sections might be erased with no notice.
4680 @itemize
4681 @item
4682 When a section of the image being written does not fill out all the
4683 sectors it uses, the unwritten parts of those sectors are necessarily
4684 also erased, because sectors can't be partially erased.
4685 @item
4686 Data stored in sector "holes" between image sections are also affected.
4687 For example, "@command{flash write_image erase ...}" of an image with
4688 one byte at the beginning of a flash bank and one byte at the end
4689 erases the entire bank -- not just the two sectors being written.
4690 @end itemize
4691 Also, when flash protection is important, you must re-apply it after
4692 it has been removed by the @option{unlock} flag.
4693 @end quotation
4694
4695 @end deffn
4696
4697 @section Other Flash commands
4698 @cindex flash protection
4699
4700 @deffn Command {flash erase_check} num
4701 Check erase state of sectors in flash bank @var{num},
4702 and display that status.
4703 The @var{num} parameter is a value shown by @command{flash banks}.
4704 @end deffn
4705
4706 @deffn Command {flash info} num [sectors]
4707 Print info about flash bank @var{num}, a list of protection blocks
4708 and their status. Use @option{sectors} to show a list of sectors instead.
4709
4710 The @var{num} parameter is a value shown by @command{flash banks}.
4711 This command will first query the hardware, it does not print cached
4712 and possibly stale information.
4713 @end deffn
4714
4715 @anchor{flashprotect}
4716 @deffn Command {flash protect} num first last (@option{on}|@option{off})
4717 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
4718 in flash bank @var{num}, starting at sector @var{first}
4719 and continuing up to and including @var{last}.
4720 Providing a @var{last} sector of @option{last}
4721 specifies "to the end of the flash bank".
4722 The @var{num} parameter is a value shown by @command{flash banks}.
4723 @end deffn
4724
4725 @deffn Command {flash padded_value} num value
4726 Sets the default value used for padding any image sections, This should
4727 normally match the flash bank erased value. If not specified by this
4728 comamnd or the flash driver then it defaults to 0xff.
4729 @end deffn
4730
4731 @anchor{program}
4732 @deffn Command {program} filename [verify] [reset] [exit] [offset]
4733 This is a helper script that simplifies using OpenOCD as a standalone
4734 programmer. The only required parameter is @option{filename}, the others are optional.
4735 @xref{Flash Programming}.
4736 @end deffn
4737
4738 @anchor{flashdriverlist}
4739 @section Flash Driver List
4740 As noted above, the @command{flash bank} command requires a driver name,
4741 and allows driver-specific options and behaviors.
4742 Some drivers also activate driver-specific commands.
4743
4744 @deffn {Flash Driver} virtual
4745 This is a special driver that maps a previously defined bank to another
4746 address. All bank settings will be copied from the master physical bank.
4747
4748 The @var{virtual} driver defines one mandatory parameters,
4749
4750 @itemize
4751 @item @var{master_bank} The bank that this virtual address refers to.
4752 @end itemize
4753
4754 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
4755 the flash bank defined at address 0x1fc00000. Any cmds executed on
4756 the virtual banks are actually performed on the physical banks.
4757 @example
4758 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
4759 flash bank vbank0 virtual 0xbfc00000 0 0 0 \
4760 $_TARGETNAME $_FLASHNAME
4761 flash bank vbank1 virtual 0x9fc00000 0 0 0 \
4762 $_TARGETNAME $_FLASHNAME
4763 @end example
4764 @end deffn
4765
4766 @subsection External Flash
4767
4768 @deffn {Flash Driver} cfi
4769 @cindex Common Flash Interface
4770 @cindex CFI
4771 The ``Common Flash Interface'' (CFI) is the main standard for
4772 external NOR flash chips, each of which connects to a
4773 specific external chip select on the CPU.
4774 Frequently the first such chip is used to boot the system.
4775 Your board's @code{reset-init} handler might need to
4776 configure additional chip selects using other commands (like: @command{mww} to
4777 configure a bus and its timings), or
4778 perhaps configure a GPIO pin that controls the ``write protect'' pin
4779 on the flash chip.
4780 The CFI driver can use a target-specific working area to significantly
4781 speed up operation.
4782
4783 The CFI driver can accept the following optional parameters, in any order:
4784
4785 @itemize
4786 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
4787 like AM29LV010 and similar types.
4788 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
4789 @item @var{bus_swap} ... when data bytes in a 16-bit flash needs to be swapped.
4790 @item @var{data_swap} ... when data bytes in a 16-bit flash needs to be
4791 swapped when writing data values (ie. not CFI commands).
4792 @end itemize
4793
4794 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
4795 wide on a sixteen bit bus:
4796
4797 @example
4798 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
4799 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
4800 @end example
4801
4802 To configure one bank of 32 MBytes
4803 built from two sixteen bit (two byte) wide parts wired in parallel
4804 to create a thirty-two bit (four byte) bus with doubled throughput:
4805
4806 @example
4807 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
4808 @end example
4809
4810 @c "cfi part_id" disabled
4811 @end deffn
4812
4813 @deffn {Flash Driver} jtagspi
4814 @cindex Generic JTAG2SPI driver
4815 @cindex SPI
4816 @cindex jtagspi
4817 @cindex bscan_spi
4818 Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
4819 SPI flash connected to them. To access this flash from the host, the device
4820 is first programmed with a special proxy bitstream that
4821 exposes the SPI flash on the device's JTAG interface. The flash can then be
4822 accessed through JTAG.
4823
4824 Since signaling between JTAG and SPI is compatible, all that is required for
4825 a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
4826 the flash chip select when the JTAG state machine is in SHIFT-DR. Such
4827 a bitstream for several Xilinx FPGAs can be found in
4828 @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires
4829 @uref{https://github.com/m-labs/migen, migen} and a Xilinx toolchain to build.
4830
4831 This flash bank driver requires a target on a JTAG tap and will access that
4832 tap directly. Since no support from the target is needed, the target can be a
4833 "testee" dummy. Since the target does not expose the flash memory
4834 mapping, target commands that would otherwise be expected to access the flash
4835 will not work. These include all @command{*_image} and
4836 @command{$target_name m*} commands as well as @command{program}. Equivalent
4837 functionality is available through the @command{flash write_bank},
4838 @command{flash read_bank}, and @command{flash verify_bank} commands.
4839
4840 @itemize
4841 @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
4842 For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
4843 @var{USER1} instruction.
4844 @item @var{dr_length} ... is the length of the DR register. This will be 1 for
4845 @file{xilinx_bscan_spi.py} bitstreams and most other cases.
4846 @end itemize
4847
4848 @example
4849 target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
4850 set _XILINX_USER1 0x02
4851 set _DR_LENGTH 1
4852 flash bank $_FLASHNAME spi 0x0 0 0 0 \
4853 $_TARGETNAME $_XILINX_USER1 $_DR_LENGTH
4854 @end example
4855 @end deffn
4856
4857 @deffn {Flash Driver} lpcspifi
4858 @cindex NXP SPI Flash Interface
4859 @cindex SPIFI
4860 @cindex lpcspifi
4861 NXP's LPC43xx and LPC18xx families include a proprietary SPI
4862 Flash Interface (SPIFI) peripheral that can drive and provide
4863 memory mapped access to external SPI flash devices.
4864
4865 The lpcspifi driver initializes this interface and provides
4866 program and erase functionality for these serial flash devices.
4867 Use of this driver @b{requires} a working area of at least 1kB
4868 to be configured on the target device; more than this will
4869 significantly reduce flash programming times.
4870
4871 The setup command only requires the @var{base} parameter. All
4872 other parameters are ignored, and the flash size and layout
4873 are configured by the driver.
4874
4875 @example
4876 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
4877 @end example
4878
4879 @end deffn
4880
4881 @deffn {Flash Driver} stmsmi
4882 @cindex STMicroelectronics Serial Memory Interface
4883 @cindex SMI
4884 @cindex stmsmi
4885 Some devices form STMicroelectronics (e.g. STR75x MCU family,
4886 SPEAr MPU family) include a proprietary
4887 ``Serial Memory Interface'' (SMI) controller able to drive external
4888 SPI flash devices.
4889 Depending on specific device and board configuration, up to 4 external
4890 flash devices can be connected.
4891
4892 SMI makes the flash content directly accessible in the CPU address
4893 space; each external device is mapped in a memory bank.
4894 CPU can directly read data, execute code and boot from SMI banks.
4895 Normal OpenOCD commands like @command{mdw} can be used to display
4896 the flash content.
4897
4898 The setup command only requires the @var{base} parameter in order
4899 to identify the memory bank.
4900 All other parameters are ignored. Additional information, like
4901 flash size, are detected automatically.
4902
4903 @example
4904 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
4905 @end example
4906
4907 @end deffn
4908
4909 @deffn {Flash Driver} mrvlqspi
4910 This driver supports QSPI flash controller of Marvell's Wireless
4911 Microcontroller platform.
4912
4913 The flash size is autodetected based on the table of known JEDEC IDs
4914 hardcoded in the OpenOCD sources.
4915
4916 @example
4917 flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
4918 @end example
4919
4920 @end deffn
4921
4922 @subsection Internal Flash (Microcontrollers)
4923
4924 @deffn {Flash Driver} aduc702x
4925 The ADUC702x analog microcontrollers from Analog Devices
4926 include internal flash and use ARM7TDMI cores.
4927 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
4928 The setup command only requires the @var{target} argument
4929 since all devices in this family have the same memory layout.
4930
4931 @example
4932 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
4933 @end example
4934 @end deffn
4935
4936 @deffn {Flash Driver} ambiqmicro
4937 @cindex ambiqmicro
4938 @cindex apollo
4939 All members of the Apollo microcontroller family from
4940 Ambiq Micro include internal flash and use ARM's Cortex-M4 core.
4941 The host connects over USB to an FTDI interface that communicates
4942 with the target using SWD.
4943
4944 The @var{ambiqmicro} driver reads the Chip Information Register detect
4945 the device class of the MCU.
4946 The Flash and Sram sizes directly follow device class, and are used
4947 to set up the flash banks.
4948 If this fails, the driver will use default values set to the minimum
4949 sizes of an Apollo chip.
4950
4951 All Apollo chips have two flash banks of the same size.
4952 In all cases the first flash bank starts at location 0,
4953 and the second bank starts after the first.
4954
4955 @example
4956 # Flash bank 0
4957 flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
4958 # Flash bank 1 - same size as bank0, starts after bank 0.
4959 flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \
4960 $_TARGETNAME
4961 @end example
4962
4963 Flash is programmed using custom entry points into the bootloader.
4964 This is the only way to program the flash as no flash control registers
4965 are available to the user.
4966
4967 The @var{ambiqmicro} driver adds some additional commands:
4968
4969 @deffn Command {ambiqmicro mass_erase} <bank>
4970 Erase entire bank.
4971 @end deffn
4972 @deffn Command {ambiqmicro page_erase} <bank> <first> <last>
4973 Erase device pages.
4974 @end deffn
4975 @deffn Command {ambiqmicro program_otp} <bank> <offset> <count>
4976 Program OTP is a one time operation to create write protected flash.
4977 The user writes sectors to sram starting at 0x10000010.
4978 Program OTP will write these sectors from sram to flash, and write protect
4979 the flash.
4980 @end deffn
4981 @end deffn
4982
4983 @anchor{at91samd}
4984 @deffn {Flash Driver} at91samd
4985 @cindex at91samd
4986 All members of the ATSAMD, ATSAMR, ATSAML and ATSAMC microcontroller
4987 families from Atmel include internal flash and use ARM's Cortex-M0+ core.
4988 This driver uses the same cmd names/syntax as @xref{at91sam3}.
4989
4990 @deffn Command {at91samd chip-erase}
4991 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
4992 used to erase a chip back to its factory state and does not require the
4993 processor to be halted.
4994 @end deffn
4995
4996 @deffn Command {at91samd set-security}
4997 Secures the Flash via the Set Security Bit (SSB) command. This prevents access
4998 to the Flash and can only be undone by using the chip-erase command which
4999 erases the Flash contents and turns off the security bit. Warning: at this
5000 time, openocd will not be able to communicate with a secured chip and it is
5001 therefore not possible to chip-erase it without using another tool.
5002
5003 @example
5004 at91samd set-security enable
5005 @end example
5006 @end deffn
5007
5008 @deffn Command {at91samd eeprom}
5009 Shows or sets the EEPROM emulation size configuration, stored in the User Row
5010 of the Flash. When setting, the EEPROM size must be specified in bytes and it
5011 must be one of the permitted sizes according to the datasheet. Settings are
5012 written immediately but only take effect on MCU reset. EEPROM emulation
5013 requires additional firmware support and the minumum EEPROM size may not be
5014 the same as the minimum that the hardware supports. Set the EEPROM size to 0
5015 in order to disable this feature.
5016
5017 @example
5018 at91samd eeprom
5019 at91samd eeprom 1024
5020 @end example
5021 @end deffn
5022
5023 @deffn Command {at91samd bootloader}
5024 Shows or sets the bootloader size configuration, stored in the User Row of the
5025 Flash. This is called the BOOTPROT region. When setting, the bootloader size
5026 must be specified in bytes and it must be one of the permitted sizes according
5027 to the datasheet. Settings are written immediately but only take effect on
5028 MCU reset. Setting the bootloader size to 0 disables bootloader protection.
5029
5030 @example
5031 at91samd bootloader
5032 at91samd bootloader 16384
5033 @end example
5034 @end deffn
5035
5036 @deffn Command {at91samd dsu_reset_deassert}
5037 This command releases internal reset held by DSU
5038 and prepares reset vector catch in case of reset halt.
5039 Command is used internally in event event reset-deassert-post.
5040 @end deffn
5041
5042 @end deffn
5043
5044 @anchor{at91sam3}
5045 @deffn {Flash Driver} at91sam3
5046 @cindex at91sam3
5047 All members of the AT91SAM3 microcontroller family from
5048 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
5049 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
5050 that the driver was orginaly developed and tested using the
5051 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
5052 the family was cribbed from the data sheet. @emph{Note to future
5053 readers/updaters: Please remove this worrysome comment after other
5054 chips are confirmed.}
5055
5056 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
5057 have one flash bank. In all cases the flash banks are at
5058 the following fixed locations:
5059
5060 @example
5061 # Flash bank 0 - all chips
5062 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
5063 # Flash bank 1 - only 256K chips
5064 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
5065 @end example
5066
5067 Internally, the AT91SAM3 flash memory is organized as follows.
5068 Unlike the AT91SAM7 chips, these are not used as parameters
5069 to the @command{flash bank} command:
5070
5071 @itemize
5072 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
5073 @item @emph{Bank Size:} 128K/64K Per flash bank
5074 @item @emph{Sectors:} 16 or 8 per bank