doc: fix xref texinfo warning
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
82 * TFTP:: TFTP
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on:
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
95 @end menu
97 @node About
98 @unnumbered About
99 @cindex about
101 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
102 at the University of Applied Sciences Augsburg (@uref{}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
105 around the world.
107 @section What is OpenOCD?
108 @cindex TAP
109 @cindex JTAG
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
113 devices.
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board connect directly to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
140 scan operations.
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD supports only
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
154 USB-based, parallel port-based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
159 (Stellaris LM3, ST STM32 and Energy Micro EFM32) and Intel Quark (x10xx)
160 based cores to be debugged via the GDB protocol.
162 @b{Flash Programming:} Flash writing is supported for external
163 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{}
182 PDF form is likewise published at:
184 @uref{}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{}
203 @section OpenOCD IRC
205 Support can also be found on irc:
206 @uref{irc://}
208 @node Developers
209 @chapter OpenOCD Developer Resources
210 @cindex developers
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD Git Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a Git repository hosted at SourceForge. The repository URL is:
225 @uref{git://}
227 or via http
229 @uref{}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{}
235 With standard Git tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a Git client:
241 @uref{}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration at the top of the source tree.
264 @section Gerrit Review System
266 All changes in the OpenOCD Git repository go through the web-based Gerrit
267 Code Review System:
269 @uref{}
271 After a one-time registration and repository setup, anyone can push commits
272 from their local Git repository directly into Gerrit.
273 All users and developers are encouraged to review, test, discuss and vote
274 for changes in Gerrit. The feedback provides the basis for a maintainer to
275 eventually submit the change to the main Git repository.
277 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
278 Developer Manual, contains basic information about how to connect a
279 repository to Gerrit, prepare and push patches. Patch authors are expected to
280 maintain their changes while they're in Gerrit, respond to feedback and if
281 necessary rework and push improved versions of the change.
283 @section OpenOCD Developer Mailing List
285 The OpenOCD Developer Mailing List provides the primary means of
286 communication between developers:
288 @uref{}
290 @section OpenOCD Bug Tracker
292 The OpenOCD Bug Tracker is hosted on SourceForge:
294 @uref{}
297 @node Debug Adapter Hardware
298 @chapter Debug Adapter Hardware
299 @cindex dongles
300 @cindex FTDI
301 @cindex wiggler
302 @cindex zy1000
303 @cindex printer port
304 @cindex USB Adapter
305 @cindex RTCK
307 Defined: @b{dongle}: A small device that plugs into a computer and serves as
308 an adapter .... [snip]
310 In the OpenOCD case, this generally refers to @b{a small adapter} that
311 attaches to your computer via USB or the parallel port. One
312 exception is the Ultimate Solutions ZY1000, packaged as a small box you
313 attach via an ethernet cable. The ZY1000 has the advantage that it does not
314 require any drivers to be installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built-in relay to power cycle targets remotely.
319 @section Choosing a Dongle
321 There are several things you should keep in mind when choosing a dongle.
323 @enumerate
324 @item @b{Transport} Does it support the kind of communication that you need?
325 OpenOCD focusses mostly on JTAG. Your version may also support
326 other ways to communicate with target devices.
327 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
328 Does your dongle support it? You might need a level converter.
329 @item @b{Pinout} What pinout does your target board use?
330 Does your dongle support it? You may be able to use jumper
331 wires, or an "octopus" connector, to convert pinouts.
332 @item @b{Connection} Does your computer have the USB, parallel, or
333 Ethernet port needed?
334 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
335 RTCK support (also known as ``adaptive clocking'')?
336 @end enumerate
338 @section Stand-alone JTAG Probe
340 The ZY1000 from Ultimate Solutions is technically not a dongle but a
341 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
342 running on the developer's host computer.
343 Once installed on a network using DHCP or a static IP assignment, users can
344 access the ZY1000 probe locally or remotely from any host with access to the
345 IP address assigned to the probe.
346 The ZY1000 provides an intuitive web interface with direct access to the
347 OpenOCD debugger.
348 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
349 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
350 the target.
351 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
352 to power cycle the target remotely.
354 For more information, visit:
356 @b{ZY1000} See: @url{}
358 @section USB FT2232 Based
360 There are many USB JTAG dongles on the market, many of them based
361 on a chip from ``Future Technology Devices International'' (FTDI)
362 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
363 See: @url{} for more information.
364 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
365 chips started to become available in JTAG adapters. Around 2012, a new
366 variant appeared - FT232H - this is a single-channel version of FT2232H.
367 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
368 clocking.)
370 The FT2232 chips are flexible enough to support some other
371 transport options, such as SWD or the SPI variants used to
372 program some chips. They have two communications channels,
373 and one can be used for a UART adapter at the same time the
374 other one is used to provide a debug adapter.
376 Also, some development boards integrate an FT2232 chip to serve as
377 a built-in low-cost debug adapter and USB-to-serial solution.
379 @itemize @bullet
380 @item @b{usbjtag}
381 @* Link @url{}
382 @item @b{jtagkey}
383 @* See: @url{}
384 @item @b{jtagkey2}
385 @* See: @url{}
386 @item @b{oocdlink}
387 @* See: @url{} By Joern Kaipf
388 @item @b{signalyzer}
389 @* See: @url{}
390 @item @b{Stellaris Eval Boards}
391 @* See: @url{} - The Stellaris eval boards
392 bundle FT2232-based JTAG and SWD support, which can be used to debug
393 the Stellaris chips. Using separate JTAG adapters is optional.
394 These boards can also be used in a "pass through" mode as JTAG adapters
395 to other target boards, disabling the Stellaris chip.
396 @item @b{TI/Luminary ICDI}
397 @* See: @url{} - TI/Luminary In-Circuit Debug
398 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
399 Evaluation Kits. Like the non-detachable FT2232 support on the other
400 Stellaris eval boards, they can be used to debug other target boards.
401 @item @b{olimex-jtag}
402 @* See: @url{}
403 @item @b{Flyswatter/Flyswatter2}
404 @* See: @url{}
405 @item @b{turtelizer2}
406 @* See:
407 @uref{, Turtelizer 2}, or
408 @url{}
409 @item @b{comstick}
410 @* Link: @url{}
411 @item @b{stm32stick}
412 @* Link @url{}
413 @item @b{axm0432_jtag}
414 @* Axiom AXM-0432 Link @url{} - NOTE: This JTAG does not appear
415 to be available anymore as of April 2012.
416 @item @b{cortino}
417 @* Link @url{}
418 @item @b{dlp-usb1232h}
419 @* Link @url{}
420 @item @b{digilent-hs1}
421 @* Link @url{}
422 @item @b{opendous}
423 @* Link @url{} FT2232H-based
424 (OpenHardware).
425 @item @b{JTAG-lock-pick Tiny 2}
426 @* Link @url{} FT232H-based
428 @item @b{GW16042}
429 @* Link: @url{}
430 FT2232H-based
432 @end itemize
433 @section USB-JTAG / Altera USB-Blaster compatibles
435 These devices also show up as FTDI devices, but are not
436 protocol-compatible with the FT2232 devices. They are, however,
437 protocol-compatible among themselves. USB-JTAG devices typically consist
438 of a FT245 followed by a CPLD that understands a particular protocol,
439 or emulates this protocol using some other hardware.
441 They may appear under different USB VID/PID depending on the particular
442 product. The driver can be configured to search for any VID/PID pair
443 (see the section on driver commands).
445 @itemize
446 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
447 @* Link: @url{}
448 @item @b{Altera USB-Blaster}
449 @* Link: @url{}
450 @end itemize
452 @section USB J-Link based
453 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
454 an example of a microcontroller based JTAG adapter, it uses an
455 AT91SAM764 internally.
457 @itemize @bullet
458 @item @b{SEGGER J-Link}
459 @* Link: @url{}
460 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
461 @* Link: @url{}
462 @item @b{IAR J-Link}
463 @end itemize
465 @section USB RLINK based
466 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
467 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
468 SWD and not JTAG, thus not supported.
470 @itemize @bullet
471 @item @b{Raisonance RLink}
472 @* Link: @url{}
473 @item @b{STM32 Primer}
474 @* Link: @url{}
475 @item @b{STM32 Primer2}
476 @* Link: @url{}
477 @end itemize
479 @section USB ST-LINK based
480 ST Micro has an adapter called @b{ST-LINK}.
481 They only work with ST Micro chips, notably STM32 and STM8.
483 @itemize @bullet
484 @item @b{ST-LINK}
485 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
486 @* Link: @url{}
487 @item @b{ST-LINK/V2}
488 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
489 @* Link: @url{}
490 @end itemize
492 For info the original ST-LINK enumerates using the mass storage usb class; however,
493 its implementation is completely broken. The result is this causes issues under Linux.
494 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
495 @itemize @bullet
496 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
497 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
498 @end itemize
500 @section USB TI/Stellaris ICDI based
501 Texas Instruments has an adapter called @b{ICDI}.
502 It is not to be confused with the FTDI based adapters that were originally fitted to their
503 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
505 @section USB CMSIS-DAP based
506 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
507 debuggers to ARM Cortex based targets @url{}.
509 @section USB Other
510 @itemize @bullet
511 @item @b{USBprog}
512 @* Link: @url{} - which uses an Atmel MEGA32 and a UBN9604
514 @item @b{USB - Presto}
515 @* Link: @url{}
517 @item @b{Versaloon-Link}
518 @* Link: @url{}
520 @item @b{ARM-JTAG-EW}
521 @* Link: @url{}
523 @item @b{Buspirate}
524 @* Link: @url{}
526 @item @b{opendous}
527 @* Link: @url{} - which uses an AT90USB162
529 @item @b{estick}
530 @* Link: @url{}
532 @item @b{Keil ULINK v1}
533 @* Link: @url{}
534 @end itemize
536 @section IBM PC Parallel Printer Port Based
538 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
539 and the Macraigor Wiggler. There are many clones and variations of
540 these on the market.
542 Note that parallel ports are becoming much less common, so if you
543 have the choice you should probably avoid these adapters in favor
544 of USB-based ones.
546 @itemize @bullet
548 @item @b{Wiggler} - There are many clones of this.
549 @* Link: @url{}
551 @item @b{DLC5} - From XILINX - There are many clones of this
552 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
553 produced, PDF schematics are easily found and it is easy to make.
555 @item @b{Amontec - JTAG Accelerator}
556 @* Link: @url{}
558 @item @b{Wiggler2}
559 @* Link: @url{}
561 @item @b{Wiggler_ntrst_inverted}
562 @* Yet another variation - See the source code, src/jtag/parport.c
564 @item @b{old_amt_wiggler}
565 @* Unknown - probably not on the market today
567 @item @b{arm-jtag}
568 @* Link: Most likely @url{} [another wiggler clone]
570 @item @b{chameleon}
571 @* Link: @url{}
573 @item @b{Triton}
574 @* Unknown.
576 @item @b{Lattice}
577 @* ispDownload from Lattice Semiconductor
578 @url{}
580 @item @b{flashlink}
581 @* From ST Microsystems;
582 @* Link: @url{}
584 @end itemize
586 @section Other...
587 @itemize @bullet
589 @item @b{ep93xx}
590 @* An EP93xx based Linux machine using the GPIO pins directly.
592 @item @b{at91rm9200}
593 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
595 @item @b{bcm2835gpio}
596 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
598 @item @b{imx_gpio}
599 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
601 @item @b{jtag_vpi}
602 @* A JTAG driver acting as a client for the JTAG VPI server interface.
603 @* Link: @url{}
605 @end itemize
607 @node About Jim-Tcl
608 @chapter About Jim-Tcl
609 @cindex Jim-Tcl
610 @cindex tcl
612 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
613 This programming language provides a simple and extensible
614 command interpreter.
616 All commands presented in this Guide are extensions to Jim-Tcl.
617 You can use them as simple commands, without needing to learn
618 much of anything about Tcl.
619 Alternatively, you can write Tcl programs with them.
621 You can learn more about Jim at its website, @url{}.
622 There is an active and responsive community, get on the mailing list
623 if you have any questions. Jim-Tcl maintainers also lurk on the
624 OpenOCD mailing list.
626 @itemize @bullet
627 @item @b{Jim vs. Tcl}
628 @* Jim-Tcl is a stripped down version of the well known Tcl language,
629 which can be found here: @url{}. Jim-Tcl has far
630 fewer features. Jim-Tcl is several dozens of .C files and .H files and
631 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
632 4.2 MB .zip file containing 1540 files.
634 @item @b{Missing Features}
635 @* Our practice has been: Add/clone the real Tcl feature if/when
636 needed. We welcome Jim-Tcl improvements, not bloat. Also there
637 are a large number of optional Jim-Tcl features that are not
638 enabled in OpenOCD.
640 @item @b{Scripts}
641 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
642 command interpreter today is a mixture of (newer)
643 Jim-Tcl commands, and the (older) original command interpreter.
645 @item @b{Commands}
646 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
647 can type a Tcl for() loop, set variables, etc.
648 Some of the commands documented in this guide are implemented
649 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
651 @item @b{Historical Note}
652 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
653 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
654 as a Git submodule, which greatly simplified upgrading Jim-Tcl
655 to benefit from new features and bugfixes in Jim-Tcl.
657 @item @b{Need a crash course in Tcl?}
658 @*@xref{Tcl Crash Course}.
659 @end itemize
661 @node Running
662 @chapter Running
663 @cindex command line options
664 @cindex logfile
665 @cindex directory search
667 Properly installing OpenOCD sets up your operating system to grant it access
668 to the debug adapters. On Linux, this usually involves installing a file
669 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
670 that works for many common adapters is shipped with OpenOCD in the
671 @file{contrib} directory. MS-Windows needs
672 complex and confusing driver configuration for every peripheral. Such issues
673 are unique to each operating system, and are not detailed in this User's Guide.
675 Then later you will invoke the OpenOCD server, with various options to
676 tell it how each debug session should work.
677 The @option{--help} option shows:
678 @verbatim
679 bash$ openocd --help
681 --help | -h display this help
682 --version | -v display OpenOCD version
683 --file | -f use configuration file <name>
684 --search | -s dir to search for config files and scripts
685 --debug | -d set debug level to 3
686 | -d<n> set debug level to <level>
687 --log_output | -l redirect log output to file <name>
688 --command | -c run <command>
689 @end verbatim
691 If you don't give any @option{-f} or @option{-c} options,
692 OpenOCD tries to read the configuration file @file{openocd.cfg}.
693 To specify one or more different
694 configuration files, use @option{-f} options. For example:
696 @example
697 openocd -f config1.cfg -f config2.cfg -f config3.cfg
698 @end example
700 Configuration files and scripts are searched for in
701 @enumerate
702 @item the current directory,
703 @item any search dir specified on the command line using the @option{-s} option,
704 @item any search dir specified using the @command{add_script_search_dir} command,
705 @item @file{$HOME/.openocd} (not on Windows),
706 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
707 @item the site wide script library @file{$pkgdatadir/site} and
708 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
709 @end enumerate
710 The first found file with a matching file name will be used.
712 @quotation Note
713 Don't try to use configuration script names or paths which
714 include the "#" character. That character begins Tcl comments.
715 @end quotation
717 @section Simple setup, no customization
719 In the best case, you can use two scripts from one of the script
720 libraries, hook up your JTAG adapter, and start the server ... and
721 your JTAG setup will just work "out of the box". Always try to
722 start by reusing those scripts, but assume you'll need more
723 customization even if this works. @xref{OpenOCD Project Setup}.
725 If you find a script for your JTAG adapter, and for your board or
726 target, you may be able to hook up your JTAG adapter then start
727 the server with some variation of one of the following:
729 @example
730 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
731 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
732 @end example
734 You might also need to configure which reset signals are present,
735 using @option{-c 'reset_config trst_and_srst'} or something similar.
736 If all goes well you'll see output something like
738 @example
739 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
740 For bug reports, read
742 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
743 (mfg: 0x23b, part: 0xba00, ver: 0x3)
744 @end example
746 Seeing that "tap/device found" message, and no warnings, means
747 the JTAG communication is working. That's a key milestone, but
748 you'll probably need more project-specific setup.
750 @section What OpenOCD does as it starts
752 OpenOCD starts by processing the configuration commands provided
753 on the command line or, if there were no @option{-c command} or
754 @option{-f file.cfg} options given, in @file{openocd.cfg}.
755 @xref{configurationstage,,Configuration Stage}.
756 At the end of the configuration stage it verifies the JTAG scan
757 chain defined using those commands; your configuration should
758 ensure that this always succeeds.
759 Normally, OpenOCD then starts running as a server.
760 Alternatively, commands may be used to terminate the configuration
761 stage early, perform work (such as updating some flash memory),
762 and then shut down without acting as a server.
764 Once OpenOCD starts running as a server, it waits for connections from
765 clients (Telnet, GDB, RPC) and processes the commands issued through
766 those channels.
768 If you are having problems, you can enable internal debug messages via
769 the @option{-d} option.
771 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
772 @option{-c} command line switch.
774 To enable debug output (when reporting problems or working on OpenOCD
775 itself), use the @option{-d} command line switch. This sets the
776 @option{debug_level} to "3", outputting the most information,
777 including debug messages. The default setting is "2", outputting only
778 informational messages, warnings and errors. You can also change this
779 setting from within a telnet or gdb session using @command{debug_level<n>}
780 (@pxref{debuglevel,,debug_level}).
782 You can redirect all output from the server to a file using the
783 @option{-l <logfile>} switch.
785 Note! OpenOCD will launch the GDB & telnet server even if it can not
786 establish a connection with the target. In general, it is possible for
787 the JTAG controller to be unresponsive until the target is set up
788 correctly via e.g. GDB monitor commands in a GDB init script.
790 @node OpenOCD Project Setup
791 @chapter OpenOCD Project Setup
793 To use OpenOCD with your development projects, you need to do more than
794 just connect the JTAG adapter hardware (dongle) to your development board
795 and start the OpenOCD server.
796 You also need to configure your OpenOCD server so that it knows
797 about your adapter and board, and helps your work.
798 You may also want to connect OpenOCD to GDB, possibly
799 using Eclipse or some other GUI.
801 @section Hooking up the JTAG Adapter
803 Today's most common case is a dongle with a JTAG cable on one side
804 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
805 and a USB cable on the other.
806 Instead of USB, some cables use Ethernet;
807 older ones may use a PC parallel port, or even a serial port.
809 @enumerate
810 @item @emph{Start with power to your target board turned off},
811 and nothing connected to your JTAG adapter.
812 If you're particularly paranoid, unplug power to the board.
813 It's important to have the ground signal properly set up,
814 unless you are using a JTAG adapter which provides
815 galvanic isolation between the target board and the
816 debugging host.
818 @item @emph{Be sure it's the right kind of JTAG connector.}
819 If your dongle has a 20-pin ARM connector, you need some kind
820 of adapter (or octopus, see below) to hook it up to
821 boards using 14-pin or 10-pin connectors ... or to 20-pin
822 connectors which don't use ARM's pinout.
824 In the same vein, make sure the voltage levels are compatible.
825 Not all JTAG adapters have the level shifters needed to work
826 with 1.2 Volt boards.
828 @item @emph{Be certain the cable is properly oriented} or you might
829 damage your board. In most cases there are only two possible
830 ways to connect the cable.
831 Connect the JTAG cable from your adapter to the board.
832 Be sure it's firmly connected.
834 In the best case, the connector is keyed to physically
835 prevent you from inserting it wrong.
836 This is most often done using a slot on the board's male connector
837 housing, which must match a key on the JTAG cable's female connector.
838 If there's no housing, then you must look carefully and
839 make sure pin 1 on the cable hooks up to pin 1 on the board.
840 Ribbon cables are frequently all grey except for a wire on one
841 edge, which is red. The red wire is pin 1.
843 Sometimes dongles provide cables where one end is an ``octopus'' of
844 color coded single-wire connectors, instead of a connector block.
845 These are great when converting from one JTAG pinout to another,
846 but are tedious to set up.
847 Use these with connector pinout diagrams to help you match up the
848 adapter signals to the right board pins.
850 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
851 A USB, parallel, or serial port connector will go to the host which
852 you are using to run OpenOCD.
853 For Ethernet, consult the documentation and your network administrator.
855 For USB-based JTAG adapters you have an easy sanity check at this point:
856 does the host operating system see the JTAG adapter? If you're running
857 Linux, try the @command{lsusb} command. If that host is an
858 MS-Windows host, you'll need to install a driver before OpenOCD works.
860 @item @emph{Connect the adapter's power supply, if needed.}
861 This step is primarily for non-USB adapters,
862 but sometimes USB adapters need extra power.
864 @item @emph{Power up the target board.}
865 Unless you just let the magic smoke escape,
866 you're now ready to set up the OpenOCD server
867 so you can use JTAG to work with that board.
869 @end enumerate
871 Talk with the OpenOCD server using
872 telnet (@code{telnet localhost 4444} on many systems) or GDB.
873 @xref{GDB and OpenOCD}.
875 @section Project Directory
877 There are many ways you can configure OpenOCD and start it up.
879 A simple way to organize them all involves keeping a
880 single directory for your work with a given board.
881 When you start OpenOCD from that directory,
882 it searches there first for configuration files, scripts,
883 files accessed through semihosting,
884 and for code you upload to the target board.
885 It is also the natural place to write files,
886 such as log files and data you download from the board.
888 @section Configuration Basics
890 There are two basic ways of configuring OpenOCD, and
891 a variety of ways you can mix them.
892 Think of the difference as just being how you start the server:
894 @itemize
895 @item Many @option{-f file} or @option{-c command} options on the command line
896 @item No options, but a @dfn{user config file}
897 in the current directory named @file{openocd.cfg}
898 @end itemize
900 Here is an example @file{openocd.cfg} file for a setup
901 using a Signalyzer FT2232-based JTAG adapter to talk to
902 a board with an Atmel AT91SAM7X256 microcontroller:
904 @example
905 source [find interface/ftdi/signalyzer.cfg]
907 # GDB can also flash my flash!
908 gdb_memory_map enable
909 gdb_flash_program enable
911 source [find target/sam7x256.cfg]
912 @end example
914 Here is the command line equivalent of that configuration:
916 @example
917 openocd -f interface/ftdi/signalyzer.cfg \
918 -c "gdb_memory_map enable" \
919 -c "gdb_flash_program enable" \
920 -f target/sam7x256.cfg
921 @end example
923 You could wrap such long command lines in shell scripts,
924 each supporting a different development task.
925 One might re-flash the board with a specific firmware version.
926 Another might set up a particular debugging or run-time environment.
928 @quotation Important
929 At this writing (October 2009) the command line method has
930 problems with how it treats variables.
931 For example, after @option{-c "set VAR value"}, or doing the
932 same in a script, the variable @var{VAR} will have no value
933 that can be tested in a later script.
934 @end quotation
936 Here we will focus on the simpler solution: one user config
937 file, including basic configuration plus any TCL procedures
938 to simplify your work.
940 @section User Config Files
941 @cindex config file, user
942 @cindex user config file
943 @cindex config file, overview
945 A user configuration file ties together all the parts of a project
946 in one place.
947 One of the following will match your situation best:
949 @itemize
950 @item Ideally almost everything comes from configuration files
951 provided by someone else.
952 For example, OpenOCD distributes a @file{scripts} directory
953 (probably in @file{/usr/share/openocd/scripts} on Linux).
954 Board and tool vendors can provide these too, as can individual
955 user sites; the @option{-s} command line option lets you say
956 where to find these files. (@xref{Running}.)
957 The AT91SAM7X256 example above works this way.
959 Three main types of non-user configuration file each have their
960 own subdirectory in the @file{scripts} directory:
962 @enumerate
963 @item @b{interface} -- one for each different debug adapter;
964 @item @b{board} -- one for each different board
965 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
966 @end enumerate
968 Best case: include just two files, and they handle everything else.
969 The first is an interface config file.
970 The second is board-specific, and it sets up the JTAG TAPs and
971 their GDB targets (by deferring to some @file{target.cfg} file),
972 declares all flash memory, and leaves you nothing to do except
973 meet your deadline:
975 @example
976 source [find interface/olimex-jtag-tiny.cfg]
977 source [find board/csb337.cfg]
978 @end example
980 Boards with a single microcontroller often won't need more
981 than the target config file, as in the AT91SAM7X256 example.
982 That's because there is no external memory (flash, DDR RAM), and
983 the board differences are encapsulated by application code.
985 @item Maybe you don't know yet what your board looks like to JTAG.
986 Once you know the @file{interface.cfg} file to use, you may
987 need help from OpenOCD to discover what's on the board.
988 Once you find the JTAG TAPs, you can just search for appropriate
989 target and board
990 configuration files ... or write your own, from the bottom up.
991 @xref{autoprobing,,Autoprobing}.
993 @item You can often reuse some standard config files but
994 need to write a few new ones, probably a @file{board.cfg} file.
995 You will be using commands described later in this User's Guide,
996 and working with the guidelines in the next chapter.
998 For example, there may be configuration files for your JTAG adapter
999 and target chip, but you need a new board-specific config file
1000 giving access to your particular flash chips.
1001 Or you might need to write another target chip configuration file
1002 for a new chip built around the Cortex-M3 core.
1004 @quotation Note
1005 When you write new configuration files, please submit
1006 them for inclusion in the next OpenOCD release.
1007 For example, a @file{board/newboard.cfg} file will help the
1008 next users of that board, and a @file{target/newcpu.cfg}
1009 will help support users of any board using that chip.
1010 @end quotation
1012 @item
1013 You may may need to write some C code.
1014 It may be as simple as supporting a new FT2232 or parport
1015 based adapter; a bit more involved, like a NAND or NOR flash
1016 controller driver; or a big piece of work like supporting
1017 a new chip architecture.
1018 @end itemize
1020 Reuse the existing config files when you can.
1021 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1022 You may find a board configuration that's a good example to follow.
1024 When you write config files, separate the reusable parts
1025 (things every user of that interface, chip, or board needs)
1026 from ones specific to your environment and debugging approach.
1027 @itemize
1029 @item
1030 For example, a @code{gdb-attach} event handler that invokes
1031 the @command{reset init} command will interfere with debugging
1032 early boot code, which performs some of the same actions
1033 that the @code{reset-init} event handler does.
1035 @item
1036 Likewise, the @command{arm9 vector_catch} command (or
1037 @cindex vector_catch
1038 its siblings @command{xscale vector_catch}
1039 and @command{cortex_m vector_catch}) can be a timesaver
1040 during some debug sessions, but don't make everyone use that either.
1041 Keep those kinds of debugging aids in your user config file,
1042 along with messaging and tracing setup.
1043 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1045 @item
1046 You might need to override some defaults.
1047 For example, you might need to move, shrink, or back up the target's
1048 work area if your application needs much SRAM.
1050 @item
1051 TCP/IP port configuration is another example of something which
1052 is environment-specific, and should only appear in
1053 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1054 @end itemize
1056 @section Project-Specific Utilities
1058 A few project-specific utility
1059 routines may well speed up your work.
1060 Write them, and keep them in your project's user config file.
1062 For example, if you are making a boot loader work on a
1063 board, it's nice to be able to debug the ``after it's
1064 loaded to RAM'' parts separately from the finicky early
1065 code which sets up the DDR RAM controller and clocks.
1066 A script like this one, or a more GDB-aware sibling,
1067 may help:
1069 @example
1070 proc ramboot @{ @} @{
1071 # Reset, running the target's "reset-init" scripts
1072 # to initialize clocks and the DDR RAM controller.
1073 # Leave the CPU halted.
1074 reset init
1076 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1077 load_image u-boot.bin 0x20000000
1079 # Start running.
1080 resume 0x20000000
1081 @}
1082 @end example
1084 Then once that code is working you will need to make it
1085 boot from NOR flash; a different utility would help.
1086 Alternatively, some developers write to flash using GDB.
1087 (You might use a similar script if you're working with a flash
1088 based microcontroller application instead of a boot loader.)
1090 @example
1091 proc newboot @{ @} @{
1092 # Reset, leaving the CPU halted. The "reset-init" event
1093 # proc gives faster access to the CPU and to NOR flash;
1094 # "reset halt" would be slower.
1095 reset init
1097 # Write standard version of U-Boot into the first two
1098 # sectors of NOR flash ... the standard version should
1099 # do the same lowlevel init as "reset-init".
1100 flash protect 0 0 1 off
1101 flash erase_sector 0 0 1
1102 flash write_bank 0 u-boot.bin 0x0
1103 flash protect 0 0 1 on
1105 # Reboot from scratch using that new boot loader.
1106 reset run
1107 @}
1108 @end example
1110 You may need more complicated utility procedures when booting
1111 from NAND.
1112 That often involves an extra bootloader stage,
1113 running from on-chip SRAM to perform DDR RAM setup so it can load
1114 the main bootloader code (which won't fit into that SRAM).
1116 Other helper scripts might be used to write production system images,
1117 involving considerably more than just a three stage bootloader.
1119 @section Target Software Changes
1121 Sometimes you may want to make some small changes to the software
1122 you're developing, to help make JTAG debugging work better.
1123 For example, in C or assembly language code you might
1124 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1125 handling issues like:
1127 @itemize @bullet
1129 @item @b{Watchdog Timers}...
1130 Watchog timers are typically used to automatically reset systems if
1131 some application task doesn't periodically reset the timer. (The
1132 assumption is that the system has locked up if the task can't run.)
1133 When a JTAG debugger halts the system, that task won't be able to run
1134 and reset the timer ... potentially causing resets in the middle of
1135 your debug sessions.
1137 It's rarely a good idea to disable such watchdogs, since their usage
1138 needs to be debugged just like all other parts of your firmware.
1139 That might however be your only option.
1141 Look instead for chip-specific ways to stop the watchdog from counting
1142 while the system is in a debug halt state. It may be simplest to set
1143 that non-counting mode in your debugger startup scripts. You may however
1144 need a different approach when, for example, a motor could be physically
1145 damaged by firmware remaining inactive in a debug halt state. That might
1146 involve a type of firmware mode where that "non-counting" mode is disabled
1147 at the beginning then re-enabled at the end; a watchdog reset might fire
1148 and complicate the debug session, but hardware (or people) would be
1149 protected.@footnote{Note that many systems support a "monitor mode" debug
1150 that is a somewhat cleaner way to address such issues. You can think of
1151 it as only halting part of the system, maybe just one task,
1152 instead of the whole thing.
1153 At this writing, January 2010, OpenOCD based debugging does not support
1154 monitor mode debug, only "halt mode" debug.}
1156 @item @b{ARM Semihosting}...
1157 @cindex ARM semihosting
1158 When linked with a special runtime library provided with many
1159 toolchains@footnote{See chapter 8 "Semihosting" in
1160 @uref{,
1161 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1162 The CodeSourcery EABI toolchain also includes a semihosting library.},
1163 your target code can use I/O facilities on the debug host. That library
1164 provides a small set of system calls which are handled by OpenOCD.
1165 It can let the debugger provide your system console and a file system,
1166 helping with early debugging or providing a more capable environment
1167 for sometimes-complex tasks like installing system firmware onto
1168 NAND or SPI flash.
1170 @item @b{ARM Wait-For-Interrupt}...
1171 Many ARM chips synchronize the JTAG clock using the core clock.
1172 Low power states which stop that core clock thus prevent JTAG access.
1173 Idle loops in tasking environments often enter those low power states
1174 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1176 You may want to @emph{disable that instruction} in source code,
1177 or otherwise prevent using that state,
1178 to ensure you can get JTAG access at any time.@footnote{As a more
1179 polite alternative, some processors have special debug-oriented
1180 registers which can be used to change various features including
1181 how the low power states are clocked while debugging.
1182 The STM32 DBGMCU_CR register is an example; at the cost of extra
1183 power consumption, JTAG can be used during low power states.}
1184 For example, the OpenOCD @command{halt} command may not
1185 work for an idle processor otherwise.
1187 @item @b{Delay after reset}...
1188 Not all chips have good support for debugger access
1189 right after reset; many LPC2xxx chips have issues here.
1190 Similarly, applications that reconfigure pins used for
1191 JTAG access as they start will also block debugger access.
1193 To work with boards like this, @emph{enable a short delay loop}
1194 the first thing after reset, before "real" startup activities.
1195 For example, one second's delay is usually more than enough
1196 time for a JTAG debugger to attach, so that
1197 early code execution can be debugged
1198 or firmware can be replaced.
1200 @item @b{Debug Communications Channel (DCC)}...
1201 Some processors include mechanisms to send messages over JTAG.
1202 Many ARM cores support these, as do some cores from other vendors.
1203 (OpenOCD may be able to use this DCC internally, speeding up some
1204 operations like writing to memory.)
1206 Your application may want to deliver various debugging messages
1207 over JTAG, by @emph{linking with a small library of code}
1208 provided with OpenOCD and using the utilities there to send
1209 various kinds of message.
1210 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1212 @end itemize
1214 @section Target Hardware Setup
1216 Chip vendors often provide software development boards which
1217 are highly configurable, so that they can support all options
1218 that product boards may require. @emph{Make sure that any
1219 jumpers or switches match the system configuration you are
1220 working with.}
1222 Common issues include:
1224 @itemize @bullet
1226 @item @b{JTAG setup} ...
1227 Boards may support more than one JTAG configuration.
1228 Examples include jumpers controlling pullups versus pulldowns
1229 on the nTRST and/or nSRST signals, and choice of connectors
1230 (e.g. which of two headers on the base board,
1231 or one from a daughtercard).
1232 For some Texas Instruments boards, you may need to jumper the
1233 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1235 @item @b{Boot Modes} ...
1236 Complex chips often support multiple boot modes, controlled
1237 by external jumpers. Make sure this is set up correctly.
1238 For example many i.MX boards from NXP need to be jumpered
1239 to "ATX mode" to start booting using the on-chip ROM, when
1240 using second stage bootloader code stored in a NAND flash chip.
1242 Such explicit configuration is common, and not limited to
1243 booting from NAND. You might also need to set jumpers to
1244 start booting using code loaded from an MMC/SD card; external
1245 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1246 flash; some external host; or various other sources.
1249 @item @b{Memory Addressing} ...
1250 Boards which support multiple boot modes may also have jumpers
1251 to configure memory addressing. One board, for example, jumpers
1252 external chipselect 0 (used for booting) to address either
1253 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1254 or NAND flash. When it's jumpered to address NAND flash, that
1255 board must also be told to start booting from on-chip ROM.
1257 Your @file{board.cfg} file may also need to be told this jumper
1258 configuration, so that it can know whether to declare NOR flash
1259 using @command{flash bank} or instead declare NAND flash with
1260 @command{nand device}; and likewise which probe to perform in
1261 its @code{reset-init} handler.
1263 A closely related issue is bus width. Jumpers might need to
1264 distinguish between 8 bit or 16 bit bus access for the flash
1265 used to start booting.
1267 @item @b{Peripheral Access} ...
1268 Development boards generally provide access to every peripheral
1269 on the chip, sometimes in multiple modes (such as by providing
1270 multiple audio codec chips).
1271 This interacts with software
1272 configuration of pin multiplexing, where for example a
1273 given pin may be routed either to the MMC/SD controller
1274 or the GPIO controller. It also often interacts with
1275 configuration jumpers. One jumper may be used to route
1276 signals to an MMC/SD card slot or an expansion bus (which
1277 might in turn affect booting); others might control which
1278 audio or video codecs are used.
1280 @end itemize
1282 Plus you should of course have @code{reset-init} event handlers
1283 which set up the hardware to match that jumper configuration.
1284 That includes in particular any oscillator or PLL used to clock
1285 the CPU, and any memory controllers needed to access external
1286 memory and peripherals. Without such handlers, you won't be
1287 able to access those resources without working target firmware
1288 which can do that setup ... this can be awkward when you're
1289 trying to debug that target firmware. Even if there's a ROM
1290 bootloader which handles a few issues, it rarely provides full
1291 access to all board-specific capabilities.
1294 @node Config File Guidelines
1295 @chapter Config File Guidelines
1297 This chapter is aimed at any user who needs to write a config file,
1298 including developers and integrators of OpenOCD and any user who
1299 needs to get a new board working smoothly.
1300 It provides guidelines for creating those files.
1302 You should find the following directories under
1303 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1304 them as-is where you can; or as models for new files.
1305 @itemize @bullet
1306 @item @file{interface} ...
1307 These are for debug adapters. Files that specify configuration to use
1308 specific JTAG, SWD and other adapters go here.
1309 @item @file{board} ...
1310 Think Circuit Board, PWA, PCB, they go by many names. Board files
1311 contain initialization items that are specific to a board.
1313 They reuse target configuration files, since the same
1314 microprocessor chips are used on many boards,
1315 but support for external parts varies widely. For
1316 example, the SDRAM initialization sequence for the board, or the type
1317 of external flash and what address it uses. Any initialization
1318 sequence to enable that external flash or SDRAM should be found in the
1319 board file. Boards may also contain multiple targets: two CPUs; or
1320 a CPU and an FPGA.
1321 @item @file{target} ...
1322 Think chip. The ``target'' directory represents the JTAG TAPs
1323 on a chip
1324 which OpenOCD should control, not a board. Two common types of targets
1325 are ARM chips and FPGA or CPLD chips.
1326 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1327 the target config file defines all of them.
1328 @item @emph{more} ... browse for other library files which may be useful.
1329 For example, there are various generic and CPU-specific utilities.
1330 @end itemize
1332 The @file{openocd.cfg} user config
1333 file may override features in any of the above files by
1334 setting variables before sourcing the target file, or by adding
1335 commands specific to their situation.
1337 @section Interface Config Files
1339 The user config file
1340 should be able to source one of these files with a command like this:
1342 @example
1343 source [find interface/FOOBAR.cfg]
1344 @end example
1346 A preconfigured interface file should exist for every debug adapter
1347 in use today with OpenOCD.
1348 That said, perhaps some of these config files
1349 have only been used by the developer who created it.
1351 A separate chapter gives information about how to set these up.
1352 @xref{Debug Adapter Configuration}.
1353 Read the OpenOCD source code (and Developer's Guide)
1354 if you have a new kind of hardware interface
1355 and need to provide a driver for it.
1357 @section Board Config Files
1358 @cindex config file, board
1359 @cindex board config file
1361 The user config file
1362 should be able to source one of these files with a command like this:
1364 @example
1365 source [find board/FOOBAR.cfg]
1366 @end example
1368 The point of a board config file is to package everything
1369 about a given board that user config files need to know.
1370 In summary the board files should contain (if present)
1372 @enumerate
1373 @item One or more @command{source [find target/...cfg]} statements
1374 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1375 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1376 @item Target @code{reset} handlers for SDRAM and I/O configuration
1377 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1378 @item All things that are not ``inside a chip''
1379 @end enumerate
1381 Generic things inside target chips belong in target config files,
1382 not board config files. So for example a @code{reset-init} event
1383 handler should know board-specific oscillator and PLL parameters,
1384 which it passes to target-specific utility code.
1386 The most complex task of a board config file is creating such a
1387 @code{reset-init} event handler.
1388 Define those handlers last, after you verify the rest of the board
1389 configuration works.
1391 @subsection Communication Between Config files
1393 In addition to target-specific utility code, another way that
1394 board and target config files communicate is by following a
1395 convention on how to use certain variables.
1397 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1398 Thus the rule we follow in OpenOCD is this: Variables that begin with
1399 a leading underscore are temporary in nature, and can be modified and
1400 used at will within a target configuration file.
1402 Complex board config files can do the things like this,
1403 for a board with three chips:
1405 @example
1406 # Chip #1: PXA270 for network side, big endian
1407 set CHIPNAME network
1408 set ENDIAN big
1409 source [find target/pxa270.cfg]
1410 # on return: _TARGETNAME = network.cpu
1411 # other commands can refer to the "network.cpu" target.
1412 $_TARGETNAME configure .... events for this CPU..
1414 # Chip #2: PXA270 for video side, little endian
1415 set CHIPNAME video
1416 set ENDIAN little
1417 source [find target/pxa270.cfg]
1418 # on return: _TARGETNAME = video.cpu
1419 # other commands can refer to the "video.cpu" target.
1420 $_TARGETNAME configure .... events for this CPU..
1422 # Chip #3: Xilinx FPGA for glue logic
1423 set CHIPNAME xilinx
1424 unset ENDIAN
1425 source [find target/spartan3.cfg]
1426 @end example
1428 That example is oversimplified because it doesn't show any flash memory,
1429 or the @code{reset-init} event handlers to initialize external DRAM
1430 or (assuming it needs it) load a configuration into the FPGA.
1431 Such features are usually needed for low-level work with many boards,
1432 where ``low level'' implies that the board initialization software may
1433 not be working. (That's a common reason to need JTAG tools. Another
1434 is to enable working with microcontroller-based systems, which often
1435 have no debugging support except a JTAG connector.)
1437 Target config files may also export utility functions to board and user
1438 config files. Such functions should use name prefixes, to help avoid
1439 naming collisions.
1441 Board files could also accept input variables from user config files.
1442 For example, there might be a @code{J4_JUMPER} setting used to identify
1443 what kind of flash memory a development board is using, or how to set
1444 up other clocks and peripherals.
1446 @subsection Variable Naming Convention
1447 @cindex variable names
1449 Most boards have only one instance of a chip.
1450 However, it should be easy to create a board with more than
1451 one such chip (as shown above).
1452 Accordingly, we encourage these conventions for naming
1453 variables associated with different @file{target.cfg} files,
1454 to promote consistency and
1455 so that board files can override target defaults.
1457 Inputs to target config files include:
1459 @itemize @bullet
1460 @item @code{CHIPNAME} ...
1461 This gives a name to the overall chip, and is used as part of
1462 tap identifier dotted names.
1463 While the default is normally provided by the chip manufacturer,
1464 board files may need to distinguish between instances of a chip.
1465 @item @code{ENDIAN} ...
1466 By default @option{little} - although chips may hard-wire @option{big}.
1467 Chips that can't change endianness don't need to use this variable.
1468 @item @code{CPUTAPID} ...
1469 When OpenOCD examines the JTAG chain, it can be told verify the
1470 chips against the JTAG IDCODE register.
1471 The target file will hold one or more defaults, but sometimes the
1472 chip in a board will use a different ID (perhaps a newer revision).
1473 @end itemize
1475 Outputs from target config files include:
1477 @itemize @bullet
1478 @item @code{_TARGETNAME} ...
1479 By convention, this variable is created by the target configuration
1480 script. The board configuration file may make use of this variable to
1481 configure things like a ``reset init'' script, or other things
1482 specific to that board and that target.
1483 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1484 @code{_TARGETNAME1}, ... etc.
1485 @end itemize
1487 @subsection The reset-init Event Handler
1488 @cindex event, reset-init
1489 @cindex reset-init handler
1491 Board config files run in the OpenOCD configuration stage;
1492 they can't use TAPs or targets, since they haven't been
1493 fully set up yet.
1494 This means you can't write memory or access chip registers;
1495 you can't even verify that a flash chip is present.
1496 That's done later in event handlers, of which the target @code{reset-init}
1497 handler is one of the most important.
1499 Except on microcontrollers, the basic job of @code{reset-init} event
1500 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1501 Microcontrollers rarely use boot loaders; they run right out of their
1502 on-chip flash and SRAM memory. But they may want to use one of these
1503 handlers too, if just for developer convenience.
1505 @quotation Note
1506 Because this is so very board-specific, and chip-specific, no examples
1507 are included here.
1508 Instead, look at the board config files distributed with OpenOCD.
1509 If you have a boot loader, its source code will help; so will
1510 configuration files for other JTAG tools
1511 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1512 @end quotation
1514 Some of this code could probably be shared between different boards.
1515 For example, setting up a DRAM controller often doesn't differ by
1516 much except the bus width (16 bits or 32?) and memory timings, so a
1517 reusable TCL procedure loaded by the @file{target.cfg} file might take
1518 those as parameters.
1519 Similarly with oscillator, PLL, and clock setup;
1520 and disabling the watchdog.
1521 Structure the code cleanly, and provide comments to help
1522 the next developer doing such work.
1523 (@emph{You might be that next person} trying to reuse init code!)
1525 The last thing normally done in a @code{reset-init} handler is probing
1526 whatever flash memory was configured. For most chips that needs to be
1527 done while the associated target is halted, either because JTAG memory
1528 access uses the CPU or to prevent conflicting CPU access.
1530 @subsection JTAG Clock Rate
1532 Before your @code{reset-init} handler has set up
1533 the PLLs and clocking, you may need to run with
1534 a low JTAG clock rate.
1535 @xref{jtagspeed,,JTAG Speed}.
1536 Then you'd increase that rate after your handler has
1537 made it possible to use the faster JTAG clock.
1538 When the initial low speed is board-specific, for example
1539 because it depends on a board-specific oscillator speed, then
1540 you should probably set it up in the board config file;
1541 if it's target-specific, it belongs in the target config file.
1543 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1544 @uref{} gives details.}
1545 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1546 Consult chip documentation to determine the peak JTAG clock rate,
1547 which might be less than that.
1549 @quotation Warning
1550 On most ARMs, JTAG clock detection is coupled to the core clock, so
1551 software using a @option{wait for interrupt} operation blocks JTAG access.
1552 Adaptive clocking provides a partial workaround, but a more complete
1553 solution just avoids using that instruction with JTAG debuggers.
1554 @end quotation
1556 If both the chip and the board support adaptive clocking,
1557 use the @command{jtag_rclk}
1558 command, in case your board is used with JTAG adapter which
1559 also supports it. Otherwise use @command{adapter_khz}.
1560 Set the slow rate at the beginning of the reset sequence,
1561 and the faster rate as soon as the clocks are at full speed.
1563 @anchor{theinitboardprocedure}
1564 @subsection The init_board procedure
1565 @cindex init_board procedure
1567 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1568 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1569 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1570 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1571 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1572 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1573 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1574 Additionally ``linear'' board config file will most likely fail when target config file uses
1575 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1576 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1577 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1578 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1580 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1581 the original), allowing greater code reuse.
1583 @example
1584 ### board_file.cfg ###
1586 # source target file that does most of the config in init_targets
1587 source [find target/target.cfg]
1589 proc enable_fast_clock @{@} @{
1590 # enables fast on-board clock source
1591 # configures the chip to use it
1592 @}
1594 # initialize only board specifics - reset, clock, adapter frequency
1595 proc init_board @{@} @{
1596 reset_config trst_and_srst trst_pulls_srst
1598 $_TARGETNAME configure -event reset-start @{
1599 adapter_khz 100
1600 @}
1602 $_TARGETNAME configure -event reset-init @{
1603 enable_fast_clock
1604 adapter_khz 10000
1605 @}
1606 @}
1607 @end example
1609 @section Target Config Files
1610 @cindex config file, target
1611 @cindex target config file
1613 Board config files communicate with target config files using
1614 naming conventions as described above, and may source one or
1615 more target config files like this:
1617 @example
1618 source [find target/FOOBAR.cfg]
1619 @end example
1621 The point of a target config file is to package everything
1622 about a given chip that board config files need to know.
1623 In summary the target files should contain
1625 @enumerate
1626 @item Set defaults
1627 @item Add TAPs to the scan chain
1628 @item Add CPU targets (includes GDB support)
1629 @item CPU/Chip/CPU-Core specific features
1630 @item On-Chip flash
1631 @end enumerate
1633 As a rule of thumb, a target file sets up only one chip.
1634 For a microcontroller, that will often include a single TAP,
1635 which is a CPU needing a GDB target, and its on-chip flash.
1637 More complex chips may include multiple TAPs, and the target
1638 config file may need to define them all before OpenOCD
1639 can talk to the chip.
1640 For example, some phone chips have JTAG scan chains that include
1641 an ARM core for operating system use, a DSP,
1642 another ARM core embedded in an image processing engine,
1643 and other processing engines.
1645 @subsection Default Value Boiler Plate Code
1647 All target configuration files should start with code like this,
1648 letting board config files express environment-specific
1649 differences in how things should be set up.
1651 @example
1652 # Boards may override chip names, perhaps based on role,
1653 # but the default should match what the vendor uses
1654 if @{ [info exists CHIPNAME] @} @{
1656 @} else @{
1657 set _CHIPNAME sam7x256
1658 @}
1660 # ONLY use ENDIAN with targets that can change it.
1661 if @{ [info exists ENDIAN] @} @{
1662 set _ENDIAN $ENDIAN
1663 @} else @{
1664 set _ENDIAN little
1665 @}
1667 # TAP identifiers may change as chips mature, for example with
1668 # new revision fields (the "3" here). Pick a good default; you
1669 # can pass several such identifiers to the "jtag newtap" command.
1670 if @{ [info exists CPUTAPID ] @} @{
1672 @} else @{
1673 set _CPUTAPID 0x3f0f0f0f
1674 @}
1675 @end example
1676 @c but 0x3f0f0f0f is for an str73x part ...
1678 @emph{Remember:} Board config files may include multiple target
1679 config files, or the same target file multiple times
1680 (changing at least @code{CHIPNAME}).
1682 Likewise, the target configuration file should define
1683 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1684 use it later on when defining debug targets:
1686 @example
1688 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1689 @end example
1691 @subsection Adding TAPs to the Scan Chain
1692 After the ``defaults'' are set up,
1693 add the TAPs on each chip to the JTAG scan chain.
1694 @xref{TAP Declaration}, and the naming convention
1695 for taps.
1697 In the simplest case the chip has only one TAP,
1698 probably for a CPU or FPGA.
1699 The config file for the Atmel AT91SAM7X256
1700 looks (in part) like this:
1702 @example
1703 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1704 @end example
1706 A board with two such at91sam7 chips would be able
1707 to source such a config file twice, with different
1708 values for @code{CHIPNAME}, so
1709 it adds a different TAP each time.
1711 If there are nonzero @option{-expected-id} values,
1712 OpenOCD attempts to verify the actual tap id against those values.
1713 It will issue error messages if there is mismatch, which
1714 can help to pinpoint problems in OpenOCD configurations.
1716 @example
1717 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1718 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1719 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1720 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1721 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1722 @end example
1724 There are more complex examples too, with chips that have
1725 multiple TAPs. Ones worth looking at include:
1727 @itemize
1728 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1729 plus a JRC to enable them
1730 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1731 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1732 is not currently used)
1733 @end itemize
1735 @subsection Add CPU targets
1737 After adding a TAP for a CPU, you should set it up so that
1738 GDB and other commands can use it.
1739 @xref{CPU Configuration}.
1740 For the at91sam7 example above, the command can look like this;
1741 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1742 to little endian, and this chip doesn't support changing that.
1744 @example
1746 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1747 @end example
1749 Work areas are small RAM areas associated with CPU targets.
1750 They are used by OpenOCD to speed up downloads,
1751 and to download small snippets of code to program flash chips.
1752 If the chip includes a form of ``on-chip-ram'' - and many do - define
1753 a work area if you can.
1754 Again using the at91sam7 as an example, this can look like:
1756 @example
1757 $_TARGETNAME configure -work-area-phys 0x00200000 \
1758 -work-area-size 0x4000 -work-area-backup 0
1759 @end example
1761 @anchor{definecputargetsworkinginsmp}
1762 @subsection Define CPU targets working in SMP
1763 @cindex SMP
1764 After setting targets, you can define a list of targets working in SMP.
1766 @example
1767 set _TARGETNAME_1 $_CHIPNAME.cpu1
1768 set _TARGETNAME_2 $_CHIPNAME.cpu2
1769 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1770 -coreid 0 -dbgbase $_DAP_DBG1
1771 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1772 -coreid 1 -dbgbase $_DAP_DBG2
1773 #define 2 targets working in smp.
1774 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1775 @end example
1776 In the above example on cortex_a, 2 cpus are working in SMP.
1777 In SMP only one GDB instance is created and :
1778 @itemize @bullet
1779 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1780 @item halt command triggers the halt of all targets in the list.
1781 @item resume command triggers the write context and the restart of all targets in the list.
1782 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1783 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1784 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1785 @end itemize
1787 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1788 command have been implemented.
1789 @itemize @bullet
1790 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1791 @item cortex_a smp_off : disable SMP mode, the current target is the one
1792 displayed in the GDB session, only this target is now controlled by GDB
1793 session. This behaviour is useful during system boot up.
1794 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1795 following example.
1796 @end itemize
1798 @example
1799 >cortex_a smp_gdb
1800 gdb coreid 0 -> -1
1801 #0 : coreid 0 is displayed to GDB ,
1802 #-> -1 : next resume triggers a real resume
1803 > cortex_a smp_gdb 1
1804 gdb coreid 0 -> 1
1805 #0 :coreid 0 is displayed to GDB ,
1806 #->1 : next resume displays coreid 1 to GDB
1807 > resume
1808 > cortex_a smp_gdb
1809 gdb coreid 1 -> 1
1810 #1 :coreid 1 is displayed to GDB ,
1811 #->1 : next resume displays coreid 1 to GDB
1812 > cortex_a smp_gdb -1
1813 gdb coreid 1 -> -1
1814 #1 :coreid 1 is displayed to GDB,
1815 #->-1 : next resume triggers a real resume
1816 @end example
1819 @subsection Chip Reset Setup
1821 As a rule, you should put the @command{reset_config} command
1822 into the board file. Most things you think you know about a
1823 chip can be tweaked by the board.
1825 Some chips have specific ways the TRST and SRST signals are
1826 managed. In the unusual case that these are @emph{chip specific}
1827 and can never be changed by board wiring, they could go here.
1828 For example, some chips can't support JTAG debugging without
1829 both signals.
1831 Provide a @code{reset-assert} event handler if you can.
1832 Such a handler uses JTAG operations to reset the target,
1833 letting this target config be used in systems which don't
1834 provide the optional SRST signal, or on systems where you
1835 don't want to reset all targets at once.
1836 Such a handler might write to chip registers to force a reset,
1837 use a JRC to do that (preferable -- the target may be wedged!),
1838 or force a watchdog timer to trigger.
1839 (For Cortex-M targets, this is not necessary. The target
1840 driver knows how to use trigger an NVIC reset when SRST is
1841 not available.)
1843 Some chips need special attention during reset handling if
1844 they're going to be used with JTAG.
1845 An example might be needing to send some commands right
1846 after the target's TAP has been reset, providing a
1847 @code{reset-deassert-post} event handler that writes a chip
1848 register to report that JTAG debugging is being done.
1849 Another would be reconfiguring the watchdog so that it stops
1850 counting while the core is halted in the debugger.
1852 JTAG clocking constraints often change during reset, and in
1853 some cases target config files (rather than board config files)
1854 are the right places to handle some of those issues.
1855 For example, immediately after reset most chips run using a
1856 slower clock than they will use later.
1857 That means that after reset (and potentially, as OpenOCD
1858 first starts up) they must use a slower JTAG clock rate
1859 than they will use later.
1860 @xref{jtagspeed,,JTAG Speed}.
1862 @quotation Important
1863 When you are debugging code that runs right after chip
1864 reset, getting these issues right is critical.
1865 In particular, if you see intermittent failures when
1866 OpenOCD verifies the scan chain after reset,
1867 look at how you are setting up JTAG clocking.
1868 @end quotation
1870 @anchor{theinittargetsprocedure}
1871 @subsection The init_targets procedure
1872 @cindex init_targets procedure
1874 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1875 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1876 procedure called @code{init_targets}, which will be executed when entering run stage
1877 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1878 Such procedure can be overriden by ``next level'' script (which sources the original).
1879 This concept faciliates code reuse when basic target config files provide generic configuration
1880 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
1881 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1882 because sourcing them executes every initialization commands they provide.
1884 @example
1885 ### generic_file.cfg ###
1887 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1888 # basic initialization procedure ...
1889 @}
1891 proc init_targets @{@} @{
1892 # initializes generic chip with 4kB of flash and 1kB of RAM
1893 setup_my_chip MY_GENERIC_CHIP 4096 1024
1894 @}
1896 ### specific_file.cfg ###
1898 source [find target/generic_file.cfg]
1900 proc init_targets @{@} @{
1901 # initializes specific chip with 128kB of flash and 64kB of RAM
1902 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1903 @}
1904 @end example
1906 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1907 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1909 For an example of this scheme see LPC2000 target config files.
1911 The @code{init_boards} procedure is a similar concept concerning board config files
1912 (@xref{theinitboardprocedure,,The init_board procedure}.)
1914 @anchor{theinittargeteventsprocedure}
1915 @subsection The init_target_events procedure
1916 @cindex init_target_events procedure
1918 A special procedure called @code{init_target_events} is run just after
1919 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1920 procedure}.) and before @code{init_board}
1921 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1922 to set up default target events for the targets that do not have those
1923 events already assigned.
1925 @subsection ARM Core Specific Hacks
1927 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1928 special high speed download features - enable it.
1930 If present, the MMU, the MPU and the CACHE should be disabled.
1932 Some ARM cores are equipped with trace support, which permits
1933 examination of the instruction and data bus activity. Trace
1934 activity is controlled through an ``Embedded Trace Module'' (ETM)
1935 on one of the core's scan chains. The ETM emits voluminous data
1936 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1937 If you are using an external trace port,
1938 configure it in your board config file.
1939 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1940 configure it in your target config file.
1942 @example
1943 etm config $_TARGETNAME 16 normal full etb
1944 etb config $_TARGETNAME $_CHIPNAME.etb
1945 @end example
1947 @subsection Internal Flash Configuration
1949 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1951 @b{Never ever} in the ``target configuration file'' define any type of
1952 flash that is external to the chip. (For example a BOOT flash on
1953 Chip Select 0.) Such flash information goes in a board file - not
1954 the TARGET (chip) file.
1956 Examples:
1957 @itemize @bullet
1958 @item at91sam7x256 - has 256K flash YES enable it.
1959 @item str912 - has flash internal YES enable it.
1960 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1961 @item pxa270 - again - CS0 flash - it goes in the board file.
1962 @end itemize
1964 @anchor{translatingconfigurationfiles}
1965 @section Translating Configuration Files
1966 @cindex translation
1967 If you have a configuration file for another hardware debugger
1968 or toolset (Abatron, BDI2000, BDI3000, CCS,
1969 Lauterbach, SEGGER, Macraigor, etc.), translating
1970 it into OpenOCD syntax is often quite straightforward. The most tricky
1971 part of creating a configuration script is oftentimes the reset init
1972 sequence where e.g. PLLs, DRAM and the like is set up.
1974 One trick that you can use when translating is to write small
1975 Tcl procedures to translate the syntax into OpenOCD syntax. This
1976 can avoid manual translation errors and make it easier to
1977 convert other scripts later on.
1979 Example of transforming quirky arguments to a simple search and
1980 replace job:
1982 @example
1983 # Lauterbach syntax(?)
1984 #
1985 # Data.Set c15:0x042f %long 0x40000015
1986 #
1987 # OpenOCD syntax when using procedure below.
1988 #
1989 # setc15 0x01 0x00050078
1991 proc setc15 @{regs value@} @{
1992 global TARGETNAME
1994 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
1996 arm mcr 15 [expr ($regs>>12)&0x7] \
1997 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
1998 [expr ($regs>>8)&0x7] $value
1999 @}
2000 @end example
2004 @node Server Configuration
2005 @chapter Server Configuration
2006 @cindex initialization
2007 The commands here are commonly found in the openocd.cfg file and are
2008 used to specify what TCP/IP ports are used, and how GDB should be
2009 supported.
2011 @anchor{configurationstage}
2012 @section Configuration Stage
2013 @cindex configuration stage
2014 @cindex config command
2016 When the OpenOCD server process starts up, it enters a
2017 @emph{configuration stage} which is the only time that
2018 certain commands, @emph{configuration commands}, may be issued.
2019 Normally, configuration commands are only available
2020 inside startup scripts.
2022 In this manual, the definition of a configuration command is
2023 presented as a @emph{Config Command}, not as a @emph{Command}
2024 which may be issued interactively.
2025 The runtime @command{help} command also highlights configuration
2026 commands, and those which may be issued at any time.
2028 Those configuration commands include declaration of TAPs,
2029 flash banks,
2030 the interface used for JTAG communication,
2031 and other basic setup.
2032 The server must leave the configuration stage before it
2033 may access or activate TAPs.
2034 After it leaves this stage, configuration commands may no
2035 longer be issued.
2037 @anchor{enteringtherunstage}
2038 @section Entering the Run Stage
2040 The first thing OpenOCD does after leaving the configuration
2041 stage is to verify that it can talk to the scan chain
2042 (list of TAPs) which has been configured.
2043 It will warn if it doesn't find TAPs it expects to find,
2044 or finds TAPs that aren't supposed to be there.
2045 You should see no errors at this point.
2046 If you see errors, resolve them by correcting the
2047 commands you used to configure the server.
2048 Common errors include using an initial JTAG speed that's too
2049 fast, and not providing the right IDCODE values for the TAPs
2050 on the scan chain.
2052 Once OpenOCD has entered the run stage, a number of commands
2053 become available.
2054 A number of these relate to the debug targets you may have declared.
2055 For example, the @command{mww} command will not be available until
2056 a target has been successfuly instantiated.
2057 If you want to use those commands, you may need to force
2058 entry to the run stage.
2060 @deffn {Config Command} init
2061 This command terminates the configuration stage and
2062 enters the run stage. This helps when you need to have
2063 the startup scripts manage tasks such as resetting the target,
2064 programming flash, etc. To reset the CPU upon startup, add "init" and
2065 "reset" at the end of the config script or at the end of the OpenOCD
2066 command line using the @option{-c} command line switch.
2068 If this command does not appear in any startup/configuration file
2069 OpenOCD executes the command for you after processing all
2070 configuration files and/or command line options.
2072 @b{NOTE:} This command normally occurs at or near the end of your
2073 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2074 targets ready. For example: If your openocd.cfg file needs to
2075 read/write memory on your target, @command{init} must occur before
2076 the memory read/write commands. This includes @command{nand probe}.
2077 @end deffn
2079 @deffn {Overridable Procedure} jtag_init
2080 This is invoked at server startup to verify that it can talk
2081 to the scan chain (list of TAPs) which has been configured.
2083 The default implementation first tries @command{jtag arp_init},
2084 which uses only a lightweight JTAG reset before examining the
2085 scan chain.
2086 If that fails, it tries again, using a harder reset
2087 from the overridable procedure @command{init_reset}.
2089 Implementations must have verified the JTAG scan chain before
2090 they return.
2091 This is done by calling @command{jtag arp_init}
2092 (or @command{jtag arp_init-reset}).
2093 @end deffn
2095 @anchor{tcpipports}
2096 @section TCP/IP Ports
2097 @cindex TCP port
2098 @cindex server
2099 @cindex port
2100 @cindex security
2101 The OpenOCD server accepts remote commands in several syntaxes.
2102 Each syntax uses a different TCP/IP port, which you may specify
2103 only during configuration (before those ports are opened).
2105 For reasons including security, you may wish to prevent remote
2106 access using one or more of these ports.
2107 In such cases, just specify the relevant port number as "disabled".
2108 If you disable all access through TCP/IP, you will need to
2109 use the command line @option{-pipe} option.
2111 @deffn {Command} gdb_port [number]
2112 @cindex GDB server
2113 Normally gdb listens to a TCP/IP port, but GDB can also
2114 communicate via pipes(stdin/out or named pipes). The name
2115 "gdb_port" stuck because it covers probably more than 90% of
2116 the normal use cases.
2118 No arguments reports GDB port. "pipe" means listen to stdin
2119 output to stdout, an integer is base port number, "disabled"
2120 disables the gdb server.
2122 When using "pipe", also use log_output to redirect the log
2123 output to a file so as not to flood the stdin/out pipes.
2125 The -p/--pipe option is deprecated and a warning is printed
2126 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2128 Any other string is interpreted as named pipe to listen to.
2129 Output pipe is the same name as input pipe, but with 'o' appended,
2130 e.g. /var/gdb, /var/gdbo.
2132 The GDB port for the first target will be the base port, the
2133 second target will listen on gdb_port + 1, and so on.
2134 When not specified during the configuration stage,
2135 the port @var{number} defaults to 3333.
2137 Note: when using "gdb_port pipe", increasing the default remote timeout in
2138 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2139 cause initialization to fail with "Unknown remote qXfer reply: OK".
2141 @end deffn
2143 @deffn {Command} tcl_port [number]
2144 Specify or query the port used for a simplified RPC
2145 connection that can be used by clients to issue TCL commands and get the
2146 output from the Tcl engine.
2147 Intended as a machine interface.
2148 When not specified during the configuration stage,
2149 the port @var{number} defaults to 6666.
2150 When specified as "disabled", this service is not activated.
2151 @end deffn
2153 @deffn {Command} telnet_port [number]
2154 Specify or query the
2155 port on which to listen for incoming telnet connections.
2156 This port is intended for interaction with one human through TCL commands.
2157 When not specified during the configuration stage,
2158 the port @var{number} defaults to 4444.
2159 When specified as "disabled", this service is not activated.
2160 @end deffn
2162 @anchor{gdbconfiguration}
2163 @section GDB Configuration
2164 @cindex GDB
2165 @cindex GDB configuration
2166 You can reconfigure some GDB behaviors if needed.
2167 The ones listed here are static and global.
2168 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2169 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2171 @anchor{gdbbreakpointoverride}
2172 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2173 Force breakpoint type for gdb @command{break} commands.
2174 This option supports GDB GUIs which don't
2175 distinguish hard versus soft breakpoints, if the default OpenOCD and
2176 GDB behaviour is not sufficient. GDB normally uses hardware
2177 breakpoints if the memory map has been set up for flash regions.
2178 @end deffn
2180 @anchor{gdbflashprogram}
2181 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2182 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2183 vFlash packet is received.
2184 The default behaviour is @option{enable}.
2185 @end deffn
2187 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2188 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2189 requested. GDB will then know when to set hardware breakpoints, and program flash
2190 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2191 for flash programming to work.
2192 Default behaviour is @option{enable}.
2193 @xref{gdbflashprogram,,gdb_flash_program}.
2194 @end deffn
2196 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2197 Specifies whether data aborts cause an error to be reported
2198 by GDB memory read packets.
2199 The default behaviour is @option{disable};
2200 use @option{enable} see these errors reported.
2201 @end deffn
2203 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2204 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2205 The default behaviour is @option{enable}.
2206 @end deffn
2208 @deffn {Command} gdb_save_tdesc
2209 Saves the target descripton file to the local file system.
2211 The file name is @i{target_name}.xml.
2212 @end deffn
2214 @anchor{eventpolling}
2215 @section Event Polling
2217 Hardware debuggers are parts of asynchronous systems,
2218 where significant events can happen at any time.
2219 The OpenOCD server needs to detect some of these events,
2220 so it can report them to through TCL command line
2221 or to GDB.
2223 Examples of such events include:
2225 @itemize
2226 @item One of the targets can stop running ... maybe it triggers
2227 a code breakpoint or data watchpoint, or halts itself.
2228 @item Messages may be sent over ``debug message'' channels ... many
2229 targets support such messages sent over JTAG,
2230 for receipt by the person debugging or tools.
2231 @item Loss of power ... some adapters can detect these events.
2232 @item Resets not issued through JTAG ... such reset sources
2233 can include button presses or other system hardware, sometimes
2234 including the target itself (perhaps through a watchdog).
2235 @item Debug instrumentation sometimes supports event triggering
2236 such as ``trace buffer full'' (so it can quickly be emptied)
2237 or other signals (to correlate with code behavior).
2238 @end itemize
2240 None of those events are signaled through standard JTAG signals.
2241 However, most conventions for JTAG connectors include voltage
2242 level and system reset (SRST) signal detection.
2243 Some connectors also include instrumentation signals, which
2244 can imply events when those signals are inputs.
2246 In general, OpenOCD needs to periodically check for those events,
2247 either by looking at the status of signals on the JTAG connector
2248 or by sending synchronous ``tell me your status'' JTAG requests
2249 to the various active targets.
2250 There is a command to manage and monitor that polling,
2251 which is normally done in the background.
2253 @deffn Command poll [@option{on}|@option{off}]
2254 Poll the current target for its current state.
2255 (Also, @pxref{targetcurstate,,target curstate}.)
2256 If that target is in debug mode, architecture
2257 specific information about the current state is printed.
2258 An optional parameter
2259 allows background polling to be enabled and disabled.
2261 You could use this from the TCL command shell, or
2262 from GDB using @command{monitor poll} command.
2263 Leave background polling enabled while you're using GDB.
2264 @example
2265 > poll
2266 background polling: on
2267 target state: halted
2268 target halted in ARM state due to debug-request, \
2269 current mode: Supervisor
2270 cpsr: 0x800000d3 pc: 0x11081bfc
2271 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2272 >
2273 @end example
2274 @end deffn
2276 @node Debug Adapter Configuration
2277 @chapter Debug Adapter Configuration
2278 @cindex config file, interface
2279 @cindex interface config file
2281 Correctly installing OpenOCD includes making your operating system give
2282 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2283 are used to select which one is used, and to configure how it is used.
2285 @quotation Note
2286 Because OpenOCD started out with a focus purely on JTAG, you may find
2287 places where it wrongly presumes JTAG is the only transport protocol
2288 in use. Be aware that recent versions of OpenOCD are removing that
2289 limitation. JTAG remains more functional than most other transports.
2290 Other transports do not support boundary scan operations, or may be
2291 specific to a given chip vendor. Some might be usable only for
2292 programming flash memory, instead of also for debugging.
2293 @end quotation
2295 Debug Adapters/Interfaces/Dongles are normally configured
2296 through commands in an interface configuration
2297 file which is sourced by your @file{openocd.cfg} file, or
2298 through a command line @option{-f interface/....cfg} option.
2300 @example
2301 source [find interface/olimex-jtag-tiny.cfg]
2302 @end example
2304 These commands tell
2305 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2306 A few cases are so simple that you only need to say what driver to use:
2308 @example
2309 # jlink interface
2310 interface jlink
2311 @end example
2313 Most adapters need a bit more configuration than that.
2316 @section Interface Configuration
2318 The interface command tells OpenOCD what type of debug adapter you are
2319 using. Depending on the type of adapter, you may need to use one or
2320 more additional commands to further identify or configure the adapter.
2322 @deffn {Config Command} {interface} name
2323 Use the interface driver @var{name} to connect to the
2324 target.
2325 @end deffn
2327 @deffn Command {interface_list}
2328 List the debug adapter drivers that have been built into
2329 the running copy of OpenOCD.
2330 @end deffn
2331 @deffn Command {interface transports} transport_name+
2332 Specifies the transports supported by this debug adapter.
2333 The adapter driver builds-in similar knowledge; use this only
2334 when external configuration (such as jumpering) changes what
2335 the hardware can support.
2336 @end deffn
2340 @deffn Command {adapter_name}
2341 Returns the name of the debug adapter driver being used.
2342 @end deffn
2344 @section Interface Drivers
2346 Each of the interface drivers listed here must be explicitly
2347 enabled when OpenOCD is configured, in order to be made
2348 available at run time.
2350 @deffn {Interface Driver} {amt_jtagaccel}
2351 Amontec Chameleon in its JTAG Accelerator configuration,
2352 connected to a PC's EPP mode parallel port.
2353 This defines some driver-specific commands:
2355 @deffn {Config Command} {parport_port} number
2356 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2357 the number of the @file{/dev/parport} device.
2358 @end deffn
2360 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2361 Displays status of RTCK option.
2362 Optionally sets that option first.
2363 @end deffn
2364 @end deffn
2366 @deffn {Interface Driver} {arm-jtag-ew}
2367 Olimex ARM-JTAG-EW USB adapter
2368 This has one driver-specific command:
2370 @deffn Command {armjtagew_info}
2371 Logs some status
2372 @end deffn
2373 @end deffn
2375 @deffn {Interface Driver} {at91rm9200}
2376 Supports bitbanged JTAG from the local system,
2377 presuming that system is an Atmel AT91rm9200
2378 and a specific set of GPIOs is used.
2379 @c command: at91rm9200_device NAME
2380 @c chooses among list of bit configs ... only one option
2381 @end deffn
2383 @deffn {Interface Driver} {cmsis-dap}
2384 ARM CMSIS-DAP compliant based adapter.
2386 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2387 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2388 the driver will attempt to auto detect the CMSIS-DAP device.
2389 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2390 @example
2391 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2392 @end example
2393 @end deffn
2395 @deffn {Config Command} {cmsis_dap_serial} [serial]
2396 Specifies the @var{serial} of the CMSIS-DAP device to use.
2397 If not specified, serial numbers are not considered.
2398 @end deffn
2400 @deffn {Command} {cmsis-dap info}
2401 Display various device information, like hardware version, firmware version, current bus status.
2402 @end deffn
2403 @end deffn
2405 @deffn {Interface Driver} {dummy}
2406 A dummy software-only driver for debugging.
2407 @end deffn
2409 @deffn {Interface Driver} {ep93xx}
2410 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2411 @end deffn
2413 @deffn {Interface Driver} {ftdi}
2414 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2415 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2417 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2418 bypassing intermediate libraries like libftdi or D2XX.
2420 Support for new FTDI based adapters can be added competely through
2421 configuration files, without the need to patch and rebuild OpenOCD.
2423 The driver uses a signal abstraction to enable Tcl configuration files to
2424 define outputs for one or several FTDI GPIO. These outputs can then be
2425 controlled using the @command{ftdi_set_signal} command. Special signal names
2426 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2427 will be used for their customary purpose. Inputs can be read using the
2428 @command{ftdi_get_signal} command.
2430 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2431 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2432 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2433 required by the protocol, to tell the adapter to drive the data output onto
2434 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2436 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2437 be controlled differently. In order to support tristateable signals such as
2438 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2439 signal. The following output buffer configurations are supported:
2441 @itemize @minus
2442 @item Push-pull with one FTDI output as (non-)inverted data line
2443 @item Open drain with one FTDI output as (non-)inverted output-enable
2444 @item Tristate with one FTDI output as (non-)inverted data line and another
2445 FTDI output as (non-)inverted output-enable
2446 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2447 switching data and direction as necessary
2448 @end itemize
2450 These interfaces have several commands, used to configure the driver
2451 before initializing the JTAG scan chain:
2453 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2454 The vendor ID and product ID of the adapter. Up to eight
2455 [@var{vid}, @var{pid}] pairs may be given, e.g.
2456 @example
2457 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2458 @end example
2459 @end deffn
2461 @deffn {Config Command} {ftdi_device_desc} description
2462 Provides the USB device description (the @emph{iProduct string})
2463 of the adapter. If not specified, the device description is ignored
2464 during device selection.
2465 @end deffn
2467 @deffn {Config Command} {ftdi_serial} serial-number
2468 Specifies the @var{serial-number} of the adapter to use,
2469 in case the vendor provides unique IDs and more than one adapter
2470 is connected to the host.
2471 If not specified, serial numbers are not considered.
2472 (Note that USB serial numbers can be arbitrary Unicode strings,
2473 and are not restricted to containing only decimal digits.)
2474 @end deffn
2476 @deffn {Config Command} {ftdi_location} <bus>:<port>[,<port>]...
2477 Specifies the physical USB port of the adapter to use. The path
2478 roots at @var{bus} and walks down the physical ports, with each
2479 @var{port} option specifying a deeper level in the bus topology, the last
2480 @var{port} denoting where the target adapter is actually plugged.
2481 The USB bus topology can be queried with the command @emph{lsusb -t}.
2483 This command is only available if your libusb1 is at least version 1.0.16.
2484 @end deffn
2486 @deffn {Config Command} {ftdi_channel} channel
2487 Selects the channel of the FTDI device to use for MPSSE operations. Most
2488 adapters use the default, channel 0, but there are exceptions.
2489 @end deffn
2491 @deffn {Config Command} {ftdi_layout_init} data direction
2492 Specifies the initial values of the FTDI GPIO data and direction registers.
2493 Each value is a 16-bit number corresponding to the concatenation of the high
2494 and low FTDI GPIO registers. The values should be selected based on the
2495 schematics of the adapter, such that all signals are set to safe levels with
2496 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2497 and initially asserted reset signals.
2498 @end deffn
2500 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2501 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2502 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2503 register bitmasks to tell the driver the connection and type of the output
2504 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2505 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2506 used with inverting data inputs and @option{-data} with non-inverting inputs.
2507 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2508 not-output-enable) input to the output buffer is connected. The options
2509 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2510 with the method @command{ftdi_get_signal}.
2512 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2513 simple open-collector transistor driver would be specified with @option{-oe}
2514 only. In that case the signal can only be set to drive low or to Hi-Z and the
2515 driver will complain if the signal is set to drive high. Which means that if
2516 it's a reset signal, @command{reset_config} must be specified as
2517 @option{srst_open_drain}, not @option{srst_push_pull}.
2519 A special case is provided when @option{-data} and @option{-oe} is set to the
2520 same bitmask. Then the FTDI pin is considered being connected straight to the
2521 target without any buffer. The FTDI pin is then switched between output and
2522 input as necessary to provide the full set of low, high and Hi-Z
2523 characteristics. In all other cases, the pins specified in a signal definition
2524 are always driven by the FTDI.
2526 If @option{-alias} or @option{-nalias} is used, the signal is created
2527 identical (or with data inverted) to an already specified signal
2528 @var{name}.
2529 @end deffn
2531 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2532 Set a previously defined signal to the specified level.
2533 @itemize @minus
2534 @item @option{0}, drive low
2535 @item @option{1}, drive high
2536 @item @option{z}, set to high-impedance
2537 @end itemize
2538 @end deffn
2540 @deffn {Command} {ftdi_get_signal} name
2541 Get the value of a previously defined signal.
2542 @end deffn
2544 @deffn {Command} {ftdi_tdo_sample_edge} @option{rising}|@option{falling}
2545 Configure TCK edge at which the adapter samples the value of the TDO signal
2547 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2548 peculiar at high JTAG clock speeds. However, FTDI chips offer a possiblity to sample
2549 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2550 stability at higher JTAG clocks.
2551 @itemize @minus
2552 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2553 @item @option{falling}, sample TDO on falling edge of TCK
2554 @end itemize
2555 @end deffn
2557 For example adapter definitions, see the configuration files shipped in the
2558 @file{interface/ftdi} directory.
2560 @end deffn
2562 @deffn {Interface Driver} {ft232r}
2563 This driver is implementing synchronous bitbang mode of an FTDI FT232R
2564 USB UART bridge IC.
2566 List of connections (pin numbers for SSOP):
2567 @itemize @minus
2568 @item RXD(5) - TDI
2569 @item TXD(1) - TCK
2570 @item RTS(3) - TDO
2571 @item CTS(11) - TMS
2572 @item DTR(2) - TRST
2573 @item DCD(10) - SRST
2574 @end itemize
2576 These interfaces have several commands, used to configure the driver
2577 before initializing the JTAG scan chain:
2579 @deffn {Config Command} {ft232r_vid_pid} @var{vid} @var{pid}
2580 The vendor ID and product ID of the adapter. If not specified, default
2581 0x0403:0x6001 is used.
2582 @end deffn
2584 @deffn {Config Command} {ft232r_serial_desc} @var{serial}
2585 Specifies the @var{serial} of the adapter to use, in case the
2586 vendor provides unique IDs and more than one adapter is connected to
2587 the host. If not specified, serial numbers are not considered.
2588 @end deffn
2590 @end deffn
2592 @deffn {Interface Driver} {remote_bitbang}
2593 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2594 with a remote process and sends ASCII encoded bitbang requests to that process
2595 instead of directly driving JTAG.
2597 The remote_bitbang driver is useful for debugging software running on
2598 processors which are being simulated.
2600 @deffn {Config Command} {remote_bitbang_port} number
2601 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2602 sockets instead of TCP.
2603 @end deffn
2605 @deffn {Config Command} {remote_bitbang_host} hostname
2606 Specifies the hostname of the remote process to connect to using TCP, or the
2607 name of the UNIX socket to use if remote_bitbang_port is 0.
2608 @end deffn
2610 For example, to connect remotely via TCP to the host foobar you might have
2611 something like:
2613 @example
2614 interface remote_bitbang
2615 remote_bitbang_port 3335
2616 remote_bitbang_host foobar
2617 @end example
2619 To connect to another process running locally via UNIX sockets with socket
2620 named mysocket:
2622 @example
2623 interface remote_bitbang
2624 remote_bitbang_port 0
2625 remote_bitbang_host mysocket
2626 @end example
2627 @end deffn
2629 @deffn {Interface Driver} {usb_blaster}
2630 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2631 for FTDI chips. These interfaces have several commands, used to
2632 configure the driver before initializing the JTAG scan chain:
2634 @deffn {Config Command} {usb_blaster_device_desc} description
2635 Provides the USB device description (the @emph{iProduct string})
2636 of the FTDI FT245 device. If not
2637 specified, the FTDI default value is used. This setting is only valid
2638 if compiled with FTD2XX support.
2639 @end deffn
2641 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2642 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2643 default values are used.
2644 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2645 Altera USB-Blaster (default):
2646 @example
2647 usb_blaster_vid_pid 0x09FB 0x6001
2648 @end example
2649 The following VID/PID is for Kolja Waschk's USB JTAG:
2650 @example
2651 usb_blaster_vid_pid 0x16C0 0x06AD
2652 @end example
2653 @end deffn
2655 @deffn {Command} {usb_blaster_pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2656 Sets the state or function of the unused GPIO pins on USB-Blasters
2657 (pins 6 and 8 on the female JTAG header). These pins can be used as
2658 SRST and/or TRST provided the appropriate connections are made on the
2659 target board.
2661 For example, to use pin 6 as SRST:
2662 @example
2663 usb_blaster_pin pin6 s
2664 reset_config srst_only
2665 @end example
2666 @end deffn
2668 @deffn {Command} {usb_blaster_lowlevel_driver} (@option{ftdi}|@option{ublast2})
2669 Chooses the low level access method for the adapter. If not specified,
2670 @option{ftdi} is selected unless it wasn't enabled during the
2671 configure stage. USB-Blaster II needs @option{ublast2}.
2672 @end deffn
2674 @deffn {Command} {usb_blaster_firmware} @var{path}
2675 This command specifies @var{path} to access USB-Blaster II firmware
2676 image. To be used with USB-Blaster II only.
2677 @end deffn
2679 @end deffn
2681 @deffn {Interface Driver} {gw16012}
2682 Gateworks GW16012 JTAG programmer.
2683 This has one driver-specific command:
2685 @deffn {Config Command} {parport_port} [port_number]
2686 Display either the address of the I/O port
2687 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2688 If a parameter is provided, first switch to use that port.
2689 This is a write-once setting.
2690 @end deffn
2691 @end deffn
2693 @deffn {Interface Driver} {jlink}
2694 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2695 transports.
2697 @quotation Compatibility Note
2698 SEGGER released many firmware versions for the many harware versions they
2699 produced. OpenOCD was extensively tested and intended to run on all of them,
2700 but some combinations were reported as incompatible. As a general
2701 recommendation, it is advisable to use the latest firmware version
2702 available for each hardware version. However the current V8 is a moving
2703 target, and SEGGER firmware versions released after the OpenOCD was
2704 released may not be compatible. In such cases it is recommended to
2705 revert to the last known functional version. For 0.5.0, this is from
2706 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2707 version is from "May 3 2012 18:36:22", packed with 4.46f.
2708 @end quotation
2710 @deffn {Command} {jlink hwstatus}
2711 Display various hardware related information, for example target voltage and pin
2712 states.
2713 @end deffn
2714 @deffn {Command} {jlink freemem}
2715 Display free device internal memory.
2716 @end deffn
2717 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2718 Set the JTAG command version to be used. Without argument, show the actual JTAG
2719 command version.
2720 @end deffn
2721 @deffn {Command} {jlink config}
2722 Display the device configuration.
2723 @end deffn
2724 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2725 Set the target power state on JTAG-pin 19. Without argument, show the target
2726 power state.
2727 @end deffn
2728 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2729 Set the MAC address of the device. Without argument, show the MAC address.
2730 @end deffn
2731 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2732 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2733 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2734 IP configuration.
2735 @end deffn
2736 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2737 Set the USB address of the device. This will also change the USB Product ID
2738 (PID) of the device. Without argument, show the USB address.
2739 @end deffn
2740 @deffn {Command} {jlink config reset}
2741 Reset the current configuration.
2742 @end deffn
2743 @deffn {Command} {jlink config write}
2744 Write the current configuration to the internal persistent storage.
2745 @end deffn
2746 @deffn {Command} {jlink emucom write <channel> <data>}
2747 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2748 pairs.
2750 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2751 the EMUCOM channel 0x10:
2752 @example
2753 > jlink emucom write 0x10 aa0b23
2754 @end example
2755 @end deffn
2756 @deffn {Command} {jlink emucom read <channel> <length>}
2757 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2758 pairs.
2760 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2761 @example
2762 > jlink emucom read 0x0 4
2763 77a90000
2764 @end example
2765 @end deffn
2766 @deffn {Config} {jlink usb} <@option{0} to @option{3}>
2767 Set the USB address of the interface, in case more than one adapter is connected
2768 to the host. If not specified, USB addresses are not considered. Device
2769 selection via USB address is deprecated and the serial number should be used
2770 instead.
2772 As a configuration command, it can be used only before 'init'.
2773 @end deffn
2774 @deffn {Config} {jlink serial} <serial number>
2775 Set the serial number of the interface, in case more than one adapter is
2776 connected to the host. If not specified, serial numbers are not considered.
2778 As a configuration command, it can be used only before 'init'.
2779 @end deffn
2780 @end deffn
2782 @deffn {Interface Driver} {kitprog}
2783 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2784 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2785 families, but it is possible to use it with some other devices. If you are using
2786 this adapter with a PSoC or a PRoC, you may need to add
2787 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2788 configuration script.
2790 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2791 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2792 be used with this driver, and must either be used with the cmsis-dap driver or
2793 switched back to KitProg mode. See the Cypress KitProg User Guide for
2794 instructions on how to switch KitProg modes.
2796 Known limitations:
2797 @itemize @bullet
2798 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2799 and 2.7 MHz.
2800 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2801 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2802 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2803 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2804 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2805 SWD sequence must be sent after every target reset in order to re-establish
2806 communications with the target.
2807 @item Due in part to the limitation above, KitProg devices with firmware below
2808 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
2809 communicate with PSoC 5LP devices. This is because, assuming debug is not
2810 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
2811 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
2812 could only be sent with an acquisition sequence.
2813 @end itemize
2815 @deffn {Config Command} {kitprog_init_acquire_psoc}
2816 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
2817 Please be aware that the acquisition sequence hard-resets the target.
2818 @end deffn
2820 @deffn {Config Command} {kitprog_serial} serial
2821 Select a KitProg device by its @var{serial}. If left unspecified, the first
2822 device detected by OpenOCD will be used.
2823 @end deffn
2825 @deffn {Command} {kitprog acquire_psoc}
2826 Run a PSoC acquisition sequence immediately. Typically, this should not be used
2827 outside of the target-specific configuration scripts since it hard-resets the
2828 target as a side-effect.
2829 This is necessary for "reset halt" on some PSoC 4 series devices.
2830 @end deffn
2832 @deffn {Command} {kitprog info}
2833 Display various adapter information, such as the hardware version, firmware
2834 version, and target voltage.
2835 @end deffn
2836 @end deffn
2838 @deffn {Interface Driver} {parport}
2839 Supports PC parallel port bit-banging cables:
2840 Wigglers, PLD download cable, and more.
2841 These interfaces have several commands, used to configure the driver
2842 before initializing the JTAG scan chain:
2844 @deffn {Config Command} {parport_cable} name
2845 Set the layout of the parallel port cable used to connect to the target.
2846 This is a write-once setting.
2847 Currently valid cable @var{name} values include:
2849 @itemize @minus
2850 @item @b{altium} Altium Universal JTAG cable.
2851 @item @b{arm-jtag} Same as original wiggler except SRST and
2852 TRST connections reversed and TRST is also inverted.
2853 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2854 in configuration mode. This is only used to
2855 program the Chameleon itself, not a connected target.
2856 @item @b{dlc5} The Xilinx Parallel cable III.
2857 @item @b{flashlink} The ST Parallel cable.
2858 @item @b{lattice} Lattice ispDOWNLOAD Cable
2859 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2860 some versions of
2861 Amontec's Chameleon Programmer. The new version available from
2862 the website uses the original Wiggler layout ('@var{wiggler}')
2863 @item @b{triton} The parallel port adapter found on the
2864 ``Karo Triton 1 Development Board''.
2865 This is also the layout used by the HollyGates design
2866 (see @uref{}).
2867 @item @b{wiggler} The original Wiggler layout, also supported by
2868 several clones, such as the Olimex ARM-JTAG
2869 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2870 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2871 @end itemize
2872 @end deffn
2874 @deffn {Config Command} {parport_port} [port_number]
2875 Display either the address of the I/O port
2876 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2877 If a parameter is provided, first switch to use that port.
2878 This is a write-once setting.
2880 When using PPDEV to access the parallel port, use the number of the parallel port:
2881 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2882 you may encounter a problem.
2883 @end deffn
2885 @deffn Command {parport_toggling_time} [nanoseconds]
2886 Displays how many nanoseconds the hardware needs to toggle TCK;
2887 the parport driver uses this value to obey the
2888 @command{adapter_khz} configuration.
2889 When the optional @var{nanoseconds} parameter is given,
2890 that setting is changed before displaying the current value.
2892 The default setting should work reasonably well on commodity PC hardware.
2893 However, you may want to calibrate for your specific hardware.
2894 @quotation Tip
2895 To measure the toggling time with a logic analyzer or a digital storage
2896 oscilloscope, follow the procedure below:
2897 @example
2898 > parport_toggling_time 1000
2899 > adapter_khz 500
2900 @end example
2901 This sets the maximum JTAG clock speed of the hardware, but
2902 the actual speed probably deviates from the requested 500 kHz.
2903 Now, measure the time between the two closest spaced TCK transitions.
2904 You can use @command{runtest 1000} or something similar to generate a
2905 large set of samples.
2906 Update the setting to match your measurement:
2907 @example
2908 > parport_toggling_time <measured nanoseconds>
2909 @end example
2910 Now the clock speed will be a better match for @command{adapter_khz rate}
2911 commands given in OpenOCD scripts and event handlers.
2913 You can do something similar with many digital multimeters, but note
2914 that you'll probably need to run the clock continuously for several
2915 seconds before it decides what clock rate to show. Adjust the
2916 toggling time up or down until the measured clock rate is a good
2917 match for the adapter_khz rate you specified; be conservative.
2918 @end quotation
2919 @end deffn
2921 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2922 This will configure the parallel driver to write a known
2923 cable-specific value to the parallel interface on exiting OpenOCD.
2924 @end deffn
2926 For example, the interface configuration file for a
2927 classic ``Wiggler'' cable on LPT2 might look something like this:
2929 @example
2930 interface parport
2931 parport_port 0x278
2932 parport_cable wiggler
2933 @end example
2934 @end deffn
2936 @deffn {Interface Driver} {presto}
2937 ASIX PRESTO USB JTAG programmer.
2938 @deffn {Config Command} {presto_serial} serial_string
2939 Configures the USB serial number of the Presto device to use.
2940 @end deffn
2941 @end deffn
2943 @deffn {Interface Driver} {rlink}
2944 Raisonance RLink USB adapter
2945 @end deffn
2947 @deffn {Interface Driver} {usbprog}
2948 usbprog is a freely programmable USB adapter.
2949 @end deffn
2951 @deffn {Interface Driver} {vsllink}
2952 vsllink is part of Versaloon which is a versatile USB programmer.
2954 @quotation Note
2955 This defines quite a few driver-specific commands,
2956 which are not currently documented here.
2957 @end quotation
2958 @end deffn
2960 @anchor{hla_interface}
2961 @deffn {Interface Driver} {hla}
2962 This is a driver that supports multiple High Level Adapters.
2963 This type of adapter does not expose some of the lower level api's
2964 that OpenOCD would normally use to access the target.
2966 Currently supported adapters include the ST STLINK and TI ICDI.
2967 STLINK firmware version >= V2.J21.S4 recommended due to issues with earlier
2968 versions of firmware where serial number is reset after first use. Suggest
2969 using ST firmware update utility to upgrade STLINK firmware even if current
2970 version reported is V2.J21.S4.
2972 @deffn {Config Command} {hla_device_desc} description
2973 Currently Not Supported.
2974 @end deffn
2976 @deffn {Config Command} {hla_serial} serial
2977 Specifies the serial number of the adapter.
2978 @end deffn
2980 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
2981 Specifies the adapter layout to use.
2982 @end deffn
2984 @deffn {Config Command} {hla_vid_pid} [vid pid]+
2985 Pairs of vendor IDs and product IDs of the device.
2986 @end deffn
2988 @deffn {Command} {hla_command} command
2989 Execute a custom adapter-specific command. The @var{command} string is
2990 passed as is to the underlying adapter layout handler.
2991 @end deffn
2992 @end deffn
2994 @deffn {Interface Driver} {opendous}
2995 opendous-jtag is a freely programmable USB adapter.
2996 @end deffn
2998 @deffn {Interface Driver} {ulink}
2999 This is the Keil ULINK v1 JTAG debugger.
3000 @end deffn
3002 @deffn {Interface Driver} {ZY1000}
3003 This is the Zylin ZY1000 JTAG debugger.
3004 @end deffn
3006 @quotation Note
3007 This defines some driver-specific commands,
3008 which are not currently documented here.
3009 @end quotation
3011 @deffn Command power [@option{on}|@option{off}]
3012 Turn power switch to target on/off.
3013 No arguments: print status.
3014 @end deffn
3016 @deffn {Interface Driver} {bcm2835gpio}
3017 This SoC is present in Raspberry Pi which is a cheap single-board computer
3018 exposing some GPIOs on its expansion header.
3020 The driver accesses memory-mapped GPIO peripheral registers directly
3021 for maximum performance, but the only possible race condition is for
3022 the pins' modes/muxing (which is highly unlikely), so it should be
3023 able to coexist nicely with both sysfs bitbanging and various
3024 peripherals' kernel drivers. The driver restores the previous
3025 configuration on exit.
3027 See @file{interface/raspberrypi-native.cfg} for a sample config and
3028 pinout.
3030 @end deffn
3032 @deffn {Interface Driver} {imx_gpio}
3033 i.MX SoC is present in many community boards. Wandboard is an example
3034 of the one which is most popular.
3036 This driver is mostly the same as bcm2835gpio.
3038 See @file{interface/imx-native.cfg} for a sample config and
3039 pinout.
3041 @end deffn
3044 @deffn {Interface Driver} {openjtag}
3045 OpenJTAG compatible USB adapter.
3046 This defines some driver-specific commands:
3048 @deffn {Config Command} {openjtag_variant} variant
3049 Specifies the variant of the OpenJTAG adapter (see @uref{}).
3050 Currently valid @var{variant} values include:
3052 @itemize @minus
3053 @item @b{standard} Standard variant (default).
3054 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3055 (see @uref{}).
3056 @end itemize
3057 @end deffn
3059 @deffn {Config Command} {openjtag_device_desc} string
3060 The USB device description string of the adapter.
3061 This value is only used with the standard variant.
3062 @end deffn
3063 @end deffn
3065 @section Transport Configuration
3066 @cindex Transport
3067 As noted earlier, depending on the version of OpenOCD you use,
3068 and the debug adapter you are using,
3069 several transports may be available to
3070 communicate with debug targets (or perhaps to program flash memory).
3071 @deffn Command {transport list}
3072 displays the names of the transports supported by this
3073 version of OpenOCD.
3074 @end deffn
3076 @deffn Command {transport select} @option{transport_name}
3077 Select which of the supported transports to use in this OpenOCD session.
3079 When invoked with @option{transport_name}, attempts to select the named
3080 transport. The transport must be supported by the debug adapter
3081 hardware and by the version of OpenOCD you are using (including the
3082 adapter's driver).
3084 If no transport has been selected and no @option{transport_name} is
3085 provided, @command{transport select} auto-selects the first transport
3086 supported by the debug adapter.
3088 @command{transport select} always returns the name of the session's selected
3089 transport, if any.
3090 @end deffn
3092 @subsection JTAG Transport
3093 @cindex JTAG
3094 JTAG is the original transport supported by OpenOCD, and most
3095 of the OpenOCD commands support it.
3096 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3097 each of which must be explicitly declared.
3098 JTAG supports both debugging and boundary scan testing.
3099 Flash programming support is built on top of debug support.
3101 JTAG transport is selected with the command @command{transport select
3102 jtag}. Unless your adapter uses @ref{hla_interface,the hla interface
3103 driver}, in which case the command is @command{transport select
3104 hla_jtag}.
3106 @subsection SWD Transport
3107 @cindex SWD
3108 @cindex Serial Wire Debug
3109 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3110 Debug Access Point (DAP, which must be explicitly declared.
3111 (SWD uses fewer signal wires than JTAG.)
3112 SWD is debug-oriented, and does not support boundary scan testing.
3113 Flash programming support is built on top of debug support.
3114 (Some processors support both JTAG and SWD.)
3116 SWD transport is selected with the command @command{transport select
3117 swd}. Unless your adapter uses @ref{hla_interface,the hla interface
3118 driver}, in which case the command is @command{transport select
3119 hla_swd}.
3121 @deffn Command {swd newdap} ...
3122 Declares a single DAP which uses SWD transport.
3123 Parameters are currently the same as "jtag newtap" but this is
3124 expected to change.
3125 @end deffn
3126 @deffn Command {swd wcr trn prescale}
3127 Updates TRN (turnaraound delay) and prescaling.fields of the
3128 Wire Control Register (WCR).
3129 No parameters: displays current settings.
3130 @end deffn
3132 @subsection SPI Transport
3133 @cindex SPI
3134 @cindex Serial Peripheral Interface
3135 The Serial Peripheral Interface (SPI) is a general purpose transport
3136 which uses four wire signaling. Some processors use it as part of a
3137 solution for flash programming.
3139 @anchor{jtagspeed}
3140 @section JTAG Speed
3141 JTAG clock setup is part of system setup.
3142 It @emph{does not belong with interface setup} since any interface
3143 only knows a few of the constraints for the JTAG clock speed.
3144 Sometimes the JTAG speed is
3145 changed during the target initialization process: (1) slow at
3146 reset, (2) program the CPU clocks, (3) run fast.
3147 Both the "slow" and "fast" clock rates are functions of the
3148 oscillators used, the chip, the board design, and sometimes
3149 power management software that may be active.
3151 The speed used during reset, and the scan chain verification which
3152 follows reset, can be adjusted using a @code{reset-start}
3153 target event handler.
3154 It can then be reconfigured to a faster speed by a
3155 @code{reset-init} target event handler after it reprograms those
3156 CPU clocks, or manually (if something else, such as a boot loader,
3157 sets up those clocks).
3158 @xref{targetevents,,Target Events}.
3159 When the initial low JTAG speed is a chip characteristic, perhaps
3160 because of a required oscillator speed, provide such a handler
3161 in the target config file.
3162 When that speed is a function of a board-specific characteristic
3163 such as which speed oscillator is used, it belongs in the board
3164 config file instead.
3165 In both cases it's safest to also set the initial JTAG clock rate
3166 to that same slow speed, so that OpenOCD never starts up using a
3167 clock speed that's faster than the scan chain can support.
3169 @example
3170 jtag_rclk 3000
3171 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3172 @end example
3174 If your system supports adaptive clocking (RTCK), configuring
3175 JTAG to use that is probably the most robust approach.
3176 However, it introduces delays to synchronize clocks; so it
3177 may not be the fastest solution.
3179 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3180 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3181 which support adaptive clocking.
3183 @deffn {Command} adapter_khz max_speed_kHz
3184 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3185 JTAG interfaces usually support a limited number of
3186 speeds. The speed actually used won't be faster
3187 than the speed specified.
3189 Chip data sheets generally include a top JTAG clock rate.
3190 The actual rate is often a function of a CPU core clock,
3191 and is normally less than that peak rate.
3192 For example, most ARM cores accept at most one sixth of the CPU clock.
3194 Speed 0 (khz) selects RTCK method.
3195 @xref{faqrtck,,FAQ RTCK}.
3196 If your system uses RTCK, you won't need to change the
3197 JTAG clocking after setup.
3198 Not all interfaces, boards, or targets support ``rtck''.
3199 If the interface device can not
3200 support it, an error is returned when you try to use RTCK.
3201 @end deffn
3203 @defun jtag_rclk fallback_speed_kHz
3204 @cindex adaptive clocking
3205 @cindex RTCK
3206 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3207 If that fails (maybe the interface, board, or target doesn't
3208 support it), falls back to the specified frequency.
3209 @example
3210 # Fall back to 3mhz if RTCK is not supported
3211 jtag_rclk 3000
3212 @end example
3213 @end defun
3215 @node Reset Configuration
3216 @chapter Reset Configuration
3217 @cindex Reset Configuration
3219 Every system configuration may require a different reset
3220 configuration. This can also be quite confusing.
3221 Resets also interact with @var{reset-init} event handlers,
3222 which do things like setting up clocks and DRAM, and
3223 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3224 They can also interact with JTAG routers.
3225 Please see the various board files for examples.
3227 @quotation Note
3228 To maintainers and integrators:
3229 Reset configuration touches several things at once.
3230 Normally the board configuration file
3231 should define it and assume that the JTAG adapter supports
3232 everything that's wired up to the board's JTAG connector.
3234 However, the target configuration file could also make note
3235 of something the silicon vendor has done inside the chip,
3236 which will be true for most (or all) boards using that chip.
3237 And when the JTAG adapter doesn't support everything, the
3238 user configuration file will need to override parts of
3239 the reset configuration provided by other files.
3240 @end quotation
3242 @section Types of Reset
3244 There are many kinds of reset possible through JTAG, but
3245 they may not all work with a given board and adapter.
3246 That's part of why reset configuration can be error prone.
3248 @itemize @bullet
3249 @item
3250 @emph{System Reset} ... the @emph{SRST} hardware signal
3251 resets all chips connected to the JTAG adapter, such as processors,
3252 power management chips, and I/O controllers. Normally resets triggered
3253 with this signal behave exactly like pressing a RESET button.
3254 @item
3255 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3256 just the TAP controllers connected to the JTAG adapter.
3257 Such resets should not be visible to the rest of the system; resetting a
3258 device's TAP controller just puts that controller into a known state.
3259 @item
3260 @emph{Emulation Reset} ... many devices can be reset through JTAG
3261 commands. These resets are often distinguishable from system
3262 resets, either explicitly (a "reset reason" register says so)
3263 or implicitly (not all parts of the chip get reset).
3264 @item
3265 @emph{Other Resets} ... system-on-chip devices often support
3266 several other types of reset.
3267 You may need to arrange that a watchdog timer stops
3268 while debugging, preventing a watchdog reset.
3269 There may be individual module resets.
3270 @end itemize
3272 In the best case, OpenOCD can hold SRST, then reset
3273 the TAPs via TRST and send commands through JTAG to halt the
3274 CPU at the reset vector before the 1st instruction is executed.
3275 Then when it finally releases the SRST signal, the system is
3276 halted under debugger control before any code has executed.
3277 This is the behavior required to support the @command{reset halt}
3278 and @command{reset init} commands; after @command{reset init} a
3279 board-specific script might do things like setting up DRAM.
3280 (@xref{resetcommand,,Reset Command}.)
3282 @anchor{srstandtrstissues}
3283 @section SRST and TRST Issues
3285 Because SRST and TRST are hardware signals, they can have a
3286 variety of system-specific constraints. Some of the most
3287 common issues are:
3289 @itemize @bullet
3291 @item @emph{Signal not available} ... Some boards don't wire
3292 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3293 support such signals even if they are wired up.
3294 Use the @command{reset_config} @var{signals} options to say
3295 when either of those signals is not connected.
3296 When SRST is not available, your code might not be able to rely
3297 on controllers having been fully reset during code startup.
3298 Missing TRST is not a problem, since JTAG-level resets can
3299 be triggered using with TMS signaling.
3301 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3302 adapter will connect SRST to TRST, instead of keeping them separate.
3303 Use the @command{reset_config} @var{combination} options to say
3304 when those signals aren't properly independent.
3306 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3307 delay circuit, reset supervisor, or on-chip features can extend
3308 the effect of a JTAG adapter's reset for some time after the adapter
3309 stops issuing the reset. For example, there may be chip or board
3310 requirements that all reset pulses last for at least a
3311 certain amount of time; and reset buttons commonly have
3312 hardware debouncing.
3313 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3314 commands to say when extra delays are needed.
3316 @item @emph{Drive type} ... Reset lines often have a pullup
3317 resistor, letting the JTAG interface treat them as open-drain
3318 signals. But that's not a requirement, so the adapter may need
3319 to use push/pull output drivers.
3320 Also, with weak pullups it may be advisable to drive
3321 signals to both levels (push/pull) to minimize rise times.
3322 Use the @command{reset_config} @var{trst_type} and
3323 @var{srst_type} parameters to say how to drive reset signals.
3325 @item @emph{Special initialization} ... Targets sometimes need
3326 special JTAG initialization sequences to handle chip-specific
3327 issues (not limited to errata).
3328 For example, certain JTAG commands might need to be issued while
3329 the system as a whole is in a reset state (SRST active)
3330 but the JTAG scan chain is usable (TRST inactive).
3331 Many systems treat combined assertion of SRST and TRST as a
3332 trigger for a harder reset than SRST alone.
3333 Such custom reset handling is discussed later in this chapter.
3334 @end itemize
3336 There can also be other issues.
3337 Some devices don't fully conform to the JTAG specifications.
3338 Trivial system-specific differences are common, such as
3339 SRST and TRST using slightly different names.
3340 There are also vendors who distribute key JTAG documentation for
3341 their chips only to developers who have signed a Non-Disclosure
3342 Agreement (NDA).
3344 Sometimes there are chip-specific extensions like a requirement to use
3345 the normally-optional TRST signal (precluding use of JTAG adapters which
3346 don't pass TRST through), or needing extra steps to complete a TAP reset.
3348 In short, SRST and especially TRST handling may be very finicky,
3349 needing to cope with both architecture and board specific constraints.
3351 @section Commands for Handling Resets
3353 @deffn {Command} adapter_nsrst_assert_width milliseconds
3354 Minimum amount of time (in milliseconds) OpenOCD should wait
3355 after asserting nSRST (active-low system reset) before
3356 allowing it to be deasserted.
3357 @end deffn
3359 @deffn {Command} adapter_nsrst_delay milliseconds
3360 How long (in milliseconds) OpenOCD should wait after deasserting
3361 nSRST (active-low system reset) before starting new JTAG operations.
3362 When a board has a reset button connected to SRST line it will
3363 probably have hardware debouncing, implying you should use this.
3364 @end deffn
3366 @deffn {Command} jtag_ntrst_assert_width milliseconds
3367 Minimum amount of time (in milliseconds) OpenOCD should wait
3368 after asserting nTRST (active-low JTAG TAP reset) before
3369 allowing it to be deasserted.
3370 @end deffn
3372 @deffn {Command} jtag_ntrst_delay milliseconds
3373 How long (in milliseconds) OpenOCD should wait after deasserting
3374 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3375 @end deffn
3377 @deffn {Command} reset_config mode_flag ...
3378 This command displays or modifies the reset configuration
3379 of your combination of JTAG board and target in target
3380 configuration scripts.
3382 Information earlier in this section describes the kind of problems
3383 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3384 As a rule this command belongs only in board config files,
3385 describing issues like @emph{board doesn't connect TRST};
3386 or in user config files, addressing limitations derived
3387 from a particular combination of interface and board.
3388 (An unlikely example would be using a TRST-only adapter
3389 with a board that only wires up SRST.)
3391 The @var{mode_flag} options can be specified in any order, but only one
3392 of each type -- @var{signals}, @var{combination}, @var{gates},
3393 @var{trst_type}, @var{srst_type} and @var{connect_type}
3394 -- may be specified at a time.
3395 If you don't provide a new value for a given type, its previous
3396 value (perhaps the default) is unchanged.
3397 For example, this means that you don't need to say anything at all about
3398 TRST just to declare that if the JTAG adapter should want to drive SRST,
3399 it must explicitly be driven high (@option{srst_push_pull}).
3401 @itemize
3402 @item
3403 @var{signals} can specify which of the reset signals are connected.
3404 For example, If the JTAG interface provides SRST, but the board doesn't
3405 connect that signal properly, then OpenOCD can't use it.
3406 Possible values are @option{none} (the default), @option{trst_only},
3407 @option{srst_only} and @option{trst_and_srst}.
3409 @quotation Tip
3410 If your board provides SRST and/or TRST through the JTAG connector,
3411 you must declare that so those signals can be used.
3412 @end quotation
3414 @item
3415 The @var{combination} is an optional value specifying broken reset
3416 signal implementations.
3417 The default behaviour if no option given is @option{separate},
3418 indicating everything behaves normally.
3419 @option{srst_pulls_trst} states that the
3420 test logic is reset together with the reset of the system (e.g. NXP
3421 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3422 the system is reset together with the test logic (only hypothetical, I
3423 haven't seen hardware with such a bug, and can be worked around).
3424 @option{combined} implies both @option{srst_pulls_trst} and
3425 @option{trst_pulls_srst}.
3427 @item
3428 The @var{gates} tokens control flags that describe some cases where
3429 JTAG may be unvailable during reset.
3430 @option{srst_gates_jtag} (default)
3431 indicates that asserting SRST gates the
3432 JTAG clock. This means that no communication can happen on JTAG
3433 while SRST is asserted.
3434 Its converse is @option{srst_nogate}, indicating that JTAG commands
3435 can safely be issued while SRST is active.
3437 @item
3438 The @var{connect_type} tokens control flags that describe some cases where
3439 SRST is asserted while connecting to the target. @option{srst_nogate}
3440 is required to use this option.
3441 @option{connect_deassert_srst} (default)
3442 indicates that SRST will not be asserted while connecting to the target.
3443 Its converse is @option{connect_assert_srst}, indicating that SRST will
3444 be asserted before any target connection.
3445 Only some targets support this feature, STM32 and STR9 are examples.
3446 This feature is useful if you are unable to connect to your target due
3447 to incorrect options byte config or illegal program execution.
3448 @end itemize
3450 The optional @var{trst_type} and @var{srst_type} parameters allow the
3451 driver mode of each reset line to be specified. These values only affect
3452 JTAG interfaces with support for different driver modes, like the Amontec
3453 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3454 relevant signal (TRST or SRST) is not connected.
3456 @itemize
3457 @item
3458 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3459 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3460 Most boards connect this signal to a pulldown, so the JTAG TAPs
3461 never leave reset unless they are hooked up to a JTAG adapter.
3463 @item
3464 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3465 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3466 Most boards connect this signal to a pullup, and allow the
3467 signal to be pulled low by various events including system
3468 powerup and pressing a reset button.
3469 @end itemize
3470 @end deffn
3472 @section Custom Reset Handling
3473 @cindex events
3475 OpenOCD has several ways to help support the various reset
3476 mechanisms provided by chip and board vendors.
3477 The commands shown in the previous section give standard parameters.
3478 There are also @emph{event handlers} associated with TAPs or Targets.
3479 Those handlers are Tcl procedures you can provide, which are invoked
3480 at particular points in the reset sequence.
3482 @emph{When SRST is not an option} you must set
3483 up a @code{reset-assert} event handler for your target.
3484 For example, some JTAG adapters don't include the SRST signal;
3485 and some boards have multiple targets, and you won't always
3486 want to reset everything at once.
3488 After configuring those mechanisms, you might still
3489 find your board doesn't start up or reset correctly.
3490 For example, maybe it needs a slightly different sequence
3491 of SRST and/or TRST manipulations, because of quirks that
3492 the @command{reset_config} mechanism doesn't address;
3493 or asserting both might trigger a stronger reset, which
3494 needs special attention.
3496 Experiment with lower level operations, such as @command{jtag_reset}
3497 and the @command{jtag arp_*} operations shown here,
3498 to find a sequence of operations that works.
3499 @xref{JTAG Commands}.
3500 When you find a working sequence, it can be used to override
3501 @command{jtag_init}, which fires during OpenOCD startup
3502 (@pxref{configurationstage,,Configuration Stage});
3503 or @command{init_reset}, which fires during reset processing.
3505 You might also want to provide some project-specific reset
3506 schemes. For example, on a multi-target board the standard
3507 @command{reset} command would reset all targets, but you
3508 may need the ability to reset only one target at time and
3509 thus want to avoid using the board-wide SRST signal.
3511 @deffn {Overridable Procedure} init_reset mode
3512 This is invoked near the beginning of the @command{reset} command,
3513 usually to provide as much of a cold (power-up) reset as practical.
3514 By default it is also invoked from @command{jtag_init} if
3515 the scan chain does not respond to pure JTAG operations.
3516 The @var{mode} parameter is the parameter given to the
3517 low level reset command (@option{halt},
3518 @option{init}, or @option{run}), @option{setup},
3519 or potentially some other value.
3521 The default implementation just invokes @command{jtag arp_init-reset}.
3522 Replacements will normally build on low level JTAG
3523 operations such as @command{jtag_reset}.
3524 Operations here must not address individual TAPs
3525 (or their associated targets)
3526 until the JTAG scan chain has first been verified to work.
3528 Implementations must have verified the JTAG scan chain before
3529 they return.
3530 This is done by calling @command{jtag arp_init}
3531 (or @command{jtag arp_init-reset}).
3532 @end deffn
3534 @deffn Command {jtag arp_init}
3535 This validates the scan chain using just the four
3536 standard JTAG signals (TMS, TCK, TDI, TDO).
3537 It starts by issuing a JTAG-only reset.
3538 Then it performs checks to verify that the scan chain configuration
3539 matches the TAPs it can observe.
3540 Those checks include checking IDCODE values for each active TAP,
3541 and verifying the length of their instruction registers using
3542 TAP @code{-ircapture} and @code{-irmask} values.
3543 If these tests all pass, TAP @code{setup} events are
3544 issued to all TAPs with handlers for that event.
3545 @end deffn
3547 @deffn Command {jtag arp_init-reset}
3548 This uses TRST and SRST to try resetting
3549 everything on the JTAG scan chain
3550 (and anything else connected to SRST).
3551 It then invokes the logic of @command{jtag arp_init}.
3552 @end deffn
3555 @node TAP Declaration
3556 @chapter TAP Declaration
3557 @cindex TAP declaration
3558 @cindex TAP configuration
3560 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3561 TAPs serve many roles, including:
3563 @itemize @bullet
3564 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3565 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3566 Others do it indirectly, making a CPU do it.
3567 @item @b{Program Download} Using the same CPU support GDB uses,
3568 you can initialize a DRAM controller, download code to DRAM, and then
3569 start running that code.
3570 @item @b{Boundary Scan} Most chips support boundary scan, which
3571 helps test for board assembly problems like solder bridges
3572 and missing connections.
3573 @end itemize
3575 OpenOCD must know about the active TAPs on your board(s).
3576 Setting up the TAPs is the core task of your configuration files.
3577 Once those TAPs are set up, you can pass their names to code
3578 which sets up CPUs and exports them as GDB targets,
3579 probes flash memory, performs low-level JTAG operations, and more.
3581 @section Scan Chains
3582 @cindex scan chain
3584 TAPs are part of a hardware @dfn{scan chain},
3585 which is a daisy chain of TAPs.
3586 They also need to be added to
3587 OpenOCD's software mirror of that hardware list,
3588 giving each member a name and associating other data with it.
3589 Simple scan chains, with a single TAP, are common in
3590 systems with a single microcontroller or microprocessor.
3591 More complex chips may have several TAPs internally.
3592 Very complex scan chains might have a dozen or more TAPs:
3593 several in one chip, more in the next, and connecting
3594 to other boards with their own chips and TAPs.
3596 You can display the list with the @command{scan_chain} command.
3597 (Don't confuse this with the list displayed by the @command{targets}
3598 command, presented in the next chapter.
3599 That only displays TAPs for CPUs which are configured as
3600 debugging targets.)
3601 Here's what the scan chain might look like for a chip more than one TAP:
3603 @verbatim
3604 TapName Enabled IdCode Expected IrLen IrCap IrMask
3605 -- ------------------ ------- ---------- ---------- ----- ----- ------
3606 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3607 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3608 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3609 @end verbatim
3611 OpenOCD can detect some of that information, but not all
3612 of it. @xref{autoprobing,,Autoprobing}.
3613 Unfortunately, those TAPs can't always be autoconfigured,
3614 because not all devices provide good support for that.
3615 JTAG doesn't require supporting IDCODE instructions, and
3616 chips with JTAG routers may not link TAPs into the chain
3617 until they are told to do so.
3619 The configuration mechanism currently supported by OpenOCD
3620 requires explicit configuration of all TAP devices using
3621 @command{jtag newtap} commands, as detailed later in this chapter.
3622 A command like this would declare one tap and name it @code{chip1.cpu}:
3624 @example
3625 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3626 @end example
3628 Each target configuration file lists the TAPs provided
3629 by a given chip.
3630 Board configuration files combine all the targets on a board,
3631 and so forth.
3632 Note that @emph{the order in which TAPs are declared is very important.}
3633 That declaration order must match the order in the JTAG scan chain,
3634 both inside a single chip and between them.
3635 @xref{faqtaporder,,FAQ TAP Order}.
3637 For example, the ST Microsystems STR912 chip has
3638 three separate TAPs@footnote{See the ST
3639 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3640 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3641 @url{}}.
3642 To configure those taps, @file{target/str912.cfg}
3643 includes commands something like this:
3645 @example
3646 jtag newtap str912 flash ... params ...
3647 jtag newtap str912 cpu ... params ...
3648 jtag newtap str912 bs ... params ...
3649 @end example
3651 Actual config files typically use a variable such as @code{$_CHIPNAME}
3652 instead of literals like @option{str912}, to support more than one chip
3653 of each type. @xref{Config File Guidelines}.
3655 @deffn Command {jtag names}
3656 Returns the names of all current TAPs in the scan chain.
3657 Use @command{jtag cget} or @command{jtag tapisenabled}
3658 to examine attributes and state of each TAP.
3659 @example
3660 foreach t [jtag names] @{
3661 puts [format "TAP: %s\n" $t]
3662 @}
3663 @end example
3664 @end deffn
3666 @deffn Command {scan_chain}
3667 Displays the TAPs in the scan chain configuration,
3668 and their status.
3669 The set of TAPs listed by this command is fixed by
3670 exiting the OpenOCD configuration stage,
3671 but systems with a JTAG router can
3672 enable or disable TAPs dynamically.
3673 @end deffn
3675 @c FIXME! "jtag cget" should be able to return all TAP
3676 @c attributes, like "$target_name cget" does for targets.
3678 @c Probably want "jtag eventlist", and a "tap-reset" event
3679 @c (on entry to RESET state).
3681 @section TAP Names
3682 @cindex dotted name
3684 When TAP objects are declared with @command{jtag newtap},
3685 a @dfn{} is created for the TAP, combining the
3686 name of a module (usually a chip) and a label for the TAP.
3687 For example: @code{xilinx.tap}, @code{str912.flash},
3688 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3689 Many other commands use that to manipulate or
3690 refer to the TAP. For example, CPU configuration uses the
3691 name, as does declaration of NAND or NOR flash banks.
3693 The components of a dotted name should follow ``C'' symbol
3694 name rules: start with an alphabetic character, then numbers
3695 and underscores are OK; while others (including dots!) are not.
3697 @section TAP Declaration Commands
3699 @c shouldn't this be(come) a {Config Command}?
3700 @deffn Command {jtag newtap} chipname tapname configparams...
3701 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3702 and configured according to the various @var{configparams}.
3704 The @var{chipname} is a symbolic name for the chip.
3705 Conventionally target config files use @code{$_CHIPNAME},
3706 defaulting to the model name given by the chip vendor but
3707 overridable.
3709 @cindex TAP naming convention
3710 The @var{tapname} reflects the role of that TAP,
3711 and should follow this convention:
3713 @itemize @bullet
3714 @item @code{bs} -- For boundary scan if this is a separate TAP;
3715 @item @code{cpu} -- The main CPU of the chip, alternatively
3716 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3717 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3718 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3719 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3720 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3721 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3722 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3723 with a single TAP;
3724 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3725 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3726 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3727 a JTAG TAP; that TAP should be named @code{sdma}.
3728 @end itemize
3730 Every TAP requires at least the following @var{configparams}:
3732 @itemize @bullet
3733 @item @code{-irlen} @var{NUMBER}
3734 @*The length in bits of the
3735 instruction register, such as 4 or 5 bits.
3736 @end itemize
3738 A TAP may also provide optional @var{configparams}:
3740 @itemize @bullet
3741 @item @code{-disable} (or @code{-enable})
3742 @*Use the @code{-disable} parameter to flag a TAP which is not
3743 linked into the scan chain after a reset using either TRST
3744 or the JTAG state machine's @sc{reset} state.
3745 You may use @code{-enable} to highlight the default state
3746 (the TAP is linked in).
3747 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3748 @item @code{-expected-id} @var{NUMBER}
3749 @*A non-zero @var{number} represents a 32-bit IDCODE
3750 which you expect to find when the scan chain is examined.
3751 These codes are not required by all JTAG devices.
3752 @emph{Repeat the option} as many times as required if more than one
3753 ID code could appear (for example, multiple versions).
3754 Specify @var{number} as zero to suppress warnings about IDCODE
3755 values that were found but not included in the list.
3757 Provide this value if at all possible, since it lets OpenOCD
3758 tell when the scan chain it sees isn't right. These values
3759 are provided in vendors' chip documentation, usually a technical
3760 reference manual. Sometimes you may need to probe the JTAG
3761 hardware to find these values.
3762 @xref{autoprobing,,Autoprobing}.
3763 @item @code{-ignore-version}
3764 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3765 option. When vendors put out multiple versions of a chip, or use the same
3766 JTAG-level ID for several largely-compatible chips, it may be more practical
3767 to ignore the version field than to update config files to handle all of
3768 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3769 @item @code{-ircapture} @var{NUMBER}
3770 @*The bit pattern loaded by the TAP into the JTAG shift register
3771 on entry to the @sc{ircapture} state, such as 0x01.
3772 JTAG requires the two LSBs of this value to be 01.
3773 By default, @code{-ircapture} and @code{-irmask} are set
3774 up to verify that two-bit value. You may provide
3775 additional bits if you know them, or indicate that
3776 a TAP doesn't conform to the JTAG specification.
3777 @item @code{-irmask} @var{NUMBER}
3778 @*A mask used with @code{-ircapture}
3779 to verify that instruction scans work correctly.
3780 Such scans are not used by OpenOCD except to verify that
3781 there seems to be no problems with JTAG scan chain operations.
3782 @end itemize
3783 @end deffn
3785 @section Other TAP commands
3787 @deffn Command {jtag cget} @option{-event} event_name
3788 @deffnx Command {jtag configure} @option{-event} event_name handler
3789 At this writing this TAP attribute
3790 mechanism is used only for event handling.
3791 (It is not a direct analogue of the @code{cget}/@code{configure}
3792 mechanism for debugger targets.)
3793 See the next section for information about the available events.
3795 The @code{configure} subcommand assigns an event handler,
3796 a TCL string which is evaluated when the event is triggered.
3797 The @code{cget} subcommand returns that handler.
3798 @end deffn
3800 @section TAP Events
3801 @cindex events
3802 @cindex TAP events
3804 OpenOCD includes two event mechanisms.
3805 The one presented here applies to all JTAG TAPs.
3806 The other applies to debugger targets,
3807 which are associated with certain TAPs.
3809 The TAP events currently defined are:
3811 @itemize @bullet
3812 @item @b{post-reset}
3813 @* The TAP has just completed a JTAG reset.
3814 The tap may still be in the JTAG @sc{reset} state.
3815 Handlers for these events might perform initialization sequences
3816 such as issuing TCK cycles, TMS sequences to ensure
3817 exit from the ARM SWD mode, and more.
3819 Because the scan chain has not yet been verified, handlers for these events
3820 @emph{should not issue commands which scan the JTAG IR or DR registers}
3821 of any particular target.
3822 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3823 @item @b{setup}
3824 @* The scan chain has been reset and verified.
3825 This handler may enable TAPs as needed.
3826 @item @b{tap-disable}
3827 @* The TAP needs to be disabled. This handler should
3828 implement @command{jtag tapdisable}
3829 by issuing the relevant JTAG commands.
3830 @item @b{tap-enable}
3831 @* The TAP needs to be enabled. This handler should
3832 implement @command{jtag tapenable}
3833 by issuing the relevant JTAG commands.
3834 @end itemize
3836 If you need some action after each JTAG reset which isn't actually
3837 specific to any TAP (since you can't yet trust the scan chain's
3838 contents to be accurate), you might:
3840 @example
3841 jtag configure CHIP.jrc -event post-reset @{
3842 echo "JTAG Reset done"
3843 ... non-scan jtag operations to be done after reset
3844 @}
3845 @end example
3848 @anchor{enablinganddisablingtaps}
3849 @section Enabling and Disabling TAPs
3850 @cindex JTAG Route Controller
3851 @cindex jrc
3853 In some systems, a @dfn{JTAG Route Controller} (JRC)
3854 is used to enable and/or disable specific JTAG TAPs.
3855 Many ARM-based chips from Texas Instruments include
3856 an ``ICEPick'' module, which is a JRC.
3857 Such chips include DaVinci and OMAP3 processors.
3859 A given TAP may not be visible until the JRC has been
3860 told to link it into the scan chain; and if the JRC
3861 has been told to unlink that TAP, it will no longer
3862 be visible.
3863 Such routers address problems that JTAG ``bypass mode''
3864 ignores, such as:
3866 @itemize
3867 @item The scan chain can only go as fast as its slowest TAP.
3868 @item Having many TAPs slows instruction scans, since all
3869 TAPs receive new instructions.
3870 @item TAPs in the scan chain must be powered up, which wastes
3871 power and prevents debugging some power management mechanisms.
3872 @end itemize
3874 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3875 as implied by the existence of JTAG routers.
3876 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3877 does include a kind of JTAG router functionality.
3879 @c (a) currently the event handlers don't seem to be able to
3880 @c fail in a way that could lead to no-change-of-state.
3882 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3883 shown below, and is implemented using TAP event handlers.
3884 So for example, when defining a TAP for a CPU connected to
3885 a JTAG router, your @file{target.cfg} file
3886 should define TAP event handlers using
3887 code that looks something like this:
3889 @example
3890 jtag configure CHIP.cpu -event tap-enable @{
3891 ... jtag operations using CHIP.jrc
3892 @}
3893 jtag configure CHIP.cpu -event tap-disable @{
3894 ... jtag operations using CHIP.jrc
3895 @}
3896 @end example
3898 Then you might want that CPU's TAP enabled almost all the time:
3900 @example
3901 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3902 @end example
3904 Note how that particular setup event handler declaration
3905 uses quotes to evaluate @code{$CHIP} when the event is configured.
3906 Using brackets @{ @} would cause it to be evaluated later,
3907 at runtime, when it might have a different value.
3909 @deffn Command {jtag tapdisable}
3910 If necessary, disables the tap
3911 by sending it a @option{tap-disable} event.
3912 Returns the string "1" if the tap
3913 specified by @var{} is enabled,
3914 and "0" if it is disabled.
3915 @end deffn
3917 @deffn Command {jtag tapenable}
3918 If necessary, enables the tap
3919 by sending it a @option{tap-enable} event.
3920 Returns the string "1" if the tap
3921 specified by @var{} is enabled,
3922 and "0" if it is disabled.
3923 @end deffn
3925 @deffn Command {jtag tapisenabled}
3926 Returns the string "1" if the tap
3927 specified by @var{} is enabled,
3928 and "0" if it is disabled.
3930 @quotation Note
3931 Humans will find the @command{scan_chain} command more helpful
3932 for querying the state of the JTAG taps.
3933 @end quotation
3934 @end deffn
3936 @anchor{autoprobing}
3937 @section Autoprobing
3938 @cindex autoprobe
3939 @cindex JTAG autoprobe
3941 TAP configuration is the first thing that needs to be done
3942 after interface and reset configuration. Sometimes it's
3943 hard finding out what TAPs exist, or how they are identified.
3944 Vendor documentation is not always easy to find and use.
3946 To help you get past such problems, OpenOCD has a limited
3947 @emph{autoprobing} ability to look at the scan chain, doing
3948 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3949 To use this mechanism, start the OpenOCD server with only data
3950 that configures your JTAG interface, and arranges to come up
3951 with a slow clock (many devices don't support fast JTAG clocks
3952 right when they come out of reset).
3954 For example, your @file{openocd.cfg} file might have:
3956 @example
3957 source [find interface/olimex-arm-usb-tiny-h.cfg]
3958 reset_config trst_and_srst
3959 jtag_rclk 8
3960 @end example
3962 When you start the server without any TAPs configured, it will
3963 attempt to autoconfigure the TAPs. There are two parts to this:
3965 @enumerate
3966 @item @emph{TAP discovery} ...
3967 After a JTAG reset (sometimes a system reset may be needed too),
3968 each TAP's data registers will hold the contents of either the
3969 IDCODE or BYPASS register.
3970 If JTAG communication is working, OpenOCD will see each TAP,
3971 and report what @option{-expected-id} to use with it.
3972 @item @emph{IR Length discovery} ...
3973 Unfortunately JTAG does not provide a reliable way to find out
3974 the value of the @option{-irlen} parameter to use with a TAP
3975 that is discovered.
3976 If OpenOCD can discover the length of a TAP's instruction
3977 register, it will report it.
3978 Otherwise you may need to consult vendor documentation, such
3979 as chip data sheets or BSDL files.
3980 @end enumerate
3982 In many cases your board will have a simple scan chain with just
3983 a single device. Here's what OpenOCD reported with one board
3984 that's a bit more complex:
3986 @example
3987 clock speed 8 kHz
3988 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3989 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3990 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3991 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3992 AUTO auto0.tap - use "... -irlen 4"
3993 AUTO auto1.tap - use "... -irlen 4"
3994 AUTO auto2.tap - use "... -irlen 6"
3995 no gdb ports allocated as no target has been specified
3996 @end example
3998 Given that information, you should be able to either find some existing
3999 config files to use, or create your own. If you create your own, you
4000 would configure from the bottom up: first a @file{target.cfg} file
4001 with these TAPs, any targets associated with them, and any on-chip
4002 resources; then a @file{board.cfg} with off-chip resources, clocking,
4003 and so forth.
4005 @node CPU Configuration
4006 @chapter CPU Configuration
4007 @cindex GDB target
4009 This chapter discusses how to set up GDB debug targets for CPUs.
4010 You can also access these targets without GDB
4011 (@pxref{Architecture and Core Commands},
4012 and @ref{targetstatehandling,,Target State handling}) and
4013 through various kinds of NAND and NOR flash commands.
4014 If you have multiple CPUs you can have multiple such targets.
4016 We'll start by looking at how to examine the targets you have,
4017 then look at how to add one more target and how to configure it.
4019 @section Target List
4020 @cindex target, current
4021 @cindex target, list
4023 All targets that have been set up are part of a list,
4024 where each member has a name.
4025 That name should normally be the same as the TAP name.
4026 You can display the list with the @command{targets}
4027 (plural!) command.
4028 This display often has only one CPU; here's what it might
4029 look like with more than one:
4030 @verbatim
4031 TargetName Type Endian TapName State
4032 -- ------------------ ---------- ------ ------------------ ------------
4033 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4034 1 MyTarget cortex_m little tap-disabled
4035 @end verbatim
4037 One member of that list is the @dfn{current target}, which
4038 is implicitly referenced by many commands.
4039 It's the one marked with a @code{*} near the target name.
4040 In particular, memory addresses often refer to the address
4041 space seen by that current target.
4042 Commands like @command{mdw} (memory display words)
4043 and @command{flash erase_address} (erase NOR flash blocks)
4044 are examples; and there are many more.
4046 Several commands let you examine the list of targets:
4048 @deffn Command {target current}
4049 Returns the name of the current target.
4050 @end deffn
4052 @deffn Command {target names}
4053 Lists the names of all current targets in the list.
4054 @example
4055 foreach t [target names] @{
4056 puts [format "Target: %s\n" $t]
4057 @}
4058 @end example
4059 @end deffn
4061 @c yep, "target list" would have been better.
4062 @c plus maybe "target setdefault".
4064 @deffn Command targets [name]
4065 @emph{Note: the name of this command is plural. Other target
4066 command names are singular.}
4068 With no parameter, this command displays a table of all known
4069 targets in a user friendly form.
4071 With a parameter, this command sets the current target to
4072 the given target with the given @var{name}; this is
4073 only relevant on boards which have more than one target.
4074 @end deffn
4076 @section Target CPU Types
4077 @cindex target type
4078 @cindex CPU type
4080 Each target has a @dfn{CPU type}, as shown in the output of
4081 the @command{targets} command. You need to specify that type
4082 when calling @command{target create}.
4083 The CPU type indicates more than just the instruction set.
4084 It also indicates how that instruction set is implemented,
4085 what kind of debug support it integrates,
4086 whether it has an MMU (and if so, what kind),
4087 what core-specific commands may be available
4088 (@pxref{Architecture and Core Commands}),
4089 and more.
4091 It's easy to see what target types are supported,
4092 since there's a command to list them.
4094 @anchor{targettypes}
4095 @deffn Command {target types}
4096 Lists all supported target types.
4097 At this writing, the supported CPU types are:
4099 @itemize @bullet
4100 @item @code{arm11} -- this is a generation of ARMv6 cores
4101 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4102 @item @code{arm7tdmi} -- this is an ARMv4 core
4103 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4104 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4105 @item @code{arm966e} -- this is an ARMv5 core
4106 @item @code{arm9tdmi} -- this is an ARMv4 core
4107 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4108 (Support for this is preliminary and incomplete.)
4109 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4110 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4111 compact Thumb2 instruction set.
4112 @item @code{aarch64} -- this is an ARMv8-A core with an MMU
4113 @item @code{dragonite} -- resembles arm966e
4114 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4115 (Support for this is still incomplete.)
4116 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4117 @item @code{feroceon} -- resembles arm926
4118 @item @code{mips_m4k} -- a MIPS core
4119 @item @code{xscale} -- this is actually an architecture,
4120 not a CPU type. It is based on the ARMv5 architecture.
4121 @item @code{openrisc} -- this is an OpenRISC 1000 core.
4122 The current implementation supports three JTAG TAP cores:
4123 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4124 allowing access to physical memory addresses independently of CPU cores.
4125 @itemize @minus
4126 @item @code{OpenCores TAP} (See: @url{,jtag})
4127 @item @code{Altera Virtual JTAG TAP} (See: @url{})
4128 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{})
4129 @end itemize
4130 And two debug interfaces cores:
4131 @itemize @minus
4132 @item @code{Advanced debug interface} (See: @url{,adv_debug_sys})
4133 @item @code{SoC Debug Interface} (See: @url{,dbg_interface})
4134 @end itemize
4135 @end itemize
4136 @end deffn
4138 To avoid being confused by the variety of ARM based cores, remember
4139 this key point: @emph{ARM is a technology licencing company}.
4140 (See: @url{}.)
4141 The CPU name used by OpenOCD will reflect the CPU design that was
4142 licenced, not a vendor brand which incorporates that design.
4143 Name prefixes like arm7, arm9, arm11, and cortex
4144 reflect design generations;
4145 while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
4146 reflect an architecture version implemented by a CPU design.
4148 @anchor{targetconfiguration}
4149 @section Target Configuration
4151 Before creating a ``target'', you must have added its TAP to the scan chain.
4152 When you've added that TAP, you will have a @code{}
4153 which is used to set up the CPU support.
4154 The chip-specific configuration file will normally configure its CPU(s)
4155 right after it adds all of the chip's TAPs to the scan chain.
4157 Although you can set up a target in one step, it's often clearer if you
4158 use shorter commands and do it in two steps: create it, then configure
4159 optional parts.
4160 All operations on the target after it's created will use a new
4161 command, created as part of target creation.
4163 The two main things to configure after target creation are
4164 a work area, which usually has target-specific defaults even
4165 if the board setup code overrides them later;
4166 and event handlers (@pxref{targetevents,,Target Events}), which tend
4167 to be much more board-specific.
4168 The key steps you use might look something like this
4170 @example
4171 target create MyTarget cortex_m -chain-position mychip.cpu
4172 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4173 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4174 $MyTarget configure -event reset-init @{ myboard_reinit @}
4175 @end example
4177 You should specify a working area if you can; typically it uses some
4178 on-chip SRAM.
4179 Such a working area can speed up many things, including bulk
4180 writes to target memory;