jtag/core: remove unused variable
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
11
12 @include version.texi
13
14 @copying
15
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
20
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
28
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A
34 copy of the license is included in the section entitled ``GNU Free
35 Documentation License''.
36 @end quotation
37 @end copying
38
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
45
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
50
51 @summarycontents
52 @contents
53
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
57
58 @insertcopying
59 @end ifnottex
60
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
87
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
94 @end menu
95
96 @node About
97 @unnumbered About
98 @cindex about
99
100 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
101 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
104 around the world.
105
106 @section What is OpenOCD?
107 @cindex TAP
108 @cindex JTAG
109
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
112 devices.
113
114 It does so with the assistance of a @dfn{debug adapter}, which is
115 a small hardware module which helps provide the right kind of
116 electrical signaling to the target being debugged. These are
117 required since the debug host (on which OpenOCD runs) won't
118 usually have native support for such signaling, or the connector
119 needed to hook up to the target.
120
121 Such debug adapters support one or more @dfn{transport} protocols,
122 each of which involves different electrical signaling (and uses
123 different messaging protocols on top of that signaling). There
124 are many types of debug adapter, and little uniformity in what
125 they are called. (There are also product naming differences.)
126
127 These adapters are sometimes packaged as discrete dongles, which
128 may generically be called @dfn{hardware interface dongles}.
129 Some development boards also integrate them directly, which may
130 let the development board connect directly to the debug
131 host over USB (and sometimes also to power it over USB).
132
133 For example, a @dfn{JTAG Adapter} supports JTAG
134 signaling, and is used to communicate
135 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
136 A @dfn{TAP} is a ``Test Access Port'', a module which processes
137 special instructions and data. TAPs are daisy-chained within and
138 between chips and boards. JTAG supports debugging and boundary
139 scan operations.
140
141 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
142 signaling to communicate with some newer ARM cores, as well as debug
143 adapters which support both JTAG and SWD transports. SWD supports only
144 debugging, whereas JTAG also supports boundary scan operations.
145
146 For some chips, there are also @dfn{Programming Adapters} supporting
147 special transports used only to write code to flash memory, without
148 support for on-chip debugging or boundary scan.
149 (At this writing, OpenOCD does not support such non-debug adapters.)
150
151
152 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
153 USB-based, parallel port-based, and other standalone boxes that run
154 OpenOCD internally. @xref{Debug Adapter Hardware}.
155
156 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
157 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
158 (Stellaris LM3, STMicroelectronics STM32 and Energy Micro EFM32) and
159 Intel Quark (x10xx) based cores to be debugged via the GDB protocol.
160
161 @b{Flash Programming:} Flash writing is supported for external
162 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
163 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
164 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
165 controllers (LPC3180, Orion, S3C24xx, more) is included.
166
167 @section OpenOCD Web Site
168
169 The OpenOCD web site provides the latest public news from the community:
170
171 @uref{http://openocd.org/}
172
173 @section Latest User's Guide:
174
175 The user's guide you are now reading may not be the latest one
176 available. A version for more recent code may be available.
177 Its HTML form is published regularly at:
178
179 @uref{http://openocd.org/doc/html/index.html}
180
181 PDF form is likewise published at:
182
183 @uref{http://openocd.org/doc/pdf/openocd.pdf}
184
185 @section OpenOCD User's Forum
186
187 There is an OpenOCD forum (phpBB) hosted by SparkFun,
188 which might be helpful to you. Note that if you want
189 anything to come to the attention of developers, you
190 should post it to the OpenOCD Developer Mailing List
191 instead of this forum.
192
193 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
194
195 @section OpenOCD User's Mailing List
196
197 The OpenOCD User Mailing List provides the primary means of
198 communication between users:
199
200 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
201
202 @section OpenOCD IRC
203
204 Support can also be found on irc:
205 @uref{irc://irc.libera.chat/openocd}
206
207 @node Developers
208 @chapter OpenOCD Developer Resources
209 @cindex developers
210
211 If you are interested in improving the state of OpenOCD's debugging and
212 testing support, new contributions will be welcome. Motivated developers
213 can produce new target, flash or interface drivers, improve the
214 documentation, as well as more conventional bug fixes and enhancements.
215
216 The resources in this chapter are available for developers wishing to explore
217 or expand the OpenOCD source code.
218
219 @section OpenOCD Git Repository
220
221 During the 0.3.x release cycle, OpenOCD switched from Subversion to
222 a Git repository hosted at SourceForge. The repository URL is:
223
224 @uref{git://git.code.sf.net/p/openocd/code}
225
226 or via http
227
228 @uref{http://git.code.sf.net/p/openocd/code}
229
230 You may prefer to use a mirror and the HTTP protocol:
231
232 @uref{http://repo.or.cz/r/openocd.git}
233
234 With standard Git tools, use @command{git clone} to initialize
235 a local repository, and @command{git pull} to update it.
236 There are also gitweb pages letting you browse the repository
237 with a web browser, or download arbitrary snapshots without
238 needing a Git client:
239
240 @uref{http://repo.or.cz/w/openocd.git}
241
242 The @file{README} file contains the instructions for building the project
243 from the repository or a snapshot.
244
245 Developers that want to contribute patches to the OpenOCD system are
246 @b{strongly} encouraged to work against mainline.
247 Patches created against older versions may require additional
248 work from their submitter in order to be updated for newer releases.
249
250 @section Doxygen Developer Manual
251
252 During the 0.2.x release cycle, the OpenOCD project began
253 providing a Doxygen reference manual. This document contains more
254 technical information about the software internals, development
255 processes, and similar documentation:
256
257 @uref{http://openocd.org/doc/doxygen/html/index.html}
258
259 This document is a work-in-progress, but contributions would be welcome
260 to fill in the gaps. All of the source files are provided in-tree,
261 listed in the Doxyfile configuration at the top of the source tree.
262
263 @section Gerrit Review System
264
265 All changes in the OpenOCD Git repository go through the web-based Gerrit
266 Code Review System:
267
268 @uref{http://openocd.zylin.com/}
269
270 After a one-time registration and repository setup, anyone can push commits
271 from their local Git repository directly into Gerrit.
272 All users and developers are encouraged to review, test, discuss and vote
273 for changes in Gerrit. The feedback provides the basis for a maintainer to
274 eventually submit the change to the main Git repository.
275
276 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
277 Developer Manual, contains basic information about how to connect a
278 repository to Gerrit, prepare and push patches. Patch authors are expected to
279 maintain their changes while they're in Gerrit, respond to feedback and if
280 necessary rework and push improved versions of the change.
281
282 @section OpenOCD Developer Mailing List
283
284 The OpenOCD Developer Mailing List provides the primary means of
285 communication between developers:
286
287 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
288
289 @section OpenOCD Bug Tracker
290
291 The OpenOCD Bug Tracker is hosted on SourceForge:
292
293 @uref{http://bugs.openocd.org/}
294
295
296 @node Debug Adapter Hardware
297 @chapter Debug Adapter Hardware
298 @cindex dongles
299 @cindex FTDI
300 @cindex wiggler
301 @cindex printer port
302 @cindex USB Adapter
303 @cindex RTCK
304
305 Defined: @b{dongle}: A small device that plugs into a computer and serves as
306 an adapter .... [snip]
307
308 In the OpenOCD case, this generally refers to @b{a small adapter} that
309 attaches to your computer via USB or the parallel port.
310
311
312 @section Choosing a Dongle
313
314 There are several things you should keep in mind when choosing a dongle.
315
316 @enumerate
317 @item @b{Transport} Does it support the kind of communication that you need?
318 OpenOCD focuses mostly on JTAG. Your version may also support
319 other ways to communicate with target devices.
320 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
321 Does your dongle support it? You might need a level converter.
322 @item @b{Pinout} What pinout does your target board use?
323 Does your dongle support it? You may be able to use jumper
324 wires, or an "octopus" connector, to convert pinouts.
325 @item @b{Connection} Does your computer have the USB, parallel, or
326 Ethernet port needed?
327 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
328 RTCK support (also known as ``adaptive clocking'')?
329 @end enumerate
330
331 @section USB FT2232 Based
332
333 There are many USB JTAG dongles on the market, many of them based
334 on a chip from ``Future Technology Devices International'' (FTDI)
335 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
336 See: @url{http://www.ftdichip.com} for more information.
337 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
338 chips started to become available in JTAG adapters. Around 2012, a new
339 variant appeared - FT232H - this is a single-channel version of FT2232H.
340 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
341 clocking.)
342
343 The FT2232 chips are flexible enough to support some other
344 transport options, such as SWD or the SPI variants used to
345 program some chips. They have two communications channels,
346 and one can be used for a UART adapter at the same time the
347 other one is used to provide a debug adapter.
348
349 Also, some development boards integrate an FT2232 chip to serve as
350 a built-in low-cost debug adapter and USB-to-serial solution.
351
352 @itemize @bullet
353 @item @b{usbjtag}
354 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
355 @item @b{jtagkey}
356 @* See: @url{http://www.amontec.com/jtagkey.shtml}
357 @item @b{jtagkey2}
358 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
359 @item @b{oocdlink}
360 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
361 @item @b{signalyzer}
362 @* See: @url{http://www.signalyzer.com}
363 @item @b{Stellaris Eval Boards}
364 @* See: @url{http://www.ti.com} - The Stellaris eval boards
365 bundle FT2232-based JTAG and SWD support, which can be used to debug
366 the Stellaris chips. Using separate JTAG adapters is optional.
367 These boards can also be used in a "pass through" mode as JTAG adapters
368 to other target boards, disabling the Stellaris chip.
369 @item @b{TI/Luminary ICDI}
370 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
371 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
372 Evaluation Kits. Like the non-detachable FT2232 support on the other
373 Stellaris eval boards, they can be used to debug other target boards.
374 @item @b{olimex-jtag}
375 @* See: @url{http://www.olimex.com}
376 @item @b{Flyswatter/Flyswatter2}
377 @* See: @url{http://www.tincantools.com}
378 @item @b{turtelizer2}
379 @* See:
380 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
381 @url{http://www.ethernut.de}
382 @item @b{comstick}
383 @* Link: @url{http://www.hitex.com/index.php?id=383}
384 @item @b{stm32stick}
385 @* Link @url{http://www.hitex.com/stm32-stick}
386 @item @b{axm0432_jtag}
387 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
388 to be available anymore as of April 2012.
389 @item @b{cortino}
390 @* Link @url{http://www.hitex.com/index.php?id=cortino}
391 @item @b{dlp-usb1232h}
392 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
393 @item @b{digilent-hs1}
394 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
395 @item @b{opendous}
396 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
397 (OpenHardware).
398 @item @b{JTAG-lock-pick Tiny 2}
399 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
400
401 @item @b{GW16042}
402 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
403 FT2232H-based
404
405 @end itemize
406 @section USB-JTAG / Altera USB-Blaster compatibles
407
408 These devices also show up as FTDI devices, but are not
409 protocol-compatible with the FT2232 devices. They are, however,
410 protocol-compatible among themselves. USB-JTAG devices typically consist
411 of a FT245 followed by a CPLD that understands a particular protocol,
412 or emulates this protocol using some other hardware.
413
414 They may appear under different USB VID/PID depending on the particular
415 product. The driver can be configured to search for any VID/PID pair
416 (see the section on driver commands).
417
418 @itemize
419 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
420 @* Link: @url{http://ixo-jtag.sourceforge.net/}
421 @item @b{Altera USB-Blaster}
422 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
423 @end itemize
424
425 @section USB J-Link based
426 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
427 an example of a microcontroller based JTAG adapter, it uses an
428 AT91SAM764 internally.
429
430 @itemize @bullet
431 @item @b{SEGGER J-Link}
432 @* Link: @url{http://www.segger.com/jlink.html}
433 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
434 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
435 @item @b{IAR J-Link}
436 @end itemize
437
438 @section USB RLINK based
439 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
440 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
441 SWD and not JTAG, thus not supported.
442
443 @itemize @bullet
444 @item @b{Raisonance RLink}
445 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
446 @item @b{STM32 Primer}
447 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
448 @item @b{STM32 Primer2}
449 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
450 @end itemize
451
452 @section USB ST-LINK based
453 STMicroelectronics has an adapter called @b{ST-LINK}.
454 They only work with STMicroelectronics chips, notably STM32 and STM8.
455
456 @itemize @bullet
457 @item @b{ST-LINK}
458 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
459 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
460 @item @b{ST-LINK/V2}
461 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
462 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
463 @item @b{STLINK-V3}
464 @* This is available standalone and as part of some kits.
465 @* Link: @url{http://www.st.com/stlink-v3}
466 @end itemize
467
468 For info the original ST-LINK enumerates using the mass storage usb class; however,
469 its implementation is completely broken. The result is this causes issues under Linux.
470 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
471 @itemize @bullet
472 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
473 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
474 @end itemize
475
476 @section USB TI/Stellaris ICDI based
477 Texas Instruments has an adapter called @b{ICDI}.
478 It is not to be confused with the FTDI based adapters that were originally fitted to their
479 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
480
481 @section USB Nuvoton Nu-Link
482 Nuvoton has an adapter called @b{Nu-Link}.
483 It is available either as stand-alone dongle and embedded on development boards.
484 It supports SWD, serial port bridge and mass storage for firmware update.
485 Both Nu-Link v1 and v2 are supported.
486
487 @section USB CMSIS-DAP based
488 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
489 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
490
491 @section USB Other
492 @itemize @bullet
493 @item @b{USBprog}
494 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
495
496 @item @b{USB - Presto}
497 @* Link: @url{http://tools.asix.net/prg_presto.htm}
498
499 @item @b{Versaloon-Link}
500 @* Link: @url{http://www.versaloon.com}
501
502 @item @b{ARM-JTAG-EW}
503 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
504
505 @item @b{Buspirate}
506 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
507
508 @item @b{opendous}
509 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
510
511 @item @b{estick}
512 @* Link: @url{http://code.google.com/p/estick-jtag/}
513
514 @item @b{Keil ULINK v1}
515 @* Link: @url{http://www.keil.com/ulink1/}
516
517 @item @b{TI XDS110 Debug Probe}
518 @* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds110.html}
519 @* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds_software_package_download.html#xds110-support-utilities}
520 @end itemize
521
522 @section IBM PC Parallel Printer Port Based
523
524 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
525 and the Macraigor Wiggler. There are many clones and variations of
526 these on the market.
527
528 Note that parallel ports are becoming much less common, so if you
529 have the choice you should probably avoid these adapters in favor
530 of USB-based ones.
531
532 @itemize @bullet
533
534 @item @b{Wiggler} - There are many clones of this.
535 @* Link: @url{http://www.macraigor.com/wiggler.htm}
536
537 @item @b{DLC5} - From XILINX - There are many clones of this
538 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
539 produced, PDF schematics are easily found and it is easy to make.
540
541 @item @b{Amontec - JTAG Accelerator}
542 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
543
544 @item @b{Wiggler2}
545 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
546
547 @item @b{Wiggler_ntrst_inverted}
548 @* Yet another variation - See the source code, src/jtag/parport.c
549
550 @item @b{old_amt_wiggler}
551 @* Unknown - probably not on the market today
552
553 @item @b{arm-jtag}
554 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
555
556 @item @b{chameleon}
557 @* Link: @url{http://www.amontec.com/chameleon.shtml}
558
559 @item @b{Triton}
560 @* Unknown.
561
562 @item @b{Lattice}
563 @* ispDownload from Lattice Semiconductor
564 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
565
566 @item @b{flashlink}
567 @* From STMicroelectronics;
568 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
569
570 @end itemize
571
572 @section Other...
573 @itemize @bullet
574
575 @item @b{ep93xx}
576 @* An EP93xx based Linux machine using the GPIO pins directly.
577
578 @item @b{at91rm9200}
579 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
580
581 @item @b{bcm2835gpio}
582 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
583
584 @item @b{imx_gpio}
585 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
586
587 @item @b{jtag_vpi}
588 @* A JTAG driver acting as a client for the JTAG VPI server interface.
589 @* Link: @url{http://github.com/fjullien/jtag_vpi}
590
591 @item @b{jtag_dpi}
592 @* A JTAG driver acting as a client for the SystemVerilog Direct Programming
593 Interface (DPI) for JTAG devices. DPI allows OpenOCD to connect to the JTAG
594 interface of a hardware model written in SystemVerilog, for example, on an
595 emulation model of target hardware.
596
597 @item @b{xlnx_pcie_xvc}
598 @* A JTAG driver exposing Xilinx Virtual Cable over PCI Express to OpenOCD as JTAG/SWD interface.
599
600 @item @b{linuxgpiod}
601 @* A bitbang JTAG driver using Linux GPIO through library libgpiod.
602
603 @item @b{sysfsgpio}
604 @* A bitbang JTAG driver using Linux legacy sysfs GPIO.
605 This is deprecated from Linux v5.3; prefer using @b{linuxgpiod}.
606
607 @end itemize
608
609 @node About Jim-Tcl
610 @chapter About Jim-Tcl
611 @cindex Jim-Tcl
612 @cindex tcl
613
614 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
615 This programming language provides a simple and extensible
616 command interpreter.
617
618 All commands presented in this Guide are extensions to Jim-Tcl.
619 You can use them as simple commands, without needing to learn
620 much of anything about Tcl.
621 Alternatively, you can write Tcl programs with them.
622
623 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
624 There is an active and responsive community, get on the mailing list
625 if you have any questions. Jim-Tcl maintainers also lurk on the
626 OpenOCD mailing list.
627
628 @itemize @bullet
629 @item @b{Jim vs. Tcl}
630 @* Jim-Tcl is a stripped down version of the well known Tcl language,
631 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
632 fewer features. Jim-Tcl is several dozens of .C files and .H files and
633 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
634 4.2 MB .zip file containing 1540 files.
635
636 @item @b{Missing Features}
637 @* Our practice has been: Add/clone the real Tcl feature if/when
638 needed. We welcome Jim-Tcl improvements, not bloat. Also there
639 are a large number of optional Jim-Tcl features that are not
640 enabled in OpenOCD.
641
642 @item @b{Scripts}
643 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
644 command interpreter today is a mixture of (newer)
645 Jim-Tcl commands, and the (older) original command interpreter.
646
647 @item @b{Commands}
648 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
649 can type a Tcl for() loop, set variables, etc.
650 Some of the commands documented in this guide are implemented
651 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
652
653 @item @b{Historical Note}
654 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
655 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
656 as a Git submodule, which greatly simplified upgrading Jim-Tcl
657 to benefit from new features and bugfixes in Jim-Tcl.
658
659 @item @b{Need a crash course in Tcl?}
660 @*@xref{Tcl Crash Course}.
661 @end itemize
662
663 @node Running
664 @chapter Running
665 @cindex command line options
666 @cindex logfile
667 @cindex directory search
668
669 Properly installing OpenOCD sets up your operating system to grant it access
670 to the debug adapters. On Linux, this usually involves installing a file
671 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
672 that works for many common adapters is shipped with OpenOCD in the
673 @file{contrib} directory. MS-Windows needs
674 complex and confusing driver configuration for every peripheral. Such issues
675 are unique to each operating system, and are not detailed in this User's Guide.
676
677 Then later you will invoke the OpenOCD server, with various options to
678 tell it how each debug session should work.
679 The @option{--help} option shows:
680 @verbatim
681 bash$ openocd --help
682
683 --help | -h display this help
684 --version | -v display OpenOCD version
685 --file | -f use configuration file <name>
686 --search | -s dir to search for config files and scripts
687 --debug | -d set debug level to 3
688 | -d<n> set debug level to <level>
689 --log_output | -l redirect log output to file <name>
690 --command | -c run <command>
691 @end verbatim
692
693 If you don't give any @option{-f} or @option{-c} options,
694 OpenOCD tries to read the configuration file @file{openocd.cfg}.
695 To specify one or more different
696 configuration files, use @option{-f} options. For example:
697
698 @example
699 openocd -f config1.cfg -f config2.cfg -f config3.cfg
700 @end example
701
702 Configuration files and scripts are searched for in
703 @enumerate
704 @item the current directory,
705 @item any search dir specified on the command line using the @option{-s} option,
706 @item any search dir specified using the @command{add_script_search_dir} command,
707 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
708 @item @file{%APPDATA%/OpenOCD} (only on Windows),
709 @item @file{$HOME/Library/Preferences/org.openocd} (only on Darwin),
710 @item @file{$XDG_CONFIG_HOME/openocd} (@env{$XDG_CONFIG_HOME} defaults to @file{$HOME/.config}),
711 @item @file{$HOME/.openocd},
712 @item the site wide script library @file{$pkgdatadir/site} and
713 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
714 @end enumerate
715 The first found file with a matching file name will be used.
716
717 @quotation Note
718 Don't try to use configuration script names or paths which
719 include the "#" character. That character begins Tcl comments.
720 @end quotation
721
722 @section Simple setup, no customization
723
724 In the best case, you can use two scripts from one of the script
725 libraries, hook up your JTAG adapter, and start the server ... and
726 your JTAG setup will just work "out of the box". Always try to
727 start by reusing those scripts, but assume you'll need more
728 customization even if this works. @xref{OpenOCD Project Setup}.
729
730 If you find a script for your JTAG adapter, and for your board or
731 target, you may be able to hook up your JTAG adapter then start
732 the server with some variation of one of the following:
733
734 @example
735 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
736 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
737 @end example
738
739 You might also need to configure which reset signals are present,
740 using @option{-c 'reset_config trst_and_srst'} or something similar.
741 If all goes well you'll see output something like
742
743 @example
744 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
745 For bug reports, read
746 http://openocd.org/doc/doxygen/bugs.html
747 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
748 (mfg: 0x23b, part: 0xba00, ver: 0x3)
749 @end example
750
751 Seeing that "tap/device found" message, and no warnings, means
752 the JTAG communication is working. That's a key milestone, but
753 you'll probably need more project-specific setup.
754
755 @section What OpenOCD does as it starts
756
757 OpenOCD starts by processing the configuration commands provided
758 on the command line or, if there were no @option{-c command} or
759 @option{-f file.cfg} options given, in @file{openocd.cfg}.
760 @xref{configurationstage,,Configuration Stage}.
761 At the end of the configuration stage it verifies the JTAG scan
762 chain defined using those commands; your configuration should
763 ensure that this always succeeds.
764 Normally, OpenOCD then starts running as a server.
765 Alternatively, commands may be used to terminate the configuration
766 stage early, perform work (such as updating some flash memory),
767 and then shut down without acting as a server.
768
769 Once OpenOCD starts running as a server, it waits for connections from
770 clients (Telnet, GDB, RPC) and processes the commands issued through
771 those channels.
772
773 If you are having problems, you can enable internal debug messages via
774 the @option{-d} option.
775
776 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
777 @option{-c} command line switch.
778
779 To enable debug output (when reporting problems or working on OpenOCD
780 itself), use the @option{-d} command line switch. This sets the
781 @option{debug_level} to "3", outputting the most information,
782 including debug messages. The default setting is "2", outputting only
783 informational messages, warnings and errors. You can also change this
784 setting from within a telnet or gdb session using @command{debug_level<n>}
785 (@pxref{debuglevel,,debug_level}).
786
787 You can redirect all output from the server to a file using the
788 @option{-l <logfile>} switch.
789
790 Note! OpenOCD will launch the GDB & telnet server even if it can not
791 establish a connection with the target. In general, it is possible for
792 the JTAG controller to be unresponsive until the target is set up
793 correctly via e.g. GDB monitor commands in a GDB init script.
794
795 @node OpenOCD Project Setup
796 @chapter OpenOCD Project Setup
797
798 To use OpenOCD with your development projects, you need to do more than
799 just connect the JTAG adapter hardware (dongle) to your development board
800 and start the OpenOCD server.
801 You also need to configure your OpenOCD server so that it knows
802 about your adapter and board, and helps your work.
803 You may also want to connect OpenOCD to GDB, possibly
804 using Eclipse or some other GUI.
805
806 @section Hooking up the JTAG Adapter
807
808 Today's most common case is a dongle with a JTAG cable on one side
809 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
810 and a USB cable on the other.
811 Instead of USB, some dongles use Ethernet;
812 older ones may use a PC parallel port, or even a serial port.
813
814 @enumerate
815 @item @emph{Start with power to your target board turned off},
816 and nothing connected to your JTAG adapter.
817 If you're particularly paranoid, unplug power to the board.
818 It's important to have the ground signal properly set up,
819 unless you are using a JTAG adapter which provides
820 galvanic isolation between the target board and the
821 debugging host.
822
823 @item @emph{Be sure it's the right kind of JTAG connector.}
824 If your dongle has a 20-pin ARM connector, you need some kind
825 of adapter (or octopus, see below) to hook it up to
826 boards using 14-pin or 10-pin connectors ... or to 20-pin
827 connectors which don't use ARM's pinout.
828
829 In the same vein, make sure the voltage levels are compatible.
830 Not all JTAG adapters have the level shifters needed to work
831 with 1.2 Volt boards.
832
833 @item @emph{Be certain the cable is properly oriented} or you might
834 damage your board. In most cases there are only two possible
835 ways to connect the cable.
836 Connect the JTAG cable from your adapter to the board.
837 Be sure it's firmly connected.
838
839 In the best case, the connector is keyed to physically
840 prevent you from inserting it wrong.
841 This is most often done using a slot on the board's male connector
842 housing, which must match a key on the JTAG cable's female connector.
843 If there's no housing, then you must look carefully and
844 make sure pin 1 on the cable hooks up to pin 1 on the board.
845 Ribbon cables are frequently all grey except for a wire on one
846 edge, which is red. The red wire is pin 1.
847
848 Sometimes dongles provide cables where one end is an ``octopus'' of
849 color coded single-wire connectors, instead of a connector block.
850 These are great when converting from one JTAG pinout to another,
851 but are tedious to set up.
852 Use these with connector pinout diagrams to help you match up the
853 adapter signals to the right board pins.
854
855 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
856 A USB, parallel, or serial port connector will go to the host which
857 you are using to run OpenOCD.
858 For Ethernet, consult the documentation and your network administrator.
859
860 For USB-based JTAG adapters you have an easy sanity check at this point:
861 does the host operating system see the JTAG adapter? If you're running
862 Linux, try the @command{lsusb} command. If that host is an
863 MS-Windows host, you'll need to install a driver before OpenOCD works.
864
865 @item @emph{Connect the adapter's power supply, if needed.}
866 This step is primarily for non-USB adapters,
867 but sometimes USB adapters need extra power.
868
869 @item @emph{Power up the target board.}
870 Unless you just let the magic smoke escape,
871 you're now ready to set up the OpenOCD server
872 so you can use JTAG to work with that board.
873
874 @end enumerate
875
876 Talk with the OpenOCD server using
877 telnet (@code{telnet localhost 4444} on many systems) or GDB.
878 @xref{GDB and OpenOCD}.
879
880 @section Project Directory
881
882 There are many ways you can configure OpenOCD and start it up.
883
884 A simple way to organize them all involves keeping a
885 single directory for your work with a given board.
886 When you start OpenOCD from that directory,
887 it searches there first for configuration files, scripts,
888 files accessed through semihosting,
889 and for code you upload to the target board.
890 It is also the natural place to write files,
891 such as log files and data you download from the board.
892
893 @section Configuration Basics
894
895 There are two basic ways of configuring OpenOCD, and
896 a variety of ways you can mix them.
897 Think of the difference as just being how you start the server:
898
899 @itemize
900 @item Many @option{-f file} or @option{-c command} options on the command line
901 @item No options, but a @dfn{user config file}
902 in the current directory named @file{openocd.cfg}
903 @end itemize
904
905 Here is an example @file{openocd.cfg} file for a setup
906 using a Signalyzer FT2232-based JTAG adapter to talk to
907 a board with an Atmel AT91SAM7X256 microcontroller:
908
909 @example
910 source [find interface/ftdi/signalyzer.cfg]
911
912 # GDB can also flash my flash!
913 gdb_memory_map enable
914 gdb_flash_program enable
915
916 source [find target/sam7x256.cfg]
917 @end example
918
919 Here is the command line equivalent of that configuration:
920
921 @example
922 openocd -f interface/ftdi/signalyzer.cfg \
923 -c "gdb_memory_map enable" \
924 -c "gdb_flash_program enable" \
925 -f target/sam7x256.cfg
926 @end example
927
928 You could wrap such long command lines in shell scripts,
929 each supporting a different development task.
930 One might re-flash the board with a specific firmware version.
931 Another might set up a particular debugging or run-time environment.
932
933 @quotation Important
934 At this writing (October 2009) the command line method has
935 problems with how it treats variables.
936 For example, after @option{-c "set VAR value"}, or doing the
937 same in a script, the variable @var{VAR} will have no value
938 that can be tested in a later script.
939 @end quotation
940
941 Here we will focus on the simpler solution: one user config
942 file, including basic configuration plus any TCL procedures
943 to simplify your work.
944
945 @section User Config Files
946 @cindex config file, user
947 @cindex user config file
948 @cindex config file, overview
949
950 A user configuration file ties together all the parts of a project
951 in one place.
952 One of the following will match your situation best:
953
954 @itemize
955 @item Ideally almost everything comes from configuration files
956 provided by someone else.
957 For example, OpenOCD distributes a @file{scripts} directory
958 (probably in @file{/usr/share/openocd/scripts} on Linux).
959 Board and tool vendors can provide these too, as can individual
960 user sites; the @option{-s} command line option lets you say
961 where to find these files. (@xref{Running}.)
962 The AT91SAM7X256 example above works this way.
963
964 Three main types of non-user configuration file each have their
965 own subdirectory in the @file{scripts} directory:
966
967 @enumerate
968 @item @b{interface} -- one for each different debug adapter;
969 @item @b{board} -- one for each different board
970 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
971 @end enumerate
972
973 Best case: include just two files, and they handle everything else.
974 The first is an interface config file.
975 The second is board-specific, and it sets up the JTAG TAPs and
976 their GDB targets (by deferring to some @file{target.cfg} file),
977 declares all flash memory, and leaves you nothing to do except
978 meet your deadline:
979
980 @example
981 source [find interface/olimex-jtag-tiny.cfg]
982 source [find board/csb337.cfg]
983 @end example
984
985 Boards with a single microcontroller often won't need more
986 than the target config file, as in the AT91SAM7X256 example.
987 That's because there is no external memory (flash, DDR RAM), and
988 the board differences are encapsulated by application code.
989
990 @item Maybe you don't know yet what your board looks like to JTAG.
991 Once you know the @file{interface.cfg} file to use, you may
992 need help from OpenOCD to discover what's on the board.
993 Once you find the JTAG TAPs, you can just search for appropriate
994 target and board
995 configuration files ... or write your own, from the bottom up.
996 @xref{autoprobing,,Autoprobing}.
997
998 @item You can often reuse some standard config files but
999 need to write a few new ones, probably a @file{board.cfg} file.
1000 You will be using commands described later in this User's Guide,
1001 and working with the guidelines in the next chapter.
1002
1003 For example, there may be configuration files for your JTAG adapter
1004 and target chip, but you need a new board-specific config file
1005 giving access to your particular flash chips.
1006 Or you might need to write another target chip configuration file
1007 for a new chip built around the Cortex-M3 core.
1008
1009 @quotation Note
1010 When you write new configuration files, please submit
1011 them for inclusion in the next OpenOCD release.
1012 For example, a @file{board/newboard.cfg} file will help the
1013 next users of that board, and a @file{target/newcpu.cfg}
1014 will help support users of any board using that chip.
1015 @end quotation
1016
1017 @item
1018 You may need to write some C code.
1019 It may be as simple as supporting a new FT2232 or parport
1020 based adapter; a bit more involved, like a NAND or NOR flash
1021 controller driver; or a big piece of work like supporting
1022 a new chip architecture.
1023 @end itemize
1024
1025 Reuse the existing config files when you can.
1026 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1027 You may find a board configuration that's a good example to follow.
1028
1029 When you write config files, separate the reusable parts
1030 (things every user of that interface, chip, or board needs)
1031 from ones specific to your environment and debugging approach.
1032 @itemize
1033
1034 @item
1035 For example, a @code{gdb-attach} event handler that invokes
1036 the @command{reset init} command will interfere with debugging
1037 early boot code, which performs some of the same actions
1038 that the @code{reset-init} event handler does.
1039
1040 @item
1041 Likewise, the @command{arm9 vector_catch} command (or
1042 @cindex vector_catch
1043 its siblings @command{xscale vector_catch}
1044 and @command{cortex_m vector_catch}) can be a time-saver
1045 during some debug sessions, but don't make everyone use that either.
1046 Keep those kinds of debugging aids in your user config file,
1047 along with messaging and tracing setup.
1048 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1049
1050 @item
1051 You might need to override some defaults.
1052 For example, you might need to move, shrink, or back up the target's
1053 work area if your application needs much SRAM.
1054
1055 @item
1056 TCP/IP port configuration is another example of something which
1057 is environment-specific, and should only appear in
1058 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1059 @end itemize
1060
1061 @section Project-Specific Utilities
1062
1063 A few project-specific utility
1064 routines may well speed up your work.
1065 Write them, and keep them in your project's user config file.
1066
1067 For example, if you are making a boot loader work on a
1068 board, it's nice to be able to debug the ``after it's
1069 loaded to RAM'' parts separately from the finicky early
1070 code which sets up the DDR RAM controller and clocks.
1071 A script like this one, or a more GDB-aware sibling,
1072 may help:
1073
1074 @example
1075 proc ramboot @{ @} @{
1076 # Reset, running the target's "reset-init" scripts
1077 # to initialize clocks and the DDR RAM controller.
1078 # Leave the CPU halted.
1079 reset init
1080
1081 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1082 load_image u-boot.bin 0x20000000
1083
1084 # Start running.
1085 resume 0x20000000
1086 @}
1087 @end example
1088
1089 Then once that code is working you will need to make it
1090 boot from NOR flash; a different utility would help.
1091 Alternatively, some developers write to flash using GDB.
1092 (You might use a similar script if you're working with a flash
1093 based microcontroller application instead of a boot loader.)
1094
1095 @example
1096 proc newboot @{ @} @{
1097 # Reset, leaving the CPU halted. The "reset-init" event
1098 # proc gives faster access to the CPU and to NOR flash;
1099 # "reset halt" would be slower.
1100 reset init
1101
1102 # Write standard version of U-Boot into the first two
1103 # sectors of NOR flash ... the standard version should
1104 # do the same lowlevel init as "reset-init".
1105 flash protect 0 0 1 off
1106 flash erase_sector 0 0 1
1107 flash write_bank 0 u-boot.bin 0x0
1108 flash protect 0 0 1 on
1109
1110 # Reboot from scratch using that new boot loader.
1111 reset run
1112 @}
1113 @end example
1114
1115 You may need more complicated utility procedures when booting
1116 from NAND.
1117 That often involves an extra bootloader stage,
1118 running from on-chip SRAM to perform DDR RAM setup so it can load
1119 the main bootloader code (which won't fit into that SRAM).
1120
1121 Other helper scripts might be used to write production system images,
1122 involving considerably more than just a three stage bootloader.
1123
1124 @section Target Software Changes
1125
1126 Sometimes you may want to make some small changes to the software
1127 you're developing, to help make JTAG debugging work better.
1128 For example, in C or assembly language code you might
1129 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1130 handling issues like:
1131
1132 @itemize @bullet
1133
1134 @item @b{Watchdog Timers}...
1135 Watchdog timers are typically used to automatically reset systems if
1136 some application task doesn't periodically reset the timer. (The
1137 assumption is that the system has locked up if the task can't run.)
1138 When a JTAG debugger halts the system, that task won't be able to run
1139 and reset the timer ... potentially causing resets in the middle of
1140 your debug sessions.
1141
1142 It's rarely a good idea to disable such watchdogs, since their usage
1143 needs to be debugged just like all other parts of your firmware.
1144 That might however be your only option.
1145
1146 Look instead for chip-specific ways to stop the watchdog from counting
1147 while the system is in a debug halt state. It may be simplest to set
1148 that non-counting mode in your debugger startup scripts. You may however
1149 need a different approach when, for example, a motor could be physically
1150 damaged by firmware remaining inactive in a debug halt state. That might
1151 involve a type of firmware mode where that "non-counting" mode is disabled
1152 at the beginning then re-enabled at the end; a watchdog reset might fire
1153 and complicate the debug session, but hardware (or people) would be
1154 protected.@footnote{Note that many systems support a "monitor mode" debug
1155 that is a somewhat cleaner way to address such issues. You can think of
1156 it as only halting part of the system, maybe just one task,
1157 instead of the whole thing.
1158 At this writing, January 2010, OpenOCD based debugging does not support
1159 monitor mode debug, only "halt mode" debug.}
1160
1161 @item @b{ARM Semihosting}...
1162 @cindex ARM semihosting
1163 When linked with a special runtime library provided with many
1164 toolchains@footnote{See chapter 8 "Semihosting" in
1165 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1166 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1167 The CodeSourcery EABI toolchain also includes a semihosting library.},
1168 your target code can use I/O facilities on the debug host. That library
1169 provides a small set of system calls which are handled by OpenOCD.
1170 It can let the debugger provide your system console and a file system,
1171 helping with early debugging or providing a more capable environment
1172 for sometimes-complex tasks like installing system firmware onto
1173 NAND or SPI flash.
1174
1175 @item @b{ARM Wait-For-Interrupt}...
1176 Many ARM chips synchronize the JTAG clock using the core clock.
1177 Low power states which stop that core clock thus prevent JTAG access.
1178 Idle loops in tasking environments often enter those low power states
1179 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1180
1181 You may want to @emph{disable that instruction} in source code,
1182 or otherwise prevent using that state,
1183 to ensure you can get JTAG access at any time.@footnote{As a more
1184 polite alternative, some processors have special debug-oriented
1185 registers which can be used to change various features including
1186 how the low power states are clocked while debugging.
1187 The STM32 DBGMCU_CR register is an example; at the cost of extra
1188 power consumption, JTAG can be used during low power states.}
1189 For example, the OpenOCD @command{halt} command may not
1190 work for an idle processor otherwise.
1191
1192 @item @b{Delay after reset}...
1193 Not all chips have good support for debugger access
1194 right after reset; many LPC2xxx chips have issues here.
1195 Similarly, applications that reconfigure pins used for
1196 JTAG access as they start will also block debugger access.
1197
1198 To work with boards like this, @emph{enable a short delay loop}
1199 the first thing after reset, before "real" startup activities.
1200 For example, one second's delay is usually more than enough
1201 time for a JTAG debugger to attach, so that
1202 early code execution can be debugged
1203 or firmware can be replaced.
1204
1205 @item @b{Debug Communications Channel (DCC)}...
1206 Some processors include mechanisms to send messages over JTAG.
1207 Many ARM cores support these, as do some cores from other vendors.
1208 (OpenOCD may be able to use this DCC internally, speeding up some
1209 operations like writing to memory.)
1210
1211 Your application may want to deliver various debugging messages
1212 over JTAG, by @emph{linking with a small library of code}
1213 provided with OpenOCD and using the utilities there to send
1214 various kinds of message.
1215 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1216
1217 @end itemize
1218
1219 @section Target Hardware Setup
1220
1221 Chip vendors often provide software development boards which
1222 are highly configurable, so that they can support all options
1223 that product boards may require. @emph{Make sure that any
1224 jumpers or switches match the system configuration you are
1225 working with.}
1226
1227 Common issues include:
1228
1229 @itemize @bullet
1230
1231 @item @b{JTAG setup} ...
1232 Boards may support more than one JTAG configuration.
1233 Examples include jumpers controlling pullups versus pulldowns
1234 on the nTRST and/or nSRST signals, and choice of connectors
1235 (e.g. which of two headers on the base board,
1236 or one from a daughtercard).
1237 For some Texas Instruments boards, you may need to jumper the
1238 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1239
1240 @item @b{Boot Modes} ...
1241 Complex chips often support multiple boot modes, controlled
1242 by external jumpers. Make sure this is set up correctly.
1243 For example many i.MX boards from NXP need to be jumpered
1244 to "ATX mode" to start booting using the on-chip ROM, when
1245 using second stage bootloader code stored in a NAND flash chip.
1246
1247 Such explicit configuration is common, and not limited to
1248 booting from NAND. You might also need to set jumpers to
1249 start booting using code loaded from an MMC/SD card; external
1250 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1251 flash; some external host; or various other sources.
1252
1253
1254 @item @b{Memory Addressing} ...
1255 Boards which support multiple boot modes may also have jumpers
1256 to configure memory addressing. One board, for example, jumpers
1257 external chipselect 0 (used for booting) to address either
1258 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1259 or NAND flash. When it's jumpered to address NAND flash, that
1260 board must also be told to start booting from on-chip ROM.
1261
1262 Your @file{board.cfg} file may also need to be told this jumper
1263 configuration, so that it can know whether to declare NOR flash
1264 using @command{flash bank} or instead declare NAND flash with
1265 @command{nand device}; and likewise which probe to perform in
1266 its @code{reset-init} handler.
1267
1268 A closely related issue is bus width. Jumpers might need to
1269 distinguish between 8 bit or 16 bit bus access for the flash
1270 used to start booting.
1271
1272 @item @b{Peripheral Access} ...
1273 Development boards generally provide access to every peripheral
1274 on the chip, sometimes in multiple modes (such as by providing
1275 multiple audio codec chips).
1276 This interacts with software
1277 configuration of pin multiplexing, where for example a
1278 given pin may be routed either to the MMC/SD controller
1279 or the GPIO controller. It also often interacts with
1280 configuration jumpers. One jumper may be used to route
1281 signals to an MMC/SD card slot or an expansion bus (which
1282 might in turn affect booting); others might control which
1283 audio or video codecs are used.
1284
1285 @end itemize
1286
1287 Plus you should of course have @code{reset-init} event handlers
1288 which set up the hardware to match that jumper configuration.
1289 That includes in particular any oscillator or PLL used to clock
1290 the CPU, and any memory controllers needed to access external
1291 memory and peripherals. Without such handlers, you won't be
1292 able to access those resources without working target firmware
1293 which can do that setup ... this can be awkward when you're
1294 trying to debug that target firmware. Even if there's a ROM
1295 bootloader which handles a few issues, it rarely provides full
1296 access to all board-specific capabilities.
1297
1298
1299 @node Config File Guidelines
1300 @chapter Config File Guidelines
1301
1302 This chapter is aimed at any user who needs to write a config file,
1303 including developers and integrators of OpenOCD and any user who
1304 needs to get a new board working smoothly.
1305 It provides guidelines for creating those files.
1306
1307 You should find the following directories under
1308 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1309 them as-is where you can; or as models for new files.
1310 @itemize @bullet
1311 @item @file{interface} ...
1312 These are for debug adapters. Files that specify configuration to use
1313 specific JTAG, SWD and other adapters go here.
1314 @item @file{board} ...
1315 Think Circuit Board, PWA, PCB, they go by many names. Board files
1316 contain initialization items that are specific to a board.
1317
1318 They reuse target configuration files, since the same
1319 microprocessor chips are used on many boards,
1320 but support for external parts varies widely. For
1321 example, the SDRAM initialization sequence for the board, or the type
1322 of external flash and what address it uses. Any initialization
1323 sequence to enable that external flash or SDRAM should be found in the
1324 board file. Boards may also contain multiple targets: two CPUs; or
1325 a CPU and an FPGA.
1326 @item @file{target} ...
1327 Think chip. The ``target'' directory represents the JTAG TAPs
1328 on a chip
1329 which OpenOCD should control, not a board. Two common types of targets
1330 are ARM chips and FPGA or CPLD chips.
1331 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1332 the target config file defines all of them.
1333 @item @emph{more} ... browse for other library files which may be useful.
1334 For example, there are various generic and CPU-specific utilities.
1335 @end itemize
1336
1337 The @file{openocd.cfg} user config
1338 file may override features in any of the above files by
1339 setting variables before sourcing the target file, or by adding
1340 commands specific to their situation.
1341
1342 @section Interface Config Files
1343
1344 The user config file
1345 should be able to source one of these files with a command like this:
1346
1347 @example
1348 source [find interface/FOOBAR.cfg]
1349 @end example
1350
1351 A preconfigured interface file should exist for every debug adapter
1352 in use today with OpenOCD.
1353 That said, perhaps some of these config files
1354 have only been used by the developer who created it.
1355
1356 A separate chapter gives information about how to set these up.
1357 @xref{Debug Adapter Configuration}.
1358 Read the OpenOCD source code (and Developer's Guide)
1359 if you have a new kind of hardware interface
1360 and need to provide a driver for it.
1361
1362 @section Board Config Files
1363 @cindex config file, board
1364 @cindex board config file
1365
1366 The user config file
1367 should be able to source one of these files with a command like this:
1368
1369 @example
1370 source [find board/FOOBAR.cfg]
1371 @end example
1372
1373 The point of a board config file is to package everything
1374 about a given board that user config files need to know.
1375 In summary the board files should contain (if present)
1376
1377 @enumerate
1378 @item One or more @command{source [find target/...cfg]} statements
1379 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1380 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1381 @item Target @code{reset} handlers for SDRAM and I/O configuration
1382 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1383 @item All things that are not ``inside a chip''
1384 @end enumerate
1385
1386 Generic things inside target chips belong in target config files,
1387 not board config files. So for example a @code{reset-init} event
1388 handler should know board-specific oscillator and PLL parameters,
1389 which it passes to target-specific utility code.
1390
1391 The most complex task of a board config file is creating such a
1392 @code{reset-init} event handler.
1393 Define those handlers last, after you verify the rest of the board
1394 configuration works.
1395
1396 @subsection Communication Between Config files
1397
1398 In addition to target-specific utility code, another way that
1399 board and target config files communicate is by following a
1400 convention on how to use certain variables.
1401
1402 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1403 Thus the rule we follow in OpenOCD is this: Variables that begin with
1404 a leading underscore are temporary in nature, and can be modified and
1405 used at will within a target configuration file.
1406
1407 Complex board config files can do the things like this,
1408 for a board with three chips:
1409
1410 @example
1411 # Chip #1: PXA270 for network side, big endian
1412 set CHIPNAME network
1413 set ENDIAN big
1414 source [find target/pxa270.cfg]
1415 # on return: _TARGETNAME = network.cpu
1416 # other commands can refer to the "network.cpu" target.
1417 $_TARGETNAME configure .... events for this CPU..
1418
1419 # Chip #2: PXA270 for video side, little endian
1420 set CHIPNAME video
1421 set ENDIAN little
1422 source [find target/pxa270.cfg]
1423 # on return: _TARGETNAME = video.cpu
1424 # other commands can refer to the "video.cpu" target.
1425 $_TARGETNAME configure .... events for this CPU..
1426
1427 # Chip #3: Xilinx FPGA for glue logic
1428 set CHIPNAME xilinx
1429 unset ENDIAN
1430 source [find target/spartan3.cfg]
1431 @end example
1432
1433 That example is oversimplified because it doesn't show any flash memory,
1434 or the @code{reset-init} event handlers to initialize external DRAM
1435 or (assuming it needs it) load a configuration into the FPGA.
1436 Such features are usually needed for low-level work with many boards,
1437 where ``low level'' implies that the board initialization software may
1438 not be working. (That's a common reason to need JTAG tools. Another
1439 is to enable working with microcontroller-based systems, which often
1440 have no debugging support except a JTAG connector.)
1441
1442 Target config files may also export utility functions to board and user
1443 config files. Such functions should use name prefixes, to help avoid
1444 naming collisions.
1445
1446 Board files could also accept input variables from user config files.
1447 For example, there might be a @code{J4_JUMPER} setting used to identify
1448 what kind of flash memory a development board is using, or how to set
1449 up other clocks and peripherals.
1450
1451 @subsection Variable Naming Convention
1452 @cindex variable names
1453
1454 Most boards have only one instance of a chip.
1455 However, it should be easy to create a board with more than
1456 one such chip (as shown above).
1457 Accordingly, we encourage these conventions for naming
1458 variables associated with different @file{target.cfg} files,
1459 to promote consistency and
1460 so that board files can override target defaults.
1461
1462 Inputs to target config files include:
1463
1464 @itemize @bullet
1465 @item @code{CHIPNAME} ...
1466 This gives a name to the overall chip, and is used as part of
1467 tap identifier dotted names.
1468 While the default is normally provided by the chip manufacturer,
1469 board files may need to distinguish between instances of a chip.
1470 @item @code{ENDIAN} ...
1471 By default @option{little} - although chips may hard-wire @option{big}.
1472 Chips that can't change endianness don't need to use this variable.
1473 @item @code{CPUTAPID} ...
1474 When OpenOCD examines the JTAG chain, it can be told verify the
1475 chips against the JTAG IDCODE register.
1476 The target file will hold one or more defaults, but sometimes the
1477 chip in a board will use a different ID (perhaps a newer revision).
1478 @end itemize
1479
1480 Outputs from target config files include:
1481
1482 @itemize @bullet
1483 @item @code{_TARGETNAME} ...
1484 By convention, this variable is created by the target configuration
1485 script. The board configuration file may make use of this variable to
1486 configure things like a ``reset init'' script, or other things
1487 specific to that board and that target.
1488 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1489 @code{_TARGETNAME1}, ... etc.
1490 @end itemize
1491
1492 @subsection The reset-init Event Handler
1493 @cindex event, reset-init
1494 @cindex reset-init handler
1495
1496 Board config files run in the OpenOCD configuration stage;
1497 they can't use TAPs or targets, since they haven't been
1498 fully set up yet.
1499 This means you can't write memory or access chip registers;
1500 you can't even verify that a flash chip is present.
1501 That's done later in event handlers, of which the target @code{reset-init}
1502 handler is one of the most important.
1503
1504 Except on microcontrollers, the basic job of @code{reset-init} event
1505 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1506 Microcontrollers rarely use boot loaders; they run right out of their
1507 on-chip flash and SRAM memory. But they may want to use one of these
1508 handlers too, if just for developer convenience.
1509
1510 @quotation Note
1511 Because this is so very board-specific, and chip-specific, no examples
1512 are included here.
1513 Instead, look at the board config files distributed with OpenOCD.
1514 If you have a boot loader, its source code will help; so will
1515 configuration files for other JTAG tools
1516 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1517 @end quotation
1518
1519 Some of this code could probably be shared between different boards.
1520 For example, setting up a DRAM controller often doesn't differ by
1521 much except the bus width (16 bits or 32?) and memory timings, so a
1522 reusable TCL procedure loaded by the @file{target.cfg} file might take
1523 those as parameters.
1524 Similarly with oscillator, PLL, and clock setup;
1525 and disabling the watchdog.
1526 Structure the code cleanly, and provide comments to help
1527 the next developer doing such work.
1528 (@emph{You might be that next person} trying to reuse init code!)
1529
1530 The last thing normally done in a @code{reset-init} handler is probing
1531 whatever flash memory was configured. For most chips that needs to be
1532 done while the associated target is halted, either because JTAG memory
1533 access uses the CPU or to prevent conflicting CPU access.
1534
1535 @subsection JTAG Clock Rate
1536
1537 Before your @code{reset-init} handler has set up
1538 the PLLs and clocking, you may need to run with
1539 a low JTAG clock rate.
1540 @xref{jtagspeed,,JTAG Speed}.
1541 Then you'd increase that rate after your handler has
1542 made it possible to use the faster JTAG clock.
1543 When the initial low speed is board-specific, for example
1544 because it depends on a board-specific oscillator speed, then
1545 you should probably set it up in the board config file;
1546 if it's target-specific, it belongs in the target config file.
1547
1548 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1549 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1550 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1551 Consult chip documentation to determine the peak JTAG clock rate,
1552 which might be less than that.
1553
1554 @quotation Warning
1555 On most ARMs, JTAG clock detection is coupled to the core clock, so
1556 software using a @option{wait for interrupt} operation blocks JTAG access.
1557 Adaptive clocking provides a partial workaround, but a more complete
1558 solution just avoids using that instruction with JTAG debuggers.
1559 @end quotation
1560
1561 If both the chip and the board support adaptive clocking,
1562 use the @command{jtag_rclk}
1563 command, in case your board is used with JTAG adapter which
1564 also supports it. Otherwise use @command{adapter speed}.
1565 Set the slow rate at the beginning of the reset sequence,
1566 and the faster rate as soon as the clocks are at full speed.
1567
1568 @anchor{theinitboardprocedure}
1569 @subsection The init_board procedure
1570 @cindex init_board procedure
1571
1572 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1573 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1574 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1575 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1576 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1577 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1578 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1579 Additionally ``linear'' board config file will most likely fail when target config file uses
1580 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1581 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1582 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1583 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1584
1585 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1586 the original), allowing greater code reuse.
1587
1588 @example
1589 ### board_file.cfg ###
1590
1591 # source target file that does most of the config in init_targets
1592 source [find target/target.cfg]
1593
1594 proc enable_fast_clock @{@} @{
1595 # enables fast on-board clock source
1596 # configures the chip to use it
1597 @}
1598
1599 # initialize only board specifics - reset, clock, adapter frequency
1600 proc init_board @{@} @{
1601 reset_config trst_and_srst trst_pulls_srst
1602
1603 $_TARGETNAME configure -event reset-start @{
1604 adapter speed 100
1605 @}
1606
1607 $_TARGETNAME configure -event reset-init @{
1608 enable_fast_clock
1609 adapter speed 10000
1610 @}
1611 @}
1612 @end example
1613
1614 @section Target Config Files
1615 @cindex config file, target
1616 @cindex target config file
1617
1618 Board config files communicate with target config files using
1619 naming conventions as described above, and may source one or
1620 more target config files like this:
1621
1622 @example
1623 source [find target/FOOBAR.cfg]
1624 @end example
1625
1626 The point of a target config file is to package everything
1627 about a given chip that board config files need to know.
1628 In summary the target files should contain
1629
1630 @enumerate
1631 @item Set defaults
1632 @item Add TAPs to the scan chain
1633 @item Add CPU targets (includes GDB support)
1634 @item CPU/Chip/CPU-Core specific features
1635 @item On-Chip flash
1636 @end enumerate
1637
1638 As a rule of thumb, a target file sets up only one chip.
1639 For a microcontroller, that will often include a single TAP,
1640 which is a CPU needing a GDB target, and its on-chip flash.
1641
1642 More complex chips may include multiple TAPs, and the target
1643 config file may need to define them all before OpenOCD
1644 can talk to the chip.
1645 For example, some phone chips have JTAG scan chains that include
1646 an ARM core for operating system use, a DSP,
1647 another ARM core embedded in an image processing engine,
1648 and other processing engines.
1649
1650 @subsection Default Value Boiler Plate Code
1651
1652 All target configuration files should start with code like this,
1653 letting board config files express environment-specific
1654 differences in how things should be set up.
1655
1656 @example
1657 # Boards may override chip names, perhaps based on role,
1658 # but the default should match what the vendor uses
1659 if @{ [info exists CHIPNAME] @} @{
1660 set _CHIPNAME $CHIPNAME
1661 @} else @{
1662 set _CHIPNAME sam7x256
1663 @}
1664
1665 # ONLY use ENDIAN with targets that can change it.
1666 if @{ [info exists ENDIAN] @} @{
1667 set _ENDIAN $ENDIAN
1668 @} else @{
1669 set _ENDIAN little
1670 @}
1671
1672 # TAP identifiers may change as chips mature, for example with
1673 # new revision fields (the "3" here). Pick a good default; you
1674 # can pass several such identifiers to the "jtag newtap" command.
1675 if @{ [info exists CPUTAPID ] @} @{
1676 set _CPUTAPID $CPUTAPID
1677 @} else @{
1678 set _CPUTAPID 0x3f0f0f0f
1679 @}
1680 @end example
1681 @c but 0x3f0f0f0f is for an str73x part ...
1682
1683 @emph{Remember:} Board config files may include multiple target
1684 config files, or the same target file multiple times
1685 (changing at least @code{CHIPNAME}).
1686
1687 Likewise, the target configuration file should define
1688 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1689 use it later on when defining debug targets:
1690
1691 @example
1692 set _TARGETNAME $_CHIPNAME.cpu
1693 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1694 @end example
1695
1696 @subsection Adding TAPs to the Scan Chain
1697 After the ``defaults'' are set up,
1698 add the TAPs on each chip to the JTAG scan chain.
1699 @xref{TAP Declaration}, and the naming convention
1700 for taps.
1701
1702 In the simplest case the chip has only one TAP,
1703 probably for a CPU or FPGA.
1704 The config file for the Atmel AT91SAM7X256
1705 looks (in part) like this:
1706
1707 @example
1708 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1709 @end example
1710
1711 A board with two such at91sam7 chips would be able
1712 to source such a config file twice, with different
1713 values for @code{CHIPNAME}, so
1714 it adds a different TAP each time.
1715
1716 If there are nonzero @option{-expected-id} values,
1717 OpenOCD attempts to verify the actual tap id against those values.
1718 It will issue error messages if there is mismatch, which
1719 can help to pinpoint problems in OpenOCD configurations.
1720
1721 @example
1722 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1723 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1724 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1725 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1726 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1727 @end example
1728
1729 There are more complex examples too, with chips that have
1730 multiple TAPs. Ones worth looking at include:
1731
1732 @itemize
1733 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1734 plus a JRC to enable them
1735 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1736 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1737 is not currently used)
1738 @end itemize
1739
1740 @subsection Add CPU targets
1741
1742 After adding a TAP for a CPU, you should set it up so that
1743 GDB and other commands can use it.
1744 @xref{CPU Configuration}.
1745 For the at91sam7 example above, the command can look like this;
1746 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1747 to little endian, and this chip doesn't support changing that.
1748
1749 @example
1750 set _TARGETNAME $_CHIPNAME.cpu
1751 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1752 @end example
1753
1754 Work areas are small RAM areas associated with CPU targets.
1755 They are used by OpenOCD to speed up downloads,
1756 and to download small snippets of code to program flash chips.
1757 If the chip includes a form of ``on-chip-ram'' - and many do - define
1758 a work area if you can.
1759 Again using the at91sam7 as an example, this can look like:
1760
1761 @example
1762 $_TARGETNAME configure -work-area-phys 0x00200000 \
1763 -work-area-size 0x4000 -work-area-backup 0
1764 @end example
1765
1766 @anchor{definecputargetsworkinginsmp}
1767 @subsection Define CPU targets working in SMP
1768 @cindex SMP
1769 After setting targets, you can define a list of targets working in SMP.
1770
1771 @example
1772 set _TARGETNAME_1 $_CHIPNAME.cpu1
1773 set _TARGETNAME_2 $_CHIPNAME.cpu2
1774 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1775 -coreid 0 -dbgbase $_DAP_DBG1
1776 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1777 -coreid 1 -dbgbase $_DAP_DBG2
1778 #define 2 targets working in smp.
1779 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1780 @end example
1781 In the above example on cortex_a, 2 cpus are working in SMP.
1782 In SMP only one GDB instance is created and :
1783 @itemize @bullet
1784 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1785 @item halt command triggers the halt of all targets in the list.
1786 @item resume command triggers the write context and the restart of all targets in the list.
1787 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1788 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1789 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1790 @end itemize
1791
1792 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1793 command have been implemented.
1794 @itemize @bullet
1795 @item cortex_a smp on : enable SMP mode, behaviour is as described above.
1796 @item cortex_a smp off : disable SMP mode, the current target is the one
1797 displayed in the GDB session, only this target is now controlled by GDB
1798 session. This behaviour is useful during system boot up.
1799 @item cortex_a smp : display current SMP mode.
1800 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1801 following example.
1802 @end itemize
1803
1804 @example
1805 >cortex_a smp_gdb
1806 gdb coreid 0 -> -1
1807 #0 : coreid 0 is displayed to GDB ,
1808 #-> -1 : next resume triggers a real resume
1809 > cortex_a smp_gdb 1
1810 gdb coreid 0 -> 1
1811 #0 :coreid 0 is displayed to GDB ,
1812 #->1 : next resume displays coreid 1 to GDB
1813 > resume
1814 > cortex_a smp_gdb
1815 gdb coreid 1 -> 1
1816 #1 :coreid 1 is displayed to GDB ,
1817 #->1 : next resume displays coreid 1 to GDB
1818 > cortex_a smp_gdb -1
1819 gdb coreid 1 -> -1
1820 #1 :coreid 1 is displayed to GDB,
1821 #->-1 : next resume triggers a real resume
1822 @end example
1823
1824
1825 @subsection Chip Reset Setup
1826
1827 As a rule, you should put the @command{reset_config} command
1828 into the board file. Most things you think you know about a
1829 chip can be tweaked by the board.
1830
1831 Some chips have specific ways the TRST and SRST signals are
1832 managed. In the unusual case that these are @emph{chip specific}
1833 and can never be changed by board wiring, they could go here.
1834 For example, some chips can't support JTAG debugging without
1835 both signals.
1836
1837 Provide a @code{reset-assert} event handler if you can.
1838 Such a handler uses JTAG operations to reset the target,
1839 letting this target config be used in systems which don't
1840 provide the optional SRST signal, or on systems where you
1841 don't want to reset all targets at once.
1842 Such a handler might write to chip registers to force a reset,
1843 use a JRC to do that (preferable -- the target may be wedged!),
1844 or force a watchdog timer to trigger.
1845 (For Cortex-M targets, this is not necessary. The target
1846 driver knows how to use trigger an NVIC reset when SRST is
1847 not available.)
1848
1849 Some chips need special attention during reset handling if
1850 they're going to be used with JTAG.
1851 An example might be needing to send some commands right
1852 after the target's TAP has been reset, providing a
1853 @code{reset-deassert-post} event handler that writes a chip
1854 register to report that JTAG debugging is being done.
1855 Another would be reconfiguring the watchdog so that it stops
1856 counting while the core is halted in the debugger.
1857
1858 JTAG clocking constraints often change during reset, and in
1859 some cases target config files (rather than board config files)
1860 are the right places to handle some of those issues.
1861 For example, immediately after reset most chips run using a
1862 slower clock than they will use later.
1863 That means that after reset (and potentially, as OpenOCD
1864 first starts up) they must use a slower JTAG clock rate
1865 than they will use later.
1866 @xref{jtagspeed,,JTAG Speed}.
1867
1868 @quotation Important
1869 When you are debugging code that runs right after chip
1870 reset, getting these issues right is critical.
1871 In particular, if you see intermittent failures when
1872 OpenOCD verifies the scan chain after reset,
1873 look at how you are setting up JTAG clocking.
1874 @end quotation
1875
1876 @anchor{theinittargetsprocedure}
1877 @subsection The init_targets procedure
1878 @cindex init_targets procedure
1879
1880 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1881 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1882 procedure called @code{init_targets}, which will be executed when entering run stage
1883 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1884 Such procedure can be overridden by ``next level'' script (which sources the original).
1885 This concept facilitates code reuse when basic target config files provide generic configuration
1886 procedures and @code{init_targets} procedure, which can then be sourced and enhanced or changed in
1887 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1888 because sourcing them executes every initialization commands they provide.
1889
1890 @example
1891 ### generic_file.cfg ###
1892
1893 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1894 # basic initialization procedure ...
1895 @}
1896
1897 proc init_targets @{@} @{
1898 # initializes generic chip with 4kB of flash and 1kB of RAM
1899 setup_my_chip MY_GENERIC_CHIP 4096 1024
1900 @}
1901
1902 ### specific_file.cfg ###
1903
1904 source [find target/generic_file.cfg]
1905
1906 proc init_targets @{@} @{
1907 # initializes specific chip with 128kB of flash and 64kB of RAM
1908 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1909 @}
1910 @end example
1911
1912 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1913 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1914
1915 For an example of this scheme see LPC2000 target config files.
1916
1917 The @code{init_boards} procedure is a similar concept concerning board config files
1918 (@xref{theinitboardprocedure,,The init_board procedure}.)
1919
1920 @anchor{theinittargeteventsprocedure}
1921 @subsection The init_target_events procedure
1922 @cindex init_target_events procedure
1923
1924 A special procedure called @code{init_target_events} is run just after
1925 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1926 procedure}.) and before @code{init_board}
1927 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1928 to set up default target events for the targets that do not have those
1929 events already assigned.
1930
1931 @subsection ARM Core Specific Hacks
1932
1933 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1934 special high speed download features - enable it.
1935
1936 If present, the MMU, the MPU and the CACHE should be disabled.
1937
1938 Some ARM cores are equipped with trace support, which permits
1939 examination of the instruction and data bus activity. Trace
1940 activity is controlled through an ``Embedded Trace Module'' (ETM)
1941 on one of the core's scan chains. The ETM emits voluminous data
1942 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1943 If you are using an external trace port,
1944 configure it in your board config file.
1945 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1946 configure it in your target config file.
1947
1948 @example
1949 etm config $_TARGETNAME 16 normal full etb
1950 etb config $_TARGETNAME $_CHIPNAME.etb
1951 @end example
1952
1953 @subsection Internal Flash Configuration
1954
1955 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1956
1957 @b{Never ever} in the ``target configuration file'' define any type of
1958 flash that is external to the chip. (For example a BOOT flash on
1959 Chip Select 0.) Such flash information goes in a board file - not
1960 the TARGET (chip) file.
1961
1962 Examples:
1963 @itemize @bullet
1964 @item at91sam7x256 - has 256K flash YES enable it.
1965 @item str912 - has flash internal YES enable it.
1966 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1967 @item pxa270 - again - CS0 flash - it goes in the board file.
1968 @end itemize
1969
1970 @anchor{translatingconfigurationfiles}
1971 @section Translating Configuration Files
1972 @cindex translation
1973 If you have a configuration file for another hardware debugger
1974 or toolset (Abatron, BDI2000, BDI3000, CCS,
1975 Lauterbach, SEGGER, Macraigor, etc.), translating
1976 it into OpenOCD syntax is often quite straightforward. The most tricky
1977 part of creating a configuration script is oftentimes the reset init
1978 sequence where e.g. PLLs, DRAM and the like is set up.
1979
1980 One trick that you can use when translating is to write small
1981 Tcl procedures to translate the syntax into OpenOCD syntax. This
1982 can avoid manual translation errors and make it easier to
1983 convert other scripts later on.
1984
1985 Example of transforming quirky arguments to a simple search and
1986 replace job:
1987
1988 @example
1989 # Lauterbach syntax(?)
1990 #
1991 # Data.Set c15:0x042f %long 0x40000015
1992 #
1993 # OpenOCD syntax when using procedure below.
1994 #
1995 # setc15 0x01 0x00050078
1996
1997 proc setc15 @{regs value@} @{
1998 global TARGETNAME
1999
2000 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2001
2002 arm mcr 15 [expr ($regs>>12)&0x7] \
2003 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2004 [expr ($regs>>8)&0x7] $value
2005 @}
2006 @end example
2007
2008
2009
2010 @node Server Configuration
2011 @chapter Server Configuration
2012 @cindex initialization
2013 The commands here are commonly found in the openocd.cfg file and are
2014 used to specify what TCP/IP ports are used, and how GDB should be
2015 supported.
2016
2017 @anchor{configurationstage}
2018 @section Configuration Stage
2019 @cindex configuration stage
2020 @cindex config command
2021
2022 When the OpenOCD server process starts up, it enters a
2023 @emph{configuration stage} which is the only time that
2024 certain commands, @emph{configuration commands}, may be issued.
2025 Normally, configuration commands are only available
2026 inside startup scripts.
2027
2028 In this manual, the definition of a configuration command is
2029 presented as a @emph{Config Command}, not as a @emph{Command}
2030 which may be issued interactively.
2031 The runtime @command{help} command also highlights configuration
2032 commands, and those which may be issued at any time.
2033
2034 Those configuration commands include declaration of TAPs,
2035 flash banks,
2036 the interface used for JTAG communication,
2037 and other basic setup.
2038 The server must leave the configuration stage before it
2039 may access or activate TAPs.
2040 After it leaves this stage, configuration commands may no
2041 longer be issued.
2042
2043 @anchor{enteringtherunstage}
2044 @section Entering the Run Stage
2045
2046 The first thing OpenOCD does after leaving the configuration
2047 stage is to verify that it can talk to the scan chain
2048 (list of TAPs) which has been configured.
2049 It will warn if it doesn't find TAPs it expects to find,
2050 or finds TAPs that aren't supposed to be there.
2051 You should see no errors at this point.
2052 If you see errors, resolve them by correcting the
2053 commands you used to configure the server.
2054 Common errors include using an initial JTAG speed that's too
2055 fast, and not providing the right IDCODE values for the TAPs
2056 on the scan chain.
2057
2058 Once OpenOCD has entered the run stage, a number of commands
2059 become available.
2060 A number of these relate to the debug targets you may have declared.
2061 For example, the @command{mww} command will not be available until
2062 a target has been successfully instantiated.
2063 If you want to use those commands, you may need to force
2064 entry to the run stage.
2065
2066 @deffn {Config Command} {init}
2067 This command terminates the configuration stage and
2068 enters the run stage. This helps when you need to have
2069 the startup scripts manage tasks such as resetting the target,
2070 programming flash, etc. To reset the CPU upon startup, add "init" and
2071 "reset" at the end of the config script or at the end of the OpenOCD
2072 command line using the @option{-c} command line switch.
2073
2074 If this command does not appear in any startup/configuration file
2075 OpenOCD executes the command for you after processing all
2076 configuration files and/or command line options.
2077
2078 @b{NOTE:} This command normally occurs at or near the end of your
2079 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2080 targets ready. For example: If your openocd.cfg file needs to
2081 read/write memory on your target, @command{init} must occur before
2082 the memory read/write commands. This includes @command{nand probe}.
2083 @end deffn
2084
2085 @deffn {Overridable Procedure} {jtag_init}
2086 This is invoked at server startup to verify that it can talk
2087 to the scan chain (list of TAPs) which has been configured.
2088
2089 The default implementation first tries @command{jtag arp_init},
2090 which uses only a lightweight JTAG reset before examining the
2091 scan chain.
2092 If that fails, it tries again, using a harder reset
2093 from the overridable procedure @command{init_reset}.
2094
2095 Implementations must have verified the JTAG scan chain before
2096 they return.
2097 This is done by calling @command{jtag arp_init}
2098 (or @command{jtag arp_init-reset}).
2099 @end deffn
2100
2101 @anchor{tcpipports}
2102 @section TCP/IP Ports
2103 @cindex TCP port
2104 @cindex server
2105 @cindex port
2106 @cindex security
2107 The OpenOCD server accepts remote commands in several syntaxes.
2108 Each syntax uses a different TCP/IP port, which you may specify
2109 only during configuration (before those ports are opened).
2110
2111 For reasons including security, you may wish to prevent remote
2112 access using one or more of these ports.
2113 In such cases, just specify the relevant port number as "disabled".
2114 If you disable all access through TCP/IP, you will need to
2115 use the command line @option{-pipe} option.
2116
2117 @anchor{gdb_port}
2118 @deffn {Config Command} {gdb_port} [number]
2119 @cindex GDB server
2120 Normally gdb listens to a TCP/IP port, but GDB can also
2121 communicate via pipes(stdin/out or named pipes). The name
2122 "gdb_port" stuck because it covers probably more than 90% of
2123 the normal use cases.
2124
2125 No arguments reports GDB port. "pipe" means listen to stdin
2126 output to stdout, an integer is base port number, "disabled"
2127 disables the gdb server.
2128
2129 When using "pipe", also use log_output to redirect the log
2130 output to a file so as not to flood the stdin/out pipes.
2131
2132 Any other string is interpreted as named pipe to listen to.
2133 Output pipe is the same name as input pipe, but with 'o' appended,
2134 e.g. /var/gdb, /var/gdbo.
2135
2136 The GDB port for the first target will be the base port, the
2137 second target will listen on gdb_port + 1, and so on.
2138 When not specified during the configuration stage,
2139 the port @var{number} defaults to 3333.
2140 When @var{number} is not a numeric value, incrementing it to compute
2141 the next port number does not work. In this case, specify the proper
2142 @var{number} for each target by using the option @code{-gdb-port} of the
2143 commands @command{target create} or @command{$target_name configure}.
2144 @xref{gdbportoverride,,option -gdb-port}.
2145
2146 Note: when using "gdb_port pipe", increasing the default remote timeout in
2147 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2148 cause initialization to fail with "Unknown remote qXfer reply: OK".
2149 @end deffn
2150
2151 @deffn {Config Command} {tcl_port} [number]
2152 Specify or query the port used for a simplified RPC
2153 connection that can be used by clients to issue TCL commands and get the
2154 output from the Tcl engine.
2155 Intended as a machine interface.
2156 When not specified during the configuration stage,
2157 the port @var{number} defaults to 6666.
2158 When specified as "disabled", this service is not activated.
2159 @end deffn
2160
2161 @deffn {Config Command} {telnet_port} [number]
2162 Specify or query the
2163 port on which to listen for incoming telnet connections.
2164 This port is intended for interaction with one human through TCL commands.
2165 When not specified during the configuration stage,
2166 the port @var{number} defaults to 4444.
2167 When specified as "disabled", this service is not activated.
2168 @end deffn
2169
2170 @anchor{gdbconfiguration}
2171 @section GDB Configuration
2172 @cindex GDB
2173 @cindex GDB configuration
2174 You can reconfigure some GDB behaviors if needed.
2175 The ones listed here are static and global.
2176 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2177 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2178
2179 @anchor{gdbbreakpointoverride}
2180 @deffn {Command} {gdb_breakpoint_override} [@option{hard}|@option{soft}|@option{disable}]
2181 Force breakpoint type for gdb @command{break} commands.
2182 This option supports GDB GUIs which don't
2183 distinguish hard versus soft breakpoints, if the default OpenOCD and
2184 GDB behaviour is not sufficient. GDB normally uses hardware
2185 breakpoints if the memory map has been set up for flash regions.
2186 @end deffn
2187
2188 @anchor{gdbflashprogram}
2189 @deffn {Config Command} {gdb_flash_program} (@option{enable}|@option{disable})
2190 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2191 vFlash packet is received.
2192 The default behaviour is @option{enable}.
2193 @end deffn
2194
2195 @deffn {Config Command} {gdb_memory_map} (@option{enable}|@option{disable})
2196 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2197 requested. GDB will then know when to set hardware breakpoints, and program flash
2198 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2199 for flash programming to work.
2200 Default behaviour is @option{enable}.
2201 @xref{gdbflashprogram,,gdb_flash_program}.
2202 @end deffn
2203
2204 @deffn {Config Command} {gdb_report_data_abort} (@option{enable}|@option{disable})
2205 Specifies whether data aborts cause an error to be reported
2206 by GDB memory read packets.
2207 The default behaviour is @option{disable};
2208 use @option{enable} see these errors reported.
2209 @end deffn
2210
2211 @deffn {Config Command} {gdb_report_register_access_error} (@option{enable}|@option{disable})
2212 Specifies whether register accesses requested by GDB register read/write
2213 packets report errors or not.
2214 The default behaviour is @option{disable};
2215 use @option{enable} see these errors reported.
2216 @end deffn
2217
2218 @deffn {Config Command} {gdb_target_description} (@option{enable}|@option{disable})
2219 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2220 The default behaviour is @option{enable}.
2221 @end deffn
2222
2223 @deffn {Command} {gdb_save_tdesc}
2224 Saves the target description file to the local file system.
2225
2226 The file name is @i{target_name}.xml.
2227 @end deffn
2228
2229 @anchor{eventpolling}
2230 @section Event Polling
2231
2232 Hardware debuggers are parts of asynchronous systems,
2233 where significant events can happen at any time.
2234 The OpenOCD server needs to detect some of these events,
2235 so it can report them to through TCL command line
2236 or to GDB.
2237
2238 Examples of such events include:
2239
2240 @itemize
2241 @item One of the targets can stop running ... maybe it triggers
2242 a code breakpoint or data watchpoint, or halts itself.
2243 @item Messages may be sent over ``debug message'' channels ... many
2244 targets support such messages sent over JTAG,
2245 for receipt by the person debugging or tools.
2246 @item Loss of power ... some adapters can detect these events.
2247 @item Resets not issued through JTAG ... such reset sources
2248 can include button presses or other system hardware, sometimes
2249 including the target itself (perhaps through a watchdog).
2250 @item Debug instrumentation sometimes supports event triggering
2251 such as ``trace buffer full'' (so it can quickly be emptied)
2252 or other signals (to correlate with code behavior).
2253 @end itemize
2254
2255 None of those events are signaled through standard JTAG signals.
2256 However, most conventions for JTAG connectors include voltage
2257 level and system reset (SRST) signal detection.
2258 Some connectors also include instrumentation signals, which
2259 can imply events when those signals are inputs.
2260
2261 In general, OpenOCD needs to periodically check for those events,
2262 either by looking at the status of signals on the JTAG connector
2263 or by sending synchronous ``tell me your status'' JTAG requests
2264 to the various active targets.
2265 There is a command to manage and monitor that polling,
2266 which is normally done in the background.
2267
2268 @deffn {Command} {poll} [@option{on}|@option{off}]
2269 Poll the current target for its current state.
2270 (Also, @pxref{targetcurstate,,target curstate}.)
2271 If that target is in debug mode, architecture
2272 specific information about the current state is printed.
2273 An optional parameter
2274 allows background polling to be enabled and disabled.
2275
2276 You could use this from the TCL command shell, or
2277 from GDB using @command{monitor poll} command.
2278 Leave background polling enabled while you're using GDB.
2279 @example
2280 > poll
2281 background polling: on
2282 target state: halted
2283 target halted in ARM state due to debug-request, \
2284 current mode: Supervisor
2285 cpsr: 0x800000d3 pc: 0x11081bfc
2286 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2287 >
2288 @end example
2289 @end deffn
2290
2291 @node Debug Adapter Configuration
2292 @chapter Debug Adapter Configuration
2293 @cindex config file, interface
2294 @cindex interface config file
2295
2296 Correctly installing OpenOCD includes making your operating system give
2297 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2298 are used to select which one is used, and to configure how it is used.
2299
2300 @quotation Note
2301 Because OpenOCD started out with a focus purely on JTAG, you may find
2302 places where it wrongly presumes JTAG is the only transport protocol
2303 in use. Be aware that recent versions of OpenOCD are removing that
2304 limitation. JTAG remains more functional than most other transports.
2305 Other transports do not support boundary scan operations, or may be
2306 specific to a given chip vendor. Some might be usable only for
2307 programming flash memory, instead of also for debugging.
2308 @end quotation
2309
2310 Debug Adapters/Interfaces/Dongles are normally configured
2311 through commands in an interface configuration
2312 file which is sourced by your @file{openocd.cfg} file, or
2313 through a command line @option{-f interface/....cfg} option.
2314
2315 @example
2316 source [find interface/olimex-jtag-tiny.cfg]
2317 @end example
2318
2319 These commands tell
2320 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2321 A few cases are so simple that you only need to say what driver to use:
2322
2323 @example
2324 # jlink interface
2325 adapter driver jlink
2326 @end example
2327
2328 Most adapters need a bit more configuration than that.
2329
2330
2331 @section Adapter Configuration
2332
2333 The @command{adapter driver} command tells OpenOCD what type of debug adapter you are
2334 using. Depending on the type of adapter, you may need to use one or
2335 more additional commands to further identify or configure the adapter.
2336
2337 @deffn {Config Command} {adapter driver} name
2338 Use the adapter driver @var{name} to connect to the
2339 target.
2340 @end deffn
2341
2342 @deffn {Command} {adapter list}
2343 List the debug adapter drivers that have been built into
2344 the running copy of OpenOCD.
2345 @end deffn
2346 @deffn {Config Command} {adapter transports} transport_name+
2347 Specifies the transports supported by this debug adapter.
2348 The adapter driver builds-in similar knowledge; use this only
2349 when external configuration (such as jumpering) changes what
2350 the hardware can support.
2351 @end deffn
2352
2353
2354
2355 @deffn {Command} {adapter name}
2356 Returns the name of the debug adapter driver being used.
2357 @end deffn
2358
2359 @anchor{adapter_usb_location}
2360 @deffn {Config Command} {adapter usb location} [<bus>-<port>[.<port>]...]
2361 Displays or specifies the physical USB port of the adapter to use. The path
2362 roots at @var{bus} and walks down the physical ports, with each
2363 @var{port} option specifying a deeper level in the bus topology, the last
2364 @var{port} denoting where the target adapter is actually plugged.
2365 The USB bus topology can be queried with the command @emph{lsusb -t} or @emph{dmesg}.
2366
2367 This command is only available if your libusb1 is at least version 1.0.16.
2368 @end deffn
2369
2370 @section Interface Drivers
2371
2372 Each of the interface drivers listed here must be explicitly
2373 enabled when OpenOCD is configured, in order to be made
2374 available at run time.
2375
2376 @deffn {Interface Driver} {amt_jtagaccel}
2377 Amontec Chameleon in its JTAG Accelerator configuration,
2378 connected to a PC's EPP mode parallel port.
2379 This defines some driver-specific commands:
2380
2381 @deffn {Config Command} {parport port} number
2382 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2383 the number of the @file{/dev/parport} device.
2384 @end deffn
2385
2386 @deffn {Config Command} {rtck} [@option{enable}|@option{disable}]
2387 Displays status of RTCK option.
2388 Optionally sets that option first.
2389 @end deffn
2390 @end deffn
2391
2392 @deffn {Interface Driver} {arm-jtag-ew}
2393 Olimex ARM-JTAG-EW USB adapter
2394 This has one driver-specific command:
2395
2396 @deffn {Command} {armjtagew_info}
2397 Logs some status
2398 @end deffn
2399 @end deffn
2400
2401 @deffn {Interface Driver} {at91rm9200}
2402 Supports bitbanged JTAG from the local system,
2403 presuming that system is an Atmel AT91rm9200
2404 and a specific set of GPIOs is used.
2405 @c command: at91rm9200_device NAME
2406 @c chooses among list of bit configs ... only one option
2407 @end deffn
2408
2409 @deffn {Interface Driver} {cmsis-dap}
2410 ARM CMSIS-DAP compliant based adapter v1 (USB HID based)
2411 or v2 (USB bulk).
2412
2413 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2414 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2415 the driver will attempt to auto detect the CMSIS-DAP device.
2416 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2417 @example
2418 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2419 @end example
2420 @end deffn
2421
2422 @deffn {Config Command} {cmsis_dap_serial} [serial]
2423 Specifies the @var{serial} of the CMSIS-DAP device to use.
2424 If not specified, serial numbers are not considered.
2425 @end deffn
2426
2427 @deffn {Config Command} {cmsis_dap_backend} [@option{auto}|@option{usb_bulk}|@option{hid}]
2428 Specifies how to communicate with the adapter:
2429
2430 @itemize @minus
2431 @item @option{hid} Use HID generic reports - CMSIS-DAP v1
2432 @item @option{usb_bulk} Use USB bulk - CMSIS-DAP v2
2433 @item @option{auto} First try USB bulk CMSIS-DAP v2, if not found try HID CMSIS-DAP v1.
2434 This is the default if @command{cmsis_dap_backend} is not specified.
2435 @end itemize
2436 @end deffn
2437
2438 @deffn {Config Command} {cmsis_dap_usb interface} [number]
2439 Specifies the @var{number} of the USB interface to use in v2 mode (USB bulk).
2440 In most cases need not to be specified and interfaces are searched by
2441 interface string or for user class interface.
2442 @end deffn
2443
2444 @deffn {Command} {cmsis-dap info}
2445 Display various device information, like hardware version, firmware version, current bus status.
2446 @end deffn
2447 @end deffn
2448
2449 @deffn {Interface Driver} {dummy}
2450 A dummy software-only driver for debugging.
2451 @end deffn
2452
2453 @deffn {Interface Driver} {ep93xx}
2454 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2455 @end deffn
2456
2457 @deffn {Interface Driver} {ftdi}
2458 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2459 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2460
2461 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2462 bypassing intermediate libraries like libftdi or D2XX.
2463
2464 Support for new FTDI based adapters can be added completely through
2465 configuration files, without the need to patch and rebuild OpenOCD.
2466
2467 The driver uses a signal abstraction to enable Tcl configuration files to
2468 define outputs for one or several FTDI GPIO. These outputs can then be
2469 controlled using the @command{ftdi set_signal} command. Special signal names
2470 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2471 will be used for their customary purpose. Inputs can be read using the
2472 @command{ftdi get_signal} command.
2473
2474 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2475 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2476 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2477 required by the protocol, to tell the adapter to drive the data output onto
2478 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2479
2480 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2481 be controlled differently. In order to support tristateable signals such as
2482 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2483 signal. The following output buffer configurations are supported:
2484
2485 @itemize @minus
2486 @item Push-pull with one FTDI output as (non-)inverted data line
2487 @item Open drain with one FTDI output as (non-)inverted output-enable
2488 @item Tristate with one FTDI output as (non-)inverted data line and another
2489 FTDI output as (non-)inverted output-enable
2490 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2491 switching data and direction as necessary
2492 @end itemize
2493
2494 These interfaces have several commands, used to configure the driver
2495 before initializing the JTAG scan chain:
2496
2497 @deffn {Config Command} {ftdi vid_pid} [vid pid]+
2498 The vendor ID and product ID of the adapter. Up to eight
2499 [@var{vid}, @var{pid}] pairs may be given, e.g.
2500 @example
2501 ftdi vid_pid 0x0403 0xcff8 0x15ba 0x0003
2502 @end example
2503 @end deffn
2504
2505 @deffn {Config Command} {ftdi device_desc} description
2506 Provides the USB device description (the @emph{iProduct string})
2507 of the adapter. If not specified, the device description is ignored
2508 during device selection.
2509 @end deffn
2510
2511 @deffn {Config Command} {ftdi serial} serial-number
2512 Specifies the @var{serial-number} of the adapter to use,
2513 in case the vendor provides unique IDs and more than one adapter
2514 is connected to the host.
2515 If not specified, serial numbers are not considered.
2516 (Note that USB serial numbers can be arbitrary Unicode strings,
2517 and are not restricted to containing only decimal digits.)
2518 @end deffn
2519
2520 @deffn {Config Command} {ftdi channel} channel
2521 Selects the channel of the FTDI device to use for MPSSE operations. Most
2522 adapters use the default, channel 0, but there are exceptions.
2523 @end deffn
2524
2525 @deffn {Config Command} {ftdi layout_init} data direction
2526 Specifies the initial values of the FTDI GPIO data and direction registers.
2527 Each value is a 16-bit number corresponding to the concatenation of the high
2528 and low FTDI GPIO registers. The values should be selected based on the
2529 schematics of the adapter, such that all signals are set to safe levels with
2530 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2531 and initially asserted reset signals.
2532 @end deffn
2533
2534 @deffn {Command} {ftdi layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2535 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2536 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2537 register bitmasks to tell the driver the connection and type of the output
2538 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2539 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2540 used with inverting data inputs and @option{-data} with non-inverting inputs.
2541 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2542 not-output-enable) input to the output buffer is connected. The options
2543 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2544 with the method @command{ftdi get_signal}.
2545
2546 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2547 simple open-collector transistor driver would be specified with @option{-oe}
2548 only. In that case the signal can only be set to drive low or to Hi-Z and the
2549 driver will complain if the signal is set to drive high. Which means that if
2550 it's a reset signal, @command{reset_config} must be specified as
2551 @option{srst_open_drain}, not @option{srst_push_pull}.
2552
2553 A special case is provided when @option{-data} and @option{-oe} is set to the
2554 same bitmask. Then the FTDI pin is considered being connected straight to the
2555 target without any buffer. The FTDI pin is then switched between output and
2556 input as necessary to provide the full set of low, high and Hi-Z
2557 characteristics. In all other cases, the pins specified in a signal definition
2558 are always driven by the FTDI.
2559
2560 If @option{-alias} or @option{-nalias} is used, the signal is created
2561 identical (or with data inverted) to an already specified signal
2562 @var{name}.
2563 @end deffn
2564
2565 @deffn {Command} {ftdi set_signal} name @option{0}|@option{1}|@option{z}
2566 Set a previously defined signal to the specified level.
2567 @itemize @minus
2568 @item @option{0}, drive low
2569 @item @option{1}, drive high
2570 @item @option{z}, set to high-impedance
2571 @end itemize
2572 @end deffn
2573
2574 @deffn {Command} {ftdi get_signal} name
2575 Get the value of a previously defined signal.
2576 @end deffn
2577
2578 @deffn {Command} {ftdi tdo_sample_edge} @option{rising}|@option{falling}
2579 Configure TCK edge at which the adapter samples the value of the TDO signal
2580
2581 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2582 peculiar at high JTAG clock speeds. However, FTDI chips offer a possibility to sample
2583 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2584 stability at higher JTAG clocks.
2585 @itemize @minus
2586 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2587 @item @option{falling}, sample TDO on falling edge of TCK
2588 @end itemize
2589 @end deffn
2590
2591 For example adapter definitions, see the configuration files shipped in the
2592 @file{interface/ftdi} directory.
2593
2594 @end deffn
2595
2596 @deffn {Interface Driver} {ft232r}
2597 This driver is implementing synchronous bitbang mode of an FTDI FT232R,
2598 FT230X, FT231X and similar USB UART bridge ICs by reusing RS232 signals as GPIO.
2599 It currently doesn't support using CBUS pins as GPIO.
2600
2601 List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
2602 @itemize @minus
2603 @item RXD(5) - TDI
2604 @item TXD(1) - TCK
2605 @item RTS(3) - TDO
2606 @item CTS(11) - TMS
2607 @item DTR(2) - TRST
2608 @item DCD(10) - SRST
2609 @end itemize
2610
2611 User can change default pinout by supplying configuration
2612 commands with GPIO numbers or RS232 signal names.
2613 GPIO numbers correspond to bit numbers in FTDI GPIO register.
2614 They differ from physical pin numbers.
2615 For details see actual FTDI chip datasheets.
2616 Every JTAG line must be configured to unique GPIO number
2617 different than any other JTAG line, even those lines
2618 that are sometimes not used like TRST or SRST.
2619
2620 FT232R
2621 @itemize @minus
2622 @item bit 7 - RI
2623 @item bit 6 - DCD
2624 @item bit 5 - DSR
2625 @item bit 4 - DTR
2626 @item bit 3 - CTS
2627 @item bit 2 - RTS
2628 @item bit 1 - RXD
2629 @item bit 0 - TXD
2630 @end itemize
2631
2632 These interfaces have several commands, used to configure the driver
2633 before initializing the JTAG scan chain:
2634
2635 @deffn {Config Command} {ft232r vid_pid} @var{vid} @var{pid}
2636 The vendor ID and product ID of the adapter. If not specified, default
2637 0x0403:0x6001 is used.
2638 @end deffn
2639
2640 @deffn {Config Command} {ft232r serial_desc} @var{serial}
2641 Specifies the @var{serial} of the adapter to use, in case the
2642 vendor provides unique IDs and more than one adapter is connected to
2643 the host. If not specified, serial numbers are not considered.
2644 @end deffn
2645
2646 @deffn {Config Command} {ft232r jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
2647 Set four JTAG GPIO numbers at once.
2648 If not specified, default 0 3 1 2 or TXD CTS RXD RTS is used.
2649 @end deffn
2650
2651 @deffn {Config Command} {ft232r tck_num} @var{tck}
2652 Set TCK GPIO number. If not specified, default 0 or TXD is used.
2653 @end deffn
2654
2655 @deffn {Config Command} {ft232r tms_num} @var{tms}
2656 Set TMS GPIO number. If not specified, default 3 or CTS is used.
2657 @end deffn
2658
2659 @deffn {Config Command} {ft232r tdi_num} @var{tdi}
2660 Set TDI GPIO number. If not specified, default 1 or RXD is used.
2661 @end deffn
2662
2663 @deffn {Config Command} {ft232r tdo_num} @var{tdo}
2664 Set TDO GPIO number. If not specified, default 2 or RTS is used.
2665 @end deffn
2666
2667 @deffn {Config Command} {ft232r trst_num} @var{trst}
2668 Set TRST GPIO number. If not specified, default 4 or DTR is used.
2669 @end deffn
2670
2671 @deffn {Config Command} {ft232r srst_num} @var{srst}
2672 Set SRST GPIO number. If not specified, default 6 or DCD is used.
2673 @end deffn
2674
2675 @deffn {Config Command} {ft232r restore_serial} @var{word}
2676 Restore serial port after JTAG. This USB bitmode control word
2677 (16-bit) will be sent before quit. Lower byte should
2678 set GPIO direction register to a "sane" state:
2679 0x15 for TXD RTS DTR as outputs (1), others as inputs (0). Higher
2680 byte is usually 0 to disable bitbang mode.
2681 When kernel driver reattaches, serial port should continue to work.
2682 Value 0xFFFF disables sending control word and serial port,
2683 then kernel driver will not reattach.
2684 If not specified, default 0xFFFF is used.
2685 @end deffn
2686
2687 @end deffn
2688
2689 @deffn {Interface Driver} {remote_bitbang}
2690 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2691 with a remote process and sends ASCII encoded bitbang requests to that process
2692 instead of directly driving JTAG.
2693
2694 The remote_bitbang driver is useful for debugging software running on
2695 processors which are being simulated.
2696
2697 @deffn {Config Command} {remote_bitbang port} number
2698 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2699 sockets instead of TCP.
2700 @end deffn
2701
2702 @deffn {Config Command} {remote_bitbang host} hostname
2703 Specifies the hostname of the remote process to connect to using TCP, or the
2704 name of the UNIX socket to use if remote_bitbang port is 0.
2705 @end deffn
2706
2707 For example, to connect remotely via TCP to the host foobar you might have
2708 something like:
2709
2710 @example
2711 adapter driver remote_bitbang
2712 remote_bitbang port 3335
2713 remote_bitbang host foobar
2714 @end example
2715
2716 To connect to another process running locally via UNIX sockets with socket
2717 named mysocket:
2718
2719 @example
2720 adapter driver remote_bitbang
2721 remote_bitbang port 0
2722 remote_bitbang host mysocket
2723 @end example
2724 @end deffn
2725
2726 @deffn {Interface Driver} {usb_blaster}
2727 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2728 for FTDI chips. These interfaces have several commands, used to
2729 configure the driver before initializing the JTAG scan chain:
2730
2731 @deffn {Config Command} {usb_blaster device_desc} description
2732 Provides the USB device description (the @emph{iProduct string})
2733 of the FTDI FT245 device. If not
2734 specified, the FTDI default value is used. This setting is only valid
2735 if compiled with FTD2XX support.
2736 @end deffn
2737
2738 @deffn {Config Command} {usb_blaster vid_pid} vid pid
2739 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2740 default values are used.
2741 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2742 Altera USB-Blaster (default):
2743 @example
2744 usb_blaster vid_pid 0x09FB 0x6001
2745 @end example
2746 The following VID/PID is for Kolja Waschk's USB JTAG:
2747 @example
2748 usb_blaster vid_pid 0x16C0 0x06AD
2749 @end example
2750 @end deffn
2751
2752 @deffn {Command} {usb_blaster pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2753 Sets the state or function of the unused GPIO pins on USB-Blasters
2754 (pins 6 and 8 on the female JTAG header). These pins can be used as
2755 SRST and/or TRST provided the appropriate connections are made on the
2756 target board.
2757
2758 For example, to use pin 6 as SRST:
2759 @example
2760 usb_blaster pin pin6 s
2761 reset_config srst_only
2762 @end example
2763 @end deffn
2764
2765 @deffn {Config Command} {usb_blaster lowlevel_driver} (@option{ftdi}|@option{ublast2})
2766 Chooses the low level access method for the adapter. If not specified,
2767 @option{ftdi} is selected unless it wasn't enabled during the
2768 configure stage. USB-Blaster II needs @option{ublast2}.
2769 @end deffn
2770
2771 @deffn {Config Command} {usb_blaster firmware} @var{path}
2772 This command specifies @var{path} to access USB-Blaster II firmware
2773 image. To be used with USB-Blaster II only.
2774 @end deffn
2775
2776 @end deffn
2777
2778 @deffn {Interface Driver} {gw16012}
2779 Gateworks GW16012 JTAG programmer.
2780 This has one driver-specific command:
2781
2782 @deffn {Config Command} {parport port} [port_number]
2783 Display either the address of the I/O port
2784 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2785 If a parameter is provided, first switch to use that port.
2786 This is a write-once setting.
2787 @end deffn
2788 @end deffn
2789
2790 @deffn {Interface Driver} {jlink}
2791 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2792 transports.
2793
2794 @quotation Compatibility Note
2795 SEGGER released many firmware versions for the many hardware versions they
2796 produced. OpenOCD was extensively tested and intended to run on all of them,
2797 but some combinations were reported as incompatible. As a general
2798 recommendation, it is advisable to use the latest firmware version
2799 available for each hardware version. However the current V8 is a moving
2800 target, and SEGGER firmware versions released after the OpenOCD was
2801 released may not be compatible. In such cases it is recommended to
2802 revert to the last known functional version. For 0.5.0, this is from
2803 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2804 version is from "May 3 2012 18:36:22", packed with 4.46f.
2805 @end quotation
2806
2807 @deffn {Command} {jlink hwstatus}
2808 Display various hardware related information, for example target voltage and pin
2809 states.
2810 @end deffn
2811 @deffn {Command} {jlink freemem}
2812 Display free device internal memory.
2813 @end deffn
2814 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2815 Set the JTAG command version to be used. Without argument, show the actual JTAG
2816 command version.
2817 @end deffn
2818 @deffn {Command} {jlink config}
2819 Display the device configuration.
2820 @end deffn
2821 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2822 Set the target power state on JTAG-pin 19. Without argument, show the target
2823 power state.
2824 @end deffn
2825 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2826 Set the MAC address of the device. Without argument, show the MAC address.
2827 @end deffn
2828 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2829 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2830 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2831 IP configuration.
2832 @end deffn
2833 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2834 Set the USB address of the device. This will also change the USB Product ID
2835 (PID) of the device. Without argument, show the USB address.
2836 @end deffn
2837 @deffn {Command} {jlink config reset}
2838 Reset the current configuration.
2839 @end deffn
2840 @deffn {Command} {jlink config write}
2841 Write the current configuration to the internal persistent storage.
2842 @end deffn
2843 @deffn {Command} {jlink emucom write <channel> <data>}
2844 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2845 pairs.
2846
2847 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2848 the EMUCOM channel 0x10:
2849 @example
2850 > jlink emucom write 0x10 aa0b23
2851 @end example
2852 @end deffn
2853 @deffn {Command} {jlink emucom read <channel> <length>}
2854 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2855 pairs.
2856
2857 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2858 @example
2859 > jlink emucom read 0x0 4
2860 77a90000
2861 @end example
2862 @end deffn
2863 @deffn {Config Command} {jlink usb} <@option{0} to @option{3}>
2864 Set the USB address of the interface, in case more than one adapter is connected
2865 to the host. If not specified, USB addresses are not considered. Device
2866 selection via USB address is not always unambiguous. It is recommended to use
2867 the serial number instead, if possible.
2868
2869 As a configuration command, it can be used only before 'init'.
2870 @end deffn
2871 @deffn {Config Command} {jlink serial} <serial number>
2872 Set the serial number of the interface, in case more than one adapter is
2873 connected to the host. If not specified, serial numbers are not considered.
2874
2875 As a configuration command, it can be used only before 'init'.
2876 @end deffn
2877 @end deffn
2878
2879 @deffn {Interface Driver} {kitprog}
2880 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2881 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2882 families, but it is possible to use it with some other devices. If you are using
2883 this adapter with a PSoC or a PRoC, you may need to add
2884 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2885 configuration script.
2886
2887 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2888 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2889 be used with this driver, and must either be used with the cmsis-dap driver or
2890 switched back to KitProg mode. See the Cypress KitProg User Guide for
2891 instructions on how to switch KitProg modes.
2892
2893 Known limitations:
2894 @itemize @bullet
2895 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2896 and 2.7 MHz.
2897 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2898 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2899 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2900 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2901 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2902 SWD sequence must be sent after every target reset in order to re-establish
2903 communications with the target.
2904 @item Due in part to the limitation above, KitProg devices with firmware below
2905 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
2906 communicate with PSoC 5LP devices. This is because, assuming debug is not
2907 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
2908 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
2909 could only be sent with an acquisition sequence.
2910 @end itemize
2911
2912 @deffn {Config Command} {kitprog_init_acquire_psoc}
2913 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
2914 Please be aware that the acquisition sequence hard-resets the target.
2915 @end deffn
2916
2917 @deffn {Config Command} {kitprog_serial} serial
2918 Select a KitProg device by its @var{serial}. If left unspecified, the first
2919 device detected by OpenOCD will be used.
2920 @end deffn
2921
2922 @deffn {Command} {kitprog acquire_psoc}
2923 Run a PSoC acquisition sequence immediately. Typically, this should not be used
2924 outside of the target-specific configuration scripts since it hard-resets the
2925 target as a side-effect.
2926 This is necessary for "reset halt" on some PSoC 4 series devices.
2927 @end deffn
2928
2929 @deffn {Command} {kitprog info}
2930 Display various adapter information, such as the hardware version, firmware
2931 version, and target voltage.
2932 @end deffn
2933 @end deffn
2934
2935 @deffn {Interface Driver} {parport}
2936 Supports PC parallel port bit-banging cables:
2937 Wigglers, PLD download cable, and more.
2938 These interfaces have several commands, used to configure the driver
2939 before initializing the JTAG scan chain:
2940
2941 @deffn {Config Command} {parport cable} name
2942 Set the layout of the parallel port cable used to connect to the target.
2943 This is a write-once setting.
2944 Currently valid cable @var{name} values include:
2945
2946 @itemize @minus
2947 @item @b{altium} Altium Universal JTAG cable.
2948 @item @b{arm-jtag} Same as original wiggler except SRST and
2949 TRST connections reversed and TRST is also inverted.
2950 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2951 in configuration mode. This is only used to
2952 program the Chameleon itself, not a connected target.
2953 @item @b{dlc5} The Xilinx Parallel cable III.
2954 @item @b{flashlink} The ST Parallel cable.
2955 @item @b{lattice} Lattice ispDOWNLOAD Cable
2956 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2957 some versions of
2958 Amontec's Chameleon Programmer. The new version available from
2959 the website uses the original Wiggler layout ('@var{wiggler}')
2960 @item @b{triton} The parallel port adapter found on the
2961 ``Karo Triton 1 Development Board''.
2962 This is also the layout used by the HollyGates design
2963 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2964 @item @b{wiggler} The original Wiggler layout, also supported by
2965 several clones, such as the Olimex ARM-JTAG
2966 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2967 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2968 @end itemize
2969 @end deffn
2970
2971 @deffn {Config Command} {parport port} [port_number]
2972 Display either the address of the I/O port
2973 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2974 If a parameter is provided, first switch to use that port.
2975 This is a write-once setting.
2976
2977 When using PPDEV to access the parallel port, use the number of the parallel port:
2978 @option{parport port 0} (the default). If @option{parport port 0x378} is specified
2979 you may encounter a problem.
2980 @end deffn
2981
2982 @deffn {Config Command} {parport toggling_time} [nanoseconds]
2983 Displays how many nanoseconds the hardware needs to toggle TCK;
2984 the parport driver uses this value to obey the
2985 @command{adapter speed} configuration.
2986 When the optional @var{nanoseconds} parameter is given,
2987 that setting is changed before displaying the current value.
2988
2989 The default setting should work reasonably well on commodity PC hardware.
2990 However, you may want to calibrate for your specific hardware.
2991 @quotation Tip
2992 To measure the toggling time with a logic analyzer or a digital storage
2993 oscilloscope, follow the procedure below:
2994 @example
2995 > parport toggling_time 1000
2996 > adapter speed 500
2997 @end example
2998 This sets the maximum JTAG clock speed of the hardware, but
2999 the actual speed probably deviates from the requested 500 kHz.
3000 Now, measure the time between the two closest spaced TCK transitions.
3001 You can use @command{runtest 1000} or something similar to generate a
3002 large set of samples.
3003 Update the setting to match your measurement:
3004 @example
3005 > parport toggling_time <measured nanoseconds>
3006 @end example
3007 Now the clock speed will be a better match for @command{adapter speed}
3008 command given in OpenOCD scripts and event handlers.
3009
3010 You can do something similar with many digital multimeters, but note
3011 that you'll probably need to run the clock continuously for several
3012 seconds before it decides what clock rate to show. Adjust the
3013 toggling time up or down until the measured clock rate is a good
3014 match with the rate you specified in the @command{adapter speed} command;
3015 be conservative.
3016 @end quotation
3017 @end deffn
3018
3019 @deffn {Config Command} {parport write_on_exit} (@option{on}|@option{off})
3020 This will configure the parallel driver to write a known
3021 cable-specific value to the parallel interface on exiting OpenOCD.
3022 @end deffn
3023
3024 For example, the interface configuration file for a
3025 classic ``Wiggler'' cable on LPT2 might look something like this:
3026
3027 @example
3028 adapter driver parport
3029 parport port 0x278
3030 parport cable wiggler
3031 @end example
3032 @end deffn
3033
3034 @deffn {Interface Driver} {presto}
3035 ASIX PRESTO USB JTAG programmer.
3036 @deffn {Config Command} {presto serial} serial_string
3037 Configures the USB serial number of the Presto device to use.
3038 @end deffn
3039 @end deffn
3040
3041 @deffn {Interface Driver} {rlink}
3042 Raisonance RLink USB adapter
3043 @end deffn
3044
3045 @deffn {Interface Driver} {usbprog}
3046 usbprog is a freely programmable USB adapter.
3047 @end deffn
3048
3049 @deffn {Interface Driver} {vsllink}
3050 vsllink is part of Versaloon which is a versatile USB programmer.
3051
3052 @quotation Note
3053 This defines quite a few driver-specific commands,
3054 which are not currently documented here.
3055 @end quotation
3056 @end deffn
3057
3058 @anchor{hla_interface}
3059 @deffn {Interface Driver} {hla}
3060 This is a driver that supports multiple High Level Adapters.
3061 This type of adapter does not expose some of the lower level api's
3062 that OpenOCD would normally use to access the target.
3063
3064 Currently supported adapters include the STMicroelectronics ST-LINK, TI ICDI
3065 and Nuvoton Nu-Link.
3066 ST-LINK firmware version >= V2.J21.S4 recommended due to issues with earlier
3067 versions of firmware where serial number is reset after first use. Suggest
3068 using ST firmware update utility to upgrade ST-LINK firmware even if current
3069 version reported is V2.J21.S4.
3070
3071 @deffn {Config Command} {hla_device_desc} description
3072 Currently Not Supported.
3073 @end deffn
3074
3075 @deffn {Config Command} {hla_serial} serial
3076 Specifies the serial number of the adapter.
3077 @end deffn
3078
3079 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi}|@option{nulink})
3080 Specifies the adapter layout to use.
3081 @end deffn
3082
3083 @deffn {Config Command} {hla_vid_pid} [vid pid]+
3084 Pairs of vendor IDs and product IDs of the device.
3085 @end deffn
3086
3087 @deffn {Config Command} {hla_stlink_backend} (usb | tcp [port])
3088 @emph{ST-Link only:} Choose between 'exclusive' USB communication (the default backend) or
3089 'shared' mode using ST-Link TCP server (the default port is 7184).
3090
3091 @emph{Note:} ST-Link TCP server is a binary application provided by ST
3092 available from @url{https://www.st.com/en/development-tools/st-link-server.html,
3093 ST-LINK server software module}.
3094 @end deffn
3095
3096 @deffn {Command} {hla_command} command
3097 Execute a custom adapter-specific command. The @var{command} string is
3098 passed as is to the underlying adapter layout handler.
3099 @end deffn
3100 @end deffn
3101
3102 @anchor{st_link_dap_interface}
3103 @deffn {Interface Driver} {st-link}
3104 This is a driver that supports STMicroelectronics adapters ST-LINK/V2
3105 (from firmware V2J24) and STLINK-V3, thanks to a new API that provides
3106 directly access the arm ADIv5 DAP.
3107
3108 The new API provide access to multiple AP on the same DAP, but the
3109 maximum number of the AP port is limited by the specific firmware version
3110 (e.g. firmware V2J29 has 3 as maximum AP number, while V2J32 has 8).
3111 An error is returned for any AP number above the maximum allowed value.
3112
3113 @emph{Note:} Either these same adapters and their older versions are
3114 also supported by @ref{hla_interface, the hla interface driver}.
3115
3116 @deffn {Config Command} {st-link backend} (usb | tcp [port])
3117 Choose between 'exclusive' USB communication (the default backend) or
3118 'shared' mode using ST-Link TCP server (the default port is 7184).
3119
3120 @emph{Note:} ST-Link TCP server is a binary application provided by ST
3121 available from @url{https://www.st.com/en/development-tools/st-link-server.html,
3122 ST-LINK server software module}.
3123
3124 @emph{Note:} ST-Link TCP server does not support the SWIM transport.
3125 @end deffn
3126
3127 @deffn {Config Command} {st-link serial} serial
3128 Specifies the serial number of the adapter.
3129 @end deffn
3130
3131 @deffn {Config Command} {st-link vid_pid} [vid pid]+
3132 Pairs of vendor IDs and product IDs of the device.
3133 @end deffn
3134 @end deffn
3135
3136 @deffn {Interface Driver} {opendous}
3137 opendous-jtag is a freely programmable USB adapter.
3138 @end deffn
3139
3140 @deffn {Interface Driver} {ulink}
3141 This is the Keil ULINK v1 JTAG debugger.
3142 @end deffn
3143
3144 @deffn {Interface Driver} {xds110}
3145 The XDS110 is included as the embedded debug probe on many Texas Instruments
3146 LaunchPad evaluation boards. The XDS110 is also available as a stand-alone USB
3147 debug probe with the added capability to supply power to the target board. The
3148 following commands are supported by the XDS110 driver:
3149
3150 @deffn {Config Command} {xds110 serial} serial_string
3151 Specifies the serial number of which XDS110 probe to use. Otherwise, the first
3152 XDS110 found will be used.
3153 @end deffn
3154
3155 @deffn {Config Command} {xds110 supply} voltage_in_millivolts
3156 Available only on the XDS110 stand-alone probe. Sets the voltage level of the
3157 XDS110 power supply. A value of 0 leaves the supply off. Otherwise, the supply
3158 can be set to any value in the range 1800 to 3600 millivolts.
3159 @end deffn
3160
3161 @deffn {Command} {xds110 info}
3162 Displays information about the connected XDS110 debug probe (e.g. firmware
3163 version).
3164 @end deffn
3165 @end deffn
3166
3167 @deffn {Interface Driver} {xlnx_pcie_xvc}
3168 This driver supports the Xilinx Virtual Cable (XVC) over PCI Express.
3169 It is commonly found in Xilinx based PCI Express designs. It allows debugging
3170 fabric based JTAG/SWD devices such as Cortex-M1/M3 microcontrollers. Access to this is
3171 exposed via extended capability registers in the PCI Express configuration space.
3172
3173 For more information see Xilinx PG245 (Section on From_PCIE_to_JTAG mode).
3174
3175 @deffn {Config Command} {xlnx_pcie_xvc config} device
3176 Specifies the PCI Express device via parameter @var{device} to use.
3177
3178 The correct value for @var{device} can be obtained by looking at the output
3179 of lscpi -D (first column) for the corresponding device.
3180
3181 The string will be of the format "DDDD:BB:SS.F" such as "0000:65:00.1".
3182
3183 @end deffn
3184 @end deffn
3185
3186 @deffn {Interface Driver} {bcm2835gpio}
3187 This SoC is present in Raspberry Pi which is a cheap single-board computer
3188 exposing some GPIOs on its expansion header.
3189
3190 The driver accesses memory-mapped GPIO peripheral registers directly
3191 for maximum performance, but the only possible race condition is for
3192 the pins' modes/muxing (which is highly unlikely), so it should be
3193 able to coexist nicely with both sysfs bitbanging and various
3194 peripherals' kernel drivers. The driver restores the previous
3195 configuration on exit.
3196
3197 See @file{interface/raspberrypi-native.cfg} for a sample config and
3198 pinout.
3199
3200 @deffn {Config Command} {bcm2835gpio jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
3201 Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order).
3202 Must be specified to enable JTAG transport. These pins can also be specified
3203 individually.
3204 @end deffn
3205
3206 @deffn {Config Command} {bcm2835gpio tck_num} @var{tck}
3207 Set TCK GPIO number. Must be specified to enable JTAG transport. Can also be
3208 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3209 @end deffn
3210
3211 @deffn {Config Command} {bcm2835gpio tms_num} @var{tms}
3212 Set TMS GPIO number. Must be specified to enable JTAG transport. Can also be
3213 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3214 @end deffn
3215
3216 @deffn {Config Command} {bcm2835gpio tdo_num} @var{tdo}
3217 Set TDO GPIO number. Must be specified to enable JTAG transport. Can also be
3218 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3219 @end deffn
3220
3221 @deffn {Config Command} {bcm2835gpio tdi_num} @var{tdi}
3222 Set TDI GPIO number. Must be specified to enable JTAG transport. Can also be
3223 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3224 @end deffn
3225
3226 @deffn {Config Command} {bcm2835gpio swd_nums} @var{swclk} @var{swdio}
3227 Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be
3228 specified to enable SWD transport. These pins can also be specified individually.
3229 @end deffn
3230
3231 @deffn {Config Command} {bcm2835gpio swclk_num} @var{swclk}
3232 Set SWCLK GPIO number. Must be specified to enable SWD transport. Can also be
3233 specified using the configuration command @command{bcm2835gpio swd_nums}.
3234 @end deffn
3235
3236 @deffn {Config Command} {bcm2835gpio swdio_num} @var{swdio}
3237 Set SWDIO GPIO number. Must be specified to enable SWD transport. Can also be
3238 specified using the configuration command @command{bcm2835gpio swd_nums}.
3239 @end deffn
3240
3241 @deffn {Config Command} {bcm2835gpio swdio_dir_num} @var{swdio} @var{dir}
3242 Set SWDIO direction control pin GPIO number. If specified, this pin can be used
3243 to control the direction of an external buffer on the SWDIO pin (set=output
3244 mode, clear=input mode). If not specified, this feature is disabled.
3245 @end deffn
3246
3247 @deffn {Config Command} {bcm2835gpio srst_num} @var{srst}
3248 Set SRST GPIO number. Must be specified to enable SRST.
3249 @end deffn
3250
3251 @deffn {Config Command} {bcm2835gpio trst_num} @var{trst}
3252 Set TRST GPIO number. Must be specified to enable TRST.
3253 @end deffn
3254
3255 @deffn {Config Command} {bcm2835gpio speed_coeffs} @var{speed_coeff} @var{speed_offset}
3256 Set SPEED_COEFF and SPEED_OFFSET for delay calculations. If unspecified,
3257 speed_coeff defaults to 113714, and speed_offset defaults to 28.
3258 @end deffn
3259
3260 @deffn {Config Command} {bcm2835gpio peripheral_base} @var{base}
3261 Set the peripheral base register address to access GPIOs. For the RPi1, use
3262 0x20000000. For RPi2 and RPi3, use 0x3F000000. For RPi4, use 0xFE000000. A full
3263 list can be found in the
3264 @uref{https://www.raspberrypi.org/documentation/hardware/raspberrypi/peripheral_addresses.md, official guide}.
3265 @end deffn
3266
3267 @end deffn
3268
3269 @deffn {Interface Driver} {imx_gpio}
3270 i.MX SoC is present in many community boards. Wandboard is an example
3271 of the one which is most popular.
3272
3273 This driver is mostly the same as bcm2835gpio.
3274
3275 See @file{interface/imx-native.cfg} for a sample config and
3276 pinout.
3277
3278 @end deffn
3279
3280
3281 @deffn {Interface Driver} {linuxgpiod}
3282 Linux provides userspace access to GPIO through libgpiod since Linux kernel version v4.6.
3283 The driver emulates either JTAG and SWD transport through bitbanging.
3284
3285 See @file{interface/dln-2-gpiod.cfg} for a sample config.
3286 @end deffn
3287
3288
3289 @deffn {Interface Driver} {sysfsgpio}
3290 Linux legacy userspace access to GPIO through sysfs is deprecated from Linux kernel version v5.3.
3291 Prefer using @b{linuxgpiod}, instead.
3292
3293 See @file{interface/sysfsgpio-raspberrypi.cfg} for a sample config.
3294 @end deffn
3295
3296
3297 @deffn {Interface Driver} {openjtag}
3298 OpenJTAG compatible USB adapter.
3299 This defines some driver-specific commands:
3300
3301 @deffn {Config Command} {openjtag variant} variant
3302 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
3303 Currently valid @var{variant} values include:
3304
3305 @itemize @minus
3306 @item @b{standard} Standard variant (default).
3307 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3308 (see @uref{http://www.cypress.com/?rID=82870}).
3309 @end itemize
3310 @end deffn
3311
3312 @deffn {Config Command} {openjtag device_desc} string
3313 The USB device description string of the adapter.
3314 This value is only used with the standard variant.
3315 @end deffn
3316 @end deffn
3317
3318
3319 @deffn {Interface Driver} {jtag_dpi}
3320 SystemVerilog Direct Programming Interface (DPI) compatible driver for
3321 JTAG devices in emulation. The driver acts as a client for the SystemVerilog
3322 DPI server interface.
3323
3324 @deffn {Config Command} {jtag_dpi set_port} port
3325 Specifies the TCP/IP port number of the SystemVerilog DPI server interface.
3326 @end deffn
3327
3328 @deffn {Config Command} {jtag_dpi set_address} address
3329 Specifies the TCP/IP address of the SystemVerilog DPI server interface.
3330 @end deffn
3331 @end deffn
3332
3333
3334 @deffn {Interface Driver} {buspirate}
3335
3336 This driver is for the Bus Pirate (see @url{http://dangerousprototypes.com/docs/Bus_Pirate}) and compatible devices.
3337 It uses a simple data protocol over a serial port connection.
3338
3339 Most hardware development boards have a UART, a real serial port, or a virtual USB serial device, so this driver
3340 allows you to start building your own JTAG adapter without the complexity of a custom USB connection.
3341
3342 @deffn {Config Command} {buspirate port} serial_port
3343 Specify the serial port's filename. For example:
3344 @example
3345 buspirate port /dev/ttyUSB0
3346 @end example
3347 @end deffn
3348
3349 @deffn {Config Command} {buspirate speed} (normal|fast)
3350 Set the communication speed to 115k (normal) or 1M (fast). For example:
3351 @example
3352 buspirate speed normal
3353 @end example
3354 @end deffn
3355
3356 @deffn {Config Command} {buspirate mode} (normal|open-drain)
3357 Set the Bus Pirate output mode.
3358 @itemize @minus
3359 @item In normal mode (push/pull), do not enable the pull-ups, and do not connect I/O header pin VPU to JTAG VREF.
3360 @item In open drain mode, you will then need to enable the pull-ups.
3361 @end itemize
3362 For example:
3363 @example
3364 buspirate mode normal
3365 @end example
3366 @end deffn
3367
3368 @deffn {Config Command} {buspirate pullup} (0|1)
3369 Whether to connect (1) or not (0) the I/O header pin VPU (JTAG VREF)
3370 to the pull-up/pull-down resistors on MOSI (JTAG TDI), CLK (JTAG TCK), MISO (JTAG TDO) and CS (JTAG TMS).
3371 For example:
3372 @example
3373 buspirate pullup 0
3374 @end example
3375 @end deffn
3376
3377 @deffn {Config Command} {buspirate vreg} (0|1)
3378 Whether to enable (1) or disable (0) the built-in voltage regulator,
3379 which can be used to supply power to a test circuit through
3380 I/O header pins +3V3 and +5V. For example:
3381 @example
3382 buspirate vreg 0
3383 @end example
3384 @end deffn
3385
3386 @deffn {Command} {buspirate led} (0|1)
3387 Turns the Bus Pirate's LED on (1) or off (0). For example:
3388 @end deffn
3389 @example
3390 buspirate led 1
3391 @end example
3392
3393 @end deffn
3394
3395
3396 @section Transport Configuration
3397 @cindex Transport
3398 As noted earlier, depending on the version of OpenOCD you use,
3399 and the debug adapter you are using,
3400 several transports may be available to
3401 communicate with debug targets (or perhaps to program flash memory).
3402 @deffn {Command} {transport list}
3403 displays the names of the transports supported by this
3404 version of OpenOCD.
3405 @end deffn
3406
3407 @deffn {Command} {transport select} @option{transport_name}
3408 Select which of the supported transports to use in this OpenOCD session.
3409
3410 When invoked with @option{transport_name}, attempts to select the named
3411 transport. The transport must be supported by the debug adapter
3412 hardware and by the version of OpenOCD you are using (including the
3413 adapter's driver).
3414
3415 If no transport has been selected and no @option{transport_name} is
3416 provided, @command{transport select} auto-selects the first transport
3417 supported by the debug adapter.
3418
3419 @command{transport select} always returns the name of the session's selected
3420 transport, if any.
3421 @end deffn
3422
3423 @subsection JTAG Transport
3424 @cindex JTAG
3425 JTAG is the original transport supported by OpenOCD, and most
3426 of the OpenOCD commands support it.
3427 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3428 each of which must be explicitly declared.
3429 JTAG supports both debugging and boundary scan testing.
3430 Flash programming support is built on top of debug support.
3431
3432 JTAG transport is selected with the command @command{transport select
3433 jtag}. Unless your adapter uses either @ref{hla_interface,the hla interface
3434 driver} (in which case the command is @command{transport select hla_jtag})
3435 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3436 the command is @command{transport select dapdirect_jtag}).
3437
3438 @subsection SWD Transport
3439 @cindex SWD
3440 @cindex Serial Wire Debug
3441 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3442 Debug Access Point (DAP, which must be explicitly declared.
3443 (SWD uses fewer signal wires than JTAG.)
3444 SWD is debug-oriented, and does not support boundary scan testing.
3445 Flash programming support is built on top of debug support.
3446 (Some processors support both JTAG and SWD.)
3447
3448 SWD transport is selected with the command @command{transport select
3449 swd}. Unless your adapter uses either @ref{hla_interface,the hla interface
3450 driver} (in which case the command is @command{transport select hla_swd})
3451 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3452 the command is @command{transport select dapdirect_swd}).
3453
3454 @deffn {Config Command} {swd newdap} ...
3455 Declares a single DAP which uses SWD transport.
3456 Parameters are currently the same as "jtag newtap" but this is
3457 expected to change.
3458 @end deffn
3459 @deffn {Command} {swd wcr trn prescale}
3460 Updates TRN (turnaround delay) and prescaling.fields of the
3461 Wire Control Register (WCR).
3462 No parameters: displays current settings.
3463 @end deffn
3464
3465 @subsection SPI Transport
3466 @cindex SPI
3467 @cindex Serial Peripheral Interface
3468 The Serial Peripheral Interface (SPI) is a general purpose transport
3469 which uses four wire signaling. Some processors use it as part of a
3470 solution for flash programming.
3471
3472 @anchor{swimtransport}
3473 @subsection SWIM Transport
3474 @cindex SWIM
3475 @cindex Single Wire Interface Module
3476 The Single Wire Interface Module (SWIM) is a low-pin-count debug protocol used
3477 by the STMicroelectronics MCU family STM8 and documented in the
3478 @uref{https://www.st.com/resource/en/user_manual/cd00173911.pdf, User Manual UM470}.
3479
3480 SWIM does not support boundary scan testing nor multiple cores.
3481
3482 The SWIM transport is selected with the command @command{transport select swim}.
3483
3484 The concept of TAPs does not fit in the protocol since SWIM does not implement
3485 a scan chain. Nevertheless, the current SW model of OpenOCD requires defining a
3486 virtual SWIM TAP through the command @command{swim newtap basename tap_type}.
3487 The TAP definition must precede the target definition command
3488 @command{target create target_name stm8 -chain-position basename.tap_type}.
3489
3490 @anchor{jtagspeed}
3491 @section JTAG Speed
3492 JTAG clock setup is part of system setup.
3493 It @emph{does not belong with interface setup} since any interface
3494 only knows a few of the constraints for the JTAG clock speed.
3495 Sometimes the JTAG speed is
3496 changed during the target initialization process: (1) slow at
3497 reset, (2) program the CPU clocks, (3) run fast.
3498 Both the "slow" and "fast" clock rates are functions of the
3499 oscillators used, the chip, the board design, and sometimes
3500 power management software that may be active.
3501
3502 The speed used during reset, and the scan chain verification which
3503 follows reset, can be adjusted using a @code{reset-start}
3504 target event handler.
3505 It can then be reconfigured to a faster speed by a
3506 @code{reset-init} target event handler after it reprograms those
3507 CPU clocks, or manually (if something else, such as a boot loader,
3508 sets up those clocks).
3509 @xref{targetevents,,Target Events}.
3510 When the initial low JTAG speed is a chip characteristic, perhaps
3511 because of a required oscillator speed, provide such a handler
3512 in the target config file.
3513 When that speed is a function of a board-specific characteristic
3514 such as which speed oscillator is used, it belongs in the board
3515 config file instead.
3516 In both cases it's safest to also set the initial JTAG clock rate
3517 to that same slow speed, so that OpenOCD never starts up using a
3518 clock speed that's faster than the scan chain can support.
3519
3520 @example
3521 jtag_rclk 3000
3522 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3523 @end example
3524
3525 If your system supports adaptive clocking (RTCK), configuring
3526 JTAG to use that is probably the most robust approach.
3527 However, it introduces delays to synchronize clocks; so it
3528 may not be the fastest solution.
3529
3530 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3531 instead of @command{adapter speed}, but only for (ARM) cores and boards
3532 which support adaptive clocking.
3533
3534 @deffn {Command} {adapter speed} max_speed_kHz
3535 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3536 JTAG interfaces usually support a limited number of
3537 speeds. The speed actually used won't be faster
3538 than the speed specified.
3539
3540 Chip data sheets generally include a top JTAG clock rate.
3541 The actual rate is often a function of a CPU core clock,
3542 and is normally less than that peak rate.
3543 For example, most ARM cores accept at most one sixth of the CPU clock.
3544
3545 Speed 0 (khz) selects RTCK method.
3546 @xref{faqrtck,,FAQ RTCK}.
3547 If your system uses RTCK, you won't need to change the
3548 JTAG clocking after setup.
3549 Not all interfaces, boards, or targets support ``rtck''.
3550 If the interface device can not
3551 support it, an error is returned when you try to use RTCK.
3552 @end deffn
3553
3554 @defun jtag_rclk fallback_speed_kHz
3555 @cindex adaptive clocking
3556 @cindex RTCK
3557 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3558 If that fails (maybe the interface, board, or target doesn't
3559 support it), falls back to the specified frequency.
3560 @example
3561 # Fall back to 3mhz if RTCK is not supported
3562 jtag_rclk 3000
3563 @end example
3564 @end defun
3565
3566 @node Reset Configuration
3567 @chapter Reset Configuration
3568 @cindex Reset Configuration
3569
3570 Every system configuration may require a different reset
3571 configuration. This can also be quite confusing.
3572 Resets also interact with @var{reset-init} event handlers,
3573 which do things like setting up clocks and DRAM, and
3574 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3575 They can also interact with JTAG routers.
3576 Please see the various board files for examples.
3577
3578 @quotation Note
3579 To maintainers and integrators:
3580 Reset configuration touches several things at once.
3581 Normally the board configuration file
3582 should define it and assume that the JTAG adapter supports
3583 everything that's wired up to the board's JTAG connector.
3584
3585 However, the target configuration file could also make note
3586 of something the silicon vendor has done inside the chip,
3587 which will be true for most (or all) boards using that chip.
3588 And when the JTAG adapter doesn't support everything, the
3589 user configuration file will need to override parts of
3590 the reset configuration provided by other files.
3591 @end quotation
3592
3593 @section Types of Reset
3594
3595 There are many kinds of reset possible through JTAG, but
3596 they may not all work with a given board and adapter.
3597 That's part of why reset configuration can be error prone.
3598
3599 @itemize @bullet
3600 @item
3601 @emph{System Reset} ... the @emph{SRST} hardware signal
3602 resets all chips connected to the JTAG adapter, such as processors,
3603 power management chips, and I/O controllers. Normally resets triggered
3604 with this signal behave exactly like pressing a RESET button.
3605 @item
3606 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3607 just the TAP controllers connected to the JTAG adapter.
3608 Such resets should not be visible to the rest of the system; resetting a
3609 device's TAP controller just puts that controller into a known state.
3610 @item
3611 @emph{Emulation Reset} ... many devices can be reset through JTAG
3612 commands. These resets are often distinguishable from system
3613 resets, either explicitly (a "reset reason" register says so)
3614 or implicitly (not all parts of the chip get reset).
3615 @item
3616 @emph{Other Resets} ... system-on-chip devices often support
3617 several other types of reset.
3618 You may need to arrange that a watchdog timer stops
3619 while debugging, preventing a watchdog reset.
3620 There may be individual module resets.
3621 @end itemize
3622
3623 In the best case, OpenOCD can hold SRST, then reset
3624 the TAPs via TRST and send commands through JTAG to halt the
3625 CPU at the reset vector before the 1st instruction is executed.
3626 Then when it finally releases the SRST signal, the system is
3627 halted under debugger control before any code has executed.
3628 This is the behavior required to support the @command{reset halt}
3629 and @command{reset init} commands; after @command{reset init} a
3630 board-specific script might do things like setting up DRAM.
3631 (@xref{resetcommand,,Reset Command}.)
3632
3633 @anchor{srstandtrstissues}
3634 @section SRST and TRST Issues
3635
3636 Because SRST and TRST are hardware signals, they can have a
3637 variety of system-specific constraints. Some of the most
3638 common issues are:
3639
3640 @itemize @bullet
3641
3642 @item @emph{Signal not available} ... Some boards don't wire
3643 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3644 support such signals even if they are wired up.
3645 Use the @command{reset_config} @var{signals} options to say
3646 when either of those signals is not connected.
3647 When SRST is not available, your code might not be able to rely
3648 on controllers having been fully reset during code startup.
3649 Missing TRST is not a problem, since JTAG-level resets can
3650 be triggered using with TMS signaling.
3651
3652 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3653 adapter will connect SRST to TRST, instead of keeping them separate.
3654 Use the @command{reset_config} @var{combination} options to say
3655 when those signals aren't properly independent.
3656
3657 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3658 delay circuit, reset supervisor, or on-chip features can extend
3659 the effect of a JTAG adapter's reset for some time after the adapter
3660 stops issuing the reset. For example, there may be chip or board
3661 requirements that all reset pulses last for at least a
3662 certain amount of time; and reset buttons commonly have
3663 hardware debouncing.
3664 Use the @command{adapter srst delay} and @command{jtag_ntrst_delay}
3665 commands to say when extra delays are needed.
3666
3667 @item @emph{Drive type} ... Reset lines often have a pullup
3668 resistor, letting the JTAG interface treat them as open-drain
3669 signals. But that's not a requirement, so the adapter may need
3670 to use push/pull output drivers.
3671 Also, with weak pullups it may be advisable to drive
3672 signals to both levels (push/pull) to minimize rise times.
3673 Use the @command{reset_config} @var{trst_type} and
3674 @var{srst_type} parameters to say how to drive reset signals.
3675
3676 @item @emph{Special initialization} ... Targets sometimes need
3677 special JTAG initialization sequences to handle chip-specific
3678 issues (not limited to errata).
3679 For example, certain JTAG commands might need to be issued while
3680 the system as a whole is in a reset state (SRST active)
3681 but the JTAG scan chain is usable (TRST inactive).
3682 Many systems treat combined assertion of SRST and TRST as a
3683 trigger for a harder reset than SRST alone.
3684 Such custom reset handling is discussed later in this chapter.
3685 @end itemize
3686
3687 There can also be other issues.
3688 Some devices don't fully conform to the JTAG specifications.
3689 Trivial system-specific differences are common, such as
3690 SRST and TRST using slightly different names.
3691 There are also vendors who distribute key JTAG documentation for
3692 their chips only to developers who have signed a Non-Disclosure
3693 Agreement (NDA).
3694
3695 Sometimes there are chip-specific extensions like a requirement to use
3696 the normally-optional TRST signal (precluding use of JTAG adapters which
3697 don't pass TRST through), or needing extra steps to complete a TAP reset.
3698
3699 In short, SRST and especially TRST handling may be very finicky,
3700 needing to cope with both architecture and board specific constraints.
3701
3702 @section Commands for Handling Resets
3703
3704 @deffn {Command} {adapter srst pulse_width} milliseconds
3705 Minimum amount of time (in milliseconds) OpenOCD should wait
3706 after asserting nSRST (active-low system reset) before
3707 allowing it to be deasserted.
3708 @end deffn
3709
3710 @deffn {Command} {adapter srst delay} milliseconds
3711 How long (in milliseconds) OpenOCD should wait after deasserting
3712 nSRST (active-low system reset) before starting new JTAG operations.
3713 When a board has a reset button connected to SRST line it will
3714 probably have hardware debouncing, implying you should use this.
3715 @end deffn
3716
3717 @deffn {Command} {jtag_ntrst_assert_width} milliseconds
3718 Minimum amount of time (in milliseconds) OpenOCD should wait
3719 after asserting nTRST (active-low JTAG TAP reset) before
3720 allowing it to be deasserted.
3721 @end deffn
3722
3723 @deffn {Command} {jtag_ntrst_delay} milliseconds
3724 How long (in milliseconds) OpenOCD should wait after deasserting
3725 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3726 @end deffn
3727
3728 @anchor{reset_config}
3729 @deffn {Command} {reset_config} mode_flag ...
3730 This command displays or modifies the reset configuration
3731 of your combination of JTAG board and target in target
3732 configuration scripts.
3733
3734 Information earlier in this section describes the kind of problems
3735 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3736 As a rule this command belongs only in board config files,
3737 describing issues like @emph{board doesn't connect TRST};
3738 or in user config files, addressing limitations derived
3739 from a particular combination of interface and board.
3740 (An unlikely example would be using a TRST-only adapter
3741 with a board that only wires up SRST.)
3742
3743 The @var{mode_flag} options can be specified in any order, but only one
3744 of each type -- @var{signals}, @var{combination}, @var{gates},
3745 @var{trst_type}, @var{srst_type} and @var{connect_type}
3746 -- may be specified at a time.
3747 If you don't provide a new value for a given type, its previous
3748 value (perhaps the default) is unchanged.
3749 For example, this means that you don't need to say anything at all about
3750 TRST just to declare that if the JTAG adapter should want to drive SRST,
3751 it must explicitly be driven high (@option{srst_push_pull}).
3752
3753 @itemize
3754 @item
3755 @var{signals} can specify which of the reset signals are connected.
3756 For example, If the JTAG interface provides SRST, but the board doesn't
3757 connect that signal properly, then OpenOCD can't use it.
3758 Possible values are @option{none} (the default), @option{trst_only},
3759 @option{srst_only} and @option{trst_and_srst}.
3760
3761 @quotation Tip
3762 If your board provides SRST and/or TRST through the JTAG connector,
3763 you must declare that so those signals can be used.
3764 @end quotation
3765
3766 @item
3767 The @var{combination} is an optional value specifying broken reset
3768 signal implementations.
3769 The default behaviour if no option given is @option{separate},
3770 indicating everything behaves normally.
3771 @option{srst_pulls_trst} states that the
3772 test logic is reset together with the reset of the system (e.g. NXP
3773 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3774 the system is reset together with the test logic (only hypothetical, I
3775 haven't seen hardware with such a bug, and can be worked around).
3776 @option{combined} implies both @option{srst_pulls_trst} and
3777 @option{trst_pulls_srst}.
3778
3779 @item
3780 The @var{gates} tokens control flags that describe some cases where
3781 JTAG may be unavailable during reset.
3782 @option{srst_gates_jtag} (default)
3783 indicates that asserting SRST gates the
3784 JTAG clock. This means that no communication can happen on JTAG
3785 while SRST is asserted.
3786 Its converse is @option{srst_nogate}, indicating that JTAG commands
3787 can safely be issued while SRST is active.
3788
3789 @item
3790 The @var{connect_type} tokens control flags that describe some cases where
3791 SRST is asserted while connecting to the target. @option{srst_nogate}
3792 is required to use this option.
3793 @option{connect_deassert_srst} (default)
3794 indicates that SRST will not be asserted while connecting to the target.
3795 Its converse is @option{connect_assert_srst}, indicating that SRST will
3796 be asserted before any target connection.
3797 Only some targets support this feature, STM32 and STR9 are examples.
3798 This feature is useful if you are unable to connect to your target due
3799 to incorrect options byte config or illegal program execution.
3800 @end itemize
3801
3802 The optional @var{trst_type} and @var{srst_type} parameters allow the
3803 driver mode of each reset line to be specified. These values only affect
3804 JTAG interfaces with support for different driver modes, like the Amontec
3805 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3806 relevant signal (TRST or SRST) is not connected.
3807
3808 @itemize
3809 @item
3810 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3811 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3812 Most boards connect this signal to a pulldown, so the JTAG TAPs
3813 never leave reset unless they are hooked up to a JTAG adapter.
3814
3815 @item
3816 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3817 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3818 Most boards connect this signal to a pullup, and allow the
3819 signal to be pulled low by various events including system
3820 power-up and pressing a reset button.
3821 @end itemize
3822 @end deffn
3823
3824 @section Custom Reset Handling
3825 @cindex events
3826
3827 OpenOCD has several ways to help support the various reset
3828 mechanisms provided by chip and board vendors.
3829 The commands shown in the previous section give standard parameters.
3830 There are also @emph{event handlers} associated with TAPs or Targets.
3831 Those handlers are Tcl procedures you can provide, which are invoked
3832 at particular points in the reset sequence.
3833
3834 @emph{When SRST is not an option} you must set
3835 up a @code{reset-assert} event handler for your target.
3836 For example, some JTAG adapters don't include the SRST signal;
3837 and some boards have multiple targets, and you won't always
3838 want to reset everything at once.
3839
3840 After configuring those mechanisms, you might still
3841 find your board doesn't start up or reset correctly.
3842 For example, maybe it needs a slightly different sequence
3843 of SRST and/or TRST manipulations, because of quirks that
3844 the @command{reset_config} mechanism doesn't address;
3845 or asserting both might trigger a stronger reset, which
3846 needs special attention.
3847
3848 Experiment with lower level operations, such as
3849 @command{adapter assert}, @command{adapter deassert}
3850 and the @command{jtag arp_*} operations shown here,
3851 to find a sequence of operations that works.
3852 @xref{JTAG Commands}.
3853 When you find a working sequence, it can be used to override
3854 @command{jtag_init}, which fires during OpenOCD startup
3855 (@pxref{configurationstage,,Configuration Stage});
3856 or @command{init_reset}, which fires during reset processing.
3857
3858 You might also want to provide some project-specific reset
3859 schemes. For example, on a multi-target board the standard
3860 @command{reset} command would reset all targets, but you
3861 may need the ability to reset only one target at time and
3862 thus want to avoid using the board-wide SRST signal.
3863
3864 @deffn {Overridable Procedure} {init_reset} mode
3865 This is invoked near the beginning of the @command{reset} command,
3866 usually to provide as much of a cold (power-up) reset as practical.
3867 By default it is also invoked from @command{jtag_init} if
3868 the scan chain does not respond to pure JTAG operations.
3869 The @var{mode} parameter is the parameter given to the
3870 low level reset command (@option{halt},
3871 @option{init}, or @option{run}), @option{setup},
3872 or potentially some other value.
3873
3874 The default implementation just invokes @command{jtag arp_init-reset}.
3875 Replacements will normally build on low level JTAG
3876 operations such as @command{adapter assert} and @command{adapter deassert}.
3877 Operations here must not address individual TAPs
3878 (or their associated targets)
3879 until the JTAG scan chain has first been verified to work.
3880
3881 Implementations must have verified the JTAG scan chain before
3882 they return.
3883 This is done by calling @command{jtag arp_init}
3884 (or @command{jtag arp_init-reset}).
3885 @end deffn
3886
3887 @deffn {Command} {jtag arp_init}
3888 This validates the scan chain using just the four
3889 standard JTAG signals (TMS, TCK, TDI, TDO).
3890 It starts by issuing a JTAG-only reset.
3891 Then it performs checks to verify that the scan chain configuration
3892 matches the TAPs it can observe.
3893 Those checks include checking IDCODE values for each active TAP,
3894 and verifying the length of their instruction registers using
3895 TAP @code{-ircapture} and @code{-irmask} values.
3896 If these tests all pass, TAP @code{setup} events are
3897 issued to all TAPs with handlers for that event.
3898 @end deffn
3899
3900 @deffn {Command} {jtag arp_init-reset}
3901 This uses TRST and SRST to try resetting
3902 everything on the JTAG scan chain
3903 (and anything else connected to SRST).
3904 It then invokes the logic of @command{jtag arp_init}.
3905 @end deffn
3906
3907
3908 @node TAP Declaration
3909 @chapter TAP Declaration
3910 @cindex TAP declaration
3911 @cindex TAP configuration
3912
3913 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3914 TAPs serve many roles, including:
3915
3916 @itemize @bullet
3917 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3918 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3919 Others do it indirectly, making a CPU do it.
3920 @item @b{Program Download} Using the same CPU support GDB uses,
3921 you can initialize a DRAM controller, download code to DRAM, and then
3922 start running that code.
3923 @item @b{Boundary Scan} Most chips support boundary scan, which
3924 helps test for board assembly problems like solder bridges
3925 and missing connections.
3926 @end itemize
3927
3928 OpenOCD must know about the active TAPs on your board(s).
3929 Setting up the TAPs is the core task of your configuration files.
3930 Once those TAPs are set up, you can pass their names to code
3931 which sets up CPUs and exports them as GDB targets,
3932 probes flash memory, performs low-level JTAG operations, and more.
3933
3934 @section Scan Chains
3935 @cindex scan chain
3936
3937 TAPs are part of a hardware @dfn{scan chain},
3938 which is a daisy chain of TAPs.
3939 They also need to be added to
3940 OpenOCD's software mirror of that hardware list,
3941 giving each member a name and associating other data with it.
3942 Simple scan chains, with a single TAP, are common in
3943 systems with a single microcontroller or microprocessor.
3944 More complex chips may have several TAPs internally.
3945 Very complex scan chains might have a dozen or more TAPs:
3946 several in one chip, more in the next, and connecting
3947 to other boards with their own chips and TAPs.
3948
3949 You can display the list with the @command{scan_chain} command.
3950 (Don't confuse this with the list displayed by the @command{targets}
3951 command, presented in the next chapter.
3952 That only displays TAPs for CPUs which are configured as
3953 debugging targets.)
3954 Here's what the scan chain might look like for a chip more than one TAP:
3955
3956 @verbatim
3957 TapName Enabled IdCode Expected IrLen IrCap IrMask
3958 -- ------------------ ------- ---------- ---------- ----- ----- ------
3959 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3960 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3961 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3962 @end verbatim
3963
3964 OpenOCD can detect some of that information, but not all
3965 of it. @xref{autoprobing,,Autoprobing}.
3966 Unfortunately, those TAPs can't always be autoconfigured,
3967 because not all devices provide good support for that.
3968 JTAG doesn't require supporting IDCODE instructions, and
3969 chips with JTAG routers may not link TAPs into the chain
3970 until they are told to do so.
3971
3972 The configuration mechanism currently supported by OpenOCD
3973 requires explicit configuration of all TAP devices using
3974 @command{jtag newtap} commands, as detailed later in this chapter.
3975 A command like this would declare one tap and name it @code{chip1.cpu}:
3976
3977 @example
3978 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3979 @end example
3980
3981 Each target configuration file lists the TAPs provided
3982 by a given chip.
3983 Board configuration files combine all the targets on a board,
3984 and so forth.
3985 Note that @emph{the order in which TAPs are declared is very important.}
3986 That declaration order must match the order in the JTAG scan chain,
3987 both inside a single chip and between them.
3988 @xref{faqtaporder,,FAQ TAP Order}.
3989
3990 For example, the STMicroelectronics STR912 chip has
3991 three separate TAPs@footnote{See the ST
3992 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3993 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3994 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3995 To configure those taps, @file{target/str912.cfg}
3996 includes commands something like this:
3997
3998 @example
3999 jtag newtap str912 flash ... params ...
4000 jtag newtap str912 cpu ... params ...
4001 jtag newtap str912 bs ... params ...
4002 @end example
4003
4004 Actual config files typically use a variable such as @code{$_CHIPNAME}
4005 instead of literals like @option{str912}, to support more than one chip
4006 of each type. @xref{Config File Guidelines}.
4007
4008 @deffn {Command} {jtag names}
4009 Returns the names of all current TAPs in the scan chain.
4010 Use @command{jtag cget} or @command{jtag tapisenabled}
4011 to examine attributes and state of each TAP.
4012 @example
4013 foreach t [jtag names] @{
4014 puts [format "TAP: %s\n" $t]
4015 @}
4016 @end example
4017 @end deffn
4018
4019 @deffn {Command} {scan_chain}
4020 Displays the TAPs in the scan chain configuration,
4021 and their status.
4022 The set of TAPs listed by this command is fixed by
4023 exiting the OpenOCD configuration stage,
4024 but systems with a JTAG router can
4025 enable or disable TAPs dynamically.
4026 @end deffn
4027
4028 @c FIXME! "jtag cget" should be able to return all TAP
4029 @c attributes, like "$target_name cget" does for targets.
4030
4031 @c Probably want "jtag eventlist", and a "tap-reset" event
4032 @c (on entry to RESET state).
4033
4034 @section TAP Names
4035 @cindex dotted name
4036
4037 When TAP objects are declared with @command{jtag newtap},
4038 a @dfn{dotted.name} is created for the TAP, combining the
4039 name of a module (usually a chip) and a label for the TAP.
4040 For example: @code{xilinx.tap}, @code{str912.flash},
4041 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
4042 Many other commands use that dotted.name to manipulate or
4043 refer to the TAP. For example, CPU configuration uses the
4044 name, as does declaration of NAND or NOR flash banks.
4045
4046 The components of a dotted name should follow ``C'' symbol
4047 name rules: start with an alphabetic character, then numbers
4048 and underscores are OK; while others (including dots!) are not.
4049
4050 @section TAP Declaration Commands
4051
4052 @deffn {Config Command} {jtag newtap} chipname tapname configparams...
4053 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
4054 and configured according to the various @var{configparams}.
4055
4056 The @var{chipname} is a symbolic name for the chip.
4057 Conventionally target config files use @code{$_CHIPNAME},
4058 defaulting to the model name given by the chip vendor but
4059 overridable.
4060
4061 @cindex TAP naming convention
4062 The @var{tapname} reflects the role of that TAP,
4063 and should follow this convention:
4064
4065 @itemize @bullet
4066 @item @code{bs} -- For boundary scan if this is a separate TAP;
4067 @item @code{cpu} -- The main CPU of the chip, alternatively
4068 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
4069 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
4070 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
4071 @item @code{flash} -- If the chip has a flash TAP, like the str912;
4072 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
4073 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
4074 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
4075 with a single TAP;
4076 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
4077 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
4078 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
4079 a JTAG TAP; that TAP should be named @code{sdma}.
4080 @end itemize
4081
4082 Every TAP requires at least the following @var{configparams}:
4083
4084 @itemize @bullet
4085 @item @code{-irlen} @var{NUMBER}
4086 @*The length in bits of the
4087 instruction register, such as 4 or 5 bits.
4088 @end itemize
4089
4090 A TAP may also provide optional @var{configparams}:
4091
4092 @itemize @bullet
4093 @item @code{-disable} (or @code{-enable})
4094 @*Use the @code{-disable} parameter to flag a TAP which is not
4095 linked into the scan chain after a reset using either TRST
4096 or the JTAG state machine's @sc{reset} state.
4097 You may use @code{-enable} to highlight the default state
4098 (the TAP is linked in).
4099 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
4100 @item @code{-expected-id} @var{NUMBER}
4101 @*A non-zero @var{number} represents a 32-bit IDCODE
4102 which you expect to find when the scan chain is examined.
4103 These codes are not required by all JTAG devices.
4104 @emph{Repeat the option} as many times as required if more than one
4105 ID code could appear (for example, multiple versions).
4106 Specify @var{number} as zero to suppress warnings about IDCODE
4107 values that were found but not included in the list.
4108
4109 Provide this value if at all possible, since it lets OpenOCD
4110 tell when the scan chain it sees isn't right. These values
4111 are provided in vendors' chip documentation, usually a technical
4112 reference manual. Sometimes you may need to probe the JTAG
4113 hardware to find these values.
4114 @xref{autoprobing,,Autoprobing}.
4115 @item @code{-ignore-version}
4116 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
4117 option. When vendors put out multiple versions of a chip, or use the same
4118 JTAG-level ID for several largely-compatible chips, it may be more practical
4119 to ignore the version field than to update config files to handle all of
4120 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
4121 @item @code{-ircapture} @var{NUMBER}
4122 @*The bit pattern loaded by the TAP into the JTAG shift register
4123 on entry to the @sc{ircapture} state, such as 0x01.
4124 JTAG requires the two LSBs of this value to be 01.
4125 By default, @code{-ircapture} and @code{-irmask} are set
4126 up to verify that two-bit value. You may provide
4127 additional bits if you know them, or indicate that
4128 a TAP doesn't conform to the JTAG specification.
4129 @item @code{-irmask} @var{NUMBER}
4130 @*A mask used with @code{-ircapture}
4131 to verify that instruction scans work correctly.
4132 Such scans are not used by OpenOCD except to verify that
4133 there seems to be no problems with JTAG scan chain operations.
4134 @item @code{-ignore-syspwrupack}
4135 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4136 register during initial examination and when checking the sticky error bit.
4137 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4138 devices do not set the ack bit until sometime later.
4139 @end itemize
4140 @end deffn
4141
4142 @section Other TAP commands
4143
4144 @deffn {Command} {jtag cget} dotted.name @option{-idcode}
4145 Get the value of the IDCODE found in hardware.
4146 @end deffn
4147
4148 @deffn {Command} {jtag cget} dotted.name @option{-event} event_name
4149 @deffnx {Command} {jtag configure} dotted.name @option{-event} event_name handler
4150 At this writing this TAP attribute
4151 mechanism is limited and used mostly for event handling.
4152 (It is not a direct analogue of the @code{cget}/@code{configure}
4153 mechanism for debugger targets.)
4154 See the next section for information about the available events.
4155
4156 The @code{configure} subcommand assigns an event handler,
4157 a TCL string which is evaluated when the event is triggered.
4158 The @code{cget} subcommand returns that handler.
4159 @end deffn
4160
4161 @section TAP Events
4162 @cindex events
4163 @cindex TAP events
4164
4165 OpenOCD includes two event mechanisms.
4166 The one presented here applies to all JTAG TAPs.
4167 The other applies to debugger targets,
4168 which are associated with certain TAPs.
4169
4170 The TAP events currently defined are:
4171
4172 @itemize @bullet
4173 @item @b{post-reset}
4174 @* The TAP has just completed a JTAG reset.
4175 The tap may still be in the JTAG @sc{reset} state.
4176 Handlers for these events might perform initialization sequences
4177 such as issuing TCK cycles, TMS sequences to ensure
4178 exit from the ARM SWD mode, and more.
4179
4180 Because the scan chain has not yet been verified, handlers for these events
4181 @emph{should not issue commands which scan the JTAG IR or DR registers}
4182 of any particular target.
4183 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
4184 @item @b{setup}
4185 @* The scan chain has been reset and verified.
4186 This handler may enable TAPs as needed.
4187 @item @b{tap-disable}
4188 @* The TAP needs to be disabled. This handler should
4189 implement @command{jtag tapdisable}
4190 by issuing the relevant JTAG commands.
4191 @item @b{tap-enable}
4192 @* The TAP needs to be enabled. This handler should
4193 implement @command{jtag tapenable}
4194 by issuing the relevant JTAG commands.
4195 @end itemize
4196
4197 If you need some action after each JTAG reset which isn't actually
4198 specific to any TAP (since you can't yet trust the scan chain's
4199 contents to be accurate), you might:
4200
4201 @example
4202 jtag configure CHIP.jrc -event post-reset @{
4203 echo "JTAG Reset done"
4204 ... non-scan jtag operations to be done after reset
4205 @}
4206 @end example
4207
4208
4209 @anchor{enablinganddisablingtaps}
4210 @section Enabling and Disabling TAPs
4211 @cindex JTAG Route Controller
4212 @cindex jrc
4213
4214 In some systems, a @dfn{JTAG Route Controller} (JRC)
4215 is used to enable and/or disable specific JTAG TAPs.
4216 Many ARM-based chips from Texas Instruments include
4217 an ``ICEPick'' module, which is a JRC.
4218 Such chips include DaVinci and OMAP3 processors.
4219
4220 A given TAP may not be visible until the JRC has been
4221 told to link it into the scan chain; and if the JRC
4222 has been told to unlink that TAP, it will no longer
4223 be visible.
4224 Such routers address problems that JTAG ``bypass mode''
4225 ignores, such as:
4226
4227 @itemize
4228 @item The scan chain can only go as fast as its slowest TAP.
4229 @item Having many TAPs slows instruction scans, since all
4230 TAPs receive new instructions.
4231 @item TAPs in the scan chain must be powered up, which wastes
4232 power and prevents debugging some power management mechanisms.
4233 @end itemize
4234
4235 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
4236 as implied by the existence of JTAG routers.
4237 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
4238 does include a kind of JTAG router functionality.
4239
4240 @c (a) currently the event handlers don't seem to be able to
4241 @c fail in a way that could lead to no-change-of-state.
4242
4243 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
4244 shown below, and is implemented using TAP event handlers.
4245 So for example, when defining a TAP for a CPU connected to
4246 a JTAG router, your @file{target.cfg} file
4247 should define TAP event handlers using
4248 code that looks something like this:
4249
4250 @example
4251 jtag configure CHIP.cpu -event tap-enable @{
4252 ... jtag operations using CHIP.jrc
4253 @}
4254 jtag configure CHIP.cpu -event tap-disable @{
4255 ... jtag operations using CHIP.jrc
4256 @}
4257 @end example
4258
4259 Then you might want that CPU's TAP enabled almost all the time:
4260
4261 @example
4262 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
4263 @end example
4264
4265 Note how that particular setup event handler declaration
4266 uses quotes to evaluate @code{$CHIP} when the event is configured.
4267 Using brackets @{ @} would cause it to be evaluated later,
4268 at runtime, when it might have a different value.
4269
4270 @deffn {Command} {jtag tapdisable} dotted.name
4271 If necessary, disables the tap
4272 by sending it a @option{tap-disable} event.
4273 Returns the string "1" if the tap
4274 specified by @var{dotted.name} is enabled,
4275 and "0" if it is disabled.
4276 @end deffn
4277
4278 @deffn {Command} {jtag tapenable} dotted.name
4279 If necessary, enables the tap
4280 by sending it a @option{tap-enable} event.
4281 Returns the string "1" if the tap
4282 specified by @var{dotted.name} is enabled,
4283 and "0" if it is disabled.
4284 @end deffn
4285
4286 @deffn {Command} {jtag tapisenabled} dotted.name
4287 Returns the string "1" if the tap
4288 specified by @var{dotted.name} is enabled,
4289 and "0" if it is disabled.
4290
4291 @quotation Note
4292 Humans will find the @command{scan_chain} command more helpful
4293 for querying the state of the JTAG taps.
4294 @end quotation
4295 @end deffn
4296
4297 @anchor{autoprobing}
4298 @section Autoprobing
4299 @cindex autoprobe
4300 @cindex JTAG autoprobe
4301
4302 TAP configuration is the first thing that needs to be done
4303 after interface and reset configuration. Sometimes it's
4304 hard finding out what TAPs exist, or how they are identified.
4305 Vendor documentation is not always easy to find and use.
4306
4307 To help you get past such problems, OpenOCD has a limited
4308 @emph{autoprobing} ability to look at the scan chain, doing
4309 a @dfn{blind interrogation} and then reporting the TAPs it finds.
4310 To use this mechanism, start the OpenOCD server with only data
4311 that configures your JTAG interface, and arranges to come up
4312 with a slow clock (many devices don't support fast JTAG clocks
4313 right when they come out of reset).
4314
4315 For example, your @file{openocd.cfg} file might have:
4316
4317 @example
4318 source [find interface/olimex-arm-usb-tiny-h.cfg]
4319 reset_config trst_and_srst
4320 jtag_rclk 8
4321 @end example
4322
4323 When you start the server without any TAPs configured, it will
4324 attempt to autoconfigure the TAPs. There are two parts to this:
4325
4326 @enumerate
4327 @item @emph{TAP discovery} ...
4328 After a JTAG reset (sometimes a system reset may be needed too),
4329 each TAP's data registers will hold the contents of either the
4330 IDCODE or BYPASS register.
4331 If JTAG communication is working, OpenOCD will see each TAP,
4332 and report what @option{-expected-id} to use with it.
4333 @item @emph{IR Length discovery} ...
4334 Unfortunately JTAG does not provide a reliable way to find out
4335 the value of the @option{-irlen} parameter to use with a TAP
4336 that is discovered.
4337 If OpenOCD can discover the length of a TAP's instruction
4338 register, it will report it.
4339 Otherwise you may need to consult vendor documentation, such
4340 as chip data sheets or BSDL files.
4341 @end enumerate
4342
4343 In many cases your board will have a simple scan chain with just
4344 a single device. Here's what OpenOCD reported with one board
4345 that's a bit more complex:
4346
4347 @example
4348 clock speed 8 kHz
4349 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4350 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4351 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4352 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4353 AUTO auto0.tap - use "... -irlen 4"
4354 AUTO auto1.tap - use "... -irlen 4"
4355 AUTO auto2.tap - use "... -irlen 6"
4356 no gdb ports allocated as no target has been specified
4357 @end example
4358
4359 Given that information, you should be able to either find some existing
4360 config files to use, or create your own. If you create your own, you
4361 would configure from the bottom up: first a @file{target.cfg} file
4362 with these TAPs, any targets associated with them, and any on-chip
4363 resources; then a @file{board.cfg} with off-chip resources, clocking,
4364 and so forth.
4365
4366 @anchor{dapdeclaration}
4367 @section DAP declaration (ARMv6-M, ARMv7 and ARMv8 targets)
4368 @cindex DAP declaration
4369
4370 Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is
4371 no longer implicitly created together with the target. It must be
4372 explicitly declared using the @command{dap create} command. For all ARMv6-M, ARMv7
4373 and ARMv8 targets, the option "@option{-dap} @var{dap_name}" has to be used
4374 instead of "@option{-chain-position} @var{dotted.name}" when the target is created.
4375
4376 The @command{dap} command group supports the following sub-commands:
4377
4378 @deffn {Command} {dap create} dap_name @option{-chain-position} dotted.name configparams...
4379 Declare a DAP instance named @var{dap_name} linked to the JTAG tap
4380 @var{dotted.name}. This also creates a new command (@command{dap_name})
4381 which is used for various purposes including additional configuration.
4382 There can only be one DAP for each JTAG tap in the system.
4383
4384 A DAP may also provide optional @var{configparams}:
4385
4386 @itemize @bullet
4387 @item @code{-ignore-syspwrupack}
4388 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4389 register during initial examination and when checking the sticky error bit.
4390 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4391 devices do not set the ack bit until sometime later.
4392 @end itemize
4393 @end deffn
4394
4395 @deffn {Command} {dap names}
4396 This command returns a list of all registered DAP objects. It it useful mainly
4397 for TCL scripting.
4398 @end deffn
4399
4400 @deffn {Command} {dap info} [num]
4401 Displays the ROM table for MEM-AP @var{num},
4402 defaulting to the currently selected AP of the currently selected target.
4403 @end deffn
4404
4405 @deffn {Command} {dap init}
4406 Initialize all registered DAPs. This command is used internally
4407 during initialization. It can be issued at any time after the
4408 initialization, too.
4409 @end deffn
4410
4411 The following commands exist as subcommands of DAP instances:
4412
4413 @deffn {Command} {$dap_name info} [num]
4414 Displays the ROM table for MEM-AP @var{num},
4415 defaulting to the currently selected AP.
4416 @end deffn
4417
4418 @deffn {Command} {$dap_name apid} [num]
4419 Displays ID register from AP @var{num}, defaulting to the currently selected AP.
4420 @end deffn
4421
4422 @anchor{DAP subcommand apreg}
4423 @deffn {Command} {$dap_name apreg} ap_num reg [value]
4424 Displays content of a register @var{reg} from AP @var{ap_num}
4425 or set a new value @var{value}.
4426 @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
4427 @end deffn
4428
4429 @deffn {Command} {$dap_name apsel} [num]
4430 Select AP @var{num}, defaulting to 0.
4431 @end deffn
4432
4433 @deffn {Command} {$dap_name dpreg} reg [value]
4434 Displays the content of DP register at address @var{reg}, or set it to a new
4435 value @var{value}.
4436
4437 In case of SWD, @var{reg} is a value in packed format
4438 @math{dpbanksel << 4 | addr} and assumes values 0, 4, 8 ... 0xfc.
4439 In case of JTAG it only assumes values 0, 4, 8 and 0xc.
4440
4441 @emph{Note:} Consider using @command{poll off} to avoid any disturbing
4442 background activity by OpenOCD while you are operating at such low-level.
4443 @end deffn
4444
4445 @deffn {Command} {$dap_name baseaddr} [num]
4446 Displays debug base address from MEM-AP @var{num},
4447 defaulting to the currently selected AP.
4448 @end deffn
4449
4450 @deffn {Command} {$dap_name memaccess} [value]
4451 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
4452 memory bus access [0-255], giving additional time to respond to reads.
4453 If @var{value} is defined, first assigns that.
4454 @end deffn
4455
4456 @deffn {Command} {$dap_name apcsw} [value [mask]]
4457 Displays or changes CSW bit pattern for MEM-AP transfers.
4458
4459 At the begin of each memory access the CSW pattern is extended (bitwise or-ed)
4460 by @dfn{Size} and @dfn{AddrInc} bit-fields according to transfer requirements
4461 and the result is written to the real CSW register. All bits except dynamically
4462 updated fields @dfn{Size} and @dfn{AddrInc} can be changed by changing
4463 the CSW pattern. Refer to ARM ADI v5 manual chapter 7.6.4 and appendix A
4464 for details.
4465
4466 Use @var{value} only syntax if you want to set the new CSW pattern as a whole.
4467 The example sets HPROT1 bit (required by Cortex-M) and clears the rest of
4468 the pattern:
4469 @example
4470 kx.dap apcsw 0x2000000
4471 @end example
4472
4473 If @var{mask} is also used, the CSW pattern is changed only on bit positions
4474 where the mask bit is 1. The following example sets HPROT3 (cacheable)
4475 and leaves the rest of the pattern intact. It configures memory access through
4476 DCache on Cortex-M7.
4477 @example
4478 set CSW_HPROT3_CACHEABLE [expr 1 << 27]
4479 samv.dap apcsw $CSW_HPROT3_CACHEABLE $CSW_HPROT3_CACHEABLE
4480 @end example
4481
4482 Another example clears SPROT bit and leaves the rest of pattern intact:
4483 @example
4484 set CSW_SPROT [expr 1 << 30]
4485 samv.dap apcsw 0 $CSW_SPROT
4486 @end example
4487
4488 @emph{Note:} If you want to check the real value of CSW, not CSW pattern, use
4489 @code{xxx.dap apreg 0}. @xref{DAP subcommand apreg,,}.
4490
4491 @emph{Warning:} Some of the CSW bits are vital for working memory transfer.
4492 If you set a wrong CSW pattern and MEM-AP stopped working, use the following
4493 example with a proper dap name:
4494 @example
4495 xxx.dap apcsw default
4496 @end example
4497 @end deffn
4498
4499 @deffn {Config Command} {$dap_name ti_be_32_quirks} [@option{enable}]
4500 Set/get quirks mode for TI TMS450/TMS570 processors
4501 Disabled by default
4502 @end deffn
4503
4504
4505 @node CPU Configuration
4506 @chapter CPU Configuration
4507 @cindex GDB target
4508
4509 This chapter discusses how to set up GDB debug targets for CPUs.
4510 You can also access these targets without GDB
4511 (@pxref{Architecture and Core Commands},
4512 and @ref{targetstatehandling,,Target State handling}) and
4513 through various kinds of NAND and NOR flash commands.
4514 If you have multiple CPUs you can have multiple such targets.
4515
4516 We'll start by looking at how to examine the targets you have,
4517 then look at how to add one more target and how to configure it.
4518
4519 @section Target List
4520 @cindex target, current
4521 @cindex target, list
4522
4523 All targets that have been set up are part of a list,
4524 where each member has a name.
4525 That name should normally be the same as the TAP name.
4526 You can display the list with the @command{targets}
4527 (plural!) command.
4528 This display often has only one CPU; here's what it might
4529 look like with more than one:
4530 @verbatim
4531 TargetName Type Endian TapName State
4532 -- ------------------ ---------- ------ ------------------ ------------
4533 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4534 1 MyTarget cortex_m little mychip.foo tap-disabled
4535 @end verbatim
4536
4537 One member of that list is the @dfn{current target}, which
4538 is implicitly referenced by many commands.
4539 It's the one marked with a @code{*} near the target name.
4540 In particular, memory addresses often refer to the address
4541 space seen by that current target.
4542 Commands like @command{mdw} (memory display words)
4543 and @command{flash erase_address} (erase NOR flash blocks)
4544 are examples; and there are many more.
4545
4546 Several commands let you examine the list of targets:
4547
4548 @deffn {Command} {target current}
4549 Returns the name of the current target.
4550 @end deffn
4551
4552 @deffn {Command} {target names}
4553 Lists the names of all current targets in the list.
4554 @example
4555 foreach t [target names] @{
4556 puts [format "Target: %s\n" $t]
4557 @}
4558 @end example
4559 @end deffn
4560
4561 @c yep, "target list" would have been better.
4562 @c plus maybe "target setdefault".
4563
4564 @deffn {Command} {targets} [name]
4565 @emph{Note: the name of this command is plural. Other target
4566 command names are singular.}
4567
4568 With no parameter, this command displays a table of all known
4569 targets in a user friendly form.
4570
4571 With a parameter, this command sets the current target to
4572 the given target with the given @var{name}; this is
4573 only relevant on boards which have more than one target.
4574 @end deffn
4575
4576 @section Target CPU Types
4577 @cindex target type
4578 @cindex CPU type
4579
4580 Each target has a @dfn{CPU type}, as shown in the output of
4581 the @command{targets} command. You need to specify that type
4582 when calling @command{target create}.
4583 The CPU type indicates more than just the instruction set.
4584 It also indicates how that instruction set is implemented,
4585 what kind of debug support it integrates,
4586 whether it has an MMU (and if so, what kind),
4587 what core-specific commands may be available
4588 (@pxref{Architecture and Core Commands}),
4589 and more.
4590
4591 It's easy to see what target types are supported,
4592 since there's a command to list them.
4593
4594 @anchor{targettypes}
4595 @deffn {Command} {target types}
4596 Lists all supported target types.
4597 At this writing, the supported CPU types are:
4598
4599 @itemize @bullet
4600 @item @code{aarch64} -- this is an ARMv8-A core with an MMU.
4601 @item @code{arm11} -- this is a generation of ARMv6 cores.
4602 @item @code{arm720t} -- this is an ARMv4 core with an MMU.
4603 @item @code{arm7tdmi} -- this is an ARMv4 core.
4604 @item @code{arm920t} -- this is an ARMv4 core with an MMU.
4605 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU.
4606 @item @code{arm946e} -- this is an ARMv5 core with an MMU.
4607 @item @code{arm966e} -- this is an ARMv5 core.
4608 @item @code{arm9tdmi} -- this is an ARMv4 core.
4609 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4610 (Support for this is preliminary and incomplete.)
4611 @item @code{avr32_ap7k} -- this an AVR32 core.
4612 @item @code{cortex_a} -- this is an ARMv7-A core with an MMU.
4613 @item @code{cortex_m} -- this is an ARMv7-M core, supporting only the
4614 compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores
4615 @item @code{cortex_r4} -- this is an ARMv7-R core.
4616 @item @code{dragonite} -- resembles arm966e.
4617 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4618 (Support for this is still incomplete.)
4619 @item @code{dsp5680xx} -- implements Freescale's 5680x DSP.
4620 @item @code{esirisc} -- this is an EnSilica eSi-RISC core.
4621 The current implementation supports eSi-32xx cores.
4622 @item @code{fa526} -- resembles arm920 (w/o Thumb).
4623 @item @code{feroceon} -- resembles arm926.
4624 @item @code{hla_target} -- a Cortex-M alternative to work with HL adapters like ST-Link.
4625 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4626 allowing access to physical memory addresses independently of CPU cores.
4627 @item @code{mem_ap} -- this is an ARM debug infrastructure Access Port without
4628 a CPU, through which bus read and write cycles can be generated; it may be
4629 useful for working with non-CPU hardware behind an AP or during development of
4630 support for new CPUs.
4631 It's possible to connect a GDB client to this target (the GDB port has to be
4632 specified, @xref{gdbportoverride,,option -gdb-port}.), and a fake ARM core will
4633 be emulated to comply to GDB remote protocol.
4634 @item @code{mips_m4k} -- a MIPS core.
4635 @item @code{mips_mips64} -- a MIPS64 core.
4636 @item @code{nds32_v2} -- this is an Andes NDS32 v2 core.
4637 @item @code{nds32_v3} -- this is an Andes NDS32 v3 core.
4638 @item @code{nds32_v3m} -- this is an Andes NDS32 v3m core.
4639 @item @code{or1k} -- this is an OpenRISC 1000 core.
4640 The current implementation supports three JTAG TAP cores:
4641 @itemize @minus
4642 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project@comma{}jtag})
4643 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4644 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4645 @end itemize
4646 And two debug interfaces cores:
4647 @itemize @minus
4648 @item @code{Advanced debug interface}
4649 @*(See: @url{http://opencores.org/project@comma{}adv_debug_sys})
4650 @item @code{SoC Debug Interface}
4651 @*(See: @url{http://opencores.org/project@comma{}dbg_interface})
4652 @end itemize
4653 @item @code{quark_d20xx} -- an Intel Quark D20xx core.
4654 @item @code{quark_x10xx} -- an Intel Quark X10xx core.
4655 @item @code{riscv} -- a RISC-V core.
4656 @item @code{stm8} -- implements an STM8 core.
4657 @item @code{testee} -- a dummy target for cases without a real CPU, e.g. CPLD.
4658 @item @code{xscale} -- this is actually an architecture,
4659 not a CPU type. It is based on the ARMv5 architecture.
4660 @end itemize
4661 @end deffn
4662
4663 To avoid being confused by the variety of ARM based cores, remember
4664 this key point: @emph{ARM is a technology licencing company}.
4665 (See: @url{http://www.arm.com}.)
4666 The CPU name used by OpenOCD will reflect the CPU design that was
4667 licensed, not a vendor brand which incorporates that design.
4668 Name prefixes like arm7, arm9, arm11, and cortex
4669 reflect design generations;
4670 while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
4671 reflect an architecture version implemented by a CPU design.
4672
4673 @anchor{targetconfiguration}
4674 @section Target Configuration
4675
4676 Before creating a ``target'', you must have added its TAP to the scan chain.
4677 When you've added that TAP, you will have a @code{dotted.name}
4678 which is used to set up the CPU support.
4679 The chip-specific configuration file will normally configure its CPU(s)
4680 right after it adds all of the chip's TAPs to the scan chain.
4681
4682 Although you can set up a target in one step, it's often clearer if you
4683 use shorter commands and do it in two steps: create it, then configure
4684 optional parts.
4685 All operations on the target after it's created will use a new
4686 command, created as part of target creation.
4687
4688 The two main things to configure after target creation are
4689 a work area, which usually has target-specific defaults even
4690 if the board setup code overrides them later;
4691 and event handlers (@pxref{targetevents,,Target Events}), which tend
4692 to be much more board-specific.
4693 The key steps you use might look something like this
4694
4695 @example
4696 dap create mychip.dap -chain-position mychip.cpu
4697 target create MyTarget cortex_m -dap mychip.dap
4698 MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4699 MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4700 MyTarget configure -event reset-init @{ myboard_reinit @}
4701 @end example
4702
4703 You should specify a working area if you can; typically it uses some
4704 on-chip SRAM.
4705 Such a working area can speed up many things, including bulk
4706 writes to target memory;
4707 flash operations like checking to see if memory needs to be erased;
4708 GDB memory checksumming;
4709 and more.
4710
4711 @quotation Warning
4712 On more complex chips, the work area can become
4713 inaccessible when application code
4714 (such as an operating system)
4715 enables or disables the MMU.
4716 For example, the particular MMU context used to access the virtual
4717 address will probably matter ... and that context might not have
4718 easy access to other addresses needed.
4719 At this writing, OpenOCD doesn't have much MMU intelligence.
4720 @end quotation
4721
4722 It's often very useful to define a @code{reset-init} event handler.
4723 For systems that are normally used with a boot loader,
4724 common tasks include updating clocks and initializing memory
4725 controllers.
4726 That may be needed to let you write the boot loader into flash,
4727 in order to ``de-brick'' your board; or to load programs into
4728 external DDR memory without having run the boot loader.
4729
4730 @deffn {Config Command} {target create} target_name type configparams...
4731 This command creates a GDB debug target that refers to a specific JTAG tap.
4732 It enters that target into a list, and creates a new
4733 command (@command{@var{target_name}}) which is used for various
4734 purposes including additional configuration.
4735
4736 @itemize @bullet
4737 @item @var{target_name} ... is the name of the debug target.
4738 By convention this should be the same as the @emph{dotted.name}
4739 of the TAP associated with this target, which must be specified here
4740 using the @code{-chain-position @var{dotted.name}} configparam.
4741
4742 This name is also used to create the target object command,
4743 referred to here as @command{$target_name},
4744 and in other places the target needs to be identified.
4745 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4746 @item @var{configparams} ... all parameters accepted by
4747 @command{$target_name configure} are permitted.
4748 If the target is big-endian, set it here with @code{-endian big}.
4749
4750 You @emph{must} set the @code{-chain-position @var{dotted.name}} or
4751 @code{-dap @var{dap_name}} here.
4752 @end itemize
4753 @end deffn
4754
4755 @deffn {Command} {$target_name configure} configparams...
4756 The options accepted by this command may also be
4757 specified as parameters to @command{target create}.
4758 Their values can later be queried one at a time by
4759 using the @command{$target_name cget} command.
4760
4761 @emph{Warning:} changing some of these after setup is dangerous.
4762 For example, moving a target from one TAP to another;
4763 and changing its endianness.
4764
4765 @itemize @bullet
4766
4767 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4768 used to access this target.
4769
4770 @item @code{-dap} @var{dap_name} -- names the DAP used to access
4771 this target. @xref{dapdeclaration,,DAP declaration}, on how to
4772 create and manage DAP instances.
4773
4774 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4775 whether the CPU uses big or little endian conventions
4776
4777 @item @code{-event} @var{event_name} @var{event_body} --
4778 @xref{targetevents,,Target Events}.
4779 Note that this updates a list of named event handlers.
4780 Calling this twice with two different event names assigns
4781 two different handlers, but calling it twice with the
4782 same event name assigns only one handler.
4783
4784 Current target is temporarily overridden to the event issuing target
4785 before handler code starts and switched back after handler is done.
4786
4787 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4788 whether the work area gets backed up; by default,
4789 @emph{it is not backed up.}
4790 When possible, use a working_area that doesn't need to be backed up,
4791 since performing a backup slows down operations.
4792 For example, the beginning of an SRAM block is likely to
4793 be used by most build systems, but the end is often unused.
4794
4795 @item @code{-work-area-size} @var{size} -- specify work are size,
4796 in bytes. The same size applies regardless of whether its physical
4797 or virtual address is being used.
4798
4799 @item @code{-work-area-phys} @var{address} -- set the work area
4800 base @var{address} to be used when no MMU is active.
4801
4802 @item @code{-work-area-virt} @var{address} -- set the work area
4803 base @var{address} to be used when an MMU is active.
4804 @emph{Do not specify a value for this except on targets with an MMU.}
4805 The value should normally correspond to a static mapping for the
4806 @code{-work-area-phys} address, set up by the current operating system.
4807
4808 @anchor{rtostype}
4809 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4810 @var{rtos_type} can be one of @option{auto}, @option{eCos},
4811 @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
4812 @option{embKernel}, @option{mqx}, @option{uCOS-III}, @option{nuttx},
4813 @option{RIOT}, @option{Zephyr}
4814 @xref{gdbrtossupport,,RTOS Support}.
4815
4816 @item @code{-defer-examine} -- skip target examination at initial JTAG chain
4817 scan and after a reset. A manual call to arp_examine is required to
4818 access the target for debugging.
4819
4820 @item @code{-ap-num} @var{ap_number} -- set DAP access port for target,
4821 @var{ap_number} is the numeric index of the DAP AP the target is connected to.
4822 Use this option with systems where multiple, independent cores are connected
4823 to separate access ports of the same DAP.
4824
4825 @item @code{-cti} @var{cti_name} -- set Cross-Trigger Interface (CTI) connected
4826 to the target. Currently, only the @code{aarch64} target makes use of this option,
4827 where it is a mandatory configuration for the target run control.
4828 @xref{armcrosstrigger,,ARM Cross-Trigger Interface},
4829 for instruction on how to declare and control a CTI instance.
4830
4831 @anchor{gdbportoverride}
4832 @item @code{-gdb-port} @var{number} -- see command @command{gdb_port} for the
4833 possible values of the parameter @var{number}, which are not only numeric values.
4834 Use this option to override, for this target only, the global parameter set with
4835 command @command{gdb_port}.
4836 @xref{gdb_port,,command gdb_port}.
4837
4838 @item @code{-gdb-max-connections} @var{number} -- EXPERIMENTAL: set the maximum
4839 number of GDB connections that are allowed for the target. Default is 1.
4840 A negative value for @var{number} means unlimited connections.
4841 See @xref{gdbmeminspect,,Using GDB as a non-intrusive memory inspector}.
4842 @end itemize
4843 @end deffn
4844
4845 @section Other $target_name Commands
4846 @cindex object command
4847
4848 The Tcl/Tk language has the concept of object commands,
4849 and OpenOCD adopts that same model for targets.
4850
4851 A good Tk example is a on screen button.
4852 Once a button is created a button
4853 has a name (a path in Tk terms) and that name is useable as a first
4854 class command. For example in Tk, one can create a button and later
4855 configure it like this:
4856
4857 @example
4858 # Create
4859 button .foobar -background red -command @{ foo @}
4860 # Modify
4861 .foobar configure -foreground blue
4862 # Query
4863 set x [.foobar cget -background]
4864 # Report
4865 puts [format "The button is %s" $x]
4866 @end example
4867
4868 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4869 button, and its object commands are invoked the same way.
4870
4871 @example
4872 str912.cpu mww 0x1234 0x42
4873 omap3530.cpu mww 0x5555 123
4874 @end example
4875
4876 The commands supported by OpenOCD target objects are: