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1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
11
12 @include version.texi
13
14 @copying
15
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
20
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009 David Brownell
27 @end itemize
28
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
38
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
45
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
50
51 @summarycontents
52 @contents
53
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
57
58 @insertcopying
59 @end ifnottex
60
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developers
64 * JTAG Hardware Dongles:: JTAG Hardware Dongles
65 * About JIM-Tcl:: About JIM-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Interface - Dongle Configuration:: Interface - Dongle Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * TFTP:: TFTP
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * Upgrading:: Deprecated/Removed Commands
85 * Target Library:: Target Library
86 * FAQ:: Frequently Asked Questions
87 * Tcl Crash Course:: Tcl Crash Course
88 * License:: GNU Free Documentation License
89
90 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
91 @comment case issue with ``Index.html'' and ``index.html''
92 @comment Occurs when creating ``--html --no-split'' output
93 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
94 * OpenOCD Concept Index:: Concept Index
95 * Command and Driver Index:: Command and Driver Index
96 @end menu
97
98 @node About
99 @unnumbered About
100 @cindex about
101
102 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
103 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
104 Since that time, the project has grown into an active open-source project,
105 supported by a diverse community of software and hardware developers from
106 around the world.
107
108 @section What is OpenOCD?
109 @cindex TAP
110 @cindex JTAG
111
112 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
113 in-system programming and boundary-scan testing for embedded target
114 devices.
115
116 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
117 with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
118 A @dfn{TAP} is a ``Test Access Port'', a module which processes
119 special instructions and data. TAPs are daisy-chained within and
120 between chips and boards.
121
122 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
123 based, parallel port based, and other standalone boxes that run
124 OpenOCD internally. @xref{JTAG Hardware Dongles}.
125
126 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
127 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
128 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
129 debugged via the GDB protocol.
130
131 @b{Flash Programing:} Flash writing is supported for external CFI
132 compatible NOR flashes (Intel and AMD/Spansion command set) and several
133 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
134 STM32x). Preliminary support for various NAND flash controllers
135 (LPC3180, Orion, S3C24xx, more) controller is included.
136
137 @section OpenOCD Web Site
138
139 The OpenOCD web site provides the latest public news from the community:
140
141 @uref{http://openocd.berlios.de/web/}
142
143 @section Latest User's Guide:
144
145 The user's guide you are now reading may not be the latest one
146 available. A version for more recent code may be available.
147 Its HTML form is published irregularly at:
148
149 @uref{http://openocd.berlios.de/doc/html/index.html}
150
151 PDF form is likewise published at:
152
153 @uref{http://openocd.berlios.de/doc/pdf/openocd.pdf}
154
155 @section OpenOCD User's Forum
156
157 There is an OpenOCD forum (phpBB) hosted by SparkFun:
158
159 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
160
161
162 @node Developers
163 @chapter OpenOCD Developer Resources
164 @cindex developers
165
166 If you are interested in improving the state of OpenOCD's debugging and
167 testing support, new contributions will be welcome. Motivated developers
168 can produce new target, flash or interface drivers, improve the
169 documentation, as well as more conventional bug fixes and enhancements.
170
171 The resources in this chapter are available for developers wishing to explore
172 or expand the OpenOCD source code.
173
174 @section OpenOCD Subversion Repository
175
176 You can download the current SVN version with an SVN client of your
177 choice from the following repositories:
178
179 @uref{svn://svn.berlios.de/openocd/trunk}
180
181 or
182
183 @uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
184
185 Using the SVN command line client, you can use the following command to
186 fetch the latest version (make sure there is no (non-svn) directory
187 called "openocd" in the current directory):
188
189 svn checkout svn://svn.berlios.de/openocd/trunk openocd
190
191 If you prefer GIT based tools, the @command{git-svn} package works too:
192
193 git svn clone -s svn://svn.berlios.de/openocd
194
195 The ``README'' file contains the instructions for building the project
196 from the repository.
197
198 Developers that want to contribute patches to the OpenOCD system are
199 @b{strongly} encouraged to base their work off of the most recent trunk
200 revision. Patches created against older versions may require additional
201 work from their submitter in order to be updated for newer releases.
202
203 @section Doxygen Developer Manual
204
205 During the development of the 0.2.0 release, the OpenOCD project began
206 providing a Doxygen reference manual. This document contains more
207 technical information about the software internals, development
208 processes, and similar documentation:
209
210 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
211
212 This document is a work-in-progress, but contributions would be welcome
213 to fill in the gaps. All of the source files are provided in-tree,
214 listed in the Doxyfile configuration in the top of the repository trunk.
215
216 @section OpenOCD Developer Mailing List
217
218 The OpenOCD Developer Mailing List provides the primary means of
219 communication between developers:
220
221 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
222
223 All drivers developers are enouraged to also subscribe to the list of
224 SVN commits to keep pace with the ongoing changes:
225
226 @uref{https://lists.berlios.de/mailman/listinfo/openocd-svn}
227
228
229 @node JTAG Hardware Dongles
230 @chapter JTAG Hardware Dongles
231 @cindex dongles
232 @cindex FTDI
233 @cindex wiggler
234 @cindex zy1000
235 @cindex printer port
236 @cindex USB Adapter
237 @cindex RTCK
238
239 Defined: @b{dongle}: A small device that plugins into a computer and serves as
240 an adapter .... [snip]
241
242 In the OpenOCD case, this generally refers to @b{a small adapater} one
243 attaches to your computer via USB or the Parallel Printer Port. The
244 execption being the Zylin ZY1000 which is a small box you attach via
245 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
246 require any drivers to be installed on the developer PC. It also has
247 a built in web interface. It supports RTCK/RCLK or adaptive clocking
248 and has a built in relay to power cycle targets remotely.
249
250
251 @section Choosing a Dongle
252
253 There are several things you should keep in mind when choosing a dongle.
254
255 @enumerate
256 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
257 Does your dongle support it? You might need a level converter.
258 @item @b{Pinout} What pinout does your target board use?
259 Does your dongle support it? You may be able to use jumper
260 wires, or an "octopus" connector, to convert pinouts.
261 @item @b{Connection} Does your computer have the USB, printer, or
262 Ethernet port needed?
263 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
264 @end enumerate
265
266 @section Stand alone Systems
267
268 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
269 dongle, but a standalone box. The ZY1000 has the advantage that it does
270 not require any drivers installed on the developer PC. It also has
271 a built in web interface. It supports RTCK/RCLK or adaptive clocking
272 and has a built in relay to power cycle targets remotely.
273
274 @section USB FT2232 Based
275
276 There are many USB JTAG dongles on the market, many of them are based
277 on a chip from ``Future Technology Devices International'' (FTDI)
278 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
279 See: @url{http://www.ftdichip.com} for more information.
280 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
281 chips are starting to become available in JTAG adapters.
282
283 @itemize @bullet
284 @item @b{usbjtag}
285 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
286 @item @b{jtagkey}
287 @* See: @url{http://www.amontec.com/jtagkey.shtml}
288 @item @b{jtagkey2}
289 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
290 @item @b{oocdlink}
291 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
292 @item @b{signalyzer}
293 @* See: @url{http://www.signalyzer.com}
294 @item @b{evb_lm3s811}
295 @* See: @url{http://www.luminarymicro.com} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
296 @item @b{luminary_icdi}
297 @* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug Interface (ICDI) Board, included in the Stellaris LM3S9B90 and LM3S9B92 Evaluation Kits.
298 @item @b{olimex-jtag}
299 @* See: @url{http://www.olimex.com}
300 @item @b{flyswatter}
301 @* See: @url{http://www.tincantools.com}
302 @item @b{turtelizer2}
303 @* See:
304 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
305 @url{http://www.ethernut.de}
306 @item @b{comstick}
307 @* Link: @url{http://www.hitex.com/index.php?id=383}
308 @item @b{stm32stick}
309 @* Link @url{http://www.hitex.com/stm32-stick}
310 @item @b{axm0432_jtag}
311 @* Axiom AXM-0432 Link @url{http://www.axman.com}
312 @item @b{cortino}
313 @* Link @url{http://www.hitex.com/index.php?id=cortino}
314 @end itemize
315
316 @section USB JLINK based
317 There are several OEM versions of the Segger @b{JLINK} adapter. It is
318 an example of a micro controller based JTAG adapter, it uses an
319 AT91SAM764 internally.
320
321 @itemize @bullet
322 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
323 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
324 @item @b{SEGGER JLINK}
325 @* Link: @url{http://www.segger.com/jlink.html}
326 @item @b{IAR J-Link}
327 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
328 @end itemize
329
330 @section USB RLINK based
331 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
332
333 @itemize @bullet
334 @item @b{Raisonance RLink}
335 @* Link: @url{http://www.raisonance.com/products/RLink.php}
336 @item @b{STM32 Primer}
337 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
338 @item @b{STM32 Primer2}
339 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
340 @end itemize
341
342 @section USB Other
343 @itemize @bullet
344 @item @b{USBprog}
345 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
346
347 @item @b{USB - Presto}
348 @* Link: @url{http://tools.asix.net/prg_presto.htm}
349
350 @item @b{Versaloon-Link}
351 @* Link: @url{http://www.simonqian.com/en/Versaloon}
352
353 @item @b{ARM-JTAG-EW}
354 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
355 @end itemize
356
357 @section IBM PC Parallel Printer Port Based
358
359 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
360 and the MacGraigor Wiggler. There are many clones and variations of
361 these on the market.
362
363 Note that parallel ports are becoming much less common, so if you
364 have the choice you should probably avoid these adapters in favor
365 of USB-based ones.
366
367 @itemize @bullet
368
369 @item @b{Wiggler} - There are many clones of this.
370 @* Link: @url{http://www.macraigor.com/wiggler.htm}
371
372 @item @b{DLC5} - From XILINX - There are many clones of this
373 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
374 produced, PDF schematics are easily found and it is easy to make.
375
376 @item @b{Amontec - JTAG Accelerator}
377 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
378
379 @item @b{GW16402}
380 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
381
382 @item @b{Wiggler2}
383 @*@uref{http://www.ccac.rwth-aachen.de/@/~michaels/@/index.php/hardware/@/armjtag,
384 Improved parallel-port wiggler-style JTAG adapter}
385
386 @item @b{Wiggler_ntrst_inverted}
387 @* Yet another variation - See the source code, src/jtag/parport.c
388
389 @item @b{old_amt_wiggler}
390 @* Unknown - probably not on the market today
391
392 @item @b{arm-jtag}
393 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
394
395 @item @b{chameleon}
396 @* Link: @url{http://www.amontec.com/chameleon.shtml}
397
398 @item @b{Triton}
399 @* Unknown.
400
401 @item @b{Lattice}
402 @* ispDownload from Lattice Semiconductor
403 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
404
405 @item @b{flashlink}
406 @* From ST Microsystems;
407 @uref{http://www.st.com/stonline/@/products/literature/um/7889.pdf,
408 FlashLINK JTAG programing cable for PSD and uPSD}
409
410 @end itemize
411
412 @section Other...
413 @itemize @bullet
414
415 @item @b{ep93xx}
416 @* An EP93xx based Linux machine using the GPIO pins directly.
417
418 @item @b{at91rm9200}
419 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
420
421 @end itemize
422
423 @node About JIM-Tcl
424 @chapter About JIM-Tcl
425 @cindex JIM Tcl
426 @cindex tcl
427
428 OpenOCD includes a small ``Tcl Interpreter'' known as JIM-Tcl.
429 This programming language provides a simple and extensible
430 command interpreter.
431
432 All commands presented in this Guide are extensions to JIM-Tcl.
433 You can use them as simple commands, without needing to learn
434 much of anything about Tcl.
435 Alternatively, can write Tcl programs with them.
436
437 You can learn more about JIM at its website, @url{http://jim.berlios.de}.
438
439 @itemize @bullet
440 @item @b{JIM vs. Tcl}
441 @* JIM-TCL is a stripped down version of the well known Tcl language,
442 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
443 fewer features. JIM-Tcl is a single .C file and a single .H file and
444 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
445 4.2 MB .zip file containing 1540 files.
446
447 @item @b{Missing Features}
448 @* Our practice has been: Add/clone the real Tcl feature if/when
449 needed. We welcome JIM Tcl improvements, not bloat.
450
451 @item @b{Scripts}
452 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
453 command interpreter today is a mixture of (newer)
454 JIM-Tcl commands, and (older) the orginal command interpreter.
455
456 @item @b{Commands}
457 @* At the OpenOCD telnet command line (or via the GDB mon command) one
458 can type a Tcl for() loop, set variables, etc.
459 Some of the commands documented in this guide are implemented
460 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
461
462 @item @b{Historical Note}
463 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
464
465 @item @b{Need a crash course in Tcl?}
466 @*@xref{Tcl Crash Course}.
467 @end itemize
468
469 @node Running
470 @chapter Running
471 @cindex command line options
472 @cindex logfile
473 @cindex directory search
474
475 The @option{--help} option shows:
476 @verbatim
477 bash$ openocd --help
478
479 --help | -h display this help
480 --version | -v display OpenOCD version
481 --file | -f use configuration file <name>
482 --search | -s dir to search for config files and scripts
483 --debug | -d set debug level <0-3>
484 --log_output | -l redirect log output to file <name>
485 --command | -c run <command>
486 --pipe | -p use pipes when talking to gdb
487 @end verbatim
488
489 By default OpenOCD reads the file configuration file @file{openocd.cfg}
490 in the current directory. To specify a different (or multiple)
491 configuration file, you can use the ``-f'' option. For example:
492
493 @example
494 openocd -f config1.cfg -f config2.cfg -f config3.cfg
495 @end example
496
497 OpenOCD starts by processing the configuration commands provided
498 on the command line or in @file{openocd.cfg}.
499 @xref{Configuration Stage}.
500 At the end of the configuration stage it verifies the JTAG scan
501 chain defined using those commands; your configuration should
502 ensure that this always succeeds.
503 Normally, OpenOCD then starts running as a daemon.
504 Alternatively, commands may be used to terminate the configuration
505 stage early, perform work (such as updating some flash memory),
506 and then shut down without acting as a daemon.
507
508 Once OpenOCD starts running as a daemon, it waits for connections from
509 clients (Telnet, GDB, Other) and processes the commands issued through
510 those channels.
511
512 If you are having problems, you can enable internal debug messages via
513 the ``-d'' option.
514
515 Also it is possible to interleave JIM-Tcl commands w/config scripts using the
516 @option{-c} command line switch.
517
518 To enable debug output (when reporting problems or working on OpenOCD
519 itself), use the @option{-d} command line switch. This sets the
520 @option{debug_level} to "3", outputting the most information,
521 including debug messages. The default setting is "2", outputting only
522 informational messages, warnings and errors. You can also change this
523 setting from within a telnet or gdb session using @command{debug_level
524 <n>} (@pxref{debug_level}).
525
526 You can redirect all output from the daemon to a file using the
527 @option{-l <logfile>} switch.
528
529 Search paths for config/script files can be added to OpenOCD by using
530 the @option{-s <search>} switch. The current directory and the OpenOCD
531 target library is in the search path by default.
532
533 For details on the @option{-p} option. @xref{Connecting to GDB}.
534
535 Note! OpenOCD will launch the GDB & telnet server even if it can not
536 establish a connection with the target. In general, it is possible for
537 the JTAG controller to be unresponsive until the target is set up
538 correctly via e.g. GDB monitor commands in a GDB init script.
539
540 @node OpenOCD Project Setup
541 @chapter OpenOCD Project Setup
542
543 To use OpenOCD with your development projects, you need to do more than
544 just connecting the JTAG adapter hardware (dongle) to your development board
545 and then starting the OpenOCD server.
546 You also need to configure that server so that it knows
547 about that adapter and board, and helps your work.
548
549 @section Hooking up the JTAG Adapter
550
551 Today's most common case is a dongle with a JTAG cable on one side
552 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
553 and a USB cable on the other.
554 Instead of USB, some cables use Ethernet;
555 older ones may use a PC parallel port, or even a serial port.
556
557 @enumerate
558 @item @emph{Start with power to your target board turned off},
559 and nothing connected to your JTAG adapter.
560 If you're particularly paranoid, unplug power to the board.
561 It's important to have the ground signal properly set up,
562 unless you are using a JTAG adapter which provides
563 galvanic isolation between the target board and the
564 debugging host.
565
566 @item @emph{Be sure it's the right kind of JTAG connector.}
567 If your dongle has a 20-pin ARM connector, you need some kind
568 of adapter (or octopus, see below) to hook it up to
569 boards using 14-pin or 10-pin connectors ... or to 20-pin
570 connectors which don't use ARM's pinout.
571
572 In the same vein, make sure the voltage levels are compatible.
573 Not all JTAG adapters have the level shifters needed to work
574 with 1.2 Volt boards.
575
576 @item @emph{Be certain the cable is properly oriented} or you might
577 damage your board. In most cases there are only two possible
578 ways to connect the cable.
579 Connect the JTAG cable from your adapter to the board.
580 Be sure it's firmly connected.
581
582 In the best case, the connector is keyed to physically
583 prevent you from inserting it wrong.
584 This is most often done using a slot on the board's male connector
585 housing, which must match a key on the JTAG cable's female connector.
586 If there's no housing, then you must look carefully and
587 make sure pin 1 on the cable hooks up to pin 1 on the board.
588 Ribbon cables are frequently all grey except for a wire on one
589 edge, which is red. The red wire is pin 1.
590
591 Sometimes dongles provide cables where one end is an ``octopus'' of
592 color coded single-wire connectors, instead of a connector block.
593 These are great when converting from one JTAG pinout to another,
594 but are tedious to set up.
595 Use these with connector pinout diagrams to help you match up the
596 adapter signals to the right board pins.
597
598 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
599 A USB, parallel, or serial port connector will go to the host which
600 you are using to run OpenOCD.
601 For Ethernet, consult the documentation and your network administrator.
602
603 For USB based JTAG adapters you have an easy sanity check at this point:
604 does the host operating system see the JTAG adapter?
605
606 @item @emph{Connect the adapter's power supply, if needed.}
607 This step is primarily for non-USB adapters,
608 but sometimes USB adapters need extra power.
609
610 @item @emph{Power up the target board.}
611 Unless you just let the magic smoke escape,
612 you're now ready to set up the OpenOCD server
613 so you can use JTAG to work with that board.
614
615 @end enumerate
616
617 Talk with the OpenOCD server using
618 telnet (@code{telnet localhost 4444} on many systems) or GDB.
619 @xref{GDB and OpenOCD}.
620
621 @section Project Directory
622
623 There are many ways you can configure OpenOCD and start it up.
624
625 A simple way to organize them all involves keeping a
626 single directory for your work with a given board.
627 When you start OpenOCD from that directory,
628 it searches there first for configuration files, scripts,
629 and for code you upload to the target board.
630 It is also the natural place to write files,
631 such as log files and data you download from the board.
632
633 @section Configuration Basics
634
635 There are two basic ways of configuring OpenOCD, and
636 a variety of ways you can mix them.
637 Think of the difference as just being how you start the server:
638
639 @itemize
640 @item Many @option{-f file} or @option{-c command} options on the command line
641 @item No options, but a @dfn{user config file}
642 in the current directory named @file{openocd.cfg}
643 @end itemize
644
645 Here is an example @file{openocd.cfg} file for a setup
646 using a Signalyzer FT2232-based JTAG adapter to talk to
647 a board with an Atmel AT91SAM7X256 microcontroller:
648
649 @example
650 source [find interface/signalyzer.cfg]
651
652 # GDB can also flash my flash!
653 gdb_memory_map enable
654 gdb_flash_program enable
655
656 source [find target/sam7x256.cfg]
657 @end example
658
659 Here is the command line equivalent of that configuration:
660
661 @example
662 openocd -f interface/signalyzer.cfg \
663 -c "gdb_memory_map enable" \
664 -c "gdb_flash_program enable" \
665 -f target/sam7x256.cfg
666 @end example
667
668 You could wrap such long command lines in shell scripts,
669 each supporting a different development task.
670 One might re-flash the board with a specific firmware version.
671 Another might set up a particular debugging or run-time environment.
672
673 Here we will focus on the simpler solution: one user config
674 file, including basic configuration plus any TCL procedures
675 to simplify your work.
676
677 @section User Config Files
678 @cindex config file, user
679 @cindex user config file
680 @cindex config file, overview
681
682 A user configuration file ties together all the parts of a project
683 in one place.
684 One of the following will match your situation best:
685
686 @itemize
687 @item Ideally almost everything comes from configuration files
688 provided by someone else.
689 For example, OpenOCD distributes a @file{scripts} directory
690 (probably in @file{/usr/share/openocd/scripts} on Linux).
691 Board and tool vendors can provide these too, as can individual
692 user sites; the @option{-s} command line option lets you say
693 where to find these files. (@xref{Running}.)
694 The AT91SAM7X256 example above works this way.
695
696 Three main types of non-user configuration file each have their
697 own subdirectory in the @file{scripts} directory:
698
699 @enumerate
700 @item @b{interface} -- one for each kind of JTAG adapter/dongle
701 @item @b{board} -- one for each different board
702 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
703 @end enumerate
704
705 Best case: include just two files, and they handle everything else.
706 The first is an interface config file.
707 The second is board-specific, and it sets up the JTAG TAPs and
708 their GDB targets (by deferring to some @file{target.cfg} file),
709 declares all flash memory, and leaves you nothing to do except
710 meet your deadline:
711
712 @example
713 source [find interface/olimex-jtag-tiny.cfg]
714 source [find board/csb337.cfg]
715 @end example
716
717 Boards with a single microcontroller often won't need more
718 than the target config file, as in the AT91SAM7X256 example.
719 That's because there is no external memory (flash, DDR RAM), and
720 the board differences are encapsulated by application code.
721
722 @item You can often reuse some standard config files but
723 need to write a few new ones, probably a @file{board.cfg} file.
724 You will be using commands described later in this User's Guide,
725 and working with the guidelines in the next chapter.
726
727 For example, there may be configuration files for your JTAG adapter
728 and target chip, but you need a new board-specific config file
729 giving access to your particular flash chips.
730 Or you might need to write another target chip configuration file
731 for a new chip built around the Cortex M3 core.
732
733 @quotation Note
734 When you write new configuration files, please submit
735 them for inclusion in the next OpenOCD release.
736 For example, a @file{board/newboard.cfg} file will help the
737 next users of that board, and a @file{target/newcpu.cfg}
738 will help support users of any board using that chip.
739 @end quotation
740
741 @item
742 You may may need to write some C code.
743 It may be as simple as a supporting a new ft2232 or parport
744 based dongle; a bit more involved, like a NAND or NOR flash
745 controller driver; or a big piece of work like supporting
746 a new chip architecture.
747 @end itemize
748
749 Reuse the existing config files when you can.
750 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
751 You may find a board configuration that's a good example to follow.
752
753 When you write config files, separate the reusable parts
754 (things every user of that interface, chip, or board needs)
755 from ones specific to your environment and debugging approach.
756 @itemize
757
758 @item
759 For example, a @code{gdb-attach} event handler that invokes
760 the @command{reset init} command will interfere with debugging
761 early boot code, which performs some of the same actions
762 that the @code{reset-init} event handler does.
763
764 @item
765 Likewise, the @command{arm9tdmi vector_catch} command (or
766 @cindex vector_catch
767 its siblings @command{xscale vector_catch}
768 and @command{cortex_m3 vector_catch}) can be a timesaver
769 during some debug sessions, but don't make everyone use that either.
770 Keep those kinds of debugging aids in your user config file,
771 along with messaging and tracing setup.
772 (@xref{Software Debug Messages and Tracing}.)
773
774 @item
775 You might need to override some defaults.
776 For example, you might need to move, shrink, or back up the target's
777 work area if your application needs much SRAM.
778
779 @item
780 TCP/IP port configuration is another example of something which
781 is environment-specific, and should only appear in
782 a user config file. @xref{TCP/IP Ports}.
783 @end itemize
784
785 @section Project-Specific Utilities
786
787 A few project-specific utility
788 routines may well speed up your work.
789 Write them, and keep them in your project's user config file.
790
791 For example, if you are making a boot loader work on a
792 board, it's nice to be able to debug the ``after it's
793 loaded to RAM'' parts separately from the finicky early
794 code which sets up the DDR RAM controller and clocks.
795 A script like this one, or a more GDB-aware sibling,
796 may help:
797
798 @example
799 proc ramboot @{ @} @{
800 # Reset, running the target's "reset-init" scripts
801 # to initialize clocks and the DDR RAM controller.
802 # Leave the CPU halted.
803 reset init
804
805 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
806 load_image u-boot.bin 0x20000000
807
808 # Start running.
809 resume 0x20000000
810 @}
811 @end example
812
813 Then once that code is working you will need to make it
814 boot from NOR flash; a different utility would help.
815 Alternatively, some developers write to flash using GDB.
816 (You might use a similar script if you're working with a flash
817 based microcontroller application instead of a boot loader.)
818
819 @example
820 proc newboot @{ @} @{
821 # Reset, leaving the CPU halted. The "reset-init" event
822 # proc gives faster access to the CPU and to NOR flash;
823 # "reset halt" would be slower.
824 reset init
825
826 # Write standard version of U-Boot into the first two
827 # sectors of NOR flash ... the standard version should
828 # do the same lowlevel init as "reset-init".
829 flash protect 0 0 1 off
830 flash erase_sector 0 0 1
831 flash write_bank 0 u-boot.bin 0x0
832 flash protect 0 0 1 on
833
834 # Reboot from scratch using that new boot loader.
835 reset run
836 @}
837 @end example
838
839 You may need more complicated utility procedures when booting
840 from NAND.
841 That often involves an extra bootloader stage,
842 running from on-chip SRAM to perform DDR RAM setup so it can load
843 the main bootloader code (which won't fit into that SRAM).
844
845 Other helper scripts might be used to write production system images,
846 involving considerably more than just a three stage bootloader.
847
848
849 @node Config File Guidelines
850 @chapter Config File Guidelines
851
852 This chapter is aimed at any user who needs to write a config file,
853 including developers and integrators of OpenOCD and any user who
854 needs to get a new board working smoothly.
855 It provides guidelines for creating those files.
856
857 You should find the following directories under @t{$(INSTALLDIR)/scripts}:
858
859 @itemize @bullet
860 @item @file{interface} ...
861 think JTAG Dongle. Files that configure JTAG adapters go here.
862 @item @file{board} ...
863 think Circuit Board, PWA, PCB, they go by many names. Board files
864 contain initialization items that are specific to a board. For
865 example, the SDRAM initialization sequence for the board, or the type
866 of external flash and what address it uses. Any initialization
867 sequence to enable that external flash or SDRAM should be found in the
868 board file. Boards may also contain multiple targets: two CPUs; or
869 a CPU and an FPGA or CPLD.
870 @item @file{target} ...
871 think chip. The ``target'' directory represents the JTAG TAPs
872 on a chip
873 which OpenOCD should control, not a board. Two common types of targets
874 are ARM chips and FPGA or CPLD chips.
875 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
876 the target config file defines all of them.
877 @end itemize
878
879 The @file{openocd.cfg} user config
880 file may override features in any of the above files by
881 setting variables before sourcing the target file, or by adding
882 commands specific to their situation.
883
884 @section Interface Config Files
885
886 The user config file
887 should be able to source one of these files with a command like this:
888
889 @example
890 source [find interface/FOOBAR.cfg]
891 @end example
892
893 A preconfigured interface file should exist for every interface in use
894 today, that said, perhaps some interfaces have only been used by the
895 sole developer who created it.
896
897 A separate chapter gives information about how to set these up.
898 @xref{Interface - Dongle Configuration}.
899 Read the OpenOCD source code if you have a new kind of hardware interface
900 and need to provide a driver for it.
901
902 @section Board Config Files
903 @cindex config file, board
904 @cindex board config file
905
906 The user config file
907 should be able to source one of these files with a command like this:
908
909 @example
910 source [find board/FOOBAR.cfg]
911 @end example
912
913 The point of a board config file is to package everything
914 about a given board that user config files need to know.
915 In summary the board files should contain (if present)
916
917 @enumerate
918 @item One or more @command{source [target/...cfg]} statements
919 @item NOR flash configuration (@pxref{NOR Configuration})
920 @item NAND flash configuration (@pxref{NAND Configuration})
921 @item Target @code{reset} handlers for SDRAM and I/O configuration
922 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
923 @item All things that are not ``inside a chip''
924 @end enumerate
925
926 Generic things inside target chips belong in target config files,
927 not board config files. So for example a @code{reset-init} event
928 handler should know board-specific oscillator and PLL parameters,
929 which it passes to target-specific utility code.
930
931 The most complex task of a board config file is creating such a
932 @code{reset-init} event handler.
933 Define those handlers last, after you verify the rest of the board
934 configuration works.
935
936 @subsection Communication Between Config files
937
938 In addition to target-specific utility code, another way that
939 board and target config files communicate is by following a
940 convention on how to use certain variables.
941
942 The full Tcl/Tk language supports ``namespaces'', but JIM-Tcl does not.
943 Thus the rule we follow in OpenOCD is this: Variables that begin with
944 a leading underscore are temporary in nature, and can be modified and
945 used at will within a target configuration file.
946
947 Complex board config files can do the things like this,
948 for a board with three chips:
949
950 @example
951 # Chip #1: PXA270 for network side, big endian
952 set CHIPNAME network
953 set ENDIAN big
954 source [find target/pxa270.cfg]
955 # on return: _TARGETNAME = network.cpu
956 # other commands can refer to the "network.cpu" target.
957 $_TARGETNAME configure .... events for this CPU..
958
959 # Chip #2: PXA270 for video side, little endian
960 set CHIPNAME video
961 set ENDIAN little
962 source [find target/pxa270.cfg]
963 # on return: _TARGETNAME = video.cpu
964 # other commands can refer to the "video.cpu" target.
965 $_TARGETNAME configure .... events for this CPU..
966
967 # Chip #3: Xilinx FPGA for glue logic
968 set CHIPNAME xilinx
969 unset ENDIAN
970 source [find target/spartan3.cfg]
971 @end example
972
973 That example is oversimplified because it doesn't show any flash memory,
974 or the @code{reset-init} event handlers to initialize external DRAM
975 or (assuming it needs it) load a configuration into the FPGA.
976 Such features are usually needed for low-level work with many boards,
977 where ``low level'' implies that the board initialization software may
978 not be working. (That's a common reason to need JTAG tools. Another
979 is to enable working with microcontroller-based systems, which often
980 have no debugging support except a JTAG connector.)
981
982 Target config files may also export utility functions to board and user
983 config files. Such functions should use name prefixes, to help avoid
984 naming collisions.
985
986 Board files could also accept input variables from user config files.
987 For example, there might be a @code{J4_JUMPER} setting used to identify
988 what kind of flash memory a development board is using, or how to set
989 up other clocks and peripherals.
990
991 @subsection Variable Naming Convention
992 @cindex variable names
993
994 Most boards have only one instance of a chip.
995 However, it should be easy to create a board with more than
996 one such chip (as shown above).
997 Accordingly, we encourage these conventions for naming
998 variables associated with different @file{target.cfg} files,
999 to promote consistency and
1000 so that board files can override target defaults.
1001
1002 Inputs to target config files include:
1003
1004 @itemize @bullet
1005 @item @code{CHIPNAME} ...
1006 This gives a name to the overall chip, and is used as part of
1007 tap identifier dotted names.
1008 While the default is normally provided by the chip manufacturer,
1009 board files may need to distinguish between instances of a chip.
1010 @item @code{ENDIAN} ...
1011 By default @option{little} - although chips may hard-wire @option{big}.
1012 Chips that can't change endianness don't need to use this variable.
1013 @item @code{CPUTAPID} ...
1014 When OpenOCD examines the JTAG chain, it can be told verify the
1015 chips against the JTAG IDCODE register.
1016 The target file will hold one or more defaults, but sometimes the
1017 chip in a board will use a different ID (perhaps a newer revision).
1018 @end itemize
1019
1020 Outputs from target config files include:
1021
1022 @itemize @bullet
1023 @item @code{_TARGETNAME} ...
1024 By convention, this variable is created by the target configuration
1025 script. The board configuration file may make use of this variable to
1026 configure things like a ``reset init'' script, or other things
1027 specific to that board and that target.
1028 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1029 @code{_TARGETNAME1}, ... etc.
1030 @end itemize
1031
1032 @subsection The reset-init Event Handler
1033 @cindex event, reset-init
1034 @cindex reset-init handler
1035
1036 Board config files run in the OpenOCD configuration stage;
1037 they can't use TAPs or targets, since they haven't been
1038 fully set up yet.
1039 This means you can't write memory or access chip registers;
1040 you can't even verify that a flash chip is present.
1041 That's done later in event handlers, of which the target @code{reset-init}
1042 handler is one of the most important.
1043
1044 Except on microcontrollers, the basic job of @code{reset-init} event
1045 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1046 Microcontrollers rarely use boot loaders; they run right out of their
1047 on-chip flash and SRAM memory. But they may want to use one of these
1048 handlers too, if just for developer convenience.
1049
1050 @quotation Note
1051 Because this is so very board-specific, and chip-specific, no examples
1052 are included here.
1053 Instead, look at the board config files distributed with OpenOCD.
1054 If you have a boot loader, its source code may also be useful.
1055 @end quotation
1056
1057 Some of this code could probably be shared between different boards.
1058 For example, setting up a DRAM controller often doesn't differ by
1059 much except the bus width (16 bits or 32?) and memory timings, so a
1060 reusable TCL procedure loaded by the @file{target.cfg} file might take
1061 those as parameters.
1062 Similarly with oscillator, PLL, and clock setup;
1063 and disabling the watchdog.
1064 Structure the code cleanly, and provide comments to help
1065 the next developer doing such work.
1066 (@emph{You might be that next person} trying to reuse init code!)
1067
1068 The last thing normally done in a @code{reset-init} handler is probing
1069 whatever flash memory was configured. For most chips that needs to be
1070 done while the associated target is halted, either because JTAG memory
1071 access uses the CPU or to prevent conflicting CPU access.
1072
1073 @subsection JTAG Clock Rate
1074
1075 Before your @code{reset-init} handler has set up
1076 the PLLs and clocking, you may need to run with
1077 a low JTAG clock rate.
1078 @xref{JTAG Speed}.
1079 Then you'd increase that rate after your handler has
1080 made it possible to use the faster JTAG clock.
1081 When the initial low speed is board-specific, for example
1082 because it depends on a board-specific oscillator speed, then
1083 you should probably set it up in the board config file;
1084 if it's target-specific, it belongs in the target config file.
1085
1086 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1087 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1088 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1089 Consult chip documentation to determine the peak JTAG clock rate,
1090 which might be less than that.
1091
1092 @quotation Warning
1093 On most ARMs, JTAG clock detection is coupled to the core clock, so
1094 software using a @option{wait for interrupt} operation blocks JTAG access.
1095 Adaptive clocking provides a partial workaround, but a more complete
1096 solution just avoids using that instruction with JTAG debuggers.
1097 @end quotation
1098
1099 If the board supports adaptive clocking, use the @command{jtag_rclk}
1100 command, in case your board is used with JTAG adapter which
1101 also supports it. Otherwise use @command{jtag_khz}.
1102 Set the slow rate at the beginning of the reset sequence,
1103 and the faster rate as soon as the clocks are at full speed.
1104
1105 @section Target Config Files
1106 @cindex config file, target
1107 @cindex target config file
1108
1109 Board config files communicate with target config files using
1110 naming conventions as described above, and may source one or
1111 more target config files like this:
1112
1113 @example
1114 source [find target/FOOBAR.cfg]
1115 @end example
1116
1117 The point of a target config file is to package everything
1118 about a given chip that board config files need to know.
1119 In summary the target files should contain
1120
1121 @enumerate
1122 @item Set defaults
1123 @item Add TAPs to the scan chain
1124 @item Add CPU targets (includes GDB support)
1125 @item CPU/Chip/CPU-Core specific features
1126 @item On-Chip flash
1127 @end enumerate
1128
1129 As a rule of thumb, a target file sets up only one chip.
1130 For a microcontroller, that will often include a single TAP,
1131 which is a CPU needing a GDB target, and its on-chip flash.
1132
1133 More complex chips may include multiple TAPs, and the target
1134 config file may need to define them all before OpenOCD
1135 can talk to the chip.
1136 For example, some phone chips have JTAG scan chains that include
1137 an ARM core for operating system use, a DSP,
1138 another ARM core embedded in an image processing engine,
1139 and other processing engines.
1140
1141 @subsection Default Value Boiler Plate Code
1142
1143 All target configuration files should start with code like this,
1144 letting board config files express environment-specific
1145 differences in how things should be set up.
1146
1147 @example
1148 # Boards may override chip names, perhaps based on role,
1149 # but the default should match what the vendor uses
1150 if @{ [info exists CHIPNAME] @} @{
1151 set _CHIPNAME $CHIPNAME
1152 @} else @{
1153 set _CHIPNAME sam7x256
1154 @}
1155
1156 # ONLY use ENDIAN with targets that can change it.
1157 if @{ [info exists ENDIAN] @} @{
1158 set _ENDIAN $ENDIAN
1159 @} else @{
1160 set _ENDIAN little
1161 @}
1162
1163 # TAP identifiers may change as chips mature, for example with
1164 # new revision fields (the "3" here). Pick a good default; you
1165 # can pass several such identifiers to the "jtag newtap" command.
1166 if @{ [info exists CPUTAPID ] @} @{
1167 set _CPUTAPID $CPUTAPID
1168 @} else @{
1169 set _CPUTAPID 0x3f0f0f0f
1170 @}
1171 @end example
1172 @c but 0x3f0f0f0f is for an str73x part ...
1173
1174 @emph{Remember:} Board config files may include multiple target
1175 config files, or the same target file multiple times
1176 (changing at least @code{CHIPNAME}).
1177
1178 Likewise, the target configuration file should define
1179 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1180 use it later on when defining debug targets:
1181
1182 @example
1183 set _TARGETNAME $_CHIPNAME.cpu
1184 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1185 @end example
1186
1187 @subsection Adding TAPs to the Scan Chain
1188 After the ``defaults'' are set up,
1189 add the TAPs on each chip to the JTAG scan chain.
1190 @xref{TAP Declaration}, and the naming convention
1191 for taps.
1192
1193 In the simplest case the chip has only one TAP,
1194 probably for a CPU or FPGA.
1195 The config file for the Atmel AT91SAM7X256
1196 looks (in part) like this:
1197
1198 @example
1199 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
1200 -expected-id $_CPUTAPID
1201 @end example
1202
1203 A board with two such at91sam7 chips would be able
1204 to source such a config file twice, with different
1205 values for @code{CHIPNAME}, so
1206 it adds a different TAP each time.
1207
1208 If there are one or more nonzero @option{-expected-id} values,
1209 OpenOCD attempts to verify the actual tap id against those values.
1210 It will issue error messages if there is mismatch, which
1211 can help to pinpoint problems in OpenOCD configurations.
1212
1213 @example
1214 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1215 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1216 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1217 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1218 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1219 @end example
1220
1221 There are more complex examples too, with chips that have
1222 multiple TAPs. Ones worth looking at include:
1223
1224 @itemize
1225 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1226 plus a JRC to enable them
1227 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1228 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1229 is not currently used)
1230 @end itemize
1231
1232 @subsection Add CPU targets
1233
1234 After adding a TAP for a CPU, you should set it up so that
1235 GDB and other commands can use it.
1236 @xref{CPU Configuration}.
1237 For the at91sam7 example above, the command can look like this;
1238 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1239 to little endian, and this chip doesn't support changing that.
1240
1241 @example
1242 set _TARGETNAME $_CHIPNAME.cpu
1243 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1244 @end example
1245
1246 Work areas are small RAM areas associated with CPU targets.
1247 They are used by OpenOCD to speed up downloads,
1248 and to download small snippets of code to program flash chips.
1249 If the chip includes a form of ``on-chip-ram'' - and many do - define
1250 a work area if you can.
1251 Again using the at91sam7 as an example, this can look like:
1252
1253 @example
1254 $_TARGETNAME configure -work-area-phys 0x00200000 \
1255 -work-area-size 0x4000 -work-area-backup 0
1256 @end example
1257
1258 @subsection Chip Reset Setup
1259
1260 As a rule, you should put the @command{reset_config} command
1261 into the board file. Most things you think you know about a
1262 chip can be tweaked by the board.
1263
1264 Some chips have specific ways the TRST and SRST signals are
1265 managed. In the unusual case that these are @emph{chip specific}
1266 and can never be changed by board wiring, they could go here.
1267
1268 Some chips need special attention during reset handling if
1269 they're going to be used with JTAG.
1270 An example might be needing to send some commands right
1271 after the target's TAP has been reset, providing a
1272 @code{reset-deassert-post} event handler that writes a chip
1273 register to report that JTAG debugging is being done.
1274
1275 JTAG clocking constraints often change during reset, and in
1276 some cases target config files (rather than board config files)
1277 are the right places to handle some of those issues.
1278 For example, immediately after reset most chips run using a
1279 slower clock than they will use later.
1280 That means that after reset (and potentially, as OpenOCD
1281 first starts up) they must use a slower JTAG clock rate
1282 than they will use later.
1283 @xref{JTAG Speed}.
1284
1285 @quotation Important
1286 When you are debugging code that runs right after chip
1287 reset, getting these issues right is critical.
1288 In particular, if you see intermittent failures when
1289 OpenOCD verifies the scan chain after reset,
1290 look at how you are setting up JTAG clocking.
1291 @end quotation
1292
1293 @subsection ARM Core Specific Hacks
1294
1295 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1296 special high speed download features - enable it.
1297
1298 If present, the MMU, the MPU and the CACHE should be disabled.
1299
1300 Some ARM cores are equipped with trace support, which permits
1301 examination of the instruction and data bus activity. Trace
1302 activity is controlled through an ``Embedded Trace Module'' (ETM)
1303 on one of the core's scan chains. The ETM emits voluminous data
1304 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
1305 If you are using an external trace port,
1306 configure it in your board config file.
1307 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1308 configure it in your target config file.
1309
1310 @example
1311 etm config $_TARGETNAME 16 normal full etb
1312 etb config $_TARGETNAME $_CHIPNAME.etb
1313 @end example
1314
1315 @subsection Internal Flash Configuration
1316
1317 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1318
1319 @b{Never ever} in the ``target configuration file'' define any type of
1320 flash that is external to the chip. (For example a BOOT flash on
1321 Chip Select 0.) Such flash information goes in a board file - not
1322 the TARGET (chip) file.
1323
1324 Examples:
1325 @itemize @bullet
1326 @item at91sam7x256 - has 256K flash YES enable it.
1327 @item str912 - has flash internal YES enable it.
1328 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1329 @item pxa270 - again - CS0 flash - it goes in the board file.
1330 @end itemize
1331
1332 @node Daemon Configuration
1333 @chapter Daemon Configuration
1334 @cindex initialization
1335 The commands here are commonly found in the openocd.cfg file and are
1336 used to specify what TCP/IP ports are used, and how GDB should be
1337 supported.
1338
1339 @anchor{Configuration Stage}
1340 @section Configuration Stage
1341 @cindex configuration stage
1342 @cindex config command
1343
1344 When the OpenOCD server process starts up, it enters a
1345 @emph{configuration stage} which is the only time that
1346 certain commands, @emph{configuration commands}, may be issued.
1347 In this manual, the definition of a configuration command is
1348 presented as a @emph{Config Command}, not as a @emph{Command}
1349 which may be issued interactively.
1350
1351 Those configuration commands include declaration of TAPs,
1352 flash banks,
1353 the interface used for JTAG communication,
1354 and other basic setup.
1355 The server must leave the configuration stage before it
1356 may access or activate TAPs.
1357 After it leaves this stage, configuration commands may no
1358 longer be issued.
1359
1360 The first thing OpenOCD does after leaving the configuration
1361 stage is to verify that it can talk to the scan chain
1362 (list of TAPs) which has been configured.
1363 It will warn if it doesn't find TAPs it expects to find,
1364 or finds TAPs that aren't supposed to be there.
1365 You should see no errors at this point.
1366 If you see errors, resolve them by correcting the
1367 commands you used to configure the server.
1368 Common errors include using an initial JTAG speed that's too
1369 fast, and not providing the right IDCODE values for the TAPs
1370 on the scan chain.
1371
1372 @deffn {Config Command} init
1373 This command terminates the configuration stage and
1374 enters the normal command mode. This can be useful to add commands to
1375 the startup scripts and commands such as resetting the target,
1376 programming flash, etc. To reset the CPU upon startup, add "init" and
1377 "reset" at the end of the config script or at the end of the OpenOCD
1378 command line using the @option{-c} command line switch.
1379
1380 If this command does not appear in any startup/configuration file
1381 OpenOCD executes the command for you after processing all
1382 configuration files and/or command line options.
1383
1384 @b{NOTE:} This command normally occurs at or near the end of your
1385 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1386 targets ready. For example: If your openocd.cfg file needs to
1387 read/write memory on your target, @command{init} must occur before
1388 the memory read/write commands. This includes @command{nand probe}.
1389 @end deffn
1390
1391 @anchor{TCP/IP Ports}
1392 @section TCP/IP Ports
1393 @cindex TCP port
1394 @cindex server
1395 @cindex port
1396 @cindex security
1397 The OpenOCD server accepts remote commands in several syntaxes.
1398 Each syntax uses a different TCP/IP port, which you may specify
1399 only during configuration (before those ports are opened).
1400
1401 For reasons including security, you may wish to prevent remote
1402 access using one or more of these ports.
1403 In such cases, just specify the relevant port number as zero.
1404 If you disable all access through TCP/IP, you will need to
1405 use the command line @option{-pipe} option.
1406
1407 @deffn {Command} gdb_port (number)
1408 @cindex GDB server
1409 Specify or query the first port used for incoming GDB connections.
1410 The GDB port for the
1411 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1412 When not specified during the configuration stage,
1413 the port @var{number} defaults to 3333.
1414 When specified as zero, this port is not activated.
1415 @end deffn
1416
1417 @deffn {Command} tcl_port (number)
1418 Specify or query the port used for a simplified RPC
1419 connection that can be used by clients to issue TCL commands and get the
1420 output from the Tcl engine.
1421 Intended as a machine interface.
1422 When not specified during the configuration stage,
1423 the port @var{number} defaults to 6666.
1424 When specified as zero, this port is not activated.
1425 @end deffn
1426
1427 @deffn {Command} telnet_port (number)
1428 Specify or query the
1429 port on which to listen for incoming telnet connections.
1430 This port is intended for interaction with one human through TCL commands.
1431 When not specified during the configuration stage,
1432 the port @var{number} defaults to 4444.
1433 When specified as zero, this port is not activated.
1434 @end deffn
1435
1436 @anchor{GDB Configuration}
1437 @section GDB Configuration
1438 @cindex GDB
1439 @cindex GDB configuration
1440 You can reconfigure some GDB behaviors if needed.
1441 The ones listed here are static and global.
1442 @xref{Target Configuration}, about configuring individual targets.
1443 @xref{Target Events}, about configuring target-specific event handling.
1444
1445 @anchor{gdb_breakpoint_override}
1446 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
1447 Force breakpoint type for gdb @command{break} commands.
1448 This option supports GDB GUIs which don't
1449 distinguish hard versus soft breakpoints, if the default OpenOCD and
1450 GDB behaviour is not sufficient. GDB normally uses hardware
1451 breakpoints if the memory map has been set up for flash regions.
1452 @end deffn
1453
1454 @deffn {Config Command} gdb_detach (@option{resume}|@option{reset}|@option{halt}|@option{nothing})
1455 Configures what OpenOCD will do when GDB detaches from the daemon.
1456 Default behaviour is @option{resume}.
1457 @end deffn
1458
1459 @anchor{gdb_flash_program}
1460 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
1461 Set to @option{enable} to cause OpenOCD to program the flash memory when a
1462 vFlash packet is received.
1463 The default behaviour is @option{enable}.
1464 @end deffn
1465
1466 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
1467 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
1468 requested. GDB will then know when to set hardware breakpoints, and program flash
1469 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1470 for flash programming to work.
1471 Default behaviour is @option{enable}.
1472 @xref{gdb_flash_program}.
1473 @end deffn
1474
1475 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
1476 Specifies whether data aborts cause an error to be reported
1477 by GDB memory read packets.
1478 The default behaviour is @option{disable};
1479 use @option{enable} see these errors reported.
1480 @end deffn
1481
1482 @anchor{Event Polling}
1483 @section Event Polling
1484
1485 Hardware debuggers are parts of asynchronous systems,
1486 where significant events can happen at any time.
1487 The OpenOCD server needs to detect some of these events,
1488 so it can report them to through TCL command line
1489 or to GDB.
1490
1491 Examples of such events include:
1492
1493 @itemize
1494 @item One of the targets can stop running ... maybe it triggers
1495 a code breakpoint or data watchpoint, or halts itself.
1496 @item Messages may be sent over ``debug message'' channels ... many
1497 targets support such messages sent over JTAG,
1498 for receipt by the person debugging or tools.
1499 @item Loss of power ... some adapters can detect these events.
1500 @item Resets not issued through JTAG ... such reset sources
1501 can include button presses or other system hardware, sometimes
1502 including the target itself (perhaps through a watchdog).
1503 @item Debug instrumentation sometimes supports event triggering
1504 such as ``trace buffer full'' (so it can quickly be emptied)
1505 or other signals (to correlate with code behavior).
1506 @end itemize
1507
1508 None of those events are signaled through standard JTAG signals.
1509 However, most conventions for JTAG connectors include voltage
1510 level and system reset (SRST) signal detection.
1511 Some connectors also include instrumentation signals, which
1512 can imply events when those signals are inputs.
1513
1514 In general, OpenOCD needs to periodically check for those events,
1515 either by looking at the status of signals on the JTAG connector
1516 or by sending synchronous ``tell me your status'' JTAG requests
1517 to the various active targets.
1518 There is a command to manage and monitor that polling,
1519 which is normally done in the background.
1520
1521 @deffn Command poll [@option{on}|@option{off}]
1522 Poll the current target for its current state.
1523 (Also, @pxref{target curstate}.)
1524 If that target is in debug mode, architecture
1525 specific information about the current state is printed.
1526 An optional parameter
1527 allows background polling to be enabled and disabled.
1528
1529 You could use this from the TCL command shell, or
1530 from GDB using @command{monitor poll} command.
1531 @example
1532 > poll
1533 background polling: on
1534 target state: halted
1535 target halted in ARM state due to debug-request, \
1536 current mode: Supervisor
1537 cpsr: 0x800000d3 pc: 0x11081bfc
1538 MMU: disabled, D-Cache: disabled, I-Cache: enabled
1539 >
1540 @end example
1541 @end deffn
1542
1543 @node Interface - Dongle Configuration
1544 @chapter Interface - Dongle Configuration
1545 @cindex config file, interface
1546 @cindex interface config file
1547
1548 JTAG Adapters/Interfaces/Dongles are normally configured
1549 through commands in an interface configuration
1550 file which is sourced by your @file{openocd.cfg} file, or
1551 through a command line @option{-f interface/....cfg} option.
1552
1553 @example
1554 source [find interface/olimex-jtag-tiny.cfg]
1555 @end example
1556
1557 These commands tell
1558 OpenOCD what type of JTAG adapter you have, and how to talk to it.
1559 A few cases are so simple that you only need to say what driver to use:
1560
1561 @example
1562 # jlink interface
1563 interface jlink
1564 @end example
1565
1566 Most adapters need a bit more configuration than that.
1567
1568
1569 @section Interface Configuration
1570
1571 The interface command tells OpenOCD what type of JTAG dongle you are
1572 using. Depending on the type of dongle, you may need to have one or
1573 more additional commands.
1574
1575 @deffn {Config Command} {interface} name
1576 Use the interface driver @var{name} to connect to the
1577 target.
1578 @end deffn
1579
1580 @deffn Command {interface_list}
1581 List the interface drivers that have been built into
1582 the running copy of OpenOCD.
1583 @end deffn
1584
1585 @deffn Command {jtag interface}
1586 Returns the name of the interface driver being used.
1587 @end deffn
1588
1589 @section Interface Drivers
1590
1591 Each of the interface drivers listed here must be explicitly
1592 enabled when OpenOCD is configured, in order to be made
1593 available at run time.
1594
1595 @deffn {Interface Driver} {amt_jtagaccel}
1596 Amontec Chameleon in its JTAG Accelerator configuration,
1597 connected to a PC's EPP mode parallel port.
1598 This defines some driver-specific commands:
1599
1600 @deffn {Config Command} {parport_port} number
1601 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1602 the number of the @file{/dev/parport} device.
1603 @end deffn
1604
1605 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
1606 Displays status of RTCK option.
1607 Optionally sets that option first.
1608 @end deffn
1609 @end deffn
1610
1611 @deffn {Interface Driver} {arm-jtag-ew}
1612 Olimex ARM-JTAG-EW USB adapter
1613 This has one driver-specific command:
1614
1615 @deffn Command {armjtagew_info}
1616 Logs some status
1617 @end deffn
1618 @end deffn
1619
1620 @deffn {Interface Driver} {at91rm9200}
1621 Supports bitbanged JTAG from the local system,
1622 presuming that system is an Atmel AT91rm9200
1623 and a specific set of GPIOs is used.
1624 @c command: at91rm9200_device NAME
1625 @c chooses among list of bit configs ... only one option
1626 @end deffn
1627
1628 @deffn {Interface Driver} {dummy}
1629 A dummy software-only driver for debugging.
1630 @end deffn
1631
1632 @deffn {Interface Driver} {ep93xx}
1633 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1634 @end deffn
1635
1636 @deffn {Interface Driver} {ft2232}
1637 FTDI FT2232 (USB) based devices over one of the userspace libraries.
1638 These interfaces have several commands, used to configure the driver
1639 before initializing the JTAG scan chain:
1640
1641 @deffn {Config Command} {ft2232_device_desc} description
1642 Provides the USB device description (the @emph{iProduct string})
1643 of the FTDI FT2232 device. If not
1644 specified, the FTDI default value is used. This setting is only valid
1645 if compiled with FTD2XX support.
1646 @end deffn
1647
1648 @deffn {Config Command} {ft2232_serial} serial-number
1649 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
1650 in case the vendor provides unique IDs and more than one FT2232 device
1651 is connected to the host.
1652 If not specified, serial numbers are not considered.
1653 (Note that USB serial numbers can be arbitrary Unicode strings,
1654 and are not restricted to containing only decimal digits.)
1655 @end deffn
1656
1657 @deffn {Config Command} {ft2232_layout} name
1658 Each vendor's FT2232 device can use different GPIO signals
1659 to control output-enables, reset signals, and LEDs.
1660 Currently valid layout @var{name} values include:
1661 @itemize @minus
1662 @item @b{axm0432_jtag} Axiom AXM-0432
1663 @item @b{comstick} Hitex STR9 comstick
1664 @item @b{cortino} Hitex Cortino JTAG interface
1665 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
1666 either for the local Cortex-M3 (SRST only)
1667 or in a passthrough mode (neither SRST nor TRST)
1668 @item @b{luminary_icdi} Luminary In-Circuit Debug Interface (ICDI) Board
1669 @item @b{flyswatter} Tin Can Tools Flyswatter
1670 @item @b{icebear} ICEbear JTAG adapter from Section 5
1671 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
1672 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
1673 @item @b{m5960} American Microsystems M5960
1674 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
1675 @item @b{oocdlink} OOCDLink
1676 @c oocdlink ~= jtagkey_prototype_v1
1677 @item @b{sheevaplug} Marvell Sheevaplug development kit
1678 @item @b{signalyzer} Xverve Signalyzer
1679 @item @b{stm32stick} Hitex STM32 Performance Stick
1680 @item @b{turtelizer2} egnite Software turtelizer2
1681 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
1682 @end itemize
1683 @end deffn
1684
1685 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
1686 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1687 default values are used.
1688 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
1689 @example
1690 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1691 @end example
1692 @end deffn
1693
1694 @deffn {Config Command} {ft2232_latency} ms
1695 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1696 ft2232_read() fails to return the expected number of bytes. This can be caused by
1697 USB communication delays and has proved hard to reproduce and debug. Setting the
1698 FT2232 latency timer to a larger value increases delays for short USB packets but it
1699 also reduces the risk of timeouts before receiving the expected number of bytes.
1700 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1701 @end deffn
1702
1703 For example, the interface config file for a
1704 Turtelizer JTAG Adapter looks something like this:
1705
1706 @example
1707 interface ft2232
1708 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
1709 ft2232_layout turtelizer2
1710 ft2232_vid_pid 0x0403 0xbdc8
1711 @end example
1712 @end deffn
1713
1714 @deffn {Interface Driver} {gw16012}
1715 Gateworks GW16012 JTAG programmer.
1716 This has one driver-specific command:
1717
1718 @deffn {Config Command} {parport_port} number
1719 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1720 the number of the @file{/dev/parport} device.
1721 @end deffn
1722 @end deffn
1723
1724 @deffn {Interface Driver} {jlink}
1725 Segger jlink USB adapter
1726 @c command: jlink_info
1727 @c dumps status
1728 @c command: jlink_hw_jtag (2|3)
1729 @c sets version 2 or 3
1730 @end deffn
1731
1732 @deffn {Interface Driver} {parport}
1733 Supports PC parallel port bit-banging cables:
1734 Wigglers, PLD download cable, and more.
1735 These interfaces have several commands, used to configure the driver
1736 before initializing the JTAG scan chain:
1737
1738 @deffn {Config Command} {parport_cable} name
1739 The layout of the parallel port cable used to connect to the target.
1740 Currently valid cable @var{name} values include:
1741
1742 @itemize @minus
1743 @item @b{altium} Altium Universal JTAG cable.
1744 @item @b{arm-jtag} Same as original wiggler except SRST and
1745 TRST connections reversed and TRST is also inverted.
1746 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
1747 in configuration mode. This is only used to
1748 program the Chameleon itself, not a connected target.
1749 @item @b{dlc5} The Xilinx Parallel cable III.
1750 @item @b{flashlink} The ST Parallel cable.
1751 @item @b{lattice} Lattice ispDOWNLOAD Cable
1752 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
1753 some versions of
1754 Amontec's Chameleon Programmer. The new version available from
1755 the website uses the original Wiggler layout ('@var{wiggler}')
1756 @item @b{triton} The parallel port adapter found on the
1757 ``Karo Triton 1 Development Board''.
1758 This is also the layout used by the HollyGates design
1759 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1760 @item @b{wiggler} The original Wiggler layout, also supported by
1761 several clones, such as the Olimex ARM-JTAG
1762 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
1763 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
1764 @end itemize
1765 @end deffn
1766
1767 @deffn {Config Command} {parport_port} number
1768 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1769 the @file{/dev/parport} device
1770
1771 When using PPDEV to access the parallel port, use the number of the parallel port:
1772 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1773 you may encounter a problem.
1774 @end deffn
1775
1776 @deffn {Config Command} {parport_write_on_exit} (on|off)
1777 This will configure the parallel driver to write a known
1778 cable-specific value to the parallel interface on exiting OpenOCD
1779 @end deffn
1780
1781 For example, the interface configuration file for a
1782 classic ``Wiggler'' cable might look something like this:
1783
1784 @example
1785 interface parport
1786 parport_port 0xc8b8
1787 parport_cable wiggler
1788 @end example
1789 @end deffn
1790
1791 @deffn {Interface Driver} {presto}
1792 ASIX PRESTO USB JTAG programmer.
1793 @c command: presto_serial str
1794 @c sets serial number
1795 @end deffn
1796
1797 @deffn {Interface Driver} {rlink}
1798 Raisonance RLink USB adapter
1799 @end deffn
1800
1801 @deffn {Interface Driver} {usbprog}
1802 usbprog is a freely programmable USB adapter.
1803 @end deffn
1804
1805 @deffn {Interface Driver} {vsllink}
1806 vsllink is part of Versaloon which is a versatile USB programmer.
1807
1808 @quotation Note
1809 This defines quite a few driver-specific commands,
1810 which are not currently documented here.
1811 @end quotation
1812 @end deffn
1813
1814 @deffn {Interface Driver} {ZY1000}
1815 This is the Zylin ZY1000 JTAG debugger.
1816
1817 @quotation Note
1818 This defines some driver-specific commands,
1819 which are not currently documented here.
1820 @end quotation
1821
1822 @deffn Command power [@option{on}|@option{off}]
1823 Turn power switch to target on/off.
1824 No arguments: print status.
1825 @end deffn
1826
1827 @end deffn
1828
1829 @anchor{JTAG Speed}
1830 @section JTAG Speed
1831 JTAG clock setup is part of system setup.
1832 It @emph{does not belong with interface setup} since any interface
1833 only knows a few of the constraints for the JTAG clock speed.
1834 Sometimes the JTAG speed is
1835 changed during the target initialization process: (1) slow at
1836 reset, (2) program the CPU clocks, (3) run fast.
1837 Both the "slow" and "fast" clock rates are functions of the
1838 oscillators used, the chip, the board design, and sometimes
1839 power management software that may be active.
1840
1841 The speed used during reset, and the scan chain verification which
1842 follows reset, can be adjusted using a @code{reset-start}
1843 target event handler.
1844 It can then be reconfigured to a faster speed by a
1845 @code{reset-init} target event handler after it reprograms those
1846 CPU clocks, or manually (if something else, such as a boot loader,
1847 sets up those clocks).
1848 @xref{Target Events}.
1849 When the initial low JTAG speed is a chip characteristic, perhaps
1850 because of a required oscillator speed, provide such a handler
1851 in the target config file.
1852 When that speed is a function of a board-specific characteristic
1853 such as which speed oscillator is used, it belongs in the board
1854 config file instead.
1855 In both cases it's safest to also set the initial JTAG clock rate
1856 to that same slow speed, so that OpenOCD never starts up using a
1857 clock speed that's faster than the scan chain can support.
1858
1859 @example
1860 jtag_rclk 3000
1861 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
1862 @end example
1863
1864 If your system supports adaptive clocking (RTCK), configuring
1865 JTAG to use that is probably the most robust approach.
1866 However, it introduces delays to synchronize clocks; so it
1867 may not be the fastest solution.
1868
1869 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
1870 instead of @command{jtag_khz}.
1871
1872 @deffn {Command} jtag_khz max_speed_kHz
1873 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
1874 JTAG interfaces usually support a limited number of
1875 speeds. The speed actually used won't be faster
1876 than the speed specified.
1877
1878 Chip data sheets generally include a top JTAG clock rate.
1879 The actual rate is often a function of a CPU core clock,
1880 and is normally less than that peak rate.
1881 For example, most ARM cores accept at most one sixth of the CPU clock.
1882
1883 Speed 0 (khz) selects RTCK method.
1884 @xref{FAQ RTCK}.
1885 If your system uses RTCK, you won't need to change the
1886 JTAG clocking after setup.
1887 Not all interfaces, boards, or targets support ``rtck''.
1888 If the interface device can not
1889 support it, an error is returned when you try to use RTCK.
1890 @end deffn
1891
1892 @defun jtag_rclk fallback_speed_kHz
1893 @cindex adaptive clocking
1894 @cindex RTCK
1895 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
1896 If that fails (maybe the interface, board, or target doesn't
1897 support it), falls back to the specified frequency.
1898 @example
1899 # Fall back to 3mhz if RTCK is not supported
1900 jtag_rclk 3000
1901 @end example
1902 @end defun
1903
1904 @node Reset Configuration
1905 @chapter Reset Configuration
1906 @cindex Reset Configuration
1907
1908 Every system configuration may require a different reset
1909 configuration. This can also be quite confusing.
1910 Resets also interact with @var{reset-init} event handlers,
1911 which do things like setting up clocks and DRAM, and
1912 JTAG clock rates. (@xref{JTAG Speed}.)
1913 They can also interact with JTAG routers.
1914 Please see the various board files for examples.
1915
1916 @quotation Note
1917 To maintainers and integrators:
1918 Reset configuration touches several things at once.
1919 Normally the board configuration file
1920 should define it and assume that the JTAG adapter supports
1921 everything that's wired up to the board's JTAG connector.
1922
1923 However, the target configuration file could also make note
1924 of something the silicon vendor has done inside the chip,
1925 which will be true for most (or all) boards using that chip.
1926 And when the JTAG adapter doesn't support everything, the
1927 user configuration file will need to override parts of
1928 the reset configuration provided by other files.
1929 @end quotation
1930
1931 @section Types of Reset
1932
1933 There are many kinds of reset possible through JTAG, but
1934 they may not all work with a given board and adapter.
1935 That's part of why reset configuration can be error prone.
1936
1937 @itemize @bullet
1938 @item
1939 @emph{System Reset} ... the @emph{SRST} hardware signal
1940 resets all chips connected to the JTAG adapter, such as processors,
1941 power management chips, and I/O controllers. Normally resets triggered
1942 with this signal behave exactly like pressing a RESET button.
1943 @item
1944 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
1945 just the TAP controllers connected to the JTAG adapter.
1946 Such resets should not be visible to the rest of the system; resetting a
1947 device's the TAP controller just puts that controller into a known state.
1948 @item
1949 @emph{Emulation Reset} ... many devices can be reset through JTAG
1950 commands. These resets are often distinguishable from system
1951 resets, either explicitly (a "reset reason" register says so)
1952 or implicitly (not all parts of the chip get reset).
1953 @item
1954 @emph{Other Resets} ... system-on-chip devices often support
1955 several other types of reset.
1956 You may need to arrange that a watchdog timer stops
1957 while debugging, preventing a watchdog reset.
1958 There may be individual module resets.
1959 @end itemize
1960
1961 In the best case, OpenOCD can hold SRST, then reset
1962 the TAPs via TRST and send commands through JTAG to halt the
1963 CPU at the reset vector before the 1st instruction is executed.
1964 Then when it finally releases the SRST signal, the system is
1965 halted under debugger control before any code has executed.
1966 This is the behavior required to support the @command{reset halt}
1967 and @command{reset init} commands; after @command{reset init} a
1968 board-specific script might do things like setting up DRAM.
1969 (@xref{Reset Command}.)
1970
1971 @anchor{SRST and TRST Issues}
1972 @section SRST and TRST Issues
1973
1974 Because SRST and TRST are hardware signals, they can have a
1975 variety of system-specific constraints. Some of the most
1976 common issues are:
1977
1978 @itemize @bullet
1979
1980 @item @emph{Signal not available} ... Some boards don't wire
1981 SRST or TRST to the JTAG connector. Some JTAG adapters don't
1982 support such signals even if they are wired up.
1983 Use the @command{reset_config} @var{signals} options to say
1984 when either of those signals is not connected.
1985 When SRST is not available, your code might not be able to rely
1986 on controllers having been fully reset during code startup.
1987 Missing TRST is not a problem, since JTAG level resets can
1988 be triggered using with TMS signaling.
1989
1990 @item @emph{Signals shorted} ... Sometimes a chip, board, or
1991 adapter will connect SRST to TRST, instead of keeping them separate.
1992 Use the @command{reset_config} @var{combination} options to say
1993 when those signals aren't properly independent.
1994
1995 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
1996 delay circuit, reset supervisor, or on-chip features can extend
1997 the effect of a JTAG adapter's reset for some time after the adapter
1998 stops issuing the reset. For example, there may be chip or board
1999 requirements that all reset pulses last for at least a
2000 certain amount of time; and reset buttons commonly have
2001 hardware debouncing.
2002 Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
2003 commands to say when extra delays are needed.
2004
2005 @item @emph{Drive type} ... Reset lines often have a pullup
2006 resistor, letting the JTAG interface treat them as open-drain
2007 signals. But that's not a requirement, so the adapter may need
2008 to use push/pull output drivers.
2009 Also, with weak pullups it may be advisable to drive
2010 signals to both levels (push/pull) to minimize rise times.
2011 Use the @command{reset_config} @var{trst_type} and
2012 @var{srst_type} parameters to say how to drive reset signals.
2013
2014 @item @emph{Special initialization} ... Targets sometimes need
2015 special JTAG initialization sequences to handle chip-specific
2016 issues (not limited to errata).
2017 For example, certain JTAG commands might need to be issued while
2018 the system as a whole is in a reset state (SRST active)
2019 but the JTAG scan chain is usable (TRST inactive).
2020 (@xref{JTAG Commands}, where the @command{jtag_reset}
2021 command is presented.)
2022 @end itemize
2023
2024 There can also be other issues.
2025 Some devices don't fully conform to the JTAG specifications.
2026 Trivial system-specific differences are common, such as
2027 SRST and TRST using slightly different names.
2028 There are also vendors who distribute key JTAG documentation for
2029 their chips only to developers who have signed a Non-Disclosure
2030 Agreement (NDA).
2031
2032 Sometimes there are chip-specific extensions like a requirement to use
2033 the normally-optional TRST signal (precluding use of JTAG adapters which
2034 don't pass TRST through), or needing extra steps to complete a TAP reset.
2035
2036 In short, SRST and especially TRST handling may be very finicky,
2037 needing to cope with both architecture and board specific constraints.
2038
2039 @section Commands for Handling Resets
2040
2041 @deffn {Command} jtag_nsrst_delay milliseconds
2042 How long (in milliseconds) OpenOCD should wait after deasserting
2043 nSRST (active-low system reset) before starting new JTAG operations.
2044 When a board has a reset button connected to SRST line it will
2045 probably have hardware debouncing, implying you should use this.
2046 @end deffn
2047
2048 @deffn {Command} jtag_ntrst_delay milliseconds
2049 How long (in milliseconds) OpenOCD should wait after deasserting
2050 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
2051 @end deffn
2052
2053 @deffn {Command} reset_config mode_flag ...
2054 This command tells OpenOCD the reset configuration
2055 of your combination of JTAG board and target in target
2056 configuration scripts.
2057
2058 Information earlier in this section describes the kind of problems
2059 the command is intended to address (@pxref{SRST and TRST Issues}).
2060 As a rule this command belongs only in board config files,
2061 describing issues like @emph{board doesn't connect TRST};
2062 or in user config files, addressing limitations derived
2063 from a particular combination of interface and board.
2064 (An unlikely example would be using a TRST-only adapter
2065 with a board that only wires up SRST.)
2066
2067 The @var{mode_flag} options can be specified in any order, but only one
2068 of each type -- @var{signals}, @var{combination}, @var{trst_type},
2069 and @var{srst_type} -- may be specified at a time.
2070 If you don't provide a new value for a given type, its previous
2071 value (perhaps the default) is unchanged.
2072 For example, this means that you don't need to say anything at all about
2073 TRST just to declare that if the JTAG adapter should want to drive SRST,
2074 it must explicitly be driven high (@option{srst_push_pull}).
2075
2076 @var{signals} can specify which of the reset signals are connected.
2077 For example, If the JTAG interface provides SRST, but the board doesn't
2078 connect that signal properly, then OpenOCD can't use it.
2079 Possible values are @option{none} (the default), @option{trst_only},
2080 @option{srst_only} and @option{trst_and_srst}.
2081
2082 @quotation Tip
2083 If your board provides SRST or TRST through the JTAG connector,
2084 you must declare that or else those signals will not be used.
2085 @end quotation
2086
2087 The @var{combination} is an optional value specifying broken reset
2088 signal implementations.
2089 The default behaviour if no option given is @option{separate},
2090 indicating everything behaves normally.
2091 @option{srst_pulls_trst} states that the
2092 test logic is reset together with the reset of the system (e.g. Philips
2093 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
2094 the system is reset together with the test logic (only hypothetical, I
2095 haven't seen hardware with such a bug, and can be worked around).
2096 @option{combined} implies both @option{srst_pulls_trst} and
2097 @option{trst_pulls_srst}.
2098
2099 @option{srst_gates_jtag} indicates that asserting SRST gates the
2100 JTAG clock. This means that no communication can happen on JTAG
2101 while SRST is asserted.
2102
2103 The optional @var{trst_type} and @var{srst_type} parameters allow the
2104 driver mode of each reset line to be specified. These values only affect
2105 JTAG interfaces with support for different driver modes, like the Amontec
2106 JTAGkey and JTAGAccelerator. Also, they are necessarily ignored if the
2107 relevant signal (TRST or SRST) is not connected.
2108
2109 Possible @var{trst_type} driver modes for the test reset signal (TRST)
2110 are @option{trst_push_pull} (default) and @option{trst_open_drain}.
2111 Most boards connect this signal to a pulldown, so the JTAG TAPs
2112 never leave reset unless they are hooked up to a JTAG adapter.
2113
2114 Possible @var{srst_type} driver modes for the system reset signal (SRST)
2115 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
2116 Most boards connect this signal to a pullup, and allow the
2117 signal to be pulled low by various events including system
2118 powerup and pressing a reset button.
2119 @end deffn
2120
2121
2122 @node TAP Declaration
2123 @chapter TAP Declaration
2124 @cindex TAP declaration
2125 @cindex TAP configuration
2126
2127 @emph{Test Access Ports} (TAPs) are the core of JTAG.
2128 TAPs serve many roles, including:
2129
2130 @itemize @bullet
2131 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
2132 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
2133 Others do it indirectly, making a CPU do it.
2134 @item @b{Program Download} Using the same CPU support GDB uses,
2135 you can initialize a DRAM controller, download code to DRAM, and then
2136 start running that code.
2137 @item @b{Boundary Scan} Most chips support boundary scan, which
2138 helps test for board assembly problems like solder bridges
2139 and missing connections
2140 @end itemize
2141
2142 OpenOCD must know about the active TAPs on your board(s).
2143 Setting up the TAPs is the core task of your configuration files.
2144 Once those TAPs are set up, you can pass their names to code
2145 which sets up CPUs and exports them as GDB targets,
2146 probes flash memory, performs low-level JTAG operations, and more.
2147
2148 @section Scan Chains
2149 @cindex scan chain
2150
2151 TAPs are part of a hardware @dfn{scan chain},
2152 which is daisy chain of TAPs.
2153 They also need to be added to
2154 OpenOCD's software mirror of that hardware list,
2155 giving each member a name and associating other data with it.
2156 Simple scan chains, with a single TAP, are common in
2157 systems with a single microcontroller or microprocessor.
2158 More complex chips may have several TAPs internally.
2159 Very complex scan chains might have a dozen or more TAPs:
2160 several in one chip, more in the next, and connecting
2161 to other boards with their own chips and TAPs.
2162
2163 You can display the list with the @command{scan_chain} command.
2164 (Don't confuse this with the list displayed by the @command{targets}
2165 command, presented in the next chapter.
2166 That only displays TAPs for CPUs which are configured as
2167 debugging targets.)
2168 Here's what the scan chain might look like for a chip more than one TAP:
2169
2170 @verbatim
2171 TapName Enabled IdCode Expected IrLen IrCap IrMask Instr
2172 -- ------------------ ------- ---------- ---------- ----- ----- ------ -----
2173 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0 0 0x...
2174 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x1 0 0xc
2175 2 omap5912.unknown Y 0x00000000 0x00000000 8 0 0 0xff
2176 @end verbatim
2177
2178 Unfortunately those TAPs can't always be autoconfigured,
2179 because not all devices provide good support for that.
2180 JTAG doesn't require supporting IDCODE instructions, and
2181 chips with JTAG routers may not link TAPs into the chain
2182 until they are told to do so.
2183
2184 The configuration mechanism currently supported by OpenOCD
2185 requires explicit configuration of all TAP devices using
2186 @command{jtag newtap} commands, as detailed later in this chapter.
2187 A command like this would declare one tap and name it @code{chip1.cpu}:
2188
2189 @example
2190 jtag newtap chip1 cpu -irlen 7 -ircapture 0x01 -irmask 0x55
2191 @end example
2192
2193 Each target configuration file lists the TAPs provided
2194 by a given chip.
2195 Board configuration files combine all the targets on a board,
2196 and so forth.
2197 Note that @emph{the order in which TAPs are declared is very important.}
2198 It must match the order in the JTAG scan chain, both inside
2199 a single chip and between them.
2200 @xref{FAQ TAP Order}.
2201
2202 For example, the ST Microsystems STR912 chip has
2203 three separate TAPs@footnote{See the ST
2204 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
2205 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
2206 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
2207 To configure those taps, @file{target/str912.cfg}
2208 includes commands something like this:
2209
2210 @example
2211 jtag newtap str912 flash ... params ...
2212 jtag newtap str912 cpu ... params ...
2213 jtag newtap str912 bs ... params ...
2214 @end example
2215
2216 Actual config files use a variable instead of literals like
2217 @option{str912}, to support more than one chip of each type.
2218 @xref{Config File Guidelines}.
2219
2220 @deffn Command {jtag names}
2221 Returns the names of all current TAPs in the scan chain.
2222 Use @command{jtag cget} or @command{jtag tapisenabled}
2223 to examine attributes and state of each TAP.
2224 @example
2225 foreach t [jtag names] @{
2226 puts [format "TAP: %s\n" $t]
2227 @}
2228 @end example
2229 @end deffn
2230
2231 @deffn Command {scan_chain}
2232 Displays the TAPs in the scan chain configuration,
2233 and their status.
2234 The set of TAPs listed by this command is fixed by
2235 exiting the OpenOCD configuration stage,
2236 but systems with a JTAG router can
2237 enable or disable TAPs dynamically.
2238 In addition to the enable/disable status, the contents of
2239 each TAP's instruction register can also change.
2240 @end deffn
2241
2242 @c FIXME! "jtag cget" should be able to return all TAP
2243 @c attributes, like "$target_name cget" does for targets.
2244
2245 @c Probably want "jtag eventlist", and a "tap-reset" event
2246 @c (on entry to RESET state).
2247
2248 @section TAP Names
2249 @cindex dotted name
2250
2251 When TAP objects are declared with @command{jtag newtap},
2252 a @dfn{dotted.name} is created for the TAP, combining the
2253 name of a module (usually a chip) and a label for the TAP.
2254 For example: @code{xilinx.tap}, @code{str912.flash},
2255 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
2256 Many other commands use that dotted.name to manipulate or
2257 refer to the TAP. For example, CPU configuration uses the
2258 name, as does declaration of NAND or NOR flash banks.
2259
2260 The components of a dotted name should follow ``C'' symbol
2261 name rules: start with an alphabetic character, then numbers
2262 and underscores are OK; while others (including dots!) are not.
2263
2264 @quotation Tip
2265 In older code, JTAG TAPs were numbered from 0..N.
2266 This feature is still present.
2267 However its use is highly discouraged, and
2268 should not be relied on; it will be removed by mid-2010.
2269 Update all of your scripts to use TAP names rather than numbers,
2270 by paying attention to the runtime warnings they trigger.
2271 Using TAP numbers in target configuration scripts prevents
2272 reusing those scripts on boards with multiple targets.
2273 @end quotation
2274
2275 @section TAP Declaration Commands
2276
2277 @c shouldn't this be(come) a {Config Command}?
2278 @anchor{jtag newtap}
2279 @deffn Command {jtag newtap} chipname tapname configparams...
2280 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
2281 and configured according to the various @var{configparams}.
2282
2283 The @var{chipname} is a symbolic name for the chip.
2284 Conventionally target config files use @code{$_CHIPNAME},
2285 defaulting to the model name given by the chip vendor but
2286 overridable.
2287
2288 @cindex TAP naming convention
2289 The @var{tapname} reflects the role of that TAP,
2290 and should follow this convention:
2291
2292 @itemize @bullet
2293 @item @code{bs} -- For boundary scan if this is a seperate TAP;
2294 @item @code{cpu} -- The main CPU of the chip, alternatively
2295 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
2296 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
2297 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
2298 @item @code{flash} -- If the chip has a flash TAP, like the str912;
2299 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
2300 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
2301 @item @code{tap} -- Should be used only FPGA or CPLD like devices
2302 with a single TAP;
2303 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
2304 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
2305 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
2306 a JTAG TAP; that TAP should be named @code{sdma}.
2307 @end itemize
2308
2309 Every TAP requires at least the following @var{configparams}:
2310
2311 @itemize @bullet
2312 @item @code{-ircapture} @var{NUMBER}
2313 @*The bit pattern loaded by the TAP into the JTAG shift register
2314 on entry to the @sc{ircapture} state, such as 0x01.
2315 JTAG requires the two LSBs of this value to be 01.
2316 The value is used to verify that instruction scans work correctly.
2317 @item @code{-irlen} @var{NUMBER}
2318 @*The length in bits of the
2319 instruction register, such as 4 or 5 bits.
2320 @item @code{-irmask} @var{NUMBER}
2321 @*A mask for the IR register.
2322 For some devices, there are bits in the IR that aren't used.
2323 This lets OpenOCD mask them off when doing IDCODE comparisons.
2324 In general, this should just be all ones for the size of the IR.
2325 @end itemize
2326
2327 A TAP may also provide optional @var{configparams}:
2328
2329 @itemize @bullet
2330 @item @code{-disable} (or @code{-enable})
2331 @*Use the @code{-disable} parameter to flag a TAP which is not
2332 linked in to the scan chain after a reset using either TRST
2333 or the JTAG state machine's @sc{reset} state.
2334 You may use @code{-enable} to highlight the default state
2335 (the TAP is linked in).
2336 @xref{Enabling and Disabling TAPs}.
2337 @item @code{-expected-id} @var{number}
2338 @*A non-zero value represents the expected 32-bit IDCODE
2339 found when the JTAG chain is examined.
2340 These codes are not required by all JTAG devices.
2341 @emph{Repeat the option} as many times as required if more than one
2342 ID code could appear (for example, multiple versions).
2343 @end itemize
2344 @end deffn
2345
2346 @c @deffn Command {jtag arp_init-reset}
2347 @c ... more or less "init" ?
2348
2349 @anchor{Enabling and Disabling TAPs}
2350 @section Enabling and Disabling TAPs
2351 @cindex TAP events
2352 @cindex JTAG Route Controller
2353 @cindex jrc
2354
2355 In some systems, a @dfn{JTAG Route Controller} (JRC)
2356 is used to enable and/or disable specific JTAG TAPs.
2357 Many ARM based chips from Texas Instruments include
2358 an ``ICEpick'' module, which is a JRC.
2359 Such chips include DaVinci and OMAP3 processors.
2360
2361 A given TAP may not be visible until the JRC has been
2362 told to link it into the scan chain; and if the JRC
2363 has been told to unlink that TAP, it will no longer
2364 be visible.
2365 Such routers address problems that JTAG ``bypass mode''
2366 ignores, such as:
2367
2368 @itemize
2369 @item The scan chain can only go as fast as its slowest TAP.
2370 @item Having many TAPs slows instruction scans, since all
2371 TAPs receive new instructions.
2372 @item TAPs in the scan chain must be powered up, which wastes
2373 power and prevents debugging some power management mechanisms.
2374 @end itemize
2375
2376 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
2377 as implied by the existence of JTAG routers.
2378 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
2379 does include a kind of JTAG router functionality.
2380
2381 @c (a) currently the event handlers don't seem to be able to
2382 @c fail in a way that could lead to no-change-of-state.
2383 @c (b) eventually non-event configuration should be possible,
2384 @c in which case some this documentation must move.
2385
2386 @deffn Command {jtag cget} dotted.name @option{-event} name
2387 @deffnx Command {jtag configure} dotted.name @option{-event} name string
2388 At this writing this mechanism is used only for event handling.
2389 Three events are available. Two events relate to TAP enabling
2390 and disabling, one to post reset handling.
2391
2392 The @code{configure} subcommand assigns an event handler,
2393 a TCL string which is evaluated when the event is triggered.
2394 The @code{cget} subcommand returns that handler.
2395 The three possible values for an event @var{name} are @option{tap-disable}, @option{tap-enable} and @option{post-reset}.
2396
2397 So for example, when defining a TAP for a CPU connected to
2398 a JTAG router, you should define TAP event handlers using
2399 code that looks something like this:
2400
2401 @example
2402 jtag configure CHIP.cpu -event tap-enable @{
2403 echo "Enabling CPU TAP"
2404 ... jtag operations using CHIP.jrc
2405 @}
2406 jtag configure CHIP.cpu -event tap-disable @{
2407 echo "Disabling CPU TAP"
2408 ... jtag operations using CHIP.jrc
2409 @}
2410 @end example
2411
2412 If you need some post reset action, you can do:
2413
2414 @example
2415 jtag configure CHIP.cpu -event post-reset @{
2416 echo "Reset done"
2417 ... jtag operations to be done after reset
2418 @}
2419 @end example
2420 @end deffn
2421
2422 @deffn Command {jtag tapdisable} dotted.name
2423 @deffnx Command {jtag tapenable} dotted.name
2424 @deffnx Command {jtag tapisenabled} dotted.name
2425 These three commands all return the string "1" if the tap
2426 specified by @var{dotted.name} is enabled,
2427 and "0" if it is disbabled.
2428 The @command{tapenable} variant first enables the tap
2429 by sending it a @option{tap-enable} event.
2430 The @command{tapdisable} variant first disables the tap
2431 by sending it a @option{tap-disable} event.
2432
2433 @quotation Note
2434 Humans will find the @command{scan_chain} command more helpful
2435 than the script-oriented @command{tapisenabled}
2436 for querying the state of the JTAG taps.
2437 @end quotation
2438 @end deffn
2439
2440 @node CPU Configuration
2441 @chapter CPU Configuration
2442 @cindex GDB target
2443
2444 This chapter discusses how to set up GDB debug targets for CPUs.
2445 You can also access these targets without GDB
2446 (@pxref{Architecture and Core Commands},
2447 and @ref{Target State handling}) and
2448 through various kinds of NAND and NOR flash commands.
2449 If you have multiple CPUs you can have multiple such targets.
2450
2451 We'll start by looking at how to examine the targets you have,
2452 then look at how to add one more target and how to configure it.
2453
2454 @section Target List
2455 @cindex target, current
2456 @cindex target, list
2457
2458 All targets that have been set up are part of a list,
2459 where each member has a name.
2460 That name should normally be the same as the TAP name.
2461 You can display the list with the @command{targets}
2462 (plural!) command.
2463 This display often has only one CPU; here's what it might
2464 look like with more than one:
2465 @verbatim
2466 TargetName Type Endian TapName State
2467 -- ------------------ ---------- ------ ------------------ ------------
2468 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
2469 1 MyTarget cortex_m3 little mychip.foo tap-disabled
2470 @end verbatim
2471
2472 One member of that list is the @dfn{current target}, which
2473 is implicitly referenced by many commands.
2474 It's the one marked with a @code{*} near the target name.
2475 In particular, memory addresses often refer to the address
2476 space seen by that current target.
2477 Commands like @command{mdw} (memory display words)
2478 and @command{flash erase_address} (erase NOR flash blocks)
2479 are examples; and there are many more.
2480
2481 Several commands let you examine the list of targets:
2482
2483 @deffn Command {target count}
2484 @emph{Note: target numbers are deprecated; don't use them.
2485 They will be removed shortly after August 2010, including this command.
2486 Iterate target using @command{target names}, not by counting.}
2487
2488 Returns the number of targets, @math{N}.
2489 The highest numbered target is @math{N - 1}.
2490 @example
2491 set c [target count]
2492 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
2493 # Assuming you have created this function
2494 print_target_details $x
2495 @}
2496 @end example
2497 @end deffn
2498
2499 @deffn Command {target current}
2500 Returns the name of the current target.
2501 @end deffn
2502
2503 @deffn Command {target names}
2504 Lists the names of all current targets in the list.
2505 @example
2506 foreach t [target names] @{
2507 puts [format "Target: %s\n" $t]
2508 @}
2509 @end example
2510 @end deffn
2511
2512 @deffn Command {target number} number
2513 @emph{Note: target numbers are deprecated; don't use them.
2514 They will be removed shortly after August 2010, including this command.}
2515
2516 The list of targets is numbered starting at zero.
2517 This command returns the name of the target at index @var{number}.
2518 @example
2519 set thename [target number $x]
2520 puts [format "Target %d is: %s\n" $x $thename]
2521 @end example
2522 @end deffn
2523
2524 @c yep, "target list" would have been better.
2525 @c plus maybe "target setdefault".
2526
2527 @deffn Command targets [name]
2528 @emph{Note: the name of this command is plural. Other target
2529 command names are singular.}
2530
2531 With no parameter, this command displays a table of all known
2532 targets in a user friendly form.
2533
2534 With a parameter, this command sets the current target to
2535 the given target with the given @var{name}; this is
2536 only relevant on boards which have more than one target.
2537 @end deffn
2538
2539 @section Target CPU Types and Variants
2540 @cindex target type
2541 @cindex CPU type
2542 @cindex CPU variant
2543
2544 Each target has a @dfn{CPU type}, as shown in the output of
2545 the @command{targets} command. You need to specify that type
2546 when calling @command{target create}.
2547 The CPU type indicates more than just the instruction set.
2548 It also indicates how that instruction set is implemented,
2549 what kind of debug support it integrates,
2550 whether it has an MMU (and if so, what kind),
2551 what core-specific commands may be available
2552 (@pxref{Architecture and Core Commands}),
2553 and more.
2554
2555 For some CPU types, OpenOCD also defines @dfn{variants} which
2556 indicate differences that affect their handling.
2557 For example, a particular implementation bug might need to be
2558 worked around in some chip versions.
2559
2560 It's easy to see what target types are supported,
2561 since there's a command to list them.
2562 However, there is currently no way to list what target variants
2563 are supported (other than by reading the OpenOCD source code).
2564
2565 @anchor{target types}
2566 @deffn Command {target types}
2567 Lists all supported target types.
2568 At this writing, the supported CPU types and variants are:
2569
2570 @itemize @bullet
2571 @item @code{arm11} -- this is a generation of ARMv6 cores
2572 @item @code{arm720t} -- this is an ARMv4 core
2573 @item @code{arm7tdmi} -- this is an ARMv4 core
2574 @item @code{arm920t} -- this is an ARMv5 core
2575 @item @code{arm926ejs} -- this is an ARMv5 core
2576 @item @code{arm966e} -- this is an ARMv5 core
2577 @item @code{arm9tdmi} -- this is an ARMv4 core
2578 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
2579 (Support for this is preliminary and incomplete.)
2580 @item @code{cortex_a8} -- this is an ARMv7 core
2581 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
2582 compact Thumb2 instruction set. It supports one variant:
2583 @itemize @minus
2584 @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
2585 This will cause OpenOCD to use a software reset rather than asserting
2586 SRST, to avoid a issue with clearing the debug registers.
2587 This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
2588 be detected and the normal reset behaviour used.
2589 @end itemize
2590 @item @code{fa526} -- resembles arm920 (w/o Thumb)
2591 @item @code{feroceon} -- resembles arm926
2592 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
2593 @itemize @minus
2594 @item @code{ejtag_srst} ... Use this when debugging targets that do not
2595 provide a functional SRST line on the EJTAG connector. This causes
2596 OpenOCD to instead use an EJTAG software reset command to reset the
2597 processor.
2598 You still need to enable @option{srst} on the @command{reset_config}
2599 command to enable OpenOCD hardware reset functionality.
2600 @end itemize
2601 @item @code{xscale} -- this is actually an architecture,
2602 not a CPU type. It is based on the ARMv5 architecture.
2603 There are several variants defined:
2604 @itemize @minus
2605 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
2606 @code{pxa27x} ... instruction register length is 7 bits
2607 @item @code{pxa250}, @code{pxa255},
2608 @code{pxa26x} ... instruction register length is 5 bits
2609 @end itemize
2610 @end itemize
2611 @end deffn
2612
2613 To avoid being confused by the variety of ARM based cores, remember
2614 this key point: @emph{ARM is a technology licencing company}.
2615 (See: @url{http://www.arm.com}.)
2616 The CPU name used by OpenOCD will reflect the CPU design that was
2617 licenced, not a vendor brand which incorporates that design.
2618 Name prefixes like arm7, arm9, arm11, and cortex
2619 reflect design generations;
2620 while names like ARMv4, ARMv5, ARMv6, and ARMv7
2621 reflect an architecture version implemented by a CPU design.
2622
2623 @anchor{Target Configuration}
2624 @section Target Configuration
2625
2626 Before creating a ``target'', you must have added its TAP to the scan chain.
2627 When you've added that TAP, you will have a @code{dotted.name}
2628 which is used to set up the CPU support.
2629 The chip-specific configuration file will normally configure its CPU(s)
2630 right after it adds all of the chip's TAPs to the scan chain.
2631
2632 Although you can set up a target in one step, it's often clearer if you
2633 use shorter commands and do it in two steps: create it, then configure
2634 optional parts.
2635 All operations on the target after it's created will use a new
2636 command, created as part of target creation.
2637
2638 The two main things to configure after target creation are
2639 a work area, which usually has target-specific defaults even
2640 if the board setup code overrides them later;
2641 and event handlers (@pxref{Target Events}), which tend
2642 to be much more board-specific.
2643 The key steps you use might look something like this
2644
2645 @example
2646 target create MyTarget cortex_m3 -chain-position mychip.cpu
2647 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
2648 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
2649 $MyTarget configure -event reset-init @{ myboard_reinit @}
2650 @end example
2651
2652 You should specify a working area if you can; typically it uses some
2653 on-chip SRAM.
2654 Such a working area can speed up many things, including bulk
2655 writes to target memory;
2656 flash operations like checking to see if memory needs to be erased;
2657 GDB memory checksumming;
2658 and more.
2659
2660 @quotation Warning
2661 On more complex chips, the work area can become
2662 inaccessible when application code
2663 (such as an operating system)
2664 enables or disables the MMU.
2665 For example, the particular MMU context used to acess the virtual
2666 address will probably matter ... and that context might not have
2667 easy access to other addresses needed.
2668 At this writing, OpenOCD doesn't have much MMU intelligence.
2669 @end quotation
2670
2671 It's often very useful to define a @code{reset-init} event handler.
2672 For systems that are normally used with a boot loader,
2673 common tasks include updating clocks and initializing memory
2674 controllers.
2675 That may be needed to let you write the boot loader into flash,
2676 in order to ``de-brick'' your board; or to load programs into
2677 external DDR memory without having run the boot loader.
2678
2679 @deffn Command {target create} target_name type configparams...
2680 This command creates a GDB debug target that refers to a specific JTAG tap.
2681 It enters that target into a list, and creates a new
2682 command (@command{@var{target_name}}) which is used for various
2683 purposes including additional configuration.
2684
2685 @itemize @bullet
2686 @item @var{target_name} ... is the name of the debug target.
2687 By convention this should be the same as the @emph{dotted.name}
2688 of the TAP associated with this target, which must be specified here
2689 using the @code{-chain-position @var{dotted.name}} configparam.
2690
2691 This name is also used to create the target object command,
2692 referred to here as @command{$target_name},
2693 and in other places the target needs to be identified.
2694 @item @var{type} ... specifies the target type. @xref{target types}.
2695 @item @var{configparams} ... all parameters accepted by
2696 @command{$target_name configure} are permitted.
2697 If the target is big-endian, set it here with @code{-endian big}.
2698 If the variant matters, set it here with @code{-variant}.
2699
2700 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
2701 @end itemize
2702 @end deffn
2703
2704 @deffn Command {$target_name configure} configparams...
2705 The options accepted by this command may also be
2706 specified as parameters to @command{target create}.
2707 Their values can later be queried one at a time by
2708 using the @command{$target_name cget} command.
2709
2710 @emph{Warning:} changing some of these after setup is dangerous.
2711 For example, moving a target from one TAP to another;
2712 and changing its endianness or variant.
2713
2714 @itemize @bullet
2715
2716 @item @code{-chain-position} @var{dotted.name} -- names the TAP
2717 used to access this target.
2718
2719 @item @code{-endian} (@option{big}|@option{little}) -- specifies
2720 whether the CPU uses big or little endian conventions
2721
2722 @item @code{-event} @var{event_name} @var{event_body} --
2723 @xref{Target Events}.
2724 Note that this updates a list of named event handlers.
2725 Calling this twice with two different event names assigns
2726 two different handlers, but calling it twice with the
2727 same event name assigns only one handler.
2728
2729 @item @code{-variant} @var{name} -- specifies a variant of the target,
2730 which OpenOCD needs to know about.
2731
2732 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
2733 whether the work area gets backed up; by default,
2734 @emph{it is not backed up.}
2735 When possible, use a working_area that doesn't need to be backed up,
2736 since performing a backup slows down operations.
2737 For example, the beginning of an SRAM block is likely to
2738 be used by most build systems, but the end is often unused.
2739
2740 @item @code{-work-area-size} @var{size} -- specify/set the work area
2741
2742 @item @code{-work-area-phys} @var{address} -- set the work area
2743 base @var{address} to be used when no MMU is active.
2744
2745 @item @code{-work-area-virt} @var{address} -- set the work area
2746 base @var{address} to be used when an MMU is active.
2747
2748 @end itemize
2749 @end deffn
2750
2751 @section Other $target_name Commands
2752 @cindex object command
2753
2754 The Tcl/Tk language has the concept of object commands,
2755 and OpenOCD adopts that same model for targets.
2756
2757 A good Tk example is a on screen button.
2758 Once a button is created a button
2759 has a name (a path in Tk terms) and that name is useable as a first
2760 class command. For example in Tk, one can create a button and later
2761 configure it like this:
2762
2763 @example
2764 # Create
2765 button .foobar -background red -command @{ foo @}
2766 # Modify
2767 .foobar configure -foreground blue
2768 # Query
2769 set x [.foobar cget -background]
2770 # Report
2771 puts [format "The button is %s" $x]
2772 @end example
2773
2774 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
2775 button, and its object commands are invoked the same way.
2776
2777 @example
2778 str912.cpu mww 0x1234 0x42
2779 omap3530.cpu mww 0x5555 123
2780 @end example
2781
2782 The commands supported by OpenOCD target objects are:
2783
2784 @deffn Command {$target_name arp_examine}
2785 @deffnx Command {$target_name arp_halt}
2786 @deffnx Command {$target_name arp_poll}
2787 @deffnx Command {$target_name arp_reset}
2788 @deffnx Command {$target_name arp_waitstate}
2789 Internal OpenOCD scripts (most notably @file{startup.tcl})
2790 use these to deal with specific reset cases.
2791 They are not otherwise documented here.
2792 @end deffn
2793
2794 @deffn Command {$target_name array2mem} arrayname width address count
2795 @deffnx Command {$target_name mem2array} arrayname width address count
2796 These provide an efficient script-oriented interface to memory.
2797 The @code{array2mem} primitive writes bytes, halfwords, or words;
2798 while @code{mem2array} reads them.
2799 In both cases, the TCL side uses an array, and
2800 the target side uses raw memory.
2801
2802 The efficiency comes from enabling the use of
2803 bulk JTAG data transfer operations.
2804 The script orientation comes from working with data
2805 values that are packaged for use by TCL scripts;
2806 @command{mdw} type primitives only print data they retrieve,
2807 and neither store nor return those values.
2808
2809 @itemize
2810 @item @var{arrayname} ... is the name of an array variable
2811 @item @var{width} ... is 8/16/32 - indicating the memory access size
2812 @item @var{address} ... is the target memory address
2813 @item @var{count} ... is the number of elements to process
2814 @end itemize
2815 @end deffn
2816
2817 @deffn Command {$target_name cget} queryparm
2818 Each configuration parameter accepted by
2819 @command{$target_name configure}
2820 can be individually queried, to return its current value.
2821 The @var{queryparm} is a parameter name
2822 accepted by that command, such as @code{-work-area-phys}.
2823 There are a few special cases:
2824
2825 @itemize @bullet
2826 @item @code{-event} @var{event_name} -- returns the handler for the
2827 event named @var{event_name}.
2828 This is a special case because setting a handler requires
2829 two parameters.
2830 @item @code{-type} -- returns the target type.
2831 This is a special case because this is set using
2832 @command{target create} and can't be changed
2833 using @command{$target_name configure}.
2834 @end itemize
2835
2836 For example, if you wanted to summarize information about
2837 all the targets you might use something like this:
2838
2839 @example
2840 foreach name [target names] @{
2841 set y [$name cget -endian]
2842 set z [$name cget -type]
2843 puts [format "Chip %d is %s, Endian: %s, type: %s" \
2844 $x $name $y $z]
2845 @}
2846 @end example
2847 @end deffn
2848
2849 @anchor{target curstate}
2850 @deffn Command {$target_name curstate}
2851 Displays the current target state:
2852 @code{debug-running},
2853 @code{halted},
2854 @code{reset},
2855 @code{running}, or @code{unknown}.
2856 (Also, @pxref{Event Polling}.)
2857 @end deffn
2858
2859 @deffn Command {$target_name eventlist}
2860 Displays a table listing all event handlers
2861 currently associated with this target.
2862 @xref{Target Events}.
2863 @end deffn
2864
2865 @deffn Command {$target_name invoke-event} event_name
2866 Invokes the handler for the event named @var{event_name}.
2867 (This is primarily intended for use by OpenOCD framework
2868 code, for example by the reset code in @file{startup.tcl}.)
2869 @end deffn
2870
2871 @deffn Command {$target_name mdw} addr [count]
2872 @deffnx Command {$target_name mdh} addr [count]
2873 @deffnx Command {$target_name mdb} addr [count]
2874 Display contents of address @var{addr}, as
2875 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
2876 or 8-bit bytes (@command{mdb}).
2877 If @var{count} is specified, displays that many units.
2878 (If you want to manipulate the data instead of displaying it,
2879 see the @code{mem2array} primitives.)
2880 @end deffn
2881
2882 @deffn Command {$target_name mww} addr word
2883 @deffnx Command {$target_name mwh} addr halfword
2884 @deffnx Command {$target_name mwb} addr byte
2885 Writes the specified @var{word} (32 bits),
2886 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
2887 at the specified address @var{addr}.
2888 @end deffn
2889
2890 @anchor{Target Events}
2891 @section Target Events
2892 @cindex events
2893 At various times, certain things can happen, or you want them to happen.
2894 For example:
2895 @itemize @bullet
2896 @item What should happen when GDB connects? Should your target reset?
2897 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
2898 @item During reset, do you need to write to certain memory locations
2899 to set up system clocks or
2900 to reconfigure the SDRAM?
2901 @end itemize
2902
2903 All of the above items can be addressed by target event handlers.
2904 These are set up by @command{$target_name configure -event} or
2905 @command{target create ... -event}.
2906
2907 The programmer's model matches the @code{-command} option used in Tcl/Tk
2908 buttons and events. The two examples below act the same, but one creates
2909 and invokes a small procedure while the other inlines it.
2910
2911 @example
2912 proc my_attach_proc @{ @} @{
2913 echo "Reset..."
2914 reset halt
2915 @}
2916 mychip.cpu configure -event gdb-attach my_attach_proc
2917 mychip.cpu configure -event gdb-attach @{
2918 echo "Reset..."
2919 reset halt
2920 @}
2921 @end example
2922
2923 The following target events are defined:
2924
2925 @itemize @bullet
2926 @item @b{debug-halted}
2927 @* The target has halted for debug reasons (i.e.: breakpoint)
2928 @item @b{debug-resumed}
2929 @* The target has resumed (i.e.: gdb said run)
2930 @item @b{early-halted}
2931 @* Occurs early in the halt process
2932 @ignore
2933 @item @b{examine-end}
2934 @* Currently not used (goal: when JTAG examine completes)
2935 @item @b{examine-start}
2936 @* Currently not used (goal: when JTAG examine starts)
2937 @end ignore
2938 @item @b{gdb-attach}
2939 @* When GDB connects
2940 @item @b{gdb-detach}
2941 @* When GDB disconnects
2942 @item @b{gdb-end}
2943 @* When the target has halted and GDB is not doing anything (see early halt)
2944 @item @b{gdb-flash-erase-start}
2945 @* Before the GDB flash process tries to erase the flash
2946 @item @b{gdb-flash-erase-end}
2947 @* After the GDB flash process has finished erasing the flash
2948 @item @b{gdb-flash-write-start}
2949 @* Before GDB writes to the flash
2950 @item @b{gdb-flash-write-end}
2951 @* After GDB writes to the flash
2952 @item @b{gdb-start}
2953 @* Before the target steps, gdb is trying to start/resume the target
2954 @item @b{halted}
2955 @* The target has halted
2956 @ignore
2957 @item @b{old-gdb_program_config}
2958 @* DO NOT USE THIS: Used internally
2959 @item @b{old-pre_resume}
2960 @* DO NOT USE THIS: Used internally
2961 @end ignore
2962 @item @b{reset-assert-pre}
2963 @* Issued as part of @command{reset} processing
2964 after SRST and/or TRST were activated and deactivated,
2965 but before SRST alone is re-asserted on the tap.
2966 @item @b{reset-assert-post}
2967 @* Issued as part of @command{reset} processing
2968 when SRST is asserted on the tap.
2969 @item @b{reset-deassert-pre}
2970 @* Issued as part of @command{reset} processing
2971 when SRST is about to be released on the tap.
2972 @item @b{reset-deassert-post}
2973 @* Issued as part of @command{reset} processing
2974 when SRST has been released on the tap.
2975 @item @b{reset-end}
2976 @* Issued as the final step in @command{reset} processing.
2977 @ignore
2978 @item @b{reset-halt-post}
2979 @* Currently not used
2980 @item @b{reset-halt-pre}
2981 @* Currently not used
2982 @end ignore
2983 @item @b{reset-init}
2984 @* Used by @b{reset init} command for board-specific initialization.
2985 This event fires after @emph{reset-deassert-post}.
2986
2987 This is where you would configure PLLs and clocking, set up DRAM so
2988 you can download programs that don't fit in on-chip SRAM, set up pin
2989 multiplexing, and so on.
2990 (You may be able to switch to a fast JTAG clock rate here, after
2991 the target clocks are fully set up.)
2992 @item @b{reset-start}
2993 @* Issued as part of @command{reset} processing
2994 before either SRST or TRST are activated.
2995
2996 This is the most robust place to switch to a low JTAG clock rate, if
2997 SRST disables PLLs needed to use a fast clock.
2998 @ignore
2999 @item @b{reset-wait-pos}
3000 @* Currently not used
3001 @item @b{reset-wait-pre}
3002 @* Currently not used
3003 @end ignore
3004 @item @b{resume-start}
3005 @* Before any target is resumed
3006 @item @b{resume-end}
3007 @* After all targets have resumed
3008 @item @b{resume-ok}
3009 @* Success
3010 @item @b{resumed}
3011 @* Target has resumed
3012 @end itemize
3013
3014
3015 @node Flash Commands
3016 @chapter Flash Commands
3017
3018 OpenOCD has different commands for NOR and NAND flash;
3019 the ``flash'' command works with NOR flash, while
3020 the ``nand'' command works with NAND flash.
3021 This partially reflects different hardware technologies:
3022 NOR flash usually supports direct CPU instruction and data bus access,
3023 while data from a NAND flash must be copied to memory before it can be
3024 used. (SPI flash must also be copied to memory before use.)
3025 However, the documentation also uses ``flash'' as a generic term;
3026 for example, ``Put flash configuration in board-specific files''.
3027
3028 Flash Steps:
3029 @enumerate
3030 @item Configure via the command @command{flash bank}
3031 @* Do this in a board-specific configuration file,
3032 passing parameters as needed by the driver.
3033 @item Operate on the flash via @command{flash subcommand}
3034 @* Often commands to manipulate the flash are typed by a human, or run
3035 via a script in some automated way. Common tasks include writing a
3036 boot loader, operating system, or other data.
3037 @item GDB Flashing
3038 @* Flashing via GDB requires the flash be configured via ``flash
3039 bank'', and the GDB flash features be enabled.
3040 @xref{GDB Configuration}.
3041 @end enumerate
3042
3043 Many CPUs have the ablity to ``boot'' from the first flash bank.
3044 This means that misprogramming that bank can ``brick'' a system,
3045 so that it can't boot.
3046 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
3047 board by (re)installing working boot firmware.
3048
3049 @anchor{NOR Configuration}
3050 @section Flash Configuration Commands
3051 @cindex flash configuration
3052
3053 @deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
3054 Configures a flash bank which provides persistent storage
3055 for addresses from @math{base} to @math{base + size - 1}.
3056 These banks will often be visible to GDB through the target's memory map.
3057 In some cases, configuring a flash bank will activate extra commands;
3058 see the driver-specific documentation.
3059
3060 @itemize @bullet
3061 @item @var{driver} ... identifies the controller driver
3062 associated with the flash bank being declared.
3063 This is usually @code{cfi} for external flash, or else
3064 the name of a microcontroller with embedded flash memory.
3065 @xref{Flash Driver List}.
3066 @item @var{base} ... Base address of the flash chip.
3067 @item @var{size} ... Size of the chip, in bytes.
3068 For some drivers, this value is detected from the hardware.
3069 @item @var{chip_width} ... Width of the flash chip, in bytes;
3070 ignored for most microcontroller drivers.
3071 @item @var{bus_width} ... Width of the data bus used to access the
3072 chip, in bytes; ignored for most microcontroller drivers.
3073 @item @var{target} ... Names the target used to issue
3074 commands to the flash controller.
3075 @comment Actually, it's currently a controller-specific parameter...
3076 @item @var{driver_options} ... drivers may support, or require,
3077 additional parameters. See the driver-specific documentation
3078 for more information.
3079 @end itemize
3080 @quotation Note
3081 This command is not available after OpenOCD initialization has completed.
3082 Use it in board specific configuration files, not interactively.
3083 @end quotation
3084 @end deffn
3085
3086 @comment the REAL name for this command is "ocd_flash_banks"
3087 @comment less confusing would be: "flash list" (like "nand list")
3088 @deffn Command {flash banks}
3089 Prints a one-line summary of each device declared
3090 using @command{flash bank}, numbered from zero.
3091 Note that this is the @emph{plural} form;
3092 the @emph{singular} form is a very different command.
3093 @end deffn
3094
3095 @deffn Command {flash probe} num
3096 Identify the flash, or validate the parameters of the configured flash. Operation
3097 depends on the flash type.
3098 The @var{num} parameter is a value shown by @command{flash banks}.
3099 Most flash commands will implicitly @emph{autoprobe} the bank;
3100 flash drivers can distinguish between probing and autoprobing,
3101 but most don't bother.
3102 @end deffn
3103
3104 @section Erasing, Reading, Writing to Flash
3105 @cindex flash erasing
3106 @cindex flash reading
3107 @cindex flash writing
3108 @cindex flash programming
3109
3110 One feature distinguishing NOR flash from NAND or serial flash technologies
3111 is that for read access, it acts exactly like any other addressible memory.
3112 This means you can use normal memory read commands like @command{mdw} or
3113 @command{dump_image} with it, with no special @command{flash} subcommands.
3114 @xref{Memory access}, and @ref{Image access}.
3115
3116 Write access works differently. Flash memory normally needs to be erased
3117 before it's written. Erasing a sector turns all of its bits to ones, and
3118 writing can turn ones into zeroes. This is why there are special commands
3119 for interactive erasing and writing, and why GDB needs to know which parts
3120 of the address space hold NOR flash memory.
3121
3122 @quotation Note
3123 Most of these erase and write commands leverage the fact that NOR flash
3124 chips consume target address space. They implicitly refer to the current
3125 JTAG target, and map from an address in that target's address space
3126 back to a flash bank.
3127 @comment In May 2009, those mappings may fail if any bank associated
3128 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
3129 A few commands use abstract addressing based on bank and sector numbers,
3130 and don't depend on searching the current target and its address space.
3131 Avoid confusing the two command models.
3132 @end quotation
3133
3134 Some flash chips implement software protection against accidental writes,
3135 since such buggy writes could in some cases ``brick'' a system.
3136 For such systems, erasing and writing may require sector protection to be
3137 disabled first.
3138 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
3139 and AT91SAM7 on-chip flash.
3140 @xref{flash protect}.
3141
3142 @anchor{flash erase_sector}
3143 @deffn Command {flash erase_sector} num first last
3144 Erase sectors in bank @var{num}, starting at sector @var{first} up to and including
3145 @var{last}. Sector numbering starts at 0.
3146 The @var{num} parameter is a value shown by @command{flash banks}.
3147 @end deffn
3148
3149 @deffn Command {flash erase_address} address length
3150 Erase sectors starting at @var{address} for @var{length} bytes.
3151 The flash bank to use is inferred from the @var{address}, and
3152 the specified length must stay within that bank.
3153 As a special case, when @var{length} is zero and @var{address} is
3154 the start of the bank, the whole flash is erased.
3155 @end deffn
3156
3157 @deffn Command {flash fillw} address word length
3158 @deffnx Command {flash fillh} address halfword length
3159 @deffnx Command {flash fillb} address byte length
3160 Fills flash memory with the specified @var{word} (32 bits),
3161 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3162 starting at @var{address} and continuing
3163 for @var{length} units (word/halfword/byte).
3164 No erasure is done before writing; when needed, that must be done
3165 before issuing this command.
3166 Writes are done in blocks of up to 1024 bytes, and each write is
3167 verified by reading back the data and comparing it to what was written.
3168 The flash bank to use is inferred from the @var{address} of
3169 each block, and the specified length must stay within that bank.
3170 @end deffn
3171 @comment no current checks for errors if fill blocks touch multiple banks!
3172
3173 @anchor{flash write_bank}
3174 @deffn Command {flash write_bank} num filename offset
3175 Write the binary @file{filename} to flash bank @var{num},
3176 starting at @var{offset} bytes from the beginning of the bank.
3177 The @var{num} parameter is a value shown by @command{flash banks}.
3178 @end deffn
3179
3180 @anchor{flash write_image}
3181 @deffn Command {flash write_image} [erase] filename [offset] [type]
3182 Write the image @file{filename} to the current target's flash bank(s).
3183 A relocation @var{offset} may be specified, in which case it is added
3184 to the base address for each section in the image.
3185 The file [@var{type}] can be specified
3186 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
3187 @option{elf} (ELF file), @option{s19} (Motorola s19).
3188 @option{mem}, or @option{builder}.
3189 The relevant flash sectors will be erased prior to programming
3190 if the @option{erase} parameter is given.
3191 The flash bank to use is inferred from the @var{address} of
3192 each image segment.
3193 @end deffn
3194
3195 @section Other Flash commands
3196 @cindex flash protection
3197
3198 @deffn Command {flash erase_check} num
3199 Check erase state of sectors in flash bank @var{num},
3200 and display that status.
3201 The @var{num} parameter is a value shown by @command{flash banks}.
3202 This is the only operation that
3203 updates the erase state information displayed by @option{flash info}. That means you have
3204 to issue an @command{flash erase_check} command after erasing or programming the device
3205 to get updated information.
3206 (Code execution may have invalidated any state records kept by OpenOCD.)
3207 @end deffn
3208
3209 @deffn Command {flash info} num
3210 Print info about flash bank @var{num}
3211 The @var{num} parameter is a value shown by @command{flash banks}.
3212 The information includes per-sector protect status.
3213 @end deffn
3214
3215 @anchor{flash protect}
3216 @deffn Command {flash protect} num first last (on|off)
3217 Enable (@var{on}) or disable (@var{off}) protection of flash sectors
3218 @var{first} to @var{last} of flash bank @var{num}.
3219 The @var{num} parameter is a value shown by @command{flash banks}.
3220 @end deffn
3221
3222 @deffn Command {flash protect_check} num
3223 Check protection state of sectors in flash bank @var{num}.
3224 The @var{num} parameter is a value shown by @command{flash banks}.
3225 @comment @option{flash erase_sector} using the same syntax.
3226 @end deffn
3227
3228 @anchor{Flash Driver List}
3229 @section Flash Drivers, Options, and Commands
3230 As noted above, the @command{flash bank} command requires a driver name,
3231 and allows driver-specific options and behaviors.
3232 Some drivers also activate driver-specific commands.
3233
3234 @subsection External Flash
3235
3236 @deffn {Flash Driver} cfi
3237 @cindex Common Flash Interface
3238 @cindex CFI
3239 The ``Common Flash Interface'' (CFI) is the main standard for
3240 external NOR flash chips, each of which connects to a
3241 specific external chip select on the CPU.
3242 Frequently the first such chip is used to boot the system.
3243 Your board's @code{reset-init} handler might need to
3244 configure additional chip selects using other commands (like: @command{mww} to
3245 configure a bus and its timings) , or
3246 perhaps configure a GPIO pin that controls the ``write protect'' pin
3247 on the flash chip.
3248 The CFI driver can use a target-specific working area to significantly
3249 speed up operation.
3250
3251 The CFI driver can accept the following optional parameters, in any order:
3252
3253 @itemize
3254 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
3255 like AM29LV010 and similar types.
3256 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
3257 @end itemize
3258
3259 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
3260 wide on a sixteen bit bus:
3261
3262 @example
3263 flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
3264 flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
3265 @end example
3266 @c "cfi part_id" disabled
3267 @end deffn
3268
3269 @subsection Internal Flash (Microcontrollers)
3270
3271 @deffn {Flash Driver} aduc702x
3272 The ADUC702x analog microcontrollers from Analog Devices
3273 include internal flash and use ARM7TDMI cores.
3274 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
3275 The setup command only requires the @var{target} argument
3276 since all devices in this family have the same memory layout.
3277
3278 @example
3279 flash bank aduc702x 0 0 0 0 $_TARGETNAME
3280 @end example
3281 @end deffn
3282
3283 @deffn {Flash Driver} at91sam3
3284 @cindex at91sam3
3285 All members of the AT91SAM3 microcontroller family from
3286 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
3287 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
3288 that the driver was orginaly developed and tested using the
3289 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
3290 the family was cribbed from the data sheet. @emph{Note to future
3291 readers/updaters: Please remove this worrysome comment after other
3292 chips are confirmed.}
3293
3294 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
3295 have one flash bank. In all cases the flash banks are at
3296 the following fixed locations:
3297
3298 @example
3299 # Flash bank 0 - all chips
3300 flash bank at91sam3 0x00080000 0 1 1 $_TARGETNAME
3301 # Flash bank 1 - only 256K chips
3302 flash bank at91sam3 0x00100000 0 1 1 $_TARGETNAME
3303 @end example
3304
3305 Internally, the AT91SAM3 flash memory is organized as follows.
3306 Unlike the AT91SAM7 chips, these are not used as parameters
3307 to the @command{flash bank} command:
3308
3309 @itemize
3310 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
3311 @item @emph{Bank Size:} 128K/64K Per flash bank
3312 @item @emph{Sectors:} 16 or 8 per bank
3313 @item @emph{SectorSize:} 8K Per Sector
3314 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
3315 @end itemize
3316
3317 The AT91SAM3 driver adds some additional commands:
3318
3319 @deffn Command {at91sam3 gpnvm}
3320 @deffnx Command {at91sam3 gpnvm clear} number
3321 @deffnx Command {at91sam3 gpnvm set} number
3322 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
3323 With no parameters, @command{show} or @command{show all},
3324 shows the status of all GPNVM bits.
3325 With @command{show} @var{number}, displays that bit.
3326
3327 With @command{set} @var{number} or @command{clear} @var{number},
3328 modifies that GPNVM bit.
3329 @end deffn
3330
3331 @deffn Command {at91sam3 info}
3332 This command attempts to display information about the AT91SAM3
3333 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
3334 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
3335 document id: doc6430A] and decodes the values. @emph{Second} it reads the
3336 various clock configuration registers and attempts to display how it
3337 believes the chip is configured. By default, the SLOWCLK is assumed to
3338 be 32768 Hz, see the command @command{at91sam3 slowclk}.
3339 @end deffn
3340
3341 @deffn Command {at91sam3 slowclk} [value]
3342 This command shows/sets the slow clock frequency used in the
3343 @command{at91sam3 info} command calculations above.
3344 @end deffn
3345 @end deffn
3346
3347 @deffn {Flash Driver} at91sam7
3348 All members of the AT91SAM7 microcontroller family from Atmel include
3349 internal flash and use ARM7TDMI cores. The driver automatically
3350 recognizes a number of these chips using the chip identification
3351 register, and autoconfigures itself.
3352
3353 @example
3354 flash bank at91sam7 0 0 0 0 $_TARGETNAME
3355 @end example
3356
3357 For chips which are not recognized by the controller driver, you must
3358 provide additional parameters in the following order:
3359
3360 @itemize
3361 @item @var{chip_model} ... label used with @command{flash info}
3362 @item @var{banks}
3363 @item @var{sectors_per_bank}
3364 @item @var{pages_per_sector}
3365 @item @var{pages_size}
3366 @item @var{num_nvm_bits}
3367 @item @var{freq_khz} ... required if an external clock is provided,
3368 optional (but recommended) when the oscillator frequency is known
3369 @end itemize
3370
3371 It is recommended that you provide zeroes for all of those values
3372 except the clock frequency, so that everything except that frequency
3373 will be autoconfigured.
3374 Knowing the frequency helps ensure correct timings for flash access.
3375
3376 The flash controller handles erases automatically on a page (128/256 byte)
3377 basis, so explicit erase commands are not necessary for flash programming.
3378 However, there is an ``EraseAll`` command that can erase an entire flash
3379 plane (of up to 256KB), and it will be used automatically when you issue
3380 @command{flash erase_sector} or @command{flash erase_address} commands.
3381
3382 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
3383 Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
3384 bit for the processor. Each processor has a number of such bits,
3385 used for controlling features such as brownout detection (so they
3386 are not truly general purpose).
3387 @quotation Note
3388 This assumes that the first flash bank (number 0) is associated with
3389 the appropriate at91sam7 target.
3390 @end quotation
3391 @end deffn
3392 @end deffn
3393
3394 @deffn {Flash Driver} avr
3395 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
3396 @emph{The current implementation is incomplete.}
3397 @comment - defines mass_erase ... pointless given flash_erase_address
3398 @end deffn
3399
3400 @deffn {Flash Driver} ecosflash
3401 @emph{No idea what this is...}
3402 The @var{ecosflash} driver defines one mandatory parameter,
3403 the name of a modules of target code which is downloaded
3404 and executed.
3405 @end deffn
3406
3407 @deffn {Flash Driver} lpc2000
3408 Most members of the LPC1700 and LPC2000 microcontroller families from NXP
3409 include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
3410
3411 @quotation Note
3412 There are LPC2000 devices which are not supported by the @var{lpc2000}
3413 driver:
3414 The LPC2888 is supported by the @var{lpc288x} driver.
3415 The LPC29xx family is supported by the @var{lpc2900} driver.
3416 @end quotation
3417
3418 The @var{lpc2000} driver defines two mandatory and one optional parameters,
3419 which must appear in the following order:
3420
3421 @itemize
3422 @item @var{variant} ... required, may be
3423 @var{lpc2000_v1} (older LPC21xx and LPC22xx)
3424 @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
3425 or @var{lpc1700} (LPC175x and LPC176x)
3426 @item @var{clock_kHz} ... the frequency, in kiloHertz,
3427 at which the core is running
3428 @item @var{calc_checksum} ... optional (but you probably want to provide this!),
3429 telling the driver to calculate a valid checksum for the exception vector table.
3430 @end itemize
3431
3432 LPC flashes don't require the chip and bus width to be specified.
3433
3434 @example
3435 flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
3436 lpc2000_v2 14765 calc_checksum
3437 @end example
3438
3439 @deffn {Command} {lpc2000 part_id} bank
3440 Displays the four byte part identifier associated with
3441 the specified flash @var{bank}.
3442 @end deffn
3443 @end deffn
3444
3445 @deffn {Flash Driver} lpc288x
3446 The LPC2888 microcontroller from NXP needs slightly different flash
3447 support from its lpc2000 siblings.
3448 The @var{lpc288x} driver defines one mandatory parameter,
3449 the programming clock rate in Hz.
3450 LPC flashes don't require the chip and bus width to be specified.
3451
3452 @example
3453 flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
3454 @end example
3455 @end deffn
3456
3457 @deffn {Flash Driver} lpc2900
3458 This driver supports the LPC29xx ARM968E based microcontroller family
3459 from NXP.
3460
3461 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
3462 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
3463 sector layout are auto-configured by the driver.
3464 The driver has one additional mandatory parameter: The CPU clock rate
3465 (in kHz) at the time the flash operations will take place. Most of the time this
3466 will not be the crystal frequency, but a higher PLL frequency. The
3467 @code{reset-init} event handler in the board script is usually the place where
3468 you start the PLL.
3469
3470 The driver rejects flashless devices (currently the LPC2930).
3471
3472 The EEPROM in LPC2900 devices is not mapped directly into the address space.
3473 It must be handled much more like NAND flash memory, and will therefore be
3474 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
3475
3476 Sector protection in terms of the LPC2900 is handled transparently. Every time a
3477 sector needs to be erased or programmed, it is automatically unprotected.
3478 What is shown as protection status in the @code{flash info} command, is
3479 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
3480 sector from ever being erased or programmed again. As this is an irreversible
3481 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
3482 and not by the standard @code{flash protect} command.
3483
3484 Example for a 125 MHz clock frequency:
3485 @example
3486 flash bank lpc2900 0 0 0 0 $_TARGETNAME 125000
3487 @end example
3488
3489 Some @code{lpc2900}-specific commands are defined. In the following command list,
3490 the @var{bank} parameter is the bank number as obtained by the
3491 @code{flash banks} command.
3492
3493 @deffn Command {lpc2900 signature} bank
3494 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
3495 content. This is a hardware feature of the flash block, hence the calculation is
3496 very fast. You may use this to verify the content of a programmed device against
3497 a known signature.
3498 Example:
3499 @example
3500 lpc2900 signature 0
3501 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
3502 @end example
3503 @end deffn
3504
3505 @deffn Command {lpc2900 read_custom} bank filename
3506 Reads the 912 bytes of customer information from the flash index sector, and
3507 saves it to a file in binary format.
3508 Example:
3509 @example
3510 lpc2900 read_custom 0 /path_to/customer_info.bin
3511 @end example
3512 @end deffn
3513
3514 The index sector of the flash is a @emph{write-only} sector. It cannot be
3515 erased! In order to guard against unintentional write access, all following
3516 commands need to be preceeded by a successful call to the @code{password}
3517 command:
3518
3519 @deffn Command {lpc2900 password} bank password
3520 You need to use this command right before each of the following commands:
3521 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
3522 @code{lpc2900 secure_jtag}.
3523
3524 The password string is fixed to "I_know_what_I_am_doing".
3525 Example:
3526 @example
3527 lpc2900 password 0 I_know_what_I_am_doing
3528 Potentially dangerous operation allowed in next command!
3529 @end example
3530 @end deffn
3531
3532 @deffn Command {lpc2900 write_custom} bank filename type
3533 Writes the content of the file into the customer info space of the flash index
3534 sector. The filetype can be specified with the @var{type} field. Possible values
3535 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
3536 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
3537 contain a single section, and the contained data length must be exactly
3538 912 bytes.
3539 @quotation Attention
3540 This cannot be reverted! Be careful!
3541 @end quotation
3542 Example:
3543 @example
3544 lpc2900 write_custom 0 /path_to/customer_info.bin bin
3545 @end example
3546 @end deffn
3547
3548 @deffn Command {lpc2900 secure_sector} bank first last
3549 Secures the sector range from @var{first} to @var{last} (including) against
3550 further program and erase operations. The sector security will be effective
3551 after the next power cycle.
3552 @quotation Attention
3553 This cannot be reverted! Be careful!
3554 @end quotation
3555 Secured sectors appear as @emph{protected} in the @code{flash info} command.
3556 Example:
3557 @example
3558 lpc2900 secure_sector 0 1 1
3559 flash info 0
3560 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
3561 # 0: 0x00000000 (0x2000 8kB) not protected
3562 # 1: 0x00002000 (0x2000 8kB) protected
3563 # 2: 0x00004000 (0x2000 8kB) not protected
3564 @end example
3565 @end deffn
3566
3567 @deffn Command {lpc2900 secure_jtag} bank
3568 Irreversibly disable the JTAG port. The new JTAG security setting will be
3569 effective after the next power cycle.
3570 @quotation Attention
3571 This cannot be reverted! Be careful!
3572 @end quotation
3573 Examples:
3574 @example
3575 lpc2900 secure_jtag 0
3576 @end example
3577 @end deffn
3578 @end deffn
3579
3580 @deffn {Flash Driver} ocl
3581 @emph{No idea what this is, other than using some arm7/arm9 core.}
3582
3583 @example
3584 flash bank ocl 0 0 0 0 $_TARGETNAME
3585 @end example
3586 @end deffn
3587
3588 @deffn {Flash Driver} pic32mx
3589 The PIC32MX microcontrollers are based on the MIPS 4K cores,
3590 and integrate flash memory.
3591 @emph{The current implementation is incomplete.}
3592
3593 @example
3594 flash bank pix32mx 0 0 0 0 $_TARGETNAME
3595 @end example
3596
3597 @comment numerous *disabled* commands are defined:
3598 @comment - chip_erase ... pointless given flash_erase_address
3599 @comment - lock, unlock ... pointless given protect on/off (yes?)
3600 @comment - pgm_word ... shouldn't bank be deduced from address??
3601 Some pic32mx-specific commands are defined:
3602 @deffn Command {pic32mx pgm_word} address value bank
3603 Programs the specified 32-bit @var{value} at the given @var{address}
3604 in the specified chip @var{bank}.
3605 @end deffn
3606 @end deffn
3607
3608 @deffn {Flash Driver} stellaris
3609 All members of the Stellaris LM3Sxxx microcontroller family from
3610 Texas Instruments
3611 include internal flash and use ARM Cortex M3 cores.
3612 The driver automatically recognizes a number of these chips using
3613 the chip identification register, and autoconfigures itself.
3614 @footnote{Currently there is a @command{stellaris mass_erase} command.
3615 That seems pointless since the same effect can be had using the
3616 standard @command{flash erase_address} command.}
3617
3618 @example
3619 flash bank stellaris 0 0 0 0 $_TARGETNAME
3620 @end example
3621 @end deffn
3622
3623 @deffn {Flash Driver} stm32x
3624 All members of the STM32 microcontroller family from ST Microelectronics
3625 include internal flash and use ARM Cortex M3 cores.
3626 The driver automatically recognizes a number of these chips using
3627 the chip identification register, and autoconfigures itself.
3628
3629 @example
3630 flash bank stm32x 0 0 0 0 $_TARGETNAME
3631 @end example
3632
3633 Some stm32x-specific commands
3634 @footnote{Currently there is a @command{stm32x mass_erase} command.
3635 That seems pointless since the same effect can be had using the
3636 standard @command{flash erase_address} command.}
3637 are defined:
3638
3639 @deffn Command {stm32x lock} num
3640 Locks the entire stm32 device.
3641 The @var{num} parameter is a value shown by @command{flash banks}.
3642 @end deffn
3643
3644 @deffn Command {stm32x unlock} num
3645 Unlocks the entire stm32 device.
3646 The @var{num} parameter is a value shown by @command{flash banks}.
3647 @end deffn
3648
3649 @deffn Command {stm32x options_read} num
3650 Read and display the stm32 option bytes written by
3651 the @command{stm32x options_write} command.
3652 The @var{num} parameter is a value shown by @command{flash banks}.
3653 @end deffn
3654
3655 @deffn Command {stm32x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
3656 Writes the stm32 option byte with the specified values.
3657 The @var{num} parameter is a value shown by @command{flash banks}.
3658 @end deffn
3659 @end deffn
3660
3661 @deffn {Flash Driver} str7x
3662 All members of the STR7 microcontroller family from ST Microelectronics
3663 include internal flash and use ARM7TDMI cores.
3664 The @var{str7x} driver defines one mandatory parameter, @var{variant},
3665 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
3666
3667 @example
3668 flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
3669 @end example
3670
3671 @deffn Command {str7x disable_jtag} bank
3672 Activate the Debug/Readout protection mechanism
3673 for the specified flash bank.
3674 @end deffn
3675 @end deffn
3676
3677 @deffn {Flash Driver} str9x
3678 Most members of the STR9 microcontroller family from ST Microelectronics
3679 include internal flash and use ARM966E cores.
3680 The str9 needs the flash controller to be configured using
3681 the @command{str9x flash_config} command prior to Flash programming.
3682
3683 @example
3684 flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
3685 str9x flash_config 0 4 2 0 0x80000
3686 @end example
3687
3688 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
3689 Configures the str9 flash controller.
3690 The @var{num} parameter is a value shown by @command{flash banks}.
3691
3692 @itemize @bullet
3693 @item @var{bbsr} - Boot Bank Size register
3694 @item @var{nbbsr} - Non Boot Bank Size register
3695 @item @var{bbadr} - Boot Bank Start Address register
3696 @item @var{nbbadr} - Boot Bank Start Address register
3697 @end itemize
3698 @end deffn
3699
3700 @end deffn
3701
3702 @deffn {Flash Driver} tms470
3703 Most members of the TMS470 microcontroller family from Texas Instruments
3704 include internal flash and use ARM7TDMI cores.
3705 This driver doesn't require the chip and bus width to be specified.
3706
3707 Some tms470-specific commands are defined:
3708
3709 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
3710 Saves programming keys in a register, to enable flash erase and write commands.
3711 @end deffn
3712
3713 @deffn Command {tms470 osc_mhz} clock_mhz
3714 Reports the clock speed, which is used to calculate timings.
3715 @end deffn
3716
3717 @deffn Command {tms470 plldis} (0|1)
3718 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
3719 the flash clock.
3720 @end deffn
3721 @end deffn
3722
3723 @subsection str9xpec driver
3724 @cindex str9xpec
3725
3726 Here is some background info to help
3727 you better understand how this driver works. OpenOCD has two flash drivers for
3728 the str9:
3729 @enumerate
3730 @item
3731 Standard driver @option{str9x} programmed via the str9 core. Normally used for
3732 flash programming as it is faster than the @option{str9xpec} driver.
3733 @item
3734 Direct programming @option{str9xpec} using the flash controller. This is an
3735 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
3736 core does not need to be running to program using this flash driver. Typical use
3737 for this driver is locking/unlocking the target and programming the option bytes.
3738 @end enumerate
3739
3740 Before we run any commands using the @option{str9xpec} driver we must first disable
3741 the str9 core. This example assumes the @option{str9xpec} driver has been
3742 configured for flash bank 0.
3743 @example
3744 # assert srst, we do not want core running
3745 # while accessing str9xpec flash driver
3746 jtag_reset 0 1
3747 # turn off target polling
3748 poll off
3749 # disable str9 core
3750 str9xpec enable_turbo 0
3751 # read option bytes
3752 str9xpec options_read 0
3753 # re-enable str9 core
3754 str9xpec disable_turbo 0
3755 poll on
3756 reset halt
3757 @end example
3758 The above example will read the str9 option bytes.
3759 When performing a unlock remember that you will not be able to halt the str9 - it
3760 has been locked. Halting the core is not required for the @option{str9xpec} driver
3761 as mentioned above, just issue the commands above manually or from a telnet prompt.
3762
3763 @deffn {Flash Driver} str9xpec
3764 Only use this driver for locking/unlocking the device or configuring the option bytes.
3765 Use the standard str9 driver for programming.
3766 Before using the flash commands the turbo mode must be enabled using the
3767 @command{str9xpec enable_turbo} command.
3768
3769 Several str9xpec-specific commands are defined:
3770
3771 @deffn Command {str9xpec disable_turbo} num
3772 Restore the str9 into JTAG chain.
3773 @end deffn
3774
3775 @deffn Command {str9xpec enable_turbo} num
3776 Enable turbo mode, will simply remove the str9 from the chain and talk
3777 directly to the embedded flash controller.
3778 @end deffn
3779
3780 @deffn Command {str9xpec lock} num
3781 Lock str9 device. The str9 will only respond to an unlock command that will
3782 erase the device.
3783 @end deffn
3784
3785 @deffn Command {str9xpec part_id} num
3786 Prints the part identifier for bank @var{num}.
3787 @end deffn
3788
3789 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
3790 Configure str9 boot bank.
3791 @end deffn
3792
3793 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
3794 Configure str9 lvd source.
3795 @end deffn
3796
3797 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
3798 Configure str9 lvd threshold.
3799 @end deffn
3800
3801 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
3802 Configure str9 lvd reset warning source.
3803 @end deffn
3804
3805 @deffn Command {str9xpec options_read} num
3806 Read str9 option bytes.
3807 @end deffn
3808
3809 @deffn Command {str9xpec options_write} num
3810 Write str9 option bytes.
3811 @end deffn
3812
3813 @deffn Command {str9xpec unlock} num
3814 unlock str9 device.
3815 @end deffn
3816
3817 @end deffn
3818
3819
3820 @section mFlash
3821
3822 @subsection mFlash Configuration
3823 @cindex mFlash Configuration
3824
3825 @deffn {Config Command} {mflash bank} soc base RST_pin target
3826 Configures a mflash for @var{soc} host bank at
3827 address @var{base}.
3828 The pin number format depends on the host GPIO naming convention.
3829 Currently, the mflash driver supports s3c2440 and pxa270.
3830
3831 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
3832
3833 @example
3834 mflash bank s3c2440 0x10000000 1b 0
3835 @end example
3836
3837 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
3838
3839 @example
3840 mflash bank pxa270 0x08000000 43 0
3841 @end example
3842 @end deffn
3843
3844 @subsection mFlash commands
3845 @cindex mFlash commands
3846
3847 @deffn Command {mflash config pll} frequency
3848 Configure mflash PLL.
3849 The @var{frequency} is the mflash input frequency, in Hz.
3850 Issuing this command will erase mflash's whole internal nand and write new pll.
3851 After this command, mflash needs power-on-reset for normal operation.
3852 If pll was newly configured, storage and boot(optional) info also need to be update.
3853 @end deffn
3854
3855 @deffn Command {mflash config boot}
3856 Configure bootable option.
3857 If bootable option is set, mflash offer the first 8 sectors
3858 (4kB) for boot.
3859 @end deffn
3860
3861 @deffn Command {mflash config storage}
3862 Configure storage information.
3863 For the normal storage operation, this information must be
3864 written.
3865 @end deffn
3866
3867 @deffn Command {mflash dump} num filename offset size
3868 Dump @var{size} bytes, starting at @var{offset} bytes from the
3869 beginning of the bank @var{num}, to the file named @var{filename}.
3870 @end deffn
3871
3872 @deffn Command {mflash probe}
3873 Probe mflash.
3874 @end deffn
3875
3876 @deffn Command {mflash write} num filename offset
3877 Write the binary file @var{filename} to mflash bank @var{num}, starting at
3878 @var{offset} bytes from the beginning of the bank.
3879 @end deffn
3880
3881 @node NAND Flash Commands
3882 @chapter NAND Flash Commands
3883 @cindex NAND
3884
3885 Compared to NOR or SPI flash, NAND devices are inexpensive
3886 and high density. Today's NAND chips, and multi-chip modules,
3887 commonly hold multiple GigaBytes of data.
3888
3889 NAND chips consist of a number of ``erase blocks'' of a given
3890 size (such as 128 KBytes), each of which is divided into a
3891 number of pages (of perhaps 512 or 2048 bytes each). Each
3892 page of a NAND flash has an ``out of band'' (OOB) area to hold
3893 Error Correcting Code (ECC) and other metadata, usually 16 bytes
3894 of OOB for every 512 bytes of page data.
3895
3896 One key characteristic of NAND flash is that its error rate
3897 is higher than that of NOR flash. In normal operation, that
3898 ECC is used to correct and detect errors. However, NAND
3899 blocks can also wear out and become unusable; those blocks
3900 are then marked "bad". NAND chips are even shipped from the
3901 manufacturer with a few bad blocks. The highest density chips
3902 use a technology (MLC) that wears out more quickly, so ECC
3903 support is increasingly important as a way to detect blocks
3904 that have begun to fail, and help to preserve data integrity
3905 with techniques such as wear leveling.
3906
3907 Software is used to manage the ECC. Some controllers don't
3908 support ECC directly; in those cases, software ECC is used.
3909 Other controllers speed up the ECC calculations with hardware.
3910 Single-bit error correction hardware is routine. Controllers
3911 geared for newer MLC chips may correct 4 or more errors for
3912 every 512 bytes of data.
3913
3914 You will need to make sure that any data you write using
3915 OpenOCD includes the apppropriate kind of ECC. For example,
3916 that may mean passing the @code{oob_softecc} flag when
3917 writing NAND data, or ensuring that the correct hardware
3918 ECC mode is used.
3919
3920 The basic steps for using NAND devices include:
3921 @enumerate
3922 @item Declare via the command @command{nand device}
3923 @* Do this in a board-specific configuration file,
3924 passing parameters as needed by the controller.
3925 @item Configure each device using @command{nand probe}.
3926 @* Do this only after the associated target is set up,
3927 such as in its reset-init script or in procures defined
3928 to access that device.
3929 @item Operate on the flash via @command{nand subcommand}
3930 @* Often commands to manipulate the flash are typed by a human, or run
3931 via a script in some automated way. Common task include writing a
3932 boot loader, operating system, or other data needed to initialize or
3933 de-brick a board.
3934 @end enumerate
3935
3936 @b{NOTE:} At the time this text was written, the largest NAND
3937 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
3938 This is because the variables used to hold offsets and lengths
3939 are only 32 bits wide.
3940 (Larger chips may work in some cases, unless an offset or length
3941 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
3942 Some larger devices will work, since they are actually multi-chip
3943 modules with two smaller chips and individual chipselect lines.
3944
3945 @anchor{NAND Configuration}
3946 @section NAND Configuration Commands
3947 @cindex NAND configuration
3948
3949 NAND chips must be declared in configuration scripts,
3950 plus some additional configuration that's done after
3951 OpenOCD has initialized.
3952
3953 @deffn {Config Command} {nand device} controller target [configparams...]
3954 Declares a NAND device, which can be read and written to
3955 after it has been configured through @command{nand probe}.
3956 In OpenOCD, devices are single chips; this is unlike some
3957 operating systems, which may manage multiple chips as if
3958 they were a single (larger) device.
3959 In some cases, configuring a device will activate extra
3960 commands; see the controller-specific documentation.
3961
3962 @b{NOTE:} This command is not available after OpenOCD
3963 initialization has completed. Use it in board specific
3964 configuration files, not interactively.
3965
3966 @itemize @bullet
3967 @item @var{controller} ... identifies the controller driver
3968 associated with the NAND device being declared.
3969 @xref{NAND Driver List}.
3970 @item @var{target} ... names the target used when issuing
3971 commands to the NAND controller.
3972 @comment Actually, it's currently a controller-specific parameter...
3973 @item @var{configparams} ... controllers may support, or require,
3974 additional parameters. See the controller-specific documentation
3975 for more information.
3976 @end itemize
3977 @end deffn
3978
3979 @deffn Command {nand list}
3980 Prints a summary of each device declared
3981 using @command{nand device}, numbered from zero.
3982 Note that un-probed devices show no details.
3983 @example
3984 > nand list
3985 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
3986 blocksize: 131072, blocks: 8192
3987 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
3988 blocksize: 131072, blocks: 8192
3989 >
3990 @end example
3991 @end deffn
3992
3993 @deffn Command {nand probe} num
3994 Probes the specified device to determine key characteristics
3995 like its page and block sizes, and how many blocks it has.
3996 The @var{num} parameter is the value shown by @command{nand list}.
3997 You must (successfully) probe a device before you can use
3998 it with most other NAND commands.
3999 @end deffn
4000
4001 @section Erasing, Reading, Writing to NAND Flash
4002
4003 @deffn Command {nand dump} num filename offset length [oob_option]
4004 @cindex NAND reading
4005 Reads binary data from the NAND device and writes it to the file,
4006 starting at the specified offset.
4007 The @var{num} parameter is the value shown by @command{nand list}.
4008
4009 Use a complete path name for @var{filename}, so you don't depend
4010 on the directory used to start the OpenOCD server.
4011
4012 The @var{offset} and @var{length} must be exact multiples of the
4013 device's page size. They describe a data region; the OOB data
4014 associated with each such page may also be accessed.
4015
4016 @b{NOTE:} At the time this text was written, no error correction
4017 was done on the data that's read, unless raw access was disabled
4018 and the underlying NAND controller driver had a @code{read_page}
4019 method which handled that error correction.
4020
4021 By default, only page data is saved to the specified file.
4022 Use an @var{oob_option} parameter to save OOB data:
4023 @itemize @bullet
4024 @item no oob_* parameter
4025 @*Output file holds only page data; OOB is discarded.
4026 @item @code{oob_raw}
4027 @*Output file interleaves page data and OOB data;
4028 the file will be longer than "length" by the size of the
4029 spare areas associated with each data page.
4030 Note that this kind of "raw" access is different from
4031 what's implied by @command{nand raw_access}, which just
4032 controls whether a hardware-aware access method is used.
4033 @item @code{oob_only}
4034 @*Output file has only raw OOB data, and will
4035 be smaller than "length" since it will contain only the
4036 spare areas associated with each data page.
4037 @end itemize
4038 @end deffn
4039
4040 @deffn Command {nand erase} num [offset length]
4041 @cindex NAND erasing
4042 @cindex NAND programming
4043 Erases blocks on the specified NAND device, starting at the
4044 specified @var{offset} and continuing for @var{length} bytes.
4045 Both of those values must be exact multiples of the device's
4046 block size, and the region they specify must fit entirely in the chip.
4047 If those parameters are not specified,
4048 the whole NAND chip will be erased.
4049 The @var{num} parameter is the value shown by @command{nand list}.
4050
4051 @b{NOTE:} This command will try to erase bad blocks, when told
4052 to do so, which will probably invalidate the manufacturer's bad
4053 block marker.
4054 For the remainder of the current server session, @command{nand info}
4055 will still report that the block ``is'' bad.
4056 @end deffn
4057
4058 @deffn Command {nand write} num filename offset [option...]
4059 @cindex NAND writing
4060 @cindex NAND programming
4061 Writes binary data from the file into the specified NAND device,
4062 starting at the specified offset. Those pages should already
4063 have been erased; you can't change zero bits to one bits.
4064 The @var{num} parameter is the value shown by @command{nand list}.
4065
4066 Use a complete path name for @var{filename}, so you don't depend
4067 on the directory used to start the OpenOCD server.
4068
4069 The @var{offset} must be an exact multiple of the device's page size.
4070 All data in the file will be written, assuming it doesn't run
4071 past the end of the device.
4072 Only full pages are written, and any extra space in the last
4073 page will be filled with 0xff bytes. (That includes OOB data,
4074 if that's being written.)
4075
4076 @b{NOTE:} At the time this text was written, bad blocks are
4077 ignored. That is, this routine will not skip bad blocks,
4078 but will instead try to write them. This can cause problems.
4079
4080 Provide at most one @var{option} parameter. With some
4081 NAND drivers, the meanings of these parameters may change
4082 if @command{nand raw_access} was used to disable hardware ECC.
4083 @itemize @bullet
4084 @item no oob_* parameter
4085 @*File has only page data, which is written.
4086 If raw acccess is in use, the OOB area will not be written.
4087 Otherwise, if the underlying NAND controller driver has
4088 a @code{write_page} routine, that routine may write the OOB
4089 with hardware-computed ECC data.
4090 @item @code{oob_only}
4091 @*File has only raw OOB data, which is written to the OOB area.
4092 Each page's data area stays untouched. @i{This can be a dangerous
4093 option}, since it can invalidate the ECC data.
4094 You may need to force raw access to use this mode.
4095 @item @code{oob_raw}
4096 @*File interleaves data and OOB data, both of which are written
4097 If raw access is enabled, the data is written first, then the
4098 un-altered OOB.
4099 Otherwise, if the underlying NAND controller driver has
4100 a @code{write_page} routine, that routine may modify the OOB
4101 before it's written, to include hardware-computed ECC data.
4102 @item @code{oob_softecc}
4103 @*File has only page data, which is written.
4104 The OOB area is filled with 0xff, except for a standard 1-bit
4105 software ECC code stored in conventional locations.
4106 You might need to force raw access to use this mode, to prevent
4107 the underlying driver from applying hardware ECC.
4108 @item @code{oob_softecc_kw}
4109 @*File has only page data, which is written.
4110 The OOB area is filled with 0xff, except for a 4-bit software ECC
4111 specific to the boot ROM in Marvell Kirkwood SoCs.
4112 You might need to force raw access to use this mode, to prevent
4113 the underlying driver from applying hardware ECC.
4114 @end itemize
4115 @end deffn
4116
4117 @section Other NAND commands
4118 @cindex NAND other commands
4119
4120 @deffn Command {nand check_bad_blocks} [offset length]
4121 Checks for manufacturer bad block markers on the specified NAND
4122 device. If no parameters are provided, checks the whole
4123 device; otherwise, starts at the specified @var{offset} and
4124 continues for @var{length} bytes.
4125 Both of those values must be exact multiples of the device's
4126 block size, and the region they specify must fit entirely in the chip.
4127 The @var{num} parameter is the value shown by @command{nand list}.
4128
4129 @b{NOTE:} Before using this command you should force raw access
4130 with @command{nand raw_access enable} to ensure that the underlying
4131 driver will not try to apply hardware ECC.
4132 @end deffn
4133
4134 @deffn Command {nand info} num
4135 The @var{num} parameter is the value shown by @command{nand list}.
4136 This prints the one-line summary from "nand list", plus for
4137 devices which have been probed this also prints any known
4138 status for each block.
4139 @end deffn
4140
4141 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
4142 Sets or clears an flag affecting how page I/O is done.
4143 The @var{num} parameter is the value shown by @command{nand list}.
4144
4145 This flag is cleared (disabled) by default, but changing that
4146 value won't affect all NAND devices. The key factor is whether
4147 the underlying driver provides @code{read_page} or @code{write_page}
4148 methods. If it doesn't provide those methods, the setting of
4149 this flag is irrelevant; all access is effectively ``raw''.
4150
4151 When those methods exist, they are normally used when reading
4152 data (@command{nand dump} or reading bad block markers) or
4153 writing it (@command{nand write}). However, enabling
4154 raw access (setting the flag) prevents use of those methods,
4155 bypassing hardware ECC logic.
4156 @i{This can be a dangerous option}, since writing blocks
4157 with the wrong ECC data can cause them to be marked as bad.
4158 @end deffn
4159
4160 @anchor{NAND Driver List}
4161 @section NAND Drivers, Options, and Commands
4162 As noted above, the @command{nand device} command allows
4163 driver-specific options and behaviors.
4164 Some controllers also activate controller-specific commands.
4165
4166 @deffn {NAND Driver} davinci
4167 This driver handles the NAND controllers found on DaVinci family
4168 chips from Texas Instruments.
4169 It takes three extra parameters:
4170 address of the NAND chip;
4171 hardware ECC mode to use (@option{hwecc1},
4172 @option{hwecc4}, @option{hwecc4_infix});
4173 address of the AEMIF controller on this processor.
4174 @example
4175 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
4176 @end example
4177 All DaVinci processors support the single-bit ECC hardware,
4178 and newer ones also support the four-bit ECC hardware.
4179 The @code{write_page} and @code{read_page} methods are used
4180 to implement those ECC modes, unless they are disabled using
4181 the @command{nand raw_access} command.
4182 @end deffn
4183
4184 @deffn {NAND Driver} lpc3180
4185 These controllers require an extra @command{nand device}
4186 parameter: the clock rate used by the controller.
4187 @deffn Command {lpc3180 select} num [mlc|slc]
4188 Configures use of the MLC or SLC controller mode.
4189 MLC implies use of hardware ECC.
4190 The @var{num} parameter is the value shown by @command{nand list}.
4191 @end deffn
4192
4193 At this writing, this driver includes @code{write_page}
4194 and @code{read_page} methods. Using @command{nand raw_access}
4195 to disable those methods will prevent use of hardware ECC
4196 in the MLC controller mode, but won't change SLC behavior.
4197 @end deffn
4198 @comment current lpc3180 code won't issue 5-byte address cycles
4199
4200 @deffn {NAND Driver} orion
4201 These controllers require an extra @command{nand device}
4202 parameter: the address of the controller.