doc: opendous interface based on ft2232H
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * NAND Flash Commands:: NAND Flash Commands
77 * PLD/FPGA Commands:: PLD/FPGA Commands
78 * General Commands:: General Commands
79 * Architecture and Core Commands:: Architecture and Core Commands
80 * JTAG Commands:: JTAG Commands
81 * Boundary Scan Commands:: Boundary Scan Commands
82 * TFTP:: TFTP
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on:
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
95 @end menu
97 @node About
98 @unnumbered About
99 @cindex about
101 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
102 University of Applied Sciences Augsburg (@uref{}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
105 around the world.
107 @section What is OpenOCD?
108 @cindex TAP
109 @cindex JTAG
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
113 devices.
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board can be directly connected to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
140 scan operations.
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD only supports
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
154 based, parallel port based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
159 Cortex-M3 (Stellaris LM3, ST STM32 and Energy Micro EFM32) based cores to be
160 debugged via the GDB protocol.
162 @b{Flash Programing:} Flash writing is supported for external CFI
163 compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3,
165 STM32x and EFM32). Preliminary support for various NAND flash controllers
166 (LPC3180, Orion, S3C24xx, more) controller is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{}
182 PDF form is likewise published at:
184 @uref{}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{}
203 @section OpenOCD IRC
205 Support can also be found on irc:
206 @uref{irc://}
208 @node Developers
209 @chapter OpenOCD Developer Resources
210 @cindex developers
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD GIT Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a GIT repository hosted at SourceForge. The repository URL is:
225 @uref{git://}
227 You may prefer to use a mirror and the HTTP protocol:
229 @uref{}
231 With standard GIT tools, use @command{git clone} to initialize
232 a local repository, and @command{git pull} to update it.
233 There are also gitweb pages letting you browse the repository
234 with a web browser, or download arbitrary snapshots without
235 needing a GIT client:
237 @uref{}
239 @uref{}
241 The @file{README} file contains the instructions for building the project
242 from the repository or a snapshot.
244 Developers that want to contribute patches to the OpenOCD system are
245 @b{strongly} encouraged to work against mainline.
246 Patches created against older versions may require additional
247 work from their submitter in order to be updated for newer releases.
249 @section Doxygen Developer Manual
251 During the 0.2.x release cycle, the OpenOCD project began
252 providing a Doxygen reference manual. This document contains more
253 technical information about the software internals, development
254 processes, and similar documentation:
256 @uref{}
258 This document is a work-in-progress, but contributions would be welcome
259 to fill in the gaps. All of the source files are provided in-tree,
260 listed in the Doxyfile configuration in the top of the source tree.
262 @section OpenOCD Developer Mailing List
264 The OpenOCD Developer Mailing List provides the primary means of
265 communication between developers:
267 @uref{}
269 Discuss and submit patches to this list.
270 The @file{HACKING} file contains basic information about how
271 to prepare patches.
273 @section OpenOCD Bug Database
275 During the 0.4.x release cycle the OpenOCD project team began
276 using Trac for its bug database:
278 @uref{}
281 @node Debug Adapter Hardware
282 @chapter Debug Adapter Hardware
283 @cindex dongles
284 @cindex FTDI
285 @cindex wiggler
286 @cindex zy1000
287 @cindex printer port
288 @cindex USB Adapter
289 @cindex RTCK
291 Defined: @b{dongle}: A small device that plugins into a computer and serves as
292 an adapter .... [snip]
294 In the OpenOCD case, this generally refers to @b{a small adapter} that
295 attaches to your computer via USB or the Parallel Printer Port. One
296 exception is the Zylin ZY1000, packaged as a small box you attach via
297 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
298 require any drivers to be installed on the developer PC. It also has
299 a built in web interface. It supports RTCK/RCLK or adaptive clocking
300 and has a built in relay to power cycle targets remotely.
303 @section Choosing a Dongle
305 There are several things you should keep in mind when choosing a dongle.
307 @enumerate
308 @item @b{Transport} Does it support the kind of communication that you need?
309 OpenOCD focusses mostly on JTAG. Your version may also support
310 other ways to communicate with target devices.
311 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
312 Does your dongle support it? You might need a level converter.
313 @item @b{Pinout} What pinout does your target board use?
314 Does your dongle support it? You may be able to use jumper
315 wires, or an "octopus" connector, to convert pinouts.
316 @item @b{Connection} Does your computer have the USB, printer, or
317 Ethernet port needed?
318 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
319 RTCK support? Also known as ``adaptive clocking''
320 @end enumerate
322 @section Stand alone Systems
324 @b{ZY1000} See: @url{} Technically, not a
325 dongle, but a standalone box. The ZY1000 has the advantage that it does
326 not require any drivers installed on the developer PC. It also has
327 a built in web interface. It supports RTCK/RCLK or adaptive clocking
328 and has a built in relay to power cycle targets remotely.
330 @section USB FT2232 Based
332 There are many USB JTAG dongles on the market, many of them are based
333 on a chip from ``Future Technology Devices International'' (FTDI)
334 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
335 See: @url{} for more information.
336 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
337 chips are starting to become available in JTAG adapters. (Adapters
338 using those high speed FT2232H chips may support adaptive clocking.)
340 The FT2232 chips are flexible enough to support some other
341 transport options, such as SWD or the SPI variants used to
342 program some chips. They have two communications channels,
343 and one can be used for a UART adapter at the same time the
344 other one is used to provide a debug adapter.
346 Also, some development boards integrate an FT2232 chip to serve as
347 a built-in low cost debug adapter and usb-to-serial solution.
349 @itemize @bullet
350 @item @b{usbjtag}
351 @* Link @url{}
352 @item @b{jtagkey}
353 @* See: @url{}
354 @item @b{jtagkey2}
355 @* See: @url{}
356 @item @b{oocdlink}
357 @* See: @url{} By Joern Kaipf
358 @item @b{signalyzer}
359 @* See: @url{}
360 @item @b{Stellaris Eval Boards}
361 @* See: @url{} - The Stellaris eval boards
362 bundle FT2232-based JTAG and SWD support, which can be used to debug
363 the Stellaris chips. Using separate JTAG adapters is optional.
364 These boards can also be used in a "pass through" mode as JTAG adapters
365 to other target boards, disabling the Stellaris chip.
366 @item @b{TI/Luminary ICDI}
367 @* See: @url{} - TI/Luminary In-Circuit Debug
368 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
369 Evaluation Kits. Like the non-detachable FT2232 support on the other
370 Stellaris eval boards, they can be used to debug other target boards.
371 @item @b{olimex-jtag}
372 @* See: @url{}
373 @item @b{Flyswatter/Flyswatter2}
374 @* See: @url{}
375 @item @b{turtelizer2}
376 @* See:
377 @uref{, Turtelizer 2}, or
378 @url{}
379 @item @b{comstick}
380 @* Link: @url{}
381 @item @b{stm32stick}
382 @* Link @url{}
383 @item @b{axm0432_jtag}
384 @* Axiom AXM-0432 Link @url{} - NOTE: This JTAG does not appear
385 to be available anymore as of April 2012.
386 @item @b{cortino}
387 @* Link @url{}
388 @item @b{dlp-usb1232h}
389 @* Link @url{}
390 @item @b{digilent-hs1}
391 @* Link @url{}
392 @item @b{opendous}
393 @* Link @url{} FT2232H-based
394 (OpenHardware).
395 @end itemize
397 @section USB-JTAG / Altera USB-Blaster compatibles
399 These devices also show up as FTDI devices, but are not
400 protocol-compatible with the FT2232 devices. They are, however,
401 protocol-compatible among themselves. USB-JTAG devices typically consist
402 of a FT245 followed by a CPLD that understands a particular protocol,
403 or emulate this protocol using some other hardware.
405 They may appear under different USB VID/PID depending on the particular
406 product. The driver can be configured to search for any VID/PID pair
407 (see the section on driver commands).
409 @itemize
410 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
411 @* Link: @url{}
412 @item @b{Altera USB-Blaster}
413 @* Link: @url{}
414 @end itemize
416 @section USB JLINK based
417 There are several OEM versions of the Segger @b{JLINK} adapter. It is
418 an example of a micro controller based JTAG adapter, it uses an
419 AT91SAM764 internally.
421 @itemize @bullet
422 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
423 @* Link: @url{}
424 @item @b{SEGGER JLINK}
425 @* Link: @url{}
426 @item @b{IAR J-Link}
427 @* Link: @url{}
428 @end itemize
430 @section USB RLINK based
431 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
433 @itemize @bullet
434 @item @b{Raisonance RLink}
435 @* Link: @url{}
436 @item @b{STM32 Primer}
437 @* Link: @url{}
438 @item @b{STM32 Primer2}
439 @* Link: @url{}
440 @end itemize
442 @section USB ST-LINK based
443 ST Micro has an adapter called @b{ST-LINK}.
444 They only work with ST Micro chips, notably STM32 and STM8.
446 @itemize @bullet
447 @item @b{ST-LINK}
448 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
449 @* Link: @url{}
450 @item @b{ST-LINK/V2}
451 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
452 @* Link: @url{}
453 @end itemize
455 For info the original ST-LINK enumerates using the mass storage usb class, however
456 it's implementation is completely broken. The result is this causes issues under linux.
457 The simplest solution is to get linux to ignore the ST-LINK using one of the following methods:
458 @itemize @bullet
459 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
460 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
461 @end itemize
463 @section USB TI/Stellaris ICDI based
464 Texas Instruments has an adapter called @b{ICDI}.
465 It is not to be confused with the FTDI based adapters that were originally fitted to their
466 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
468 @section USB Other
469 @itemize @bullet
470 @item @b{USBprog}
471 @* Link: @url{} - which uses an Atmel MEGA32 and a UBN9604
473 @item @b{USB - Presto}
474 @* Link: @url{}
476 @item @b{Versaloon-Link}
477 @* Link: @url{}
479 @item @b{ARM-JTAG-EW}
480 @* Link: @url{}
482 @item @b{Buspirate}
483 @* Link: @url{}
485 @item @b{opendous}
486 @* Link: @url{} - which uses an AT90USB162
488 @item @b{estick}
489 @* Link: @url{}
491 @item @b{Keil ULINK v1}
492 @* Link: @url{}
493 @end itemize
495 @section IBM PC Parallel Printer Port Based
497 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
498 and the Macraigor Wiggler. There are many clones and variations of
499 these on the market.
501 Note that parallel ports are becoming much less common, so if you
502 have the choice you should probably avoid these adapters in favor
503 of USB-based ones.
505 @itemize @bullet
507 @item @b{Wiggler} - There are many clones of this.
508 @* Link: @url{}
510 @item @b{DLC5} - From XILINX - There are many clones of this
511 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
512 produced, PDF schematics are easily found and it is easy to make.
514 @item @b{Amontec - JTAG Accelerator}
515 @* Link: @url{}
517 @item @b{GW16402}
518 @* Link: @url{}
520 @item @b{Wiggler2}
521 @* Link: @url{}
523 @item @b{Wiggler_ntrst_inverted}
524 @* Yet another variation - See the source code, src/jtag/parport.c
526 @item @b{old_amt_wiggler}
527 @* Unknown - probably not on the market today
529 @item @b{arm-jtag}
530 @* Link: Most likely @url{} [another wiggler clone]
532 @item @b{chameleon}
533 @* Link: @url{}
535 @item @b{Triton}
536 @* Unknown.
538 @item @b{Lattice}
539 @* ispDownload from Lattice Semiconductor
540 @url{}
542 @item @b{flashlink}
543 @* From ST Microsystems;
544 @* Link: @url{}
546 @end itemize
548 @section Other...
549 @itemize @bullet
551 @item @b{ep93xx}
552 @* An EP93xx based Linux machine using the GPIO pins directly.
554 @item @b{at91rm9200}
555 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
557 @end itemize
559 @node About Jim-Tcl
560 @chapter About Jim-Tcl
561 @cindex Jim-Tcl
562 @cindex tcl
564 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
565 This programming language provides a simple and extensible
566 command interpreter.
568 All commands presented in this Guide are extensions to Jim-Tcl.
569 You can use them as simple commands, without needing to learn
570 much of anything about Tcl.
571 Alternatively, can write Tcl programs with them.
573 You can learn more about Jim at its website, @url{}.
574 There is an active and responsive community, get on the mailing list
575 if you have any questions. Jim-Tcl maintainers also lurk on the
576 OpenOCD mailing list.
578 @itemize @bullet
579 @item @b{Jim vs. Tcl}
580 @* Jim-Tcl is a stripped down version of the well known Tcl language,
581 which can be found here: @url{}. Jim-Tcl has far
582 fewer features. Jim-Tcl is several dozens of .C files and .H files and
583 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
584 4.2 MB .zip file containing 1540 files.
586 @item @b{Missing Features}
587 @* Our practice has been: Add/clone the real Tcl feature if/when
588 needed. We welcome Jim-Tcl improvements, not bloat. Also there
589 are a large number of optional Jim-Tcl features that are not
590 enabled in OpenOCD.
592 @item @b{Scripts}
593 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
594 command interpreter today is a mixture of (newer)
595 Jim-Tcl commands, and (older) the orginal command interpreter.
597 @item @b{Commands}
598 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
599 can type a Tcl for() loop, set variables, etc.
600 Some of the commands documented in this guide are implemented
601 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
603 @item @b{Historical Note}
604 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
605 before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
606 as a git submodule, which greatly simplified upgrading Jim Tcl
607 to benefit from new features and bugfixes in Jim Tcl.
609 @item @b{Need a crash course in Tcl?}
610 @*@xref{Tcl Crash Course}.
611 @end itemize
613 @node Running
614 @chapter Running
615 @cindex command line options
616 @cindex logfile
617 @cindex directory search
619 Properly installing OpenOCD sets up your operating system to grant it access
620 to the debug adapters. On Linux, this usually involves installing a file
621 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
622 complex and confusing driver configuration for every peripheral. Such issues
623 are unique to each operating system, and are not detailed in this User's Guide.
625 Then later you will invoke the OpenOCD server, with various options to
626 tell it how each debug session should work.
627 The @option{--help} option shows:
628 @verbatim
629 bash$ openocd --help
631 --help | -h display this help
632 --version | -v display OpenOCD version
633 --file | -f use configuration file <name>
634 --search | -s dir to search for config files and scripts
635 --debug | -d set debug level <0-3>
636 --log_output | -l redirect log output to file <name>
637 --command | -c run <command>
638 @end verbatim
640 If you don't give any @option{-f} or @option{-c} options,
641 OpenOCD tries to read the configuration file @file{openocd.cfg}.
642 To specify one or more different
643 configuration files, use @option{-f} options. For example:
645 @example
646 openocd -f config1.cfg -f config2.cfg -f config3.cfg
647 @end example
649 Configuration files and scripts are searched for in
650 @enumerate
651 @item the current directory,
652 @item any search dir specified on the command line using the @option{-s} option,
653 @item any search dir specified using the @command{add_script_search_dir} command,
654 @item @file{$HOME/.openocd} (not on Windows),
655 @item the site wide script library @file{$pkgdatadir/site} and
656 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
657 @end enumerate
658 The first found file with a matching file name will be used.
660 @quotation Note
661 Don't try to use configuration script names or paths which
662 include the "#" character. That character begins Tcl comments.
663 @end quotation
665 @section Simple setup, no customization
667 In the best case, you can use two scripts from one of the script
668 libraries, hook up your JTAG adapter, and start the server ... and
669 your JTAG setup will just work "out of the box". Always try to
670 start by reusing those scripts, but assume you'll need more
671 customization even if this works. @xref{OpenOCD Project Setup}.
673 If you find a script for your JTAG adapter, and for your board or
674 target, you may be able to hook up your JTAG adapter then start
675 the server like:
677 @example
678 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
679 @end example
681 You might also need to configure which reset signals are present,
682 using @option{-c 'reset_config trst_and_srst'} or something similar.
683 If all goes well you'll see output something like
685 @example
686 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
687 For bug reports, read
689 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
690 (mfg: 0x23b, part: 0xba00, ver: 0x3)
691 @end example
693 Seeing that "tap/device found" message, and no warnings, means
694 the JTAG communication is working. That's a key milestone, but
695 you'll probably need more project-specific setup.
697 @section What OpenOCD does as it starts
699 OpenOCD starts by processing the configuration commands provided
700 on the command line or, if there were no @option{-c command} or
701 @option{-f file.cfg} options given, in @file{openocd.cfg}.
702 @xref{Configuration Stage}.
703 At the end of the configuration stage it verifies the JTAG scan
704 chain defined using those commands; your configuration should
705 ensure that this always succeeds.
706 Normally, OpenOCD then starts running as a daemon.
707 Alternatively, commands may be used to terminate the configuration
708 stage early, perform work (such as updating some flash memory),
709 and then shut down without acting as a daemon.
711 Once OpenOCD starts running as a daemon, it waits for connections from
712 clients (Telnet, GDB, Other) and processes the commands issued through
713 those channels.
715 If you are having problems, you can enable internal debug messages via
716 the @option{-d} option.
718 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
719 @option{-c} command line switch.
721 To enable debug output (when reporting problems or working on OpenOCD
722 itself), use the @option{-d} command line switch. This sets the
723 @option{debug_level} to "3", outputting the most information,
724 including debug messages. The default setting is "2", outputting only
725 informational messages, warnings and errors. You can also change this
726 setting from within a telnet or gdb session using @command{debug_level
727 <n>} (@pxref{debug_level}).
729 You can redirect all output from the daemon to a file using the
730 @option{-l <logfile>} switch.
732 Note! OpenOCD will launch the GDB & telnet server even if it can not
733 establish a connection with the target. In general, it is possible for
734 the JTAG controller to be unresponsive until the target is set up
735 correctly via e.g. GDB monitor commands in a GDB init script.
737 @node OpenOCD Project Setup
738 @chapter OpenOCD Project Setup
740 To use OpenOCD with your development projects, you need to do more than
741 just connecting the JTAG adapter hardware (dongle) to your development board
742 and then starting the OpenOCD server.
743 You also need to configure that server so that it knows
744 about that adapter and board, and helps your work.
745 You may also want to connect OpenOCD to GDB, possibly
746 using Eclipse or some other GUI.
748 @section Hooking up the JTAG Adapter
750 Today's most common case is a dongle with a JTAG cable on one side
751 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
752 and a USB cable on the other.
753 Instead of USB, some cables use Ethernet;
754 older ones may use a PC parallel port, or even a serial port.
756 @enumerate
757 @item @emph{Start with power to your target board turned off},
758 and nothing connected to your JTAG adapter.
759 If you're particularly paranoid, unplug power to the board.
760 It's important to have the ground signal properly set up,
761 unless you are using a JTAG adapter which provides
762 galvanic isolation between the target board and the
763 debugging host.
765 @item @emph{Be sure it's the right kind of JTAG connector.}
766 If your dongle has a 20-pin ARM connector, you need some kind
767 of adapter (or octopus, see below) to hook it up to
768 boards using 14-pin or 10-pin connectors ... or to 20-pin
769 connectors which don't use ARM's pinout.
771 In the same vein, make sure the voltage levels are compatible.
772 Not all JTAG adapters have the level shifters needed to work
773 with 1.2 Volt boards.
775 @item @emph{Be certain the cable is properly oriented} or you might
776 damage your board. In most cases there are only two possible
777 ways to connect the cable.
778 Connect the JTAG cable from your adapter to the board.
779 Be sure it's firmly connected.
781 In the best case, the connector is keyed to physically
782 prevent you from inserting it wrong.
783 This is most often done using a slot on the board's male connector
784 housing, which must match a key on the JTAG cable's female connector.
785 If there's no housing, then you must look carefully and
786 make sure pin 1 on the cable hooks up to pin 1 on the board.
787 Ribbon cables are frequently all grey except for a wire on one
788 edge, which is red. The red wire is pin 1.
790 Sometimes dongles provide cables where one end is an ``octopus'' of
791 color coded single-wire connectors, instead of a connector block.
792 These are great when converting from one JTAG pinout to another,
793 but are tedious to set up.
794 Use these with connector pinout diagrams to help you match up the
795 adapter signals to the right board pins.
797 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
798 A USB, parallel, or serial port connector will go to the host which
799 you are using to run OpenOCD.
800 For Ethernet, consult the documentation and your network administrator.
802 For USB based JTAG adapters you have an easy sanity check at this point:
803 does the host operating system see the JTAG adapter? If that host is an
804 MS-Windows host, you'll need to install a driver before OpenOCD works.
806 @item @emph{Connect the adapter's power supply, if needed.}
807 This step is primarily for non-USB adapters,
808 but sometimes USB adapters need extra power.
810 @item @emph{Power up the target board.}
811 Unless you just let the magic smoke escape,
812 you're now ready to set up the OpenOCD server
813 so you can use JTAG to work with that board.
815 @end enumerate
817 Talk with the OpenOCD server using
818 telnet (@code{telnet localhost 4444} on many systems) or GDB.
819 @xref{GDB and OpenOCD}.
821 @section Project Directory
823 There are many ways you can configure OpenOCD and start it up.
825 A simple way to organize them all involves keeping a
826 single directory for your work with a given board.
827 When you start OpenOCD from that directory,
828 it searches there first for configuration files, scripts,
829 files accessed through semihosting,
830 and for code you upload to the target board.
831 It is also the natural place to write files,
832 such as log files and data you download from the board.
834 @section Configuration Basics
836 There are two basic ways of configuring OpenOCD, and
837 a variety of ways you can mix them.
838 Think of the difference as just being how you start the server:
840 @itemize
841 @item Many @option{-f file} or @option{-c command} options on the command line
842 @item No options, but a @dfn{user config file}
843 in the current directory named @file{openocd.cfg}
844 @end itemize
846 Here is an example @file{openocd.cfg} file for a setup
847 using a Signalyzer FT2232-based JTAG adapter to talk to
848 a board with an Atmel AT91SAM7X256 microcontroller:
850 @example
851 source [find interface/signalyzer.cfg]
853 # GDB can also flash my flash!
854 gdb_memory_map enable
855 gdb_flash_program enable
857 source [find target/sam7x256.cfg]
858 @end example
860 Here is the command line equivalent of that configuration:
862 @example
863 openocd -f interface/signalyzer.cfg \
864 -c "gdb_memory_map enable" \
865 -c "gdb_flash_program enable" \
866 -f target/sam7x256.cfg
867 @end example
869 You could wrap such long command lines in shell scripts,
870 each supporting a different development task.
871 One might re-flash the board with a specific firmware version.
872 Another might set up a particular debugging or run-time environment.
874 @quotation Important
875 At this writing (October 2009) the command line method has
876 problems with how it treats variables.
877 For example, after @option{-c "set VAR value"}, or doing the
878 same in a script, the variable @var{VAR} will have no value
879 that can be tested in a later script.
880 @end quotation
882 Here we will focus on the simpler solution: one user config
883 file, including basic configuration plus any TCL procedures
884 to simplify your work.
886 @section User Config Files
887 @cindex config file, user
888 @cindex user config file
889 @cindex config file, overview
891 A user configuration file ties together all the parts of a project
892 in one place.
893 One of the following will match your situation best:
895 @itemize
896 @item Ideally almost everything comes from configuration files
897 provided by someone else.
898 For example, OpenOCD distributes a @file{scripts} directory
899 (probably in @file{/usr/share/openocd/scripts} on Linux).
900 Board and tool vendors can provide these too, as can individual
901 user sites; the @option{-s} command line option lets you say
902 where to find these files. (@xref{Running}.)
903 The AT91SAM7X256 example above works this way.
905 Three main types of non-user configuration file each have their
906 own subdirectory in the @file{scripts} directory:
908 @enumerate
909 @item @b{interface} -- one for each different debug adapter;
910 @item @b{board} -- one for each different board
911 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
912 @end enumerate
914 Best case: include just two files, and they handle everything else.
915 The first is an interface config file.
916 The second is board-specific, and it sets up the JTAG TAPs and
917 their GDB targets (by deferring to some @file{target.cfg} file),
918 declares all flash memory, and leaves you nothing to do except
919 meet your deadline:
921 @example
922 source [find interface/olimex-jtag-tiny.cfg]
923 source [find board/csb337.cfg]
924 @end example
926 Boards with a single microcontroller often won't need more
927 than the target config file, as in the AT91SAM7X256 example.
928 That's because there is no external memory (flash, DDR RAM), and
929 the board differences are encapsulated by application code.
931 @item Maybe you don't know yet what your board looks like to JTAG.
932 Once you know the @file{interface.cfg} file to use, you may
933 need help from OpenOCD to discover what's on the board.
934 Once you find the JTAG TAPs, you can just search for appropriate
935 target and board
936 configuration files ... or write your own, from the bottom up.
937 @xref{Autoprobing}.
939 @item You can often reuse some standard config files but
940 need to write a few new ones, probably a @file{board.cfg} file.
941 You will be using commands described later in this User's Guide,
942 and working with the guidelines in the next chapter.
944 For example, there may be configuration files for your JTAG adapter
945 and target chip, but you need a new board-specific config file
946 giving access to your particular flash chips.
947 Or you might need to write another target chip configuration file
948 for a new chip built around the Cortex M3 core.
950 @quotation Note
951 When you write new configuration files, please submit
952 them for inclusion in the next OpenOCD release.
953 For example, a @file{board/newboard.cfg} file will help the
954 next users of that board, and a @file{target/newcpu.cfg}
955 will help support users of any board using that chip.
956 @end quotation
958 @item
959 You may may need to write some C code.
960 It may be as simple as a supporting a new ft2232 or parport
961 based adapter; a bit more involved, like a NAND or NOR flash
962 controller driver; or a big piece of work like supporting
963 a new chip architecture.
964 @end itemize
966 Reuse the existing config files when you can.
967 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
968 You may find a board configuration that's a good example to follow.
970 When you write config files, separate the reusable parts
971 (things every user of that interface, chip, or board needs)
972 from ones specific to your environment and debugging approach.
973 @itemize
975 @item
976 For example, a @code{gdb-attach} event handler that invokes
977 the @command{reset init} command will interfere with debugging
978 early boot code, which performs some of the same actions
979 that the @code{reset-init} event handler does.
981 @item
982 Likewise, the @command{arm9 vector_catch} command (or
983 @cindex vector_catch
984 its siblings @command{xscale vector_catch}
985 and @command{cortex_m3 vector_catch}) can be a timesaver
986 during some debug sessions, but don't make everyone use that either.
987 Keep those kinds of debugging aids in your user config file,
988 along with messaging and tracing setup.
989 (@xref{Software Debug Messages and Tracing}.)
991 @item
992 You might need to override some defaults.
993 For example, you might need to move, shrink, or back up the target's
994 work area if your application needs much SRAM.
996 @item
997 TCP/IP port configuration is another example of something which
998 is environment-specific, and should only appear in
999 a user config file. @xref{TCP/IP Ports}.
1000 @end itemize
1002 @section Project-Specific Utilities
1004 A few project-specific utility
1005 routines may well speed up your work.
1006 Write them, and keep them in your project's user config file.
1008 For example, if you are making a boot loader work on a
1009 board, it's nice to be able to debug the ``after it's
1010 loaded to RAM'' parts separately from the finicky early
1011 code which sets up the DDR RAM controller and clocks.
1012 A script like this one, or a more GDB-aware sibling,
1013 may help:
1015 @example
1016 proc ramboot @{ @} @{
1017 # Reset, running the target's "reset-init" scripts
1018 # to initialize clocks and the DDR RAM controller.
1019 # Leave the CPU halted.
1020 reset init
1022 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1023 load_image u-boot.bin 0x20000000
1025 # Start running.
1026 resume 0x20000000
1027 @}
1028 @end example
1030 Then once that code is working you will need to make it
1031 boot from NOR flash; a different utility would help.
1032 Alternatively, some developers write to flash using GDB.
1033 (You might use a similar script if you're working with a flash
1034 based microcontroller application instead of a boot loader.)
1036 @example
1037 proc newboot @{ @} @{
1038 # Reset, leaving the CPU halted. The "reset-init" event
1039 # proc gives faster access to the CPU and to NOR flash;
1040 # "reset halt" would be slower.
1041 reset init
1043 # Write standard version of U-Boot into the first two
1044 # sectors of NOR flash ... the standard version should
1045 # do the same lowlevel init as "reset-init".
1046 flash protect 0 0 1 off
1047 flash erase_sector 0 0 1
1048 flash write_bank 0 u-boot.bin 0x0
1049 flash protect 0 0 1 on
1051 # Reboot from scratch using that new boot loader.
1052 reset run
1053 @}
1054 @end example
1056 You may need more complicated utility procedures when booting
1057 from NAND.
1058 That often involves an extra bootloader stage,
1059 running from on-chip SRAM to perform DDR RAM setup so it can load
1060 the main bootloader code (which won't fit into that SRAM).
1062 Other helper scripts might be used to write production system images,
1063 involving considerably more than just a three stage bootloader.
1065 @section Target Software Changes
1067 Sometimes you may want to make some small changes to the software
1068 you're developing, to help make JTAG debugging work better.
1069 For example, in C or assembly language code you might
1070 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1071 handling issues like:
1073 @itemize @bullet
1075 @item @b{Watchdog Timers}...
1076 Watchog timers are typically used to automatically reset systems if
1077 some application task doesn't periodically reset the timer. (The
1078 assumption is that the system has locked up if the task can't run.)
1079 When a JTAG debugger halts the system, that task won't be able to run
1080 and reset the timer ... potentially causing resets in the middle of
1081 your debug sessions.
1083 It's rarely a good idea to disable such watchdogs, since their usage
1084 needs to be debugged just like all other parts of your firmware.
1085 That might however be your only option.
1087 Look instead for chip-specific ways to stop the watchdog from counting
1088 while the system is in a debug halt state. It may be simplest to set
1089 that non-counting mode in your debugger startup scripts. You may however
1090 need a different approach when, for example, a motor could be physically
1091 damaged by firmware remaining inactive in a debug halt state. That might
1092 involve a type of firmware mode where that "non-counting" mode is disabled
1093 at the beginning then re-enabled at the end; a watchdog reset might fire
1094 and complicate the debug session, but hardware (or people) would be
1095 protected.@footnote{Note that many systems support a "monitor mode" debug
1096 that is a somewhat cleaner way to address such issues. You can think of
1097 it as only halting part of the system, maybe just one task,
1098 instead of the whole thing.
1099 At this writing, January 2010, OpenOCD based debugging does not support
1100 monitor mode debug, only "halt mode" debug.}
1102 @item @b{ARM Semihosting}...
1103 @cindex ARM semihosting
1104 When linked with a special runtime library provided with many
1105 toolchains@footnote{See chapter 8 "Semihosting" in
1106 @uref{,
1107 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1108 The CodeSourcery EABI toolchain also includes a semihosting library.},
1109 your target code can use I/O facilities on the debug host. That library
1110 provides a small set of system calls which are handled by OpenOCD.
1111 It can let the debugger provide your system console and a file system,
1112 helping with early debugging or providing a more capable environment
1113 for sometimes-complex tasks like installing system firmware onto
1114 NAND or SPI flash.
1116 @item @b{ARM Wait-For-Interrupt}...
1117 Many ARM chips synchronize the JTAG clock using the core clock.
1118 Low power states which stop that core clock thus prevent JTAG access.
1119 Idle loops in tasking environments often enter those low power states
1120 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1122 You may want to @emph{disable that instruction} in source code,
1123 or otherwise prevent using that state,
1124 to ensure you can get JTAG access at any time.@footnote{As a more
1125 polite alternative, some processors have special debug-oriented
1126 registers which can be used to change various features including
1127 how the low power states are clocked while debugging.
1128 The STM32 DBGMCU_CR register is an example; at the cost of extra
1129 power consumption, JTAG can be used during low power states.}
1130 For example, the OpenOCD @command{halt} command may not
1131 work for an idle processor otherwise.
1133 @item @b{Delay after reset}...
1134 Not all chips have good support for debugger access
1135 right after reset; many LPC2xxx chips have issues here.
1136 Similarly, applications that reconfigure pins used for
1137 JTAG access as they start will also block debugger access.
1139 To work with boards like this, @emph{enable a short delay loop}
1140 the first thing after reset, before "real" startup activities.
1141 For example, one second's delay is usually more than enough
1142 time for a JTAG debugger to attach, so that
1143 early code execution can be debugged
1144 or firmware can be replaced.
1146 @item @b{Debug Communications Channel (DCC)}...
1147 Some processors include mechanisms to send messages over JTAG.
1148 Many ARM cores support these, as do some cores from other vendors.
1149 (OpenOCD may be able to use this DCC internally, speeding up some
1150 operations like writing to memory.)
1152 Your application may want to deliver various debugging messages
1153 over JTAG, by @emph{linking with a small library of code}
1154 provided with OpenOCD and using the utilities there to send
1155 various kinds of message.
1156 @xref{Software Debug Messages and Tracing}.
1158 @end itemize
1160 @section Target Hardware Setup
1162 Chip vendors often provide software development boards which
1163 are highly configurable, so that they can support all options
1164 that product boards may require. @emph{Make sure that any
1165 jumpers or switches match the system configuration you are
1166 working with.}
1168 Common issues include:
1170 @itemize @bullet
1172 @item @b{JTAG setup} ...
1173 Boards may support more than one JTAG configuration.
1174 Examples include jumpers controlling pullups versus pulldowns
1175 on the nTRST and/or nSRST signals, and choice of connectors
1176 (e.g. which of two headers on the base board,
1177 or one from a daughtercard).
1178 For some Texas Instruments boards, you may need to jumper the
1179 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1181 @item @b{Boot Modes} ...
1182 Complex chips often support multiple boot modes, controlled
1183 by external jumpers. Make sure this is set up correctly.
1184 For example many i.MX boards from NXP need to be jumpered
1185 to "ATX mode" to start booting using the on-chip ROM, when
1186 using second stage bootloader code stored in a NAND flash chip.
1188 Such explicit configuration is common, and not limited to
1189 booting from NAND. You might also need to set jumpers to
1190 start booting using code loaded from an MMC/SD card; external
1191 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1192 flash; some external host; or various other sources.
1195 @item @b{Memory Addressing} ...
1196 Boards which support multiple boot modes may also have jumpers
1197 to configure memory addressing. One board, for example, jumpers
1198 external chipselect 0 (used for booting) to address either
1199 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1200 or NAND flash. When it's jumpered to address NAND flash, that
1201 board must also be told to start booting from on-chip ROM.
1203 Your @file{board.cfg} file may also need to be told this jumper
1204 configuration, so that it can know whether to declare NOR flash
1205 using @command{flash bank} or instead declare NAND flash with
1206 @command{nand device}; and likewise which probe to perform in
1207 its @code{reset-init} handler.
1209 A closely related issue is bus width. Jumpers might need to
1210 distinguish between 8 bit or 16 bit bus access for the flash
1211 used to start booting.
1213 @item @b{Peripheral Access} ...
1214 Development boards generally provide access to every peripheral
1215 on the chip, sometimes in multiple modes (such as by providing
1216 multiple audio codec chips).
1217 This interacts with software
1218 configuration of pin multiplexing, where for example a
1219 given pin may be routed either to the MMC/SD controller
1220 or the GPIO controller. It also often interacts with
1221 configuration jumpers. One jumper may be used to route
1222 signals to an MMC/SD card slot or an expansion bus (which
1223 might in turn affect booting); others might control which
1224 audio or video codecs are used.
1226 @end itemize
1228 Plus you should of course have @code{reset-init} event handlers
1229 which set up the hardware to match that jumper configuration.
1230 That includes in particular any oscillator or PLL used to clock
1231 the CPU, and any memory controllers needed to access external
1232 memory and peripherals. Without such handlers, you won't be
1233 able to access those resources without working target firmware
1234 which can do that setup ... this can be awkward when you're
1235 trying to debug that target firmware. Even if there's a ROM
1236 bootloader which handles a few issues, it rarely provides full
1237 access to all board-specific capabilities.
1240 @node Config File Guidelines
1241 @chapter Config File Guidelines
1243 This chapter is aimed at any user who needs to write a config file,
1244 including developers and integrators of OpenOCD and any user who
1245 needs to get a new board working smoothly.
1246 It provides guidelines for creating those files.
1248 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1249 with files including the ones listed here.
1250 Use them as-is where you can; or as models for new files.
1251 @itemize @bullet
1252 @item @file{interface} ...
1253 These are for debug adapters.
1254 Files that configure JTAG adapters go here.
1255 @example
1256 $ ls interface
1257 altera-usb-blaster.cfg hilscher_nxhx50_etm.cfg openrd.cfg
1258 arm-jtag-ew.cfg hilscher_nxhx50_re.cfg osbdm.cfg
1259 arm-usb-ocd.cfg hitex_str9-comstick.cfg parport.cfg
1260 at91rm9200.cfg icebear.cfg parport_dlc5.cfg
1261 axm0432.cfg jlink.cfg redbee-econotag.cfg
1262 busblaster.cfg jtagkey2.cfg redbee-usb.cfg
1263 buspirate.cfg jtagkey2p.cfg rlink.cfg
1264 calao-usb-a9260-c01.cfg jtagkey.cfg sheevaplug.cfg
1265 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg signalyzer.cfg
1266 calao-usb-a9260.cfg kt-link.cfg signalyzer-h2.cfg
1267 chameleon.cfg lisa-l.cfg signalyzer-h4.cfg
1268 cortino.cfg luminary.cfg signalyzer-lite.cfg
1269 digilent-hs1.cfg luminary-icdi.cfg stlink-v1.cfg
1270 dlp-usb1232h.cfg luminary-lm3s811.cfg stlink-v2.cfg
1271 dummy.cfg minimodule.cfg stm32-stick.cfg
1272 estick.cfg neodb.cfg turtelizer2.cfg
1273 flashlink.cfg ngxtech.cfg ulink.cfg
1274 flossjtag.cfg olimex-arm-usb-ocd.cfg usb-jtag.cfg
1275 flossjtag-noeeprom.cfg olimex-arm-usb-ocd-h.cfg usbprog.cfg
1276 flyswatter2.cfg olimex-arm-usb-tiny-h.cfg vpaclink.cfg
1277 flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
1278 hilscher_nxhx10_etm.cfg oocdlink.cfg xds100v2.cfg
1279 hilscher_nxhx500_etm.cfg opendous.cfg
1280 hilscher_nxhx500_re.cfg openocd-usb.cfg
1281 $
1282 @end example
1283 @item @file{board} ...
1284 think Circuit Board, PWA, PCB, they go by many names. Board files
1285 contain initialization items that are specific to a board.
1286 They reuse target configuration files, since the same
1287 microprocessor chips are used on many boards,
1288 but support for external parts varies widely. For
1289 example, the SDRAM initialization sequence for the board, or the type
1290 of external flash and what address it uses. Any initialization
1291 sequence to enable that external flash or SDRAM should be found in the
1292 board file. Boards may also contain multiple targets: two CPUs; or
1293 a CPU and an FPGA.
1294 @example
1295 $ ls board
1296 actux3.cfg logicpd_imx27.cfg
1297 am3517evm.cfg lubbock.cfg
1298 arm_evaluator7t.cfg mcb1700.cfg
1299 at91cap7a-stk-sdram.cfg microchip_explorer16.cfg
1300 at91eb40a.cfg mini2440.cfg
1301 at91rm9200-dk.cfg mini6410.cfg
1302 at91rm9200-ek.cfg olimex_LPC2378STK.cfg
1303 at91sam9261-ek.cfg olimex_lpc_h2148.cfg
1304 at91sam9263-ek.cfg olimex_sam7_ex256.cfg
1305 at91sam9g20-ek.cfg olimex_sam9_l9260.cfg
1306 atmel_at91sam7s-ek.cfg olimex_stm32_h103.cfg
1307 atmel_at91sam9260-ek.cfg olimex_stm32_h107.cfg
1308 atmel_at91sam9rl-ek.cfg olimex_stm32_p107.cfg
1309 atmel_sam3n_ek.cfg omap2420_h4.cfg
1310 atmel_sam3s_ek.cfg open-bldc.cfg
1311 atmel_sam3u_ek.cfg openrd.cfg
1312 atmel_sam3x_ek.cfg osk5912.cfg
1313 atmel_sam4s_ek.cfg phytec_lpc3250.cfg
1314 balloon3-cpu.cfg pic-p32mx.cfg
1315 colibri.cfg propox_mmnet1001.cfg
1316 crossbow_tech_imote2.cfg pxa255_sst.cfg
1317 csb337.cfg redbee.cfg
1318 csb732.cfg rsc-w910.cfg
1319 da850evm.cfg sheevaplug.cfg
1320 digi_connectcore_wi-9c.cfg smdk6410.cfg
1321 diolan_lpc4350-db1.cfg spear300evb.cfg
1322 dm355evm.cfg spear300evb_mod.cfg
1323 dm365evm.cfg spear310evb20.cfg
1324 dm6446evm.cfg spear310evb20_mod.cfg
1325 efikamx.cfg spear320cpu.cfg
1326 eir.cfg spear320cpu_mod.cfg
1327 ek-lm3s1968.cfg steval_pcc010.cfg
1328 ek-lm3s3748.cfg stm320518_eval_stlink.cfg
1329 ek-lm3s6965.cfg stm32100b_eval.cfg
1330 ek-lm3s811.cfg stm3210b_eval.cfg
1331 ek-lm3s811-revb.cfg stm3210c_eval.cfg
1332 ek-lm3s9b9x.cfg stm3210e_eval.cfg
1333 ek-lm4f232.cfg stm3220g_eval.cfg
1334 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1335 ethernut3.cfg stm3241g_eval.cfg
1336 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1337 hammer.cfg stm32f0discovery.cfg
1338 hilscher_nxdb500sys.cfg stm32f4discovery.cfg
1339 hilscher_nxeb500hmi.cfg stm32ldiscovery.cfg
1340 hilscher_nxhx10.cfg stm32vldiscovery.cfg
1341 hilscher_nxhx500.cfg str910-eval.cfg
1342 hilscher_nxhx50.cfg telo.cfg
1343 hilscher_nxsb100.cfg ti_beagleboard.cfg
1344 hitex_lpc2929.cfg ti_beagleboard_xm.cfg
1345 hitex_stm32-performancestick.cfg ti_beaglebone.cfg
1346 hitex_str9-comstick.cfg ti_blaze.cfg
1347 iar_lpc1768.cfg ti_pandaboard.cfg
1348 iar_str912_sk.cfg ti_pandaboard_es.cfg
1349 icnova_imx53_sodimm.cfg topas910.cfg
1350 icnova_sam9g45_sodimm.cfg topasa900.cfg
1351 imx27ads.cfg twr-k60n512.cfg
1352 imx27lnst.cfg tx25_stk5.cfg
1353 imx28evk.cfg tx27_stk5.cfg
1354 imx31pdk.cfg unknown_at91sam9260.cfg
1355 imx35pdk.cfg uptech_2410.cfg
1356 imx53loco.cfg verdex.cfg
1357 keil_mcb1700.cfg voipac.cfg
1358 keil_mcb2140.cfg voltcraft_dso-3062c.cfg
1359 kwikstik.cfg x300t.cfg
1360 linksys_nslu2.cfg zy1000.cfg
1361 lisa-l.cfg
1362 $
1363 @end example
1364 @item @file{target} ...
1365 think chip. The ``target'' directory represents the JTAG TAPs
1366 on a chip
1367 which OpenOCD should control, not a board. Two common types of targets
1368 are ARM chips and FPGA or CPLD chips.
1369 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1370 the target config file defines all of them.
1371 @example
1372 $ ls target
1373 $duc702x.cfg ixp42x.cfg
1374 am335x.cfg k40.cfg
1375 amdm37x.cfg k60.cfg
1376 ar71xx.cfg lpc1768.cfg
1377 at32ap7000.cfg lpc2103.cfg
1378 at91r40008.cfg lpc2124.cfg
1379 at91rm9200.cfg lpc2129.cfg
1380 at91sam3ax_4x.cfg lpc2148.cfg
1381 at91sam3ax_8x.cfg lpc2294.cfg
1382 at91sam3ax_xx.cfg lpc2378.cfg
1383 at91sam3nXX.cfg lpc2460.cfg
1384 at91sam3sXX.cfg lpc2478.cfg
1385 at91sam3u1c.cfg lpc2900.cfg
1386 at91sam3u1e.cfg lpc2xxx.cfg
1387 at91sam3u2c.cfg lpc3131.cfg
1388 at91sam3u2e.cfg lpc3250.cfg
1389 at91sam3u4c.cfg lpc4350.cfg
1390 at91sam3u4e.cfg mc13224v.cfg
1391 at91sam3uxx.cfg nuc910.cfg
1392 at91sam3XXX.cfg omap2420.cfg
1393 at91sam4sXX.cfg omap3530.cfg
1394 at91sam4XXX.cfg omap4430.cfg
1395 at91sam7se512.cfg omap4460.cfg
1396 at91sam7sx.cfg omap5912.cfg
1397 at91sam7x256.cfg omapl138.cfg
1398 at91sam7x512.cfg pic32mx.cfg
1399 at91sam9260.cfg pxa255.cfg
1400 at91sam9260_ext_RAM_ext_flash.cfg pxa270.cfg
1401 at91sam9261.cfg pxa3xx.cfg
1402 at91sam9263.cfg readme.txt
1403 at91sam9.cfg samsung_s3c2410.cfg
1404 at91sam9g10.cfg samsung_s3c2440.cfg
1405 at91sam9g20.cfg samsung_s3c2450.cfg
1406 at91sam9g45.cfg samsung_s3c4510.cfg
1407 at91sam9rl.cfg samsung_s3c6410.cfg
1408 atmega128.cfg sharp_lh79532.cfg
1409 avr32.cfg smp8634.cfg
1410 c100.cfg spear3xx.cfg
1411 c100config.tcl stellaris.cfg
1412 c100helper.tcl stm32.cfg
1413 c100regs.tcl stm32f0x_stlink.cfg
1414 cs351x.cfg stm32f1x.cfg
1415 davinci.cfg stm32f1x_stlink.cfg
1416 dragonite.cfg stm32f2x.cfg
1417 dsp56321.cfg stm32f2x_stlink.cfg
1418 dsp568013.cfg stm32f2xxx.cfg
1419 dsp568037.cfg stm32f4x.cfg
1420 epc9301.cfg stm32f4x_stlink.cfg
1421 faux.cfg stm32l.cfg
1422 feroceon.cfg stm32lx_stlink.cfg
1423 fm3.cfg stm32_stlink.cfg
1424 hilscher_netx10.cfg stm32xl.cfg
1425 hilscher_netx500.cfg str710.cfg
1426 hilscher_netx50.cfg str730.cfg
1427 icepick.cfg str750.cfg
1428 imx21.cfg str912.cfg
1429 imx25.cfg swj-dp.tcl
1430 imx27.cfg test_reset_syntax_error.cfg
1431 imx28.cfg test_syntax_error.cfg
1432 imx31.cfg ti_dm355.cfg
1433 imx35.cfg ti_dm365.cfg
1434 imx51.cfg ti_dm6446.cfg
1435 imx53.cfg tmpa900.cfg
1436 imx.cfg tmpa910.cfg
1437 is5114.cfg u8500.cfg
1438 @end example
1439 @item @emph{more} ... browse for other library files which may be useful.
1440 For example, there are various generic and CPU-specific utilities.
1441 @end itemize
1443 The @file{openocd.cfg} user config
1444 file may override features in any of the above files by
1445 setting variables before sourcing the target file, or by adding
1446 commands specific to their situation.
1448 @section Interface Config Files
1450 The user config file
1451 should be able to source one of these files with a command like this:
1453 @example
1454 source [find interface/FOOBAR.cfg]
1455 @end example
1457 A preconfigured interface file should exist for every debug adapter
1458 in use today with OpenOCD.
1459 That said, perhaps some of these config files
1460 have only been used by the developer who created it.
1462 A separate chapter gives information about how to set these up.
1463 @xref{Debug Adapter Configuration}.
1464 Read the OpenOCD source code (and Developer's Guide)
1465 if you have a new kind of hardware interface
1466 and need to provide a driver for it.
1468 @section Board Config Files
1469 @cindex config file, board
1470 @cindex board config file
1472 The user config file
1473 should be able to source one of these files with a command like this:
1475 @example
1476 source [find board/FOOBAR.cfg]
1477 @end example
1479 The point of a board config file is to package everything
1480 about a given board that user config files need to know.
1481 In summary the board files should contain (if present)
1483 @enumerate
1484 @item One or more @command{source [target/...cfg]} statements
1485 @item NOR flash configuration (@pxref{NOR Configuration})
1486 @item NAND flash configuration (@pxref{NAND Configuration})
1487 @item Target @code{reset} handlers for SDRAM and I/O configuration
1488 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1489 @item All things that are not ``inside a chip''
1490 @end enumerate
1492 Generic things inside target chips belong in target config files,
1493 not board config files. So for example a @code{reset-init} event
1494 handler should know board-specific oscillator and PLL parameters,
1495 which it passes to target-specific utility code.
1497 The most complex task of a board config file is creating such a
1498 @code{reset-init} event handler.
1499 Define those handlers last, after you verify the rest of the board
1500 configuration works.
1502 @subsection Communication Between Config files
1504 In addition to target-specific utility code, another way that
1505 board and target config files communicate is by following a
1506 convention on how to use certain variables.
1508 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1509 Thus the rule we follow in OpenOCD is this: Variables that begin with
1510 a leading underscore are temporary in nature, and can be modified and
1511 used at will within a target configuration file.
1513 Complex board config files can do the things like this,
1514 for a board with three chips:
1516 @example
1517 # Chip #1: PXA270 for network side, big endian
1518 set CHIPNAME network
1519 set ENDIAN big
1520 source [find target/pxa270.cfg]
1521 # on return: _TARGETNAME = network.cpu
1522 # other commands can refer to the "network.cpu" target.
1523 $_TARGETNAME configure .... events for this CPU..
1525 # Chip #2: PXA270 for video side, little endian
1526 set CHIPNAME video
1527 set ENDIAN little
1528 source [find target/pxa270.cfg]
1529 # on return: _TARGETNAME = video.cpu
1530 # other commands can refer to the "video.cpu" target.
1531 $_TARGETNAME configure .... events for this CPU..
1533 # Chip #3: Xilinx FPGA for glue logic
1534 set CHIPNAME xilinx
1535 unset ENDIAN
1536 source [find target/spartan3.cfg]
1537 @end example
1539 That example is oversimplified because it doesn't show any flash memory,
1540 or the @code{reset-init} event handlers to initialize external DRAM
1541 or (assuming it needs it) load a configuration into the FPGA.
1542 Such features are usually needed for low-level work with many boards,
1543 where ``low level'' implies that the board initialization software may
1544 not be working. (That's a common reason to need JTAG tools. Another
1545 is to enable working with microcontroller-based systems, which often
1546 have no debugging support except a JTAG connector.)
1548 Target config files may also export utility functions to board and user
1549 config files. Such functions should use name prefixes, to help avoid
1550 naming collisions.
1552 Board files could also accept input variables from user config files.
1553 For example, there might be a @code{J4_JUMPER} setting used to identify
1554 what kind of flash memory a development board is using, or how to set
1555 up other clocks and peripherals.
1557 @subsection Variable Naming Convention
1558 @cindex variable names
1560 Most boards have only one instance of a chip.
1561 However, it should be easy to create a board with more than
1562 one such chip (as shown above).
1563 Accordingly, we encourage these conventions for naming
1564 variables associated with different @file{target.cfg} files,
1565 to promote consistency and
1566 so that board files can override target defaults.
1568 Inputs to target config files include:
1570 @itemize @bullet
1571 @item @code{CHIPNAME} ...
1572 This gives a name to the overall chip, and is used as part of
1573 tap identifier dotted names.
1574 While the default is normally provided by the chip manufacturer,
1575 board files may need to distinguish between instances of a chip.
1576 @item @code{ENDIAN} ...
1577 By default @option{little} - although chips may hard-wire @option{big}.
1578 Chips that can't change endianness don't need to use this variable.
1579 @item @code{CPUTAPID} ...
1580 When OpenOCD examines the JTAG chain, it can be told verify the
1581 chips against the JTAG IDCODE register.
1582 The target file will hold one or more defaults, but sometimes the
1583 chip in a board will use a different ID (perhaps a newer revision).
1584 @end itemize
1586 Outputs from target config files include:
1588 @itemize @bullet
1589 @item @code{_TARGETNAME} ...
1590 By convention, this variable is created by the target configuration
1591 script. The board configuration file may make use of this variable to
1592 configure things like a ``reset init'' script, or other things
1593 specific to that board and that target.
1594 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1595 @code{_TARGETNAME1}, ... etc.
1596 @end itemize
1598 @subsection The reset-init Event Handler
1599 @cindex event, reset-init
1600 @cindex reset-init handler
1602 Board config files run in the OpenOCD configuration stage;
1603 they can't use TAPs or targets, since they haven't been
1604 fully set up yet.
1605 This means you can't write memory or access chip registers;
1606 you can't even verify that a flash chip is present.
1607 That's done later in event handlers, of which the target @code{reset-init}
1608 handler is one of the most important.
1610 Except on microcontrollers, the basic job of @code{reset-init} event
1611 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1612 Microcontrollers rarely use boot loaders; they run right out of their
1613 on-chip flash and SRAM memory. But they may want to use one of these
1614 handlers too, if just for developer convenience.
1616 @quotation Note
1617 Because this is so very board-specific, and chip-specific, no examples
1618 are included here.
1619 Instead, look at the board config files distributed with OpenOCD.
1620 If you have a boot loader, its source code will help; so will
1621 configuration files for other JTAG tools
1622 (@pxref{Translating Configuration Files}).
1623 @end quotation
1625 Some of this code could probably be shared between different boards.
1626 For example, setting up a DRAM controller often doesn't differ by
1627 much except the bus width (16 bits or 32?) and memory timings, so a
1628 reusable TCL procedure loaded by the @file{target.cfg} file might take
1629 those as parameters.
1630 Similarly with oscillator, PLL, and clock setup;
1631 and disabling the watchdog.
1632 Structure the code cleanly, and provide comments to help
1633 the next developer doing such work.
1634 (@emph{You might be that next person} trying to reuse init code!)
1636 The last thing normally done in a @code{reset-init} handler is probing
1637 whatever flash memory was configured. For most chips that needs to be
1638 done while the associated target is halted, either because JTAG memory
1639 access uses the CPU or to prevent conflicting CPU access.
1641 @subsection JTAG Clock Rate
1643 Before your @code{reset-init} handler has set up
1644 the PLLs and clocking, you may need to run with
1645 a low JTAG clock rate.
1646 @xref{JTAG Speed}.
1647 Then you'd increase that rate after your handler has
1648 made it possible to use the faster JTAG clock.
1649 When the initial low speed is board-specific, for example
1650 because it depends on a board-specific oscillator speed, then
1651 you should probably set it up in the board config file;
1652 if it's target-specific, it belongs in the target config file.
1654 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1655 @uref{} gives details.}
1656 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1657 Consult chip documentation to determine the peak JTAG clock rate,
1658 which might be less than that.
1660 @quotation Warning
1661 On most ARMs, JTAG clock detection is coupled to the core clock, so
1662 software using a @option{wait for interrupt} operation blocks JTAG access.
1663 Adaptive clocking provides a partial workaround, but a more complete
1664 solution just avoids using that instruction with JTAG debuggers.
1665 @end quotation
1667 If both the chip and the board support adaptive clocking,
1668 use the @command{jtag_rclk}
1669 command, in case your board is used with JTAG adapter which
1670 also supports it. Otherwise use @command{adapter_khz}.
1671 Set the slow rate at the beginning of the reset sequence,
1672 and the faster rate as soon as the clocks are at full speed.
1674 @anchor{The init_board procedure}
1675 @subsection The init_board procedure
1676 @cindex init_board procedure
1678 The concept of @code{init_board} procedure is very similar to @code{init_targets} (@xref{The init_targets procedure}.)
1679 - it's a replacement of ``linear'' configuration scripts. This procedure is meant to be executed when OpenOCD enters run
1680 stage (@xref{Entering the Run Stage},) after @code{init_targets}. The idea to have spearate @code{init_targets} and
1681 @code{init_board} procedures is to allow the first one to configure everything target specific (internal flash,
1682 internal RAM, etc.) and the second one to configure everything board specific (reset signals, chip frequency,
1683 reset-init event handler, external memory, etc.). Additionally ``linear'' board config file will most likely fail when
1684 target config file uses @code{init_targets} scheme (``linear'' script is executed before @code{init} and
1685 @code{init_targets} - after), so separating these two configuration stages is very convenient, as the easiest way to
1686 overcome this problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1687 need to override @code{init_targets} defined in target config files when they only need to to add some specifics.
1689 Just as @code{init_targets}, the @code{init_board} procedure can be overriden by ``next level'' script (which sources
1690 the original), allowing greater code reuse.
1692 @example
1693 ### board_file.cfg ###
1695 # source target file that does most of the config in init_targets
1696 source [find target/target.cfg]
1698 proc enable_fast_clock @{@} @{
1699 # enables fast on-board clock source
1700 # configures the chip to use it
1701 @}
1703 # initialize only board specifics - reset, clock, adapter frequency
1704 proc init_board @{@} @{
1705 reset_config trst_and_srst trst_pulls_srst
1707 $_TARGETNAME configure -event reset-init @{
1708 adapter_khz 1
1709 enable_fast_clock
1710 adapter_khz 10000
1711 @}
1712 @}
1713 @end example
1715 @section Target Config Files
1716 @cindex config file, target
1717 @cindex target config file
1719 Board config files communicate with target config files using
1720 naming conventions as described above, and may source one or
1721 more target config files like this:
1723 @example
1724 source [find target/FOOBAR.cfg]
1725 @end example
1727 The point of a target config file is to package everything
1728 about a given chip that board config files need to know.
1729 In summary the target files should contain
1731 @enumerate
1732 @item Set defaults
1733 @item Add TAPs to the scan chain
1734 @item Add CPU targets (includes GDB support)
1735 @item CPU/Chip/CPU-Core specific features
1736 @item On-Chip flash
1737 @end enumerate
1739 As a rule of thumb, a target file sets up only one chip.
1740 For a microcontroller, that will often include a single TAP,
1741 which is a CPU needing a GDB target, and its on-chip flash.
1743 More complex chips may include multiple TAPs, and the target
1744 config file may need to define them all before OpenOCD
1745 can talk to the chip.
1746 For example, some phone chips have JTAG scan chains that include
1747 an ARM core for operating system use, a DSP,
1748 another ARM core embedded in an image processing engine,
1749 and other processing engines.
1751 @subsection Default Value Boiler Plate Code
1753 All target configuration files should start with code like this,
1754 letting board config files express environment-specific
1755 differences in how things should be set up.
1757 @example
1758 # Boards may override chip names, perhaps based on role,
1759 # but the default should match what the vendor uses
1760 if @{ [info exists CHIPNAME] @} @{
1762 @} else @{
1763 set _CHIPNAME sam7x256
1764 @}
1766 # ONLY use ENDIAN with targets that can change it.
1767 if @{ [info exists ENDIAN] @} @{
1768 set _ENDIAN $ENDIAN
1769 @} else @{
1770 set _ENDIAN little
1771 @}
1773 # TAP identifiers may change as chips mature, for example with
1774 # new revision fields (the "3" here). Pick a good default; you
1775 # can pass several such identifiers to the "jtag newtap" command.
1776 if @{ [info exists CPUTAPID ] @} @{
1778 @} else @{
1779 set _CPUTAPID 0x3f0f0f0f
1780 @}
1781 @end example
1782 @c but 0x3f0f0f0f is for an str73x part ...
1784 @emph{Remember:} Board config files may include multiple target
1785 config files, or the same target file multiple times
1786 (changing at least @code{CHIPNAME}).
1788 Likewise, the target configuration file should define
1789 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1790 use it later on when defining debug targets:
1792 @example
1794 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1795 @end example
1797 @subsection Adding TAPs to the Scan Chain
1798 After the ``defaults'' are set up,
1799 add the TAPs on each chip to the JTAG scan chain.
1800 @xref{TAP Declaration}, and the naming convention
1801 for taps.
1803 In the simplest case the chip has only one TAP,
1804 probably for a CPU or FPGA.
1805 The config file for the Atmel AT91SAM7X256
1806 looks (in part) like this:
1808 @example
1809 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1810 @end example
1812 A board with two such at91sam7 chips would be able
1813 to source such a config file twice, with different
1814 values for @code{CHIPNAME}, so
1815 it adds a different TAP each time.
1817 If there are nonzero @option{-expected-id} values,
1818 OpenOCD attempts to verify the actual tap id against those values.
1819 It will issue error messages if there is mismatch, which
1820 can help to pinpoint problems in OpenOCD configurations.
1822 @example
1823 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1824 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1825 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1826 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1827 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1828 @end example
1830 There are more complex examples too, with chips that have
1831 multiple TAPs. Ones worth looking at include:
1833 @itemize
1834 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1835 plus a JRC to enable them
1836 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1837 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1838 is not currently used)
1839 @end itemize
1841 @subsection Add CPU targets
1843 After adding a TAP for a CPU, you should set it up so that
1844 GDB and other commands can use it.
1845 @xref{CPU Configuration}.
1846 For the at91sam7 example above, the command can look like this;
1847 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1848 to little endian, and this chip doesn't support changing that.
1850 @example
1852 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1853 @end example
1855 Work areas are small RAM areas associated with CPU targets.
1856 They are used by OpenOCD to speed up downloads,
1857 and to download small snippets of code to program flash chips.
1858 If the chip includes a form of ``on-chip-ram'' - and many do - define
1859 a work area if you can.
1860 Again using the at91sam7 as an example, this can look like:
1862 @example
1863 $_TARGETNAME configure -work-area-phys 0x00200000 \
1864 -work-area-size 0x4000 -work-area-backup 0
1865 @end example
1867 @anchor{Define CPU targets working in SMP}
1868 @subsection Define CPU targets working in SMP
1869 @cindex SMP
1870 After setting targets, you can define a list of targets working in SMP.
1872 @example
1873 set _TARGETNAME_1 $_CHIPNAME.cpu1
1874 set _TARGETNAME_2 $_CHIPNAME.cpu2
1875 target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap \
1876 -coreid 0 -dbgbase $_DAP_DBG1
1877 target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap \
1878 -coreid 1 -dbgbase $_DAP_DBG2
1879 #define 2 targets working in smp.
1880 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1881 @end example
1882 In the above example on cortex_a8, 2 cpus are working in SMP.
1883 In SMP only one GDB instance is created and :
1884 @itemize @bullet
1885 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1886 @item halt command triggers the halt of all targets in the list.
1887 @item resume command triggers the write context and the restart of all targets in the list.
1888 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1889 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1890 displayed by the GDB session @pxref{Using openocd SMP with GDB}.
1891 @end itemize
1893 The SMP behaviour can be disabled/enabled dynamically. On cortex_a8 following
1894 command have been implemented.
1895 @itemize @bullet
1896 @item cortex_a8 smp_on : enable SMP mode, behaviour is as described above.
1897 @item cortex_a8 smp_off : disable SMP mode, the current target is the one
1898 displayed in the GDB session, only this target is now controlled by GDB
1899 session. This behaviour is useful during system boot up.
1900 @item cortex_a8 smp_gdb : display/fix the core id displayed in GDB session see
1901 following example.
1902 @end itemize
1904 @example
1905 >cortex_a8 smp_gdb
1906 gdb coreid 0 -> -1
1907 #0 : coreid 0 is displayed to GDB ,
1908 #-> -1 : next resume triggers a real resume
1909 > cortex_a8 smp_gdb 1
1910 gdb coreid 0 -> 1
1911 #0 :coreid 0 is displayed to GDB ,
1912 #->1 : next resume displays coreid 1 to GDB
1913 > resume
1914 > cortex_a8 smp_gdb
1915 gdb coreid 1 -> 1
1916 #1 :coreid 1 is displayed to GDB ,
1917 #->1 : next resume displays coreid 1 to GDB
1918 > cortex_a8 smp_gdb -1
1919 gdb coreid 1 -> -1
1920 #1 :coreid 1 is displayed to GDB,
1921 #->-1 : next resume triggers a real resume
1922 @end example
1925 @subsection Chip Reset Setup
1927 As a rule, you should put the @command{reset_config} command
1928 into the board file. Most things you think you know about a
1929 chip can be tweaked by the board.
1931 Some chips have specific ways the TRST and SRST signals are
1932 managed. In the unusual case that these are @emph{chip specific}
1933 and can never be changed by board wiring, they could go here.
1934 For example, some chips can't support JTAG debugging without
1935 both signals.
1937 Provide a @code{reset-assert} event handler if you can.
1938 Such a handler uses JTAG operations to reset the target,
1939 letting this target config be used in systems which don't
1940 provide the optional SRST signal, or on systems where you
1941 don't want to reset all targets at once.
1942 Such a handler might write to chip registers to force a reset,
1943 use a JRC to do that (preferable -- the target may be wedged!),
1944 or force a watchdog timer to trigger.
1945 (For Cortex-M3 targets, this is not necessary. The target
1946 driver knows how to use trigger an NVIC reset when SRST is
1947 not available.)
1949 Some chips need special attention during reset handling if
1950 they're going to be used with JTAG.
1951 An example might be needing to send some commands right
1952 after the target's TAP has been reset, providing a
1953 @code{reset-deassert-post} event handler that writes a chip
1954 register to report that JTAG debugging is being done.
1955 Another would be reconfiguring the watchdog so that it stops
1956 counting while the core is halted in the debugger.
1958 JTAG clocking constraints often change during reset, and in
1959 some cases target config files (rather than board config files)
1960 are the right places to handle some of those issues.
1961 For example, immediately after reset most chips run using a
1962 slower clock than they will use later.
1963 That means that after reset (and potentially, as OpenOCD
1964 first starts up) they must use a slower JTAG clock rate
1965 than they will use later.
1966 @xref{JTAG Speed}.
1968 @quotation Important
1969 When you are debugging code that runs right after chip
1970 reset, getting these issues right is critical.
1971 In particular, if you see intermittent failures when
1972 OpenOCD verifies the scan chain after reset,
1973 look at how you are setting up JTAG clocking.
1974 @end quotation
1976 @anchor{The init_targets procedure}
1977 @subsection The init_targets procedure
1978 @cindex init_targets procedure
1980 Target config files can either be ``linear'' (script executed line-by-line when parsed in configuration stage,
1981 @xref{Configuration Stage},) or they can contain a special procedure called @code{init_targets}, which will be executed
1982 when entering run stage (after parsing all config files or after @code{init} command, @xref{Entering the Run Stage}.)
1983 Such procedure can be overriden by ``next level'' script (which sources the original). This concept faciliates code
1984 reuse when basic target config files provide generic configuration procedures and @code{init_targets} procedure, which
1985 can then be sourced and enchanced or changed in a ``more specific'' target config file. This is not possible with
1986 ``linear'' config scripts, because sourcing them executes every initialization commands they provide.
1988 @example
1989 ### generic_file.cfg ###
1991 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1992 # basic initialization procedure ...
1993 @}
1995 proc init_targets @{@} @{
1996 # initializes generic chip with 4kB of flash and 1kB of RAM
1997 setup_my_chip MY_GENERIC_CHIP 4096 1024
1998 @}
2000 ### specific_file.cfg ###
2002 source [find target/generic_file.cfg]
2004 proc init_targets @{@} @{
2005 # initializes specific chip with 128kB of flash and 64kB of RAM
2006 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
2007 @}
2008 @end example
2010 The easiest way to convert ``linear'' config files to @code{init_targets} version is to enclose every line of ``code''
2011 (i.e. not @code{source} commands, procedures, etc.) in this procedure.
2013 For an example of this scheme see LPC2000 target config files.
2015 The @code{init_boards} procedure is a similar concept concerning board config files (@xref{The init_board procedure}.)
2017 @subsection ARM Core Specific Hacks
2019 If the chip has a DCC, enable it. If the chip is an ARM9 with some
2020 special high speed download features - enable it.
2022 If present, the MMU, the MPU and the CACHE should be disabled.
2024 Some ARM cores are equipped with trace support, which permits
2025 examination of the instruction and data bus activity. Trace
2026 activity is controlled through an ``Embedded Trace Module'' (ETM)
2027 on one of the core's scan chains. The ETM emits voluminous data
2028 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
2029 If you are using an external trace port,
2030 configure it in your board config file.
2031 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2032 configure it in your target config file.
2034 @example
2035 etm config $_TARGETNAME 16 normal full etb
2036 etb config $_TARGETNAME $_CHIPNAME.etb
2037 @end example
2039 @subsection Internal Flash Configuration
2041 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2043 @b{Never ever} in the ``target configuration file'' define any type of
2044 flash that is external to the chip. (For example a BOOT flash on
2045 Chip Select 0.) Such flash information goes in a board file - not
2046 the TARGET (chip) file.
2048 Examples:
2049 @itemize @bullet
2050 @item at91sam7x256 - has 256K flash YES enable it.
2051 @item str912 - has flash internal YES enable it.
2052 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2053 @item pxa270 - again - CS0 flash - it goes in the board file.
2054 @end itemize
2056 @anchor{Translating Configuration Files}
2057 @section Translating Configuration Files
2058 @cindex translation
2059 If you have a configuration file for another hardware debugger
2060 or toolset (Abatron, BDI2000, BDI3000, CCS,
2061 Lauterbach, Segger, Macraigor, etc.), translating
2062 it into OpenOCD syntax is often quite straightforward. The most tricky
2063 part of creating a configuration script is oftentimes the reset init
2064 sequence where e.g. PLLs, DRAM and the like is set up.
2066 One trick that you can use when translating is to write small
2067 Tcl procedures to translate the syntax into OpenOCD syntax. This
2068 can avoid manual translation errors and make it easier to
2069 convert other scripts later on.
2071 Example of transforming quirky arguments to a simple search and
2072 replace job:
2074 @example
2075 # Lauterbach syntax(?)
2076 #
2077 # Data.Set c15:0x042f %long 0x40000015
2078 #
2079 # OpenOCD syntax when using procedure below.
2080 #
2081 # setc15 0x01 0x00050078
2083 proc setc15 @{regs value@} @{
2084 global TARGETNAME
2086 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2088 arm mcr 15 [expr ($regs>>12)&0x7] \
2089 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2090 [expr ($regs>>8)&0x7] $value
2091 @}
2092 @end example
2096 @node Daemon Configuration
2097 @chapter Daemon Configuration
2098 @cindex initialization
2099 The commands here are commonly found in the openocd.cfg file and are
2100 used to specify what TCP/IP ports are used, and how GDB should be
2101 supported.
2103 @anchor{Configuration Stage}
2104 @section Configuration Stage
2105 @cindex configuration stage
2106 @cindex config command
2108 When the OpenOCD server process starts up, it enters a
2109 @emph{configuration stage} which is the only time that
2110 certain commands, @emph{configuration commands}, may be issued.
2111 Normally, configuration commands are only available
2112 inside startup scripts.
2114 In this manual, the definition of a configuration command is
2115 presented as a @emph{Config Command}, not as a @emph{Command}
2116 which may be issued interactively.
2117 The runtime @command{help} command also highlights configuration
2118 commands, and those which may be issued at any time.
2120 Those configuration commands include declaration of TAPs,
2121 flash banks,
2122 the interface used for JTAG communication,
2123 and other basic setup.
2124 The server must leave the configuration stage before it
2125 may access or activate TAPs.
2126 After it leaves this stage, configuration commands may no
2127 longer be issued.
2129 @anchor{Entering the Run Stage}
2130 @section Entering the Run Stage
2132 The first thing OpenOCD does after leaving the configuration
2133 stage is to verify that it can talk to the scan chain
2134 (list of TAPs) which has been configured.
2135 It will warn if it doesn't find TAPs it expects to find,
2136 or finds TAPs that aren't supposed to be there.
2137 You should see no errors at this point.
2138 If you see errors, resolve them by correcting the
2139 commands you used to configure the server.
2140 Common errors include using an initial JTAG speed that's too
2141 fast, and not providing the right IDCODE values for the TAPs
2142 on the scan chain.
2144 Once OpenOCD has entered the run stage, a number of commands
2145 become available.
2146 A number of these relate to the debug targets you may have declared.
2147 For example, the @command{mww} command will not be available until
2148 a target has been successfuly instantiated.
2149 If you want to use those commands, you may need to force
2150 entry to the run stage.
2152 @deffn {Config Command} init
2153 This command terminates the configuration stage and
2154 enters the run stage. This helps when you need to have
2155 the startup scripts manage tasks such as resetting the target,
2156 programming flash, etc. To reset the CPU upon startup, add "init" and
2157 "reset" at the end of the config script or at the end of the OpenOCD
2158 command line using the @option{-c} command line switch.
2160 If this command does not appear in any startup/configuration file
2161 OpenOCD executes the command for you after processing all
2162 configuration files and/or command line options.
2164 @b{NOTE:} This command normally occurs at or near the end of your
2165 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2166 targets ready. For example: If your openocd.cfg file needs to
2167 read/write memory on your target, @command{init} must occur before
2168 the memory read/write commands. This includes @command{nand probe}.
2169 @end deffn
2171 @deffn {Overridable Procedure} jtag_init
2172 This is invoked at server startup to verify that it can talk
2173 to the scan chain (list of TAPs) which has been configured.
2175 The default implementation first tries @command{jtag arp_init},
2176 which uses only a lightweight JTAG reset before examining the
2177 scan chain.
2178 If that fails, it tries again, using a harder reset
2179 from the overridable procedure @command{init_reset}.
2181 Implementations must have verified the JTAG scan chain before
2182 they return.
2183 This is done by calling @command{jtag arp_init}
2184 (or @command{jtag arp_init-reset}).
2185 @end deffn
2187 @anchor{TCP/IP Ports}
2188 @section TCP/IP Ports
2189 @cindex TCP port
2190 @cindex server
2191 @cindex port
2192 @cindex security
2193 The OpenOCD server accepts remote commands in several syntaxes.
2194 Each syntax uses a different TCP/IP port, which you may specify
2195 only during configuration (before those ports are opened).
2197 For reasons including security, you may wish to prevent remote
2198 access using one or more of these ports.
2199 In such cases, just specify the relevant port number as zero.
2200 If you disable all access through TCP/IP, you will need to
2201 use the command line @option{-pipe} option.
2203 @deffn {Command} gdb_port [number]
2204 @cindex GDB server
2205 Normally gdb listens to a TCP/IP port, but GDB can also
2206 communicate via pipes(stdin/out or named pipes). The name
2207 "gdb_port" stuck because it covers probably more than 90% of
2208 the normal use cases.
2210 No arguments reports GDB port. "pipe" means listen to stdin
2211 output to stdout, an integer is base port number, "disable"
2212 disables the gdb server.
2214 When using "pipe", also use log_output to redirect the log
2215 output to a file so as not to flood the stdin/out pipes.
2217 The -p/--pipe option is deprecated and a warning is printed
2218 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2220 Any other string is interpreted as named pipe to listen to.
2221 Output pipe is the same name as input pipe, but with 'o' appended,
2222 e.g. /var/gdb, /var/gdbo.
2224 The GDB port for the first target will be the base port, the
2225 second target will listen on gdb_port + 1, and so on.
2226 When not specified during the configuration stage,
2227 the port @var{number} defaults to 3333.
2228 @end deffn
2230 @deffn {Command} tcl_port [number]
2231 Specify or query the port used for a simplified RPC
2232 connection that can be used by clients to issue TCL commands and get the
2233 output from the Tcl engine.
2234 Intended as a machine interface.
2235 When not specified during the configuration stage,
2236 the port @var{number} defaults to 6666.
2238 @end deffn
2240 @deffn {Command} telnet_port [number]
2241 Specify or query the
2242 port on which to listen for incoming telnet connections.
2243 This port is intended for interaction with one human through TCL commands.
2244 When not specified during the configuration stage,
2245 the port @var{number} defaults to 4444.
2246 When specified as zero, this port is not activated.
2247 @end deffn
2249 @anchor{GDB Configuration}
2250 @section GDB Configuration
2251 @cindex GDB
2252 @cindex GDB configuration
2253 You can reconfigure some GDB behaviors if needed.
2254 The ones listed here are static and global.
2255 @xref{Target Configuration}, about configuring individual targets.
2256 @xref{Target Events}, about configuring target-specific event handling.
2258 @anchor{gdb_breakpoint_override}
2259 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2260 Force breakpoint type for gdb @command{break} commands.
2261 This option supports GDB GUIs which don't
2262 distinguish hard versus soft breakpoints, if the default OpenOCD and
2263 GDB behaviour is not sufficient. GDB normally uses hardware
2264 breakpoints if the memory map has been set up for flash regions.
2265 @end deffn
2267 @anchor{gdb_flash_program}
2268 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2269 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2270 vFlash packet is received.
2271 The default behaviour is @option{enable}.
2272 @end deffn
2274 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2275 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2276 requested. GDB will then know when to set hardware breakpoints, and program flash
2277 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2278 for flash programming to work.
2279 Default behaviour is @option{enable}.
2280 @xref{gdb_flash_program}.
2281 @end deffn
2283 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2284 Specifies whether data aborts cause an error to be reported
2285 by GDB memory read packets.
2286 The default behaviour is @option{disable};
2287 use @option{enable} see these errors reported.
2288 @end deffn
2290 @anchor{Event Polling}
2291 @section Event Polling
2293 Hardware debuggers are parts of asynchronous systems,
2294 where significant events can happen at any time.
2295 The OpenOCD server needs to detect some of these events,
2296 so it can report them to through TCL command line
2297 or to GDB.
2299 Examples of such events include:
2301 @itemize
2302 @item One of the targets can stop running ... maybe it triggers
2303 a code breakpoint or data watchpoint, or halts itself.
2304 @item Messages may be sent over ``debug message'' channels ... many
2305 targets support such messages sent over JTAG,
2306 for receipt by the person debugging or tools.
2307 @item Loss of power ... some adapters can detect these events.
2308 @item Resets not issued through JTAG ... such reset sources
2309 can include button presses or other system hardware, sometimes
2310 including the target itself (perhaps through a watchdog).
2311 @item Debug instrumentation sometimes supports event triggering
2312 such as ``trace buffer full'' (so it can quickly be emptied)
2313 or other signals (to correlate with code behavior).
2314 @end itemize
2316 None of those events are signaled through standard JTAG signals.
2317 However, most conventions for JTAG connectors include voltage
2318 level and system reset (SRST) signal detection.
2319 Some connectors also include instrumentation signals, which
2320 can imply events when those signals are inputs.
2322 In general, OpenOCD needs to periodically check for those events,
2323 either by looking at the status of signals on the JTAG connector
2324 or by sending synchronous ``tell me your status'' JTAG requests
2325 to the various active targets.
2326 There is a command to manage and monitor that polling,
2327 which is normally done in the background.
2329 @deffn Command poll [@option{on}|@option{off}]
2330 Poll the current target for its current state.
2331 (Also, @pxref{target curstate}.)
2332 If that target is in debug mode, architecture
2333 specific information about the current state is printed.
2334 An optional parameter
2335 allows background polling to be enabled and disabled.
2337 You could use this from the TCL command shell, or
2338 from GDB using @command{monitor poll} command.
2339 Leave background polling enabled while you're using GDB.
2340 @example
2341 > poll
2342 background polling: on
2343 target state: halted
2344 target halted in ARM state due to debug-request, \
2345 current mode: Supervisor
2346 cpsr: 0x800000d3 pc: 0x11081bfc
2347 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2348 >
2349 @end example
2350 @end deffn
2352 @node Debug Adapter Configuration
2353 @chapter Debug Adapter Configuration
2354 @cindex config file, interface
2355 @cindex interface config file
2357 Correctly installing OpenOCD includes making your operating system give
2358 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2359 are used to select which one is used, and to configure how it is used.
2361 @quotation Note
2362 Because OpenOCD started out with a focus purely on JTAG, you may find
2363 places where it wrongly presumes JTAG is the only transport protocol
2364 in use. Be aware that recent versions of OpenOCD are removing that
2365 limitation. JTAG remains more functional than most other transports.
2366 Other transports do not support boundary scan operations, or may be
2367 specific to a given chip vendor. Some might be usable only for
2368 programming flash memory, instead of also for debugging.
2369 @end quotation
2371 Debug Adapters/Interfaces/Dongles are normally configured
2372 through commands in an interface configuration
2373 file which is sourced by your @file{openocd.cfg} file, or
2374 through a command line @option{-f interface/....cfg} option.
2376 @example
2377 source [find interface/olimex-jtag-tiny.cfg]
2378 @end example
2380 These commands tell
2381 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2382 A few cases are so simple that you only need to say what driver to use:
2384 @example
2385 # jlink interface
2386 interface jlink
2387 @end example
2389 Most adapters need a bit more configuration than that.
2392 @section Interface Configuration
2394 The interface command tells OpenOCD what type of debug adapter you are
2395 using. Depending on the type of adapter, you may need to use one or
2396 more additional commands to further identify or configure the adapter.
2398 @deffn {Config Command} {interface} name
2399 Use the interface driver @var{name} to connect to the
2400 target.
2401 @end deffn
2403 @deffn Command {interface_list}
2404 List the debug adapter drivers that have been built into
2405 the running copy of OpenOCD.
2406 @end deffn
2407 @deffn Command {interface transports} transport_name+
2408 Specifies the transports supported by this debug adapter.
2409 The adapter driver builds-in similar knowledge; use this only
2410 when external configuration (such as jumpering) changes what
2411 the hardware can support.
2412 @end deffn
2416 @deffn Command {adapter_name}
2417 Returns the name of the debug adapter driver being used.
2418 @end deffn
2420 @section Interface Drivers
2422 Each of the interface drivers listed here must be explicitly
2423 enabled when OpenOCD is configured, in order to be made
2424 available at run time.
2426 @deffn {Interface Driver} {amt_jtagaccel}
2427 Amontec Chameleon in its JTAG Accelerator configuration,
2428 connected to a PC's EPP mode parallel port.
2429 This defines some driver-specific commands:
2431 @deffn {Config Command} {parport_port} number
2432 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2433 the number of the @file{/dev/parport} device.
2434 @end deffn
2436 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2437 Displays status of RTCK option.
2438 Optionally sets that option first.
2439 @end deffn
2440 @end deffn
2442 @deffn {Interface Driver} {arm-jtag-ew}
2443 Olimex ARM-JTAG-EW USB adapter
2444 This has one driver-specific command:
2446 @deffn Command {armjtagew_info}
2447 Logs some status
2448 @end deffn
2449 @end deffn
2451 @deffn {Interface Driver} {at91rm9200}
2452 Supports bitbanged JTAG from the local system,
2453 presuming that system is an Atmel AT91rm9200
2454 and a specific set of GPIOs is used.
2455 @c command: at91rm9200_device NAME
2456 @c chooses among list of bit configs ... only one option
2457 @end deffn
2459 @deffn {Interface Driver} {dummy}
2460 A dummy software-only driver for debugging.
2461 @end deffn
2463 @deffn {Interface Driver} {ep93xx}
2464 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2465 @end deffn
2467 @deffn {Interface Driver} {ft2232}
2468 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2470 Note that this driver has several flaws and the @command{ftdi} driver is
2471 recommended as its replacement.
2473 These interfaces have several commands, used to configure the driver
2474 before initializing the JTAG scan chain:
2476 @deffn {Config Command} {ft2232_device_desc} description
2477 Provides the USB device description (the @emph{iProduct string})
2478 of the FTDI FT2232 device. If not
2479 specified, the FTDI default value is used. This setting is only valid
2480 if compiled with FTD2XX support.
2481 @end deffn
2483 @deffn {Config Command} {ft2232_serial} serial-number
2484 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2485 in case the vendor provides unique IDs and more than one FT2232 device
2486 is connected to the host.
2487 If not specified, serial numbers are not considered.
2488 (Note that USB serial numbers can be arbitrary Unicode strings,
2489 and are not restricted to containing only decimal digits.)
2490 @end deffn
2492 @deffn {Config Command} {ft2232_layout} name
2493 Each vendor's FT2232 device can use different GPIO signals
2494 to control output-enables, reset signals, and LEDs.
2495 Currently valid layout @var{name} values include:
2496 @itemize @minus
2497 @item @b{axm0432_jtag} Axiom AXM-0432
2498 @item @b{comstick} Hitex STR9 comstick
2499 @item @b{cortino} Hitex Cortino JTAG interface
2500 @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
2501 either for the local Cortex-M3 (SRST only)
2502 or in a passthrough mode (neither SRST nor TRST)
2503 This layout can not support the SWO trace mechanism, and should be
2504 used only for older boards (before rev C).
2505 @item @b{luminary_icdi} This layout should be used with most TI/Luminary
2506 eval boards, including Rev C LM3S811 eval boards and the eponymous
2507 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2508 to debug some other target. It can support the SWO trace mechanism.
2509 @item @b{flyswatter} Tin Can Tools Flyswatter
2510 @item @b{icebear} ICEbear JTAG adapter from Section 5
2511 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2512 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2513 @item @b{m5960} American Microsystems M5960
2514 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2515 @item @b{oocdlink} OOCDLink
2516 @c oocdlink ~= jtagkey_prototype_v1
2517 @item @b{redbee-econotag} Integrated with a Redbee development board.
2518 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2519 @item @b{sheevaplug} Marvell Sheevaplug development kit
2520 @item @b{signalyzer} Xverve Signalyzer
2521 @item @b{stm32stick} Hitex STM32 Performance Stick
2522 @item @b{turtelizer2} egnite Software turtelizer2
2523 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2524 @end itemize
2525 @end deffn
2527 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2528 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2529 default values are used.
2530 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2531 @example
2532 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2533 @end example
2534 @end deffn
2536 @deffn {Config Command} {ft2232_latency} ms
2537 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2538 ft2232_read() fails to return the expected number of bytes. This can be caused by
2539 USB communication delays and has proved hard to reproduce and debug. Setting the
2540 FT2232 latency timer to a larger value increases delays for short USB packets but it
2541 also reduces the risk of timeouts before receiving the expected number of bytes.
2542 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2543 @end deffn
2545 @deffn {Config Command} {ft2232_channel} channel
2546 Used to select the channel of the ft2232 chip to use (between 1 and 4).
2547 The default value is 1.
2548 @end deffn
2550 For example, the interface config file for a
2551 Turtelizer JTAG Adapter looks something like this:
2553 @example
2554 interface ft2232
2555 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2556 ft2232_layout turtelizer2
2557 ft2232_vid_pid 0x0403 0xbdc8
2558 @end example
2559 @end deffn
2561 @deffn {Interface Driver} {ftdi}
2562 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2563 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2564 It is a complete rewrite to address a large number of problems with the ft2232
2565 interface driver.
2567 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2568 bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
2569 consistently faster than the ft2232 driver, sometimes several times faster.
2571 A major improvement of this driver is that support for new FTDI based adapters
2572 can be added competely through configuration files, without the need to patch
2573 and rebuild OpenOCD.
2575 The driver uses a signal abstraction to enable Tcl configuration files to
2576 define outputs for one or several FTDI GPIO. These outputs can then be
2577 controlled using the @command{ftdi_set_signal} command. Special signal names
2578 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2579 will be used for their customary purpose.
2581 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2582 be controlled differently. In order to support tristateable signals such as
2583 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2584 signal. The following output buffer configurations are supported:
2586 @itemize @minus
2587 @item Push-pull with one FTDI output as (non-)inverted data line
2588 @item Open drain with one FTDI output as (non-)inverted output-enable
2589 @item Tristate with one FTDI output as (non-)inverted data line and another
2590 FTDI output as (non-)inverted output-enable
2591 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2592 switching data and direction as necessary
2593 @end itemize
2595 These interfaces have several commands, used to configure the driver
2596 before initializing the JTAG scan chain:
2598 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2599 The vendor ID and product ID of the adapter. If not specified, the FTDI
2600 default values are used.
2601 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2602 @example
2603 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2604 @end example
2605 @end deffn
2607 @deffn {Config Command} {ftdi_device_desc} description
2608 Provides the USB device description (the @emph{iProduct string})
2609 of the adapter. If not specified, the device description is ignored
2610 during device selection.
2611 @end deffn
2613 @deffn {Config Command} {ftdi_serial} serial-number
2614 Specifies the @var{serial-number} of the adapter to use,
2615 in case the vendor provides unique IDs and more than one adapter
2616 is connected to the host.
2617 If not specified, serial numbers are not considered.
2618 (Note that USB serial numbers can be arbitrary Unicode strings,
2619 and are not restricted to containing only decimal digits.)
2620 @end deffn
2622 @deffn {Config Command} {ftdi_channel} channel
2623 Selects the channel of the FTDI device to use for MPSSE operations. Most
2624 adapters use the default, channel 0, but there are exceptions.
2625 @end deffn
2627 @deffn {Config Command} {ftdi_layout_init} data direction
2628 Specifies the initial values of the FTDI GPIO data and direction registers.
2629 Each value is a 16-bit number corresponding to the concatenation of the high
2630 and low FTDI GPIO registers. The values should be selected based on the
2631 schematics of the adapter, such that all signals are set to safe levels with
2632 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2633 and initially asserted reset signals.
2634 @end deffn
2636 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask]
2637 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2638 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2639 register bitmasks to tell the driver the connection and type of the output
2640 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2641 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2642 used with inverting data inputs and @option{-data} with non-inverting inputs.
2643 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2644 not-output-enable) input to the output buffer is connected.
2646 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2647 simple open-collector transistor driver would be specified with @option{-oe}
2648 only. In that case the signal can only be set to drive low or to Hi-Z and the
2649 driver will complain if the signal is set to drive high. Which means that if
2650 it's a reset signal, @command{reset_config} must be specified as
2651 @option{srst_open_drain}, not @option{srst_push_pull}.
2653 A special case is provided when @option{-data} and @option{-oe} is set to the
2654 same bitmask. Then the FTDI pin is considered being connected straight to the
2655 target without any buffer. The FTDI pin is then switched between output and
2656 input as necessary to provide the full set of low, high and Hi-Z
2657 characteristics. In all other cases, the pins specified in a signal definition
2658 are always driven by the FTDI.
2659 @end deffn
2661 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2662 Set a previously defined signal to the specified level.
2663 @itemize @minus
2664 @item @option{0}, drive low
2665 @item @option{1}, drive high
2666 @item @option{z}, set to high-impedance
2667 @end itemize
2668 @end deffn
2670 For example adapter definitions, see the configuration files shipped in the
2671 @file{interface/ftdi} directory.
2672 @end deffn
2674 @deffn {Interface Driver} {remote_bitbang}
2675 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2676 with a remote process and sends ASCII encoded bitbang requests to that process
2677 instead of directly driving JTAG.
2679 The remote_bitbang driver is useful for debugging software running on
2680 processors which are being simulated.
2682 @deffn {Config Command} {remote_bitbang_port} number
2683 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2684 sockets instead of TCP.
2685 @end deffn
2687 @deffn {Config Command} {remote_bitbang_host} hostname
2688 Specifies the hostname of the remote process to connect to using TCP, or the
2689 name of the UNIX socket to use if remote_bitbang_port is 0.
2690 @end deffn
2692 For example, to connect remotely via TCP to the host foobar you might have
2693 something like:
2695 @example
2696 interface remote_bitbang
2697 remote_bitbang_port 3335
2698 remote_bitbang_host foobar
2699 @end example
2701 To connect to another process running locally via UNIX sockets with socket
2702 named mysocket:
2704 @example
2705 interface remote_bitbang
2706 remote_bitbang_port 0
2707 remote_bitbang_host mysocket
2708 @end example
2709 @end deffn
2711 @deffn {Interface Driver} {usb_blaster}
2712 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2713 for FTDI chips. These interfaces have several commands, used to
2714 configure the driver before initializing the JTAG scan chain:
2716 @deffn {Config Command} {usb_blaster_device_desc} description
2717 Provides the USB device description (the @emph{iProduct string})
2718 of the FTDI FT245 device. If not
2719 specified, the FTDI default value is used. This setting is only valid
2720 if compiled with FTD2XX support.
2721 @end deffn
2723 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2724 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2725 default values are used.
2726 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2727 Altera USB-Blaster (default):
2728 @example
2729 usb_blaster_vid_pid 0x09FB 0x6001
2730 @end example
2731 The following VID/PID is for Kolja Waschk's USB JTAG:
2732 @example
2733 usb_blaster_vid_pid 0x16C0 0x06AD
2734 @end example
2735 @end deffn
2737 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2738 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2739 female JTAG header). These pins can be used as SRST and/or TRST provided the
2740 appropriate connections are made on the target board.
2742 For example, to use pin 6 as SRST (as with an AVR board):
2743 @example
2744 $_TARGETNAME configure -event reset-assert \
2745 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2746 @end example
2747 @end deffn
2749 @end deffn
2751 @deffn {Interface Driver} {gw16012}
2752 Gateworks GW16012 JTAG programmer.
2753 This has one driver-specific command:
2755 @deffn {Config Command} {parport_port} [port_number]
2756 Display either the address of the I/O port
2757 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2758 If a parameter is provided, first switch to use that port.
2759 This is a write-once setting.
2760 @end deffn
2761 @end deffn
2763 @deffn {Interface Driver} {jlink}
2764 Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
2766 @quotation Compatibility Note
2767 Segger released many firmware versions for the many harware versions they
2768 produced. OpenOCD was extensively tested and intended to run on all of them,
2769 but some combinations were reported as incompatible. As a general
2770 recommendation, it is advisable to use the latest firmware version
2771 available for each hardware version. However the current V8 is a moving
2772 target, and Segger firmware versions released after the OpenOCD was
2773 released may not be compatible. In such cases it is recommended to
2774 revert to the last known functional version. For 0.5.0, this is from
2775 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2776 version is from "May 3 2012 18:36:22", packed with 4.46f.
2777 @end quotation
2779 @deffn {Command} {jlink caps}
2780 Display the device firmware capabilities.
2781 @end deffn
2782 @deffn {Command} {jlink info}
2783 Display various device information, like hardware version, firmware version, current bus status.
2784 @end deffn
2785 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2786 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2787 @end deffn
2788 @deffn {Command} {jlink config}
2789 Display the J-Link configuration.
2790 @end deffn
2791 @deffn {Command} {jlink config kickstart} [val]
2792 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2793 @end deffn
2794 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2795 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2796 @end deffn
2797 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2798 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2799 E the bit of the subnet mask and
2800 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2801 @end deffn
2802 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2803 Set the USB address; this will also change the product id. Without argument, show the USB address.
2804 @end deffn
2805 @deffn {Command} {jlink config reset}
2806 Reset the current configuration.
2807 @end deffn
2808 @deffn {Command} {jlink config save}
2809 Save the current configuration to the internal persistent storage.
2810 @end deffn
2811 @deffn {Config} {jlink pid} val
2812 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2813 @end deffn
2814 @end deffn
2816 @deffn {Interface Driver} {parport}
2817 Supports PC parallel port bit-banging cables:
2818 Wigglers, PLD download cable, and more.
2819 These interfaces have several commands, used to configure the driver
2820 before initializing the JTAG scan chain:
2822 @deffn {Config Command} {parport_cable} name
2823 Set the layout of the parallel port cable used to connect to the target.
2824 This is a write-once setting.
2825 Currently valid cable @var{name} values include:
2827 @itemize @minus
2828 @item @b{altium} Altium Universal JTAG cable.
2829 @item @b{arm-jtag} Same as original wiggler except SRST and
2830 TRST connections reversed and TRST is also inverted.
2831 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2832 in configuration mode. This is only used to
2833 program the Chameleon itself, not a connected target.
2834 @item @b{dlc5} The Xilinx Parallel cable III.
2835 @item @b{flashlink} The ST Parallel cable.
2836 @item @b{lattice} Lattice ispDOWNLOAD Cable
2837 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2838 some versions of
2839 Amontec's Chameleon Programmer. The new version available from
2840 the website uses the original Wiggler layout ('@var{wiggler}')
2841 @item @b{triton} The parallel port adapter found on the
2842 ``Karo Triton 1 Development Board''.
2843 This is also the layout used by the HollyGates design
2844 (see @uref{}).
2845 @item @b{wiggler} The original Wiggler layout, also supported by
2846 several clones, such as the Olimex ARM-JTAG
2847 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2848 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2849 @end itemize
2850 @end deffn
2852 @deffn {Config Command} {parport_port} [port_number]
2853 Display either the address of the I/O port
2854 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2855 If a parameter is provided, first switch to use that port.
2856 This is a write-once setting.
2858 When using PPDEV to access the parallel port, use the number of the parallel port:
2859 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2860 you may encounter a problem.
2861 @end deffn
2863 @deffn Command {parport_toggling_time} [nanoseconds]
2864 Displays how many nanoseconds the hardware needs to toggle TCK;
2865 the parport driver uses this value to obey the
2866 @command{adapter_khz} configuration.
2867 When the optional @var{nanoseconds} parameter is given,
2868 that setting is changed before displaying the current value.
2870 The default setting should work reasonably well on commodity PC hardware.
2871 However, you may want to calibrate for your specific hardware.
2872 @quotation Tip
2873 To measure the toggling time with a logic analyzer or a digital storage
2874 oscilloscope, follow the procedure below:
2875 @example
2876 > parport_toggling_time 1000
2877 > adapter_khz 500
2878 @end example
2879 This sets the maximum JTAG clock speed of the hardware, but
2880 the actual speed probably deviates from the requested 500 kHz.
2881 Now, measure the time between the two closest spaced TCK transitions.
2882 You can use @command{runtest 1000} or something similar to generate a
2883 large set of samples.
2884 Update the setting to match your measurement:
2885 @example
2886 > parport_toggling_time <measured nanoseconds>
2887 @end example
2888 Now the clock speed will be a better match for @command{adapter_khz rate}
2889 commands given in OpenOCD scripts and event handlers.
2891 You can do something similar with many digital multimeters, but note
2892 that you'll probably need to run the clock continuously for several
2893 seconds before it decides what clock rate to show. Adjust the
2894 toggling time up or down until the measured clock rate is a good
2895 match for the adapter_khz rate you specified; be conservative.
2896 @end quotation
2897 @end deffn
2899 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2900 This will configure the parallel driver to write a known
2901 cable-specific value to the parallel interface on exiting OpenOCD.
2902 @end deffn
2904 For example, the interface configuration file for a
2905 classic ``Wiggler'' cable on LPT2 might look something like this:
2907 @example
2908 interface parport
2909 parport_port 0x278
2910 parport_cable wiggler
2911 @end example
2912 @end deffn
2914 @deffn {Interface Driver} {presto}
2915 ASIX PRESTO USB JTAG programmer.
2916 @deffn {Config Command} {presto_serial} serial_string
2917 Configures the USB serial number of the Presto device to use.
2918 @end deffn
2919 @end deffn
2921 @deffn {Interface Driver} {rlink}
2922 Raisonance RLink USB adapter
2923 @end deffn
2925 @deffn {Interface Driver} {usbprog}
2926 usbprog is a freely programmable USB adapter.
2927 @end deffn
2929 @deffn {Interface Driver} {vsllink}
2930 vsllink is part of Versaloon which is a versatile USB programmer.
2932 @quotation Note
2933 This defines quite a few driver-specific commands,
2934 which are not currently documented here.
2935 @end quotation
2936 @end deffn
2938 @deffn {Interface Driver} {hla}
2939 This is a driver that supports multiple High Level Adapters.
2940 This type of adapter does not expose some of the lower level api's
2941 that OpenOCD would normally use to access the target.
2943 Currently supported adapters include the ST STLINK and TI ICDI.
2945 @deffn {Config Command} {hla_device_desc} description
2946 Currently Not Supported.
2947 @end deffn
2949 @deffn {Config Command} {hla_serial} serial
2950 Currently Not Supported.
2951 @end deffn
2953 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
2954 Specifies the adapter layout to use.
2955 @end deffn
2957 @deffn {Config Command} {hla_vid_pid} vid pid
2958 The vendor ID and product ID of the device.
2959 @end deffn
2961 @deffn {Config Command} {stlink_api} api_level
2962 Manually sets the stlink api used, valid options are 1 or 2. (@b{STLINK Only}).
2963 @end deffn
2964 @end deffn
2966 @deffn {Interface Driver} {opendous}
2967 opendous-jtag is a freely programmable USB adapter.
2968 @end deffn
2970 @deffn {Interface Driver} {ulink}
2971 This is the Keil ULINK v1 JTAG debugger.
2972 @end deffn
2974 @deffn {Interface Driver} {ZY1000}
2975 This is the Zylin ZY1000 JTAG debugger.
2976 @end deffn
2978 @quotation Note
2979 This defines some driver-specific commands,
2980 which are not currently documented here.
2981 @end quotation
2983 @deffn Command power [@option{on}|@option{off}]
2984 Turn power switch to target on/off.
2985 No arguments: print status.
2986 @end deffn
2988 @section Transport Configuration
2989 @cindex Transport
2990 As noted earlier, depending on the version of OpenOCD you use,
2991 and the debug adapter you are using,
2992 several transports may be available to
2993 communicate with debug targets (or perhaps to program flash memory).
2994 @deffn Command {transport list}
2995 displays the names of the transports supported by this
2996 version of OpenOCD.
2997 @end deffn
2999 @deffn Command {transport select} transport_name
3000 Select which of the supported transports to use in this OpenOCD session.
3001 The transport must be supported by the debug adapter hardware and by the
3002 version of OPenOCD you are using (including the adapter's driver).
3003 No arguments: returns name of session's selected transport.
3004 @end deffn
3006 @subsection JTAG Transport
3007 @cindex JTAG
3008 JTAG is the original transport supported by OpenOCD, and most
3009 of the OpenOCD commands support it.
3010 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3011 each of which must be explicitly declared.
3012 JTAG supports both debugging and boundary scan testing.
3013 Flash programming support is built on top of debug support.
3014 @subsection SWD Transport
3015 @cindex SWD
3016 @cindex Serial Wire Debug
3017 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3018 Debug Access Point (DAP, which must be explicitly declared.
3019 (SWD uses fewer signal wires than JTAG.)
3020 SWD is debug-oriented, and does not support boundary scan testing.
3021 Flash programming support is built on top of debug support.
3022 (Some processors support both JTAG and SWD.)
3023 @deffn Command {swd newdap} ...
3024 Declares a single DAP which uses SWD transport.
3025 Parameters are currently the same as "jtag newtap" but this is
3026 expected to change.
3027 @end deffn
3028 @deffn Command {swd wcr trn prescale}
3029 Updates TRN (turnaraound delay) and prescaling.fields of the
3030 Wire Control Register (WCR).
3031 No parameters: displays current settings.
3032 @end deffn
3034 @subsection SPI Transport
3035 @cindex SPI
3036 @cindex Serial Peripheral Interface
3037 The Serial Peripheral Interface (SPI) is a general purpose transport
3038 which uses four wire signaling. Some processors use it as part of a
3039 solution for flash programming.
3041 @anchor{JTAG Speed}
3042 @section JTAG Speed
3043 JTAG clock setup is part of system setup.
3044 It @emph{does not belong with interface setup} since any interface
3045 only knows a few of the constraints for the JTAG clock speed.
3046 Sometimes the JTAG speed is
3047 changed during the target initialization process: (1) slow at
3048 reset, (2) program the CPU clocks, (3) run fast.
3049 Both the "slow" and "fast" clock rates are functions of the
3050 oscillators used, the chip, the board design, and sometimes
3051 power management software that may be active.
3053 The speed used during reset, and the scan chain verification which
3054 follows reset, can be adjusted using a @code{reset-start}
3055 target event handler.
3056 It can then be reconfigured to a faster speed by a
3057 @code{reset-init} target event handler after it reprograms those
3058 CPU clocks, or manually (if something else, such as a boot loader,
3059 sets up those clocks).
3060 @xref{Target Events}.
3061 When the initial low JTAG speed is a chip characteristic, perhaps
3062 because of a required oscillator speed, provide such a handler
3063 in the target config file.
3064 When that speed is a function of a board-specific characteristic
3065 such as which speed oscillator is used, it belongs in the board
3066 config file instead.
3067 In both cases it's safest to also set the initial JTAG clock rate
3068 to that same slow speed, so that OpenOCD never starts up using a
3069 clock speed that's faster than the scan chain can support.
3071 @example
3072 jtag_rclk 3000
3073 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3074 @end example
3076 If your system supports adaptive clocking (RTCK), configuring
3077 JTAG to use that is probably the most robust approach.
3078 However, it introduces delays to synchronize clocks; so it
3079 may not be the fastest solution.
3081 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3082 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3083 which support adaptive clocking.
3085 @deffn {Command} adapter_khz max_speed_kHz
3086 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3087 JTAG interfaces usually support a limited number of
3088 speeds. The speed actually used won't be faster
3089 than the speed specified.
3091 Chip data sheets generally include a top JTAG clock rate.
3092 The actual rate is often a function of a CPU core clock,
3093 and is normally less than that peak rate.
3094 For example, most ARM cores accept at most one sixth of the CPU clock.
3096 Speed 0 (khz) selects RTCK method.
3097 @xref{FAQ RTCK}.
3098 If your system uses RTCK, you won't need to change the
3099 JTAG clocking after setup.
3100 Not all interfaces, boards, or targets support ``rtck''.
3101 If the interface device can not
3102 support it, an error is returned when you try to use RTCK.
3103 @end deffn
3105 @defun jtag_rclk fallback_speed_kHz
3106 @cindex adaptive clocking
3107 @cindex RTCK
3108 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3109 If that fails (maybe the interface, board, or target doesn't
3110 support it), falls back to the specified frequency.
3111 @example
3112 # Fall back to 3mhz if RTCK is not supported
3113 jtag_rclk 3000
3114 @end example
3115 @end defun
3117 @node Reset Configuration
3118 @chapter Reset Configuration
3119 @cindex Reset Configuration
3121 Every system configuration may require a different reset
3122 configuration. This can also be quite confusing.
3123 Resets also interact with @var{reset-init} event handlers,
3124 which do things like setting up clocks and DRAM, and
3125 JTAG clock rates. (@xref{JTAG Speed}.)
3126 They can also interact with JTAG routers.
3127 Please see the various board files for examples.
3129 @quotation Note
3130 To maintainers and integrators:
3131 Reset configuration touches several things at once.
3132 Normally the board configuration file
3133 should define it and assume that the JTAG adapter supports
3134 everything that's wired up to the board's JTAG connector.
3136 However, the target configuration file could also make note
3137 of something the silicon vendor has done inside the chip,
3138 which will be true for most (or all) boards using that chip.
3139 And when the JTAG adapter doesn't support everything, the
3140 user configuration file will need to override parts of
3141 the reset configuration provided by other files.
3142 @end quotation
3144 @section Types of Reset
3146 There are many kinds of reset possible through JTAG, but
3147 they may not all work with a given board and adapter.
3148 That's part of why reset configuration can be error prone.
3150 @itemize @bullet
3151 @item
3152 @emph{System Reset} ... the @emph{SRST} hardware signal
3153 resets all chips connected to the JTAG adapter, such as processors,
3154 power management chips, and I/O controllers. Normally resets triggered
3155 with this signal behave exactly like pressing a RESET button.
3156 @item
3157 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3158 just the TAP controllers connected to the JTAG adapter.
3159 Such resets should not be visible to the rest of the system; resetting a
3160 device's TAP controller just puts that controller into a known state.
3161 @item
3162 @emph{Emulation Reset} ... many devices can be reset through JTAG
3163 commands. These resets are often distinguishable from system
3164 resets, either explicitly (a "reset reason" register says so)
3165 or implicitly (not all parts of the chip get reset).
3166 @item
3167 @emph{Other Resets} ... system-on-chip devices often support
3168 several other types of reset.
3169 You may need to arrange that a watchdog timer stops
3170 while debugging, preventing a watchdog reset.
3171 There may be individual module resets.
3172 @end itemize
3174 In the best case, OpenOCD can hold SRST, then reset
3175 the TAPs via TRST and send commands through JTAG to halt the
3176 CPU at the reset vector before the 1st instruction is executed.
3177 Then when it finally releases the SRST signal, the system is
3178 halted under debugger control before any code has executed.
3179 This is the behavior required to support the @command{reset halt}
3180 and @command{reset init} commands; after @command{reset init} a
3181 board-specific script might do things like setting up DRAM.
3182 (@xref{Reset Command}.)
3184 @anchor{SRST and TRST Issues}
3185 @section SRST and TRST Issues
3187 Because SRST and TRST are hardware signals, they can have a
3188 variety of system-specific constraints. Some of the most
3189 common issues are:
3191 @itemize @bullet
3193 @item @emph{Signal not available} ... Some boards don't wire
3194 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3195 support such signals even if they are wired up.
3196 Use the @command{reset_config} @var{signals} options to say
3197 when either of those signals is not connected.
3198 When SRST is not available, your code might not be able to rely
3199 on controllers having been fully reset during code startup.
3200 Missing TRST is not a problem, since JTAG-level resets can
3201 be triggered using with TMS signaling.
3203 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3204 adapter will connect SRST to TRST, instead of keeping them separate.
3205 Use the @command{reset_config} @var{combination} options to say
3206 when those signals aren't properly independent.
3208 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3209 delay circuit, reset supervisor, or on-chip features can extend
3210 the effect of a JTAG adapter's reset for some time after the adapter
3211 stops issuing the reset. For example, there may be chip or board
3212 requirements that all reset pulses last for at least a
3213 certain amount of time; and reset buttons commonly have
3214 hardware debouncing.
3215 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3216 commands to say when extra delays are needed.
3218 @item @emph{Drive type} ... Reset lines often have a pullup
3219 resistor, letting the JTAG interface treat them as open-drain
3220 signals. But that's not a requirement, so the adapter may need
3221 to use push/pull output drivers.
3222 Also, with weak pullups it may be advisable to drive
3223 signals to both levels (push/pull) to minimize rise times.
3224 Use the @command{reset_config} @var{trst_type} and
3225 @var{srst_type} parameters to say how to drive reset signals.
3227 @item @emph{Special initialization} ... Targets sometimes need
3228 special JTAG initialization sequences to handle chip-specific
3229 issues (not limited to errata).
3230 For example, certain JTAG commands might need to be issued while
3231 the system as a whole is in a reset state (SRST active)
3232 but the JTAG scan chain is usable (TRST inactive).
3233 Many systems treat combined assertion of SRST and TRST as a
3234 trigger for a harder reset than SRST alone.
3235 Such custom reset handling is discussed later in this chapter.
3236 @end itemize
3238 There can also be other issues.
3239 Some devices don't fully conform to the JTAG specifications.
3240 Trivial system-specific differences are common, such as
3241 SRST and TRST using slightly different names.
3242 There are also vendors who distribute key JTAG documentation for
3243 their chips only to developers who have signed a Non-Disclosure
3244 Agreement (NDA).
3246 Sometimes there are chip-specific extensions like a requirement to use
3247 the normally-optional TRST signal (precluding use of JTAG adapters which
3248 don't pass TRST through), or needing extra steps to complete a TAP reset.
3250 In short, SRST and especially TRST handling may be very finicky,
3251 needing to cope with both architecture and board specific constraints.
3253 @section Commands for Handling Resets
3255 @deffn {Command} adapter_nsrst_assert_width milliseconds
3256 Minimum amount of time (in milliseconds) OpenOCD should wait
3257 after asserting nSRST (active-low system reset) before
3258 allowing it to be deasserted.
3259 @end deffn
3261 @deffn {Command} adapter_nsrst_delay milliseconds
3262 How long (in milliseconds) OpenOCD should wait after deasserting
3263 nSRST (active-low system reset) before starting new JTAG operations.
3264 When a board has a reset button connected to SRST line it will
3265 probably have hardware debouncing, implying you should use this.
3266 @end deffn
3268 @deffn {Command} jtag_ntrst_assert_width milliseconds
3269 Minimum amount of time (in milliseconds) OpenOCD should wait
3270 after asserting nTRST (active-low JTAG TAP reset) before
3271 allowing it to be deasserted.
3272 @end deffn
3274 @deffn {Command} jtag_ntrst_delay milliseconds
3275 How long (in milliseconds) OpenOCD should wait after deasserting
3276 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3277 @end deffn
3279 @deffn {Command} reset_config mode_flag ...
3280 This command displays or modifies the reset configuration
3281 of your combination of JTAG board and target in target
3282 configuration scripts.
3284 Information earlier in this section describes the kind of problems
3285 the command is intended to address (@pxref{SRST and TRST Issues}).
3286 As a rule this command belongs only in board config files,
3287 describing issues like @emph{board doesn't connect TRST};
3288 or in user config files, addressing limitations derived
3289 from a particular combination of interface and board.
3290 (An unlikely example would be using a TRST-only adapter
3291 with a board that only wires up SRST.)
3293 The @var{mode_flag} options can be specified in any order, but only one
3294 of each type -- @var{signals}, @var{combination}, @var{gates},
3295 @var{trst_type}, @var{srst_type} and @var{connect_type}
3296 -- may be specified at a time.
3297 If you don't provide a new value for a given type, its previous
3298 value (perhaps the default) is unchanged.
3299 For example, this means that you don't need to say anything at all about
3300 TRST just to declare that if the JTAG adapter should want to drive SRST,
3301 it must explicitly be driven high (@option{srst_push_pull}).
3303 @itemize
3304 @item
3305 @var{signals} can specify which of the reset signals are connected.
3306 For example, If the JTAG interface provides SRST, but the board doesn't
3307 connect that signal properly, then OpenOCD can't use it.
3308 Possible values are @option{none} (the default), @option{trst_only},
3309 @option{srst_only} and @option{trst_and_srst}.
3311 @quotation Tip
3312 If your board provides SRST and/or TRST through the JTAG connector,
3313 you must declare that so those signals can be used.
3314 @end quotation
3316 @item
3317 The @var{combination} is an optional value specifying broken reset
3318 signal implementations.
3319 The default behaviour if no option given is @option{separate},
3320 indicating everything behaves normally.
3321 @option{srst_pulls_trst} states that the
3322 test logic is reset together with the reset of the system (e.g. NXP
3323 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3324 the system is reset together with the test logic (only hypothetical, I
3325 haven't seen hardware with such a bug, and can be worked around).
3326 @option{combined} implies both @option{srst_pulls_trst} and
3327 @option{trst_pulls_srst}.
3329 @item
3330 The @var{gates} tokens control flags that describe some cases where
3331 JTAG may be unvailable during reset.
3332 @option{srst_gates_jtag} (default)
3333 indicates that asserting SRST gates the
3334 JTAG clock. This means that no communication can happen on JTAG
3335 while SRST is asserted.
3336 Its converse is @option{srst_nogate}, indicating that JTAG commands
3337 can safely be issued while SRST is active.
3339 @item
3340 The @var{connect_type} tokens control flags that describe some cases where
3341 SRST is asserted while connecting to the target. @option{srst_nogate}
3342 is required to use this option.
3343 @option{connect_deassert_srst} (default)
3344 indicates that SRST will not be asserted while connecting to the target.
3345 Its converse is @option{connect_assert_srst}, indicating that SRST will
3346 be asserted before any target connection.
3347 Only some targets support this feature, STM32 and STR9 are examples.
3348 This feature is useful if you are unable to connect to your target due
3349 to incorrect options byte config or illegal program execution.
3350 @end itemize
3352 The optional @var{trst_type} and @var{srst_type} parameters allow the
3353 driver mode of each reset line to be specified. These values only affect
3354 JTAG interfaces with support for different driver modes, like the Amontec
3355 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3356 relevant signal (TRST or SRST) is not connected.
3358 @itemize
3359 @item
3360 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3361 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3362 Most boards connect this signal to a pulldown, so the JTAG TAPs
3363 never leave reset unless they are hooked up to a JTAG adapter.
3365 @item
3366 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3367 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3368 Most boards connect this signal to a pullup, and allow the
3369 signal to be pulled low by various events including system
3370 powerup and pressing a reset button.
3371 @end itemize
3372 @end deffn
3374 @section Custom Reset Handling
3375 @cindex events
3377 OpenOCD has several ways to help support the various reset
3378 mechanisms provided by chip and board vendors.
3379 The commands shown in the previous section give standard parameters.
3380 There are also @emph{event handlers} associated with TAPs or Targets.
3381 Those handlers are Tcl procedures you can provide, which are invoked
3382 at particular points in the reset sequence.
3384 @emph{When SRST is not an option} you must set
3385 up a @code{reset-assert} event handler for your target.
3386 For example, some JTAG adapters don't include the SRST signal;
3387 and some boards have multiple targets, and you won't always
3388 want to reset everything at once.
3390 After configuring those mechanisms, you might still
3391 find your board doesn't start up or reset correctly.
3392 For example, maybe it needs a slightly different sequence
3393 of SRST and/or TRST manipulations, because of quirks that
3394 the @command{reset_config} mechanism doesn't address;
3395 or asserting both might trigger a stronger reset, which
3396 needs special attention.
3398 Experiment with lower level operations, such as @command{jtag_reset}
3399 and the @command{jtag arp_*} operations shown here,
3400 to find a sequence of operations that works.
3401 @xref{JTAG Commands}.
3402 When you find a working sequence, it can be used to override
3403 @command{jtag_init}, which fires during OpenOCD startup
3404 (@pxref{Configuration Stage});
3405 or @command{init_reset}, which fires during reset processing.
3407 You might also want to provide some project-specific reset
3408 schemes. For example, on a multi-target board the standard
3409 @command{reset} command would reset all targets, but you
3410 may need the ability to reset only one target at time and
3411 thus want to avoid using the board-wide SRST signal.
3413 @deffn {Overridable Procedure} init_reset mode
3414 This is invoked near the beginning of the @command{reset} command,
3415 usually to provide as much of a cold (power-up) reset as practical.
3416 By default it is also invoked from @command{jtag_init} if
3417 the scan chain does not respond to pure JTAG operations.
3418 The @var{mode} parameter is the parameter given to the
3419 low level reset command (@option{halt},
3420 @option{init}, or @option{run}), @option{setup},
3421 or potentially some other value.
3423 The default implementation just invokes @command{jtag arp_init-reset}.
3424 Replacements will normally build on low level JTAG
3425 operations such as @command{jtag_reset}.
3426 Operations here must not address individual TAPs
3427 (or their associated targets)
3428 until the JTAG scan chain has first been verified to work.
3430 Implementations must have verified the JTAG scan chain before
3431 they return.
3432 This is done by calling @command{jtag arp_init}
3433 (or @command{jtag arp_init-reset}).
3434 @end deffn
3436 @deffn Command {jtag arp_init}
3437 This validates the scan chain using just the four
3438 standard JTAG signals (TMS, TCK, TDI, TDO).
3439 It starts by issuing a JTAG-only reset.
3440 Then it performs checks to verify that the scan chain configuration
3441 matches the TAPs it can observe.
3442 Those checks include checking IDCODE values for each active TAP,
3443 and verifying the length of their instruction registers using
3444 TAP @code{-ircapture} and @code{-irmask} values.
3445 If these tests all pass, TAP @code{setup} events are
3446 issued to all TAPs with handlers for that event.
3447 @end deffn
3449 @deffn Command {jtag arp_init-reset}
3450 This uses TRST and SRST to try resetting
3451 everything on the JTAG scan chain
3452 (and anything else connected to SRST).
3453 It then invokes the logic of @command{jtag arp_init}.
3454 @end deffn
3457 @node TAP Declaration
3458 @chapter TAP Declaration
3459 @cindex TAP declaration
3460 @cindex TAP configuration
3462 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3463 TAPs serve many roles, including:
3465 @itemize @bullet
3466 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
3467 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
3468 Others do it indirectly, making a CPU do it.
3469 @item @b{Program Download} Using the same CPU support GDB uses,
3470 you can initialize a DRAM controller, download code to DRAM, and then
3471 start running that code.
3472 @item @b{Boundary Scan} Most chips support boundary scan, which
3473 helps test for board assembly problems like solder bridges
3474 and missing connections
3475 @end itemize
3477 OpenOCD must know about the active TAPs on your board(s).
3478 Setting up the TAPs is the core task of your configuration files.
3479 Once those TAPs are set up, you can pass their names to code
3480 which sets up CPUs and exports them as GDB targets,
3481 probes flash memory, performs low-level JTAG operations, and more.
3483 @section Scan Chains
3484 @cindex scan chain
3486 TAPs are part of a hardware @dfn{scan chain},
3487 which is daisy chain of TAPs.
3488 They also need to be added to
3489 OpenOCD's software mirror of that hardware list,
3490 giving each member a name and associating other data with it.
3491 Simple scan chains, with a single TAP, are common in
3492 systems with a single microcontroller or microprocessor.
3493 More complex chips may have several TAPs internally.
3494 Very complex scan chains might have a dozen or more TAPs:
3495 several in one chip, more in the next, and connecting
3496 to other boards with their own chips and TAPs.
3498 You can display the list with the @command{scan_chain} command.
3499 (Don't confuse this with the list displayed by the @command{targets}
3500 command, presented in the next chapter.
3501 That only displays TAPs for CPUs which are configured as
3502 debugging targets.)
3503 Here's what the scan chain might look like for a chip more than one TAP:
3505 @verbatim
3506 TapName Enabled IdCode Expected IrLen IrCap IrMask
3507 -- ------------------ ------- ---------- ---------- ----- ----- ------
3508 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3509 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3510 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3511 @end verbatim
3513 OpenOCD can detect some of that information, but not all
3514 of it. @xref{Autoprobing}.
3515 Unfortunately those TAPs can't always be autoconfigured,
3516 because not all devices provide good support for that.
3517 JTAG doesn't require supporting IDCODE instructions, and
3518 chips with JTAG routers may not link TAPs into the chain
3519 until they are told to do so.
3521 The configuration mechanism currently supported by OpenOCD
3522 requires explicit configuration of all TAP devices using
3523 @command{jtag newtap} commands, as detailed later in this chapter.
3524 A command like this would declare one tap and name it @code{chip1.cpu}:
3526 @example
3527 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3528 @end example
3530 Each target configuration file lists the TAPs provided
3531 by a given chip.
3532 Board configuration files combine all the targets on a board,
3533 and so forth.
3534 Note that @emph{the order in which TAPs are declared is very important.}
3535 It must match the order in the JTAG scan chain, both inside
3536 a single chip and between them.
3537 @xref{FAQ TAP Order}.
3539 For example, the ST Microsystems STR912 chip has
3540 three separate TAPs@footnote{See the ST
3541 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3542 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3543 @url{}}.
3544 To configure those taps, @file{target/str912.cfg}
3545 includes commands something like this:
3547 @example
3548 jtag newtap str912 flash ... params ...
3549 jtag newtap str912 cpu ... params ...
3550 jtag newtap str912 bs ... params ...
3551 @end example
3553 Actual config files use a variable instead of literals like
3554 @option{str912}, to support more than one chip of each type.
3555 @xref{Config File Guidelines}.
3557 @deffn Command {jtag names}
3558 Returns the names of all current TAPs in the scan chain.
3559 Use @command{jtag cget} or @command{jtag tapisenabled}
3560 to examine attributes and state of each TAP.
3561 @example
3562 foreach t [jtag names] @{
3563 puts [format "TAP: %s\n" $t]
3564 @}
3565 @end example
3566 @end deffn
3568 @deffn Command {scan_chain}
3569 Displays the TAPs in the scan chain configuration,
3570 and their status.
3571 The set of TAPs listed by this command is fixed by
3572 exiting the OpenOCD configuration stage,
3573 but systems with a JTAG router can
3574 enable or disable TAPs dynamically.
3575 @end deffn
3577 @c FIXME! "jtag cget" should be able to return all TAP
3578 @c attributes, like "$target_name cget" does for targets.
3580 @c Probably want "jtag eventlist", and a "tap-reset" event
3581 @c (on entry to RESET state).
3583 @section TAP Names
3584 @cindex dotted name
3586 When TAP objects are declared with @command{jtag newtap},
3587 a @dfn{} is created for the TAP, combining the
3588 name of a module (usually a chip) and a label for the TAP.
3589 For example: @code{xilinx.tap}, @code{str912.flash},
3590 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3591 Many other commands use that to manipulate or
3592 refer to the TAP. For example, CPU configuration uses the
3593 name, as does declaration of NAND or NOR flash banks.
3595 The components of a dotted name should follow ``C'' symbol
3596 name rules: start with an alphabetic character, then numbers
3597 and underscores are OK; while others (including dots!) are not.
3599 @quotation Tip
3600 In older code, JTAG TAPs were numbered from 0..N.
3601 This feature is still present.
3602 However its use is highly discouraged, and
3603 should not be relied on; it will be removed by mid-2010.
3604 Update all of your scripts to use TAP names rather than numbers,
3605 by paying attention to the runtime warnings they trigger.
3606 Using TAP numbers in target configuration scripts prevents
3607 reusing those scripts on boards with multiple targets.
3608 @end quotation
3610 @section TAP Declaration Commands
3612 @c shouldn't this be(come) a {Config Command}?
3613 @anchor{jtag newtap}
3614 @deffn Command {jtag newtap} chipname tapname configparams...
3615 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3616 and configured according to the various @var{configparams}.
3618 The @var{chipname} is a symbolic name for the chip.
3619 Conventionally target config files use @code{$_CHIPNAME},
3620 defaulting to the model name given by the chip vendor but
3621 overridable.
3623 @cindex TAP naming convention
3624 The @var{tapname} reflects the role of that TAP,
3625 and should follow this convention:
3627 @itemize @bullet
3628 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3629 @item @code{cpu} -- The main CPU of the chip, alternatively
3630 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3631 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3632 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3633 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3634 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3635 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3636 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3637 with a single TAP;
3638 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3639 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3640 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3641 a JTAG TAP; that TAP should be named @code{sdma}.
3642 @end itemize
3644 Every TAP requires at least the following @var{configparams}:
3646 @itemize @bullet
3647 @item @code{-irlen} @var{NUMBER}
3648 @*The length in bits of the
3649 instruction register, such as 4 or 5 bits.
3650 @end itemize
3652 A TAP may also provide optional @var{configparams}:
3654 @itemize @bullet
3655 @item @code{-disable} (or @code{-enable})
3656 @*Use the @code{-disable} parameter to flag a TAP which is not
3657 linked in to the scan chain after a reset using either TRST
3658 or the JTAG state machine's @sc{reset} state.
3659 You may use @code{-enable} to highlight the default state
3660 (the TAP is linked in).
3661 @xref{Enabling and Disabling TAPs}.
3662 @item @code{-expected-id} @var{number}
3663 @*A non-zero @var{number} represents a 32-bit IDCODE
3664 which you expect to find when the scan chain is examined.
3665 These codes are not required by all JTAG devices.
3666 @emph{Repeat the option} as many times as required if more than one
3667 ID code could appear (for example, multiple versions).
3668 Specify @var{number} as zero to suppress warnings about IDCODE
3669 values that were found but not included in the list.
3671 Provide this value if at all possible, since it lets OpenOCD
3672 tell when the scan chain it sees isn't right. These values
3673 are provided in vendors' chip documentation, usually a technical
3674 reference manual. Sometimes you may need to probe the JTAG
3675 hardware to find these values.
3676 @xref{Autoprobing}.
3677 @item @code{-ignore-version}
3678 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3679 option. When vendors put out multiple versions of a chip, or use the same
3680 JTAG-level ID for several largely-compatible chips, it may be more practical
3681 to ignore the version field than to update config files to handle all of
3682 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3683 @item @code{-ircapture} @var{NUMBER}
3684 @*The bit pattern loaded by the TAP into the JTAG shift register
3685 on entry to the @sc{ircapture} state, such as 0x01.
3686 JTAG requires the two LSBs of this value to be 01.
3687 By default, @code{-ircapture} and @code{-irmask} are set
3688 up to verify that two-bit value. You may provide
3689 additional bits, if you know them, or indicate that
3690 a TAP doesn't conform to the JTAG specification.
3691 @item @code{-irmask} @var{NUMBER}
3692 @*A mask used with @code{-ircapture}
3693 to verify that instruction scans work correctly.
3694 Such scans are not used by OpenOCD except to verify that
3695 there seems to be no problems with JTAG scan chain operations.
3696 @end itemize
3697 @end deffn
3699 @section Other TAP commands
3701 @deffn Command {jtag cget} @option{-event} name
3702 @deffnx Command {jtag configure} @option{-event} name string
3703 At this writing this TAP attribute
3704 mechanism is used only for event handling.
3705 (It is not a direct analogue of the @code{cget}/@code{configure}
3706 mechanism for debugger targets.)
3707 See the next section for information about the available events.
3709 The @code{configure} subcommand assigns an event handler,
3710 a TCL string which is evaluated when the event is triggered.
3711 The @code{cget} subcommand returns that handler.
3712 @end deffn
3714 @anchor{TAP Events}
3715 @section TAP Events
3716 @cindex events
3717 @cindex TAP events
3719 OpenOCD includes two event mechanisms.
3720 The one presented here applies to all JTAG TAPs.
3721 The other applies to debugger targets,
3722 which are associated with certain TAPs.
3724 The TAP events currently defined are:
3726 @itemize @bullet
3727 @item @b{post-reset}
3728 @* The TAP has just completed a JTAG reset.
3729 The tap may still be in the JTAG @sc{reset} state.
3730 Handlers for these events might perform initialization sequences
3731 such as issuing TCK cycles, TMS sequences to ensure
3732 exit from the ARM SWD mode, and more.
3734 Because the scan chain has not yet been verified, handlers for these events
3735 @emph{should not issue commands which scan the JTAG IR or DR registers}
3736 of any particular target.
3737 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3738 @item @b{setup}
3739 @* The scan chain has been reset and verified.
3740 This handler may enable TAPs as needed.
3741 @item @b{tap-disable}
3742 @* The TAP needs to be disabled. This handler should
3743 implement @command{jtag tapdisable}
3744 by issuing the relevant JTAG commands.
3745 @item @b{tap-enable}
3746 @* The TAP needs to be enabled. This handler should
3747 implement @command{jtag tapenable}
3748 by issuing the relevant JTAG commands.
3749 @end itemize
3751 If you need some action after each JTAG reset, which isn't actually
3752 specific to any TAP (since you can't yet trust the scan chain's
3753 contents to be accurate), you might:
3755 @example
3756 jtag configure CHIP.jrc -event post-reset @{
3757 echo "JTAG Reset done"
3758 ... non-scan jtag operations to be done after reset
3759 @}
3760 @end example
3763 @anchor{Enabling and Disabling TAPs}
3764 @section Enabling and Disabling TAPs
3765 @cindex JTAG Route Controller
3766 @cindex jrc
3768 In some systems, a @dfn{JTAG Route Controller} (JRC)
3769 is used to enable and/or disable specific JTAG TAPs.
3770 Many ARM based chips from Texas Instruments include
3771 an ``ICEpick'' module, which is a JRC.
3772 Such chips include DaVinci and OMAP3 processors.
3774 A given TAP may not be visible until the JRC has been
3775 told to link it into the scan chain; and if the JRC
3776 has been told to unlink that TAP, it will no longer
3777 be visible.
3778 Such routers address problems that JTAG ``bypass mode''
3779 ignores, such as:
3781 @itemize
3782 @item The scan chain can only go as fast as its slowest TAP.
3783 @item Having many TAPs slows instruction scans, since all
3784 TAPs receive new instructions.
3785 @item TAPs in the scan chain must be powered up, which wastes
3786 power and prevents debugging some power management mechanisms.
3787 @end itemize
3789 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3790 as implied by the existence of JTAG routers.
3791 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3792 does include a kind of JTAG router functionality.
3794 @c (a) currently the event handlers don't seem to be able to
3795 @c fail in a way that could lead to no-change-of-state.
3797 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3798 shown below, and is implemented using TAP event handlers.
3799 So for example, when defining a TAP for a CPU connected to
3800 a JTAG router, your @file{target.cfg} file
3801 should define TAP event handlers using
3802 code that looks something like this:
3804 @example
3805 jtag configure CHIP.cpu -event tap-enable @{
3806 ... jtag operations using CHIP.jrc
3807 @}
3808 jtag configure CHIP.cpu -event tap-disable @{
3809 ... jtag operations using CHIP.jrc
3810 @}
3811 @end example
3813 Then you might want that CPU's TAP enabled almost all the time:
3815 @example
3816 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3817 @end example
3819 Note how that particular setup event handler declaration
3820 uses quotes to evaluate @code{$CHIP} when the event is configured.
3821 Using brackets @{ @} would cause it to be evaluated later,
3822 at runtime, when it might have a different value.
3824 @deffn Command {jtag tapdisable}
3825 If necessary, disables the tap
3826 by sending it a @option{tap-disable} event.
3827 Returns the string "1" if the tap
3828 specified by @var{} is enabled,
3829 and "0" if it is disabled.
3830 @end deffn
3832 @deffn Command {jtag tapenable}
3833 If necessary, enables the tap
3834 by sending it a @option{tap-enable} event.
3835 Returns the string "1" if the tap
3836 specified by @var{} is enabled,
3837 and "0" if it is disabled.
3838 @end deffn
3840 @deffn Command {jtag tapisenabled}
3841 Returns the string "1" if the tap
3842 specified by @var{} is enabled,
3843 and "0" if it is disabled.
3845 @quotation Note
3846 Humans will find the @command{scan_chain} command more helpful
3847 for querying the state of the JTAG taps.
3848 @end quotation
3849 @end deffn
3851 @anchor{Autoprobing}
3852 @section Autoprobing
3853 @cindex autoprobe
3854 @cindex JTAG autoprobe
3856 TAP configuration is the first thing that needs to be done
3857 after interface and reset configuration. Sometimes it's
3858 hard finding out what TAPs exist, or how they are identified.
3859 Vendor documentation is not always easy to find and use.
3861 To help you get past such problems, OpenOCD has a limited
3862 @emph{autoprobing} ability to look at the scan chain, doing
3863 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3864 To use this mechanism, start the OpenOCD server with only data
3865 that configures your JTAG interface, and arranges to come up
3866 with a slow clock (many devices don't support fast JTAG clocks
3867 right when they come out of reset).
3869 For example, your @file{openocd.cfg} file might have:
3871 @example
3872 source [find interface/olimex-arm-usb-tiny-h.cfg]
3873 reset_config trst_and_srst
3874 jtag_rclk 8
3875 @end example
3877 When you start the server without any TAPs configured, it will
3878 attempt to autoconfigure the TAPs. There are two parts to this:
3880 @enumerate
3881 @item @emph{TAP discovery} ...
3882 After a JTAG reset (sometimes a system reset may be needed too),
3883 each TAP's data registers will hold the contents of either the
3884 IDCODE or BYPASS register.
3885 If JTAG communication is working, OpenOCD will see each TAP,
3886 and report what @option{-expected-id} to use with it.
3887 @item @emph{IR Length discovery} ...
3888 Unfortunately JTAG does not provide a reliable way to find out
3889 the value of the @option{-irlen} parameter to use with a TAP
3890 that is discovered.
3891 If OpenOCD can discover the length of a TAP's instruction
3892 register, it will report it.
3893 Otherwise you may need to consult vendor documentation, such
3894 as chip data sheets or BSDL files.
3895 @end enumerate
3897 In many cases your board will have a simple scan chain with just
3898 a single device. Here's what OpenOCD reported with one board
3899 that's a bit more complex:
3901 @example
3902 clock speed 8 kHz
3903 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3904 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3905 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3906 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3907 AUTO auto0.tap - use "... -irlen 4"
3908 AUTO auto1.tap - use "... -irlen 4"
3909 AUTO auto2.tap - use "... -irlen 6"
3910 no gdb ports allocated as no target has been specified
3911 @end example
3913 Given that information, you should be able to either find some existing
3914 config files to use, or create your own. If you create your own, you
3915 would configure from the bottom up: first a @file{target.cfg} file
3916 with these TAPs, any targets associated with them, and any on-chip
3917 resources; then a @file{board.cfg} with off-chip resources, clocking,
3918 and so forth.
3920 @node CPU Configuration
3921 @chapter CPU Configuration
3922 @cindex GDB target
3924 This chapter discusses how to set up GDB debug targets for CPUs.
3925 You can also access these targets without GDB
3926 (@pxref{Architecture and Core Commands},
3927 and @ref{Target State handling}) and
3928 through various kinds of NAND and NOR flash commands.
3929 If you have multiple CPUs you can have multiple such targets.
3931 We'll start by looking at how to examine the targets you have,
3932 then look at how to add one more target and how to configure it.
3934 @section Target List
3935 @cindex target, current
3936 @cindex target, list
3938 All targets that have been set up are part of a list,
3939 where each member has a name.
3940 That name should normally be the same as the TAP name.
3941 You can display the list with the @command{targets}
3942 (plural!) command.
3943 This display often has only one CPU; here's what it might
3944 look like with more than one:
3945 @verbatim
3946 TargetName Type Endian TapName State
3947 -- ------------------ ---------- ------ ------------------ ------------
3948 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
3949 1 MyTarget cortex_m3 little tap-disabled
3950 @end verbatim
3952 One member of that list is the @dfn{current target}, which
3953 is implicitly referenced by many commands.
3954 It's the one marked with a @code{*} near the target name.
3955 In particular, memory addresses often refer to the address
3956 space seen by that current target.
3957 Commands like @command{mdw} (memory display words)
3958 and @command{flash erase_address} (erase NOR flash blocks)
3959 are examples; and there are many more.
3961 Several commands let you examine the list of targets:
3963 @deffn Command {target count}
3964 @emph{Note: target numbers are deprecated; don't use them.
3965 They will be removed shortly after August 2010, including this command.
3966 Iterate target using @command{target names}, not by counting.}
3968 Returns the number of targets, @math{N}.
3969 The highest numbered target is @math{N - 1}.
3970 @example
3971 set c [target count]
3972 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
3973 # Assuming you have created this function
3974 print_target_details $x
3975 @}
3976 @end example
3977 @end deffn
3979 @deffn Command {target current}
3980 Returns the name of the current target.
3981 @end deffn
3983 @deffn Command {target names}
3984 Lists the names of all current targets in the list.
3985 @example
3986 foreach t [target names] @{
3987 puts [format "Target: %s\n" $t]
3988 @}
3989 @end example
3990 @end deffn
3992 @deffn Command {target number} number
3993 @emph{Note: target numbers are deprecated; don't use them.
3994 They will be removed shortly after August 2010, including this command.}
3996 The list of targets is numbered starting at zero.
3997 This command returns the name of the target at index @var{number}.
3998 @example
3999 set thename [target number $x]
4000 puts [format "Target %d is: %s\n" $x $thename]
4001 @end example
4002 @end deffn
4004 @c yep, "target list" would have been better.
4005 @c plus maybe "target setdefault".
4007 @deffn Command targets [name]
4008 @emph{Note: the name of this command is plural. Other target
4009 command names are singular.}
4011 With no parameter, this command displays a table of all known
4012 targets in a user friendly form.
4014 With a parameter, this command sets the current target to
4015 the given target with the given @var{name}; this is
4016 only relevant on boards which have more than one target.
4017 @end deffn
4019 @section Target CPU Types and Variants
4020 @cindex target type
4021 @cindex CPU type
4022 @cindex CPU variant
4024 Each target has a @dfn{CPU type}, as shown in the output of
4025 the @command{targets} command. You need to specify that type
4026 when calling @command{target create}.
4027 The CPU type indicates more than just the instruction set.
4028 It also indicates how that instruction set is implemented,
4029 what kind of debug support it integrates,
4030 whether it has an MMU (and if so, what kind),
4031 what core-specific commands may be available
4032 (@pxref{Architecture and Core Commands}),
4033 and more.
4035 For some CPU types, OpenOCD also defines @dfn{variants} which
4036 indicate differences that affect their handling.
4037 For example, a particular implementation bug might need to be
4038 worked around in some chip versions.
4040 It's easy to see what target types are supported,
4041 since there's a command to list them.
4042 However, there is currently no way to list what target variants
4043 are supported (other than by reading the OpenOCD source code).
4045 @anchor{target types}
4046 @deffn Command {target types}
4047 Lists all supported target types.
4048 At this writing, the supported CPU types and variants are:
4050 @itemize @bullet
4051 @item @code{arm11} -- this is a generation of ARMv6 cores
4052 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4053 @item @code{arm7tdmi} -- this is an ARMv4 core
4054 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4055 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4056 @item @code{arm966e} -- this is an ARMv5 core
4057 @item @code{arm9tdmi} -- this is an ARMv4 core
4058 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4059 (Support for this is preliminary and incomplete.)
4060 @item @code{cortex_a8} -- this is an ARMv7 core with an MMU
4061 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
4062 compact Thumb2 instruction set.
4063 @item @code{dragonite} -- resembles arm966e
4064 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4065 (Support for this is still incomplete.)
4066 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4067 @item @code{feroceon} -- resembles arm926
4068 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
4069 @item @code{xscale} -- this is actually an architecture,
4070 not a CPU type. It is based on the ARMv5 architecture.
4071 There are several variants defined:
4072 @itemize @minus
4073 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
4074 @code{pxa27x} ... instruction register length is 7 bits
4075 @item @code{pxa250}, @code{pxa255},
4076 @code{pxa26x} ... instruction register length is 5 bits
4077 @item @code{pxa3xx} ... instruction register length is 11 bits
4078 @end itemize
4079 @end itemize
4080 @end deffn
4082 To avoid being confused by the variety of ARM based cores, remember
4083 this key point: @emph{ARM is a technology licencing company}.
4084 (See: @url{}.)
4085 The CPU name used by OpenOCD will reflect the CPU design that was
4086 licenced, not a vendor brand which incorporates that design.
4087 Name prefixes like arm7, arm9, arm11, and cortex
4088 reflect design generations;
4089 while names like ARMv4, ARMv5, ARMv6, and ARMv7
4090 reflect an architecture version implemented by a CPU design.
4092 @anchor{Target Configuration}
4093 @section Target Configuration
4095 Before creating a ``target'', you must have added its TAP to the scan chain.
4096 When you've added that TAP, you will have a @code{}
4097 which is used to set up the CPU support.
4098 The chip-specific configuration file will normally configure its CPU(s)
4099 right after it adds all of the chip's TAPs to the scan chain.
4101 Although you can set up a target in one step, it's often clearer if you
4102 use shorter commands and do it in two steps: create it, then configure
4103 optional parts.
4104 All operations on the target after it's created will use a new
4105 command, created as part of target creation.
4107 The two main things to configure after target creation are
4108 a work area, which usually has target-specific defaults even
4109 if the board setup code overrides them later;
4110 and event handlers (@pxref{Target Events}), which tend
4111 to be much more board-specific.
4112 The key steps you use might look something like this
4114 @example
4115 target create MyTarget cortex_m3 -chain-position mychip.cpu
4116 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4117 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4118 $MyTarget configure -event reset-init @{ myboard_reinit @}
4119 @end example
4121 You should specify a working area if you can; typically it uses some
4122 on-chip SRAM.
4123 Such a working area can speed up many things, including bulk
4124 writes to target memory;
4125 flash operations like checking to see if memory needs to be erased;
4126 GDB memory checksumming;
4127 and more.
4129 @quotation Warning
4130 On more complex chips, the work area can become
4131 inaccessible when application code
4132 (such as an operating system)
4133 enables or disables the MMU.
4134 For example, the particular MMU context used to acess the virtual
4135 address will probably matter ... and that context might not have
4136 easy access to other addresses needed.
4137 At this writing, OpenOCD doesn't have much MMU intelligence.
4138 @end quotation
4140 It's often very useful to define a @code{reset-init} event handler.
4141 For systems that are normally used with a boot loader,
4142 common tasks include updating clocks and initializing memory
4143 controllers.
4144 That may be needed to let you write the boot loader into flash,
4145 in order to ``de-brick'' your board; or to load programs into
4146 external DDR memory without having run the boot loader.
4148 @deffn Command {target create} target_name type configparams...
4149 This command creates a GDB debug target that refers to a specific JTAG tap.
4150 It enters that target into a list, and creates a new
4151 command (@command{@var{target_name}}) which is used for various
4152 purposes including additional configuration.
4154 @itemize @bullet
4155 @item @var{target_name} ... is the name of the debug target.
4156 By convention this should be the same as the @emph{}
4157 of the TAP associated with this target, which must be specified here
4158 using the @code{-chain-position @var{}} configparam.
4160 This name is also used to create the target object command,
4161 referred to here as @command{$target_name},
4162 and in other places the target needs to be identified.
4163 @item @var{type} ... specifies the target type. @xref{target types}.
4164 @item @var{configparams} ... all parameters accepted by
4165 @command{$target_name configure} are permitted.
4166 If the target is big-endian, set it here with @code{-endian big}.
4167 If the variant matters, set it here with @code{-variant}.
4169 You @emph{must} set the @code{-chain-position @var{}} here.
4170 @end itemize
4171 @end deffn
4173 @deffn Command {$target_name configure} configparams...
4174 The options accepted by this command may also be
4175 specified as parameters to @command{target create}.
4176 Their value