[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * NAND Flash Commands:: NAND Flash Commands
77 * PLD/FPGA Commands:: PLD/FPGA Commands
78 * General Commands:: General Commands
79 * Architecture and Core Commands:: Architecture and Core Commands
80 * JTAG Commands:: JTAG Commands
81 * Boundary Scan Commands:: Boundary Scan Commands
82 * Utility Commands:: Utility Commands
83 * TFTP:: TFTP
84 * GDB and OpenOCD:: Using GDB and OpenOCD
85 * Tcl Scripting API:: Tcl Scripting API
86 * FAQ:: Frequently Asked Questions
87 * Tcl Crash Course:: Tcl Crash Course
88 * License:: GNU Free Documentation License
90 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
91 @comment case issue with ``Index.html'' and ``index.html''
92 @comment Occurs when creating ``--html --no-split'' output
93 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
94 * OpenOCD Concept Index:: Concept Index
95 * Command and Driver Index:: Command and Driver Index
96 @end menu
98 @node About
99 @unnumbered About
100 @cindex about
102 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
103 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
104 Since that time, the project has grown into an active open-source project,
105 supported by a diverse community of software and hardware developers from
106 around the world.
108 @section What is OpenOCD?
109 @cindex TAP
110 @cindex JTAG
112 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
113 in-system programming and boundary-scan testing for embedded target
114 devices.
116 It does so with the assistance of a @dfn{debug adapter}, which is
117 a small hardware module which helps provide the right kind of
118 electrical signaling to the target being debugged. These are
119 required since the debug host (on which OpenOCD runs) won't
120 usually have native support for such signaling, or the connector
121 needed to hook up to the target.
123 Such debug adapters support one or more @dfn{transport} protocols,
124 each of which involves different electrical signaling (and uses
125 different messaging protocols on top of that signaling). There
126 are many types of debug adapter, and little uniformity in what
127 they are called. (There are also product naming differences.)
129 These adapters are sometimes packaged as discrete dongles, which
130 may generically be called @dfn{hardware interface dongles}.
131 Some development boards also integrate them directly, which may
132 let the development board can be directly connected to the debug
133 host over USB (and sometimes also to power it over USB).
135 For example, a @dfn{JTAG Adapter} supports JTAG
136 signaling, and is used to communicate
137 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
138 A @dfn{TAP} is a ``Test Access Port'', a module which processes
139 special instructions and data. TAPs are daisy-chained within and
140 between chips and boards. JTAG supports debugging and boundary
141 scan operations.
143 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
144 signaling to communicate with some newer ARM cores, as well as debug
145 adapters which support both JTAG and SWD transports. SWD only supports
146 debugging, whereas JTAG also supports boundary scan operations.
148 For some chips, there are also @dfn{Programming Adapters} supporting
149 special transports used only to write code to flash memory, without
150 support for on-chip debugging or boundary scan.
151 (At this writing, OpenOCD does not support such non-debug adapters.)
154 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
155 based, parallel port based, and other standalone boxes that run
156 OpenOCD internally. @xref{Debug Adapter Hardware}.
158 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
159 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
160 Cortex-M3 (Stellaris LM3, ST STM32 and Energy Micro EFM32) based cores to be
161 debugged via the GDB protocol.
163 @b{Flash Programing:} Flash writing is supported for external CFI
164 compatible NOR flashes (Intel and AMD/Spansion command set) and several
165 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
166 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
167 controllers (LPC3180, Orion, S3C24xx, more) controller is included.
169 @section OpenOCD Web Site
171 The OpenOCD web site provides the latest public news from the community:
173 @uref{http://openocd.sourceforge.net/}
175 @section Latest User's Guide:
177 The user's guide you are now reading may not be the latest one
178 available. A version for more recent code may be available.
179 Its HTML form is published regularly at:
181 @uref{http://openocd.sourceforge.net/doc/html/index.html}
183 PDF form is likewise published at:
185 @uref{http://openocd.sourceforge.net/doc/pdf/openocd.pdf}
187 @section OpenOCD User's Forum
189 There is an OpenOCD forum (phpBB) hosted by SparkFun,
190 which might be helpful to you. Note that if you want
191 anything to come to the attention of developers, you
192 should post it to the OpenOCD Developer Mailing List
193 instead of this forum.
195 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
197 @section OpenOCD User's Mailing List
199 The OpenOCD User Mailing List provides the primary means of
200 communication between users:
202 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
204 @section OpenOCD IRC
206 Support can also be found on irc:
207 @uref{irc://irc.freenode.net/openocd}
209 @node Developers
210 @chapter OpenOCD Developer Resources
211 @cindex developers
213 If you are interested in improving the state of OpenOCD's debugging and
214 testing support, new contributions will be welcome. Motivated developers
215 can produce new target, flash or interface drivers, improve the
216 documentation, as well as more conventional bug fixes and enhancements.
218 The resources in this chapter are available for developers wishing to explore
219 or expand the OpenOCD source code.
221 @section OpenOCD GIT Repository
223 During the 0.3.x release cycle, OpenOCD switched from Subversion to
224 a GIT repository hosted at SourceForge. The repository URL is:
226 @uref{git://git.code.sf.net/p/openocd/code}
228 or via http
230 @uref{http://git.code.sf.net/p/openocd/code}
232 You may prefer to use a mirror and the HTTP protocol:
234 @uref{http://repo.or.cz/r/openocd.git}
236 With standard GIT tools, use @command{git clone} to initialize
237 a local repository, and @command{git pull} to update it.
238 There are also gitweb pages letting you browse the repository
239 with a web browser, or download arbitrary snapshots without
240 needing a GIT client:
242 @uref{http://repo.or.cz/w/openocd.git}
244 The @file{README} file contains the instructions for building the project
245 from the repository or a snapshot.
247 Developers that want to contribute patches to the OpenOCD system are
248 @b{strongly} encouraged to work against mainline.
249 Patches created against older versions may require additional
250 work from their submitter in order to be updated for newer releases.
252 @section Doxygen Developer Manual
254 During the 0.2.x release cycle, the OpenOCD project began
255 providing a Doxygen reference manual. This document contains more
256 technical information about the software internals, development
257 processes, and similar documentation:
259 @uref{http://openocd.sourceforge.net/doc/doxygen/html/index.html}
261 This document is a work-in-progress, but contributions would be welcome
262 to fill in the gaps. All of the source files are provided in-tree,
263 listed in the Doxyfile configuration in the top of the source tree.
265 @section OpenOCD Developer Mailing List
267 The OpenOCD Developer Mailing List provides the primary means of
268 communication between developers:
270 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
272 Discuss and submit patches to this list.
273 The @file{HACKING} file contains basic information about how
274 to prepare patches.
276 @section OpenOCD Bug Database
278 During the 0.4.x release cycle the OpenOCD project team began
279 using Trac for its bug database:
281 @uref{https://sourceforge.net/apps/trac/openocd}
284 @node Debug Adapter Hardware
285 @chapter Debug Adapter Hardware
286 @cindex dongles
287 @cindex FTDI
288 @cindex wiggler
289 @cindex zy1000
290 @cindex printer port
291 @cindex USB Adapter
292 @cindex RTCK
294 Defined: @b{dongle}: A small device that plugins into a computer and serves as
295 an adapter .... [snip]
297 In the OpenOCD case, this generally refers to @b{a small adapter} that
298 attaches to your computer via USB or the Parallel Printer Port. One
299 exception is the Zylin ZY1000, packaged as a small box you attach via
300 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
301 require any drivers to be installed on the developer PC. It also has
302 a built in web interface. It supports RTCK/RCLK or adaptive clocking
303 and has a built in relay to power cycle targets remotely.
306 @section Choosing a Dongle
308 There are several things you should keep in mind when choosing a dongle.
310 @enumerate
311 @item @b{Transport} Does it support the kind of communication that you need?
312 OpenOCD focusses mostly on JTAG. Your version may also support
313 other ways to communicate with target devices.
314 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
315 Does your dongle support it? You might need a level converter.
316 @item @b{Pinout} What pinout does your target board use?
317 Does your dongle support it? You may be able to use jumper
318 wires, or an "octopus" connector, to convert pinouts.
319 @item @b{Connection} Does your computer have the USB, printer, or
320 Ethernet port needed?
321 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
322 RTCK support? Also known as ``adaptive clocking''
323 @end enumerate
325 @section Stand-alone JTAG Probe
327 The ZY1000 from Ultimate Solutions is technically not a dongle but a
328 stand-alone JTAG probe that unlikemost dongles doesn’t require any drivers
329 running on the developers host computer.
330 Once installed on a network using DHCP or a static IP assignment, users can
331 access the ZY1000 probe locally or remotely from any host with access to the
332 IP address assigned to the probe.
333 The ZY1000 provides an intuitive web interface with direct access to the
334 OpenOCD debugger.
335 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
336 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
337 the target.
338 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
339 to power cycle the target remotely.
341 For more information, visit:
343 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/33-zylin-zy1000-jtag-probe}
345 @section USB FT2232 Based
347 There are many USB JTAG dongles on the market, many of them are based
348 on a chip from ``Future Technology Devices International'' (FTDI)
349 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
350 See: @url{http://www.ftdichip.com} for more information.
351 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
352 chips are starting to become available in JTAG adapters. Around 2012 a new
353 variant appeared - FT232H - this is a single-channel version of FT2232H.
354 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
355 clocking.)
357 The FT2232 chips are flexible enough to support some other
358 transport options, such as SWD or the SPI variants used to
359 program some chips. They have two communications channels,
360 and one can be used for a UART adapter at the same time the
361 other one is used to provide a debug adapter.
363 Also, some development boards integrate an FT2232 chip to serve as
364 a built-in low cost debug adapter and usb-to-serial solution.
366 @itemize @bullet
367 @item @b{usbjtag}
368 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
369 @item @b{jtagkey}
370 @* See: @url{http://www.amontec.com/jtagkey.shtml}
371 @item @b{jtagkey2}
372 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
373 @item @b{oocdlink}
374 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
375 @item @b{signalyzer}
376 @* See: @url{http://www.signalyzer.com}
377 @item @b{Stellaris Eval Boards}
378 @* See: @url{http://www.ti.com} - The Stellaris eval boards
379 bundle FT2232-based JTAG and SWD support, which can be used to debug
380 the Stellaris chips. Using separate JTAG adapters is optional.
381 These boards can also be used in a "pass through" mode as JTAG adapters
382 to other target boards, disabling the Stellaris chip.
383 @item @b{TI/Luminary ICDI}
384 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
385 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
386 Evaluation Kits. Like the non-detachable FT2232 support on the other
387 Stellaris eval boards, they can be used to debug other target boards.
388 @item @b{olimex-jtag}
389 @* See: @url{http://www.olimex.com}
390 @item @b{Flyswatter/Flyswatter2}
391 @* See: @url{http://www.tincantools.com}
392 @item @b{turtelizer2}
393 @* See:
394 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
395 @url{http://www.ethernut.de}
396 @item @b{comstick}
397 @* Link: @url{http://www.hitex.com/index.php?id=383}
398 @item @b{stm32stick}
399 @* Link @url{http://www.hitex.com/stm32-stick}
400 @item @b{axm0432_jtag}
401 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
402 to be available anymore as of April 2012.
403 @item @b{cortino}
404 @* Link @url{http://www.hitex.com/index.php?id=cortino}
405 @item @b{dlp-usb1232h}
406 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
407 @item @b{digilent-hs1}
408 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
409 @item @b{opendous}
410 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
411 (OpenHardware).
412 @item @b{JTAG-lock-pick Tiny 2}
413 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
415 @item @b{GW16042}
416 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
417 FT2232H-based
419 @end itemize
420 @section USB-JTAG / Altera USB-Blaster compatibles
422 These devices also show up as FTDI devices, but are not
423 protocol-compatible with the FT2232 devices. They are, however,
424 protocol-compatible among themselves. USB-JTAG devices typically consist
425 of a FT245 followed by a CPLD that understands a particular protocol,
426 or emulate this protocol using some other hardware.
428 They may appear under different USB VID/PID depending on the particular
429 product. The driver can be configured to search for any VID/PID pair
430 (see the section on driver commands).
432 @itemize
433 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
434 @* Link: @url{http://ixo-jtag.sourceforge.net/}
435 @item @b{Altera USB-Blaster}
436 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
437 @end itemize
439 @section USB JLINK based
440 There are several OEM versions of the Segger @b{JLINK} adapter. It is
441 an example of a micro controller based JTAG adapter, it uses an
442 AT91SAM764 internally.
444 @itemize @bullet
445 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
446 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
447 @item @b{SEGGER JLINK}
448 @* Link: @url{http://www.segger.com/jlink.html}
449 @item @b{IAR J-Link}
450 @* Link: @url{http://www.iar.com/en/products/hardware-debug-probes/iar-j-link/}
451 @end itemize
453 @section USB RLINK based
454 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
455 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
456 SWD and not JTAG, thus not supported.
458 @itemize @bullet
459 @item @b{Raisonance RLink}
460 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
461 @item @b{STM32 Primer}
462 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
463 @item @b{STM32 Primer2}
464 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
465 @end itemize
467 @section USB ST-LINK based
468 ST Micro has an adapter called @b{ST-LINK}.
469 They only work with ST Micro chips, notably STM32 and STM8.
471 @itemize @bullet
472 @item @b{ST-LINK}
473 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
474 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
475 @item @b{ST-LINK/V2}
476 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
477 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
478 @end itemize
480 For info the original ST-LINK enumerates using the mass storage usb class, however
481 it's implementation is completely broken. The result is this causes issues under linux.
482 The simplest solution is to get linux to ignore the ST-LINK using one of the following methods:
483 @itemize @bullet
484 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
485 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
486 @end itemize
488 @section USB TI/Stellaris ICDI based
489 Texas Instruments has an adapter called @b{ICDI}.
490 It is not to be confused with the FTDI based adapters that were originally fitted to their
491 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
493 @section USB Other
494 @itemize @bullet
495 @item @b{USBprog}
496 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
498 @item @b{USB - Presto}
499 @* Link: @url{http://tools.asix.net/prg_presto.htm}
501 @item @b{Versaloon-Link}
502 @* Link: @url{http://www.versaloon.com}
504 @item @b{ARM-JTAG-EW}
505 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
507 @item @b{Buspirate}
508 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
510 @item @b{opendous}
511 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
513 @item @b{estick}
514 @* Link: @url{http://code.google.com/p/estick-jtag/}
516 @item @b{Keil ULINK v1}
517 @* Link: @url{http://www.keil.com/ulink1/}
518 @end itemize
520 @section IBM PC Parallel Printer Port Based
522 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
523 and the Macraigor Wiggler. There are many clones and variations of
524 these on the market.
526 Note that parallel ports are becoming much less common, so if you
527 have the choice you should probably avoid these adapters in favor
528 of USB-based ones.
530 @itemize @bullet
532 @item @b{Wiggler} - There are many clones of this.
533 @* Link: @url{http://www.macraigor.com/wiggler.htm}
535 @item @b{DLC5} - From XILINX - There are many clones of this
536 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
537 produced, PDF schematics are easily found and it is easy to make.
539 @item @b{Amontec - JTAG Accelerator}
540 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
542 @item @b{Wiggler2}
543 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
545 @item @b{Wiggler_ntrst_inverted}
546 @* Yet another variation - See the source code, src/jtag/parport.c
548 @item @b{old_amt_wiggler}
549 @* Unknown - probably not on the market today
551 @item @b{arm-jtag}
552 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
554 @item @b{chameleon}
555 @* Link: @url{http://www.amontec.com/chameleon.shtml}
557 @item @b{Triton}
558 @* Unknown.
560 @item @b{Lattice}
561 @* ispDownload from Lattice Semiconductor
562 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
564 @item @b{flashlink}
565 @* From ST Microsystems;
566 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
568 @end itemize
570 @section Other...
571 @itemize @bullet
573 @item @b{ep93xx}
574 @* An EP93xx based Linux machine using the GPIO pins directly.
576 @item @b{at91rm9200}
577 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
579 @item @b{bcm2835gpio}
580 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
582 @item @b{jtag_vpi}
583 @* A JTAG driver acting as a client for the JTAG VPI server interface.
584 @* Link: @url{http://github.com/fjullien/jtag_vpi}
586 @end itemize
588 @node About Jim-Tcl
589 @chapter About Jim-Tcl
590 @cindex Jim-Tcl
591 @cindex tcl
593 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
594 This programming language provides a simple and extensible
595 command interpreter.
597 All commands presented in this Guide are extensions to Jim-Tcl.
598 You can use them as simple commands, without needing to learn
599 much of anything about Tcl.
600 Alternatively, can write Tcl programs with them.
602 You can learn more about Jim at its website, @url{http://jim.berlios.de}.
603 There is an active and responsive community, get on the mailing list
604 if you have any questions. Jim-Tcl maintainers also lurk on the
605 OpenOCD mailing list.
607 @itemize @bullet
608 @item @b{Jim vs. Tcl}
609 @* Jim-Tcl is a stripped down version of the well known Tcl language,
610 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
611 fewer features. Jim-Tcl is several dozens of .C files and .H files and
612 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
613 4.2 MB .zip file containing 1540 files.
615 @item @b{Missing Features}
616 @* Our practice has been: Add/clone the real Tcl feature if/when
617 needed. We welcome Jim-Tcl improvements, not bloat. Also there
618 are a large number of optional Jim-Tcl features that are not
619 enabled in OpenOCD.
621 @item @b{Scripts}
622 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
623 command interpreter today is a mixture of (newer)
624 Jim-Tcl commands, and (older) the orginal command interpreter.
626 @item @b{Commands}
627 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
628 can type a Tcl for() loop, set variables, etc.
629 Some of the commands documented in this guide are implemented
630 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
632 @item @b{Historical Note}
633 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
634 before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
635 as a git submodule, which greatly simplified upgrading Jim Tcl
636 to benefit from new features and bugfixes in Jim Tcl.
638 @item @b{Need a crash course in Tcl?}
639 @*@xref{Tcl Crash Course}.
640 @end itemize
642 @node Running
643 @chapter Running
644 @cindex command line options
645 @cindex logfile
646 @cindex directory search
648 Properly installing OpenOCD sets up your operating system to grant it access
649 to the debug adapters. On Linux, this usually involves installing a file
650 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
651 complex and confusing driver configuration for every peripheral. Such issues
652 are unique to each operating system, and are not detailed in this User's Guide.
654 Then later you will invoke the OpenOCD server, with various options to
655 tell it how each debug session should work.
656 The @option{--help} option shows:
657 @verbatim
658 bash$ openocd --help
660 --help | -h display this help
661 --version | -v display OpenOCD version
662 --file | -f use configuration file <name>
663 --search | -s dir to search for config files and scripts
664 --debug | -d set debug level <0-3>
665 --log_output | -l redirect log output to file <name>
666 --command | -c run <command>
667 @end verbatim
669 If you don't give any @option{-f} or @option{-c} options,
670 OpenOCD tries to read the configuration file @file{openocd.cfg}.
671 To specify one or more different
672 configuration files, use @option{-f} options. For example:
674 @example
675 openocd -f config1.cfg -f config2.cfg -f config3.cfg
676 @end example
678 Configuration files and scripts are searched for in
679 @enumerate
680 @item the current directory,
681 @item any search dir specified on the command line using the @option{-s} option,
682 @item any search dir specified using the @command{add_script_search_dir} command,
683 @item @file{$HOME/.openocd} (not on Windows),
684 @item the site wide script library @file{$pkgdatadir/site} and
685 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
686 @end enumerate
687 The first found file with a matching file name will be used.
689 @quotation Note
690 Don't try to use configuration script names or paths which
691 include the "#" character. That character begins Tcl comments.
692 @end quotation
694 @section Simple setup, no customization
696 In the best case, you can use two scripts from one of the script
697 libraries, hook up your JTAG adapter, and start the server ... and
698 your JTAG setup will just work "out of the box". Always try to
699 start by reusing those scripts, but assume you'll need more
700 customization even if this works. @xref{OpenOCD Project Setup}.
702 If you find a script for your JTAG adapter, and for your board or
703 target, you may be able to hook up your JTAG adapter then start
704 the server like:
706 @example
707 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
708 @end example
710 You might also need to configure which reset signals are present,
711 using @option{-c 'reset_config trst_and_srst'} or something similar.
712 If all goes well you'll see output something like
714 @example
715 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
716 For bug reports, read
717 http://openocd.sourceforge.net/doc/doxygen/bugs.html
718 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
719 (mfg: 0x23b, part: 0xba00, ver: 0x3)
720 @end example
722 Seeing that "tap/device found" message, and no warnings, means
723 the JTAG communication is working. That's a key milestone, but
724 you'll probably need more project-specific setup.
726 @section What OpenOCD does as it starts
728 OpenOCD starts by processing the configuration commands provided
729 on the command line or, if there were no @option{-c command} or
730 @option{-f file.cfg} options given, in @file{openocd.cfg}.
731 @xref{configurationstage,,Configuration Stage}.
732 At the end of the configuration stage it verifies the JTAG scan
733 chain defined using those commands; your configuration should
734 ensure that this always succeeds.
735 Normally, OpenOCD then starts running as a daemon.
736 Alternatively, commands may be used to terminate the configuration
737 stage early, perform work (such as updating some flash memory),
738 and then shut down without acting as a daemon.
740 Once OpenOCD starts running as a daemon, it waits for connections from
741 clients (Telnet, GDB, Other) and processes the commands issued through
742 those channels.
744 If you are having problems, you can enable internal debug messages via
745 the @option{-d} option.
747 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
748 @option{-c} command line switch.
750 To enable debug output (when reporting problems or working on OpenOCD
751 itself), use the @option{-d} command line switch. This sets the
752 @option{debug_level} to "3", outputting the most information,
753 including debug messages. The default setting is "2", outputting only
754 informational messages, warnings and errors. You can also change this
755 setting from within a telnet or gdb session using @command{debug_level<n>}
756 (@pxref{debuglevel,,debug_level}).
758 You can redirect all output from the daemon to a file using the
759 @option{-l <logfile>} switch.
761 Note! OpenOCD will launch the GDB & telnet server even if it can not
762 establish a connection with the target. In general, it is possible for
763 the JTAG controller to be unresponsive until the target is set up
764 correctly via e.g. GDB monitor commands in a GDB init script.
766 @node OpenOCD Project Setup
767 @chapter OpenOCD Project Setup
769 To use OpenOCD with your development projects, you need to do more than
770 just connecting the JTAG adapter hardware (dongle) to your development board
771 and then starting the OpenOCD server.
772 You also need to configure that server so that it knows
773 about that adapter and board, and helps your work.
774 You may also want to connect OpenOCD to GDB, possibly
775 using Eclipse or some other GUI.
777 @section Hooking up the JTAG Adapter
779 Today's most common case is a dongle with a JTAG cable on one side
780 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
781 and a USB cable on the other.
782 Instead of USB, some cables use Ethernet;
783 older ones may use a PC parallel port, or even a serial port.
785 @enumerate
786 @item @emph{Start with power to your target board turned off},
787 and nothing connected to your JTAG adapter.
788 If you're particularly paranoid, unplug power to the board.
789 It's important to have the ground signal properly set up,
790 unless you are using a JTAG adapter which provides
791 galvanic isolation between the target board and the
792 debugging host.
794 @item @emph{Be sure it's the right kind of JTAG connector.}
795 If your dongle has a 20-pin ARM connector, you need some kind
796 of adapter (or octopus, see below) to hook it up to
797 boards using 14-pin or 10-pin connectors ... or to 20-pin
798 connectors which don't use ARM's pinout.
800 In the same vein, make sure the voltage levels are compatible.
801 Not all JTAG adapters have the level shifters needed to work
802 with 1.2 Volt boards.
804 @item @emph{Be certain the cable is properly oriented} or you might
805 damage your board. In most cases there are only two possible
806 ways to connect the cable.
807 Connect the JTAG cable from your adapter to the board.
808 Be sure it's firmly connected.
810 In the best case, the connector is keyed to physically
811 prevent you from inserting it wrong.
812 This is most often done using a slot on the board's male connector
813 housing, which must match a key on the JTAG cable's female connector.
814 If there's no housing, then you must look carefully and
815 make sure pin 1 on the cable hooks up to pin 1 on the board.
816 Ribbon cables are frequently all grey except for a wire on one
817 edge, which is red. The red wire is pin 1.
819 Sometimes dongles provide cables where one end is an ``octopus'' of
820 color coded single-wire connectors, instead of a connector block.
821 These are great when converting from one JTAG pinout to another,
822 but are tedious to set up.
823 Use these with connector pinout diagrams to help you match up the
824 adapter signals to the right board pins.
826 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
827 A USB, parallel, or serial port connector will go to the host which
828 you are using to run OpenOCD.
829 For Ethernet, consult the documentation and your network administrator.
831 For USB based JTAG adapters you have an easy sanity check at this point:
832 does the host operating system see the JTAG adapter? If that host is an
833 MS-Windows host, you'll need to install a driver before OpenOCD works.
835 @item @emph{Connect the adapter's power supply, if needed.}
836 This step is primarily for non-USB adapters,
837 but sometimes USB adapters need extra power.
839 @item @emph{Power up the target board.}
840 Unless you just let the magic smoke escape,
841 you're now ready to set up the OpenOCD server
842 so you can use JTAG to work with that board.
844 @end enumerate
846 Talk with the OpenOCD server using
847 telnet (@code{telnet localhost 4444} on many systems) or GDB.
848 @xref{GDB and OpenOCD}.
850 @section Project Directory
852 There are many ways you can configure OpenOCD and start it up.
854 A simple way to organize them all involves keeping a
855 single directory for your work with a given board.
856 When you start OpenOCD from that directory,
857 it searches there first for configuration files, scripts,
858 files accessed through semihosting,
859 and for code you upload to the target board.
860 It is also the natural place to write files,
861 such as log files and data you download from the board.
863 @section Configuration Basics
865 There are two basic ways of configuring OpenOCD, and
866 a variety of ways you can mix them.
867 Think of the difference as just being how you start the server:
869 @itemize
870 @item Many @option{-f file} or @option{-c command} options on the command line
871 @item No options, but a @dfn{user config file}
872 in the current directory named @file{openocd.cfg}
873 @end itemize
875 Here is an example @file{openocd.cfg} file for a setup
876 using a Signalyzer FT2232-based JTAG adapter to talk to
877 a board with an Atmel AT91SAM7X256 microcontroller:
879 @example
880 source [find interface/signalyzer.cfg]
882 # GDB can also flash my flash!
883 gdb_memory_map enable
884 gdb_flash_program enable
886 source [find target/sam7x256.cfg]
887 @end example
889 Here is the command line equivalent of that configuration:
891 @example
892 openocd -f interface/signalyzer.cfg \
893 -c "gdb_memory_map enable" \
894 -c "gdb_flash_program enable" \
895 -f target/sam7x256.cfg
896 @end example
898 You could wrap such long command lines in shell scripts,
899 each supporting a different development task.
900 One might re-flash the board with a specific firmware version.
901 Another might set up a particular debugging or run-time environment.
903 @quotation Important
904 At this writing (October 2009) the command line method has
905 problems with how it treats variables.
906 For example, after @option{-c "set VAR value"}, or doing the
907 same in a script, the variable @var{VAR} will have no value
908 that can be tested in a later script.
909 @end quotation
911 Here we will focus on the simpler solution: one user config
912 file, including basic configuration plus any TCL procedures
913 to simplify your work.
915 @section User Config Files
916 @cindex config file, user
917 @cindex user config file
918 @cindex config file, overview
920 A user configuration file ties together all the parts of a project
921 in one place.
922 One of the following will match your situation best:
924 @itemize
925 @item Ideally almost everything comes from configuration files
926 provided by someone else.
927 For example, OpenOCD distributes a @file{scripts} directory
928 (probably in @file{/usr/share/openocd/scripts} on Linux).
929 Board and tool vendors can provide these too, as can individual
930 user sites; the @option{-s} command line option lets you say
931 where to find these files. (@xref{Running}.)
932 The AT91SAM7X256 example above works this way.
934 Three main types of non-user configuration file each have their
935 own subdirectory in the @file{scripts} directory:
937 @enumerate
938 @item @b{interface} -- one for each different debug adapter;
939 @item @b{board} -- one for each different board
940 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
941 @end enumerate
943 Best case: include just two files, and they handle everything else.
944 The first is an interface config file.
945 The second is board-specific, and it sets up the JTAG TAPs and
946 their GDB targets (by deferring to some @file{target.cfg} file),
947 declares all flash memory, and leaves you nothing to do except
948 meet your deadline:
950 @example
951 source [find interface/olimex-jtag-tiny.cfg]
952 source [find board/csb337.cfg]
953 @end example
955 Boards with a single microcontroller often won't need more
956 than the target config file, as in the AT91SAM7X256 example.
957 That's because there is no external memory (flash, DDR RAM), and
958 the board differences are encapsulated by application code.
960 @item Maybe you don't know yet what your board looks like to JTAG.
961 Once you know the @file{interface.cfg} file to use, you may
962 need help from OpenOCD to discover what's on the board.
963 Once you find the JTAG TAPs, you can just search for appropriate
964 target and board
965 configuration files ... or write your own, from the bottom up.
966 @xref{autoprobing,,Autoprobing}.
968 @item You can often reuse some standard config files but
969 need to write a few new ones, probably a @file{board.cfg} file.
970 You will be using commands described later in this User's Guide,
971 and working with the guidelines in the next chapter.
973 For example, there may be configuration files for your JTAG adapter
974 and target chip, but you need a new board-specific config file
975 giving access to your particular flash chips.
976 Or you might need to write another target chip configuration file
977 for a new chip built around the Cortex M3 core.
979 @quotation Note
980 When you write new configuration files, please submit
981 them for inclusion in the next OpenOCD release.
982 For example, a @file{board/newboard.cfg} file will help the
983 next users of that board, and a @file{target/newcpu.cfg}
984 will help support users of any board using that chip.
985 @end quotation
987 @item
988 You may may need to write some C code.
989 It may be as simple as a supporting a new ft2232 or parport
990 based adapter; a bit more involved, like a NAND or NOR flash
991 controller driver; or a big piece of work like supporting
992 a new chip architecture.
993 @end itemize
995 Reuse the existing config files when you can.
996 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
997 You may find a board configuration that's a good example to follow.
999 When you write config files, separate the reusable parts
1000 (things every user of that interface, chip, or board needs)
1001 from ones specific to your environment and debugging approach.
1002 @itemize
1004 @item
1005 For example, a @code{gdb-attach} event handler that invokes
1006 the @command{reset init} command will interfere with debugging
1007 early boot code, which performs some of the same actions
1008 that the @code{reset-init} event handler does.
1010 @item
1011 Likewise, the @command{arm9 vector_catch} command (or
1012 @cindex vector_catch
1013 its siblings @command{xscale vector_catch}
1014 and @command{cortex_m vector_catch}) can be a timesaver
1015 during some debug sessions, but don't make everyone use that either.
1016 Keep those kinds of debugging aids in your user config file,
1017 along with messaging and tracing setup.
1018 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1020 @item
1021 You might need to override some defaults.
1022 For example, you might need to move, shrink, or back up the target's
1023 work area if your application needs much SRAM.
1025 @item
1026 TCP/IP port configuration is another example of something which
1027 is environment-specific, and should only appear in
1028 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1029 @end itemize
1031 @section Project-Specific Utilities
1033 A few project-specific utility
1034 routines may well speed up your work.
1035 Write them, and keep them in your project's user config file.
1037 For example, if you are making a boot loader work on a
1038 board, it's nice to be able to debug the ``after it's
1039 loaded to RAM'' parts separately from the finicky early
1040 code which sets up the DDR RAM controller and clocks.
1041 A script like this one, or a more GDB-aware sibling,
1042 may help:
1044 @example
1045 proc ramboot @{ @} @{
1046 # Reset, running the target's "reset-init" scripts
1047 # to initialize clocks and the DDR RAM controller.
1048 # Leave the CPU halted.
1049 reset init
1051 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1052 load_image u-boot.bin 0x20000000
1054 # Start running.
1055 resume 0x20000000
1056 @}
1057 @end example
1059 Then once that code is working you will need to make it
1060 boot from NOR flash; a different utility would help.
1061 Alternatively, some developers write to flash using GDB.
1062 (You might use a similar script if you're working with a flash
1063 based microcontroller application instead of a boot loader.)
1065 @example
1066 proc newboot @{ @} @{
1067 # Reset, leaving the CPU halted. The "reset-init" event
1068 # proc gives faster access to the CPU and to NOR flash;
1069 # "reset halt" would be slower.
1070 reset init
1072 # Write standard version of U-Boot into the first two
1073 # sectors of NOR flash ... the standard version should
1074 # do the same lowlevel init as "reset-init".
1075 flash protect 0 0 1 off
1076 flash erase_sector 0 0 1
1077 flash write_bank 0 u-boot.bin 0x0
1078 flash protect 0 0 1 on
1080 # Reboot from scratch using that new boot loader.
1081 reset run
1082 @}
1083 @end example
1085 You may need more complicated utility procedures when booting
1086 from NAND.
1087 That often involves an extra bootloader stage,
1088 running from on-chip SRAM to perform DDR RAM setup so it can load
1089 the main bootloader code (which won't fit into that SRAM).
1091 Other helper scripts might be used to write production system images,
1092 involving considerably more than just a three stage bootloader.
1094 @section Target Software Changes
1096 Sometimes you may want to make some small changes to the software
1097 you're developing, to help make JTAG debugging work better.
1098 For example, in C or assembly language code you might
1099 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1100 handling issues like:
1102 @itemize @bullet
1104 @item @b{Watchdog Timers}...
1105 Watchog timers are typically used to automatically reset systems if
1106 some application task doesn't periodically reset the timer. (The
1107 assumption is that the system has locked up if the task can't run.)
1108 When a JTAG debugger halts the system, that task won't be able to run
1109 and reset the timer ... potentially causing resets in the middle of
1110 your debug sessions.
1112 It's rarely a good idea to disable such watchdogs, since their usage
1113 needs to be debugged just like all other parts of your firmware.
1114 That might however be your only option.
1116 Look instead for chip-specific ways to stop the watchdog from counting
1117 while the system is in a debug halt state. It may be simplest to set
1118 that non-counting mode in your debugger startup scripts. You may however
1119 need a different approach when, for example, a motor could be physically
1120 damaged by firmware remaining inactive in a debug halt state. That might
1121 involve a type of firmware mode where that "non-counting" mode is disabled
1122 at the beginning then re-enabled at the end; a watchdog reset might fire
1123 and complicate the debug session, but hardware (or people) would be
1124 protected.@footnote{Note that many systems support a "monitor mode" debug
1125 that is a somewhat cleaner way to address such issues. You can think of
1126 it as only halting part of the system, maybe just one task,
1127 instead of the whole thing.
1128 At this writing, January 2010, OpenOCD based debugging does not support
1129 monitor mode debug, only "halt mode" debug.}
1131 @item @b{ARM Semihosting}...
1132 @cindex ARM semihosting
1133 When linked with a special runtime library provided with many
1134 toolchains@footnote{See chapter 8 "Semihosting" in
1135 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1136 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1137 The CodeSourcery EABI toolchain also includes a semihosting library.},
1138 your target code can use I/O facilities on the debug host. That library
1139 provides a small set of system calls which are handled by OpenOCD.
1140 It can let the debugger provide your system console and a file system,
1141 helping with early debugging or providing a more capable environment
1142 for sometimes-complex tasks like installing system firmware onto
1143 NAND or SPI flash.
1145 @item @b{ARM Wait-For-Interrupt}...
1146 Many ARM chips synchronize the JTAG clock using the core clock.
1147 Low power states which stop that core clock thus prevent JTAG access.
1148 Idle loops in tasking environments often enter those low power states
1149 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1151 You may want to @emph{disable that instruction} in source code,
1152 or otherwise prevent using that state,
1153 to ensure you can get JTAG access at any time.@footnote{As a more
1154 polite alternative, some processors have special debug-oriented
1155 registers which can be used to change various features including
1156 how the low power states are clocked while debugging.
1157 The STM32 DBGMCU_CR register is an example; at the cost of extra
1158 power consumption, JTAG can be used during low power states.}
1159 For example, the OpenOCD @command{halt} command may not
1160 work for an idle processor otherwise.
1162 @item @b{Delay after reset}...
1163 Not all chips have good support for debugger access
1164 right after reset; many LPC2xxx chips have issues here.
1165 Similarly, applications that reconfigure pins used for
1166 JTAG access as they start will also block debugger access.
1168 To work with boards like this, @emph{enable a short delay loop}
1169 the first thing after reset, before "real" startup activities.
1170 For example, one second's delay is usually more than enough
1171 time for a JTAG debugger to attach, so that
1172 early code execution can be debugged
1173 or firmware can be replaced.
1175 @item @b{Debug Communications Channel (DCC)}...
1176 Some processors include mechanisms to send messages over JTAG.
1177 Many ARM cores support these, as do some cores from other vendors.
1178 (OpenOCD may be able to use this DCC internally, speeding up some
1179 operations like writing to memory.)
1181 Your application may want to deliver various debugging messages
1182 over JTAG, by @emph{linking with a small library of code}
1183 provided with OpenOCD and using the utilities there to send
1184 various kinds of message.
1185 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1187 @end itemize
1189 @section Target Hardware Setup
1191 Chip vendors often provide software development boards which
1192 are highly configurable, so that they can support all options
1193 that product boards may require. @emph{Make sure that any
1194 jumpers or switches match the system configuration you are
1195 working with.}
1197 Common issues include:
1199 @itemize @bullet
1201 @item @b{JTAG setup} ...
1202 Boards may support more than one JTAG configuration.
1203 Examples include jumpers controlling pullups versus pulldowns
1204 on the nTRST and/or nSRST signals, and choice of connectors
1205 (e.g. which of two headers on the base board,
1206 or one from a daughtercard).
1207 For some Texas Instruments boards, you may need to jumper the
1208 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1210 @item @b{Boot Modes} ...
1211 Complex chips often support multiple boot modes, controlled
1212 by external jumpers. Make sure this is set up correctly.
1213 For example many i.MX boards from NXP need to be jumpered
1214 to "ATX mode" to start booting using the on-chip ROM, when
1215 using second stage bootloader code stored in a NAND flash chip.
1217 Such explicit configuration is common, and not limited to
1218 booting from NAND. You might also need to set jumpers to
1219 start booting using code loaded from an MMC/SD card; external
1220 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1221 flash; some external host; or various other sources.
1224 @item @b{Memory Addressing} ...
1225 Boards which support multiple boot modes may also have jumpers
1226 to configure memory addressing. One board, for example, jumpers
1227 external chipselect 0 (used for booting) to address either
1228 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1229 or NAND flash. When it's jumpered to address NAND flash, that
1230 board must also be told to start booting from on-chip ROM.
1232 Your @file{board.cfg} file may also need to be told this jumper
1233 configuration, so that it can know whether to declare NOR flash
1234 using @command{flash bank} or instead declare NAND flash with
1235 @command{nand device}; and likewise which probe to perform in
1236 its @code{reset-init} handler.
1238 A closely related issue is bus width. Jumpers might need to
1239 distinguish between 8 bit or 16 bit bus access for the flash
1240 used to start booting.
1242 @item @b{Peripheral Access} ...
1243 Development boards generally provide access to every peripheral
1244 on the chip, sometimes in multiple modes (such as by providing
1245 multiple audio codec chips).
1246 This interacts with software
1247 configuration of pin multiplexing, where for example a
1248 given pin may be routed either to the MMC/SD controller
1249 or the GPIO controller. It also often interacts with
1250 configuration jumpers. One jumper may be used to route
1251 signals to an MMC/SD card slot or an expansion bus (which
1252 might in turn affect booting); others might control which
1253 audio or video codecs are used.
1255 @end itemize
1257 Plus you should of course have @code{reset-init} event handlers
1258 which set up the hardware to match that jumper configuration.
1259 That includes in particular any oscillator or PLL used to clock
1260 the CPU, and any memory controllers needed to access external
1261 memory and peripherals. Without such handlers, you won't be
1262 able to access those resources without working target firmware
1263 which can do that setup ... this can be awkward when you're
1264 trying to debug that target firmware. Even if there's a ROM
1265 bootloader which handles a few issues, it rarely provides full
1266 access to all board-specific capabilities.
1269 @node Config File Guidelines
1270 @chapter Config File Guidelines
1272 This chapter is aimed at any user who needs to write a config file,
1273 including developers and integrators of OpenOCD and any user who
1274 needs to get a new board working smoothly.
1275 It provides guidelines for creating those files.
1277 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1278 with files including the ones listed here.
1279 Use them as-is where you can; or as models for new files.
1280 @itemize @bullet
1281 @item @file{interface} ...
1282 These are for debug adapters.
1283 Files that configure JTAG adapters go here.
1284 @example
1285 $ ls interface -R
1286 interface/:
1287 altera-usb-blaster.cfg hilscher_nxhx50_re.cfg openocd-usb-hs.cfg
1288 arm-jtag-ew.cfg hitex_str9-comstick.cfg openrd.cfg
1289 at91rm9200.cfg icebear.cfg osbdm.cfg
1290 axm0432.cfg jlink.cfg parport.cfg
1291 busblaster.cfg jtagkey2.cfg parport_dlc5.cfg
1292 buspirate.cfg jtagkey2p.cfg redbee-econotag.cfg
1293 calao-usb-a9260-c01.cfg jtagkey.cfg redbee-usb.cfg
1294 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg rlink.cfg
1295 calao-usb-a9260.cfg jtag-lock-pick_tiny_2.cfg sheevaplug.cfg
1296 chameleon.cfg kt-link.cfg signalyzer.cfg
1297 cortino.cfg lisa-l.cfg signalyzer-h2.cfg
1298 digilent-hs1.cfg luminary.cfg signalyzer-h4.cfg
1299 dlp-usb1232h.cfg luminary-icdi.cfg signalyzer-lite.cfg
1300 dummy.cfg luminary-lm3s811.cfg stlink-v1.cfg
1301 estick.cfg minimodule.cfg stlink-v2.cfg
1302 flashlink.cfg neodb.cfg stm32-stick.cfg
1303 flossjtag.cfg ngxtech.cfg sysfsgpio-raspberrypi.cfg
1304 flossjtag-noeeprom.cfg olimex-arm-usb-ocd.cfg ti-icdi.cfg
1305 flyswatter2.cfg olimex-arm-usb-ocd-h.cfg turtelizer2.cfg
1306 flyswatter.cfg olimex-arm-usb-tiny-h.cfg ulink.cfg
1307 ftdi olimex-jtag-tiny.cfg usb-jtag.cfg
1308 hilscher_nxhx10_etm.cfg oocdlink.cfg usbprog.cfg
1309 hilscher_nxhx500_etm.cfg opendous.cfg vpaclink.cfg
1310 hilscher_nxhx500_re.cfg opendous_ftdi.cfg vsllink.cfg
1311 hilscher_nxhx50_etm.cfg openocd-usb.cfg xds100v2.cfg
1313 interface/ftdi:
1314 axm0432.cfg hitex_str9-comstick.cfg olimex-jtag-tiny.cfg
1315 calao-usb-a9260-c01.cfg icebear.cfg oocdlink.cfg
1316 calao-usb-a9260-c02.cfg jtagkey2.cfg opendous_ftdi.cfg
1317 cortino.cfg jtagkey2p.cfg openocd-usb.cfg
1318 dlp-usb1232h.cfg jtagkey.cfg openocd-usb-hs.cfg
1319 dp_busblaster.cfg jtag-lock-pick_tiny_2.cfg openrd.cfg
1320 flossjtag.cfg kt-link.cfg redbee-econotag.cfg
1321 flossjtag-noeeprom.cfg lisa-l.cfg redbee-usb.cfg
1322 flyswatter2.cfg luminary.cfg sheevaplug.cfg
1323 flyswatter.cfg luminary-icdi.cfg signalyzer.cfg
1324 gw16042.cfg luminary-lm3s811.cfg signalyzer-lite.cfg
1325 hilscher_nxhx10_etm.cfg minimodule.cfg stm32-stick.cfg
1326 hilscher_nxhx500_etm.cfg neodb.cfg turtelizer2-revB.cfg
1327 hilscher_nxhx500_re.cfg ngxtech.cfg turtelizer2-revC.cfg
1328 hilscher_nxhx50_etm.cfg olimex-arm-usb-ocd.cfg vpaclink.cfg
1329 hilscher_nxhx50_re.cfg olimex-arm-usb-ocd-h.cfg xds100v2.cfg
1330 hitex_lpc1768stick.cfg olimex-arm-usb-tiny-h.cfg
1331 $
1332 @end example
1333 @item @file{board} ...
1334 think Circuit Board, PWA, PCB, they go by many names. Board files
1335 contain initialization items that are specific to a board.
1336 They reuse target configuration files, since the same
1337 microprocessor chips are used on many boards,
1338 but support for external parts varies widely. For
1339 example, the SDRAM initialization sequence for the board, or the type
1340 of external flash and what address it uses. Any initialization
1341 sequence to enable that external flash or SDRAM should be found in the
1342 board file. Boards may also contain multiple targets: two CPUs; or
1343 a CPU and an FPGA.
1344 @example
1345 $ ls board
1346 actux3.cfg lpc1850_spifi_generic.cfg
1347 am3517evm.cfg lpc4350_spifi_generic.cfg
1348 arm_evaluator7t.cfg lubbock.cfg
1349 at91cap7a-stk-sdram.cfg mcb1700.cfg
1350 at91eb40a.cfg microchip_explorer16.cfg
1351 at91rm9200-dk.cfg mini2440.cfg
1352 at91rm9200-ek.cfg mini6410.cfg
1353 at91sam9261-ek.cfg netgear-dg834v3.cfg
1354 at91sam9263-ek.cfg olimex_LPC2378STK.cfg
1355 at91sam9g20-ek.cfg olimex_lpc_h2148.cfg
1356 atmel_at91sam7s-ek.cfg olimex_sam7_ex256.cfg
1357 atmel_at91sam9260-ek.cfg olimex_sam9_l9260.cfg
1358 atmel_at91sam9rl-ek.cfg olimex_stm32_h103.cfg
1359 atmel_sam3n_ek.cfg olimex_stm32_h107.cfg
1360 atmel_sam3s_ek.cfg olimex_stm32_p107.cfg
1361 atmel_sam3u_ek.cfg omap2420_h4.cfg
1362 atmel_sam3x_ek.cfg open-bldc.cfg
1363 atmel_sam4s_ek.cfg openrd.cfg
1364 balloon3-cpu.cfg osk5912.cfg
1365 colibri.cfg phone_se_j100i.cfg
1366 crossbow_tech_imote2.cfg phytec_lpc3250.cfg
1367 csb337.cfg pic-p32mx.cfg
1368 csb732.cfg propox_mmnet1001.cfg
1369 da850evm.cfg pxa255_sst.cfg
1370 digi_connectcore_wi-9c.cfg redbee.cfg
1371 diolan_lpc4350-db1.cfg rsc-w910.cfg
1372 dm355evm.cfg sheevaplug.cfg
1373 dm365evm.cfg smdk6410.cfg
1374 dm6446evm.cfg spear300evb.cfg
1375 efikamx.cfg spear300evb_mod.cfg
1376 eir.cfg spear310evb20.cfg
1377 ek-lm3s1968.cfg spear310evb20_mod.cfg
1378 ek-lm3s3748.cfg spear320cpu.cfg
1379 ek-lm3s6965.cfg spear320cpu_mod.cfg
1380 ek-lm3s811.cfg steval_pcc010.cfg
1381 ek-lm3s811-revb.cfg stm320518_eval_stlink.cfg
1382 ek-lm3s8962.cfg stm32100b_eval.cfg
1383 ek-lm3s9b9x.cfg stm3210b_eval.cfg
1384 ek-lm3s9d92.cfg stm3210c_eval.cfg
1385 ek-lm4f120xl.cfg stm3210e_eval.cfg
1386 ek-lm4f232.cfg stm3220g_eval.cfg
1387 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1388 ethernut3.cfg stm3241g_eval.cfg
1389 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1390 hammer.cfg stm32f0discovery.cfg
1391 hilscher_nxdb500sys.cfg stm32f3discovery.cfg
1392 hilscher_nxeb500hmi.cfg stm32f4discovery.cfg
1393 hilscher_nxhx10.cfg stm32ldiscovery.cfg
1394 hilscher_nxhx500.cfg stm32vldiscovery.cfg
1395 hilscher_nxhx50.cfg str910-eval.cfg
1396 hilscher_nxsb100.cfg telo.cfg
1397 hitex_lpc1768stick.cfg ti_am335xevm.cfg
1398 hitex_lpc2929.cfg ti_beagleboard.cfg
1399 hitex_stm32-performancestick.cfg ti_beagleboard_xm.cfg
1400 hitex_str9-comstick.cfg ti_beaglebone.cfg
1401 iar_lpc1768.cfg ti_blaze.cfg
1402 iar_str912_sk.cfg ti_pandaboard.cfg
1403 icnova_imx53_sodimm.cfg ti_pandaboard_es.cfg
1404 icnova_sam9g45_sodimm.cfg topas910.cfg
1405 imx27ads.cfg topasa900.cfg
1406 imx27lnst.cfg twr-k60f120m.cfg
1407 imx28evk.cfg twr-k60n512.cfg
1408 imx31pdk.cfg tx25_stk5.cfg
1409 imx35pdk.cfg tx27_stk5.cfg
1410 imx53loco.cfg unknown_at91sam9260.cfg
1411 keil_mcb1700.cfg uptech_2410.cfg
1412 keil_mcb2140.cfg verdex.cfg
1413 kwikstik.cfg voipac.cfg
1414 linksys_nslu2.cfg voltcraft_dso-3062c.cfg
1415 lisa-l.cfg x300t.cfg
1416 logicpd_imx27.cfg zy1000.cfg
1417 $
1418 @end example
1419 @item @file{target} ...
1420 think chip. The ``target'' directory represents the JTAG TAPs
1421 on a chip
1422 which OpenOCD should control, not a board. Two common types of targets
1423 are ARM chips and FPGA or CPLD chips.
1424 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1425 the target config file defines all of them.
1426 @example
1427 $ ls target
1428 aduc702x.cfg lpc1763.cfg
1429 am335x.cfg lpc1764.cfg
1430 amdm37x.cfg lpc1765.cfg
1431 ar71xx.cfg lpc1766.cfg
1432 at32ap7000.cfg lpc1767.cfg
1433 at91r40008.cfg lpc1768.cfg
1434 at91rm9200.cfg lpc1769.cfg
1435 at91sam3ax_4x.cfg lpc1788.cfg
1436 at91sam3ax_8x.cfg lpc17xx.cfg
1437 at91sam3ax_xx.cfg lpc1850.cfg
1438 at91sam3nXX.cfg lpc2103.cfg
1439 at91sam3sXX.cfg lpc2124.cfg
1440 at91sam3u1c.cfg lpc2129.cfg
1441 at91sam3u1e.cfg lpc2148.cfg
1442 at91sam3u2c.cfg lpc2294.cfg
1443 at91sam3u2e.cfg lpc2378.cfg
1444 at91sam3u4c.cfg lpc2460.cfg
1445 at91sam3u4e.cfg lpc2478.cfg
1446 at91sam3uxx.cfg lpc2900.cfg
1447 at91sam3XXX.cfg lpc2xxx.cfg
1448 at91sam4sd32x.cfg lpc3131.cfg
1449 at91sam4sXX.cfg lpc3250.cfg
1450 at91sam4XXX.cfg lpc4350.cfg
1451 at91sam7se512.cfg lpc4350.cfg.orig
1452 at91sam7sx.cfg mc13224v.cfg
1453 at91sam7x256.cfg nuc910.cfg
1454 at91sam7x512.cfg omap2420.cfg
1455 at91sam9260.cfg omap3530.cfg
1456 at91sam9260_ext_RAM_ext_flash.cfg omap4430.cfg
1457 at91sam9261.cfg omap4460.cfg
1458 at91sam9263.cfg omap5912.cfg
1459 at91sam9.cfg omapl138.cfg
1460 at91sam9g10.cfg pic32mx.cfg
1461 at91sam9g20.cfg pxa255.cfg
1462 at91sam9g45.cfg pxa270.cfg
1463 at91sam9rl.cfg pxa3xx.cfg
1464 atmega128.cfg readme.txt
1465 avr32.cfg samsung_s3c2410.cfg
1466 c100.cfg samsung_s3c2440.cfg
1467 c100config.tcl samsung_s3c2450.cfg
1468 c100helper.tcl samsung_s3c4510.cfg
1469 c100regs.tcl samsung_s3c6410.cfg
1470 cs351x.cfg sharp_lh79532.cfg
1471 davinci.cfg smp8634.cfg
1472 dragonite.cfg spear3xx.cfg
1473 dsp56321.cfg stellaris.cfg
1474 dsp568013.cfg stellaris_icdi.cfg
1475 dsp568037.cfg stm32f0x_stlink.cfg
1476 efm32_stlink.cfg stm32f1x.cfg
1477 epc9301.cfg stm32f1x_stlink.cfg
1478 faux.cfg stm32f2x.cfg
1479 feroceon.cfg stm32f2x_stlink.cfg
1480 fm3.cfg stm32f3x.cfg
1481 hilscher_netx10.cfg stm32f3x_stlink.cfg
1482 hilscher_netx500.cfg stm32f4x.cfg
1483 hilscher_netx50.cfg stm32f4x_stlink.cfg
1484 icepick.cfg stm32l.cfg
1485 imx21.cfg stm32lx_dual_bank.cfg
1486 imx25.cfg stm32lx_stlink.cfg
1487 imx27.cfg stm32_stlink.cfg
1488 imx28.cfg stm32w108_stlink.cfg
1489 imx31.cfg stm32xl.cfg
1490 imx35.cfg str710.cfg
1491 imx51.cfg str730.cfg
1492 imx53.cfg str750.cfg
1493 imx6.cfg str912.cfg
1494 imx.cfg swj-dp.tcl
1495 is5114.cfg test_reset_syntax_error.cfg
1496 ixp42x.cfg test_syntax_error.cfg
1497 k40.cfg ti-ar7.cfg
1498 k60.cfg ti_calypso.cfg
1499 lpc1751.cfg ti_dm355.cfg
1500 lpc1752.cfg ti_dm365.cfg
1501 lpc1754.cfg ti_dm6446.cfg
1502 lpc1756.cfg tmpa900.cfg
1503 lpc1758.cfg tmpa910.cfg
1504 lpc1759.cfg u8500.cfg
1505 @end example
1506 @item @emph{more} ... browse for other library files which may be useful.
1507 For example, there are various generic and CPU-specific utilities.
1508 @end itemize
1510 The @file{openocd.cfg} user config
1511 file may override features in any of the above files by
1512 setting variables before sourcing the target file, or by adding
1513 commands specific to their situation.
1515 @section Interface Config Files
1517 The user config file
1518 should be able to source one of these files with a command like this:
1520 @example
1521 source [find interface/FOOBAR.cfg]
1522 @end example
1524 A preconfigured interface file should exist for every debug adapter
1525 in use today with OpenOCD.
1526 That said, perhaps some of these config files
1527 have only been used by the developer who created it.
1529 A separate chapter gives information about how to set these up.
1530 @xref{Debug Adapter Configuration}.
1531 Read the OpenOCD source code (and Developer's Guide)
1532 if you have a new kind of hardware interface
1533 and need to provide a driver for it.
1535 @section Board Config Files
1536 @cindex config file, board
1537 @cindex board config file
1539 The user config file
1540 should be able to source one of these files with a command like this:
1542 @example
1543 source [find board/FOOBAR.cfg]
1544 @end example
1546 The point of a board config file is to package everything
1547 about a given board that user config files need to know.
1548 In summary the board files should contain (if present)
1550 @enumerate
1551 @item One or more @command{source [target/...cfg]} statements
1552 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1553 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1554 @item Target @code{reset} handlers for SDRAM and I/O configuration
1555 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1556 @item All things that are not ``inside a chip''
1557 @end enumerate
1559 Generic things inside target chips belong in target config files,
1560 not board config files. So for example a @code{reset-init} event
1561 handler should know board-specific oscillator and PLL parameters,
1562 which it passes to target-specific utility code.
1564 The most complex task of a board config file is creating such a
1565 @code{reset-init} event handler.
1566 Define those handlers last, after you verify the rest of the board
1567 configuration works.
1569 @subsection Communication Between Config files
1571 In addition to target-specific utility code, another way that
1572 board and target config files communicate is by following a
1573 convention on how to use certain variables.
1575 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1576 Thus the rule we follow in OpenOCD is this: Variables that begin with
1577 a leading underscore are temporary in nature, and can be modified and
1578 used at will within a target configuration file.
1580 Complex board config files can do the things like this,
1581 for a board with three chips:
1583 @example
1584 # Chip #1: PXA270 for network side, big endian
1585 set CHIPNAME network
1586 set ENDIAN big
1587 source [find target/pxa270.cfg]
1588 # on return: _TARGETNAME = network.cpu
1589 # other commands can refer to the "network.cpu" target.
1590 $_TARGETNAME configure .... events for this CPU..
1592 # Chip #2: PXA270 for video side, little endian
1593 set CHIPNAME video
1594 set ENDIAN little
1595 source [find target/pxa270.cfg]
1596 # on return: _TARGETNAME = video.cpu
1597 # other commands can refer to the "video.cpu" target.
1598 $_TARGETNAME configure .... events for this CPU..
1600 # Chip #3: Xilinx FPGA for glue logic
1601 set CHIPNAME xilinx
1602 unset ENDIAN
1603 source [find target/spartan3.cfg]
1604 @end example
1606 That example is oversimplified because it doesn't show any flash memory,
1607 or the @code{reset-init} event handlers to initialize external DRAM
1608 or (assuming it needs it) load a configuration into the FPGA.
1609 Such features are usually needed for low-level work with many boards,
1610 where ``low level'' implies that the board initialization software may
1611 not be working. (That's a common reason to need JTAG tools. Another
1612 is to enable working with microcontroller-based systems, which often
1613 have no debugging support except a JTAG connector.)
1615 Target config files may also export utility functions to board and user
1616 config files. Such functions should use name prefixes, to help avoid
1617 naming collisions.
1619 Board files could also accept input variables from user config files.
1620 For example, there might be a @code{J4_JUMPER} setting used to identify
1621 what kind of flash memory a development board is using, or how to set
1622 up other clocks and peripherals.
1624 @subsection Variable Naming Convention
1625 @cindex variable names
1627 Most boards have only one instance of a chip.
1628 However, it should be easy to create a board with more than
1629 one such chip (as shown above).
1630 Accordingly, we encourage these conventions for naming
1631 variables associated with different @file{target.cfg} files,
1632 to promote consistency and
1633 so that board files can override target defaults.
1635 Inputs to target config files include:
1637 @itemize @bullet
1638 @item @code{CHIPNAME} ...
1639 This gives a name to the overall chip, and is used as part of
1640 tap identifier dotted names.
1641 While the default is normally provided by the chip manufacturer,
1642 board files may need to distinguish between instances of a chip.
1643 @item @code{ENDIAN} ...
1644 By default @option{little} - although chips may hard-wire @option{big}.
1645 Chips that can't change endianness don't need to use this variable.
1646 @item @code{CPUTAPID} ...
1647 When OpenOCD examines the JTAG chain, it can be told verify the
1648 chips against the JTAG IDCODE register.
1649 The target file will hold one or more defaults, but sometimes the
1650 chip in a board will use a different ID (perhaps a newer revision).
1651 @end itemize
1653 Outputs from target config files include:
1655 @itemize @bullet
1656 @item @code{_TARGETNAME} ...
1657 By convention, this variable is created by the target configuration
1658 script. The board configuration file may make use of this variable to
1659 configure things like a ``reset init'' script, or other things
1660 specific to that board and that target.
1661 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1662 @code{_TARGETNAME1}, ... etc.
1663 @end itemize
1665 @subsection The reset-init Event Handler
1666 @cindex event, reset-init
1667 @cindex reset-init handler
1669 Board config files run in the OpenOCD configuration stage;
1670 they can't use TAPs or targets, since they haven't been
1671 fully set up yet.
1672 This means you can't write memory or access chip registers;
1673 you can't even verify that a flash chip is present.
1674 That's done later in event handlers, of which the target @code{reset-init}
1675 handler is one of the most important.
1677 Except on microcontrollers, the basic job of @code{reset-init} event
1678 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1679 Microcontrollers rarely use boot loaders; they run right out of their
1680 on-chip flash and SRAM memory. But they may want to use one of these
1681 handlers too, if just for developer convenience.
1683 @quotation Note
1684 Because this is so very board-specific, and chip-specific, no examples
1685 are included here.
1686 Instead, look at the board config files distributed with OpenOCD.
1687 If you have a boot loader, its source code will help; so will
1688 configuration files for other JTAG tools
1689 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1690 @end quotation
1692 Some of this code could probably be shared between different boards.
1693 For example, setting up a DRAM controller often doesn't differ by
1694 much except the bus width (16 bits or 32?) and memory timings, so a
1695 reusable TCL procedure loaded by the @file{target.cfg} file might take
1696 those as parameters.
1697 Similarly with oscillator, PLL, and clock setup;
1698 and disabling the watchdog.
1699 Structure the code cleanly, and provide comments to help
1700 the next developer doing such work.
1701 (@emph{You might be that next person} trying to reuse init code!)
1703 The last thing normally done in a @code{reset-init} handler is probing
1704 whatever flash memory was configured. For most chips that needs to be
1705 done while the associated target is halted, either because JTAG memory
1706 access uses the CPU or to prevent conflicting CPU access.
1708 @subsection JTAG Clock Rate
1710 Before your @code{reset-init} handler has set up
1711 the PLLs and clocking, you may need to run with
1712 a low JTAG clock rate.
1713 @xref{jtagspeed,,JTAG Speed}.
1714 Then you'd increase that rate after your handler has
1715 made it possible to use the faster JTAG clock.
1716 When the initial low speed is board-specific, for example
1717 because it depends on a board-specific oscillator speed, then
1718 you should probably set it up in the board config file;
1719 if it's target-specific, it belongs in the target config file.
1721 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1722 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1723 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1724 Consult chip documentation to determine the peak JTAG clock rate,
1725 which might be less than that.
1727 @quotation Warning
1728 On most ARMs, JTAG clock detection is coupled to the core clock, so
1729 software using a @option{wait for interrupt} operation blocks JTAG access.
1730 Adaptive clocking provides a partial workaround, but a more complete
1731 solution just avoids using that instruction with JTAG debuggers.
1732 @end quotation
1734 If both the chip and the board support adaptive clocking,
1735 use the @command{jtag_rclk}
1736 command, in case your board is used with JTAG adapter which
1737 also supports it. Otherwise use @command{adapter_khz}.
1738 Set the slow rate at the beginning of the reset sequence,
1739 and the faster rate as soon as the clocks are at full speed.
1741 @anchor{theinitboardprocedure}
1742 @subsection The init_board procedure
1743 @cindex init_board procedure
1745 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1746 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1747 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1748 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1749 spearate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1750 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1751 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1752 Additionally ``linear'' board config file will most likely fail when target config file uses
1753 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1754 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1755 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1756 need to override @code{init_targets} defined in target config files when they only need to to add some specifics.
1758 Just as @code{init_targets}, the @code{init_board} procedure can be overriden by ``next level'' script (which sources
1759 the original), allowing greater code reuse.
1761 @example
1762 ### board_file.cfg ###
1764 # source target file that does most of the config in init_targets
1765 source [find target/target.cfg]
1767 proc enable_fast_clock @{@} @{
1768 # enables fast on-board clock source
1769 # configures the chip to use it
1770 @}
1772 # initialize only board specifics - reset, clock, adapter frequency
1773 proc init_board @{@} @{
1774 reset_config trst_and_srst trst_pulls_srst
1776 $_TARGETNAME configure -event reset-init @{
1777 adapter_khz 1
1778 enable_fast_clock
1779 adapter_khz 10000
1780 @}
1781 @}
1782 @end example
1784 @section Target Config Files
1785 @cindex config file, target
1786 @cindex target config file
1788 Board config files communicate with target config files using
1789 naming conventions as described above, and may source one or
1790 more target config files like this:
1792 @example
1793 source [find target/FOOBAR.cfg]
1794 @end example
1796 The point of a target config file is to package everything
1797 about a given chip that board config files need to know.
1798 In summary the target files should contain
1800 @enumerate
1801 @item Set defaults
1802 @item Add TAPs to the scan chain
1803 @item Add CPU targets (includes GDB support)
1804 @item CPU/Chip/CPU-Core specific features
1805 @item On-Chip flash
1806 @end enumerate
1808 As a rule of thumb, a target file sets up only one chip.
1809 For a microcontroller, that will often include a single TAP,
1810 which is a CPU needing a GDB target, and its on-chip flash.
1812 More complex chips may include multiple TAPs, and the target
1813 config file may need to define them all before OpenOCD
1814 can talk to the chip.
1815 For example, some phone chips have JTAG scan chains that include
1816 an ARM core for operating system use, a DSP,
1817 another ARM core embedded in an image processing engine,
1818 and other processing engines.
1820 @subsection Default Value Boiler Plate Code
1822 All target configuration files should start with code like this,
1823 letting board config files express environment-specific
1824 differences in how things should be set up.
1826 @example
1827 # Boards may override chip names, perhaps based on role,
1828 # but the default should match what the vendor uses
1829 if @{ [info exists CHIPNAME] @} @{
1831 @} else @{
1832 set _CHIPNAME sam7x256
1833 @}
1835 # ONLY use ENDIAN with targets that can change it.
1836 if @{ [info exists ENDIAN] @} @{
1837 set _ENDIAN $ENDIAN
1838 @} else @{
1839 set _ENDIAN little
1840 @}
1842 # TAP identifiers may change as chips mature, for example with
1843 # new revision fields (the "3" here). Pick a good default; you
1844 # can pass several such identifiers to the "jtag newtap" command.
1845 if @{ [info exists CPUTAPID ] @} @{
1847 @} else @{
1848 set _CPUTAPID 0x3f0f0f0f
1849 @}
1850 @end example
1851 @c but 0x3f0f0f0f is for an str73x part ...
1853 @emph{Remember:} Board config files may include multiple target
1854 config files, or the same target file multiple times
1855 (changing at least @code{CHIPNAME}).
1857 Likewise, the target configuration file should define
1858 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1859 use it later on when defining debug targets:
1861 @example
1863 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1864 @end example
1866 @subsection Adding TAPs to the Scan Chain
1867 After the ``defaults'' are set up,
1868 add the TAPs on each chip to the JTAG scan chain.
1869 @xref{TAP Declaration}, and the naming convention
1870 for taps.
1872 In the simplest case the chip has only one TAP,
1873 probably for a CPU or FPGA.
1874 The config file for the Atmel AT91SAM7X256
1875 looks (in part) like this:
1877 @example
1878 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1879 @end example
1881 A board with two such at91sam7 chips would be able
1882 to source such a config file twice, with different
1883 values for @code{CHIPNAME}, so
1884 it adds a different TAP each time.
1886 If there are nonzero @option{-expected-id} values,
1887 OpenOCD attempts to verify the actual tap id against those values.
1888 It will issue error messages if there is mismatch, which
1889 can help to pinpoint problems in OpenOCD configurations.
1891 @example
1892 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1893 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1894 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1895 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1896 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1897 @end example
1899 There are more complex examples too, with chips that have
1900 multiple TAPs. Ones worth looking at include:
1902 @itemize
1903 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1904 plus a JRC to enable them
1905 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1906 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1907 is not currently used)
1908 @end itemize
1910 @subsection Add CPU targets
1912 After adding a TAP for a CPU, you should set it up so that
1913 GDB and other commands can use it.
1914 @xref{CPU Configuration}.
1915 For the at91sam7 example above, the command can look like this;
1916 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1917 to little endian, and this chip doesn't support changing that.
1919 @example
1921 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1922 @end example
1924 Work areas are small RAM areas associated with CPU targets.
1925 They are used by OpenOCD to speed up downloads,
1926 and to download small snippets of code to program flash chips.
1927 If the chip includes a form of ``on-chip-ram'' - and many do - define
1928 a work area if you can.
1929 Again using the at91sam7 as an example, this can look like:
1931 @example
1932 $_TARGETNAME configure -work-area-phys 0x00200000 \
1933 -work-area-size 0x4000 -work-area-backup 0
1934 @end example
1936 @anchor{definecputargetsworkinginsmp}
1937 @subsection Define CPU targets working in SMP
1938 @cindex SMP
1939 After setting targets, you can define a list of targets working in SMP.
1941 @example
1942 set _TARGETNAME_1 $_CHIPNAME.cpu1
1943 set _TARGETNAME_2 $_CHIPNAME.cpu2
1944 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1945 -coreid 0 -dbgbase $_DAP_DBG1
1946 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1947 -coreid 1 -dbgbase $_DAP_DBG2
1948 #define 2 targets working in smp.
1949 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1950 @end example
1951 In the above example on cortex_a, 2 cpus are working in SMP.
1952 In SMP only one GDB instance is created and :
1953 @itemize @bullet
1954 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1955 @item halt command triggers the halt of all targets in the list.
1956 @item resume command triggers the write context and the restart of all targets in the list.
1957 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1958 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1959 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1960 @end itemize
1962 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1963 command have been implemented.
1964 @itemize @bullet
1965 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1966 @item cortex_a smp_off : disable SMP mode, the current target is the one
1967 displayed in the GDB session, only this target is now controlled by GDB
1968 session. This behaviour is useful during system boot up.
1969 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1970 following example.
1971 @end itemize
1973 @example
1974 >cortex_a smp_gdb
1975 gdb coreid 0 -> -1
1976 #0 : coreid 0 is displayed to GDB ,
1977 #-> -1 : next resume triggers a real resume
1978 > cortex_a smp_gdb 1
1979 gdb coreid 0 -> 1
1980 #0 :coreid 0 is displayed to GDB ,
1981 #->1 : next resume displays coreid 1 to GDB
1982 > resume
1983 > cortex_a smp_gdb
1984 gdb coreid 1 -> 1
1985 #1 :coreid 1 is displayed to GDB ,
1986 #->1 : next resume displays coreid 1 to GDB
1987 > cortex_a smp_gdb -1
1988 gdb coreid 1 -> -1
1989 #1 :coreid 1 is displayed to GDB,
1990 #->-1 : next resume triggers a real resume
1991 @end example
1994 @subsection Chip Reset Setup
1996 As a rule, you should put the @command{reset_config} command
1997 into the board file. Most things you think you know about a
1998 chip can be tweaked by the board.
2000 Some chips have specific ways the TRST and SRST signals are
2001 managed. In the unusual case that these are @emph{chip specific}
2002 and can never be changed by board wiring, they could go here.
2003 For example, some chips can't support JTAG debugging without
2004 both signals.
2006 Provide a @code{reset-assert} event handler if you can.
2007 Such a handler uses JTAG operations to reset the target,
2008 letting this target config be used in systems which don't
2009 provide the optional SRST signal, or on systems where you
2010 don't want to reset all targets at once.
2011 Such a handler might write to chip registers to force a reset,
2012 use a JRC to do that (preferable -- the target may be wedged!),
2013 or force a watchdog timer to trigger.
2014 (For Cortex-M targets, this is not necessary. The target
2015 driver knows how to use trigger an NVIC reset when SRST is
2016 not available.)
2018 Some chips need special attention during reset handling if
2019 they're going to be used with JTAG.
2020 An example might be needing to send some commands right
2021 after the target's TAP has been reset, providing a
2022 @code{reset-deassert-post} event handler that writes a chip
2023 register to report that JTAG debugging is being done.
2024 Another would be reconfiguring the watchdog so that it stops
2025 counting while the core is halted in the debugger.
2027 JTAG clocking constraints often change during reset, and in
2028 some cases target config files (rather than board config files)
2029 are the right places to handle some of those issues.
2030 For example, immediately after reset most chips run using a
2031 slower clock than they will use later.
2032 That means that after reset (and potentially, as OpenOCD
2033 first starts up) they must use a slower JTAG clock rate
2034 than they will use later.
2035 @xref{jtagspeed,,JTAG Speed}.
2037 @quotation Important
2038 When you are debugging code that runs right after chip
2039 reset, getting these issues right is critical.
2040 In particular, if you see intermittent failures when
2041 OpenOCD verifies the scan chain after reset,
2042 look at how you are setting up JTAG clocking.
2043 @end quotation
2045 @anchor{theinittargetsprocedure}
2046 @subsection The init_targets procedure
2047 @cindex init_targets procedure
2049 Target config files can either be ``linear'' (script executed line-by-line when parsed in
2050 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
2051 procedure called @code{init_targets}, which will be executed when entering run stage
2052 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
2053 Such procedure can be overriden by ``next level'' script (which sources the original).
2054 This concept faciliates code reuse when basic target config files provide generic configuration
2055 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
2056 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
2057 because sourcing them executes every initialization commands they provide.
2059 @example
2060 ### generic_file.cfg ###
2062 proc setup_my_chip @{chip_name flash_size ram_size@} @{
2063 # basic initialization procedure ...
2064 @}
2066 proc init_targets @{@} @{
2067 # initializes generic chip with 4kB of flash and 1kB of RAM
2068 setup_my_chip MY_GENERIC_CHIP 4096 1024
2069 @}
2071 ### specific_file.cfg ###
2073 source [find target/generic_file.cfg]
2075 proc init_targets @{@} @{
2076 # initializes specific chip with 128kB of flash and 64kB of RAM
2077 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
2078 @}
2079 @end example
2081 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
2082 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
2084 For an example of this scheme see LPC2000 target config files.
2086 The @code{init_boards} procedure is a similar concept concerning board config files
2087 (@xref{theinitboardprocedure,,The init_board procedure}.)
2089 @subsection ARM Core Specific Hacks
2091 If the chip has a DCC, enable it. If the chip is an ARM9 with some
2092 special high speed download features - enable it.
2094 If present, the MMU, the MPU and the CACHE should be disabled.
2096 Some ARM cores are equipped with trace support, which permits
2097 examination of the instruction and data bus activity. Trace
2098 activity is controlled through an ``Embedded Trace Module'' (ETM)
2099 on one of the core's scan chains. The ETM emits voluminous data
2100 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
2101 If you are using an external trace port,
2102 configure it in your board config file.
2103 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2104 configure it in your target config file.
2106 @example
2107 etm config $_TARGETNAME 16 normal full etb
2108 etb config $_TARGETNAME $_CHIPNAME.etb
2109 @end example
2111 @subsection Internal Flash Configuration
2113 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2115 @b{Never ever} in the ``target configuration file'' define any type of
2116 flash that is external to the chip. (For example a BOOT flash on
2117 Chip Select 0.) Such flash information goes in a board file - not
2118 the TARGET (chip) file.
2120 Examples:
2121 @itemize @bullet
2122 @item at91sam7x256 - has 256K flash YES enable it.
2123 @item str912 - has flash internal YES enable it.
2124 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2125 @item pxa270 - again - CS0 flash - it goes in the board file.
2126 @end itemize
2128 @anchor{translatingconfigurationfiles}
2129 @section Translating Configuration Files
2130 @cindex translation
2131 If you have a configuration file for another hardware debugger
2132 or toolset (Abatron, BDI2000, BDI3000, CCS,
2133 Lauterbach, Segger, Macraigor, etc.), translating
2134 it into OpenOCD syntax is often quite straightforward. The most tricky
2135 part of creating a configuration script is oftentimes the reset init
2136 sequence where e.g. PLLs, DRAM and the like is set up.
2138 One trick that you can use when translating is to write small
2139 Tcl procedures to translate the syntax into OpenOCD syntax. This
2140 can avoid manual translation errors and make it easier to
2141 convert other scripts later on.
2143 Example of transforming quirky arguments to a simple search and
2144 replace job:
2146 @example
2147 # Lauterbach syntax(?)
2148 #
2149 # Data.Set c15:0x042f %long 0x40000015
2150 #
2151 # OpenOCD syntax when using procedure below.
2152 #
2153 # setc15 0x01 0x00050078
2155 proc setc15 @{regs value@} @{
2156 global TARGETNAME
2158 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2160 arm mcr 15 [expr ($regs>>12)&0x7] \
2161 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2162 [expr ($regs>>8)&0x7] $value
2163 @}
2164 @end example
2168 @node Daemon Configuration
2169 @chapter Daemon Configuration
2170 @cindex initialization
2171 The commands here are commonly found in the openocd.cfg file and are
2172 used to specify what TCP/IP ports are used, and how GDB should be
2173 supported.
2175 @anchor{configurationstage}
2176 @section Configuration Stage
2177 @cindex configuration stage
2178 @cindex config command
2180 When the OpenOCD server process starts up, it enters a
2181 @emph{configuration stage} which is the only time that
2182 certain commands, @emph{configuration commands}, may be issued.
2183 Normally, configuration commands are only available
2184 inside startup scripts.
2186 In this manual, the definition of a configuration command is
2187 presented as a @emph{Config Command}, not as a @emph{Command}
2188 which may be issued interactively.
2189 The runtime @command{help} command also highlights configuration
2190 commands, and those which may be issued at any time.
2192 Those configuration commands include declaration of TAPs,
2193 flash banks,
2194 the interface used for JTAG communication,
2195 and other basic setup.
2196 The server must leave the configuration stage before it
2197 may access or activate TAPs.
2198 After it leaves this stage, configuration commands may no
2199 longer be issued.
2201 @anchor{enteringtherunstage}
2202 @section Entering the Run Stage
2204 The first thing OpenOCD does after leaving the configuration
2205 stage is to verify that it can talk to the scan chain
2206 (list of TAPs) which has been configured.
2207 It will warn if it doesn't find TAPs it expects to find,
2208 or finds TAPs that aren't supposed to be there.
2209 You should see no errors at this point.
2210 If you see errors, resolve them by correcting the
2211 commands you used to configure the server.
2212 Common errors include using an initial JTAG speed that's too
2213 fast, and not providing the right IDCODE values for the TAPs
2214 on the scan chain.
2216 Once OpenOCD has entered the run stage, a number of commands
2217 become available.
2218 A number of these relate to the debug targets you may have declared.
2219 For example, the @command{mww} command will not be available until
2220 a target has been successfuly instantiated.
2221 If you want to use those commands, you may need to force
2222 entry to the run stage.
2224 @deffn {Config Command} init
2225 This command terminates the configuration stage and
2226 enters the run stage. This helps when you need to have
2227 the startup scripts manage tasks such as resetting the target,
2228 programming flash, etc. To reset the CPU upon startup, add "init" and
2229 "reset" at the end of the config script or at the end of the OpenOCD
2230 command line using the @option{-c} command line switch.
2232 If this command does not appear in any startup/configuration file
2233 OpenOCD executes the command for you after processing all
2234 configuration files and/or command line options.
2236 @b{NOTE:} This command normally occurs at or near the end of your
2237 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2238 targets ready. For example: If your openocd.cfg file needs to
2239 read/write memory on your target, @command{init} must occur before
2240 the memory read/write commands. This includes @command{nand probe}.
2241 @end deffn
2243 @deffn {Overridable Procedure} jtag_init
2244 This is invoked at server startup to verify that it can talk
2245 to the scan chain (list of TAPs) which has been configured.
2247 The default implementation first tries @command{jtag arp_init},
2248 which uses only a lightweight JTAG reset before examining the
2249 scan chain.
2250 If that fails, it tries again, using a harder reset
2251 from the overridable procedure @command{init_reset}.
2253 Implementations must have verified the JTAG scan chain before
2254 they return.
2255 This is done by calling @command{jtag arp_init}
2256 (or @command{jtag arp_init-reset}).
2257 @end deffn
2259 @anchor{tcpipports}
2260 @section TCP/IP Ports
2261 @cindex TCP port
2262 @cindex server
2263 @cindex port
2264 @cindex security
2265 The OpenOCD server accepts remote commands in several syntaxes.
2266 Each syntax uses a different TCP/IP port, which you may specify
2267 only during configuration (before those ports are opened).
2269 For reasons including security, you may wish to prevent remote
2270 access using one or more of these ports.
2271 In such cases, just specify the relevant port number as zero.
2272 If you disable all access through TCP/IP, you will need to
2273 use the command line @option{-pipe} option.
2275 @deffn {Command} gdb_port [number]
2276 @cindex GDB server
2277 Normally gdb listens to a TCP/IP port, but GDB can also
2278 communicate via pipes(stdin/out or named pipes). The name
2279 "gdb_port" stuck because it covers probably more than 90% of
2280 the normal use cases.
2282 No arguments reports GDB port. "pipe" means listen to stdin
2283 output to stdout, an integer is base port number, "disable"
2284 disables the gdb server.
2286 When using "pipe", also use log_output to redirect the log
2287 output to a file so as not to flood the stdin/out pipes.
2289 The -p/--pipe option is deprecated and a warning is printed
2290 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2292 Any other string is interpreted as named pipe to listen to.
2293 Output pipe is the same name as input pipe, but with 'o' appended,
2294 e.g. /var/gdb, /var/gdbo.
2296 The GDB port for the first target will be the base port, the
2297 second target will listen on gdb_port + 1, and so on.
2298 When not specified during the configuration stage,
2299 the port @var{number} defaults to 3333.
2300 @end deffn
2302 @deffn {Command} tcl_port [number]
2303 Specify or query the port used for a simplified RPC
2304 connection that can be used by clients to issue TCL commands and get the
2305 output from the Tcl engine.
2306 Intended as a machine interface.
2307 When not specified during the configuration stage,
2308 the port @var{number} defaults to 6666.
2310 @end deffn
2312 @deffn {Command} telnet_port [number]
2313 Specify or query the
2314 port on which to listen for incoming telnet connections.
2315 This port is intended for interaction with one human through TCL commands.
2316 When not specified during the configuration stage,
2317 the port @var{number} defaults to 4444.
2318 When specified as zero, this port is not activated.
2319 @end deffn
2321 @anchor{gdbconfiguration}
2322 @section GDB Configuration
2323 @cindex GDB
2324 @cindex GDB configuration
2325 You can reconfigure some GDB behaviors if needed.
2326 The ones listed here are static and global.
2327 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2328 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2330 @anchor{gdbbreakpointoverride}
2331 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2332 Force breakpoint type for gdb @command{break} commands.
2333 This option supports GDB GUIs which don't
2334 distinguish hard versus soft breakpoints, if the default OpenOCD and
2335 GDB behaviour is not sufficient. GDB normally uses hardware
2336 breakpoints if the memory map has been set up for flash regions.
2337 @end deffn
2339 @anchor{gdbflashprogram}
2340 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2341 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2342 vFlash packet is received.
2343 The default behaviour is @option{enable}.
2344 @end deffn
2346 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2347 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2348 requested. GDB will then know when to set hardware breakpoints, and program flash
2349 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2350 for flash programming to work.
2351 Default behaviour is @option{enable}.
2352 @xref{gdbflashprogram,,gdb_flash_program}.
2353 @end deffn
2355 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2356 Specifies whether data aborts cause an error to be reported
2357 by GDB memory read packets.
2358 The default behaviour is @option{disable};
2359 use @option{enable} see these errors reported.
2360 @end deffn
2362 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2363 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2364 The default behaviour is @option{disable}.
2365 @end deffn
2367 @deffn {Command} gdb_save_tdesc
2368 Saves the target descripton file to the local file system.
2370 The file name is @i{target_name}.xml.
2371 @end deffn
2373 @anchor{eventpolling}
2374 @section Event Polling
2376 Hardware debuggers are parts of asynchronous systems,
2377 where significant events can happen at any time.
2378 The OpenOCD server needs to detect some of these events,
2379 so it can report them to through TCL command line
2380 or to GDB.
2382 Examples of such events include:
2384 @itemize
2385 @item One of the targets can stop running ... maybe it triggers
2386 a code breakpoint or data watchpoint, or halts itself.
2387 @item Messages may be sent over ``debug message'' channels ... many
2388 targets support such messages sent over JTAG,
2389 for receipt by the person debugging or tools.
2390 @item Loss of power ... some adapters can detect these events.
2391 @item Resets not issued through JTAG ... such reset sources
2392 can include button presses or other system hardware, sometimes
2393 including the target itself (perhaps through a watchdog).
2394 @item Debug instrumentation sometimes supports event triggering
2395 such as ``trace buffer full'' (so it can quickly be emptied)
2396 or other signals (to correlate with code behavior).
2397 @end itemize
2399 None of those events are signaled through standard JTAG signals.
2400 However, most conventions for JTAG connectors include voltage
2401 level and system reset (SRST) signal detection.
2402 Some connectors also include instrumentation signals, which
2403 can imply events when those signals are inputs.
2405 In general, OpenOCD needs to periodically check for those events,
2406 either by looking at the status of signals on the JTAG connector
2407 or by sending synchronous ``tell me your status'' JTAG requests
2408 to the various active targets.
2409 There is a command to manage and monitor that polling,
2410 which is normally done in the background.
2412 @deffn Command poll [@option{on}|@option{off}]
2413 Poll the current target for its current state.
2414 (Also, @pxref{targetcurstate,,target curstate}.)
2415 If that target is in debug mode, architecture
2416 specific information about the current state is printed.
2417 An optional parameter
2418 allows background polling to be enabled and disabled.
2420 You could use this from the TCL command shell, or
2421 from GDB using @command{monitor poll} command.
2422 Leave background polling enabled while you're using GDB.
2423 @example
2424 > poll
2425 background polling: on
2426 target state: halted
2427 target halted in ARM state due to debug-request, \
2428 current mode: Supervisor
2429 cpsr: 0x800000d3 pc: 0x11081bfc
2430 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2431 >
2432 @end example
2433 @end deffn
2435 @node Debug Adapter Configuration
2436 @chapter Debug Adapter Configuration
2437 @cindex config file, interface
2438 @cindex interface config file
2440 Correctly installing OpenOCD includes making your operating system give
2441 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2442 are used to select which one is used, and to configure how it is used.
2444 @quotation Note
2445 Because OpenOCD started out with a focus purely on JTAG, you may find
2446 places where it wrongly presumes JTAG is the only transport protocol
2447 in use. Be aware that recent versions of OpenOCD are removing that
2448 limitation. JTAG remains more functional than most other transports.
2449 Other transports do not support boundary scan operations, or may be
2450 specific to a given chip vendor. Some might be usable only for
2451 programming flash memory, instead of also for debugging.
2452 @end quotation
2454 Debug Adapters/Interfaces/Dongles are normally configured
2455 through commands in an interface configuration
2456 file which is sourced by your @file{openocd.cfg} file, or
2457 through a command line @option{-f interface/....cfg} option.
2459 @example
2460 source [find interface/olimex-jtag-tiny.cfg]
2461 @end example
2463 These commands tell
2464 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2465 A few cases are so simple that you only need to say what driver to use:
2467 @example
2468 # jlink interface
2469 interface jlink
2470 @end example
2472 Most adapters need a bit more configuration than that.
2475 @section Interface Configuration
2477 The interface command tells OpenOCD what type of debug adapter you are
2478 using. Depending on the type of adapter, you may need to use one or
2479 more additional commands to further identify or configure the adapter.
2481 @deffn {Config Command} {interface} name
2482 Use the interface driver @var{name} to connect to the
2483 target.
2484 @end deffn
2486 @deffn Command {interface_list}
2487 List the debug adapter drivers that have been built into
2488 the running copy of OpenOCD.
2489 @end deffn
2490 @deffn Command {interface transports} transport_name+
2491 Specifies the transports supported by this debug adapter.
2492 The adapter driver builds-in similar knowledge; use this only
2493 when external configuration (such as jumpering) changes what
2494 the hardware can support.
2495 @end deffn
2499 @deffn Command {adapter_name}
2500 Returns the name of the debug adapter driver being used.
2501 @end deffn
2503 @section Interface Drivers
2505 Each of the interface drivers listed here must be explicitly
2506 enabled when OpenOCD is configured, in order to be made
2507 available at run time.
2509 @deffn {Interface Driver} {amt_jtagaccel}
2510 Amontec Chameleon in its JTAG Accelerator configuration,
2511 connected to a PC's EPP mode parallel port.
2512 This defines some driver-specific commands:
2514 @deffn {Config Command} {parport_port} number
2515 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2516 the number of the @file{/dev/parport} device.
2517 @end deffn
2519 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2520 Displays status of RTCK option.
2521 Optionally sets that option first.
2522 @end deffn
2523 @end deffn
2525 @deffn {Interface Driver} {arm-jtag-ew}
2526 Olimex ARM-JTAG-EW USB adapter
2527 This has one driver-specific command:
2529 @deffn Command {armjtagew_info}
2530 Logs some status
2531 @end deffn
2532 @end deffn
2534 @deffn {Interface Driver} {at91rm9200}
2535 Supports bitbanged JTAG from the local system,
2536 presuming that system is an Atmel AT91rm9200
2537 and a specific set of GPIOs is used.
2538 @c command: at91rm9200_device NAME
2539 @c chooses among list of bit configs ... only one option
2540 @end deffn
2542 @deffn {Interface Driver} {dummy}
2543 A dummy software-only driver for debugging.
2544 @end deffn
2546 @deffn {Interface Driver} {ep93xx}
2547 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2548 @end deffn
2550 @deffn {Interface Driver} {ft2232}
2551 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2553 Note that this driver has several flaws and the @command{ftdi} driver is
2554 recommended as its replacement.
2556 These interfaces have several commands, used to configure the driver
2557 before initializing the JTAG scan chain:
2559 @deffn {Config Command} {ft2232_device_desc} description
2560 Provides the USB device description (the @emph{iProduct string})
2561 of the FTDI FT2232 device. If not
2562 specified, the FTDI default value is used. This setting is only valid
2563 if compiled with FTD2XX support.
2564 @end deffn
2566 @deffn {Config Command} {ft2232_serial} serial-number
2567 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2568 in case the vendor provides unique IDs and more than one FT2232 device
2569 is connected to the host.
2570 If not specified, serial numbers are not considered.
2571 (Note that USB serial numbers can be arbitrary Unicode strings,
2572 and are not restricted to containing only decimal digits.)
2573 @end deffn
2575 @deffn {Config Command} {ft2232_layout} name
2576 Each vendor's FT2232 device can use different GPIO signals
2577 to control output-enables, reset signals, and LEDs.
2578 Currently valid layout @var{name} values include:
2579 @itemize @minus
2580 @item @b{axm0432_jtag} Axiom AXM-0432
2581 @item @b{comstick} Hitex STR9 comstick
2582 @item @b{cortino} Hitex Cortino JTAG interface
2583 @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
2584 either for the local Cortex-M3 (SRST only)
2585 or in a passthrough mode (neither SRST nor TRST)
2586 This layout can not support the SWO trace mechanism, and should be
2587 used only for older boards (before rev C).
2588 @item @b{luminary_icdi} This layout should be used with most TI/Luminary
2589 eval boards, including Rev C LM3S811 eval boards and the eponymous
2590 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2591 to debug some other target. It can support the SWO trace mechanism.
2592 @item @b{flyswatter} Tin Can Tools Flyswatter
2593 @item @b{icebear} ICEbear JTAG adapter from Section 5
2594 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2595 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2596 @item @b{m5960} American Microsystems M5960
2597 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2598 @item @b{oocdlink} OOCDLink
2599 @c oocdlink ~= jtagkey_prototype_v1
2600 @item @b{redbee-econotag} Integrated with a Redbee development board.
2601 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2602 @item @b{sheevaplug} Marvell Sheevaplug development kit
2603 @item @b{signalyzer} Xverve Signalyzer
2604 @item @b{stm32stick} Hitex STM32 Performance Stick
2605 @item @b{turtelizer2} egnite Software turtelizer2
2606 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2607 @end itemize
2608 @end deffn
2610 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2611 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2612 default values are used.
2613 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2614 @example
2615 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2616 @end example
2617 @end deffn
2619 @deffn {Config Command} {ft2232_latency} ms
2620 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2621 ft2232_read() fails to return the expected number of bytes. This can be caused by
2622 USB communication delays and has proved hard to reproduce and debug. Setting the
2623 FT2232 latency timer to a larger value increases delays for short USB packets but it
2624 also reduces the risk of timeouts before receiving the expected number of bytes.
2625 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2626 @end deffn
2628 @deffn {Config Command} {ft2232_channel} channel
2629 Used to select the channel of the ft2232 chip to use (between 1 and 4).
2630 The default value is 1.
2631 @end deffn
2633 For example, the interface config file for a
2634 Turtelizer JTAG Adapter looks something like this:
2636 @example
2637 interface ft2232
2638 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2639 ft2232_layout turtelizer2
2640 ft2232_vid_pid 0x0403 0xbdc8
2641 @end example
2642 @end deffn
2644 @deffn {Interface Driver} {ftdi}
2645 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2646 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2647 It is a complete rewrite to address a large number of problems with the ft2232
2648 interface driver.
2650 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2651 bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
2652 consistently faster than the ft2232 driver, sometimes several times faster.
2654 A major improvement of this driver is that support for new FTDI based adapters
2655 can be added competely through configuration files, without the need to patch
2656 and rebuild OpenOCD.
2658 The driver uses a signal abstraction to enable Tcl configuration files to
2659 define outputs for one or several FTDI GPIO. These outputs can then be
2660 controlled using the @command{ftdi_set_signal} command. Special signal names
2661 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2662 will be used for their customary purpose.
2664 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2665 be controlled differently. In order to support tristateable signals such as
2666 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2667 signal. The following output buffer configurations are supported:
2669 @itemize @minus
2670 @item Push-pull with one FTDI output as (non-)inverted data line
2671 @item Open drain with one FTDI output as (non-)inverted output-enable
2672 @item Tristate with one FTDI output as (non-)inverted data line and another
2673 FTDI output as (non-)inverted output-enable
2674 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2675 switching data and direction as necessary
2676 @end itemize
2678 These interfaces have several commands, used to configure the driver
2679 before initializing the JTAG scan chain:
2681 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2682 The vendor ID and product ID of the adapter. If not specified, the FTDI
2683 default values are used.
2684 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2685 @example
2686 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2687 @end example
2688 @end deffn
2690 @deffn {Config Command} {ftdi_device_desc} description
2691 Provides the USB device description (the @emph{iProduct string})
2692 of the adapter. If not specified, the device description is ignored
2693 during device selection.
2694 @end deffn
2696 @deffn {Config Command} {ftdi_serial} serial-number
2697 Specifies the @var{serial-number} of the adapter to use,
2698 in case the vendor provides unique IDs and more than one adapter
2699 is connected to the host.
2700 If not specified, serial numbers are not considered.
2701 (Note that USB serial numbers can be arbitrary Unicode strings,
2702 and are not restricted to containing only decimal digits.)
2703 @end deffn
2705 @deffn {Config Command} {ftdi_channel} channel
2706 Selects the channel of the FTDI device to use for MPSSE operations. Most
2707 adapters use the default, channel 0, but there are exceptions.
2708 @end deffn
2710 @deffn {Config Command} {ftdi_layout_init} data direction
2711 Specifies the initial values of the FTDI GPIO data and direction registers.
2712 Each value is a 16-bit number corresponding to the concatenation of the high
2713 and low FTDI GPIO registers. The values should be selected based on the
2714 schematics of the adapter, such that all signals are set to safe levels with
2715 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2716 and initially asserted reset signals.
2717 @end deffn
2719 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask]
2720 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2721 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2722 register bitmasks to tell the driver the connection and type of the output
2723 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2724 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2725 used with inverting data inputs and @option{-data} with non-inverting inputs.
2726 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2727 not-output-enable) input to the output buffer is connected.
2729 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2730 simple open-collector transistor driver would be specified with @option{-oe}
2731 only. In that case the signal can only be set to drive low or to Hi-Z and the
2732 driver will complain if the signal is set to drive high. Which means that if
2733 it's a reset signal, @command{reset_config} must be specified as
2734 @option{srst_open_drain}, not @option{srst_push_pull}.
2736 A special case is provided when @option{-data} and @option{-oe} is set to the
2737 same bitmask. Then the FTDI pin is considered being connected straight to the
2738 target without any buffer. The FTDI pin is then switched between output and
2739 input as necessary to provide the full set of low, high and Hi-Z
2740 characteristics. In all other cases, the pins specified in a signal definition
2741 are always driven by the FTDI.
2742 @end deffn
2744 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2745 Set a previously defined signal to the specified level.
2746 @itemize @minus
2747 @item @option{0}, drive low
2748 @item @option{1}, drive high
2749 @item @option{z}, set to high-impedance
2750 @end itemize
2751 @end deffn
2753 For example adapter definitions, see the configuration files shipped in the
2754 @file{interface/ftdi} directory.
2755 @end deffn
2757 @deffn {Interface Driver} {remote_bitbang}
2758 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2759 with a remote process and sends ASCII encoded bitbang requests to that process
2760 instead of directly driving JTAG.
2762 The remote_bitbang driver is useful for debugging software running on
2763 processors which are being simulated.
2765 @deffn {Config Command} {remote_bitbang_port} number
2766 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2767 sockets instead of TCP.
2768 @end deffn
2770 @deffn {Config Command} {remote_bitbang_host} hostname
2771 Specifies the hostname of the remote process to connect to using TCP, or the
2772 name of the UNIX socket to use if remote_bitbang_port is 0.
2773 @end deffn
2775 For example, to connect remotely via TCP to the host foobar you might have
2776 something like:
2778 @example
2779 interface remote_bitbang
2780 remote_bitbang_port 3335
2781 remote_bitbang_host foobar
2782 @end example
2784 To connect to another process running locally via UNIX sockets with socket
2785 named mysocket:
2787 @example
2788 interface remote_bitbang
2789 remote_bitbang_port 0
2790 remote_bitbang_host mysocket
2791 @end example
2792 @end deffn
2794 @deffn {Interface Driver} {usb_blaster}
2795 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2796 for FTDI chips. These interfaces have several commands, used to
2797 configure the driver before initializing the JTAG scan chain:
2799 @deffn {Config Command} {usb_blaster_device_desc} description
2800 Provides the USB device description (the @emph{iProduct string})
2801 of the FTDI FT245 device. If not
2802 specified, the FTDI default value is used. This setting is only valid
2803 if compiled with FTD2XX support.
2804 @end deffn
2806 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2807 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2808 default values are used.
2809 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2810 Altera USB-Blaster (default):
2811 @example
2812 usb_blaster_vid_pid 0x09FB 0x6001
2813 @end example
2814 The following VID/PID is for Kolja Waschk's USB JTAG:
2815 @example
2816 usb_blaster_vid_pid 0x16C0 0x06AD
2817 @end example
2818 @end deffn
2820 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2821 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2822 female JTAG header). These pins can be used as SRST and/or TRST provided the
2823 appropriate connections are made on the target board.
2825 For example, to use pin 6 as SRST (as with an AVR board):
2826 @example
2827 $_TARGETNAME configure -event reset-assert \
2828 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2829 @end example
2830 @end deffn
2832 @end deffn
2834 @deffn {Interface Driver} {gw16012}
2835 Gateworks GW16012 JTAG programmer.
2836 This has one driver-specific command:
2838 @deffn {Config Command} {parport_port} [port_number]
2839 Display either the address of the I/O port
2840 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2841 If a parameter is provided, first switch to use that port.
2842 This is a write-once setting.
2843 @end deffn
2844 @end deffn
2846 @deffn {Interface Driver} {jlink}
2847 Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
2849 @quotation Compatibility Note
2850 Segger released many firmware versions for the many harware versions they
2851 produced. OpenOCD was extensively tested and intended to run on all of them,
2852 but some combinations were reported as incompatible. As a general
2853 recommendation, it is advisable to use the latest firmware version
2854 available for each hardware version. However the current V8 is a moving
2855 target, and Segger firmware versions released after the OpenOCD was
2856 released may not be compatible. In such cases it is recommended to
2857 revert to the last known functional version. For 0.5.0, this is from
2858 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2859 version is from "May 3 2012 18:36:22", packed with 4.46f.
2860 @end quotation
2862 @deffn {Command} {jlink caps}
2863 Display the device firmware capabilities.
2864 @end deffn
2865 @deffn {Command} {jlink info}
2866 Display various device information, like hardware version, firmware version, current bus status.
2867 @end deffn
2868 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2869 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2870 @end deffn
2871 @deffn {Command} {jlink config}
2872 Display the J-Link configuration.
2873 @end deffn
2874 @deffn {Command} {jlink config kickstart} [val]
2875 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2876 @end deffn
2877 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2878 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2879 @end deffn
2880 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2881 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2882 E the bit of the subnet mask and
2883 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2884 @end deffn
2885 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2886 Set the USB address; this will also change the product id. Without argument, show the USB address.
2887 @end deffn
2888 @deffn {Command} {jlink config reset}
2889 Reset the current configuration.
2890 @end deffn
2891 @deffn {Command} {jlink config save}
2892 Save the current configuration to the internal persistent storage.
2893 @end deffn
2894 @deffn {Config} {jlink pid} val
2895 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2896 @end deffn
2897 @end deffn
2899 @deffn {Interface Driver} {parport}
2900 Supports PC parallel port bit-banging cables:
2901 Wigglers, PLD download cable, and more.
2902 These interfaces have several commands, used to configure the driver
2903 before initializing the JTAG scan chain:
2905 @deffn {Config Command} {parport_cable} name
2906 Set the layout of the parallel port cable used to connect to the target.
2907 This is a write-once setting.
2908 Currently valid cable @var{name} values include:
2910 @itemize @minus
2911 @item @b{altium} Altium Universal JTAG cable.
2912 @item @b{arm-jtag} Same as original wiggler except SRST and
2913 TRST connections reversed and TRST is also inverted.
2914 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2915 in configuration mode. This is only used to
2916 program the Chameleon itself, not a connected target.
2917 @item @b{dlc5} The Xilinx Parallel cable III.
2918 @item @b{flashlink} The ST Parallel cable.
2919 @item @b{lattice} Lattice ispDOWNLOAD Cable
2920 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2921 some versions of
2922 Amontec's Chameleon Programmer. The new version available from
2923 the website uses the original Wiggler layout ('@var{wiggler}')
2924 @item @b{triton} The parallel port adapter found on the
2925 ``Karo Triton 1 Development Board''.
2926 This is also the layout used by the HollyGates design
2927 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2928 @item @b{wiggler} The original Wiggler layout, also supported by
2929 several clones, such as the Olimex ARM-JTAG
2930 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2931 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2932 @end itemize
2933 @end deffn
2935 @deffn {Config Command} {parport_port} [port_number]
2936 Display either the address of the I/O port
2937 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2938 If a parameter is provided, first switch to use that port.
2939 This is a write-once setting.
2941 When using PPDEV to access the parallel port, use the number of the parallel port:
2942 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2943 you may encounter a problem.
2944 @end deffn
2946 @deffn Command {parport_toggling_time} [nanoseconds]
2947 Displays how many nanoseconds the hardware needs to toggle TCK;
2948 the parport driver uses this value to obey the
2949 @command{adapter_khz} configuration.
2950 When the optional @var{nanoseconds} parameter is given,
2951 that setting is changed before displaying the current value.
2953 The default setting should work reasonably well on commodity PC hardware.
2954 However, you may want to calibrate for your specific hardware.
2955 @quotation Tip
2956 To measure the toggling time with a logic analyzer or a digital storage
2957 oscilloscope, follow the procedure below:
2958 @example
2959 > parport_toggling_time 1000
2960 > adapter_khz 500
2961 @end example
2962 This sets the maximum JTAG clock speed of the hardware, but
2963 the actual speed probably deviates from the requested 500 kHz.
2964 Now, measure the time between the two closest spaced TCK transitions.
2965 You can use @command{runtest 1000} or something similar to generate a
2966 large set of samples.
2967 Update the setting to match your measurement:
2968 @example
2969 > parport_toggling_time <measured nanoseconds>
2970 @end example
2971 Now the clock speed will be a better match for @command{adapter_khz rate}
2972 commands given in OpenOCD scripts and event handlers.
2974 You can do something similar with many digital multimeters, but note
2975 that you'll probably need to run the clock continuously for several
2976 seconds before it decides what clock rate to show. Adjust the
2977 toggling time up or down until the measured clock rate is a good
2978 match for the adapter_khz rate you specified; be conservative.
2979 @end quotation
2980 @end deffn
2982 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2983 This will configure the parallel driver to write a known
2984 cable-specific value to the parallel interface on exiting OpenOCD.
2985 @end deffn
2987 For example, the interface configuration file for a
2988 classic ``Wiggler'' cable on LPT2 might look something like this:
2990 @example
2991 interface parport
2992 parport_port 0x278
2993 parport_cable wiggler
2994 @end example
2995 @end deffn
2997 @deffn {Interface Driver} {presto}
2998 ASIX PRESTO USB JTAG programmer.
2999 @deffn {Config Command} {presto_serial} serial_string
3000 Configures the USB serial number of the Presto device to use.
3001 @end deffn
3002 @end deffn
3004 @deffn {Interface Driver} {rlink}
3005 Raisonance RLink USB adapter
3006 @end deffn
3008 @deffn {Interface Driver} {usbprog}
3009 usbprog is a freely programmable USB adapter.
3010 @end deffn
3012 @deffn {Interface Driver} {vsllink}
3013 vsllink is part of Versaloon which is a versatile USB programmer.
3015 @quotation Note
3016 This defines quite a few driver-specific commands,
3017 which are not currently documented here.
3018 @end quotation
3019 @end deffn
3021 @deffn {Interface Driver} {hla}
3022 This is a driver that supports multiple High Level Adapters.
3023 This type of adapter does not expose some of the lower level api's
3024 that OpenOCD would normally use to access the target.
3026 Currently supported adapters include the ST STLINK and TI ICDI.
3028 @deffn {Config Command} {hla_device_desc} description
3029 Currently Not Supported.
3030 @end deffn
3032 @deffn {Config Command} {hla_serial} serial
3033 Currently Not Supported.
3034 @end deffn
3036 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
3037 Specifies the adapter layout to use.
3038 @end deffn
3040 @deffn {Config Command} {hla_vid_pid} vid pid
3041 The vendor ID and product ID of the device.
3042 @end deffn
3044 @deffn {Config Command} {trace} source_clock_hz [output_file_path]
3045 Enable SWO tracing (if supported). The source clock rate for the
3046 trace port must be specified, this is typically the CPU clock rate. If
3047 the optional output file is specified then raw trace data is appended
3048 to the file, and the file is created if it does not exist.
3049 @end deffn
3050 @end deffn
3052 @deffn {Interface Driver} {opendous}
3053 opendous-jtag is a freely programmable USB adapter.
3054 @end deffn
3056 @deffn {Interface Driver} {ulink}
3057 This is the Keil ULINK v1 JTAG debugger.
3058 @end deffn
3060 @deffn {Interface Driver} {ZY1000}
3061 This is the Zylin ZY1000 JTAG debugger.
3062 @end deffn
3064 @quotation Note
3065 This defines some driver-specific commands,
3066 which are not currently documented here.
3067 @end quotation
3069 @deffn Command power [@option{on}|@option{off}]
3070 Turn power switch to target on/off.
3071 No arguments: print status.
3072 @end deffn
3074 @deffn {Interface Driver} {bcm2835gpio}
3075 This SoC is present in Raspberry Pi which is a cheap single-board computer
3076 exposing some GPIOs on its expansion header.
3078 The driver accesses memory-mapped GPIO peripheral registers directly
3079 for maximum performance, but the only possible race condition is for
3080 the pins' modes/muxing (which is highly unlikely), so it should be
3081 able to coexist nicely with both sysfs bitbanging and various
3082 peripherals' kernel drivers. The driver restores the previous
3083 configuration on exit.
3085 See @file{interface/raspberrypi-native.cfg} for a sample config and
3086 pinout.
3088 @end deffn
3090 @section Transport Configuration
3091 @cindex Transport
3092 As noted earlier, depending on the version of OpenOCD you use,
3093 and the debug adapter you are using,
3094 several transports may be available to
3095 communicate with debug targets (or perhaps to program flash memory).
3096 @deffn Command {transport list}
3097 displays the names of the transports supported by this
3098 version of OpenOCD.
3099 @end deffn
3101 @deffn Command {transport select} transport_name
3102 Select which of the supported transports to use in this OpenOCD session.
3103 The transport must be supported by the debug adapter hardware and by the
3104 version of OpenOCD you are using (including the adapter's driver).
3105 No arguments: returns name of session's selected transport.
3106 @end deffn
3108 @subsection JTAG Transport
3109 @cindex JTAG
3110 JTAG is the original transport supported by OpenOCD, and most
3111 of the OpenOCD commands support it.
3112 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3113 each of which must be explicitly declared.
3114 JTAG supports both debugging and boundary scan testing.
3115 Flash programming support is built on top of debug support.
3116 @subsection SWD Transport
3117 @cindex SWD
3118 @cindex Serial Wire Debug
3119 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3120 Debug Access Point (DAP, which must be explicitly declared.
3121 (SWD uses fewer signal wires than JTAG.)
3122 SWD is debug-oriented, and does not support boundary scan testing.
3123 Flash programming support is built on top of debug support.
3124 (Some processors support both JTAG and SWD.)
3125 @deffn Command {swd newdap} ...
3126 Declares a single DAP which uses SWD transport.
3127 Parameters are currently the same as "jtag newtap" but this is
3128 expected to change.
3129 @end deffn
3130 @deffn Command {swd wcr trn prescale}
3131 Updates TRN (turnaraound delay) and prescaling.fields of the
3132 Wire Control Register (WCR).
3133 No parameters: displays current settings.
3134 @end deffn
3136 @subsection SPI Transport
3137 @cindex SPI
3138 @cindex Serial Peripheral Interface
3139 The Serial Peripheral Interface (SPI) is a general purpose transport
3140 which uses four wire signaling. Some processors use it as part of a
3141 solution for flash programming.
3143 @anchor{jtagspeed}
3144 @section JTAG Speed
3145 JTAG clock setup is part of system setup.
3146 It @emph{does not belong with interface setup} since any interface
3147 only knows a few of the constraints for the JTAG clock speed.
3148 Sometimes the JTAG speed is
3149 changed during the target initialization process: (1) slow at
3150 reset, (2) program the CPU clocks, (3) run fast.
3151 Both the "slow" and "fast" clock rates are functions of the
3152 oscillators used, the chip, the board design, and sometimes
3153 power management software that may be active.
3155 The speed used during reset, and the scan chain verification which
3156 follows reset, can be adjusted using a @code{reset-start}
3157 target event handler.
3158 It can then be reconfigured to a faster speed by a
3159 @code{reset-init} target event handler after it reprograms those
3160 CPU clocks, or manually (if something else, such as a boot loader,
3161 sets up those clocks).
3162 @xref{targetevents,,Target Events}.
3163 When the initial low JTAG speed is a chip characteristic, perhaps
3164 because of a required oscillator speed, provide such a handler
3165 in the target config file.
3166 When that speed is a function of a board-specific characteristic
3167 such as which speed oscillator is used, it belongs in the board
3168 config file instead.
3169 In both cases it's safest to also set the initial JTAG clock rate
3170 to that same slow speed, so that OpenOCD never starts up using a
3171 clock speed that's faster than the scan chain can support.
3173 @example
3174 jtag_rclk 3000
3175 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3176 @end example
3178 If your system supports adaptive clocking (RTCK), configuring
3179 JTAG to use that is probably the most robust approach.
3180 However, it introduces delays to synchronize clocks; so it
3181 may not be the fastest solution.
3183 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3184 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3185 which support adaptive clocking.
3187 @deffn {Command} adapter_khz max_speed_kHz
3188 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3189 JTAG interfaces usually support a limited number of
3190 speeds. The speed actually used won't be faster
3191 than the speed specified.
3193 Chip data sheets generally include a top JTAG clock rate.
3194 The actual rate is often a function of a CPU core clock,
3195 and is normally less than that peak rate.
3196 For example, most ARM cores accept at most one sixth of the CPU clock.
3198 Speed 0 (khz) selects RTCK method.
3199 @xref{faqrtck,,FAQ RTCK}.
3200 If your system uses RTCK, you won't need to change the
3201 JTAG clocking after setup.
3202 Not all interfaces, boards, or targets support ``rtck''.
3203 If the interface device can not
3204 support it, an error is returned when you try to use RTCK.
3205 @end deffn
3207 @defun jtag_rclk fallback_speed_kHz
3208 @cindex adaptive clocking
3209 @cindex RTCK
3210 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3211 If that fails (maybe the interface, board, or target doesn't
3212 support it), falls back to the specified frequency.
3213 @example
3214 # Fall back to 3mhz if RTCK is not supported
3215 jtag_rclk 3000
3216 @end example
3217 @end defun
3219 @node Reset Configuration
3220 @chapter Reset Configuration
3221 @cindex Reset Configuration
3223 Every system configuration may require a different reset
3224 configuration. This can also be quite confusing.
3225 Resets also interact with @var{reset-init} event handlers,
3226 which do things like setting up clocks and DRAM, and
3227 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3228 They can also interact with JTAG routers.
3229 Please see the various board files for examples.
3231 @quotation Note
3232 To maintainers and integrators:
3233 Reset configuration touches several things at once.
3234 Normally the board configuration file
3235 should define it and assume that the JTAG adapter supports
3236 everything that's wired up to the board's JTAG connector.
3238 However, the target configuration file could also make note
3239 of something the silicon vendor has done inside the chip,
3240 which will be true for most (or all) boards using that chip.
3241 And when the JTAG adapter doesn't support everything, the
3242 user configuration file will need to override parts of
3243 the reset configuration provided by other files.
3244 @end quotation
3246 @section Types of Reset
3248 There are many kinds of reset possible through JTAG, but
3249 they may not all work with a given board and adapter.
3250 That's part of why reset configuration can be error prone.
3252 @itemize @bullet
3253 @item
3254 @emph{System Reset} ... the @emph{SRST} hardware signal
3255 resets all chips connected to the JTAG adapter, such as processors,
3256 power management chips, and I/O controllers. Normally resets triggered
3257 with this signal behave exactly like pressing a RESET button.
3258 @item
3259 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3260 just the TAP controllers connected to the JTAG adapter.
3261 Such resets should not be visible to the rest of the system; resetting a
3262 device's TAP controller just puts that controller into a known state.
3263 @item
3264 @emph{Emulation Reset} ... many devices can be reset through JTAG
3265 commands. These resets are often distinguishable from system
3266 resets, either explicitly (a "reset reason" register says so)
3267 or implicitly (not all parts of the chip get reset).
3268 @item
3269 @emph{Other Resets} ... system-on-chip devices often support
3270 several other types of reset.
3271 You may need to arrange that a watchdog timer stops
3272 while debugging, preventing a watchdog reset.
3273 There may be individual module resets.
3274 @end itemize
3276 In the best case, OpenOCD can hold SRST, then reset
3277 the TAPs via TRST and send commands through JTAG to halt the
3278 CPU at the reset vector before the 1st instruction is executed.
3279 Then when it finally releases the SRST signal, the system is
3280 halted under debugger control before any code has executed.
3281 This is the behavior required to support the @command{reset halt}
3282 and @command{reset init} commands; after @command{reset init} a
3283 board-specific script might do things like setting up DRAM.
3284 (@xref{resetcommand,,Reset Command}.)
3286 @anchor{srstandtrstissues}
3287 @section SRST and TRST Issues
3289 Because SRST and TRST are hardware signals, they can have a
3290 variety of system-specific constraints. Some of the most
3291 common issues are:
3293 @itemize @bullet
3295 @item @emph{Signal not available} ... Some boards don't wire
3296 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3297 support such signals even if they are wired up.
3298 Use the @command{reset_config} @var{signals} options to say
3299 when either of those signals is not connected.
3300 When SRST is not available, your code might not be able to rely
3301 on controllers having been fully reset during code startup.
3302 Missing TRST is not a problem, since JTAG-level resets can
3303 be triggered using with TMS signaling.
3305 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3306 adapter will connect SRST to TRST, instead of keeping them separate.
3307 Use the @command{reset_config} @var{combination} options to say
3308 when those signals aren't properly independent.
3310 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3311 delay circuit, reset supervisor, or on-chip features can extend
3312 the effect of a JTAG adapter's reset for some time after the adapter
3313 stops issuing the reset. For example, there may be chip or board
3314 requirements that all reset pulses last for at least a
3315 certain amount of time; and reset buttons commonly have
3316 hardware debouncing.
3317 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3318 commands to say when extra delays are needed.
3320 @item @emph{Drive type} ... Reset lines often have a pullup
3321 resistor, letting the JTAG interface treat them as open-drain
3322 signals. But that's not a requirement, so the adapter may need
3323 to use push/pull output drivers.
3324 Also, with weak pullups it may be advisable to drive
3325 signals to both levels (push/pull) to minimize rise times.
3326 Use the @command{reset_config} @var{trst_type} and
3327 @var{srst_type} parameters to say how to drive reset signals.
3329 @item @emph{Special initialization} ... Targets sometimes need
3330 special JTAG initialization sequences to handle chip-specific
3331 issues (not limited to errata).
3332 For example, certain JTAG commands might need to be issued while
3333 the system as a whole is in a reset state (SRST active)
3334 but the JTAG scan chain is usable (TRST inactive).
3335 Many systems treat combined assertion of SRST and TRST as a
3336 trigger for a harder reset than SRST alone.
3337 Such custom reset handling is discussed later in this chapter.
3338 @end itemize
3340 There can also be other issues.
3341 Some devices don't fully conform to the JTAG specifications.
3342 Trivial system-specific differences are common, such as
3343 SRST and TRST using slightly different names.
3344 There are also vendors who distribute key JTAG documentation for
3345 their chips only to developers who have signed a Non-Disclosure
3346 Agreement (NDA).
3348 Sometimes there are chip-specific extensions like a requirement to use
3349 the normally-optional TRST signal (precluding use of JTAG adapters which
3350 don't pass TRST through), or needing extra steps to complete a TAP reset.
3352 In short, SRST and especially TRST handling may be very finicky,
3353 needing to cope with both architecture and board specific constraints.
3355 @section Commands for Handling Resets
3357 @deffn {Command} adapter_nsrst_assert_width milliseconds
3358 Minimum amount of time (in milliseconds) OpenOCD should wait
3359 after asserting nSRST (active-low system reset) before
3360 allowing it to be deasserted.
3361 @end deffn
3363 @deffn {Command} adapter_nsrst_delay milliseconds
3364 How long (in milliseconds) OpenOCD should wait after deasserting
3365 nSRST (active-low system reset) before starting new JTAG operations.
3366 When a board has a reset button connected to SRST line it will
3367 probably have hardware debouncing, implying you should use this.
3368 @end deffn
3370 @deffn {Command} jtag_ntrst_assert_width milliseconds
3371 Minimum amount of time (in milliseconds) OpenOCD should wait
3372 after asserting nTRST (active-low JTAG TAP reset) before
3373 allowing it to be deasserted.
3374 @end deffn
3376 @deffn {Command} jtag_ntrst_delay milliseconds
3377 How long (in milliseconds) OpenOCD should wait after deasserting
3378 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3379 @end deffn
3381 @deffn {Command} reset_config mode_flag ...
3382 This command displays or modifies the reset configuration
3383 of your combination of JTAG board and target in target
3384 configuration scripts.
3386 Information earlier in this section describes the kind of problems
3387 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3388 As a rule this command belongs only in board config files,
3389 describing issues like @emph{board doesn't connect TRST};
3390 or in user config files, addressing limitations derived
3391 from a particular combination of interface and board.
3392 (An unlikely example would be using a TRST-only adapter
3393 with a board that only wires up SRST.)
3395 The @var{mode_flag} options can be specified in any order, but only one
3396 of each type -- @var{signals}, @var{combination}, @var{gates},
3397 @var{trst_type}, @var{srst_type} and @var{connect_type}
3398 -- may be specified at a time.
3399 If you don't provide a new value for a given type, its previous
3400 value (perhaps the default) is unchanged.
3401 For example, this means that you don't need to say anything at all about
3402 TRST just to declare that if the JTAG adapter should want to drive SRST,
3403 it must explicitly be driven high (@option{srst_push_pull}).
3405 @itemize
3406 @item
3407 @var{signals} can specify which of the reset signals are connected.
3408 For example, If the JTAG interface provides SRST, but the board doesn't
3409 connect that signal properly, then OpenOCD can't use it.
3410 Possible values are @option{none} (the default), @option{trst_only},
3411 @option{srst_only} and @option{trst_and_srst}.
3413 @quotation Tip
3414 If your board provides SRST and/or TRST through the JTAG connector,
3415 you must declare that so those signals can be used.
3416 @end quotation
3418 @item
3419 The @var{combination} is an optional value specifying broken reset
3420 signal implementations.
3421 The default behaviour if no option given is @option{separate},
3422 indicating everything behaves normally.
3423 @option{srst_pulls_trst} states that the
3424 test logic is reset together with the reset of the system (e.g. NXP
3425 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3426 the system is reset together with the test logic (only hypothetical, I
3427 haven't seen hardware with such a bug, and can be worked around).
3428 @option{combined} implies both @option{srst_pulls_trst} and
3429 @option{trst_pulls_srst}.
3431 @item
3432 The @var{gates} tokens control flags that describe some cases where
3433 JTAG may be unvailable during reset.
3434 @option{srst_gates_jtag} (default)
3435 indicates that asserting SRST gates the
3436 JTAG clock. This means that no communication can happen on JTAG
3437 while SRST is asserted.
3438 Its converse is @option{srst_nogate}, indicating that JTAG commands
3439 can safely be issued while SRST is active.
3441 @item
3442 The @var{connect_type} tokens control flags that describe some cases where
3443 SRST is asserted while connecting to the target. @option{srst_nogate}
3444 is required to use this option.
3445 @option{connect_deassert_srst} (default)
3446 indicates that SRST will not be asserted while connecting to the target.
3447 Its converse is @option{connect_assert_srst}, indicating that SRST will
3448 be asserted before any target connection.
3449 Only some targets support this feature, STM32 and STR9 are examples.
3450 This feature is useful if you are unable to connect to your target due
3451 to incorrect options byte config or illegal program execution.
3452 @end itemize
3454 The optional @var{trst_type} and @var{srst_type} parameters allow the
3455 driver mode of each reset line to be specified. These values only affect
3456 JTAG interfaces with support for different driver modes, like the Amontec
3457 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3458 relevant signal (TRST or SRST) is not connected.
3460 @itemize
3461 @item
3462 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3463 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3464 Most boards connect this signal to a pulldown, so the JTAG TAPs
3465 never leave reset unless they are hooked up to a JTAG adapter.
3467 @item
3468 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3469 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3470 Most boards connect this signal to a pullup, and allow the
3471 signal to be pulled low by various events including system
3472 powerup and pressing a reset button.
3473 @end itemize
3474 @end deffn
3476 @section Custom Reset Handling
3477 @cindex events
3479 OpenOCD has several ways to help support the various reset
3480 mechanisms provided by chip and board vendors.
3481 The commands shown in the previous section give standard parameters.
3482 There are also @emph{event handlers} associated with TAPs or Targets.
3483 Those handlers are Tcl procedures you can provide, which are invoked
3484 at particular points in the reset sequence.
3486 @emph{When SRST is not an option} you must set
3487 up a @code{reset-assert} event handler for your target.
3488 For example, some JTAG adapters don't include the SRST signal;
3489 and some boards have multiple targets, and you won't always
3490 want to reset everything at once.
3492 After configuring those mechanisms, you might still
3493 find your board doesn't start up or reset correctly.
3494 For example, maybe it needs a slightly different sequence
3495 of SRST and/or TRST manipulations, because of quirks that
3496 the @command{reset_config} mechanism doesn't address;
3497 or asserting both might trigger a stronger reset, which
3498 needs special attention.
3500 Experiment with lower level operations, such as @command{jtag_reset}
3501 and the @command{jtag arp_*} operations shown here,
3502 to find a sequence of operations that works.
3503 @xref{JTAG Commands}.
3504 When you find a working sequence, it can be used to override
3505 @command{jtag_init}, which fires during OpenOCD startup
3506 (@pxref{configurationstage,,Configuration Stage});
3507 or @command{init_reset}, which fires during reset processing.
3509 You might also want to provide some project-specific reset
3510 schemes. For example, on a multi-target board the standard
3511 @command{reset} command would reset all targets, but you
3512 may need the ability to reset only one target at time and
3513 thus want to avoid using the board-wide SRST signal.
3515 @deffn {Overridable Procedure} init_reset mode
3516 This is invoked near the beginning of the @command{reset} command,
3517 usually to provide as much of a cold (power-up) reset as practical.
3518 By default it is also invoked from @command{jtag_init} if
3519 the scan chain does not respond to pure JTAG operations.
3520 The @var{mode} parameter is the parameter given to the
3521 low level reset command (@option{halt},
3522 @option{init}, or @option{run}), @option{setup},
3523 or potentially some other value.
3525 The default implementation just invokes @command{jtag arp_init-reset}.
3526 Replacements will normally build on low level JTAG
3527 operations such as @command{jtag_reset}.
3528 Operations here must not address individual TAPs
3529 (or their associated targets)
3530 until the JTAG scan chain has first been verified to work.
3532 Implementations must have verified the JTAG scan chain before
3533 they return.
3534 This is done by calling @command{jtag arp_init}
3535 (or @command{jtag arp_init-reset}).
3536 @end deffn
3538 @deffn Command {jtag arp_init}
3539 This validates the scan chain using just the four
3540 standard JTAG signals (TMS, TCK, TDI, TDO).
3541 It starts by issuing a JTAG-only reset.
3542 Then it performs checks to verify that the scan chain configuration
3543 matches the TAPs it can observe.
3544 Those checks include checking IDCODE values for each active TAP,
3545 and verifying the length of their instruction registers using
3546 TAP @code{-ircapture} and @code{-irmask} values.
3547 If these tests all pass, TAP @code{setup} events are
3548 issued to all TAPs with handlers for that event.
3549 @end deffn
3551 @deffn Command {jtag arp_init-reset}
3552 This uses TRST and SRST to try resetting
3553 everything on the JTAG scan chain
3554 (and anything else connected to SRST).
3555 It then invokes the logic of @command{jtag arp_init}.
3556 @end deffn
3559 @node TAP Declaration
3560 @chapter TAP Declaration
3561 @cindex TAP declaration
3562 @cindex TAP configuration
3564 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3565 TAPs serve many roles, including:
3567 @itemize @bullet
3568 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
3569 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
3570 Others do it indirectly, making a CPU do it.
3571 @item @b{Program Download} Using the same CPU support GDB uses,
3572 you can initialize a DRAM controller, download code to DRAM, and then
3573 start running that code.
3574 @item @b{Boundary Scan} Most chips support boundary scan, which
3575 helps test for board assembly problems like solder bridges
3576 and missing connections
3577 @end itemize
3579 OpenOCD must know about the active TAPs on your board(s).
3580 Setting up the TAPs is the core task of your configuration files.
3581 Once those TAPs are set up, you can pass their names to code
3582 which sets up CPUs and exports them as GDB targets,
3583 probes flash memory, performs low-level JTAG operations, and more.
3585 @section Scan Chains
3586 @cindex scan chain
3588 TAPs are part of a hardware @dfn{scan chain},
3589 which is daisy chain of TAPs.
3590 They also need to be added to
3591 OpenOCD's software mirror of that hardware list,
3592 giving each member a name and associating other data with it.
3593 Simple scan chains, with a single TAP, are common in
3594 systems with a single microcontroller or microprocessor.
3595 More complex chips may have several TAPs internally.
3596 Very complex scan chains might have a dozen or more TAPs:
3597 several in one chip, more in the next, and connecting
3598 to other boards with their own chips and TAPs.
3600 You can display the list with the @command{scan_chain} command.
3601 (Don't confuse this with the list displayed by the @command{targets}
3602 command, presented in the next chapter.
3603 That only displays TAPs for CPUs which are configured as
3604 debugging targets.)
3605 Here's what the scan chain might look like for a chip more than one TAP:
3607 @verbatim
3608 TapName Enabled IdCode Expected IrLen IrCap IrMask
3609 -- ------------------ ------- ---------- ---------- ----- ----- ------
3610 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3611 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3612 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3613 @end verbatim
3615 OpenOCD can detect some of that information, but not all
3616 of it. @xref{autoprobing,,Autoprobing}.
3617 Unfortunately those TAPs can't always be autoconfigured,
3618 because not all devices provide good support for that.
3619 JTAG doesn't require supporting IDCODE instructions, and
3620 chips with JTAG routers may not link TAPs into the chain
3621 until they are told to do so.
3623 The configuration mechanism currently supported by OpenOCD
3624 requires explicit configuration of all TAP devices using
3625 @command{jtag newtap} commands, as detailed later in this chapter.
3626 A command like this would declare one tap and name it @code{chip1.cpu}:
3628 @example
3629 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3630 @end example
3632 Each target configuration file lists the TAPs provided
3633 by a given chip.
3634 Board configuration files combine all the targets on a board,
3635 and so forth.
3636 Note that @emph{the order in which TAPs are declared is very important.}
3637 It must match the order in the JTAG scan chain, both inside
3638 a single chip and between them.
3639 @xref{faqtaporder,,FAQ TAP Order}.
3641 For example, the ST Microsystems STR912 chip has
3642 three separate TAPs@footnote{See the ST
3643 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3644 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3645 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3646 To configure those taps, @file{target/str912.cfg}
3647 includes commands something like this:
3649 @example
3650 jtag newtap str912 flash ... params ...
3651 jtag newtap str912 cpu ... params ...
3652 jtag newtap str912 bs ... params ...
3653 @end example
3655 Actual config files use a variable instead of literals like
3656 @option{str912}, to support more than one chip of each type.
3657 @xref{Config File Guidelines}.
3659 @deffn Command {jtag names}
3660 Returns the names of all current TAPs in the scan chain.
3661 Use @command{jtag cget} or @command{jtag tapisenabled}
3662 to examine attributes and state of each TAP.
3663 @example
3664 foreach t [jtag names] @{
3665 puts [format "TAP: %s\n" $t]
3666 @}
3667 @end example
3668 @end deffn
3670 @deffn Command {scan_chain}
3671 Displays the TAPs in the scan chain configuration,
3672 and their status.
3673 The set of TAPs listed by this command is fixed by
3674 exiting the OpenOCD configuration stage,
3675 but systems with a JTAG router can
3676 enable or disable TAPs dynamically.
3677 @end deffn
3679 @c FIXME! "jtag cget" should be able to return all TAP
3680 @c attributes, like "$target_name cget" does for targets.
3682 @c Probably want "jtag eventlist", and a "tap-reset" event
3683 @c (on entry to RESET state).
3685 @section TAP Names
3686 @cindex dotted name
3688 When TAP objects are declared with @command{jtag newtap},
3689 a @dfn{dotted.name} is created for the TAP, combining the
3690 name of a module (usually a chip) and a label for the TAP.
3691 For example: @code{xilinx.tap}, @code{str912.flash},
3692 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3693 Many other commands use that dotted.name to manipulate or
3694 refer to the TAP. For example, CPU configuration uses the
3695 name, as does declaration of NAND or NOR flash banks.
3697 The components of a dotted name should follow ``C'' symbol
3698 name rules: start with an alphabetic character, then numbers
3699 and underscores are OK; while others (including dots!) are not.
3701 @quotation Tip
3702 In older code, JTAG TAPs were numbered from 0..N.
3703 This feature is still present.
3704 However its use is highly discouraged, and
3705 should not be relied on; it will be removed by mid-2010.
3706 Update all of your scripts to use TAP names rather than numbers,
3707 by paying attention to the runtime warnings they trigger.
3708 Using TAP numbers in target configuration scripts prevents
3709 reusing those scripts on boards with multiple targets.
3710 @end quotation
3712 @section TAP Declaration Commands
3714 @c shouldn't this be(come) a {Config Command}?
3715 @deffn Command {jtag newtap} chipname tapname configparams...
3716 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3717 and configured according to the various @var{configparams}.
3719 The @var{chipname} is a symbolic name for the chip.
3720 Conventionally target config files use @code{$_CHIPNAME},
3721 defaulting to the model name given by the chip vendor but
3722 overridable.
3724 @cindex TAP naming convention
3725 The @var{tapname} reflects the role of that TAP,
3726 and should follow this convention:
3728 @itemize @bullet
3729 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3730 @item @code{cpu} -- The main CPU of the chip, alternatively
3731 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3732 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3733 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3734 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3735 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3736 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3737 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3738 with a single TAP;
3739 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3740 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3741 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3742 a JTAG TAP; that TAP should be named @code{sdma}.
3743 @end itemize
3745 Every TAP requires at least the following @var{configparams}:
3747 @itemize @bullet
3748 @item @code{-irlen} @var{NUMBER}
3749 @*The length in bits of the
3750 instruction register, such as 4 or 5 bits.
3751 @end itemize
3753 A TAP may also provide optional @var{configparams}:
3755 @itemize @bullet
3756 @item @code{-disable} (or @code{-enable})
3757 @*Use the @code{-disable} parameter to flag a TAP which is not
3758 linked in to the scan chain after a reset using either TRST
3759 or the JTAG state machine's @sc{reset} state.
3760 You may use @code{-enable} to highlight the default state
3761 (the TAP is linked in).
3762 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3763 @item @code{-expected-id} @var{number}
3764 @*A non-zero @var{number} represents a 32-bit IDCODE
3765 which you expect to find when the scan chain is examined.
3766 These codes are not required by all JTAG devices.
3767 @emph{Repeat the option} as many times as required if more than one
3768 ID code could appear (for example, multiple versions).
3769 Specify @var{number} as zero to suppress warnings about IDCODE
3770 values that were found but not included in the list.
3772 Provide this value if at all possible, since it lets OpenOCD
3773 tell when the scan chain it sees isn't right. These values
3774 are provided in vendors' chip documentation, usually a technical
3775 reference manual. Sometimes you may need to probe the JTAG
3776 hardware to find these values.
3777 @xref{autoprobing,,Autoprobing}.
3778 @item @code{-ignore-version}
3779 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3780 option. When vendors put out multiple versions of a chip, or use the same
3781 JTAG-level ID for several largely-compatible chips, it may be more practical
3782 to ignore the version field than to update config files to handle all of
3783 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3784 @item @code{-ircapture} @var{NUMBER}
3785 @*The bit pattern loaded by the TAP into the JTAG shift register
3786 on entry to the @sc{ircapture} state, such as 0x01.
3787 JTAG requires the two LSBs of this value to be 01.
3788 By default, @code{-ircapture} and @code{-irmask} are set
3789 up to verify that two-bit value. You may provide
3790 additional bits, if you know them, or indicate that
3791 a TAP doesn't conform to the JTAG specification.
3792 @item @code{-irmask} @var{NUMBER}
3793 @*A mask used with @code{-ircapture}
3794 to verify that instruction scans work correctly.
3795 Such scans are not used by OpenOCD except to verify that
3796 there seems to be no problems with JTAG scan chain operations.
3797 @end itemize
3798 @end deffn
3800 @section Other TAP commands
3802 @deffn Command {jtag cget} dotted.name @option{-event} name
3803 @deffnx Command {jtag configure} dotted.name @option{-event} name string
3804 At this writing this TAP attribute
3805 mechanism is used only for event handling.
3806 (It is not a direct analogue of the @code{cget}/@code{configure}
3807 mechanism for debugger targets.)
3808 See the next section for information about the available events.
3810 The @code{configure} subcommand assigns an event handler,
3811 a TCL string which is evaluated when the event is triggered.
3812 The @code{cget} subcommand returns that handler.
3813 @end deffn
3815 @section TAP Events
3816 @cindex events
3817 @cindex TAP events
3819 OpenOCD includes two event mechanisms.
3820 The one presented here applies to all JTAG TAPs.
3821 The other applies to debugger targets,
3822 which are associated with certain TAPs.
3824 The TAP events currently defined are:
3826 @itemize @bullet
3827 @item @b{post-reset}
3828 @* The TAP has just completed a JTAG reset.
3829 The tap may still be in the JTAG @sc{reset} state.
3830 Handlers for these events might perform initialization sequences
3831 such as issuing TCK cycles, TMS sequences to ensure
3832 exit from the ARM SWD mode, and more.
3834 Because the scan chain has not yet been verified, handlers for these events
3835 @emph{should not issue commands which scan the JTAG IR or DR registers}
3836 of any particular target.
3837 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3838 @item @b{setup}
3839 @* The scan chain has been reset and verified.
3840 This handler may enable TAPs as needed.
3841 @item @b{tap-disable}
3842 @* The TAP needs to be disabled. This handler should
3843 implement @command{jtag tapdisable}
3844 by issuing the relevant JTAG commands.
3845 @item @b{tap-enable}
3846 @* The TAP needs to be enabled. This handler should
3847 implement @command{jtag tapenable}
3848 by issuing the relevant JTAG commands.
3849 @end itemize
3851 If you need some action after each JTAG reset, which isn't actually
3852 specific to any TAP (since you can't yet trust the scan chain's
3853 contents to be accurate), you might:
3855 @example
3856 jtag configure CHIP.jrc -event post-reset @{
3857 echo "JTAG Reset done"
3858 ... non-scan jtag operations to be done after reset
3859 @}
3860 @end example
3863 @anchor{enablinganddisablingtaps}
3864 @section Enabling and Disabling TAPs
3865 @cindex JTAG Route Controller
3866 @cindex jrc
3868 In some systems, a @dfn{JTAG Route Controller} (JRC)
3869 is used to enable and/or disable specific JTAG TAPs.
3870 Many ARM based chips from Texas Instruments include
3871 an ``ICEpick'' module, which is a JRC.
3872 Such chips include DaVinci and OMAP3 processors.
3874 A given TAP may not be visible until the JRC has been
3875 told to link it into the scan chain; and if the JRC
3876 has been told to unlink that TAP, it will no longer
3877 be visible.
3878 Such routers address problems that JTAG ``bypass mode''
3879 ignores, such as:
3881 @itemize
3882 @item The scan chain can only go as fast as its slowest TAP.
3883 @item Having many TAPs slows instruction scans, since all
3884 TAPs receive new instructions.
3885 @item TAPs in the scan chain must be powered up, which wastes
3886 power and prevents debugging some power management mechanisms.
3887 @end itemize
3889 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3890 as implied by the existence of JTAG routers.
3891 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3892 does include a kind of JTAG router functionality.
3894 @c (a) currently the event handlers don't seem to be able to
3895 @c fail in a way that could lead to no-change-of-state.
3897 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3898 shown below, and is implemented using TAP event handlers.
3899 So for example, when defining a TAP for a CPU connected to
3900 a JTAG router, your @file{target.cfg} file
3901 should define TAP event handlers using
3902 code that looks something like this:
3904 @example
3905 jtag configure CHIP.cpu -event tap-enable @{
3906 ... jtag operations using CHIP.jrc
3907 @}
3908 jtag configure CHIP.cpu -event tap-disable @{
3909 ... jtag operations using CHIP.jrc
3910 @}
3911 @end example
3913 Then you might want that CPU's TAP enabled almost all the time:
3915 @example
3916 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3917 @end example
3919 Note how that particular setup event handler declaration
3920 uses quotes to evaluate @code{$CHIP} when the event is configured.
3921 Using brackets @{ @} would cause it to be evaluated later,
3922 at runtime, when it might have a different value.
3924 @deffn Command {jtag tapdisable} dotted.name
3925 If necessary, disables the tap
3926 by sending it a @option{tap-disable} event.
3927 Returns the string "1" if the tap
3928 specified by @var{dotted.name} is enabled,
3929 and "0" if it is disabled.
3930 @end deffn
3932 @deffn Command {jtag tapenable} dotted.name
3933 If necessary, enables the tap
3934 by sending it a @option{tap-enable} event.
3935 Returns the string "1" if the tap
3936 specified by @var{dotted.name} is enabled,
3937 and "0" if it is disabled.
3938 @end deffn
3940 @deffn Command {jtag tapisenabled} dotted.name
3941 Returns the string "1" if the tap
3942 specified by @var{dotted.name} is enabled,
3943 and "0" if it is disabled.
3945 @quotation Note
3946 Humans will find the @command{scan_chain} command more helpful
3947 for querying the state of the JTAG taps.
3948 @end quotation
3949 @end deffn
3951 @anchor{autoprobing}
3952 @section Autoprobing
3953 @cindex autoprobe
3954 @cindex JTAG autoprobe
3956 TAP configuration is the first thing that needs to be done
3957 after interface and reset configuration. Sometimes it's
3958 hard finding out what TAPs exist, or how they are identified.
3959 Vendor documentation is not always easy to find and use.
3961 To help you get past such problems, OpenOCD has a limited
3962 @emph{autoprobing} ability to look at the scan chain, doing
3963 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3964 To use this mechanism, start the OpenOCD server with only data
3965 that configures your JTAG interface, and arranges to come up
3966 with a slow clock (many devices don't support fast JTAG clocks
3967 right when they come out of reset).
3969 For example, your @file{openocd.cfg} file might have:
3971 @example
3972 source [find interface/olimex-arm-usb-tiny-h.cfg]
3973 reset_config trst_and_srst
3974 jtag_rclk 8
3975 @end example
3977 When you start the server without any TAPs configured, it will
3978 attempt to autoconfigure the TAPs. There are two parts to this:
3980 @enumerate
3981 @item @emph{TAP discovery} ...
3982 After a JTAG reset (sometimes a system reset may be needed too),
3983 each TAP's data registers will hold the contents of either the
3984 IDCODE or BYPASS register.
3985 If JTAG communication is working, OpenOCD will see each TAP,
3986 and report what @option{-expected-id} to use with it.
3987 @item @emph{IR Length discovery} ...
3988 Unfortunately JTAG does not provide a reliable way to find out
3989 the value of the @option{-irlen} parameter to use with a TAP
3990 that is discovered.
3991 If OpenOCD can discover the length of a TAP's instruction
3992 register, it will report it.
3993 Otherwise you may need to consult vendor documentation, such
3994 as chip data sheets or BSDL files.
3995 @end enumerate
3997 In many cases your board will have a simple scan chain with just
3998 a single device. Here's what OpenOCD reported with one board
3999 that's a bit more complex:
4001 @example
4002 clock speed 8 kHz
4003 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4004 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4005 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4006 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4007 AUTO auto0.tap - use "... -irlen 4"
4008 AUTO auto1.tap - use "... -irlen 4"
4009 AUTO auto2.tap - use "... -irlen 6"
4010 no gdb ports allocated as no target has been specified
4011 @end example
4013 Given that information, you should be able to either find some existing
4014 config files to use, or create your own. If you create your own, you
4015 would configure from the bottom up: first a @file{target.cfg} file
4016 with these TAPs, any targets associated with them, and any on-chip
4017 resources; then a @file{board.cfg} with off-chip resources, clocking,
4018 and so forth.
4020 @node CPU Configuration
4021 @chapter CPU Configuration
4022 @cindex GDB target
4024 This chapter discusses how to set up GDB debug targets for CPUs.
4025 You can also access these targets without GDB
4026 (@pxref{Architecture and Core Commands},
4027 and @ref{targetstatehandling,,Target State handling}) and
4028 through various kinds of NAND and NOR flash commands.
4029 If you have multiple CPUs you can have multiple such targets.
4031 We'll start by looking at how to examine the targets you have,
4032 then look at how to add one more target and how to configure it.
4034 @section Target List
4035 @cindex target, current
4036 @cindex target, list
4038 All targets that have been set up are part of a list,
4039 where each member has a name.
4040 That name should normally be the same as the TAP name.
4041 You can display the list with the @command{targets}
4042 (plural!) command.
4043 This display often has only one CPU; here's what it might
4044 look like with more than one:
4045 @verbatim
4046 TargetName Type Endian TapName State
4047 -- ------------------ ---------- ------ ------------------ ------------
4048 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4049 1 MyTarget cortex_m little mychip.foo tap-disabled
4050 @end verbatim
4052 One member of that list is the @dfn{current target}, which
4053 is implicitly referenced by many commands.
4054 It's the one marked with a @code{*} near the target name.
4055 In particular, memory addresses often refer to the address
4056 space seen by that current target.
4057 Commands like @command{mdw} (memory display words)
4058 and @command{flash erase_address} (erase NOR flash blocks)
4059 are examples; and there are many more.
4061 Several commands let you examine the list of targets:
4063 @deffn Command {target count}
4064 @emph{Note: target numbers are deprecated; don't use them.
4065 They will be removed shortly after August 2010, including this command.
4066 Iterate target using @command{target names}, not by counting.}
4068 Returns the number of targets, @math{N}.
4069 The highest numbered target is @math{N - 1}.
4070 @example
4071 set c [target count]
4072 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
4073 # Assuming you have created this function
4074 print_target_details $x
4075 @}
4076 @end example
4077 @end deffn
4079 @deffn Command {target current}
4080 Returns the name of the current target.
4081 @end deffn
4083 @deffn Command {target names}
4084 Lists the names of all current targets in the list.
4085 @example
4086 foreach t [target names] @{
4087 puts [format "Target: %s\n" $t]
4088 @}
4089 @end example
4090 @end deffn
4092 @deffn Command {target number} number
4093 @emph{Note: target numbers are deprecated; don't use them.
4094 They will be removed shortly after August 2010, including this command.}
4096 The list of targets is numbered starting at zero.
4097 This command returns the name of the target at index @var{number}.
4098 @example
4099 set thename [target number $x]
4100 puts [format "Target %d is: %s\n" $x $thename]
4101 @end example
4102 @end deffn
4104 @c yep, "target list" would have been better.
4105 @c plus maybe "target setdefault".
4107 @deffn Command targets [name]
4108 @emph{Note: the name of this command is plural. Other target
4109 command names are singular.}
4111 With no parameter, this command displays a table of all known
4112 targets in a user friendly form.
4114 With a parameter, this command sets the current target to
4115 the given target with the given @var{name}; this is
4116 only relevant on boards which have more than one target.
4117 @end deffn
4119 @section Target CPU Types and Variants
4120 @cindex target type
4121 @cindex CPU type
4122 @cindex CPU variant
4124 Each target has a @dfn{CPU type}, as shown in the output of
4125 the @command{targets} command. You need to specify that type
4126 when calling @command{target create}.
4127 The CPU type indicates more than just the instruction set.
4128 It also indicates how that instruction set is implemented,
4129 what kind of debug support it integrates,
4130 whether it has an MMU (and if so, what kind),
4131 what core-specific commands may be available
4132 (@pxref{Architecture and Core Commands}),
4133 and more.
4135 For some CPU types, OpenOCD also defines @dfn{variants} which
4136 indicate differences that affect their handling.
4137 For example, a particular implementation bug might need to be
4138 worked around in some chip versions.
4140 It's easy to see what target types are supported,
4141 since there's a command to list them.
4142 However, there is currently no way to list what target variants
4143 are supported (other than by reading the OpenOCD source code).
4145 @anchor{targettypes}
4146 @deffn Command {target types}
4147 Lists all supported target types.
4148 At this writing, the supported CPU types and variants are:
4150 @itemize @bullet
4151 @item @code{arm11} -- this is a generation of ARMv6 cores
4152 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4153 @item @code{arm7tdmi} -- this is an ARMv4 core
4154 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4155 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4156 @item @code{arm966e} -- this is an ARMv5 core
4157 @item @code{arm9tdmi} -- this is an ARMv4 core
4158 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4159 (Support for this is preliminary and incomplete.)
4160 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4161 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4162 compact Thumb2 instruction set.
4163 @item @code{dragonite} -- resembles arm966e
4164 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4165 (Support for this is still incomplete.)
4166 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4167 @item @code{feroceon} -- resembles arm926
4168 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
4169 @item @code{xscale} -- this is actually an architecture,
4170 not a CPU type. It is based on the ARMv5 architecture.
4171 There are several variants defined:
4172 @itemize @minus
4173 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
4174 @code{pxa27x} ... instruction register length is 7 bits
4175 @item @code{pxa250}, @code{pxa255},
4176 @code{pxa26x} ... instruction register length is 5 bits
4177 @item @code{pxa3xx} ... instruction register length is 11 bits
4178 @end itemize
4179 @item @code{openrisc} -- this is an OpenRISC 1000 core.
4180 The current implementation supports three JTAG TAP cores:
4181 @itemize @minus
4182 @item @code{OpenCores TAP} (See: @emph{http://opencores.org/project,jtag})
4183 @item @code{Altera Virtual JTAG TAP} (See: @emph{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4184 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @emph{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4185 @end itemize
4186 And two debug interfaces cores:
4187 @itemize @minus
4188 @item @code{Advanced debug interface} (See: @emph{http://opencores.org/project,adv_debug_sys})
4189 @item @code{SoC Debug Interface} (See: @emph{http://opencores.org/project,dbg_interface})
4190 @end itemize
4191 @end itemize
4192 @end deffn
4194 To avoid being confused by the variety of ARM based cores, remember
4195 this key point: @emph{ARM is a technology licencing company}.
4196 (See: @url{http://www.arm.com}.)
4197 The CPU name used by OpenOCD will reflect the CPU design that was
4198 licenced, not a vendor brand which incorporates that design.
4199 Name prefixes like arm7, arm9, arm11, and cortex
4200 reflect design generations;
4201 while names like ARMv4, ARMv5, ARMv6, and ARMv7
4202 reflect an architecture version implemented by a CPU design.
4204 @anchor{targetconfiguration}
4205 @section Target Configuration
4207 Before creating a ``target'', you must have added its TAP to the scan chain.
4208 When you've added that TAP, you will have a @code{dotted.name}
4209 which is used to set up the CPU support.
4210 The chip-specific configuration file will normally configure its CPU(s)
4211 right after it adds all of the chip's TAPs to the scan chain.
4213 Although you can set up a target in one step, it's often clearer if you
4214 use shorter commands and do it in two steps: create it, then configure
4215 optional parts.
4216 All operations on the target after it's created will use a new
4217 command, created as part of target creation.
4219 The two main things to configure after target creation are
4220 a work area, which usually has target-specific defaults even
4221 if the board setup code overrides them later;
4222 and event handlers (@pxref{targetevents,,Target Events}), which tend
4223 to be much more board-specific.
4224 The key steps you use might look something like this
4226 @example
4227 target create MyTarget cortex_m -chain-position mychip.cpu
4228 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4229 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4230 $MyTarget configure -event reset-init @{ myboard_reinit @}
4231 @end example
4233 You should specify a working area if you can; typically it uses some
4234 on-chip SRAM.
4235 Such a working area can speed up many things, including bulk
4236 writes to target memory;
4237 flash operations like checking to see if memory needs to be erased;
4238 GDB memory checksumming;
4239 and more.
4241 @quotation Warning
4242 On more complex chips, the work area can become
4243 inaccessible when application code
4244 (such as an operating system)
4245 enables or disables the MMU.
4246 For example, the particular MMU context used to acess the virtual
4247 address will probably matter ... and that context might not have
4248 easy access to other addresses needed.
4249 At this writing, OpenOCD doesn't have much MMU intelligence.
4250 @end quotation
4252 It's often very useful to define a @code{reset-init} event handler.
4253 For systems that are normally used with a boot loader,
4254 common tasks include updating clocks and initializing memory
4255 controllers.
4256 That may be needed to let you write the boot loader into flash,
4257 in order to ``de-brick'' your board; or to load programs into
4258 external DDR memory without having run the boot loader.
4260 @deffn Command {target create} target_name type configparams...
4261 This command creates a GDB debug target that refers to a specific JTAG tap.
4262 It enters that target into a list, and creates a new
4263 command (@command{@var{target_name}}) which is used for various
4264 purposes including additional configuration.
4266 @itemize @bullet
4267 @item @var{target_name} ... is the name of the debug target.
4268 By convention this should be the same as the @emph{dotted.name}
4269 of the TAP associated with this target, which must be specified here
4270 using the @code{-chain-position @var{dotted.name}} configparam.
4272 This name is also used to create the target object command,
4273 referred to here as @command{$target_name},
4274 and in other places the target needs to be identified.
4275 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4276 @item @var{configparams} ... all parameters accepted by
4277 @command{$target_name configure} are permitted.
4278 If the target is big-endian, set it here with @code{-endian big}.
4279 If the variant matters, set it here with @code{-variant}.
4281 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
4282 @end itemize
4283 @end deffn
4285 @deffn Command {$target_name configure} configparams...
4286 The options accepted by this command may also be
4287 specified as parameters to @command{target create}.
4288 Their values can later be queried one at a time by
4289 using the @command{$target_name cget} command.
4291 @emph{Warning:} changing some of these after setup is dangerous.
4292 For example, moving a target from one TAP to another;
4293 and changing its endianness or variant.
4295 @itemize @bullet
4297 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4298 used to access this target.
4300 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4301 whether the CPU uses big or little endian conventions
4303 @item @code{-event} @var{event_name} @var{event_body} --
4304 @xref{targetevents,,Target Events}.
4305 Note that this updates a list of named event handlers.
4306 Calling this twice with two different event names assigns
4307 two different handlers, but calling it twice with the
4308 same event name assigns only one handler.
4310 @item @code{-variant} @var{name} -- specifies a variant of the target,
4311 which OpenOCD needs to know about.
4313 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4314 whether the work area gets backed up; by default,
4315 @emph{it is not backed up.}
4316 When possible, use a working_area that doesn't need to be backed up,
4317 since performing a backup slows down operations.
4318 For example, the beginning of an SRAM block is likely to
4319 be used by most build systems, but the end is often unused.
4321 @item @code{-work-area-size} @var{size} -- specify work are size,
4322 in bytes. The same size applies regardless of whether its physical
4323 or virtual address is being used.
4325 @item @code{-work-area-phys} @var{address} -- set the work area
4326 base @var{address} to be used when no MMU is active.
4328 @item @code{-work-area-virt} @var{address} -- set the work area
4329 base @var{address} to be used when an MMU is active.
4330 @emph{Do not specify a value for this except on targets with an MMU.}
4331 The value should normally correspond to a static mapping for the
4332 @code{-work-area-phys} address, set up by the current operating system.
4334 @anchor{rtostype}
4335 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4336 @var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}|
4337 @option{FreeRTOS}|@option{linux}|@option{ChibiOS}|@option{embKernel}
4338 @xref{gdbrtossupport,,RTOS Support}.
4340 @end itemize
4341 @end deffn
4343 @section Other $target_name Commands
4344 @cindex object command
4346 The Tcl/Tk language has the concept of object commands,
4347 and OpenOCD adopts that same model for targets.
4349 A good Tk example is a on screen button.
4350 Once a button is created a button
4351 has a name (a path in Tk terms) and that name is useable as a first
4352 class command. For example in Tk, one can create a button and later
4353 configure it like this:
4355 @example
4356 # Create
4357 button .foobar -background red -command @{ foo @}
4358 # Modify
4359 .foobar configure -foreground blue
4360 # Query
4361 set x [.foobar cget -background]
4362 # Report
4363 puts [format "The button is %s" $x]
4364 @end example
4366 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4367 button, and its object commands are invoked the same way.
4369 @example
4370 str912.cpu mww 0x1234 0x42
4371 omap3530.cpu mww 0x5555 123
4372 @end example
4374 The commands supported by OpenOCD target objects are:
4376 @deffn Command {$target_name arp_examine}
4377 @deffnx Command {$target_name arp_halt}
4378 @deffnx Command {$target_name arp_poll}
4379 @deffnx Command {$target_name arp_reset}
4380 @deffnx Command {$target_name arp_waitstate}
4381 Internal OpenOCD scripts (most notably @file{startup.tcl})
4382 use these to deal with specific reset cases.
4383 They are not otherwise documented here.
4384 @end deffn
4386 @deffn Command {$target_name array2mem} arrayname width address count
4387 @deffnx Command {$target_name mem2array} arrayname width address count
4388 These provide an efficient script-oriented interface to memory.
4389 The @code{array2mem} primitive writes bytes, halfwords, or words;
4390 while @code{mem2array} reads them.
4391 In both cases, the TCL side uses an array, and
4392 the target side uses raw memory.
4394 The efficiency comes from enabling the use of
4395 bulk JTAG data transfer operations.
4396 The script orientation comes from working with data
4397 values that are packaged for use by TCL scripts;
4398 @command{mdw} type primitives only print data they retrieve,
4399 and neither store nor return those values.
4401 @itemize
4402 @item @var{arrayname} ... is the name of an array variable
4403 @item @var{width} ... is 8/16/32 - indicating the memory access size
4404 @item @var{address} ... is the target memory address
4405 @item @var{count} ... is the number of elements to process
4406 @end itemize
4407 @end deffn
4409 @deffn Command {$target_name cget} queryparm
4410 Each configuration parameter accepted by
4411 @command{$target_name configure}
4412 can be individually queried, to return its current value.
4413 The @var{queryparm} is a parameter name
4414 accepted by that command, such as @code{-work-area-phys}.
4415 There are a few special cases:
4417 @itemize @bullet
4418 @item @code{-event} @var{event_name} -- returns the handler for the
4419 event named @var{event_name}.
4420 This is a special case because setting a handler requires
4421 two parameters.
4422 @item @code{-type} -- returns the target type.
4423 This is a special case because this is set using
4424 @command{target create} and can't be changed
4425 using @command{$target_name configure}.
4426 @end itemize
4428 For example, if you wanted to summarize information about
4429 all the targets you might use something like this:
4431 @example
4432 foreach name [target names] @{
4433 set y [$name cget -endian]
4434 set z [$name cget -type]
4435 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4436 $x $name $y $z]
4437 @}
4438 @end example
4439 @end deffn
4441 @anchor{targetcurstate}
4442 @deffn Command {$target_name curstate}
4443 Displays the current target state:
4444 @code{debug-running},
4445 @code{halted},
4446 @code{reset},
4447 @code{running}, or @code{unknown}.
4448 (Also, @pxref{eventpolling,,Event Polling}.)
4449 @end deffn
4451 @deffn Command {$target_name eventlist}
4452 Displays a table listing all event handlers
4453 currently associated with this target.
4454 @xref{targetevents,,Target Events}.
4455 @end deffn
4457 @deffn Command {$target_name invoke-event} event_name
4458 Invokes the handler for the event named @var{event_name}.
4459 (This is primarily intended for use by OpenOCD framework
4460 code, for example by the reset code in @file{startup.tcl}.)
4461 @end deffn
4463 @deffn Command {$target_name mdw} addr [count]
4464 @deffnx Command {$target_name mdh} addr [count]
4465 @deffnx Command {$target_name mdb} addr [count]
4466 Display contents of address @var{addr}, as
4467 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4468 or 8-bit bytes (@command{mdb}).
4469 If @var{count} is specified, displays that many units.
4470 (If you want to manipulate the data instead of displaying it,
4471 see the @code{mem2array} primitives.)
4472 @end deffn
4474 @deffn Command {$target_name mww} addr word
4475 @deffnx Command {$target_name mwh} addr halfword
4476 @deffnx Command {$target_name mwb} addr byte
4477 Writes the specified @var{word} (32 bits),
4478 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4479 at the specified address @var{addr}.
4480 @end deffn
4482 @anchor{targetevents}
4483 @section Target Events
4484 @cindex target events
4485 @cindex events
4486 At various times, certain things can happen, or you want them to happen.
4487 For example:
4488 @itemize @bullet
4489 @item What should happen when GDB connects? Should your target reset?
4490 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4491 @item Is using SRST appropriate (and possible) on your system?
4492 Or instead of that, do you need to issue JTAG commands to trigger reset?
4493 SRST usually resets everything on the scan chain, which can be inappropriate.
4494 @item During reset, do you need to write to certain memory locations
4495 to set up system clocks or
4496 to reconfigure the SDRAM?
4497 How about configuring the watchdog timer, or other peripherals,
4498 to stop running while you hold the core stopped for debugging?
4499 @end itemize
4501 All of the above items can be addressed by target event handlers.
4502 These are set up by @command{$target_name configure -event} or
4503 @command{target create ... -event}.
4505 The programmer's model matches the @code{-command} option used in Tcl/Tk
4506 buttons and events. The two examples below act the same, but one creates
4507 and invokes a small procedure while the other inlines it.
4509 @example
4510 proc my_attach_proc @{ @} @{
4511 echo "Reset..."
4512 reset halt
4513 @}
4514 mychip.cpu configure -event gdb-attach my_attach_proc
4515 mychip.cpu configure -event gdb-attach @{
4516 echo "Reset..."
4517 # To make flash probe and gdb load to flash work we need a reset init.
4518 reset init
4519 @}
4520 @end example
4522 The following target events are defined:
4524 @itemize @bullet
4525 @item @b{debug-halted}
4526 @* The target has halted for debug reasons (i.e.: breakpoint)
4527 @item @b{debug-resumed}
4528 @* The target has resumed (i.e.: gdb said run)
4529 @item @b{early-halted}
4530 @* Occurs early in the halt process
4531 @item @b{examine-start}
4532 @* Before target examine is called.
4533 @item @b{examine-end}
4534 @* After target examine is called with no errors.
4535 @item @b{gdb-attach}
4536 @* When GDB connects. This is before any communication with the target, so this
4537 can be used to set up the target so it is possible to probe flash. Probing flash
4538 is necessary during gdb connect if gdb load is to write the image to flash. Another
4539 use of the flash memory map is for GDB to automatically hardware/software breakpoints
4540 depending on whether the breakpoint is in RAM or read only memory.
4541 @item @b{gdb-detach}
4542 @* When GDB disconnects
4543 @item @b{gdb-end}
4544 @* When the target has halted and GDB is not doing anything (see early halt)
4545 @item @b{gdb-flash-erase-start}
4546 @* Before the GDB flash process tries to erase the flash
4547 @item @b{gdb-flash-erase-end}
4548 @* After the GDB flash process has finished erasing the flash
4549 @item @b{gdb-flash-write-start}
4550 @* Before GDB writes to the flash
4551 @item @b{gdb-flash-write-end}
4552 @* After GDB writes to the flash
4553 @item @b{gdb-start}
4554 @* Before the target steps, gdb is trying to start/resume the target
4555 @item @b{halted}
4556 @* The target has halted
4557 @item @b{reset-assert-pre}
4558 @* Issued as part of @command{reset} processing
4559 after @command{reset_init} was triggered
4560 but before either SRST alone is re-asserted on the scan chain,
4561 or @code{reset-assert} is triggered.
4562 @item @b{reset-assert}
4563 @* Issued as part of @command{reset} processing
4564 after @command{reset-assert-pre} was triggered.
4565 When such a handler is present, cores which support this event will use
4566 it instead of asserting SRST.
4567 This support is essential for debugging with JTAG interfaces which
4568 don't include an SRST line (JTAG doesn't require SRST), and for
4569 selective reset on scan chains that have multiple targets.
4570 @item @b{reset-assert-post}
4571 @* Issued as part of @command{reset} processing
4572 after @code{reset-assert} has been triggered.
4573 or the target asserted SRST on the entire scan chain.
4574 @item @b{reset-deassert-pre}
4575 @* Issued as part of @command{reset} processing
4576 after @code{reset-assert-post} has been triggered.
4577 @item @b{reset-deassert-post}
4578 @* Issued as part of @command{reset} processing
4579 after @code{reset-deassert-pre} has been triggered
4580 and (if the target is using it) after SRST has been
4581 released on the scan chain.
4582 @item @b{reset-end}
4583 @* Issued as the final step in @command{reset} processing.
4584 @ignore
4585 @item @b{reset-halt-post}
4586 @* Currently not used
4587 @item @b{reset-halt-pre}
4588 @* Currently not used
4589 @end ignore
4590 @item @b{reset-init}
4591 @* Used by @b{reset init} command for board-specific initialization.
4592 This event fires after @emph{reset-deassert-post}.
4594 This is where you would configure PLLs and clocking, set up DRAM so
4595 you can download programs that don't fit in on-chip SRAM, set up pin
4596 multiplexing, and so on.
4597 (You may be able to switch to a fast JTAG clock rate here, after
4598 the target clocks are fully set up.)
4599 @item @b{reset-start}
4600 @* Issued as part of @command{reset} processing
4601 before @command{reset_init} is called.
4603 This is the most robust place to use @command{jtag_rclk}
4604 or @command{adapter_khz} to switch to a low JTAG clock rate,
4605 when reset disables PLLs needed to use a fast clock.
4606 @ignore
4607 @item @b{reset-wait-pos}
4608 @* Currently not used
4609 @item @b{reset-wait-pre}
4610 @* Currently not used
4611 @end ignore
4612 @item @b{resume-start}
4613 @* Before any target is resumed
4614 @item @b{resume-end}
4615 @* After all targets have resumed
4616 @item @b{resumed}
4617 @* Target has resumed
4618 @end itemize
4620 @node Flash Commands
4621 @chapter Flash Commands
4623 OpenOCD has different commands for NOR and NAND flash;
4624 the ``flash'' command works with NOR flash, while
4625 the ``nand'' command works with NAND flash.
4626 This partially reflects different hardware technologies:
4627 NOR flash usually supports direct CPU instruction and data bus access,
4628 while data from a NAND flash must be copied to memory before it can be
4629 used. (SPI flash must also be copied to memory before use.)
4630 However, the documentation also uses ``flash'' as a generic term;
4631 for example, ``Put flash configuration in board-specific files''.
4633 Flash Steps:
4634 @enumerate
4635 @item Configure via the command @command{flash bank}
4636 @* Do this in a board-specific configuration file,
4637 passing parameters as needed by the driver.
4638 @item Operate on the flash via @command{flash subcommand}
4639 @* Often commands to manipulate the flash are typed by a human, or run
4640 via a script in some automated way. Common tasks include writing a
4641 boot loader, operating system, or other data.
4642 @item GDB Flashing
4643 @* Flashing via GDB requires the flash be configured via ``flash
4644 bank'', and the GDB flash features be enabled.
4645 @xref{gdbconfiguration,,GDB Configuration}.
4646 @end enumerate
4648 Many CPUs have the ablity to ``boot'' from the first flash bank.
4649 This means that misprogramming that bank can ``brick'' a system,
4650 so that it can't boot.
4651 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4652 board by (re)installing working boot firmware.
4654 @anchor{norconfiguration}
4655 @section Flash Configuration Commands
4656 @cindex flash configuration
4658 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4659 Configures a flash bank which provides persistent storage
4660 for addresses from @math{base} to @math{base + size - 1}.
4661 These banks will often be visible to GDB through the target's memory map.
4662 In some cases, configuring a flash bank will activate extra commands;
4663 see the driver-specific documentation.
4665 @itemize @bullet
4666 @item @var{name} ... may be used to reference the flash bank
4667 in other flash commands. A number is also available.
4668 @item @var{driver} ... identifies the controller driver
4669 associated with the flash bank being declared.
4670 This is usually @code{cfi} for external flash, or else
4671 the name of a microcontroller with embedded flash memory.
4672 @xref{flashdriverlist,,Flash Driver List}.
4673 @item @var{base} ... Base address of the flash chip.
4674 @item @var{size} ... Size of the chip, in bytes.
4675 For some drivers, this value is detected from the hardware.
4676 @item @var{chip_width} ... Width of the flash chip, in bytes;
4677 ignored for most microcontroller drivers.
4678 @item @var{bus_width} ... Width of the data bus used to access the
4679 chip, in bytes; ignored for most microcontroller drivers.
4680 @item @var{target} ... Names the target used to issue
4681 commands to the flash controller.
4682 @comment Actually, it's currently a controller-specific parameter...
4683 @item @var{driver_options} ... drivers may support, or require,
4684 additional parameters. See the driver-specific documentation
4685 for more information.
4686 @end itemize
4687 @quotation Note
4688 This command is not available after OpenOCD initialization has completed.
4689 Use it in board specific configuration files, not interactively.
4690 @end quotation
4691 @end deffn
4693 @comment the REAL name for this command is "ocd_flash_banks"
4694 @comment less confusing would be: "flash list" (like "nand list")
4695 @deffn Command {flash banks}
4696 Prints a one-line summary of each device that was
4697 declared using @command{flash bank}, numbered from zero.
4698 Note that this is the @emph{plural} form;
4699 the @emph{singular} form is a very different command.
4700 @end deffn
4702 @deffn Command {flash list}
4703 Retrieves a list of associative arrays for each device that was
4704 declared using @command{flash bank}, numbered from zero.
4705 This returned list can be manipulated easily from within scripts.
4706 @end deffn
4708 @deffn Command {flash probe} num
4709 Identify the flash, or validate the parameters of the configured flash. Operation
4710 depends on the flash type.
4711 The @var{num} parameter is a value shown by @command{flash banks}.
4712 Most flash commands will implicitly @emph{autoprobe} the bank;
4713 flash drivers can distinguish between probing and autoprobing,
4714 but most don't bother.
4715 @end deffn
4717 @section Erasing, Reading, Writing to Flash
4718 @cindex flash erasing
4719 @cindex flash reading
4720 @cindex flash writing
4721 @cindex flash programming
4722 @anchor{flashprogrammingcommands}
4724 One feature distinguishing NOR flash from NAND or serial flash technologies
4725 is that for read access, it acts exactly like any other addressible memory.
4726 This means you can use normal memory read commands like @command{mdw} or
4727 @command{dump_image} with it, with no special @command{flash} subcommands.
4728 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
4730 Write access works differently. Flash memory normally needs to be erased
4731 before it's written. Erasing a sector turns all of its bits to ones, and
4732 writing can turn ones into zeroes. This is why there are special commands
4733 for interactive erasing and writing, and why GDB needs to know which parts
4734 of the address space hold NOR flash memory.
4736 @quotation Note
4737 Most of these erase and write commands leverage the fact that NOR flash
4738 chips consume target address space. They implicitly refer to the current
4739 JTAG target, and map from an address in that target's address space
4740 back to a flash bank.
4741 @comment In May 2009, those mappings may fail if any bank associated
4742 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
4743 A few commands use abstract addressing based on bank and sector numbers,
4744 and don't depend on searching the current target and its address space.
4745 Avoid confusing the two command models.
4746 @end quotation
4748 Some flash chips implement software protection against accidental writes,
4749 since such buggy writes could in some cases ``brick'' a system.
4750 For such systems, erasing and writing may require sector protection to be
4751 disabled first.
4752 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4753 and AT91SAM7 on-chip flash.
4754 @xref{flashprotect,,flash protect}.
4756 @deffn Command {flash erase_sector} num first last
4757 Erase sectors in bank @var{num}, starting at sector @var{first}
4758 up to and including @var{last}.
4759 Sector numbering starts at 0.
4760 Providing a @var{last} sector of @option{last}
4761 specifies "to the end of the flash bank".
4762 The @var{num} parameter is a value shown by @command{flash banks}.
4763 @end deffn
4765 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4766 Erase sectors starting at @var{address} for @var{length} bytes.
4767 Unless @option{pad} is specified, @math{address} must begin a
4768 flash sector, and @math{address + length - 1} must end a sector.
4769 Specifying @option{pad} erases extra data at the beginning and/or
4770 end of the specified region, as needed to erase only full sectors.
4771 The flash bank to use is inferred from the @var{address}, and
4772 the specified length must stay within that bank.
4773 As a special case, when @var{length} is zero and @var{address} is
4774 the start of the bank, the whole flash is erased.
4775 If @option{unlock} is specified, then the flash is unprotected
4776 before erase starts.
4777 @end deffn
4779 @deffn Command {flash fillw} address word length
4780 @deffnx Command {flash fillh} address halfword length
4781 @deffnx Command {flash fillb} address byte length
4782 Fills flash memory with the specified @var{word} (32 bits),
4783 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4784 starting at @var{address} and continuing
4785 for @var{length} units (word/halfword/byte).
4786 No erasure is done before writing; when needed, that must be done
4787 before issuing this command.
4788 Writes are done in blocks of up to 1024 bytes, and each write is
4789 verified by reading back the data and comparing it to what was written.
4790 The flash bank to use is inferred from the @var{address} of
4791 each block, and the specified length must stay within that bank.
4792 @end deffn
4793 @comment no current checks for errors if fill blocks touch multiple banks!
4795 @deffn Command {flash write_bank} num filename offset
4796 Write the binary @file{filename} to flash bank @var{num},
4797 starting at @var{offset} bytes from the beginning of the bank.
4798 The @var{num} parameter is a value shown by @command{flash banks}.
4799 @end deffn
4801 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4802 Write the image @file{filename} to the current target's flash bank(s).
4803 A relocation @var{offset} may be specified, in which case it is added
4804 to the base address for each section in the image.
4805 The file [@var{type}] can be specified
4806 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4807 @option{elf} (ELF file), @option{s19} (Motorola s19).
4808 @option{mem}, or @option{builder}.
4809 The relevant flash sectors will be erased prior to programming
4810 if the @option{erase} parameter is given. If @option{unlock} is
4811 provided, then the flash banks are unlocked before erase and
4812 program. The flash bank to use is inferred from the address of
4813 each image section.
4815 @quotation Warning
4816 Be careful using the @option{erase} flag when the flash is holding
4817 data you want to preserve.
4818 Portions of the flash outside those described in the image's
4819 sections might be erased with no notice.
4820 @itemize
4821 @item
4822 When a section of the image being written does not fill out all the
4823 sectors it uses, the unwritten parts of those sectors are necessarily
4824 also erased, because sectors can't be partially erased.
4825 @item
4826 Data stored in sector "holes" between image sections are also affected.
4827 For example, "@command{flash write_image erase ...}" of an image with
4828 one byte at the beginning of a flash bank and one byte at the end
4829 erases the entire bank -- not just the two sectors being written.
4830 @end itemize
4831 Also, when flash protection is important, you must re-apply it after
4832 it has been removed by the @option{unlock} flag.
4833 @end quotation
4835 @end deffn
4837 @section Other Flash commands
4838 @cindex flash protection
4840 @deffn Command {flash erase_check} num
4841 Check erase state of sectors in flash bank @var{num},
4842 and display that status.
4843 The @var{num} parameter is a value shown by @command{flash banks}.
4844 @end deffn
4846 @deffn Command {flash info} num
4847 Print info about flash bank @var{num}
4848 The @var{num} parameter is a value shown by @command{flash banks}.
4849 This command will first query the hardware, it does not print cached
4850 and possibly stale information.
4851 @end deffn
4853 @anchor{flashprotect}
4854 @deffn Command {flash protect} num first last (@option{on}|@option{off})
4855 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
4856 in flash bank @var{num}, starting at sector @var{first}
4857 and continuing up to and including @var{last}.
4858 Providing a @var{last} sector of @option{last}
4859 specifies "to the end of the flash bank".
4860 The @var{num} parameter is a value shown by @command{flash banks}.
4861 @end deffn
4863 @deffn Command {flash padded_value} num value
4864 Sets the default value used for padding any image sections, This should
4865 normally match the flash bank erased value. If not specified by this
4866 comamnd or the flash driver then it defaults to 0xff.
4867 @end deffn
4869 @anchor{program}
4870 @deffn Command {program} filename [verify] [reset] [offset]
4871 This is a helper script that simplifies using OpenOCD as a standalone
4872 programmer. The only required parameter is @option{filename}, the others are optional.
4873 @xref{Flash Programming}.
4874 @end deffn
4876 @anchor{flashdriverlist}
4877 @section Flash Driver List
4878 As noted above, the @command{flash bank} command requires a driver name,
4879 and allows driver-specific options and behaviors.
4880 Some drivers also activate driver-specific commands.
4882 @subsection External Flash
4884 @deffn {Flash Driver} cfi
4885 @cindex Common Flash Interface
4886 @cindex CFI
4887 The ``Common Flash Interface'' (CFI) is the main standard for
4888 external NOR flash chips, each of which connects to a
4889 specific external chip select on the CPU.
4890 Frequently the first such chip is used to boot the system.
4891 Your board's @code{reset-init} handler might need to
4892 configure additional chip selects using other commands (like: @command{mww} to
4893 configure a bus and its timings), or
4894 perhaps configure a GPIO pin that controls the ``write protect'' pin
4895 on the flash chip.
4896 The CFI driver can use a target-specific working area to significantly
4897 speed up operation.
4899 The CFI driver can accept the following optional parameters, in any order:
4901 @itemize
4902 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
4903 like AM29LV010 and similar types.
4904 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
4905 @end itemize
4907 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
4908 wide on a sixteen bit bus:
4910 @example
4911 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
4912 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
4913 @end example
4915 To configure one bank of 32 MBytes
4916 built from two sixteen bit (two byte) wide parts wired in parallel
4917 to create a thirty-two bit (four byte) bus with doubled throughput:
4919 @example
4920 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
4921 @end example
4923 @c "cfi part_id" disabled
4924 @end deffn
4926 @deffn {Flash Driver} lpcspifi
4927 @cindex NXP SPI Flash Interface
4928 @cindex SPIFI
4929 @cindex lpcspifi
4930 NXP's LPC43xx and LPC18xx families include a proprietary SPI
4931 Flash Interface (SPIFI) peripheral that can drive and provide
4932 memory mapped access to external SPI flash devices.
4934 The lpcspifi driver initializes this interface and provides
4935 program and erase functionality for these serial flash devices.
4936 Use of this driver @b{requires} a working area of at least 1kB
4937 to be configured on the target device; more than this will
4938 significantly reduce flash programming times.
4940 The setup command only requires the @var{base} parameter. All
4941 other parameters are ignored, and the flash size and layout
4942 are configured by the driver.
4944 @example
4945 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
4946 @end example
4948 @end deffn
4950 @deffn {Flash Driver} stmsmi
4951 @cindex STMicroelectronics Serial Memory Interface
4952 @cindex SMI
4953 @cindex stmsmi
4954 Some devices form STMicroelectronics (e.g. STR75x MCU family,
4955 SPEAr MPU family) include a proprietary
4956 ``Serial Memory Interface'' (SMI) controller able to drive external
4957 SPI flash devices.
4958 Depending on specific device and board configuration, up to 4 external
4959 flash devices can be connected.
4961 SMI makes the flash content directly accessible in the CPU address
4962 space; each external device is mapped in a memory bank.
4963 CPU can directly read data, execute code and boot from SMI banks.
4964 Normal OpenOCD commands like @command{mdw} can be used to display
4965 the flash content.
4967 The setup command only requires the @var{base} parameter in order
4968 to identify the memory bank.
4969 All other parameters are ignored. Additional information, like
4970 flash size, are detected automatically.
4972 @example
4973 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
4974 @end example
4976 @end deffn
4978 @subsection Internal Flash (Microcontrollers)
4980 @deffn {Flash Driver} aduc702x
4981 The ADUC702x analog microcontrollers from Analog Devices
4982 include internal flash and use ARM7TDMI cores.
4983 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
4984 The setup command only requires the @var{target} argument
4985 since all devices in this family have the same memory layout.
4987 @example
4988 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
4989 @end example
4990 @end deffn
4992 @anchor{at91sam3}
4993 @deffn {Flash Driver} at91sam3
4994 @cindex at91sam3
4995 All members of the AT91SAM3 microcontroller family from
4996 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
4997 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
4998 that the driver was orginaly developed and tested using the
4999 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
5000 the family was cribbed from the data sheet. @emph{Note to future
5001 readers/updaters: Please remove this worrysome comment after other
5002 chips are confirmed.}
5004 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
5005 have one flash bank. In all cases the flash banks are at
5006 the following fixed locations:
5008 @example
5009 # Flash bank 0 - all chips
5010 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
5011 # Flash bank 1 - only 256K chips
5012 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
5013 @end example
5015 Internally, the AT91SAM3 flash memory is organized as follows.
5016 Unlike the AT91SAM7 chips, these are not used as parameters
5017 to the @command{flash bank} command:
5019 @itemize
5020 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
5021 @item @emph{Bank Size:} 128K/64K Per flash bank
5022 @item @emph{Sectors:} 16 or 8 per bank
5023 @item @emph{SectorSize:} 8K Per Sector
5024 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
5025 @end itemize
5027 The AT91SAM3 driver adds some additional commands:
5029 @deffn Command {at91sam3 gpnvm}
5030 @deffnx Command {at91sam3 gpnvm clear} number
5031 @deffnx Command {at91sam3 gpnvm set} number
5032 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
5033 With no parameters, @command{show} or @command{show all},
5034 shows the status of all GPNVM bits.
5035 With @command{show} @var{number}, displays that bit.
5037 With @command{set} @var{number} or @command{clear} @var{number},
5038 modifies that GPNVM bit.
5039 @end deffn
5041 @deffn Command {at91sam3 info}
5042 This command attempts to display information about the AT91SAM3
5043 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
5044 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
5045 document id: doc6430A] and decodes the values. @emph{Second} it reads the
5046 various clock configuration registers and attempts to display how it
5047 believes the chip is configured. By default, the SLOWCLK is assumed to
5048 be 32768 Hz, see the command @command{at91sam3 slowclk}.
5049 @end deffn
5051 @deffn Command {at91sam3 slowclk} [value]
5052 This command shows/sets the slow clock frequency used in the
5053 @command{at91sam3 info} command calculations above.
5054 @end deffn
5055 @end deffn
5057 @deffn {Flash Driver} at91sam4
5058 @cindex at91sam4
5059 All members of the AT91SAM4 microcontroller family from
5060 Atmel include internal flash and use ARM's Cortex-M4 core.
5061 This driver uses the same cmd names/syntax as @xref{at91sam3}.
5062 @end deffn
5064 @deffn {Flash Driver} at91sam7