nrf51: Implement the support for Nordic's nRF51 devices
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * NAND Flash Commands:: NAND Flash Commands
77 * PLD/FPGA Commands:: PLD/FPGA Commands
78 * General Commands:: General Commands
79 * Architecture and Core Commands:: Architecture and Core Commands
80 * JTAG Commands:: JTAG Commands
81 * Boundary Scan Commands:: Boundary Scan Commands
82 * Utility Commands:: Utility Commands
83 * TFTP:: TFTP
84 * GDB and OpenOCD:: Using GDB and OpenOCD
85 * Tcl Scripting API:: Tcl Scripting API
86 * FAQ:: Frequently Asked Questions
87 * Tcl Crash Course:: Tcl Crash Course
88 * License:: GNU Free Documentation License
90 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
91 @comment case issue with ``Index.html'' and ``index.html''
92 @comment Occurs when creating ``--html --no-split'' output
93 @comment This fix is based on:
94 * OpenOCD Concept Index:: Concept Index
95 * Command and Driver Index:: Command and Driver Index
96 @end menu
98 @node About
99 @unnumbered About
100 @cindex about
102 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
103 at the University of Applied Sciences Augsburg (@uref{}).
104 Since that time, the project has grown into an active open-source project,
105 supported by a diverse community of software and hardware developers from
106 around the world.
108 @section What is OpenOCD?
109 @cindex TAP
110 @cindex JTAG
112 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
113 in-system programming and boundary-scan testing for embedded target
114 devices.
116 It does so with the assistance of a @dfn{debug adapter}, which is
117 a small hardware module which helps provide the right kind of
118 electrical signaling to the target being debugged. These are
119 required since the debug host (on which OpenOCD runs) won't
120 usually have native support for such signaling, or the connector
121 needed to hook up to the target.
123 Such debug adapters support one or more @dfn{transport} protocols,
124 each of which involves different electrical signaling (and uses
125 different messaging protocols on top of that signaling). There
126 are many types of debug adapter, and little uniformity in what
127 they are called. (There are also product naming differences.)
129 These adapters are sometimes packaged as discrete dongles, which
130 may generically be called @dfn{hardware interface dongles}.
131 Some development boards also integrate them directly, which may
132 let the development board connect directly to the debug
133 host over USB (and sometimes also to power it over USB).
135 For example, a @dfn{JTAG Adapter} supports JTAG
136 signaling, and is used to communicate
137 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
138 A @dfn{TAP} is a ``Test Access Port'', a module which processes
139 special instructions and data. TAPs are daisy-chained within and
140 between chips and boards. JTAG supports debugging and boundary
141 scan operations.
143 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
144 signaling to communicate with some newer ARM cores, as well as debug
145 adapters which support both JTAG and SWD transports. SWD supports only
146 debugging, whereas JTAG also supports boundary scan operations.
148 For some chips, there are also @dfn{Programming Adapters} supporting
149 special transports used only to write code to flash memory, without
150 support for on-chip debugging or boundary scan.
151 (At this writing, OpenOCD does not support such non-debug adapters.)
154 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
155 USB-based, parallel port-based, and other standalone boxes that run
156 OpenOCD internally. @xref{Debug Adapter Hardware}.
158 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
159 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
160 (Stellaris LM3, ST STM32 and Energy Micro EFM32) and Intel Quark (x10xx)
161 based cores to be debugged via the GDB protocol.
163 @b{Flash Programming:} Flash writing is supported for external
164 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
165 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
166 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
167 controllers (LPC3180, Orion, S3C24xx, more) is included.
169 @section OpenOCD Web Site
171 The OpenOCD web site provides the latest public news from the community:
173 @uref{}
175 @section Latest User's Guide:
177 The user's guide you are now reading may not be the latest one
178 available. A version for more recent code may be available.
179 Its HTML form is published regularly at:
181 @uref{}
183 PDF form is likewise published at:
185 @uref{}
187 @section OpenOCD User's Forum
189 There is an OpenOCD forum (phpBB) hosted by SparkFun,
190 which might be helpful to you. Note that if you want
191 anything to come to the attention of developers, you
192 should post it to the OpenOCD Developer Mailing List
193 instead of this forum.
195 @uref{}
197 @section OpenOCD User's Mailing List
199 The OpenOCD User Mailing List provides the primary means of
200 communication between users:
202 @uref{}
204 @section OpenOCD IRC
206 Support can also be found on irc:
207 @uref{irc://}
209 @node Developers
210 @chapter OpenOCD Developer Resources
211 @cindex developers
213 If you are interested in improving the state of OpenOCD's debugging and
214 testing support, new contributions will be welcome. Motivated developers
215 can produce new target, flash or interface drivers, improve the
216 documentation, as well as more conventional bug fixes and enhancements.
218 The resources in this chapter are available for developers wishing to explore
219 or expand the OpenOCD source code.
221 @section OpenOCD Git Repository
223 During the 0.3.x release cycle, OpenOCD switched from Subversion to
224 a Git repository hosted at SourceForge. The repository URL is:
226 @uref{git://}
228 or via http
230 @uref{}
232 You may prefer to use a mirror and the HTTP protocol:
234 @uref{}
236 With standard Git tools, use @command{git clone} to initialize
237 a local repository, and @command{git pull} to update it.
238 There are also gitweb pages letting you browse the repository
239 with a web browser, or download arbitrary snapshots without
240 needing a Git client:
242 @uref{}
244 The @file{README} file contains the instructions for building the project
245 from the repository or a snapshot.
247 Developers that want to contribute patches to the OpenOCD system are
248 @b{strongly} encouraged to work against mainline.
249 Patches created against older versions may require additional
250 work from their submitter in order to be updated for newer releases.
252 @section Doxygen Developer Manual
254 During the 0.2.x release cycle, the OpenOCD project began
255 providing a Doxygen reference manual. This document contains more
256 technical information about the software internals, development
257 processes, and similar documentation:
259 @uref{}
261 This document is a work-in-progress, but contributions would be welcome
262 to fill in the gaps. All of the source files are provided in-tree,
263 listed in the Doxyfile configuration at the top of the source tree.
265 @section Gerrit Review System
267 All changes in the OpenOCD Git repository go through the web-based Gerrit
268 Code Review System:
270 @uref{}
272 After a one-time registration and repository setup, anyone can push commits
273 from their local Git repository directly into Gerrit.
274 All users and developers are encouraged to review, test, discuss and vote
275 for changes in Gerrit. The feedback provides the basis for a maintainer to
276 eventually submit the change to the main Git repository.
278 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
279 Developer Manual, contains basic information about how to connect a
280 repository to Gerrit, prepare and push patches. Patch authors are expected to
281 maintain their changes while they're in Gerrit, respond to feedback and if
282 necessary rework and push improved versions of the change.
284 @section OpenOCD Developer Mailing List
286 The OpenOCD Developer Mailing List provides the primary means of
287 communication between developers:
289 @uref{}
291 @section OpenOCD Bug Database
293 During the 0.4.x release cycle the OpenOCD project team began
294 using Trac for its bug database:
296 @uref{}
299 @node Debug Adapter Hardware
300 @chapter Debug Adapter Hardware
301 @cindex dongles
302 @cindex FTDI
303 @cindex wiggler
304 @cindex zy1000
305 @cindex printer port
306 @cindex USB Adapter
307 @cindex RTCK
309 Defined: @b{dongle}: A small device that plugs into a computer and serves as
310 an adapter .... [snip]
312 In the OpenOCD case, this generally refers to @b{a small adapter} that
313 attaches to your computer via USB or the parallel port. One
314 exception is the Ultimate Solutions ZY1000, packaged as a small box you
315 attach via an ethernet cable. The ZY1000 has the advantage that it does not
316 require any drivers to be installed on the developer PC. It also has
317 a built in web interface. It supports RTCK/RCLK or adaptive clocking
318 and has a built-in relay to power cycle targets remotely.
321 @section Choosing a Dongle
323 There are several things you should keep in mind when choosing a dongle.
325 @enumerate
326 @item @b{Transport} Does it support the kind of communication that you need?
327 OpenOCD focusses mostly on JTAG. Your version may also support
328 other ways to communicate with target devices.
329 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
330 Does your dongle support it? You might need a level converter.
331 @item @b{Pinout} What pinout does your target board use?
332 Does your dongle support it? You may be able to use jumper
333 wires, or an "octopus" connector, to convert pinouts.
334 @item @b{Connection} Does your computer have the USB, parallel, or
335 Ethernet port needed?
336 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
337 RTCK support (also known as ``adaptive clocking'')?
338 @end enumerate
340 @section Stand-alone JTAG Probe
342 The ZY1000 from Ultimate Solutions is technically not a dongle but a
343 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
344 running on the developer's host computer.
345 Once installed on a network using DHCP or a static IP assignment, users can
346 access the ZY1000 probe locally or remotely from any host with access to the
347 IP address assigned to the probe.
348 The ZY1000 provides an intuitive web interface with direct access to the
349 OpenOCD debugger.
350 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
351 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
352 the target.
353 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
354 to power cycle the target remotely.
356 For more information, visit:
358 @b{ZY1000} See: @url{}
360 @section USB FT2232 Based
362 There are many USB JTAG dongles on the market, many of them based
363 on a chip from ``Future Technology Devices International'' (FTDI)
364 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
365 See: @url{} for more information.
366 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
367 chips started to become available in JTAG adapters. Around 2012, a new
368 variant appeared - FT232H - this is a single-channel version of FT2232H.
369 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
370 clocking.)
372 The FT2232 chips are flexible enough to support some other
373 transport options, such as SWD or the SPI variants used to
374 program some chips. They have two communications channels,
375 and one can be used for a UART adapter at the same time the
376 other one is used to provide a debug adapter.
378 Also, some development boards integrate an FT2232 chip to serve as
379 a built-in low-cost debug adapter and USB-to-serial solution.
381 @itemize @bullet
382 @item @b{usbjtag}
383 @* Link @url{}
384 @item @b{jtagkey}
385 @* See: @url{}
386 @item @b{jtagkey2}
387 @* See: @url{}
388 @item @b{oocdlink}
389 @* See: @url{} By Joern Kaipf
390 @item @b{signalyzer}
391 @* See: @url{}
392 @item @b{Stellaris Eval Boards}
393 @* See: @url{} - The Stellaris eval boards
394 bundle FT2232-based JTAG and SWD support, which can be used to debug
395 the Stellaris chips. Using separate JTAG adapters is optional.
396 These boards can also be used in a "pass through" mode as JTAG adapters
397 to other target boards, disabling the Stellaris chip.
398 @item @b{TI/Luminary ICDI}
399 @* See: @url{} - TI/Luminary In-Circuit Debug
400 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
401 Evaluation Kits. Like the non-detachable FT2232 support on the other
402 Stellaris eval boards, they can be used to debug other target boards.
403 @item @b{olimex-jtag}
404 @* See: @url{}
405 @item @b{Flyswatter/Flyswatter2}
406 @* See: @url{}
407 @item @b{turtelizer2}
408 @* See:
409 @uref{, Turtelizer 2}, or
410 @url{}
411 @item @b{comstick}
412 @* Link: @url{}
413 @item @b{stm32stick}
414 @* Link @url{}
415 @item @b{axm0432_jtag}
416 @* Axiom AXM-0432 Link @url{} - NOTE: This JTAG does not appear
417 to be available anymore as of April 2012.
418 @item @b{cortino}
419 @* Link @url{}
420 @item @b{dlp-usb1232h}
421 @* Link @url{}
422 @item @b{digilent-hs1}
423 @* Link @url{}
424 @item @b{opendous}
425 @* Link @url{} FT2232H-based
426 (OpenHardware).
427 @item @b{JTAG-lock-pick Tiny 2}
428 @* Link @url{} FT232H-based
430 @item @b{GW16042}
431 @* Link: @url{}
432 FT2232H-based
434 @end itemize
435 @section USB-JTAG / Altera USB-Blaster compatibles
437 These devices also show up as FTDI devices, but are not
438 protocol-compatible with the FT2232 devices. They are, however,
439 protocol-compatible among themselves. USB-JTAG devices typically consist
440 of a FT245 followed by a CPLD that understands a particular protocol,
441 or emulates this protocol using some other hardware.
443 They may appear under different USB VID/PID depending on the particular
444 product. The driver can be configured to search for any VID/PID pair
445 (see the section on driver commands).
447 @itemize
448 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
449 @* Link: @url{}
450 @item @b{Altera USB-Blaster}
451 @* Link: @url{}
452 @end itemize
454 @section USB JLINK based
455 There are several OEM versions of the Segger @b{JLINK} adapter. It is
456 an example of a micro controller based JTAG adapter, it uses an
457 AT91SAM764 internally.
459 @itemize @bullet
460 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
461 @* Link: @url{}
462 @item @b{SEGGER JLINK}
463 @* Link: @url{}
464 @item @b{IAR J-Link}
465 @* Link: @url{}
466 @end itemize
468 @section USB RLINK based
469 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
470 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
471 SWD and not JTAG, thus not supported.
473 @itemize @bullet
474 @item @b{Raisonance RLink}
475 @* Link: @url{}
476 @item @b{STM32 Primer}
477 @* Link: @url{}
478 @item @b{STM32 Primer2}
479 @* Link: @url{}
480 @end itemize
482 @section USB ST-LINK based
483 ST Micro has an adapter called @b{ST-LINK}.
484 They only work with ST Micro chips, notably STM32 and STM8.
486 @itemize @bullet
487 @item @b{ST-LINK}
488 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
489 @* Link: @url{}
490 @item @b{ST-LINK/V2}
491 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
492 @* Link: @url{}
493 @end itemize
495 For info the original ST-LINK enumerates using the mass storage usb class; however,
496 its implementation is completely broken. The result is this causes issues under Linux.
497 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
498 @itemize @bullet
499 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
500 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
501 @end itemize
503 @section USB TI/Stellaris ICDI based
504 Texas Instruments has an adapter called @b{ICDI}.
505 It is not to be confused with the FTDI based adapters that were originally fitted to their
506 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
508 @section USB CMSIS-DAP based
509 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
510 debuggers to ARM Cortex based targets @url{}.
512 @section USB Other
513 @itemize @bullet
514 @item @b{USBprog}
515 @* Link: @url{} - which uses an Atmel MEGA32 and a UBN9604
517 @item @b{USB - Presto}
518 @* Link: @url{}
520 @item @b{Versaloon-Link}
521 @* Link: @url{}
523 @item @b{ARM-JTAG-EW}
524 @* Link: @url{}
526 @item @b{Buspirate}
527 @* Link: @url{}
529 @item @b{opendous}
530 @* Link: @url{} - which uses an AT90USB162
532 @item @b{estick}
533 @* Link: @url{}
535 @item @b{Keil ULINK v1}
536 @* Link: @url{}
537 @end itemize
539 @section IBM PC Parallel Printer Port Based
541 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
542 and the Macraigor Wiggler. There are many clones and variations of
543 these on the market.
545 Note that parallel ports are becoming much less common, so if you
546 have the choice you should probably avoid these adapters in favor
547 of USB-based ones.
549 @itemize @bullet
551 @item @b{Wiggler} - There are many clones of this.
552 @* Link: @url{}
554 @item @b{DLC5} - From XILINX - There are many clones of this
555 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
556 produced, PDF schematics are easily found and it is easy to make.
558 @item @b{Amontec - JTAG Accelerator}
559 @* Link: @url{}
561 @item @b{Wiggler2}
562 @* Link: @url{}
564 @item @b{Wiggler_ntrst_inverted}
565 @* Yet another variation - See the source code, src/jtag/parport.c
567 @item @b{old_amt_wiggler}
568 @* Unknown - probably not on the market today
570 @item @b{arm-jtag}
571 @* Link: Most likely @url{} [another wiggler clone]
573 @item @b{chameleon}
574 @* Link: @url{}
576 @item @b{Triton}
577 @* Unknown.
579 @item @b{Lattice}
580 @* ispDownload from Lattice Semiconductor
581 @url{}
583 @item @b{flashlink}
584 @* From ST Microsystems;
585 @* Link: @url{}
587 @end itemize
589 @section Other...
590 @itemize @bullet
592 @item @b{ep93xx}
593 @* An EP93xx based Linux machine using the GPIO pins directly.
595 @item @b{at91rm9200}
596 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
598 @item @b{bcm2835gpio}
599 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
601 @item @b{jtag_vpi}
602 @* A JTAG driver acting as a client for the JTAG VPI server interface.
603 @* Link: @url{}
605 @end itemize
607 @node About Jim-Tcl
608 @chapter About Jim-Tcl
609 @cindex Jim-Tcl
610 @cindex tcl
612 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
613 This programming language provides a simple and extensible
614 command interpreter.
616 All commands presented in this Guide are extensions to Jim-Tcl.
617 You can use them as simple commands, without needing to learn
618 much of anything about Tcl.
619 Alternatively, you can write Tcl programs with them.
621 You can learn more about Jim at its website, @url{}.
622 There is an active and responsive community, get on the mailing list
623 if you have any questions. Jim-Tcl maintainers also lurk on the
624 OpenOCD mailing list.
626 @itemize @bullet
627 @item @b{Jim vs. Tcl}
628 @* Jim-Tcl is a stripped down version of the well known Tcl language,
629 which can be found here: @url{}. Jim-Tcl has far
630 fewer features. Jim-Tcl is several dozens of .C files and .H files and
631 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
632 4.2 MB .zip file containing 1540 files.
634 @item @b{Missing Features}
635 @* Our practice has been: Add/clone the real Tcl feature if/when
636 needed. We welcome Jim-Tcl improvements, not bloat. Also there
637 are a large number of optional Jim-Tcl features that are not
638 enabled in OpenOCD.
640 @item @b{Scripts}
641 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
642 command interpreter today is a mixture of (newer)
643 Jim-Tcl commands, and the (older) original command interpreter.
645 @item @b{Commands}
646 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
647 can type a Tcl for() loop, set variables, etc.
648 Some of the commands documented in this guide are implemented
649 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
651 @item @b{Historical Note}
652 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
653 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
654 as a Git submodule, which greatly simplified upgrading Jim-Tcl
655 to benefit from new features and bugfixes in Jim-Tcl.
657 @item @b{Need a crash course in Tcl?}
658 @*@xref{Tcl Crash Course}.
659 @end itemize
661 @node Running
662 @chapter Running
663 @cindex command line options
664 @cindex logfile
665 @cindex directory search
667 Properly installing OpenOCD sets up your operating system to grant it access
668 to the debug adapters. On Linux, this usually involves installing a file
669 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
670 complex and confusing driver configuration for every peripheral. Such issues
671 are unique to each operating system, and are not detailed in this User's Guide.
673 Then later you will invoke the OpenOCD server, with various options to
674 tell it how each debug session should work.
675 The @option{--help} option shows:
676 @verbatim
677 bash$ openocd --help
679 --help | -h display this help
680 --version | -v display OpenOCD version
681 --file | -f use configuration file <name>
682 --search | -s dir to search for config files and scripts
683 --debug | -d set debug level <0-3>
684 --log_output | -l redirect log output to file <name>
685 --command | -c run <command>
686 @end verbatim
688 If you don't give any @option{-f} or @option{-c} options,
689 OpenOCD tries to read the configuration file @file{openocd.cfg}.
690 To specify one or more different
691 configuration files, use @option{-f} options. For example:
693 @example
694 openocd -f config1.cfg -f config2.cfg -f config3.cfg
695 @end example
697 Configuration files and scripts are searched for in
698 @enumerate
699 @item the current directory,
700 @item any search dir specified on the command line using the @option{-s} option,
701 @item any search dir specified using the @command{add_script_search_dir} command,
702 @item @file{$HOME/.openocd} (not on Windows),
703 @item the site wide script library @file{$pkgdatadir/site} and
704 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
705 @end enumerate
706 The first found file with a matching file name will be used.
708 @quotation Note
709 Don't try to use configuration script names or paths which
710 include the "#" character. That character begins Tcl comments.
711 @end quotation
713 @section Simple setup, no customization
715 In the best case, you can use two scripts from one of the script
716 libraries, hook up your JTAG adapter, and start the server ... and
717 your JTAG setup will just work "out of the box". Always try to
718 start by reusing those scripts, but assume you'll need more
719 customization even if this works. @xref{OpenOCD Project Setup}.
721 If you find a script for your JTAG adapter, and for your board or
722 target, you may be able to hook up your JTAG adapter then start
723 the server with some variation of one of the following:
725 @example
726 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
727 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
728 @end example
730 You might also need to configure which reset signals are present,
731 using @option{-c 'reset_config trst_and_srst'} or something similar.
732 If all goes well you'll see output something like
734 @example
735 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
736 For bug reports, read
738 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
739 (mfg: 0x23b, part: 0xba00, ver: 0x3)
740 @end example
742 Seeing that "tap/device found" message, and no warnings, means
743 the JTAG communication is working. That's a key milestone, but
744 you'll probably need more project-specific setup.
746 @section What OpenOCD does as it starts
748 OpenOCD starts by processing the configuration commands provided
749 on the command line or, if there were no @option{-c command} or
750 @option{-f file.cfg} options given, in @file{openocd.cfg}.
751 @xref{configurationstage,,Configuration Stage}.
752 At the end of the configuration stage it verifies the JTAG scan
753 chain defined using those commands; your configuration should
754 ensure that this always succeeds.
755 Normally, OpenOCD then starts running as a daemon.
756 Alternatively, commands may be used to terminate the configuration
757 stage early, perform work (such as updating some flash memory),
758 and then shut down without acting as a daemon.
760 Once OpenOCD starts running as a daemon, it waits for connections from
761 clients (Telnet, GDB, Other) and processes the commands issued through
762 those channels.
764 If you are having problems, you can enable internal debug messages via
765 the @option{-d} option.
767 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
768 @option{-c} command line switch.
770 To enable debug output (when reporting problems or working on OpenOCD
771 itself), use the @option{-d} command line switch. This sets the
772 @option{debug_level} to "3", outputting the most information,
773 including debug messages. The default setting is "2", outputting only
774 informational messages, warnings and errors. You can also change this
775 setting from within a telnet or gdb session using @command{debug_level<n>}
776 (@pxref{debuglevel,,debug_level}).
778 You can redirect all output from the daemon to a file using the
779 @option{-l <logfile>} switch.
781 Note! OpenOCD will launch the GDB & telnet server even if it can not
782 establish a connection with the target. In general, it is possible for
783 the JTAG controller to be unresponsive until the target is set up
784 correctly via e.g. GDB monitor commands in a GDB init script.
786 @node OpenOCD Project Setup
787 @chapter OpenOCD Project Setup
789 To use OpenOCD with your development projects, you need to do more than
790 just connect the JTAG adapter hardware (dongle) to your development board
791 and start the OpenOCD server.
792 You also need to configure your OpenOCD server so that it knows
793 about your adapter and board, and helps your work.
794 You may also want to connect OpenOCD to GDB, possibly
795 using Eclipse or some other GUI.
797 @section Hooking up the JTAG Adapter
799 Today's most common case is a dongle with a JTAG cable on one side
800 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
801 and a USB cable on the other.
802 Instead of USB, some cables use Ethernet;
803 older ones may use a PC parallel port, or even a serial port.
805 @enumerate
806 @item @emph{Start with power to your target board turned off},
807 and nothing connected to your JTAG adapter.
808 If you're particularly paranoid, unplug power to the board.
809 It's important to have the ground signal properly set up,
810 unless you are using a JTAG adapter which provides
811 galvanic isolation between the target board and the
812 debugging host.
814 @item @emph{Be sure it's the right kind of JTAG connector.}
815 If your dongle has a 20-pin ARM connector, you need some kind
816 of adapter (or octopus, see below) to hook it up to
817 boards using 14-pin or 10-pin connectors ... or to 20-pin
818 connectors which don't use ARM's pinout.
820 In the same vein, make sure the voltage levels are compatible.
821 Not all JTAG adapters have the level shifters needed to work
822 with 1.2 Volt boards.
824 @item @emph{Be certain the cable is properly oriented} or you might
825 damage your board. In most cases there are only two possible
826 ways to connect the cable.
827 Connect the JTAG cable from your adapter to the board.
828 Be sure it's firmly connected.
830 In the best case, the connector is keyed to physically
831 prevent you from inserting it wrong.
832 This is most often done using a slot on the board's male connector
833 housing, which must match a key on the JTAG cable's female connector.
834 If there's no housing, then you must look carefully and
835 make sure pin 1 on the cable hooks up to pin 1 on the board.
836 Ribbon cables are frequently all grey except for a wire on one
837 edge, which is red. The red wire is pin 1.
839 Sometimes dongles provide cables where one end is an ``octopus'' of
840 color coded single-wire connectors, instead of a connector block.
841 These are great when converting from one JTAG pinout to another,
842 but are tedious to set up.
843 Use these with connector pinout diagrams to help you match up the
844 adapter signals to the right board pins.
846 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
847 A USB, parallel, or serial port connector will go to the host which
848 you are using to run OpenOCD.
849 For Ethernet, consult the documentation and your network administrator.
851 For USB-based JTAG adapters you have an easy sanity check at this point:
852 does the host operating system see the JTAG adapter? If you're running
853 Linux, try the @command{lsusb} command. If that host is an
854 MS-Windows host, you'll need to install a driver before OpenOCD works.
856 @item @emph{Connect the adapter's power supply, if needed.}
857 This step is primarily for non-USB adapters,
858 but sometimes USB adapters need extra power.
860 @item @emph{Power up the target board.}
861 Unless you just let the magic smoke escape,
862 you're now ready to set up the OpenOCD server
863 so you can use JTAG to work with that board.
865 @end enumerate
867 Talk with the OpenOCD server using
868 telnet (@code{telnet localhost 4444} on many systems) or GDB.
869 @xref{GDB and OpenOCD}.
871 @section Project Directory
873 There are many ways you can configure OpenOCD and start it up.
875 A simple way to organize them all involves keeping a
876 single directory for your work with a given board.
877 When you start OpenOCD from that directory,
878 it searches there first for configuration files, scripts,
879 files accessed through semihosting,
880 and for code you upload to the target board.
881 It is also the natural place to write files,
882 such as log files and data you download from the board.
884 @section Configuration Basics
886 There are two basic ways of configuring OpenOCD, and
887 a variety of ways you can mix them.
888 Think of the difference as just being how you start the server:
890 @itemize
891 @item Many @option{-f file} or @option{-c command} options on the command line
892 @item No options, but a @dfn{user config file}
893 in the current directory named @file{openocd.cfg}
894 @end itemize
896 Here is an example @file{openocd.cfg} file for a setup
897 using a Signalyzer FT2232-based JTAG adapter to talk to
898 a board with an Atmel AT91SAM7X256 microcontroller:
900 @example
901 source [find interface/signalyzer.cfg]
903 # GDB can also flash my flash!
904 gdb_memory_map enable
905 gdb_flash_program enable
907 source [find target/sam7x256.cfg]
908 @end example
910 Here is the command line equivalent of that configuration:
912 @example
913 openocd -f interface/signalyzer.cfg \
914 -c "gdb_memory_map enable" \
915 -c "gdb_flash_program enable" \
916 -f target/sam7x256.cfg
917 @end example
919 You could wrap such long command lines in shell scripts,
920 each supporting a different development task.
921 One might re-flash the board with a specific firmware version.
922 Another might set up a particular debugging or run-time environment.
924 @quotation Important
925 At this writing (October 2009) the command line method has
926 problems with how it treats variables.
927 For example, after @option{-c "set VAR value"}, or doing the
928 same in a script, the variable @var{VAR} will have no value
929 that can be tested in a later script.
930 @end quotation
932 Here we will focus on the simpler solution: one user config
933 file, including basic configuration plus any TCL procedures
934 to simplify your work.
936 @section User Config Files
937 @cindex config file, user
938 @cindex user config file
939 @cindex config file, overview
941 A user configuration file ties together all the parts of a project
942 in one place.
943 One of the following will match your situation best:
945 @itemize
946 @item Ideally almost everything comes from configuration files
947 provided by someone else.
948 For example, OpenOCD distributes a @file{scripts} directory
949 (probably in @file{/usr/share/openocd/scripts} on Linux).
950 Board and tool vendors can provide these too, as can individual
951 user sites; the @option{-s} command line option lets you say
952 where to find these files. (@xref{Running}.)
953 The AT91SAM7X256 example above works this way.
955 Three main types of non-user configuration file each have their
956 own subdirectory in the @file{scripts} directory:
958 @enumerate
959 @item @b{interface} -- one for each different debug adapter;
960 @item @b{board} -- one for each different board
961 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
962 @end enumerate
964 Best case: include just two files, and they handle everything else.
965 The first is an interface config file.
966 The second is board-specific, and it sets up the JTAG TAPs and
967 their GDB targets (by deferring to some @file{target.cfg} file),
968 declares all flash memory, and leaves you nothing to do except
969 meet your deadline:
971 @example
972 source [find interface/olimex-jtag-tiny.cfg]
973 source [find board/csb337.cfg]
974 @end example
976 Boards with a single microcontroller often won't need more
977 than the target config file, as in the AT91SAM7X256 example.
978 That's because there is no external memory (flash, DDR RAM), and
979 the board differences are encapsulated by application code.
981 @item Maybe you don't know yet what your board looks like to JTAG.
982 Once you know the @file{interface.cfg} file to use, you may
983 need help from OpenOCD to discover what's on the board.
984 Once you find the JTAG TAPs, you can just search for appropriate
985 target and board
986 configuration files ... or write your own, from the bottom up.
987 @xref{autoprobing,,Autoprobing}.
989 @item You can often reuse some standard config files but
990 need to write a few new ones, probably a @file{board.cfg} file.
991 You will be using commands described later in this User's Guide,
992 and working with the guidelines in the next chapter.
994 For example, there may be configuration files for your JTAG adapter
995 and target chip, but you need a new board-specific config file
996 giving access to your particular flash chips.
997 Or you might need to write another target chip configuration file
998 for a new chip built around the Cortex M3 core.
1000 @quotation Note
1001 When you write new configuration files, please submit
1002 them for inclusion in the next OpenOCD release.
1003 For example, a @file{board/newboard.cfg} file will help the
1004 next users of that board, and a @file{target/newcpu.cfg}
1005 will help support users of any board using that chip.
1006 @end quotation
1008 @item
1009 You may may need to write some C code.
1010 It may be as simple as supporting a new FT2232 or parport
1011 based adapter; a bit more involved, like a NAND or NOR flash
1012 controller driver; or a big piece of work like supporting
1013 a new chip architecture.
1014 @end itemize
1016 Reuse the existing config files when you can.
1017 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1018 You may find a board configuration that's a good example to follow.
1020 When you write config files, separate the reusable parts
1021 (things every user of that interface, chip, or board needs)
1022 from ones specific to your environment and debugging approach.
1023 @itemize
1025 @item
1026 For example, a @code{gdb-attach} event handler that invokes
1027 the @command{reset init} command will interfere with debugging
1028 early boot code, which performs some of the same actions
1029 that the @code{reset-init} event handler does.
1031 @item
1032 Likewise, the @command{arm9 vector_catch} command (or
1033 @cindex vector_catch
1034 its siblings @command{xscale vector_catch}
1035 and @command{cortex_m vector_catch}) can be a timesaver
1036 during some debug sessions, but don't make everyone use that either.
1037 Keep those kinds of debugging aids in your user config file,
1038 along with messaging and tracing setup.
1039 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1041 @item
1042 You might need to override some defaults.
1043 For example, you might need to move, shrink, or back up the target's
1044 work area if your application needs much SRAM.
1046 @item
1047 TCP/IP port configuration is another example of something which
1048 is environment-specific, and should only appear in
1049 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1050 @end itemize
1052 @section Project-Specific Utilities
1054 A few project-specific utility
1055 routines may well speed up your work.
1056 Write them, and keep them in your project's user config file.
1058 For example, if you are making a boot loader work on a
1059 board, it's nice to be able to debug the ``after it's
1060 loaded to RAM'' parts separately from the finicky early
1061 code which sets up the DDR RAM controller and clocks.
1062 A script like this one, or a more GDB-aware sibling,
1063 may help:
1065 @example
1066 proc ramboot @{ @} @{
1067 # Reset, running the target's "reset-init" scripts
1068 # to initialize clocks and the DDR RAM controller.
1069 # Leave the CPU halted.
1070 reset init
1072 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1073 load_image u-boot.bin 0x20000000
1075 # Start running.
1076 resume 0x20000000
1077 @}
1078 @end example
1080 Then once that code is working you will need to make it
1081 boot from NOR flash; a different utility would help.
1082 Alternatively, some developers write to flash using GDB.
1083 (You might use a similar script if you're working with a flash
1084 based microcontroller application instead of a boot loader.)
1086 @example
1087 proc newboot @{ @} @{
1088 # Reset, leaving the CPU halted. The "reset-init" event
1089 # proc gives faster access to the CPU and to NOR flash;
1090 # "reset halt" would be slower.
1091 reset init
1093 # Write standard version of U-Boot into the first two
1094 # sectors of NOR flash ... the standard version should
1095 # do the same lowlevel init as "reset-init".
1096 flash protect 0 0 1 off
1097 flash erase_sector 0 0 1
1098 flash write_bank 0 u-boot.bin 0x0
1099 flash protect 0 0 1 on
1101 # Reboot from scratch using that new boot loader.
1102 reset run
1103 @}
1104 @end example
1106 You may need more complicated utility procedures when booting
1107 from NAND.
1108 That often involves an extra bootloader stage,
1109 running from on-chip SRAM to perform DDR RAM setup so it can load
1110 the main bootloader code (which won't fit into that SRAM).
1112 Other helper scripts might be used to write production system images,
1113 involving considerably more than just a three stage bootloader.
1115 @section Target Software Changes
1117 Sometimes you may want to make some small changes to the software
1118 you're developing, to help make JTAG debugging work better.
1119 For example, in C or assembly language code you might
1120 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1121 handling issues like:
1123 @itemize @bullet
1125 @item @b{Watchdog Timers}...
1126 Watchog timers are typically used to automatically reset systems if
1127 some application task doesn't periodically reset the timer. (The
1128 assumption is that the system has locked up if the task can't run.)
1129 When a JTAG debugger halts the system, that task won't be able to run
1130 and reset the timer ... potentially causing resets in the middle of
1131 your debug sessions.
1133 It's rarely a good idea to disable such watchdogs, since their usage
1134 needs to be debugged just like all other parts of your firmware.
1135 That might however be your only option.
1137 Look instead for chip-specific ways to stop the watchdog from counting
1138 while the system is in a debug halt state. It may be simplest to set
1139 that non-counting mode in your debugger startup scripts. You may however
1140 need a different approach when, for example, a motor could be physically
1141 damaged by firmware remaining inactive in a debug halt state. That might
1142 involve a type of firmware mode where that "non-counting" mode is disabled
1143 at the beginning then re-enabled at the end; a watchdog reset might fire
1144 and complicate the debug session, but hardware (or people) would be
1145 protected.@footnote{Note that many systems support a "monitor mode" debug
1146 that is a somewhat cleaner way to address such issues. You can think of
1147 it as only halting part of the system, maybe just one task,
1148 instead of the whole thing.
1149 At this writing, January 2010, OpenOCD based debugging does not support
1150 monitor mode debug, only "halt mode" debug.}
1152 @item @b{ARM Semihosting}...
1153 @cindex ARM semihosting
1154 When linked with a special runtime library provided with many
1155 toolchains@footnote{See chapter 8 "Semihosting" in
1156 @uref{,
1157 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1158 The CodeSourcery EABI toolchain also includes a semihosting library.},
1159 your target code can use I/O facilities on the debug host. That library
1160 provides a small set of system calls which are handled by OpenOCD.
1161 It can let the debugger provide your system console and a file system,
1162 helping with early debugging or providing a more capable environment
1163 for sometimes-complex tasks like installing system firmware onto
1164 NAND or SPI flash.
1166 @item @b{ARM Wait-For-Interrupt}...
1167 Many ARM chips synchronize the JTAG clock using the core clock.
1168 Low power states which stop that core clock thus prevent JTAG access.
1169 Idle loops in tasking environments often enter those low power states
1170 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1172 You may want to @emph{disable that instruction} in source code,
1173 or otherwise prevent using that state,
1174 to ensure you can get JTAG access at any time.@footnote{As a more
1175 polite alternative, some processors have special debug-oriented
1176 registers which can be used to change various features including
1177 how the low power states are clocked while debugging.
1178 The STM32 DBGMCU_CR register is an example; at the cost of extra
1179 power consumption, JTAG can be used during low power states.}
1180 For example, the OpenOCD @command{halt} command may not
1181 work for an idle processor otherwise.
1183 @item @b{Delay after reset}...
1184 Not all chips have good support for debugger access
1185 right after reset; many LPC2xxx chips have issues here.
1186 Similarly, applications that reconfigure pins used for
1187 JTAG access as they start will also block debugger access.
1189 To work with boards like this, @emph{enable a short delay loop}
1190 the first thing after reset, before "real" startup activities.
1191 For example, one second's delay is usually more than enough
1192 time for a JTAG debugger to attach, so that
1193 early code execution can be debugged
1194 or firmware can be replaced.
1196 @item @b{Debug Communications Channel (DCC)}...
1197 Some processors include mechanisms to send messages over JTAG.
1198 Many ARM cores support these, as do some cores from other vendors.
1199 (OpenOCD may be able to use this DCC internally, speeding up some
1200 operations like writing to memory.)
1202 Your application may want to deliver various debugging messages
1203 over JTAG, by @emph{linking with a small library of code}
1204 provided with OpenOCD and using the utilities there to send
1205 various kinds of message.
1206 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1208 @end itemize
1210 @section Target Hardware Setup
1212 Chip vendors often provide software development boards which
1213 are highly configurable, so that they can support all options
1214 that product boards may require. @emph{Make sure that any
1215 jumpers or switches match the system configuration you are
1216 working with.}
1218 Common issues include:
1220 @itemize @bullet
1222 @item @b{JTAG setup} ...
1223 Boards may support more than one JTAG configuration.
1224 Examples include jumpers controlling pullups versus pulldowns
1225 on the nTRST and/or nSRST signals, and choice of connectors
1226 (e.g. which of two headers on the base board,
1227 or one from a daughtercard).
1228 For some Texas Instruments boards, you may need to jumper the
1229 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1231 @item @b{Boot Modes} ...
1232 Complex chips often support multiple boot modes, controlled
1233 by external jumpers. Make sure this is set up correctly.
1234 For example many i.MX boards from NXP need to be jumpered
1235 to "ATX mode" to start booting using the on-chip ROM, when
1236 using second stage bootloader code stored in a NAND flash chip.
1238 Such explicit configuration is common, and not limited to
1239 booting from NAND. You might also need to set jumpers to
1240 start booting using code loaded from an MMC/SD card; external
1241 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1242 flash; some external host; or various other sources.
1245 @item @b{Memory Addressing} ...
1246 Boards which support multiple boot modes may also have jumpers
1247 to configure memory addressing. One board, for example, jumpers
1248 external chipselect 0 (used for booting) to address either
1249 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1250 or NAND flash. When it's jumpered to address NAND flash, that
1251 board must also be told to start booting from on-chip ROM.
1253 Your @file{board.cfg} file may also need to be told this jumper
1254 configuration, so that it can know whether to declare NOR flash
1255 using @command{flash bank} or instead declare NAND flash with
1256 @command{nand device}; and likewise which probe to perform in
1257 its @code{reset-init} handler.
1259 A closely related issue is bus width. Jumpers might need to
1260 distinguish between 8 bit or 16 bit bus access for the flash
1261 used to start booting.
1263 @item @b{Peripheral Access} ...
1264 Development boards generally provide access to every peripheral
1265 on the chip, sometimes in multiple modes (such as by providing
1266 multiple audio codec chips).
1267 This interacts with software
1268 configuration of pin multiplexing, where for example a
1269 given pin may be routed either to the MMC/SD controller
1270 or the GPIO controller. It also often interacts with
1271 configuration jumpers. One jumper may be used to route
1272 signals to an MMC/SD card slot or an expansion bus (which
1273 might in turn affect booting); others might control which
1274 audio or video codecs are used.
1276 @end itemize
1278 Plus you should of course have @code{reset-init} event handlers
1279 which set up the hardware to match that jumper configuration.
1280 That includes in particular any oscillator or PLL used to clock
1281 the CPU, and any memory controllers needed to access external
1282 memory and peripherals. Without such handlers, you won't be
1283 able to access those resources without working target firmware
1284 which can do that setup ... this can be awkward when you're
1285 trying to debug that target firmware. Even if there's a ROM
1286 bootloader which handles a few issues, it rarely provides full
1287 access to all board-specific capabilities.
1290 @node Config File Guidelines
1291 @chapter Config File Guidelines
1293 This chapter is aimed at any user who needs to write a config file,
1294 including developers and integrators of OpenOCD and any user who
1295 needs to get a new board working smoothly.
1296 It provides guidelines for creating those files.
1298 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1299 with files including the ones listed here.
1300 Use them as-is where you can; or as models for new files.
1301 @itemize @bullet
1302 @item @file{interface} ...
1303 These are for debug adapters.
1304 Files that configure JTAG adapters go here.
1305 @example
1306 $ ls interface -R
1307 interface/:
1308 altera-usb-blaster.cfg hilscher_nxhx50_re.cfg openocd-usb-hs.cfg
1309 arm-jtag-ew.cfg hitex_str9-comstick.cfg openrd.cfg
1310 at91rm9200.cfg icebear.cfg osbdm.cfg
1311 axm0432.cfg jlink.cfg parport.cfg
1312 busblaster.cfg jtagkey2.cfg parport_dlc5.cfg
1313 buspirate.cfg jtagkey2p.cfg redbee-econotag.cfg
1314 calao-usb-a9260-c01.cfg jtagkey.cfg redbee-usb.cfg
1315 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg rlink.cfg
1316 calao-usb-a9260.cfg jtag-lock-pick_tiny_2.cfg sheevaplug.cfg
1317 chameleon.cfg kt-link.cfg signalyzer.cfg
1318 cortino.cfg lisa-l.cfg signalyzer-h2.cfg
1319 digilent-hs1.cfg luminary.cfg signalyzer-h4.cfg
1320 dlp-usb1232h.cfg luminary-icdi.cfg signalyzer-lite.cfg
1321 dummy.cfg luminary-lm3s811.cfg stlink-v1.cfg
1322 estick.cfg minimodule.cfg stlink-v2.cfg
1323 flashlink.cfg neodb.cfg stm32-stick.cfg
1324 flossjtag.cfg ngxtech.cfg sysfsgpio-raspberrypi.cfg
1325 flossjtag-noeeprom.cfg olimex-arm-usb-ocd.cfg ti-icdi.cfg
1326 flyswatter2.cfg olimex-arm-usb-ocd-h.cfg turtelizer2.cfg
1327 flyswatter.cfg olimex-arm-usb-tiny-h.cfg ulink.cfg
1328 ftdi olimex-jtag-tiny.cfg usb-jtag.cfg
1329 hilscher_nxhx10_etm.cfg oocdlink.cfg usbprog.cfg
1330 hilscher_nxhx500_etm.cfg opendous.cfg vpaclink.cfg
1331 hilscher_nxhx500_re.cfg opendous_ftdi.cfg vsllink.cfg
1332 hilscher_nxhx50_etm.cfg openocd-usb.cfg xds100v2.cfg
1334 interface/ftdi:
1335 axm0432.cfg hitex_str9-comstick.cfg olimex-jtag-tiny.cfg
1336 calao-usb-a9260-c01.cfg icebear.cfg oocdlink.cfg
1337 calao-usb-a9260-c02.cfg jtagkey2.cfg opendous_ftdi.cfg
1338 cortino.cfg jtagkey2p.cfg openocd-usb.cfg
1339 dlp-usb1232h.cfg jtagkey.cfg openocd-usb-hs.cfg
1340 dp_busblaster.cfg jtag-lock-pick_tiny_2.cfg openrd.cfg
1341 flossjtag.cfg kt-link.cfg redbee-econotag.cfg
1342 flossjtag-noeeprom.cfg lisa-l.cfg redbee-usb.cfg
1343 flyswatter2.cfg luminary.cfg sheevaplug.cfg
1344 flyswatter.cfg luminary-icdi.cfg signalyzer.cfg
1345 gw16042.cfg luminary-lm3s811.cfg signalyzer-lite.cfg
1346 hilscher_nxhx10_etm.cfg minimodule.cfg stm32-stick.cfg
1347 hilscher_nxhx500_etm.cfg neodb.cfg turtelizer2-revB.cfg
1348 hilscher_nxhx500_re.cfg ngxtech.cfg turtelizer2-revC.cfg
1349 hilscher_nxhx50_etm.cfg olimex-arm-usb-ocd.cfg vpaclink.cfg
1350 hilscher_nxhx50_re.cfg olimex-arm-usb-ocd-h.cfg xds100v2.cfg
1351 hitex_lpc1768stick.cfg olimex-arm-usb-tiny-h.cfg
1352 $
1353 @end example
1354 @item @file{board} ...
1355 think Circuit Board, PWA, PCB, they go by many names. Board files
1356 contain initialization items that are specific to a board.
1357 They reuse target configuration files, since the same
1358 microprocessor chips are used on many boards,
1359 but support for external parts varies widely. For
1360 example, the SDRAM initialization sequence for the board, or the type
1361 of external flash and what address it uses. Any initialization
1362 sequence to enable that external flash or SDRAM should be found in the
1363 board file. Boards may also contain multiple targets: two CPUs; or
1364 a CPU and an FPGA.
1365 @example
1366 $ ls board
1367 actux3.cfg lpc1850_spifi_generic.cfg
1368 am3517evm.cfg lpc4350_spifi_generic.cfg
1369 arm_evaluator7t.cfg lubbock.cfg
1370 at91cap7a-stk-sdram.cfg mcb1700.cfg
1371 at91eb40a.cfg microchip_explorer16.cfg
1372 at91rm9200-dk.cfg mini2440.cfg
1373 at91rm9200-ek.cfg mini6410.cfg
1374 at91sam9261-ek.cfg netgear-dg834v3.cfg
1375 at91sam9263-ek.cfg olimex_LPC2378STK.cfg
1376 at91sam9g20-ek.cfg olimex_lpc_h2148.cfg
1377 atmel_at91sam7s-ek.cfg olimex_sam7_ex256.cfg
1378 atmel_at91sam9260-ek.cfg olimex_sam9_l9260.cfg
1379 atmel_at91sam9rl-ek.cfg olimex_stm32_h103.cfg
1380 atmel_sam3n_ek.cfg olimex_stm32_h107.cfg
1381 atmel_sam3s_ek.cfg olimex_stm32_p107.cfg
1382 atmel_sam3u_ek.cfg omap2420_h4.cfg
1383 atmel_sam3x_ek.cfg open-bldc.cfg
1384 atmel_sam4s_ek.cfg openrd.cfg
1385 balloon3-cpu.cfg osk5912.cfg
1386 colibri.cfg phone_se_j100i.cfg
1387 crossbow_tech_imote2.cfg phytec_lpc3250.cfg
1388 csb337.cfg pic-p32mx.cfg
1389 csb732.cfg propox_mmnet1001.cfg
1390 da850evm.cfg pxa255_sst.cfg
1391 digi_connectcore_wi-9c.cfg redbee.cfg
1392 diolan_lpc4350-db1.cfg rsc-w910.cfg
1393 dm355evm.cfg sheevaplug.cfg
1394 dm365evm.cfg smdk6410.cfg
1395 dm6446evm.cfg spear300evb.cfg
1396 efikamx.cfg spear300evb_mod.cfg
1397 eir.cfg spear310evb20.cfg
1398 ek-lm3s1968.cfg spear310evb20_mod.cfg
1399 ek-lm3s3748.cfg spear320cpu.cfg
1400 ek-lm3s6965.cfg spear320cpu_mod.cfg
1401 ek-lm3s811.cfg steval_pcc010.cfg
1402 ek-lm3s811-revb.cfg stm320518_eval_stlink.cfg
1403 ek-lm3s8962.cfg stm32100b_eval.cfg
1404 ek-lm3s9b9x.cfg stm3210b_eval.cfg
1405 ek-lm3s9d92.cfg stm3210c_eval.cfg
1406 ek-lm4f120xl.cfg stm3210e_eval.cfg
1407 ek-lm4f232.cfg stm3220g_eval.cfg
1408 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1409 ethernut3.cfg stm3241g_eval.cfg
1410 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1411 hammer.cfg stm32f0discovery.cfg
1412 hilscher_nxdb500sys.cfg stm32f3discovery.cfg
1413 hilscher_nxeb500hmi.cfg stm32f4discovery.cfg
1414 hilscher_nxhx10.cfg stm32ldiscovery.cfg
1415 hilscher_nxhx500.cfg stm32vldiscovery.cfg
1416 hilscher_nxhx50.cfg str910-eval.cfg
1417 hilscher_nxsb100.cfg telo.cfg
1418 hitex_lpc1768stick.cfg ti_am335xevm.cfg
1419 hitex_lpc2929.cfg ti_beagleboard.cfg
1420 hitex_stm32-performancestick.cfg ti_beagleboard_xm.cfg
1421 hitex_str9-comstick.cfg ti_beaglebone.cfg
1422 iar_lpc1768.cfg ti_blaze.cfg
1423 iar_str912_sk.cfg ti_pandaboard.cfg
1424 icnova_imx53_sodimm.cfg ti_pandaboard_es.cfg
1425 icnova_sam9g45_sodimm.cfg topas910.cfg
1426 imx27ads.cfg topasa900.cfg
1427 imx27lnst.cfg twr-k60f120m.cfg
1428 imx28evk.cfg twr-k60n512.cfg
1429 imx31pdk.cfg tx25_stk5.cfg
1430 imx35pdk.cfg tx27_stk5.cfg
1431 imx53loco.cfg unknown_at91sam9260.cfg
1432 keil_mcb1700.cfg uptech_2410.cfg
1433 keil_mcb2140.cfg verdex.cfg
1434 kwikstik.cfg voipac.cfg
1435 linksys_nslu2.cfg voltcraft_dso-3062c.cfg
1436 lisa-l.cfg x300t.cfg
1437 logicpd_imx27.cfg zy1000.cfg
1438 $
1439 @end example
1440 @item @file{target} ...
1441 think chip. The ``target'' directory represents the JTAG TAPs
1442 on a chip
1443 which OpenOCD should control, not a board. Two common types of targets
1444 are ARM chips and FPGA or CPLD chips.
1445 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1446 the target config file defines all of them.
1447 @example
1448 $ ls target
1449 aduc702x.cfg lpc1763.cfg
1450 am335x.cfg lpc1764.cfg
1451 amdm37x.cfg lpc1765.cfg
1452 ar71xx.cfg lpc1766.cfg
1453 at32ap7000.cfg lpc1767.cfg
1454 at91r40008.cfg lpc1768.cfg
1455 at91rm9200.cfg lpc1769.cfg
1456 at91sam3ax_4x.cfg lpc1788.cfg
1457 at91sam3ax_8x.cfg lpc17xx.cfg
1458 at91sam3ax_xx.cfg lpc1850.cfg
1459 at91sam3nXX.cfg lpc2103.cfg
1460 at91sam3sXX.cfg lpc2124.cfg
1461 at91sam3u1c.cfg lpc2129.cfg
1462 at91sam3u1e.cfg lpc2148.cfg
1463 at91sam3u2c.cfg lpc2294.cfg
1464 at91sam3u2e.cfg lpc2378.cfg
1465 at91sam3u4c.cfg lpc2460.cfg
1466 at91sam3u4e.cfg lpc2478.cfg
1467 at91sam3uxx.cfg lpc2900.cfg
1468 at91sam3XXX.cfg lpc2xxx.cfg
1469 at91sam4sd32x.cfg lpc3131.cfg
1470 at91sam4sXX.cfg lpc3250.cfg
1471 at91sam4XXX.cfg lpc4350.cfg
1472 at91sam7se512.cfg lpc4350.cfg.orig
1473 at91sam7sx.cfg mc13224v.cfg
1474 at91sam7x256.cfg nuc910.cfg
1475 at91sam7x512.cfg omap2420.cfg
1476 at91sam9260.cfg omap3530.cfg
1477 at91sam9260_ext_RAM_ext_flash.cfg omap4430.cfg
1478 at91sam9261.cfg omap4460.cfg
1479 at91sam9263.cfg omap5912.cfg
1480 at91sam9.cfg omapl138.cfg
1481 at91sam9g10.cfg pic32mx.cfg
1482 at91sam9g20.cfg pxa255.cfg
1483 at91sam9g45.cfg pxa270.cfg
1484 at91sam9rl.cfg pxa3xx.cfg
1485 atmega128.cfg readme.txt
1486 avr32.cfg samsung_s3c2410.cfg
1487 c100.cfg samsung_s3c2440.cfg
1488 c100config.tcl samsung_s3c2450.cfg
1489 c100helper.tcl samsung_s3c4510.cfg
1490 c100regs.tcl samsung_s3c6410.cfg
1491 cs351x.cfg sharp_lh79532.cfg
1492 davinci.cfg smp8634.cfg
1493 dragonite.cfg spear3xx.cfg
1494 dsp56321.cfg stellaris.cfg
1495 dsp568013.cfg stellaris_icdi.cfg
1496 dsp568037.cfg stm32f0x_stlink.cfg
1497 efm32_stlink.cfg stm32f1x.cfg
1498 epc9301.cfg stm32f1x_stlink.cfg
1499 faux.cfg stm32f2x.cfg
1500 feroceon.cfg stm32f2x_stlink.cfg
1501 fm3.cfg stm32f3x.cfg
1502 hilscher_netx10.cfg stm32f3x_stlink.cfg
1503 hilscher_netx500.cfg stm32f4x.cfg
1504 hilscher_netx50.cfg stm32f4x_stlink.cfg
1505 icepick.cfg stm32l.cfg
1506 imx21.cfg stm32lx_dual_bank.cfg
1507 imx25.cfg stm32lx_stlink.cfg
1508 imx27.cfg stm32_stlink.cfg
1509 imx28.cfg stm32w108_stlink.cfg
1510 imx31.cfg stm32xl.cfg
1511 imx35.cfg str710.cfg
1512 imx51.cfg str730.cfg
1513 imx53.cfg str750.cfg
1514 imx6.cfg str912.cfg
1515 imx.cfg swj-dp.tcl
1516 is5114.cfg test_reset_syntax_error.cfg
1517 ixp42x.cfg test_syntax_error.cfg
1518 k40.cfg ti-ar7.cfg
1519 k60.cfg ti_calypso.cfg
1520 lpc1751.cfg ti_dm355.cfg
1521 lpc1752.cfg ti_dm365.cfg
1522 lpc1754.cfg ti_dm6446.cfg
1523 lpc1756.cfg tmpa900.cfg
1524 lpc1758.cfg tmpa910.cfg
1525 lpc1759.cfg u8500.cfg
1526 @end example
1527 @item @emph{more} ... browse for other library files which may be useful.
1528 For example, there are various generic and CPU-specific utilities.
1529 @end itemize
1531 The @file{openocd.cfg} user config
1532 file may override features in any of the above files by
1533 setting variables before sourcing the target file, or by adding
1534 commands specific to their situation.
1536 @section Interface Config Files
1538 The user config file
1539 should be able to source one of these files with a command like this:
1541 @example
1542 source [find interface/FOOBAR.cfg]
1543 @end example
1545 A preconfigured interface file should exist for every debug adapter
1546 in use today with OpenOCD.
1547 That said, perhaps some of these config files
1548 have only been used by the developer who created it.
1550 A separate chapter gives information about how to set these up.
1551 @xref{Debug Adapter Configuration}.
1552 Read the OpenOCD source code (and Developer's Guide)
1553 if you have a new kind of hardware interface
1554 and need to provide a driver for it.
1556 @section Board Config Files
1557 @cindex config file, board
1558 @cindex board config file
1560 The user config file
1561 should be able to source one of these files with a command like this:
1563 @example
1564 source [find board/FOOBAR.cfg]
1565 @end example
1567 The point of a board config file is to package everything
1568 about a given board that user config files need to know.
1569 In summary the board files should contain (if present)
1571 @enumerate
1572 @item One or more @command{source [find target/...cfg]} statements
1573 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1574 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1575 @item Target @code{reset} handlers for SDRAM and I/O configuration
1576 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1577 @item All things that are not ``inside a chip''
1578 @end enumerate
1580 Generic things inside target chips belong in target config files,
1581 not board config files. So for example a @code{reset-init} event
1582 handler should know board-specific oscillator and PLL parameters,
1583 which it passes to target-specific utility code.
1585 The most complex task of a board config file is creating such a
1586 @code{reset-init} event handler.
1587 Define those handlers last, after you verify the rest of the board
1588 configuration works.
1590 @subsection Communication Between Config files
1592 In addition to target-specific utility code, another way that
1593 board and target config files communicate is by following a
1594 convention on how to use certain variables.
1596 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1597 Thus the rule we follow in OpenOCD is this: Variables that begin with
1598 a leading underscore are temporary in nature, and can be modified and
1599 used at will within a target configuration file.
1601 Complex board config files can do the things like this,
1602 for a board with three chips:
1604 @example
1605 # Chip #1: PXA270 for network side, big endian
1606 set CHIPNAME network
1607 set ENDIAN big
1608 source [find target/pxa270.cfg]
1609 # on return: _TARGETNAME = network.cpu
1610 # other commands can refer to the "network.cpu" target.
1611 $_TARGETNAME configure .... events for this CPU..
1613 # Chip #2: PXA270 for video side, little endian
1614 set CHIPNAME video
1615 set ENDIAN little
1616 source [find target/pxa270.cfg]
1617 # on return: _TARGETNAME = video.cpu
1618 # other commands can refer to the "video.cpu" target.
1619 $_TARGETNAME configure .... events for this CPU..
1621 # Chip #3: Xilinx FPGA for glue logic
1622 set CHIPNAME xilinx
1623 unset ENDIAN
1624 source [find target/spartan3.cfg]
1625 @end example
1627 That example is oversimplified because it doesn't show any flash memory,
1628 or the @code{reset-init} event handlers to initialize external DRAM
1629 or (assuming it needs it) load a configuration into the FPGA.
1630 Such features are usually needed for low-level work with many boards,
1631 where ``low level'' implies that the board initialization software may
1632 not be working. (That's a common reason to need JTAG tools. Another
1633 is to enable working with microcontroller-based systems, which often
1634 have no debugging support except a JTAG connector.)
1636 Target config files may also export utility functions to board and user
1637 config files. Such functions should use name prefixes, to help avoid
1638 naming collisions.
1640 Board files could also accept input variables from user config files.
1641 For example, there might be a @code{J4_JUMPER} setting used to identify
1642 what kind of flash memory a development board is using, or how to set
1643 up other clocks and peripherals.
1645 @subsection Variable Naming Convention
1646 @cindex variable names
1648 Most boards have only one instance of a chip.
1649 However, it should be easy to create a board with more than
1650 one such chip (as shown above).
1651 Accordingly, we encourage these conventions for naming
1652 variables associated with different @file{target.cfg} files,
1653 to promote consistency and
1654 so that board files can override target defaults.
1656 Inputs to target config files include:
1658 @itemize @bullet
1659 @item @code{CHIPNAME} ...
1660 This gives a name to the overall chip, and is used as part of
1661 tap identifier dotted names.
1662 While the default is normally provided by the chip manufacturer,
1663 board files may need to distinguish between instances of a chip.
1664 @item @code{ENDIAN} ...
1665 By default @option{little} - although chips may hard-wire @option{big}.
1666 Chips that can't change endianness don't need to use this variable.
1667 @item @code{CPUTAPID} ...
1668 When OpenOCD examines the JTAG chain, it can be told verify the
1669 chips against the JTAG IDCODE register.
1670 The target file will hold one or more defaults, but sometimes the
1671 chip in a board will use a different ID (perhaps a newer revision).
1672 @end itemize
1674 Outputs from target config files include:
1676 @itemize @bullet
1677 @item @code{_TARGETNAME} ...
1678 By convention, this variable is created by the target configuration
1679 script. The board configuration file may make use of this variable to
1680 configure things like a ``reset init'' script, or other things
1681 specific to that board and that target.
1682 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1683 @code{_TARGETNAME1}, ... etc.
1684 @end itemize
1686 @subsection The reset-init Event Handler
1687 @cindex event, reset-init
1688 @cindex reset-init handler
1690 Board config files run in the OpenOCD configuration stage;
1691 they can't use TAPs or targets, since they haven't been
1692 fully set up yet.
1693 This means you can't write memory or access chip registers;
1694 you can't even verify that a flash chip is present.
1695 That's done later in event handlers, of which the target @code{reset-init}
1696 handler is one of the most important.
1698 Except on microcontrollers, the basic job of @code{reset-init} event
1699 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1700 Microcontrollers rarely use boot loaders; they run right out of their
1701 on-chip flash and SRAM memory. But they may want to use one of these
1702 handlers too, if just for developer convenience.
1704 @quotation Note
1705 Because this is so very board-specific, and chip-specific, no examples
1706 are included here.
1707 Instead, look at the board config files distributed with OpenOCD.
1708 If you have a boot loader, its source code will help; so will
1709 configuration files for other JTAG tools
1710 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1711 @end quotation
1713 Some of this code could probably be shared between different boards.
1714 For example, setting up a DRAM controller often doesn't differ by
1715 much except the bus width (16 bits or 32?) and memory timings, so a
1716 reusable TCL procedure loaded by the @file{target.cfg} file might take
1717 those as parameters.
1718 Similarly with oscillator, PLL, and clock setup;
1719 and disabling the watchdog.
1720 Structure the code cleanly, and provide comments to help
1721 the next developer doing such work.
1722 (@emph{You might be that next person} trying to reuse init code!)
1724 The last thing normally done in a @code{reset-init} handler is probing
1725 whatever flash memory was configured. For most chips that needs to be
1726 done while the associated target is halted, either because JTAG memory
1727 access uses the CPU or to prevent conflicting CPU access.
1729 @subsection JTAG Clock Rate
1731 Before your @code{reset-init} handler has set up
1732 the PLLs and clocking, you may need to run with
1733 a low JTAG clock rate.
1734 @xref{jtagspeed,,JTAG Speed}.
1735 Then you'd increase that rate after your handler has
1736 made it possible to use the faster JTAG clock.
1737 When the initial low speed is board-specific, for example
1738 because it depends on a board-specific oscillator speed, then
1739 you should probably set it up in the board config file;
1740 if it's target-specific, it belongs in the target config file.
1742 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1743 @uref{} gives details.}
1744 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1745 Consult chip documentation to determine the peak JTAG clock rate,
1746 which might be less than that.
1748 @quotation Warning
1749 On most ARMs, JTAG clock detection is coupled to the core clock, so
1750 software using a @option{wait for interrupt} operation blocks JTAG access.
1751 Adaptive clocking provides a partial workaround, but a more complete
1752 solution just avoids using that instruction with JTAG debuggers.
1753 @end quotation
1755 If both the chip and the board support adaptive clocking,
1756 use the @command{jtag_rclk}
1757 command, in case your board is used with JTAG adapter which
1758 also supports it. Otherwise use @command{adapter_khz}.
1759 Set the slow rate at the beginning of the reset sequence,
1760 and the faster rate as soon as the clocks are at full speed.
1762 @anchor{theinitboardprocedure}
1763 @subsection The init_board procedure
1764 @cindex init_board procedure
1766 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1767 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1768 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1769 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1770 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1771 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1772 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1773 Additionally ``linear'' board config file will most likely fail when target config file uses
1774 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1775 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1776 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1777 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1779 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1780 the original), allowing greater code reuse.
1782 @example
1783 ### board_file.cfg ###
1785 # source target file that does most of the config in init_targets
1786 source [find target/target.cfg]
1788 proc enable_fast_clock @{@} @{
1789 # enables fast on-board clock source
1790 # configures the chip to use it
1791 @}
1793 # initialize only board specifics - reset, clock, adapter frequency
1794 proc init_board @{@} @{
1795 reset_config trst_and_srst trst_pulls_srst
1797 $_TARGETNAME configure -event reset-init @{
1798 adapter_khz 1
1799 enable_fast_clock
1800 adapter_khz 10000
1801 @}
1802 @}
1803 @end example
1805 @section Target Config Files
1806 @cindex config file, target
1807 @cindex target config file
1809 Board config files communicate with target config files using
1810 naming conventions as described above, and may source one or
1811 more target config files like this:
1813 @example
1814 source [find target/FOOBAR.cfg]
1815 @end example
1817 The point of a target config file is to package everything
1818 about a given chip that board config files need to know.
1819 In summary the target files should contain
1821 @enumerate
1822 @item Set defaults
1823 @item Add TAPs to the scan chain
1824 @item Add CPU targets (includes GDB support)
1825 @item CPU/Chip/CPU-Core specific features
1826 @item On-Chip flash
1827 @end enumerate
1829 As a rule of thumb, a target file sets up only one chip.
1830 For a microcontroller, that will often include a single TAP,
1831 which is a CPU needing a GDB target, and its on-chip flash.
1833 More complex chips may include multiple TAPs, and the target
1834 config file may need to define them all before OpenOCD
1835 can talk to the chip.
1836 For example, some phone chips have JTAG scan chains that include
1837 an ARM core for operating system use, a DSP,
1838 another ARM core embedded in an image processing engine,
1839 and other processing engines.
1841 @subsection Default Value Boiler Plate Code
1843 All target configuration files should start with code like this,
1844 letting board config files express environment-specific
1845 differences in how things should be set up.
1847 @example
1848 # Boards may override chip names, perhaps based on role,
1849 # but the default should match what the vendor uses
1850 if @{ [info exists CHIPNAME] @} @{
1852 @} else @{
1853 set _CHIPNAME sam7x256
1854 @}
1856 # ONLY use ENDIAN with targets that can change it.
1857 if @{ [info exists ENDIAN] @} @{
1858 set _ENDIAN $ENDIAN
1859 @} else @{
1860 set _ENDIAN little
1861 @}
1863 # TAP identifiers may change as chips mature, for example with
1864 # new revision fields (the "3" here). Pick a good default; you
1865 # can pass several such identifiers to the "jtag newtap" command.
1866 if @{ [info exists CPUTAPID ] @} @{
1868 @} else @{
1869 set _CPUTAPID 0x3f0f0f0f
1870 @}
1871 @end example
1872 @c but 0x3f0f0f0f is for an str73x part ...
1874 @emph{Remember:} Board config files may include multiple target
1875 config files, or the same target file multiple times
1876 (changing at least @code{CHIPNAME}).
1878 Likewise, the target configuration file should define
1879 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1880 use it later on when defining debug targets:
1882 @example
1884 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1885 @end example
1887 @subsection Adding TAPs to the Scan Chain
1888 After the ``defaults'' are set up,
1889 add the TAPs on each chip to the JTAG scan chain.
1890 @xref{TAP Declaration}, and the naming convention
1891 for taps.
1893 In the simplest case the chip has only one TAP,
1894 probably for a CPU or FPGA.
1895 The config file for the Atmel AT91SAM7X256
1896 looks (in part) like this:
1898 @example
1899 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1900 @end example
1902 A board with two such at91sam7 chips would be able
1903 to source such a config file twice, with different
1904 values for @code{CHIPNAME}, so
1905 it adds a different TAP each time.
1907 If there are nonzero @option{-expected-id} values,
1908 OpenOCD attempts to verify the actual tap id against those values.
1909 It will issue error messages if there is mismatch, which
1910 can help to pinpoint problems in OpenOCD configurations.
1912 @example
1913 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1914 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1915 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1916 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1917 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1918 @end example
1920 There are more complex examples too, with chips that have
1921 multiple TAPs. Ones worth looking at include:
1923 @itemize
1924 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1925 plus a JRC to enable them
1926 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1927 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1928 is not currently used)
1929 @end itemize
1931 @subsection Add CPU targets
1933 After adding a TAP for a CPU, you should set it up so that
1934 GDB and other commands can use it.
1935 @xref{CPU Configuration}.
1936 For the at91sam7 example above, the command can look like this;
1937 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1938 to little endian, and this chip doesn't support changing that.
1940 @example
1942 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1943 @end example
1945 Work areas are small RAM areas associated with CPU targets.
1946 They are used by OpenOCD to speed up downloads,
1947 and to download small snippets of code to program flash chips.
1948 If the chip includes a form of ``on-chip-ram'' - and many do - define
1949 a work area if you can.
1950 Again using the at91sam7 as an example, this can look like:
1952 @example
1953 $_TARGETNAME configure -work-area-phys 0x00200000 \
1954 -work-area-size 0x4000 -work-area-backup 0
1955 @end example
1957 @anchor{definecputargetsworkinginsmp}
1958 @subsection Define CPU targets working in SMP
1959 @cindex SMP
1960 After setting targets, you can define a list of targets working in SMP.
1962 @example
1963 set _TARGETNAME_1 $_CHIPNAME.cpu1
1964 set _TARGETNAME_2 $_CHIPNAME.cpu2
1965 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1966 -coreid 0 -dbgbase $_DAP_DBG1
1967 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1968 -coreid 1 -dbgbase $_DAP_DBG2
1969 #define 2 targets working in smp.
1970 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1971 @end example
1972 In the above example on cortex_a, 2 cpus are working in SMP.
1973 In SMP only one GDB instance is created and :
1974 @itemize @bullet
1975 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1976 @item halt command triggers the halt of all targets in the list.
1977 @item resume command triggers the write context and the restart of all targets in the list.
1978 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1979 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1980 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1981 @end itemize
1983 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1984 command have been implemented.
1985 @itemize @bullet
1986 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1987 @item cortex_a smp_off : disable SMP mode, the current target is the one
1988 displayed in the GDB session, only this target is now controlled by GDB
1989 session. This behaviour is useful during system boot up.
1990 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1991 following example.
1992 @end itemize
1994 @example
1995 >cortex_a smp_gdb
1996 gdb coreid 0 -> -1
1997 #0 : coreid 0 is displayed to GDB ,
1998 #-> -1 : next resume triggers a real resume
1999 > cortex_a smp_gdb 1
2000 gdb coreid 0 -> 1
2001 #0 :coreid 0 is displayed to GDB ,
2002 #->1 : next resume displays coreid 1 to GDB
2003 > resume
2004 > cortex_a smp_gdb
2005 gdb coreid 1 -> 1
2006 #1 :coreid 1 is displayed to GDB ,
2007 #->1 : next resume displays coreid 1 to GDB
2008 > cortex_a smp_gdb -1
2009 gdb coreid 1 -> -1
2010 #1 :coreid 1 is displayed to GDB,
2011 #->-1 : next resume triggers a real resume
2012 @end example
2015 @subsection Chip Reset Setup
2017 As a rule, you should put the @command{reset_config} command
2018 into the board file. Most things you think you know about a
2019 chip can be tweaked by the board.
2021 Some chips have specific ways the TRST and SRST signals are
2022 managed. In the unusual case that these are @emph{chip specific}
2023 and can never be changed by board wiring, they could go here.
2024 For example, some chips can't support JTAG debugging without
2025 both signals.
2027 Provide a @code{reset-assert} event handler if you can.
2028 Such a handler uses JTAG operations to reset the target,
2029 letting this target config be used in systems which don't
2030 provide the optional SRST signal, or on systems where you
2031 don't want to reset all targets at once.
2032 Such a handler might write to chip registers to force a reset,
2033 use a JRC to do that (preferable -- the target may be wedged!),
2034 or force a watchdog timer to trigger.
2035 (For Cortex-M targets, this is not necessary. The target
2036 driver knows how to use trigger an NVIC reset when SRST is
2037 not available.)
2039 Some chips need special attention during reset handling if
2040 they're going to be used with JTAG.
2041 An example might be needing to send some commands right
2042 after the target's TAP has been reset, providing a
2043 @code{reset-deassert-post} event handler that writes a chip
2044 register to report that JTAG debugging is being done.
2045 Another would be reconfiguring the watchdog so that it stops
2046 counting while the core is halted in the debugger.
2048 JTAG clocking constraints often change during reset, and in
2049 some cases target config files (rather than board config files)
2050 are the right places to handle some of those issues.
2051 For example, immediately after reset most chips run using a
2052 slower clock than they will use later.
2053 That means that after reset (and potentially, as OpenOCD
2054 first starts up) they must use a slower JTAG clock rate
2055 than they will use later.
2056 @xref{jtagspeed,,JTAG Speed}.
2058 @quotation Important
2059 When you are debugging code that runs right after chip
2060 reset, getting these issues right is critical.
2061 In particular, if you see intermittent failures when
2062 OpenOCD verifies the scan chain after reset,
2063 look at how you are setting up JTAG clocking.
2064 @end quotation
2066 @anchor{theinittargetsprocedure}
2067 @subsection The init_targets procedure
2068 @cindex init_targets procedure
2070 Target config files can either be ``linear'' (script executed line-by-line when parsed in
2071 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
2072 procedure called @code{init_targets}, which will be executed when entering run stage
2073 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
2074 Such procedure can be overriden by ``next level'' script (which sources the original).
2075 This concept faciliates code reuse when basic target config files provide generic configuration
2076 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
2077 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
2078 because sourcing them executes every initialization commands they provide.
2080 @example
2081 ### generic_file.cfg ###
2083 proc setup_my_chip @{chip_name flash_size ram_size@} @{
2084 # basic initialization procedure ...
2085 @}
2087 proc init_targets @{@} @{
2088 # initializes generic chip with 4kB of flash and 1kB of RAM
2089 setup_my_chip MY_GENERIC_CHIP 4096 1024
2090 @}
2092 ### specific_file.cfg ###
2094 source [find target/generic_file.cfg]
2096 proc init_targets @{@} @{
2097 # initializes specific chip with 128kB of flash and 64kB of RAM
2098 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
2099 @}
2100 @end example
2102 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
2103 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
2105 For an example of this scheme see LPC2000 target config files.
2107 The @code{init_boards} procedure is a similar concept concerning board config files
2108 (@xref{theinitboardprocedure,,The init_board procedure}.)
2110 @subsection ARM Core Specific Hacks
2112 If the chip has a DCC, enable it. If the chip is an ARM9 with some
2113 special high speed download features - enable it.
2115 If present, the MMU, the MPU and the CACHE should be disabled.
2117 Some ARM cores are equipped with trace support, which permits
2118 examination of the instruction and data bus activity. Trace
2119 activity is controlled through an ``Embedded Trace Module'' (ETM)
2120 on one of the core's scan chains. The ETM emits voluminous data
2121 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
2122 If you are using an external trace port,
2123 configure it in your board config file.
2124 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2125 configure it in your target config file.
2127 @example
2128 etm config $_TARGETNAME 16 normal full etb
2129 etb config $_TARGETNAME $_CHIPNAME.etb
2130 @end example
2132 @subsection Internal Flash Configuration
2134 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2136 @b{Never ever} in the ``target configuration file'' define any type of
2137 flash that is external to the chip. (For example a BOOT flash on
2138 Chip Select 0.) Such flash information goes in a board file - not
2139 the TARGET (chip) file.
2141 Examples:
2142 @itemize @bullet
2143 @item at91sam7x256 - has 256K flash YES enable it.
2144 @item str912 - has flash internal YES enable it.
2145 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2146 @item pxa270 - again - CS0 flash - it goes in the board file.
2147 @end itemize
2149 @anchor{translatingconfigurationfiles}
2150 @section Translating Configuration Files
2151 @cindex translation
2152 If you have a configuration file for another hardware debugger
2153 or toolset (Abatron, BDI2000, BDI3000, CCS,
2154 Lauterbach, Segger, Macraigor, etc.), translating
2155 it into OpenOCD syntax is often quite straightforward. The most tricky
2156 part of creating a configuration script is oftentimes the reset init
2157 sequence where e.g. PLLs, DRAM and the like is set up.
2159 One trick that you can use when translating is to write small
2160 Tcl procedures to translate the syntax into OpenOCD syntax. This
2161 can avoid manual translation errors and make it easier to
2162 convert other scripts later on.
2164 Example of transforming quirky arguments to a simple search and
2165 replace job:
2167 @example
2168 # Lauterbach syntax(?)
2169 #
2170 # Data.Set c15:0x042f %long 0x40000015
2171 #
2172 # OpenOCD syntax when using procedure below.
2173 #
2174 # setc15 0x01 0x00050078
2176 proc setc15 @{regs value@} @{
2177 global TARGETNAME
2179 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2181 arm mcr 15 [expr ($regs>>12)&0x7] \
2182 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2183 [expr ($regs>>8)&0x7] $value
2184 @}
2185 @end example
2189 @node Daemon Configuration
2190 @chapter Daemon Configuration
2191 @cindex initialization
2192 The commands here are commonly found in the openocd.cfg file and are
2193 used to specify what TCP/IP ports are used, and how GDB should be
2194 supported.
2196 @anchor{configurationstage}
2197 @section Configuration Stage
2198 @cindex configuration stage
2199 @cindex config command
2201 When the OpenOCD server process starts up, it enters a
2202 @emph{configuration stage} which is the only time that
2203 certain commands, @emph{configuration commands}, may be issued.
2204 Normally, configuration commands are only available
2205 inside startup scripts.
2207 In this manual, the definition of a configuration command is
2208 presented as a @emph{Config Command}, not as a @emph{Command}
2209 which may be issued interactively.
2210 The runtime @command{help} command also highlights configuration
2211 commands, and those which may be issued at any time.
2213 Those configuration commands include declaration of TAPs,
2214 flash banks,
2215 the interface used for JTAG communication,
2216 and other basic setup.
2217 The server must leave the configuration stage before it
2218 may access or activate TAPs.
2219 After it leaves this stage, configuration commands may no
2220 longer be issued.
2222 @anchor{enteringtherunstage}
2223 @section Entering the Run Stage
2225 The first thing OpenOCD does after leaving the configuration
2226 stage is to verify that it can talk to the scan chain
2227 (list of TAPs) which has been configured.
2228 It will warn if it doesn't find TAPs it expects to find,
2229 or finds TAPs that aren't supposed to be there.
2230 You should see no errors at this point.
2231 If you see errors, resolve them by correcting the
2232 commands you used to configure the server.
2233 Common errors include using an initial JTAG speed that's too
2234 fast, and not providing the right IDCODE values for the TAPs
2235 on the scan chain.
2237 Once OpenOCD has entered the run stage, a number of commands
2238 become available.
2239 A number of these relate to the debug targets you may have declared.
2240 For example, the @command{mww} command will not be available until
2241 a target has been successfuly instantiated.
2242 If you want to use those commands, you may need to force
2243 entry to the run stage.
2245 @deffn {Config Command} init
2246 This command terminates the configuration stage and
2247 enters the run stage. This helps when you need to have
2248 the startup scripts manage tasks such as resetting the target,
2249 programming flash, etc. To reset the CPU upon startup, add "init" and
2250 "reset" at the end of the config script or at the end of the OpenOCD
2251 command line using the @option{-c} command line switch.
2253 If this command does not appear in any startup/configuration file
2254 OpenOCD executes the command for you after processing all
2255 configuration files and/or command line options.
2257 @b{NOTE:} This command normally occurs at or near the end of your
2258 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2259 targets ready. For example: If your openocd.cfg file needs to
2260 read/write memory on your target, @command{init} must occur before
2261 the memory read/write commands. This includes @command{nand probe}.
2262 @end deffn
2264 @deffn {Overridable Procedure} jtag_init
2265 This is invoked at server startup to verify that it can talk
2266 to the scan chain (list of TAPs) which has been configured.
2268 The default implementation first tries @command{jtag arp_init},
2269 which uses only a lightweight JTAG reset before examining the
2270 scan chain.
2271 If that fails, it tries again, using a harder reset
2272 from the overridable procedure @command{init_reset}.
2274 Implementations must have verified the JTAG scan chain before
2275 they return.
2276 This is done by calling @command{jtag arp_init}
2277 (or @command{jtag arp_init-reset}).
2278 @end deffn
2280 @anchor{tcpipports}
2281 @section TCP/IP Ports
2282 @cindex TCP port
2283 @cindex server
2284 @cindex port
2285 @cindex security
2286 The OpenOCD server accepts remote commands in several syntaxes.
2287 Each syntax uses a different TCP/IP port, which you may specify
2288 only during configuration (before those ports are opened).
2290 For reasons including security, you may wish to prevent remote
2291 access using one or more of these ports.
2292 In such cases, just specify the relevant port number as zero.
2293 If you disable all access through TCP/IP, you will need to
2294 use the command line @option{-pipe} option.
2296 @deffn {Command} gdb_port [number]
2297 @cindex GDB server
2298 Normally gdb listens to a TCP/IP port, but GDB can also
2299 communicate via pipes(stdin/out or named pipes). The name
2300 "gdb_port" stuck because it covers probably more than 90% of
2301 the normal use cases.
2303 No arguments reports GDB port. "pipe" means listen to stdin
2304 output to stdout, an integer is base port number, "disable"
2305 disables the gdb server.
2307 When using "pipe", also use log_output to redirect the log
2308 output to a file so as not to flood the stdin/out pipes.
2310 The -p/--pipe option is deprecated and a warning is printed
2311 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2313 Any other string is interpreted as named pipe to listen to.
2314 Output pipe is the same name as input pipe, but with 'o' appended,
2315 e.g. /var/gdb, /var/gdbo.
2317 The GDB port for the first target will be the base port, the
2318 second target will listen on gdb_port + 1, and so on.
2319 When not specified during the configuration stage,
2320 the port @var{number} defaults to 3333.
2321 @end deffn
2323 @deffn {Command} tcl_port [number]
2324 Specify or query the port used for a simplified RPC
2325 connection that can be used by clients to issue TCL commands and get the
2326 output from the Tcl engine.
2327 Intended as a machine interface.
2328 When not specified during the configuration stage,
2329 the port @var{number} defaults to 6666.
2331 @end deffn
2333 @deffn {Command} telnet_port [number]
2334 Specify or query the
2335 port on which to listen for incoming telnet connections.
2336 This port is intended for interaction with one human through TCL commands.
2337 When not specified during the configuration stage,
2338 the port @var{number} defaults to 4444.
2339 When specified as zero, this port is not activated.
2340 @end deffn
2342 @anchor{gdbconfiguration}
2343 @section GDB Configuration
2344 @cindex GDB
2345 @cindex GDB configuration
2346 You can reconfigure some GDB behaviors if needed.
2347 The ones listed here are static and global.
2348 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2349 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2351 @anchor{gdbbreakpointoverride}
2352 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2353 Force breakpoint type for gdb @command{break} commands.
2354 This option supports GDB GUIs which don't
2355 distinguish hard versus soft breakpoints, if the default OpenOCD and
2356 GDB behaviour is not sufficient. GDB normally uses hardware
2357 breakpoints if the memory map has been set up for flash regions.
2358 @end deffn
2360 @anchor{gdbflashprogram}
2361 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2362 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2363 vFlash packet is received.
2364 The default behaviour is @option{enable}.
2365 @end deffn
2367 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2368 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2369 requested. GDB will then know when to set hardware breakpoints, and program flash
2370 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2371 for flash programming to work.
2372 Default behaviour is @option{enable}.
2373 @xref{gdbflashprogram,,gdb_flash_program}.
2374 @end deffn
2376 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2377 Specifies whether data aborts cause an error to be reported
2378 by GDB memory read packets.
2379 The default behaviour is @option{disable};
2380 use @option{enable} see these errors reported.
2381 @end deffn
2383 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2384 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2385 The default behaviour is @option{disable}.
2386 @end deffn
2388 @deffn {Command} gdb_save_tdesc
2389 Saves the target descripton file to the local file system.
2391 The file name is @i{target_name}.xml.
2392 @end deffn
2394 @anchor{eventpolling}
2395 @section Event Polling
2397 Hardware debuggers are parts of asynchronous systems,
2398 where significant events can happen at any time.
2399 The OpenOCD server needs to detect some of these events,
2400 so it can report them to through TCL command line
2401 or to GDB.
2403 Examples of such events include:
2405 @itemize
2406 @item One of the targets can stop running ... maybe it triggers
2407 a code breakpoint or data watchpoint, or halts itself.
2408 @item Messages may be sent over ``debug message'' channels ... many
2409 targets support such messages sent over JTAG,
2410 for receipt by the person debugging or tools.
2411 @item Loss of power ... some adapters can detect these events.
2412 @item Resets not issued through JTAG ... such reset sources
2413 can include button presses or other system hardware, sometimes
2414 including the target itself (perhaps through a watchdog).
2415 @item Debug instrumentation sometimes supports event triggering
2416 such as ``trace buffer full'' (so it can quickly be emptied)
2417 or other signals (to correlate with code behavior).
2418 @end itemize
2420 None of those events are signaled through standard JTAG signals.
2421 However, most conventions for JTAG connectors include voltage
2422 level and system reset (SRST) signal detection.
2423 Some connectors also include instrumentation signals, which
2424 can imply events when those signals are inputs.
2426 In general, OpenOCD needs to periodically check for those events,
2427 either by looking at the status of signals on the JTAG connector
2428 or by sending synchronous ``tell me your status'' JTAG requests
2429 to the various active targets.
2430 There is a command to manage and monitor that polling,
2431 which is normally done in the background.
2433 @deffn Command poll [@option{on}|@option{off}]
2434 Poll the current target for its current state.
2435 (Also, @pxref{targetcurstate,,target curstate}.)
2436 If that target is in debug mode, architecture
2437 specific information about the current state is printed.
2438 An optional parameter
2439 allows background polling to be enabled and disabled.
2441 You could use this from the TCL command shell, or
2442 from GDB using @command{monitor poll} command.
2443 Leave background polling enabled while you're using GDB.
2444 @example
2445 > poll
2446 background polling: on
2447 target state: halted
2448 target halted in ARM state due to debug-request, \
2449 current mode: Supervisor
2450 cpsr: 0x800000d3 pc: 0x11081bfc
2451 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2452 >
2453 @end example
2454 @end deffn
2456 @node Debug Adapter Configuration
2457 @chapter Debug Adapter Configuration
2458 @cindex config file, interface
2459 @cindex interface config file
2461 Correctly installing OpenOCD includes making your operating system give
2462 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2463 are used to select which one is used, and to configure how it is used.
2465 @quotation Note
2466 Because OpenOCD started out with a focus purely on JTAG, you may find
2467 places where it wrongly presumes JTAG is the only transport protocol
2468 in use. Be aware that recent versions of OpenOCD are removing that
2469 limitation. JTAG remains more functional than most other transports.
2470 Other transports do not support boundary scan operations, or may be
2471 specific to a given chip vendor. Some might be usable only for
2472 programming flash memory, instead of also for debugging.
2473 @end quotation
2475 Debug Adapters/Interfaces/Dongles are normally configured
2476 through commands in an interface configuration
2477 file which is sourced by your @file{openocd.cfg} file, or
2478 through a command line @option{-f interface/....cfg} option.
2480 @example
2481 source [find interface/olimex-jtag-tiny.cfg]
2482 @end example
2484 These commands tell
2485 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2486 A few cases are so simple that you only need to say what driver to use:
2488 @example
2489 # jlink interface
2490 interface jlink
2491 @end example
2493 Most adapters need a bit more configuration than that.
2496 @section Interface Configuration
2498 The interface command tells OpenOCD what type of debug adapter you are
2499 using. Depending on the type of adapter, you may need to use one or
2500 more additional commands to further identify or configure the adapter.
2502 @deffn {Config Command} {interface} name
2503 Use the interface driver @var{name} to connect to the
2504 target.
2505 @end deffn
2507 @deffn Command {interface_list}
2508 List the debug adapter drivers that have been built into
2509 the running copy of OpenOCD.
2510 @end deffn
2511 @deffn Command {interface transports} transport_name+
2512 Specifies the transports supported by this debug adapter.
2513 The adapter driver builds-in similar knowledge; use this only
2514 when external configuration (such as jumpering) changes what
2515 the hardware can support.
2516 @end deffn
2520 @deffn Command {adapter_name}
2521 Returns the name of the debug adapter driver being used.
2522 @end deffn
2524 @section Interface Drivers
2526 Each of the interface drivers listed here must be explicitly
2527 enabled when OpenOCD is configured, in order to be made
2528 available at run time.
2530 @deffn {Interface Driver} {amt_jtagaccel}
2531 Amontec Chameleon in its JTAG Accelerator configuration,
2532 connected to a PC's EPP mode parallel port.
2533 This defines some driver-specific commands:
2535 @deffn {Config Command} {parport_port} number
2536 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2537 the number of the @file{/dev/parport} device.
2538 @end deffn
2540 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2541 Displays status of RTCK option.
2542 Optionally sets that option first.
2543 @end deffn
2544 @end deffn
2546 @deffn {Interface Driver} {arm-jtag-ew}
2547 Olimex ARM-JTAG-EW USB adapter
2548 This has one driver-specific command:
2550 @deffn Command {armjtagew_info}
2551 Logs some status
2552 @end deffn
2553 @end deffn
2555 @deffn {Interface Driver} {at91rm9200}
2556 Supports bitbanged JTAG from the local system,
2557 presuming that system is an Atmel AT91rm9200
2558 and a specific set of GPIOs is used.
2559 @c command: at91rm9200_device NAME
2560 @c chooses among list of bit configs ... only one option
2561 @end deffn
2563 @deffn {Interface Driver} {cmsis-dap}
2564 ARM CMSIS-DAP compliant based adapter.
2566 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2567 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2568 the driver will attempt to auto detect the CMSIS-DAP device.
2569 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2570 @example
2571 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2572 @end example
2573 @end deffn
2575 @deffn {Command} {cmsis-dap info}
2576 Display various device information, like hardware version, firmware version, current bus status.
2577 @end deffn
2578 @end deffn
2580 @deffn {Interface Driver} {dummy}
2581 A dummy software-only driver for debugging.
2582 @end deffn
2584 @deffn {Interface Driver} {ep93xx}
2585 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2586 @end deffn
2588 @deffn {Interface Driver} {ft2232}
2589 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2591 Note that this driver has several flaws and the @command{ftdi} driver is
2592 recommended as its replacement.
2594 These interfaces have several commands, used to configure the driver
2595 before initializing the JTAG scan chain:
2597 @deffn {Config Command} {ft2232_device_desc} description
2598 Provides the USB device description (the @emph{iProduct string})
2599 of the FTDI FT2232 device. If not
2600 specified, the FTDI default value is used. This setting is only valid
2601 if compiled with FTD2XX support.
2602 @end deffn
2604 @deffn {Config Command} {ft2232_serial} serial-number
2605 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2606 in case the vendor provides unique IDs and more than one FT2232 device
2607 is connected to the host.
2608 If not specified, serial numbers are not considered.
2609 (Note that USB serial numbers can be arbitrary Unicode strings,
2610 and are not restricted to containing only decimal digits.)
2611 @end deffn
2613 @deffn {Config Command} {ft2232_layout} name
2614 Each vendor's FT2232 device can use different GPIO signals
2615 to control output-enables, reset signals, and LEDs.
2616 Currently valid layout @var{name} values include:
2617 @itemize @minus
2618 @item @b{axm0432_jtag} Axiom AXM-0432
2619 @item @b{comstick} Hitex STR9 comstick
2620 @item @b{cortino} Hitex Cortino JTAG interface
2621 @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
2622 either for the local Cortex-M3 (SRST only)
2623 or in a passthrough mode (neither SRST nor TRST)
2624 This layout can not support the SWO trace mechanism, and should be
2625 used only for older boards (before rev C).
2626 @item @b{luminary_icdi} This layout should be used with most TI/Luminary
2627 eval boards, including Rev C LM3S811 eval boards and the eponymous
2628 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2629 to debug some other target. It can support the SWO trace mechanism.
2630 @item @b{flyswatter} Tin Can Tools Flyswatter
2631 @item @b{icebear} ICEbear JTAG adapter from Section 5
2632 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2633 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2634 @item @b{m5960} American Microsystems M5960
2635 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2636 @item @b{oocdlink} OOCDLink
2637 @c oocdlink ~= jtagkey_prototype_v1
2638 @item @b{redbee-econotag} Integrated with a Redbee development board.
2639 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2640 @item @b{sheevaplug} Marvell Sheevaplug development kit
2641 @item @b{signalyzer} Xverve Signalyzer
2642 @item @b{stm32stick} Hitex STM32 Performance Stick
2643 @item @b{turtelizer2} egnite Software turtelizer2
2644 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2645 @end itemize
2646 @end deffn
2648 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2649 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2650 default values are used.
2651 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2652 @example
2653 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2654 @end example
2655 @end deffn
2657 @deffn {Config Command} {ft2232_latency} ms
2658 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2659 ft2232_read() fails to return the expected number of bytes. This can be caused by
2660 USB communication delays and has proved hard to reproduce and debug. Setting the
2661 FT2232 latency timer to a larger value increases delays for short USB packets but it
2662 also reduces the risk of timeouts before receiving the expected number of bytes.
2663 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2664 @end deffn
2666 @deffn {Config Command} {ft2232_channel} channel
2667 Used to select the channel of the ft2232 chip to use (between 1 and 4).
2668 The default value is 1.
2669 @end deffn
2671 For example, the interface config file for a
2672 Turtelizer JTAG Adapter looks something like this:
2674 @example
2675 interface ft2232
2676 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2677 ft2232_layout turtelizer2
2678 ft2232_vid_pid 0x0403 0xbdc8
2679 @end example
2680 @end deffn
2682 @deffn {Interface Driver} {ftdi}
2683 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2684 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2685 It is a complete rewrite to address a large number of problems with the ft2232
2686 interface driver.
2688 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2689 bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
2690 consistently faster than the ft2232 driver, sometimes several times faster.
2692 A major improvement of this driver is that support for new FTDI based adapters
2693 can be added competely through configuration files, without the need to patch
2694 and rebuild OpenOCD.
2696 The driver uses a signal abstraction to enable Tcl configuration files to
2697 define outputs for one or several FTDI GPIO. These outputs can then be
2698 controlled using the @command{ftdi_set_signal} command. Special signal names
2699 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2700 will be used for their customary purpose.
2702 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2703 be controlled differently. In order to support tristateable signals such as
2704 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2705 signal. The following output buffer configurations are supported:
2707 @itemize @minus
2708 @item Push-pull with one FTDI output as (non-)inverted data line
2709 @item Open drain with one FTDI output as (non-)inverted output-enable
2710 @item Tristate with one FTDI output as (non-)inverted data line and another
2711 FTDI output as (non-)inverted output-enable
2712 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2713 switching data and direction as necessary
2714 @end itemize
2716 These interfaces have several commands, used to configure the driver
2717 before initializing the JTAG scan chain:
2719 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2720 The vendor ID and product ID of the adapter. If not specified, the FTDI
2721 default values are used.
2722 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2723 @example
2724 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2725 @end example
2726 @end deffn
2728 @deffn {Config Command} {ftdi_device_desc} description
2729 Provides the USB device description (the @emph{iProduct string})
2730 of the adapter. If not specified, the device description is ignored
2731 during device selection.
2732 @end deffn
2734 @deffn {Config Command} {ftdi_serial} serial-number
2735 Specifies the @var{serial-number} of the adapter to use,
2736 in case the vendor provides unique IDs and more than one adapter
2737 is connected to the host.
2738 If not specified, serial numbers are not considered.
2739 (Note that USB serial numbers can be arbitrary Unicode strings,
2740 and are not restricted to containing only decimal digits.)
2741 @end deffn
2743 @deffn {Config Command} {ftdi_channel} channel
2744 Selects the channel of the FTDI device to use for MPSSE operations. Most
2745 adapters use the default, channel 0, but there are exceptions.
2746 @end deffn
2748 @deffn {Config Command} {ftdi_layout_init} data direction
2749 Specifies the initial values of the FTDI GPIO data and direction registers.
2750 Each value is a 16-bit number corresponding to the concatenation of the high
2751 and low FTDI GPIO registers. The values should be selected based on the
2752 schematics of the adapter, such that all signals are set to safe levels with
2753 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2754 and initially asserted reset signals.
2755 @end deffn
2757 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask]
2758 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2759 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2760 register bitmasks to tell the driver the connection and type of the output
2761 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2762 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2763 used with inverting data inputs and @option{-data} with non-inverting inputs.
2764 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2765 not-output-enable) input to the output buffer is connected.
2767 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2768 simple open-collector transistor driver would be specified with @option{-oe}
2769 only. In that case the signal can only be set to drive low or to Hi-Z and the
2770 driver will complain if the signal is set to drive high. Which means that if
2771 it's a reset signal, @command{reset_config} must be specified as
2772 @option{srst_open_drain}, not @option{srst_push_pull}.
2774 A special case is provided when @option{-data} and @option{-oe} is set to the
2775 same bitmask. Then the FTDI pin is considered being connected straight to the
2776 target without any buffer. The FTDI pin is then switched between output and
2777 input as necessary to provide the full set of low, high and Hi-Z
2778 characteristics. In all other cases, the pins specified in a signal definition
2779 are always driven by the FTDI.
2780 @end deffn
2782 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2783 Set a previously defined signal to the specified level.
2784 @itemize @minus
2785 @item @option{0}, drive low
2786 @item @option{1}, drive high
2787 @item @option{z}, set to high-impedance
2788 @end itemize
2789 @end deffn
2791 For example adapter definitions, see the configuration files shipped in the
2792 @file{interface/ftdi} directory.
2793 @end deffn
2795 @deffn {Interface Driver} {remote_bitbang}
2796 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2797 with a remote process and sends ASCII encoded bitbang requests to that process
2798 instead of directly driving JTAG.
2800 The remote_bitbang driver is useful for debugging software running on
2801 processors which are being simulated.
2803 @deffn {Config Command} {remote_bitbang_port} number
2804 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2805 sockets instead of TCP.
2806 @end deffn
2808 @deffn {Config Command} {remote_bitbang_host} hostname
2809 Specifies the hostname of the remote process to connect to using TCP, or the
2810 name of the UNIX socket to use if remote_bitbang_port is 0.
2811 @end deffn
2813 For example, to connect remotely via TCP to the host foobar you might have
2814 something like:
2816 @example
2817 interface remote_bitbang
2818 remote_bitbang_port 3335
2819 remote_bitbang_host foobar
2820 @end example
2822 To connect to another process running locally via UNIX sockets with socket
2823 named mysocket:
2825 @example
2826 interface remote_bitbang
2827 remote_bitbang_port 0
2828 remote_bitbang_host mysocket
2829 @end example
2830 @end deffn
2832 @deffn {Interface Driver} {usb_blaster}
2833 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2834 for FTDI chips. These interfaces have several commands, used to
2835 configure the driver before initializing the JTAG scan chain:
2837 @deffn {Config Command} {usb_blaster_device_desc} description
2838 Provides the USB device description (the @emph{iProduct string})
2839 of the FTDI FT245 device. If not
2840 specified, the FTDI default value is used. This setting is only valid
2841 if compiled with FTD2XX support.
2842 @end deffn
2844 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2845 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2846 default values are used.
2847 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2848 Altera USB-Blaster (default):
2849 @example
2850 usb_blaster_vid_pid 0x09FB 0x6001
2851 @end example
2852 The following VID/PID is for Kolja Waschk's USB JTAG:
2853 @example
2854 usb_blaster_vid_pid 0x16C0 0x06AD
2855 @end example
2856 @end deffn
2858 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2859 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2860 female JTAG header). These pins can be used as SRST and/or TRST provided the
2861 appropriate connections are made on the target board.
2863 For example, to use pin 6 as SRST (as with an AVR board):
2864 @example
2865 $_TARGETNAME configure -event reset-assert \
2866 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2867 @end example
2868 @end deffn
2870 @end deffn
2872 @deffn {Interface Driver} {gw16012}
2873 Gateworks GW16012 JTAG programmer.
2874 This has one driver-specific command:
2876 @deffn {Config Command} {parport_port} [port_number]
2877 Display either the address of the I/O port
2878 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2879 If a parameter is provided, first switch to use that port.
2880 This is a write-once setting.
2881 @end deffn
2882 @end deffn
2884 @deffn {Interface Driver} {jlink}
2885 Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
2887 @quotation Compatibility Note
2888 Segger released many firmware versions for the many harware versions they
2889 produced. OpenOCD was extensively tested and intended to run on all of them,
2890 but some combinations were reported as incompatible. As a general
2891 recommendation, it is advisable to use the latest firmware version
2892 available for each hardware version. However the current V8 is a moving
2893 target, and Segger firmware versions released after the OpenOCD was
2894 released may not be compatible. In such cases it is recommended to
2895 revert to the last known functional version. For 0.5.0, this is from
2896 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2897 version is from "May 3 2012 18:36:22", packed with 4.46f.
2898 @end quotation
2900 @deffn {Command} {jlink caps}
2901 Display the device firmware capabilities.
2902 @end deffn
2903 @deffn {Command} {jlink info}
2904 Display various device information, like hardware version, firmware version, current bus status.
2905 @end deffn
2906 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2907 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2908 @end deffn
2909 @deffn {Command} {jlink config}
2910 Display the J-Link configuration.
2911 @end deffn
2912 @deffn {Command} {jlink config kickstart} [val]
2913 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2914 @end deffn
2915 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2916 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2917 @end deffn
2918 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2919 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2920 E the bit of the subnet mask and
2921 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2922 @end deffn
2923 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2924 Set the USB address; this will also change the product id. Without argument, show the USB address.
2925 @end deffn
2926 @deffn {Command} {jlink config reset}
2927 Reset the current configuration.
2928 @end deffn
2929 @deffn {Command} {jlink config save}
2930 Save the current configuration to the internal persistent storage.
2931 @end deffn
2932 @deffn {Config} {jlink pid} val
2933 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2934 @end deffn
2935 @end deffn
2937 @deffn {Interface Driver} {parport}
2938 Supports PC parallel port bit-banging cables:
2939 Wigglers, PLD download cable, and more.
2940 These interfaces have several commands, used to configure the driver
2941 before initializing the JTAG scan chain:
2943 @deffn {Config Command} {parport_cable} name
2944 Set the layout of the parallel port cable used to connect to the target.
2945 This is a write-once setting.
2946 Currently valid cable @var{name} values include:
2948 @itemize @minus
2949 @item @b{altium} Altium Universal JTAG cable.
2950 @item @b{arm-jtag} Same as original wiggler except SRST and
2951 TRST connections reversed and TRST is also inverted.
2952 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2953 in configuration mode. This is only used to
2954 program the Chameleon itself, not a connected target.
2955 @item @b{dlc5} The Xilinx Parallel cable III.
2956 @item @b{flashlink} The ST Parallel cable.
2957 @item @b{lattice} Lattice ispDOWNLOAD Cable
2958 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2959 some versions of
2960 Amontec's Chameleon Programmer. The new version available from
2961 the website uses the original Wiggler layout ('@var{wiggler}')
2962 @item @b{triton} The parallel port adapter found on the
2963 ``Karo Triton 1 Development Board''.
2964 This is also the layout used by the HollyGates design
2965 (see @uref{}).
2966 @item @b{wiggler} The original Wiggler layout, also supported by
2967 several clones, such as the Olimex ARM-JTAG
2968 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2969 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2970 @end itemize
2971 @end deffn
2973 @deffn {Config Command} {parport_port} [port_number]
2974 Display either the address of the I/O port
2975 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2976 If a parameter is provided, first switch to use that port.
2977 This is a write-once setting.
2979 When using PPDEV to access the parallel port, use the number of the parallel port:
2980 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2981 you may encounter a problem.
2982 @end deffn
2984 @deffn Command {parport_toggling_time} [nanoseconds]
2985 Displays how many nanoseconds the hardware needs to toggle TCK;
2986 the parport driver uses this value to obey the
2987 @command{adapter_khz} configuration.
2988 When the optional @var{nanoseconds} parameter is given,
2989 that setting is changed before displaying the current value.
2991 The default setting should work reasonably well on commodity PC hardware.
2992 However, you may want to calibrate for your specific hardware.
2993 @quotation Tip
2994 To measure the toggling time with a logic analyzer or a digital storage
2995 oscilloscope, follow the procedure below:
2996 @example
2997 > parport_toggling_time 1000
2998 > adapter_khz 500
2999 @end example
3000 This sets the maximum JTAG clock speed of the hardware, but
3001 the actual speed probably deviates from the requested 500 kHz.
3002 Now, measure the time between the two closest spaced TCK transitions.
3003 You can use @command{runtest 1000} or something similar to generate a
3004 large set of samples.
3005 Update the setting to match your measurement:
3006 @example
3007 > parport_toggling_time <measured nanoseconds>
3008 @end example
3009 Now the clock speed will be a better match for @command{adapter_khz rate}
3010 commands given in OpenOCD scripts and event handlers.
3012 You can do something similar with many digital multimeters, but note
3013 that you'll probably need to run the clock continuously for several
3014 seconds before it decides what clock rate to show. Adjust the
3015 toggling time up or down until the measured clock rate is a good
3016 match for the adapter_khz rate you specified; be conservative.
3017 @end quotation
3018 @end deffn
3020 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
3021 This will configure the parallel driver to write a known
3022 cable-specific value to the parallel interface on exiting OpenOCD.
3023 @end deffn
3025 For example, the interface configuration file for a
3026 classic ``Wiggler'' cable on LPT2 might look something like this:
3028 @example
3029 interface parport
3030 parport_port 0x278
3031 parport_cable wiggler
3032 @end example
3033 @end deffn
3035 @deffn {Interface Driver} {presto}
3036 ASIX PRESTO USB JTAG programmer.
3037 @deffn {Config Command} {presto_serial} serial_string
3038 Configures the USB serial number of the Presto device to use.
3039 @end deffn
3040 @end deffn
3042 @deffn {Interface Driver} {rlink}
3043 Raisonance RLink USB adapter
3044 @end deffn
3046 @deffn {Interface Driver} {usbprog}
3047 usbprog is a freely programmable USB adapter.
3048 @end deffn
3050 @deffn {Interface Driver} {vsllink}
3051 vsllink is part of Versaloon which is a versatile USB programmer.
3053 @quotation Note
3054 This defines quite a few driver-specific commands,
3055 which are not currently documented here.
3056 @end quotation
3057 @end deffn
3059 @deffn {Interface Driver} {hla}
3060 This is a driver that supports multiple High Level Adapters.
3061 This type of adapter does not expose some of the lower level api's
3062 that OpenOCD would normally use to access the target.
3064 Currently supported adapters include the ST STLINK and TI ICDI.
3066 @deffn {Config Command} {hla_device_desc} description
3067 Currently Not Supported.
3068 @end deffn
3070 @deffn {Config Command} {hla_serial} serial
3071 Currently Not Supported.
3072 @end deffn
3074 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
3075 Specifies the adapter layout to use.
3076 @end deffn
3078 @deffn {Config Command} {hla_vid_pid} vid pid
3079 The vendor ID and product ID of the device.
3080 @end deffn
3082 @deffn {Config Command} {trace} source_clock_hz [output_file_path]
3083 Enable SWO tracing (if supported). The source clock rate for the
3084 trace port must be specified, this is typically the CPU clock rate. If
3085 the optional output file is specified then raw trace data is appended
3086 to the file, and the file is created if it does not exist.
3087 @end deffn
3088 @end deffn
3090 @deffn {Interface Driver} {opendous}
3091 opendous-jtag is a freely programmable USB adapter.
3092 @end deffn
3094 @deffn {Interface Driver} {ulink}
3095 This is the Keil ULINK v1 JTAG debugger.
3096 @end deffn
3098 @deffn {Interface Driver} {ZY1000}
3099 This is the Zylin ZY1000 JTAG debugger.
3100 @end deffn
3102 @quotation Note
3103 This defines some driver-specific commands,
3104 which are not currently documented here.
3105 @end quotation
3107 @deffn Command power [@option{on}|@option{off}]
3108 Turn power switch to target on/off.
3109 No arguments: print status.
3110 @end deffn
3112 @deffn {Interface Driver} {bcm2835gpio}
3113 This SoC is present in Raspberry Pi which is a cheap single-board computer
3114 exposing some GPIOs on its expansion header.
3116 The driver accesses memory-mapped GPIO peripheral registers directly
3117 for maximum performance, but the only possible race condition is for
3118 the pins' modes/muxing (which is highly unlikely), so it should be
3119 able to coexist nicely with both sysfs bitbanging and various
3120 peripherals' kernel drivers. The driver restores the previous
3121 configuration on exit.
3123 See @file{interface/raspberrypi-native.cfg} for a sample config and
3124 pinout.
3126 @end deffn
3128 @section Transport Configuration
3129 @cindex Transport
3130 As noted earlier, depending on the version of OpenOCD you use,
3131 and the debug adapter you are using,
3132 several transports may be available to
3133 communicate with debug targets (or perhaps to program flash memory).
3134 @deffn Command {transport list}
3135 displays the names of the transports supported by this
3136 version of OpenOCD.
3137 @end deffn
3139 @deffn Command {transport select} transport_name
3140 Select which of the supported transports to use in this OpenOCD session.
3141 The transport must be supported by the debug adapter hardware and by the
3142 version of OpenOCD you are using (including the adapter's driver).
3143 No arguments: returns name of session's selected transport.
3144 @end deffn
3146 @subsection JTAG Transport
3147 @cindex JTAG
3148 JTAG is the original transport supported by OpenOCD, and most
3149 of the OpenOCD commands support it.
3150 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3151 each of which must be explicitly declared.
3152 JTAG supports both debugging and boundary scan testing.
3153 Flash programming support is built on top of debug support.
3154 @subsection SWD Transport
3155 @cindex SWD
3156 @cindex Serial Wire Debug
3157 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3158 Debug Access Point (DAP, which must be explicitly declared.
3159 (SWD uses fewer signal wires than JTAG.)
3160 SWD is debug-oriented, and does not support boundary scan testing.
3161 Flash programming support is built on top of debug support.
3162 (Some processors support both JTAG and SWD.)
3163 @deffn Command {swd newdap} ...
3164 Declares a single DAP which uses SWD transport.
3165 Parameters are currently the same as "jtag newtap" but this is
3166 expected to change.
3167 @end deffn
3168 @deffn Command {swd wcr trn prescale}
3169 Updates TRN (turnaraound delay) and prescaling.fields of the
3170 Wire Control Register (WCR).
3171 No parameters: displays current settings.
3172 @end deffn
3174 @subsection CMSIS-DAP Transport
3175 @cindex CMSIS-DAP
3176 CMSIS-DAP is an ARM-specific transport that is used to connect to
3177 compilant debuggers.
3179 @subsection SPI Transport
3180 @cindex SPI
3181 @cindex Serial Peripheral Interface
3182 The Serial Peripheral Interface (SPI) is a general purpose transport
3183 which uses four wire signaling. Some processors use it as part of a
3184 solution for flash programming.
3186 @anchor{jtagspeed}
3187 @section JTAG Speed
3188 JTAG clock setup is part of system setup.
3189 It @emph{does not belong with interface setup} since any interface
3190 only knows a few of the constraints for the JTAG clock speed.
3191 Sometimes the JTAG speed is
3192 changed during the target initialization process: (1) slow at
3193 reset, (2) program the CPU clocks, (3) run fast.
3194 Both the "slow" and "fast" clock rates are functions of the
3195 oscillators used, the chip, the board design, and sometimes
3196 power management software that may be active.
3198 The speed used during reset, and the scan chain verification which
3199 follows reset, can be adjusted using a @code{reset-start}
3200 target event handler.
3201 It can then be reconfigured to a faster speed by a
3202 @code{reset-init} target event handler after it reprograms those
3203 CPU clocks, or manually (if something else, such as a boot loader,
3204 sets up those clocks).
3205 @xref{targetevents,,Target Events}.
3206 When the initial low JTAG speed is a chip characteristic, perhaps
3207 because of a required oscillator speed, provide such a handler
3208 in the target config file.
3209 When that speed is a function of a board-specific characteristic
3210 such as which speed oscillator is used, it belongs in the board
3211 config file instead.
3212 In both cases it's safest to also set the initial JTAG clock rate
3213 to that same slow speed, so that OpenOCD never starts up using a
3214 clock speed that's faster than the scan chain can support.
3216 @example
3217 jtag_rclk 3000
3218 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3219 @end example
3221 If your system supports adaptive clocking (RTCK), configuring
3222 JTAG to use that is probably the most robust approach.
3223 However, it introduces delays to synchronize clocks; so it
3224 may not be the fastest solution.
3226 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3227 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3228 which support adaptive clocking.
3230 @deffn {Command} adapter_khz max_speed_kHz
3231 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3232 JTAG interfaces usually support a limited number of
3233 speeds. The speed actually used won't be faster
3234 than the speed specified.
3236 Chip data sheets generally include a top JTAG clock rate.
3237 The actual rate is often a function of a CPU core clock,
3238 and is normally less than that peak rate.
3239 For example, most ARM cores accept at most one sixth of the CPU clock.
3241 Speed 0 (khz) selects RTCK method.
3242 @xref{faqrtck,,FAQ RTCK}.
3243 If your system uses RTCK, you won't need to change the
3244 JTAG clocking after setup.
3245 Not all interfaces, boards, or targets support ``rtck''.
3246 If the interface device can not
3247 support it, an error is returned when you try to use RTCK.
3248 @end deffn
3250 @defun jtag_rclk fallback_speed_kHz
3251 @cindex adaptive clocking
3252 @cindex RTCK
3253 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3254 If that fails (maybe the interface, board, or target doesn't
3255 support it), falls back to the specified frequency.
3256 @example
3257 # Fall back to 3mhz if RTCK is not supported
3258 jtag_rclk 3000
3259 @end example
3260 @end defun
3262 @node Reset Configuration
3263 @chapter Reset Configuration
3264 @cindex Reset Configuration
3266 Every system configuration may require a different reset
3267 configuration. This can also be quite confusing.
3268 Resets also interact with @var{reset-init} event handlers,
3269 which do things like setting up clocks and DRAM, and
3270 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3271 They can also interact with JTAG routers.
3272 Please see the various board files for examples.
3274 @quotation Note
3275 To maintainers and integrators:
3276 Reset configuration touches several things at once.
3277 Normally the board configuration file
3278 should define it and assume that the JTAG adapter supports
3279 everything that's wired up to the board's JTAG connector.
3281 However, the target configuration file could also make note
3282 of something the silicon vendor has done inside the chip,
3283 which will be true for most (or all) boards using that chip.
3284 And when the JTAG adapter doesn't support everything, the
3285 user configuration file will need to override parts of
3286 the reset configuration provided by other files.
3287 @end quotation
3289 @section Types of Reset
3291 There are many kinds of reset possible through JTAG, but
3292 they may not all work with a given board and adapter.
3293 That's part of why reset configuration can be error prone.
3295 @itemize @bullet
3296 @item
3297 @emph{System Reset} ... the @emph{SRST} hardware signal
3298 resets all chips connected to the JTAG adapter, such as processors,
3299 power management chips, and I/O controllers. Normally resets triggered
3300 with this signal behave exactly like pressing a RESET button.
3301 @item
3302 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3303 just the TAP controllers connected to the JTAG adapter.
3304 Such resets should not be visible to the rest of the system; resetting a
3305 device's TAP controller just puts that controller into a known state.
3306 @item
3307 @emph{Emulation Reset} ... many devices can be reset through JTAG
3308 commands. These resets are often distinguishable from system
3309 resets, either explicitly (a "reset reason" register says so)
3310 or implicitly (not all parts of the chip get reset).
3311 @item
3312 @emph{Other Resets} ... system-on-chip devices often support
3313 several other types of reset.
3314 You may need to arrange that a watchdog timer stops
3315 while debugging, preventing a watchdog reset.
3316 There may be individual module resets.
3317 @end itemize
3319 In the best case, OpenOCD can hold SRST, then reset
3320 the TAPs via TRST and send commands through JTAG to halt the
3321 CPU at the reset vector before the 1st instruction is executed.
3322 Then when it finally releases the SRST signal, the system is
3323 halted under debugger control before any code has executed.
3324 This is the behavior required to support the @command{reset halt}
3325 and @command{reset init} commands; after @command{reset init} a
3326 board-specific script might do things like setting up DRAM.
3327 (@xref{resetcommand,,Reset Command}.)
3329 @anchor{srstandtrstissues}
3330 @section SRST and TRST Issues
3332 Because SRST and TRST are hardware signals, they can have a
3333 variety of system-specific constraints. Some of the most
3334 common issues are:
3336 @itemize @bullet
3338 @item @emph{Signal not available} ... Some boards don't wire
3339 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3340 support such signals even if they are wired up.
3341 Use the @command{reset_config} @var{signals} options to say
3342 when either of those signals is not connected.
3343 When SRST is not available, your code might not be able to rely
3344 on controllers having been fully reset during code startup.
3345 Missing TRST is not a problem, since JTAG-level resets can
3346 be triggered using with TMS signaling.
3348 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3349 adapter will connect SRST to TRST, instead of keeping them separate.
3350 Use the @command{reset_config} @var{combination} options to say
3351 when those signals aren't properly independent.
3353 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3354 delay circuit, reset supervisor, or on-chip features can extend
3355 the effect of a JTAG adapter's reset for some time after the adapter
3356 stops issuing the reset. For example, there may be chip or board
3357 requirements that all reset pulses last for at least a
3358 certain amount of time; and reset buttons commonly have
3359 hardware debouncing.
3360 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3361 commands to say when extra delays are needed.
3363 @item @emph{Drive type} ... Reset lines often have a pullup
3364 resistor, letting the JTAG interface treat them as open-drain
3365 signals. But that's not a requirement, so the adapter may need
3366 to use push/pull output drivers.
3367 Also, with weak pullups it may be advisable to drive
3368 signals to both levels (push/pull) to minimize rise times.
3369 Use the @command{reset_config} @var{trst_type} and
3370 @var{srst_type} parameters to say how to drive reset signals.
3372 @item @emph{Special initialization} ... Targets sometimes need
3373 special JTAG initialization sequences to handle chip-specific
3374 issues (not limited to errata).
3375 For example, certain JTAG commands might need to be issued while
3376 the system as a whole is in a reset state (SRST active)
3377 but the JTAG scan chain is usable (TRST inactive).
3378 Many systems treat combined assertion of SRST and TRST as a
3379 trigger for a harder reset than SRST alone.
3380 Such custom reset handling is discussed later in this chapter.
3381 @end itemize
3383 There can also be other issues.
3384 Some devices don't fully conform to the JTAG specifications.
3385 Trivial system-specific differences are common, such as
3386 SRST and TRST using slightly different names.
3387 There are also vendors who distribute key JTAG documentation for
3388 their chips only to developers who have signed a Non-Disclosure
3389 Agreement (NDA).
3391 Sometimes there are chip-specific extensions like a requirement to use
3392 the normally-optional TRST signal (precluding use of JTAG adapters which
3393 don't pass TRST through), or needing extra steps to complete a TAP reset.
3395 In short, SRST and especially TRST handling may be very finicky,
3396 needing to cope with both architecture and board specific constraints.
3398 @section Commands for Handling Resets
3400 @deffn {Command} adapter_nsrst_assert_width milliseconds
3401 Minimum amount of time (in milliseconds) OpenOCD should wait
3402 after asserting nSRST (active-low system reset) before
3403 allowing it to be deasserted.
3404 @end deffn
3406 @deffn {Command} adapter_nsrst_delay milliseconds
3407 How long (in milliseconds) OpenOCD should wait after deasserting
3408 nSRST (active-low system reset) before starting new JTAG operations.
3409 When a board has a reset button connected to SRST line it will
3410 probably have hardware debouncing, implying you should use this.
3411 @end deffn
3413 @deffn {Command} jtag_ntrst_assert_width milliseconds
3414 Minimum amount of time (in milliseconds) OpenOCD should wait
3415 after asserting nTRST (active-low JTAG TAP reset) before
3416 allowing it to be deasserted.
3417 @end deffn
3419 @deffn {Command} jtag_ntrst_delay milliseconds
3420 How long (in milliseconds) OpenOCD should wait after deasserting
3421 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3422 @end deffn
3424 @deffn {Command} reset_config mode_flag ...
3425 This command displays or modifies the reset configuration
3426 of your combination of JTAG board and target in target
3427 configuration scripts.
3429 Information earlier in this section describes the kind of problems
3430 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3431 As a rule this command belongs only in board config files,
3432 describing issues like @emph{board doesn't connect TRST};
3433 or in user config files, addressing limitations derived
3434 from a particular combination of interface and board.
3435 (An unlikely example would be using a TRST-only adapter
3436 with a board that only wires up SRST.)
3438 The @var{mode_flag} options can be specified in any order, but only one
3439 of each type -- @var{signals}, @var{combination}, @var{gates},
3440 @var{trst_type}, @var{srst_type} and @var{connect_type}
3441 -- may be specified at a time.
3442 If you don't provide a new value for a given type, its previous
3443 value (perhaps the default) is unchanged.
3444 For example, this means that you don't need to say anything at all about
3445 TRST just to declare that if the JTAG adapter should want to drive SRST,
3446 it must explicitly be driven high (@option{srst_push_pull}).
3448 @itemize
3449 @item
3450 @var{signals} can specify which of the reset signals are connected.
3451 For example, If the JTAG interface provides SRST, but the board doesn't
3452 connect that signal properly, then OpenOCD can't use it.
3453 Possible values are @option{none} (the default), @option{trst_only},
3454 @option{srst_only} and @option{trst_and_srst}.
3456 @quotation Tip
3457 If your board provides SRST and/or TRST through the JTAG connector,
3458 you must declare that so those signals can be used.
3459 @end quotation
3461 @item
3462 The @var{combination} is an optional value specifying broken reset
3463 signal implementations.
3464 The default behaviour if no option given is @option{separate},
3465 indicating everything behaves normally.
3466 @option{srst_pulls_trst} states that the
3467 test logic is reset together with the reset of the system (e.g. NXP
3468 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3469 the system is reset together with the test logic (only hypothetical, I
3470 haven't seen hardware with such a bug, and can be worked around).
3471 @option{combined} implies both @option{srst_pulls_trst} and
3472 @option{trst_pulls_srst}.
3474 @item
3475 The @var{gates} tokens control flags that describe some cases where
3476 JTAG may be unvailable during reset.
3477 @option{srst_gates_jtag} (default)
3478 indicates that asserting SRST gates the
3479 JTAG clock. This means that no communication can happen on JTAG
3480 while SRST is asserted.
3481 Its converse is @option{srst_nogate}, indicating that JTAG commands
3482 can safely be issued while SRST is active.
3484 @item
3485 The @var{connect_type} tokens control flags that describe some cases where
3486 SRST is asserted while connecting to the target. @option{srst_nogate}
3487 is required to use this option.
3488 @option{connect_deassert_srst} (default)
3489 indicates that SRST will not be asserted while connecting to the target.
3490 Its converse is @option{connect_assert_srst}, indicating that SRST will
3491 be asserted before any target connection.
3492 Only some targets support this feature, STM32 and STR9 are examples.
3493 This feature is useful if you are unable to connect to your target due
3494 to incorrect options byte config or illegal program execution.
3495 @end itemize
3497 The optional @var{trst_type} and @var{srst_type} parameters allow the
3498 driver mode of each reset line to be specified. These values only affect
3499 JTAG interfaces with support for different driver modes, like the Amontec
3500 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3501 relevant signal (TRST or SRST) is not connected.
3503 @itemize
3504 @item
3505 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3506 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3507 Most boards connect this signal to a pulldown, so the JTAG TAPs
3508 never leave reset unless they are hooked up to a JTAG adapter.
3510 @item
3511 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3512 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3513 Most boards connect this signal to a pullup, and allow the
3514 signal to be pulled low by various events including system
3515 powerup and pressing a reset button.
3516 @end itemize
3517 @end deffn
3519 @section Custom Reset Handling
3520 @cindex events
3522 OpenOCD has several ways to help support the various reset
3523 mechanisms provided by chip and board vendors.
3524 The commands shown in the previous section give standard parameters.
3525 There are also @emph{event handlers} associated with TAPs or Targets.
3526 Those handlers are Tcl procedures you can provide, which are invoked
3527 at particular points in the reset sequence.
3529 @emph{When SRST is not an option} you must set
3530 up a @code{reset-assert} event handler for your target.
3531 For example, some JTAG adapters don't include the SRST signal;
3532 and some boards have multiple targets, and you won't always
3533 want to reset everything at once.
3535 After configuring those mechanisms, you might still
3536 find your board doesn't start up or reset correctly.
3537 For example, maybe it needs a slightly different sequence
3538 of SRST and/or TRST manipulations, because of quirks that
3539 the @command{reset_config} mechanism doesn't address;
3540 or asserting both might trigger a stronger reset, which
3541 needs special attention.
3543 Experiment with lower level operations, such as @command{jtag_reset}
3544 and the @command{jtag arp_*} operations shown here,
3545 to find a sequence of operations that works.
3546 @xref{JTAG Commands}.
3547 When you find a working sequence, it can be used to override
3548 @command{jtag_init}, which fires during OpenOCD startup
3549 (@pxref{configurationstage,,Configuration Stage});
3550 or @command{init_reset}, which fires during reset processing.
3552 You might also want to provide some project-specific reset
3553 schemes. For example, on a multi-target board the standard
3554 @command{reset} command would reset all targets, but you
3555 may need the ability to reset only one target at time and
3556 thus want to avoid using the board-wide SRST signal.
3558 @deffn {Overridable Procedure} init_reset mode
3559 This is invoked near the beginning of the @command{reset} command,
3560 usually to provide as much of a cold (power-up) reset as practical.
3561 By default it is also invoked from @command{jtag_init} if
3562 the scan chain does not respond to pure JTAG operations.
3563 The @var{mode} parameter is the parameter given to the
3564 low level reset command (@option{halt},
3565 @option{init}, or @option{run}), @option{setup},
3566 or potentially some other value.
3568 The default implementation just invokes @command{jtag arp_init-reset}.
3569 Replacements will normally build on low level JTAG
3570 operations such as @command{jtag_reset}.
3571 Operations here must not address individual TAPs
3572 (or their associated targets)
3573 until the JTAG scan chain has first been verified to work.
3575 Implementations must have verified the JTAG scan chain before
3576 they return.
3577 This is done by calling @command{jtag arp_init}
3578 (or @command{jtag arp_init-reset}).
3579 @end deffn
3581 @deffn Command {jtag arp_init}
3582 This validates the scan chain using just the four
3583 standard JTAG signals (TMS, TCK, TDI, TDO).
3584 It starts by issuing a JTAG-only reset.
3585 Then it performs checks to verify that the scan chain configuration
3586 matches the TAPs it can observe.
3587 Those checks include checking IDCODE values for each active TAP,
3588 and verifying the length of their instruction registers using
3589 TAP @code{-ircapture} and @code{-irmask} values.
3590 If these tests all pass, TAP @code{setup} events are
3591 issued to all TAPs with handlers for that event.
3592 @end deffn
3594 @deffn Command {jtag arp_init-reset}
3595 This uses TRST and SRST to try resetting
3596 everything on the JTAG scan chain
3597 (and anything else connected to SRST).
3598 It then invokes the logic of @command{jtag arp_init}.
3599 @end deffn
3602 @node TAP Declaration
3603 @chapter TAP Declaration
3604 @cindex TAP declaration
3605 @cindex TAP configuration
3607 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3608 TAPs serve many roles, including:
3610 @itemize @bullet
3611 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3612 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3613 Others do it indirectly, making a CPU do it.
3614 @item @b{Program Download} Using the same CPU support GDB uses,
3615 you can initialize a DRAM controller, download code to DRAM, and then
3616 start running that code.
3617 @item @b{Boundary Scan} Most chips support boundary scan, which
3618 helps test for board assembly problems like solder bridges
3619 and missing connections.
3620 @end itemize
3622 OpenOCD must know about the active TAPs on your board(s).
3623 Setting up the TAPs is the core task of your configuration files.
3624 Once those TAPs are set up, you can pass their names to code
3625 which sets up CPUs and exports them as GDB targets,
3626 probes flash memory, performs low-level JTAG operations, and more.
3628 @section Scan Chains
3629 @cindex scan chain
3631 TAPs are part of a hardware @dfn{scan chain},
3632 which is a daisy chain of TAPs.
3633 They also need to be added to
3634 OpenOCD's software mirror of that hardware list,
3635 giving each member a name and associating other data with it.
3636 Simple scan chains, with a single TAP, are common in
3637 systems with a single microcontroller or microprocessor.
3638 More complex chips may have several TAPs internally.
3639 Very complex scan chains might have a dozen or more TAPs:
3640 several in one chip, more in the next, and connecting
3641 to other boards with their own chips and TAPs.
3643 You can display the list with the @command{scan_chain} command.
3644 (Don't confuse this with the list displayed by the @command{targets}
3645 command, presented in the next chapter.
3646 That only displays TAPs for CPUs which are configured as
3647 debugging targets.)
3648 Here's what the scan chain might look like for a chip more than one TAP:
3650 @verbatim
3651 TapName Enabled IdCode Expected IrLen IrCap IrMask
3652 -- ------------------ ------- ---------- ---------- ----- ----- ------
3653 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3654 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3655 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3656 @end verbatim
3658 OpenOCD can detect some of that information, but not all
3659 of it. @xref{autoprobing,,Autoprobing}.
3660 Unfortunately, those TAPs can't always be autoconfigured,
3661 because not all devices provide good support for that.
3662 JTAG doesn't require supporting IDCODE instructions, and
3663 chips with JTAG routers may not link TAPs into the chain
3664 until they are told to do so.
3666 The configuration mechanism currently supported by OpenOCD
3667 requires explicit configuration of all TAP devices using
3668 @command{jtag newtap} commands, as detailed later in this chapter.
3669 A command like this would declare one tap and name it @code{chip1.cpu}:
3671 @example
3672 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3673 @end example
3675 Each target configuration file lists the TAPs provided
3676 by a given chip.
3677 Board configuration files combine all the targets on a board,
3678 and so forth.
3679 Note that @emph{the order in which TAPs are declared is very important.}
3680 That declaration order must match the order in the JTAG scan chain,
3681 both inside a single chip and between them.
3682 @xref{faqtaporder,,FAQ TAP Order}.
3684 For example, the ST Microsystems STR912 chip has
3685 three separate TAPs@footnote{See the ST
3686 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3687 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3688 @url{}}.
3689 To configure those taps, @file{target/str912.cfg}
3690 includes commands something like this:
3692 @example
3693 jtag newtap str912 flash ... params ...
3694 jtag newtap str912 cpu ... params ...
3695 jtag newtap str912 bs ... params ...
3696 @end example
3698 Actual config files typically use a variable such as @code{$_CHIPNAME}
3699 instead of literals like @option{str912}, to support more than one chip
3700 of each type. @xref{Config File Guidelines}.
3702 @deffn Command {jtag names}
3703 Returns the names of all current TAPs in the scan chain.
3704 Use @command{jtag cget} or @command{jtag tapisenabled}
3705 to examine attributes and state of each TAP.
3706 @example
3707 foreach t [jtag names] @{
3708 puts [format "TAP: %s\n" $t]
3709 @}
3710 @end example
3711 @end deffn
3713 @deffn Command {scan_chain}
3714 Displays the TAPs in the scan chain configuration,
3715 and their status.
3716 The set of TAPs listed by this command is fixed by
3717 exiting the OpenOCD configuration stage,
3718 but systems with a JTAG router can
3719 enable or disable TAPs dynamically.
3720 @end deffn
3722 @c FIXME! "jtag cget" should be able to return all TAP
3723 @c attributes, like "$target_name cget" does for targets.
3725 @c Probably want "jtag eventlist", and a "tap-reset" event
3726 @c (on entry to RESET state).
3728 @section TAP Names
3729 @cindex dotted name
3731 When TAP objects are declared with @command{jtag newtap},
3732 a @dfn{} is created for the TAP, combining the
3733 name of a module (usually a chip) and a label for the TAP.
3734 For example: @code{xilinx.tap}, @code{str912.flash},
3735 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3736 Many other commands use that to manipulate or
3737 refer to the TAP. For example, CPU configuration uses the
3738 name, as does declaration of NAND or NOR flash banks.
3740 The components of a dotted name should follow ``C'' symbol
3741 name rules: start with an alphabetic character, then numbers
3742 and underscores are OK; while others (including dots!) are not.
3744 @section TAP Declaration Commands
3746 @c shouldn't this be(come) a {Config Command}?
3747 @deffn Command {jtag newtap} chipname tapname configparams...
3748 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3749 and configured according to the various @var{configparams}.
3751 The @var{chipname} is a symbolic name for the chip.
3752 Conventionally target config files use @code{$_CHIPNAME},
3753 defaulting to the model name given by the chip vendor but
3754 overridable.
3756 @cindex TAP naming convention
3757 The @var{tapname} reflects the role of that TAP,
3758 and should follow this convention:
3760 @itemize @bullet
3761 @item @code{bs} -- For boundary scan if this is a separate TAP;
3762 @item @code{cpu} -- The main CPU of the chip, alternatively
3763 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3764 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3765 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3766 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3767 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3768 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3769 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3770 with a single TAP;
3771 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3772 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3773 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3774 a JTAG TAP; that TAP should be named @code{sdma}.
3775 @end itemize
3777 Every TAP requires at least the following @var{configparams}:
3779 @itemize @bullet
3780 @item @code{-irlen} @var{NUMBER}
3781 @*The length in bits of the
3782 instruction register, such as 4 or 5 bits.
3783 @end itemize
3785 A TAP may also provide optional @var{configparams}:
3787 @itemize @bullet
3788 @item @code{-disable} (or @code{-enable})
3789 @*Use the @code{-disable} parameter to flag a TAP which is not
3790 linked into the scan chain after a reset using either TRST
3791 or the JTAG state machine's @sc{reset} state.
3792 You may use @code{-enable} to highlight the default state
3793 (the TAP is linked in).
3794 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3795 @item @code{-expected-id} @var{NUMBER}
3796 @*A non-zero @var{number} represents a 32-bit IDCODE
3797 which you expect to find when the scan chain is examined.
3798 These codes are not required by all JTAG devices.
3799 @emph{Repeat the option} as many times as required if more than one
3800 ID code could appear (for example, multiple versions).
3801 Specify @var{number} as zero to suppress warnings about IDCODE
3802 values that were found but not included in the list.
3804 Provide this value if at all possible, since it lets OpenOCD
3805 tell when the scan chain it sees isn't right. These values
3806 are provided in vendors' chip documentation, usually a technical
3807 reference manual. Sometimes you may need to probe the JTAG
3808 hardware to find these values.
3809 @xref{autoprobing,,Autoprobing}.
3810 @item @code{-ignore-version}
3811 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3812 option. When vendors put out multiple versions of a chip, or use the same
3813 JTAG-level ID for several largely-compatible chips, it may be more practical
3814 to ignore the version field than to update config files to handle all of
3815 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3816 @item @code{-ircapture} @var{NUMBER}
3817 @*The bit pattern loaded by the TAP into the JTAG shift register
3818 on entry to the @sc{ircapture} state, such as 0x01.
3819 JTAG requires the two LSBs of this value to be 01.
3820 By default, @code{-ircapture} and @code{-irmask} are set
3821 up to verify that two-bit value. You may provide
3822 additional bits if you know them, or indicate that
3823 a TAP doesn't conform to the JTAG specification.
3824 @item @code{-irmask} @var{NUMBER}
3825 @*A mask used with @code{-ircapture}
3826 to verify that instruction scans work correctly.
3827 Such scans are not used by OpenOCD except to verify that
3828 there seems to be no problems with JTAG scan chain operations.
3829 @end itemize
3830 @end deffn
3832 @section Other TAP commands
3834 @deffn Command {jtag cget} @option{-event} event_name
3835 @deffnx Command {jtag configure} @option{-event} event_name handler
3836 At this writing this TAP attribute
3837 mechanism is used only for event handling.
3838 (It is not a direct analogue of the @code{cget}/@code{configure}
3839 mechanism for debugger targets.)
3840 See the next section for information about the available events.
3842 The @code{configure} subcommand assigns an event handler,
3843 a TCL string which is evaluated when the event is triggered.
3844 The @code{cget} subcommand returns that handler.
3845 @end deffn
3847 @section TAP Events
3848 @cindex events
3849 @cindex TAP events
3851 OpenOCD includes two event mechanisms.
3852 The one presented here applies to all JTAG TAPs.
3853 The other applies to debugger targets,
3854 which are associated with certain TAPs.
3856 The TAP events currently defined are:
3858 @itemize @bullet
3859 @item @b{post-reset}
3860 @* The TAP has just completed a JTAG reset.
3861 The tap may still be in the JTAG @sc{reset} state.
3862 Handlers for these events might perform initialization sequences
3863 such as issuing TCK cycles, TMS sequences to ensure
3864 exit from the ARM SWD mode, and more.
3866 Because the scan chain has not yet been verified, handlers for these events
3867 @emph{should not issue commands which scan the JTAG IR or DR registers}
3868 of any particular target.
3869 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3870 @item @b{setup}
3871 @* The scan chain has been reset and verified.
3872 This handler may enable TAPs as needed.
3873 @item @b{tap-disable}
3874 @* The TAP needs to be disabled. This handler should
3875 implement @command{jtag tapdisable}
3876 by issuing the relevant JTAG commands.
3877 @item @b{tap-enable}
3878 @* The TAP needs to be enabled. This handler should
3879 implement @command{jtag tapenable}
3880 by issuing the relevant JTAG commands.
3881 @end itemize
3883 If you need some action after each JTAG reset which isn't actually
3884 specific to any TAP (since you can't yet trust the scan chain's
3885 contents to be accurate), you might:
3887 @example
3888 jtag configure CHIP.jrc -event post-reset @{
3889 echo "JTAG Reset done"
3890 ... non-scan jtag operations to be done after reset
3891 @}
3892 @end example
3895 @anchor{enablinganddisablingtaps}
3896 @section Enabling and Disabling TAPs
3897 @cindex JTAG Route Controller
3898 @cindex jrc
3900 In some systems, a @dfn{JTAG Route Controller} (JRC)
3901 is used to enable and/or disable specific JTAG TAPs.
3902 Many ARM-based chips from Texas Instruments include
3903 an ``ICEPick'' module, which is a JRC.
3904 Such chips include DaVinci and OMAP3 processors.
3906 A given TAP may not be visible until the JRC has been
3907 told to link it into the scan chain; and if the JRC
3908 has been told to unlink that TAP, it will no longer
3909 be visible.
3910 Such routers address problems that JTAG ``bypass mode''
3911 ignores, such as:
3913 @itemize
3914 @item The scan chain can only go as fast as its slowest TAP.
3915 @item Having many TAPs slows instruction scans, since all
3916 TAPs receive new instructions.
3917 @item TAPs in the scan chain must be powered up, which wastes
3918 power and prevents debugging some power management mechanisms.
3919 @end itemize
3921 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3922 as implied by the existence of JTAG routers.
3923 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3924 does include a kind of JTAG router functionality.
3926 @c (a) currently the event handlers don't seem to be able to
3927 @c fail in a way that could lead to no-change-of-state.
3929 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3930 shown below, and is implemented using TAP event handlers.
3931 So for example, when defining a TAP for a CPU connected to
3932 a JTAG router, your @file{target.cfg} file
3933 should define TAP event handlers using
3934 code that looks something like this:
3936 @example
3937 jtag configure CHIP.cpu -event tap-enable @{
3938 ... jtag operations using CHIP.jrc
3939 @}
3940 jtag configure CHIP.cpu -event tap-disable @{
3941 ... jtag operations using CHIP.jrc
3942 @}
3943 @end example
3945 Then you might want that CPU's TAP enabled almost all the time:
3947 @example
3948 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3949 @end example
3951 Note how that particular setup event handler declaration
3952 uses quotes to evaluate @code{$CHIP} when the event is configured.
3953 Using brackets @{ @} would cause it to be evaluated later,
3954 at runtime, when it might have a different value.
3956 @deffn Command {jtag tapdisable}
3957 If necessary, disables the tap
3958 by sending it a @option{tap-disable} event.
3959 Returns the string "1" if the tap
3960 specified by @var{} is enabled,
3961 and "0" if it is disabled.
3962 @end deffn
3964 @deffn Command {jtag tapenable}
3965 If necessary, enables the tap
3966 by sending it a @option{tap-enable} event.
3967 Returns the string "1" if the tap
3968 specified by @var{} is enabled,
3969 and "0" if it is disabled.
3970 @end deffn
3972 @deffn Command {jtag tapisenabled}
3973 Returns the string "1" if the tap
3974 specified by @var{} is enabled,
3975 and "0" if it is disabled.
3977 @quotation Note
3978 Humans will find the @command{scan_chain} command more helpful
3979 for querying the state of the JTAG taps.
3980 @end quotation
3981 @end deffn
3983 @anchor{autoprobing}
3984 @section Autoprobing
3985 @cindex autoprobe
3986 @cindex JTAG autoprobe
3988 TAP configuration is the first thing that needs to be done
3989 after interface and reset configuration. Sometimes it's
3990 hard finding out what TAPs exist, or how they are identified.
3991 Vendor documentation is not always easy to find and use.
3993 To help you get past such problems, OpenOCD has a limited
3994 @emph{autoprobing} ability to look at the scan chain, doing
3995 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3996 To use this mechanism, start the OpenOCD server with only data
3997 that configures your JTAG interface, and arranges to come up
3998 with a slow clock (many devices don't support fast JTAG clocks
3999 right when they come out of reset).
4001 For example, your @file{openocd.cfg} file might have:
4003 @example
4004 source [find interface/olimex-arm-usb-tiny-h.cfg]
4005 reset_config trst_and_srst
4006 jtag_rclk 8
4007 @end example
4009 When you start the server without any TAPs configured, it will
4010 attempt to autoconfigure the TAPs. There are two parts to this:
4012 @enumerate
4013 @item @emph{TAP discovery} ...
4014 After a JTAG reset (sometimes a system reset may be needed too),
4015 each TAP's data registers will hold the contents of either the
4016 IDCODE or BYPASS register.
4017 If JTAG communication is working, OpenOCD will see each TAP,
4018 and report what @option{-expected-id} to use with it.
4019 @item @emph{IR Length discovery} ...
4020 Unfortunately JTAG does not provide a reliable way to find out
4021 the value of the @option{-irlen} parameter to use with a TAP
4022 that is discovered.
4023 If OpenOCD can discover the length of a TAP's instruction
4024 register, it will report it.
4025 Otherwise you may need to consult vendor documentation, such
4026 as chip data sheets or BSDL files.
4027 @end enumerate
4029 In many cases your board will have a simple scan chain with just
4030 a single device. Here's what OpenOCD reported with one board
4031 that's a bit more complex:
4033 @example
4034 clock speed 8 kHz
4035 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4036 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4037 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4038 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4039 AUTO auto0.tap - use "... -irlen 4"
4040 AUTO auto1.tap - use "... -irlen 4"
4041 AUTO auto2.tap - use "... -irlen 6"
4042 no gdb ports allocated as no target has been specified
4043 @end example
4045 Given that information, you should be able to either find some existing
4046 config files to use, or create your own. If you create your own, you
4047 would configure from the bottom up: first a @file{target.cfg} file
4048 with these TAPs, any targets associated with them, and any on-chip
4049 resources; then a @file{board.cfg} with off-chip resources, clocking,
4050 and so forth.
4052 @node CPU Configuration
4053 @chapter CPU Configuration
4054 @cindex GDB target
4056 This chapter discusses how to set up GDB debug targets for CPUs.
4057 You can also access these targets without GDB
4058 (@pxref{Architecture and Core Commands},
4059 and @ref{targetstatehandling,,Target State handling}) and
4060 through various kinds of NAND and NOR flash commands.
4061 If you have multiple CPUs you can have multiple such targets.
4063 We'll start by looking at how to examine the targets you have,
4064 then look at how to add one more target and how to configure it.
4066 @section Target List
4067 @cindex target, current
4068 @cindex target, list
4070 All targets that have been set up are part of a list,
4071 where each member has a name.
4072 That name should normally be the same as the TAP name.
4073 You can display the list with the @command{targets}
4074 (plural!) command.
4075 This display often has only one CPU; here's what it might
4076 look like with more than one:
4077 @verbatim
4078 TargetName Type Endian TapName State
4079 -- ------------------ ---------- ------ ------------------ ------------
4080 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4081 1 MyTarget cortex_m little tap-disabled
4082 @end verbatim
4084 One member of that list is the @dfn{current target}, which
4085 is implicitly referenced by many commands.
4086 It's the one marked with a @code{*} near the target name.
4087 In particular, memory addresses often refer to the address
4088 space seen by that current target.
4089 Commands like @command{mdw} (memory display words)
4090 and @command{flash erase_address} (erase NOR flash blocks)
4091 are examples; and there are many more.
4093 Several commands let you examine the list of targets:
4095 @deffn Command {target count}
4096 @emph{Note: target numbers are deprecated; don't use them.
4097 They will be removed shortly after August 2010, including this command.
4098 Iterate target using @command{target names}, not by counting.}
4100 Returns the number of targets, @math{N}.
4101 The highest numbered target is @math{N - 1}.
4102 @example
4103 set c [target count]
4104 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
4105 # Assuming you have created this function
4106 print_target_details $x
4107 @}
4108 @end example
4109 @end deffn
4111 @deffn Command {target current}
4112 Returns the name of the current target.
4113 @end deffn
4115 @deffn Command {target names}
4116 Lists the names of all current targets in the list.
4117 @example
4118 foreach t [target names] @{
4119 puts [format "Target: %s\n" $t]
4120 @}
4121 @end example
4122 @end deffn
4124 @deffn Command {target number} number
4125 @emph{Note: target numbers are deprecated; don't use them.
4126 They will be removed shortly after August 2010, including this command.}
4128 The list of targets is numbered starting at zero.
4129 This command returns the name of the target at index @var{number}.
4130 @example
4131 set thename [target number $x]
4132 puts [format "Target %d is: %s\n" $x $thename]
4133 @end example
4134 @end deffn
4136 @c yep, "target list" would have been better.
4137 @c plus maybe "target setdefault".
4139 @deffn Command targets [name]
4140 @emph{Note: the name of this command is plural. Other target
4141 command names are singular.}
4143 With no parameter, this command displays a table of all known
4144 targets in a user friendly form.
4146 With a parameter, this command sets the current target to
4147 the given target with the given @var{name}; this is
4148 only relevant on boards which have more than one target.
4149 @end deffn
4151 @section Target CPU Types and Variants
4152 @cindex target type
4153 @cindex CPU type
4154 @cindex CPU variant
4156 Each target has a @dfn{CPU type}, as shown in the output of
4157 the @command{targets} command. You need to specify that type
4158 when calling @command{target create}.
4159 The CPU type indicates more than just the instruction set.
4160 It also indicates how that instruction set is implemented,
4161 what kind of debug support it integrates,
4162 whether it has an MMU (and if so, what kind),
4163 what core-specific commands may be available
4164 (@pxref{Architecture and Core Commands}),
4165 and more.
4167 For some CPU types, OpenOCD also defines @dfn{variants} which
4168 indicate differences that affect their handling.
4169 For example, a particular implementation bug might need to be
4170 worked around in some chip versions.
4172 It's easy to see what target types are supported,
4173 since there's a command to list them.
4174 However, there is currently no way to list what target variant