replace berlios url's with sourceforge url's
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * TFTP:: TFTP
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on:
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
94 @end menu
96 @node About
97 @unnumbered About
98 @cindex about
100 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
101 University of Applied Sciences Augsburg (@uref{}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
104 around the world.
106 @section What is OpenOCD?
107 @cindex TAP
108 @cindex JTAG
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
112 devices.
114 It does so with the assistance of a @dfn{debug adapter}, which is
115 a small hardware module which helps provide the right kind of
116 electrical signaling to the target being debugged. These are
117 required since the debug host (on which OpenOCD runs) won't
118 usually have native support for such signaling, or the connector
119 needed to hook up to the target.
121 Such debug adapters support one or more @dfn{transport} protocols,
122 each of which involves different electrical signaling (and uses
123 different messaging protocols on top of that signaling). There
124 are many types of debug adapter, and little uniformity in what
125 they are called. (There are also product naming differences.)
127 These adapters are sometimes packaged as discrete dongles, which
128 may generically be called @dfn{hardware interface dongles}.
129 Some development boards also integrate them directly, which may
130 let the development board can be directly connected to the debug
131 host over USB (and sometimes also to power it over USB).
133 For example, a @dfn{JTAG Adapter} supports JTAG
134 signaling, and is used to communicate
135 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
136 A @dfn{TAP} is a ``Test Access Port'', a module which processes
137 special instructions and data. TAPs are daisy-chained within and
138 between chips and boards. JTAG supports debugging and boundary
139 scan operations.
141 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
142 signaling to communicate with some newer ARM cores, as well as debug
143 adapters which support both JTAG and SWD transports. SWD only supports
144 debugging, whereas JTAG also supports boundary scan operations.
146 For some chips, there are also @dfn{Programming Adapters} supporting
147 special transports used only to write code to flash memory, without
148 support for on-chip debugging or boundary scan.
149 (At this writing, OpenOCD does not support such non-debug adapters.)
152 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
153 based, parallel port based, and other standalone boxes that run
154 OpenOCD internally. @xref{Debug Adapter Hardware}.
156 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
157 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
158 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
159 debugged via the GDB protocol.
161 @b{Flash Programing:} Flash writing is supported for external CFI
162 compatible NOR flashes (Intel and AMD/Spansion command set) and several
163 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
164 STM32x). Preliminary support for various NAND flash controllers
165 (LPC3180, Orion, S3C24xx, more) controller is included.
167 @section OpenOCD Web Site
169 The OpenOCD web site provides the latest public news from the community:
171 @uref{}
173 @section Latest User's Guide:
175 The user's guide you are now reading may not be the latest one
176 available. A version for more recent code may be available.
177 Its HTML form is published irregularly at:
179 @uref{}
181 PDF form is likewise published at:
183 @uref{}
185 @section OpenOCD User's Forum
187 There is an OpenOCD forum (phpBB) hosted by SparkFun,
188 which might be helpful to you. Note that if you want
189 anything to come to the attention of developers, you
190 should post it to the OpenOCD Developer Mailing List
191 instead of this forum.
193 @uref{}
196 @node Developers
197 @chapter OpenOCD Developer Resources
198 @cindex developers
200 If you are interested in improving the state of OpenOCD's debugging and
201 testing support, new contributions will be welcome. Motivated developers
202 can produce new target, flash or interface drivers, improve the
203 documentation, as well as more conventional bug fixes and enhancements.
205 The resources in this chapter are available for developers wishing to explore
206 or expand the OpenOCD source code.
208 @section OpenOCD GIT Repository
210 During the 0.3.x release cycle, OpenOCD switched from Subversion to
211 a GIT repository hosted at SourceForge. The repository URL is:
213 @uref{git://}
215 You may prefer to use a mirror and the HTTP protocol:
217 @uref{}
219 With standard GIT tools, use @command{git clone} to initialize
220 a local repository, and @command{git pull} to update it.
221 There are also gitweb pages letting you browse the repository
222 with a web browser, or download arbitrary snapshots without
223 needing a GIT client:
225 @uref{}
227 @uref{}
229 The @file{README} file contains the instructions for building the project
230 from the repository or a snapshot.
232 Developers that want to contribute patches to the OpenOCD system are
233 @b{strongly} encouraged to work against mainline.
234 Patches created against older versions may require additional
235 work from their submitter in order to be updated for newer releases.
237 @section Doxygen Developer Manual
239 During the 0.2.x release cycle, the OpenOCD project began
240 providing a Doxygen reference manual. This document contains more
241 technical information about the software internals, development
242 processes, and similar documentation:
244 @uref{}
246 This document is a work-in-progress, but contributions would be welcome
247 to fill in the gaps. All of the source files are provided in-tree,
248 listed in the Doxyfile configuration in the top of the source tree.
250 @section OpenOCD Developer Mailing List
252 The OpenOCD Developer Mailing List provides the primary means of
253 communication between developers:
255 @uref{}
257 Discuss and submit patches to this list.
258 The @file{PATCHES.txt} file contains basic information about how
259 to prepare patches.
261 @section OpenOCD Bug Database
263 During the 0.4.x release cycle the OpenOCD project team began
264 using Trac for its bug database:
266 @uref{}
269 @node Debug Adapter Hardware
270 @chapter Debug Adapter Hardware
271 @cindex dongles
272 @cindex FTDI
273 @cindex wiggler
274 @cindex zy1000
275 @cindex printer port
276 @cindex USB Adapter
277 @cindex RTCK
279 Defined: @b{dongle}: A small device that plugins into a computer and serves as
280 an adapter .... [snip]
282 In the OpenOCD case, this generally refers to @b{a small adapter} that
283 attaches to your computer via USB or the Parallel Printer Port. One
284 exception is the Zylin ZY1000, packaged as a small box you attach via
285 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
286 require any drivers to be installed on the developer PC. It also has
287 a built in web interface. It supports RTCK/RCLK or adaptive clocking
288 and has a built in relay to power cycle targets remotely.
291 @section Choosing a Dongle
293 There are several things you should keep in mind when choosing a dongle.
295 @enumerate
296 @item @b{Transport} Does it support the kind of communication that you need?
297 OpenOCD focusses mostly on JTAG. Your version may also support
298 other ways to communicate with target devices.
299 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
300 Does your dongle support it? You might need a level converter.
301 @item @b{Pinout} What pinout does your target board use?
302 Does your dongle support it? You may be able to use jumper
303 wires, or an "octopus" connector, to convert pinouts.
304 @item @b{Connection} Does your computer have the USB, printer, or
305 Ethernet port needed?
306 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
307 RTCK support? Also known as ``adaptive clocking''
308 @end enumerate
310 @section Stand alone Systems
312 @b{ZY1000} See: @url{} Technically, not a
313 dongle, but a standalone box. The ZY1000 has the advantage that it does
314 not require any drivers installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built in relay to power cycle targets remotely.
318 @section USB FT2232 Based
320 There are many USB JTAG dongles on the market, many of them are based
321 on a chip from ``Future Technology Devices International'' (FTDI)
322 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
323 See: @url{} for more information.
324 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
325 chips are starting to become available in JTAG adapters. (Adapters
326 using those high speed FT2232H chips may support adaptive clocking.)
328 The FT2232 chips are flexible enough to support some other
329 transport options, such as SWD or the SPI variants used to
330 program some chips. They have two communications channels,
331 and one can be used for a UART adapter at the same time the
332 other one is used to provide a debug adapter.
334 Also, some development boards integrate an FT2232 chip to serve as
335 a built-in low cost debug adapter and usb-to-serial solution.
337 @itemize @bullet
338 @item @b{usbjtag}
339 @* Link @url{}
340 @item @b{jtagkey}
341 @* See: @url{}
342 @item @b{jtagkey2}
343 @* See: @url{}
344 @item @b{oocdlink}
345 @* See: @url{} By Joern Kaipf
346 @item @b{signalyzer}
347 @* See: @url{}
348 @item @b{Stellaris Eval Boards}
349 @* See: @url{} - The Stellaris eval boards
350 bundle FT2232-based JTAG and SWD support, which can be used to debug
351 the Stellaris chips. Using separate JTAG adapters is optional.
352 These boards can also be used in a "pass through" mode as JTAG adapters
353 to other target boards, disabling the Stellaris chip.
354 @item @b{Luminary ICDI}
355 @* See: @url{} - Luminary In-Circuit Debug
356 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
357 Evaluation Kits. Like the non-detachable FT2232 support on the other
358 Stellaris eval boards, they can be used to debug other target boards.
359 @item @b{olimex-jtag}
360 @* See: @url{}
361 @item @b{flyswatter}
362 @* See: @url{}
363 @item @b{turtelizer2}
364 @* See:
365 @uref{, Turtelizer 2}, or
366 @url{}
367 @item @b{comstick}
368 @* Link: @url{}
369 @item @b{stm32stick}
370 @* Link @url{}
371 @item @b{axm0432_jtag}
372 @* Axiom AXM-0432 Link @url{}
373 @item @b{cortino}
374 @* Link @url{}
375 @end itemize
377 @section USB-JTAG / Altera USB-Blaster compatibles
379 These devices also show up as FTDI devices, but are not
380 protocol-compatible with the FT2232 devices. They are, however,
381 protocol-compatible among themselves. USB-JTAG devices typically consist
382 of a FT245 followed by a CPLD that understands a particular protocol,
383 or emulate this protocol using some other hardware.
385 They may appear under different USB VID/PID depending on the particular
386 product. The driver can be configured to search for any VID/PID pair
387 (see the section on driver commands).
389 @itemize
390 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
391 @* Link: @url{}
392 @item @b{Altera USB-Blaster}
393 @* Link: @url{}
394 @end itemize
396 @section USB JLINK based
397 There are several OEM versions of the Segger @b{JLINK} adapter. It is
398 an example of a micro controller based JTAG adapter, it uses an
399 AT91SAM764 internally.
401 @itemize @bullet
402 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
403 @* Link: @url{}
404 @item @b{SEGGER JLINK}
405 @* Link: @url{}
406 @item @b{IAR J-Link}
407 @* Link: @url{}
408 @end itemize
410 @section USB RLINK based
411 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
413 @itemize @bullet
414 @item @b{Raisonance RLink}
415 @* Link: @url{}
416 @item @b{STM32 Primer}
417 @* Link: @url{}
418 @item @b{STM32 Primer2}
419 @* Link: @url{}
420 @end itemize
422 @section USB Other
423 @itemize @bullet
424 @item @b{USBprog}
425 @* Link: @url{} - which uses an Atmel MEGA32 and a UBN9604
427 @item @b{USB - Presto}
428 @* Link: @url{}
430 @item @b{Versaloon-Link}
431 @* Link: @url{}
433 @item @b{ARM-JTAG-EW}
434 @* Link: @url{}
436 @item @b{Buspirate}
437 @* Link: @url{}
438 @end itemize
440 @section IBM PC Parallel Printer Port Based
442 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
443 and the MacGraigor Wiggler. There are many clones and variations of
444 these on the market.
446 Note that parallel ports are becoming much less common, so if you
447 have the choice you should probably avoid these adapters in favor
448 of USB-based ones.
450 @itemize @bullet
452 @item @b{Wiggler} - There are many clones of this.
453 @* Link: @url{}
455 @item @b{DLC5} - From XILINX - There are many clones of this
456 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
457 produced, PDF schematics are easily found and it is easy to make.
459 @item @b{Amontec - JTAG Accelerator}
460 @* Link: @url{}
462 @item @b{GW16402}
463 @* Link: @url{}
465 @item @b{Wiggler2}
466 @*@uref{,
467 Improved parallel-port wiggler-style JTAG adapter}
469 @item @b{Wiggler_ntrst_inverted}
470 @* Yet another variation - See the source code, src/jtag/parport.c
472 @item @b{old_amt_wiggler}
473 @* Unknown - probably not on the market today
475 @item @b{arm-jtag}
476 @* Link: Most likely @url{} [another wiggler clone]
478 @item @b{chameleon}
479 @* Link: @url{}
481 @item @b{Triton}
482 @* Unknown.
484 @item @b{Lattice}
485 @* ispDownload from Lattice Semiconductor
486 @url{}
488 @item @b{flashlink}
489 @* From ST Microsystems;
490 @uref{,
491 FlashLINK JTAG programing cable for PSD and uPSD}
493 @end itemize
495 @section Other...
496 @itemize @bullet
498 @item @b{ep93xx}
499 @* An EP93xx based Linux machine using the GPIO pins directly.
501 @item @b{at91rm9200}
502 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
504 @end itemize
506 @node About Jim-Tcl
507 @chapter About Jim-Tcl
508 @cindex Jim-Tcl
509 @cindex tcl
511 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
512 This programming language provides a simple and extensible
513 command interpreter.
515 All commands presented in this Guide are extensions to Jim-Tcl.
516 You can use them as simple commands, without needing to learn
517 much of anything about Tcl.
518 Alternatively, can write Tcl programs with them.
520 You can learn more about Jim at its website, @url{}.
521 There is an active and responsive community, get on the mailing list
522 if you have any questions. Jim-Tcl maintainers also lurk on the
523 OpenOCD mailing list.
525 @itemize @bullet
526 @item @b{Jim vs. Tcl}
527 @* Jim-Tcl is a stripped down version of the well known Tcl language,
528 which can be found here: @url{}. Jim-Tcl has far
529 fewer features. Jim-Tcl is several dozens of .C files and .H files and
530 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
531 4.2 MB .zip file containing 1540 files.
533 @item @b{Missing Features}
534 @* Our practice has been: Add/clone the real Tcl feature if/when
535 needed. We welcome Jim-Tcl improvements, not bloat. Also there
536 are a large number of optional Jim-Tcl features that are not
537 enabled in OpenOCD.
539 @item @b{Scripts}
540 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
541 command interpreter today is a mixture of (newer)
542 Jim-Tcl commands, and (older) the orginal command interpreter.
544 @item @b{Commands}
545 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
546 can type a Tcl for() loop, set variables, etc.
547 Some of the commands documented in this guide are implemented
548 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
550 @item @b{Historical Note}
551 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
552 before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
553 as a git submodule, which greatly simplified upgrading Jim Tcl
554 to benefit from new features and bugfixes in Jim Tcl.
556 @item @b{Need a crash course in Tcl?}
557 @*@xref{Tcl Crash Course}.
558 @end itemize
560 @node Running
561 @chapter Running
562 @cindex command line options
563 @cindex logfile
564 @cindex directory search
566 Properly installing OpenOCD sets up your operating system to grant it access
567 to the debug adapters. On Linux, this usually involves installing a file
568 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
569 complex and confusing driver configuration for every peripheral. Such issues
570 are unique to each operating system, and are not detailed in this User's Guide.
572 Then later you will invoke the OpenOCD server, with various options to
573 tell it how each debug session should work.
574 The @option{--help} option shows:
575 @verbatim
576 bash$ openocd --help
578 --help | -h display this help
579 --version | -v display OpenOCD version
580 --file | -f use configuration file <name>
581 --search | -s dir to search for config files and scripts
582 --debug | -d set debug level <0-3>
583 --log_output | -l redirect log output to file <name>
584 --command | -c run <command>
585 @end verbatim
587 If you don't give any @option{-f} or @option{-c} options,
588 OpenOCD tries to read the configuration file @file{openocd.cfg}.
589 To specify one or more different
590 configuration files, use @option{-f} options. For example:
592 @example
593 openocd -f config1.cfg -f config2.cfg -f config3.cfg
594 @end example
596 Configuration files and scripts are searched for in
597 @enumerate
598 @item the current directory,
599 @item any search dir specified on the command line using the @option{-s} option,
600 @item any search dir specified using the @command{add_script_search_dir} command,
601 @item @file{$HOME/.openocd} (not on Windows),
602 @item the site wide script library @file{$pkgdatadir/site} and
603 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
604 @end enumerate
605 The first found file with a matching file name will be used.
607 @quotation Note
608 Don't try to use configuration script names or paths which
609 include the "#" character. That character begins Tcl comments.
610 @end quotation
612 @section Simple setup, no customization
614 In the best case, you can use two scripts from one of the script
615 libraries, hook up your JTAG adapter, and start the server ... and
616 your JTAG setup will just work "out of the box". Always try to
617 start by reusing those scripts, but assume you'll need more
618 customization even if this works. @xref{OpenOCD Project Setup}.
620 If you find a script for your JTAG adapter, and for your board or
621 target, you may be able to hook up your JTAG adapter then start
622 the server like:
624 @example
625 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
626 @end example
628 You might also need to configure which reset signals are present,
629 using @option{-c 'reset_config trst_and_srst'} or something similar.
630 If all goes well you'll see output something like
632 @example
633 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
634 For bug reports, read
636 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
637 (mfg: 0x23b, part: 0xba00, ver: 0x3)
638 @end example
640 Seeing that "tap/device found" message, and no warnings, means
641 the JTAG communication is working. That's a key milestone, but
642 you'll probably need more project-specific setup.
644 @section What OpenOCD does as it starts
646 OpenOCD starts by processing the configuration commands provided
647 on the command line or, if there were no @option{-c command} or
648 @option{-f file.cfg} options given, in @file{openocd.cfg}.
649 @xref{Configuration Stage}.
650 At the end of the configuration stage it verifies the JTAG scan
651 chain defined using those commands; your configuration should
652 ensure that this always succeeds.
653 Normally, OpenOCD then starts running as a daemon.
654 Alternatively, commands may be used to terminate the configuration
655 stage early, perform work (such as updating some flash memory),
656 and then shut down without acting as a daemon.
658 Once OpenOCD starts running as a daemon, it waits for connections from
659 clients (Telnet, GDB, Other) and processes the commands issued through
660 those channels.
662 If you are having problems, you can enable internal debug messages via
663 the @option{-d} option.
665 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
666 @option{-c} command line switch.
668 To enable debug output (when reporting problems or working on OpenOCD
669 itself), use the @option{-d} command line switch. This sets the
670 @option{debug_level} to "3", outputting the most information,
671 including debug messages. The default setting is "2", outputting only
672 informational messages, warnings and errors. You can also change this
673 setting from within a telnet or gdb session using @command{debug_level
674 <n>} (@pxref{debug_level}).
676 You can redirect all output from the daemon to a file using the
677 @option{-l <logfile>} switch.
679 Note! OpenOCD will launch the GDB & telnet server even if it can not
680 establish a connection with the target. In general, it is possible for
681 the JTAG controller to be unresponsive until the target is set up
682 correctly via e.g. GDB monitor commands in a GDB init script.
684 @node OpenOCD Project Setup
685 @chapter OpenOCD Project Setup
687 To use OpenOCD with your development projects, you need to do more than
688 just connecting the JTAG adapter hardware (dongle) to your development board
689 and then starting the OpenOCD server.
690 You also need to configure that server so that it knows
691 about that adapter and board, and helps your work.
692 You may also want to connect OpenOCD to GDB, possibly
693 using Eclipse or some other GUI.
695 @section Hooking up the JTAG Adapter
697 Today's most common case is a dongle with a JTAG cable on one side
698 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
699 and a USB cable on the other.
700 Instead of USB, some cables use Ethernet;
701 older ones may use a PC parallel port, or even a serial port.
703 @enumerate
704 @item @emph{Start with power to your target board turned off},
705 and nothing connected to your JTAG adapter.
706 If you're particularly paranoid, unplug power to the board.
707 It's important to have the ground signal properly set up,
708 unless you are using a JTAG adapter which provides
709 galvanic isolation between the target board and the
710 debugging host.
712 @item @emph{Be sure it's the right kind of JTAG connector.}
713 If your dongle has a 20-pin ARM connector, you need some kind
714 of adapter (or octopus, see below) to hook it up to
715 boards using 14-pin or 10-pin connectors ... or to 20-pin
716 connectors which don't use ARM's pinout.
718 In the same vein, make sure the voltage levels are compatible.
719 Not all JTAG adapters have the level shifters needed to work
720 with 1.2 Volt boards.
722 @item @emph{Be certain the cable is properly oriented} or you might
723 damage your board. In most cases there are only two possible
724 ways to connect the cable.
725 Connect the JTAG cable from your adapter to the board.
726 Be sure it's firmly connected.
728 In the best case, the connector is keyed to physically
729 prevent you from inserting it wrong.
730 This is most often done using a slot on the board's male connector
731 housing, which must match a key on the JTAG cable's female connector.
732 If there's no housing, then you must look carefully and
733 make sure pin 1 on the cable hooks up to pin 1 on the board.
734 Ribbon cables are frequently all grey except for a wire on one
735 edge, which is red. The red wire is pin 1.
737 Sometimes dongles provide cables where one end is an ``octopus'' of
738 color coded single-wire connectors, instead of a connector block.
739 These are great when converting from one JTAG pinout to another,
740 but are tedious to set up.
741 Use these with connector pinout diagrams to help you match up the
742 adapter signals to the right board pins.
744 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
745 A USB, parallel, or serial port connector will go to the host which
746 you are using to run OpenOCD.
747 For Ethernet, consult the documentation and your network administrator.
749 For USB based JTAG adapters you have an easy sanity check at this point:
750 does the host operating system see the JTAG adapter? If that host is an
751 MS-Windows host, you'll need to install a driver before OpenOCD works.
753 @item @emph{Connect the adapter's power supply, if needed.}
754 This step is primarily for non-USB adapters,
755 but sometimes USB adapters need extra power.
757 @item @emph{Power up the target board.}
758 Unless you just let the magic smoke escape,
759 you're now ready to set up the OpenOCD server
760 so you can use JTAG to work with that board.
762 @end enumerate
764 Talk with the OpenOCD server using
765 telnet (@code{telnet localhost 4444} on many systems) or GDB.
766 @xref{GDB and OpenOCD}.
768 @section Project Directory
770 There are many ways you can configure OpenOCD and start it up.
772 A simple way to organize them all involves keeping a
773 single directory for your work with a given board.
774 When you start OpenOCD from that directory,
775 it searches there first for configuration files, scripts,
776 files accessed through semihosting,
777 and for code you upload to the target board.
778 It is also the natural place to write files,
779 such as log files and data you download from the board.
781 @section Configuration Basics
783 There are two basic ways of configuring OpenOCD, and
784 a variety of ways you can mix them.
785 Think of the difference as just being how you start the server:
787 @itemize
788 @item Many @option{-f file} or @option{-c command} options on the command line
789 @item No options, but a @dfn{user config file}
790 in the current directory named @file{openocd.cfg}
791 @end itemize
793 Here is an example @file{openocd.cfg} file for a setup
794 using a Signalyzer FT2232-based JTAG adapter to talk to
795 a board with an Atmel AT91SAM7X256 microcontroller:
797 @example
798 source [find interface/signalyzer.cfg]
800 # GDB can also flash my flash!
801 gdb_memory_map enable
802 gdb_flash_program enable
804 source [find target/sam7x256.cfg]
805 @end example
807 Here is the command line equivalent of that configuration:
809 @example
810 openocd -f interface/signalyzer.cfg \
811 -c "gdb_memory_map enable" \
812 -c "gdb_flash_program enable" \
813 -f target/sam7x256.cfg
814 @end example
816 You could wrap such long command lines in shell scripts,
817 each supporting a different development task.
818 One might re-flash the board with a specific firmware version.
819 Another might set up a particular debugging or run-time environment.
821 @quotation Important
822 At this writing (October 2009) the command line method has
823 problems with how it treats variables.
824 For example, after @option{-c "set VAR value"}, or doing the
825 same in a script, the variable @var{VAR} will have no value
826 that can be tested in a later script.
827 @end quotation
829 Here we will focus on the simpler solution: one user config
830 file, including basic configuration plus any TCL procedures
831 to simplify your work.
833 @section User Config Files
834 @cindex config file, user
835 @cindex user config file
836 @cindex config file, overview
838 A user configuration file ties together all the parts of a project
839 in one place.
840 One of the following will match your situation best:
842 @itemize
843 @item Ideally almost everything comes from configuration files
844 provided by someone else.
845 For example, OpenOCD distributes a @file{scripts} directory
846 (probably in @file{/usr/share/openocd/scripts} on Linux).
847 Board and tool vendors can provide these too, as can individual
848 user sites; the @option{-s} command line option lets you say
849 where to find these files. (@xref{Running}.)
850 The AT91SAM7X256 example above works this way.
852 Three main types of non-user configuration file each have their
853 own subdirectory in the @file{scripts} directory:
855 @enumerate
856 @item @b{interface} -- one for each different debug adapter;
857 @item @b{board} -- one for each different board
858 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
859 @end enumerate
861 Best case: include just two files, and they handle everything else.
862 The first is an interface config file.
863 The second is board-specific, and it sets up the JTAG TAPs and
864 their GDB targets (by deferring to some @file{target.cfg} file),
865 declares all flash memory, and leaves you nothing to do except
866 meet your deadline:
868 @example
869 source [find interface/olimex-jtag-tiny.cfg]
870 source [find board/csb337.cfg]
871 @end example
873 Boards with a single microcontroller often won't need more
874 than the target config file, as in the AT91SAM7X256 example.
875 That's because there is no external memory (flash, DDR RAM), and
876 the board differences are encapsulated by application code.
878 @item Maybe you don't know yet what your board looks like to JTAG.
879 Once you know the @file{interface.cfg} file to use, you may
880 need help from OpenOCD to discover what's on the board.
881 Once you find the JTAG TAPs, you can just search for appropriate
882 target and board
883 configuration files ... or write your own, from the bottom up.
884 @xref{Autoprobing}.
886 @item You can often reuse some standard config files but
887 need to write a few new ones, probably a @file{board.cfg} file.
888 You will be using commands described later in this User's Guide,
889 and working with the guidelines in the next chapter.
891 For example, there may be configuration files for your JTAG adapter
892 and target chip, but you need a new board-specific config file
893 giving access to your particular flash chips.
894 Or you might need to write another target chip configuration file
895 for a new chip built around the Cortex M3 core.
897 @quotation Note
898 When you write new configuration files, please submit
899 them for inclusion in the next OpenOCD release.
900 For example, a @file{board/newboard.cfg} file will help the
901 next users of that board, and a @file{target/newcpu.cfg}
902 will help support users of any board using that chip.
903 @end quotation
905 @item
906 You may may need to write some C code.
907 It may be as simple as a supporting a new ft2232 or parport
908 based adapter; a bit more involved, like a NAND or NOR flash
909 controller driver; or a big piece of work like supporting
910 a new chip architecture.
911 @end itemize
913 Reuse the existing config files when you can.
914 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
915 You may find a board configuration that's a good example to follow.
917 When you write config files, separate the reusable parts
918 (things every user of that interface, chip, or board needs)
919 from ones specific to your environment and debugging approach.
920 @itemize
922 @item
923 For example, a @code{gdb-attach} event handler that invokes
924 the @command{reset init} command will interfere with debugging
925 early boot code, which performs some of the same actions
926 that the @code{reset-init} event handler does.
928 @item
929 Likewise, the @command{arm9 vector_catch} command (or
930 @cindex vector_catch
931 its siblings @command{xscale vector_catch}
932 and @command{cortex_m3 vector_catch}) can be a timesaver
933 during some debug sessions, but don't make everyone use that either.
934 Keep those kinds of debugging aids in your user config file,
935 along with messaging and tracing setup.
936 (@xref{Software Debug Messages and Tracing}.)
938 @item
939 You might need to override some defaults.
940 For example, you might need to move, shrink, or back up the target's
941 work area if your application needs much SRAM.
943 @item
944 TCP/IP port configuration is another example of something which
945 is environment-specific, and should only appear in
946 a user config file. @xref{TCP/IP Ports}.
947 @end itemize
949 @section Project-Specific Utilities
951 A few project-specific utility
952 routines may well speed up your work.
953 Write them, and keep them in your project's user config file.
955 For example, if you are making a boot loader work on a
956 board, it's nice to be able to debug the ``after it's
957 loaded to RAM'' parts separately from the finicky early
958 code which sets up the DDR RAM controller and clocks.
959 A script like this one, or a more GDB-aware sibling,
960 may help:
962 @example
963 proc ramboot @{ @} @{
964 # Reset, running the target's "reset-init" scripts
965 # to initialize clocks and the DDR RAM controller.
966 # Leave the CPU halted.
967 reset init
969 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
970 load_image u-boot.bin 0x20000000
972 # Start running.
973 resume 0x20000000
974 @}
975 @end example
977 Then once that code is working you will need to make it
978 boot from NOR flash; a different utility would help.
979 Alternatively, some developers write to flash using GDB.
980 (You might use a similar script if you're working with a flash
981 based microcontroller application instead of a boot loader.)
983 @example
984 proc newboot @{ @} @{
985 # Reset, leaving the CPU halted. The "reset-init" event
986 # proc gives faster access to the CPU and to NOR flash;
987 # "reset halt" would be slower.
988 reset init
990 # Write standard version of U-Boot into the first two
991 # sectors of NOR flash ... the standard version should
992 # do the same lowlevel init as "reset-init".
993 flash protect 0 0 1 off
994 flash erase_sector 0 0 1
995 flash write_bank 0 u-boot.bin 0x0
996 flash protect 0 0 1 on
998 # Reboot from scratch using that new boot loader.
999 reset run
1000 @}
1001 @end example
1003 You may need more complicated utility procedures when booting
1004 from NAND.
1005 That often involves an extra bootloader stage,
1006 running from on-chip SRAM to perform DDR RAM setup so it can load
1007 the main bootloader code (which won't fit into that SRAM).
1009 Other helper scripts might be used to write production system images,
1010 involving considerably more than just a three stage bootloader.
1012 @section Target Software Changes
1014 Sometimes you may want to make some small changes to the software
1015 you're developing, to help make JTAG debugging work better.
1016 For example, in C or assembly language code you might
1017 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1018 handling issues like:
1020 @itemize @bullet
1022 @item @b{Watchdog Timers}...
1023 Watchog timers are typically used to automatically reset systems if
1024 some application task doesn't periodically reset the timer. (The
1025 assumption is that the system has locked up if the task can't run.)
1026 When a JTAG debugger halts the system, that task won't be able to run
1027 and reset the timer ... potentially causing resets in the middle of
1028 your debug sessions.
1030 It's rarely a good idea to disable such watchdogs, since their usage
1031 needs to be debugged just like all other parts of your firmware.
1032 That might however be your only option.
1034 Look instead for chip-specific ways to stop the watchdog from counting
1035 while the system is in a debug halt state. It may be simplest to set
1036 that non-counting mode in your debugger startup scripts. You may however
1037 need a different approach when, for example, a motor could be physically
1038 damaged by firmware remaining inactive in a debug halt state. That might
1039 involve a type of firmware mode where that "non-counting" mode is disabled
1040 at the beginning then re-enabled at the end; a watchdog reset might fire
1041 and complicate the debug session, but hardware (or people) would be
1042 protected.@footnote{Note that many systems support a "monitor mode" debug
1043 that is a somewhat cleaner way to address such issues. You can think of
1044 it as only halting part of the system, maybe just one task,
1045 instead of the whole thing.
1046 At this writing, January 2010, OpenOCD based debugging does not support
1047 monitor mode debug, only "halt mode" debug.}
1049 @item @b{ARM Semihosting}...
1050 @cindex ARM semihosting
1051 When linked with a special runtime library provided with many
1052 toolchains@footnote{See chapter 8 "Semihosting" in
1053 @uref{,
1054 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1055 The CodeSourcery EABI toolchain also includes a semihosting library.},
1056 your target code can use I/O facilities on the debug host. That library
1057 provides a small set of system calls which are handled by OpenOCD.
1058 It can let the debugger provide your system console and a file system,
1059 helping with early debugging or providing a more capable environment
1060 for sometimes-complex tasks like installing system firmware onto
1061 NAND or SPI flash.
1063 @item @b{ARM Wait-For-Interrupt}...
1064 Many ARM chips synchronize the JTAG clock using the core clock.
1065 Low power states which stop that core clock thus prevent JTAG access.
1066 Idle loops in tasking environments often enter those low power states
1067 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1069 You may want to @emph{disable that instruction} in source code,
1070 or otherwise prevent using that state,
1071 to ensure you can get JTAG access at any time.@footnote{As a more
1072 polite alternative, some processors have special debug-oriented
1073 registers which can be used to change various features including
1074 how the low power states are clocked while debugging.
1075 The STM32 DBGMCU_CR register is an example; at the cost of extra
1076 power consumption, JTAG can be used during low power states.}
1077 For example, the OpenOCD @command{halt} command may not
1078 work for an idle processor otherwise.
1080 @item @b{Delay after reset}...
1081 Not all chips have good support for debugger access
1082 right after reset; many LPC2xxx chips have issues here.
1083 Similarly, applications that reconfigure pins used for
1084 JTAG access as they start will also block debugger access.
1086 To work with boards like this, @emph{enable a short delay loop}
1087 the first thing after reset, before "real" startup activities.
1088 For example, one second's delay is usually more than enough
1089 time for a JTAG debugger to attach, so that
1090 early code execution can be debugged
1091 or firmware can be replaced.
1093 @item @b{Debug Communications Channel (DCC)}...
1094 Some processors include mechanisms to send messages over JTAG.
1095 Many ARM cores support these, as do some cores from other vendors.
1096 (OpenOCD may be able to use this DCC internally, speeding up some
1097 operations like writing to memory.)
1099 Your application may want to deliver various debugging messages
1100 over JTAG, by @emph{linking with a small library of code}
1101 provided with OpenOCD and using the utilities there to send
1102 various kinds of message.
1103 @xref{Software Debug Messages and Tracing}.
1105 @end itemize
1107 @section Target Hardware Setup
1109 Chip vendors often provide software development boards which
1110 are highly configurable, so that they can support all options
1111 that product boards may require. @emph{Make sure that any
1112 jumpers or switches match the system configuration you are
1113 working with.}
1115 Common issues include:
1117 @itemize @bullet
1119 @item @b{JTAG setup} ...
1120 Boards may support more than one JTAG configuration.
1121 Examples include jumpers controlling pullups versus pulldowns
1122 on the nTRST and/or nSRST signals, and choice of connectors
1123 (e.g. which of two headers on the base board,
1124 or one from a daughtercard).
1125 For some Texas Instruments boards, you may need to jumper the
1126 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1128 @item @b{Boot Modes} ...
1129 Complex chips often support multiple boot modes, controlled
1130 by external jumpers. Make sure this is set up correctly.
1131 For example many i.MX boards from NXP need to be jumpered
1132 to "ATX mode" to start booting using the on-chip ROM, when
1133 using second stage bootloader code stored in a NAND flash chip.
1135 Such explicit configuration is common, and not limited to
1136 booting from NAND. You might also need to set jumpers to
1137 start booting using code loaded from an MMC/SD card; external
1138 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1139 flash; some external host; or various other sources.
1142 @item @b{Memory Addressing} ...
1143 Boards which support multiple boot modes may also have jumpers
1144 to configure memory addressing. One board, for example, jumpers
1145 external chipselect 0 (used for booting) to address either
1146 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1147 or NAND flash. When it's jumpered to address NAND flash, that
1148 board must also be told to start booting from on-chip ROM.
1150 Your @file{board.cfg} file may also need to be told this jumper
1151 configuration, so that it can know whether to declare NOR flash
1152 using @command{flash bank} or instead declare NAND flash with
1153 @command{nand device}; and likewise which probe to perform in
1154 its @code{reset-init} handler.
1156 A closely related issue is bus width. Jumpers might need to
1157 distinguish between 8 bit or 16 bit bus access for the flash
1158 used to start booting.
1160 @item @b{Peripheral Access} ...
1161 Development boards generally provide access to every peripheral
1162 on the chip, sometimes in multiple modes (such as by providing
1163 multiple audio codec chips).
1164 This interacts with software
1165 configuration of pin multiplexing, where for example a
1166 given pin may be routed either to the MMC/SD controller
1167 or the GPIO controller. It also often interacts with
1168 configuration jumpers. One jumper may be used to route
1169 signals to an MMC/SD card slot or an expansion bus (which
1170 might in turn affect booting); others might control which
1171 audio or video codecs are used.
1173 @end itemize
1175 Plus you should of course have @code{reset-init} event handlers
1176 which set up the hardware to match that jumper configuration.
1177 That includes in particular any oscillator or PLL used to clock
1178 the CPU, and any memory controllers needed to access external
1179 memory and peripherals. Without such handlers, you won't be
1180 able to access those resources without working target firmware
1181 which can do that setup ... this can be awkward when you're
1182 trying to debug that target firmware. Even if there's a ROM
1183 bootloader which handles a few issues, it rarely provides full
1184 access to all board-specific capabilities.
1187 @node Config File Guidelines
1188 @chapter Config File Guidelines
1190 This chapter is aimed at any user who needs to write a config file,
1191 including developers and integrators of OpenOCD and any user who
1192 needs to get a new board working smoothly.
1193 It provides guidelines for creating those files.
1195 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1196 with files including the ones listed here.
1197 Use them as-is where you can; or as models for new files.
1198 @itemize @bullet
1199 @item @file{interface} ...
1200 These are for debug adapters.
1201 Files that configure JTAG adapters go here.
1202 @example
1203 $ ls interface
1204 arm-jtag-ew.cfg hitex_str9-comstick.cfg oocdlink.cfg
1205 arm-usb-ocd.cfg icebear.cfg openocd-usb.cfg
1206 at91rm9200.cfg jlink.cfg parport.cfg
1207 axm0432.cfg jtagkey2.cfg parport_dlc5.cfg
1208 calao-usb-a9260-c01.cfg jtagkey.cfg rlink.cfg
1209 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg sheevaplug.cfg
1210 calao-usb-a9260.cfg luminary.cfg signalyzer.cfg
1211 chameleon.cfg luminary-icdi.cfg stm32-stick.cfg
1212 cortino.cfg luminary-lm3s811.cfg turtelizer2.cfg
1213 dummy.cfg olimex-arm-usb-ocd.cfg usbprog.cfg
1214 flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
1215 $
1216 @end example
1217 @item @file{board} ...
1218 think Circuit Board, PWA, PCB, they go by many names. Board files
1219 contain initialization items that are specific to a board.
1220 They reuse target configuration files, since the same
1221 microprocessor chips are used on many boards,
1222 but support for external parts varies widely. For
1223 example, the SDRAM initialization sequence for the board, or the type
1224 of external flash and what address it uses. Any initialization
1225 sequence to enable that external flash or SDRAM should be found in the
1226 board file. Boards may also contain multiple targets: two CPUs; or
1227 a CPU and an FPGA.
1228 @example
1229 $ ls board
1230 arm_evaluator7t.cfg keil_mcb1700.cfg
1231 at91rm9200-dk.cfg keil_mcb2140.cfg
1232 at91sam9g20-ek.cfg linksys_nslu2.cfg
1233 atmel_at91sam7s-ek.cfg logicpd_imx27.cfg
1234 atmel_at91sam9260-ek.cfg mini2440.cfg
1235 atmel_sam3u_ek.cfg olimex_LPC2378STK.cfg
1236 crossbow_tech_imote2.cfg olimex_lpc_h2148.cfg
1237 csb337.cfg olimex_sam7_ex256.cfg
1238 csb732.cfg olimex_sam9_l9260.cfg
1239 digi_connectcore_wi-9c.cfg olimex_stm32_h103.cfg
1240 dm355evm.cfg omap2420_h4.cfg
1241 dm365evm.cfg osk5912.cfg
1242 dm6446evm.cfg pic-p32mx.cfg
1243 eir.cfg propox_mmnet1001.cfg
1244 ek-lm3s1968.cfg pxa255_sst.cfg
1245 ek-lm3s3748.cfg sheevaplug.cfg
1246 ek-lm3s811.cfg stm3210e_eval.cfg
1247 ek-lm3s9b9x.cfg stm32f10x_128k_eval.cfg
1248 hammer.cfg str910-eval.cfg
1249 hitex_lpc2929.cfg telo.cfg
1250 hitex_stm32-performancestick.cfg ti_beagleboard.cfg
1251 hitex_str9-comstick.cfg topas910.cfg
1252 iar_str912_sk.cfg topasa900.cfg
1253 imx27ads.cfg unknown_at91sam9260.cfg
1254 imx27lnst.cfg x300t.cfg
1255 imx31pdk.cfg zy1000.cfg
1256 $
1257 @end example
1258 @item @file{target} ...
1259 think chip. The ``target'' directory represents the JTAG TAPs
1260 on a chip
1261 which OpenOCD should control, not a board. Two common types of targets
1262 are ARM chips and FPGA or CPLD chips.
1263 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1264 the target config file defines all of them.
1265 @example
1266 $ ls target
1267 aduc702x.cfg imx27.cfg pxa255.cfg
1268 ar71xx.cfg imx31.cfg pxa270.cfg
1269 at91eb40a.cfg imx35.cfg readme.txt
1270 at91r40008.cfg is5114.cfg sam7se512.cfg
1271 at91rm9200.cfg ixp42x.cfg sam7x256.cfg
1272 at91sam3u1c.cfg lm3s1968.cfg samsung_s3c2410.cfg
1273 at91sam3u1e.cfg lm3s3748.cfg samsung_s3c2440.cfg
1274 at91sam3u2c.cfg lm3s6965.cfg samsung_s3c2450.cfg
1275 at91sam3u2e.cfg lm3s811.cfg samsung_s3c4510.cfg
1276 at91sam3u4c.cfg lm3s9b9x.cfg samsung_s3c6410.cfg
1277 at91sam3u4e.cfg lpc1768.cfg sharp_lh79532.cfg
1278 at91sam3uXX.cfg lpc2103.cfg smdk6410.cfg
1279 at91sam7sx.cfg lpc2124.cfg smp8634.cfg
1280 at91sam9260.cfg lpc2129.cfg stm32f1x.cfg
1281 c100.cfg lpc2148.cfg str710.cfg
1282 c100config.tcl lpc2294.cfg str730.cfg
1283 c100helper.tcl lpc2378.cfg str750.cfg
1284 c100regs.tcl lpc2478.cfg str912.cfg
1285 cs351x.cfg lpc2900.cfg telo.cfg
1286 davinci.cfg mega128.cfg ti_dm355.cfg
1287 dragonite.cfg netx500.cfg ti_dm365.cfg
1288 epc9301.cfg omap2420.cfg ti_dm6446.cfg
1289 feroceon.cfg omap3530.cfg tmpa900.cfg
1290 icepick.cfg omap5912.cfg tmpa910.cfg
1291 imx21.cfg pic32mx.cfg xba_revA3.cfg
1292 $
1293 @end example
1294 @item @emph{more} ... browse for other library files which may be useful.
1295 For example, there are various generic and CPU-specific utilities.
1296 @end itemize
1298 The @file{openocd.cfg} user config
1299 file may override features in any of the above files by
1300 setting variables before sourcing the target file, or by adding
1301 commands specific to their situation.
1303 @section Interface Config Files
1305 The user config file
1306 should be able to source one of these files with a command like this:
1308 @example
1309 source [find interface/FOOBAR.cfg]
1310 @end example
1312 A preconfigured interface file should exist for every debug adapter
1313 in use today with OpenOCD.
1314 That said, perhaps some of these config files
1315 have only been used by the developer who created it.
1317 A separate chapter gives information about how to set these up.
1318 @xref{Debug Adapter Configuration}.
1319 Read the OpenOCD source code (and Developer's GUide)
1320 if you have a new kind of hardware interface
1321 and need to provide a driver for it.
1323 @section Board Config Files
1324 @cindex config file, board
1325 @cindex board config file
1327 The user config file
1328 should be able to source one of these files with a command like this:
1330 @example
1331 source [find board/FOOBAR.cfg]
1332 @end example
1334 The point of a board config file is to package everything
1335 about a given board that user config files need to know.
1336 In summary the board files should contain (if present)
1338 @enumerate
1339 @item One or more @command{source [target/...cfg]} statements
1340 @item NOR flash configuration (@pxref{NOR Configuration})
1341 @item NAND flash configuration (@pxref{NAND Configuration})
1342 @item Target @code{reset} handlers for SDRAM and I/O configuration
1343 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1344 @item All things that are not ``inside a chip''
1345 @end enumerate
1347 Generic things inside target chips belong in target config files,
1348 not board config files. So for example a @code{reset-init} event
1349 handler should know board-specific oscillator and PLL parameters,
1350 which it passes to target-specific utility code.
1352 The most complex task of a board config file is creating such a
1353 @code{reset-init} event handler.
1354 Define those handlers last, after you verify the rest of the board
1355 configuration works.
1357 @subsection Communication Between Config files
1359 In addition to target-specific utility code, another way that
1360 board and target config files communicate is by following a
1361 convention on how to use certain variables.
1363 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1364 Thus the rule we follow in OpenOCD is this: Variables that begin with
1365 a leading underscore are temporary in nature, and can be modified and
1366 used at will within a target configuration file.
1368 Complex board config files can do the things like this,
1369 for a board with three chips:
1371 @example
1372 # Chip #1: PXA270 for network side, big endian
1373 set CHIPNAME network
1374 set ENDIAN big
1375 source [find target/pxa270.cfg]
1376 # on return: _TARGETNAME = network.cpu
1377 # other commands can refer to the "network.cpu" target.
1378 $_TARGETNAME configure .... events for this CPU..
1380 # Chip #2: PXA270 for video side, little endian
1381 set CHIPNAME video
1382 set ENDIAN little
1383 source [find target/pxa270.cfg]
1384 # on return: _TARGETNAME = video.cpu
1385 # other commands can refer to the "video.cpu" target.
1386 $_TARGETNAME configure .... events for this CPU..
1388 # Chip #3: Xilinx FPGA for glue logic
1389 set CHIPNAME xilinx
1390 unset ENDIAN
1391 source [find target/spartan3.cfg]
1392 @end example
1394 That example is oversimplified because it doesn't show any flash memory,
1395 or the @code{reset-init} event handlers to initialize external DRAM
1396 or (assuming it needs it) load a configuration into the FPGA.
1397 Such features are usually needed for low-level work with many boards,
1398 where ``low level'' implies that the board initialization software may
1399 not be working. (That's a common reason to need JTAG tools. Another
1400 is to enable working with microcontroller-based systems, which often
1401 have no debugging support except a JTAG connector.)
1403 Target config files may also export utility functions to board and user
1404 config files. Such functions should use name prefixes, to help avoid
1405 naming collisions.
1407 Board files could also accept input variables from user config files.
1408 For example, there might be a @code{J4_JUMPER} setting used to identify
1409 what kind of flash memory a development board is using, or how to set
1410 up other clocks and peripherals.
1412 @subsection Variable Naming Convention
1413 @cindex variable names
1415 Most boards have only one instance of a chip.
1416 However, it should be easy to create a board with more than
1417 one such chip (as shown above).
1418 Accordingly, we encourage these conventions for naming
1419 variables associated with different @file{target.cfg} files,
1420 to promote consistency and
1421 so that board files can override target defaults.
1423 Inputs to target config files include:
1425 @itemize @bullet
1426 @item @code{CHIPNAME} ...
1427 This gives a name to the overall chip, and is used as part of
1428 tap identifier dotted names.
1429 While the default is normally provided by the chip manufacturer,
1430 board files may need to distinguish between instances of a chip.
1431 @item @code{ENDIAN} ...
1432 By default @option{little} - although chips may hard-wire @option{big}.
1433 Chips that can't change endianness don't need to use this variable.
1434 @item @code{CPUTAPID} ...
1435 When OpenOCD examines the JTAG chain, it can be told verify the
1436 chips against the JTAG IDCODE register.
1437 The target file will hold one or more defaults, but sometimes the
1438 chip in a board will use a different ID (perhaps a newer revision).
1439 @end itemize
1441 Outputs from target config files include:
1443 @itemize @bullet
1444 @item @code{_TARGETNAME} ...
1445 By convention, this variable is created by the target configuration
1446 script. The board configuration file may make use of this variable to
1447 configure things like a ``reset init'' script, or other things
1448 specific to that board and that target.
1449 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1450 @code{_TARGETNAME1}, ... etc.
1451 @end itemize
1453 @subsection The reset-init Event Handler
1454 @cindex event, reset-init
1455 @cindex reset-init handler
1457 Board config files run in the OpenOCD configuration stage;
1458 they can't use TAPs or targets, since they haven't been
1459 fully set up yet.
1460 This means you can't write memory or access chip registers;
1461 you can't even verify that a flash chip is present.
1462 That's done later in event handlers, of which the target @code{reset-init}
1463 handler is one of the most important.
1465 Except on microcontrollers, the basic job of @code{reset-init} event
1466 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1467 Microcontrollers rarely use boot loaders; they run right out of their
1468 on-chip flash and SRAM memory. But they may want to use one of these
1469 handlers too, if just for developer convenience.
1471 @quotation Note
1472 Because this is so very board-specific, and chip-specific, no examples
1473 are included here.
1474 Instead, look at the board config files distributed with OpenOCD.
1475 If you have a boot loader, its source code will help; so will
1476 configuration files for other JTAG tools
1477 (@pxref{Translating Configuration Files}).
1478 @end quotation
1480 Some of this code could probably be shared between different boards.
1481 For example, setting up a DRAM controller often doesn't differ by
1482 much except the bus width (16 bits or 32?) and memory timings, so a
1483 reusable TCL procedure loaded by the @file{target.cfg} file might take
1484 those as parameters.
1485 Similarly with oscillator, PLL, and clock setup;
1486 and disabling the watchdog.
1487 Structure the code cleanly, and provide comments to help
1488 the next developer doing such work.
1489 (@emph{You might be that next person} trying to reuse init code!)
1491 The last thing normally done in a @code{reset-init} handler is probing
1492 whatever flash memory was configured. For most chips that needs to be
1493 done while the associated target is halted, either because JTAG memory
1494 access uses the CPU or to prevent conflicting CPU access.
1496 @subsection JTAG Clock Rate
1498 Before your @code{reset-init} handler has set up
1499 the PLLs and clocking, you may need to run with
1500 a low JTAG clock rate.
1501 @xref{JTAG Speed}.
1502 Then you'd increase that rate after your handler has
1503 made it possible to use the faster JTAG clock.
1504 When the initial low speed is board-specific, for example
1505 because it depends on a board-specific oscillator speed, then
1506 you should probably set it up in the board config file;
1507 if it's target-specific, it belongs in the target config file.
1509 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1510 @uref{} gives details.}
1511 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1512 Consult chip documentation to determine the peak JTAG clock rate,
1513 which might be less than that.
1515 @quotation Warning
1516 On most ARMs, JTAG clock detection is coupled to the core clock, so
1517 software using a @option{wait for interrupt} operation blocks JTAG access.
1518 Adaptive clocking provides a partial workaround, but a more complete
1519 solution just avoids using that instruction with JTAG debuggers.
1520 @end quotation
1522 If both the chip and the board support adaptive clocking,
1523 use the @command{jtag_rclk}
1524 command, in case your board is used with JTAG adapter which
1525 also supports it. Otherwise use @command{adapter_khz}.
1526 Set the slow rate at the beginning of the reset sequence,
1527 and the faster rate as soon as the clocks are at full speed.
1529 @section Target Config Files
1530 @cindex config file, target
1531 @cindex target config file
1533 Board config files communicate with target config files using
1534 naming conventions as described above, and may source one or
1535 more target config files like this:
1537 @example
1538 source [find target/FOOBAR.cfg]
1539 @end example
1541 The point of a target config file is to package everything
1542 about a given chip that board config files need to know.
1543 In summary the target files should contain
1545 @enumerate
1546 @item Set defaults
1547 @item Add TAPs to the scan chain
1548 @item Add CPU targets (includes GDB support)
1549 @item CPU/Chip/CPU-Core specific features
1550 @item On-Chip flash
1551 @end enumerate
1553 As a rule of thumb, a target file sets up only one chip.
1554 For a microcontroller, that will often include a single TAP,
1555 which is a CPU needing a GDB target, and its on-chip flash.
1557 More complex chips may include multiple TAPs, and the target
1558 config file may need to define them all before OpenOCD
1559 can talk to the chip.
1560 For example, some phone chips have JTAG scan chains that include
1561 an ARM core for operating system use, a DSP,
1562 another ARM core embedded in an image processing engine,
1563 and other processing engines.
1565 @subsection Default Value Boiler Plate Code
1567 All target configuration files should start with code like this,
1568 letting board config files express environment-specific
1569 differences in how things should be set up.
1571 @example
1572 # Boards may override chip names, perhaps based on role,
1573 # but the default should match what the vendor uses
1574 if @{ [info exists CHIPNAME] @} @{
1576 @} else @{
1577 set _CHIPNAME sam7x256
1578 @}
1580 # ONLY use ENDIAN with targets that can change it.
1581 if @{ [info exists ENDIAN] @} @{
1582 set _ENDIAN $ENDIAN
1583 @} else @{
1584 set _ENDIAN little
1585 @}
1587 # TAP identifiers may change as chips mature, for example with
1588 # new revision fields (the "3" here). Pick a good default; you
1589 # can pass several such identifiers to the "jtag newtap" command.
1590 if @{ [info exists CPUTAPID ] @} @{
1592 @} else @{
1593 set _CPUTAPID 0x3f0f0f0f
1594 @}
1595 @end example
1596 @c but 0x3f0f0f0f is for an str73x part ...
1598 @emph{Remember:} Board config files may include multiple target
1599 config files, or the same target file multiple times
1600 (changing at least @code{CHIPNAME}).
1602 Likewise, the target configuration file should define
1603 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1604 use it later on when defining debug targets:
1606 @example
1608 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1609 @end example
1611 @subsection Adding TAPs to the Scan Chain
1612 After the ``defaults'' are set up,
1613 add the TAPs on each chip to the JTAG scan chain.
1614 @xref{TAP Declaration}, and the naming convention
1615 for taps.
1617 In the simplest case the chip has only one TAP,
1618 probably for a CPU or FPGA.
1619 The config file for the Atmel AT91SAM7X256
1620 looks (in part) like this:
1622 @example
1623 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1624 @end example
1626 A board with two such at91sam7 chips would be able
1627 to source such a config file twice, with different
1628 values for @code{CHIPNAME}, so
1629 it adds a different TAP each time.
1631 If there are nonzero @option{-expected-id} values,
1632 OpenOCD attempts to verify the actual tap id against those values.
1633 It will issue error messages if there is mismatch, which
1634 can help to pinpoint problems in OpenOCD configurations.
1636 @example
1637 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1638 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1639 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1640 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1641 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1642 @end example
1644 There are more complex examples too, with chips that have
1645 multiple TAPs. Ones worth looking at include:
1647 @itemize
1648 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1649 plus a JRC to enable them
1650 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1651 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1652 is not currently used)
1653 @end itemize
1655 @subsection Add CPU targets
1657 After adding a TAP for a CPU, you should set it up so that
1658 GDB and other commands can use it.
1659 @xref{CPU Configuration}.
1660 For the at91sam7 example above, the command can look like this;
1661 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1662 to little endian, and this chip doesn't support changing that.
1664 @example
1666 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1667 @end example
1669 Work areas are small RAM areas associated with CPU targets.
1670 They are used by OpenOCD to speed up downloads,
1671 and to download small snippets of code to program flash chips.
1672 If the chip includes a form of ``on-chip-ram'' - and many do - define
1673 a work area if you can.
1674 Again using the at91sam7 as an example, this can look like:
1676 @example
1677 $_TARGETNAME configure -work-area-phys 0x00200000 \
1678 -work-area-size 0x4000 -work-area-backup 0
1679 @end example
1681 @anchor{Define CPU targets working in SMP}
1682 @subsection Define CPU targets working in SMP
1683 @cindex SMP
1684 After setting targets, you can define a list of targets working in SMP.
1686 @example
1687 set _TARGETNAME_1 $_CHIPNAME.cpu1
1688 set _TARGETNAME_2 $_CHIPNAME.cpu2
1689 target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap \
1690 -coreid 0 -dbgbase $_DAP_DBG1
1691 target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap \
1692 -coreid 1 -dbgbase $_DAP_DBG2
1693 #define 2 targets working in smp.
1694 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1695 @end example
1696 In the above example on cortex_a8, 2 cpus are working in SMP.
1697 In SMP only one GDB instance is created and :
1698 @itemize @bullet
1699 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1700 @item halt command triggers the halt of all targets in the list.
1701 @item resume command triggers the write context and the restart of all targets in the list.
1702 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1703 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1704 displayed by the GDB session @pxref{Using openocd SMP with GDB}.
1705 @end itemize
1707 The SMP behaviour can be disabled/enabled dynamically. On cortex_a8 following
1708 command have been implemented.
1709 @itemize @bullet
1710 @item cortex_a8 smp_on : enable SMP mode, behaviour is as described above.
1711 @item cortex_a8 smp_off : disable SMP mode, the current target is the one
1712 displayed in the GDB session, only this target is now controlled by GDB
1713 session. This behaviour is useful during system boot up.
1714 @item cortex_a8 smp_gdb : display/fix the core id displayed in GDB session see
1715 following example.
1716 @end itemize
1718 @example
1719 >cortex_a8 smp_gdb
1720 gdb coreid 0 -> -1
1721 #0 : coreid 0 is displayed to GDB ,
1722 #-> -1 : next resume triggers a real resume
1723 > cortex_a8 smp_gdb 1
1724 gdb coreid 0 -> 1
1725 #0 :coreid 0 is displayed to GDB ,
1726 #->1 : next resume displays coreid 1 to GDB
1727 > resume
1728 > cortex_a8 smp_gdb
1729 gdb coreid 1 -> 1
1730 #1 :coreid 1 is displayed to GDB ,
1731 #->1 : next resume displays coreid 1 to GDB
1732 > cortex_a8 smp_gdb -1
1733 gdb coreid 1 -> -1
1734 #1 :coreid 1 is displayed to GDB,
1735 #->-1 : next resume triggers a real resume
1736 @end example
1739 @subsection Chip Reset Setup
1741 As a rule, you should put the @command{reset_config} command
1742 into the board file. Most things you think you know about a
1743 chip can be tweaked by the board.
1745 Some chips have specific ways the TRST and SRST signals are
1746 managed. In the unusual case that these are @emph{chip specific}
1747 and can never be changed by board wiring, they could go here.
1748 For example, some chips can't support JTAG debugging without
1749 both signals.
1751 Provide a @code{reset-assert} event handler if you can.
1752 Such a handler uses JTAG operations to reset the target,
1753 letting this target config be used in systems which don't
1754 provide the optional SRST signal, or on systems where you
1755 don't want to reset all targets at once.
1756 Such a handler might write to chip registers to force a reset,
1757 use a JRC to do that (preferable -- the target may be wedged!),
1758 or force a watchdog timer to trigger.
1759 (For Cortex-M3 targets, this is not necessary. The target
1760 driver knows how to use trigger an NVIC reset when SRST is
1761 not available.)
1763 Some chips need special attention during reset handling if
1764 they're going to be used with JTAG.
1765 An example might be needing to send some commands right
1766 after the target's TAP has been reset, providing a
1767 @code{reset-deassert-post} event handler that writes a chip
1768 register to report that JTAG debugging is being done.
1769 Another would be reconfiguring the watchdog so that it stops
1770 counting while the core is halted in the debugger.
1772 JTAG clocking constraints often change during reset, and in
1773 some cases target config files (rather than board config files)
1774 are the right places to handle some of those issues.
1775 For example, immediately after reset most chips run using a
1776 slower clock than they will use later.
1777 That means that after reset (and potentially, as OpenOCD
1778 first starts up) they must use a slower JTAG clock rate
1779 than they will use later.
1780 @xref{JTAG Speed}.
1782 @quotation Important
1783 When you are debugging code that runs right after chip
1784 reset, getting these issues right is critical.
1785 In particular, if you see intermittent failures when
1786 OpenOCD verifies the scan chain after reset,
1787 look at how you are setting up JTAG clocking.
1788 @end quotation
1790 @subsection ARM Core Specific Hacks
1792 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1793 special high speed download features - enable it.
1795 If present, the MMU, the MPU and the CACHE should be disabled.
1797 Some ARM cores are equipped with trace support, which permits
1798 examination of the instruction and data bus activity. Trace
1799 activity is controlled through an ``Embedded Trace Module'' (ETM)
1800 on one of the core's scan chains. The ETM emits voluminous data
1801 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
1802 If you are using an external trace port,
1803 configure it in your board config file.
1804 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1805 configure it in your target config file.
1807 @example
1808 etm config $_TARGETNAME 16 normal full etb
1809 etb config $_TARGETNAME $_CHIPNAME.etb
1810 @end example
1812 @subsection Internal Flash Configuration
1814 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1816 @b{Never ever} in the ``target configuration file'' define any type of
1817 flash that is external to the chip. (For example a BOOT flash on
1818 Chip Select 0.) Such flash information goes in a board file - not
1819 the TARGET (chip) file.
1821 Examples:
1822 @itemize @bullet
1823 @item at91sam7x256 - has 256K flash YES enable it.
1824 @item str912 - has flash internal YES enable it.
1825 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1826 @item pxa270 - again - CS0 flash - it goes in the board file.
1827 @end itemize
1829 @anchor{Translating Configuration Files}
1830 @section Translating Configuration Files
1831 @cindex translation
1832 If you have a configuration file for another hardware debugger
1833 or toolset (Abatron, BDI2000, BDI3000, CCS,
1834 Lauterbach, Segger, Macraigor, etc.), translating
1835 it into OpenOCD syntax is often quite straightforward. The most tricky
1836 part of creating a configuration script is oftentimes the reset init
1837 sequence where e.g. PLLs, DRAM and the like is set up.
1839 One trick that you can use when translating is to write small
1840 Tcl procedures to translate the syntax into OpenOCD syntax. This
1841 can avoid manual translation errors and make it easier to
1842 convert other scripts later on.
1844 Example of transforming quirky arguments to a simple search and
1845 replace job:
1847 @example
1848 # Lauterbach syntax(?)
1849 #
1850 # Data.Set c15:0x042f %long 0x40000015
1851 #
1852 # OpenOCD syntax when using procedure below.
1853 #
1854 # setc15 0x01 0x00050078
1856 proc setc15 @{regs value@} @{
1857 global TARGETNAME
1859 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
1861 arm mcr 15 [expr ($regs>>12)&0x7] \
1862 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
1863 [expr ($regs>>8)&0x7] $value
1864 @}
1865 @end example
1869 @node Daemon Configuration
1870 @chapter Daemon Configuration
1871 @cindex initialization
1872 The commands here are commonly found in the openocd.cfg file and are
1873 used to specify what TCP/IP ports are used, and how GDB should be
1874 supported.
1876 @anchor{Configuration Stage}
1877 @section Configuration Stage
1878 @cindex configuration stage
1879 @cindex config command
1881 When the OpenOCD server process starts up, it enters a
1882 @emph{configuration stage} which is the only time that
1883 certain commands, @emph{configuration commands}, may be issued.
1884 Normally, configuration commands are only available
1885 inside startup scripts.
1887 In this manual, the definition of a configuration command is
1888 presented as a @emph{Config Command}, not as a @emph{Command}
1889 which may be issued interactively.
1890 The runtime @command{help} command also highlights configuration
1891 commands, and those which may be issued at any time.
1893 Those configuration commands include declaration of TAPs,
1894 flash banks,
1895 the interface used for JTAG communication,
1896 and other basic setup.
1897 The server must leave the configuration stage before it
1898 may access or activate TAPs.
1899 After it leaves this stage, configuration commands may no
1900 longer be issued.
1902 @section Entering the Run Stage
1904 The first thing OpenOCD does after leaving the configuration
1905 stage is to verify that it can talk to the scan chain
1906 (list of TAPs) which has been configured.
1907 It will warn if it doesn't find TAPs it expects to find,
1908 or finds TAPs that aren't supposed to be there.
1909 You should see no errors at this point.
1910 If you see errors, resolve them by correcting the
1911 commands you used to configure the server.
1912 Common errors include using an initial JTAG speed that's too
1913 fast, and not providing the right IDCODE values for the TAPs
1914 on the scan chain.
1916 Once OpenOCD has entered the run stage, a number of commands
1917 become available.
1918 A number of these relate to the debug targets you may have declared.
1919 For example, the @command{mww} command will not be available until
1920 a target has been successfuly instantiated.
1921 If you want to use those commands, you may need to force
1922 entry to the run stage.
1924 @deffn {Config Command} init
1925 This command terminates the configuration stage and
1926 enters the run stage. This helps when you need to have
1927 the startup scripts manage tasks such as resetting the target,
1928 programming flash, etc. To reset the CPU upon startup, add "init" and
1929 "reset" at the end of the config script or at the end of the OpenOCD
1930 command line using the @option{-c} command line switch.
1932 If this command does not appear in any startup/configuration file
1933 OpenOCD executes the command for you after processing all
1934 configuration files and/or command line options.
1936 @b{NOTE:} This command normally occurs at or near the end of your
1937 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1938 targets ready. For example: If your openocd.cfg file needs to
1939 read/write memory on your target, @command{init} must occur before
1940 the memory read/write commands. This includes @command{nand probe}.
1941 @end deffn
1943 @deffn {Overridable Procedure} jtag_init
1944 This is invoked at server startup to verify that it can talk
1945 to the scan chain (list of TAPs) which has been configured.
1947 The default implementation first tries @command{jtag arp_init},
1948 which uses only a lightweight JTAG reset before examining the
1949 scan chain.
1950 If that fails, it tries again, using a harder reset
1951 from the overridable procedure @command{init_reset}.
1953 Implementations must have verified the JTAG scan chain before
1954 they return.
1955 This is done by calling @command{jtag arp_init}
1956 (or @command{jtag arp_init-reset}).
1957 @end deffn
1959 @anchor{TCP/IP Ports}
1960 @section TCP/IP Ports
1961 @cindex TCP port
1962 @cindex server
1963 @cindex port
1964 @cindex security
1965 The OpenOCD server accepts remote commands in several syntaxes.
1966 Each syntax uses a different TCP/IP port, which you may specify
1967 only during configuration (before those ports are opened).
1969 For reasons including security, you may wish to prevent remote
1970 access using one or more of these ports.
1971 In such cases, just specify the relevant port number as zero.
1972 If you disable all access through TCP/IP, you will need to
1973 use the command line @option{-pipe} option.
1975 @deffn {Command} gdb_port [number]
1976 @cindex GDB server
1977 Normally gdb listens to a TCP/IP port, but GDB can also
1978 communicate via pipes(stdin/out or named pipes). The name
1979 "gdb_port" stuck because it covers probably more than 90% of
1980 the normal use cases.
1982 No arguments reports GDB port. "pipe" means listen to stdin
1983 output to stdout, an integer is base port number, "disable"
1984 disables the gdb server.
1986 When using "pipe", also use log_output to redirect the log
1987 output to a file so as not to flood the stdin/out pipes.
1989 The -p/--pipe option is deprecated and a warning is printed
1990 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
1992 Any other string is interpreted as named pipe to listen to.
1993 Output pipe is the same name as input pipe, but with 'o' appended,
1994 e.g. /var/gdb, /var/gdbo.
1996 The GDB port for the first target will be the base port, the
1997 second target will listen on gdb_port + 1, and so on.
1998 When not specified during the configuration stage,
1999 the port @var{number} defaults to 3333.
2000 @end deffn
2002 @deffn {Command} tcl_port [number]
2003 Specify or query the port used for a simplified RPC
2004 connection that can be used by clients to issue TCL commands and get the
2005 output from the Tcl engine.
2006 Intended as a machine interface.
2007 When not specified during the configuration stage,
2008 the port @var{number} defaults to 6666.
2010 @end deffn
2012 @deffn {Command} telnet_port [number]
2013 Specify or query the
2014 port on which to listen for incoming telnet connections.
2015 This port is intended for interaction with one human through TCL commands.
2016 When not specified during the configuration stage,
2017 the port @var{number} defaults to 4444.
2018 When specified as zero, this port is not activated.
2019 @end deffn
2021 @anchor{GDB Configuration}
2022 @section GDB Configuration
2023 @cindex GDB
2024 @cindex GDB configuration
2025 You can reconfigure some GDB behaviors if needed.
2026 The ones listed here are static and global.
2027 @xref{Target Configuration}, about configuring individual targets.
2028 @xref{Target Events}, about configuring target-specific event handling.
2030 @anchor{gdb_breakpoint_override}
2031 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2032 Force breakpoint type for gdb @command{break} commands.
2033 This option supports GDB GUIs which don't
2034 distinguish hard versus soft breakpoints, if the default OpenOCD and
2035 GDB behaviour is not sufficient. GDB normally uses hardware
2036 breakpoints if the memory map has been set up for flash regions.
2037 @end deffn
2039 @anchor{gdb_flash_program}
2040 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2041 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2042 vFlash packet is received.
2043 The default behaviour is @option{enable}.
2044 @end deffn
2046 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2047 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2048 requested. GDB will then know when to set hardware breakpoints, and program flash
2049 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2050 for flash programming to work.
2051 Default behaviour is @option{enable}.
2052 @xref{gdb_flash_program}.
2053 @end deffn
2055 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2056 Specifies whether data aborts cause an error to be reported
2057 by GDB memory read packets.
2058 The default behaviour is @option{disable};
2059 use @option{enable} see these errors reported.
2060 @end deffn
2062 @anchor{Event Polling}
2063 @section Event Polling
2065 Hardware debuggers are parts of asynchronous systems,
2066 where significant events can happen at any time.
2067 The OpenOCD server needs to detect some of these events,
2068 so it can report them to through TCL command line
2069 or to GDB.
2071 Examples of such events include:
2073 @itemize
2074 @item One of the targets can stop running ... maybe it triggers
2075 a code breakpoint or data watchpoint, or halts itself.
2076 @item Messages may be sent over ``debug message'' channels ... many
2077 targets support such messages sent over JTAG,
2078 for receipt by the person debugging or tools.
2079 @item Loss of power ... some adapters can detect these events.
2080 @item Resets not issued through JTAG ... such reset sources
2081 can include button presses or other system hardware, sometimes
2082 including the target itself (perhaps through a watchdog).
2083 @item Debug instrumentation sometimes supports event triggering
2084 such as ``trace buffer full'' (so it can quickly be emptied)
2085 or other signals (to correlate with code behavior).
2086 @end itemize
2088 None of those events are signaled through standard JTAG signals.
2089 However, most conventions for JTAG connectors include voltage
2090 level and system reset (SRST) signal detection.
2091 Some connectors also include instrumentation signals, which
2092 can imply events when those signals are inputs.
2094 In general, OpenOCD needs to periodically check for those events,
2095 either by looking at the status of signals on the JTAG connector
2096 or by sending synchronous ``tell me your status'' JTAG requests
2097 to the various active targets.
2098 There is a command to manage and monitor that polling,
2099 which is normally done in the background.
2101 @deffn Command poll [@option{on}|@option{off}]
2102 Poll the current target for its current state.
2103 (Also, @pxref{target curstate}.)
2104 If that target is in debug mode, architecture
2105 specific information about the current state is printed.
2106 An optional parameter
2107 allows background polling to be enabled and disabled.
2109 You could use this from the TCL command shell, or
2110 from GDB using @command{monitor poll} command.
2111 Leave background polling enabled while you're using GDB.
2112 @example
2113 > poll
2114 background polling: on
2115 target state: halted
2116 target halted in ARM state due to debug-request, \
2117 current mode: Supervisor
2118 cpsr: 0x800000d3 pc: 0x11081bfc
2119 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2120 >
2121 @end example
2122 @end deffn
2124 @node Debug Adapter Configuration
2125 @chapter Debug Adapter Configuration
2126 @cindex config file, interface
2127 @cindex interface config file
2129 Correctly installing OpenOCD includes making your operating system give
2130 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2131 are used to select which one is used, and to configure how it is used.
2133 @quotation Note
2134 Because OpenOCD started out with a focus purely on JTAG, you may find
2135 places where it wrongly presumes JTAG is the only transport protocol
2136 in use. Be aware that recent versions of OpenOCD are removing that
2137 limitation. JTAG remains more functional than most other transports.
2138 Other transports do not support boundary scan operations, or may be
2139 specific to a given chip vendor. Some might be usable only for
2140 programming flash memory, instead of also for debugging.
2141 @end quotation
2143 Debug Adapters/Interfaces/Dongles are normally configured
2144 through commands in an interface configuration
2145 file which is sourced by your @file{openocd.cfg} file, or
2146 through a command line @option{-f interface/....cfg} option.
2148 @example
2149 source [find interface/olimex-jtag-tiny.cfg]
2150 @end example
2152 These commands tell
2153 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2154 A few cases are so simple that you only need to say what driver to use:
2156 @example
2157 # jlink interface
2158 interface jlink
2159 @end example
2161 Most adapters need a bit more configuration than that.
2164 @section Interface Configuration
2166 The interface command tells OpenOCD what type of debug adapter you are
2167 using. Depending on the type of adapter, you may need to use one or
2168 more additional commands to further identify or configure the adapter.
2170 @deffn {Config Command} {interface} name
2171 Use the interface driver @var{name} to connect to the
2172 target.
2173 @end deffn
2175 @deffn Command {interface_list}
2176 List the debug adapter drivers that have been built into
2177 the running copy of OpenOCD.
2178 @end deffn
2179 @deffn Command {interface transports} transport_name+
2180 Specifies the transports supported by this debug adapter.
2181 The adapter driver builds-in similar knowledge; use this only
2182 when external configuration (such as jumpering) changes what
2183 the hardware can support.
2184 @end deffn
2188 @deffn Command {adapter_name}
2189 Returns the name of the debug adapter driver being used.
2190 @end deffn
2192 @section Interface Drivers
2194 Each of the interface drivers listed here must be explicitly
2195 enabled when OpenOCD is configured, in order to be made
2196 available at run time.
2198 @deffn {Interface Driver} {amt_jtagaccel}
2199 Amontec Chameleon in its JTAG Accelerator configuration,
2200 connected to a PC's EPP mode parallel port.
2201 This defines some driver-specific commands:
2203 @deffn {Config Command} {parport_port} number
2204 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2205 the number of the @file{/dev/parport} device.
2206 @end deffn
2208 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2209 Displays status of RTCK option.
2210 Optionally sets that option first.
2211 @end deffn
2212 @end deffn
2214 @deffn {Interface Driver} {arm-jtag-ew}
2215 Olimex ARM-JTAG-EW USB adapter
2216 This has one driver-specific command:
2218 @deffn Command {armjtagew_info}
2219 Logs some status
2220 @end deffn
2221 @end deffn
2223 @deffn {Interface Driver} {at91rm9200}
2224 Supports bitbanged JTAG from the local system,
2225 presuming that system is an Atmel AT91rm9200
2226 and a specific set of GPIOs is used.
2227 @c command: at91rm9200_device NAME
2228 @c chooses among list of bit configs ... only one option
2229 @end deffn
2231 @deffn {Interface Driver} {dummy}
2232 A dummy software-only driver for debugging.
2233 @end deffn
2235 @deffn {Interface Driver} {ep93xx}
2236 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2237 @end deffn
2239 @deffn {Interface Driver} {ft2232}
2240 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2241 These interfaces have several commands, used to configure the driver
2242 before initializing the JTAG scan chain:
2244 @deffn {Config Command} {ft2232_device_desc} description
2245 Provides the USB device description (the @emph{iProduct string})
2246 of the FTDI FT2232 device. If not
2247 specified, the FTDI default value is used. This setting is only valid
2248 if compiled with FTD2XX support.
2249 @end deffn
2251 @deffn {Config Command} {ft2232_serial} serial-number
2252 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2253 in case the vendor provides unique IDs and more than one FT2232 device
2254 is connected to the host.
2255 If not specified, serial numbers are not considered.
2256 (Note that USB serial numbers can be arbitrary Unicode strings,
2257 and are not restricted to containing only decimal digits.)
2258 @end deffn
2260 @deffn {Config Command} {ft2232_layout} name
2261 Each vendor's FT2232 device can use different GPIO signals
2262 to control output-enables, reset signals, and LEDs.
2263 Currently valid layout @var{name} values include:
2264 @itemize @minus
2265 @item @b{axm0432_jtag} Axiom AXM-0432
2266 @item @b{comstick} Hitex STR9 comstick
2267 @item @b{cortino} Hitex Cortino JTAG interface
2268 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
2269 either for the local Cortex-M3 (SRST only)
2270 or in a passthrough mode (neither SRST nor TRST)
2271 This layout can not support the SWO trace mechanism, and should be
2272 used only for older boards (before rev C).
2273 @item @b{luminary_icdi} This layout should be used with most Luminary
2274 eval boards, including Rev C LM3S811 eval boards and the eponymous
2275 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2276 to debug some other target. It can support the SWO trace mechanism.
2277 @item @b{flyswatter} Tin Can Tools Flyswatter
2278 @item @b{icebear} ICEbear JTAG adapter from Section 5
2279 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2280 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2281 @item @b{m5960} American Microsystems M5960
2282 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2283 @item @b{oocdlink} OOCDLink
2284 @c oocdlink ~= jtagkey_prototype_v1
2285 @item @b{redbee-econotag} Integrated with a Redbee development board.
2286 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2287 @item @b{sheevaplug} Marvell Sheevaplug development kit
2288 @item @b{signalyzer} Xverve Signalyzer
2289 @item @b{stm32stick} Hitex STM32 Performance Stick
2290 @item @b{turtelizer2} egnite Software turtelizer2
2291 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2292 @end itemize
2293 @end deffn
2295 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2296 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2297 default values are used.
2298 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2299 @example
2300 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2301 @end example
2302 @end deffn
2304 @deffn {Config Command} {ft2232_latency} ms
2305 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2306 ft2232_read() fails to return the expected number of bytes. This can be caused by
2307 USB communication delays and has proved hard to reproduce and debug. Setting the
2308 FT2232 latency timer to a larger value increases delays for short USB packets but it
2309 also reduces the risk of timeouts before receiving the expected number of bytes.
2310 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2311 @end deffn
2313 For example, the interface config file for a
2314 Turtelizer JTAG Adapter looks something like this:
2316 @example
2317 interface ft2232
2318 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2319 ft2232_layout turtelizer2
2320 ft2232_vid_pid 0x0403 0xbdc8
2321 @end example
2322 @end deffn
2324 @deffn {Interface Driver} {remote_bitbang}
2325 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2326 with a remote process and sends ASCII encoded bitbang requests to that process
2327 instead of directly driving JTAG.
2329 The remote_bitbang driver is useful for debugging software running on
2330 processors which are being simulated.
2332 @deffn {Config Command} {remote_bitbang_port} number
2333 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2334 sockets instead of TCP.
2335 @end deffn
2337 @deffn {Config Command} {remote_bitbang_host} hostname
2338 Specifies the hostname of the remote process to connect to using TCP, or the
2339 name of the UNIX socket to use if remote_bitbang_port is 0.
2340 @end deffn
2342 For example, to connect remotely via TCP to the host foobar you might have
2343 something like:
2345 @example
2346 interface remote_bitbang
2347 remote_bitbang_port 3335
2348 remote_bitbang_host foobar
2349 @end example
2351 To connect to another process running locally via UNIX sockets with socket
2352 named mysocket:
2354 @example
2355 interface remote_bitbang
2356 remote_bitbang_port 0
2357 remote_bitbang_host mysocket
2358 @end example
2359 @end deffn
2361 @deffn {Interface Driver} {usb_blaster}
2362 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2363 for FTDI chips. These interfaces have several commands, used to
2364 configure the driver before initializing the JTAG scan chain:
2366 @deffn {Config Command} {usb_blaster_device_desc} description
2367 Provides the USB device description (the @emph{iProduct string})
2368 of the FTDI FT245 device. If not
2369 specified, the FTDI default value is used. This setting is only valid
2370 if compiled with FTD2XX support.
2371 @end deffn
2373 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2374 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2375 default values are used.
2376 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2377 Altera USB-Blaster (default):
2378 @example
2379 usb_blaster_vid_pid 0x09FB 0x6001
2380 @end example
2381 The following VID/PID is for Kolja Waschk's USB JTAG:
2382 @example
2383 usb_blaster_vid_pid 0x16C0 0x06AD
2384 @end example
2385 @end deffn
2387 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2388 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2389 female JTAG header). These pins can be used as SRST and/or TRST provided the
2390 appropriate connections are made on the target board.
2392 For example, to use pin 6 as SRST (as with an AVR board):
2393 @example
2394 $_TARGETNAME configure -event reset-assert \
2395 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2396 @end example
2397 @end deffn
2399 @end deffn
2401 @deffn {Interface Driver} {gw16012}
2402 Gateworks GW16012 JTAG programmer.
2403 This has one driver-specific command:
2405 @deffn {Config Command} {parport_port} [port_number]
2406 Display either the address of the I/O port
2407 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2408 If a parameter is provided, first switch to use that port.
2409 This is a write-once setting.
2410 @end deffn
2411 @end deffn
2413 @deffn {Interface Driver} {jlink}
2414 Segger jlink USB adapter
2415 @c command: jlink caps
2416 @c dumps jlink capabilities
2417 @c command: jlink config
2418 @c access J-Link configurationif no argument this will dump the config
2419 @c command: jlink config kickstart [val]
2420 @c set Kickstart power on JTAG-pin 19.
2421 @c command: jlink config mac_address [ff:ff:ff:ff:ff:ff]
2422 @c set the MAC Address
2423 @c command: jlink config ip [A.B.C.D[/E] [F.G.H.I]]
2424 @c set the ip address of the J-Link Pro, "
2425 @c where A.B.C.D is the ip,
2426 @c E the bit of the subnet mask
2427 @c F.G.H.I the subnet mask
2428 @c command: jlink config reset
2429 @c reset the current config
2430 @c command: jlink config save
2431 @c save the current config
2432 @c command: jlink config usb_address [0x00 to 0x03 or 0xff]
2433 @c set the USB-Address,
2434 @c This will change the product id
2435 @c command: jlink info
2436 @c dumps status
2437 @c command: jlink hw_jtag (2|3)
2438 @c sets version 2 or 3
2439 @c command: jlink pid
2440 @c set the pid of the interface we want to use
2441 @end deffn
2443 @deffn {Interface Driver} {parport}
2444 Supports PC parallel port bit-banging cables:
2445 Wigglers, PLD download cable, and more.
2446 These interfaces have several commands, used to configure the driver
2447 before initializing the JTAG scan chain:
2449 @deffn {Config Command} {parport_cable} name
2450 Set the layout of the parallel port cable used to connect to the target.
2451 This is a write-once setting.
2452 Currently valid cable @var{name} values include:
2454 @itemize @minus
2455 @item @b{altium} Altium Universal JTAG cable.
2456 @item @b{arm-jtag} Same as original wiggler except SRST and
2457 TRST connections reversed and TRST is also inverted.
2458 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2459 in configuration mode. This is only used to
2460 program the Chameleon itself, not a connected target.
2461 @item @b{dlc5} The Xilinx Parallel cable III.
2462 @item @b{flashlink} The ST Parallel cable.
2463 @item @b{lattice} Lattice ispDOWNLOAD Cable
2464 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2465 some versions of
2466 Amontec's Chameleon Programmer. The new version available from
2467 the website uses the original Wiggler layout ('@var{wiggler}')
2468 @item @b{triton} The parallel port adapter found on the
2469 ``Karo Triton 1 Development Board''.
2470 This is also the layout used by the HollyGates design
2471 (see @uref{}).
2472 @item @b{wiggler} The original Wiggler layout, also supported by
2473 several clones, such as the Olimex ARM-JTAG
2474 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2475 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2476 @end itemize
2477 @end deffn
2479 @deffn {Config Command} {parport_port} [port_number]
2480 Display either the address of the I/O port
2481 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2482 If a parameter is provided, first switch to use that port.
2483 This is a write-once setting.
2485 When using PPDEV to access the parallel port, use the number of the parallel port:
2486 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2487 you may encounter a problem.
2488 @end deffn
2490 @deffn Command {parport_toggling_time} [nanoseconds]
2491 Displays how many nanoseconds the hardware needs to toggle TCK;
2492 the parport driver uses this value to obey the
2493 @command{adapter_khz} configuration.
2494 When the optional @var{nanoseconds} parameter is given,
2495 that setting is changed before displaying the current value.
2497 The default setting should work reasonably well on commodity PC hardware.
2498 However, you may want to calibrate for your specific hardware.
2499 @quotation Tip
2500 To measure the toggling time with a logic analyzer or a digital storage
2501 oscilloscope, follow the procedure below:
2502 @example
2503 > parport_toggling_time 1000
2504 > adapter_khz 500
2505 @end example
2506 This sets the maximum JTAG clock speed of the hardware, but
2507 the actual speed probably deviates from the requested 500 kHz.
2508 Now, measure the time between the two closest spaced TCK transitions.
2509 You can use @command{runtest 1000} or something similar to generate a
2510 large set of samples.
2511 Update the setting to match your measurement:
2512 @example
2513 > parport_toggling_time <measured nanoseconds>
2514 @end example
2515 Now the clock speed will be a better match for @command{adapter_khz rate}
2516 commands given in OpenOCD scripts and event handlers.
2518 You can do something similar with many digital multimeters, but note
2519 that you'll probably need to run the clock continuously for several
2520 seconds before it decides what clock rate to show. Adjust the
2521 toggling time up or down until the measured clock rate is a good
2522 match for the adapter_khz rate you specified; be conservative.
2523 @end quotation
2524 @end deffn
2526 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2527 This will configure the parallel driver to write a known
2528 cable-specific value to the parallel interface on exiting OpenOCD.
2529 @end deffn
2531 For example, the interface configuration file for a
2532 classic ``Wiggler'' cable on LPT2 might look something like this:
2534 @example
2535 interface parport
2536 parport_port 0x278
2537 parport_cable wiggler
2538 @end example
2539 @end deffn
2541 @deffn {Interface Driver} {presto}
2542 ASIX PRESTO USB JTAG programmer.
2543 @deffn {Config Command} {presto_serial} serial_string
2544 Configures the USB serial number of the Presto device to use.
2545 @end deffn
2546 @end deffn
2548 @deffn {Interface Driver} {rlink}
2549 Raisonance RLink USB adapter
2550 @end deffn
2552 @deffn {Interface Driver} {usbprog}
2553 usbprog is a freely programmable USB adapter.
2554 @end deffn
2556 @deffn {Interface Driver} {vsllink}
2557 vsllink is part of Versaloon which is a versatile USB programmer.
2559 @quotation Note
2560 This defines quite a few driver-specific commands,
2561 which are not currently documented here.
2562 @end quotation
2563 @end deffn
2565 @deffn {Interface Driver} {ZY1000}
2566 This is the Zylin ZY1000 JTAG debugger.
2567 @end deffn
2569 @quotation Note
2570 This defines some driver-specific commands,
2571 which are not currently documented here.
2572 @end quotation
2574 @deffn Command power [@option{on}|@option{off}]
2575 Turn power switch to target on/off.
2576 No arguments: print status.
2577 @end deffn
2579 @section Transport Configuration
2580 @cindex Transport
2581 As noted earlier, depending on the version of OpenOCD you use,
2582 and the debug adapter you are using,
2583 several transports may be available to
2584 communicate with debug targets (or perhaps to program flash memory).
2585 @deffn Command {transport list}
2586 displays the names of the transports supported by this
2587 version of OpenOCD.
2588 @end deffn
2590 @deffn Command {transport select} transport_name
2591 Select which of the supported transports to use in this OpenOCD session.
2592 The transport must be supported by the debug adapter hardware and by the
2593 version of OPenOCD you are using (including the adapter's driver).
2594 No arguments: returns name of session's selected transport.
2595 @end deffn
2597 @subsection JTAG Transport
2598 @cindex JTAG
2599 JTAG is the original transport supported by OpenOCD, and most
2600 of the OpenOCD commands support it.
2601 JTAG transports expose a chain of one or more Test Access Points (TAPs),
2602 each of which must be explicitly declared.
2603 JTAG supports both debugging and boundary scan testing.
2604 Flash programming support is built on top of debug support.
2605 @subsection SWD Transport
2606 @cindex SWD
2607 @cindex Serial Wire Debug
2608 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
2609 Debug Access Point (DAP, which must be explicitly declared.
2610 (SWD uses fewer signal wires than JTAG.)
2611 SWD is debug-oriented, and does not support boundary scan testing.
2612 Flash programming support is built on top of debug support.
2613 (Some processors support both JTAG and SWD.)
2614 @deffn Command {swd newdap} ...
2615 Declares a single DAP which uses SWD transport.
2616 Parameters are currently the same as "jtag newtap" but this is
2617 expected to change.
2618 @end deffn
2619 @deffn Command {swd wcr trn prescale}
2620 Updates TRN (turnaraound delay) and prescaling.fields of the
2621 Wire Control Register (WCR).
2622 No parameters: displays current settings.
2623 @end deffn
2625 @subsection SPI Transport
2626 @cindex SPI
2627 @cindex Serial Peripheral Interface
2628 The Serial Peripheral Interface (SPI) is a general purpose transport
2629 which uses four wire signaling. Some processors use it as part of a
2630 solution for flash programming.
2632 @anchor{JTAG Speed}
2633 @section JTAG Speed
2634 JTAG clock setup is part of system setup.
2635 It @emph{does not belong with interface setup} since any interface
2636 only knows a few of the constraints for the JTAG clock speed.
2637 Sometimes the JTAG speed is
2638 changed during the target initialization process: (1) slow at
2639 reset, (2) program the CPU clocks, (3) run fast.
2640 Both the "slow" and "fast" clock rates are functions of the
2641 oscillators used, the chip, the board design, and sometimes
2642 power management software that may be active.
2644 The speed used during reset, and the scan chain verification which
2645 follows reset, can be adjusted using a @code{reset-start}
2646 target event handler.
2647 It can then be reconfigured to a faster speed by a
2648 @code{reset-init} target event handler after it reprograms those
2649 CPU clocks, or manually (if something else, such as a boot loader,
2650 sets up those clocks).
2651 @xref{Target Events}.
2652 When the initial low JTAG speed is a chip characteristic, perhaps
2653 because of a required oscillator speed, provide such a handler
2654 in the target config file.
2655 When that speed is a function of a board-specific characteristic
2656 such as which speed oscillator is used, it belongs in the board
2657 config file instead.
2658 In both cases it's safest to also set the initial JTAG clock rate
2659 to that same slow speed, so that OpenOCD never starts up using a
2660 clock speed that's faster than the scan chain can support.
2662 @example
2663 jtag_rclk 3000
2664 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
2665 @end example
2667 If your system supports adaptive clocking (RTCK), configuring
2668 JTAG to use that is probably the most robust approach.
2669 However, it introduces delays to synchronize clocks; so it
2670 may not be the fastest solution.
2672 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
2673 instead of @command{adapter_khz}, but only for (ARM) cores and boards
2674 which support adaptive clocking.
2676 @deffn {Command} adapter_khz max_speed_kHz
2677 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
2678 JTAG interfaces usually support a limited number of
2679 speeds. The speed actually used won't be faster
2680 than the speed specified.
2682 Chip data sheets generally include a top JTAG clock rate.
2683 The actual rate is often a function of a CPU core clock,
2684 and is normally less than that peak rate.
2685 For example, most ARM cores accept at most one sixth of the CPU clock.
2687 Speed 0 (khz) selects RTCK method.
2688 @xref{FAQ RTCK}.
2689 If your system uses RTCK, you won't need to change the
2690 JTAG clocking after setup.
2691 Not all interfaces, boards, or targets support ``rtck''.
2692 If the interface device can not
2693 support it, an error is returned when you try to use RTCK.
2694 @end deffn
2696 @defun jtag_rclk fallback_speed_kHz
2697 @cindex adaptive clocking
2698 @cindex RTCK
2699 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
2700 If that fails (maybe the interface, board, or target doesn't
2701 support it), falls back to the specified frequency.
2702 @example
2703 # Fall back to 3mhz if RTCK is not supported
2704 jtag_rclk 3000
2705 @end example
2706 @end defun
2708 @node Reset Configuration
2709 @chapter Reset Configuration
2710 @cindex Reset Configuration
2712 Every system configuration may require a different reset
2713 configuration. This can also be quite confusing.
2714 Resets also interact with @var{reset-init} event handlers,
2715 which do things like setting up clocks and DRAM, and
2716 JTAG clock rates. (@xref{JTAG Speed}.)
2717 They can also interact with JTAG routers.
2718 Please see the various board files for examples.
2720 @quotation Note
2721 To maintainers and integrators:
2722 Reset configuration touches several things at once.
2723 Normally the board configuration file
2724 should define it and assume that the JTAG adapter supports
2725 everything that's wired up to the board's JTAG connector.
2727 However, the target configuration file could also make note
2728 of something the silicon vendor has done inside the chip,
2729 which will be true for most (or all) boards using that chip.
2730 And when the JTAG adapter doesn't support everything, the
2731 user configuration file will need to override parts of
2732 the reset configuration provided by other files.
2733 @end quotation
2735 @section Types of Reset
2737 There are many kinds of reset possible through JTAG, but
2738 they may not all work with a given board and adapter.
2739 That's part of why reset configuration can be error prone.
2741 @itemize @bullet
2742 @item
2743 @emph{System Reset} ... the @emph{SRST} hardware signal
2744 resets all chips connected to the JTAG adapter, such as processors,
2745 power management chips, and I/O controllers. Normally resets triggered
2746 with this signal behave exactly like pressing a RESET button.
2747 @item
2748 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
2749 just the TAP controllers connected to the JTAG adapter.
2750 Such resets should not be visible to the rest of the system; resetting a
2751 device's TAP controller just puts that controller into a known state.
2752 @item
2753 @emph{Emulation Reset} ... many devices can be reset through JTAG
2754 commands. These resets are often distinguishable from system
2755 resets, either explicitly (a "reset reason" register says so)
2756 or implicitly (not all parts of the chip get reset).
2757 @item
2758 @emph{Other Resets} ... system-on-chip devices often support
2759 several other types of reset.
2760 You may need to arrange that a watchdog timer stops
2761 while debugging, preventing a watchdog reset.
2762 There may be individual module resets.
2763 @end itemize
2765 In the best case, OpenOCD can hold SRST, then reset
2766 the TAPs via TRST and send commands through JTAG to halt the
2767 CPU at the reset vector before the 1st instruction is executed.
2768 Then when it finally releases the SRST signal, the system is
2769 halted under debugger control before any code has executed.
2770 This is the behavior required to support the @command{reset halt}
2771 and @command{reset init} commands; after @command{reset init} a
2772 board-specific script might do things like setting up DRAM.
2773 (@xref{Reset Command}.)
2775 @anchor{SRST and TRST Issues}
2776 @section SRST and TRST Issues
2778 Because SRST and TRST are hardware signals, they can have a
2779 variety of system-specific constraints. Some of the most
2780 common issues are:
2782 @itemize @bullet
2784 @item @emph{Signal not available} ... Some boards don't wire
2785 SRST or TRST to the JTAG connector. Some JTAG adapters don't
2786 support such signals even if they are wired up.
2787 Use the @command{reset_config} @var{signals} options to say
2788 when either of those signals is not connected.
2789 When SRST is not available, your code might not be able to rely
2790 on controllers having been fully reset during code startup.
2791 Missing TRST is not a problem, since JTAG-level resets can
2792 be triggered using with TMS signaling.
2794 @item @emph{Signals shorted} ... Sometimes a chip, board, or
2795 adapter will connect SRST to TRST, instead of keeping them separate.
2796 Use the @command{reset_config} @var{combination} options to say
2797 when those signals aren't properly independent.
2799 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
2800 delay circuit, reset supervisor, or on-chip features can extend
2801 the effect of a JTAG adapter's reset for some time after the adapter
2802 stops issuing the reset. For example, there may be chip or board
2803 requirements that all reset pulses last for at least a
2804 certain amount of time; and reset buttons commonly have
2805 hardware debouncing.
2806 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
2807 commands to say when extra delays are needed.
2809 @item @emph{Drive type} ... Reset lines often have a pullup
2810 resistor, letting the JTAG interface treat them as open-drain
2811 signals. But that's not a requirement, so the adapter may need
2812 to use push/pull output drivers.
2813 Also, with weak pullups it may be advisable to drive
2814 signals to both levels (push/pull) to minimize rise times.
2815 Use the @command{reset_config} @var{trst_type} and
2816 @var{srst_type} parameters to say how to drive reset signals.
2818 @item @emph{Special initialization} ... Targets sometimes need
2819 special JTAG initialization sequences to handle chip-specific
2820 issues (not limited to errata).
2821 For example, certain JTAG commands might need to be issued while
2822 the system as a whole is in a reset state (SRST active)
2823 but the JTAG scan chain is usable (TRST inactive).
2824 Many systems treat combined assertion of SRST and TRST as a
2825 trigger for a harder reset than SRST alone.
2826 Such custom reset handling is discussed later in this chapter.
2827 @end itemize
2829 There can also be other issues.
2830 Some devices don't fully conform to the JTAG specifications.
2831 Trivial system-specific differences are common, such as
2832 SRST and TRST using slightly different names.
2833 There are also vendors who distribute key JTAG documentation for
2834 their chips only to developers who have signed a Non-Disclosure
2835 Agreement (NDA).
2837 Sometimes there are chip-specific extensions like a requirement to use
2838 the normally-optional TRST signal (precluding use of JTAG adapters which
2839 don't pass TRST through), or needing extra steps to complete a TAP reset.
2841 In short, SRST and especially TRST handling may be very finicky,
2842 needing to cope with both architecture and board specific constraints.
2844 @section Commands for Handling Resets
2846 @deffn {Command} adapter_nsrst_assert_width milliseconds
2847 Minimum amount of time (in milliseconds) OpenOCD should wait
2848 after asserting nSRST (active-low system reset) before
2849 allowing it to be deasserted.
2850 @end deffn
2852 @deffn {Command} adapter_nsrst_delay milliseconds
2853 How long (in milliseconds) OpenOCD should wait after deasserting
2854 nSRST (active-low system reset) before starting new JTAG operations.
2855 When a board has a reset button connected to SRST line it will
2856 probably have hardware debouncing, implying you should use this.
2857 @end deffn
2859 @deffn {Command} jtag_ntrst_assert_width milliseconds
2860 Minimum amount of time (in milliseconds) OpenOCD should wait
2861 after asserting nTRST (active-low JTAG TAP reset) before
2862 allowing it to be deasserted.
2863 @end deffn
2865 @deffn {Command} jtag_ntrst_delay milliseconds
2866 How long (in milliseconds) OpenOCD should wait after deasserting
2867 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
2868 @end deffn
2870 @deffn {Command} reset_config mode_flag ...
2871 This command displays or modifies the reset configuration
2872 of your combination of JTAG board and target in target
2873 configuration scripts.
2875 Information earlier in this section describes the kind of problems
2876 the command is intended to address (@pxref{SRST and TRST Issues}).
2877 As a rule this command belongs only in board config files,
2878 describing issues like @emph{board doesn't connect TRST};
2879 or in user config files, addressing limitations derived
2880 from a particular combination of interface and board.
2881 (An unlikely example would be using a TRST-only adapter
2882 with a board that only wires up SRST.)
2884 The @var{mode_flag} options can be specified in any order, but only one
2885 of each type -- @var{signals}, @var{combination},
2886 @var{gates},
2887 @var{trst_type},
2888 and @var{srst_type} -- may be specified at a time.
2889 If you don't provide a new value for a given type, its previous
2890 value (perhaps the default) is unchanged.
2891 For example, this means that you don't need to say anything at all about
2892 TRST just to declare that if the JTAG adapter should want to drive SRST,
2893 it must explicitly be driven high (@option{srst_push_pull}).
2895 @itemize
2896 @item
2897 @var{signals} can specify which of the reset signals are connected.
2898 For example, If the JTAG interface provides SRST, but the board doesn't
2899 connect that signal properly, then OpenOCD can't use it.
2900 Possible values are @option{none} (the default), @option{trst_only},
2901 @option{srst_only} and @option{trst_and_srst}.
2903 @quotation Tip
2904 If your board provides SRST and/or TRST through the JTAG connector,
2905 you must declare that so those signals can be used.
2906 @end quotation
2908 @item
2909 The @var{combination} is an optional value specifying broken reset
2910 signal implementations.
2911 The default behaviour if no option given is @option{separate},
2912 indicating everything behaves normally.
2913 @option{srst_pulls_trst} states that the
2914 test logic is reset together with the reset of the system (e.g. NXP
2915 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
2916 the system is reset together with the test logic (only hypothetical, I
2917 haven't seen hardware with such a bug, and can be worked around).
2918 @option{combined} implies both @option{srst_pulls_trst} and
2919 @option{trst_pulls_srst}.
2921 @item
2922 The @var{gates} tokens control flags that describe some cases where
2923 JTAG may be unvailable during reset.
2924 @option{srst_gates_jtag} (default)
2925 indicates that asserting SRST gates the
2926 JTAG clock. This means that no communication can happen on JTAG
2927 while SRST is asserted.
2928 Its converse is @option{srst_nogate}, indicating that JTAG commands
2929 can safely be issued while SRST is active.
2930 @end itemize
2932 The optional @var{trst_type} and @var{srst_type} parameters allow the
2933 driver mode of each reset line to be specified. These values only affect
2934 JTAG interfaces with support for different driver modes, like the Amontec
2935 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
2936 relevant signal (TRST or SRST) is not connected.
2938 @itemize
2939 @item
2940 Possible @var{trst_type} driver modes for the test reset signal (TRST)
2941 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
2942 Most boards connect this signal to a pulldown, so the JTAG TAPs
2943 never leave reset unless they are hooked up to a JTAG adapter.
2945 @item
2946 Possible @var{srst_type} driver modes for the system reset signal (SRST)
2947 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
2948 Most boards connect this signal to a pullup, and allow the
2949 signal to be pulled low by various events including system
2950 powerup and pressing a reset button.
2951 @end itemize
2952 @end deffn
2954 @section Custom Reset Handling
2955 @cindex events
2957 OpenOCD has several ways to help support the various reset
2958 mechanisms provided by chip and board vendors.
2959 The commands shown in the previous section give standard parameters.
2960 There are also @emph{event handlers} associated with TAPs or Targets.
2961 Those handlers are Tcl procedures you can provide, which are invoked
2962 at particular points in the reset sequence.
2964 @emph{When SRST is not an option} you must set
2965 up a @code{reset-assert} event handler for your target.
2966 For example, some JTAG adapters don't include the SRST signal;
2967 and some boards have multiple targets, and you won't always
2968 want to reset everything at once.
2970 After configuring those mechanisms, you might still
2971 find your board doesn't start up or reset correctly.
2972 For example, maybe it needs a slightly different sequence
2973 of SRST and/or TRST manipulations, because of quirks that
2974 the @command{reset_config} mechanism doesn't address;
2975 or asserting both might trigger a stronger reset, which
2976 needs special attention.
2978 Experiment with lower level operations, such as @command{jtag_reset}
2979 and the @command{jtag arp_*} operations shown here,
2980 to find a sequence of operations that works.
2981 @xref{JTAG Commands}.
2982 When you find a working sequence, it can be used to override
2983 @command{jtag_init}, which fires during OpenOCD startup
2984 (@pxref{Configuration Stage});
2985 or @command{init_reset}, which fires during reset processing.
2987 You might also want to provide some project-specific reset
2988 schemes. For example, on a multi-target board the standard
2989 @command{reset} command would reset all targets, but you
2990 may need the ability to reset only one target at time and
2991 thus want to avoid using the board-wide SRST signal.
2993 @deffn {Overridable Procedure} init_reset mode
2994 This is invoked near the beginning of the @command{reset} command,
2995 usually to provide as much of a cold (power-up) reset as practical.
2996 By default it is also invoked from @command{jtag_init} if
2997 the scan chain does not respond to pure JTAG operations.
2998 The @var{mode} parameter is the parameter given to the
2999 low level reset command (@option{halt},
3000 @option{init}, or @option{run}), @option{setup},
3001 or potentially some other value.
3003 The default implementation just invokes @command{jtag arp_init-reset}.
3004 Replacements will normally build on low level JTAG
3005 operations such as @command{jtag_reset}.
3006 Operations here must not address individual TAPs
3007 (or their associated targets)
3008 until the JTAG scan chain has first been verified to work.
3010 Implementations must have verified the JTAG scan chain before
3011 they return.
3012 This is done by calling @command{jtag arp_init}
3013 (or @command{jtag arp_init-reset}).
3014 @end deffn
3016 @deffn Command {jtag arp_init}
3017 This validates the scan chain using just the four
3018 standard JTAG signals (TMS, TCK, TDI, TDO).
3019 It starts by issuing a JTAG-only reset.
3020 Then it performs checks to verify that the scan chain configuration
3021 matches the TAPs it can observe.
3022 Those checks include checking IDCODE values for each active TAP,
3023 and verifying the length of their instruction registers using
3024 TAP @code{-ircapture} and @code{-irmask} values.
3025 If these tests all pass, TAP @code{setup} events are
3026 issued to all TAPs with handlers for that event.
3027 @end deffn
3029 @deffn Command {jtag arp_init-reset}
3030 This uses TRST and SRST to try resetting
3031 everything on the JTAG scan chain
3032 (and anything else connected to SRST).
3033 It then invokes the logic of @command{jtag arp_init}.
3034 @end deffn
3037 @node TAP Declaration
3038 @chapter TAP Declaration
3039 @cindex TAP declaration
3040 @cindex TAP configuration
3042 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3043 TAPs serve many roles, including:
3045 @itemize @bullet
3046 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
3047 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
3048 Others do it indirectly, making a CPU do it.
3049 @item @b{Program Download} Using the same CPU support GDB uses,
3050 you can initialize a DRAM controller, download code to DRAM, and then
3051 start running that code.
3052 @item @b{Boundary Scan} Most chips support boundary scan, which
3053 helps test for board assembly problems like solder bridges
3054 and missing connections
3055 @end itemize
3057 OpenOCD must know about the active TAPs on your board(s).
3058 Setting up the TAPs is the core task of your configuration files.
3059 Once those TAPs are set up, you can pass their names to code
3060 which sets up CPUs and exports them as GDB targets,
3061 probes flash memory, performs low-level JTAG operations, and more.
3063 @section Scan Chains
3064 @cindex scan chain
3066 TAPs are part of a hardware @dfn{scan chain},
3067 which is daisy chain of TAPs.
3068 They also need to be added to
3069 OpenOCD's software mirror of that hardware list,
3070 giving each member a name and associating other data with it.
3071 Simple scan chains, with a single TAP, are common in
3072 systems with a single microcontroller or microprocessor.
3073 More complex chips may have several TAPs internally.
3074 Very complex scan chains might have a dozen or more TAPs:
3075 several in one chip, more in the next, and connecting
3076 to other boards with their own chips and TAPs.
3078 You can display the list with the @command{scan_chain} command.
3079 (Don't confuse this with the list displayed by the @command{targets}
3080 command, presented in the next chapter.
3081 That only displays TAPs for CPUs which are configured as
3082 debugging targets.)
3083 Here's what the scan chain might look like for a chip more than one TAP:
3085 @verbatim
3086 TapName Enabled IdCode Expected IrLen IrCap IrMask
3087 -- ------------------ ------- ---------- ---------- ----- ----- ------
3088 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3089 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3090 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3091 @end verbatim
3093 OpenOCD can detect some of that information, but not all
3094 of it. @xref{Autoprobing}.
3095 Unfortunately those TAPs can't always be autoconfigured,
3096 because not all devices provide good support for that.
3097 JTAG doesn't require supporting IDCODE instructions, and
3098 chips with JTAG routers may not link TAPs into the chain
3099 until they are told to do so.
3101 The configuration mechanism currently supported by OpenOCD
3102 requires explicit configuration of all TAP devices using
3103 @command{jtag newtap} commands, as detailed later in this chapter.
3104 A command like this would declare one tap and name it @code{chip1.cpu}:
3106 @example
3107 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3108 @end example
3110 Each target configuration file lists the TAPs provided
3111 by a given chip.
3112 Board configuration files combine all the targets on a board,
3113 and so forth.
3114 Note that @emph{the order in which TAPs are declared is very important.}
3115 It must match the order in the JTAG scan chain, both inside
3116 a single chip and between them.
3117 @xref{FAQ TAP Order}.
3119 For example, the ST Microsystems STR912 chip has
3120 three separate TAPs@footnote{See the ST
3121 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3122 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3123 @url{}}.
3124 To configure those taps, @file{target/str912.cfg}
3125 includes commands something like this:
3127 @example
3128 jtag newtap str912 flash ... params ...
3129 jtag newtap str912 cpu ... params ...
3130 jtag newtap str912 bs ... params ...
3131 @end example
3133 Actual config files use a variable instead of literals like
3134 @option{str912}, to support more than one chip of each type.
3135 @xref{Config File Guidelines}.
3137 @deffn Command {jtag names}
3138 Returns the names of all current TAPs in the scan chain.
3139 Use @command{jtag cget} or @command{jtag tapisenabled}
3140 to examine attributes and state of each TAP.
3141 @example
3142 foreach t [jtag names] @{
3143 puts [format "TAP: %s\n" $t]
3144 @}
3145 @end example
3146 @end deffn
3148 @deffn Command {scan_chain}
3149 Displays the TAPs in the scan chain configuration,
3150 and their status.
3151 The set of TAPs listed by this command is fixed by
3152 exiting the OpenOCD configuration stage,
3153 but systems with a JTAG router can
3154 enable or disable TAPs dynamically.
3155 @end deffn
3157 @c FIXME! "jtag cget" should be able to return all TAP
3158 @c attributes, like "$target_name cget" does for targets.
3160 @c Probably want "jtag eventlist", and a "tap-reset" event
3161 @c (on entry to RESET state).
3163 @section TAP Names
3164 @cindex dotted name
3166 When TAP objects are declared with @command{jtag newtap},
3167 a @dfn{} is created for the TAP, combining the
3168 name of a module (usually a chip) and a label for the TAP.
3169 For example: @code{xilinx.tap}, @code{str912.flash},
3170 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3171 Many other commands use that to manipulate or
3172 refer to the TAP. For example, CPU configuration uses the
3173 name, as does declaration of NAND or NOR flash banks.
3175 The components of a dotted name should follow ``C'' symbol
3176 name rules: start with an alphabetic character, then numbers
3177 and underscores are OK; while others (including dots!) are not.
3179 @quotation Tip
3180 In older code, JTAG TAPs were numbered from 0..N.
3181 This feature is still present.
3182 However its use is highly discouraged, and
3183 should not be relied on; it will be removed by mid-2010.
3184 Update all of your scripts to use TAP names rather than numbers,
3185 by paying attention to the runtime warnings they trigger.
3186 Using TAP numbers in target configuration scripts prevents
3187 reusing those scripts on boards with multiple targets.
3188 @end quotation
3190 @section TAP Declaration Commands
3192 @c shouldn't this be(come) a {Config Command}?
3193 @anchor{jtag newtap}
3194 @deffn Command {jtag newtap} chipname tapname configparams...
3195 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3196 and configured according to the various @var{configparams}.
3198 The @var{chipname} is a symbolic name for the chip.
3199 Conventionally target config files use @code{$_CHIPNAME},
3200 defaulting to the model name given by the chip vendor but
3201 overridable.
3203 @cindex TAP naming convention
3204 The @var{tapname} reflects the role of that TAP,
3205 and should follow this convention:
3207 @itemize @bullet
3208 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3209 @item @code{cpu} -- The main CPU of the chip, alternatively
3210 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3211 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3212 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3213 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3214 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3215 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3216 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3217 with a single TAP;
3218 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3219 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3220 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3221 a JTAG TAP; that TAP should be named @code{sdma}.
3222 @end itemize
3224 Every TAP requires at least the following @var{configparams}:
3226 @itemize @bullet
3227 @item @code{-irlen} @var{NUMBER}
3228 @*The length in bits of the
3229 instruction register, such as 4 or 5 bits.
3230 @end itemize
3232 A TAP may also provide optional @var{configparams}:
3234 @itemize @bullet
3235 @item @code{-disable} (or @code{-enable})
3236 @*Use the @code{-disable} parameter to flag a TAP which is not
3237 linked in to the scan chain after a reset using either TRST
3238 or the JTAG state machine's @sc{reset} state.
3239 You may use @code{-enable} to highlight the default state
3240 (the TAP is linked in).
3241 @xref{Enabling and Disabling TAPs}.
3242 @item @code{-expected-id} @var{number}
3243 @*A non-zero @var{number} represents a 32-bit IDCODE
3244 which you expect to find when the scan chain is examined.
3245 These codes are not required by all JTAG devices.
3246 @emph{Repeat the option} as many times as required if more than one
3247 ID code could appear (for example, multiple versions).
3248 Specify @var{number} as zero to suppress warnings about IDCODE
3249 values that were found but not included in the list.
3251 Provide this value if at all possible, since it lets OpenOCD
3252 tell when the scan chain it sees isn't right. These values
3253 are provided in vendors' chip documentation, usually a technical
3254 reference manual. Sometimes you may need to probe the JTAG
3255 hardware to find these values.
3256 @xref{Autoprobing}.
3257 @item @code{-ignore-version}
3258 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3259 option. When vendors put out multiple versions of a chip, or use the same
3260 JTAG-level ID for several largely-compatible chips, it may be more practical
3261 to ignore the version field than to update config files to handle all of
3262 the various chip IDs.
3263 @item @code{-ircapture} @var{NUMBER}
3264 @*The bit pattern loaded by the TAP into the JTAG shift register
3265 on entry to the @sc{ircapture} state, such as 0x01.
3266 JTAG requires the two LSBs of this value to be 01.
3267 By default, @code{-ircapture} and @code{-irmask} are set
3268 up to verify that two-bit value. You may provide
3269 additional bits, if you know them, or indicate that
3270 a TAP doesn't conform to the JTAG specification.
3271 @item @code{-irmask} @var{NUMBER}
3272 @*A mask used with @code{-ircapture}
3273 to verify that instruction scans work correctly.
3274 Such scans are not used by OpenOCD except to verify that
3275 there seems to be no problems with JTAG scan chain operations.
3276 @end itemize
3277 @end deffn
3279 @section Other TAP commands
3281 @deffn Command {jtag cget} @option{-event} name
3282 @deffnx Command {jtag configure} @option{-event} name string
3283 At this writing this TAP attribute
3284 mechanism is used only for event handling.
3285 (It is not a direct analogue of the @code{cget}/@code{configure}
3286 mechanism for debugger targets.)
3287 See the next section for information about the available events.
3289 The @code{configure} subcommand assigns an event handler,
3290 a TCL string which is evaluated when the event is triggered.
3291 The @code{cget} subcommand returns that handler.
3292 @end deffn
3294 @anchor{TAP Events}
3295 @section TAP Events
3296 @cindex events
3297 @cindex TAP events
3299 OpenOCD includes two event mechanisms.
3300 The one presented here applies to all JTAG TAPs.
3301 The other applies to debugger targets,
3302 which are associated with certain TAPs.
3304 The TAP events currently defined are:
3306 @itemize @bullet
3307 @item @b{post-reset}
3308 @* The TAP has just completed a JTAG reset.
3309 The tap may still be in the JTAG @sc{reset} state.
3310 Handlers for these events might perform initialization sequences
3311 such as issuing TCK cycles, TMS sequences to ensure
3312 exit from the ARM SWD mode, and more.
3314 Because the scan chain has not yet been verified, handlers for these events
3315 @emph{should not issue commands which scan the JTAG IR or DR registers}
3316 of any particular target.
3317 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3318 @item @b{setup}
3319 @* The scan chain has been reset and verified.
3320 This handler may enable TAPs as needed.
3321 @item @b{tap-disable}
3322 @* The TAP needs to be disabled. This handler should
3323 implement @command{jtag tapdisable}
3324 by issuing the relevant JTAG commands.
3325 @item @b{tap-enable}
3326 @* The TAP needs to be enabled. This handler should
3327 implement @command{jtag tapenable}
3328 by issuing the relevant JTAG commands.
3329 @end itemize
3331 If you need some action after each JTAG reset, which isn't actually
3332 specific to any TAP (since you can't yet trust the scan chain's
3333 contents to be accurate), you might:
3335 @example
3336 jtag configure CHIP.jrc -event post-reset @{
3337 echo "JTAG Reset done"
3338 ... non-scan jtag operations to be done after reset
3339 @}
3340 @end example
3343 @anchor{Enabling and Disabling TAPs}
3344 @section Enabling and Disabling TAPs
3345 @cindex JTAG Route Controller
3346 @cindex jrc
3348 In some systems, a @dfn{JTAG Route Controller} (JRC)
3349 is used to enable and/or disable specific JTAG TAPs.
3350 Many ARM based chips from Texas Instruments include
3351 an ``ICEpick'' module, which is a JRC.
3352 Such chips include DaVinci and OMAP3 processors.
3354 A given TAP may not be visible until the JRC has been
3355 told to link it into the scan chain; and if the JRC
3356 has been told to unlink that TAP, it will no longer
3357 be visible.
3358 Such routers address problems that JTAG ``bypass mode''
3359 ignores, such as:
3361 @itemize
3362 @item The scan chain can only go as fast as its slowest TAP.
3363 @item Having many TAPs slows instruction scans, since all
3364 TAPs receive new instructions.
3365 @item TAPs in the scan chain must be powered up, which wastes
3366 power and prevents debugging some power management mechanisms.
3367 @end itemize
3369 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3370 as implied by the existence of JTAG routers.
3371 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3372 does include a kind of JTAG router functionality.
3374 @c (a) currently the event handlers don't seem to be able to
3375 @c fail in a way that could lead to no-change-of-state.
3377 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3378 shown below, and is implemented using TAP event handlers.
3379 So for example, when defining a TAP for a CPU connected to
3380 a JTAG router, your @file{target.cfg} file
3381 should define TAP event handlers using
3382 code that looks something like this:
3384 @example
3385 jtag configure CHIP.cpu -event tap-enable @{
3386 ... jtag operations using CHIP.jrc
3387 @}
3388 jtag configure CHIP.cpu -event tap-disable @{
3389 ... jtag operations using CHIP.jrc
3390 @}
3391 @end example
3393 Then you might want that CPU's TAP enabled almost all the time:
3395 @example
3396 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3397 @end example
3399 Note how that particular setup event handler declaration
3400 uses quotes to evaluate @code{$CHIP} when the event is configured.
3401 Using brackets @{ @} would cause it to be evaluated later,
3402 at runtime, when it might have a different value.
3404 @deffn Command {jtag tapdisable}
3405 If necessary, disables the tap
3406 by sending it a @option{tap-disable} event.
3407 Returns the string "1" if the tap
3408 specified by @var{} is enabled,
3409 and "0" if it is disabled.
3410 @end deffn
3412 @deffn Command {jtag tapenable}
3413 If necessary, enables the tap
3414 by sending it a @option{tap-enable} event.
3415 Returns the string "1" if the tap
3416 specified by @var{} is enabled,
3417 and "0" if it is disabled.
3418 @end deffn
3420 @deffn Command {jtag tapisenabled}
3421 Returns the string "1" if the tap
3422 specified by @var{} is enabled,
3423 and "0" if it is disabled.
3425 @quotation Note
3426 Humans will find the @command{scan_chain} command more helpful
3427 for querying the state of the JTAG taps.
3428 @end quotation
3429 @end deffn
3431 @anchor{Autoprobing}
3432 @section Autoprobing
3433 @cindex autoprobe
3434 @cindex JTAG autoprobe
3436 TAP configuration is the first thing that needs to be done
3437 after interface and reset configuration. Sometimes it's
3438 hard finding out what TAPs exist, or how they are identified.
3439 Vendor documentation is not always easy to find and use.
3441 To help you get past such problems, OpenOCD has a limited
3442 @emph{autoprobing} ability to look at the scan chain, doing
3443 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3444 To use this mechanism, start the OpenOCD server with only data
3445 that configures your JTAG interface, and arranges to come up
3446 with a slow clock (many devices don't support fast JTAG clocks
3447 right when they come out of reset).
3449 For example, your @file{openocd.cfg} file might have:
3451 @example
3452 source [find interface/olimex-arm-usb-tiny-h.cfg]
3453 reset_config trst_and_srst
3454 jtag_rclk 8
3455 @end example
3457 When you start the server without any TAPs configured, it will
3458 attempt to autoconfigure the TAPs. There are two parts to this:
3460 @enumerate
3461 @item @emph{TAP discovery} ...
3462 After a JTAG reset (sometimes a system reset may be needed too),
3463 each TAP's data registers will hold the contents of either the
3464 IDCODE or BYPASS register.
3465 If JTAG communication is working, OpenOCD will see each TAP,
3466 and report what @option{-expected-id} to use with it.
3467 @item @emph{IR Length discovery} ...
3468 Unfortunately JTAG does not provide a reliable way to find out
3469 the value of the @option{-irlen} parameter to use with a TAP
3470 that is discovered.
3471 If OpenOCD can discover the length of a TAP's instruction
3472 register, it will report it.
3473 Otherwise you may need to consult vendor documentation, such
3474 as chip data sheets or BSDL files.
3475 @end enumerate
3477 In many cases your board will have a simple scan chain with just
3478 a single device. Here's what OpenOCD reported with one board
3479 that's a bit more complex:
3481 @example
3482 clock speed 8 kHz
3483 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3484 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3485 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3486 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3487 AUTO auto0.tap - use "... -irlen 4"
3488 AUTO auto1.tap - use "... -irlen 4"
3489 AUTO auto2.tap - use "... -irlen 6"
3490 no gdb ports allocated as no target has been specified
3491 @end example
3493 Given that information, you should be able to either find some existing
3494 config files to use, or create your own. If you create your own, you
3495 would configure from the bottom up: first a @file{target.cfg} file
3496 with these TAPs, any targets associated with them, and any on-chip
3497 resources; then a @file{board.cfg} with off-chip resources, clocking,
3498 and so forth.
3500 @node CPU Configuration
3501 @chapter CPU Configuration
3502 @cindex GDB target
3504 This chapter discusses how to set up GDB debug targets for CPUs.
3505 You can also access these targets without GDB
3506 (@pxref{Architecture and Core Commands},
3507 and @ref{Target State handling}) and
3508 through various kinds of NAND and NOR flash commands.
3509 If you have multiple CPUs you can have multiple such targets.
3511 We'll start by looking at how to examine the targets you have,
3512 then look at how to add one more target and how to configure it.
3514 @section Target List
3515 @cindex target, current
3516 @cindex target, list
3518 All targets that have been set up are part of a list,
3519 where each member has a name.
3520 That name should normally be the same as the TAP name.
3521 You can display the list with the @command{targets}
3522 (plural!) command.
3523 This display often has only one CPU; here's what it might
3524 look like with more than one:
3525 @verbatim
3526 TargetName Type Endian TapName State
3527 -- ------------------ ---------- ------ ------------------ ------------
3528 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
3529 1 MyTarget cortex_m3 little tap-disabled
3530 @end verbatim
3532 One member of that list is the @dfn{current target}, which
3533 is implicitly referenced by many commands.
3534 It's the one marked with a @code{*} near the target name.
3535 In particular, memory addresses often refer to the address
3536 space seen by that current target.
3537 Commands like @command{mdw} (memory display words)
3538 and @command{flash erase_address} (erase NOR flash blocks)
3539 are examples; and there are many more.
3541 Several commands let you examine the list of targets:
3543 @deffn Command {target count}
3544 @emph{Note: target numbers are deprecated; don't use them.
3545 They will be removed shortly after August 2010, including this command.
3546 Iterate target using @command{target names}, not by counting.}
3548 Returns the number of targets, @math{N}.
3549 The highest numbered target is @math{N - 1}.
3550 @example
3551 set c [target count]
3552 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
3553 # Assuming you have created this function
3554 print_target_details $x
3555 @}
3556 @end example
3557 @end deffn
3559 @deffn Command {target current}
3560 Returns the name of the current target.
3561 @end deffn
3563 @deffn Command {target names}
3564 Lists the names of all current targets in the list.
3565 @example
3566 foreach t [target names] @{
3567 puts [format "Target: %s\n" $t]
3568 @}
3569 @end example
3570 @end deffn
3572 @deffn Command {target number} number
3573 @emph{Note: target numbers are deprecated; don't use them.
3574 They will be removed shortly after August 2010, including this command.}
3576 The list of targets is numbered starting at zero.
3577 This command returns the name of the target at index @var{number}.
3578 @example
3579 set thename [target number $x]
3580 puts [format "Target %d is: %s\n" $x $thename]
3581 @end example
3582 @end deffn
3584 @c yep, "target list" would have been better.
3585 @c plus maybe "target setdefault".
3587 @deffn Command targets [name]
3588 @emph{Note: the name of this command is plural. Other target
3589 command names are singular.}
3591 With no parameter, this command displays a table of all known
3592 targets in a user friendly form.
3594 With a parameter, this command sets the current target to
3595 the given target with the given @var{name}; this is
3596 only relevant on boards which have more than one target.
3597 @end deffn
3599 @section Target CPU Types and Variants
3600 @cindex target type
3601 @cindex CPU type
3602 @cindex CPU variant
3604 Each target has a @dfn{CPU type}, as shown in the output of
3605 the @command{targets} command. You need to specify that type
3606 when calling @command{target create}.
3607 The CPU type indicates more than just the instruction set.
3608 It also indicates how that instruction set is implemented,
3609 what kind of debug support it integrates,
3610 whether it has an MMU (and if so, what kind),
3611 what core-specific commands may be available
3612 (@pxref{Architecture and Core Commands}),
3613 and more.
3615 For some CPU types, OpenOCD also defines @dfn{variants} which
3616 indicate differences that affect their handling.
3617 For example, a particular implementation bug might need to be
3618 worked around in some chip versions.
3620 It's easy to see what target types are supported,
3621 since there's a command to list them.
3622 However, there is currently no way to list what target variants
3623 are supported (other than by reading the OpenOCD source code).
3625 @anchor{target types}
3626 @deffn Command {target types}
3627 Lists all supported target types.
3628 At this writing, the supported CPU types and variants are:
3630 @itemize @bullet
3631 @item @code{arm11} -- this is a generation of ARMv6 cores
3632 @item @code{arm720t} -- this is an ARMv4 core with an MMU
3633 @item @code{arm7tdmi} -- this is an ARMv4 core
3634 @item @code{arm920t} -- this is an ARMv4 core with an MMU
3635 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
3636 @item @code{arm966e} -- this is an ARMv5 core
3637 @item @code{arm9tdmi} -- this is an ARMv4 core
3638 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
3639 (Support for this is preliminary and incomplete.)
3640 @item @code{cortex_a8} -- this is an ARMv7 core with an MMU
3641 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
3642 compact Thumb2 instruction set.
3643 @item @code{dragonite} -- resembles arm966e
3644 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
3645 (Support for this is still incomplete.)
3646 @item @code{fa526} -- resembles arm920 (w/o Thumb)
3647 @item @code{feroceon} -- resembles arm926
3648 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
3649 @item @code{xscale} -- this is actually an architecture,
3650 not a CPU type. It is based on the ARMv5 architecture.
3651 There are several variants defined:
3652 @itemize @minus
3653 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
3654 @code{pxa27x} ... instruction register length is 7 bits
3655 @item @code{pxa250}, @code{pxa255},
3656 @code{pxa26x} ... instruction register length is 5 bits
3657 @item @code{pxa3xx} ... instruction register length is 11 bits
3658 @end itemize
3659 @end itemize
3660 @end deffn
3662 To avoid being confused by the variety of ARM based cores, remember
3663 this key point: @emph{ARM is a technology licencing company}.
3664 (See: @url{}.)
3665 The CPU name used by OpenOCD will reflect the CPU design that was
3666 licenced, not a vendor brand which incorporates that design.
3667 Name prefixes like arm7, arm9, arm11, and cortex
3668 reflect design generations;
3669 while names like ARMv4, ARMv5, ARMv6, and ARMv7
3670 reflect an architecture version implemented by a CPU design.
3672 @anchor{Target Configuration}
3673 @section Target Configuration
3675 Before creating a ``target'', you must have added its TAP to the scan chain.
3676 When you've added that TAP, you will have a @code{}
3677 which is used to set up the CPU support.
3678 The chip-specific configuration file will normally configure its CPU(s)
3679 right after it adds all of the chip's TAPs to the scan chain.
3681 Although you can set up a target in one step, it's often clearer if you
3682 use shorter commands and do it in two steps: create it, then configure
3683 optional parts.
3684 All operations on the target after it's created will use a new
3685 command, created as part of target creation.
3687 The two main things to configure after target creation are
3688 a work area, which usually has target-specific defaults even
3689 if the board setup code overrides them later;
3690 and event handlers (@pxref{Target Events}), which tend
3691 to be much more board-specific.
3692 The key steps you use might look something like this
3694 @example
3695 target create MyTarget cortex_m3 -chain-position mychip.cpu
3696 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
3697 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
3698 $MyTarget configure -event reset-init @{ myboard_reinit @}
3699 @end example
3701 You should specify a working area if you can; typically it uses some
3702 on-chip SRAM.
3703 Such a working area can speed up many things, including bulk
3704 writes to target memory;
3705 flash operations like checking to see if memory needs to be erased;
3706 GDB memory checksumming;
3707 and more.
3709 @quotation Warning
3710 On more complex chips, the work area can become
3711 inaccessible when application code
3712 (such as an operating system)
3713 enables or disables the MMU.
3714 For example, the particular MMU context used to acess the virtual
3715 address will probably matter ... and that context might not have
3716 easy access to other addresses needed.
3717 At this writing, OpenOCD doesn't have much MMU intelligence.
3718 @end quotation
3720 It's often very useful to define a @code{reset-init} event handler.
3721 For systems that are normally used with a boot loader,
3722 common tasks include updating clocks and initializing memory
3723 controllers.
3724 That may be needed to let you write the boot loader into flash,
3725 in order to ``de-brick'' your board; or to load programs into
3726 external DDR memory without having run the boot loader.
3728 @deffn Command {target create} target_name type configparams...
3729 This command creates a GDB debug target that refers to a specific JTAG tap.
3730 It enters that target into a list, and creates a new
3731 command (@command{@var{target_name}}) which is used for various
3732 purposes including additional configuration.
3734 @itemize @bullet
3735 @item @var{target_name} ... is the name of the debug target.
3736 By convention this should be the same as the @emph{}
3737 of the TAP associated with this target, which must be specified here
3738 using the @code{-chain-position @var{}} configparam.
3740 This name is also used to create the target object command,
3741 referred to here as @command{$target_name},
3742 and in other places the target needs to be identified.
3743 @item @var{type} ... specifies the target type. @xref{target types}.
3744 @item @var{configparams} ... all parameters accepted by
3745 @command{$target_name configure} are permitted.
3746 If the target is big-endian, set it here with @code{-endian big}.
3747 If the variant matters, set it here with @code{-variant}.
3749 You @emph{must} set the @code{-chain-position @var{}} here.
3750 @end itemize
3751 @end deffn
3753 @deffn Command {$target_name configure} configparams...
3754 The options accepted by this command may also be
3755 specified as parameters to @command{target create}.
3756 Their values can later be queried one at a time by
3757 using the @command{$target_name cget} command.
3759 @emph{Warning:} changing some of these after setup is dangerous.
3760 For example, moving a target from one TAP to another;
3761 and changing its endianness or variant.
3763 @itemize @bullet
3765 @item @code{-chain-position} @var{} -- names the TAP
3766 used to access this target.
3768 @item @code{-endian} (@option{big}|@option{little}) -- specifies
3769 whether the CPU uses big or little endian conventions
3771 @item @code{-event} @var{event_name} @var{event_body} --
3772 @xref{Target Events}.
3773 Note that this updates a list of named event handlers.
3774 Calling this twice with two different event names assigns
3775 two different handlers, but calling it twice with the
3776 same event name assigns only one handler.
3778 @item @code{-variant} @var{name} -- specifies a variant of the target,
3779 which OpenOCD needs to know about.
3781 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
3782 whether the work area gets backed up; by default,
3783 @emph{it is not backed up.}
3784 When possible, use a working_area that doesn't need to be backed up,
3785 since performing a backup slows down operations.
3786 For example, the beginning of an SRAM block is likely to
3787 be used by most build systems, but the end is often unused.
3789 @item @code{-work-area-size} @var{size} -- specify work are size,
3790 in bytes. The same size applies regardless of whether its physical
3791 or virtual address is being used.
3793 @item @code{-work-area-phys} @var{address} -- set the work area
3794 base @var{address} to be used when no MMU is active.
3796 @item @code{-work-area-virt} @var{address} -- set the work area
3797 base @var{address} to be used when an MMU is active.
3798 @emph{Do not specify a value for this except on targets with an MMU.}
3799 The value should normally correspond to a static mapping for the
3800 @code{-work-area-phys} address, set up by the current operating system.
3802 @end itemize
3803 @end deffn
3805 @section Other $target_name Commands
3806 @cindex object command
3808 The Tcl/Tk language has the concept of object commands,
3809 and OpenOCD adopts that same model for targets.
3811 A good Tk example is a on screen button.
3812 Once a button is created a button
3813 has a name (a path in Tk terms) and that name is useable as a first
3814 class command. For example in Tk, one can create a button and later
3815 configure it like this:
3817 @example
3818 # Create
3819 button .foobar -background red -command @{ foo @}
3820 # Modify
3821 .foobar configure -foreground blue
3822 # Query
3823 set x [.foobar cget -background]
3824 # Report
3825 puts [format "The button is %s" $x]
3826 @end example
3828 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
3829 button, and its object commands are invoked the same way.
3831 @example
3832 str912.cpu mww 0x1234 0x42
3833 omap3530.cpu mww 0x5555 123
3834 @end example
3836 The commands supported by OpenOCD target objects are:
3838 @deffn Command {$target_name arp_examine}
3839 @deffnx Command {$target_name arp_halt}
3840 @deffnx Command {$target_name arp_poll}
3841 @deffnx Command {$target_name arp_reset}
3842 @deffnx Command {$target_name arp_waitstate}
3843 Internal OpenOCD scripts (most notably @file{startup.tcl})
3844 use these to deal with specific reset cases.
3845 They are not otherwise documented here.
3846 @end deffn
3848 @deffn Command {$target_name array2mem} arrayname width address count
3849 @deffnx Command {$target_name mem2array} arrayname width address count
3850 These provide an efficient script-oriented interface to memory.
3851 The @code{array2mem} primitive writes bytes, halfwords, or words;
3852 while @code{mem2array} reads them.
3853 In both cases, the TCL side uses an array, and
3854 the target side uses raw memory.
3856 The efficiency comes from enabling the use of
3857 bulk JTAG data transfer operations.
3858 The script orientation comes from working with data
3859 values that are packaged for use by TCL scripts;
3860 @command{mdw} type primitives only print data they retrieve,
3861 and neither store nor return those values.
3863 @itemize
3864 @item @var{arrayname} ... is the name of an array variable
3865 @item @var{width} ... is 8/16/32 - indicating the memory access size
3866 @item @var{address} ... is the target memory address
3867 @item @var{count} ... is the number of elements to process
3868 @end itemize
3869 @end deffn
3871 @deffn Command {$target_name cget} queryparm
3872 Each configuration parameter accepted by
3873 @command{$target_name configure}
3874 can be individually queried, to return its current value.
3875 The @var{queryparm} is a parameter name
3876 accepted by that command, such as @code{-work-area-phys}.
3877 There are a few special cases:
3879 @itemize @bullet
3880 @item @code{-event} @var{event_name} -- returns the handler for the
3881 event named @var{event_name}.
3882 This is a special case because setting a handler requires
3883 two parameters.
3884 @item @code{-type} -- returns the target type.
3885 This is a special case because this is set using
3886 @command{target create} and can't be changed
3887 using @command{$target_name configure}.
3888 @end itemize
3890 For example, if you wanted to summarize information about
3891 all the targets you might use something like this:
3893 @example
3894 foreach name [target names] @{
3895 set y [$name cget -endian]
3896 set z [$name cget -type]
3897 puts [format "Chip %d is %s, Endian: %s, type: %s" \
3898 $x $name $y $z]
3899 @}
3900 @end example
3901 @end deffn
3903 @anchor{target curstate}
3904 @deffn Command {$target_name curstate}
3905 Displays the current target state:
3906 @code{debug-running},
3907 @code{halted},
3908 @code{reset},
3909 @code{running}, or @code{unknown}.
3910 (Also, @pxref{Event Polling}.)
3911 @end deffn
3913 @deffn Command {$target_name eventlist}
3914 Displays a table listing all event handlers
3915 currently associated with this target.
3916 @xref{Target Events}.
3917 @end deffn
3919 @deffn Command {$target_name invoke-event} event_name
3920 Invokes the handler for the event named @var{event_name}.
3921 (This is primarily intended for use by OpenOCD framework
3922 code, for example by the reset code in @file{startup.tcl}.)
3923 @end deffn
3925 @deffn Command {$target_name mdw} addr [count]
3926 @deffnx Command {$target_name mdh} addr [count]
3927 @deffnx Command {$target_name mdb} addr [count]
3928 Display contents of address @var{addr}, as
3929 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
3930 or 8-bit bytes (@command{mdb}).
3931 If @var{count} is specified, displays that many units.
3932 (If you want to manipulate the data instead of displaying it,
3933 see the @code{mem2array} primitives.)
3934 @end deffn
3936 @deffn Command {$target_name mww} addr word
3937 @deffnx Command {$target_name mwh} addr halfword
3938 @deffnx Command {$target_name mwb} addr byte
3939 Writes the specified @var{word} (32 bits),
3940 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3941 at the specified address @var{addr}.
3942 @end deffn
3944 @anchor{Target Events}
3945 @section Target Events
3946 @cindex target events
3947 @cindex events
3948 At various times, certain things can happen, or you want them to happen.
3949 For example:
3950 @itemize @bullet
3951 @item What should happen when GDB connects? Should your target reset?
3952 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
3953 @item Is using SRST appropriate (and possible) on your system?
3954 Or instead of that, do you need to issue JTAG commands to trigger reset?
3955 SRST usually resets everything on the scan chain, which can be inappropriate.
3956 @item During reset, do you need to write to certain memory locations
3957 to set up system clocks or
3958 to reconfigure the SDRAM?
3959 How about configuring the watchdog timer, or other peripherals,
3960 to stop running while you hold the core stopped for debugging?
3961 @end itemize
3963 All of the above items can be addressed by target event handlers.
3964 These are set up by @command{$target_name configure -event} or
3965 @command{target create ... -event}.
3967 The programmer's model matches the @code{-command} option used in Tcl/Tk
3968 buttons and events. The two examples below act the same, but one creates
3969 and invokes a small procedure while the other inlines it.
3971 @example
3972 proc my_attach_proc @{ @} @{
3973 echo "Reset..."
3974 reset halt
3975 @}
3976 mychip.cpu configure -event gdb-attach my_attach_proc
3977 mychip.cpu configure -event gdb-attach @{
3978 echo "Reset..."
3979 # To make flash probe and gdb load to flash work we need a reset init.
3980 reset init
3981 @}
3982 @end example
3984 The following target events are defined:
3986 @itemize @bullet
3987 @item @b{debug-halted}
3988 @* The target has halted for debug reasons (i.e.: breakpoint)
3989 @item @b{debug-resumed}
3990 @* The target has resumed (i.e.: gdb said run)
3991 @item @b{early-halted}
3992 @* Occurs early in the halt process
3993 @ignore
3994 @item @b{examine-end}
3995 @* Currently not used (goal: when JTAG examine completes)
3996 @item @b{examine-start}
3997 @* Currently not used (goal: when JTAG examine starts)
3998 @end ignore
3999 @item @b{gdb-attach}
4000 @* When GDB connects. This is before any communication with the target, so this
4001 can be used to set up the target so it is possible to probe flash. Probing flash
4002 is necessary during gdb connect if gdb load is to write the image to flash. Another
4003 use of the flash memory map is for GDB to automatically hardware/software breakpoints
4004 depending on whether the breakpoint is in RAM or read only memory.
4005 @item @b{gdb-detach}
4006 @* When GDB disconnects
4007 @item @b{gdb-end}
4008 @* When the target has halted and GDB is not doing anything (see early halt)
4009 @item @b{gdb-flash-erase-start}
4010 @* Before the GDB flash process tries to erase the flash
4011 @item @b{gdb-flash-erase-end}
4012 @* After the GDB flash process has finished erasing the flash
4013 @item @b{gdb-flash-write-start}
4014 @* Before GDB writes to the flash
4015 @item @b{gdb-flash-write-end}
4016 @* After GDB writes to the flash
4017 @item @b{gdb-start}
4018 @* Before the target steps, gdb is trying to start/resume the target
4019 @item @b{halted}
4020 @* The target has halted
4021 @ignore
4022 @item @b{old-gdb_program_config}
4023 @* DO NOT USE THIS: Used internally
4024 @item @b{old-pre_resume}
4025 @* DO NOT USE THIS: Used internally
4026 @end ignore
4027 @item @b{reset-assert-pre}
4028 @* Issued as part of @command{reset} processing
4029 after @command{reset_init} was triggered
4030 but before either SRST alone is re-asserted on the scan chain,
4031 or @code{reset-assert} is triggered.
4032 @item @b{reset-assert}
4033 @* Issued as part of @command{reset} processing
4034 after @command{reset-assert-pre} was triggered.
4035 When such a handler is present, cores which support this event will use
4036 it instead of asserting SRST.
4037 This support is essential for debugging with JTAG interfaces which
4038 don't include an SRST line (JTAG doesn't require SRST), and for
4039 selective reset on scan chains that have multiple targets.
4040 @item @b{reset-assert-post}
4041 @* Issued as part of @command{reset} processing
4042 after @code{reset-assert} has been triggered.
4043 or the target asserted SRST on the entire scan chain.
4044 @item @b{reset-deassert-pre}
4045 @* Issued as part of @command{reset} processing
4046 after @code{reset-assert-post} has been triggered.
4047 @item @b{reset-deassert-post}
4048 @* Issued as part of @command{reset} processing
4049 after @code{reset-deassert-pre} has been triggered
4050 and (if the target is using it) after SRST has been
4051 released on the scan chain.
4052 @item @b{reset-end}
4053 @* Issued as the final step in @command{reset} processing.
4054 @ignore
4055 @item @b{reset-halt-post}
4056 @* Currently not used
4057 @item @b{reset-halt-pre}
4058 @* Currently not used
4059 @end ignore
4060 @item @b{reset-init}
4061 @* Used by @b{reset init} command for board-specific initialization.
4062 This event fires after @emph{reset-deassert-post}.
4064 This is where you would configure PLLs and clocking, set up DRAM so
4065 you can download programs that don't fit in on-chip SRAM, set up pin
4066 multiplexing, and so on.
4067 (You may be able to switch to a fast JTAG clock rate here, after
4068 the target clocks are fully set up.)
4069 @item @b{reset-start}
4070 @* Issued as part of @command{reset} processing
4071 before @command{reset_init} is called.
4073 This is the most robust place to use @command{jtag_rclk}
4074 or @command{adapter_khz} to switch to a low JTAG clock rate,
4075 when reset disables PLLs needed to use a fast clock.
4076 @ignore
4077 @item @b{reset-wait-pos}
4078 @* Currently not used
4079 @item @b{reset-wait-pre}
4080 @* Currently not used
4081 @end ignore
4082 @item @b{resume-start}
4083 @* Before any target is resumed
4084 @item @b{resume-end}
4085 @* After all targets have resumed
4086 @item @b{resume-ok}
4087 @* Success
4088 @item @b{resumed}
4089 @* Target has resumed
4090 @end itemize
4093 @node Flash Commands
4094 @chapter Flash Commands
4096 OpenOCD has different commands for NOR and NAND flash;
4097 the ``flash'' command works with NOR flash, while
4098 the ``nand'' command works with NAND flash.
4099 This partially reflects different hardware technologies:
4100 NOR flash usually supports direct CPU instruction and data bus access,
4101 while data from a NAND flash must be copied to memory before it can be
4102 used. (SPI flash must also be copied to memory before use.)
4103 However, the documentation also uses ``flash'' as a generic term;
4104 for example, ``Put flash configuration in board-specific files''.
4106 Flash Steps:
4107 @enumerate
4108 @item Configure via the command @command{flash bank}
4109 @* Do this in a board-specific configuration file,
4110 passing parameters as needed by the driver.
4111 @item Operate on the flash via @command{flash subcommand}
4112 @* Often commands to manipulate the flash are typed by a human, or run
4113 via a script in some automated way. Common tasks include writing a
4114 boot loader, operating system, or other data.
4115 @item GDB Flashing
4116 @* Flashing via GDB requires the flash be configured via ``flash
4117 bank'', and the GDB flash features be enabled.
4118 @xref{GDB Configuration}.
4119 @end enumerate
4121 Many CPUs have the ablity to ``boot'' from the first flash bank.
4122 This means that misprogramming that bank can ``brick'' a system,
4123 so that it can't boot.
4124 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4125 board by (re)installing working boot firmware.
4127 @anchor{NOR Configuration}
4128 @section Flash Configuration Commands
4129 @cindex flash configuration
4131 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4132 Configures a flash bank which provides persistent storage
4133 for addresses from @math{base} to @math{base + size - 1}.
4134 These banks will often be visible to GDB through the target's memory map.
4135 In some cases, configuring a flash bank will activate extra commands;
4136 see the driver-specific documentation.
4138 @itemize @bullet
4139 @item @var{name} ... may be used to reference the flash bank
4140 in other flash commands. A number is also available.
4141 @item @var{driver} ... identifies the controller driver
4142 associated with the flash bank being declared.
4143 This is usually @code{cfi} for external flash, or else
4144 the name of a microcontroller with embedded flash memory.
4145 @xref{Flash Driver List}.
4146 @item @var{base} ... Base address of the flash chip.
4147 @item @var{size} ... Size of the chip, in bytes.
4148 For some drivers, this value is detected from the hardware.
4149 @item @var{chip_width} ... Width of the flash chip, in bytes;
4150 ignored for most microcontroller drivers.
4151 @item @var{bus_width} ... Width of the data bus used to access the
4152 chip, in bytes; ignored for most microcontroller drivers.
4153 @item @var{target} ... Names the target used to issue
4154 commands to the flash controller.
4155 @comment Actually, it's currently a controller-specific parameter...
4156 @item @var{driver_options} ... drivers may support, or require,
4157 additional parameters. See the driver-specific documentation
4158 for more information.
4159 @end itemize
4160 @quotation Note
4161 This command is not available after OpenOCD initialization has completed.
4162 Use it in board specific configuration files, not interactively.
4163 @end quotation
4164 @end deffn
4166 @comment the REAL name for this command is "ocd_flash_banks"
4167 @comment less confusing would be: "flash list" (like "nand list")
4168 @deffn Command {flash banks}
4169 Prints a one-line summary of each device that was
4170 declared using @command{flash bank}, numbered from zero.
4171 Note that this is the @emph{plural} form;
4172 the @emph{singular} form is a very different command.
4173 @end deffn
4175 @deffn Command {flash list}
4176 Retrieves a list of associative arrays for each device that was
4177 declared using @command{flash bank}, numbered from zero.
4178 This returned list can be manipulated easily from within scripts.
4179 @end deffn
4181 @deffn Command {flash probe} num
4182 Identify the flash, or validate the parameters of the configured flash. Operation
4183 depends on the flash type.
4184 The @var{num} parameter is a value shown by @command{flash banks}.
4185 Most flash commands will implicitly @emph{autoprobe} the bank;
4186 flash drivers can distinguish between probing and autoprobing,
4187 but most don't bother.
4188 @end deffn
4190 @section Erasing, Reading, Writing to Flash