[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
82 * TFTP:: TFTP
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
95 @end menu
97 @node About
98 @unnumbered About
99 @cindex about
101 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
102 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
105 around the world.
107 @section What is OpenOCD?
108 @cindex TAP
109 @cindex JTAG
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
113 devices.
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board connect directly to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
140 scan operations.
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD supports only
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
154 USB-based, parallel port-based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
159 (Stellaris LM3, ST STM32 and Energy Micro EFM32) and Intel Quark (x10xx)
160 based cores to be debugged via the GDB protocol.
162 @b{Flash Programming:} Flash writing is supported for external
163 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{http://openocd.org/}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{http://openocd.org/doc/html/index.html}
182 PDF form is likewise published at:
184 @uref{http://openocd.org/doc/pdf/openocd.pdf}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
203 @section OpenOCD IRC
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
208 @node Developers
209 @chapter OpenOCD Developer Resources
210 @cindex developers
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD Git Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a Git repository hosted at SourceForge. The repository URL is:
225 @uref{git://git.code.sf.net/p/openocd/code}
227 or via http
229 @uref{http://git.code.sf.net/p/openocd/code}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{http://repo.or.cz/r/openocd.git}
235 With standard Git tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a Git client:
241 @uref{http://repo.or.cz/w/openocd.git}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{http://openocd.org/doc/doxygen/html/index.html}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration at the top of the source tree.
264 @section Gerrit Review System
266 All changes in the OpenOCD Git repository go through the web-based Gerrit
267 Code Review System:
269 @uref{http://openocd.zylin.com/}
271 After a one-time registration and repository setup, anyone can push commits
272 from their local Git repository directly into Gerrit.
273 All users and developers are encouraged to review, test, discuss and vote
274 for changes in Gerrit. The feedback provides the basis for a maintainer to
275 eventually submit the change to the main Git repository.
277 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
278 Developer Manual, contains basic information about how to connect a
279 repository to Gerrit, prepare and push patches. Patch authors are expected to
280 maintain their changes while they're in Gerrit, respond to feedback and if
281 necessary rework and push improved versions of the change.
283 @section OpenOCD Developer Mailing List
285 The OpenOCD Developer Mailing List provides the primary means of
286 communication between developers:
288 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
290 @section OpenOCD Bug Tracker
292 The OpenOCD Bug Tracker is hosted on SourceForge:
294 @uref{http://bugs.openocd.org/}
297 @node Debug Adapter Hardware
298 @chapter Debug Adapter Hardware
299 @cindex dongles
300 @cindex FTDI
301 @cindex wiggler
302 @cindex zy1000
303 @cindex printer port
304 @cindex USB Adapter
305 @cindex RTCK
307 Defined: @b{dongle}: A small device that plugs into a computer and serves as
308 an adapter .... [snip]
310 In the OpenOCD case, this generally refers to @b{a small adapter} that
311 attaches to your computer via USB or the parallel port. One
312 exception is the Ultimate Solutions ZY1000, packaged as a small box you
313 attach via an ethernet cable. The ZY1000 has the advantage that it does not
314 require any drivers to be installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built-in relay to power cycle targets remotely.
319 @section Choosing a Dongle
321 There are several things you should keep in mind when choosing a dongle.
323 @enumerate
324 @item @b{Transport} Does it support the kind of communication that you need?
325 OpenOCD focusses mostly on JTAG. Your version may also support
326 other ways to communicate with target devices.
327 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
328 Does your dongle support it? You might need a level converter.
329 @item @b{Pinout} What pinout does your target board use?
330 Does your dongle support it? You may be able to use jumper
331 wires, or an "octopus" connector, to convert pinouts.
332 @item @b{Connection} Does your computer have the USB, parallel, or
333 Ethernet port needed?
334 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
335 RTCK support (also known as ``adaptive clocking'')?
336 @end enumerate
338 @section Stand-alone JTAG Probe
340 The ZY1000 from Ultimate Solutions is technically not a dongle but a
341 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
342 running on the developer's host computer.
343 Once installed on a network using DHCP or a static IP assignment, users can
344 access the ZY1000 probe locally or remotely from any host with access to the
345 IP address assigned to the probe.
346 The ZY1000 provides an intuitive web interface with direct access to the
347 OpenOCD debugger.
348 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
349 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
350 the target.
351 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
352 to power cycle the target remotely.
354 For more information, visit:
356 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/210-zylin-zy1000-main}
358 @section USB FT2232 Based
360 There are many USB JTAG dongles on the market, many of them based
361 on a chip from ``Future Technology Devices International'' (FTDI)
362 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
363 See: @url{http://www.ftdichip.com} for more information.
364 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
365 chips started to become available in JTAG adapters. Around 2012, a new
366 variant appeared - FT232H - this is a single-channel version of FT2232H.
367 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
368 clocking.)
370 The FT2232 chips are flexible enough to support some other
371 transport options, such as SWD or the SPI variants used to
372 program some chips. They have two communications channels,
373 and one can be used for a UART adapter at the same time the
374 other one is used to provide a debug adapter.
376 Also, some development boards integrate an FT2232 chip to serve as
377 a built-in low-cost debug adapter and USB-to-serial solution.
379 @itemize @bullet
380 @item @b{usbjtag}
381 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
382 @item @b{jtagkey}
383 @* See: @url{http://www.amontec.com/jtagkey.shtml}
384 @item @b{jtagkey2}
385 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
386 @item @b{oocdlink}
387 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
388 @item @b{signalyzer}
389 @* See: @url{http://www.signalyzer.com}
390 @item @b{Stellaris Eval Boards}
391 @* See: @url{http://www.ti.com} - The Stellaris eval boards
392 bundle FT2232-based JTAG and SWD support, which can be used to debug
393 the Stellaris chips. Using separate JTAG adapters is optional.
394 These boards can also be used in a "pass through" mode as JTAG adapters
395 to other target boards, disabling the Stellaris chip.
396 @item @b{TI/Luminary ICDI}
397 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
398 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
399 Evaluation Kits. Like the non-detachable FT2232 support on the other
400 Stellaris eval boards, they can be used to debug other target boards.
401 @item @b{olimex-jtag}
402 @* See: @url{http://www.olimex.com}
403 @item @b{Flyswatter/Flyswatter2}
404 @* See: @url{http://www.tincantools.com}
405 @item @b{turtelizer2}
406 @* See:
407 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
408 @url{http://www.ethernut.de}
409 @item @b{comstick}
410 @* Link: @url{http://www.hitex.com/index.php?id=383}
411 @item @b{stm32stick}
412 @* Link @url{http://www.hitex.com/stm32-stick}
413 @item @b{axm0432_jtag}
414 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
415 to be available anymore as of April 2012.
416 @item @b{cortino}
417 @* Link @url{http://www.hitex.com/index.php?id=cortino}
418 @item @b{dlp-usb1232h}
419 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
420 @item @b{digilent-hs1}
421 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
422 @item @b{opendous}
423 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
424 (OpenHardware).
425 @item @b{JTAG-lock-pick Tiny 2}
426 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
428 @item @b{GW16042}
429 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
430 FT2232H-based
432 @end itemize
433 @section USB-JTAG / Altera USB-Blaster compatibles
435 These devices also show up as FTDI devices, but are not
436 protocol-compatible with the FT2232 devices. They are, however,
437 protocol-compatible among themselves. USB-JTAG devices typically consist
438 of a FT245 followed by a CPLD that understands a particular protocol,
439 or emulates this protocol using some other hardware.
441 They may appear under different USB VID/PID depending on the particular
442 product. The driver can be configured to search for any VID/PID pair
443 (see the section on driver commands).
445 @itemize
446 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
447 @* Link: @url{http://ixo-jtag.sourceforge.net/}
448 @item @b{Altera USB-Blaster}
449 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
450 @end itemize
452 @section USB JLINK based
453 There are several OEM versions of the Segger @b{JLINK} adapter. It is
454 an example of a micro controller based JTAG adapter, it uses an
455 AT91SAM764 internally.
457 @itemize @bullet
458 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
459 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
460 @item @b{SEGGER JLINK}
461 @* Link: @url{http://www.segger.com/jlink.html}
462 @item @b{IAR J-Link}
463 @* Link: @url{http://www.iar.com/en/products/hardware-debug-probes/iar-j-link/}
464 @end itemize
466 @section USB RLINK based
467 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
468 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
469 SWD and not JTAG, thus not supported.
471 @itemize @bullet
472 @item @b{Raisonance RLink}
473 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
474 @item @b{STM32 Primer}
475 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
476 @item @b{STM32 Primer2}
477 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
478 @end itemize
480 @section USB ST-LINK based
481 ST Micro has an adapter called @b{ST-LINK}.
482 They only work with ST Micro chips, notably STM32 and STM8.
484 @itemize @bullet
485 @item @b{ST-LINK}
486 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
487 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
488 @item @b{ST-LINK/V2}
489 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
490 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
491 @end itemize
493 For info the original ST-LINK enumerates using the mass storage usb class; however,
494 its implementation is completely broken. The result is this causes issues under Linux.
495 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
496 @itemize @bullet
497 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
498 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
499 @end itemize
501 @section USB TI/Stellaris ICDI based
502 Texas Instruments has an adapter called @b{ICDI}.
503 It is not to be confused with the FTDI based adapters that were originally fitted to their
504 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
506 @section USB CMSIS-DAP based
507 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
508 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
510 @section USB Other
511 @itemize @bullet
512 @item @b{USBprog}
513 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
515 @item @b{USB - Presto}
516 @* Link: @url{http://tools.asix.net/prg_presto.htm}
518 @item @b{Versaloon-Link}
519 @* Link: @url{http://www.versaloon.com}
521 @item @b{ARM-JTAG-EW}
522 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
524 @item @b{Buspirate}
525 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
527 @item @b{opendous}
528 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
530 @item @b{estick}
531 @* Link: @url{http://code.google.com/p/estick-jtag/}
533 @item @b{Keil ULINK v1}
534 @* Link: @url{http://www.keil.com/ulink1/}
535 @end itemize
537 @section IBM PC Parallel Printer Port Based
539 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
540 and the Macraigor Wiggler. There are many clones and variations of
541 these on the market.
543 Note that parallel ports are becoming much less common, so if you
544 have the choice you should probably avoid these adapters in favor
545 of USB-based ones.
547 @itemize @bullet
549 @item @b{Wiggler} - There are many clones of this.
550 @* Link: @url{http://www.macraigor.com/wiggler.htm}
552 @item @b{DLC5} - From XILINX - There are many clones of this
553 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
554 produced, PDF schematics are easily found and it is easy to make.
556 @item @b{Amontec - JTAG Accelerator}
557 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
559 @item @b{Wiggler2}
560 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
562 @item @b{Wiggler_ntrst_inverted}
563 @* Yet another variation - See the source code, src/jtag/parport.c
565 @item @b{old_amt_wiggler}
566 @* Unknown - probably not on the market today
568 @item @b{arm-jtag}
569 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
571 @item @b{chameleon}
572 @* Link: @url{http://www.amontec.com/chameleon.shtml}
574 @item @b{Triton}
575 @* Unknown.
577 @item @b{Lattice}
578 @* ispDownload from Lattice Semiconductor
579 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
581 @item @b{flashlink}
582 @* From ST Microsystems;
583 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
585 @end itemize
587 @section Other...
588 @itemize @bullet
590 @item @b{ep93xx}
591 @* An EP93xx based Linux machine using the GPIO pins directly.
593 @item @b{at91rm9200}
594 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
596 @item @b{bcm2835gpio}
597 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
599 @item @b{jtag_vpi}
600 @* A JTAG driver acting as a client for the JTAG VPI server interface.
601 @* Link: @url{http://github.com/fjullien/jtag_vpi}
603 @end itemize
605 @node About Jim-Tcl
606 @chapter About Jim-Tcl
607 @cindex Jim-Tcl
608 @cindex tcl
610 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
611 This programming language provides a simple and extensible
612 command interpreter.
614 All commands presented in this Guide are extensions to Jim-Tcl.
615 You can use them as simple commands, without needing to learn
616 much of anything about Tcl.
617 Alternatively, you can write Tcl programs with them.
619 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
620 There is an active and responsive community, get on the mailing list
621 if you have any questions. Jim-Tcl maintainers also lurk on the
622 OpenOCD mailing list.
624 @itemize @bullet
625 @item @b{Jim vs. Tcl}
626 @* Jim-Tcl is a stripped down version of the well known Tcl language,
627 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
628 fewer features. Jim-Tcl is several dozens of .C files and .H files and
629 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
630 4.2 MB .zip file containing 1540 files.
632 @item @b{Missing Features}
633 @* Our practice has been: Add/clone the real Tcl feature if/when
634 needed. We welcome Jim-Tcl improvements, not bloat. Also there
635 are a large number of optional Jim-Tcl features that are not
636 enabled in OpenOCD.
638 @item @b{Scripts}
639 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
640 command interpreter today is a mixture of (newer)
641 Jim-Tcl commands, and the (older) original command interpreter.
643 @item @b{Commands}
644 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
645 can type a Tcl for() loop, set variables, etc.
646 Some of the commands documented in this guide are implemented
647 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
649 @item @b{Historical Note}
650 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
651 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
652 as a Git submodule, which greatly simplified upgrading Jim-Tcl
653 to benefit from new features and bugfixes in Jim-Tcl.
655 @item @b{Need a crash course in Tcl?}
656 @*@xref{Tcl Crash Course}.
657 @end itemize
659 @node Running
660 @chapter Running
661 @cindex command line options
662 @cindex logfile
663 @cindex directory search
665 Properly installing OpenOCD sets up your operating system to grant it access
666 to the debug adapters. On Linux, this usually involves installing a file
667 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
668 that works for many common adapters is shipped with OpenOCD in the
669 @file{contrib} directory. MS-Windows needs
670 complex and confusing driver configuration for every peripheral. Such issues
671 are unique to each operating system, and are not detailed in this User's Guide.
673 Then later you will invoke the OpenOCD server, with various options to
674 tell it how each debug session should work.
675 The @option{--help} option shows:
676 @verbatim
677 bash$ openocd --help
679 --help | -h display this help
680 --version | -v display OpenOCD version
681 --file | -f use configuration file <name>
682 --search | -s dir to search for config files and scripts
683 --debug | -d set debug level <0-3>
684 --log_output | -l redirect log output to file <name>
685 --command | -c run <command>
686 @end verbatim
688 If you don't give any @option{-f} or @option{-c} options,
689 OpenOCD tries to read the configuration file @file{openocd.cfg}.
690 To specify one or more different
691 configuration files, use @option{-f} options. For example:
693 @example
694 openocd -f config1.cfg -f config2.cfg -f config3.cfg
695 @end example
697 Configuration files and scripts are searched for in
698 @enumerate
699 @item the current directory,
700 @item any search dir specified on the command line using the @option{-s} option,
701 @item any search dir specified using the @command{add_script_search_dir} command,
702 @item @file{$HOME/.openocd} (not on Windows),
703 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
704 @item the site wide script library @file{$pkgdatadir/site} and
705 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
706 @end enumerate
707 The first found file with a matching file name will be used.
709 @quotation Note
710 Don't try to use configuration script names or paths which
711 include the "#" character. That character begins Tcl comments.
712 @end quotation
714 @section Simple setup, no customization
716 In the best case, you can use two scripts from one of the script
717 libraries, hook up your JTAG adapter, and start the server ... and
718 your JTAG setup will just work "out of the box". Always try to
719 start by reusing those scripts, but assume you'll need more
720 customization even if this works. @xref{OpenOCD Project Setup}.
722 If you find a script for your JTAG adapter, and for your board or
723 target, you may be able to hook up your JTAG adapter then start
724 the server with some variation of one of the following:
726 @example
727 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
728 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
729 @end example
731 You might also need to configure which reset signals are present,
732 using @option{-c 'reset_config trst_and_srst'} or something similar.
733 If all goes well you'll see output something like
735 @example
736 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
737 For bug reports, read
738 http://openocd.org/doc/doxygen/bugs.html
739 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
740 (mfg: 0x23b, part: 0xba00, ver: 0x3)
741 @end example
743 Seeing that "tap/device found" message, and no warnings, means
744 the JTAG communication is working. That's a key milestone, but
745 you'll probably need more project-specific setup.
747 @section What OpenOCD does as it starts
749 OpenOCD starts by processing the configuration commands provided
750 on the command line or, if there were no @option{-c command} or
751 @option{-f file.cfg} options given, in @file{openocd.cfg}.
752 @xref{configurationstage,,Configuration Stage}.
753 At the end of the configuration stage it verifies the JTAG scan
754 chain defined using those commands; your configuration should
755 ensure that this always succeeds.
756 Normally, OpenOCD then starts running as a daemon.
757 Alternatively, commands may be used to terminate the configuration
758 stage early, perform work (such as updating some flash memory),
759 and then shut down without acting as a daemon.
761 Once OpenOCD starts running as a daemon, it waits for connections from
762 clients (Telnet, GDB, Other) and processes the commands issued through
763 those channels.
765 If you are having problems, you can enable internal debug messages via
766 the @option{-d} option.
768 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
769 @option{-c} command line switch.
771 To enable debug output (when reporting problems or working on OpenOCD
772 itself), use the @option{-d} command line switch. This sets the
773 @option{debug_level} to "3", outputting the most information,
774 including debug messages. The default setting is "2", outputting only
775 informational messages, warnings and errors. You can also change this
776 setting from within a telnet or gdb session using @command{debug_level<n>}
777 (@pxref{debuglevel,,debug_level}).
779 You can redirect all output from the daemon to a file using the
780 @option{-l <logfile>} switch.
782 Note! OpenOCD will launch the GDB & telnet server even if it can not
783 establish a connection with the target. In general, it is possible for
784 the JTAG controller to be unresponsive until the target is set up
785 correctly via e.g. GDB monitor commands in a GDB init script.
787 @node OpenOCD Project Setup
788 @chapter OpenOCD Project Setup
790 To use OpenOCD with your development projects, you need to do more than
791 just connect the JTAG adapter hardware (dongle) to your development board
792 and start the OpenOCD server.
793 You also need to configure your OpenOCD server so that it knows
794 about your adapter and board, and helps your work.
795 You may also want to connect OpenOCD to GDB, possibly
796 using Eclipse or some other GUI.
798 @section Hooking up the JTAG Adapter
800 Today's most common case is a dongle with a JTAG cable on one side
801 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
802 and a USB cable on the other.
803 Instead of USB, some cables use Ethernet;
804 older ones may use a PC parallel port, or even a serial port.
806 @enumerate
807 @item @emph{Start with power to your target board turned off},
808 and nothing connected to your JTAG adapter.
809 If you're particularly paranoid, unplug power to the board.
810 It's important to have the ground signal properly set up,
811 unless you are using a JTAG adapter which provides
812 galvanic isolation between the target board and the
813 debugging host.
815 @item @emph{Be sure it's the right kind of JTAG connector.}
816 If your dongle has a 20-pin ARM connector, you need some kind
817 of adapter (or octopus, see below) to hook it up to
818 boards using 14-pin or 10-pin connectors ... or to 20-pin
819 connectors which don't use ARM's pinout.
821 In the same vein, make sure the voltage levels are compatible.
822 Not all JTAG adapters have the level shifters needed to work
823 with 1.2 Volt boards.
825 @item @emph{Be certain the cable is properly oriented} or you might
826 damage your board. In most cases there are only two possible
827 ways to connect the cable.
828 Connect the JTAG cable from your adapter to the board.
829 Be sure it's firmly connected.
831 In the best case, the connector is keyed to physically
832 prevent you from inserting it wrong.
833 This is most often done using a slot on the board's male connector
834 housing, which must match a key on the JTAG cable's female connector.
835 If there's no housing, then you must look carefully and
836 make sure pin 1 on the cable hooks up to pin 1 on the board.
837 Ribbon cables are frequently all grey except for a wire on one
838 edge, which is red. The red wire is pin 1.
840 Sometimes dongles provide cables where one end is an ``octopus'' of
841 color coded single-wire connectors, instead of a connector block.
842 These are great when converting from one JTAG pinout to another,
843 but are tedious to set up.
844 Use these with connector pinout diagrams to help you match up the
845 adapter signals to the right board pins.
847 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
848 A USB, parallel, or serial port connector will go to the host which
849 you are using to run OpenOCD.
850 For Ethernet, consult the documentation and your network administrator.
852 For USB-based JTAG adapters you have an easy sanity check at this point:
853 does the host operating system see the JTAG adapter? If you're running
854 Linux, try the @command{lsusb} command. If that host is an
855 MS-Windows host, you'll need to install a driver before OpenOCD works.
857 @item @emph{Connect the adapter's power supply, if needed.}
858 This step is primarily for non-USB adapters,
859 but sometimes USB adapters need extra power.
861 @item @emph{Power up the target board.}
862 Unless you just let the magic smoke escape,
863 you're now ready to set up the OpenOCD server
864 so you can use JTAG to work with that board.
866 @end enumerate
868 Talk with the OpenOCD server using
869 telnet (@code{telnet localhost 4444} on many systems) or GDB.
870 @xref{GDB and OpenOCD}.
872 @section Project Directory
874 There are many ways you can configure OpenOCD and start it up.
876 A simple way to organize them all involves keeping a
877 single directory for your work with a given board.
878 When you start OpenOCD from that directory,
879 it searches there first for configuration files, scripts,
880 files accessed through semihosting,
881 and for code you upload to the target board.
882 It is also the natural place to write files,
883 such as log files and data you download from the board.
885 @section Configuration Basics
887 There are two basic ways of configuring OpenOCD, and
888 a variety of ways you can mix them.
889 Think of the difference as just being how you start the server:
891 @itemize
892 @item Many @option{-f file} or @option{-c command} options on the command line
893 @item No options, but a @dfn{user config file}
894 in the current directory named @file{openocd.cfg}
895 @end itemize
897 Here is an example @file{openocd.cfg} file for a setup
898 using a Signalyzer FT2232-based JTAG adapter to talk to
899 a board with an Atmel AT91SAM7X256 microcontroller:
901 @example
902 source [find interface/signalyzer.cfg]
904 # GDB can also flash my flash!
905 gdb_memory_map enable
906 gdb_flash_program enable
908 source [find target/sam7x256.cfg]
909 @end example
911 Here is the command line equivalent of that configuration:
913 @example
914 openocd -f interface/signalyzer.cfg \
915 -c "gdb_memory_map enable" \
916 -c "gdb_flash_program enable" \
917 -f target/sam7x256.cfg
918 @end example
920 You could wrap such long command lines in shell scripts,
921 each supporting a different development task.
922 One might re-flash the board with a specific firmware version.
923 Another might set up a particular debugging or run-time environment.
925 @quotation Important
926 At this writing (October 2009) the command line method has
927 problems with how it treats variables.
928 For example, after @option{-c "set VAR value"}, or doing the
929 same in a script, the variable @var{VAR} will have no value
930 that can be tested in a later script.
931 @end quotation
933 Here we will focus on the simpler solution: one user config
934 file, including basic configuration plus any TCL procedures
935 to simplify your work.
937 @section User Config Files
938 @cindex config file, user
939 @cindex user config file
940 @cindex config file, overview
942 A user configuration file ties together all the parts of a project
943 in one place.
944 One of the following will match your situation best:
946 @itemize
947 @item Ideally almost everything comes from configuration files
948 provided by someone else.
949 For example, OpenOCD distributes a @file{scripts} directory
950 (probably in @file{/usr/share/openocd/scripts} on Linux).
951 Board and tool vendors can provide these too, as can individual
952 user sites; the @option{-s} command line option lets you say
953 where to find these files. (@xref{Running}.)
954 The AT91SAM7X256 example above works this way.
956 Three main types of non-user configuration file each have their
957 own subdirectory in the @file{scripts} directory:
959 @enumerate
960 @item @b{interface} -- one for each different debug adapter;
961 @item @b{board} -- one for each different board
962 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
963 @end enumerate
965 Best case: include just two files, and they handle everything else.
966 The first is an interface config file.
967 The second is board-specific, and it sets up the JTAG TAPs and
968 their GDB targets (by deferring to some @file{target.cfg} file),
969 declares all flash memory, and leaves you nothing to do except
970 meet your deadline:
972 @example
973 source [find interface/olimex-jtag-tiny.cfg]
974 source [find board/csb337.cfg]
975 @end example
977 Boards with a single microcontroller often won't need more
978 than the target config file, as in the AT91SAM7X256 example.
979 That's because there is no external memory (flash, DDR RAM), and
980 the board differences are encapsulated by application code.
982 @item Maybe you don't know yet what your board looks like to JTAG.
983 Once you know the @file{interface.cfg} file to use, you may
984 need help from OpenOCD to discover what's on the board.
985 Once you find the JTAG TAPs, you can just search for appropriate
986 target and board
987 configuration files ... or write your own, from the bottom up.
988 @xref{autoprobing,,Autoprobing}.
990 @item You can often reuse some standard config files but
991 need to write a few new ones, probably a @file{board.cfg} file.
992 You will be using commands described later in this User's Guide,
993 and working with the guidelines in the next chapter.
995 For example, there may be configuration files for your JTAG adapter
996 and target chip, but you need a new board-specific config file
997 giving access to your particular flash chips.
998 Or you might need to write another target chip configuration file
999 for a new chip built around the Cortex M3 core.
1001 @quotation Note
1002 When you write new configuration files, please submit
1003 them for inclusion in the next OpenOCD release.
1004 For example, a @file{board/newboard.cfg} file will help the
1005 next users of that board, and a @file{target/newcpu.cfg}
1006 will help support users of any board using that chip.
1007 @end quotation
1009 @item
1010 You may may need to write some C code.
1011 It may be as simple as supporting a new FT2232 or parport
1012 based adapter; a bit more involved, like a NAND or NOR flash
1013 controller driver; or a big piece of work like supporting
1014 a new chip architecture.
1015 @end itemize
1017 Reuse the existing config files when you can.
1018 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1019 You may find a board configuration that's a good example to follow.
1021 When you write config files, separate the reusable parts
1022 (things every user of that interface, chip, or board needs)
1023 from ones specific to your environment and debugging approach.
1024 @itemize
1026 @item
1027 For example, a @code{gdb-attach} event handler that invokes
1028 the @command{reset init} command will interfere with debugging
1029 early boot code, which performs some of the same actions
1030 that the @code{reset-init} event handler does.
1032 @item
1033 Likewise, the @command{arm9 vector_catch} command (or
1034 @cindex vector_catch
1035 its siblings @command{xscale vector_catch}
1036 and @command{cortex_m vector_catch}) can be a timesaver
1037 during some debug sessions, but don't make everyone use that either.
1038 Keep those kinds of debugging aids in your user config file,
1039 along with messaging and tracing setup.
1040 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1042 @item
1043 You might need to override some defaults.
1044 For example, you might need to move, shrink, or back up the target's
1045 work area if your application needs much SRAM.
1047 @item
1048 TCP/IP port configuration is another example of something which
1049 is environment-specific, and should only appear in
1050 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1051 @end itemize
1053 @section Project-Specific Utilities
1055 A few project-specific utility
1056 routines may well speed up your work.
1057 Write them, and keep them in your project's user config file.
1059 For example, if you are making a boot loader work on a
1060 board, it's nice to be able to debug the ``after it's
1061 loaded to RAM'' parts separately from the finicky early
1062 code which sets up the DDR RAM controller and clocks.
1063 A script like this one, or a more GDB-aware sibling,
1064 may help:
1066 @example
1067 proc ramboot @{ @} @{
1068 # Reset, running the target's "reset-init" scripts
1069 # to initialize clocks and the DDR RAM controller.
1070 # Leave the CPU halted.
1071 reset init
1073 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1074 load_image u-boot.bin 0x20000000
1076 # Start running.
1077 resume 0x20000000
1078 @}
1079 @end example
1081 Then once that code is working you will need to make it
1082 boot from NOR flash; a different utility would help.
1083 Alternatively, some developers write to flash using GDB.
1084 (You might use a similar script if you're working with a flash
1085 based microcontroller application instead of a boot loader.)
1087 @example
1088 proc newboot @{ @} @{
1089 # Reset, leaving the CPU halted. The "reset-init" event
1090 # proc gives faster access to the CPU and to NOR flash;
1091 # "reset halt" would be slower.
1092 reset init
1094 # Write standard version of U-Boot into the first two
1095 # sectors of NOR flash ... the standard version should
1096 # do the same lowlevel init as "reset-init".
1097 flash protect 0 0 1 off
1098 flash erase_sector 0 0 1
1099 flash write_bank 0 u-boot.bin 0x0
1100 flash protect 0 0 1 on
1102 # Reboot from scratch using that new boot loader.
1103 reset run
1104 @}
1105 @end example
1107 You may need more complicated utility procedures when booting
1108 from NAND.
1109 That often involves an extra bootloader stage,
1110 running from on-chip SRAM to perform DDR RAM setup so it can load
1111 the main bootloader code (which won't fit into that SRAM).
1113 Other helper scripts might be used to write production system images,
1114 involving considerably more than just a three stage bootloader.
1116 @section Target Software Changes
1118 Sometimes you may want to make some small changes to the software
1119 you're developing, to help make JTAG debugging work better.
1120 For example, in C or assembly language code you might
1121 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1122 handling issues like:
1124 @itemize @bullet
1126 @item @b{Watchdog Timers}...
1127 Watchog timers are typically used to automatically reset systems if
1128 some application task doesn't periodically reset the timer. (The
1129 assumption is that the system has locked up if the task can't run.)
1130 When a JTAG debugger halts the system, that task won't be able to run
1131 and reset the timer ... potentially causing resets in the middle of
1132 your debug sessions.
1134 It's rarely a good idea to disable such watchdogs, since their usage
1135 needs to be debugged just like all other parts of your firmware.
1136 That might however be your only option.
1138 Look instead for chip-specific ways to stop the watchdog from counting
1139 while the system is in a debug halt state. It may be simplest to set
1140 that non-counting mode in your debugger startup scripts. You may however
1141 need a different approach when, for example, a motor could be physically
1142 damaged by firmware remaining inactive in a debug halt state. That might
1143 involve a type of firmware mode where that "non-counting" mode is disabled
1144 at the beginning then re-enabled at the end; a watchdog reset might fire
1145 and complicate the debug session, but hardware (or people) would be
1146 protected.@footnote{Note that many systems support a "monitor mode" debug
1147 that is a somewhat cleaner way to address such issues. You can think of
1148 it as only halting part of the system, maybe just one task,
1149 instead of the whole thing.
1150 At this writing, January 2010, OpenOCD based debugging does not support
1151 monitor mode debug, only "halt mode" debug.}
1153 @item @b{ARM Semihosting}...
1154 @cindex ARM semihosting
1155 When linked with a special runtime library provided with many
1156 toolchains@footnote{See chapter 8 "Semihosting" in
1157 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1158 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1159 The CodeSourcery EABI toolchain also includes a semihosting library.},
1160 your target code can use I/O facilities on the debug host. That library
1161 provides a small set of system calls which are handled by OpenOCD.
1162 It can let the debugger provide your system console and a file system,
1163 helping with early debugging or providing a more capable environment
1164 for sometimes-complex tasks like installing system firmware onto
1165 NAND or SPI flash.
1167 @item @b{ARM Wait-For-Interrupt}...
1168 Many ARM chips synchronize the JTAG clock using the core clock.
1169 Low power states which stop that core clock thus prevent JTAG access.
1170 Idle loops in tasking environments often enter those low power states
1171 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1173 You may want to @emph{disable that instruction} in source code,
1174 or otherwise prevent using that state,
1175 to ensure you can get JTAG access at any time.@footnote{As a more
1176 polite alternative, some processors have special debug-oriented
1177 registers which can be used to change various features including
1178 how the low power states are clocked while debugging.
1179 The STM32 DBGMCU_CR register is an example; at the cost of extra
1180 power consumption, JTAG can be used during low power states.}
1181 For example, the OpenOCD @command{halt} command may not
1182 work for an idle processor otherwise.
1184 @item @b{Delay after reset}...
1185 Not all chips have good support for debugger access
1186 right after reset; many LPC2xxx chips have issues here.
1187 Similarly, applications that reconfigure pins used for
1188 JTAG access as they start will also block debugger access.
1190 To work with boards like this, @emph{enable a short delay loop}
1191 the first thing after reset, before "real" startup activities.
1192 For example, one second's delay is usually more than enough
1193 time for a JTAG debugger to attach, so that
1194 early code execution can be debugged
1195 or firmware can be replaced.
1197 @item @b{Debug Communications Channel (DCC)}...
1198 Some processors include mechanisms to send messages over JTAG.
1199 Many ARM cores support these, as do some cores from other vendors.
1200 (OpenOCD may be able to use this DCC internally, speeding up some
1201 operations like writing to memory.)
1203 Your application may want to deliver various debugging messages
1204 over JTAG, by @emph{linking with a small library of code}
1205 provided with OpenOCD and using the utilities there to send
1206 various kinds of message.
1207 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1209 @end itemize
1211 @section Target Hardware Setup
1213 Chip vendors often provide software development boards which
1214 are highly configurable, so that they can support all options
1215 that product boards may require. @emph{Make sure that any
1216 jumpers or switches match the system configuration you are
1217 working with.}
1219 Common issues include:
1221 @itemize @bullet
1223 @item @b{JTAG setup} ...
1224 Boards may support more than one JTAG configuration.
1225 Examples include jumpers controlling pullups versus pulldowns
1226 on the nTRST and/or nSRST signals, and choice of connectors
1227 (e.g. which of two headers on the base board,
1228 or one from a daughtercard).
1229 For some Texas Instruments boards, you may need to jumper the
1230 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1232 @item @b{Boot Modes} ...
1233 Complex chips often support multiple boot modes, controlled
1234 by external jumpers. Make sure this is set up correctly.
1235 For example many i.MX boards from NXP need to be jumpered
1236 to "ATX mode" to start booting using the on-chip ROM, when
1237 using second stage bootloader code stored in a NAND flash chip.
1239 Such explicit configuration is common, and not limited to
1240 booting from NAND. You might also need to set jumpers to
1241 start booting using code loaded from an MMC/SD card; external
1242 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1243 flash; some external host; or various other sources.
1246 @item @b{Memory Addressing} ...
1247 Boards which support multiple boot modes may also have jumpers
1248 to configure memory addressing. One board, for example, jumpers
1249 external chipselect 0 (used for booting) to address either
1250 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1251 or NAND flash. When it's jumpered to address NAND flash, that
1252 board must also be told to start booting from on-chip ROM.
1254 Your @file{board.cfg} file may also need to be told this jumper
1255 configuration, so that it can know whether to declare NOR flash
1256 using @command{flash bank} or instead declare NAND flash with
1257 @command{nand device}; and likewise which probe to perform in
1258 its @code{reset-init} handler.
1260 A closely related issue is bus width. Jumpers might need to
1261 distinguish between 8 bit or 16 bit bus access for the flash
1262 used to start booting.
1264 @item @b{Peripheral Access} ...
1265 Development boards generally provide access to every peripheral
1266 on the chip, sometimes in multiple modes (such as by providing
1267 multiple audio codec chips).
1268 This interacts with software
1269 configuration of pin multiplexing, where for example a
1270 given pin may be routed either to the MMC/SD controller
1271 or the GPIO controller. It also often interacts with
1272 configuration jumpers. One jumper may be used to route
1273 signals to an MMC/SD card slot or an expansion bus (which
1274 might in turn affect booting); others might control which
1275 audio or video codecs are used.
1277 @end itemize
1279 Plus you should of course have @code{reset-init} event handlers
1280 which set up the hardware to match that jumper configuration.
1281 That includes in particular any oscillator or PLL used to clock
1282 the CPU, and any memory controllers needed to access external
1283 memory and peripherals. Without such handlers, you won't be
1284 able to access those resources without working target firmware
1285 which can do that setup ... this can be awkward when you're
1286 trying to debug that target firmware. Even if there's a ROM
1287 bootloader which handles a few issues, it rarely provides full
1288 access to all board-specific capabilities.
1291 @node Config File Guidelines
1292 @chapter Config File Guidelines
1294 This chapter is aimed at any user who needs to write a config file,
1295 including developers and integrators of OpenOCD and any user who
1296 needs to get a new board working smoothly.
1297 It provides guidelines for creating those files.
1299 You should find the following directories under
1300 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1301 them as-is where you can; or as models for new files.
1302 @itemize @bullet
1303 @item @file{interface} ...
1304 These are for debug adapters. Files that specify configuration to use
1305 specific JTAG, SWD and other adapters go here.
1306 @item @file{board} ...
1307 Think Circuit Board, PWA, PCB, they go by many names. Board files
1308 contain initialization items that are specific to a board.
1310 They reuse target configuration files, since the same
1311 microprocessor chips are used on many boards,
1312 but support for external parts varies widely. For
1313 example, the SDRAM initialization sequence for the board, or the type
1314 of external flash and what address it uses. Any initialization
1315 sequence to enable that external flash or SDRAM should be found in the
1316 board file. Boards may also contain multiple targets: two CPUs; or
1317 a CPU and an FPGA.
1318 @item @file{target} ...
1319 Think chip. The ``target'' directory represents the JTAG TAPs
1320 on a chip
1321 which OpenOCD should control, not a board. Two common types of targets
1322 are ARM chips and FPGA or CPLD chips.
1323 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1324 the target config file defines all of them.
1325 @item @emph{more} ... browse for other library files which may be useful.
1326 For example, there are various generic and CPU-specific utilities.
1327 @end itemize
1329 The @file{openocd.cfg} user config
1330 file may override features in any of the above files by
1331 setting variables before sourcing the target file, or by adding
1332 commands specific to their situation.
1334 @section Interface Config Files
1336 The user config file
1337 should be able to source one of these files with a command like this:
1339 @example
1340 source [find interface/FOOBAR.cfg]
1341 @end example
1343 A preconfigured interface file should exist for every debug adapter
1344 in use today with OpenOCD.
1345 That said, perhaps some of these config files
1346 have only been used by the developer who created it.
1348 A separate chapter gives information about how to set these up.
1349 @xref{Debug Adapter Configuration}.
1350 Read the OpenOCD source code (and Developer's Guide)
1351 if you have a new kind of hardware interface
1352 and need to provide a driver for it.
1354 @section Board Config Files
1355 @cindex config file, board
1356 @cindex board config file
1358 The user config file
1359 should be able to source one of these files with a command like this:
1361 @example
1362 source [find board/FOOBAR.cfg]
1363 @end example
1365 The point of a board config file is to package everything
1366 about a given board that user config files need to know.
1367 In summary the board files should contain (if present)
1369 @enumerate
1370 @item One or more @command{source [find target/...cfg]} statements
1371 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1372 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1373 @item Target @code{reset} handlers for SDRAM and I/O configuration
1374 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1375 @item All things that are not ``inside a chip''
1376 @end enumerate
1378 Generic things inside target chips belong in target config files,
1379 not board config files. So for example a @code{reset-init} event
1380 handler should know board-specific oscillator and PLL parameters,
1381 which it passes to target-specific utility code.
1383 The most complex task of a board config file is creating such a
1384 @code{reset-init} event handler.
1385 Define those handlers last, after you verify the rest of the board
1386 configuration works.
1388 @subsection Communication Between Config files
1390 In addition to target-specific utility code, another way that
1391 board and target config files communicate is by following a
1392 convention on how to use certain variables.
1394 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1395 Thus the rule we follow in OpenOCD is this: Variables that begin with
1396 a leading underscore are temporary in nature, and can be modified and
1397 used at will within a target configuration file.
1399 Complex board config files can do the things like this,
1400 for a board with three chips:
1402 @example
1403 # Chip #1: PXA270 for network side, big endian
1404 set CHIPNAME network
1405 set ENDIAN big
1406 source [find target/pxa270.cfg]
1407 # on return: _TARGETNAME = network.cpu
1408 # other commands can refer to the "network.cpu" target.
1409 $_TARGETNAME configure .... events for this CPU..
1411 # Chip #2: PXA270 for video side, little endian
1412 set CHIPNAME video
1413 set ENDIAN little
1414 source [find target/pxa270.cfg]
1415 # on return: _TARGETNAME = video.cpu
1416 # other commands can refer to the "video.cpu" target.
1417 $_TARGETNAME configure .... events for this CPU..
1419 # Chip #3: Xilinx FPGA for glue logic
1420 set CHIPNAME xilinx
1421 unset ENDIAN
1422 source [find target/spartan3.cfg]
1423 @end example
1425 That example is oversimplified because it doesn't show any flash memory,
1426 or the @code{reset-init} event handlers to initialize external DRAM
1427 or (assuming it needs it) load a configuration into the FPGA.
1428 Such features are usually needed for low-level work with many boards,
1429 where ``low level'' implies that the board initialization software may
1430 not be working. (That's a common reason to need JTAG tools. Another
1431 is to enable working with microcontroller-based systems, which often
1432 have no debugging support except a JTAG connector.)
1434 Target config files may also export utility functions to board and user
1435 config files. Such functions should use name prefixes, to help avoid
1436 naming collisions.
1438 Board files could also accept input variables from user config files.
1439 For example, there might be a @code{J4_JUMPER} setting used to identify
1440 what kind of flash memory a development board is using, or how to set
1441 up other clocks and peripherals.
1443 @subsection Variable Naming Convention
1444 @cindex variable names
1446 Most boards have only one instance of a chip.
1447 However, it should be easy to create a board with more than
1448 one such chip (as shown above).
1449 Accordingly, we encourage these conventions for naming
1450 variables associated with different @file{target.cfg} files,
1451 to promote consistency and
1452 so that board files can override target defaults.
1454 Inputs to target config files include:
1456 @itemize @bullet
1457 @item @code{CHIPNAME} ...
1458 This gives a name to the overall chip, and is used as part of
1459 tap identifier dotted names.
1460 While the default is normally provided by the chip manufacturer,
1461 board files may need to distinguish between instances of a chip.
1462 @item @code{ENDIAN} ...
1463 By default @option{little} - although chips may hard-wire @option{big}.
1464 Chips that can't change endianness don't need to use this variable.
1465 @item @code{CPUTAPID} ...
1466 When OpenOCD examines the JTAG chain, it can be told verify the
1467 chips against the JTAG IDCODE register.
1468 The target file will hold one or more defaults, but sometimes the
1469 chip in a board will use a different ID (perhaps a newer revision).
1470 @end itemize
1472 Outputs from target config files include:
1474 @itemize @bullet
1475 @item @code{_TARGETNAME} ...
1476 By convention, this variable is created by the target configuration
1477 script. The board configuration file may make use of this variable to
1478 configure things like a ``reset init'' script, or other things
1479 specific to that board and that target.
1480 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1481 @code{_TARGETNAME1}, ... etc.
1482 @end itemize
1484 @subsection The reset-init Event Handler
1485 @cindex event, reset-init
1486 @cindex reset-init handler
1488 Board config files run in the OpenOCD configuration stage;
1489 they can't use TAPs or targets, since they haven't been
1490 fully set up yet.
1491 This means you can't write memory or access chip registers;
1492 you can't even verify that a flash chip is present.
1493 That's done later in event handlers, of which the target @code{reset-init}
1494 handler is one of the most important.
1496 Except on microcontrollers, the basic job of @code{reset-init} event
1497 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1498 Microcontrollers rarely use boot loaders; they run right out of their
1499 on-chip flash and SRAM memory. But they may want to use one of these
1500 handlers too, if just for developer convenience.
1502 @quotation Note
1503 Because this is so very board-specific, and chip-specific, no examples
1504 are included here.
1505 Instead, look at the board config files distributed with OpenOCD.
1506 If you have a boot loader, its source code will help; so will
1507 configuration files for other JTAG tools
1508 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1509 @end quotation
1511 Some of this code could probably be shared between different boards.
1512 For example, setting up a DRAM controller often doesn't differ by
1513 much except the bus width (16 bits or 32?) and memory timings, so a
1514 reusable TCL procedure loaded by the @file{target.cfg} file might take
1515 those as parameters.
1516 Similarly with oscillator, PLL, and clock setup;
1517 and disabling the watchdog.
1518 Structure the code cleanly, and provide comments to help
1519 the next developer doing such work.
1520 (@emph{You might be that next person} trying to reuse init code!)
1522 The last thing normally done in a @code{reset-init} handler is probing
1523 whatever flash memory was configured. For most chips that needs to be
1524 done while the associated target is halted, either because JTAG memory
1525 access uses the CPU or to prevent conflicting CPU access.
1527 @subsection JTAG Clock Rate
1529 Before your @code{reset-init} handler has set up
1530 the PLLs and clocking, you may need to run with
1531 a low JTAG clock rate.
1532 @xref{jtagspeed,,JTAG Speed}.
1533 Then you'd increase that rate after your handler has
1534 made it possible to use the faster JTAG clock.
1535 When the initial low speed is board-specific, for example
1536 because it depends on a board-specific oscillator speed, then
1537 you should probably set it up in the board config file;
1538 if it's target-specific, it belongs in the target config file.
1540 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1541 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1542 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1543 Consult chip documentation to determine the peak JTAG clock rate,
1544 which might be less than that.
1546 @quotation Warning
1547 On most ARMs, JTAG clock detection is coupled to the core clock, so
1548 software using a @option{wait for interrupt} operation blocks JTAG access.
1549 Adaptive clocking provides a partial workaround, but a more complete
1550 solution just avoids using that instruction with JTAG debuggers.
1551 @end quotation
1553 If both the chip and the board support adaptive clocking,
1554 use the @command{jtag_rclk}
1555 command, in case your board is used with JTAG adapter which
1556 also supports it. Otherwise use @command{adapter_khz}.
1557 Set the slow rate at the beginning of the reset sequence,
1558 and the faster rate as soon as the clocks are at full speed.
1560 @anchor{theinitboardprocedure}
1561 @subsection The init_board procedure
1562 @cindex init_board procedure
1564 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1565 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1566 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1567 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1568 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1569 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1570 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1571 Additionally ``linear'' board config file will most likely fail when target config file uses
1572 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1573 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1574 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1575 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1577 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1578 the original), allowing greater code reuse.
1580 @example
1581 ### board_file.cfg ###
1583 # source target file that does most of the config in init_targets
1584 source [find target/target.cfg]
1586 proc enable_fast_clock @{@} @{
1587 # enables fast on-board clock source
1588 # configures the chip to use it
1589 @}
1591 # initialize only board specifics - reset, clock, adapter frequency
1592 proc init_board @{@} @{
1593 reset_config trst_and_srst trst_pulls_srst
1595 $_TARGETNAME configure -event reset-init @{
1596 adapter_khz 1
1597 enable_fast_clock
1598 adapter_khz 10000
1599 @}
1600 @}
1601 @end example
1603 @section Target Config Files
1604 @cindex config file, target
1605 @cindex target config file
1607 Board config files communicate with target config files using
1608 naming conventions as described above, and may source one or
1609 more target config files like this:
1611 @example
1612 source [find target/FOOBAR.cfg]
1613 @end example
1615 The point of a target config file is to package everything
1616 about a given chip that board config files need to know.
1617 In summary the target files should contain
1619 @enumerate
1620 @item Set defaults
1621 @item Add TAPs to the scan chain
1622 @item Add CPU targets (includes GDB support)
1623 @item CPU/Chip/CPU-Core specific features
1624 @item On-Chip flash
1625 @end enumerate
1627 As a rule of thumb, a target file sets up only one chip.
1628 For a microcontroller, that will often include a single TAP,
1629 which is a CPU needing a GDB target, and its on-chip flash.
1631 More complex chips may include multiple TAPs, and the target
1632 config file may need to define them all before OpenOCD
1633 can talk to the chip.
1634 For example, some phone chips have JTAG scan chains that include
1635 an ARM core for operating system use, a DSP,
1636 another ARM core embedded in an image processing engine,
1637 and other processing engines.
1639 @subsection Default Value Boiler Plate Code
1641 All target configuration files should start with code like this,
1642 letting board config files express environment-specific
1643 differences in how things should be set up.
1645 @example
1646 # Boards may override chip names, perhaps based on role,
1647 # but the default should match what the vendor uses
1648 if @{ [info exists CHIPNAME] @} @{
1650 @} else @{
1651 set _CHIPNAME sam7x256
1652 @}
1654 # ONLY use ENDIAN with targets that can change it.
1655 if @{ [info exists ENDIAN] @} @{
1656 set _ENDIAN $ENDIAN
1657 @} else @{
1658 set _ENDIAN little
1659 @}
1661 # TAP identifiers may change as chips mature, for example with
1662 # new revision fields (the "3" here). Pick a good default; you
1663 # can pass several such identifiers to the "jtag newtap" command.
1664 if @{ [info exists CPUTAPID ] @} @{
1666 @} else @{
1667 set _CPUTAPID 0x3f0f0f0f
1668 @}
1669 @end example
1670 @c but 0x3f0f0f0f is for an str73x part ...
1672 @emph{Remember:} Board config files may include multiple target
1673 config files, or the same target file multiple times
1674 (changing at least @code{CHIPNAME}).
1676 Likewise, the target configuration file should define
1677 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1678 use it later on when defining debug targets:
1680 @example
1682 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1683 @end example
1685 @subsection Adding TAPs to the Scan Chain
1686 After the ``defaults'' are set up,
1687 add the TAPs on each chip to the JTAG scan chain.
1688 @xref{TAP Declaration}, and the naming convention
1689 for taps.
1691 In the simplest case the chip has only one TAP,
1692 probably for a CPU or FPGA.
1693 The config file for the Atmel AT91SAM7X256
1694 looks (in part) like this:
1696 @example
1697 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1698 @end example
1700 A board with two such at91sam7 chips would be able
1701 to source such a config file twice, with different
1702 values for @code{CHIPNAME}, so
1703 it adds a different TAP each time.
1705 If there are nonzero @option{-expected-id} values,
1706 OpenOCD attempts to verify the actual tap id against those values.
1707 It will issue error messages if there is mismatch, which
1708 can help to pinpoint problems in OpenOCD configurations.
1710 @example
1711 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1712 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1713 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1714 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1715 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1716 @end example
1718 There are more complex examples too, with chips that have
1719 multiple TAPs. Ones worth looking at include:
1721 @itemize
1722 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1723 plus a JRC to enable them
1724 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1725 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1726 is not currently used)
1727 @end itemize
1729 @subsection Add CPU targets
1731 After adding a TAP for a CPU, you should set it up so that
1732 GDB and other commands can use it.
1733 @xref{CPU Configuration}.
1734 For the at91sam7 example above, the command can look like this;
1735 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1736 to little endian, and this chip doesn't support changing that.
1738 @example
1740 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1741 @end example
1743 Work areas are small RAM areas associated with CPU targets.
1744 They are used by OpenOCD to speed up downloads,
1745 and to download small snippets of code to program flash chips.
1746 If the chip includes a form of ``on-chip-ram'' - and many do - define
1747 a work area if you can.
1748 Again using the at91sam7 as an example, this can look like:
1750 @example
1751 $_TARGETNAME configure -work-area-phys 0x00200000 \
1752 -work-area-size 0x4000 -work-area-backup 0
1753 @end example
1755 @anchor{definecputargetsworkinginsmp}
1756 @subsection Define CPU targets working in SMP
1757 @cindex SMP
1758 After setting targets, you can define a list of targets working in SMP.
1760 @example
1761 set _TARGETNAME_1 $_CHIPNAME.cpu1
1762 set _TARGETNAME_2 $_CHIPNAME.cpu2
1763 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1764 -coreid 0 -dbgbase $_DAP_DBG1
1765 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1766 -coreid 1 -dbgbase $_DAP_DBG2
1767 #define 2 targets working in smp.
1768 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1769 @end example
1770 In the above example on cortex_a, 2 cpus are working in SMP.
1771 In SMP only one GDB instance is created and :
1772 @itemize @bullet
1773 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1774 @item halt command triggers the halt of all targets in the list.
1775 @item resume command triggers the write context and the restart of all targets in the list.
1776 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1777 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1778 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1779 @end itemize
1781 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1782 command have been implemented.
1783 @itemize @bullet
1784 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1785 @item cortex_a smp_off : disable SMP mode, the current target is the one
1786 displayed in the GDB session, only this target is now controlled by GDB
1787 session. This behaviour is useful during system boot up.
1788 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1789 following example.
1790 @end itemize
1792 @example
1793 >cortex_a smp_gdb
1794 gdb coreid 0 -> -1
1795 #0 : coreid 0 is displayed to GDB ,
1796 #-> -1 : next resume triggers a real resume
1797 > cortex_a smp_gdb 1
1798 gdb coreid 0 -> 1
1799 #0 :coreid 0 is displayed to GDB ,
1800 #->1 : next resume displays coreid 1 to GDB
1801 > resume
1802 > cortex_a smp_gdb
1803 gdb coreid 1 -> 1
1804 #1 :coreid 1 is displayed to GDB ,
1805 #->1 : next resume displays coreid 1 to GDB
1806 > cortex_a smp_gdb -1
1807 gdb coreid 1 -> -1
1808 #1 :coreid 1 is displayed to GDB,
1809 #->-1 : next resume triggers a real resume
1810 @end example
1813 @subsection Chip Reset Setup
1815 As a rule, you should put the @command{reset_config} command
1816 into the board file. Most things you think you know about a
1817 chip can be tweaked by the board.
1819 Some chips have specific ways the TRST and SRST signals are
1820 managed. In the unusual case that these are @emph{chip specific}
1821 and can never be changed by board wiring, they could go here.
1822 For example, some chips can't support JTAG debugging without
1823 both signals.
1825 Provide a @code{reset-assert} event handler if you can.
1826 Such a handler uses JTAG operations to reset the target,
1827 letting this target config be used in systems which don't
1828 provide the optional SRST signal, or on systems where you
1829 don't want to reset all targets at once.
1830 Such a handler might write to chip registers to force a reset,
1831 use a JRC to do that (preferable -- the target may be wedged!),
1832 or force a watchdog timer to trigger.
1833 (For Cortex-M targets, this is not necessary. The target
1834 driver knows how to use trigger an NVIC reset when SRST is
1835 not available.)
1837 Some chips need special attention during reset handling if
1838 they're going to be used with JTAG.
1839 An example might be needing to send some commands right
1840 after the target's TAP has been reset, providing a
1841 @code{reset-deassert-post} event handler that writes a chip
1842 register to report that JTAG debugging is being done.
1843 Another would be reconfiguring the watchdog so that it stops
1844 counting while the core is halted in the debugger.
1846 JTAG clocking constraints often change during reset, and in
1847 some cases target config files (rather than board config files)
1848 are the right places to handle some of those issues.
1849 For example, immediately after reset most chips run using a
1850 slower clock than they will use later.
1851 That means that after reset (and potentially, as OpenOCD
1852 first starts up) they must use a slower JTAG clock rate
1853 than they will use later.
1854 @xref{jtagspeed,,JTAG Speed}.
1856 @quotation Important
1857 When you are debugging code that runs right after chip
1858 reset, getting these issues right is critical.
1859 In particular, if you see intermittent failures when
1860 OpenOCD verifies the scan chain after reset,
1861 look at how you are setting up JTAG clocking.
1862 @end quotation
1864 @anchor{theinittargetsprocedure}
1865 @subsection The init_targets procedure
1866 @cindex init_targets procedure
1868 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1869 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1870 procedure called @code{init_targets}, which will be executed when entering run stage
1871 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1872 Such procedure can be overriden by ``next level'' script (which sources the original).
1873 This concept faciliates code reuse when basic target config files provide generic configuration
1874 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
1875 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1876 because sourcing them executes every initialization commands they provide.
1878 @example
1879 ### generic_file.cfg ###
1881 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1882 # basic initialization procedure ...
1883 @}
1885 proc init_targets @{@} @{
1886 # initializes generic chip with 4kB of flash and 1kB of RAM
1887 setup_my_chip MY_GENERIC_CHIP 4096 1024
1888 @}
1890 ### specific_file.cfg ###
1892 source [find target/generic_file.cfg]
1894 proc init_targets @{@} @{
1895 # initializes specific chip with 128kB of flash and 64kB of RAM
1896 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1897 @}
1898 @end example
1900 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1901 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1903 For an example of this scheme see LPC2000 target config files.
1905 The @code{init_boards} procedure is a similar concept concerning board config files
1906 (@xref{theinitboardprocedure,,The init_board procedure}.)
1908 @anchor{theinittargeteventsprocedure}
1909 @subsection The init_target_events procedure
1910 @cindex init_target_events procedure
1912 A special procedure called @code{init_target_events} is run just after
1913 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1914 procedure}.) and before @code{init_board}
1915 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1916 to set up default target events for the targets that do not have those
1917 events already assigned.
1919 @subsection ARM Core Specific Hacks
1921 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1922 special high speed download features - enable it.
1924 If present, the MMU, the MPU and the CACHE should be disabled.
1926 Some ARM cores are equipped with trace support, which permits
1927 examination of the instruction and data bus activity. Trace
1928 activity is controlled through an ``Embedded Trace Module'' (ETM)
1929 on one of the core's scan chains. The ETM emits voluminous data
1930 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1931 If you are using an external trace port,
1932 configure it in your board config file.
1933 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1934 configure it in your target config file.
1936 @example
1937 etm config $_TARGETNAME 16 normal full etb
1938 etb config $_TARGETNAME $_CHIPNAME.etb
1939 @end example
1941 @subsection Internal Flash Configuration
1943 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1945 @b{Never ever} in the ``target configuration file'' define any type of
1946 flash that is external to the chip. (For example a BOOT flash on
1947 Chip Select 0.) Such flash information goes in a board file - not
1948 the TARGET (chip) file.
1950 Examples:
1951 @itemize @bullet
1952 @item at91sam7x256 - has 256K flash YES enable it.
1953 @item str912 - has flash internal YES enable it.
1954 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1955 @item pxa270 - again - CS0 flash - it goes in the board file.
1956 @end itemize
1958 @anchor{translatingconfigurationfiles}
1959 @section Translating Configuration Files
1960 @cindex translation
1961 If you have a configuration file for another hardware debugger
1962 or toolset (Abatron, BDI2000, BDI3000, CCS,
1963 Lauterbach, Segger, Macraigor, etc.), translating
1964 it into OpenOCD syntax is often quite straightforward. The most tricky
1965 part of creating a configuration script is oftentimes the reset init
1966 sequence where e.g. PLLs, DRAM and the like is set up.
1968 One trick that you can use when translating is to write small
1969 Tcl procedures to translate the syntax into OpenOCD syntax. This
1970 can avoid manual translation errors and make it easier to
1971 convert other scripts later on.
1973 Example of transforming quirky arguments to a simple search and
1974 replace job:
1976 @example
1977 # Lauterbach syntax(?)
1978 #
1979 # Data.Set c15:0x042f %long 0x40000015
1980 #
1981 # OpenOCD syntax when using procedure below.
1982 #
1983 # setc15 0x01 0x00050078
1985 proc setc15 @{regs value@} @{
1986 global TARGETNAME
1988 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
1990 arm mcr 15 [expr ($regs>>12)&0x7] \
1991 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
1992 [expr ($regs>>8)&0x7] $value
1993 @}
1994 @end example
1998 @node Daemon Configuration
1999 @chapter Daemon Configuration
2000 @cindex initialization
2001 The commands here are commonly found in the openocd.cfg file and are
2002 used to specify what TCP/IP ports are used, and how GDB should be
2003 supported.
2005 @anchor{configurationstage}
2006 @section Configuration Stage
2007 @cindex configuration stage
2008 @cindex config command
2010 When the OpenOCD server process starts up, it enters a
2011 @emph{configuration stage} which is the only time that
2012 certain commands, @emph{configuration commands}, may be issued.
2013 Normally, configuration commands are only available
2014 inside startup scripts.
2016 In this manual, the definition of a configuration command is
2017 presented as a @emph{Config Command}, not as a @emph{Command}
2018 which may be issued interactively.
2019 The runtime @command{help} command also highlights configuration
2020 commands, and those which may be issued at any time.
2022 Those configuration commands include declaration of TAPs,
2023 flash banks,
2024 the interface used for JTAG communication,
2025 and other basic setup.
2026 The server must leave the configuration stage before it
2027 may access or activate TAPs.
2028 After it leaves this stage, configuration commands may no
2029 longer be issued.
2031 @anchor{enteringtherunstage}
2032 @section Entering the Run Stage
2034 The first thing OpenOCD does after leaving the configuration
2035 stage is to verify that it can talk to the scan chain
2036 (list of TAPs) which has been configured.
2037 It will warn if it doesn't find TAPs it expects to find,
2038 or finds TAPs that aren't supposed to be there.
2039 You should see no errors at this point.
2040 If you see errors, resolve them by correcting the
2041 commands you used to configure the server.
2042 Common errors include using an initial JTAG speed that's too
2043 fast, and not providing the right IDCODE values for the TAPs
2044 on the scan chain.
2046 Once OpenOCD has entered the run stage, a number of commands
2047 become available.
2048 A number of these relate to the debug targets you may have declared.
2049 For example, the @command{mww} command will not be available until
2050 a target has been successfuly instantiated.
2051 If you want to use those commands, you may need to force
2052 entry to the run stage.
2054 @deffn {Config Command} init
2055 This command terminates the configuration stage and
2056 enters the run stage. This helps when you need to have
2057 the startup scripts manage tasks such as resetting the target,
2058 programming flash, etc. To reset the CPU upon startup, add "init" and
2059 "reset" at the end of the config script or at the end of the OpenOCD
2060 command line using the @option{-c} command line switch.
2062 If this command does not appear in any startup/configuration file
2063 OpenOCD executes the command for you after processing all
2064 configuration files and/or command line options.
2066 @b{NOTE:} This command normally occurs at or near the end of your
2067 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2068 targets ready. For example: If your openocd.cfg file needs to
2069 read/write memory on your target, @command{init} must occur before
2070 the memory read/write commands. This includes @command{nand probe}.
2071 @end deffn
2073 @deffn {Overridable Procedure} jtag_init
2074 This is invoked at server startup to verify that it can talk
2075 to the scan chain (list of TAPs) which has been configured.
2077 The default implementation first tries @command{jtag arp_init},
2078 which uses only a lightweight JTAG reset before examining the
2079 scan chain.
2080 If that fails, it tries again, using a harder reset
2081 from the overridable procedure @command{init_reset}.
2083 Implementations must have verified the JTAG scan chain before
2084 they return.
2085 This is done by calling @command{jtag arp_init}
2086 (or @command{jtag arp_init-reset}).
2087 @end deffn
2089 @anchor{tcpipports}
2090 @section TCP/IP Ports
2091 @cindex TCP port
2092 @cindex server
2093 @cindex port
2094 @cindex security
2095 The OpenOCD server accepts remote commands in several syntaxes.
2096 Each syntax uses a different TCP/IP port, which you may specify
2097 only during configuration (before those ports are opened).
2099 For reasons including security, you may wish to prevent remote
2100 access using one or more of these ports.
2101 In such cases, just specify the relevant port number as zero.
2102 If you disable all access through TCP/IP, you will need to
2103 use the command line @option{-pipe} option.
2105 @deffn {Command} gdb_port [number]
2106 @cindex GDB server
2107 Normally gdb listens to a TCP/IP port, but GDB can also
2108 communicate via pipes(stdin/out or named pipes). The name
2109 "gdb_port" stuck because it covers probably more than 90% of
2110 the normal use cases.
2112 No arguments reports GDB port. "pipe" means listen to stdin
2113 output to stdout, an integer is base port number, "disable"
2114 disables the gdb server.
2116 When using "pipe", also use log_output to redirect the log
2117 output to a file so as not to flood the stdin/out pipes.
2119 The -p/--pipe option is deprecated and a warning is printed
2120 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2122 Any other string is interpreted as named pipe to listen to.
2123 Output pipe is the same name as input pipe, but with 'o' appended,
2124 e.g. /var/gdb, /var/gdbo.
2126 The GDB port for the first target will be the base port, the
2127 second target will listen on gdb_port + 1, and so on.
2128 When not specified during the configuration stage,
2129 the port @var{number} defaults to 3333.
2131 Note: when using "gdb_port pipe", increasing the default remote timeout in
2132 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2133 cause initialization to fail with "Unknown remote qXfer reply: OK".
2135 @end deffn
2137 @deffn {Command} tcl_port [number]
2138 Specify or query the port used for a simplified RPC
2139 connection that can be used by clients to issue TCL commands and get the
2140 output from the Tcl engine.
2141 Intended as a machine interface.
2142 When not specified during the configuration stage,
2143 the port @var{number} defaults to 6666.
2145 @end deffn
2147 @deffn {Command} telnet_port [number]
2148 Specify or query the
2149 port on which to listen for incoming telnet connections.
2150 This port is intended for interaction with one human through TCL commands.
2151 When not specified during the configuration stage,
2152 the port @var{number} defaults to 4444.
2153 When specified as zero, this port is not activated.
2154 @end deffn
2156 @anchor{gdbconfiguration}
2157 @section GDB Configuration
2158 @cindex GDB
2159 @cindex GDB configuration
2160 You can reconfigure some GDB behaviors if needed.
2161 The ones listed here are static and global.
2162 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2163 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2165 @anchor{gdbbreakpointoverride}
2166 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2167 Force breakpoint type for gdb @command{break} commands.
2168 This option supports GDB GUIs which don't
2169 distinguish hard versus soft breakpoints, if the default OpenOCD and
2170 GDB behaviour is not sufficient. GDB normally uses hardware
2171 breakpoints if the memory map has been set up for flash regions.
2172 @end deffn
2174 @anchor{gdbflashprogram}
2175 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2176 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2177 vFlash packet is received.
2178 The default behaviour is @option{enable}.
2179 @end deffn
2181 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2182 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2183 requested. GDB will then know when to set hardware breakpoints, and program flash
2184 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2185 for flash programming to work.
2186 Default behaviour is @option{enable}.
2187 @xref{gdbflashprogram,,gdb_flash_program}.
2188 @end deffn
2190 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2191 Specifies whether data aborts cause an error to be reported
2192 by GDB memory read packets.
2193 The default behaviour is @option{disable};
2194 use @option{enable} see these errors reported.
2195 @end deffn
2197 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2198 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2199 The default behaviour is @option{enable}.
2200 @end deffn
2202 @deffn {Command} gdb_save_tdesc
2203 Saves the target descripton file to the local file system.
2205 The file name is @i{target_name}.xml.
2206 @end deffn
2208 @anchor{eventpolling}
2209 @section Event Polling
2211 Hardware debuggers are parts of asynchronous systems,
2212 where significant events can happen at any time.
2213 The OpenOCD server needs to detect some of these events,
2214 so it can report them to through TCL command line
2215 or to GDB.
2217 Examples of such events include:
2219 @itemize
2220 @item One of the targets can stop running ... maybe it triggers
2221 a code breakpoint or data watchpoint, or halts itself.
2222 @item Messages may be sent over ``debug message'' channels ... many
2223 targets support such messages sent over JTAG,
2224 for receipt by the person debugging or tools.
2225 @item Loss of power ... some adapters can detect these events.
2226 @item Resets not issued through JTAG ... such reset sources
2227 can include button presses or other system hardware, sometimes
2228 including the target itself (perhaps through a watchdog).
2229 @item Debug instrumentation sometimes supports event triggering
2230 such as ``trace buffer full'' (so it can quickly be emptied)
2231 or other signals (to correlate with code behavior).
2232 @end itemize
2234 None of those events are signaled through standard JTAG signals.
2235 However, most conventions for JTAG connectors include voltage
2236 level and system reset (SRST) signal detection.
2237 Some connectors also include instrumentation signals, which
2238 can imply events when those signals are inputs.
2240 In general, OpenOCD needs to periodically check for those events,
2241 either by looking at the status of signals on the JTAG connector
2242 or by sending synchronous ``tell me your status'' JTAG requests
2243 to the various active targets.
2244 There is a command to manage and monitor that polling,
2245 which is normally done in the background.
2247 @deffn Command poll [@option{on}|@option{off}]
2248 Poll the current target for its current state.
2249 (Also, @pxref{targetcurstate,,target curstate}.)
2250 If that target is in debug mode, architecture
2251 specific information about the current state is printed.
2252 An optional parameter
2253 allows background polling to be enabled and disabled.
2255 You could use this from the TCL command shell, or
2256 from GDB using @command{monitor poll} command.
2257 Leave background polling enabled while you're using GDB.
2258 @example
2259 > poll
2260 background polling: on
2261 target state: halted
2262 target halted in ARM state due to debug-request, \
2263 current mode: Supervisor
2264 cpsr: 0x800000d3 pc: 0x11081bfc
2265 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2266 >
2267 @end example
2268 @end deffn
2270 @node Debug Adapter Configuration
2271 @chapter Debug Adapter Configuration
2272 @cindex config file, interface
2273 @cindex interface config file
2275 Correctly installing OpenOCD includes making your operating system give
2276 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2277 are used to select which one is used, and to configure how it is used.
2279 @quotation Note
2280 Because OpenOCD started out with a focus purely on JTAG, you may find
2281 places where it wrongly presumes JTAG is the only transport protocol
2282 in use. Be aware that recent versions of OpenOCD are removing that
2283 limitation. JTAG remains more functional than most other transports.
2284 Other transports do not support boundary scan operations, or may be
2285 specific to a given chip vendor. Some might be usable only for
2286 programming flash memory, instead of also for debugging.
2287 @end quotation
2289 Debug Adapters/Interfaces/Dongles are normally configured
2290 through commands in an interface configuration
2291 file which is sourced by your @file{openocd.cfg} file, or
2292 through a command line @option{-f interface/....cfg} option.
2294 @example
2295 source [find interface/olimex-jtag-tiny.cfg]
2296 @end example
2298 These commands tell
2299 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2300 A few cases are so simple that you only need to say what driver to use:
2302 @example
2303 # jlink interface
2304 interface jlink
2305 @end example
2307 Most adapters need a bit more configuration than that.
2310 @section Interface Configuration
2312 The interface command tells OpenOCD what type of debug adapter you are
2313 using. Depending on the type of adapter, you may need to use one or
2314 more additional commands to further identify or configure the adapter.
2316 @deffn {Config Command} {interface} name
2317 Use the interface driver @var{name} to connect to the
2318 target.
2319 @end deffn
2321 @deffn Command {interface_list}
2322 List the debug adapter drivers that have been built into
2323 the running copy of OpenOCD.
2324 @end deffn
2325 @deffn Command {interface transports} transport_name+
2326 Specifies the transports supported by this debug adapter.
2327 The adapter driver builds-in similar knowledge; use this only
2328 when external configuration (such as jumpering) changes what
2329 the hardware can support.
2330 @end deffn
2334 @deffn Command {adapter_name}
2335 Returns the name of the debug adapter driver being used.
2336 @end deffn
2338 @section Interface Drivers
2340 Each of the interface drivers listed here must be explicitly
2341 enabled when OpenOCD is configured, in order to be made
2342 available at run time.
2344 @deffn {Interface Driver} {amt_jtagaccel}
2345 Amontec Chameleon in its JTAG Accelerator configuration,
2346 connected to a PC's EPP mode parallel port.
2347 This defines some driver-specific commands:
2349 @deffn {Config Command} {parport_port} number
2350 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2351 the number of the @file{/dev/parport} device.
2352 @end deffn
2354 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2355 Displays status of RTCK option.
2356 Optionally sets that option first.
2357 @end deffn
2358 @end deffn
2360 @deffn {Interface Driver} {arm-jtag-ew}
2361 Olimex ARM-JTAG-EW USB adapter
2362 This has one driver-specific command:
2364 @deffn Command {armjtagew_info}
2365 Logs some status
2366 @end deffn
2367 @end deffn
2369 @deffn {Interface Driver} {at91rm9200}
2370 Supports bitbanged JTAG from the local system,
2371 presuming that system is an Atmel AT91rm9200
2372 and a specific set of GPIOs is used.
2373 @c command: at91rm9200_device NAME
2374 @c chooses among list of bit configs ... only one option
2375 @end deffn
2377 @deffn {Interface Driver} {cmsis-dap}
2378 ARM CMSIS-DAP compliant based adapter.
2380 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2381 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2382 the driver will attempt to auto detect the CMSIS-DAP device.
2383 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2384 @example
2385 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2386 @end example
2387 @end deffn
2389 @deffn {Config Command} {cmsis_dap_serial} [serial]
2390 Specifies the @var{serial} of the CMSIS-DAP device to use.
2391 If not specified, serial numbers are not considered.
2392 @end deffn
2394 @deffn {Command} {cmsis-dap info}
2395 Display various device information, like hardware version, firmware version, current bus status.
2396 @end deffn
2397 @end deffn
2399 @deffn {Interface Driver} {dummy}
2400 A dummy software-only driver for debugging.
2401 @end deffn
2403 @deffn {Interface Driver} {ep93xx}
2404 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2405 @end deffn
2407 @deffn {Interface Driver} {ft2232}
2408 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2410 Note that this driver has several flaws and the @command{ftdi} driver is
2411 recommended as its replacement.
2413 These interfaces have several commands, used to configure the driver
2414 before initializing the JTAG scan chain:
2416 @deffn {Config Command} {ft2232_device_desc} description
2417 Provides the USB device description (the @emph{iProduct string})
2418 of the FTDI FT2232 device. If not
2419 specified, the FTDI default value is used. This setting is only valid
2420 if compiled with FTD2XX support.
2421 @end deffn
2423 @deffn {Config Command} {ft2232_serial} serial-number
2424 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2425 in case the vendor provides unique IDs and more than one FT2232 device
2426 is connected to the host.
2427 If not specified, serial numbers are not considered.
2428 (Note that USB serial numbers can be arbitrary Unicode strings,
2429 and are not restricted to containing only decimal digits.)
2430 @end deffn
2432 @deffn {Config Command} {ft2232_layout} name
2433 Each vendor's FT2232 device can use different GPIO signals
2434 to control output-enables, reset signals, and LEDs.
2435 Currently valid layout @var{name} values include:
2436 @itemize @minus
2437 @item @b{axm0432_jtag} Axiom AXM-0432
2438 @item @b{comstick} Hitex STR9 comstick
2439 @item @b{cortino} Hitex Cortino JTAG interface
2440 @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
2441 either for the local Cortex-M3 (SRST only)
2442 or in a passthrough mode (neither SRST nor TRST)
2443 This layout can not support the SWO trace mechanism, and should be
2444 used only for older boards (before rev C).
2445 @item @b{luminary_icdi} This layout should be used with most TI/Luminary
2446 eval boards, including Rev C LM3S811 eval boards and the eponymous
2447 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2448 to debug some other target. It can support the SWO trace mechanism.
2449 @item @b{flyswatter} Tin Can Tools Flyswatter
2450 @item @b{icebear} ICEbear JTAG adapter from Section 5
2451 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2452 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2453 @item @b{m5960} American Microsystems M5960
2454 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2455 @item @b{oocdlink} OOCDLink
2456 @c oocdlink ~= jtagkey_prototype_v1
2457 @item @b{redbee-econotag} Integrated with a Redbee development board.
2458 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2459 @item @b{sheevaplug} Marvell Sheevaplug development kit
2460 @item @b{signalyzer} Xverve Signalyzer
2461 @item @b{stm32stick} Hitex STM32 Performance Stick
2462 @item @b{turtelizer2} egnite Software turtelizer2
2463 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2464 @end itemize
2465 @end deffn
2467 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2468 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2469 default values are used.
2470 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2471 @example
2472 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2473 @end example
2474 @end deffn
2476 @deffn {Config Command} {ft2232_latency} ms
2477 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2478 ft2232_read() fails to return the expected number of bytes. This can be caused by
2479 USB communication delays and has proved hard to reproduce and debug. Setting the
2480 FT2232 latency timer to a larger value increases delays for short USB packets but it
2481 also reduces the risk of timeouts before receiving the expected number of bytes.
2482 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2483 @end deffn
2485 @deffn {Config Command} {ft2232_channel} channel
2486 Used to select the channel of the ft2232 chip to use (between 1 and 4).
2487 The default value is 1.
2488 @end deffn
2490 For example, the interface config file for a
2491 Turtelizer JTAG Adapter looks something like this:
2493 @example
2494 interface ft2232
2495 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2496 ft2232_layout turtelizer2
2497 ft2232_vid_pid 0x0403 0xbdc8
2498 @end example
2499 @end deffn
2501 @deffn {Interface Driver} {ftdi}
2502 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2503 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2504 It is a complete rewrite to address a large number of problems with the ft2232
2505 interface driver.
2507 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2508 bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
2509 consistently faster than the ft2232 driver, sometimes several times faster.
2511 A major improvement of this driver is that support for new FTDI based adapters
2512 can be added competely through configuration files, without the need to patch
2513 and rebuild OpenOCD.
2515 The driver uses a signal abstraction to enable Tcl configuration files to
2516 define outputs for one or several FTDI GPIO. These outputs can then be
2517 controlled using the @command{ftdi_set_signal} command. Special signal names
2518 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2519 will be used for their customary purpose.
2521 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2522 be controlled differently. In order to support tristateable signals such as
2523 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2524 signal. The following output buffer configurations are supported:
2526 @itemize @minus
2527 @item Push-pull with one FTDI output as (non-)inverted data line
2528 @item Open drain with one FTDI output as (non-)inverted output-enable
2529 @item Tristate with one FTDI output as (non-)inverted data line and another
2530 FTDI output as (non-)inverted output-enable
2531 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2532 switching data and direction as necessary
2533 @end itemize
2535 These interfaces have several commands, used to configure the driver
2536 before initializing the JTAG scan chain:
2538 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2539 The vendor ID and product ID of the adapter. If not specified, the FTDI
2540 default values are used.
2541 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2542 @example
2543 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2544 @end example
2545 @end deffn
2547 @deffn {Config Command} {ftdi_device_desc} description
2548 Provides the USB device description (the @emph{iProduct string})
2549 of the adapter. If not specified, the device description is ignored
2550 during device selection.
2551 @end deffn
2553 @deffn {Config Command} {ftdi_serial} serial-number
2554 Specifies the @var{serial-number} of the adapter to use,
2555 in case the vendor provides unique IDs and more than one adapter
2556 is connected to the host.
2557 If not specified, serial numbers are not considered.
2558 (Note that USB serial numbers can be arbitrary Unicode strings,
2559 and are not restricted to containing only decimal digits.)
2560 @end deffn
2562 @deffn {Config Command} {ftdi_channel} channel
2563 Selects the channel of the FTDI device to use for MPSSE operations. Most
2564 adapters use the default, channel 0, but there are exceptions.
2565 @end deffn
2567 @deffn {Config Command} {ftdi_layout_init} data direction
2568 Specifies the initial values of the FTDI GPIO data and direction registers.
2569 Each value is a 16-bit number corresponding to the concatenation of the high
2570 and low FTDI GPIO registers. The values should be selected based on the
2571 schematics of the adapter, such that all signals are set to safe levels with
2572 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2573 and initially asserted reset signals.
2574 @end deffn
2576 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2577 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2578 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2579 register bitmasks to tell the driver the connection and type of the output
2580 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2581 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2582 used with inverting data inputs and @option{-data} with non-inverting inputs.
2583 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2584 not-output-enable) input to the output buffer is connected.
2586 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2587 simple open-collector transistor driver would be specified with @option{-oe}
2588 only. In that case the signal can only be set to drive low or to Hi-Z and the
2589 driver will complain if the signal is set to drive high. Which means that if
2590 it's a reset signal, @command{reset_config} must be specified as
2591 @option{srst_open_drain}, not @option{srst_push_pull}.
2593 A special case is provided when @option{-data} and @option{-oe} is set to the
2594 same bitmask. Then the FTDI pin is considered being connected straight to the
2595 target without any buffer. The FTDI pin is then switched between output and
2596 input as necessary to provide the full set of low, high and Hi-Z
2597 characteristics. In all other cases, the pins specified in a signal definition
2598 are always driven by the FTDI.
2600 If @option{-alias} or @option{-nalias} is used, the signal is created
2601 identical (or with data inverted) to an already specified signal
2602 @var{name}.
2603 @end deffn
2605 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2606 Set a previously defined signal to the specified level.
2607 @itemize @minus
2608 @item @option{0}, drive low
2609 @item @option{1}, drive high
2610 @item @option{z}, set to high-impedance
2611 @end itemize
2612 @end deffn
2614 For example adapter definitions, see the configuration files shipped in the
2615 @file{interface/ftdi} directory.
2616 @end deffn
2618 @deffn {Interface Driver} {remote_bitbang}
2619 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2620 with a remote process and sends ASCII encoded bitbang requests to that process
2621 instead of directly driving JTAG.
2623 The remote_bitbang driver is useful for debugging software running on
2624 processors which are being simulated.
2626 @deffn {Config Command} {remote_bitbang_port} number
2627 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2628 sockets instead of TCP.
2629 @end deffn
2631 @deffn {Config Command} {remote_bitbang_host} hostname
2632 Specifies the hostname of the remote process to connect to using TCP, or the
2633 name of the UNIX socket to use if remote_bitbang_port is 0.
2634 @end deffn
2636 For example, to connect remotely via TCP to the host foobar you might have
2637 something like:
2639 @example
2640 interface remote_bitbang
2641 remote_bitbang_port 3335
2642 remote_bitbang_host foobar
2643 @end example
2645 To connect to another process running locally via UNIX sockets with socket
2646 named mysocket:
2648 @example
2649 interface remote_bitbang
2650 remote_bitbang_port 0
2651 remote_bitbang_host mysocket
2652 @end example
2653 @end deffn
2655 @deffn {Interface Driver} {usb_blaster}
2656 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2657 for FTDI chips. These interfaces have several commands, used to
2658 configure the driver before initializing the JTAG scan chain:
2660 @deffn {Config Command} {usb_blaster_device_desc} description
2661 Provides the USB device description (the @emph{iProduct string})
2662 of the FTDI FT245 device. If not
2663 specified, the FTDI default value is used. This setting is only valid
2664 if compiled with FTD2XX support.
2665 @end deffn
2667 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2668 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2669 default values are used.
2670 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2671 Altera USB-Blaster (default):
2672 @example
2673 usb_blaster_vid_pid 0x09FB 0x6001
2674 @end example
2675 The following VID/PID is for Kolja Waschk's USB JTAG:
2676 @example
2677 usb_blaster_vid_pid 0x16C0 0x06AD
2678 @end example
2679 @end deffn
2681 @deffn {Command} {usb_blaster_pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2682 Sets the state or function of the unused GPIO pins on USB-Blasters
2683 (pins 6 and 8 on the female JTAG header). These pins can be used as
2684 SRST and/or TRST provided the appropriate connections are made on the
2685 target board.
2687 For example, to use pin 6 as SRST:
2688 @example
2689 usb_blaster_pin pin6 s
2690 reset_config srst_only
2691 @end example
2692 @end deffn
2694 @deffn {Command} {usb_blaster_lowlevel_driver} (@option{ftdi}|@option{ftd2xx}|@option{ublast2})
2695 Chooses the low level access method for the adapter. If not specified,
2696 @option{ftdi} is selected unless it wasn't enabled during the
2697 configure stage. USB-Blaster II needs @option{ublast2}.
2698 @end deffn
2700 @deffn {Command} {usb_blaster_firmware} @var{path}
2701 This command specifies @var{path} to access USB-Blaster II firmware
2702 image. To be used with USB-Blaster II only.
2703 @end deffn
2705 @end deffn
2707 @deffn {Interface Driver} {gw16012}
2708 Gateworks GW16012 JTAG programmer.
2709 This has one driver-specific command:
2711 @deffn {Config Command} {parport_port} [port_number]
2712 Display either the address of the I/O port
2713 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2714 If a parameter is provided, first switch to use that port.
2715 This is a write-once setting.
2716 @end deffn
2717 @end deffn
2719 @deffn {Interface Driver} {jlink}
2720 Segger J-Link family of USB adapters. It currently supports JTAG and SWD transports.
2722 @quotation Compatibility Note
2723 Segger released many firmware versions for the many harware versions they
2724 produced. OpenOCD was extensively tested and intended to run on all of them,
2725 but some combinations were reported as incompatible. As a general
2726 recommendation, it is advisable to use the latest firmware version
2727 available for each hardware version. However the current V8 is a moving
2728 target, and Segger firmware versions released after the OpenOCD was
2729 released may not be compatible. In such cases it is recommended to
2730 revert to the last known functional version. For 0.5.0, this is from
2731 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2732 version is from "May 3 2012 18:36:22", packed with 4.46f.
2733 @end quotation
2735 @deffn {Command} {jlink caps}
2736 Display the device firmware capabilities.
2737 @end deffn
2738 @deffn {Command} {jlink info}
2739 Display various device information, like hardware version, firmware version, current bus status.
2740 @end deffn
2741 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2742 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2743 @end deffn
2744 @deffn {Command} {jlink config}
2745 Display the J-Link configuration.
2746 @end deffn
2747 @deffn {Command} {jlink config kickstart} [val]
2748 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2749 @end deffn
2750 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2751 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2752 @end deffn
2753 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2754 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2755 E the bit of the subnet mask and
2756 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2757 @end deffn
2758 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2759 Set the USB address; this will also change the product id. Without argument, show the USB address.
2760 @end deffn
2761 @deffn {Command} {jlink config reset}
2762 Reset the current configuration.
2763 @end deffn
2764 @deffn {Command} {jlink config save}
2765 Save the current configuration to the internal persistent storage.
2766 @end deffn
2767 @deffn {Config} {jlink pid} val
2768 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2769 @end deffn
2770 @deffn {Config} {jlink serial} serial-number
2771 Set the @var{serial-number} of the interface, in case more than one adapter is connected to the host.
2772 If not specified, serial numbers are not considered.
2774 Note that there may be leading zeros in the @var{serial-number} string
2775 that will not show in the Segger software, but must be specified here.
2776 Debug level 3 output contains serial numbers if there is a mismatch.
2778 As a configuration command, it can be used only before 'init'.
2779 @end deffn
2780 @end deffn
2782 @deffn {Interface Driver} {parport}
2783 Supports PC parallel port bit-banging cables:
2784 Wigglers, PLD download cable, and more.
2785 These interfaces have several commands, used to configure the driver
2786 before initializing the JTAG scan chain:
2788 @deffn {Config Command} {parport_cable} name
2789 Set the layout of the parallel port cable used to connect to the target.
2790 This is a write-once setting.
2791 Currently valid cable @var{name} values include:
2793 @itemize @minus
2794 @item @b{altium} Altium Universal JTAG cable.
2795 @item @b{arm-jtag} Same as original wiggler except SRST and
2796 TRST connections reversed and TRST is also inverted.
2797 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2798 in configuration mode. This is only used to
2799 program the Chameleon itself, not a connected target.
2800 @item @b{dlc5} The Xilinx Parallel cable III.
2801 @item @b{flashlink} The ST Parallel cable.
2802 @item @b{lattice} Lattice ispDOWNLOAD Cable
2803 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2804 some versions of
2805 Amontec's Chameleon Programmer. The new version available from
2806 the website uses the original Wiggler layout ('@var{wiggler}')
2807 @item @b{triton} The parallel port adapter found on the
2808 ``Karo Triton 1 Development Board''.
2809 This is also the layout used by the HollyGates design
2810 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2811 @item @b{wiggler} The original Wiggler layout, also supported by
2812 several clones, such as the Olimex ARM-JTAG
2813 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2814 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2815 @end itemize
2816 @end deffn
2818 @deffn {Config Command} {parport_port} [port_number]
2819 Display either the address of the I/O port
2820 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2821 If a parameter is provided, first switch to use that port.
2822 This is a write-once setting.
2824 When using PPDEV to access the parallel port, use the number of the parallel port:
2825 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2826 you may encounter a problem.
2827 @end deffn
2829 @deffn Command {parport_toggling_time} [nanoseconds]
2830 Displays how many nanoseconds the hardware needs to toggle TCK;
2831 the parport driver uses this value to obey the
2832 @command{adapter_khz} configuration.
2833 When the optional @var{nanoseconds} parameter is given,
2834 that setting is changed before displaying the current value.
2836 The default setting should work reasonably well on commodity PC hardware.
2837 However, you may want to calibrate for your specific hardware.
2838 @quotation Tip
2839 To measure the toggling time with a logic analyzer or a digital storage
2840 oscilloscope, follow the procedure below:
2841 @example
2842 > parport_toggling_time 1000
2843 > adapter_khz 500
2844 @end example
2845 This sets the maximum JTAG clock speed of the hardware, but
2846 the actual speed probably deviates from the requested 500 kHz.
2847 Now, measure the time between the two closest spaced TCK transitions.
2848 You can use @command{runtest 1000} or something similar to generate a
2849 large set of samples.
2850 Update the setting to match your measurement:
2851 @example
2852 > parport_toggling_time <measured nanoseconds>
2853 @end example
2854 Now the clock speed will be a better match for @command{adapter_khz rate}
2855 commands given in OpenOCD scripts and event handlers.
2857 You can do something similar with many digital multimeters, but note
2858 that you'll probably need to run the clock continuously for several
2859 seconds before it decides what clock rate to show. Adjust the
2860 toggling time up or down until the measured clock rate is a good
2861 match for the adapter_khz rate you specified; be conservative.
2862 @end quotation
2863 @end deffn
2865 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2866 This will configure the parallel driver to write a known
2867 cable-specific value to the parallel interface on exiting OpenOCD.
2868 @end deffn
2870 For example, the interface configuration file for a
2871 classic ``Wiggler'' cable on LPT2 might look something like this:
2873 @example
2874 interface parport
2875 parport_port 0x278
2876 parport_cable wiggler
2877 @end example
2878 @end deffn
2880 @deffn {Interface Driver} {presto}
2881 ASIX PRESTO USB JTAG programmer.
2882 @deffn {Config Command} {presto_serial} serial_string
2883 Configures the USB serial number of the Presto device to use.
2884 @end deffn
2885 @end deffn
2887 @deffn {Interface Driver} {rlink}
2888 Raisonance RLink USB adapter
2889 @end deffn
2891 @deffn {Interface Driver} {usbprog}
2892 usbprog is a freely programmable USB adapter.
2893 @end deffn
2895 @deffn {Interface Driver} {vsllink}
2896 vsllink is part of Versaloon which is a versatile USB programmer.
2898 @quotation Note
2899 This defines quite a few driver-specific commands,
2900 which are not currently documented here.
2901 @end quotation
2902 @end deffn
2904 @anchor{hla_interface}
2905 @deffn {Interface Driver} {hla}
2906 This is a driver that supports multiple High Level Adapters.
2907 This type of adapter does not expose some of the lower level api's
2908 that OpenOCD would normally use to access the target.
2910 Currently supported adapters include the ST STLINK and TI ICDI.
2911 STLINK firmware version >= V2.J21.S4 recommended due to issues with earlier
2912 versions of firmware where serial number is reset after first use. Suggest
2913 using ST firmware update utility to upgrade STLINK firmware even if current
2914 version reported is V2.J21.S4.
2916 @deffn {Config Command} {hla_device_desc} description
2917 Currently Not Supported.
2918 @end deffn
2920 @deffn {Config Command} {hla_serial} serial
2921 Specifies the serial number of the adapter.
2922 @end deffn
2924 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
2925 Specifies the adapter layout to use.
2926 @end deffn
2928 @deffn {Config Command} {hla_vid_pid} vid pid
2929 The vendor ID and product ID of the device.
2930 @end deffn
2932 @deffn {Command} {hla_command} command
2933 Execute a custom adapter-specific command. The @var{command} string is
2934 passed as is to the underlying adapter layout handler.
2935 @end deffn
2936 @end deffn
2938 @deffn {Interface Driver} {opendous}
2939 opendous-jtag is a freely programmable USB adapter.
2940 @end deffn
2942 @deffn {Interface Driver} {ulink}
2943 This is the Keil ULINK v1 JTAG debugger.
2944 @end deffn
2946 @deffn {Interface Driver} {ZY1000}
2947 This is the Zylin ZY1000 JTAG debugger.
2948 @end deffn
2950 @quotation Note
2951 This defines some driver-specific commands,
2952 which are not currently documented here.
2953 @end quotation
2955 @deffn Command power [@option{on}|@option{off}]
2956 Turn power switch to target on/off.
2957 No arguments: print status.
2958 @end deffn
2960 @deffn {Interface Driver} {bcm2835gpio}
2961 This SoC is present in Raspberry Pi which is a cheap single-board computer
2962 exposing some GPIOs on its expansion header.
2964 The driver accesses memory-mapped GPIO peripheral registers directly
2965 for maximum performance, but the only possible race condition is for
2966 the pins' modes/muxing (which is highly unlikely), so it should be
2967 able to coexist nicely with both sysfs bitbanging and various
2968 peripherals' kernel drivers. The driver restores the previous
2969 configuration on exit.
2971 See @file{interface/raspberrypi-native.cfg} for a sample config and
2972 pinout.
2974 @end deffn
2976 @section Transport Configuration
2977 @cindex Transport
2978 As noted earlier, depending on the version of OpenOCD you use,
2979 and the debug adapter you are using,
2980 several transports may be available to
2981 communicate with debug targets (or perhaps to program flash memory).
2982 @deffn Command {transport list}
2983 displays the names of the transports supported by this
2984 version of OpenOCD.
2985 @end deffn
2987 @deffn Command {transport select} @option{transport_name}
2988 Select which of the supported transports to use in this OpenOCD session.
2990 When invoked with @option{transport_name}, attempts to select the named
2991 transport. The transport must be supported by the debug adapter
2992 hardware and by the version of OpenOCD you are using (including the
2993 adapter's driver).
2995 If no transport has been selected and no @option{transport_name} is
2996 provided, @command{transport select} auto-selects the first transport
2997 supported by the debug adapter.
2999 @command{transport select} always returns the name of the session's selected
3000 transport, if any.
3001 @end deffn
3003 @subsection JTAG Transport
3004 @cindex JTAG
3005 JTAG is the original transport supported by OpenOCD, and most
3006 of the OpenOCD commands support it.
3007 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3008 each of which must be explicitly declared.
3009 JTAG supports both debugging and boundary scan testing.
3010 Flash programming support is built on top of debug support.
3012 JTAG transport is selected with the command @command{transport select
3013 jtag}. Unless your adapter uses @ref{hla_interface,the hla interface
3014 driver}, in which case the command is @command{transport select
3015 hla_jtag}.
3017 @subsection SWD Transport
3018 @cindex SWD
3019 @cindex Serial Wire Debug
3020 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3021 Debug Access Point (DAP, which must be explicitly declared.
3022 (SWD uses fewer signal wires than JTAG.)
3023 SWD is debug-oriented, and does not support boundary scan testing.
3024 Flash programming support is built on top of debug support.
3025 (Some processors support both JTAG and SWD.)
3027 SWD transport is selected with the command @command{transport select
3028 swd}. Unless your adapter uses @ref{hla_interface,the hla interface
3029 driver}, in which case the command is @command{transport select
3030 hla_swd}.
3032 @deffn Command {swd newdap} ...
3033 Declares a single DAP which uses SWD transport.
3034 Parameters are currently the same as "jtag newtap" but this is
3035 expected to change.
3036 @end deffn
3037 @deffn Command {swd wcr trn prescale}
3038 Updates TRN (turnaraound delay) and prescaling.fields of the
3039 Wire Control Register (WCR).
3040 No parameters: displays current settings.
3041 @end deffn
3043 @subsection SPI Transport
3044 @cindex SPI
3045 @cindex Serial Peripheral Interface
3046 The Serial Peripheral Interface (SPI) is a general purpose transport
3047 which uses four wire signaling. Some processors use it as part of a
3048 solution for flash programming.
3050 @anchor{jtagspeed}
3051 @section JTAG Speed
3052 JTAG clock setup is part of system setup.
3053 It @emph{does not belong with interface setup} since any interface
3054 only knows a few of the constraints for the JTAG clock speed.
3055 Sometimes the JTAG speed is
3056 changed during the target initialization process: (1) slow at
3057 reset, (2) program the CPU clocks, (3) run fast.
3058 Both the "slow" and "fast" clock rates are functions of the
3059 oscillators used, the chip, the board design, and sometimes
3060 power management software that may be active.
3062 The speed used during reset, and the scan chain verification which
3063 follows reset, can be adjusted using a @code{reset-start}
3064 target event handler.
3065 It can then be reconfigured to a faster speed by a
3066 @code{reset-init} target event handler after it reprograms those
3067 CPU clocks, or manually (if something else, such as a boot loader,
3068 sets up those clocks).
3069 @xref{targetevents,,Target Events}.
3070 When the initial low JTAG speed is a chip characteristic, perhaps
3071 because of a required oscillator speed, provide such a handler
3072 in the target config file.
3073 When that speed is a function of a board-specific characteristic
3074 such as which speed oscillator is used, it belongs in the board
3075 config file instead.
3076 In both cases it's safest to also set the initial JTAG clock rate
3077 to that same slow speed, so that OpenOCD never starts up using a
3078 clock speed that's faster than the scan chain can support.
3080 @example
3081 jtag_rclk 3000
3082 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3083 @end example
3085 If your system supports adaptive clocking (RTCK), configuring
3086 JTAG to use that is probably the most robust approach.
3087 However, it introduces delays to synchronize clocks; so it
3088 may not be the fastest solution.
3090 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3091 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3092 which support adaptive clocking.
3094 @deffn {Command} adapter_khz max_speed_kHz
3095 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3096 JTAG interfaces usually support a limited number of
3097 speeds. The speed actually used won't be faster
3098 than the speed specified.
3100 Chip data sheets generally include a top JTAG clock rate.
3101 The actual rate is often a function of a CPU core clock,
3102 and is normally less than that peak rate.
3103 For example, most ARM cores accept at most one sixth of the CPU clock.
3105 Speed 0 (khz) selects RTCK method.
3106 @xref{faqrtck,,FAQ RTCK}.
3107 If your system uses RTCK, you won't need to change the
3108 JTAG clocking after setup.
3109 Not all interfaces, boards, or targets support ``rtck''.
3110 If the interface device can not
3111 support it, an error is returned when you try to use RTCK.
3112 @end deffn
3114 @defun jtag_rclk fallback_speed_kHz
3115 @cindex adaptive clocking
3116 @cindex RTCK
3117 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3118 If that fails (maybe the interface, board, or target doesn't
3119 support it), falls back to the specified frequency.
3120 @example
3121 # Fall back to 3mhz if RTCK is not supported
3122 jtag_rclk 3000
3123 @end example
3124 @end defun
3126 @node Reset Configuration
3127 @chapter Reset Configuration
3128 @cindex Reset Configuration
3130 Every system configuration may require a different reset
3131 configuration. This can also be quite confusing.
3132 Resets also interact with @var{reset-init} event handlers,
3133 which do things like setting up clocks and DRAM, and
3134 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3135 They can also interact with JTAG routers.
3136 Please see the various board files for examples.
3138 @quotation Note
3139 To maintainers and integrators:
3140 Reset configuration touches several things at once.
3141 Normally the board configuration file
3142 should define it and assume that the JTAG adapter supports
3143 everything that's wired up to the board's JTAG connector.
3145 However, the target configuration file could also make note
3146 of something the silicon vendor has done inside the chip,
3147 which will be true for most (or all) boards using that chip.
3148 And when the JTAG adapter doesn't support everything, the
3149 user configuration file will need to override parts of
3150 the reset configuration provided by other files.
3151 @end quotation
3153 @section Types of Reset
3155 There are many kinds of reset possible through JTAG, but
3156 they may not all work with a given board and adapter.
3157 That's part of why reset configuration can be error prone.
3159 @itemize @bullet
3160 @item
3161 @emph{System Reset} ... the @emph{SRST} hardware signal
3162 resets all chips connected to the JTAG adapter, such as processors,
3163 power management chips, and I/O controllers. Normally resets triggered
3164 with this signal behave exactly like pressing a RESET button.
3165 @item
3166 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3167 just the TAP controllers connected to the JTAG adapter.
3168 Such resets should not be visible to the rest of the system; resetting a
3169 device's TAP controller just puts that controller into a known state.
3170 @item
3171 @emph{Emulation Reset} ... many devices can be reset through JTAG
3172 commands. These resets are often distinguishable from system
3173 resets, either explicitly (a "reset reason" register says so)
3174 or implicitly (not all parts of the chip get reset).
3175 @item
3176 @emph{Other Resets} ... system-on-chip devices often support
3177 several other types of reset.
3178 You may need to arrange that a watchdog timer stops
3179 while debugging, preventing a watchdog reset.
3180 There may be individual module resets.
3181 @end itemize
3183 In the best case, OpenOCD can hold SRST, then reset
3184 the TAPs via TRST and send commands through JTAG to halt the
3185 CPU at the reset vector before the 1st instruction is executed.
3186 Then when it finally releases the SRST signal, the system is
3187 halted under debugger control before any code has executed.
3188 This is the behavior required to support the @command{reset halt}
3189 and @command{reset init} commands; after @command{reset init} a
3190 board-specific script might do things like setting up DRAM.
3191 (@xref{resetcommand,,Reset Command}.)
3193 @anchor{srstandtrstissues}
3194 @section SRST and TRST Issues
3196 Because SRST and TRST are hardware signals, they can have a
3197 variety of system-specific constraints. Some of the most
3198 common issues are:
3200 @itemize @bullet
3202 @item @emph{Signal not available} ... Some boards don't wire
3203 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3204 support such signals even if they are wired up.
3205 Use the @command{reset_config} @var{signals} options to say
3206 when either of those signals is not connected.
3207 When SRST is not available, your code might not be able to rely
3208 on controllers having been fully reset during code startup.
3209 Missing TRST is not a problem, since JTAG-level resets can
3210 be triggered using with TMS signaling.
3212 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3213 adapter will connect SRST to TRST, instead of keeping them separate.
3214 Use the @command{reset_config} @var{combination} options to say
3215 when those signals aren't properly independent.
3217 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3218 delay circuit, reset supervisor, or on-chip features can extend
3219 the effect of a JTAG adapter's reset for some time after the adapter
3220 stops issuing the reset. For example, there may be chip or board
3221 requirements that all reset pulses last for at least a
3222 certain amount of time; and reset buttons commonly have
3223 hardware debouncing.
3224 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3225 commands to say when extra delays are needed.
3227 @item @emph{Drive type} ... Reset lines often have a pullup
3228 resistor, letting the JTAG interface treat them as open-drain
3229 signals. But that's not a requirement, so the adapter may need
3230 to use push/pull output drivers.
3231 Also, with weak pullups it may be advisable to drive
3232 signals to both levels (push/pull) to minimize rise times.
3233 Use the @command{reset_config} @var{trst_type} and
3234 @var{srst_type} parameters to say how to drive reset signals.
3236 @item @emph{Special initialization} ... Targets sometimes need
3237 special JTAG initialization sequences to handle chip-specific
3238 issues (not limited to errata).
3239 For example, certain JTAG commands might need to be issued while
3240 the system as a whole is in a reset state (SRST active)
3241 but the JTAG scan chain is usable (TRST inactive).
3242 Many systems treat combined assertion of SRST and TRST as a
3243 trigger for a harder reset than SRST alone.
3244 Such custom reset handling is discussed later in this chapter.
3245 @end itemize
3247 There can also be other issues.
3248 Some devices don't fully conform to the JTAG specifications.
3249 Trivial system-specific differences are common, such as
3250 SRST and TRST using slightly different names.
3251 There are also vendors who distribute key JTAG documentation for
3252 their chips only to developers who have signed a Non-Disclosure
3253 Agreement (NDA).
3255 Sometimes there are chip-specific extensions like a requirement to use
3256 the normally-optional TRST signal (precluding use of JTAG adapters which
3257 don't pass TRST through), or needing extra steps to complete a TAP reset.
3259 In short, SRST and especially TRST handling may be very finicky,
3260 needing to cope with both architecture and board specific constraints.
3262 @section Commands for Handling Resets
3264 @deffn {Command} adapter_nsrst_assert_width milliseconds
3265 Minimum amount of time (in milliseconds) OpenOCD should wait
3266 after asserting nSRST (active-low system reset) before
3267 allowing it to be deasserted.
3268 @end deffn
3270 @deffn {Command} adapter_nsrst_delay milliseconds
3271 How long (in milliseconds) OpenOCD should wait after deasserting
3272 nSRST (active-low system reset) before starting new JTAG operations.
3273 When a board has a reset button connected to SRST line it will
3274 probably have hardware debouncing, implying you should use this.
3275 @end deffn
3277 @deffn {Command} jtag_ntrst_assert_width milliseconds
3278 Minimum amount of time (in milliseconds) OpenOCD should wait
3279 after asserting nTRST (active-low JTAG TAP reset) before
3280 allowing it to be deasserted.
3281 @end deffn
3283 @deffn {Command} jtag_ntrst_delay milliseconds
3284 How long (in milliseconds) OpenOCD should wait after deasserting
3285 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3286 @end deffn
3288 @deffn {Command} reset_config mode_flag ...
3289 This command displays or modifies the reset configuration
3290 of your combination of JTAG board and target in target
3291 configuration scripts.
3293 Information earlier in this section describes the kind of problems
3294 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3295 As a rule this command belongs only in board config files,
3296 describing issues like @emph{board doesn't connect TRST};
3297 or in user config files, addressing limitations derived
3298 from a particular combination of interface and board.
3299 (An unlikely example would be using a TRST-only adapter
3300 with a board that only wires up SRST.)
3302 The @var{mode_flag} options can be specified in any order, but only one
3303 of each type -- @var{signals}, @var{combination}, @var{gates},
3304 @var{trst_type}, @var{srst_type} and @var{connect_type}
3305 -- may be specified at a time.
3306 If you don't provide a new value for a given type, its previous
3307 value (perhaps the default) is unchanged.
3308 For example, this means that you don't need to say anything at all about
3309 TRST just to declare that if the JTAG adapter should want to drive SRST,
3310 it must explicitly be driven high (@option{srst_push_pull}).
3312 @itemize
3313 @item
3314 @var{signals} can specify which of the reset signals are connected.
3315 For example, If the JTAG interface provides SRST, but the board doesn't
3316 connect that signal properly, then OpenOCD can't use it.
3317 Possible values are @option{none} (the default), @option{trst_only},
3318 @option{srst_only} and @option{trst_and_srst}.
3320 @quotation Tip
3321 If your board provides SRST and/or TRST through the JTAG connector,
3322 you must declare that so those signals can be used.
3323 @end quotation
3325 @item
3326 The @var{combination} is an optional value specifying broken reset
3327 signal implementations.
3328 The default behaviour if no option given is @option{separate},
3329 indicating everything behaves normally.
3330 @option{srst_pulls_trst} states that the
3331 test logic is reset together with the reset of the system (e.g. NXP
3332 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3333 the system is reset together with the test logic (only hypothetical, I
3334 haven't seen hardware with such a bug, and can be worked around).
3335 @option{combined} implies both @option{srst_pulls_trst} and
3336 @option{trst_pulls_srst}.
3338 @item
3339 The @var{gates} tokens control flags that describe some cases where
3340 JTAG may be unvailable during reset.
3341 @option{srst_gates_jtag} (default)
3342 indicates that asserting SRST gates the
3343 JTAG clock. This means that no communication can happen on JTAG
3344 while SRST is asserted.
3345 Its converse is @option{srst_nogate}, indicating that JTAG commands
3346 can safely be issued while SRST is active.
3348 @item
3349 The @var{connect_type} tokens control flags that describe some cases where
3350 SRST is asserted while connecting to the target. @option{srst_nogate}
3351 is required to use this option.
3352 @option{connect_deassert_srst} (default)
3353 indicates that SRST will not be asserted while connecting to the target.
3354 Its converse is @option{connect_assert_srst}, indicating that SRST will
3355 be asserted before any target connection.
3356 Only some targets support this feature, STM32 and STR9 are examples.
3357 This feature is useful if you are unable to connect to your target due
3358 to incorrect options byte config or illegal program execution.
3359 @end itemize
3361 The optional @var{trst_type} and @var{srst_type} parameters allow the
3362 driver mode of each reset line to be specified. These values only affect
3363 JTAG interfaces with support for different driver modes, like the Amontec
3364 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3365 relevant signal (TRST or SRST) is not connected.
3367 @itemize
3368 @item
3369 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3370 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3371 Most boards connect this signal to a pulldown, so the JTAG TAPs
3372 never leave reset unless they are hooked up to a JTAG adapter.
3374 @item
3375 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3376 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3377 Most boards connect this signal to a pullup, and allow the
3378 signal to be pulled low by various events including system
3379 powerup and pressing a reset button.
3380 @end itemize
3381 @end deffn
3383 @section Custom Reset Handling
3384 @cindex events
3386 OpenOCD has several ways to help support the various reset
3387 mechanisms provided by chip and board vendors.
3388 The commands shown in the previous section give standard parameters.
3389 There are also @emph{event handlers} associated with TAPs or Targets.
3390 Those handlers are Tcl procedures you can provide, which are invoked
3391 at particular points in the reset sequence.
3393 @emph{When SRST is not an option} you must set
3394 up a @code{reset-assert} event handler for your target.
3395 For example, some JTAG adapters don't include the SRST signal;
3396 and some boards have multiple targets, and you won't always
3397 want to reset everything at once.
3399 After configuring those mechanisms, you might still
3400 find your board doesn't start up or reset correctly.
3401 For example, maybe it needs a slightly different sequence
3402 of SRST and/or TRST manipulations, because of quirks that
3403 the @command{reset_config} mechanism doesn't address;
3404 or asserting both might trigger a stronger reset, which
3405 needs special attention.
3407 Experiment with lower level operations, such as @command{jtag_reset}
3408 and the @command{jtag arp_*} operations shown here,
3409 to find a sequence of operations that works.
3410 @xref{JTAG Commands}.
3411 When you find a working sequence, it can be used to override
3412 @command{jtag_init}, which fires during OpenOCD startup
3413 (@pxref{configurationstage,,Configuration Stage});
3414 or @command{init_reset}, which fires during reset processing.
3416 You might also want to provide some project-specific reset
3417 schemes. For example, on a multi-target board the standard
3418 @command{reset} command would reset all targets, but you
3419 may need the ability to reset only one target at time and
3420 thus want to avoid using the board-wide SRST signal.
3422 @deffn {Overridable Procedure} init_reset mode
3423 This is invoked near the beginning of the @command{reset} command,
3424 usually to provide as much of a cold (power-up) reset as practical.
3425 By default it is also invoked from @command{jtag_init} if
3426 the scan chain does not respond to pure JTAG operations.
3427 The @var{mode} parameter is the parameter given to the
3428 low level reset command (@option{halt},
3429 @option{init}, or @option{run}), @option{setup},
3430 or potentially some other value.
3432 The default implementation just invokes @command{jtag arp_init-reset}.
3433 Replacements will normally build on low level JTAG
3434 operations such as @command{jtag_reset}.
3435 Operations here must not address individual TAPs
3436 (or their associated targets)
3437 until the JTAG scan chain has first been verified to work.
3439 Implementations must have verified the JTAG scan chain before
3440 they return.
3441 This is done by calling @command{jtag arp_init}
3442 (or @command{jtag arp_init-reset}).
3443 @end deffn
3445 @deffn Command {jtag arp_init}
3446 This validates the scan chain using just the four
3447 standard JTAG signals (TMS, TCK, TDI, TDO).
3448 It starts by issuing a JTAG-only reset.
3449 Then it performs checks to verify that the scan chain configuration
3450 matches the TAPs it can observe.
3451 Those checks include checking IDCODE values for each active TAP,
3452 and verifying the length of their instruction registers using
3453 TAP @code{-ircapture} and @code{-irmask} values.
3454 If these tests all pass, TAP @code{setup} events are
3455 issued to all TAPs with handlers for that event.
3456 @end deffn
3458 @deffn Command {jtag arp_init-reset}
3459 This uses TRST and SRST to try resetting
3460 everything on the JTAG scan chain
3461 (and anything else connected to SRST).
3462 It then invokes the logic of @command{jtag arp_init}.
3463 @end deffn
3466 @node TAP Declaration
3467 @chapter TAP Declaration
3468 @cindex TAP declaration
3469 @cindex TAP configuration
3471 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3472 TAPs serve many roles, including:
3474 @itemize @bullet
3475 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3476 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3477 Others do it indirectly, making a CPU do it.
3478 @item @b{Program Download} Using the same CPU support GDB uses,
3479 you can initialize a DRAM controller, download code to DRAM, and then
3480 start running that code.
3481 @item @b{Boundary Scan} Most chips support boundary scan, which
3482 helps test for board assembly problems like solder bridges
3483 and missing connections.
3484 @end itemize
3486 OpenOCD must know about the active TAPs on your board(s).
3487 Setting up the TAPs is the core task of your configuration files.
3488 Once those TAPs are set up, you can pass their names to code
3489 which sets up CPUs and exports them as GDB targets,
3490 probes flash memory, performs low-level JTAG operations, and more.
3492 @section Scan Chains
3493 @cindex scan chain
3495 TAPs are part of a hardware @dfn{scan chain},
3496 which is a daisy chain of TAPs.
3497 They also need to be added to
3498 OpenOCD's software mirror of that hardware list,
3499 giving each member a name and associating other data with it.
3500 Simple scan chains, with a single TAP, are common in
3501 systems with a single microcontroller or microprocessor.
3502 More complex chips may have several TAPs internally.
3503 Very complex scan chains might have a dozen or more TAPs:
3504 several in one chip, more in the next, and connecting
3505 to other boards with their own chips and TAPs.
3507 You can display the list with the @command{scan_chain} command.
3508 (Don't confuse this with the list displayed by the @command{targets}
3509 command, presented in the next chapter.
3510 That only displays TAPs for CPUs which are configured as
3511 debugging targets.)
3512 Here's what the scan chain might look like for a chip more than one TAP:
3514 @verbatim
3515 TapName Enabled IdCode Expected IrLen IrCap IrMask
3516 -- ------------------ ------- ---------- ---------- ----- ----- ------
3517 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3518 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3519 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3520 @end verbatim
3522 OpenOCD can detect some of that information, but not all
3523 of it. @xref{autoprobing,,Autoprobing}.
3524 Unfortunately, those TAPs can't always be autoconfigured,
3525 because not all devices provide good support for that.
3526 JTAG doesn't require supporting IDCODE instructions, and
3527 chips with JTAG routers may not link TAPs into the chain
3528 until they are told to do so.
3530 The configuration mechanism currently supported by OpenOCD
3531 requires explicit configuration of all TAP devices using
3532 @command{jtag newtap} commands, as detailed later in this chapter.
3533 A command like this would declare one tap and name it @code{chip1.cpu}:
3535 @example
3536 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3537 @end example
3539 Each target configuration file lists the TAPs provided
3540 by a given chip.
3541 Board configuration files combine all the targets on a board,
3542 and so forth.
3543 Note that @emph{the order in which TAPs are declared is very important.}
3544 That declaration order must match the order in the JTAG scan chain,
3545 both inside a single chip and between them.
3546 @xref{faqtaporder,,FAQ TAP Order}.
3548 For example, the ST Microsystems STR912 chip has
3549 three separate TAPs@footnote{See the ST
3550 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3551 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3552 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3553 To configure those taps, @file{target/str912.cfg}
3554 includes commands something like this:
3556 @example
3557 jtag newtap str912 flash ... params ...
3558 jtag newtap str912 cpu ... params ...
3559 jtag newtap str912 bs ... params ...
3560 @end example
3562 Actual config files typically use a variable such as @code{$_CHIPNAME}
3563 instead of literals like @option{str912}, to support more than one chip
3564 of each type. @xref{Config File Guidelines}.
3566 @deffn Command {jtag names}
3567 Returns the names of all current TAPs in the scan chain.
3568 Use @command{jtag cget} or @command{jtag tapisenabled}
3569 to examine attributes and state of each TAP.
3570 @example
3571 foreach t [jtag names] @{
3572 puts [format "TAP: %s\n" $t]
3573 @}
3574 @end example
3575 @end deffn
3577 @deffn Command {scan_chain}
3578 Displays the TAPs in the scan chain configuration,
3579 and their status.
3580 The set of TAPs listed by this command is fixed by
3581 exiting the OpenOCD configuration stage,
3582 but systems with a JTAG router can
3583 enable or disable TAPs dynamically.
3584 @end deffn
3586 @c FIXME! "jtag cget" should be able to return all TAP
3587 @c attributes, like "$target_name cget" does for targets.
3589 @c Probably want "jtag eventlist", and a "tap-reset" event
3590 @c (on entry to RESET state).
3592 @section TAP Names
3593 @cindex dotted name
3595 When TAP objects are declared with @command{jtag newtap},
3596 a @dfn{dotted.name} is created for the TAP, combining the
3597 name of a module (usually a chip) and a label for the TAP.
3598 For example: @code{xilinx.tap}, @code{str912.flash},
3599 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3600 Many other commands use that dotted.name to manipulate or
3601 refer to the TAP. For example, CPU configuration uses the
3602 name, as does declaration of NAND or NOR flash banks.
3604 The components of a dotted name should follow ``C'' symbol
3605 name rules: start with an alphabetic character, then numbers
3606 and underscores are OK; while others (including dots!) are not.
3608 @section TAP Declaration Commands
3610 @c shouldn't this be(come) a {Config Command}?
3611 @deffn Command {jtag newtap} chipname tapname configparams...
3612 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3613 and configured according to the various @var{configparams}.
3615 The @var{chipname} is a symbolic name for the chip.
3616 Conventionally target config files use @code{$_CHIPNAME},
3617 defaulting to the model name given by the chip vendor but
3618 overridable.
3620 @cindex TAP naming convention
3621 The @var{tapname} reflects the role of that TAP,
3622 and should follow this convention:
3624 @itemize @bullet
3625 @item @code{bs} -- For boundary scan if this is a separate TAP;
3626 @item @code{cpu} -- The main CPU of the chip, alternatively
3627 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3628 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3629 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3630 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3631 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3632 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3633 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3634 with a single TAP;
3635 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3636 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3637 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3638 a JTAG TAP; that TAP should be named @code{sdma}.
3639 @end itemize
3641 Every TAP requires at least the following @var{configparams}:
3643 @itemize @bullet
3644 @item @code{-irlen} @var{NUMBER}
3645 @*The length in bits of the
3646 instruction register, such as 4 or 5 bits.
3647 @end itemize
3649 A TAP may also provide optional @var{configparams}:
3651 @itemize @bullet
3652 @item @code{-disable} (or @code{-enable})
3653 @*Use the @code{-disable} parameter to flag a TAP which is not
3654 linked into the scan chain after a reset using either TRST
3655 or the JTAG state machine's @sc{reset} state.
3656 You may use @code{-enable} to highlight the default state
3657 (the TAP is linked in).
3658 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3659 @item @code{-expected-id} @var{NUMBER}
3660 @*A non-zero @var{number} represents a 32-bit IDCODE
3661 which you expect to find when the scan chain is examined.
3662 These codes are not required by all JTAG devices.
3663 @emph{Repeat the option} as many times as required if more than one
3664 ID code could appear (for example, multiple versions).
3665 Specify @var{number} as zero to suppress warnings about IDCODE
3666 values that were found but not included in the list.
3668 Provide this value if at all possible, since it lets OpenOCD
3669 tell when the scan chain it sees isn't right. These values
3670 are provided in vendors' chip documentation, usually a technical
3671 reference manual. Sometimes you may need to probe the JTAG
3672 hardware to find these values.
3673 @xref{autoprobing,,Autoprobing}.
3674 @item @code{-ignore-version}
3675 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3676 option. When vendors put out multiple versions of a chip, or use the same
3677 JTAG-level ID for several largely-compatible chips, it may be more practical
3678 to ignore the version field than to update config files to handle all of
3679 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3680 @item @code{-ircapture} @var{NUMBER}
3681 @*The bit pattern loaded by the TAP into the JTAG shift register
3682 on entry to the @sc{ircapture} state, such as 0x01.
3683 JTAG requires the two LSBs of this value to be 01.
3684 By default, @code{-ircapture} and @code{-irmask} are set
3685 up to verify that two-bit value. You may provide
3686 additional bits if you know them, or indicate that
3687 a TAP doesn't conform to the JTAG specification.
3688 @item @code{-irmask} @var{NUMBER}
3689 @*A mask used with @code{-ircapture}
3690 to verify that instruction scans work correctly.
3691 Such scans are not used by OpenOCD except to verify that
3692 there seems to be no problems with JTAG scan chain operations.
3693 @end itemize
3694 @end deffn
3696 @section Other TAP commands
3698 @deffn Command {jtag cget} dotted.name @option{-event} event_name
3699 @deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
3700 At this writing this TAP attribute
3701 mechanism is used only for event handling.
3702 (It is not a direct analogue of the @code{cget}/@code{configure}
3703 mechanism for debugger targets.)
3704 See the next section for information about the available events.
3706 The @code{configure} subcommand assigns an event handler,
3707 a TCL string which is evaluated when the event is triggered.
3708 The @code{cget} subcommand returns that handler.
3709 @end deffn
3711 @section TAP Events
3712 @cindex events
3713 @cindex TAP events
3715 OpenOCD includes two event mechanisms.
3716 The one presented here applies to all JTAG TAPs.
3717 The other applies to debugger targets,
3718 which are associated with certain TAPs.
3720 The TAP events currently defined are:
3722 @itemize @bullet
3723 @item @b{post-reset}
3724 @* The TAP has just completed a JTAG reset.
3725 The tap may still be in the JTAG @sc{reset} state.
3726 Handlers for these events might perform initialization sequences
3727 such as issuing TCK cycles, TMS sequences to ensure
3728 exit from the ARM SWD mode, and more.
3730 Because the scan chain has not yet been verified, handlers for these events
3731 @emph{should not issue commands which scan the JTAG IR or DR registers}
3732 of any particular target.
3733 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3734 @item @b{setup}
3735 @* The scan chain has been reset and verified.
3736 This handler may enable TAPs as needed.
3737 @item @b{tap-disable}
3738 @* The TAP needs to be disabled. This handler should
3739 implement @command{jtag tapdisable}
3740 by issuing the relevant JTAG commands.
3741 @item @b{tap-enable}
3742 @* The TAP needs to be enabled. This handler should
3743 implement @command{jtag tapenable}
3744 by issuing the relevant JTAG commands.
3745 @end itemize
3747 If you need some action after each JTAG reset which isn't actually
3748 specific to any TAP (since you can't yet trust the scan chain's
3749 contents to be accurate), you might:
3751 @example
3752 jtag configure CHIP.jrc -event post-reset @{
3753 echo "JTAG Reset done"
3754 ... non-scan jtag operations to be done after reset
3755 @}
3756 @end example
3759 @anchor{enablinganddisablingtaps}
3760 @section Enabling and Disabling TAPs
3761 @cindex JTAG Route Controller
3762 @cindex jrc
3764 In some systems, a @dfn{JTAG Route Controller} (JRC)
3765 is used to enable and/or disable specific JTAG TAPs.
3766 Many ARM-based chips from Texas Instruments include
3767 an ``ICEPick'' module, which is a JRC.
3768 Such chips include DaVinci and OMAP3 processors.
3770 A given TAP may not be visible until the JRC has been
3771 told to link it into the scan chain; and if the JRC
3772 has been told to unlink that TAP, it will no longer
3773 be visible.
3774 Such routers address problems that JTAG ``bypass mode''
3775 ignores, such as:
3777 @itemize
3778 @item The scan chain can only go as fast as its slowest TAP.
3779 @item Having many TAPs slows instruction scans, since all
3780 TAPs receive new instructions.
3781 @item TAPs in the scan chain must be powered up, which wastes
3782 power and prevents debugging some power management mechanisms.
3783 @end itemize
3785 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3786 as implied by the existence of JTAG routers.
3787 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3788 does include a kind of JTAG router functionality.
3790 @c (a) currently the event handlers don't seem to be able to
3791 @c fail in a way that could lead to no-change-of-state.
3793 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3794 shown below, and is implemented using TAP event handlers.
3795 So for example, when defining a TAP for a CPU connected to
3796 a JTAG router, your @file{target.cfg} file
3797 should define TAP event handlers using
3798 code that looks something like this:
3800 @example
3801 jtag configure CHIP.cpu -event tap-enable @{
3802 ... jtag operations using CHIP.jrc
3803 @}
3804 jtag configure CHIP.cpu -event tap-disable @{
3805 ... jtag operations using CHIP.jrc
3806 @}
3807 @end example
3809 Then you might want that CPU's TAP enabled almost all the time:
3811 @example
3812 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3813 @end example
3815 Note how that particular setup event handler declaration
3816 uses quotes to evaluate @code{$CHIP} when the event is configured.
3817 Using brackets @{ @} would cause it to be evaluated later,
3818 at runtime, when it might have a different value.
3820 @deffn Command {jtag tapdisable} dotted.name
3821 If necessary, disables the tap
3822 by sending it a @option{tap-disable} event.
3823 Returns the string "1" if the tap
3824 specified by @var{dotted.name} is enabled,
3825 and "0" if it is disabled.
3826 @end deffn
3828 @deffn Command {jtag tapenable} dotted.name
3829 If necessary, enables the tap
3830 by sending it a @option{tap-enable} event.
3831 Returns the string "1" if the tap
3832 specified by @var{dotted.name} is enabled,
3833 and "0" if it is disabled.
3834 @end deffn
3836 @deffn Command {jtag tapisenabled} dotted.name
3837 Returns the string "1" if the tap
3838 specified by @var{dotted.name} is enabled,
3839 and "0" if it is disabled.
3841 @quotation Note
3842 Humans will find the @command{scan_chain} command more helpful
3843 for querying the state of the JTAG taps.
3844 @end quotation
3845 @end deffn
3847 @anchor{autoprobing}
3848 @section Autoprobing
3849 @cindex autoprobe
3850 @cindex JTAG autoprobe
3852 TAP configuration is the first thing that needs to be done
3853 after interface and reset configuration. Sometimes it's
3854 hard finding out what TAPs exist, or how they are identified.
3855 Vendor documentation is not always easy to find and use.
3857 To help you get past such problems, OpenOCD has a limited
3858 @emph{autoprobing} ability to look at the scan chain, doing
3859 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3860 To use this mechanism, start the OpenOCD server with only data
3861 that configures your JTAG interface, and arranges to come up
3862 with a slow clock (many devices don't support fast JTAG clocks
3863 right when they come out of reset).
3865 For example, your @file{openocd.cfg} file might have:
3867 @example
3868 source [find interface/olimex-arm-usb-tiny-h.cfg]
3869 reset_config trst_and_srst
3870 jtag_rclk 8
3871 @end example
3873 When you start the server without any TAPs configured, it will
3874 attempt to autoconfigure the TAPs. There are two parts to this:
3876 @enumerate
3877 @item @emph{TAP discovery} ...
3878 After a JTAG reset (sometimes a system reset may be needed too),
3879 each TAP's data registers will hold the contents of either the
3880 IDCODE or BYPASS register.
3881 If JTAG communication is working, OpenOCD will see each TAP,
3882 and report what @option{-expected-id} to use with it.
3883 @item @emph{IR Length discovery} ...
3884 Unfortunately JTAG does not provide a reliable way to find out
3885 the value of the @option{-irlen} parameter to use with a TAP
3886 that is discovered.
3887 If OpenOCD can discover the length of a TAP's instruction
3888 register, it will report it.
3889 Otherwise you may need to consult vendor documentation, such
3890 as chip data sheets or BSDL files.
3891 @end enumerate
3893 In many cases your board will have a simple scan chain with just
3894 a single device. Here's what OpenOCD reported with one board
3895 that's a bit more complex:
3897 @example
3898 clock speed 8 kHz
3899 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3900 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3901 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3902 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3903 AUTO auto0.tap - use "... -irlen 4"
3904 AUTO auto1.tap - use "... -irlen 4"
3905 AUTO auto2.tap - use "... -irlen 6"
3906 no gdb ports allocated as no target has been specified
3907 @end example
3909 Given that information, you should be able to either find some existing
3910 config files to use, or create your own. If you create your own, you
3911 would configure from the bottom up: first a @file{target.cfg} file
3912 with these TAPs, any targets associated with them, and any on-chip
3913 resources; then a @file{board.cfg} with off-chip resources, clocking,
3914 and so forth.
3916 @node CPU Configuration
3917 @chapter CPU Configuration
3918 @cindex GDB target
3920 This chapter discusses how to set up GDB debug targets for CPUs.
3921 You can also access these targets without GDB
3922 (@pxref{Architecture and Core Commands},
3923 and @ref{targetstatehandling,,Target State handling}) and
3924 through various kinds of NAND and NOR flash commands.
3925 If you have multiple CPUs you can have multiple such targets.
3927 We'll start by looking at how to examine the targets you have,
3928 then look at how to add one more target and how to configure it.
3930 @section Target List
3931 @cindex target, current
3932 @cindex target, list
3934 All targets that have been set up are part of a list,
3935 where each member has a name.
3936 That name should normally be the same as the TAP name.
3937 You can display the list with the @command{targets}
3938 (plural!) command.
3939 This display often has only one CPU; here's what it might
3940 look like with more than one:
3941 @verbatim
3942 TargetName Type Endian TapName State
3943 -- ------------------ ---------- ------ ------------------ ------------
3944 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
3945 1 MyTarget cortex_m little mychip.foo tap-disabled
3946 @end verbatim
3948 One member of that list is the @dfn{current target}, which
3949 is implicitly referenced by many commands.
3950 It's the one marked with a @code{*} near the target name.
3951 In particular, memory addresses often refer to the address
3952 space seen by that current target.
3953 Commands like @command{mdw} (memory display words)
3954 and @command{flash erase_address} (erase NOR flash blocks)
3955 are examples; and there are many more.
3957 Several commands let you examine the list of targets:
3959 @deffn Command {target current}
3960 Returns the name of the current target.
3961 @end deffn
3963 @deffn Command {target names}
3964 Lists the names of all current targets in the list.
3965 @example
3966 foreach t [target names] @{
3967 puts [format "Target: %s\n" $t]
3968 @}
3969 @end example
3970 @end deffn
3972 @c yep, "target list" would have been better.
3973 @c plus maybe "target setdefault".
3975 @deffn Command targets [name]
3976 @emph{Note: the name of this command is plural. Other target
3977 command names are singular.}
3979 With no parameter, this command displays a table of all known
3980 targets in a user friendly form.
3982 With a parameter, this command sets the current target to
3983 the given target with the given @var{name}; this is
3984 only relevant on boards which have more than one target.
3985 @end deffn
3987 @section Target CPU Types
3988 @cindex target type
3989 @cindex CPU type
3991 Each target has a @dfn{CPU type}, as shown in the output of
3992 the @command{targets} command. You need to specify that type
3993 when calling @command{target create}.
3994 The CPU type indicates more than just the instruction set.
3995 It also indicates how that instruction set is implemented,
3996 what kind of debug support it integrates,
3997 whether it has an MMU (and if so, what kind),
3998 what core-specific commands may be available
3999 (@pxref{Architecture and Core Commands}),
4000 and more.
4002 It's easy to see what target types are supported,
4003 since there's a command to list them.
4005 @anchor{targettypes}
4006 @deffn Command {target types}
4007 Lists all supported target types.
4008 At this writing, the supported CPU types are:
4010 @itemize @bullet
4011 @item @code{arm11} -- this is a generation of ARMv6 cores
4012 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4013 @item @code{arm7tdmi} -- this is an ARMv4 core
4014 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4015 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4016 @item @code{arm966e} -- this is an ARMv5 core
4017 @item @code{arm9tdmi} -- this is an ARMv4 core
4018 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4019 (Support for this is preliminary and incomplete.)
4020 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4021 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4022 compact Thumb2 instruction set.
4023 @item @code{dragonite} -- resembles arm966e
4024 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4025 (Support for this is still incomplete.)
4026 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4027 @item @code{feroceon} -- resembles arm926
4028 @item @code{mips_m4k} -- a MIPS core
4029 @item @code{xscale} -- this is actually an architecture,
4030 not a CPU type. It is based on the ARMv5 architecture.
4031 @item @code{openrisc} -- this is an OpenRISC 1000 core.
4032 The current implementation supports three JTAG TAP cores:
4033 @itemize @minus
4034 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag})
4035 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4036 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4037 @end itemize
4038 And two debug interfaces cores:
4039 @itemize @minus
4040 @item @code{Advanced debug interface} (See: @url{http://opencores.org/project,adv_debug_sys})
4041 @item @code{SoC Debug Interface} (See: @url{http://opencores.org/project,dbg_interface})
4042 @end itemize
4043 @end itemize
4044 @end deffn
4046 To avoid being confused by the variety of ARM based cores, remember
4047 this key point: @emph{ARM is a technology licencing company}.
4048 (See: @url{http://www.arm.com}.)
4049 The CPU name used by OpenOCD will reflect the CPU design that was
4050 licenced, not a vendor brand which incorporates that design.
4051 Name prefixes like arm7, arm9, arm11, and cortex
4052 reflect design generations;
4053 while names like ARMv4, ARMv5, ARMv6, and ARMv7
4054 reflect an architecture version implemented by a CPU design.
4056 @anchor{targetconfiguration}
4057 @section Target Configuration
4059 Before creating a ``target'', you must have added its TAP to the scan chain.
4060 When you've added that TAP, you will have a @code{dotted.name}
4061 which is used to set up the CPU support.
4062 The chip-specific configuration file will normally configure its CPU(s)
4063 right after it adds all of the chip's TAPs to the scan chain.
4065 Although you can set up a target in one step, it's often clearer if you
4066 use shorter commands and do it in two steps: create it, then configure
4067 optional parts.
4068 All operations on the target after it's created will use a new
4069 command, created as part of target creation.
4071 The two main things to configure after target creation are
4072 a work area, which usually has target-specific defaults even
4073 if the board setup code overrides them later;
4074 and event handlers (@pxref{targetevents,,Target Events}), which tend
4075 to be much more board-specific.
4076 The key steps you use might look something like this
4078 @example
4079 target create MyTarget cortex_m -chain-position mychip.cpu
4080 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4081 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4082 $MyTarget configure -event reset-init @{ myboard_reinit @}
4083 @end example
4085 You should specify a working area if you can; typically it uses some
4086 on-chip SRAM.
4087 Such a working area can speed up many things, including bulk
4088 writes to target memory;
4089 flash operations like checking to see if memory needs to be erased;
4090 GDB memory checksumming;
4091 and more.
4093 @quotation Warning
4094 On more complex chips, the work area can become
4095 inaccessible when application code
4096 (such as an operating system)
4097 enables or disables the MMU.
4098 For example, the particular MMU context used to acess the virtual
4099 address will probably matter ... and that context might not have
4100 easy access to other addresses needed.
4101 At this writing, OpenOCD doesn't have much MMU intelligence.
4102 @end quotation
4104 It's often very useful to define a @code{reset-init} event handler.
4105 For systems that are normally used with a boot loader,
4106 common tasks include updating clocks and initializing memory
4107 controllers.
4108 That may be needed to let you write the boot loader into flash,
4109 in order to ``de-brick'' your board; or to load programs into
4110 external DDR memory without having run the boot loader.
4112 @deffn Command {target create} target_name type configparams...
4113 This command creates a GDB debug target that refers to a specific JTAG tap.
4114 It enters that target into a list, and creates a new
4115 command (@command{@var{target_name}}) which is used for various
4116 purposes including additional configuration.
4118 @itemize @bullet
4119 @item @var{target_name} ... is the name of the debug target.
4120 By convention this should be the same as the @emph{dotted.name}
4121 of the TAP associated with this target, which must be specified here
4122 using the @code{-chain-position @var{dotted.name}} configparam.
4124 This name is also used to create the target object command,
4125 referred to here as @command{$target_name},
4126 and in other places the target needs to be identified.
4127 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4128 @item @var{configparams} ... all parameters accepted by
4129 @command{$target_name configure} are permitted.
4130 If the target is big-endian, set it here with @code{-endian big}.
4132 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
4133 @end itemize
4134 @end deffn
4136 @deffn Command {$target_name configure} configparams...
4137 The options accepted by this command may also be
4138 specified as parameters to @command{target create}.
4139 Their values can later be queried one at a time by
4140 using the @command{$target_name cget} command.
4142 @emph{Warning:} changing some of these after setup is dangerous.
4143 For example, moving a target from one TAP to another;
4144 and changing its endianness.
4146 @itemize @bullet
4148 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4149 used to access this target.
4151 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4152 whether the CPU uses big or little endian conventions
4154 @item @code{-event} @var{event_name} @var{event_body} --
4155 @xref{targetevents,,Target Events}.
4156 Note that this updates a list of named event handlers.
4157 Calling this twice with two different event names assigns
4158 two different handlers, but calling it twice with the
4159 same event name assigns only one handler.
4161 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4162 whether the work area gets backed up; by default,
4163 @emph{it is not backed up.}
4164 When possible, use a working_area that doesn't need to be backed up,
4165 since performing a backup slows down operations.
4166 For example, the beginning of an SRAM block is likely to
4167 be used by most build systems, but the end is often unused.
4169 @item @code{-work-area-size} @var{size} -- specify work are size,
4170 in bytes. The same size applies regardless of whether its physical
4171 or virtual address is being used.
4173 @item @code{-work-area-phys} @var{address} -- set the work area
4174 base @var{address} to be used when no MMU is active.
4176 @item @code{-work-area-virt} @var{address} -- set the work area
4177 base @var{address} to be used when an MMU is active.
4178 @emph{Do not specify a value for this except on targets with an MMU.}
4179 The value should normally correspond to a static mapping for the
4180 @code{-work-area-phys} address, set up by the current operating system.
4182 @anchor{rtostype}
4183 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4184 @var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}|
4185 @option{FreeRTOS}|@option{linux}|@option{ChibiOS}|@option{embKernel}|@option{mqx}
4186 @xref{gdbrtossupport,,RTOS Support}.
4188 @end itemize
4189 @end deffn
4191 @section Other $target_name Commands
4192 @cindex object command
4194 The Tcl/Tk language has the concept of object commands,
4195 and OpenOCD adopts that same model for targets.
4197 A good Tk example is a on screen button.
4198 Once a button is created a button
4199 has a name (a path in Tk terms) and that name is useable as a first
4200 class command. For example in Tk, one can create a button and later
4201 configure it like this:
4203 @example
4204 # Create
4205 button .foobar -background red -command @{ foo @}
4206 # Modify
4207 .foobar configure -foreground blue
4208 # Query
4209 set x [.foobar cget -background]
4210 # Report
4211 puts [format "The button is %s" $x]
4212 @end example
4214 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4215 button, and its object commands are invoked the same way.
4217 @example
4218 str912.cpu mww 0x1234 0x42
4219 omap3530.cpu mww 0x5555 123
4220 @end example
4222 The commands supported by OpenOCD target objects are:
4224 @deffn Command {$target_name arp_examine}
4225 @deffnx Command {$target_name arp_halt}
4226 @deffnx Command {$target_name arp_poll}
4227 @deffnx Command {$target_name arp_reset}
4228 @deffnx Command {$target_name arp_waitstate}
4229 Internal OpenOCD scripts (most notably @file{startup.tcl})
4230 use these to deal with specific reset cases.
4231 They are not otherwise documented here.
4232 @end deffn
4234 @deffn Command {$target_name array2mem} arrayname width address count
4235 @deffnx Command {$target_name mem2array} arrayname width address count
4236 These provide an efficient script-oriented interface to memory.
4237 The @code{array2mem} primitive writes bytes, halfwords, or words;
4238 while @code{mem2array} reads them.
4239 In both cases, the TCL side uses an array, and
4240 the target side uses raw memory.
4242 The efficiency comes from enabling the use of
4243 bulk JTAG data transfer operations.
4244 The script orientation comes from working with data
4245 values that are packaged for use by TCL scripts;
4246 @command{mdw} type primitives only print data they retrieve,
4247 and neither store nor return those values.
4249 @itemize
4250 @item @var{arrayname} ... is the name of an array variable
4251 @item @var{width} ... is 8/16/32 - indicating the memory access size
4252 @item @var{address} ... is the target memory address
4253 @item @var{count} ... is the number of elements to process
4254 @end itemize
4255 @end deffn
4257 @deffn Command {$target_name cget} queryparm
4258 Each configuration parameter accepted by
4259 @command{$target_name configure}
4260 can be individually queried, to return its current value.
4261 The @var{queryparm} is a parameter name
4262 accepted by that command, such as @code{-work-area-phys}.
4263 There are a few special cases:
4265 @itemize @bullet
4266 @item @code{-event} @var{event_name} -- returns the handler for the
4267 event named @var{event_name}.
4268 This is a special case because setting a handler requires
4269 two parameters.
4270 @item @code{-type} -- returns the target type.
4271 This is a special case because this is set using
4272 @command{target create} and can't be changed
4273 using @command{$target_name configure}.
4274 @end itemize
4276 For example, if you wanted to summarize information about
4277 all the targets you might use something like this:
4279 @example
4280 foreach name [target names] @{
4281 set y [$name cget -endian]
4282 set z [$name cget -type]
4283 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4284 $x $name $y $z]
4285 @}
4286 @end example
4287 @end deffn
4289 @anchor{targetcurstate}
4290 @deffn Command {$target_name curstate}
4291 Displays the current target state:
4292 @code{debug-running},
4293 @code{halted},
4294 @code{reset},
4295 @code{running}, or @code{unknown}.
4296 (Also, @pxref{eventpolling,,Event Polling}.)
4297 @end deffn
4299 @deffn Command {$target_name eventlist}
4300 Displays a table listing all event handlers
4301 currently associated with this target.
4302 @xref{targetevents,,Target Events}.
4303 @end deffn
4305 @deffn Command {$target_name invoke-event} event_name
4306 Invokes the handler for the event named @var{event_name}.
4307 (This is primarily intended for use by OpenOCD framework
4308 code, for example by the reset code in @file{startup.tcl}.)
4309 @end deffn
4311 @deffn Command {$target_name mdw} addr [count]
4312 @deffnx Command {$target_name mdh} addr [count]
4313 @deffnx Command {$target_name mdb} addr [count]
4314 Display contents of address @var{addr}, as
4315 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4316 or 8-bit bytes (@command{mdb}).
4317 If @var{count} is specified, displays that many units.
4318 (If you want to manipulate the data instead of displaying it,
4319 see the @code{mem2array} primitives.)
4320 @end deffn
4322 @deffn Command {$target_name mww} addr word
4323 @deffnx Command {$target_name mwh} addr halfword
4324 @deffnx Command {$target_name mwb} addr byte
4325 Writes the specified @var{word} (32 bits),
4326 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4327 at the specified address @var{addr}.
4328 @end deffn
4330 @anchor{targetevents}
4331 @section Target Events
4332 @cindex target events
4333 @cindex events
4334 At various times, certain things can happen, or you want them to happen.
4335 For example:
4336 @itemize @bullet
4337 @item What should happen when GDB connects? Should your target reset?
4338 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4339 @item Is using SRST appropriate (and possible) on your system?
4340 Or instead of that, do you need to issue JTAG commands to trigger reset?
4341 SRST usually resets everything on the scan chain, which can be inappropriate.
4342 @item During reset, do you need to write to certain memory locations
4343 to set up system clocks or
4344 to reconfigure the SDRAM?
4345 How about configuring the watchdog timer, or other peripherals,
4346 to stop running while you hold the core stopped for debugging?
4347 @end itemize
4349 All of the above items can be addressed by target event handlers.
4350 These are set up by @command{$target_name configure -event} or
4351 @command{target create ... -event}.
4353 The programmer's model matches the @code{-command} option used in Tcl/Tk
4354 buttons and events. The two examples below act the same, but one creates
4355 and invokes a small procedure while the other inlines it.
4357 @example
4358 proc my_attach_proc @{ @} @{
4359 echo "Reset..."
4360 reset halt
4361 @}
4362 mychip.cpu configure -event gdb-attach my_attach_proc
4363 mychip.cpu configure -event gdb-attach @{
4364 echo "Reset..."
4365 # To make flash probe and gdb load to flash work
4366 # we need a reset init.
4367 reset init
4368 @}
4369 @end example
4371 The following target events are defined:
4373 @itemize @bullet
4374 @item @b{debug-halted}
4375 @* The target has halted for debug reasons (i.e.: breakpoint)
4376 @item @b{debug-resumed}
4377 @* The target has resumed (i.e.: gdb said run)
4378 @item @b{early-halted}
4379 @* Occurs early in the halt process
4380 @item @b{examine-start}
4381 @* Before target examine is called.
4382 @item @b{examine-end}
4383 @* After target examine is called with no errors.
4384 @item @b{gdb-attach}
4385 @* When GDB connects. This is before any communication with the target, so this
4386 can be used to set up the target so it is possible to probe flash. Probing flash
4387 is necessary during gdb connect if gdb load is to write the image to flash. Another
4388 use of the flash memory map is for GDB to automatically hardware/software breakpoints
4389 depending on whether the breakpoint is in RAM or read only memory.
4390 @item @b{gdb-detach}
4391 @* When GDB disconnects
4392 @item @b{gdb-end}
4393 @* When the target has halted and GDB is not doing anything (see early halt)
4394 @item @b{gdb-flash-erase-start}
4395 @* Before the GDB flash process tries to erase the flash (default is
4396 @code{reset init})
4397 @item @b{gdb-flash-erase-end}
4398 @* After the GDB flash process has finished erasing the flash
4399 @item @b{gdb-flash-write-start}
4400 @* Before GDB writes to the flash
4401 @item @b{gdb-flash-write-end}
4402 @* After GDB writes to the flash (default is @code{reset halt})
4403 @item @b{gdb-start}
4404 @* Before the target steps, gdb is trying to start/resume the target
4405 @item @b{halted}
4406 @* The target has halted
4407 @item @b{reset-assert-pre}
4408 @* Issued as part of @command{reset} processing
4409 after @command{reset_init} was triggered
4410 but before either SRST alone is re-asserted on the scan chain,
4411 or @code{reset-assert} is triggered.
4412 @item @b{reset-assert}
4413 @* Issued as part of @command{reset} processing
4414 after @command{reset-assert-pre} was triggered.
4415 When such a handler is present, cores which support this event will use
4416 it instead of asserting SRST.
4417 This support is essential for debugging with JTAG interfaces which
4418 don't include an SRST line (JTAG doesn't require SRST), and for
4419 selective reset on scan chains that have multiple targets.
4420 @item @b{reset-assert-post}
4421 @* Issued as part of @command{reset} processing
4422 after @code{reset-assert} has been triggered.
4423 or the target asserted SRST on the entire scan chain.
4424 @item @b{reset-deassert-pre}
4425 @* Issued as part of @command{reset} processing
4426 after @code{reset-assert-post} has been triggered.
4427 @item @b{reset-deassert-post}
4428 @* Issued as part of @command{reset} processing
4429 after @code{reset-deassert-pre} has been triggered
4430 and (if the target is using it) after SRST has been
4431 released on the scan chain.
4432 @item @b{reset-end}
4433 @* Issued as the final step in @command{reset} processing.
4434 @ignore
4435 @item @b{reset-halt-post}
4436 @* Currently not used
4437 @item @b{reset-halt-pre}
4438 @* Currently not used
4439 @end ignore
4440 @item @b{reset-init}
4441 @* Used by @b{reset init} command for board-specific initialization.
4442 This event fires after @emph{reset-deassert-post}.
4444 This is where you would configure PLLs and clocking, set up DRAM so
4445 you can download programs that don't fit in on-chip SRAM, set up pin
4446 multiplexing, and so on.
4447 (You may be able to switch to a fast JTAG clock rate here, after
4448 the target clocks are fully set up.)
4449 @item @b{reset-start}
4450 @* Issued as part of @command{reset} processing
4451 before @command{reset_init} is called.
4453 This is the most robust place to use @command{jtag_rclk}
4454 or @command{adapter_khz} to switch to a low JTAG clock rate,
4455 when reset disables PLLs needed to use a fast clock.
4456 @ignore
4457 @item @b{reset-wait-pos}
4458 @* Currently not used
4459 @item @b{reset-wait-pre}
4460 @* Currently not used
4461 @end ignore
4462 @item @b{resume-start}
4463 @* Before any target is resumed
4464 @item @b{resume-end}
4465 @* After all targets have resumed
4466 @item @b{resumed}
4467 @* Target has resumed
4468 @item @b{trace-config}
4469 @* After target hardware trace configuration was changed
4470 @end itemize
4472 @node Flash Commands
4473 @chapter Flash Commands
4475 OpenOCD has different commands for NOR and NAND flash;
4476 the ``flash'' command works with NOR flash, while
4477 the ``nand'' command works with NAND flash.
4478 This partially reflects different hardware technologies:
4479 NOR flash usually supports direct CPU instruction and data bus access,
4480 while data from a NAND flash must be copied to memory before it can be
4481 used. (SPI flash must also be copied to memory before use.)
4482 However, the documentation also uses ``flash'' as a generic term;
4483 for example, ``Put flash configuration in board-specific files''.
4485 Flash Steps:
4486 @enumerate
4487 @item Configure via the command @command{flash bank}
4488 @* Do this in a board-specific configuration file,
4489 passing parameters as needed by the driver.
4490 @item Operate on the flash via @command{flash subcommand}
4491 @* Often commands to manipulate the flash are typed by a human, or run
4492 via a script in some automated way. Common tasks include writing a
4493 boot loader, operating system, or other data.
4494 @item GDB Flashing
4495 @* Flashing via GDB requires the flash be configured via ``flash
4496 bank'', and the GDB flash features be enabled.
4497 @xref{gdbconfiguration,,GDB Configuration}.
4498 @end enumerate
4500 Many CPUs have the ablity to ``boot'' from the first flash bank.
4501 This means that misprogramming that bank can ``brick'' a system,
4502 so that it can't boot.
4503 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4504 board by (re)installing working boot firmware.
4506 @anchor{norconfiguration}
4507 @section Flash Configuration Commands
4508 @cindex flash configuration
4510 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4511 Configures a flash bank which provides persistent storage
4512 for addresses from @math{base} to @math{base + size - 1}.
4513 These banks will often be visible to GDB through the target's memory map.
4514 In some cases, configuring a flash bank will activate extra commands;
4515 see the driver-specific documentation.
4517 @itemize @bullet
4518 @item @var{name} ... may be used to reference the flash bank
4519 in other flash commands. A number is also available.
4520 @item @var{driver} ... identifies the controller driver
4521 associated with the flash bank being declared.
4522 This is usually @code{cfi} for external flash, or else
4523 the name of a microcontroller with embedded flash memory.
4524 @xref{flashdriverlist,,Flash Driver List}.
4525 @item @var{base} ... Base address of the flash chip.
4526 @item @var{size} ... Size of the chip, in bytes.
4527 For some drivers, this value is detected from the hardware.
4528 @item @var{chip_width} ... Width of the flash chip, in bytes;
4529 ignored for most microcontroller drivers.
4530 @item @var{bus_width} ... Width of the data bus used to access the
4531 chip, in bytes; ignored for most microcontroller drivers.
4532 @item @var{target} ... Names the target used to issue
4533 commands to the flash controller.
4534 @comment Actually, it's currently a controller-specific parameter...
4535 @item @var{driver_options} ... drivers may support, or require,
4536 additional parameters. See the driver-specific documentation
4537 for more information.
4538 @end itemize
4539 @quotation Note
4540 This command is not available after OpenOCD initialization has completed.
4541 Use it in board specific configuration files, not interactively.
4542 @end quotation
4543 @end deffn
4545 @comment the REAL name for this command is "ocd_flash_banks"
4546 @comment less confusing would be: "flash list" (like "nand list")
4547 @deffn Command {flash banks}
4548 Prints a one-line summary of each device that was
4549 declared using @command{flash bank}, numbered from zero.
4550 Note that this is the @emph{plural} form;
4551 the @emph{singular} form is a very different command.
4552 @end deffn
4554 @deffn Command {flash list}
4555 Retrieves a list of associative arrays for each device that was
4556 declared using @command{flash bank}, numbered from zero.
4557 This returned list can be manipulated easily from within scripts.
4558 @end deffn
4560 @deffn Command {flash probe} num
4561 Identify the flash, or validate the parameters of the configured flash. Operation
4562 depends on the flash type.
4563 The @var{num} parameter is a value shown by @command{flash banks}.
4564 Most flash commands will implicitly @emph{autoprobe} the bank;
4565 flash drivers can distinguish between probing and autoprobing,
4566 but most don't bother.
4567 @end deffn
4569 @section Erasing, Reading, Writing to Flash
4570 @cindex flash erasing
4571 @cindex flash reading
4572 @cindex flash writing
4573 @cindex flash programming
4574 @anchor{flashprogrammingcommands}
4576 One feature distinguishing NOR flash from NAND or serial flash technologies
4577 is that for read access, it acts exactly like any other addressible memory.
4578 This means you can use normal memory read commands like @command{mdw} or
4579 @command{dump_image} with it, with no special @command{flash} subcommands.
4580 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
4582 Write access works differently. Flash memory normally needs to be erased
4583 before it's written. Erasing a sector turns all of its bits to ones, and
4584 writing can turn ones into zeroes. This is why there are special commands
4585 for interactive erasing and writing, and why GDB needs to know which parts
4586 of the address space hold NOR flash memory.
4588 @quotation Note
4589 Most of these erase and write commands leverage the fact that NOR flash
4590 chips consume target address space. They implicitly refer to the current
4591 JTAG target, and map from an address in that target's address space
4592 back to a flash bank.
4593 @comment In May 2009, those mappings may fail if any bank associated
4594 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
4595 A few commands use abstract addressing based on bank and sector numbers,
4596 and don't depend on searching the current target and its address space.
4597 Avoid confusing the two command models.
4598 @end quotation
4600 Some flash chips implement software protection against accidental writes,
4601 since such buggy writes could in some cases ``brick'' a system.
4602 For such systems, erasing and writing may require sector protection to be
4603 disabled first.
4604 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4605 and AT91SAM7 on-chip flash.
4606 @xref{flashprotect,,flash protect}.
4608 @deffn Command {flash erase_sector} num first last
4609 Erase sectors in bank @var{num}, starting at sector @var{first}
4610 up to and including @var{last}.
4611 Sector numbering starts at 0.
4612 Providing a @var{last} sector of @option{last}
4613 specifies "to the end of the flash bank".
4614 The @var{num} parameter is a value shown by @command{flash banks}.
4615 @end deffn
4617 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4618 Erase sectors starting at @var{address} for @var{length} bytes.
4619 Unless @option{pad} is specified, @math{address} must begin a
4620 flash sector, and @math{address + length - 1} must end a sector.
4621 Specifying @option{pad} erases extra data at the beginning and/or
4622 end of the specified region, as needed to erase only full sectors.
4623 The flash bank to use is inferred from the @var{address}, and
4624 the specified length must stay within that bank.
4625 As a special case, when @var{length} is zero and @var{address} is
4626 the start of the bank, the whole flash is erased.
4627 If @option{unlock} is specified, then the flash is unprotected
4628 before erase starts.
4629 @end deffn
4631 @deffn Command {flash fillw} address word length
4632 @deffnx Command {flash fillh} address halfword length
4633 @deffnx Command {flash fillb} address byte length
4634 Fills flash memory with the specified @var{word} (32 bits),
4635 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4636 starting at @var{address} and continuing
4637 for @var{length} units (word/halfword/byte).
4638 No erasure is done before writing; when needed, that must be done
4639 before issuing this command.
4640 Writes are done in blocks of up to 1024 bytes, and each write is
4641 verified by reading back the data and comparing it to what was written.
4642 The flash bank to use is inferred from the @var{address} of
4643 each block, and the specified length must stay within that bank.
4644 @end deffn
4645 @comment no current checks for errors if fill blocks touch multiple banks!
4647 @deffn Command {flash write_bank} num filename offset
4648 Write the binary @file{filename} to flash bank @var{num},
4649 starting at @var{offset} bytes from the beginning of the bank.
4650 The @var{num} parameter is a value shown by @command{flash banks}.
4651 @end deffn
4653 @deffn Command {flash read_bank} num filename offset length
4654 Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
4655 and write the contents to the binary @file{filename}.
4656 The @var{num} parameter is a value shown by @command{flash banks}.
4657 @end deffn
4659 @deffn Command {flash verify_bank} num filename offset
4660 Compare the contents of the binary file @var{filename} with the contents of the
4661 flash @var{num} starting at @var{offset}. Fails if the contents do not match.
4662 The @var{num} parameter is a value shown by @command{flash banks}.
4663 @end deffn
4665 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4666 Write the image @file{filename} to the current target's flash bank(s).
4667 Only loadable sections from the image are written.
4668 A relocation @var{offset} may be specified, in which case it is added
4669 to the base address for each section in the image.
4670 The file [@var{type}] can be specified
4671 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4672 @option{elf} (ELF file), @option{s19} (Motorola s19).
4673 @option{mem}, or @option{builder}.
4674 The relevant flash sectors will be erased prior to programming
4675 if the @option{erase} parameter is given. If @option{unlock} is
4676 provided, then the flash banks are unlocked before erase and
4677 program. The flash bank to use is inferred from the address of
4678 each image section.
4680 @quotation Warning
4681 Be careful using the @option{erase} flag when the flash is holding
4682 data you want to preserve.
4683 Portions of the flash outside those described in the image's
4684 sections might be erased with no notice.
4685 @itemize
4686 @item
4687 When a section of the image being written does not fill out all the
4688 sectors it uses, the unwritten parts of those sectors are necessarily
4689 also erased, because sectors can't be partially erased.
4690 @item
4691 Data stored in sector "holes" between image sections are also affected.
4692 For example, "@command{flash write_image erase ...}" of an image with
4693 one byte at the beginning of a flash bank and one byte at the end
4694 erases the entire bank -- not just the two sectors being written.
4695 @end itemize
4696 Also, when flash protection is important, you must re-apply it after
4697 it has been removed by the @option{unlock} flag.
4698 @end quotation
4700 @end deffn
4702 @section Other Flash commands
4703 @cindex flash protection
4705 @deffn Command {flash erase_check} num
4706 Check erase state of sectors in flash bank @var{num},
4707 and display that status.
4708 The @var{num} parameter is a value shown by @command{flash banks}.
4709 @end deffn
4711 @deffn Command {flash info} num
4712 Print info about flash bank @var{num}
4713 The @var{num} parameter is a value shown by @command{flash banks}.
4714 This command will first query the hardware, it does not print cached
4715 and possibly stale information.
4716 @end deffn
4718 @anchor{flashprotect}
4719 @deffn Command {flash protect} num first last (@option{on}|@option{off})
4720 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
4721 in flash bank @var{num}, starting at sector @var{first}
4722 and continuing up to and including @var{last}.
4723 Providing a @var{last} sector of @option{last}
4724 specifies "to the end of the flash bank".
4725 The @var{num} parameter is a value shown by @command{flash banks}.
4726 @end deffn
4728 @deffn Command {flash padded_value} num value
4729 Sets the default value used for padding any image sections, This should
4730 normally match the flash bank erased value. If not specified by this
4731 comamnd or the flash driver then it defaults to 0xff.
4732 @end deffn
4734 @anchor{program}
4735 @deffn Command {program} filename [verify] [reset] [exit] [offset]
4736 This is a helper script that simplifies using OpenOCD as a standalone
4737 programmer. The only required parameter is @option{filename}, the others are optional.
4738 @xref{Flash Programming}.
4739 @end deffn
4741 @anchor{flashdriverlist}
4742 @section Flash Driver List
4743 As noted above, the @command{flash bank} command requires a driver name,
4744 and allows driver-specific options and behaviors.
4745 Some drivers also activate driver-specific commands.
4747 @deffn {Flash Driver} virtual
4748 This is a special driver that maps a previously defined bank to another
4749 address. All bank settings will be copied from the master physical bank.
4751 The @var{virtual} driver defines one mandatory parameters,
4753 @itemize
4754 @item @var{master_bank} The bank that this virtual address refers to.
4755 @end itemize
4757 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
4758 the flash bank defined at address 0x1fc00000. Any cmds executed on
4759 the virtual banks are actually performed on the physical banks.
4760 @example
4761 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
4762 flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
4763 flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
4764 @end example
4765 @end deffn
4767 @subsection External Flash
4769 @deffn {Flash Driver} cfi
4770 @cindex Common Flash Interface
4771 @cindex CFI
4772 The ``Common Flash Interface'' (CFI) is the main standard for
4773 external NOR flash chips, each of which connects to a
4774 specific external chip select on the CPU.
4775 Frequently the first such chip is used to boot the system.
4776 Your board's @code{reset-init} handler might need to
4777 configure additional chip selects using other commands (like: @command{mww} to
4778 configure a bus and its timings), or
4779 perhaps configure a GPIO pin that controls the ``write protect'' pin
4780 on the flash chip.
4781 The CFI driver can use a target-specific working area to significantly
4782 speed up operation.
4784 The CFI driver can accept the following optional parameters, in any order:
4786 @itemize
4787 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
4788 like AM29LV010 and similar types.
4789 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
4790 @end itemize
4792 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
4793 wide on a sixteen bit bus:
4795 @example
4796 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
4797 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
4798 @end example
4800 To configure one bank of 32 MBytes
4801 built from two sixteen bit (two byte) wide parts wired in parallel
4802 to create a thirty-two bit (four byte) bus with doubled throughput:
4804 @example
4805 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
4806 @end example
4808 @c "cfi part_id" disabled
4809 @end deffn
4811 @deffn {Flash Driver} jtagspi
4812 @cindex Generic JTAG2SPI driver
4813 @cindex SPI
4814 @cindex jtagspi
4815 @cindex bscan_spi
4816 Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
4817 SPI flash connected to them. To access this flash from the host, the device
4818 is first programmed with a special proxy bitstream that
4819 exposes the SPI flash on the device's JTAG interface. The flash can then be
4820 accessed through JTAG.
4822 Since signaling between JTAG and SPI is compatible, all that is required for
4823 a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
4824 the flash chip select when the JTAG state machine is in SHIFT-DR. Such
4825 a bitstream for several Xilinx FPGAs can be found in
4826 @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires migen
4827 (@url{http://github.com/m-labs/migen}) and a Xilinx toolchain to build.
4829 This flash bank driver requires a target on a JTAG tap and will access that
4830 tap directly. Since no support from the target is needed, the target can be a
4831 "testee" dummy. Since the target does not expose the flash memory
4832 mapping, target commands that would otherwise be expected to access the flash
4833 will not work. These include all @command{*_image} and
4834 @command{$target_name m*} commands as well as @command{program}. Equivalent
4835 functionality is available through the @command{flash write_bank},
4836 @command{flash read_bank}, and @command{flash verify_bank} commands.
4838 @itemize
4839 @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
4840 For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
4841 @var{USER1} instruction.
4842 @item @var{dr_length} ... is the length of the DR register. This will be 1 for
4843 @file{xilinx_bscan_spi.py} bitstreams and most other cases.
4844 @end itemize
4846 @example
4847 target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
4848 set _XILINX_USER1 0x02
4849 set _DR_LENGTH 1
4850 flash bank $_FLASHNAME spi 0x0 0 0 0 $_TARGETNAME $_XILINX_USER1 $_DR_LENGTH
4851 @end example
4852 @end deffn
4854 @deffn {Flash Driver} lpcspifi
4855 @cindex NXP SPI Flash Interface
4856 @cindex SPIFI
4857 @cindex lpcspifi
4858 NXP's LPC43xx and LPC18xx families include a proprietary SPI
4859 Flash Interface (SPIFI) peripheral that can drive and provide
4860 memory mapped access to external SPI flash devices.
4862 The lpcspifi driver initializes this interface and provides
4863 program and erase functionality for these serial flash devices.
4864 Use of this driver @b{requires} a working area of at least 1kB
4865 to be configured on the target device; more than this will
4866 significantly reduce flash programming times.
4868 The setup command only requires the @var{base} parameter. All
4869 other parameters are ignored, and the flash size and layout
4870 are configured by the driver.
4872 @example
4873 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
4874 @end example
4876 @end deffn
4878 @deffn {Flash Driver} stmsmi
4879 @cindex STMicroelectronics Serial Memory Interface
4880 @cindex SMI
4881 @cindex stmsmi
4882 Some devices form STMicroelectronics (e.g. STR75x MCU family,
4883 SPEAr MPU family) include a proprietary
4884 ``Serial Memory Interface'' (SMI) controller able to drive external
4885 SPI flash devices.
4886 Depending on specific device and board configuration, up to 4 external
4887 flash devices can be connected.
4889 SMI makes the flash content directly accessible in the CPU address
4890 space; each external device is mapped in a memory bank.
4891 CPU can directly read data, execute code and boot from SMI banks.
4892 Normal OpenOCD commands like @command{mdw} can be used to display
4893 the flash content.
4895 The setup command only requires the @var{base} parameter in order
4896 to identify the memory bank.
4897 All other parameters are ignored. Additional information, like
4898 flash size, are detected automatically.
4900 @example
4901 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
4902 @end example
4904 @end deffn
4906 @deffn {Flash Driver} mrvlqspi
4907 This driver supports QSPI flash controller of Marvell's Wireless
4908 Microcontroller platform.
4910 The flash size is autodetected based on the table of known JEDEC IDs
4911 hardcoded in the OpenOCD sources.
4913 @example
4914 flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
4915 @end example
4917 @end deffn
4919 @subsection Internal Flash (Microcontrollers)
4921 @deffn {Flash Driver} aduc702x
4922 The ADUC702x analog microcontrollers from Analog Devices
4923 include internal flash and use ARM7TDMI cores.
4924 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
4925 The setup command only requires the @var{target} argument
4926 since all devices in this family have the same memory layout.
4928 @example
4929 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
4930 @end example
4931 @end deffn
4933 @anchor{at91samd}
4934 @deffn {Flash Driver} at91samd
4935 @cindex at91samd
4936 All members of the ATSAMD, ATSAMR, ATSAML and ATSAMC microcontroller
4937 families from Atmel include internal flash and use ARM's Cortex-M0+ core.
4938 This driver uses the same cmd names/syntax as @xref{at91sam3}.
4940 @deffn Command {at91samd chip-erase}
4941 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
4942 used to erase a chip back to its factory state and does not require the
4943 processor to be halted.
4944 @end deffn
4946 @deffn Command {at91samd set-security}
4947 Secures the Flash via the Set Security Bit (SSB) command. This prevents access
4948 to the Flash and can only be undone by using the chip-erase command which
4949 erases the Flash contents and turns off the security bit. Warning: at this
4950 time, openocd will not be able to communicate with a secured chip and it is
4951 therefore not possible to chip-erase it without using another tool.
4953 @example
4954 at91samd set-security enable
4955 @end example
4956 @end deffn
4958 @deffn Command {at91samd eeprom}
4959 Shows or sets the EEPROM emulation size configuration, stored in the User Row
4960 of the Flash. When setting, the EEPROM size must be specified in bytes and it
4961 must be one of the permitted sizes according to the datasheet. Settings are
4962 written immediately but only take effect on MCU reset. EEPROM emulation
4963 requires additional firmware support and the minumum EEPROM size may not be
4964 the same as the minimum that the hardware supports. Set the EEPROM size to 0
4965 in order to disable this feature.
4967 @example
4968 at91samd eeprom
4969 at91samd eeprom 1024
4970 @end example
4971 @end deffn
4973 @deffn Command {at91samd bootloader}
4974 Shows or sets the bootloader size configuration, stored in the User Row of the
4975 Flash. This is called the BOOTPROT region. When setting, the bootloader size
4976 must be specified in bytes and it must be one of the permitted sizes according
4977 to the datasheet. Settings are written immediately but only take effect on
4978 MCU reset. Setting the bootloader size to 0 disables bootloader protection.
4980 @example
4981 at91samd bootloader
4982 at91samd bootloader 16384
4983 @end example
4984 @end deffn
4986 @deffn Command {at91samd dsu_reset_deassert}
4987 This command releases internal reset held by DSU
4988 and prepares reset vector catch in case of reset halt.
4989 Command is used internally in event event reset-deassert-post.
4990 @end deffn
4992 @end deffn
4994 @anchor{at91sam3}
4995 @deffn {Flash Driver} at91sam3
4996 @cindex at91sam3
4997 All members of the AT91SAM3 microcontroller family from
4998 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
4999 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
5000 that the driver was orginaly developed and tested using the
5001 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
5002 the family was cribbed from the data sheet. @emph{Note to future
5003 readers/updaters: Please remove this worrysome comment after other
5004 chips are confirmed.}
5006 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
5007 have one flash bank. In all cases the flash banks are at
5008 the following fixed locations:
5010 @example
5011 # Flash bank 0 - all chips
5012 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
5013 # Flash bank 1 - only 256K chips
5014 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
5015 @end example
5017 Internally, the AT91SAM3 flash memory is organized as follows.
5018 Unlike the AT91SAM7 chips, these are not used as parameters
5019 to the @command{flash bank} command:
5021 @itemize
5022 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
5023 @item @emph{Bank Size:} 128K/64K Per flash bank
5024 @item @emph{Sectors:} 16 or 8 per bank
5025 @item @emph{SectorSize:} 8K Per Sector
5026 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
5027 @end itemize
5029 The AT91SAM3 driver adds some additional commands:
5031 @deffn Command {at91sam3 gpnvm}
5032 @deffnx Command {at91sam3 gpnvm clear} number
5033 @deffnx Command {at91sam3 gpnvm set} number
5034 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
5035 With no parameters, @command{show} or @command{show all},
5036 shows the status of all GPNVM bits.
5037 With @command{show} @var{number}, displays that bit.
5039 With @command{set} @var{number} or @command{clear} @var{number},
5040 modifies that GPNVM bit.
5041 @end deffn
5043 @deffn Command {at91sam3 info}
5044 This command attempts to display information about the AT91SAM3
5045 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
5046 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
5047 document id: doc6430A] and decodes the values. @emph{Second} it reads the
5048 various clock configuration registers and attempts to display how it
5049 believes the chip is configured. By default, the SLOWCLK is assumed to
5050 be 32768 Hz, see the command @command{at91sam3 slowclk}.
5051 @end deffn
5053 @deffn Command {at91sam3 slowclk} [value]
5054 This command shows/sets the slow clock frequency used in the
5055 @command{at91sam3 info} command calculations above.
5056 @end deffn
5057 @end deffn
5059 @deffn {Flash Driver} at91sam4
5060 @cindex at91sam4
5061 All members of the AT91SAM4 microcontroller family from
5062 Atmel include internal flash and use ARM's Cortex-M4 core.
5063 This driver uses the same cmd names/syntax as @xref{at91sam3}.
5064 @end deffn
5066 @deffn {Flash Driver} at91sam4l
5067 @cindex at91sam4l
5068 All members of the AT91SAM4L microcontroller family from
5069 Atmel include internal flash and use ARM's Cortex-M4 core.
5070 This driver uses the same cmd names/syntax as @xref{at91sam3}.