Add LPC8Nxx and NHS3xx support.
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
82 * TFTP:: TFTP
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on:
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
95 @end menu
97 @node About
98 @unnumbered About
99 @cindex about
101 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
102 at the University of Applied Sciences Augsburg (@uref{}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
105 around the world.
107 @section What is OpenOCD?
108 @cindex TAP
109 @cindex JTAG
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
113 devices.
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board connect directly to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
140 scan operations.
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD supports only
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
154 USB-based, parallel port-based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
159 (Stellaris LM3, STMicroelectronics STM32 and Energy Micro EFM32) and
160 Intel Quark (x10xx) based cores to be debugged via the GDB protocol.
162 @b{Flash Programming:} Flash writing is supported for external
163 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{}
182 PDF form is likewise published at:
184 @uref{}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{}
203 @section OpenOCD IRC
205 Support can also be found on irc:
206 @uref{irc://}
208 @node Developers
209 @chapter OpenOCD Developer Resources
210 @cindex developers
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD Git Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a Git repository hosted at SourceForge. The repository URL is:
225 @uref{git://}
227 or via http
229 @uref{}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{}
235 With standard Git tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a Git client:
241 @uref{}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration at the top of the source tree.
264 @section Gerrit Review System
266 All changes in the OpenOCD Git repository go through the web-based Gerrit
267 Code Review System:
269 @uref{}
271 After a one-time registration and repository setup, anyone can push commits
272 from their local Git repository directly into Gerrit.
273 All users and developers are encouraged to review, test, discuss and vote
274 for changes in Gerrit. The feedback provides the basis for a maintainer to
275 eventually submit the change to the main Git repository.
277 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
278 Developer Manual, contains basic information about how to connect a
279 repository to Gerrit, prepare and push patches. Patch authors are expected to
280 maintain their changes while they're in Gerrit, respond to feedback and if
281 necessary rework and push improved versions of the change.
283 @section OpenOCD Developer Mailing List
285 The OpenOCD Developer Mailing List provides the primary means of
286 communication between developers:
288 @uref{}
290 @section OpenOCD Bug Tracker
292 The OpenOCD Bug Tracker is hosted on SourceForge:
294 @uref{}
297 @node Debug Adapter Hardware
298 @chapter Debug Adapter Hardware
299 @cindex dongles
300 @cindex FTDI
301 @cindex wiggler
302 @cindex zy1000
303 @cindex printer port
304 @cindex USB Adapter
305 @cindex RTCK
307 Defined: @b{dongle}: A small device that plugs into a computer and serves as
308 an adapter .... [snip]
310 In the OpenOCD case, this generally refers to @b{a small adapter} that
311 attaches to your computer via USB or the parallel port. One
312 exception is the Ultimate Solutions ZY1000, packaged as a small box you
313 attach via an ethernet cable. The ZY1000 has the advantage that it does not
314 require any drivers to be installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built-in relay to power cycle targets remotely.
319 @section Choosing a Dongle
321 There are several things you should keep in mind when choosing a dongle.
323 @enumerate
324 @item @b{Transport} Does it support the kind of communication that you need?
325 OpenOCD focusses mostly on JTAG. Your version may also support
326 other ways to communicate with target devices.
327 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
328 Does your dongle support it? You might need a level converter.
329 @item @b{Pinout} What pinout does your target board use?
330 Does your dongle support it? You may be able to use jumper
331 wires, or an "octopus" connector, to convert pinouts.
332 @item @b{Connection} Does your computer have the USB, parallel, or
333 Ethernet port needed?
334 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
335 RTCK support (also known as ``adaptive clocking'')?
336 @end enumerate
338 @section Stand-alone JTAG Probe
340 The ZY1000 from Ultimate Solutions is technically not a dongle but a
341 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
342 running on the developer's host computer.
343 Once installed on a network using DHCP or a static IP assignment, users can
344 access the ZY1000 probe locally or remotely from any host with access to the
345 IP address assigned to the probe.
346 The ZY1000 provides an intuitive web interface with direct access to the
347 OpenOCD debugger.
348 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
349 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
350 the target.
351 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
352 to power cycle the target remotely.
354 For more information, visit:
356 @b{ZY1000} See: @url{}
358 @section USB FT2232 Based
360 There are many USB JTAG dongles on the market, many of them based
361 on a chip from ``Future Technology Devices International'' (FTDI)
362 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
363 See: @url{} for more information.
364 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
365 chips started to become available in JTAG adapters. Around 2012, a new
366 variant appeared - FT232H - this is a single-channel version of FT2232H.
367 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
368 clocking.)
370 The FT2232 chips are flexible enough to support some other
371 transport options, such as SWD or the SPI variants used to
372 program some chips. They have two communications channels,
373 and one can be used for a UART adapter at the same time the
374 other one is used to provide a debug adapter.
376 Also, some development boards integrate an FT2232 chip to serve as
377 a built-in low-cost debug adapter and USB-to-serial solution.
379 @itemize @bullet
380 @item @b{usbjtag}
381 @* Link @url{}
382 @item @b{jtagkey}
383 @* See: @url{}
384 @item @b{jtagkey2}
385 @* See: @url{}
386 @item @b{oocdlink}
387 @* See: @url{} By Joern Kaipf
388 @item @b{signalyzer}
389 @* See: @url{}
390 @item @b{Stellaris Eval Boards}
391 @* See: @url{} - The Stellaris eval boards
392 bundle FT2232-based JTAG and SWD support, which can be used to debug
393 the Stellaris chips. Using separate JTAG adapters is optional.
394 These boards can also be used in a "pass through" mode as JTAG adapters
395 to other target boards, disabling the Stellaris chip.
396 @item @b{TI/Luminary ICDI}
397 @* See: @url{} - TI/Luminary In-Circuit Debug
398 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
399 Evaluation Kits. Like the non-detachable FT2232 support on the other
400 Stellaris eval boards, they can be used to debug other target boards.
401 @item @b{olimex-jtag}
402 @* See: @url{}
403 @item @b{Flyswatter/Flyswatter2}
404 @* See: @url{}
405 @item @b{turtelizer2}
406 @* See:
407 @uref{, Turtelizer 2}, or
408 @url{}
409 @item @b{comstick}
410 @* Link: @url{}
411 @item @b{stm32stick}
412 @* Link @url{}
413 @item @b{axm0432_jtag}
414 @* Axiom AXM-0432 Link @url{} - NOTE: This JTAG does not appear
415 to be available anymore as of April 2012.
416 @item @b{cortino}
417 @* Link @url{}
418 @item @b{dlp-usb1232h}
419 @* Link @url{}
420 @item @b{digilent-hs1}
421 @* Link @url{}
422 @item @b{opendous}
423 @* Link @url{} FT2232H-based
424 (OpenHardware).
425 @item @b{JTAG-lock-pick Tiny 2}
426 @* Link @url{} FT232H-based
428 @item @b{GW16042}
429 @* Link: @url{}
430 FT2232H-based
432 @end itemize
433 @section USB-JTAG / Altera USB-Blaster compatibles
435 These devices also show up as FTDI devices, but are not
436 protocol-compatible with the FT2232 devices. They are, however,
437 protocol-compatible among themselves. USB-JTAG devices typically consist
438 of a FT245 followed by a CPLD that understands a particular protocol,
439 or emulates this protocol using some other hardware.
441 They may appear under different USB VID/PID depending on the particular
442 product. The driver can be configured to search for any VID/PID pair
443 (see the section on driver commands).
445 @itemize
446 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
447 @* Link: @url{}
448 @item @b{Altera USB-Blaster}
449 @* Link: @url{}
450 @end itemize
452 @section USB J-Link based
453 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
454 an example of a microcontroller based JTAG adapter, it uses an
455 AT91SAM764 internally.
457 @itemize @bullet
458 @item @b{SEGGER J-Link}
459 @* Link: @url{}
460 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
461 @* Link: @url{}
462 @item @b{IAR J-Link}
463 @end itemize
465 @section USB RLINK based
466 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
467 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
468 SWD and not JTAG, thus not supported.
470 @itemize @bullet
471 @item @b{Raisonance RLink}
472 @* Link: @url{}
473 @item @b{STM32 Primer}
474 @* Link: @url{}
475 @item @b{STM32 Primer2}
476 @* Link: @url{}
477 @end itemize
479 @section USB ST-LINK based
480 STMicroelectronics has an adapter called @b{ST-LINK}.
481 They only work with STMicroelectronics chips, notably STM32 and STM8.
483 @itemize @bullet
484 @item @b{ST-LINK}
485 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
486 @* Link: @url{}
487 @item @b{ST-LINK/V2}
488 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
489 @* Link: @url{}
490 @item @b{STLINK-V3}
491 @* This is available standalone and as part of some kits.
492 @* Link: @url{}
493 @end itemize
495 For info the original ST-LINK enumerates using the mass storage usb class; however,
496 its implementation is completely broken. The result is this causes issues under Linux.
497 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
498 @itemize @bullet
499 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
500 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
501 @end itemize
503 @section USB TI/Stellaris ICDI based
504 Texas Instruments has an adapter called @b{ICDI}.
505 It is not to be confused with the FTDI based adapters that were originally fitted to their
506 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
508 @section USB CMSIS-DAP based
509 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
510 debuggers to ARM Cortex based targets @url{}.
512 @section USB Other
513 @itemize @bullet
514 @item @b{USBprog}
515 @* Link: @url{} - which uses an Atmel MEGA32 and a UBN9604
517 @item @b{USB - Presto}
518 @* Link: @url{}
520 @item @b{Versaloon-Link}
521 @* Link: @url{}
523 @item @b{ARM-JTAG-EW}
524 @* Link: @url{}
526 @item @b{Buspirate}
527 @* Link: @url{}
529 @item @b{opendous}
530 @* Link: @url{} - which uses an AT90USB162
532 @item @b{estick}
533 @* Link: @url{}
535 @item @b{Keil ULINK v1}
536 @* Link: @url{}
538 @item @b{TI XDS110 Debug Probe}
539 @* The XDS110 is included as the embedded debug probe on many Texas Instruments
540 LaunchPad evaluation boards.
541 @* Link: @url{}
542 @* Link: @url{}
543 @end itemize
545 @section IBM PC Parallel Printer Port Based
547 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
548 and the Macraigor Wiggler. There are many clones and variations of
549 these on the market.
551 Note that parallel ports are becoming much less common, so if you
552 have the choice you should probably avoid these adapters in favor
553 of USB-based ones.
555 @itemize @bullet
557 @item @b{Wiggler} - There are many clones of this.
558 @* Link: @url{}
560 @item @b{DLC5} - From XILINX - There are many clones of this
561 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
562 produced, PDF schematics are easily found and it is easy to make.
564 @item @b{Amontec - JTAG Accelerator}
565 @* Link: @url{}
567 @item @b{Wiggler2}
568 @* Link: @url{}
570 @item @b{Wiggler_ntrst_inverted}
571 @* Yet another variation - See the source code, src/jtag/parport.c
573 @item @b{old_amt_wiggler}
574 @* Unknown - probably not on the market today
576 @item @b{arm-jtag}
577 @* Link: Most likely @url{} [another wiggler clone]
579 @item @b{chameleon}
580 @* Link: @url{}
582 @item @b{Triton}
583 @* Unknown.
585 @item @b{Lattice}
586 @* ispDownload from Lattice Semiconductor
587 @url{}
589 @item @b{flashlink}
590 @* From STMicroelectronics;
591 @* Link: @url{}
593 @end itemize
595 @section Other...
596 @itemize @bullet
598 @item @b{ep93xx}
599 @* An EP93xx based Linux machine using the GPIO pins directly.
601 @item @b{at91rm9200}
602 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
604 @item @b{bcm2835gpio}
605 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
607 @item @b{imx_gpio}
608 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
610 @item @b{jtag_vpi}
611 @* A JTAG driver acting as a client for the JTAG VPI server interface.
612 @* Link: @url{}
614 @end itemize
616 @node About Jim-Tcl
617 @chapter About Jim-Tcl
618 @cindex Jim-Tcl
619 @cindex tcl
621 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
622 This programming language provides a simple and extensible
623 command interpreter.
625 All commands presented in this Guide are extensions to Jim-Tcl.
626 You can use them as simple commands, without needing to learn
627 much of anything about Tcl.
628 Alternatively, you can write Tcl programs with them.
630 You can learn more about Jim at its website, @url{}.
631 There is an active and responsive community, get on the mailing list
632 if you have any questions. Jim-Tcl maintainers also lurk on the
633 OpenOCD mailing list.
635 @itemize @bullet
636 @item @b{Jim vs. Tcl}
637 @* Jim-Tcl is a stripped down version of the well known Tcl language,
638 which can be found here: @url{}. Jim-Tcl has far
639 fewer features. Jim-Tcl is several dozens of .C files and .H files and
640 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
641 4.2 MB .zip file containing 1540 files.
643 @item @b{Missing Features}
644 @* Our practice has been: Add/clone the real Tcl feature if/when
645 needed. We welcome Jim-Tcl improvements, not bloat. Also there
646 are a large number of optional Jim-Tcl features that are not
647 enabled in OpenOCD.
649 @item @b{Scripts}
650 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
651 command interpreter today is a mixture of (newer)
652 Jim-Tcl commands, and the (older) original command interpreter.
654 @item @b{Commands}
655 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
656 can type a Tcl for() loop, set variables, etc.
657 Some of the commands documented in this guide are implemented
658 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
660 @item @b{Historical Note}
661 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
662 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
663 as a Git submodule, which greatly simplified upgrading Jim-Tcl
664 to benefit from new features and bugfixes in Jim-Tcl.
666 @item @b{Need a crash course in Tcl?}
667 @*@xref{Tcl Crash Course}.
668 @end itemize
670 @node Running
671 @chapter Running
672 @cindex command line options
673 @cindex logfile
674 @cindex directory search
676 Properly installing OpenOCD sets up your operating system to grant it access
677 to the debug adapters. On Linux, this usually involves installing a file
678 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
679 that works for many common adapters is shipped with OpenOCD in the
680 @file{contrib} directory. MS-Windows needs
681 complex and confusing driver configuration for every peripheral. Such issues
682 are unique to each operating system, and are not detailed in this User's Guide.
684 Then later you will invoke the OpenOCD server, with various options to
685 tell it how each debug session should work.
686 The @option{--help} option shows:
687 @verbatim
688 bash$ openocd --help
690 --help | -h display this help
691 --version | -v display OpenOCD version
692 --file | -f use configuration file <name>
693 --search | -s dir to search for config files and scripts
694 --debug | -d set debug level to 3
695 | -d<n> set debug level to <level>
696 --log_output | -l redirect log output to file <name>
697 --command | -c run <command>
698 @end verbatim
700 If you don't give any @option{-f} or @option{-c} options,
701 OpenOCD tries to read the configuration file @file{openocd.cfg}.
702 To specify one or more different
703 configuration files, use @option{-f} options. For example:
705 @example
706 openocd -f config1.cfg -f config2.cfg -f config3.cfg
707 @end example
709 Configuration files and scripts are searched for in
710 @enumerate
711 @item the current directory,
712 @item any search dir specified on the command line using the @option{-s} option,
713 @item any search dir specified using the @command{add_script_search_dir} command,
714 @item @file{$HOME/.openocd} (not on Windows),
715 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
716 @item the site wide script library @file{$pkgdatadir/site} and
717 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
718 @end enumerate
719 The first found file with a matching file name will be used.
721 @quotation Note
722 Don't try to use configuration script names or paths which
723 include the "#" character. That character begins Tcl comments.
724 @end quotation
726 @section Simple setup, no customization
728 In the best case, you can use two scripts from one of the script
729 libraries, hook up your JTAG adapter, and start the server ... and
730 your JTAG setup will just work "out of the box". Always try to
731 start by reusing those scripts, but assume you'll need more
732 customization even if this works. @xref{OpenOCD Project Setup}.
734 If you find a script for your JTAG adapter, and for your board or
735 target, you may be able to hook up your JTAG adapter then start
736 the server with some variation of one of the following:
738 @example
739 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
740 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
741 @end example
743 You might also need to configure which reset signals are present,
744 using @option{-c 'reset_config trst_and_srst'} or something similar.
745 If all goes well you'll see output something like
747 @example
748 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
749 For bug reports, read
751 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
752 (mfg: 0x23b, part: 0xba00, ver: 0x3)
753 @end example
755 Seeing that "tap/device found" message, and no warnings, means
756 the JTAG communication is working. That's a key milestone, but
757 you'll probably need more project-specific setup.
759 @section What OpenOCD does as it starts
761 OpenOCD starts by processing the configuration commands provided
762 on the command line or, if there were no @option{-c command} or
763 @option{-f file.cfg} options given, in @file{openocd.cfg}.
764 @xref{configurationstage,,Configuration Stage}.
765 At the end of the configuration stage it verifies the JTAG scan
766 chain defined using those commands; your configuration should
767 ensure that this always succeeds.
768 Normally, OpenOCD then starts running as a server.
769 Alternatively, commands may be used to terminate the configuration
770 stage early, perform work (such as updating some flash memory),
771 and then shut down without acting as a server.
773 Once OpenOCD starts running as a server, it waits for connections from
774 clients (Telnet, GDB, RPC) and processes the commands issued through
775 those channels.
777 If you are having problems, you can enable internal debug messages via
778 the @option{-d} option.
780 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
781 @option{-c} command line switch.
783 To enable debug output (when reporting problems or working on OpenOCD
784 itself), use the @option{-d} command line switch. This sets the
785 @option{debug_level} to "3", outputting the most information,
786 including debug messages. The default setting is "2", outputting only
787 informational messages, warnings and errors. You can also change this
788 setting from within a telnet or gdb session using @command{debug_level<n>}
789 (@pxref{debuglevel,,debug_level}).
791 You can redirect all output from the server to a file using the
792 @option{-l <logfile>} switch.
794 Note! OpenOCD will launch the GDB & telnet server even if it can not
795 establish a connection with the target. In general, it is possible for
796 the JTAG controller to be unresponsive until the target is set up
797 correctly via e.g. GDB monitor commands in a GDB init script.
799 @node OpenOCD Project Setup
800 @chapter OpenOCD Project Setup
802 To use OpenOCD with your development projects, you need to do more than
803 just connect the JTAG adapter hardware (dongle) to your development board
804 and start the OpenOCD server.
805 You also need to configure your OpenOCD server so that it knows
806 about your adapter and board, and helps your work.
807 You may also want to connect OpenOCD to GDB, possibly
808 using Eclipse or some other GUI.
810 @section Hooking up the JTAG Adapter
812 Today's most common case is a dongle with a JTAG cable on one side
813 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
814 and a USB cable on the other.
815 Instead of USB, some cables use Ethernet;
816 older ones may use a PC parallel port, or even a serial port.
818 @enumerate
819 @item @emph{Start with power to your target board turned off},
820 and nothing connected to your JTAG adapter.
821 If you're particularly paranoid, unplug power to the board.
822 It's important to have the ground signal properly set up,
823 unless you are using a JTAG adapter which provides
824 galvanic isolation between the target board and the
825 debugging host.
827 @item @emph{Be sure it's the right kind of JTAG connector.}
828 If your dongle has a 20-pin ARM connector, you need some kind
829 of adapter (or octopus, see below) to hook it up to
830 boards using 14-pin or 10-pin connectors ... or to 20-pin
831 connectors which don't use ARM's pinout.
833 In the same vein, make sure the voltage levels are compatible.
834 Not all JTAG adapters have the level shifters needed to work
835 with 1.2 Volt boards.
837 @item @emph{Be certain the cable is properly oriented} or you might
838 damage your board. In most cases there are only two possible
839 ways to connect the cable.
840 Connect the JTAG cable from your adapter to the board.
841 Be sure it's firmly connected.
843 In the best case, the connector is keyed to physically
844 prevent you from inserting it wrong.
845 This is most often done using a slot on the board's male connector
846 housing, which must match a key on the JTAG cable's female connector.
847 If there's no housing, then you must look carefully and
848 make sure pin 1 on the cable hooks up to pin 1 on the board.
849 Ribbon cables are frequently all grey except for a wire on one
850 edge, which is red. The red wire is pin 1.
852 Sometimes dongles provide cables where one end is an ``octopus'' of
853 color coded single-wire connectors, instead of a connector block.
854 These are great when converting from one JTAG pinout to another,
855 but are tedious to set up.
856 Use these with connector pinout diagrams to help you match up the
857 adapter signals to the right board pins.
859 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
860 A USB, parallel, or serial port connector will go to the host which
861 you are using to run OpenOCD.
862 For Ethernet, consult the documentation and your network administrator.
864 For USB-based JTAG adapters you have an easy sanity check at this point:
865 does the host operating system see the JTAG adapter? If you're running
866 Linux, try the @command{lsusb} command. If that host is an
867 MS-Windows host, you'll need to install a driver before OpenOCD works.
869 @item @emph{Connect the adapter's power supply, if needed.}
870 This step is primarily for non-USB adapters,
871 but sometimes USB adapters need extra power.
873 @item @emph{Power up the target board.}
874 Unless you just let the magic smoke escape,
875 you're now ready to set up the OpenOCD server
876 so you can use JTAG to work with that board.
878 @end enumerate
880 Talk with the OpenOCD server using
881 telnet (@code{telnet localhost 4444} on many systems) or GDB.
882 @xref{GDB and OpenOCD}.
884 @section Project Directory
886 There are many ways you can configure OpenOCD and start it up.
888 A simple way to organize them all involves keeping a
889 single directory for your work with a given board.
890 When you start OpenOCD from that directory,
891 it searches there first for configuration files, scripts,
892 files accessed through semihosting,
893 and for code you upload to the target board.
894 It is also the natural place to write files,
895 such as log files and data you download from the board.
897 @section Configuration Basics
899 There are two basic ways of configuring OpenOCD, and
900 a variety of ways you can mix them.
901 Think of the difference as just being how you start the server:
903 @itemize
904 @item Many @option{-f file} or @option{-c command} options on the command line
905 @item No options, but a @dfn{user config file}
906 in the current directory named @file{openocd.cfg}
907 @end itemize
909 Here is an example @file{openocd.cfg} file for a setup
910 using a Signalyzer FT2232-based JTAG adapter to talk to
911 a board with an Atmel AT91SAM7X256 microcontroller:
913 @example
914 source [find interface/ftdi/signalyzer.cfg]
916 # GDB can also flash my flash!
917 gdb_memory_map enable
918 gdb_flash_program enable
920 source [find target/sam7x256.cfg]
921 @end example
923 Here is the command line equivalent of that configuration:
925 @example
926 openocd -f interface/ftdi/signalyzer.cfg \
927 -c "gdb_memory_map enable" \
928 -c "gdb_flash_program enable" \
929 -f target/sam7x256.cfg
930 @end example
932 You could wrap such long command lines in shell scripts,
933 each supporting a different development task.
934 One might re-flash the board with a specific firmware version.
935 Another might set up a particular debugging or run-time environment.
937 @quotation Important
938 At this writing (October 2009) the command line method has
939 problems with how it treats variables.
940 For example, after @option{-c "set VAR value"}, or doing the
941 same in a script, the variable @var{VAR} will have no value
942 that can be tested in a later script.
943 @end quotation
945 Here we will focus on the simpler solution: one user config
946 file, including basic configuration plus any TCL procedures
947 to simplify your work.
949 @section User Config Files
950 @cindex config file, user
951 @cindex user config file
952 @cindex config file, overview
954 A user configuration file ties together all the parts of a project
955 in one place.
956 One of the following will match your situation best:
958 @itemize
959 @item Ideally almost everything comes from configuration files
960 provided by someone else.
961 For example, OpenOCD distributes a @file{scripts} directory
962 (probably in @file{/usr/share/openocd/scripts} on Linux).
963 Board and tool vendors can provide these too, as can individual
964 user sites; the @option{-s} command line option lets you say
965 where to find these files. (@xref{Running}.)
966 The AT91SAM7X256 example above works this way.
968 Three main types of non-user configuration file each have their
969 own subdirectory in the @file{scripts} directory:
971 @enumerate
972 @item @b{interface} -- one for each different debug adapter;
973 @item @b{board} -- one for each different board
974 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
975 @end enumerate
977 Best case: include just two files, and they handle everything else.
978 The first is an interface config file.
979 The second is board-specific, and it sets up the JTAG TAPs and
980 their GDB targets (by deferring to some @file{target.cfg} file),
981 declares all flash memory, and leaves you nothing to do except
982 meet your deadline:
984 @example
985 source [find interface/olimex-jtag-tiny.cfg]
986 source [find board/csb337.cfg]
987 @end example
989 Boards with a single microcontroller often won't need more
990 than the target config file, as in the AT91SAM7X256 example.
991 That's because there is no external memory (flash, DDR RAM), and
992 the board differences are encapsulated by application code.
994 @item Maybe you don't know yet what your board looks like to JTAG.
995 Once you know the @file{interface.cfg} file to use, you may
996 need help from OpenOCD to discover what's on the board.
997 Once you find the JTAG TAPs, you can just search for appropriate
998 target and board
999 configuration files ... or write your own, from the bottom up.
1000 @xref{autoprobing,,Autoprobing}.
1002 @item You can often reuse some standard config files but
1003 need to write a few new ones, probably a @file{board.cfg} file.
1004 You will be using commands described later in this User's Guide,
1005 and working with the guidelines in the next chapter.
1007 For example, there may be configuration files for your JTAG adapter
1008 and target chip, but you need a new board-specific config file
1009 giving access to your particular flash chips.
1010 Or you might need to write another target chip configuration file
1011 for a new chip built around the Cortex-M3 core.
1013 @quotation Note
1014 When you write new configuration files, please submit
1015 them for inclusion in the next OpenOCD release.
1016 For example, a @file{board/newboard.cfg} file will help the
1017 next users of that board, and a @file{target/newcpu.cfg}
1018 will help support users of any board using that chip.
1019 @end quotation
1021 @item
1022 You may may need to write some C code.
1023 It may be as simple as supporting a new FT2232 or parport
1024 based adapter; a bit more involved, like a NAND or NOR flash
1025 controller driver; or a big piece of work like supporting
1026 a new chip architecture.
1027 @end itemize
1029 Reuse the existing config files when you can.
1030 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1031 You may find a board configuration that's a good example to follow.
1033 When you write config files, separate the reusable parts
1034 (things every user of that interface, chip, or board needs)
1035 from ones specific to your environment and debugging approach.
1036 @itemize
1038 @item
1039 For example, a @code{gdb-attach} event handler that invokes
1040 the @command{reset init} command will interfere with debugging
1041 early boot code, which performs some of the same actions
1042 that the @code{reset-init} event handler does.
1044 @item
1045 Likewise, the @command{arm9 vector_catch} command (or
1046 @cindex vector_catch
1047 its siblings @command{xscale vector_catch}
1048 and @command{cortex_m vector_catch}) can be a time-saver
1049 during some debug sessions, but don't make everyone use that either.
1050 Keep those kinds of debugging aids in your user config file,
1051 along with messaging and tracing setup.
1052 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1054 @item
1055 You might need to override some defaults.
1056 For example, you might need to move, shrink, or back up the target's
1057 work area if your application needs much SRAM.
1059 @item
1060 TCP/IP port configuration is another example of something which
1061 is environment-specific, and should only appear in
1062 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1063 @end itemize
1065 @section Project-Specific Utilities
1067 A few project-specific utility
1068 routines may well speed up your work.
1069 Write them, and keep them in your project's user config file.
1071 For example, if you are making a boot loader work on a
1072 board, it's nice to be able to debug the ``after it's
1073 loaded to RAM'' parts separately from the finicky early
1074 code which sets up the DDR RAM controller and clocks.
1075 A script like this one, or a more GDB-aware sibling,
1076 may help:
1078 @example
1079 proc ramboot @{ @} @{
1080 # Reset, running the target's "reset-init" scripts
1081 # to initialize clocks and the DDR RAM controller.
1082 # Leave the CPU halted.
1083 reset init
1085 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1086 load_image u-boot.bin 0x20000000
1088 # Start running.
1089 resume 0x20000000
1090 @}
1091 @end example
1093 Then once that code is working you will need to make it
1094 boot from NOR flash; a different utility would help.
1095 Alternatively, some developers write to flash using GDB.
1096 (You might use a similar script if you're working with a flash
1097 based microcontroller application instead of a boot loader.)
1099 @example
1100 proc newboot @{ @} @{
1101 # Reset, leaving the CPU halted. The "reset-init" event
1102 # proc gives faster access to the CPU and to NOR flash;
1103 # "reset halt" would be slower.
1104 reset init
1106 # Write standard version of U-Boot into the first two
1107 # sectors of NOR flash ... the standard version should
1108 # do the same lowlevel init as "reset-init".
1109 flash protect 0 0 1 off
1110 flash erase_sector 0 0 1
1111 flash write_bank 0 u-boot.bin 0x0
1112 flash protect 0 0 1 on
1114 # Reboot from scratch using that new boot loader.
1115 reset run
1116 @}
1117 @end example
1119 You may need more complicated utility procedures when booting
1120 from NAND.
1121 That often involves an extra bootloader stage,
1122 running from on-chip SRAM to perform DDR RAM setup so it can load
1123 the main bootloader code (which won't fit into that SRAM).
1125 Other helper scripts might be used to write production system images,
1126 involving considerably more than just a three stage bootloader.
1128 @section Target Software Changes
1130 Sometimes you may want to make some small changes to the software
1131 you're developing, to help make JTAG debugging work better.
1132 For example, in C or assembly language code you might
1133 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1134 handling issues like:
1136 @itemize @bullet
1138 @item @b{Watchdog Timers}...
1139 Watchdog timers are typically used to automatically reset systems if
1140 some application task doesn't periodically reset the timer. (The
1141 assumption is that the system has locked up if the task can't run.)
1142 When a JTAG debugger halts the system, that task won't be able to run
1143 and reset the timer ... potentially causing resets in the middle of
1144 your debug sessions.
1146 It's rarely a good idea to disable such watchdogs, since their usage
1147 needs to be debugged just like all other parts of your firmware.
1148 That might however be your only option.
1150 Look instead for chip-specific ways to stop the watchdog from counting
1151 while the system is in a debug halt state. It may be simplest to set
1152 that non-counting mode in your debugger startup scripts. You may however
1153 need a different approach when, for example, a motor could be physically
1154 damaged by firmware remaining inactive in a debug halt state. That might
1155 involve a type of firmware mode where that "non-counting" mode is disabled
1156 at the beginning then re-enabled at the end; a watchdog reset might fire
1157 and complicate the debug session, but hardware (or people) would be
1158 protected.@footnote{Note that many systems support a "monitor mode" debug
1159 that is a somewhat cleaner way to address such issues. You can think of
1160 it as only halting part of the system, maybe just one task,
1161 instead of the whole thing.
1162 At this writing, January 2010, OpenOCD based debugging does not support
1163 monitor mode debug, only "halt mode" debug.}
1165 @item @b{ARM Semihosting}...
1166 @cindex ARM semihosting
1167 When linked with a special runtime library provided with many
1168 toolchains@footnote{See chapter 8 "Semihosting" in
1169 @uref{,
1170 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1171 The CodeSourcery EABI toolchain also includes a semihosting library.},
1172 your target code can use I/O facilities on the debug host. That library
1173 provides a small set of system calls which are handled by OpenOCD.
1174 It can let the debugger provide your system console and a file system,
1175 helping with early debugging or providing a more capable environment
1176 for sometimes-complex tasks like installing system firmware onto
1177 NAND or SPI flash.
1179 @item @b{ARM Wait-For-Interrupt}...
1180 Many ARM chips synchronize the JTAG clock using the core clock.
1181 Low power states which stop that core clock thus prevent JTAG access.
1182 Idle loops in tasking environments often enter those low power states
1183 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1185 You may want to @emph{disable that instruction} in source code,
1186 or otherwise prevent using that state,
1187 to ensure you can get JTAG access at any time.@footnote{As a more
1188 polite alternative, some processors have special debug-oriented
1189 registers which can be used to change various features including
1190 how the low power states are clocked while debugging.
1191 The STM32 DBGMCU_CR register is an example; at the cost of extra
1192 power consumption, JTAG can be used during low power states.}
1193 For example, the OpenOCD @command{halt} command may not
1194 work for an idle processor otherwise.
1196 @item @b{Delay after reset}...
1197 Not all chips have good support for debugger access
1198 right after reset; many LPC2xxx chips have issues here.
1199 Similarly, applications that reconfigure pins used for
1200 JTAG access as they start will also block debugger access.
1202 To work with boards like this, @emph{enable a short delay loop}
1203 the first thing after reset, before "real" startup activities.
1204 For example, one second's delay is usually more than enough
1205 time for a JTAG debugger to attach, so that
1206 early code execution can be debugged
1207 or firmware can be replaced.
1209 @item @b{Debug Communications Channel (DCC)}...
1210 Some processors include mechanisms to send messages over JTAG.
1211 Many ARM cores support these, as do some cores from other vendors.
1212 (OpenOCD may be able to use this DCC internally, speeding up some
1213 operations like writing to memory.)
1215 Your application may want to deliver various debugging messages
1216 over JTAG, by @emph{linking with a small library of code}
1217 provided with OpenOCD and using the utilities there to send
1218 various kinds of message.
1219 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1221 @end itemize
1223 @section Target Hardware Setup
1225 Chip vendors often provide software development boards which
1226 are highly configurable, so that they can support all options
1227 that product boards may require. @emph{Make sure that any
1228 jumpers or switches match the system configuration you are
1229 working with.}
1231 Common issues include:
1233 @itemize @bullet
1235 @item @b{JTAG setup} ...
1236 Boards may support more than one JTAG configuration.
1237 Examples include jumpers controlling pullups versus pulldowns
1238 on the nTRST and/or nSRST signals, and choice of connectors
1239 (e.g. which of two headers on the base board,
1240 or one from a daughtercard).
1241 For some Texas Instruments boards, you may need to jumper the
1242 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1244 @item @b{Boot Modes} ...
1245 Complex chips often support multiple boot modes, controlled
1246 by external jumpers. Make sure this is set up correctly.
1247 For example many i.MX boards from NXP need to be jumpered
1248 to "ATX mode" to start booting using the on-chip ROM, when
1249 using second stage bootloader code stored in a NAND flash chip.
1251 Such explicit configuration is common, and not limited to
1252 booting from NAND. You might also need to set jumpers to
1253 start booting using code loaded from an MMC/SD card; external
1254 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1255 flash; some external host; or various other sources.
1258 @item @b{Memory Addressing} ...
1259 Boards which support multiple boot modes may also have jumpers
1260 to configure memory addressing. One board, for example, jumpers
1261 external chipselect 0 (used for booting) to address either
1262 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1263 or NAND flash. When it's jumpered to address NAND flash, that
1264 board must also be told to start booting from on-chip ROM.
1266 Your @file{board.cfg} file may also need to be told this jumper
1267 configuration, so that it can know whether to declare NOR flash
1268 using @command{flash bank} or instead declare NAND flash with
1269 @command{nand device}; and likewise which probe to perform in
1270 its @code{reset-init} handler.
1272 A closely related issue is bus width. Jumpers might need to
1273 distinguish between 8 bit or 16 bit bus access for the flash
1274 used to start booting.
1276 @item @b{Peripheral Access} ...
1277 Development boards generally provide access to every peripheral
1278 on the chip, sometimes in multiple modes (such as by providing
1279 multiple audio codec chips).
1280 This interacts with software
1281 configuration of pin multiplexing, where for example a
1282 given pin may be routed either to the MMC/SD controller
1283 or the GPIO controller. It also often interacts with
1284 configuration jumpers. One jumper may be used to route
1285 signals to an MMC/SD card slot or an expansion bus (which
1286 might in turn affect booting); others might control which
1287 audio or video codecs are used.
1289 @end itemize
1291 Plus you should of course have @code{reset-init} event handlers
1292 which set up the hardware to match that jumper configuration.
1293 That includes in particular any oscillator or PLL used to clock
1294 the CPU, and any memory controllers needed to access external
1295 memory and peripherals. Without such handlers, you won't be
1296 able to access those resources without working target firmware
1297 which can do that setup ... this can be awkward when you're
1298 trying to debug that target firmware. Even if there's a ROM
1299 bootloader which handles a few issues, it rarely provides full
1300 access to all board-specific capabilities.
1303 @node Config File Guidelines
1304 @chapter Config File Guidelines
1306 This chapter is aimed at any user who needs to write a config file,
1307 including developers and integrators of OpenOCD and any user who
1308 needs to get a new board working smoothly.
1309 It provides guidelines for creating those files.
1311 You should find the following directories under
1312 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1313 them as-is where you can; or as models for new files.
1314 @itemize @bullet
1315 @item @file{interface} ...
1316 These are for debug adapters. Files that specify configuration to use
1317 specific JTAG, SWD and other adapters go here.
1318 @item @file{board} ...
1319 Think Circuit Board, PWA, PCB, they go by many names. Board files
1320 contain initialization items that are specific to a board.
1322 They reuse target configuration files, since the same
1323 microprocessor chips are used on many boards,
1324 but support for external parts varies widely. For
1325 example, the SDRAM initialization sequence for the board, or the type
1326 of external flash and what address it uses. Any initialization
1327 sequence to enable that external flash or SDRAM should be found in the
1328 board file. Boards may also contain multiple targets: two CPUs; or
1329 a CPU and an FPGA.
1330 @item @file{target} ...
1331 Think chip. The ``target'' directory represents the JTAG TAPs
1332 on a chip
1333 which OpenOCD should control, not a board. Two common types of targets
1334 are ARM chips and FPGA or CPLD chips.
1335 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1336 the target config file defines all of them.
1337 @item @emph{more} ... browse for other library files which may be useful.
1338 For example, there are various generic and CPU-specific utilities.
1339 @end itemize
1341 The @file{openocd.cfg} user config
1342 file may override features in any of the above files by
1343 setting variables before sourcing the target file, or by adding
1344 commands specific to their situation.
1346 @section Interface Config Files
1348 The user config file
1349 should be able to source one of these files with a command like this:
1351 @example
1352 source [find interface/FOOBAR.cfg]
1353 @end example
1355 A preconfigured interface file should exist for every debug adapter
1356 in use today with OpenOCD.
1357 That said, perhaps some of these config files
1358 have only been used by the developer who created it.
1360 A separate chapter gives information about how to set these up.
1361 @xref{Debug Adapter Configuration}.
1362 Read the OpenOCD source code (and Developer's Guide)
1363 if you have a new kind of hardware interface
1364 and need to provide a driver for it.
1366 @section Board Config Files
1367 @cindex config file, board
1368 @cindex board config file
1370 The user config file
1371 should be able to source one of these files with a command like this:
1373 @example
1374 source [find board/FOOBAR.cfg]
1375 @end example
1377 The point of a board config file is to package everything
1378 about a given board that user config files need to know.
1379 In summary the board files should contain (if present)
1381 @enumerate
1382 @item One or more @command{source [find target/...cfg]} statements
1383 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1384 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1385 @item Target @code{reset} handlers for SDRAM and I/O configuration
1386 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1387 @item All things that are not ``inside a chip''
1388 @end enumerate
1390 Generic things inside target chips belong in target config files,
1391 not board config files. So for example a @code{reset-init} event
1392 handler should know board-specific oscillator and PLL parameters,
1393 which it passes to target-specific utility code.
1395 The most complex task of a board config file is creating such a
1396 @code{reset-init} event handler.
1397 Define those handlers last, after you verify the rest of the board
1398 configuration works.
1400 @subsection Communication Between Config files
1402 In addition to target-specific utility code, another way that
1403 board and target config files communicate is by following a
1404 convention on how to use certain variables.
1406 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1407 Thus the rule we follow in OpenOCD is this: Variables that begin with
1408 a leading underscore are temporary in nature, and can be modified and
1409 used at will within a target configuration file.
1411 Complex board config files can do the things like this,
1412 for a board with three chips:
1414 @example
1415 # Chip #1: PXA270 for network side, big endian
1416 set CHIPNAME network
1417 set ENDIAN big
1418 source [find target/pxa270.cfg]
1419 # on return: _TARGETNAME = network.cpu
1420 # other commands can refer to the "network.cpu" target.
1421 $_TARGETNAME configure .... events for this CPU..
1423 # Chip #2: PXA270 for video side, little endian
1424 set CHIPNAME video
1425 set ENDIAN little
1426 source [find target/pxa270.cfg]
1427 # on return: _TARGETNAME = video.cpu
1428 # other commands can refer to the "video.cpu" target.
1429 $_TARGETNAME configure .... events for this CPU..
1431 # Chip #3: Xilinx FPGA for glue logic
1432 set CHIPNAME xilinx
1433 unset ENDIAN
1434 source [find target/spartan3.cfg]
1435 @end example
1437 That example is oversimplified because it doesn't show any flash memory,
1438 or the @code{reset-init} event handlers to initialize external DRAM
1439 or (assuming it needs it) load a configuration into the FPGA.
1440 Such features are usually needed for low-level work with many boards,
1441 where ``low level'' implies that the board initialization software may
1442 not be working. (That's a common reason to need JTAG tools. Another
1443 is to enable working with microcontroller-based systems, which often
1444 have no debugging support except a JTAG connector.)
1446 Target config files may also export utility functions to board and user
1447 config files. Such functions should use name prefixes, to help avoid
1448 naming collisions.
1450 Board files could also accept input variables from user config files.
1451 For example, there might be a @code{J4_JUMPER} setting used to identify
1452 what kind of flash memory a development board is using, or how to set
1453 up other clocks and peripherals.
1455 @subsection Variable Naming Convention
1456 @cindex variable names
1458 Most boards have only one instance of a chip.
1459 However, it should be easy to create a board with more than
1460 one such chip (as shown above).
1461 Accordingly, we encourage these conventions for naming
1462 variables associated with different @file{target.cfg} files,
1463 to promote consistency and
1464 so that board files can override target defaults.
1466 Inputs to target config files include:
1468 @itemize @bullet
1469 @item @code{CHIPNAME} ...
1470 This gives a name to the overall chip, and is used as part of
1471 tap identifier dotted names.
1472 While the default is normally provided by the chip manufacturer,
1473 board files may need to distinguish between instances of a chip.
1474 @item @code{ENDIAN} ...
1475 By default @option{little} - although chips may hard-wire @option{big}.
1476 Chips that can't change endianess don't need to use this variable.
1477 @item @code{CPUTAPID} ...
1478 When OpenOCD examines the JTAG chain, it can be told verify the
1479 chips against the JTAG IDCODE register.
1480 The target file will hold one or more defaults, but sometimes the
1481 chip in a board will use a different ID (perhaps a newer revision).
1482 @end itemize
1484 Outputs from target config files include:
1486 @itemize @bullet
1487 @item @code{_TARGETNAME} ...
1488 By convention, this variable is created by the target configuration
1489 script. The board configuration file may make use of this variable to
1490 configure things like a ``reset init'' script, or other things
1491 specific to that board and that target.
1492 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1493 @code{_TARGETNAME1}, ... etc.
1494 @end itemize
1496 @subsection The reset-init Event Handler
1497 @cindex event, reset-init
1498 @cindex reset-init handler
1500 Board config files run in the OpenOCD configuration stage;
1501 they can't use TAPs or targets, since they haven't been
1502 fully set up yet.
1503 This means you can't write memory or access chip registers;
1504 you can't even verify that a flash chip is present.
1505 That's done later in event handlers, of which the target @code{reset-init}
1506 handler is one of the most important.
1508 Except on microcontrollers, the basic job of @code{reset-init} event
1509 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1510 Microcontrollers rarely use boot loaders; they run right out of their
1511 on-chip flash and SRAM memory. But they may want to use one of these
1512 handlers too, if just for developer convenience.
1514 @quotation Note
1515 Because this is so very board-specific, and chip-specific, no examples
1516 are included here.
1517 Instead, look at the board config files distributed with OpenOCD.
1518 If you have a boot loader, its source code will help; so will
1519 configuration files for other JTAG tools
1520 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1521 @end quotation
1523 Some of this code could probably be shared between different boards.
1524 For example, setting up a DRAM controller often doesn't differ by
1525 much except the bus width (16 bits or 32?) and memory timings, so a
1526 reusable TCL procedure loaded by the @file{target.cfg} file might take
1527 those as parameters.
1528 Similarly with oscillator, PLL, and clock setup;
1529 and disabling the watchdog.
1530 Structure the code cleanly, and provide comments to help
1531 the next developer doing such work.
1532 (@emph{You might be that next person} trying to reuse init code!)
1534 The last thing normally done in a @code{reset-init} handler is probing
1535 whatever flash memory was configured. For most chips that needs to be
1536 done while the associated target is halted, either because JTAG memory
1537 access uses the CPU or to prevent conflicting CPU access.
1539 @subsection JTAG Clock Rate
1541 Before your @code{reset-init} handler has set up
1542 the PLLs and clocking, you may need to run with
1543 a low JTAG clock rate.
1544 @xref{jtagspeed,,JTAG Speed}.
1545 Then you'd increase that rate after your handler has
1546 made it possible to use the faster JTAG clock.
1547 When the initial low speed is board-specific, for example
1548 because it depends on a board-specific oscillator speed, then
1549 you should probably set it up in the board config file;
1550 if it's target-specific, it belongs in the target config file.
1552 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1553 @uref{} gives details.}
1554 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1555 Consult chip documentation to determine the peak JTAG clock rate,
1556 which might be less than that.
1558 @quotation Warning
1559 On most ARMs, JTAG clock detection is coupled to the core clock, so
1560 software using a @option{wait for interrupt} operation blocks JTAG access.
1561 Adaptive clocking provides a partial workaround, but a more complete
1562 solution just avoids using that instruction with JTAG debuggers.
1563 @end quotation
1565 If both the chip and the board support adaptive clocking,
1566 use the @command{jtag_rclk}
1567 command, in case your board is used with JTAG adapter which
1568 also supports it. Otherwise use @command{adapter_khz}.
1569 Set the slow rate at the beginning of the reset sequence,
1570 and the faster rate as soon as the clocks are at full speed.
1572 @anchor{theinitboardprocedure}
1573 @subsection The init_board procedure
1574 @cindex init_board procedure
1576 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1577 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1578 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1579 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1580 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1581 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1582 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1583 Additionally ``linear'' board config file will most likely fail when target config file uses
1584 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1585 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1586 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1587 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1589 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1590 the original), allowing greater code reuse.
1592 @example
1593 ### board_file.cfg ###
1595 # source target file that does most of the config in init_targets
1596 source [find target/target.cfg]
1598 proc enable_fast_clock @{@} @{
1599 # enables fast on-board clock source
1600 # configures the chip to use it
1601 @}
1603 # initialize only board specifics - reset, clock, adapter frequency
1604 proc init_board @{@} @{
1605 reset_config trst_and_srst trst_pulls_srst
1607 $_TARGETNAME configure -event reset-start @{
1608 adapter_khz 100
1609 @}
1611 $_TARGETNAME configure -event reset-init @{
1612 enable_fast_clock
1613 adapter_khz 10000
1614 @}
1615 @}
1616 @end example
1618 @section Target Config Files
1619 @cindex config file, target
1620 @cindex target config file
1622 Board config files communicate with target config files using
1623 naming conventions as described above, and may source one or
1624 more target config files like this:
1626 @example
1627 source [find target/FOOBAR.cfg]
1628 @end example
1630 The point of a target config file is to package everything
1631 about a given chip that board config files need to know.
1632 In summary the target files should contain
1634 @enumerate
1635 @item Set defaults
1636 @item Add TAPs to the scan chain
1637 @item Add CPU targets (includes GDB support)
1638 @item CPU/Chip/CPU-Core specific features
1639 @item On-Chip flash
1640 @end enumerate
1642 As a rule of thumb, a target file sets up only one chip.
1643 For a microcontroller, that will often include a single TAP,
1644 which is a CPU needing a GDB target, and its on-chip flash.
1646 More complex chips may include multiple TAPs, and the target
1647 config file may need to define them all before OpenOCD
1648 can talk to the chip.
1649 For example, some phone chips have JTAG scan chains that include
1650 an ARM core for operating system use, a DSP,
1651 another ARM core embedded in an image processing engine,
1652 and other processing engines.
1654 @subsection Default Value Boiler Plate Code
1656 All target configuration files should start with code like this,
1657 letting board config files express environment-specific
1658 differences in how things should be set up.
1660 @example
1661 # Boards may override chip names, perhaps based on role,
1662 # but the default should match what the vendor uses
1663 if @{ [info exists CHIPNAME] @} @{
1665 @} else @{
1666 set _CHIPNAME sam7x256
1667 @}
1669 # ONLY use ENDIAN with targets that can change it.
1670 if @{ [info exists ENDIAN] @} @{
1671 set _ENDIAN $ENDIAN
1672 @} else @{
1673 set _ENDIAN little
1674 @}
1676 # TAP identifiers may change as chips mature, for example with
1677 # new revision fields (the "3" here). Pick a good default; you
1678 # can pass several such identifiers to the "jtag newtap" command.
1679 if @{ [info exists CPUTAPID ] @} @{
1681 @} else @{
1682 set _CPUTAPID 0x3f0f0f0f
1683 @}
1684 @end example
1685 @c but 0x3f0f0f0f is for an str73x part ...
1687 @emph{Remember:} Board config files may include multiple target
1688 config files, or the same target file multiple times
1689 (changing at least @code{CHIPNAME}).
1691 Likewise, the target configuration file should define
1692 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1693 use it later on when defining debug targets:
1695 @example
1697 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1698 @end example
1700 @subsection Adding TAPs to the Scan Chain
1701 After the ``defaults'' are set up,
1702 add the TAPs on each chip to the JTAG scan chain.
1703 @xref{TAP Declaration}, and the naming convention
1704 for taps.
1706 In the simplest case the chip has only one TAP,
1707 probably for a CPU or FPGA.
1708 The config file for the Atmel AT91SAM7X256
1709 looks (in part) like this:
1711 @example
1712 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1713 @end example
1715 A board with two such at91sam7 chips would be able
1716 to source such a config file twice, with different
1717 values for @code{CHIPNAME}, so
1718 it adds a different TAP each time.
1720 If there are nonzero @option{-expected-id} values,
1721 OpenOCD attempts to verify the actual tap id against those values.
1722 It will issue error messages if there is mismatch, which
1723 can help to pinpoint problems in OpenOCD configurations.
1725 @example
1726 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1727 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1728 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1729 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1730 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1731 @end example
1733 There are more complex examples too, with chips that have
1734 multiple TAPs. Ones worth looking at include:
1736 @itemize
1737 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1738 plus a JRC to enable them
1739 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1740 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1741 is not currently used)
1742 @end itemize
1744 @subsection Add CPU targets
1746 After adding a TAP for a CPU, you should set it up so that
1747 GDB and other commands can use it.
1748 @xref{CPU Configuration}.
1749 For the at91sam7 example above, the command can look like this;
1750 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1751 to little endian, and this chip doesn't support changing that.
1753 @example
1755 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1756 @end example
1758 Work areas are small RAM areas associated with CPU targets.
1759 They are used by OpenOCD to speed up downloads,
1760 and to download small snippets of code to program flash chips.
1761 If the chip includes a form of ``on-chip-ram'' - and many do - define
1762 a work area if you can.
1763 Again using the at91sam7 as an example, this can look like:
1765 @example
1766 $_TARGETNAME configure -work-area-phys 0x00200000 \
1767 -work-area-size 0x4000 -work-area-backup 0
1768 @end example
1770 @anchor{definecputargetsworkinginsmp}
1771 @subsection Define CPU targets working in SMP
1772 @cindex SMP
1773 After setting targets, you can define a list of targets working in SMP.
1775 @example
1776 set _TARGETNAME_1 $_CHIPNAME.cpu1
1777 set _TARGETNAME_2 $_CHIPNAME.cpu2
1778 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1779 -coreid 0 -dbgbase $_DAP_DBG1
1780 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1781 -coreid 1 -dbgbase $_DAP_DBG2
1782 #define 2 targets working in smp.
1783 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1784 @end example
1785 In the above example on cortex_a, 2 cpus are working in SMP.
1786 In SMP only one GDB instance is created and :
1787 @itemize @bullet
1788 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1789 @item halt command triggers the halt of all targets in the list.
1790 @item resume command triggers the write context and the restart of all targets in the list.
1791 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1792 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1793 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1794 @end itemize
1796 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1797 command have been implemented.
1798 @itemize @bullet
1799 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1800 @item cortex_a smp_off : disable SMP mode, the current target is the one
1801 displayed in the GDB session, only this target is now controlled by GDB
1802 session. This behaviour is useful during system boot up.
1803 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1804 following example.
1805 @end itemize
1807 @example
1808 >cortex_a smp_gdb
1809 gdb coreid 0 -> -1
1810 #0 : coreid 0 is displayed to GDB ,
1811 #-> -1 : next resume triggers a real resume
1812 > cortex_a smp_gdb 1
1813 gdb coreid 0 -> 1
1814 #0 :coreid 0 is displayed to GDB ,
1815 #->1 : next resume displays coreid 1 to GDB
1816 > resume
1817 > cortex_a smp_gdb
1818 gdb coreid 1 -> 1
1819 #1 :coreid 1 is displayed to GDB ,
1820 #->1 : next resume displays coreid 1 to GDB
1821 > cortex_a smp_gdb -1
1822 gdb coreid 1 -> -1
1823 #1 :coreid 1 is displayed to GDB,
1824 #->-1 : next resume triggers a real resume
1825 @end example
1828 @subsection Chip Reset Setup
1830 As a rule, you should put the @command{reset_config} command
1831 into the board file. Most things you think you know about a
1832 chip can be tweaked by the board.
1834 Some chips have specific ways the TRST and SRST signals are
1835 managed. In the unusual case that these are @emph{chip specific}
1836 and can never be changed by board wiring, they could go here.
1837 For example, some chips can't support JTAG debugging without
1838 both signals.
1840 Provide a @code{reset-assert} event handler if you can.
1841 Such a handler uses JTAG operations to reset the target,
1842 letting this target config be used in systems which don't
1843 provide the optional SRST signal, or on systems where you
1844 don't want to reset all targets at once.
1845 Such a handler might write to chip registers to force a reset,
1846 use a JRC to do that (preferable -- the target may be wedged!),
1847 or force a watchdog timer to trigger.
1848 (For Cortex-M targets, this is not necessary. The target
1849 driver knows how to use trigger an NVIC reset when SRST is
1850 not available.)
1852 Some chips need special attention during reset handling if
1853 they're going to be used with JTAG.
1854 An example might be needing to send some commands right
1855 after the target's TAP has been reset, providing a
1856 @code{reset-deassert-post} event handler that writes a chip
1857 register to report that JTAG debugging is being done.
1858 Another would be reconfiguring the watchdog so that it stops
1859 counting while the core is halted in the debugger.
1861 JTAG clocking constraints often change during reset, and in
1862 some cases target config files (rather than board config files)
1863 are the right places to handle some of those issues.
1864 For example, immediately after reset most chips run using a
1865 slower clock than they will use later.
1866 That means that after reset (and potentially, as OpenOCD
1867 first starts up) they must use a slower JTAG clock rate
1868 than they will use later.
1869 @xref{jtagspeed,,JTAG Speed}.
1871 @quotation Important
1872 When you are debugging code that runs right after chip
1873 reset, getting these issues right is critical.
1874 In particular, if you see intermittent failures when
1875 OpenOCD verifies the scan chain after reset,
1876 look at how you are setting up JTAG clocking.
1877 @end quotation
1879 @anchor{theinittargetsprocedure}
1880 @subsection The init_targets procedure
1881 @cindex init_targets procedure
1883 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1884 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1885 procedure called @code{init_targets}, which will be executed when entering run stage
1886 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1887 Such procedure can be overridden by ``next level'' script (which sources the original).
1888 This concept facilitates code reuse when basic target config files provide generic configuration
1889 procedures and @code{init_targets} procedure, which can then be sourced and enhanced or changed in
1890 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1891 because sourcing them executes every initialization commands they provide.
1893 @example
1894 ### generic_file.cfg ###
1896 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1897 # basic initialization procedure ...
1898 @}
1900 proc init_targets @{@} @{
1901 # initializes generic chip with 4kB of flash and 1kB of RAM
1902 setup_my_chip MY_GENERIC_CHIP 4096 1024
1903 @}
1905 ### specific_file.cfg ###
1907 source [find target/generic_file.cfg]
1909 proc init_targets @{@} @{
1910 # initializes specific chip with 128kB of flash and 64kB of RAM
1911 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1912 @}
1913 @end example
1915 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1916 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1918 For an example of this scheme see LPC2000 target config files.
1920 The @code{init_boards} procedure is a similar concept concerning board config files
1921 (@xref{theinitboardprocedure,,The init_board procedure}.)
1923 @anchor{theinittargeteventsprocedure}
1924 @subsection The init_target_events procedure
1925 @cindex init_target_events procedure
1927 A special procedure called @code{init_target_events} is run just after
1928 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1929 procedure}.) and before @code{init_board}
1930 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1931 to set up default target events for the targets that do not have those
1932 events already assigned.
1934 @subsection ARM Core Specific Hacks
1936 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1937 special high speed download features - enable it.
1939 If present, the MMU, the MPU and the CACHE should be disabled.
1941 Some ARM cores are equipped with trace support, which permits
1942 examination of the instruction and data bus activity. Trace
1943 activity is controlled through an ``Embedded Trace Module'' (ETM)
1944 on one of the core's scan chains. The ETM emits voluminous data
1945 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1946 If you are using an external trace port,
1947 configure it in your board config file.
1948 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1949 configure it in your target config file.
1951 @example
1952 etm config $_TARGETNAME 16 normal full etb
1953 etb config $_TARGETNAME $_CHIPNAME.etb
1954 @end example
1956 @subsection Internal Flash Configuration
1958 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1960 @b{Never ever} in the ``target configuration file'' define any type of
1961 flash that is external to the chip. (For example a BOOT flash on
1962 Chip Select 0.) Such flash information goes in a board file - not
1963 the TARGET (chip) file.
1965 Examples:
1966 @itemize @bullet
1967 @item at91sam7x256 - has 256K flash YES enable it.
1968 @item str912 - has flash internal YES enable it.
1969 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1970 @item pxa270 - again - CS0 flash - it goes in the board file.
1971 @end itemize
1973 @anchor{translatingconfigurationfiles}
1974 @section Translating Configuration Files
1975 @cindex translation
1976 If you have a configuration file for another hardware debugger
1977 or toolset (Abatron, BDI2000, BDI3000, CCS,
1978 Lauterbach, SEGGER, Macraigor, etc.), translating
1979 it into OpenOCD syntax is often quite straightforward. The most tricky
1980 part of creating a configuration script is oftentimes the reset init
1981 sequence where e.g. PLLs, DRAM and the like is set up.
1983 One trick that you can use when translating is to write small
1984 Tcl procedures to translate the syntax into OpenOCD syntax. This
1985 can avoid manual translation errors and make it easier to
1986 convert other scripts later on.
1988 Example of transforming quirky arguments to a simple search and
1989 replace job:
1991 @example
1992 # Lauterbach syntax(?)
1993 #
1994 # Data.Set c15:0x042f %long 0x40000015
1995 #
1996 # OpenOCD syntax when using procedure below.
1997 #
1998 # setc15 0x01 0x00050078
2000 proc setc15 @{regs value@} @{
2001 global TARGETNAME
2003 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2005 arm mcr 15 [expr ($regs>>12)&0x7] \
2006 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2007 [expr ($regs>>8)&0x7] $value
2008 @}
2009 @end example
2013 @node Server Configuration
2014 @chapter Server Configuration
2015 @cindex initialization
2016 The commands here are commonly found in the openocd.cfg file and are
2017 used to specify what TCP/IP ports are used, and how GDB should be
2018 supported.
2020 @anchor{configurationstage}
2021 @section Configuration Stage
2022 @cindex configuration stage
2023 @cindex config command
2025 When the OpenOCD server process starts up, it enters a
2026 @emph{configuration stage} which is the only time that
2027 certain commands, @emph{configuration commands}, may be issued.
2028 Normally, configuration commands are only available
2029 inside startup scripts.
2031 In this manual, the definition of a configuration command is
2032 presented as a @emph{Config Command}, not as a @emph{Command}
2033 which may be issued interactively.
2034 The runtime @command{help} command also highlights configuration
2035 commands, and those which may be issued at any time.
2037 Those configuration commands include declaration of TAPs,
2038 flash banks,
2039 the interface used for JTAG communication,
2040 and other basic setup.
2041 The server must leave the configuration stage before it
2042 may access or activate TAPs.
2043 After it leaves this stage, configuration commands may no
2044 longer be issued.
2046 @anchor{enteringtherunstage}
2047 @section Entering the Run Stage
2049 The first thing OpenOCD does after leaving the configuration
2050 stage is to verify that it can talk to the scan chain
2051 (list of TAPs) which has been configured.
2052 It will warn if it doesn't find TAPs it expects to find,
2053 or finds TAPs that aren't supposed to be there.
2054 You should see no errors at this point.
2055 If you see errors, resolve them by correcting the
2056 commands you used to configure the server.
2057 Common errors include using an initial JTAG speed that's too
2058 fast, and not providing the right IDCODE values for the TAPs
2059 on the scan chain.
2061 Once OpenOCD has entered the run stage, a number of commands
2062 become available.
2063 A number of these relate to the debug targets you may have declared.
2064 For example, the @command{mww} command will not be available until
2065 a target has been successfully instantiated.
2066 If you want to use those commands, you may need to force
2067 entry to the run stage.
2069 @deffn {Config Command} init
2070 This command terminates the configuration stage and
2071 enters the run stage. This helps when you need to have
2072 the startup scripts manage tasks such as resetting the target,
2073 programming flash, etc. To reset the CPU upon startup, add "init" and
2074 "reset" at the end of the config script or at the end of the OpenOCD
2075 command line using the @option{-c} command line switch.
2077 If this command does not appear in any startup/configuration file
2078 OpenOCD executes the command for you after processing all
2079 configuration files and/or command line options.
2081 @b{NOTE:} This command normally occurs at or near the end of your
2082 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2083 targets ready. For example: If your openocd.cfg file needs to
2084 read/write memory on your target, @command{init} must occur before
2085 the memory read/write commands. This includes @command{nand probe}.
2086 @end deffn
2088 @deffn {Overridable Procedure} jtag_init
2089 This is invoked at server startup to verify that it can talk
2090 to the scan chain (list of TAPs) which has been configured.
2092 The default implementation first tries @command{jtag arp_init},
2093 which uses only a lightweight JTAG reset before examining the
2094 scan chain.
2095 If that fails, it tries again, using a harder reset
2096 from the overridable procedure @command{init_reset}.
2098 Implementations must have verified the JTAG scan chain before
2099 they return.
2100 This is done by calling @command{jtag arp_init}
2101 (or @command{jtag arp_init-reset}).
2102 @end deffn
2104 @anchor{tcpipports}
2105 @section TCP/IP Ports
2106 @cindex TCP port
2107 @cindex server
2108 @cindex port
2109 @cindex security
2110 The OpenOCD server accepts remote commands in several syntaxes.
2111 Each syntax uses a different TCP/IP port, which you may specify
2112 only during configuration (before those ports are opened).
2114 For reasons including security, you may wish to prevent remote
2115 access using one or more of these ports.
2116 In such cases, just specify the relevant port number as "disabled".
2117 If you disable all access through TCP/IP, you will need to
2118 use the command line @option{-pipe} option.
2120 @anchor{gdb_port}
2121 @deffn {Command} gdb_port [number]
2122 @cindex GDB server
2123 Normally gdb listens to a TCP/IP port, but GDB can also
2124 communicate via pipes(stdin/out or named pipes). The name
2125 "gdb_port" stuck because it covers probably more than 90% of
2126 the normal use cases.
2128 No arguments reports GDB port. "pipe" means listen to stdin
2129 output to stdout, an integer is base port number, "disabled"
2130 disables the gdb server.
2132 When using "pipe", also use log_output to redirect the log
2133 output to a file so as not to flood the stdin/out pipes.
2135 The -p/--pipe option is deprecated and a warning is printed
2136 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2138 Any other string is interpreted as named pipe to listen to.
2139 Output pipe is the same name as input pipe, but with 'o' appended,
2140 e.g. /var/gdb, /var/gdbo.
2142 The GDB port for the first target will be the base port, the
2143 second target will listen on gdb_port + 1, and so on.
2144 When not specified during the configuration stage,
2145 the port @var{number} defaults to 3333.
2146 When @var{number} is not a numeric value, incrementing it to compute
2147 the next port number does not work. In this case, specify the proper
2148 @var{number} for each target by using the option @code{-gdb-port} of the
2149 commands @command{target create} or @command{$target_name configure}.
2150 @xref{gdbportoverride,,option -gdb-port}.
2152 Note: when using "gdb_port pipe", increasing the default remote timeout in
2153 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2154 cause initialization to fail with "Unknown remote qXfer reply: OK".
2155 @end deffn
2157 @deffn {Command} tcl_port [number]
2158 Specify or query the port used for a simplified RPC
2159 connection that can be used by clients to issue TCL commands and get the
2160 output from the Tcl engine.
2161 Intended as a machine interface.
2162 When not specified during the configuration stage,
2163 the port @var{number} defaults to 6666.
2164 When specified as "disabled", this service is not activated.
2165 @end deffn
2167 @deffn {Command} telnet_port [number]
2168 Specify or query the
2169 port on which to listen for incoming telnet connections.
2170 This port is intended for interaction with one human through TCL commands.
2171 When not specified during the configuration stage,
2172 the port @var{number} defaults to 4444.
2173 When specified as "disabled", this service is not activated.
2174 @end deffn
2176 @anchor{gdbconfiguration}
2177 @section GDB Configuration
2178 @cindex GDB
2179 @cindex GDB configuration
2180 You can reconfigure some GDB behaviors if needed.
2181 The ones listed here are static and global.
2182 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2183 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2185 @anchor{gdbbreakpointoverride}
2186 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2187 Force breakpoint type for gdb @command{break} commands.
2188 This option supports GDB GUIs which don't
2189 distinguish hard versus soft breakpoints, if the default OpenOCD and
2190 GDB behaviour is not sufficient. GDB normally uses hardware
2191 breakpoints if the memory map has been set up for flash regions.
2192 @end deffn
2194 @anchor{gdbflashprogram}
2195 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2196 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2197 vFlash packet is received.
2198 The default behaviour is @option{enable}.
2199 @end deffn
2201 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2202 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2203 requested. GDB will then know when to set hardware breakpoints, and program flash
2204 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2205 for flash programming to work.
2206 Default behaviour is @option{enable}.
2207 @xref{gdbflashprogram,,gdb_flash_program}.
2208 @end deffn
2210 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2211 Specifies whether data aborts cause an error to be reported
2212 by GDB memory read packets.
2213 The default behaviour is @option{disable};
2214 use @option{enable} see these errors reported.
2215 @end deffn
2217 @deffn {Config Command} gdb_report_register_access_error (@option{enable}|@option{disable})
2218 Specifies whether register accesses requested by GDB register read/write
2219 packets report errors or not.
2220 The default behaviour is @option{disable};
2221 use @option{enable} see these errors reported.
2222 @end deffn
2224 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2225 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2226 The default behaviour is @option{enable}.
2227 @end deffn
2229 @deffn {Command} gdb_save_tdesc
2230 Saves the target description file to the local file system.
2232 The file name is @i{target_name}.xml.
2233 @end deffn
2235 @anchor{eventpolling}
2236 @section Event Polling
2238 Hardware debuggers are parts of asynchronous systems,
2239 where significant events can happen at any time.
2240 The OpenOCD server needs to detect some of these events,
2241 so it can report them to through TCL command line
2242 or to GDB.
2244 Examples of such events include:
2246 @itemize
2247 @item One of the targets can stop running ... maybe it triggers
2248 a code breakpoint or data watchpoint, or halts itself.
2249 @item Messages may be sent over ``debug message'' channels ... many
2250 targets support such messages sent over JTAG,
2251 for receipt by the person debugging or tools.
2252 @item Loss of power ... some adapters can detect these events.
2253 @item Resets not issued through JTAG ... such reset sources
2254 can include button presses or other system hardware, sometimes
2255 including the target itself (perhaps through a watchdog).
2256 @item Debug instrumentation sometimes supports event triggering
2257 such as ``trace buffer full'' (so it can quickly be emptied)
2258 or other signals (to correlate with code behavior).
2259 @end itemize
2261 None of those events are signaled through standard JTAG signals.
2262 However, most conventions for JTAG connectors include voltage
2263 level and system reset (SRST) signal detection.
2264 Some connectors also include instrumentation signals, which
2265 can imply events when those signals are inputs.
2267 In general, OpenOCD needs to periodically check for those events,
2268 either by looking at the status of signals on the JTAG connector
2269 or by sending synchronous ``tell me your status'' JTAG requests
2270 to the various active targets.
2271 There is a command to manage and monitor that polling,
2272 which is normally done in the background.
2274 @deffn Command poll [@option{on}|@option{off}]
2275 Poll the current target for its current state.
2276 (Also, @pxref{targetcurstate,,target curstate}.)
2277 If that target is in debug mode, architecture
2278 specific information about the current state is printed.
2279 An optional parameter
2280 allows background polling to be enabled and disabled.
2282 You could use this from the TCL command shell, or
2283 from GDB using @command{monitor poll} command.
2284 Leave background polling enabled while you're using GDB.
2285 @example
2286 > poll
2287 background polling: on
2288 target state: halted
2289 target halted in ARM state due to debug-request, \
2290 current mode: Supervisor
2291 cpsr: 0x800000d3 pc: 0x11081bfc
2292 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2293 >
2294 @end example
2295 @end deffn
2297 @node Debug Adapter Configuration
2298 @chapter Debug Adapter Configuration
2299 @cindex config file, interface
2300 @cindex interface config file
2302 Correctly installing OpenOCD includes making your operating system give
2303 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2304 are used to select which one is used, and to configure how it is used.
2306 @quotation Note
2307 Because OpenOCD started out with a focus purely on JTAG, you may find
2308 places where it wrongly presumes JTAG is the only transport protocol
2309 in use. Be aware that recent versions of OpenOCD are removing that
2310 limitation. JTAG remains more functional than most other transports.
2311 Other transports do not support boundary scan operations, or may be
2312 specific to a given chip vendor. Some might be usable only for
2313 programming flash memory, instead of also for debugging.
2314 @end quotation
2316 Debug Adapters/Interfaces/Dongles are normally configured
2317 through commands in an interface configuration
2318 file which is sourced by your @file{openocd.cfg} file, or
2319 through a command line @option{-f interface/....cfg} option.
2321 @example
2322 source [find interface/olimex-jtag-tiny.cfg]
2323 @end example
2325 These commands tell
2326 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2327 A few cases are so simple that you only need to say what driver to use:
2329 @example
2330 # jlink interface
2331 interface jlink
2332 @end example
2334 Most adapters need a bit more configuration than that.
2337 @section Interface Configuration
2339 The interface command tells OpenOCD what type of debug adapter you are
2340 using. Depending on the type of adapter, you may need to use one or
2341 more additional commands to further identify or configure the adapter.
2343 @deffn {Config Command} {interface} name
2344 Use the interface driver @var{name} to connect to the
2345 target.
2346 @end deffn
2348 @deffn Command {interface_list}
2349 List the debug adapter drivers that have been built into
2350 the running copy of OpenOCD.
2351 @end deffn
2352 @deffn Command {interface transports} transport_name+
2353 Specifies the transports supported by this debug adapter.
2354 The adapter driver builds-in similar knowledge; use this only
2355 when external configuration (such as jumpering) changes what
2356 the hardware can support.
2357 @end deffn
2361 @deffn Command {adapter_name}
2362 Returns the name of the debug adapter driver being used.
2363 @end deffn
2365 @section Interface Drivers
2367 Each of the interface drivers listed here must be explicitly
2368 enabled when OpenOCD is configured, in order to be made
2369 available at run time.
2371 @deffn {Interface Driver} {amt_jtagaccel}
2372 Amontec Chameleon in its JTAG Accelerator configuration,
2373 connected to a PC's EPP mode parallel port.
2374 This defines some driver-specific commands:
2376 @deffn {Config Command} {parport_port} number
2377 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2378 the number of the @file{/dev/parport} device.
2379 @end deffn
2381 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2382 Displays status of RTCK option.
2383 Optionally sets that option first.
2384 @end deffn
2385 @end deffn
2387 @deffn {Interface Driver} {arm-jtag-ew}
2388 Olimex ARM-JTAG-EW USB adapter
2389 This has one driver-specific command:
2391 @deffn Command {armjtagew_info}
2392 Logs some status
2393 @end deffn
2394 @end deffn
2396 @deffn {Interface Driver} {at91rm9200}
2397 Supports bitbanged JTAG from the local system,
2398 presuming that system is an Atmel AT91rm9200
2399 and a specific set of GPIOs is used.
2400 @c command: at91rm9200_device NAME
2401 @c chooses among list of bit configs ... only one option
2402 @end deffn
2404 @deffn {Interface Driver} {cmsis-dap}
2405 ARM CMSIS-DAP compliant based adapter.
2407 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2408 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2409 the driver will attempt to auto detect the CMSIS-DAP device.
2410 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2411 @example
2412 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2413 @end example
2414 @end deffn
2416 @deffn {Config Command} {cmsis_dap_serial} [serial]
2417 Specifies the @var{serial} of the CMSIS-DAP device to use.
2418 If not specified, serial numbers are not considered.
2419 @end deffn
2421 @deffn {Command} {cmsis-dap info}
2422 Display various device information, like hardware version, firmware version, current bus status.
2423 @end deffn
2424 @end deffn
2426 @deffn {Interface Driver} {dummy}
2427 A dummy software-only driver for debugging.
2428 @end deffn
2430 @deffn {Interface Driver} {ep93xx}
2431 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2432 @end deffn
2434 @deffn {Interface Driver} {ftdi}
2435 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2436 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2438 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2439 bypassing intermediate libraries like libftdi or D2XX.
2441 Support for new FTDI based adapters can be added completely through
2442 configuration files, without the need to patch and rebuild OpenOCD.
2444 The driver uses a signal abstraction to enable Tcl configuration files to
2445 define outputs for one or several FTDI GPIO. These outputs can then be
2446 controlled using the @command{ftdi_set_signal} command. Special signal names
2447 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2448 will be used for their customary purpose. Inputs can be read using the
2449 @command{ftdi_get_signal} command.
2451 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2452 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2453 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2454 required by the protocol, to tell the adapter to drive the data output onto
2455 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2457 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2458 be controlled differently. In order to support tristateable signals such as
2459 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2460 signal. The following output buffer configurations are supported:
2462 @itemize @minus
2463 @item Push-pull with one FTDI output as (non-)inverted data line
2464 @item Open drain with one FTDI output as (non-)inverted output-enable
2465 @item Tristate with one FTDI output as (non-)inverted data line and another
2466 FTDI output as (non-)inverted output-enable
2467 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2468 switching data and direction as necessary
2469 @end itemize
2471 These interfaces have several commands, used to configure the driver
2472 before initializing the JTAG scan chain:
2474 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2475 The vendor ID and product ID of the adapter. Up to eight
2476 [@var{vid}, @var{pid}] pairs may be given, e.g.
2477 @example
2478 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2479 @end example
2480 @end deffn
2482 @deffn {Config Command} {ftdi_device_desc} description
2483 Provides the USB device description (the @emph{iProduct string})
2484 of the adapter. If not specified, the device description is ignored
2485 during device selection.
2486 @end deffn
2488 @deffn {Config Command} {ftdi_serial} serial-number
2489 Specifies the @var{serial-number} of the adapter to use,
2490 in case the vendor provides unique IDs and more than one adapter
2491 is connected to the host.
2492 If not specified, serial numbers are not considered.
2493 (Note that USB serial numbers can be arbitrary Unicode strings,
2494 and are not restricted to containing only decimal digits.)
2495 @end deffn
2497 @deffn {Config Command} {ftdi_location} <bus>:<port>[,<port>]...
2498 Specifies the physical USB port of the adapter to use. The path
2499 roots at @var{bus} and walks down the physical ports, with each
2500 @var{port} option specifying a deeper level in the bus topology, the last
2501 @var{port} denoting where the target adapter is actually plugged.
2502 The USB bus topology can be queried with the command @emph{lsusb -t}.
2504 This command is only available if your libusb1 is at least version 1.0.16.
2505 @end deffn
2507 @deffn {Config Command} {ftdi_channel} channel
2508 Selects the channel of the FTDI device to use for MPSSE operations. Most
2509 adapters use the default, channel 0, but there are exceptions.
2510 @end deffn
2512 @deffn {Config Command} {ftdi_layout_init} data direction
2513 Specifies the initial values of the FTDI GPIO data and direction registers.
2514 Each value is a 16-bit number corresponding to the concatenation of the high
2515 and low FTDI GPIO registers. The values should be selected based on the
2516 schematics of the adapter, such that all signals are set to safe levels with
2517 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2518 and initially asserted reset signals.
2519 @end deffn
2521 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2522 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2523 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2524 register bitmasks to tell the driver the connection and type of the output
2525 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2526 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2527 used with inverting data inputs and @option{-data} with non-inverting inputs.
2528 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2529 not-output-enable) input to the output buffer is connected. The options
2530 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2531 with the method @command{ftdi_get_signal}.
2533 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2534 simple open-collector transistor driver would be specified with @option{-oe}
2535 only. In that case the signal can only be set to drive low or to Hi-Z and the
2536 driver will complain if the signal is set to drive high. Which means that if
2537 it's a reset signal, @command{reset_config} must be specified as
2538 @option{srst_open_drain}, not @option{srst_push_pull}.
2540 A special case is provided when @option{-data} and @option{-oe} is set to the
2541 same bitmask. Then the FTDI pin is considered being connected straight to the
2542 target without any buffer. The FTDI pin is then switched between output and
2543 input as necessary to provide the full set of low, high and Hi-Z
2544 characteristics. In all other cases, the pins specified in a signal definition
2545 are always driven by the FTDI.
2547 If @option{-alias} or @option{-nalias} is used, the signal is created
2548 identical (or with data inverted) to an already specified signal
2549 @var{name}.
2550 @end deffn
2552 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2553 Set a previously defined signal to the specified level.
2554 @itemize @minus
2555 @item @option{0}, drive low
2556 @item @option{1}, drive high
2557 @item @option{z}, set to high-impedance
2558 @end itemize
2559 @end deffn
2561 @deffn {Command} {ftdi_get_signal} name
2562 Get the value of a previously defined signal.
2563 @end deffn
2565 @deffn {Command} {ftdi_tdo_sample_edge} @option{rising}|@option{falling}
2566 Configure TCK edge at which the adapter samples the value of the TDO signal
2568 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2569 peculiar at high JTAG clock speeds. However, FTDI chips offer a possibility to sample
2570 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2571 stability at higher JTAG clocks.
2572 @itemize @minus
2573 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2574 @item @option{falling}, sample TDO on falling edge of TCK
2575 @end itemize
2576 @end deffn
2578 For example adapter definitions, see the configuration files shipped in the
2579 @file{interface/ftdi} directory.
2581 @end deffn
2583 @deffn {Interface Driver} {ft232r}
2584 This driver is implementing synchronous bitbang mode of an FTDI FT232R,
2585 FT230X, FT231X and similar USB UART bridge ICs by reusing RS232 signals as GPIO.
2586 It currently doesn't support using CBUS pins as GPIO.
2588 List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
2589 @itemize @minus
2590 @item RXD(5) - TDI
2591 @item TXD(1) - TCK
2592 @item RTS(3) - TDO
2593 @item CTS(11) - TMS
2594 @item DTR(2) - TRST
2595 @item DCD(10) - SRST
2596 @end itemize
2598 User can change default pinout by supplying configuration
2599 commands with GPIO numbers or RS232 signal names.
2600 GPIO numbers correspond to bit numbers in FTDI GPIO register.
2601 They differ from physical pin numbers.
2602 For details see actual FTDI chip datasheets.
2603 Every JTAG line must be configured to unique GPIO number
2604 different than any other JTAG line, even those lines
2605 that are sometimes not used like TRST or SRST.
2607 FT232R
2608 @itemize @minus
2609 @item bit 7 - RI
2610 @item bit 6 - DCD
2611 @item bit 5 - DSR
2612 @item bit 4 - DTR
2613 @item bit 3 - CTS
2614 @item bit 2 - RTS
2615 @item bit 1 - RXD
2616 @item bit 0 - TXD
2617 @end itemize
2619 These interfaces have several commands, used to configure the driver
2620 before initializing the JTAG scan chain:
2622 @deffn {Config Command} {ft232r_vid_pid} @var{vid} @var{pid}
2623 The vendor ID and product ID of the adapter. If not specified, default
2624 0x0403:0x6001 is used.
2625 @end deffn
2627 @deffn {Config Command} {ft232r_serial_desc} @var{serial}
2628 Specifies the @var{serial} of the adapter to use, in case the
2629 vendor provides unique IDs and more than one adapter is connected to
2630 the host. If not specified, serial numbers are not considered.
2631 @end deffn
2633 @deffn {Config Command} {ft232r_jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
2634 Set four JTAG GPIO numbers at once.
2635 If not specified, default 0 3 1 2 or TXD CTS RXD RTS is used.
2636 @end deffn
2638 @deffn {Config Command} {ft232r_tck_num} @var{tck}
2639 Set TCK GPIO number. If not specified, default 0 or TXD is used.
2640 @end deffn
2642 @deffn {Config Command} {ft232r_tms_num} @var{tms}
2643 Set TMS GPIO number. If not specified, default 3 or CTS is used.
2644 @end deffn
2646 @deffn {Config Command} {ft232r_tdi_num} @var{tdi}
2647 Set TDI GPIO number. If not specified, default 1 or RXD is used.
2648 @end deffn
2650 @deffn {Config Command} {ft232r_tdo_num} @var{tdo}
2651 Set TDO GPIO number. If not specified, default 2 or RTS is used.
2652 @end deffn
2654 @deffn {Config Command} {ft232r_trst_num} @var{trst}
2655 Set TRST GPIO number. If not specified, default 4 or DTR is used.
2656 @end deffn
2658 @deffn {Config Command} {ft232r_srst_num} @var{srst}
2659 Set SRST GPIO number. If not specified, default 6 or DCD is used.
2660 @end deffn
2662 @deffn {Config Command} {ft232r_restore_serial} @var{word}
2663 Restore serial port after JTAG. This USB bitmode control word
2664 (16-bit) will be sent before quit. Lower byte should
2665 set GPIO direction register to a "sane" state:
2666 0x15 for TXD RTS DTR as outputs (1), others as inputs (0). Higher
2667 byte is usually 0 to disable bitbang mode.
2668 When kernel driver reattaches, serial port should continue to work.
2669 Value 0xFFFF disables sending control word and serial port,
2670 then kernel driver will not reattach.
2671 If not specified, default 0xFFFF is used.
2672 @end deffn
2674 @end deffn
2676 @deffn {Interface Driver} {remote_bitbang}
2677 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2678 with a remote process and sends ASCII encoded bitbang requests to that process
2679 instead of directly driving JTAG.
2681 The remote_bitbang driver is useful for debugging software running on
2682 processors which are being simulated.
2684 @deffn {Config Command} {remote_bitbang_port} number
2685 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2686 sockets instead of TCP.
2687 @end deffn
2689 @deffn {Config Command} {remote_bitbang_host} hostname
2690 Specifies the hostname of the remote process to connect to using TCP, or the
2691 name of the UNIX socket to use if remote_bitbang_port is 0.
2692 @end deffn
2694 For example, to connect remotely via TCP to the host foobar you might have
2695 something like:
2697 @example
2698 interface remote_bitbang
2699 remote_bitbang_port 3335
2700 remote_bitbang_host foobar
2701 @end example
2703 To connect to another process running locally via UNIX sockets with socket
2704 named mysocket:
2706 @example
2707 interface remote_bitbang
2708 remote_bitbang_port 0
2709 remote_bitbang_host mysocket
2710 @end example
2711 @end deffn
2713 @deffn {Interface Driver} {usb_blaster}
2714 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2715 for FTDI chips. These interfaces have several commands, used to
2716 configure the driver before initializing the JTAG scan chain:
2718 @deffn {Config Command} {usb_blaster_device_desc} description
2719 Provides the USB device description (the @emph{iProduct string})
2720 of the FTDI FT245 device. If not
2721 specified, the FTDI default value is used. This setting is only valid
2722 if compiled with FTD2XX support.
2723 @end deffn
2725 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2726 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2727 default values are used.
2728 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2729 Altera USB-Blaster (default):
2730 @example
2731 usb_blaster_vid_pid 0x09FB 0x6001
2732 @end example
2733 The following VID/PID is for Kolja Waschk's USB JTAG:
2734 @example
2735 usb_blaster_vid_pid 0x16C0 0x06AD
2736 @end example
2737 @end deffn
2739 @deffn {Command} {usb_blaster_pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2740 Sets the state or function of the unused GPIO pins on USB-Blasters
2741 (pins 6 and 8 on the female JTAG header). These pins can be used as
2742 SRST and/or TRST provided the appropriate connections are made on the
2743 target board.
2745 For example, to use pin 6 as SRST:
2746 @example
2747 usb_blaster_pin pin6 s
2748 reset_config srst_only
2749 @end example
2750 @end deffn
2752 @deffn {Command} {usb_blaster_lowlevel_driver} (@option{ftdi}|@option{ublast2})
2753 Chooses the low level access method for the adapter. If not specified,
2754 @option{ftdi} is selected unless it wasn't enabled during the
2755 configure stage. USB-Blaster II needs @option{ublast2}.
2756 @end deffn
2758 @deffn {Command} {usb_blaster_firmware} @var{path}
2759 This command specifies @var{path} to access USB-Blaster II firmware
2760 image. To be used with USB-Blaster II only.
2761 @end deffn
2763 @end deffn
2765 @deffn {Interface Driver} {gw16012}
2766 Gateworks GW16012 JTAG programmer.
2767 This has one driver-specific command:
2769 @deffn {Config Command} {parport_port} [port_number]
2770 Display either the address of the I/O port
2771 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2772 If a parameter is provided, first switch to use that port.
2773 This is a write-once setting.
2774 @end deffn
2775 @end deffn
2777 @deffn {Interface Driver} {jlink}
2778 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2779 transports.
2781 @quotation Compatibility Note
2782 SEGGER released many firmware versions for the many hardware versions they
2783 produced. OpenOCD was extensively tested and intended to run on all of them,
2784 but some combinations were reported as incompatible. As a general
2785 recommendation, it is advisable to use the latest firmware version
2786 available for each hardware version. However the current V8 is a moving
2787 target, and SEGGER firmware versions released after the OpenOCD was
2788 released may not be compatible. In such cases it is recommended to
2789 revert to the last known functional version. For 0.5.0, this is from
2790 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2791 version is from "May 3 2012 18:36:22", packed with 4.46f.
2792 @end quotation
2794 @deffn {Command} {jlink hwstatus}
2795 Display various hardware related information, for example target voltage and pin
2796 states.
2797 @end deffn
2798 @deffn {Command} {jlink freemem}
2799 Display free device internal memory.
2800 @end deffn
2801 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2802 Set the JTAG command version to be used. Without argument, show the actual JTAG
2803 command version.
2804 @end deffn
2805 @deffn {Command} {jlink config}
2806 Display the device configuration.
2807 @end deffn
2808 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2809 Set the target power state on JTAG-pin 19. Without argument, show the target
2810 power state.
2811 @end deffn
2812 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2813 Set the MAC address of the device. Without argument, show the MAC address.
2814 @end deffn
2815 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2816 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2817 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2818 IP configuration.
2819 @end deffn
2820 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2821 Set the USB address of the device. This will also change the USB Product ID
2822 (PID) of the device. Without argument, show the USB address.
2823 @end deffn
2824 @deffn {Command} {jlink config reset}
2825 Reset the current configuration.
2826 @end deffn
2827 @deffn {Command} {jlink config write}
2828 Write the current configuration to the internal persistent storage.
2829 @end deffn
2830 @deffn {Command} {jlink emucom write <channel> <data>}
2831 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2832 pairs.
2834 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2835 the EMUCOM channel 0x10:
2836 @example
2837 > jlink emucom write 0x10 aa0b23
2838 @end example
2839 @end deffn
2840 @deffn {Command} {jlink emucom read <channel> <length>}
2841 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2842 pairs.
2844 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2845 @example
2846 > jlink emucom read 0x0 4
2847 77a90000
2848 @end example
2849 @end deffn
2850 @deffn {Config} {jlink usb} <@option{0} to @option{3}>
2851 Set the USB address of the interface, in case more than one adapter is connected
2852 to the host. If not specified, USB addresses are not considered. Device
2853 selection via USB address is deprecated and the serial number should be used
2854 instead.
2856 As a configuration command, it can be used only before 'init'.
2857 @end deffn
2858 @deffn {Config} {jlink serial} <serial number>
2859 Set the serial number of the interface, in case more than one adapter is
2860 connected to the host. If not specified, serial numbers are not considered.
2862 As a configuration command, it can be used only before 'init'.
2863 @end deffn
2864 @end deffn
2866 @deffn {Interface Driver} {kitprog}
2867 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2868 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2869 families, but it is possible to use it with some other devices. If you are using
2870 this adapter with a PSoC or a PRoC, you may need to add
2871 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2872 configuration script.
2874 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2875 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2876 be used with this driver, and must either be used with the cmsis-dap driver or
2877 switched back to KitProg mode. See the Cypress KitProg User Guide for
2878 instructions on how to switch KitProg modes.
2880 Known limitations:
2881 @itemize @bullet
2882 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2883 and 2.7 MHz.
2884 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2885 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2886 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2887 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2888 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2889 SWD sequence must be sent after every target reset in order to re-establish
2890 communications with the target.
2891 @item Due in part to the limitation above, KitProg devices with firmware below
2892 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
2893 communicate with PSoC 5LP devices. This is because, assuming debug is not
2894 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
2895 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
2896 could only be sent with an acquisition sequence.
2897 @end itemize
2899 @deffn {Config Command} {kitprog_init_acquire_psoc}
2900 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
2901 Please be aware that the acquisition sequence hard-resets the target.
2902 @end deffn
2904 @deffn {Config Command} {kitprog_serial} serial
2905 Select a KitProg device by its @var{serial}. If left unspecified, the first
2906 device detected by OpenOCD will be used.
2907 @end deffn
2909 @deffn {Command} {kitprog acquire_psoc}
2910 Run a PSoC acquisition sequence immediately. Typically, this should not be used
2911 outside of the target-specific configuration scripts since it hard-resets the
2912 target as a side-effect.
2913 This is necessary for "reset halt" on some PSoC 4 series devices.
2914 @end deffn
2916 @deffn {Command} {kitprog info}
2917 Display various adapter information, such as the hardware version, firmware
2918 version, and target voltage.
2919 @end deffn
2920 @end deffn
2922 @deffn {Interface Driver} {parport}
2923 Supports PC parallel port bit-banging cables:
2924 Wigglers, PLD download cable, and more.
2925 These interfaces have several commands, used to configure the driver
2926 before initializing the JTAG scan chain:
2928 @deffn {Config Command} {parport_cable} name
2929 Set the layout of the parallel port cable used to connect to the target.
2930 This is a write-once setting.
2931 Currently valid cable @var{name} values include:
2933 @itemize @minus
2934 @item @b{altium} Altium Universal JTAG cable.
2935 @item @b{arm-jtag} Same as original wiggler except SRST and
2936 TRST connections reversed and TRST is also inverted.
2937 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2938 in configuration mode. This is only used to
2939 program the Chameleon itself, not a connected target.
2940 @item @b{dlc5} The Xilinx Parallel cable III.
2941 @item @b{flashlink} The ST Parallel cable.
2942 @item @b{lattice} Lattice ispDOWNLOAD Cable
2943 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2944 some versions of
2945 Amontec's Chameleon Programmer. The new version available from
2946 the website uses the original Wiggler layout ('@var{wiggler}')
2947 @item @b{triton} The parallel port adapter found on the
2948 ``Karo Triton 1 Development Board''.
2949 This is also the layout used by the HollyGates design
2950 (see @uref{}).
2951 @item @b{wiggler} The original Wiggler layout, also supported by
2952 several clones, such as the Olimex ARM-JTAG
2953 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2954 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2955 @end itemize
2956 @end deffn
2958 @deffn {Config Command} {parport_port} [port_number]
2959 Display either the address of the I/O port
2960 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2961 If a parameter is provided, first switch to use that port.
2962 This is a write-once setting.
2964 When using PPDEV to access the parallel port, use the number of the parallel port:
2965 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2966 you may encounter a problem.
2967 @end deffn
2969 @deffn Command {parport_toggling_time} [nanoseconds]
2970 Displays how many nanoseconds the hardware needs to toggle TCK;
2971 the parport driver uses this value to obey the
2972 @command{adapter_khz} configuration.
2973 When the optional @var{nanoseconds} parameter is given,
2974 that setting is changed before displaying the current value.
2976 The default setting should work reasonably well on commodity PC hardware.
2977 However, you may want to calibrate for your specific hardware.
2978 @quotation Tip
2979 To measure the toggling time with a logic analyzer or a digital storage
2980 oscilloscope, follow the procedure below:
2981 @example
2982 > parport_toggling_time 1000
2983 > adapter_khz 500
2984 @end example
2985 This sets the maximum JTAG clock speed of the hardware, but
2986 the actual speed probably deviates from the requested 500 kHz.
2987 Now, measure the time between the two closest spaced TCK transitions.
2988 You can use @command{runtest 1000} or something similar to generate a
2989 large set of samples.
2990 Update the setting to match your measurement:
2991 @example
2992 > parport_toggling_time <measured nanoseconds>
2993 @end example
2994 Now the clock speed will be a better match for @command{adapter_khz rate}
2995 commands given in OpenOCD scripts and event handlers.
2997 You can do something similar with many digital multimeters, but note
2998 that you'll probably need to run the clock continuously for several
2999 seconds before it decides what clock rate to show. Adjust the
3000 toggling time up or down until the measured clock rate is a good
3001 match for the adapter_khz rate you specified; be conservative.
3002 @end quotation
3003 @end deffn
3005 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
3006 This will configure the parallel driver to write a known
3007 cable-specific value to the parallel interface on exiting OpenOCD.
3008 @end deffn
3010 For example, the interface configuration file for a
3011 classic ``Wiggler'' cable on LPT2 might look something like this:
3013 @example
3014 interface parport
3015 parport_port 0x278
3016 parport_cable wiggler
3017 @end example
3018 @end deffn
3020 @deffn {Interface Driver} {presto}
3021 ASIX PRESTO USB JTAG programmer.
3022 @deffn {Config Command} {presto_serial} serial_string
3023 Configures the USB serial number of the Presto device to use.
3024 @end deffn
3025 @end deffn
3027 @deffn {Interface Driver} {rlink}
3028 Raisonance RLink USB adapter
3029 @end deffn
3031 @deffn {Interface Driver} {usbprog}
3032 usbprog is a freely programmable USB adapter.
3033 @end deffn
3035 @deffn {Interface Driver} {vsllink}
3036 vsllink is part of Versaloon which is a versatile USB programmer.
3038 @quotation Note
3039 This defines quite a few driver-specific commands,
3040 which are not currently documented here.
3041 @end quotation
3042 @end deffn
3044 @anchor{hla_interface}
3045 @deffn {Interface Driver} {hla}
3046 This is a driver that supports multiple High Level Adapters.
3047 This type of adapter does not expose some of the lower level api's
3048 that OpenOCD would normally use to access the target.
3050 Currently supported adapters include the STMicroelectronics ST-LINK and TI ICDI.
3051 ST-LINK firmware version >= V2.J21.S4 recommended due to issues with earlier
3052 versions of firmware where serial number is reset after first use. Suggest
3053 using ST firmware update utility to upgrade ST-LINK firmware even if current
3054 version reported is V2.J21.S4.
3056 @deffn {Config Command} {hla_device_desc} description
3057 Currently Not Supported.
3058 @end deffn
3060 @deffn {Config Command} {hla_serial} serial
3061 Specifies the serial number of the adapter.
3062 @end deffn
3064 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
3065 Specifies the adapter layout to use.
3066 @end deffn
3068 @deffn {Config Command} {hla_vid_pid} [vid pid]+
3069 Pairs of vendor IDs and product IDs of the device.
3070 @end deffn
3072 @deffn {Command} {hla_command} command
3073 Execute a custom adapter-specific command. The @var{command} string is
3074 passed as is to the underlying adapter layout handler.
3075 @end deffn
3076 @end deffn
3078 @deffn {Interface Driver} {opendous}
3079 opendous-jtag is a freely programmable USB adapter.
3080 @end deffn
3082 @deffn {Interface Driver} {ulink}
3083 This is the Keil ULINK v1 JTAG debugger.
3084 @end deffn
3086 @deffn {Interface Driver} {ZY1000}
3087 This is the Zylin ZY1000 JTAG debugger.
3088 @end deffn
3090 @quotation Note
3091 This defines some driver-specific commands,
3092 which are not currently documented here.
3093 @end quotation
3095 @deffn Command power [@option{on}|@option{off}]
3096 Turn power switch to target on/off.
3097 No arguments: print status.
3098 @end deffn
3100 @deffn {Interface Driver} {bcm2835gpio}
3101 This SoC is present in Raspberry Pi which is a cheap single-board computer
3102 exposing some GPIOs on its expansion header.
3104 The driver accesses memory-mapped GPIO peripheral registers directly
3105 for maximum performance, but the only possible race condition is for
3106 the pins' modes/muxing (which is highly unlikely), so it should be
3107 able to coexist nicely with both sysfs bitbanging and various
3108 peripherals' kernel drivers. The driver restores the previous
3109 configuration on exit.
3111 See @file{interface/raspberrypi-native.cfg} for a sample config and
3112 pinout.
3114 @end deffn
3116 @deffn {Interface Driver} {imx_gpio}
3117 i.MX SoC is present in many community boards. Wandboard is an example
3118 of the one which is most popular.
3120 This driver is mostly the same as bcm2835gpio.
3122 See @file{interface/imx-native.cfg} for a sample config and
3123 pinout.
3125 @end deffn
3128 @deffn {Interface Driver} {openjtag}
3129 OpenJTAG compatible USB adapter.
3130 This defines some driver-specific commands:
3132 @deffn {Config Command} {openjtag_variant} variant
3133 Specifies the variant of the OpenJTAG adapter (see @uref{}).
3134 Currently valid @var{variant} values include:
3136 @itemize @minus
3137 @item @b{standard} Standard variant (default).
3138 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3139 (see @uref{}).
3140 @end itemize
3141 @end deffn
3143 @deffn {Config Command} {openjtag_device_desc} string
3144 The USB device description string of the adapter.
3145 This value is only used with the standard variant.
3146 @end deffn
3147 @end deffn
3149 @section Transport Configuration
3150 @cindex Transport
3151 As noted earlier, depending on the version of OpenOCD you use,
3152 and the debug adapter you are using,
3153 several transports may be available to
3154 communicate with debug targets (or perhaps to program flash memory).
3155 @deffn Command {transport list}
3156 displays the names of the transports supported by this
3157 version of OpenOCD.
3158 @end deffn
3160 @deffn Command {transport select} @option{transport_name}
3161 Select which of the supported transports to use in this OpenOCD session.
3163 When invoked with @option{transport_name}, attempts to select the named
3164 transport. The transport must be supported by the debug adapter
3165 hardware and by the version of OpenOCD you are using (including the
3166 adapter's driver).
3168 If no transport has been selected and no @option{transport_name} is
3169 provided, @command{transport select} auto-selects the first transport
3170 supported by the debug adapter.
3172 @command{transport select} always returns the name of the session's selected
3173 transport, if any.
3174 @end deffn
3176 @subsection JTAG Transport
3177 @cindex JTAG
3178 JTAG is the original transport supported by OpenOCD, and most
3179 of the OpenOCD commands support it.
3180 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3181 each of which must be explicitly declared.
3182 JTAG supports both debugging and boundary scan testing.
3183 Flash programming support is built on top of debug support.
3185 JTAG transport is selected with the command @command{transport select
3186 jtag}. Unless your adapter uses @ref{hla_interface,the hla interface
3187 driver}, in which case the command is @command{transport select
3188 hla_jtag}.
3190 @subsection SWD Transport
3191 @cindex SWD
3192 @cindex Serial Wire Debug
3193 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3194 Debug Access Point (DAP, which must be explicitly declared.
3195 (SWD uses fewer signal wires than JTAG.)
3196 SWD is debug-oriented, and does not support boundary scan testing.
3197 Flash programming support is built on top of debug support.
3198 (Some processors support both JTAG and SWD.)
3200 SWD transport is selected with the command @command{transport select
3201 swd}. Unless your adapter uses @ref{hla_interface,the hla interface
3202 driver}, in which case the command is @command{transport select
3203 hla_swd}.
3205 @deffn Command {swd newdap} ...
3206 Declares a single DAP which uses SWD transport.
3207 Parameters are currently the same as "jtag newtap" but this is
3208 expected to change.
3209 @end deffn
3210 @deffn Command {swd wcr trn prescale}
3211 Updates TRN (turnaround delay) and prescaling.fields of the
3212 Wire Control Register (WCR).
3213 No parameters: displays current settings.
3214 @end deffn
3216 @subsection SPI Transport
3217 @cindex SPI
3218 @cindex Serial Peripheral Interface
3219 The Serial Peripheral Interface (SPI) is a general purpose transport
3220 which uses four wire signaling. Some processors use it as part of a
3221 solution for flash programming.
3223 @anchor{jtagspeed}
3224 @section JTAG Speed
3225 JTAG clock setup is part of system setup.
3226 It @emph{does not belong with interface setup} since any interface
3227 only knows a few of the constraints for the JTAG clock speed.
3228 Sometimes the JTAG speed is
3229 changed during the target initialization process: (1) slow at
3230 reset, (2) program the CPU clocks, (3) run fast.
3231 Both the "slow" and "fast" clock rates are functions of the
3232 oscillators used, the chip, the board design, and sometimes
3233 power management software that may be active.
3235 The speed used during reset, and the scan chain verification which
3236 follows reset, can be adjusted using a @code{reset-start}
3237 target event handler.
3238 It can then be reconfigured to a faster speed by a
3239 @code{reset-init} target event handler after it reprograms those
3240 CPU clocks, or manually (if something else, such as a boot loader,
3241 sets up those clocks).
3242 @xref{targetevents,,Target Events}.
3243 When the initial low JTAG speed is a chip characteristic, perhaps
3244 because of a required oscillator speed, provide such a handler
3245 in the target config file.
3246 When that speed is a function of a board-specific characteristic
3247 such as which speed oscillator is used, it belongs in the board
3248 config file instead.
3249 In both cases it's safest to also set the initial JTAG clock rate
3250 to that same slow speed, so that OpenOCD never starts up using a
3251 clock speed that's faster than the scan chain can support.
3253 @example
3254 jtag_rclk 3000
3255 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3256 @end example
3258 If your system supports adaptive clocking (RTCK), configuring
3259 JTAG to use that is probably the most robust approach.
3260 However, it introduces delays to synchronize clocks; so it
3261 may not be the fastest solution.
3263 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3264 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3265 which support adaptive clocking.
3267 @deffn {Command} adapter_khz max_speed_kHz
3268 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3269 JTAG interfaces usually support a limited number of
3270 speeds. The speed actually used won't be faster
3271 than the speed specified.
3273 Chip data sheets generally include a top JTAG clock rate.
3274 The actual rate is often a function of a CPU core clock,
3275 and is normally less than that peak rate.
3276 For example, most ARM cores accept at most one sixth of the CPU clock.
3278 Speed 0 (khz) selects RTCK method.
3279 @xref{faqrtck,,FAQ RTCK}.
3280 If your system uses RTCK, you won't need to change the
3281 JTAG clocking after setup.
3282 Not all interfaces, boards, or targets support ``rtck''.
3283 If the interface device can not
3284 support it, an error is returned when you try to use RTCK.
3285 @end deffn
3287 @defun jtag_rclk fallback_speed_kHz
3288 @cindex adaptive clocking
3289 @cindex RTCK
3290 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3291 If that fails (maybe the interface, board, or target doesn't
3292 support it), falls back to the specified frequency.
3293 @example
3294 # Fall back to 3mhz if RTCK is not supported
3295 jtag_rclk 3000
3296 @end example
3297 @end defun
3299 @node Reset Configuration
3300 @chapter Reset Configuration
3301 @cindex Reset Configuration
3303 Every system configuration may require a different reset
3304 configuration. This can also be quite confusing.
3305 Resets also interact with @var{reset-init} event handlers,
3306 which do things like setting up clocks and DRAM, and
3307 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3308 They can also interact with JTAG routers.
3309 Please see the various board files for examples.
3311 @quotation Note
3312 To maintainers and integrators:
3313 Reset configuration touches several things at once.
3314 Normally the board configuration file
3315 should define it and assume that the JTAG adapter supports
3316 everything that's wired up to the board's JTAG connector.
3318 However, the target configuration file could also make note
3319 of something the silicon vendor has done inside the chip,
3320 which will be true for most (or all) boards using that chip.
3321 And when the JTAG adapter doesn't support everything, the
3322 user configuration file will need to override parts of
3323 the reset configuration provided by other files.
3324 @end quotation
3326 @section Types of Reset
3328 There are many kinds of reset possible through JTAG, but
3329 they may not all work with a given board and adapter.
3330 That's part of why reset configuration can be error prone.
3332 @itemize @bullet
3333 @item
3334 @emph{System Reset} ... the @emph{SRST} hardware signal
3335 resets all chips connected to the JTAG adapter, such as processors,
3336 power management chips, and I/O controllers. Normally resets triggered
3337 with this signal behave exactly like pressing a RESET button.
3338 @item
3339 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3340 just the TAP controllers connected to the JTAG adapter.
3341 Such resets should not be visible to the rest of the system; resetting a
3342 device's TAP controller just puts that controller into a known state.
3343 @item
3344 @emph{Emulation Reset} ... many devices can be reset through JTAG
3345 commands. These resets are often distinguishable from system
3346 resets, either explicitly (a "reset reason" register says so)
3347 or implicitly (not all parts of the chip get reset).
3348 @item
3349 @emph{Other Resets} ... system-on-chip devices often support
3350 several other types of reset.
3351 You may need to arrange that a watchdog timer stops
3352 while debugging, preventing a watchdog reset.
3353 There may be individual module resets.
3354 @end itemize
3356 In the best case, OpenOCD can hold SRST, then reset
3357 the TAPs via TRST and send commands through JTAG to halt the
3358 CPU at the reset vector before the 1st instruction is executed.
3359 Then when it finally releases the SRST signal, the system is
3360 halted under debugger control before any code has executed.
3361 This is the behavior required to support the @command{reset halt}
3362 and @command{reset init} commands; after @command{reset init} a
3363 board-specific script might do things like setting up DRAM.
3364 (@xref{resetcommand,,Reset Command}.)
3366 @anchor{srstandtrstissues}
3367 @section SRST and TRST Issues
3369 Because SRST and TRST are hardware signals, they can have a
3370 variety of system-specific constraints. Some of the most
3371 common issues are:
3373 @itemize @bullet
3375 @item @emph{Signal not available} ... Some boards don't wire
3376 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3377 support such signals even if they are wired up.
3378 Use the @command{reset_config} @var{signals} options to say
3379 when either of those signals is not connected.
3380 When SRST is not available, your code might not be able to rely
3381 on controllers having been fully reset during code startup.
3382 Missing TRST is not a problem, since JTAG-level resets can
3383 be triggered using with TMS signaling.
3385 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3386 adapter will connect SRST to TRST, instead of keeping them separate.
3387 Use the @command{reset_config} @var{combination} options to say
3388 when those signals aren't properly independent.
3390 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3391 delay circuit, reset supervisor, or on-chip features can extend
3392 the effect of a JTAG adapter's reset for some time after the adapter
3393 stops issuing the reset. For example, there may be chip or board
3394 requirements that all reset pulses last for at least a
3395 certain amount of time; and reset buttons commonly have
3396 hardware debouncing.
3397 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3398 commands to say when extra delays are needed.
3400 @item @emph{Drive type} ... Reset lines often have a pullup
3401 resistor, letting the JTAG interface treat them as open-drain
3402 signals. But that's not a requirement, so the adapter may need
3403 to use push/pull output drivers.
3404 Also, with weak pullups it may be advisable to drive
3405 signals to both levels (push/pull) to minimize rise times.
3406 Use the @command{reset_config} @var{trst_type} and
3407 @var{srst_type} parameters to say how to drive reset signals.
3409 @item @emph{Special initialization} ... Targets sometimes need
3410 special JTAG initialization sequences to handle chip-specific
3411 issues (not limited to errata).
3412 For example, certain JTAG commands might need to be issued while
3413 the system as a whole is in a reset state (SRST active)
3414 but the JTAG scan chain is usable (TRST inactive).
3415 Many systems treat combined assertion of SRST and TRST as a
3416 trigger for a harder reset than SRST alone.
3417 Such custom reset handling is discussed later in this chapter.
3418 @end itemize
3420 There can also be other issues.
3421 Some devices don't fully conform to the JTAG specifications.
3422 Trivial system-specific differences are common, such as
3423 SRST and TRST using slightly different names.
3424 There are also vendors who distribute key JTAG documentation for
3425 their chips only to developers who have signed a Non-Disclosure
3426 Agreement (NDA).
3428 Sometimes there are chip-specific extensions like a requirement to use
3429 the normally-optional TRST signal (precluding use of JTAG adapters which
3430 don't pass TRST through), or needing extra steps to complete a TAP reset.
3432 In short, SRST and especially TRST handling may be very finicky,
3433 needing to cope with both architecture and board specific constraints.
3435 @section Commands for Handling Resets
3437 @deffn {Command} adapter_nsrst_assert_width milliseconds
3438 Minimum amount of time (in milliseconds) OpenOCD should wait
3439 after asserting nSRST (active-low system reset) before
3440 allowing it to be deasserted.
3441 @end deffn
3443 @deffn {Command} adapter_nsrst_delay milliseconds
3444 How long (in milliseconds) OpenOCD should wait after deasserting
3445 nSRST (active-low system reset) before starting new JTAG operations.
3446 When a board has a reset button connected to SRST line it will
3447 probably have hardware debouncing, implying you should use this.
3448 @end deffn
3450 @deffn {Command} jtag_ntrst_assert_width milliseconds
3451 Minimum amount of time (in milliseconds) OpenOCD should wait
3452 after asserting nTRST (active-low JTAG TAP reset) before
3453 allowing it to be deasserted.
3454 @end deffn
3456 @deffn {Command} jtag_ntrst_delay milliseconds
3457 How long (in milliseconds) OpenOCD should wait after deasserting
3458 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3459 @end deffn
3461 @anchor {reset_config}
3462 @deffn {Command} reset_config mode_flag ...
3463 This command displays or modifies the reset configuration
3464 of your combination of JTAG board and target in target
3465 configuration scripts.
3467 Information earlier in this section describes the kind of problems
3468 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3469 As a rule this command belongs only in board config files,
3470 describing issues like @emph{board doesn't connect TRST};
3471 or in user config files, addressing limitations derived
3472 from a particular combination of interface and board.
3473 (An unlikely example would be using a TRST-only adapter
3474 with a board that only wires up SRST.)
3476 The @var{mode_flag} options can be specified in any order, but only one
3477 of each type -- @var{signals}, @var{combination}, @var{gates},
3478 @var{trst_type}, @var{srst_type} and @var{connect_type}
3479 -- may be specified at a time.
3480 If you don't provide a new value for a given type, its previous
3481 value (perhaps the default) is unchanged.
3482 For example, this means that you don't need to say anything at all about
3483 TRST just to declare that if the JTAG adapter should want to drive SRST,
3484 it must explicitly be driven high (@option{srst_push_pull}).
3486 @itemize
3487 @item
3488 @var{signals} can specify which of the reset signals are connected.
3489 For example, If the JTAG interface provides SRST, but the board doesn't
3490 connect that signal properly, then OpenOCD can't use it.
3491 Possible values are @option{none} (the default), @option{trst_only},
3492 @option{srst_only} and @option{trst_and_srst}.
3494 @quotation Tip
3495 If your board provides SRST and/or TRST through the JTAG connector,
3496 you must declare that so those signals can be used.
3497 @end quotation
3499 @item
3500 The @var{combination} is an optional value specifying broken reset
3501 signal implementations.
3502 The default behaviour if no option given is @option{separate},
3503 indicating everything behaves normally.
3504 @option{srst_pulls_trst} states that the
3505 test logic is reset together with the reset of the system (e.g. NXP
3506 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3507 the system is reset together with the test logic (only hypothetical, I
3508 haven't seen hardware with such a bug, and can be worked around).
3509 @option{combined} implies both @option{srst_pulls_trst} and
3510 @option{trst_pulls_srst}.
3512 @item
3513 The @var{gates} tokens control flags that describe some cases where
3514 JTAG may be unavailable during reset.
3515 @option{srst_gates_jtag} (default)
3516 indicates that asserting SRST gates the
3517 JTAG clock. This means that no communication can happen on JTAG
3518 while SRST is asserted.
3519 Its converse is @option{srst_nogate}, indicating that JTAG commands
3520 can safely be issued while SRST is active.
3522 @item
3523 The @var{connect_type} tokens control flags that describe some cases where
3524 SRST is asserted while connecting to the target. @option{srst_nogate}
3525 is required to use this option.
3526 @option{connect_deassert_srst} (default)
3527 indicates that SRST will not be asserted while connecting to the target.
3528 Its converse is @option{connect_assert_srst}, indicating that SRST will
3529 be asserted before any target connection.
3530 Only some targets support this feature, STM32 and STR9 are examples.
3531 This feature is useful if you are unable to connect to your target due
3532 to incorrect options byte config or illegal program execution.
3533 @end itemize
3535 The optional @var{trst_type} and @var{srst_type} parameters allow the
3536 driver mode of each reset line to be specified. These values only affect
3537 JTAG interfaces with support for different driver modes, like the Amontec
3538 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3539 relevant signal (TRST or SRST) is not connected.
3541 @itemize
3542 @item
3543 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3544 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3545 Most boards connect this signal to a pulldown, so the JTAG TAPs
3546 never leave reset unless they are hooked up to a JTAG adapter.
3548 @item
3549 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3550 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3551 Most boards connect this signal to a pullup, and allow the
3552 signal to be pulled low by various events including system
3553 power-up and pressing a reset button.
3554 @end itemize
3555 @end deffn
3557 @section Custom Reset Handling
3558 @cindex events
3560 OpenOCD has several ways to help support the various reset
3561 mechanisms provided by chip and board vendors.
3562 The commands shown in the previous section give standard parameters.
3563 There are also @emph{event handlers} associated with TAPs or Targets.
3564 Those handlers are Tcl procedures you can provide, which are invoked
3565 at particular points in the reset sequence.
3567 @emph{When SRST is not an option} you must set
3568 up a @code{reset-assert} event handler for your target.
3569 For example, some JTAG adapters don't include the SRST signal;
3570 and some boards have multiple targets, and you won't always
3571 want to reset everything at once.
3573 After configuring those mechanisms, you might still
3574 find your board doesn't start up or reset correctly.
3575 For example, maybe it needs a slightly different sequence
3576 of SRST and/or TRST manipulations, because of quirks that
3577 the @command{reset_config} mechanism doesn't address;
3578 or asserting both might trigger a stronger reset, which
3579 needs special attention.
3581 Experiment with lower level operations, such as @command{jtag_reset}
3582 and the @command{jtag arp_*} operations shown here,
3583 to find a sequence of operations that works.
3584 @xref{JTAG Commands}.
3585 When you find a working sequence, it can be used to override
3586 @command{jtag_init}, which fires during OpenOCD startup
3587 (@pxref{configurationstage,,Configuration Stage});
3588 or @command{init_reset}, which fires during reset processing.
3590 You might also want to provide some project-specific reset
3591 schemes. For example, on a multi-target board the standard
3592 @command{reset} command would reset all targets, but you
3593 may need the ability to reset only one target at time and
3594 thus want to avoid using the board-wide SRST signal.
3596 @deffn {Overridable Procedure} init_reset mode
3597 This is invoked near the beginning of the @command{reset} command,
3598 usually to provide as much of a cold (power-up) reset as practical.
3599 By default it is also invoked from @command{jtag_init} if
3600 the scan chain does not respond to pure JTAG operations.
3601 The @var{mode} parameter is the parameter given to the
3602 low level reset command (@option{halt},
3603 @option{init}, or @option{run}), @option{setup},
3604 or potentially some other value.
3606 The default implementation just invokes @command{jtag arp_init-reset}.
3607 Replacements will normally build on low level JTAG
3608 operations such as @command{jtag_reset}.
3609 Operations here must not address individual TAPs
3610 (or their associated targets)
3611 until the JTAG scan chain has first been verified to work.
3613 Implementations must have verified the JTAG scan chain before
3614 they return.
3615 This is done by calling @command{jtag arp_init}
3616 (or @command{jtag arp_init-reset}).
3617 @end deffn
3619 @deffn Command {jtag arp_init}
3620 This validates the scan chain using just the four
3621 standard JTAG signals (TMS, TCK, TDI, TDO).
3622 It starts by issuing a JTAG-only reset.
3623 Then it performs checks to verify that the scan chain configuration
3624 matches the TAPs it can observe.
3625 Those checks include checking IDCODE values for each active TAP,
3626 and verifying the length of their instruction registers using
3627 TAP @code{-ircapture} and @code{-irmask} values.
3628 If these tests all pass, TAP @code{setup} events are
3629 issued to all TAPs with handlers for that event.
3630 @end deffn
3632 @deffn Command {jtag arp_init-reset}
3633 This uses TRST and SRST to try resetting
3634 everything on the JTAG scan chain
3635 (and anything else connected to SRST).
3636 It then invokes the logic of @command{jtag arp_init}.
3637 @end deffn
3640 @node TAP Declaration
3641 @chapter TAP Declaration
3642 @cindex TAP declaration
3643 @cindex TAP configuration
3645 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3646 TAPs serve many roles, including:
3648 @itemize @bullet
3649 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3650 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3651 Others do it indirectly, making a CPU do it.
3652 @item @b{Program Download} Using the same CPU support GDB uses,
3653 you can initialize a DRAM controller, download code to DRAM, and then
3654 start running that code.
3655 @item @b{Boundary Scan} Most chips support boundary scan, which
3656 helps test for board assembly problems like solder bridges
3657 and missing connections.
3658 @end itemize
3660 OpenOCD must know about the active TAPs on your board(s).
3661 Setting up the TAPs is the core task of your configuration files.
3662 Once those TAPs are set up, you can pass their names to code
3663 which sets up CPUs and exports them as GDB targets,
3664 probes flash memory, performs low-level JTAG operations, and more.
3666 @section Scan Chains
3667 @cindex scan chain
3669 TAPs are part of a hardware @dfn{scan chain},
3670 which is a daisy chain of TAPs.
3671 They also need to be added to
3672 OpenOCD's software mirror of that hardware list,
3673 giving each member a name and associating other data with it.
3674 Simple scan chains, with a single TAP, are common in
3675 systems with a single microcontroller or microprocessor.
3676 More complex chips may have several TAPs internally.
3677 Very complex scan chains might have a dozen or more TAPs:
3678 several in one chip, more in the next, and connecting
3679 to other boards with their own chips and TAPs.
3681 You can display the list with the @command{scan_chain} command.
3682 (Don't confuse this with the list displayed by the @command{targets}
3683 command, presented in the next chapter.
3684 That only displays TAPs for CPUs which are configured as
3685 debugging targets.)
3686 Here's what the scan chain might look like for a chip more than one TAP:
3688 @verbatim
3689 TapName Enabled IdCode Expected IrLen IrCap IrMask
3690 -- ------------------ ------- ---------- ---------- ----- ----- ------
3691 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3692 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3693 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3694 @end verbatim
3696 OpenOCD can detect some of that information, but not all
3697 of it. @xref{autoprobing,,Autoprobing}.
3698 Unfortunately, those TAPs can't always be autoconfigured,
3699 because not all devices provide good support for that.
3700 JTAG doesn't require supporting IDCODE instructions, and
3701 chips with JTAG routers may not link TAPs into the chain
3702 until they are told to do so.
3704 The configuration mechanism currently supported by OpenOCD
3705 requires explicit configuration of all TAP devices using
3706 @command{jtag newtap} commands, as detailed later in this chapter.
3707 A command like this would declare one tap and name it @code{chip1.cpu}:
3709 @example
3710 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3711 @end example
3713 Each target configuration file lists the TAPs provided
3714 by a given chip.
3715 Board configuration files combine all the targets on a board,
3716 and so forth.
3717 Note that @emph{the order in which TAPs are declared is very important.}
3718 That declaration order must match the order in the JTAG scan chain,
3719 both inside a single chip and between them.
3720 @xref{faqtaporder,,FAQ TAP Order}.
3722 For example, the STMicroelectronics STR912 chip has
3723 three separate TAPs@footnote{See the ST
3724 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3725 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3726 @url{}}.
3727 To configure those taps, @file{target/str912.cfg}
3728 includes commands something like this:
3730 @example
3731 jtag newtap str912 flash ... params ...
3732 jtag newtap str912 cpu ... params ...
3733 jtag newtap str912 bs ... params ...
3734 @end example
3736 Actual config files typically use a variable such as @code{$_CHIPNAME}
3737 instead of literals like @option{str912}, to support more than one chip
3738 of each type. @xref{Config File Guidelines}.
3740 @deffn Command {jtag names}
3741 Returns the names of all current TAPs in the scan chain.
3742 Use @command{jtag cget} or @command{jtag tapisenabled}
3743 to examine attributes and state of each TAP.
3744 @example
3745 foreach t [jtag names] @{
3746 puts [format "TAP: %s\n" $t]
3747 @}
3748 @end example
3749 @end deffn
3751 @deffn Command {scan_chain}
3752 Displays the TAPs in the scan chain configuration,
3753 and their status.
3754 The set of TAPs listed by this command is fixed by
3755 exiting the OpenOCD configuration stage,
3756 but systems with a JTAG router can
3757 enable or disable TAPs dynamically.
3758 @end deffn
3760 @c FIXME! "jtag cget" should be able to return all TAP
3761 @c attributes, like "$target_name cget" does for targets.
3763 @c Probably want "jtag eventlist", and a "tap-reset" event
3764 @c (on entry to RESET state).
3766 @section TAP Names
3767 @cindex dotted name
3769 When TAP objects are declared with @command{jtag newtap},
3770 a @dfn{} is created for the TAP, combining the
3771 name of a module (usually a chip) and a label for the TAP.
3772 For example: @code{xilinx.tap}, @code{str912.flash},
3773 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3774 Many other commands use that to manipulate or
3775 refer to the TAP. For example, CPU configuration uses the
3776 name, as does declaration of NAND or NOR flash banks.
3778 The components of a dotted name should follow ``C'' symbol
3779 name rules: start with an alphabetic character, then numbers
3780 and underscores are OK; while others (including dots!) are not.
3782 @section TAP Declaration Commands
3784 @c shouldn't this be(come) a {Config Command}?
3785 @deffn Command {jtag newtap} chipname tapname configparams...
3786 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3787 and configured according to the various @var{configparams}.
3789 The @var{chipname} is a symbolic name for the chip.
3790 Conventionally target config files use @code{$_CHIPNAME},
3791 defaulting to the model name given by the chip vendor but
3792 overridable.
3794 @cindex TAP naming convention
3795 The @var{tapname} reflects the role of that TAP,
3796 and should follow this convention:
3798 @itemize @bullet
3799 @item @code{bs} -- For boundary scan if this is a separate TAP;
3800 @item @code{cpu} -- The main CPU of the chip, alternatively
3801 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3802 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3803 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3804 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3805 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3806 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3807 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3808 with a single TAP;
3809 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3810 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3811 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3812 a JTAG TAP; that TAP should be named @code{sdma}.
3813 @end itemize
3815 Every TAP requires at least the following @var{configparams}:
3817 @itemize @bullet
3818 @item @code{-irlen} @var{NUMBER}
3819 @*The length in bits of the
3820 instruction register, such as 4 or 5 bits.
3821 @end itemize
3823 A TAP may also provide optional @var{configparams}:
3825 @itemize @bullet
3826 @item @code{-disable} (or @code{-enable})
3827 @*Use the @code{-disable} parameter to flag a TAP which is not
3828 linked into the scan chain after a reset using either TRST
3829 or the JTAG state machine's @sc{reset} state.
3830 You may use @code{-enable} to highlight the default state
3831 (the TAP is linked in).
3832 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3833 @item @code{-expected-id} @var{NUMBER}
3834 @*A non-zero @var{number} represents a 32-bit IDCODE
3835 which you expect to find when the scan chain is examined.
3836 These codes are not required by all JTAG devices.
3837 @emph{Repeat the option} as many times as required if more than one
3838 ID code could appear (for example, multiple versions).
3839 Specify @var{number} as zero to suppress warnings about IDCODE
3840 values that were found but not included in the list.
3842 Provide this value if at all possible, since it lets OpenOCD
3843 tell when the scan chain it sees isn't right. These values
3844 are provided in vendors' chip documentation, usually a technical
3845 reference manual. Sometimes you may need to probe the JTAG
3846 hardware to find these values.
3847 @xref{autoprobing,,Autoprobing}.
3848 @item @code{-ignore-version}
3849 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3850 option. When vendors put out multiple versions of a chip, or use the same
3851 JTAG-level ID for several largely-compatible chips, it may be more practical
3852 to ignore the version field than to update config files to handle all of
3853 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3854 @item @code{-ircapture} @var{NUMBER}
3855 @*The bit pattern loaded by the TAP into the JTAG shift register
3856 on entry to the @sc{ircapture} state, such as 0x01.
3857 JTAG requires the two LSBs of this value to be 01.
3858 By default, @code{-ircapture} and @code{-irmask} are set
3859 up to verify that two-bit value. You may provide
3860 additional bits if you know them, or indicate that
3861 a TAP doesn't conform to the JTAG specification.
3862 @item @code{-irmask} @var{NUMBER}
3863 @*A mask used with @code{-ircapture}
3864 to verify that instruction scans work correctly.
3865 Such scans are not used by OpenOCD except to verify that
3866 there seems to be no problems with JTAG scan chain operations.
3867 @item @code{-ignore-syspwrupack}
3868 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
3869 register during initial examination and when checking the sticky error bit.
3870 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
3871 devices do not set the ack bit until sometime later.
3872 @end itemize
3873 @end deffn
3875 @section Other TAP commands
3877 @deffn Command {jtag cget} @option{-event} event_name
3878 @deffnx Command {jtag configure} @option{-event} event_name handler
3879 At this writing this TAP attribute
3880 mechanism is used only for event handling.
3881 (It is not a direct analogue of the @code{cget}/@code{configure}
3882 mechanism for debugger targets.)
3883 See the next section for information about the available events.
3885 The @code{configure} subcommand assigns an event handler,
3886 a TCL string which is evaluated when the event is triggered.
3887 The @code{cget} subcommand returns that handler.
3888 @end deffn
3890 @section TAP Events
3891 @cindex events
3892 @cindex TAP events
3894 OpenOCD includes two event mechanisms.
3895 The one presented here applies to all JTAG TAPs.
3896 The other applies to debugger targets,
3897 which are associated with certain TAPs.
3899 The TAP events currently defined are:
3901 @itemize @bullet
3902 @item @b{post-reset}
3903 @* The TAP has just completed a JTAG reset.
3904 The tap may still be in the JTAG @sc{reset} state.
3905 Handlers for these events might perform initialization sequences
3906 such as issuing TCK cycles, TMS sequences to ensure
3907 exit from the ARM SWD mode, and more.
3909 Because the scan chain has not yet been verified, handlers for these events
3910 @emph{should not issue commands which scan the JTAG IR or DR registers}
3911 of any particular target.
3912 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3913 @item @b{setup}
3914 @* The scan chain has been reset and verified.
3915 This handler may enable TAPs as needed.
3916 @item @b{tap-disable}
3917 @* The TAP needs to be disabled. This handler should
3918 implement @command{jtag tapdisable}
3919 by issuing the relevant JTAG commands.
3920 @item @b{tap-enable}
3921 @* The TAP needs to be enabled. This handler should
3922 implement @command{jtag tapenable}
3923 by issuing the relevant JTAG commands.
3924 @end itemize
3926 If you need some action after each JTAG reset which isn't actually
3927 specific to any TAP (since you can't yet trust the scan chain's
3928 contents to be accurate), you might:
3930 @example
3931 jtag configure CHIP.jrc -event post-reset @{
3932 echo "JTAG Reset done"
3933 ... non-scan jtag operations to be done after reset
3934 @}
3935 @end example
3938 @anchor{enablinganddisablingtaps}
3939 @section Enabling and Disabling TAPs
3940 @cindex JTAG Route Controller
3941 @cindex jrc
3943 In some systems, a @dfn{JTAG Route Controller} (JRC)
3944 is used to enable and/or disable specific JTAG TAPs.
3945 Many ARM-based chips from Texas Instruments include
3946 an ``ICEPick'' module, which is a JRC.
3947 Such chips include DaVinci and OMAP3 processors.
3949 A given TAP may not be visible until the JRC has been
3950 told to link it into the scan chain; and if the JRC
3951 has been told to unlink that TAP, it will no longer
3952 be visible.
3953 Such routers address problems that JTAG ``bypass mode''
3954 ignores, such as:
3956 @itemize
3957 @item The scan chain can only go as fast as its slowest TAP.
3958 @item Having many TAPs slows instruction scans, since all
3959 TAPs receive new instructions.
3960 @item TAPs in the scan chain must be powered up, which wastes
3961 power and prevents debugging some power management mechanisms.
3962 @end itemize
3964 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3965 as implied by the existence of JTAG routers.
3966 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3967 does include a kind of JTAG router functionality.
3969 @c (a) currently the event handlers don't seem to be able to
3970 @c fail in a way that could lead to no-change-of-state.
3972 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3973 shown below, and is implemented using TAP event handlers.
3974 So for example, when defining a TAP for a CPU connected to
3975 a JTAG router, your @file{target.cfg} file
3976 should define TAP event handlers using
3977 code that looks something like this:
3979 @example
3980 jtag configure CHIP.cpu -event tap-enable @{
3981 ... jtag operations using CHIP.jrc
3982 @}
3983 jtag configure CHIP.cpu -event tap-disable @{
3984 ... jtag operations using CHIP.jrc
3985 @}
3986 @end example
3988 Then you might want that CPU's TAP enabled almost all the time:
3990 @example
3991 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3992 @end example
3994 Note how that particular setup event handler declaration
3995 uses quotes to evaluate @code{$CHIP} when the event is configured.
3996 Using brackets @{ @} would cause it to be evaluated later,
3997 at runtime, when it might have a different value.
3999 @deffn Command {jtag tapdisable}
4000 If necessary, disables the tap
4001 by sending it a @option{tap-disable} event.
4002 Returns the string "1" if the tap
4003 specified by @var{} is enabled,
4004 and "0" if it is disabled.
4005 @end deffn
4007 @deffn Command {jtag tapenable}
4008 If necessary, enables the tap
4009 by sending it a @option{tap-enable} event.
4010 Returns the string "1" if the tap
4011 specified by @var{} is enabled,
4012 and "0" if it is disabled.
4013 @end deffn
4015 @deffn Command {jtag tapisenabled}
4016 Returns the string "1" if the tap
4017 specified by @var{} is enabled,
4018 and "0" if it is disabled.
4020 @quotation Note
4021 Humans will find the @command{scan_chain} command more helpful
4022 for querying the state of the JTAG taps.
4023 @end quotation
4024 @end deffn
4026 @anchor{autoprobing}
4027 @section Autoprobing
4028 @cindex autoprobe
4029 @cindex JTAG autoprobe
4031 TAP configuration is the first thing that needs to be done
4032 after interface and reset configuration. Sometimes it's
4033 hard finding out what TAPs exist, or how they are identified.
4034 Vendor documentation is not always easy to find and use.
4036 To help you get past such problems, OpenOCD has a limited
4037 @emph{autoprobing} ability to look at the scan chain, doing
4038 a @dfn{blind interrogation} and then reporting the TAPs it finds.
4039 To use this mechanism, start the OpenOCD server with only data
4040 that configures your JTAG interface, and arranges to come up
4041 with a slow clock (many devices don't support fast JTAG clocks
4042 right when they come out of reset).
4044 For example, your @file{openocd.cfg} file might have:
4046 @example
4047 source [find interface/olimex-arm-usb-tiny-h.cfg]
4048 reset_config trst_and_srst
4049 jtag_rclk 8
4050 @end example
4052 When you start the server without any TAPs configured, it will
4053 attempt to autoconfigure the TAPs. There are two parts to this:
4055 @enumerate
4056 @item @emph{TAP discovery} ...
4057 After a JTAG reset (sometimes a system reset may be needed too),
4058 each TAP's data registers will hold the contents of either the
4059 IDCODE or BYPASS register.
4060 If JTAG communication is working, OpenOCD will see each TAP,
4061 and report what @option{-expected-id} to use with it.
4062 @item @emph{IR Length discovery} ...
4063 Unfortunately JTAG does not provide a reliable way to find out
4064 the value of the @option{-irlen} parameter to use with a TAP
4065 that is discovered.
4066 If OpenOCD can discover the length of a TAP's instruction
4067 register, it will report it.
4068 Otherwise you may need to consult vendor documentation, such
4069 as chip data sheets or BSDL files.
4070 @end enumerate
4072 In many cases your board will have a simple scan chain with just
4073 a single device. Here's what OpenOCD reported with one board
4074 that's a bit more complex:
4076 @example
4077 clock speed 8 kHz
4078 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4079 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4080 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4081 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4082 AUTO auto0.tap - use "... -irlen 4"
4083 AUTO auto1.tap - use "... -irlen 4"
4084 AUTO auto2.tap - use "... -irlen 6"
4085 no gdb ports allocated as no target has been specified
4086 @end example
4088 Given that information, you should be able to either find some existing
4089 config files to use, or create your own. If you create your own, you
4090 would configure from the bottom up: first a @file{target.cfg} file
4091 with these TAPs, any targets associated with them, and any on-chip
4092 resources; then a @file{board.cfg} with off-chip resources, clocking,
4093 and so forth.
4095 @anchor{dapdeclaration}
4096 @section DAP declaration (ARMv6-M, ARMv7 and ARMv8 targets)
4097 @cindex DAP declaration
4099 Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is
4100 no longer implicitly created together with the target. It must be
4101 explicitly declared using the @command{dap create} command. For all ARMv6-M, ARMv7
4102 and ARMv8 targets, the option "@option{-dap} @var{dap_name}" has to be used
4103 instead of "@option{-chain-position} @var{}" when the target is created.
4105 The @command{dap} command group supports the following sub-commands:
4107 @deffn Command {dap create} dap_name @option{-chain-position} configparams...
4108 Declare a DAP instance named @var{dap_name} linked to the JTAG tap
4109 @var{}. This also creates a new command (@command{dap_name})
4110 which is used for various purposes including additional configuration.
4111 There can only be one DAP for each JTAG tap in the system.
4113 A DAP may also provide optional @var{configparams}:
4115 @itemize @bullet
4116 @item @code{-ignore-syspwrupack}
4117 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4118 register during initial examination and when checking the sticky error bit.
4119 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4120 devices do not set the ack bit until sometime later.
4121 @end itemize
4122 @end deffn
4124 @deffn Command {dap names}
4125 This command returns a list of all registered DAP objects. It it useful mainly
4126 for TCL scripting.
4127 @end deffn
4129 @deffn Command {dap info} [num]
4130 Displays the ROM table for MEM-AP @var{num},
4131 defaulting to the currently selected AP of the currently selected target.
4132 @end deffn
4134 @deffn Command {dap init}
4135 Initialize all registered DAPs. This command is used internally
4136 during initialization. It can be issued at any time after the
4137 initialization, too.
4138 @end deffn
4140 The following commands exist as subcommands of DAP instances:
4142 @deffn Command {$dap_name info} [num]
4143 Displays the ROM table for MEM-AP @var{num},
4144 defaulting to the currently selected AP.
4145 @end deffn
4147 @deffn Command {$dap_name apid} [num]
4148 Displays ID register from AP @var{num}, defaulting to the currently selected AP.
4149 @end deffn
4151 @anchor{DAP subcommand apreg}
4152 @deffn Command {$dap_name apreg} ap_num reg [value]
4153 Displays content of a register @var{reg} from AP @var{ap_num}
4154 or set a new value @var{value}.
4155 @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
4156 @end deffn
4158 @deffn Command {$dap_name apsel} [num]
4159 Select AP @var{num}, defaulting to 0.
4160 @end deffn
4162 @deffn Command {$dap_name dpreg} reg [value]
4163 Displays the content of DP register at address @var{reg}, or set it to a new
4164 value @var{value}.
4166 In case of SWD, @var{reg} is a value in packed format
4167 @math{dpbanksel << 4 | addr} and assumes values 0, 4, 8 ... 0xfc.
4168 In case of JTAG it only assumes values 0, 4, 8 and 0xc.
4170 @emph{Note:} Consider using @command{poll off} to avoid any disturbing
4171 background activity by OpenOCD while you are operating at such low-level.
4172 @end deffn
4174 @deffn Command {$dap_name baseaddr} [num]
4175 Displays debug base address from MEM-AP @var{num},
4176 defaulting to the currently selected AP.
4177 @end deffn
4179 @deffn Command {$dap_name memaccess} [value]
4180 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP