[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
82 * TFTP:: TFTP
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
95 @end menu
97 @node About
98 @unnumbered About
99 @cindex about
101 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
102 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
105 around the world.
107 @section What is OpenOCD?
108 @cindex TAP
109 @cindex JTAG
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
113 devices.
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board connect directly to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
140 scan operations.
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD supports only
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
154 USB-based, parallel port-based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
159 (Stellaris LM3, STMicroelectronics STM32 and Energy Micro EFM32) and
160 Intel Quark (x10xx) based cores to be debugged via the GDB protocol.
162 @b{Flash Programming:} Flash writing is supported for external
163 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{http://openocd.org/}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{http://openocd.org/doc/html/index.html}
182 PDF form is likewise published at:
184 @uref{http://openocd.org/doc/pdf/openocd.pdf}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
203 @section OpenOCD IRC
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
208 @node Developers
209 @chapter OpenOCD Developer Resources
210 @cindex developers
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD Git Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a Git repository hosted at SourceForge. The repository URL is:
225 @uref{git://git.code.sf.net/p/openocd/code}
227 or via http
229 @uref{http://git.code.sf.net/p/openocd/code}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{http://repo.or.cz/r/openocd.git}
235 With standard Git tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a Git client:
241 @uref{http://repo.or.cz/w/openocd.git}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{http://openocd.org/doc/doxygen/html/index.html}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration at the top of the source tree.
264 @section Gerrit Review System
266 All changes in the OpenOCD Git repository go through the web-based Gerrit
267 Code Review System:
269 @uref{http://openocd.zylin.com/}
271 After a one-time registration and repository setup, anyone can push commits
272 from their local Git repository directly into Gerrit.
273 All users and developers are encouraged to review, test, discuss and vote
274 for changes in Gerrit. The feedback provides the basis for a maintainer to
275 eventually submit the change to the main Git repository.
277 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
278 Developer Manual, contains basic information about how to connect a
279 repository to Gerrit, prepare and push patches. Patch authors are expected to
280 maintain their changes while they're in Gerrit, respond to feedback and if
281 necessary rework and push improved versions of the change.
283 @section OpenOCD Developer Mailing List
285 The OpenOCD Developer Mailing List provides the primary means of
286 communication between developers:
288 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
290 @section OpenOCD Bug Tracker
292 The OpenOCD Bug Tracker is hosted on SourceForge:
294 @uref{http://bugs.openocd.org/}
297 @node Debug Adapter Hardware
298 @chapter Debug Adapter Hardware
299 @cindex dongles
300 @cindex FTDI
301 @cindex wiggler
302 @cindex zy1000
303 @cindex printer port
304 @cindex USB Adapter
305 @cindex RTCK
307 Defined: @b{dongle}: A small device that plugs into a computer and serves as
308 an adapter .... [snip]
310 In the OpenOCD case, this generally refers to @b{a small adapter} that
311 attaches to your computer via USB or the parallel port. One
312 exception is the Ultimate Solutions ZY1000, packaged as a small box you
313 attach via an ethernet cable. The ZY1000 has the advantage that it does not
314 require any drivers to be installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built-in relay to power cycle targets remotely.
319 @section Choosing a Dongle
321 There are several things you should keep in mind when choosing a dongle.
323 @enumerate
324 @item @b{Transport} Does it support the kind of communication that you need?
325 OpenOCD focusses mostly on JTAG. Your version may also support
326 other ways to communicate with target devices.
327 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
328 Does your dongle support it? You might need a level converter.
329 @item @b{Pinout} What pinout does your target board use?
330 Does your dongle support it? You may be able to use jumper
331 wires, or an "octopus" connector, to convert pinouts.
332 @item @b{Connection} Does your computer have the USB, parallel, or
333 Ethernet port needed?
334 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
335 RTCK support (also known as ``adaptive clocking'')?
336 @end enumerate
338 @section Stand-alone JTAG Probe
340 The ZY1000 from Ultimate Solutions is technically not a dongle but a
341 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
342 running on the developer's host computer.
343 Once installed on a network using DHCP or a static IP assignment, users can
344 access the ZY1000 probe locally or remotely from any host with access to the
345 IP address assigned to the probe.
346 The ZY1000 provides an intuitive web interface with direct access to the
347 OpenOCD debugger.
348 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
349 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
350 the target.
351 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
352 to power cycle the target remotely.
354 For more information, visit:
356 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/210-zylin-zy1000-main}
358 @section USB FT2232 Based
360 There are many USB JTAG dongles on the market, many of them based
361 on a chip from ``Future Technology Devices International'' (FTDI)
362 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
363 See: @url{http://www.ftdichip.com} for more information.
364 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
365 chips started to become available in JTAG adapters. Around 2012, a new
366 variant appeared - FT232H - this is a single-channel version of FT2232H.
367 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
368 clocking.)
370 The FT2232 chips are flexible enough to support some other
371 transport options, such as SWD or the SPI variants used to
372 program some chips. They have two communications channels,
373 and one can be used for a UART adapter at the same time the
374 other one is used to provide a debug adapter.
376 Also, some development boards integrate an FT2232 chip to serve as
377 a built-in low-cost debug adapter and USB-to-serial solution.
379 @itemize @bullet
380 @item @b{usbjtag}
381 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
382 @item @b{jtagkey}
383 @* See: @url{http://www.amontec.com/jtagkey.shtml}
384 @item @b{jtagkey2}
385 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
386 @item @b{oocdlink}
387 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
388 @item @b{signalyzer}
389 @* See: @url{http://www.signalyzer.com}
390 @item @b{Stellaris Eval Boards}
391 @* See: @url{http://www.ti.com} - The Stellaris eval boards
392 bundle FT2232-based JTAG and SWD support, which can be used to debug
393 the Stellaris chips. Using separate JTAG adapters is optional.
394 These boards can also be used in a "pass through" mode as JTAG adapters
395 to other target boards, disabling the Stellaris chip.
396 @item @b{TI/Luminary ICDI}
397 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
398 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
399 Evaluation Kits. Like the non-detachable FT2232 support on the other
400 Stellaris eval boards, they can be used to debug other target boards.
401 @item @b{olimex-jtag}
402 @* See: @url{http://www.olimex.com}
403 @item @b{Flyswatter/Flyswatter2}
404 @* See: @url{http://www.tincantools.com}
405 @item @b{turtelizer2}
406 @* See:
407 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
408 @url{http://www.ethernut.de}
409 @item @b{comstick}
410 @* Link: @url{http://www.hitex.com/index.php?id=383}
411 @item @b{stm32stick}
412 @* Link @url{http://www.hitex.com/stm32-stick}
413 @item @b{axm0432_jtag}
414 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
415 to be available anymore as of April 2012.
416 @item @b{cortino}
417 @* Link @url{http://www.hitex.com/index.php?id=cortino}
418 @item @b{dlp-usb1232h}
419 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
420 @item @b{digilent-hs1}
421 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
422 @item @b{opendous}
423 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
424 (OpenHardware).
425 @item @b{JTAG-lock-pick Tiny 2}
426 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
428 @item @b{GW16042}
429 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
430 FT2232H-based
432 @end itemize
433 @section USB-JTAG / Altera USB-Blaster compatibles
435 These devices also show up as FTDI devices, but are not
436 protocol-compatible with the FT2232 devices. They are, however,
437 protocol-compatible among themselves. USB-JTAG devices typically consist
438 of a FT245 followed by a CPLD that understands a particular protocol,
439 or emulates this protocol using some other hardware.
441 They may appear under different USB VID/PID depending on the particular
442 product. The driver can be configured to search for any VID/PID pair
443 (see the section on driver commands).
445 @itemize
446 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
447 @* Link: @url{http://ixo-jtag.sourceforge.net/}
448 @item @b{Altera USB-Blaster}
449 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
450 @end itemize
452 @section USB J-Link based
453 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
454 an example of a microcontroller based JTAG adapter, it uses an
455 AT91SAM764 internally.
457 @itemize @bullet
458 @item @b{SEGGER J-Link}
459 @* Link: @url{http://www.segger.com/jlink.html}
460 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
461 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
462 @item @b{IAR J-Link}
463 @end itemize
465 @section USB RLINK based
466 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
467 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
468 SWD and not JTAG, thus not supported.
470 @itemize @bullet
471 @item @b{Raisonance RLink}
472 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
473 @item @b{STM32 Primer}
474 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
475 @item @b{STM32 Primer2}
476 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
477 @end itemize
479 @section USB ST-LINK based
480 STMicroelectronics has an adapter called @b{ST-LINK}.
481 They only work with STMicroelectronics chips, notably STM32 and STM8.
483 @itemize @bullet
484 @item @b{ST-LINK}
485 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
486 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
487 @item @b{ST-LINK/V2}
488 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
489 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
490 @item @b{STLINK-V3}
491 @* This is available standalone and as part of some kits.
492 @* Link: @url{http://www.st.com/stlink-v3}
493 @end itemize
495 For info the original ST-LINK enumerates using the mass storage usb class; however,
496 its implementation is completely broken. The result is this causes issues under Linux.
497 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
498 @itemize @bullet
499 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
500 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
501 @end itemize
503 @section USB TI/Stellaris ICDI based
504 Texas Instruments has an adapter called @b{ICDI}.
505 It is not to be confused with the FTDI based adapters that were originally fitted to their
506 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
508 @section USB CMSIS-DAP based
509 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
510 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
512 @section USB Other
513 @itemize @bullet
514 @item @b{USBprog}
515 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
517 @item @b{USB - Presto}
518 @* Link: @url{http://tools.asix.net/prg_presto.htm}
520 @item @b{Versaloon-Link}
521 @* Link: @url{http://www.versaloon.com}
523 @item @b{ARM-JTAG-EW}
524 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
526 @item @b{Buspirate}
527 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
529 @item @b{opendous}
530 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
532 @item @b{estick}
533 @* Link: @url{http://code.google.com/p/estick-jtag/}
535 @item @b{Keil ULINK v1}
536 @* Link: @url{http://www.keil.com/ulink1/}
538 @item @b{TI XDS110 Debug Probe}
539 @* The XDS110 is included as the embedded debug probe on many Texas Instruments
540 LaunchPad evaluation boards.
541 @* The XDS110 is also available as a stand-alone USB debug probe. The XDS110
542 stand-alone probe has the additional ability to supply voltage to the target
543 board via its AUX FUNCTIONS port. Use the
544 @command{xds110_supply_voltage <millivolts>} command to set the voltage. 0 turns
545 off the supply. Otherwise, the supply can be set to any value in the range 1800
546 to 3600 millivolts.
547 @* Link: @url{http://processors.wiki.ti.com/index.php/XDS110}
548 @* Link: @url{http://processors.wiki.ti.com/index.php/XDS_Emulation_Software_Package#XDS110_Support_Utilities}
549 @end itemize
551 @section IBM PC Parallel Printer Port Based
553 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
554 and the Macraigor Wiggler. There are many clones and variations of
555 these on the market.
557 Note that parallel ports are becoming much less common, so if you
558 have the choice you should probably avoid these adapters in favor
559 of USB-based ones.
561 @itemize @bullet
563 @item @b{Wiggler} - There are many clones of this.
564 @* Link: @url{http://www.macraigor.com/wiggler.htm}
566 @item @b{DLC5} - From XILINX - There are many clones of this
567 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
568 produced, PDF schematics are easily found and it is easy to make.
570 @item @b{Amontec - JTAG Accelerator}
571 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
573 @item @b{Wiggler2}
574 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
576 @item @b{Wiggler_ntrst_inverted}
577 @* Yet another variation - See the source code, src/jtag/parport.c
579 @item @b{old_amt_wiggler}
580 @* Unknown - probably not on the market today
582 @item @b{arm-jtag}
583 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
585 @item @b{chameleon}
586 @* Link: @url{http://www.amontec.com/chameleon.shtml}
588 @item @b{Triton}
589 @* Unknown.
591 @item @b{Lattice}
592 @* ispDownload from Lattice Semiconductor
593 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
595 @item @b{flashlink}
596 @* From STMicroelectronics;
597 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
599 @end itemize
601 @section Other...
602 @itemize @bullet
604 @item @b{ep93xx}
605 @* An EP93xx based Linux machine using the GPIO pins directly.
607 @item @b{at91rm9200}
608 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
610 @item @b{bcm2835gpio}
611 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
613 @item @b{imx_gpio}
614 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
616 @item @b{jtag_vpi}
617 @* A JTAG driver acting as a client for the JTAG VPI server interface.
618 @* Link: @url{http://github.com/fjullien/jtag_vpi}
620 @end itemize
622 @node About Jim-Tcl
623 @chapter About Jim-Tcl
624 @cindex Jim-Tcl
625 @cindex tcl
627 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
628 This programming language provides a simple and extensible
629 command interpreter.
631 All commands presented in this Guide are extensions to Jim-Tcl.
632 You can use them as simple commands, without needing to learn
633 much of anything about Tcl.
634 Alternatively, you can write Tcl programs with them.
636 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
637 There is an active and responsive community, get on the mailing list
638 if you have any questions. Jim-Tcl maintainers also lurk on the
639 OpenOCD mailing list.
641 @itemize @bullet
642 @item @b{Jim vs. Tcl}
643 @* Jim-Tcl is a stripped down version of the well known Tcl language,
644 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
645 fewer features. Jim-Tcl is several dozens of .C files and .H files and
646 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
647 4.2 MB .zip file containing 1540 files.
649 @item @b{Missing Features}
650 @* Our practice has been: Add/clone the real Tcl feature if/when
651 needed. We welcome Jim-Tcl improvements, not bloat. Also there
652 are a large number of optional Jim-Tcl features that are not
653 enabled in OpenOCD.
655 @item @b{Scripts}
656 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
657 command interpreter today is a mixture of (newer)
658 Jim-Tcl commands, and the (older) original command interpreter.
660 @item @b{Commands}
661 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
662 can type a Tcl for() loop, set variables, etc.
663 Some of the commands documented in this guide are implemented
664 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
666 @item @b{Historical Note}
667 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
668 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
669 as a Git submodule, which greatly simplified upgrading Jim-Tcl
670 to benefit from new features and bugfixes in Jim-Tcl.
672 @item @b{Need a crash course in Tcl?}
673 @*@xref{Tcl Crash Course}.
674 @end itemize
676 @node Running
677 @chapter Running
678 @cindex command line options
679 @cindex logfile
680 @cindex directory search
682 Properly installing OpenOCD sets up your operating system to grant it access
683 to the debug adapters. On Linux, this usually involves installing a file
684 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
685 that works for many common adapters is shipped with OpenOCD in the
686 @file{contrib} directory. MS-Windows needs
687 complex and confusing driver configuration for every peripheral. Such issues
688 are unique to each operating system, and are not detailed in this User's Guide.
690 Then later you will invoke the OpenOCD server, with various options to
691 tell it how each debug session should work.
692 The @option{--help} option shows:
693 @verbatim
694 bash$ openocd --help
696 --help | -h display this help
697 --version | -v display OpenOCD version
698 --file | -f use configuration file <name>
699 --search | -s dir to search for config files and scripts
700 --debug | -d set debug level to 3
701 | -d<n> set debug level to <level>
702 --log_output | -l redirect log output to file <name>
703 --command | -c run <command>
704 @end verbatim
706 If you don't give any @option{-f} or @option{-c} options,
707 OpenOCD tries to read the configuration file @file{openocd.cfg}.
708 To specify one or more different
709 configuration files, use @option{-f} options. For example:
711 @example
712 openocd -f config1.cfg -f config2.cfg -f config3.cfg
713 @end example
715 Configuration files and scripts are searched for in
716 @enumerate
717 @item the current directory,
718 @item any search dir specified on the command line using the @option{-s} option,
719 @item any search dir specified using the @command{add_script_search_dir} command,
720 @item @file{$HOME/.openocd} (not on Windows),
721 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
722 @item the site wide script library @file{$pkgdatadir/site} and
723 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
724 @end enumerate
725 The first found file with a matching file name will be used.
727 @quotation Note
728 Don't try to use configuration script names or paths which
729 include the "#" character. That character begins Tcl comments.
730 @end quotation
732 @section Simple setup, no customization
734 In the best case, you can use two scripts from one of the script
735 libraries, hook up your JTAG adapter, and start the server ... and
736 your JTAG setup will just work "out of the box". Always try to
737 start by reusing those scripts, but assume you'll need more
738 customization even if this works. @xref{OpenOCD Project Setup}.
740 If you find a script for your JTAG adapter, and for your board or
741 target, you may be able to hook up your JTAG adapter then start
742 the server with some variation of one of the following:
744 @example
745 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
746 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
747 @end example
749 You might also need to configure which reset signals are present,
750 using @option{-c 'reset_config trst_and_srst'} or something similar.
751 If all goes well you'll see output something like
753 @example
754 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
755 For bug reports, read
756 http://openocd.org/doc/doxygen/bugs.html
757 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
758 (mfg: 0x23b, part: 0xba00, ver: 0x3)
759 @end example
761 Seeing that "tap/device found" message, and no warnings, means
762 the JTAG communication is working. That's a key milestone, but
763 you'll probably need more project-specific setup.
765 @section What OpenOCD does as it starts
767 OpenOCD starts by processing the configuration commands provided
768 on the command line or, if there were no @option{-c command} or
769 @option{-f file.cfg} options given, in @file{openocd.cfg}.
770 @xref{configurationstage,,Configuration Stage}.
771 At the end of the configuration stage it verifies the JTAG scan
772 chain defined using those commands; your configuration should
773 ensure that this always succeeds.
774 Normally, OpenOCD then starts running as a server.
775 Alternatively, commands may be used to terminate the configuration
776 stage early, perform work (such as updating some flash memory),
777 and then shut down without acting as a server.
779 Once OpenOCD starts running as a server, it waits for connections from
780 clients (Telnet, GDB, RPC) and processes the commands issued through
781 those channels.
783 If you are having problems, you can enable internal debug messages via
784 the @option{-d} option.
786 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
787 @option{-c} command line switch.
789 To enable debug output (when reporting problems or working on OpenOCD
790 itself), use the @option{-d} command line switch. This sets the
791 @option{debug_level} to "3", outputting the most information,
792 including debug messages. The default setting is "2", outputting only
793 informational messages, warnings and errors. You can also change this
794 setting from within a telnet or gdb session using @command{debug_level<n>}
795 (@pxref{debuglevel,,debug_level}).
797 You can redirect all output from the server to a file using the
798 @option{-l <logfile>} switch.
800 Note! OpenOCD will launch the GDB & telnet server even if it can not
801 establish a connection with the target. In general, it is possible for
802 the JTAG controller to be unresponsive until the target is set up
803 correctly via e.g. GDB monitor commands in a GDB init script.
805 @node OpenOCD Project Setup
806 @chapter OpenOCD Project Setup
808 To use OpenOCD with your development projects, you need to do more than
809 just connect the JTAG adapter hardware (dongle) to your development board
810 and start the OpenOCD server.
811 You also need to configure your OpenOCD server so that it knows
812 about your adapter and board, and helps your work.
813 You may also want to connect OpenOCD to GDB, possibly
814 using Eclipse or some other GUI.
816 @section Hooking up the JTAG Adapter
818 Today's most common case is a dongle with a JTAG cable on one side
819 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
820 and a USB cable on the other.
821 Instead of USB, some cables use Ethernet;
822 older ones may use a PC parallel port, or even a serial port.
824 @enumerate
825 @item @emph{Start with power to your target board turned off},
826 and nothing connected to your JTAG adapter.
827 If you're particularly paranoid, unplug power to the board.
828 It's important to have the ground signal properly set up,
829 unless you are using a JTAG adapter which provides
830 galvanic isolation between the target board and the
831 debugging host.
833 @item @emph{Be sure it's the right kind of JTAG connector.}
834 If your dongle has a 20-pin ARM connector, you need some kind
835 of adapter (or octopus, see below) to hook it up to
836 boards using 14-pin or 10-pin connectors ... or to 20-pin
837 connectors which don't use ARM's pinout.
839 In the same vein, make sure the voltage levels are compatible.
840 Not all JTAG adapters have the level shifters needed to work
841 with 1.2 Volt boards.
843 @item @emph{Be certain the cable is properly oriented} or you might
844 damage your board. In most cases there are only two possible
845 ways to connect the cable.
846 Connect the JTAG cable from your adapter to the board.
847 Be sure it's firmly connected.
849 In the best case, the connector is keyed to physically
850 prevent you from inserting it wrong.
851 This is most often done using a slot on the board's male connector
852 housing, which must match a key on the JTAG cable's female connector.
853 If there's no housing, then you must look carefully and
854 make sure pin 1 on the cable hooks up to pin 1 on the board.
855 Ribbon cables are frequently all grey except for a wire on one
856 edge, which is red. The red wire is pin 1.
858 Sometimes dongles provide cables where one end is an ``octopus'' of
859 color coded single-wire connectors, instead of a connector block.
860 These are great when converting from one JTAG pinout to another,
861 but are tedious to set up.
862 Use these with connector pinout diagrams to help you match up the
863 adapter signals to the right board pins.
865 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
866 A USB, parallel, or serial port connector will go to the host which
867 you are using to run OpenOCD.
868 For Ethernet, consult the documentation and your network administrator.
870 For USB-based JTAG adapters you have an easy sanity check at this point:
871 does the host operating system see the JTAG adapter? If you're running
872 Linux, try the @command{lsusb} command. If that host is an
873 MS-Windows host, you'll need to install a driver before OpenOCD works.
875 @item @emph{Connect the adapter's power supply, if needed.}
876 This step is primarily for non-USB adapters,
877 but sometimes USB adapters need extra power.
879 @item @emph{Power up the target board.}
880 Unless you just let the magic smoke escape,
881 you're now ready to set up the OpenOCD server
882 so you can use JTAG to work with that board.
884 @end enumerate
886 Talk with the OpenOCD server using
887 telnet (@code{telnet localhost 4444} on many systems) or GDB.
888 @xref{GDB and OpenOCD}.
890 @section Project Directory
892 There are many ways you can configure OpenOCD and start it up.
894 A simple way to organize them all involves keeping a
895 single directory for your work with a given board.
896 When you start OpenOCD from that directory,
897 it searches there first for configuration files, scripts,
898 files accessed through semihosting,
899 and for code you upload to the target board.
900 It is also the natural place to write files,
901 such as log files and data you download from the board.
903 @section Configuration Basics
905 There are two basic ways of configuring OpenOCD, and
906 a variety of ways you can mix them.
907 Think of the difference as just being how you start the server:
909 @itemize
910 @item Many @option{-f file} or @option{-c command} options on the command line
911 @item No options, but a @dfn{user config file}
912 in the current directory named @file{openocd.cfg}
913 @end itemize
915 Here is an example @file{openocd.cfg} file for a setup
916 using a Signalyzer FT2232-based JTAG adapter to talk to
917 a board with an Atmel AT91SAM7X256 microcontroller:
919 @example
920 source [find interface/ftdi/signalyzer.cfg]
922 # GDB can also flash my flash!
923 gdb_memory_map enable
924 gdb_flash_program enable
926 source [find target/sam7x256.cfg]
927 @end example
929 Here is the command line equivalent of that configuration:
931 @example
932 openocd -f interface/ftdi/signalyzer.cfg \
933 -c "gdb_memory_map enable" \
934 -c "gdb_flash_program enable" \
935 -f target/sam7x256.cfg
936 @end example
938 You could wrap such long command lines in shell scripts,
939 each supporting a different development task.
940 One might re-flash the board with a specific firmware version.
941 Another might set up a particular debugging or run-time environment.
943 @quotation Important
944 At this writing (October 2009) the command line method has
945 problems with how it treats variables.
946 For example, after @option{-c "set VAR value"}, or doing the
947 same in a script, the variable @var{VAR} will have no value
948 that can be tested in a later script.
949 @end quotation
951 Here we will focus on the simpler solution: one user config
952 file, including basic configuration plus any TCL procedures
953 to simplify your work.
955 @section User Config Files
956 @cindex config file, user
957 @cindex user config file
958 @cindex config file, overview
960 A user configuration file ties together all the parts of a project
961 in one place.
962 One of the following will match your situation best:
964 @itemize
965 @item Ideally almost everything comes from configuration files
966 provided by someone else.
967 For example, OpenOCD distributes a @file{scripts} directory
968 (probably in @file{/usr/share/openocd/scripts} on Linux).
969 Board and tool vendors can provide these too, as can individual
970 user sites; the @option{-s} command line option lets you say
971 where to find these files. (@xref{Running}.)
972 The AT91SAM7X256 example above works this way.
974 Three main types of non-user configuration file each have their
975 own subdirectory in the @file{scripts} directory:
977 @enumerate
978 @item @b{interface} -- one for each different debug adapter;
979 @item @b{board} -- one for each different board
980 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
981 @end enumerate
983 Best case: include just two files, and they handle everything else.
984 The first is an interface config file.
985 The second is board-specific, and it sets up the JTAG TAPs and
986 their GDB targets (by deferring to some @file{target.cfg} file),
987 declares all flash memory, and leaves you nothing to do except
988 meet your deadline:
990 @example
991 source [find interface/olimex-jtag-tiny.cfg]
992 source [find board/csb337.cfg]
993 @end example
995 Boards with a single microcontroller often won't need more
996 than the target config file, as in the AT91SAM7X256 example.
997 That's because there is no external memory (flash, DDR RAM), and
998 the board differences are encapsulated by application code.
1000 @item Maybe you don't know yet what your board looks like to JTAG.
1001 Once you know the @file{interface.cfg} file to use, you may
1002 need help from OpenOCD to discover what's on the board.
1003 Once you find the JTAG TAPs, you can just search for appropriate
1004 target and board
1005 configuration files ... or write your own, from the bottom up.
1006 @xref{autoprobing,,Autoprobing}.
1008 @item You can often reuse some standard config files but
1009 need to write a few new ones, probably a @file{board.cfg} file.
1010 You will be using commands described later in this User's Guide,
1011 and working with the guidelines in the next chapter.
1013 For example, there may be configuration files for your JTAG adapter
1014 and target chip, but you need a new board-specific config file
1015 giving access to your particular flash chips.
1016 Or you might need to write another target chip configuration file
1017 for a new chip built around the Cortex-M3 core.
1019 @quotation Note
1020 When you write new configuration files, please submit
1021 them for inclusion in the next OpenOCD release.
1022 For example, a @file{board/newboard.cfg} file will help the
1023 next users of that board, and a @file{target/newcpu.cfg}
1024 will help support users of any board using that chip.
1025 @end quotation
1027 @item
1028 You may may need to write some C code.
1029 It may be as simple as supporting a new FT2232 or parport
1030 based adapter; a bit more involved, like a NAND or NOR flash
1031 controller driver; or a big piece of work like supporting
1032 a new chip architecture.
1033 @end itemize
1035 Reuse the existing config files when you can.
1036 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1037 You may find a board configuration that's a good example to follow.
1039 When you write config files, separate the reusable parts
1040 (things every user of that interface, chip, or board needs)
1041 from ones specific to your environment and debugging approach.
1042 @itemize
1044 @item
1045 For example, a @code{gdb-attach} event handler that invokes
1046 the @command{reset init} command will interfere with debugging
1047 early boot code, which performs some of the same actions
1048 that the @code{reset-init} event handler does.
1050 @item
1051 Likewise, the @command{arm9 vector_catch} command (or
1052 @cindex vector_catch
1053 its siblings @command{xscale vector_catch}
1054 and @command{cortex_m vector_catch}) can be a time-saver
1055 during some debug sessions, but don't make everyone use that either.
1056 Keep those kinds of debugging aids in your user config file,
1057 along with messaging and tracing setup.
1058 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1060 @item
1061 You might need to override some defaults.
1062 For example, you might need to move, shrink, or back up the target's
1063 work area if your application needs much SRAM.
1065 @item
1066 TCP/IP port configuration is another example of something which
1067 is environment-specific, and should only appear in
1068 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1069 @end itemize
1071 @section Project-Specific Utilities
1073 A few project-specific utility
1074 routines may well speed up your work.
1075 Write them, and keep them in your project's user config file.
1077 For example, if you are making a boot loader work on a
1078 board, it's nice to be able to debug the ``after it's
1079 loaded to RAM'' parts separately from the finicky early
1080 code which sets up the DDR RAM controller and clocks.
1081 A script like this one, or a more GDB-aware sibling,
1082 may help:
1084 @example
1085 proc ramboot @{ @} @{
1086 # Reset, running the target's "reset-init" scripts
1087 # to initialize clocks and the DDR RAM controller.
1088 # Leave the CPU halted.
1089 reset init
1091 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1092 load_image u-boot.bin 0x20000000
1094 # Start running.
1095 resume 0x20000000
1096 @}
1097 @end example
1099 Then once that code is working you will need to make it
1100 boot from NOR flash; a different utility would help.
1101 Alternatively, some developers write to flash using GDB.
1102 (You might use a similar script if you're working with a flash
1103 based microcontroller application instead of a boot loader.)
1105 @example
1106 proc newboot @{ @} @{
1107 # Reset, leaving the CPU halted. The "reset-init" event
1108 # proc gives faster access to the CPU and to NOR flash;
1109 # "reset halt" would be slower.
1110 reset init
1112 # Write standard version of U-Boot into the first two
1113 # sectors of NOR flash ... the standard version should
1114 # do the same lowlevel init as "reset-init".
1115 flash protect 0 0 1 off
1116 flash erase_sector 0 0 1
1117 flash write_bank 0 u-boot.bin 0x0
1118 flash protect 0 0 1 on
1120 # Reboot from scratch using that new boot loader.
1121 reset run
1122 @}
1123 @end example
1125 You may need more complicated utility procedures when booting
1126 from NAND.
1127 That often involves an extra bootloader stage,
1128 running from on-chip SRAM to perform DDR RAM setup so it can load
1129 the main bootloader code (which won't fit into that SRAM).
1131 Other helper scripts might be used to write production system images,
1132 involving considerably more than just a three stage bootloader.
1134 @section Target Software Changes
1136 Sometimes you may want to make some small changes to the software
1137 you're developing, to help make JTAG debugging work better.
1138 For example, in C or assembly language code you might
1139 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1140 handling issues like:
1142 @itemize @bullet
1144 @item @b{Watchdog Timers}...
1145 Watchdog timers are typically used to automatically reset systems if
1146 some application task doesn't periodically reset the timer. (The
1147 assumption is that the system has locked up if the task can't run.)
1148 When a JTAG debugger halts the system, that task won't be able to run
1149 and reset the timer ... potentially causing resets in the middle of
1150 your debug sessions.
1152 It's rarely a good idea to disable such watchdogs, since their usage
1153 needs to be debugged just like all other parts of your firmware.
1154 That might however be your only option.
1156 Look instead for chip-specific ways to stop the watchdog from counting
1157 while the system is in a debug halt state. It may be simplest to set
1158 that non-counting mode in your debugger startup scripts. You may however
1159 need a different approach when, for example, a motor could be physically
1160 damaged by firmware remaining inactive in a debug halt state. That might
1161 involve a type of firmware mode where that "non-counting" mode is disabled
1162 at the beginning then re-enabled at the end; a watchdog reset might fire
1163 and complicate the debug session, but hardware (or people) would be
1164 protected.@footnote{Note that many systems support a "monitor mode" debug
1165 that is a somewhat cleaner way to address such issues. You can think of
1166 it as only halting part of the system, maybe just one task,
1167 instead of the whole thing.
1168 At this writing, January 2010, OpenOCD based debugging does not support
1169 monitor mode debug, only "halt mode" debug.}
1171 @item @b{ARM Semihosting}...
1172 @cindex ARM semihosting
1173 When linked with a special runtime library provided with many
1174 toolchains@footnote{See chapter 8 "Semihosting" in
1175 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1176 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1177 The CodeSourcery EABI toolchain also includes a semihosting library.},
1178 your target code can use I/O facilities on the debug host. That library
1179 provides a small set of system calls which are handled by OpenOCD.
1180 It can let the debugger provide your system console and a file system,
1181 helping with early debugging or providing a more capable environment
1182 for sometimes-complex tasks like installing system firmware onto
1183 NAND or SPI flash.
1185 @item @b{ARM Wait-For-Interrupt}...
1186 Many ARM chips synchronize the JTAG clock using the core clock.
1187 Low power states which stop that core clock thus prevent JTAG access.
1188 Idle loops in tasking environments often enter those low power states
1189 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1191 You may want to @emph{disable that instruction} in source code,
1192 or otherwise prevent using that state,
1193 to ensure you can get JTAG access at any time.@footnote{As a more
1194 polite alternative, some processors have special debug-oriented
1195 registers which can be used to change various features including
1196 how the low power states are clocked while debugging.
1197 The STM32 DBGMCU_CR register is an example; at the cost of extra
1198 power consumption, JTAG can be used during low power states.}
1199 For example, the OpenOCD @command{halt} command may not
1200 work for an idle processor otherwise.
1202 @item @b{Delay after reset}...
1203 Not all chips have good support for debugger access
1204 right after reset; many LPC2xxx chips have issues here.
1205 Similarly, applications that reconfigure pins used for
1206 JTAG access as they start will also block debugger access.
1208 To work with boards like this, @emph{enable a short delay loop}
1209 the first thing after reset, before "real" startup activities.
1210 For example, one second's delay is usually more than enough
1211 time for a JTAG debugger to attach, so that
1212 early code execution can be debugged
1213 or firmware can be replaced.
1215 @item @b{Debug Communications Channel (DCC)}...
1216 Some processors include mechanisms to send messages over JTAG.
1217 Many ARM cores support these, as do some cores from other vendors.
1218 (OpenOCD may be able to use this DCC internally, speeding up some
1219 operations like writing to memory.)
1221 Your application may want to deliver various debugging messages
1222 over JTAG, by @emph{linking with a small library of code}
1223 provided with OpenOCD and using the utilities there to send
1224 various kinds of message.
1225 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1227 @end itemize
1229 @section Target Hardware Setup
1231 Chip vendors often provide software development boards which
1232 are highly configurable, so that they can support all options
1233 that product boards may require. @emph{Make sure that any
1234 jumpers or switches match the system configuration you are
1235 working with.}
1237 Common issues include:
1239 @itemize @bullet
1241 @item @b{JTAG setup} ...
1242 Boards may support more than one JTAG configuration.
1243 Examples include jumpers controlling pullups versus pulldowns
1244 on the nTRST and/or nSRST signals, and choice of connectors
1245 (e.g. which of two headers on the base board,
1246 or one from a daughtercard).
1247 For some Texas Instruments boards, you may need to jumper the
1248 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1250 @item @b{Boot Modes} ...
1251 Complex chips often support multiple boot modes, controlled
1252 by external jumpers. Make sure this is set up correctly.
1253 For example many i.MX boards from NXP need to be jumpered
1254 to "ATX mode" to start booting using the on-chip ROM, when
1255 using second stage bootloader code stored in a NAND flash chip.
1257 Such explicit configuration is common, and not limited to
1258 booting from NAND. You might also need to set jumpers to
1259 start booting using code loaded from an MMC/SD card; external
1260 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1261 flash; some external host; or various other sources.
1264 @item @b{Memory Addressing} ...
1265 Boards which support multiple boot modes may also have jumpers
1266 to configure memory addressing. One board, for example, jumpers
1267 external chipselect 0 (used for booting) to address either
1268 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1269 or NAND flash. When it's jumpered to address NAND flash, that
1270 board must also be told to start booting from on-chip ROM.
1272 Your @file{board.cfg} file may also need to be told this jumper
1273 configuration, so that it can know whether to declare NOR flash
1274 using @command{flash bank} or instead declare NAND flash with
1275 @command{nand device}; and likewise which probe to perform in
1276 its @code{reset-init} handler.
1278 A closely related issue is bus width. Jumpers might need to
1279 distinguish between 8 bit or 16 bit bus access for the flash
1280 used to start booting.
1282 @item @b{Peripheral Access} ...
1283 Development boards generally provide access to every peripheral
1284 on the chip, sometimes in multiple modes (such as by providing
1285 multiple audio codec chips).
1286 This interacts with software
1287 configuration of pin multiplexing, where for example a
1288 given pin may be routed either to the MMC/SD controller
1289 or the GPIO controller. It also often interacts with
1290 configuration jumpers. One jumper may be used to route
1291 signals to an MMC/SD card slot or an expansion bus (which
1292 might in turn affect booting); others might control which
1293 audio or video codecs are used.
1295 @end itemize
1297 Plus you should of course have @code{reset-init} event handlers
1298 which set up the hardware to match that jumper configuration.
1299 That includes in particular any oscillator or PLL used to clock
1300 the CPU, and any memory controllers needed to access external
1301 memory and peripherals. Without such handlers, you won't be
1302 able to access those resources without working target firmware
1303 which can do that setup ... this can be awkward when you're
1304 trying to debug that target firmware. Even if there's a ROM
1305 bootloader which handles a few issues, it rarely provides full
1306 access to all board-specific capabilities.
1309 @node Config File Guidelines
1310 @chapter Config File Guidelines
1312 This chapter is aimed at any user who needs to write a config file,
1313 including developers and integrators of OpenOCD and any user who
1314 needs to get a new board working smoothly.
1315 It provides guidelines for creating those files.
1317 You should find the following directories under
1318 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1319 them as-is where you can; or as models for new files.
1320 @itemize @bullet
1321 @item @file{interface} ...
1322 These are for debug adapters. Files that specify configuration to use
1323 specific JTAG, SWD and other adapters go here.
1324 @item @file{board} ...
1325 Think Circuit Board, PWA, PCB, they go by many names. Board files
1326 contain initialization items that are specific to a board.
1328 They reuse target configuration files, since the same
1329 microprocessor chips are used on many boards,
1330 but support for external parts varies widely. For
1331 example, the SDRAM initialization sequence for the board, or the type
1332 of external flash and what address it uses. Any initialization
1333 sequence to enable that external flash or SDRAM should be found in the
1334 board file. Boards may also contain multiple targets: two CPUs; or
1335 a CPU and an FPGA.
1336 @item @file{target} ...
1337 Think chip. The ``target'' directory represents the JTAG TAPs
1338 on a chip
1339 which OpenOCD should control, not a board. Two common types of targets
1340 are ARM chips and FPGA or CPLD chips.
1341 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1342 the target config file defines all of them.
1343 @item @emph{more} ... browse for other library files which may be useful.
1344 For example, there are various generic and CPU-specific utilities.
1345 @end itemize
1347 The @file{openocd.cfg} user config
1348 file may override features in any of the above files by
1349 setting variables before sourcing the target file, or by adding
1350 commands specific to their situation.
1352 @section Interface Config Files
1354 The user config file
1355 should be able to source one of these files with a command like this:
1357 @example
1358 source [find interface/FOOBAR.cfg]
1359 @end example
1361 A preconfigured interface file should exist for every debug adapter
1362 in use today with OpenOCD.
1363 That said, perhaps some of these config files
1364 have only been used by the developer who created it.
1366 A separate chapter gives information about how to set these up.
1367 @xref{Debug Adapter Configuration}.
1368 Read the OpenOCD source code (and Developer's Guide)
1369 if you have a new kind of hardware interface
1370 and need to provide a driver for it.
1372 @section Board Config Files
1373 @cindex config file, board
1374 @cindex board config file
1376 The user config file
1377 should be able to source one of these files with a command like this:
1379 @example
1380 source [find board/FOOBAR.cfg]
1381 @end example
1383 The point of a board config file is to package everything
1384 about a given board that user config files need to know.
1385 In summary the board files should contain (if present)
1387 @enumerate
1388 @item One or more @command{source [find target/...cfg]} statements
1389 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1390 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1391 @item Target @code{reset} handlers for SDRAM and I/O configuration
1392 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1393 @item All things that are not ``inside a chip''
1394 @end enumerate
1396 Generic things inside target chips belong in target config files,
1397 not board config files. So for example a @code{reset-init} event
1398 handler should know board-specific oscillator and PLL parameters,
1399 which it passes to target-specific utility code.
1401 The most complex task of a board config file is creating such a
1402 @code{reset-init} event handler.
1403 Define those handlers last, after you verify the rest of the board
1404 configuration works.
1406 @subsection Communication Between Config files
1408 In addition to target-specific utility code, another way that
1409 board and target config files communicate is by following a
1410 convention on how to use certain variables.
1412 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1413 Thus the rule we follow in OpenOCD is this: Variables that begin with
1414 a leading underscore are temporary in nature, and can be modified and
1415 used at will within a target configuration file.
1417 Complex board config files can do the things like this,
1418 for a board with three chips:
1420 @example
1421 # Chip #1: PXA270 for network side, big endian
1422 set CHIPNAME network
1423 set ENDIAN big
1424 source [find target/pxa270.cfg]
1425 # on return: _TARGETNAME = network.cpu
1426 # other commands can refer to the "network.cpu" target.
1427 $_TARGETNAME configure .... events for this CPU..
1429 # Chip #2: PXA270 for video side, little endian
1430 set CHIPNAME video
1431 set ENDIAN little
1432 source [find target/pxa270.cfg]
1433 # on return: _TARGETNAME = video.cpu
1434 # other commands can refer to the "video.cpu" target.
1435 $_TARGETNAME configure .... events for this CPU..
1437 # Chip #3: Xilinx FPGA for glue logic
1438 set CHIPNAME xilinx
1439 unset ENDIAN
1440 source [find target/spartan3.cfg]
1441 @end example
1443 That example is oversimplified because it doesn't show any flash memory,
1444 or the @code{reset-init} event handlers to initialize external DRAM
1445 or (assuming it needs it) load a configuration into the FPGA.
1446 Such features are usually needed for low-level work with many boards,
1447 where ``low level'' implies that the board initialization software may
1448 not be working. (That's a common reason to need JTAG tools. Another
1449 is to enable working with microcontroller-based systems, which often
1450 have no debugging support except a JTAG connector.)
1452 Target config files may also export utility functions to board and user
1453 config files. Such functions should use name prefixes, to help avoid
1454 naming collisions.
1456 Board files could also accept input variables from user config files.
1457 For example, there might be a @code{J4_JUMPER} setting used to identify
1458 what kind of flash memory a development board is using, or how to set
1459 up other clocks and peripherals.
1461 @subsection Variable Naming Convention
1462 @cindex variable names
1464 Most boards have only one instance of a chip.
1465 However, it should be easy to create a board with more than
1466 one such chip (as shown above).
1467 Accordingly, we encourage these conventions for naming
1468 variables associated with different @file{target.cfg} files,
1469 to promote consistency and
1470 so that board files can override target defaults.
1472 Inputs to target config files include:
1474 @itemize @bullet
1475 @item @code{CHIPNAME} ...
1476 This gives a name to the overall chip, and is used as part of
1477 tap identifier dotted names.
1478 While the default is normally provided by the chip manufacturer,
1479 board files may need to distinguish between instances of a chip.
1480 @item @code{ENDIAN} ...
1481 By default @option{little} - although chips may hard-wire @option{big}.
1482 Chips that can't change endianess don't need to use this variable.
1483 @item @code{CPUTAPID} ...
1484 When OpenOCD examines the JTAG chain, it can be told verify the
1485 chips against the JTAG IDCODE register.
1486 The target file will hold one or more defaults, but sometimes the
1487 chip in a board will use a different ID (perhaps a newer revision).
1488 @end itemize
1490 Outputs from target config files include:
1492 @itemize @bullet
1493 @item @code{_TARGETNAME} ...
1494 By convention, this variable is created by the target configuration
1495 script. The board configuration file may make use of this variable to
1496 configure things like a ``reset init'' script, or other things
1497 specific to that board and that target.
1498 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1499 @code{_TARGETNAME1}, ... etc.
1500 @end itemize
1502 @subsection The reset-init Event Handler
1503 @cindex event, reset-init
1504 @cindex reset-init handler
1506 Board config files run in the OpenOCD configuration stage;
1507 they can't use TAPs or targets, since they haven't been
1508 fully set up yet.
1509 This means you can't write memory or access chip registers;
1510 you can't even verify that a flash chip is present.
1511 That's done later in event handlers, of which the target @code{reset-init}
1512 handler is one of the most important.
1514 Except on microcontrollers, the basic job of @code{reset-init} event
1515 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1516 Microcontrollers rarely use boot loaders; they run right out of their
1517 on-chip flash and SRAM memory. But they may want to use one of these
1518 handlers too, if just for developer convenience.
1520 @quotation Note
1521 Because this is so very board-specific, and chip-specific, no examples
1522 are included here.
1523 Instead, look at the board config files distributed with OpenOCD.
1524 If you have a boot loader, its source code will help; so will
1525 configuration files for other JTAG tools
1526 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1527 @end quotation
1529 Some of this code could probably be shared between different boards.
1530 For example, setting up a DRAM controller often doesn't differ by
1531 much except the bus width (16 bits or 32?) and memory timings, so a
1532 reusable TCL procedure loaded by the @file{target.cfg} file might take
1533 those as parameters.
1534 Similarly with oscillator, PLL, and clock setup;
1535 and disabling the watchdog.
1536 Structure the code cleanly, and provide comments to help
1537 the next developer doing such work.
1538 (@emph{You might be that next person} trying to reuse init code!)
1540 The last thing normally done in a @code{reset-init} handler is probing
1541 whatever flash memory was configured. For most chips that needs to be
1542 done while the associated target is halted, either because JTAG memory
1543 access uses the CPU or to prevent conflicting CPU access.
1545 @subsection JTAG Clock Rate
1547 Before your @code{reset-init} handler has set up
1548 the PLLs and clocking, you may need to run with
1549 a low JTAG clock rate.
1550 @xref{jtagspeed,,JTAG Speed}.
1551 Then you'd increase that rate after your handler has
1552 made it possible to use the faster JTAG clock.
1553 When the initial low speed is board-specific, for example
1554 because it depends on a board-specific oscillator speed, then
1555 you should probably set it up in the board config file;
1556 if it's target-specific, it belongs in the target config file.
1558 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1559 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1560 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1561 Consult chip documentation to determine the peak JTAG clock rate,
1562 which might be less than that.
1564 @quotation Warning
1565 On most ARMs, JTAG clock detection is coupled to the core clock, so
1566 software using a @option{wait for interrupt} operation blocks JTAG access.
1567 Adaptive clocking provides a partial workaround, but a more complete
1568 solution just avoids using that instruction with JTAG debuggers.
1569 @end quotation
1571 If both the chip and the board support adaptive clocking,
1572 use the @command{jtag_rclk}
1573 command, in case your board is used with JTAG adapter which
1574 also supports it. Otherwise use @command{adapter_khz}.
1575 Set the slow rate at the beginning of the reset sequence,
1576 and the faster rate as soon as the clocks are at full speed.
1578 @anchor{theinitboardprocedure}
1579 @subsection The init_board procedure
1580 @cindex init_board procedure
1582 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1583 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1584 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1585 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1586 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1587 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1588 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1589 Additionally ``linear'' board config file will most likely fail when target config file uses
1590 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1591 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1592 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1593 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1595 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1596 the original), allowing greater code reuse.
1598 @example
1599 ### board_file.cfg ###
1601 # source target file that does most of the config in init_targets
1602 source [find target/target.cfg]
1604 proc enable_fast_clock @{@} @{
1605 # enables fast on-board clock source
1606 # configures the chip to use it
1607 @}
1609 # initialize only board specifics - reset, clock, adapter frequency
1610 proc init_board @{@} @{
1611 reset_config trst_and_srst trst_pulls_srst
1613 $_TARGETNAME configure -event reset-start @{
1614 adapter_khz 100
1615 @}
1617 $_TARGETNAME configure -event reset-init @{
1618 enable_fast_clock
1619 adapter_khz 10000
1620 @}
1621 @}
1622 @end example
1624 @section Target Config Files
1625 @cindex config file, target
1626 @cindex target config file
1628 Board config files communicate with target config files using
1629 naming conventions as described above, and may source one or
1630 more target config files like this:
1632 @example
1633 source [find target/FOOBAR.cfg]
1634 @end example
1636 The point of a target config file is to package everything
1637 about a given chip that board config files need to know.
1638 In summary the target files should contain
1640 @enumerate
1641 @item Set defaults
1642 @item Add TAPs to the scan chain
1643 @item Add CPU targets (includes GDB support)
1644 @item CPU/Chip/CPU-Core specific features
1645 @item On-Chip flash
1646 @end enumerate
1648 As a rule of thumb, a target file sets up only one chip.
1649 For a microcontroller, that will often include a single TAP,
1650 which is a CPU needing a GDB target, and its on-chip flash.
1652 More complex chips may include multiple TAPs, and the target
1653 config file may need to define them all before OpenOCD
1654 can talk to the chip.
1655 For example, some phone chips have JTAG scan chains that include
1656 an ARM core for operating system use, a DSP,
1657 another ARM core embedded in an image processing engine,
1658 and other processing engines.
1660 @subsection Default Value Boiler Plate Code
1662 All target configuration files should start with code like this,
1663 letting board config files express environment-specific
1664 differences in how things should be set up.
1666 @example
1667 # Boards may override chip names, perhaps based on role,
1668 # but the default should match what the vendor uses
1669 if @{ [info exists CHIPNAME] @} @{
1671 @} else @{
1672 set _CHIPNAME sam7x256
1673 @}
1675 # ONLY use ENDIAN with targets that can change it.
1676 if @{ [info exists ENDIAN] @} @{
1677 set _ENDIAN $ENDIAN
1678 @} else @{
1679 set _ENDIAN little
1680 @}
1682 # TAP identifiers may change as chips mature, for example with
1683 # new revision fields (the "3" here). Pick a good default; you
1684 # can pass several such identifiers to the "jtag newtap" command.
1685 if @{ [info exists CPUTAPID ] @} @{
1687 @} else @{
1688 set _CPUTAPID 0x3f0f0f0f
1689 @}
1690 @end example
1691 @c but 0x3f0f0f0f is for an str73x part ...
1693 @emph{Remember:} Board config files may include multiple target
1694 config files, or the same target file multiple times
1695 (changing at least @code{CHIPNAME}).
1697 Likewise, the target configuration file should define
1698 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1699 use it later on when defining debug targets:
1701 @example
1703 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1704 @end example
1706 @subsection Adding TAPs to the Scan Chain
1707 After the ``defaults'' are set up,
1708 add the TAPs on each chip to the JTAG scan chain.
1709 @xref{TAP Declaration}, and the naming convention
1710 for taps.
1712 In the simplest case the chip has only one TAP,
1713 probably for a CPU or FPGA.
1714 The config file for the Atmel AT91SAM7X256
1715 looks (in part) like this:
1717 @example
1718 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1719 @end example
1721 A board with two such at91sam7 chips would be able
1722 to source such a config file twice, with different
1723 values for @code{CHIPNAME}, so
1724 it adds a different TAP each time.
1726 If there are nonzero @option{-expected-id} values,
1727 OpenOCD attempts to verify the actual tap id against those values.
1728 It will issue error messages if there is mismatch, which
1729 can help to pinpoint problems in OpenOCD configurations.
1731 @example
1732 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1733 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1734 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1735 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1736 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1737 @end example
1739 There are more complex examples too, with chips that have
1740 multiple TAPs. Ones worth looking at include:
1742 @itemize
1743 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1744 plus a JRC to enable them
1745 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1746 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1747 is not currently used)
1748 @end itemize
1750 @subsection Add CPU targets
1752 After adding a TAP for a CPU, you should set it up so that
1753 GDB and other commands can use it.
1754 @xref{CPU Configuration}.
1755 For the at91sam7 example above, the command can look like this;
1756 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1757 to little endian, and this chip doesn't support changing that.
1759 @example
1761 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1762 @end example
1764 Work areas are small RAM areas associated with CPU targets.
1765 They are used by OpenOCD to speed up downloads,
1766 and to download small snippets of code to program flash chips.
1767 If the chip includes a form of ``on-chip-ram'' - and many do - define
1768 a work area if you can.
1769 Again using the at91sam7 as an example, this can look like:
1771 @example
1772 $_TARGETNAME configure -work-area-phys 0x00200000 \
1773 -work-area-size 0x4000 -work-area-backup 0
1774 @end example
1776 @anchor{definecputargetsworkinginsmp}
1777 @subsection Define CPU targets working in SMP
1778 @cindex SMP
1779 After setting targets, you can define a list of targets working in SMP.
1781 @example
1782 set _TARGETNAME_1 $_CHIPNAME.cpu1
1783 set _TARGETNAME_2 $_CHIPNAME.cpu2
1784 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1785 -coreid 0 -dbgbase $_DAP_DBG1
1786 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1787 -coreid 1 -dbgbase $_DAP_DBG2
1788 #define 2 targets working in smp.
1789 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1790 @end example
1791 In the above example on cortex_a, 2 cpus are working in SMP.
1792 In SMP only one GDB instance is created and :
1793 @itemize @bullet
1794 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1795 @item halt command triggers the halt of all targets in the list.
1796 @item resume command triggers the write context and the restart of all targets in the list.
1797 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1798 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1799 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1800 @end itemize
1802 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1803 command have been implemented.
1804 @itemize @bullet
1805 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1806 @item cortex_a smp_off : disable SMP mode, the current target is the one
1807 displayed in the GDB session, only this target is now controlled by GDB
1808 session. This behaviour is useful during system boot up.
1809 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1810 following example.
1811 @end itemize
1813 @example
1814 >cortex_a smp_gdb
1815 gdb coreid 0 -> -1
1816 #0 : coreid 0 is displayed to GDB ,
1817 #-> -1 : next resume triggers a real resume
1818 > cortex_a smp_gdb 1
1819 gdb coreid 0 -> 1
1820 #0 :coreid 0 is displayed to GDB ,
1821 #->1 : next resume displays coreid 1 to GDB
1822 > resume
1823 > cortex_a smp_gdb
1824 gdb coreid 1 -> 1
1825 #1 :coreid 1 is displayed to GDB ,
1826 #->1 : next resume displays coreid 1 to GDB
1827 > cortex_a smp_gdb -1
1828 gdb coreid 1 -> -1
1829 #1 :coreid 1 is displayed to GDB,
1830 #->-1 : next resume triggers a real resume
1831 @end example
1834 @subsection Chip Reset Setup
1836 As a rule, you should put the @command{reset_config} command
1837 into the board file. Most things you think you know about a
1838 chip can be tweaked by the board.
1840 Some chips have specific ways the TRST and SRST signals are
1841 managed. In the unusual case that these are @emph{chip specific}
1842 and can never be changed by board wiring, they could go here.
1843 For example, some chips can't support JTAG debugging without
1844 both signals.
1846 Provide a @code{reset-assert} event handler if you can.
1847 Such a handler uses JTAG operations to reset the target,
1848 letting this target config be used in systems which don't
1849 provide the optional SRST signal, or on systems where you
1850 don't want to reset all targets at once.
1851 Such a handler might write to chip registers to force a reset,
1852 use a JRC to do that (preferable -- the target may be wedged!),
1853 or force a watchdog timer to trigger.
1854 (For Cortex-M targets, this is not necessary. The target
1855 driver knows how to use trigger an NVIC reset when SRST is
1856 not available.)
1858 Some chips need special attention during reset handling if
1859 they're going to be used with JTAG.
1860 An example might be needing to send some commands right
1861 after the target's TAP has been reset, providing a
1862 @code{reset-deassert-post} event handler that writes a chip
1863 register to report that JTAG debugging is being done.
1864 Another would be reconfiguring the watchdog so that it stops
1865 counting while the core is halted in the debugger.
1867 JTAG clocking constraints often change during reset, and in
1868 some cases target config files (rather than board config files)
1869 are the right places to handle some of those issues.
1870 For example, immediately after reset most chips run using a
1871 slower clock than they will use later.
1872 That means that after reset (and potentially, as OpenOCD
1873 first starts up) they must use a slower JTAG clock rate
1874 than they will use later.
1875 @xref{jtagspeed,,JTAG Speed}.
1877 @quotation Important
1878 When you are debugging code that runs right after chip
1879 reset, getting these issues right is critical.
1880 In particular, if you see intermittent failures when
1881 OpenOCD verifies the scan chain after reset,
1882 look at how you are setting up JTAG clocking.
1883 @end quotation
1885 @anchor{theinittargetsprocedure}
1886 @subsection The init_targets procedure
1887 @cindex init_targets procedure
1889 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1890 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1891 procedure called @code{init_targets}, which will be executed when entering run stage
1892 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1893 Such procedure can be overridden by ``next level'' script (which sources the original).
1894 This concept facilitates code reuse when basic target config files provide generic configuration
1895 procedures and @code{init_targets} procedure, which can then be sourced and enhanced or changed in
1896 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1897 because sourcing them executes every initialization commands they provide.
1899 @example
1900 ### generic_file.cfg ###
1902 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1903 # basic initialization procedure ...
1904 @}
1906 proc init_targets @{@} @{
1907 # initializes generic chip with 4kB of flash and 1kB of RAM
1908 setup_my_chip MY_GENERIC_CHIP 4096 1024
1909 @}
1911 ### specific_file.cfg ###
1913 source [find target/generic_file.cfg]
1915 proc init_targets @{@} @{
1916 # initializes specific chip with 128kB of flash and 64kB of RAM
1917 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1918 @}
1919 @end example
1921 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1922 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1924 For an example of this scheme see LPC2000 target config files.
1926 The @code{init_boards} procedure is a similar concept concerning board config files
1927 (@xref{theinitboardprocedure,,The init_board procedure}.)
1929 @anchor{theinittargeteventsprocedure}
1930 @subsection The init_target_events procedure
1931 @cindex init_target_events procedure
1933 A special procedure called @code{init_target_events} is run just after
1934 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1935 procedure}.) and before @code{init_board}
1936 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1937 to set up default target events for the targets that do not have those
1938 events already assigned.
1940 @subsection ARM Core Specific Hacks
1942 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1943 special high speed download features - enable it.
1945 If present, the MMU, the MPU and the CACHE should be disabled.
1947 Some ARM cores are equipped with trace support, which permits
1948 examination of the instruction and data bus activity. Trace
1949 activity is controlled through an ``Embedded Trace Module'' (ETM)
1950 on one of the core's scan chains. The ETM emits voluminous data
1951 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1952 If you are using an external trace port,
1953 configure it in your board config file.
1954 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1955 configure it in your target config file.
1957 @example
1958 etm config $_TARGETNAME 16 normal full etb
1959 etb config $_TARGETNAME $_CHIPNAME.etb
1960 @end example
1962 @subsection Internal Flash Configuration
1964 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1966 @b{Never ever} in the ``target configuration file'' define any type of
1967 flash that is external to the chip. (For example a BOOT flash on
1968 Chip Select 0.) Such flash information goes in a board file - not
1969 the TARGET (chip) file.
1971 Examples:
1972 @itemize @bullet
1973 @item at91sam7x256 - has 256K flash YES enable it.
1974 @item str912 - has flash internal YES enable it.
1975 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1976 @item pxa270 - again - CS0 flash - it goes in the board file.
1977 @end itemize
1979 @anchor{translatingconfigurationfiles}
1980 @section Translating Configuration Files
1981 @cindex translation
1982 If you have a configuration file for another hardware debugger
1983 or toolset (Abatron, BDI2000, BDI3000, CCS,
1984 Lauterbach, SEGGER, Macraigor, etc.), translating
1985 it into OpenOCD syntax is often quite straightforward. The most tricky
1986 part of creating a configuration script is oftentimes the reset init
1987 sequence where e.g. PLLs, DRAM and the like is set up.
1989 One trick that you can use when translating is to write small
1990 Tcl procedures to translate the syntax into OpenOCD syntax. This
1991 can avoid manual translation errors and make it easier to
1992 convert other scripts later on.
1994 Example of transforming quirky arguments to a simple search and
1995 replace job:
1997 @example
1998 # Lauterbach syntax(?)
1999 #
2000 # Data.Set c15:0x042f %long 0x40000015
2001 #
2002 # OpenOCD syntax when using procedure below.
2003 #
2004 # setc15 0x01 0x00050078
2006 proc setc15 @{regs value@} @{
2007 global TARGETNAME
2009 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2011 arm mcr 15 [expr ($regs>>12)&0x7] \
2012 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2013 [expr ($regs>>8)&0x7] $value
2014 @}
2015 @end example
2019 @node Server Configuration
2020 @chapter Server Configuration
2021 @cindex initialization
2022 The commands here are commonly found in the openocd.cfg file and are
2023 used to specify what TCP/IP ports are used, and how GDB should be
2024 supported.
2026 @anchor{configurationstage}
2027 @section Configuration Stage
2028 @cindex configuration stage
2029 @cindex config command
2031 When the OpenOCD server process starts up, it enters a
2032 @emph{configuration stage} which is the only time that
2033 certain commands, @emph{configuration commands}, may be issued.
2034 Normally, configuration commands are only available
2035 inside startup scripts.
2037 In this manual, the definition of a configuration command is
2038 presented as a @emph{Config Command}, not as a @emph{Command}
2039 which may be issued interactively.
2040 The runtime @command{help} command also highlights configuration
2041 commands, and those which may be issued at any time.
2043 Those configuration commands include declaration of TAPs,
2044 flash banks,
2045 the interface used for JTAG communication,
2046 and other basic setup.
2047 The server must leave the configuration stage before it
2048 may access or activate TAPs.
2049 After it leaves this stage, configuration commands may no
2050 longer be issued.
2052 @anchor{enteringtherunstage}
2053 @section Entering the Run Stage
2055 The first thing OpenOCD does after leaving the configuration
2056 stage is to verify that it can talk to the scan chain
2057 (list of TAPs) which has been configured.
2058 It will warn if it doesn't find TAPs it expects to find,
2059 or finds TAPs that aren't supposed to be there.
2060 You should see no errors at this point.
2061 If you see errors, resolve them by correcting the
2062 commands you used to configure the server.
2063 Common errors include using an initial JTAG speed that's too
2064 fast, and not providing the right IDCODE values for the TAPs
2065 on the scan chain.
2067 Once OpenOCD has entered the run stage, a number of commands
2068 become available.
2069 A number of these relate to the debug targets you may have declared.
2070 For example, the @command{mww} command will not be available until
2071 a target has been successfully instantiated.
2072 If you want to use those commands, you may need to force
2073 entry to the run stage.
2075 @deffn {Config Command} init
2076 This command terminates the configuration stage and
2077 enters the run stage. This helps when you need to have
2078 the startup scripts manage tasks such as resetting the target,
2079 programming flash, etc. To reset the CPU upon startup, add "init" and
2080 "reset" at the end of the config script or at the end of the OpenOCD
2081 command line using the @option{-c} command line switch.
2083 If this command does not appear in any startup/configuration file
2084 OpenOCD executes the command for you after processing all
2085 configuration files and/or command line options.
2087 @b{NOTE:} This command normally occurs at or near the end of your
2088 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2089 targets ready. For example: If your openocd.cfg file needs to
2090 read/write memory on your target, @command{init} must occur before
2091 the memory read/write commands. This includes @command{nand probe}.
2092 @end deffn
2094 @deffn {Overridable Procedure} jtag_init
2095 This is invoked at server startup to verify that it can talk
2096 to the scan chain (list of TAPs) which has been configured.
2098 The default implementation first tries @command{jtag arp_init},
2099 which uses only a lightweight JTAG reset before examining the
2100 scan chain.
2101 If that fails, it tries again, using a harder reset
2102 from the overridable procedure @command{init_reset}.
2104 Implementations must have verified the JTAG scan chain before
2105 they return.
2106 This is done by calling @command{jtag arp_init}
2107 (or @command{jtag arp_init-reset}).
2108 @end deffn
2110 @anchor{tcpipports}
2111 @section TCP/IP Ports
2112 @cindex TCP port
2113 @cindex server
2114 @cindex port
2115 @cindex security
2116 The OpenOCD server accepts remote commands in several syntaxes.
2117 Each syntax uses a different TCP/IP port, which you may specify
2118 only during configuration (before those ports are opened).
2120 For reasons including security, you may wish to prevent remote
2121 access using one or more of these ports.
2122 In such cases, just specify the relevant port number as "disabled".
2123 If you disable all access through TCP/IP, you will need to
2124 use the command line @option{-pipe} option.
2126 @anchor{gdb_port}
2127 @deffn {Command} gdb_port [number]
2128 @cindex GDB server
2129 Normally gdb listens to a TCP/IP port, but GDB can also
2130 communicate via pipes(stdin/out or named pipes). The name
2131 "gdb_port" stuck because it covers probably more than 90% of
2132 the normal use cases.
2134 No arguments reports GDB port. "pipe" means listen to stdin
2135 output to stdout, an integer is base port number, "disabled"
2136 disables the gdb server.
2138 When using "pipe", also use log_output to redirect the log
2139 output to a file so as not to flood the stdin/out pipes.
2141 The -p/--pipe option is deprecated and a warning is printed
2142 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2144 Any other string is interpreted as named pipe to listen to.
2145 Output pipe is the same name as input pipe, but with 'o' appended,
2146 e.g. /var/gdb, /var/gdbo.
2148 The GDB port for the first target will be the base port, the
2149 second target will listen on gdb_port + 1, and so on.
2150 When not specified during the configuration stage,
2151 the port @var{number} defaults to 3333.
2152 When @var{number} is not a numeric value, incrementing it to compute
2153 the next port number does not work. In this case, specify the proper
2154 @var{number} for each target by using the option @code{-gdb-port} of the
2155 commands @command{target create} or @command{$target_name configure}.
2156 @xref{gdbportoverride,,option -gdb-port}.
2158 Note: when using "gdb_port pipe", increasing the default remote timeout in
2159 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2160 cause initialization to fail with "Unknown remote qXfer reply: OK".
2161 @end deffn
2163 @deffn {Command} tcl_port [number]
2164 Specify or query the port used for a simplified RPC
2165 connection that can be used by clients to issue TCL commands and get the
2166 output from the Tcl engine.
2167 Intended as a machine interface.
2168 When not specified during the configuration stage,
2169 the port @var{number} defaults to 6666.
2170 When specified as "disabled", this service is not activated.
2171 @end deffn
2173 @deffn {Command} telnet_port [number]
2174 Specify or query the
2175 port on which to listen for incoming telnet connections.
2176 This port is intended for interaction with one human through TCL commands.
2177 When not specified during the configuration stage,
2178 the port @var{number} defaults to 4444.
2179 When specified as "disabled", this service is not activated.
2180 @end deffn
2182 @anchor{gdbconfiguration}
2183 @section GDB Configuration
2184 @cindex GDB
2185 @cindex GDB configuration
2186 You can reconfigure some GDB behaviors if needed.
2187 The ones listed here are static and global.
2188 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2189 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2191 @anchor{gdbbreakpointoverride}
2192 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2193 Force breakpoint type for gdb @command{break} commands.
2194 This option supports GDB GUIs which don't
2195 distinguish hard versus soft breakpoints, if the default OpenOCD and
2196 GDB behaviour is not sufficient. GDB normally uses hardware
2197 breakpoints if the memory map has been set up for flash regions.
2198 @end deffn
2200 @anchor{gdbflashprogram}
2201 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2202 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2203 vFlash packet is received.
2204 The default behaviour is @option{enable}.
2205 @end deffn
2207 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2208 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2209 requested. GDB will then know when to set hardware breakpoints, and program flash
2210 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2211 for flash programming to work.
2212 Default behaviour is @option{enable}.
2213 @xref{gdbflashprogram,,gdb_flash_program}.
2214 @end deffn
2216 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2217 Specifies whether data aborts cause an error to be reported
2218 by GDB memory read packets.
2219 The default behaviour is @option{disable};
2220 use @option{enable} see these errors reported.
2221 @end deffn
2223 @deffn {Config Command} gdb_report_register_access_error (@option{enable}|@option{disable})
2224 Specifies whether register accesses requested by GDB register read/write
2225 packets report errors or not.
2226 The default behaviour is @option{disable};
2227 use @option{enable} see these errors reported.
2228 @end deffn
2230 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2231 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2232 The default behaviour is @option{enable}.
2233 @end deffn
2235 @deffn {Command} gdb_save_tdesc
2236 Saves the target description file to the local file system.
2238 The file name is @i{target_name}.xml.
2239 @end deffn
2241 @anchor{eventpolling}
2242 @section Event Polling
2244 Hardware debuggers are parts of asynchronous systems,
2245 where significant events can happen at any time.
2246 The OpenOCD server needs to detect some of these events,
2247 so it can report them to through TCL command line
2248 or to GDB.
2250 Examples of such events include:
2252 @itemize
2253 @item One of the targets can stop running ... maybe it triggers
2254 a code breakpoint or data watchpoint, or halts itself.
2255 @item Messages may be sent over ``debug message'' channels ... many
2256 targets support such messages sent over JTAG,
2257 for receipt by the person debugging or tools.
2258 @item Loss of power ... some adapters can detect these events.
2259 @item Resets not issued through JTAG ... such reset sources
2260 can include button presses or other system hardware, sometimes
2261 including the target itself (perhaps through a watchdog).
2262 @item Debug instrumentation sometimes supports event triggering
2263 such as ``trace buffer full'' (so it can quickly be emptied)
2264 or other signals (to correlate with code behavior).
2265 @end itemize
2267 None of those events are signaled through standard JTAG signals.
2268 However, most conventions for JTAG connectors include voltage
2269 level and system reset (SRST) signal detection.
2270 Some connectors also include instrumentation signals, which
2271 can imply events when those signals are inputs.
2273 In general, OpenOCD needs to periodically check for those events,
2274 either by looking at the status of signals on the JTAG connector
2275 or by sending synchronous ``tell me your status'' JTAG requests
2276 to the various active targets.
2277 There is a command to manage and monitor that polling,
2278 which is normally done in the background.
2280 @deffn Command poll [@option{on}|@option{off}]
2281 Poll the current target for its current state.
2282 (Also, @pxref{targetcurstate,,target curstate}.)
2283 If that target is in debug mode, architecture
2284 specific information about the current state is printed.
2285 An optional parameter
2286 allows background polling to be enabled and disabled.
2288 You could use this from the TCL command shell, or
2289 from GDB using @command{monitor poll} command.
2290 Leave background polling enabled while you're using GDB.
2291 @example
2292 > poll
2293 background polling: on
2294 target state: halted
2295 target halted in ARM state due to debug-request, \
2296 current mode: Supervisor
2297 cpsr: 0x800000d3 pc: 0x11081bfc
2298 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2299 >
2300 @end example
2301 @end deffn
2303 @node Debug Adapter Configuration
2304 @chapter Debug Adapter Configuration
2305 @cindex config file, interface
2306 @cindex interface config file
2308 Correctly installing OpenOCD includes making your operating system give
2309 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2310 are used to select which one is used, and to configure how it is used.
2312 @quotation Note
2313 Because OpenOCD started out with a focus purely on JTAG, you may find
2314 places where it wrongly presumes JTAG is the only transport protocol
2315 in use. Be aware that recent versions of OpenOCD are removing that
2316 limitation. JTAG remains more functional than most other transports.
2317 Other transports do not support boundary scan operations, or may be
2318 specific to a given chip vendor. Some might be usable only for
2319 programming flash memory, instead of also for debugging.
2320 @end quotation
2322 Debug Adapters/Interfaces/Dongles are normally configured
2323 through commands in an interface configuration
2324 file which is sourced by your @file{openocd.cfg} file, or
2325 through a command line @option{-f interface/....cfg} option.
2327 @example
2328 source [find interface/olimex-jtag-tiny.cfg]
2329 @end example
2331 These commands tell
2332 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2333 A few cases are so simple that you only need to say what driver to use:
2335 @example
2336 # jlink interface
2337 interface jlink
2338 @end example
2340 Most adapters need a bit more configuration than that.
2343 @section Interface Configuration
2345 The interface command tells OpenOCD what type of debug adapter you are
2346 using. Depending on the type of adapter, you may need to use one or
2347 more additional commands to further identify or configure the adapter.
2349 @deffn {Config Command} {interface} name
2350 Use the interface driver @var{name} to connect to the
2351 target.
2352 @end deffn
2354 @deffn Command {interface_list}
2355 List the debug adapter drivers that have been built into
2356 the running copy of OpenOCD.
2357 @end deffn
2358 @deffn Command {interface transports} transport_name+
2359 Specifies the transports supported by this debug adapter.
2360 The adapter driver builds-in similar knowledge; use this only
2361 when external configuration (such as jumpering) changes what
2362 the hardware can support.
2363 @end deffn
2367 @deffn Command {adapter_name}
2368 Returns the name of the debug adapter driver being used.
2369 @end deffn
2371 @anchor{adapter_usb_location}
2372 @deffn Command {adapter usb location} <bus>-<port>[.<port>]...
2373 Specifies the physical USB port of the adapter to use. The path
2374 roots at @var{bus} and walks down the physical ports, with each
2375 @var{port} option specifying a deeper level in the bus topology, the last
2376 @var{port} denoting where the target adapter is actually plugged.
2377 The USB bus topology can be queried with the command @emph{lsusb -t} or @emph{dmesg}.
2379 This command is only available if your libusb1 is at least version 1.0.16.
2380 @end deffn
2382 @section Interface Drivers
2384 Each of the interface drivers listed here must be explicitly
2385 enabled when OpenOCD is configured, in order to be made
2386 available at run time.
2388 @deffn {Interface Driver} {amt_jtagaccel}
2389 Amontec Chameleon in its JTAG Accelerator configuration,
2390 connected to a PC's EPP mode parallel port.
2391 This defines some driver-specific commands:
2393 @deffn {Config Command} {parport_port} number
2394 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2395 the number of the @file{/dev/parport} device.
2396 @end deffn
2398 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2399 Displays status of RTCK option.
2400 Optionally sets that option first.
2401 @end deffn
2402 @end deffn
2404 @deffn {Interface Driver} {arm-jtag-ew}
2405 Olimex ARM-JTAG-EW USB adapter
2406 This has one driver-specific command:
2408 @deffn Command {armjtagew_info}
2409 Logs some status
2410 @end deffn
2411 @end deffn
2413 @deffn {Interface Driver} {at91rm9200}
2414 Supports bitbanged JTAG from the local system,
2415 presuming that system is an Atmel AT91rm9200
2416 and a specific set of GPIOs is used.
2417 @c command: at91rm9200_device NAME
2418 @c chooses among list of bit configs ... only one option
2419 @end deffn
2421 @deffn {Interface Driver} {cmsis-dap}
2422 ARM CMSIS-DAP compliant based adapter.
2424 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2425 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2426 the driver will attempt to auto detect the CMSIS-DAP device.
2427 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2428 @example
2429 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2430 @end example
2431 @end deffn
2433 @deffn {Config Command} {cmsis_dap_serial} [serial]
2434 Specifies the @var{serial} of the CMSIS-DAP device to use.
2435 If not specified, serial numbers are not considered.
2436 @end deffn
2438 @deffn {Command} {cmsis-dap info}
2439 Display various device information, like hardware version, firmware version, current bus status.
2440 @end deffn
2441 @end deffn
2443 @deffn {Interface Driver} {dummy}
2444 A dummy software-only driver for debugging.
2445 @end deffn
2447 @deffn {Interface Driver} {ep93xx}
2448 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2449 @end deffn
2451 @deffn {Interface Driver} {ftdi}
2452 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2453 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2455 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2456 bypassing intermediate libraries like libftdi or D2XX.
2458 Support for new FTDI based adapters can be added completely through
2459 configuration files, without the need to patch and rebuild OpenOCD.
2461 The driver uses a signal abstraction to enable Tcl configuration files to
2462 define outputs for one or several FTDI GPIO. These outputs can then be
2463 controlled using the @command{ftdi_set_signal} command. Special signal names
2464 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2465 will be used for their customary purpose. Inputs can be read using the
2466 @command{ftdi_get_signal} command.
2468 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2469 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2470 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2471 required by the protocol, to tell the adapter to drive the data output onto
2472 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2474 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2475 be controlled differently. In order to support tristateable signals such as
2476 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2477 signal. The following output buffer configurations are supported:
2479 @itemize @minus
2480 @item Push-pull with one FTDI output as (non-)inverted data line
2481 @item Open drain with one FTDI output as (non-)inverted output-enable
2482 @item Tristate with one FTDI output as (non-)inverted data line and another
2483 FTDI output as (non-)inverted output-enable
2484 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2485 switching data and direction as necessary
2486 @end itemize
2488 These interfaces have several commands, used to configure the driver
2489 before initializing the JTAG scan chain:
2491 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2492 The vendor ID and product ID of the adapter. Up to eight
2493 [@var{vid}, @var{pid}] pairs may be given, e.g.
2494 @example
2495 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2496 @end example
2497 @end deffn
2499 @deffn {Config Command} {ftdi_device_desc} description
2500 Provides the USB device description (the @emph{iProduct string})
2501 of the adapter. If not specified, the device description is ignored
2502 during device selection.
2503 @end deffn
2505 @deffn {Config Command} {ftdi_serial} serial-number
2506 Specifies the @var{serial-number} of the adapter to use,
2507 in case the vendor provides unique IDs and more than one adapter
2508 is connected to the host.
2509 If not specified, serial numbers are not considered.
2510 (Note that USB serial numbers can be arbitrary Unicode strings,
2511 and are not restricted to containing only decimal digits.)
2512 @end deffn
2514 @deffn {Config Command} {ftdi_location} <bus>-<port>[.<port>]...
2515 @emph{DEPRECATED -- avoid using this.
2516 Use the @xref{adapter_usb_location, adapter usb location} command instead.}
2518 Specifies the physical USB port of the adapter to use. The path
2519 roots at @var{bus} and walks down the physical ports, with each
2520 @var{port} option specifying a deeper level in the bus topology, the last
2521 @var{port} denoting where the target adapter is actually plugged.
2522 The USB bus topology can be queried with the command @emph{lsusb -t}.
2524 This command is only available if your libusb1 is at least version 1.0.16.
2525 @end deffn
2527 @deffn {Config Command} {ftdi_channel} channel
2528 Selects the channel of the FTDI device to use for MPSSE operations. Most
2529 adapters use the default, channel 0, but there are exceptions.
2530 @end deffn
2532 @deffn {Config Command} {ftdi_layout_init} data direction
2533 Specifies the initial values of the FTDI GPIO data and direction registers.
2534 Each value is a 16-bit number corresponding to the concatenation of the high
2535 and low FTDI GPIO registers. The values should be selected based on the
2536 schematics of the adapter, such that all signals are set to safe levels with
2537 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2538 and initially asserted reset signals.
2539 @end deffn
2541 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2542 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2543 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2544 register bitmasks to tell the driver the connection and type of the output
2545 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2546 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2547 used with inverting data inputs and @option{-data} with non-inverting inputs.
2548 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2549 not-output-enable) input to the output buffer is connected. The options
2550 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2551 with the method @command{ftdi_get_signal}.
2553 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2554 simple open-collector transistor driver would be specified with @option{-oe}
2555 only. In that case the signal can only be set to drive low or to Hi-Z and the
2556 driver will complain if the signal is set to drive high. Which means that if
2557 it's a reset signal, @command{reset_config} must be specified as
2558 @option{srst_open_drain}, not @option{srst_push_pull}.
2560 A special case is provided when @option{-data} and @option{-oe} is set to the
2561 same bitmask. Then the FTDI pin is considered being connected straight to the
2562 target without any buffer. The FTDI pin is then switched between output and
2563 input as necessary to provide the full set of low, high and Hi-Z
2564 characteristics. In all other cases, the pins specified in a signal definition
2565 are always driven by the FTDI.
2567 If @option{-alias} or @option{-nalias} is used, the signal is created
2568 identical (or with data inverted) to an already specified signal
2569 @var{name}.
2570 @end deffn
2572 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2573 Set a previously defined signal to the specified level.
2574 @itemize @minus
2575 @item @option{0}, drive low
2576 @item @option{1}, drive high
2577 @item @option{z}, set to high-impedance
2578 @end itemize
2579 @end deffn
2581 @deffn {Command} {ftdi_get_signal} name
2582 Get the value of a previously defined signal.
2583 @end deffn
2585 @deffn {Command} {ftdi_tdo_sample_edge} @option{rising}|@option{falling}
2586 Configure TCK edge at which the adapter samples the value of the TDO signal
2588 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2589 peculiar at high JTAG clock speeds. However, FTDI chips offer a possibility to sample
2590 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2591 stability at higher JTAG clocks.
2592 @itemize @minus
2593 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2594 @item @option{falling}, sample TDO on falling edge of TCK
2595 @end itemize
2596 @end deffn
2598 For example adapter definitions, see the configuration files shipped in the
2599 @file{interface/ftdi} directory.
2601 @end deffn
2603 @deffn {Interface Driver} {ft232r}
2604 This driver is implementing synchronous bitbang mode of an FTDI FT232R,
2605 FT230X, FT231X and similar USB UART bridge ICs by reusing RS232 signals as GPIO.
2606 It currently doesn't support using CBUS pins as GPIO.
2608 List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
2609 @itemize @minus
2610 @item RXD(5) - TDI
2611 @item TXD(1) - TCK
2612 @item RTS(3) - TDO
2613 @item CTS(11) - TMS
2614 @item DTR(2) - TRST
2615 @item DCD(10) - SRST
2616 @end itemize
2618 User can change default pinout by supplying configuration
2619 commands with GPIO numbers or RS232 signal names.
2620 GPIO numbers correspond to bit numbers in FTDI GPIO register.
2621 They differ from physical pin numbers.
2622 For details see actual FTDI chip datasheets.
2623 Every JTAG line must be configured to unique GPIO number
2624 different than any other JTAG line, even those lines
2625 that are sometimes not used like TRST or SRST.
2627 FT232R
2628 @itemize @minus
2629 @item bit 7 - RI
2630 @item bit 6 - DCD
2631 @item bit 5 - DSR
2632 @item bit 4 - DTR
2633 @item bit 3 - CTS
2634 @item bit 2 - RTS
2635 @item bit 1 - RXD
2636 @item bit 0 - TXD
2637 @end itemize
2639 These interfaces have several commands, used to configure the driver
2640 before initializing the JTAG scan chain:
2642 @deffn {Config Command} {ft232r_vid_pid} @var{vid} @var{pid}
2643 The vendor ID and product ID of the adapter. If not specified, default
2644 0x0403:0x6001 is used.
2645 @end deffn
2647 @deffn {Config Command} {ft232r_serial_desc} @var{serial}
2648 Specifies the @var{serial} of the adapter to use, in case the
2649 vendor provides unique IDs and more than one adapter is connected to
2650 the host. If not specified, serial numbers are not considered.
2651 @end deffn
2653 @deffn {Config Command} {ft232r_jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
2654 Set four JTAG GPIO numbers at once.
2655 If not specified, default 0 3 1 2 or TXD CTS RXD RTS is used.
2656 @end deffn
2658 @deffn {Config Command} {ft232r_tck_num} @var{tck}
2659 Set TCK GPIO number. If not specified, default 0 or TXD is used.
2660 @end deffn
2662 @deffn {Config Command} {ft232r_tms_num} @var{tms}
2663 Set TMS GPIO number. If not specified, default 3 or CTS is used.
2664 @end deffn
2666 @deffn {Config Command} {ft232r_tdi_num} @var{tdi}
2667 Set TDI GPIO number. If not specified, default 1 or RXD is used.
2668 @end deffn
2670 @deffn {Config Command} {ft232r_tdo_num} @var{tdo}
2671 Set TDO GPIO number. If not specified, default 2 or RTS is used.
2672 @end deffn
2674 @deffn {Config Command} {ft232r_trst_num} @var{trst}
2675 Set TRST GPIO number. If not specified, default 4 or DTR is used.
2676 @end deffn
2678 @deffn {Config Command} {ft232r_srst_num} @var{srst}
2679 Set SRST GPIO number. If not specified, default 6 or DCD is used.
2680 @end deffn
2682 @deffn {Config Command} {ft232r_restore_serial} @var{word}
2683 Restore serial port after JTAG. This USB bitmode control word
2684 (16-bit) will be sent before quit. Lower byte should
2685 set GPIO direction register to a "sane" state:
2686 0x15 for TXD RTS DTR as outputs (1), others as inputs (0). Higher
2687 byte is usually 0 to disable bitbang mode.
2688 When kernel driver reattaches, serial port should continue to work.
2689 Value 0xFFFF disables sending control word and serial port,
2690 then kernel driver will not reattach.
2691 If not specified, default 0xFFFF is used.
2692 @end deffn
2694 @end deffn
2696 @deffn {Interface Driver} {remote_bitbang}
2697 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2698 with a remote process and sends ASCII encoded bitbang requests to that process
2699 instead of directly driving JTAG.
2701 The remote_bitbang driver is useful for debugging software running on
2702 processors which are being simulated.
2704 @deffn {Config Command} {remote_bitbang_port} number
2705 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2706 sockets instead of TCP.
2707 @end deffn
2709 @deffn {Config Command} {remote_bitbang_host} hostname
2710 Specifies the hostname of the remote process to connect to using TCP, or the
2711 name of the UNIX socket to use if remote_bitbang_port is 0.
2712 @end deffn
2714 For example, to connect remotely via TCP to the host foobar you might have
2715 something like:
2717 @example
2718 interface remote_bitbang
2719 remote_bitbang_port 3335
2720 remote_bitbang_host foobar
2721 @end example
2723 To connect to another process running locally via UNIX sockets with socket
2724 named mysocket:
2726 @example
2727 interface remote_bitbang
2728 remote_bitbang_port 0
2729 remote_bitbang_host mysocket
2730 @end example
2731 @end deffn
2733 @deffn {Interface Driver} {usb_blaster}
2734 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2735 for FTDI chips. These interfaces have several commands, used to
2736 configure the driver before initializing the JTAG scan chain:
2738 @deffn {Config Command} {usb_blaster_device_desc} description
2739 Provides the USB device description (the @emph{iProduct string})
2740 of the FTDI FT245 device. If not
2741 specified, the FTDI default value is used. This setting is only valid
2742 if compiled with FTD2XX support.
2743 @end deffn
2745 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2746 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2747 default values are used.
2748 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2749 Altera USB-Blaster (default):
2750 @example
2751 usb_blaster_vid_pid 0x09FB 0x6001
2752 @end example
2753 The following VID/PID is for Kolja Waschk's USB JTAG:
2754 @example
2755 usb_blaster_vid_pid 0x16C0 0x06AD
2756 @end example
2757 @end deffn
2759 @deffn {Command} {usb_blaster_pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2760 Sets the state or function of the unused GPIO pins on USB-Blasters
2761 (pins 6 and 8 on the female JTAG header). These pins can be used as
2762 SRST and/or TRST provided the appropriate connections are made on the
2763 target board.
2765 For example, to use pin 6 as SRST:
2766 @example
2767 usb_blaster_pin pin6 s
2768 reset_config srst_only
2769 @end example
2770 @end deffn
2772 @deffn {Command} {usb_blaster_lowlevel_driver} (@option{ftdi}|@option{ublast2})
2773 Chooses the low level access method for the adapter. If not specified,
2774 @option{ftdi} is selected unless it wasn't enabled during the
2775 configure stage. USB-Blaster II needs @option{ublast2}.
2776 @end deffn
2778 @deffn {Command} {usb_blaster_firmware} @var{path}
2779 This command specifies @var{path} to access USB-Blaster II firmware
2780 image. To be used with USB-Blaster II only.
2781 @end deffn
2783 @end deffn
2785 @deffn {Interface Driver} {gw16012}
2786 Gateworks GW16012 JTAG programmer.
2787 This has one driver-specific command:
2789 @deffn {Config Command} {parport_port} [port_number]
2790 Display either the address of the I/O port
2791 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2792 If a parameter is provided, first switch to use that port.
2793 This is a write-once setting.
2794 @end deffn
2795 @end deffn
2797 @deffn {Interface Driver} {jlink}
2798 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2799 transports.
2801 @quotation Compatibility Note
2802 SEGGER released many firmware versions for the many hardware versions they
2803 produced. OpenOCD was extensively tested and intended to run on all of them,
2804 but some combinations were reported as incompatible. As a general
2805 recommendation, it is advisable to use the latest firmware version
2806 available for each hardware version. However the current V8 is a moving
2807 target, and SEGGER firmware versions released after the OpenOCD was
2808 released may not be compatible. In such cases it is recommended to
2809 revert to the last known functional version. For 0.5.0, this is from
2810 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2811 version is from "May 3 2012 18:36:22", packed with 4.46f.
2812 @end quotation
2814 @deffn {Command} {jlink hwstatus}
2815 Display various hardware related information, for example target voltage and pin
2816 states.
2817 @end deffn
2818 @deffn {Command} {jlink freemem}
2819 Display free device internal memory.
2820 @end deffn
2821 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2822 Set the JTAG command version to be used. Without argument, show the actual JTAG
2823 command version.
2824 @end deffn
2825 @deffn {Command} {jlink config}
2826 Display the device configuration.
2827 @end deffn
2828 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2829 Set the target power state on JTAG-pin 19. Without argument, show the target
2830 power state.
2831 @end deffn
2832 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2833 Set the MAC address of the device. Without argument, show the MAC address.
2834 @end deffn
2835 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2836 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2837 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2838 IP configuration.
2839 @end deffn
2840 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2841 Set the USB address of the device. This will also change the USB Product ID
2842 (PID) of the device. Without argument, show the USB address.
2843 @end deffn
2844 @deffn {Command} {jlink config reset}
2845 Reset the current configuration.
2846 @end deffn
2847 @deffn {Command} {jlink config write}
2848 Write the current configuration to the internal persistent storage.
2849 @end deffn
2850 @deffn {Command} {jlink emucom write <channel> <data>}
2851 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2852 pairs.
2854 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2855 the EMUCOM channel 0x10:
2856 @example
2857 > jlink emucom write 0x10 aa0b23
2858 @end example
2859 @end deffn
2860 @deffn {Command} {jlink emucom read <channel> <length>}
2861 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2862 pairs.
2864 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2865 @example
2866 > jlink emucom read 0x0 4
2867 77a90000
2868 @end example
2869 @end deffn
2870 @deffn {Config} {jlink usb} <@option{0} to @option{3}>
2871 Set the USB address of the interface, in case more than one adapter is connected
2872 to the host. If not specified, USB addresses are not considered. Device
2873 selection via USB address is deprecated and the serial number should be used
2874 instead.
2876 As a configuration command, it can be used only before 'init'.
2877 @end deffn
2878 @deffn {Config} {jlink serial} <serial number>
2879 Set the serial number of the interface, in case more than one adapter is
2880 connected to the host. If not specified, serial numbers are not considered.
2882 As a configuration command, it can be used only before 'init'.
2883 @end deffn
2884 @end deffn
2886 @deffn {Interface Driver} {kitprog}
2887 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2888 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2889 families, but it is possible to use it with some other devices. If you are using
2890 this adapter with a PSoC or a PRoC, you may need to add
2891 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2892 configuration script.
2894 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2895 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2896 be used with this driver, and must either be used with the cmsis-dap driver or
2897 switched back to KitProg mode. See the Cypress KitProg User Guide for
2898 instructions on how to switch KitProg modes.
2900 Known limitations:
2901 @itemize @bullet
2902 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2903 and 2.7 MHz.
2904 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2905 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2906 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2907 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2908 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2909 SWD sequence must be sent after every target reset in order to re-establish
2910 communications with the target.
2911 @item Due in part to the limitation above, KitProg devices with firmware below
2912 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
2913 communicate with PSoC 5LP devices. This is because, assuming debug is not
2914 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
2915 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
2916 could only be sent with an acquisition sequence.
2917 @end itemize
2919 @deffn {Config Command} {kitprog_init_acquire_psoc}
2920 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
2921 Please be aware that the acquisition sequence hard-resets the target.
2922 @end deffn
2924 @deffn {Config Command} {kitprog_serial} serial
2925 Select a KitProg device by its @var{serial}. If left unspecified, the first
2926 device detected by OpenOCD will be used.
2927 @end deffn
2929 @deffn {Command} {kitprog acquire_psoc}
2930 Run a PSoC acquisition sequence immediately. Typically, this should not be used
2931 outside of the target-specific configuration scripts since it hard-resets the
2932 target as a side-effect.
2933 This is necessary for "reset halt" on some PSoC 4 series devices.
2934 @end deffn
2936 @deffn {Command} {kitprog info}
2937 Display various adapter information, such as the hardware version, firmware
2938 version, and target voltage.
2939 @end deffn
2940 @end deffn
2942 @deffn {Interface Driver} {parport}
2943 Supports PC parallel port bit-banging cables:
2944 Wigglers, PLD download cable, and more.
2945 These interfaces have several commands, used to configure the driver
2946 before initializing the JTAG scan chain:
2948 @deffn {Config Command} {parport_cable} name
2949 Set the layout of the parallel port cable used to connect to the target.
2950 This is a write-once setting.
2951 Currently valid cable @var{name} values include:
2953 @itemize @minus
2954 @item @b{altium} Altium Universal JTAG cable.
2955 @item @b{arm-jtag} Same as original wiggler except SRST and
2956 TRST connections reversed and TRST is also inverted.
2957 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2958 in configuration mode. This is only used to
2959 program the Chameleon itself, not a connected target.
2960 @item @b{dlc5} The Xilinx Parallel cable III.
2961 @item @b{flashlink} The ST Parallel cable.
2962 @item @b{lattice} Lattice ispDOWNLOAD Cable
2963 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2964 some versions of
2965 Amontec's Chameleon Programmer. The new version available from
2966 the website uses the original Wiggler layout ('@var{wiggler}')
2967 @item @b{triton} The parallel port adapter found on the
2968 ``Karo Triton 1 Development Board''.
2969 This is also the layout used by the HollyGates design
2970 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2971 @item @b{wiggler} The original Wiggler layout, also supported by
2972 several clones, such as the Olimex ARM-JTAG
2973 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2974 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2975 @end itemize
2976 @end deffn
2978 @deffn {Config Command} {parport_port} [port_number]
2979 Display either the address of the I/O port
2980 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2981 If a parameter is provided, first switch to use that port.
2982 This is a write-once setting.
2984 When using PPDEV to access the parallel port, use the number of the parallel port:
2985 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2986 you may encounter a problem.
2987 @end deffn
2989 @deffn Command {parport_toggling_time} [nanoseconds]
2990 Displays how many nanoseconds the hardware needs to toggle TCK;
2991 the parport driver uses this value to obey the
2992 @command{adapter_khz} configuration.
2993 When the optional @var{nanoseconds} parameter is given,
2994 that setting is changed before displaying the current value.
2996 The default setting should work reasonably well on commodity PC hardware.
2997 However, you may want to calibrate for your specific hardware.
2998 @quotation Tip
2999 To measure the toggling time with a logic analyzer or a digital storage
3000 oscilloscope, follow the procedure below:
3001 @example
3002 > parport_toggling_time 1000
3003 > adapter_khz 500
3004 @end example
3005 This sets the maximum JTAG clock speed of the hardware, but
3006 the actual speed probably deviates from the requested 500 kHz.
3007 Now, measure the time between the two closest spaced TCK transitions.
3008 You can use @command{runtest 1000} or something similar to generate a
3009 large set of samples.
3010 Update the setting to match your measurement:
3011 @example
3012 > parport_toggling_time <measured nanoseconds>
3013 @end example
3014 Now the clock speed will be a better match for @command{adapter_khz rate}
3015 commands given in OpenOCD scripts and event handlers.
3017 You can do something similar with many digital multimeters, but note
3018 that you'll probably need to run the clock continuously for several
3019 seconds before it decides what clock rate to show. Adjust the
3020 toggling time up or down until the measured clock rate is a good
3021 match for the adapter_khz rate you specified; be conservative.
3022 @end quotation
3023 @end deffn
3025 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
3026 This will configure the parallel driver to write a known
3027 cable-specific value to the parallel interface on exiting OpenOCD.
3028 @end deffn
3030 For example, the interface configuration file for a
3031 classic ``Wiggler'' cable on LPT2 might look something like this:
3033 @example
3034 interface parport
3035 parport_port 0x278
3036 parport_cable wiggler
3037 @end example
3038 @end deffn
3040 @deffn {Interface Driver} {presto}
3041 ASIX PRESTO USB JTAG programmer.
3042 @deffn {Config Command} {presto_serial} serial_string
3043 Configures the USB serial number of the Presto device to use.
3044 @end deffn
3045 @end deffn
3047 @deffn {Interface Driver} {rlink}
3048 Raisonance RLink USB adapter
3049 @end deffn
3051 @deffn {Interface Driver} {usbprog}
3052 usbprog is a freely programmable USB adapter.
3053 @end deffn
3055 @deffn {Interface Driver} {vsllink}
3056 vsllink is part of Versaloon which is a versatile USB programmer.
3058 @quotation Note
3059 This defines quite a few driver-specific commands,
3060 which are not currently documented here.
3061 @end quotation
3062 @end deffn
3064 @anchor{hla_interface}
3065 @deffn {Interface Driver} {hla}
3066 This is a driver that supports multiple High Level Adapters.
3067 This type of adapter does not expose some of the lower level api's
3068 that OpenOCD would normally use to access the target.
3070 Currently supported adapters include the STMicroelectronics ST-LINK and TI ICDI.
3071 ST-LINK firmware version >= V2.J21.S4 recommended due to issues with earlier
3072 versions of firmware where serial number is reset after first use. Suggest
3073 using ST firmware update utility to upgrade ST-LINK firmware even if current
3074 version reported is V2.J21.S4.
3076 @deffn {Config Command} {hla_device_desc} description
3077 Currently Not Supported.
3078 @end deffn
3080 @deffn {Config Command} {hla_serial} serial
3081 Specifies the serial number of the adapter.
3082 @end deffn
3084 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
3085 Specifies the adapter layout to use.
3086 @end deffn
3088 @deffn {Config Command} {hla_vid_pid} [vid pid]+
3089 Pairs of vendor IDs and product IDs of the device.
3090 @end deffn
3092 @deffn {Command} {hla_command} command
3093 Execute a custom adapter-specific command. The @var{command} string is
3094 passed as is to the underlying adapter layout handler.
3095 @end deffn
3096 @end deffn
3098 @deffn {Interface Driver} {opendous}
3099 opendous-jtag is a freely programmable USB adapter.
3100 @end deffn
3102 @deffn {Interface Driver} {ulink}
3103 This is the Keil ULINK v1 JTAG debugger.
3104 @end deffn
3106 @deffn {Interface Driver} {ZY1000}
3107 This is the Zylin ZY1000 JTAG debugger.
3108 @end deffn
3110 @quotation Note
3111 This defines some driver-specific commands,
3112 which are not currently documented here.
3113 @end quotation
3115 @deffn Command power [@option{on}|@option{off}]
3116 Turn power switch to target on/off.
3117 No arguments: print status.
3118 @end deffn
3120 @deffn {Interface Driver} {bcm2835gpio}
3121 This SoC is present in Raspberry Pi which is a cheap single-board computer
3122 exposing some GPIOs on its expansion header.
3124 The driver accesses memory-mapped GPIO peripheral registers directly
3125 for maximum performance, but the only possible race condition is for
3126 the pins' modes/muxing (which is highly unlikely), so it should be
3127 able to coexist nicely with both sysfs bitbanging and various
3128 peripherals' kernel drivers. The driver restores the previous
3129 configuration on exit.
3131 See @file{interface/raspberrypi-native.cfg} for a sample config and
3132 pinout.
3134 @end deffn
3136 @deffn {Interface Driver} {imx_gpio}
3137 i.MX SoC is present in many community boards. Wandboard is an example
3138 of the one which is most popular.
3140 This driver is mostly the same as bcm2835gpio.
3142 See @file{interface/imx-native.cfg} for a sample config and
3143 pinout.
3145 @end deffn
3148 @deffn {Interface Driver} {openjtag}
3149 OpenJTAG compatible USB adapter.
3150 This defines some driver-specific commands:
3152 @deffn {Config Command} {openjtag_variant} variant
3153 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
3154 Currently valid @var{variant} values include:
3156 @itemize @minus
3157 @item @b{standard} Standard variant (default).
3158 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3159 (see @uref{http://www.cypress.com/?rID=82870}).
3160 @end itemize
3161 @end deffn
3163 @deffn {Config Command} {openjtag_device_desc} string
3164 The USB device description string of the adapter.
3165 This value is only used with the standard variant.
3166 @end deffn
3167 @end deffn
3169 @section Transport Configuration
3170 @cindex Transport
3171 As noted earlier, depending on the version of OpenOCD you use,
3172 and the debug adapter you are using,
3173 several transports may be available to
3174 communicate with debug targets (or perhaps to program flash memory).
3175 @deffn Command {transport list}
3176 displays the names of the transports supported by this
3177 version of OpenOCD.
3178 @end deffn
3180 @deffn Command {transport select} @option{transport_name}
3181 Select which of the supported transports to use in this OpenOCD session.
3183 When invoked with @option{transport_name}, attempts to select the named
3184 transport. The transport must be supported by the debug adapter
3185 hardware and by the version of OpenOCD you are using (including the
3186 adapter's driver).
3188 If no transport has been selected and no @option{transport_name} is
3189 provided, @command{transport select} auto-selects the first transport
3190 supported by the debug adapter.
3192 @command{transport select} always returns the name of the session's selected
3193 transport, if any.
3194 @end deffn
3196 @subsection JTAG Transport
3197 @cindex JTAG
3198 JTAG is the original transport supported by OpenOCD, and most
3199 of the OpenOCD commands support it.
3200 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3201 each of which must be explicitly declared.
3202 JTAG supports both debugging and boundary scan testing.
3203 Flash programming support is built on top of debug support.
3205 JTAG transport is selected with the command @command{transport select
3206 jtag}. Unless your adapter uses @ref{hla_interface,the hla interface
3207 driver}, in which case the command is @command{transport select
3208 hla_jtag}.
3210 @subsection SWD Transport
3211 @cindex SWD
3212 @cindex Serial Wire Debug
3213 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3214 Debug Access Point (DAP, which must be explicitly declared.
3215 (SWD uses fewer signal wires than JTAG.)
3216 SWD is debug-oriented, and does not support boundary scan testing.
3217 Flash programming support is built on top of debug support.
3218 (Some processors support both JTAG and SWD.)
3220 SWD transport is selected with the command @command{transport select
3221 swd}. Unless your adapter uses @ref{hla_interface,the hla interface
3222 driver}, in which case the command is @command{transport select
3223 hla_swd}.
3225 @deffn Command {swd newdap} ...
3226 Declares a single DAP which uses SWD transport.
3227 Parameters are currently the same as "jtag newtap" but this is
3228 expected to change.
3229 @end deffn
3230 @deffn Command {swd wcr trn prescale}
3231 Updates TRN (turnaround delay) and prescaling.fields of the
3232 Wire Control Register (WCR).
3233 No parameters: displays current settings.
3234 @end deffn
3236 @subsection SPI Transport
3237 @cindex SPI
3238 @cindex Serial Peripheral Interface
3239 The Serial Peripheral Interface (SPI) is a general purpose transport
3240 which uses four wire signaling. Some processors use it as part of a
3241 solution for flash programming.
3243 @anchor{jtagspeed}
3244 @section JTAG Speed
3245 JTAG clock setup is part of system setup.
3246 It @emph{does not belong with interface setup} since any interface
3247 only knows a few of the constraints for the JTAG clock speed.
3248 Sometimes the JTAG speed is
3249 changed during the target initialization process: (1) slow at
3250 reset, (2) program the CPU clocks, (3) run fast.
3251 Both the "slow" and "fast" clock rates are functions of the
3252 oscillators used, the chip, the board design, and sometimes
3253 power management software that may be active.
3255 The speed used during reset, and the scan chain verification which
3256 follows reset, can be adjusted using a @code{reset-start}
3257 target event handler.
3258 It can then be reconfigured to a faster speed by a
3259 @code{reset-init} target event handler after it reprograms those
3260 CPU clocks, or manually (if something else, such as a boot loader,
3261 sets up those clocks).
3262 @xref{targetevents,,Target Events}.
3263 When the initial low JTAG speed is a chip characteristic, perhaps
3264 because of a required oscillator speed, provide such a handler
3265 in the target config file.
3266 When that speed is a function of a board-specific characteristic
3267 such as which speed oscillator is used, it belongs in the board
3268 config file instead.
3269 In both cases it's safest to also set the initial JTAG clock rate
3270 to that same slow speed, so that OpenOCD never starts up using a
3271 clock speed that's faster than the scan chain can support.
3273 @example
3274 jtag_rclk 3000
3275 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3276 @end example
3278 If your system supports adaptive clocking (RTCK), configuring
3279 JTAG to use that is probably the most robust approach.
3280 However, it introduces delays to synchronize clocks; so it
3281 may not be the fastest solution.
3283 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3284 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3285 which support adaptive clocking.
3287 @deffn {Command} adapter_khz max_speed_kHz
3288 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3289 JTAG interfaces usually support a limited number of
3290 speeds. The speed actually used won't be faster
3291 than the speed specified.
3293 Chip data sheets generally include a top JTAG clock rate.
3294 The actual rate is often a function of a CPU core clock,
3295 and is normally less than that peak rate.
3296 For example, most ARM cores accept at most one sixth of the CPU clock.
3298 Speed 0 (khz) selects RTCK method.
3299 @xref{faqrtck,,FAQ RTCK}.
3300 If your system uses RTCK, you won't need to change the
3301 JTAG clocking after setup.
3302 Not all interfaces, boards, or targets support ``rtck''.
3303 If the interface device can not
3304 support it, an error is returned when you try to use RTCK.
3305 @end deffn
3307 @defun jtag_rclk fallback_speed_kHz
3308 @cindex adaptive clocking
3309 @cindex RTCK
3310 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3311 If that fails (maybe the interface, board, or target doesn't
3312 support it), falls back to the specified frequency.
3313 @example
3314 # Fall back to 3mhz if RTCK is not supported
3315 jtag_rclk 3000
3316 @end example
3317 @end defun
3319 @node Reset Configuration
3320 @chapter Reset Configuration
3321 @cindex Reset Configuration
3323 Every system configuration may require a different reset
3324 configuration. This can also be quite confusing.
3325 Resets also interact with @var{reset-init} event handlers,
3326 which do things like setting up clocks and DRAM, and
3327 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3328 They can also interact with JTAG routers.
3329 Please see the various board files for examples.
3331 @quotation Note
3332 To maintainers and integrators:
3333 Reset configuration touches several things at once.
3334 Normally the board configuration file
3335 should define it and assume that the JTAG adapter supports
3336 everything that's wired up to the board's JTAG connector.
3338 However, the target configuration file could also make note
3339 of something the silicon vendor has done inside the chip,
3340 which will be true for most (or all) boards using that chip.
3341 And when the JTAG adapter doesn't support everything, the
3342 user configuration file will need to override parts of
3343 the reset configuration provided by other files.
3344 @end quotation
3346 @section Types of Reset
3348 There are many kinds of reset possible through JTAG, but
3349 they may not all work with a given board and adapter.
3350 That's part of why reset configuration can be error prone.
3352 @itemize @bullet
3353 @item
3354 @emph{System Reset} ... the @emph{SRST} hardware signal
3355 resets all chips connected to the JTAG adapter, such as processors,
3356 power management chips, and I/O controllers. Normally resets triggered
3357 with this signal behave exactly like pressing a RESET button.
3358 @item
3359 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3360 just the TAP controllers connected to the JTAG adapter.
3361 Such resets should not be visible to the rest of the system; resetting a
3362 device's TAP controller just puts that controller into a known state.
3363 @item
3364 @emph{Emulation Reset} ... many devices can be reset through JTAG
3365 commands. These resets are often distinguishable from system
3366 resets, either explicitly (a "reset reason" register says so)
3367 or implicitly (not all parts of the chip get reset).
3368 @item
3369 @emph{Other Resets} ... system-on-chip devices often support
3370 several other types of reset.
3371 You may need to arrange that a watchdog timer stops
3372 while debugging, preventing a watchdog reset.
3373 There may be individual module resets.
3374 @end itemize
3376 In the best case, OpenOCD can hold SRST, then reset
3377 the TAPs via TRST and send commands through JTAG to halt the
3378 CPU at the reset vector before the 1st instruction is executed.
3379 Then when it finally releases the SRST signal, the system is
3380 halted under debugger control before any code has executed.
3381 This is the behavior required to support the @command{reset halt}
3382 and @command{reset init} commands; after @command{reset init} a
3383 board-specific script might do things like setting up DRAM.
3384 (@xref{resetcommand,,Reset Command}.)
3386 @anchor{srstandtrstissues}
3387 @section SRST and TRST Issues
3389 Because SRST and TRST are hardware signals, they can have a
3390 variety of system-specific constraints. Some of the most
3391 common issues are:
3393 @itemize @bullet
3395 @item @emph{Signal not available} ... Some boards don't wire
3396 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3397 support such signals even if they are wired up.
3398 Use the @command{reset_config} @var{signals} options to say
3399 when either of those signals is not connected.
3400 When SRST is not available, your code might not be able to rely
3401 on controllers having been fully reset during code startup.
3402 Missing TRST is not a problem, since JTAG-level resets can
3403 be triggered using with TMS signaling.
3405 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3406 adapter will connect SRST to TRST, instead of keeping them separate.
3407 Use the @command{reset_config} @var{combination} options to say
3408 when those signals aren't properly independent.
3410 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3411 delay circuit, reset supervisor, or on-chip features can extend
3412 the effect of a JTAG adapter's reset for some time after the adapter
3413 stops issuing the reset. For example, there may be chip or board
3414 requirements that all reset pulses last for at least a
3415 certain amount of time; and reset buttons commonly have
3416 hardware debouncing.
3417 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3418 commands to say when extra delays are needed.
3420 @item @emph{Drive type} ... Reset lines often have a pullup
3421 resistor, letting the JTAG interface treat them as open-drain
3422 signals. But that's not a requirement, so the adapter may need
3423 to use push/pull output drivers.
3424 Also, with weak pullups it may be advisable to drive
3425 signals to both levels (push/pull) to minimize rise times.
3426 Use the @command{reset_config} @var{trst_type} and
3427 @var{srst_type} parameters to say how to drive reset signals.
3429 @item @emph{Special initialization} ... Targets sometimes need
3430 special JTAG initialization sequences to handle chip-specific
3431 issues (not limited to errata).
3432 For example, certain JTAG commands might need to be issued while
3433 the system as a whole is in a reset state (SRST active)
3434 but the JTAG scan chain is usable (TRST inactive).
3435 Many systems treat combined assertion of SRST and TRST as a
3436 trigger for a harder reset than SRST alone.
3437 Such custom reset handling is discussed later in this chapter.
3438 @end itemize
3440 There can also be other issues.
3441 Some devices don't fully conform to the JTAG specifications.
3442 Trivial system-specific differences are common, such as
3443 SRST and TRST using slightly different names.
3444 There are also vendors who distribute key JTAG documentation for
3445 their chips only to developers who have signed a Non-Disclosure
3446 Agreement (NDA).
3448 Sometimes there are chip-specific extensions like a requirement to use
3449 the normally-optional TRST signal (precluding use of JTAG adapters which
3450 don't pass TRST through), or needing extra steps to complete a TAP reset.
3452 In short, SRST and especially TRST handling may be very finicky,
3453 needing to cope with both architecture and board specific constraints.
3455 @section Commands for Handling Resets
3457 @deffn {Command} adapter_nsrst_assert_width milliseconds
3458 Minimum amount of time (in milliseconds) OpenOCD should wait
3459 after asserting nSRST (active-low system reset) before
3460 allowing it to be deasserted.
3461 @end deffn
3463 @deffn {Command} adapter_nsrst_delay milliseconds
3464 How long (in milliseconds) OpenOCD should wait after deasserting
3465 nSRST (active-low system reset) before starting new JTAG operations.
3466 When a board has a reset button connected to SRST line it will
3467 probably have hardware debouncing, implying you should use this.
3468 @end deffn
3470 @deffn {Command} jtag_ntrst_assert_width milliseconds
3471 Minimum amount of time (in milliseconds) OpenOCD should wait
3472 after asserting nTRST (active-low JTAG TAP reset) before
3473 allowing it to be deasserted.
3474 @end deffn
3476 @deffn {Command} jtag_ntrst_delay milliseconds
3477 How long (in milliseconds) OpenOCD should wait after deasserting
3478 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3479 @end deffn
3481 @anchor {reset_config}
3482 @deffn {Command} reset_config mode_flag ...
3483 This command displays or modifies the reset configuration
3484 of your combination of JTAG board and target in target
3485 configuration scripts.
3487 Information earlier in this section describes the kind of problems
3488 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3489 As a rule this command belongs only in board config files,
3490 describing issues like @emph{board doesn't connect TRST};
3491 or in user config files, addressing limitations derived
3492 from a particular combination of interface and board.
3493 (An unlikely example would be using a TRST-only adapter
3494 with a board that only wires up SRST.)
3496 The @var{mode_flag} options can be specified in any order, but only one
3497 of each type -- @var{signals}, @var{combination}, @var{gates},
3498 @var{trst_type}, @var{srst_type} and @var{connect_type}
3499 -- may be specified at a time.
3500 If you don't provide a new value for a given type, its previous
3501 value (perhaps the default) is unchanged.
3502 For example, this means that you don't need to say anything at all about
3503 TRST just to declare that if the JTAG adapter should want to drive SRST,
3504 it must explicitly be driven high (@option{srst_push_pull}).
3506 @itemize
3507 @item
3508 @var{signals} can specify which of the reset signals are connected.
3509 For example, If the JTAG interface provides SRST, but the board doesn't
3510 connect that signal properly, then OpenOCD can't use it.
3511 Possible values are @option{none} (the default), @option{trst_only},
3512 @option{srst_only} and @option{trst_and_srst}.
3514 @quotation Tip
3515 If your board provides SRST and/or TRST through the JTAG connector,
3516 you must declare that so those signals can be used.
3517 @end quotation
3519 @item
3520 The @var{combination} is an optional value specifying broken reset
3521 signal implementations.
3522 The default behaviour if no option given is @option{separate},
3523 indicating everything behaves normally.
3524 @option{srst_pulls_trst} states that the
3525 test logic is reset together with the reset of the system (e.g. NXP
3526 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3527 the system is reset together with the test logic (only hypothetical, I
3528 haven't seen hardware with such a bug, and can be worked around).
3529 @option{combined} implies both @option{srst_pulls_trst} and
3530 @option{trst_pulls_srst}.
3532 @item
3533 The @var{gates} tokens control flags that describe some cases where
3534 JTAG may be unavailable during reset.
3535 @option{srst_gates_jtag} (default)
3536 indicates that asserting SRST gates the
3537 JTAG clock. This means that no communication can happen on JTAG
3538 while SRST is asserted.
3539 Its converse is @option{srst_nogate}, indicating that JTAG commands
3540 can safely be issued while SRST is active.
3542 @item
3543 The @var{connect_type} tokens control flags that describe some cases where
3544 SRST is asserted while connecting to the target. @option{srst_nogate}
3545 is required to use this option.
3546 @option{connect_deassert_srst} (default)
3547 indicates that SRST will not be asserted while connecting to the target.
3548 Its converse is @option{connect_assert_srst}, indicating that SRST will
3549 be asserted before any target connection.
3550 Only some targets support this feature, STM32 and STR9 are examples.
3551 This feature is useful if you are unable to connect to your target due
3552 to incorrect options byte config or illegal program execution.
3553 @end itemize
3555 The optional @var{trst_type} and @var{srst_type} parameters allow the
3556 driver mode of each reset line to be specified. These values only affect
3557 JTAG interfaces with support for different driver modes, like the Amontec
3558 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3559 relevant signal (TRST or SRST) is not connected.
3561 @itemize
3562 @item
3563 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3564 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3565 Most boards connect this signal to a pulldown, so the JTAG TAPs
3566 never leave reset unless they are hooked up to a JTAG adapter.
3568 @item
3569 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3570 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3571 Most boards connect this signal to a pullup, and allow the
3572 signal to be pulled low by various events including system
3573 power-up and pressing a reset button.
3574 @end itemize
3575 @end deffn
3577 @section Custom Reset Handling
3578 @cindex events
3580 OpenOCD has several ways to help support the various reset
3581 mechanisms provided by chip and board vendors.
3582 The commands shown in the previous section give standard parameters.
3583 There are also @emph{event handlers} associated with TAPs or Targets.
3584 Those handlers are Tcl procedures you can provide, which are invoked
3585 at particular points in the reset sequence.
3587 @emph{When SRST is not an option} you must set
3588 up a @code{reset-assert} event handler for your target.
3589 For example, some JTAG adapters don't include the SRST signal;
3590 and some boards have multiple targets, and you won't always
3591 want to reset everything at once.
3593 After configuring those mechanisms, you might still
3594 find your board doesn't start up or reset correctly.
3595 For example, maybe it needs a slightly different sequence
3596 of SRST and/or TRST manipulations, because of quirks that
3597 the @command{reset_config} mechanism doesn't address;
3598 or asserting both might trigger a stronger reset, which
3599 needs special attention.
3601 Experiment with lower level operations, such as @command{jtag_reset}
3602 and the @command{jtag arp_*} operations shown here,
3603 to find a sequence of operations that works.
3604 @xref{JTAG Commands}.
3605 When you find a working sequence, it can be used to override
3606 @command{jtag_init}, which fires during OpenOCD startup
3607 (@pxref{configurationstage,,Configuration Stage});
3608 or @command{init_reset}, which fires during reset processing.
3610 You might also want to provide some project-specific reset
3611 schemes. For example, on a multi-target board the standard
3612 @command{reset} command would reset all targets, but you
3613 may need the ability to reset only one target at time and
3614 thus want to avoid using the board-wide SRST signal.
3616 @deffn {Overridable Procedure} init_reset mode
3617 This is invoked near the beginning of the @command{reset} command,
3618 usually to provide as much of a cold (power-up) reset as practical.
3619 By default it is also invoked from @command{jtag_init} if
3620 the scan chain does not respond to pure JTAG operations.
3621 The @var{mode} parameter is the parameter given to the
3622 low level reset command (@option{halt},
3623 @option{init}, or @option{run}), @option{setup},
3624 or potentially some other value.
3626 The default implementation just invokes @command{jtag arp_init-reset}.
3627 Replacements will normally build on low level JTAG
3628 operations such as @command{jtag_reset}.
3629 Operations here must not address individual TAPs
3630 (or their associated targets)
3631 until the JTAG scan chain has first been verified to work.
3633 Implementations must have verified the JTAG scan chain before
3634 they return.
3635 This is done by calling @command{jtag arp_init}
3636 (or @command{jtag arp_init-reset}).
3637 @end deffn
3639 @deffn Command {jtag arp_init}
3640 This validates the scan chain using just the four
3641 standard JTAG signals (TMS, TCK, TDI, TDO).
3642 It starts by issuing a JTAG-only reset.
3643 Then it performs checks to verify that the scan chain configuration
3644 matches the TAPs it can observe.
3645 Those checks include checking IDCODE values for each active TAP,
3646 and verifying the length of their instruction registers using
3647 TAP @code{-ircapture} and @code{-irmask} values.
3648 If these tests all pass, TAP @code{setup} events are
3649 issued to all TAPs with handlers for that event.
3650 @end deffn
3652 @deffn Command {jtag arp_init-reset}
3653 This uses TRST and SRST to try resetting
3654 everything on the JTAG scan chain
3655 (and anything else connected to SRST).
3656 It then invokes the logic of @command{jtag arp_init}.
3657 @end deffn
3660 @node TAP Declaration
3661 @chapter TAP Declaration
3662 @cindex TAP declaration
3663 @cindex TAP configuration
3665 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3666 TAPs serve many roles, including:
3668 @itemize @bullet
3669 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3670 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3671 Others do it indirectly, making a CPU do it.
3672 @item @b{Program Download} Using the same CPU support GDB uses,
3673 you can initialize a DRAM controller, download code to DRAM, and then
3674 start running that code.
3675 @item @b{Boundary Scan} Most chips support boundary scan, which
3676 helps test for board assembly problems like solder bridges
3677 and missing connections.
3678 @end itemize
3680 OpenOCD must know about the active TAPs on your board(s).
3681 Setting up the TAPs is the core task of your configuration files.
3682 Once those TAPs are set up, you can pass their names to code
3683 which sets up CPUs and exports them as GDB targets,
3684 probes flash memory, performs low-level JTAG operations, and more.
3686 @section Scan Chains
3687 @cindex scan chain
3689 TAPs are part of a hardware @dfn{scan chain},
3690 which is a daisy chain of TAPs.
3691 They also need to be added to
3692 OpenOCD's software mirror of that hardware list,
3693 giving each member a name and associating other data with it.
3694 Simple scan chains, with a single TAP, are common in
3695 systems with a single microcontroller or microprocessor.
3696 More complex chips may have several TAPs internally.
3697 Very complex scan chains might have a dozen or more TAPs:
3698 several in one chip, more in the next, and connecting
3699 to other boards with their own chips and TAPs.
3701 You can display the list with the @command{scan_chain} command.
3702 (Don't confuse this with the list displayed by the @command{targets}
3703 command, presented in the next chapter.
3704 That only displays TAPs for CPUs which are configured as
3705 debugging targets.)
3706 Here's what the scan chain might look like for a chip more than one TAP:
3708 @verbatim
3709 TapName Enabled IdCode Expected IrLen IrCap IrMask
3710 -- ------------------ ------- ---------- ---------- ----- ----- ------
3711 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3712 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3713 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3714 @end verbatim
3716 OpenOCD can detect some of that information, but not all
3717 of it. @xref{autoprobing,,Autoprobing}.
3718 Unfortunately, those TAPs can't always be autoconfigured,
3719 because not all devices provide good support for that.
3720 JTAG doesn't require supporting IDCODE instructions, and
3721 chips with JTAG routers may not link TAPs into the chain
3722 until they are told to do so.
3724 The configuration mechanism currently supported by OpenOCD
3725 requires explicit configuration of all TAP devices using
3726 @command{jtag newtap} commands, as detailed later in this chapter.
3727 A command like this would declare one tap and name it @code{chip1.cpu}:
3729 @example
3730 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3731 @end example
3733 Each target configuration file lists the TAPs provided
3734 by a given chip.
3735 Board configuration files combine all the targets on a board,
3736 and so forth.
3737 Note that @emph{the order in which TAPs are declared is very important.}
3738 That declaration order must match the order in the JTAG scan chain,
3739 both inside a single chip and between them.
3740 @xref{faqtaporder,,FAQ TAP Order}.
3742 For example, the STMicroelectronics STR912 chip has
3743 three separate TAPs@footnote{See the ST
3744 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3745 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3746 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3747 To configure those taps, @file{target/str912.cfg}
3748 includes commands something like this:
3750 @example
3751 jtag newtap str912 flash ... params ...
3752 jtag newtap str912 cpu ... params ...
3753 jtag newtap str912 bs ... params ...
3754 @end example
3756 Actual config files typically use a variable such as @code{$_CHIPNAME}
3757 instead of literals like @option{str912}, to support more than one chip
3758 of each type. @xref{Config File Guidelines}.
3760 @deffn Command {jtag names}
3761 Returns the names of all current TAPs in the scan chain.
3762 Use @command{jtag cget} or @command{jtag tapisenabled}
3763 to examine attributes and state of each TAP.
3764 @example
3765 foreach t [jtag names] @{
3766 puts [format "TAP: %s\n" $t]
3767 @}
3768 @end example
3769 @end deffn
3771 @deffn Command {scan_chain}
3772 Displays the TAPs in the scan chain configuration,
3773 and their status.
3774 The set of TAPs listed by this command is fixed by
3775 exiting the OpenOCD configuration stage,
3776 but systems with a JTAG router can
3777 enable or disable TAPs dynamically.
3778 @end deffn
3780 @c FIXME! "jtag cget" should be able to return all TAP
3781 @c attributes, like "$target_name cget" does for targets.
3783 @c Probably want "jtag eventlist", and a "tap-reset" event
3784 @c (on entry to RESET state).
3786 @section TAP Names
3787 @cindex dotted name
3789 When TAP objects are declared with @command{jtag newtap},
3790 a @dfn{dotted.name} is created for the TAP, combining the
3791 name of a module (usually a chip) and a label for the TAP.
3792 For example: @code{xilinx.tap}, @code{str912.flash},
3793 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3794 Many other commands use that dotted.name to manipulate or
3795 refer to the TAP. For example, CPU configuration uses the
3796 name, as does declaration of NAND or NOR flash banks.
3798 The components of a dotted name should follow ``C'' symbol
3799 name rules: start with an alphabetic character, then numbers
3800 and underscores are OK; while others (including dots!) are not.
3802 @section TAP Declaration Commands
3804 @c shouldn't this be(come) a {Config Command}?
3805 @deffn Command {jtag newtap} chipname tapname configparams...
3806 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3807 and configured according to the various @var{configparams}.
3809 The @var{chipname} is a symbolic name for the chip.
3810 Conventionally target config files use @code{$_CHIPNAME},
3811 defaulting to the model name given by the chip vendor but
3812 overridable.
3814 @cindex TAP naming convention
3815 The @var{tapname} reflects the role of that TAP,
3816 and should follow this convention:
3818 @itemize @bullet
3819 @item @code{bs} -- For boundary scan if this is a separate TAP;
3820 @item @code{cpu} -- The main CPU of the chip, alternatively
3821 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3822 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3823 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3824 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3825 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3826 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3827 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3828 with a single TAP;
3829 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3830 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3831 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3832 a JTAG TAP; that TAP should be named @code{sdma}.
3833 @end itemize
3835 Every TAP requires at least the following @var{configparams}:
3837 @itemize @bullet
3838 @item @code{-irlen} @var{NUMBER}
3839 @*The length in bits of the
3840 instruction register, such as 4 or 5 bits.
3841 @end itemize
3843 A TAP may also provide optional @var{configparams}:
3845 @itemize @bullet
3846 @item @code{-disable} (or @code{-enable})
3847 @*Use the @code{-disable} parameter to flag a TAP which is not
3848 linked into the scan chain after a reset using either TRST
3849 or the JTAG state machine's @sc{reset} state.
3850 You may use @code{-enable} to highlight the default state
3851 (the TAP is linked in).
3852 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3853 @item @code{-expected-id} @var{NUMBER}
3854 @*A non-zero @var{number} represents a 32-bit IDCODE
3855 which you expect to find when the scan chain is examined.
3856 These codes are not required by all JTAG devices.
3857 @emph{Repeat the option} as many times as required if more than one
3858 ID code could appear (for example, multiple versions).
3859 Specify @var{number} as zero to suppress warnings about IDCODE
3860 values that were found but not included in the list.
3862 Provide this value if at all possible, since it lets OpenOCD
3863 tell when the scan chain it sees isn't right. These values
3864 are provided in vendors' chip documentation, usually a technical
3865 reference manual. Sometimes you may need to probe the JTAG
3866 hardware to find these values.
3867 @xref{autoprobing,,Autoprobing}.
3868 @item @code{-ignore-version}
3869 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3870 option. When vendors put out multiple versions of a chip, or use the same
3871 JTAG-level ID for several largely-compatible chips, it may be more practical
3872 to ignore the version field than to update config files to handle all of
3873 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3874 @item @code{-ircapture} @var{NUMBER}
3875 @*The bit pattern loaded by the TAP into the JTAG shift register
3876 on entry to the @sc{ircapture} state, such as 0x01.
3877 JTAG requires the two LSBs of this value to be 01.
3878 By default, @code{-ircapture} and @code{-irmask} are set
3879 up to verify that two-bit value. You may provide
3880 additional bits if you know them, or indicate that
3881 a TAP doesn't conform to the JTAG specification.
3882 @item @code{-irmask} @var{NUMBER}
3883 @*A mask used with @code{-ircapture}
3884 to verify that instruction scans work correctly.
3885 Such scans are not used by OpenOCD except to verify that
3886 there seems to be no problems with JTAG scan chain operations.
3887 @item @code{-ignore-syspwrupack}
3888 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
3889 register during initial examination and when checking the sticky error bit.
3890 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
3891 devices do not set the ack bit until sometime later.
3892 @end itemize
3893 @end deffn
3895 @section Other TAP commands
3897 @deffn Command {jtag cget} dotted.name @option{-event} event_name
3898 @deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
3899 At this writing this TAP attribute
3900 mechanism is used only for event handling.
3901 (It is not a direct analogue of the @code{cget}/@code{configure}
3902 mechanism for debugger targets.)
3903 See the next section for information about the available events.
3905 The @code{configure} subcommand assigns an event handler,
3906 a TCL string which is evaluated when the event is triggered.
3907 The @code{cget} subcommand returns that handler.
3908 @end deffn
3910 @section TAP Events
3911 @cindex events
3912 @cindex TAP events
3914 OpenOCD includes two event mechanisms.
3915 The one presented here applies to all JTAG TAPs.
3916 The other applies to debugger targets,
3917 which are associated with certain TAPs.
3919 The TAP events currently defined are:
3921 @itemize @bullet
3922 @item @b{post-reset}
3923 @* The TAP has just completed a JTAG reset.
3924 The tap may still be in the JTAG @sc{reset} state.
3925 Handlers for these events might perform initialization sequences
3926 such as issuing TCK cycles, TMS sequences to ensure
3927 exit from the ARM SWD mode, and more.
3929 Because the scan chain has not yet been verified, handlers for these events
3930 @emph{should not issue commands which scan the JTAG IR or DR registers}
3931 of any particular target.
3932 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3933 @item @b{setup}
3934 @* The scan chain has been reset and verified.
3935 This handler may enable TAPs as needed.
3936 @item @b{tap-disable}
3937 @* The TAP needs to be disabled. This handler should
3938 implement @command{jtag tapdisable}
3939 by issuing the relevant JTAG commands.
3940 @item @b{tap-enable}
3941 @* The TAP needs to be enabled. This handler should
3942 implement @command{jtag tapenable}
3943 by issuing the relevant JTAG commands.
3944 @end itemize
3946 If you need some action after each JTAG reset which isn't actually
3947 specific to any TAP (since you can't yet trust the scan chain's
3948 contents to be accurate), you might:
3950 @example
3951 jtag configure CHIP.jrc -event post-reset @{
3952 echo "JTAG Reset done"
3953 ... non-scan jtag operations to be done after reset
3954 @}
3955 @end example
3958 @anchor{enablinganddisablingtaps}
3959 @section Enabling and Disabling TAPs
3960 @cindex JTAG Route Controller
3961 @cindex jrc
3963 In some systems, a @dfn{JTAG Route Controller} (JRC)
3964 is used to enable and/or disable specific JTAG TAPs.
3965 Many ARM-based chips from Texas Instruments include
3966 an ``ICEPick'' module, which is a JRC.
3967 Such chips include DaVinci and OMAP3 processors.
3969 A given TAP may not be visible until the JRC has been
3970 told to link it into the scan chain; and if the JRC
3971 has been told to unlink that TAP, it will no longer
3972 be visible.
3973 Such routers address problems that JTAG ``bypass mode''
3974 ignores, such as:
3976 @itemize
3977 @item The scan chain can only go as fast as its slowest TAP.
3978 @item Having many TAPs slows instruction scans, since all
3979 TAPs receive new instructions.
3980 @item TAPs in the scan chain must be powered up, which wastes
3981 power and prevents debugging some power management mechanisms.
3982 @end itemize
3984 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3985 as implied by the existence of JTAG routers.
3986 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3987 does include a kind of JTAG router functionality.
3989 @c (a) currently the event handlers don't seem to be able to
3990 @c fail in a way that could lead to no-change-of-state.
3992 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3993 shown below, and is implemented using TAP event handlers.
3994 So for example, when defining a TAP for a CPU connected to
3995 a JTAG router, your @file{target.cfg} file
3996 should define TAP event handlers using
3997 code that looks something like this:
3999 @example
4000 jtag configure CHIP.cpu -event tap-enable @{
4001 ... jtag operations using CHIP.jrc
4002 @}
4003 jtag configure CHIP.cpu -event tap-disable @{
4004 ... jtag operations using CHIP.jrc
4005 @}
4006 @end example
4008 Then you might want that CPU's TAP enabled almost all the time:
4010 @example
4011 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
4012 @end example
4014 Note how that particular setup event handler declaration
4015 uses quotes to evaluate @code{$CHIP} when the event is configured.
4016 Using brackets @{ @} would cause it to be evaluated later,
4017 at runtime, when it might have a different value.
4019 @deffn Command {jtag tapdisable} dotted.name
4020 If necessary, disables the tap
4021 by sending it a @option{tap-disable} event.
4022 Returns the string "1" if the tap
4023 specified by @var{dotted.name} is enabled,
4024 and "0" if it is disabled.
4025 @end deffn
4027 @deffn Command {jtag tapenable} dotted.name
4028 If necessary, enables the tap
4029 by sending it a @option{tap-enable} event.
4030 Returns the string "1" if the tap
4031 specified by @var{dotted.name} is enabled,
4032 and "0" if it is disabled.
4033 @end deffn
4035 @deffn Command {jtag tapisenabled} dotted.name
4036 Returns the string "1" if the tap
4037 specified by @var{dotted.name} is enabled,
4038 and "0" if it is disabled.
4040 @quotation Note
4041 Humans will find the @command{scan_chain} command more helpful
4042 for querying the state of the JTAG taps.
4043 @end quotation
4044 @end deffn
4046 @anchor{autoprobing}
4047 @section Autoprobing
4048 @cindex autoprobe
4049 @cindex JTAG autoprobe
4051 TAP configuration is the first thing that needs to be done
4052 after interface and reset configuration. Sometimes it's
4053 hard finding out what TAPs exist, or how they are identified.
4054 Vendor documentation is not always easy to find and use.
4056 To help you get past such problems, OpenOCD has a limited
4057 @emph{autoprobing} ability to look at the scan chain, doing
4058 a @dfn{blind interrogation} and then reporting the TAPs it finds.
4059 To use this mechanism, start the OpenOCD server with only data
4060 that configures your JTAG interface, and arranges to come up
4061 with a slow clock (many devices don't support fast JTAG clocks
4062 right when they come out of reset).
4064 For example, your @file{openocd.cfg} file might have:
4066 @example
4067 source [find interface/olimex-arm-usb-tiny-h.cfg]
4068 reset_config trst_and_srst
4069 jtag_rclk 8
4070 @end example
4072 When you start the server without any TAPs configured, it will
4073 attempt to autoconfigure the TAPs. There are two parts to this:
4075 @enumerate
4076 @item @emph{TAP discovery} ...
4077 After a JTAG reset (sometimes a system reset may be needed too),
4078 each TAP's data registers will hold the contents of either the
4079 IDCODE or BYPASS register.
4080 If JTAG communication is working, OpenOCD will see each TAP,
4081 and report what @option{-expected-id} to use with it.
4082 @item @emph{IR Length discovery} ...
4083 Unfortunately JTAG does not provide a reliable way to find out
4084 the value of the @option{-irlen} parameter to use with a TAP
4085 that is discovered.
4086 If OpenOCD can discover the length of a TAP's instruction
4087 register, it will report it.
4088 Otherwise you may need to consult vendor documentation, such
4089 as chip data sheets or BSDL files.
4090 @end enumerate
4092 In many cases your board will have a simple scan chain with just
4093 a single device. Here's what OpenOCD reported with one board
4094 that's a bit more complex:
4096 @example
4097 clock speed 8 kHz
4098 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4099 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4100 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4101 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4102 AUTO auto0.tap - use "... -irlen 4"
4103 AUTO auto1.tap - use "... -irlen 4"
4104 AUTO auto2.tap - use "... -irlen 6"
4105 no gdb ports allocated as no target has been specified
4106 @end example
4108 Given that information, you should be able to either find some existing
4109 config files to use, or create your own. If you create your own, you
4110 would configure from the bottom up: first a @file{target.cfg} file
4111 with these TAPs, any targets associated with them, and any on-chip
4112 resources; then a @file{board.cfg} with off-chip resources, clocking,
4113 and so forth.
4115 @anchor{dapdeclaration}
4116 @section DAP declaration (ARMv6-M, ARMv7 and ARMv8 targets)
4117 @cindex DAP declaration
4119 Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is
4120 no longer implicitly created together with the target. It must be
4121 explicitly declared using the @command{dap create} command. For all ARMv6-M, ARMv7
4122 and ARMv8 targets, the option "@option{-dap} @var{dap_name}" has to be used
4123 instead of "@option{-chain-position} @var{dotted.name}" when the target is created.
4125 The @command{dap} command group supports the following sub-commands:
4127 @deffn Command {dap create} dap_name @option{-chain-position} dotted.name configparams...
4128 Declare a DAP instance named @var{dap_name} linked to the JTAG tap
4129 @var{dotted.name}. This also creates a new command (@command{dap_name})
4130 which is used for various purposes including additional configuration.
4131 There can only be one DAP for each JTAG tap in the system.
4133 A DAP may also provide optional @var{configparams}:
4135 @itemize @bullet
4136 @item @code{-ignore-syspwrupack}
4137 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4138 register during initial examination and when checking the sticky error bit.
4139 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4140 devices do not set the ack bit until sometime later.
4141 @end itemize
4142 @end deffn
4144 @deffn Command {dap names}
4145 This command returns a list of all registered DAP objects. It it useful mainly
4146 for TCL scripting.
4147 @end deffn
4149 @deffn Command {dap info} [num]
4150 Displays the ROM table for MEM-AP @var{num},
4151 defaulting to the currently selected AP of the currently selected target.
4152 @end deffn
4154 @deffn Command {dap init}
4155 Initialize all registered DAPs. This command is used internally
4156 during initialization. It can be issued at any time after the
4157 initialization, too.
4158 @end deffn
4160 The following commands exist as subcommands of DAP instances:
4162 @deffn Command {$dap_name info} [num]
4163 Displays the ROM table for MEM-AP @var{num},
4164 defaulting to the currently selected AP.
4165 @end deffn
4167 @deffn Command {$dap_name apid} [num]
4168 Displays ID register from AP @var{num}, defaulting to the currently selected AP.
4169 @end deffn
4171 @anchor{DAP subcommand apreg}
4172 @deffn Command {$dap_name apreg} ap_num reg [value]
4173 Displays content of a register @var{reg} from AP @var{ap_num}
4174 or set a new value @var{value}.
4175 @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
4176 @end deffn
4178 @deffn Command {$dap_name apsel} [num]
4179 Select AP @var{num}, defaulting to 0.
4180 @end deffn
4182 @deffn Command {$dap_name dpreg} reg [value]
4183 Displays the content of DP register at address @var{reg}, or set it to a new
4184 value @var{value}.
4186 In case of SWD, @var{reg} is a value in packed format
4187 @math{dpbanksel << 4 | addr} and assumes values 0, 4, 8 ... 0xfc.
4188 In case of JTAG it only assumes values 0, 4, 8 and 0xc.
4190 @emph{Note:} Consider using @command{poll off} to avoid any disturbing
4191 background activity by OpenOCD while you are operating at such low-level.
4192 @end deffn
4194 @deffn Command {$dap_name baseaddr} [num]
4195 Displays debug base address from MEM-AP @var{num},
4196 defaulting to the currently selected AP.
4197 @end deffn
4199 @deffn Command {$dap_name memaccess} [value]
4200 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
4201 memory bus access [0-255], giving additional time to respond to reads.
4202 If @var{value} is defined, first assigns that.
4203 @end deffn
4205 @deffn Command {$dap_name apcsw} [value [mask]]
4206 Displays or changes CSW bit pattern for MEM-AP transfers.
4208 At the begin of each memory access the CSW pattern is extended (bitwise or-ed)
4209 by @dfn{Size} and @dfn{AddrInc} bit-fields according to transfer requirements
4210 and the result is written to the real CSW register. All bits except dynamically
4211 updated fields @dfn{Size} and @dfn{AddrInc} can be changed by changing
4212 the CSW pattern. Refer to ARM ADI v5 manual chapter 7.6.4 and appendix A
4213 for details.
4215 Use @var{value} only syntax if you want to set the new CSW pattern as a whole.
4216 The example sets HPROT1 bit (required by Cortex-M) and clears the rest of
4217 the pattern:
4218 @example
4219 kx.dap apcsw 0x2000000
4220 @end example
4222 If @var{mask} is also used, the CSW pattern is changed only on bit positions
4223 where the mask bit is 1. The following example sets HPROT3 (cacheable)
4224 and leaves the rest of the pattern intact. It configures memory access through
4225 DCache on Cortex-M7.
4226 @example
4227 set CSW_HPROT3_CACHEABLE [expr 1 << 27]
4229 @end example
4231 Another example clears SPROT bit and leaves the rest of pattern intact:
4232 @example
4233 set CSW_SPROT [expr 1 << 30]
4234 samv.dap apcsw 0 $CSW_SPROT
4235 @end example
4237 @emph{Note:} If you want to check the real value of CSW, not CSW pattern, use
4238 @code{xxx.dap apreg 0}. @xref{DAP subcommand apreg,,}.
4240 @emph{Warning:} Some of the CSW bits are vital for working memory transfer.
4241 If you set a wrong CSW pattern and MEM-AP stopped working, use the following
4242 example with a proper dap name:
4243 @example
4244 xxx.dap apcsw default
4245 @end example
4246 @end deffn
4248 @deffn Command {$dap_name ti_be_32_quirks} [@option{enable}]
4249 Set/get quirks mode for TI TMS450/TMS570 processors
4250 Disabled by default
4251 @end deffn
4254 @node CPU Configuration
4255 @chapter CPU Configuration
4256 @cindex GDB target
4258 This chapter discusses how to set up GDB debug targets for CPUs.
4259 You can also access these targets without GDB
4260 (@pxref{Architecture and Core Commands},
4261 and @ref{targetstatehandling,,Target State handling}) and
4262 through various kinds of NAND and NOR flash commands.
4263 If you have multiple CPUs you can have multiple such targets.
4265 We'll start by looking at how to examine the targets you have,
4266 then look at how to add one more target and how to configure it.
4268 @section Target List
4269 @cindex target, current
4270 @cindex target, list
4272 All targets that have been set up are part of a list,
4273 where each member has a name.
4274 That name should normally be the same as the TAP name.
4275 You can display the list with the @command{targets}
4276 (plural!) command.
4277 This display often has only one CPU; here's what it might
4278 look like with more than one:
4279 @verbatim
4280 TargetName Type Endian TapName State
4281 -- ------------------ ---------- ------ ------------------ ------------
4282 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4283 1 MyTarget cortex_m little mychip.foo tap-disabled
4284 @end verbatim
4286 One member of that list is the @dfn{current target}, which
4287 is implicitly referenced by many commands.
4288 It's the one marked with a @code{*} near the target name.
4289 In particular, memory addresses often refer to the address
4290 space seen by that current target.
4291 Commands like @command{mdw} (memory display words)
4292 and @command{flash erase_address} (erase NOR flash blocks)
4293 are examples; and there are many more.
4295 Several commands let you examine the list of targets:
4297 @deffn Command {target current}
4298 Returns the name of the current target.
4299 @end deffn
4301 @deffn Command {target names}
4302 Lists the names of all current targets in the list.
4303 @example
4304 foreach t [target names] @{
4305 puts [format "Target: %s\n" $t]
4306 @}
4307 @end example
4308 @end deffn
4310 @c yep, "target list" would have been better.
4311 @c plus maybe "target setdefault".
4313 @deffn Command targets [name]
4314 @emph{Note: the name of this command is plural. Other target
4315 command names are singular.}
4317 With no parameter, this command displays a table of all known
4318 targets in a user friendly form.
4320 With a parameter, this command sets the current target to
4321 the given target with the given @var{name}; this is
4322 only relevant on boards which have more than one target.
4323 @end deffn
4325 @section Target CPU Types
4326 @cindex target type
4327 @cindex CPU type
4329 Each target has a @dfn{CPU type}, as shown in the output of
4330 the @command{targets} command. You need to specify that type
4331 when calling @command{target create}.
4332 The CPU type indicates more than just the instruction set.
4333 It also indicates how that instruction set is implemented,
4334 what kind of debug support it integrates,
4335 whether it has an MMU (and if so, what kind),
4336 what core-specific commands may be available
4337 (@pxref{Architecture and Core Commands}),
4338 and more.
4340 It's easy to see what target types are supported,
4341 since there's a command to list them.
4343 @anchor{targettypes}
4344 @deffn Command {target types}
4345 Lists all supported target types.
4346 At this writing, the supported CPU types are:
4348 @itemize @bullet
4349 @item @code{arm11} -- this is a generation of ARMv6 cores
4350 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4351 @item @code{arm7tdmi} -- this is an ARMv4 core
4352 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4353 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4354 @item @code{arm966e} -- this is an ARMv5 core
4355 @item @code{arm9tdmi} -- this is an ARMv4 core
4356 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4357 (Support for this is preliminary and incomplete.)
4358 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4359 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4360 compact Thumb2 instruction set.
4361 @item @code{aarch64} -- this is an ARMv8-A core with an MMU
4362 @item @code{dragonite} -- resembles arm966e
4363 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4364 (Support for this is still incomplete.)
4365 @item @code{esirisc} -- this is an EnSilica eSi-RISC core.
4366 The current implementation supports eSi-32xx cores.
4367 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4368 @item @code{feroceon} -- resembles arm926
4369 @item @code{mips_m4k} -- a MIPS core
4370 @item @code{xscale} -- this is actually an architecture,
4371 not a CPU type. It is based on the ARMv5 architecture.
4372 @item @code{openrisc} -- this is an OpenRISC 1000 core.
4373 The current implementation supports three JTAG TAP cores:
4374 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4375 allowing access to physical memory addresses independently of CPU cores.
4376 @itemize @minus
4377 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag})
4378 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4379 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4380 @end itemize
4381 And two debug interfaces cores:
4382 @itemize @minus
4383 @item @code{Advanced debug interface} (See: @url{http://opencores.org/project,adv_debug_sys})
4384 @item @code{SoC Debug Interface} (See: @url{http://opencores.org/project,dbg_interface})
4385 @end itemize
4386 @end itemize
4387 @end deffn
4389 To avoid being confused by the variety of ARM based cores, remember
4390 this key point: @emph{ARM is a technology licencing company}.
4391 (See: @url{http://www.arm.com}.)
4392 The CPU name used by OpenOCD will reflect the CPU design that was
4393 licensed, not a vendor brand which incorporates that design.
4394 Name prefixes like arm7, arm9, arm11, and cortex
4395 reflect design generations;
4396 while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
4397 reflect an architecture version implemented by a CPU design.
4399 @anchor{targetconfiguration}
4400 @section Target Configuration
4402 Before creating a ``target'', you must have added its TAP to the scan chain.
4403 When you've added that TAP, you will have a @code{dotted.name}
4404 which is used to set up the CPU support.
4405 The chip-specific configuration file will normally configure its CPU(s)
4406 right after it adds all of the chip's TAPs to the scan chain.
4408 Although you can set up a target in one step, it's often clearer if you
4409 use shorter commands and do it in two steps: create it, then configure
4410 optional parts.
4411 All operations on the target after it's created will use a new
4412 command, created as part of target creation.
4414 The two main things to configure after target creation are
4415 a work area, which usually has target-specific defaults even
4416 if the board setup code overrides them later;
4417 and event handlers (@pxref{targetevents,,Target Events}), which tend
4418 to be much more board-specific.
4419 The key steps you use might look something like this
4421 @example
4422 dap create mychip.dap -chain-position mychip.cpu
4423 target create MyTarget cortex_m -dap mychip.dap
4424 MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4425 MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4426 MyTarget configure -event reset-init @{ myboard_reinit @}
4427 @end example
4429 You should specify a working area if you can; typically it uses some
4430 on-chip SRAM.
4431 Such a working area can speed up many things, including bulk
4432 writes to target memory;
4433 flash operations like checking to see if memory needs to be erased;
4434 GDB memory checksumming;
4435 and more.
4437 @quotation Warning
4438 On more complex chips, the work area can become
4439 inaccessible when application code
4440 (such as an operating system)
4441 enables or disables the MMU.
4442 For example, the particular MMU context used to access the virtual
4443 address will probably matter ... and that context might not have
4444 easy access to other addresses needed.
4445 At this writing, OpenOCD doesn't have much MMU intelligence.
4446 @end quotation
4448 It's often very useful to define a @code{reset-init} event handler.
4449 For systems that are normally used with a boot loader,
4450 common tasks include updating clocks and initializing memory
4451 controllers.
4452 That may be needed to let you write the boot loader into flash,
4453 in order to ``de-brick'' your board; or to load programs into
4454 external DDR memory without having run the boot loader.
4456 @deffn Command {target create} target_name type configparams...
4457 This command creates a GDB debug target that refers to a specific JTAG tap.
4458 It enters that target into a list, and creates a new
4459 command (@command{@var{target_name}}) which is used for various
4460 purposes including additional configuration.
4462 @itemize @bullet
4463 @item @var{target_name} ... is the name of the debug target.
4464 By convention this should be the same as the @emph{dotted.name}
4465 of the TAP associated with this target, which must be specified here
4466 using the @code{-chain-position @var{dotted.name}} configparam.
4468 This name is also used to create the target object command,
4469 referred to here as @command{$target_name},
4470 and in other places the target needs to be identified.
4471 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4472 @item @var{configparams} ... all parameters accepted by
4473 @command{$target_name configure} are permitted.
4474 If the target is big-endian, set it here with @code{-endian big}.
4476 You @emph{must} set the @code{-chain-position @var{dotted.name}} or
4477 @code{-dap @var{dap_name}} here.
4478 @end itemize
4479 @end deffn
4481 @deffn Command {$target_name configure} configparams...
4482 The options accepted by this command may also be
4483 specified as parameters to @command{target create}.
4484 Their values can later be queried one at a time by
4485 using the @command{$target_name cget} command.
4487 @emph{Warning:} changing some of these after setup is dangerous.
4488 For example, moving a target from one TAP to another;
4489 and changing its endianness.
4491 @itemize @bullet
4493 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4494 used to access this target.
4496 @item @code{-dap} @var{dap_name} -- names the DAP used to access
4497 this target. @xref{dapdeclaration,,DAP declaration}, on how to
4498 create and manage DAP instances.
4500 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4501 whether the CPU uses big or little endian conventions
4503 @item @code{-event} @var{event_name} @var{event_body} --
4504 @xref{targetevents,,Target Events}.
4505 Note that this updates a list of named event handlers.
4506 Calling this twice with two different event names assigns
4507 two different handlers, but calling it twice with the
4508 same event name assigns only one handler.
4510 Current target is temporarily overridden to the event issuing target
4511 before handler code starts and switched back after handler is done.
4513 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4514 whether the work area gets backed up; by default,
4515 @emph{it is not backed up.}
4516 When possible, use a working_area that doesn't need to be backed up,
4517 since performing a backup slows down operations.
4518 For example, the beginning of an SRAM block is likely to
4519 be used by most build systems, but the end is often unused.
4521 @item @code{-work-area-size} @var{size} -- specify work are size,
4522 in bytes. The same size applies regardless of whether its physical
4523 or virtual address is being used.
4525 @item @code{-work-area-phys} @var{address} -- set the work area
4526 base @var{address} to be used when no MMU is active.
4528 @item @code{-work-area-virt} @var{address} -- set the work area
4529 base @var{address} to be used when an MMU is active.
4530 @emph{Do not specify a value for this except on targets with an MMU.}
4531 The value should normally correspond to a static mapping for the
4532 @code{-work-area-phys} address, set up by the current operating system.
4534 @anchor{rtostype}
4535 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4536 @var{rtos_type} can be one of @option{auto}, @option{eCos},
4537 @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
4538 @option{embKernel}, @option{mqx}, @option{uCOS-III}, @option{nuttx}
4539 @xref{gdbrtossupport,,RTOS Support}.
4541 @item @code{-defer-examine} -- skip target examination at initial JTAG chain
4542 scan and after a reset. A manual call to arp_examine is required to
4543 access the target for debugging.
4545 @item @code{-ap-num} @var{ap_number} -- set DAP access port for target,
4546 @var{ap_number} is the numeric index of the DAP AP the target is connected to.
4547 Use this option with systems where multiple, independent cores are connected
4548 to separate access ports of the same DAP.
4550 @item @code{-cti} @var{cti_name} -- set Cross-Trigger Interface (CTI) connected
4551 to the target. Currently, only the @code{aarch64} target makes use of this option,
4552 where it is a mandatory configuration for the target run control.
4553 @xref{armcrosstrigger,,ARM Cross-Trigger Interface},
4554 for instruction on how to declare and control a CTI instance.
4556 @anchor{gdbportoverride}
4557 @item @code{-gdb-port} @var{number} -- see command @command{gdb_port} for the
4558 possible values of the parameter @var{number}, which are not only numeric values.
4559 Use this option to override, for this target only, the global parameter set with
4560 command @command{gdb_port}.
4561 @xref{gdb_port,,command gdb_port}.
4562 @end itemize
4563 @end deffn
4565 @section Other $target_name Commands
4566 @cindex object command
4568 The Tcl/Tk language has the concept of object commands,
4569 and OpenOCD adopts that same model for targets.
4571 A good Tk example is a on screen button.
4572 Once a button is created a button
4573 has a name (a path in Tk terms) and that name is useable as a first
4574 class command. For example in Tk, one can create a button and later
4575 configure it like this:
4577 @example
4578 # Create
4579 button .foobar -background red -command @{ foo @}
4580 # Modify
4581 .foobar configure -foreground blue
4582 # Query
4583 set x [.foobar cget -background]
4584 # Report
4585 puts [format "The button is %s" $x]
4586 @end example
4588 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4589 button, and its object commands are invoked the same way.
4591 @example
4592 str912.cpu mww 0x1234 0x42
4593 omap3530.cpu mww 0x5555 123
4594 @end example
4596 The commands supported by OpenOCD target objects are:
4598 @deffn Command {$target_name arp_examine} @option{allow-defer}
4599 @deffnx Command {$target_name arp_halt}
4600 @deffnx Command {$target_name arp_poll}
4601 @deffnx Command {$target_name arp_reset}
4602 @deffnx Command {$target_name arp_waitstate}
4603 Internal OpenOCD scripts (most notably @file{startup.tcl})
4604 use these to deal with specific reset cases.
4605 They are not otherwise documented here.
4606 @end deffn
4608 @deffn Command {$target_name array2mem} arrayname width address count
4609 @deffnx Command {$target_name mem2array} arrayname width address count
4610 These provide an efficient script-oriented interface to memory.
4611 The @code{array2mem} primitive writes bytes, halfwords, or words;
4612 while @code{mem2array} reads them.
4613 In both cases, the TCL side uses an array, and
4614 the target side uses raw memory.
4616 The efficiency comes from enabling the use of
4617 bulk JTAG data transfer operations.
4618 The script orientation comes from working with data
4619 values that are packaged for use by TCL scripts;
4620 @command{mdw} type primitives only print data they retrieve,
4621 and neither store nor return those values.
4623 @itemize
4624 @item @var{arrayname} ... is the name of an array variable
4625 @item @var{width} ... is 8/16/32 - indicating the memory access size
4626 @item @var{address} ... is the target memory address
4627 @item @var{count} ... is the number of elements to process
4628 @end itemize
4629 @end deffn
4631 @deffn Command {$target_name cget} queryparm
4632 Each configuration parameter accepted by
4633 @command{$target_name configure}
4634 can be individually queried, to return its current value.
4635 The @var{queryparm} is a parameter name
4636 accepted by that command, such as @code{-work-area-phys}.
4637 There are a few special cases:
4639 @itemize @bullet
4640 @item @code{-event} @var{event_name} -- returns the handler for the
4641 event named @var{event_name}.
4642 This is a special case because setting a handler requires
4643 two parameters.
4644 @item @code{-type} -- returns the target type.
4645 This is a special case because this is set using
4646 @command{target create} and can't be changed
4647 using @command{$target_name configure}.
4648 @end itemize
4650 For example, if you wanted to summarize information about
4651 all the targets you might use something like this:
4653 @example
4654 foreach name [target names] @{
4655 set y [$name cget -endian]
4656 set z [$name cget -type]
4657 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4658 $x $name $y $z]
4659 @}
4660 @end example
4661 @end deffn
4663 @anchor{targetcurstate}
4664 @deffn Command {$target_name curstate}
4665 Displays the current target state:
4666 @code{debug-running},
4667 @code{halted},
4668 @code{reset},
4669 @code{running}, or @code{unknown}.
4670 (Also, @pxref{eventpolling,,Event Polling}.)
4671 @end deffn
4673 @deffn Command {$target_name eventlist}
4674 Displays a table listing all event handlers
4675 currently associated with this target.
4676 @xref{targetevents,,Target Events}.
4677 @end deffn
4679 @deffn Command {$target_name invoke-event} event_name
4680 Invokes the handler for the event named @var{event_name}.
4681 (This is primarily intended for use by OpenOCD framework
4682 code, for example by the reset code in @file{startup.tcl}.)
4683 @end deffn
4685 @deffn Command {$target_name mdw} addr [count]
4686 @deffnx Command {$target_name mdh} addr [count]
4687 @deffnx Command {$target_name mdb} addr [count]
4688 Display contents of address @var{addr}, as
4689 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4690 or 8-bit bytes (@command{mdb}).
4691 If @var{count} is specified, displays that many units.
4692 (If you want to manipulate the data instead of displaying it,
4693 see the @code{mem2array} primitives.)
4694 @end deffn
4696 @deffn Command {$target_name mww} addr word
4697 @deffnx Command {$target_name mwh} addr halfword
4698 @deffnx Command {$target_name mwb} addr byte
4699 Writes the specified @var{word} (32 bits),
4700 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4701 at the specified address @var{addr}.
4702 @end deffn
4704 @anchor{targetevents}
4705 @section Target Events
4706 @cindex target events
4707 @cindex events
4708 At various times, certain things can happen, or you want them to happen.
4709 For example:
4710 @itemize @bullet
4711 @item What should happen when GDB connects? Should your target reset?
4712 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4713 @item Is using SRST appropriate (and possible) on your system?
4714 Or instead of that, do you need to issue JTAG commands to trigger reset?
4715 SRST usually resets everything on the scan chain, which can be inappropriate.
4716 @item During reset, do you need to write to certain memory locations
4717 to set up system clocks or
4718 to reconfigure the SDRAM?
4719 How about configuring the watchdog timer, or other peripherals,
4720 to stop running while you hold the core stopped for debugging?
4721 @end itemize
4723 All of the above items can be addressed by target event handlers.
4724 These are set up by @command{$target_name configure -event} or
4725 @command{target create ... -event}.
4727 The programmer's model matches the @code{-command} option used in Tcl/Tk
4728 buttons and events. The two examples below act the same, but one creates
4729 and invokes a small procedure while the other inlines it.
4731 @example
4732 proc my_init_proc @{ @} @{
4733 echo "Disabling watchdog..."
4734 mww 0xfffffd44 0x00008000
4735 @}
4736 mychip.cpu configure -event reset-init my_init_proc
4737 mychip.cpu configure -event reset-init @{
4738 echo "Disabling watchdog..."
4739 mww 0xfffffd44 0x00008000
4740 @}
4741 @end example
4743 The following target events are defined:
4745 @itemize @bullet
4746 @item @b{debug-halted}
4747 @* The target has halted for debug reasons (i.e.: breakpoint)
4748 @item @b{debug-resumed}
4749 @* The target has resumed (i.e.: GDB said run)
4750 @item @b{early-halted}
4751 @* Occurs early in the halt process
4752 @item @b{examine-start}
4753 @* Before target examine is called.
4754 @item @b{examine-end}
4755 @* After target examine is called with no errors.
4756 @item @b{gdb-attach}
4757 @* When GDB connects. Issued before any GDB communication with the target
4758 starts. GDB expects the target is halted during attachment.
4759 @xref{gdbmeminspect,,GDB as a non-intrusive memory inspector}, how to
4760 connect GDB to running target.
4761 The event can be also used to set up the target so it is possible to probe flash.
4762 Probing flash is necessary during GDB connect if you want to use
4763 @pxref{programmingusinggdb,,programming using GDB}.
4764 Another use of the flash memory map is for GDB to automatically choose
4765 hardware or software breakpoints depending on whether the breakpoint
4766 is in RAM or read only memory.
4767 Default is @code{halt}
4768 @item @b{gdb-detach}
4769 @* When GDB disconnects
4770 @item @b{gdb-end}
4771 @* When the target has halted and GDB is not doing anything (see early halt)
4772 @item @b{gdb-flash-erase-start}
4773 @* Before the GDB flash process tries to erase the flash (default is
4774 @code{reset init})
4775 @item @b{gdb-flash-erase-end}
4776 @* After the GDB flash process has finished erasing the flash
4777 @item @b{gdb-flash-write-start}
4778 @* Before GDB writes to the flash
4779 @item @b{gdb-flash-write-end}
4780 @* After GDB writes to the flash (default is @code{reset halt})
4781 @item @b{gdb-start}
4782 @* Before the target steps, GDB is trying to start/resume the target
4783 @item @b{halted}
4784 @* The target has halted
4785 @item @b{reset-assert-pre}
4786 @* Issued as part of @command{reset} processing
4787 after @command{reset-start} was triggered
4788 but before either SRST alone is asserted on the scan chain,
4789 or @code{reset-assert} is triggered.
4790 @item @b{reset-assert}
4791 @* Issued as part of @command{reset} processing
4792 after @command{reset-assert-pre} was triggered.
4793 When such a handler is present, cores which support this event will use
4794 it instead of asserting SRST.
4795 This support is essential for debugging with JTAG interfaces which
4796 don't include an SRST line (JTAG doesn't require SRST), and for
4797 selective reset on scan chains that have multiple targets.
4798 @item @b{reset-assert-post}
4799 @* Issued as part of @command{reset} processing
4800 after @code{reset-assert} has been triggered.
4801 or the target asserted SRST on the entire scan chain.
4802 @item @b{reset-deassert-pre}
4803 @* Issued as part of @command{reset} processing
4804 after @code{reset-assert-post} has been triggered.
4805 @item @b{reset-deassert-post}
4806 @* Issued as part of @command{reset} processing
4807 after @code{reset-deassert-pre} has been triggered
4808 and (if the target is using it) after SRST has been
4809 released on the scan chain.
4810 @item @b{reset-end}
4811 @* Issued as the final step in @command{reset} processing.
4812 @item @b{reset-init}
4813 @* Used by @b{reset init} command for board-specific initialization.
4814 This event fires after @emph{reset-deassert-post}.
4816 This is where you would configure PLLs and clocking, set up DRAM so
4817 you can download programs that don't fit in on-chip SRAM, set up pin
4818 multiplexing, and so on.
4819 (You may be able to switch to a fast JTAG clock rate here, after
4820 the target clocks are fully set up.)
4821 @item @b{reset-start}
4822 @* Issued as the first step in @command{reset} processing
4823 before @command{reset-assert-pre} is called.
4825 This is the most robust place to use @command{jtag_rclk}
4826 or @command{adapter_khz} to switch to a low JTAG clock rate,
4827 when reset disables PLLs needed to use a fast clock.
4828 @item @b{resume-start}
4829 @* Before any target is resumed
4830 @item @b{resume-end}
4831 @* After all targets have resumed
4832 @item @b{resumed}
4833 @* Target has resumed
4834 @item @b{trace-config}
4835 @* After target hardware trace configuration was changed
4836 @end itemize
4838 @node Flash Commands
4839 @chapter Flash Commands
4841 OpenOCD has different commands for NOR and NAND flash;
4842 the ``flash'' command works with NOR flash, while
4843 the ``nand'' command works with NAND flash.
4844 This partially reflects different hardware technologies:
4845 NOR flash usually supports direct CPU instruction and data bus access,
4846 while data from a NAND flash must be copied to memory before it can be
4847 used. (SPI flash must also be copied to memory before use.)
4848 However, the documentation also uses ``flash'' as a generic term;
4849 for example, ``Put flash configuration in board-specific files''.
4851 Flash Steps:
4852 @enumerate
4853 @item Configure via the command @command{flash bank}
4854 @* Do this in a board-specific configuration file,
4855 passing parameters as needed by the driver.
4856 @item Operate on the flash via @command{flash subcommand}
4857 @* Often commands to manipulate the flash are typed by a human, or run
4858 via a script in some automated way. Common tasks include writing a
4859 boot loader, operating system, or other data.
4860 @item GDB Flashing
4861 @* Flashing via GDB requires the flash be configured via ``flash
4862 bank'', and the GDB flash features be enabled.
4863 @xref{gdbconfiguration,,GDB Configuration}.
4864 @end enumerate
4866 Many CPUs have the ability to ``boot'' from the first flash bank.
4867 This means that misprogramming that bank can ``brick'' a system,
4868 so that it can't boot.
4869 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4870 board by (re)installing working boot firmware.
4872 @anchor{norconfiguration}
4873 @section Flash Configuration Commands
4874 @cindex flash configuration
4876 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4877 Configures a flash bank which provides persistent storage
4878 for addresses from @math{base} to @math{base + size - 1}.
4879 These banks will often be visible to GDB through the target's memory map.
4880 In some cases, configuring a flash bank will activate extra commands;
4881 see the driver-specific documentation.
4883 @itemize @bullet
4884 @item @var{name} ... may be used to reference the flash bank
4885 in other flash commands. A number is also available.
4886 @item @var{driver} ... identifies the controller driver
4887 associated with the flash bank being declared.
4888 This is usually @code{cfi} for external flash, or else
4889 the name of a microcontroller with embedded flash memory.
4890 @xref{flashdriverlist,,Flash Driver List}.
4891 @item @var{base} ... Base address of the flash chip.
4892 @item @var{size} ... Size of the chip, in bytes.
4893 For some drivers, this value is detected from the hardware.
4894 @item @var{chip_width} ... Width of the flash chip, in bytes;
4895 ignored for most microcontroller drivers.
4896 @item @var{bus_width} ... Width of the data bus used to access the
4897 chip, in bytes; ignored for most microcontroller drivers.
4898 @item @var{target} ... Names the target used to issue
4899 commands to the flash controller.
4900 @comment Actually, it's currently a controller-specific parameter...
4901 @item @var{driver_options} ... drivers may support, or require,
4902 additional parameters. See the driver-specific documentation
4903 for more information.
4904 @end itemize
4905 @quotation Note
4906 This command is not available after OpenOCD initialization has completed.
4907 Use it in board specific configuration files, not interactively.
4908 @end quotation
4909 @end deffn
4911 @comment the REAL name for this command is "ocd_flash_banks"
4912 @comment less confusing would be: "flash list" (like "nand list")
4913 @deffn Command {flash banks}
4914 Prints a one-line summary of each device that was
4915 declared using @command{flash bank}, numbered from zero.
4916 Note that this is the @emph{plural} form;
4917 the @emph{singular} form is a very different command.
4918 @end deffn
4920 @deffn Command {flash list}
4921 Retrieves a list of associative arrays for each device that was
4922 declared using @command{flash bank}, numbered from zero.
4923 This returned list can be manipulated easily from within scripts.
4924 @end deffn
4926 @deffn Command {flash probe} num
4927 Identify the flash, or validate the parameters of the configured flash. Operation
4928 depends on the flash type.
4929 The @var{num} parameter is a value shown by @command{flash banks}.
4930 Most flash commands will implicitly @emph{autoprobe} the bank;
4931 flash drivers can distinguish between probing and autoprobing,
4932 but most don't bother.
4933 @end deffn
4935 @section Erasing, Reading, Writing to Flash
4936 @cindex flash erasing
4937 @cindex flash reading
4938 @cindex flash writing
4939 @cindex flash programming
4940 @anchor{flashprogrammingcommands}
4942 One feature distinguishing NOR flash from NAND or serial flash technologies
4943 is that for read access, it acts exactly like any other addressable memory.
4944 This means you can use normal memory read commands like @command{mdw} or
4945 @command{dump_image} with it, with no special @command{flash} subcommands.
4946 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
4948 Write access works differently. Flash memory normally needs to be erased
4949 before it's written. Erasing a sector turns all of its bits to ones, and
4950 writing can turn ones into zeroes. This is why there are special commands
4951 for interactive erasing and writing, and why GDB needs to know which parts
4952 of the address space hold NOR flash memory.
4954 @quotation Note
4955 Most of these erase and write commands leverage the fact that NOR flash
4956 chips consume target address space. They implicitly refer to the current
4957 JTAG target, and map from an address in that target's address space
4958 back to a flash bank.
4959 @comment In May 2009, those mappings may fail if any bank associated
4960 @comment with that target doesn't successfully autoprobe ... bug worth fixing?
4961 A few commands use abstract addressing based on bank and sector numbers,
4962 and don't depend on searching the current target and its address space.
4963 Avoid confusing the two command models.
4964 @end quotation
4966 Some flash chips implement software protection against accidental writes,
4967 since such buggy writes could in some cases ``brick'' a system.
4968 For such systems, erasing and writing may require sector protection to be
4969 disabled first.
4970 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4971 and AT91SAM7 on-chip flash.
4972 @xref{flashprotect,,flash protect}.
4974 @deffn Command {flash erase_sector} num first last
4975 Erase sectors in bank @var{num}, starting at sector @var{first}
4976 up to and including @var{last}.
4977 Sector numbering starts at 0.
4978 Providing a @var{last} sector of @option{last}
4979 specifies "to the end of the flash bank".
4980 The @var{num} parameter is a value shown by @command{flash banks}.
4981 @end deffn
4983 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4984 Erase sectors starting at @var{address} for @var{length} bytes.
4985 Unless @option{pad} is specified, @math{address} must begin a
4986 flash sector, and @math{address + length - 1} must end a sector.
4987 Specifying @option{pad} erases extra data at the beginning and/or
4988 end of the specified region, as needed to erase only full sectors.
4989 The flash bank to use is inferred from the @var{address}, and
4990 the specified length must stay within that bank.
4991 As a special case, when @var{length} is zero and @var{address} is
4992 the start of the bank, the whole flash is erased.
4993 If @option{unlock} is specified, then the flash is unprotected
4994 before erase starts.
4995 @end deffn
4997 @deffn Command {flash fillw} address word length
4998 @deffnx Command {flash fillh} address halfword length
4999 @deffnx Command {flash fillb} address byte length
5000 Fills flash memory with the specified @var{word} (32 bits),
5001 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5002 starting at @var{address} and continuing
5003 for @var{length} units (word/halfword/byte).
5004 No erasure is done before writing; when needed, that must be done
5005 before issuing this command.
5006 Writes are done in blocks of up to 1024 bytes, and each write is
5007 verified by reading back the data and comparing it to what was written.
5008 The flash bank to use is inferred from the @var{address} of
5009 each block, and the specified length must stay within that bank.
5010 @end deffn
5011 @comment no current checks for errors if fill blocks touch multiple banks!
5013 @deffn Command {flash write_bank} num filename [offset]
5014 Write the binary @file{filename} to flash bank @var{num},
5015 starting at @var{offset} bytes from the beginning of the bank. If @var{offset}
5016 is omitted, start at the beginning of the flash bank.
5017 The @var{num} parameter is a value shown by @command{flash banks}.
5018 @end deffn
5020 @deffn Command {flash read_bank} num filename [offset [length]]
5021 Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
5022 and write the contents to the binary @file{filename}. If @var{offset} is
5023 omitted, start at the beginning of the flash bank. If @var{length} is omitted,
5024 read the remaining bytes from the flash bank.
5025 The @var{num} parameter is a value shown by @command{flash banks}.
5026 @end deffn
5028 @deffn Command {flash verify_bank} num filename [offset]
5029 Compare the contents of the binary file @var{filename} with the contents of the
5030 flash bank @var{num} starting at @var{offset}. If @var{offset} is omitted,
5031 start at the beginning of the flash bank. Fail if the contents do not match.
5032 The @var{num} parameter is a value shown by @command{flash banks}.
5033 @end deffn
5035 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
5036 Write the image @file{filename} to the current target's flash bank(s).
5037 Only loadable sections from the image are written.
5038 A relocation @var{offset} may be specified, in which case it is added
5039 to the base address for each section in the image.
5040 The file [@var{type}] can be specified
5041 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
5042 @option{elf} (ELF file), @option{s19} (Motorola s19).
5043 @option{mem}, or @option{builder}.
5044 The relevant flash sectors will be erased prior to programming
5045 if the @option{erase} parameter is given. If @option{unlock} is
5046 provided, then the flash banks are unlocked before erase and
5047 program. The flash bank to use is inferred from the address of
5048 each image section.
5050 @quotation Warning
5051 Be careful using the @option{erase} flag when the flash is holding
5052 data you want to preserve.
5053 Portions of the flash outside those described in the image's
5054 sections might be erased with no notice.
5055 @itemize
5056 @item
5057 When a section of the image being written does not fill out all the
5058 sectors it uses, the unwritten parts of those sectors are necessarily
5059 also erased, because sectors can't be partially erased.
5060 @item
5061 Data stored in sector "holes" between image sections are also affected.
5062 For example, "@command{flash write_image erase ...}" of an image with
5063 one byte at the beginning of a flash bank and one byte at the end
5064 erases the entire bank -- not just the two sectors being written.
5065 @end itemize