[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * TFTP:: TFTP
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
94 @end menu
96 @node About
97 @unnumbered About
98 @cindex about
100 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
101 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
104 around the world.
106 @section What is OpenOCD?
107 @cindex TAP
108 @cindex JTAG
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
112 devices.
114 It does so with the assistance of a @dfn{debug adapter}, which is
115 a small hardware module which helps provide the right kind of
116 electrical signaling to the target being debugged. These are
117 required since the debug host (on which OpenOCD runs) won't
118 usually have native support for such signaling, or the connector
119 needed to hook up to the target.
121 Such debug adapters support one or more @dfn{transport} protocols,
122 each of which involves different electrical signaling (and uses
123 different messaging protocols on top of that signaling). There
124 are many types of debug adapter, and little uniformity in what
125 they are called. (There are also product naming differences.)
127 These adapters are sometimes packaged as discrete dongles, which
128 may generically be called @dfn{hardware interface dongles}.
129 Some development boards also integrate them directly, which may
130 let the development board can be directly connected to the debug
131 host over USB (and sometimes also to power it over USB).
133 For example, a @dfn{JTAG Adapter} supports JTAG
134 signaling, and is used to communicate
135 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
136 A @dfn{TAP} is a ``Test Access Port'', a module which processes
137 special instructions and data. TAPs are daisy-chained within and
138 between chips and boards. JTAG supports debugging and boundary
139 scan operations.
141 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
142 signaling to communicate with some newer ARM cores, as well as debug
143 adapters which support both JTAG and SWD transports. SWD only supports
144 debugging, whereas JTAG also supports boundary scan operations.
146 For some chips, there are also @dfn{Programming Adapters} supporting
147 special transports used only to write code to flash memory, without
148 support for on-chip debugging or boundary scan.
149 (At this writing, OpenOCD does not support such non-debug adapters.)
152 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
153 based, parallel port based, and other standalone boxes that run
154 OpenOCD internally. @xref{Debug Adapter Hardware}.
156 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
157 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
158 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
159 debugged via the GDB protocol.
161 @b{Flash Programing:} Flash writing is supported for external CFI
162 compatible NOR flashes (Intel and AMD/Spansion command set) and several
163 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
164 STM32x). Preliminary support for various NAND flash controllers
165 (LPC3180, Orion, S3C24xx, more) controller is included.
167 @section OpenOCD Web Site
169 The OpenOCD web site provides the latest public news from the community:
171 @uref{http://openocd.sourceforge.net/}
173 @section Latest User's Guide:
175 The user's guide you are now reading may not be the latest one
176 available. A version for more recent code may be available.
177 Its HTML form is published irregularly at:
179 @uref{http://openocd.sourceforge.net/doc/html/index.html}
181 PDF form is likewise published at:
183 @uref{http://openocd.sourceforge.net/doc/pdf/openocd.pdf}
185 @section OpenOCD User's Forum
187 There is an OpenOCD forum (phpBB) hosted by SparkFun,
188 which might be helpful to you. Note that if you want
189 anything to come to the attention of developers, you
190 should post it to the OpenOCD Developer Mailing List
191 instead of this forum.
193 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @node Developers
197 @chapter OpenOCD Developer Resources
198 @cindex developers
200 If you are interested in improving the state of OpenOCD's debugging and
201 testing support, new contributions will be welcome. Motivated developers
202 can produce new target, flash or interface drivers, improve the
203 documentation, as well as more conventional bug fixes and enhancements.
205 The resources in this chapter are available for developers wishing to explore
206 or expand the OpenOCD source code.
208 @section OpenOCD GIT Repository
210 During the 0.3.x release cycle, OpenOCD switched from Subversion to
211 a GIT repository hosted at SourceForge. The repository URL is:
213 @uref{git://openocd.git.sourceforge.net/gitroot/openocd/openocd}
215 You may prefer to use a mirror and the HTTP protocol:
217 @uref{http://repo.or.cz/r/openocd.git}
219 With standard GIT tools, use @command{git clone} to initialize
220 a local repository, and @command{git pull} to update it.
221 There are also gitweb pages letting you browse the repository
222 with a web browser, or download arbitrary snapshots without
223 needing a GIT client:
225 @uref{http://openocd.git.sourceforge.net/git/gitweb.cgi?p=openocd/openocd}
227 @uref{http://repo.or.cz/w/openocd.git}
229 The @file{README} file contains the instructions for building the project
230 from the repository or a snapshot.
232 Developers that want to contribute patches to the OpenOCD system are
233 @b{strongly} encouraged to work against mainline.
234 Patches created against older versions may require additional
235 work from their submitter in order to be updated for newer releases.
237 @section Doxygen Developer Manual
239 During the 0.2.x release cycle, the OpenOCD project began
240 providing a Doxygen reference manual. This document contains more
241 technical information about the software internals, development
242 processes, and similar documentation:
244 @uref{http://openocd.sourceforge.net/doc/doxygen/html/index.html}
246 This document is a work-in-progress, but contributions would be welcome
247 to fill in the gaps. All of the source files are provided in-tree,
248 listed in the Doxyfile configuration in the top of the source tree.
250 @section OpenOCD Developer Mailing List
252 The OpenOCD Developer Mailing List provides the primary means of
253 communication between developers:
255 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
257 Discuss and submit patches to this list.
258 The @file{HACKING} file contains basic information about how
259 to prepare patches.
261 @section OpenOCD Bug Database
263 During the 0.4.x release cycle the OpenOCD project team began
264 using Trac for its bug database:
266 @uref{https://sourceforge.net/apps/trac/openocd}
269 @node Debug Adapter Hardware
270 @chapter Debug Adapter Hardware
271 @cindex dongles
272 @cindex FTDI
273 @cindex wiggler
274 @cindex zy1000
275 @cindex printer port
276 @cindex USB Adapter
277 @cindex RTCK
279 Defined: @b{dongle}: A small device that plugins into a computer and serves as
280 an adapter .... [snip]
282 In the OpenOCD case, this generally refers to @b{a small adapter} that
283 attaches to your computer via USB or the Parallel Printer Port. One
284 exception is the Zylin ZY1000, packaged as a small box you attach via
285 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
286 require any drivers to be installed on the developer PC. It also has
287 a built in web interface. It supports RTCK/RCLK or adaptive clocking
288 and has a built in relay to power cycle targets remotely.
291 @section Choosing a Dongle
293 There are several things you should keep in mind when choosing a dongle.
295 @enumerate
296 @item @b{Transport} Does it support the kind of communication that you need?
297 OpenOCD focusses mostly on JTAG. Your version may also support
298 other ways to communicate with target devices.
299 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
300 Does your dongle support it? You might need a level converter.
301 @item @b{Pinout} What pinout does your target board use?
302 Does your dongle support it? You may be able to use jumper
303 wires, or an "octopus" connector, to convert pinouts.
304 @item @b{Connection} Does your computer have the USB, printer, or
305 Ethernet port needed?
306 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
307 RTCK support? Also known as ``adaptive clocking''
308 @end enumerate
310 @section Stand alone Systems
312 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/33-zylin-zy1000-jtag-probe} Technically, not a
313 dongle, but a standalone box. The ZY1000 has the advantage that it does
314 not require any drivers installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built in relay to power cycle targets remotely.
318 @section USB FT2232 Based
320 There are many USB JTAG dongles on the market, many of them are based
321 on a chip from ``Future Technology Devices International'' (FTDI)
322 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
323 See: @url{http://www.ftdichip.com} for more information.
324 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
325 chips are starting to become available in JTAG adapters. (Adapters
326 using those high speed FT2232H chips may support adaptive clocking.)
328 The FT2232 chips are flexible enough to support some other
329 transport options, such as SWD or the SPI variants used to
330 program some chips. They have two communications channels,
331 and one can be used for a UART adapter at the same time the
332 other one is used to provide a debug adapter.
334 Also, some development boards integrate an FT2232 chip to serve as
335 a built-in low cost debug adapter and usb-to-serial solution.
337 @itemize @bullet
338 @item @b{usbjtag}
339 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
340 @item @b{jtagkey}
341 @* See: @url{http://www.amontec.com/jtagkey.shtml}
342 @item @b{jtagkey2}
343 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
344 @item @b{oocdlink}
345 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
346 @item @b{signalyzer}
347 @* See: @url{http://www.signalyzer.com}
348 @item @b{Stellaris Eval Boards}
349 @* See: @url{http://www.luminarymicro.com} - The Stellaris eval boards
350 bundle FT2232-based JTAG and SWD support, which can be used to debug
351 the Stellaris chips. Using separate JTAG adapters is optional.
352 These boards can also be used in a "pass through" mode as JTAG adapters
353 to other target boards, disabling the Stellaris chip.
354 @item @b{Luminary ICDI}
355 @* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug
356 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
357 Evaluation Kits. Like the non-detachable FT2232 support on the other
358 Stellaris eval boards, they can be used to debug other target boards.
359 @item @b{olimex-jtag}
360 @* See: @url{http://www.olimex.com}
361 @item @b{Flyswatter/Flyswatter2}
362 @* See: @url{http://www.tincantools.com}
363 @item @b{turtelizer2}
364 @* See:
365 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
366 @url{http://www.ethernut.de}
367 @item @b{comstick}
368 @* Link: @url{http://www.hitex.com/index.php?id=383}
369 @item @b{stm32stick}
370 @* Link @url{http://www.hitex.com/stm32-stick}
371 @item @b{axm0432_jtag}
372 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
373 to be available anymore as of April 2012.
374 @item @b{cortino}
375 @* Link @url{http://www.hitex.com/index.php?id=cortino}
376 @item @b{dlp-usb1232h}
377 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
378 @item @b{digilent-hs1}
379 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
380 @end itemize
382 @section USB-JTAG / Altera USB-Blaster compatibles
384 These devices also show up as FTDI devices, but are not
385 protocol-compatible with the FT2232 devices. They are, however,
386 protocol-compatible among themselves. USB-JTAG devices typically consist
387 of a FT245 followed by a CPLD that understands a particular protocol,
388 or emulate this protocol using some other hardware.
390 They may appear under different USB VID/PID depending on the particular
391 product. The driver can be configured to search for any VID/PID pair
392 (see the section on driver commands).
394 @itemize
395 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
396 @* Link: @url{http://ixo-jtag.sourceforge.net/}
397 @item @b{Altera USB-Blaster}
398 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
399 @end itemize
401 @section USB JLINK based
402 There are several OEM versions of the Segger @b{JLINK} adapter. It is
403 an example of a micro controller based JTAG adapter, it uses an
404 AT91SAM764 internally.
406 @itemize @bullet
407 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
408 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
409 @item @b{SEGGER JLINK}
410 @* Link: @url{http://www.segger.com/jlink.html}
411 @item @b{IAR J-Link}
412 @* Link: @url{http://www.iar.com/en/products/hardware-debug-probes/iar-j-link/}
413 @end itemize
415 @section USB RLINK based
416 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
418 @itemize @bullet
419 @item @b{Raisonance RLink}
420 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
421 @item @b{STM32 Primer}
422 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
423 @item @b{STM32 Primer2}
424 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
425 @end itemize
427 @section USB ST-LINK based
428 ST Micro has an adapter called @b{ST-LINK}.
429 They only work with ST Micro chips, notably STM32 and STM8.
431 @itemize @bullet
432 @item @b{ST-LINK}
433 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
434 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
435 @item @b{ST-LINK/V2}
436 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
437 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
438 @end itemize
440 For info the original ST-LINK enumerates using the mass storage usb class, however
441 it's implementation is completely broken. The result is this causes issues under linux.
442 The simplest solution is to get linux to ignore the ST-LINK using one of the following methods:
443 @itemize @bullet
444 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
445 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
446 @end itemize
448 @section USB Other
449 @itemize @bullet
450 @item @b{USBprog}
451 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
453 @item @b{USB - Presto}
454 @* Link: @url{http://tools.asix.net/prg_presto.htm}
456 @item @b{Versaloon-Link}
457 @* Link: @url{http://www.versaloon.com}
459 @item @b{ARM-JTAG-EW}
460 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
462 @item @b{Buspirate}
463 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
465 @item @b{opendous}
466 @* Link: @url{http://code.google.com/p/opendous-jtag/}
468 @item @b{estick}
469 @* Link: @url{http://code.google.com/p/estick-jtag/}
470 @end itemize
472 @section IBM PC Parallel Printer Port Based
474 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
475 and the Macraigor Wiggler. There are many clones and variations of
476 these on the market.
478 Note that parallel ports are becoming much less common, so if you
479 have the choice you should probably avoid these adapters in favor
480 of USB-based ones.
482 @itemize @bullet
484 @item @b{Wiggler} - There are many clones of this.
485 @* Link: @url{http://www.macraigor.com/wiggler.htm}
487 @item @b{DLC5} - From XILINX - There are many clones of this
488 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
489 produced, PDF schematics are easily found and it is easy to make.
491 @item @b{Amontec - JTAG Accelerator}
492 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
494 @item @b{GW16402}
495 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
497 @item @b{Wiggler2}
498 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
500 @item @b{Wiggler_ntrst_inverted}
501 @* Yet another variation - See the source code, src/jtag/parport.c
503 @item @b{old_amt_wiggler}
504 @* Unknown - probably not on the market today
506 @item @b{arm-jtag}
507 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
509 @item @b{chameleon}
510 @* Link: @url{http://www.amontec.com/chameleon.shtml}
512 @item @b{Triton}
513 @* Unknown.
515 @item @b{Lattice}
516 @* ispDownload from Lattice Semiconductor
517 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
519 @item @b{flashlink}
520 @* From ST Microsystems;
521 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
523 @end itemize
525 @section Other...
526 @itemize @bullet
528 @item @b{ep93xx}
529 @* An EP93xx based Linux machine using the GPIO pins directly.
531 @item @b{at91rm9200}
532 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
534 @end itemize
536 @node About Jim-Tcl
537 @chapter About Jim-Tcl
538 @cindex Jim-Tcl
539 @cindex tcl
541 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
542 This programming language provides a simple and extensible
543 command interpreter.
545 All commands presented in this Guide are extensions to Jim-Tcl.
546 You can use them as simple commands, without needing to learn
547 much of anything about Tcl.
548 Alternatively, can write Tcl programs with them.
550 You can learn more about Jim at its website, @url{http://jim.berlios.de}.
551 There is an active and responsive community, get on the mailing list
552 if you have any questions. Jim-Tcl maintainers also lurk on the
553 OpenOCD mailing list.
555 @itemize @bullet
556 @item @b{Jim vs. Tcl}
557 @* Jim-Tcl is a stripped down version of the well known Tcl language,
558 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
559 fewer features. Jim-Tcl is several dozens of .C files and .H files and
560 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
561 4.2 MB .zip file containing 1540 files.
563 @item @b{Missing Features}
564 @* Our practice has been: Add/clone the real Tcl feature if/when
565 needed. We welcome Jim-Tcl improvements, not bloat. Also there
566 are a large number of optional Jim-Tcl features that are not
567 enabled in OpenOCD.
569 @item @b{Scripts}
570 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
571 command interpreter today is a mixture of (newer)
572 Jim-Tcl commands, and (older) the orginal command interpreter.
574 @item @b{Commands}
575 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
576 can type a Tcl for() loop, set variables, etc.
577 Some of the commands documented in this guide are implemented
578 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
580 @item @b{Historical Note}
581 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
582 before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
583 as a git submodule, which greatly simplified upgrading Jim Tcl
584 to benefit from new features and bugfixes in Jim Tcl.
586 @item @b{Need a crash course in Tcl?}
587 @*@xref{Tcl Crash Course}.
588 @end itemize
590 @node Running
591 @chapter Running
592 @cindex command line options
593 @cindex logfile
594 @cindex directory search
596 Properly installing OpenOCD sets up your operating system to grant it access
597 to the debug adapters. On Linux, this usually involves installing a file
598 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
599 complex and confusing driver configuration for every peripheral. Such issues
600 are unique to each operating system, and are not detailed in this User's Guide.
602 Then later you will invoke the OpenOCD server, with various options to
603 tell it how each debug session should work.
604 The @option{--help} option shows:
605 @verbatim
606 bash$ openocd --help
608 --help | -h display this help
609 --version | -v display OpenOCD version
610 --file | -f use configuration file <name>
611 --search | -s dir to search for config files and scripts
612 --debug | -d set debug level <0-3>
613 --log_output | -l redirect log output to file <name>
614 --command | -c run <command>
615 @end verbatim
617 If you don't give any @option{-f} or @option{-c} options,
618 OpenOCD tries to read the configuration file @file{openocd.cfg}.
619 To specify one or more different
620 configuration files, use @option{-f} options. For example:
622 @example
623 openocd -f config1.cfg -f config2.cfg -f config3.cfg
624 @end example
626 Configuration files and scripts are searched for in
627 @enumerate
628 @item the current directory,
629 @item any search dir specified on the command line using the @option{-s} option,
630 @item any search dir specified using the @command{add_script_search_dir} command,
631 @item @file{$HOME/.openocd} (not on Windows),
632 @item the site wide script library @file{$pkgdatadir/site} and
633 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
634 @end enumerate
635 The first found file with a matching file name will be used.
637 @quotation Note
638 Don't try to use configuration script names or paths which
639 include the "#" character. That character begins Tcl comments.
640 @end quotation
642 @section Simple setup, no customization
644 In the best case, you can use two scripts from one of the script
645 libraries, hook up your JTAG adapter, and start the server ... and
646 your JTAG setup will just work "out of the box". Always try to
647 start by reusing those scripts, but assume you'll need more
648 customization even if this works. @xref{OpenOCD Project Setup}.
650 If you find a script for your JTAG adapter, and for your board or
651 target, you may be able to hook up your JTAG adapter then start
652 the server like:
654 @example
655 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
656 @end example
658 You might also need to configure which reset signals are present,
659 using @option{-c 'reset_config trst_and_srst'} or something similar.
660 If all goes well you'll see output something like
662 @example
663 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
664 For bug reports, read
665 http://openocd.sourceforge.net/doc/doxygen/bugs.html
666 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
667 (mfg: 0x23b, part: 0xba00, ver: 0x3)
668 @end example
670 Seeing that "tap/device found" message, and no warnings, means
671 the JTAG communication is working. That's a key milestone, but
672 you'll probably need more project-specific setup.
674 @section What OpenOCD does as it starts
676 OpenOCD starts by processing the configuration commands provided
677 on the command line or, if there were no @option{-c command} or
678 @option{-f file.cfg} options given, in @file{openocd.cfg}.
679 @xref{Configuration Stage}.
680 At the end of the configuration stage it verifies the JTAG scan
681 chain defined using those commands; your configuration should
682 ensure that this always succeeds.
683 Normally, OpenOCD then starts running as a daemon.
684 Alternatively, commands may be used to terminate the configuration
685 stage early, perform work (such as updating some flash memory),
686 and then shut down without acting as a daemon.
688 Once OpenOCD starts running as a daemon, it waits for connections from
689 clients (Telnet, GDB, Other) and processes the commands issued through
690 those channels.
692 If you are having problems, you can enable internal debug messages via
693 the @option{-d} option.
695 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
696 @option{-c} command line switch.
698 To enable debug output (when reporting problems or working on OpenOCD
699 itself), use the @option{-d} command line switch. This sets the
700 @option{debug_level} to "3", outputting the most information,
701 including debug messages. The default setting is "2", outputting only
702 informational messages, warnings and errors. You can also change this
703 setting from within a telnet or gdb session using @command{debug_level
704 <n>} (@pxref{debug_level}).
706 You can redirect all output from the daemon to a file using the
707 @option{-l <logfile>} switch.
709 Note! OpenOCD will launch the GDB & telnet server even if it can not
710 establish a connection with the target. In general, it is possible for
711 the JTAG controller to be unresponsive until the target is set up
712 correctly via e.g. GDB monitor commands in a GDB init script.
714 @node OpenOCD Project Setup
715 @chapter OpenOCD Project Setup
717 To use OpenOCD with your development projects, you need to do more than
718 just connecting the JTAG adapter hardware (dongle) to your development board
719 and then starting the OpenOCD server.
720 You also need to configure that server so that it knows
721 about that adapter and board, and helps your work.
722 You may also want to connect OpenOCD to GDB, possibly
723 using Eclipse or some other GUI.
725 @section Hooking up the JTAG Adapter
727 Today's most common case is a dongle with a JTAG cable on one side
728 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
729 and a USB cable on the other.
730 Instead of USB, some cables use Ethernet;
731 older ones may use a PC parallel port, or even a serial port.
733 @enumerate
734 @item @emph{Start with power to your target board turned off},
735 and nothing connected to your JTAG adapter.
736 If you're particularly paranoid, unplug power to the board.
737 It's important to have the ground signal properly set up,
738 unless you are using a JTAG adapter which provides
739 galvanic isolation between the target board and the
740 debugging host.
742 @item @emph{Be sure it's the right kind of JTAG connector.}
743 If your dongle has a 20-pin ARM connector, you need some kind
744 of adapter (or octopus, see below) to hook it up to
745 boards using 14-pin or 10-pin connectors ... or to 20-pin
746 connectors which don't use ARM's pinout.
748 In the same vein, make sure the voltage levels are compatible.
749 Not all JTAG adapters have the level shifters needed to work
750 with 1.2 Volt boards.
752 @item @emph{Be certain the cable is properly oriented} or you might
753 damage your board. In most cases there are only two possible
754 ways to connect the cable.
755 Connect the JTAG cable from your adapter to the board.
756 Be sure it's firmly connected.
758 In the best case, the connector is keyed to physically
759 prevent you from inserting it wrong.
760 This is most often done using a slot on the board's male connector
761 housing, which must match a key on the JTAG cable's female connector.
762 If there's no housing, then you must look carefully and
763 make sure pin 1 on the cable hooks up to pin 1 on the board.
764 Ribbon cables are frequently all grey except for a wire on one
765 edge, which is red. The red wire is pin 1.
767 Sometimes dongles provide cables where one end is an ``octopus'' of
768 color coded single-wire connectors, instead of a connector block.
769 These are great when converting from one JTAG pinout to another,
770 but are tedious to set up.
771 Use these with connector pinout diagrams to help you match up the
772 adapter signals to the right board pins.
774 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
775 A USB, parallel, or serial port connector will go to the host which
776 you are using to run OpenOCD.
777 For Ethernet, consult the documentation and your network administrator.
779 For USB based JTAG adapters you have an easy sanity check at this point:
780 does the host operating system see the JTAG adapter? If that host is an
781 MS-Windows host, you'll need to install a driver before OpenOCD works.
783 @item @emph{Connect the adapter's power supply, if needed.}
784 This step is primarily for non-USB adapters,
785 but sometimes USB adapters need extra power.
787 @item @emph{Power up the target board.}
788 Unless you just let the magic smoke escape,
789 you're now ready to set up the OpenOCD server
790 so you can use JTAG to work with that board.
792 @end enumerate
794 Talk with the OpenOCD server using
795 telnet (@code{telnet localhost 4444} on many systems) or GDB.
796 @xref{GDB and OpenOCD}.
798 @section Project Directory
800 There are many ways you can configure OpenOCD and start it up.
802 A simple way to organize them all involves keeping a
803 single directory for your work with a given board.
804 When you start OpenOCD from that directory,
805 it searches there first for configuration files, scripts,
806 files accessed through semihosting,
807 and for code you upload to the target board.
808 It is also the natural place to write files,
809 such as log files and data you download from the board.
811 @section Configuration Basics
813 There are two basic ways of configuring OpenOCD, and
814 a variety of ways you can mix them.
815 Think of the difference as just being how you start the server:
817 @itemize
818 @item Many @option{-f file} or @option{-c command} options on the command line
819 @item No options, but a @dfn{user config file}
820 in the current directory named @file{openocd.cfg}
821 @end itemize
823 Here is an example @file{openocd.cfg} file for a setup
824 using a Signalyzer FT2232-based JTAG adapter to talk to
825 a board with an Atmel AT91SAM7X256 microcontroller:
827 @example
828 source [find interface/signalyzer.cfg]
830 # GDB can also flash my flash!
831 gdb_memory_map enable
832 gdb_flash_program enable
834 source [find target/sam7x256.cfg]
835 @end example
837 Here is the command line equivalent of that configuration:
839 @example
840 openocd -f interface/signalyzer.cfg \
841 -c "gdb_memory_map enable" \
842 -c "gdb_flash_program enable" \
843 -f target/sam7x256.cfg
844 @end example
846 You could wrap such long command lines in shell scripts,
847 each supporting a different development task.
848 One might re-flash the board with a specific firmware version.
849 Another might set up a particular debugging or run-time environment.
851 @quotation Important
852 At this writing (October 2009) the command line method has
853 problems with how it treats variables.
854 For example, after @option{-c "set VAR value"}, or doing the
855 same in a script, the variable @var{VAR} will have no value
856 that can be tested in a later script.
857 @end quotation
859 Here we will focus on the simpler solution: one user config
860 file, including basic configuration plus any TCL procedures
861 to simplify your work.
863 @section User Config Files
864 @cindex config file, user
865 @cindex user config file
866 @cindex config file, overview
868 A user configuration file ties together all the parts of a project
869 in one place.
870 One of the following will match your situation best:
872 @itemize
873 @item Ideally almost everything comes from configuration files
874 provided by someone else.
875 For example, OpenOCD distributes a @file{scripts} directory
876 (probably in @file{/usr/share/openocd/scripts} on Linux).
877 Board and tool vendors can provide these too, as can individual
878 user sites; the @option{-s} command line option lets you say
879 where to find these files. (@xref{Running}.)
880 The AT91SAM7X256 example above works this way.
882 Three main types of non-user configuration file each have their
883 own subdirectory in the @file{scripts} directory:
885 @enumerate
886 @item @b{interface} -- one for each different debug adapter;
887 @item @b{board} -- one for each different board
888 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
889 @end enumerate
891 Best case: include just two files, and they handle everything else.
892 The first is an interface config file.
893 The second is board-specific, and it sets up the JTAG TAPs and
894 their GDB targets (by deferring to some @file{target.cfg} file),
895 declares all flash memory, and leaves you nothing to do except
896 meet your deadline:
898 @example
899 source [find interface/olimex-jtag-tiny.cfg]
900 source [find board/csb337.cfg]
901 @end example
903 Boards with a single microcontroller often won't need more
904 than the target config file, as in the AT91SAM7X256 example.
905 That's because there is no external memory (flash, DDR RAM), and
906 the board differences are encapsulated by application code.
908 @item Maybe you don't know yet what your board looks like to JTAG.
909 Once you know the @file{interface.cfg} file to use, you may
910 need help from OpenOCD to discover what's on the board.
911 Once you find the JTAG TAPs, you can just search for appropriate
912 target and board
913 configuration files ... or write your own, from the bottom up.
914 @xref{Autoprobing}.
916 @item You can often reuse some standard config files but
917 need to write a few new ones, probably a @file{board.cfg} file.
918 You will be using commands described later in this User's Guide,
919 and working with the guidelines in the next chapter.
921 For example, there may be configuration files for your JTAG adapter
922 and target chip, but you need a new board-specific config file
923 giving access to your particular flash chips.
924 Or you might need to write another target chip configuration file
925 for a new chip built around the Cortex M3 core.
927 @quotation Note
928 When you write new configuration files, please submit
929 them for inclusion in the next OpenOCD release.
930 For example, a @file{board/newboard.cfg} file will help the
931 next users of that board, and a @file{target/newcpu.cfg}
932 will help support users of any board using that chip.
933 @end quotation
935 @item
936 You may may need to write some C code.
937 It may be as simple as a supporting a new ft2232 or parport
938 based adapter; a bit more involved, like a NAND or NOR flash
939 controller driver; or a big piece of work like supporting
940 a new chip architecture.
941 @end itemize
943 Reuse the existing config files when you can.
944 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
945 You may find a board configuration that's a good example to follow.
947 When you write config files, separate the reusable parts
948 (things every user of that interface, chip, or board needs)
949 from ones specific to your environment and debugging approach.
950 @itemize
952 @item
953 For example, a @code{gdb-attach} event handler that invokes
954 the @command{reset init} command will interfere with debugging
955 early boot code, which performs some of the same actions
956 that the @code{reset-init} event handler does.
958 @item
959 Likewise, the @command{arm9 vector_catch} command (or
960 @cindex vector_catch
961 its siblings @command{xscale vector_catch}
962 and @command{cortex_m3 vector_catch}) can be a timesaver
963 during some debug sessions, but don't make everyone use that either.
964 Keep those kinds of debugging aids in your user config file,
965 along with messaging and tracing setup.
966 (@xref{Software Debug Messages and Tracing}.)
968 @item
969 You might need to override some defaults.
970 For example, you might need to move, shrink, or back up the target's
971 work area if your application needs much SRAM.
973 @item
974 TCP/IP port configuration is another example of something which
975 is environment-specific, and should only appear in
976 a user config file. @xref{TCP/IP Ports}.
977 @end itemize
979 @section Project-Specific Utilities
981 A few project-specific utility
982 routines may well speed up your work.
983 Write them, and keep them in your project's user config file.
985 For example, if you are making a boot loader work on a
986 board, it's nice to be able to debug the ``after it's
987 loaded to RAM'' parts separately from the finicky early
988 code which sets up the DDR RAM controller and clocks.
989 A script like this one, or a more GDB-aware sibling,
990 may help:
992 @example
993 proc ramboot @{ @} @{
994 # Reset, running the target's "reset-init" scripts
995 # to initialize clocks and the DDR RAM controller.
996 # Leave the CPU halted.
997 reset init
999 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1000 load_image u-boot.bin 0x20000000
1002 # Start running.
1003 resume 0x20000000
1004 @}
1005 @end example
1007 Then once that code is working you will need to make it
1008 boot from NOR flash; a different utility would help.
1009 Alternatively, some developers write to flash using GDB.
1010 (You might use a similar script if you're working with a flash
1011 based microcontroller application instead of a boot loader.)
1013 @example
1014 proc newboot @{ @} @{
1015 # Reset, leaving the CPU halted. The "reset-init" event
1016 # proc gives faster access to the CPU and to NOR flash;
1017 # "reset halt" would be slower.
1018 reset init
1020 # Write standard version of U-Boot into the first two
1021 # sectors of NOR flash ... the standard version should
1022 # do the same lowlevel init as "reset-init".
1023 flash protect 0 0 1 off
1024 flash erase_sector 0 0 1
1025 flash write_bank 0 u-boot.bin 0x0
1026 flash protect 0 0 1 on
1028 # Reboot from scratch using that new boot loader.
1029 reset run
1030 @}
1031 @end example
1033 You may need more complicated utility procedures when booting
1034 from NAND.
1035 That often involves an extra bootloader stage,
1036 running from on-chip SRAM to perform DDR RAM setup so it can load
1037 the main bootloader code (which won't fit into that SRAM).
1039 Other helper scripts might be used to write production system images,
1040 involving considerably more than just a three stage bootloader.
1042 @section Target Software Changes
1044 Sometimes you may want to make some small changes to the software
1045 you're developing, to help make JTAG debugging work better.
1046 For example, in C or assembly language code you might
1047 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1048 handling issues like:
1050 @itemize @bullet
1052 @item @b{Watchdog Timers}...
1053 Watchog timers are typically used to automatically reset systems if
1054 some application task doesn't periodically reset the timer. (The
1055 assumption is that the system has locked up if the task can't run.)
1056 When a JTAG debugger halts the system, that task won't be able to run
1057 and reset the timer ... potentially causing resets in the middle of
1058 your debug sessions.
1060 It's rarely a good idea to disable such watchdogs, since their usage
1061 needs to be debugged just like all other parts of your firmware.
1062 That might however be your only option.
1064 Look instead for chip-specific ways to stop the watchdog from counting
1065 while the system is in a debug halt state. It may be simplest to set
1066 that non-counting mode in your debugger startup scripts. You may however
1067 need a different approach when, for example, a motor could be physically
1068 damaged by firmware remaining inactive in a debug halt state. That might
1069 involve a type of firmware mode where that "non-counting" mode is disabled
1070 at the beginning then re-enabled at the end; a watchdog reset might fire
1071 and complicate the debug session, but hardware (or people) would be
1072 protected.@footnote{Note that many systems support a "monitor mode" debug
1073 that is a somewhat cleaner way to address such issues. You can think of
1074 it as only halting part of the system, maybe just one task,
1075 instead of the whole thing.
1076 At this writing, January 2010, OpenOCD based debugging does not support
1077 monitor mode debug, only "halt mode" debug.}
1079 @item @b{ARM Semihosting}...
1080 @cindex ARM semihosting
1081 When linked with a special runtime library provided with many
1082 toolchains@footnote{See chapter 8 "Semihosting" in
1083 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1084 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1085 The CodeSourcery EABI toolchain also includes a semihosting library.},
1086 your target code can use I/O facilities on the debug host. That library
1087 provides a small set of system calls which are handled by OpenOCD.
1088 It can let the debugger provide your system console and a file system,
1089 helping with early debugging or providing a more capable environment
1090 for sometimes-complex tasks like installing system firmware onto
1091 NAND or SPI flash.
1093 @item @b{ARM Wait-For-Interrupt}...
1094 Many ARM chips synchronize the JTAG clock using the core clock.
1095 Low power states which stop that core clock thus prevent JTAG access.
1096 Idle loops in tasking environments often enter those low power states
1097 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1099 You may want to @emph{disable that instruction} in source code,
1100 or otherwise prevent using that state,
1101 to ensure you can get JTAG access at any time.@footnote{As a more
1102 polite alternative, some processors have special debug-oriented
1103 registers which can be used to change various features including
1104 how the low power states are clocked while debugging.
1105 The STM32 DBGMCU_CR register is an example; at the cost of extra
1106 power consumption, JTAG can be used during low power states.}
1107 For example, the OpenOCD @command{halt} command may not
1108 work for an idle processor otherwise.
1110 @item @b{Delay after reset}...
1111 Not all chips have good support for debugger access
1112 right after reset; many LPC2xxx chips have issues here.
1113 Similarly, applications that reconfigure pins used for
1114 JTAG access as they start will also block debugger access.
1116 To work with boards like this, @emph{enable a short delay loop}
1117 the first thing after reset, before "real" startup activities.
1118 For example, one second's delay is usually more than enough
1119 time for a JTAG debugger to attach, so that
1120 early code execution can be debugged
1121 or firmware can be replaced.
1123 @item @b{Debug Communications Channel (DCC)}...
1124 Some processors include mechanisms to send messages over JTAG.
1125 Many ARM cores support these, as do some cores from other vendors.
1126 (OpenOCD may be able to use this DCC internally, speeding up some
1127 operations like writing to memory.)
1129 Your application may want to deliver various debugging messages
1130 over JTAG, by @emph{linking with a small library of code}
1131 provided with OpenOCD and using the utilities there to send
1132 various kinds of message.
1133 @xref{Software Debug Messages and Tracing}.
1135 @end itemize
1137 @section Target Hardware Setup
1139 Chip vendors often provide software development boards which
1140 are highly configurable, so that they can support all options
1141 that product boards may require. @emph{Make sure that any
1142 jumpers or switches match the system configuration you are
1143 working with.}
1145 Common issues include:
1147 @itemize @bullet
1149 @item @b{JTAG setup} ...
1150 Boards may support more than one JTAG configuration.
1151 Examples include jumpers controlling pullups versus pulldowns
1152 on the nTRST and/or nSRST signals, and choice of connectors
1153 (e.g. which of two headers on the base board,
1154 or one from a daughtercard).
1155 For some Texas Instruments boards, you may need to jumper the
1156 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1158 @item @b{Boot Modes} ...
1159 Complex chips often support multiple boot modes, controlled
1160 by external jumpers. Make sure this is set up correctly.
1161 For example many i.MX boards from NXP need to be jumpered
1162 to "ATX mode" to start booting using the on-chip ROM, when
1163 using second stage bootloader code stored in a NAND flash chip.
1165 Such explicit configuration is common, and not limited to
1166 booting from NAND. You might also need to set jumpers to
1167 start booting using code loaded from an MMC/SD card; external
1168 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1169 flash; some external host; or various other sources.
1172 @item @b{Memory Addressing} ...
1173 Boards which support multiple boot modes may also have jumpers
1174 to configure memory addressing. One board, for example, jumpers
1175 external chipselect 0 (used for booting) to address either
1176 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1177 or NAND flash. When it's jumpered to address NAND flash, that
1178 board must also be told to start booting from on-chip ROM.
1180 Your @file{board.cfg} file may also need to be told this jumper
1181 configuration, so that it can know whether to declare NOR flash
1182 using @command{flash bank} or instead declare NAND flash with
1183 @command{nand device}; and likewise which probe to perform in
1184 its @code{reset-init} handler.
1186 A closely related issue is bus width. Jumpers might need to
1187 distinguish between 8 bit or 16 bit bus access for the flash
1188 used to start booting.
1190 @item @b{Peripheral Access} ...
1191 Development boards generally provide access to every peripheral
1192 on the chip, sometimes in multiple modes (such as by providing
1193 multiple audio codec chips).
1194 This interacts with software
1195 configuration of pin multiplexing, where for example a
1196 given pin may be routed either to the MMC/SD controller
1197 or the GPIO controller. It also often interacts with
1198 configuration jumpers. One jumper may be used to route
1199 signals to an MMC/SD card slot or an expansion bus (which
1200 might in turn affect booting); others might control which
1201 audio or video codecs are used.
1203 @end itemize
1205 Plus you should of course have @code{reset-init} event handlers
1206 which set up the hardware to match that jumper configuration.
1207 That includes in particular any oscillator or PLL used to clock
1208 the CPU, and any memory controllers needed to access external
1209 memory and peripherals. Without such handlers, you won't be
1210 able to access those resources without working target firmware
1211 which can do that setup ... this can be awkward when you're
1212 trying to debug that target firmware. Even if there's a ROM
1213 bootloader which handles a few issues, it rarely provides full
1214 access to all board-specific capabilities.
1217 @node Config File Guidelines
1218 @chapter Config File Guidelines
1220 This chapter is aimed at any user who needs to write a config file,
1221 including developers and integrators of OpenOCD and any user who
1222 needs to get a new board working smoothly.
1223 It provides guidelines for creating those files.
1225 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1226 with files including the ones listed here.
1227 Use them as-is where you can; or as models for new files.
1228 @itemize @bullet
1229 @item @file{interface} ...
1230 These are for debug adapters.
1231 Files that configure JTAG adapters go here.
1232 @example
1233 $ ls interface
1234 altera-usb-blaster.cfg hilscher_nxhx50_etm.cfg openrd.cfg
1235 arm-jtag-ew.cfg hilscher_nxhx50_re.cfg osbdm.cfg
1236 arm-usb-ocd.cfg hitex_str9-comstick.cfg parport.cfg
1237 at91rm9200.cfg icebear.cfg parport_dlc5.cfg
1238 axm0432.cfg jlink.cfg redbee-econotag.cfg
1239 busblaster.cfg jtagkey2.cfg redbee-usb.cfg
1240 buspirate.cfg jtagkey2p.cfg rlink.cfg
1241 calao-usb-a9260-c01.cfg jtagkey.cfg sheevaplug.cfg
1242 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg signalyzer.cfg
1243 calao-usb-a9260.cfg kt-link.cfg signalyzer-h2.cfg
1244 chameleon.cfg lisa-l.cfg signalyzer-h4.cfg
1245 cortino.cfg luminary.cfg signalyzer-lite.cfg
1246 digilent-hs1.cfg luminary-icdi.cfg stlink-v1.cfg
1247 dlp-usb1232h.cfg luminary-lm3s811.cfg stlink-v2.cfg
1248 dummy.cfg minimodule.cfg stm32-stick.cfg
1249 estick.cfg neodb.cfg turtelizer2.cfg
1250 flashlink.cfg ngxtech.cfg ulink.cfg
1251 flossjtag.cfg olimex-arm-usb-ocd.cfg usb-jtag.cfg
1252 flossjtag-noeeprom.cfg olimex-arm-usb-ocd-h.cfg usbprog.cfg
1253 flyswatter2.cfg olimex-arm-usb-tiny-h.cfg vpaclink.cfg
1254 flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
1255 hilscher_nxhx10_etm.cfg oocdlink.cfg xds100v2.cfg
1256 hilscher_nxhx500_etm.cfg opendous.cfg
1257 hilscher_nxhx500_re.cfg openocd-usb.cfg
1258 $
1259 @end example
1260 @item @file{board} ...
1261 think Circuit Board, PWA, PCB, they go by many names. Board files
1262 contain initialization items that are specific to a board.
1263 They reuse target configuration files, since the same
1264 microprocessor chips are used on many boards,
1265 but support for external parts varies widely. For
1266 example, the SDRAM initialization sequence for the board, or the type
1267 of external flash and what address it uses. Any initialization
1268 sequence to enable that external flash or SDRAM should be found in the
1269 board file. Boards may also contain multiple targets: two CPUs; or
1270 a CPU and an FPGA.
1271 @example
1272 $ ls board
1273 actux3.cfg logicpd_imx27.cfg
1274 am3517evm.cfg lubbock.cfg
1275 arm_evaluator7t.cfg mcb1700.cfg
1276 at91cap7a-stk-sdram.cfg microchip_explorer16.cfg
1277 at91eb40a.cfg mini2440.cfg
1278 at91rm9200-dk.cfg mini6410.cfg
1279 at91rm9200-ek.cfg olimex_LPC2378STK.cfg
1280 at91sam9261-ek.cfg olimex_lpc_h2148.cfg
1281 at91sam9263-ek.cfg olimex_sam7_ex256.cfg
1282 at91sam9g20-ek.cfg olimex_sam9_l9260.cfg
1283 atmel_at91sam7s-ek.cfg olimex_stm32_h103.cfg
1284 atmel_at91sam9260-ek.cfg olimex_stm32_h107.cfg
1285 atmel_at91sam9rl-ek.cfg olimex_stm32_p107.cfg
1286 atmel_sam3n_ek.cfg omap2420_h4.cfg
1287 atmel_sam3s_ek.cfg open-bldc.cfg
1288 atmel_sam3u_ek.cfg openrd.cfg
1289 atmel_sam3x_ek.cfg osk5912.cfg
1290 atmel_sam4s_ek.cfg phytec_lpc3250.cfg
1291 balloon3-cpu.cfg pic-p32mx.cfg
1292 colibri.cfg propox_mmnet1001.cfg
1293 crossbow_tech_imote2.cfg pxa255_sst.cfg
1294 csb337.cfg redbee.cfg
1295 csb732.cfg rsc-w910.cfg
1296 da850evm.cfg sheevaplug.cfg
1297 digi_connectcore_wi-9c.cfg smdk6410.cfg
1298 diolan_lpc4350-db1.cfg spear300evb.cfg
1299 dm355evm.cfg spear300evb_mod.cfg
1300 dm365evm.cfg spear310evb20.cfg
1301 dm6446evm.cfg spear310evb20_mod.cfg
1302 efikamx.cfg spear320cpu.cfg
1303 eir.cfg spear320cpu_mod.cfg
1304 ek-lm3s1968.cfg steval_pcc010.cfg
1305 ek-lm3s3748.cfg stm320518_eval_stlink.cfg
1306 ek-lm3s6965.cfg stm32100b_eval.cfg
1307 ek-lm3s811.cfg stm3210b_eval.cfg
1308 ek-lm3s811-revb.cfg stm3210c_eval.cfg
1309 ek-lm3s9b9x.cfg stm3210e_eval.cfg
1310 ek-lm4f232.cfg stm3220g_eval.cfg
1311 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1312 ethernut3.cfg stm3241g_eval.cfg
1313 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1314 hammer.cfg stm32f0discovery.cfg
1315 hilscher_nxdb500sys.cfg stm32f4discovery.cfg
1316 hilscher_nxeb500hmi.cfg stm32ldiscovery.cfg
1317 hilscher_nxhx10.cfg stm32vldiscovery.cfg
1318 hilscher_nxhx500.cfg str910-eval.cfg
1319 hilscher_nxhx50.cfg telo.cfg
1320 hilscher_nxsb100.cfg ti_beagleboard.cfg
1321 hitex_lpc2929.cfg ti_beagleboard_xm.cfg
1322 hitex_stm32-performancestick.cfg ti_beaglebone.cfg
1323 hitex_str9-comstick.cfg ti_blaze.cfg
1324 iar_lpc1768.cfg ti_pandaboard.cfg
1325 iar_str912_sk.cfg ti_pandaboard_es.cfg
1326 icnova_imx53_sodimm.cfg topas910.cfg
1327 icnova_sam9g45_sodimm.cfg topasa900.cfg
1328 imx27ads.cfg twr-k60n512.cfg
1329 imx27lnst.cfg tx25_stk5.cfg
1330 imx28evk.cfg tx27_stk5.cfg
1331 imx31pdk.cfg unknown_at91sam9260.cfg
1332 imx35pdk.cfg uptech_2410.cfg
1333 imx53loco.cfg verdex.cfg
1334 keil_mcb1700.cfg voipac.cfg
1335 keil_mcb2140.cfg voltcraft_dso-3062c.cfg
1336 kwikstik.cfg x300t.cfg
1337 linksys_nslu2.cfg zy1000.cfg
1338 lisa-l.cfg
1339 $
1340 @end example
1341 @item @file{target} ...
1342 think chip. The ``target'' directory represents the JTAG TAPs
1343 on a chip
1344 which OpenOCD should control, not a board. Two common types of targets
1345 are ARM chips and FPGA or CPLD chips.
1346 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1347 the target config file defines all of them.
1348 @example
1349 $ ls target
1350 $duc702x.cfg ixp42x.cfg
1351 am335x.cfg k40.cfg
1352 amdm37x.cfg k60.cfg
1353 ar71xx.cfg lpc1768.cfg
1354 at32ap7000.cfg lpc2103.cfg
1355 at91r40008.cfg lpc2124.cfg
1356 at91rm9200.cfg lpc2129.cfg
1357 at91sam3ax_4x.cfg lpc2148.cfg
1358 at91sam3ax_8x.cfg lpc2294.cfg
1359 at91sam3ax_xx.cfg lpc2378.cfg
1360 at91sam3nXX.cfg lpc2460.cfg
1361 at91sam3sXX.cfg lpc2478.cfg
1362 at91sam3u1c.cfg lpc2900.cfg
1363 at91sam3u1e.cfg lpc2xxx.cfg
1364 at91sam3u2c.cfg lpc3131.cfg
1365 at91sam3u2e.cfg lpc3250.cfg
1366 at91sam3u4c.cfg lpc4350.cfg
1367 at91sam3u4e.cfg mc13224v.cfg
1368 at91sam3uxx.cfg nuc910.cfg
1369 at91sam3XXX.cfg omap2420.cfg
1370 at91sam4sXX.cfg omap3530.cfg
1371 at91sam4XXX.cfg omap4430.cfg
1372 at91sam7se512.cfg omap4460.cfg
1373 at91sam7sx.cfg omap5912.cfg
1374 at91sam7x256.cfg omapl138.cfg
1375 at91sam7x512.cfg pic32mx.cfg
1376 at91sam9260.cfg pxa255.cfg
1377 at91sam9260_ext_RAM_ext_flash.cfg pxa270.cfg
1378 at91sam9261.cfg pxa3xx.cfg
1379 at91sam9263.cfg readme.txt
1380 at91sam9.cfg samsung_s3c2410.cfg
1381 at91sam9g10.cfg samsung_s3c2440.cfg
1382 at91sam9g20.cfg samsung_s3c2450.cfg
1383 at91sam9g45.cfg samsung_s3c4510.cfg
1384 at91sam9rl.cfg samsung_s3c6410.cfg
1385 atmega128.cfg sharp_lh79532.cfg
1386 avr32.cfg smp8634.cfg
1387 c100.cfg spear3xx.cfg
1388 c100config.tcl stellaris.cfg
1389 c100helper.tcl stm32.cfg
1390 c100regs.tcl stm32f0x_stlink.cfg
1391 cs351x.cfg stm32f1x.cfg
1392 davinci.cfg stm32f1x_stlink.cfg
1393 dragonite.cfg stm32f2x.cfg
1394 dsp56321.cfg stm32f2x_stlink.cfg
1395 dsp568013.cfg stm32f2xxx.cfg
1396 dsp568037.cfg stm32f4x.cfg
1397 epc9301.cfg stm32f4x_stlink.cfg
1398 faux.cfg stm32l.cfg
1399 feroceon.cfg stm32lx_stlink.cfg
1400 fm3.cfg stm32_stlink.cfg
1401 hilscher_netx10.cfg stm32xl.cfg
1402 hilscher_netx500.cfg str710.cfg
1403 hilscher_netx50.cfg str730.cfg
1404 icepick.cfg str750.cfg
1405 imx21.cfg str912.cfg
1406 imx25.cfg swj-dp.tcl
1407 imx27.cfg test_reset_syntax_error.cfg
1408 imx28.cfg test_syntax_error.cfg
1409 imx31.cfg ti_dm355.cfg
1410 imx35.cfg ti_dm365.cfg
1411 imx51.cfg ti_dm6446.cfg
1412 imx53.cfg tmpa900.cfg
1413 imx.cfg tmpa910.cfg
1414 is5114.cfg u8500.cfg
1415 @end example
1416 @item @emph{more} ... browse for other library files which may be useful.
1417 For example, there are various generic and CPU-specific utilities.
1418 @end itemize
1420 The @file{openocd.cfg} user config
1421 file may override features in any of the above files by
1422 setting variables before sourcing the target file, or by adding
1423 commands specific to their situation.
1425 @section Interface Config Files
1427 The user config file
1428 should be able to source one of these files with a command like this:
1430 @example
1431 source [find interface/FOOBAR.cfg]
1432 @end example
1434 A preconfigured interface file should exist for every debug adapter
1435 in use today with OpenOCD.
1436 That said, perhaps some of these config files
1437 have only been used by the developer who created it.
1439 A separate chapter gives information about how to set these up.
1440 @xref{Debug Adapter Configuration}.
1441 Read the OpenOCD source code (and Developer's Guide)
1442 if you have a new kind of hardware interface
1443 and need to provide a driver for it.
1445 @section Board Config Files
1446 @cindex config file, board
1447 @cindex board config file
1449 The user config file
1450 should be able to source one of these files with a command like this:
1452 @example
1453 source [find board/FOOBAR.cfg]
1454 @end example
1456 The point of a board config file is to package everything
1457 about a given board that user config files need to know.
1458 In summary the board files should contain (if present)
1460 @enumerate
1461 @item One or more @command{source [target/...cfg]} statements
1462 @item NOR flash configuration (@pxref{NOR Configuration})
1463 @item NAND flash configuration (@pxref{NAND Configuration})
1464 @item Target @code{reset} handlers for SDRAM and I/O configuration
1465 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1466 @item All things that are not ``inside a chip''
1467 @end enumerate
1469 Generic things inside target chips belong in target config files,
1470 not board config files. So for example a @code{reset-init} event
1471 handler should know board-specific oscillator and PLL parameters,
1472 which it passes to target-specific utility code.
1474 The most complex task of a board config file is creating such a
1475 @code{reset-init} event handler.
1476 Define those handlers last, after you verify the rest of the board
1477 configuration works.
1479 @subsection Communication Between Config files
1481 In addition to target-specific utility code, another way that
1482 board and target config files communicate is by following a
1483 convention on how to use certain variables.
1485 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1486 Thus the rule we follow in OpenOCD is this: Variables that begin with
1487 a leading underscore are temporary in nature, and can be modified and
1488 used at will within a target configuration file.
1490 Complex board config files can do the things like this,
1491 for a board with three chips:
1493 @example
1494 # Chip #1: PXA270 for network side, big endian
1495 set CHIPNAME network
1496 set ENDIAN big
1497 source [find target/pxa270.cfg]
1498 # on return: _TARGETNAME = network.cpu
1499 # other commands can refer to the "network.cpu" target.
1500 $_TARGETNAME configure .... events for this CPU..
1502 # Chip #2: PXA270 for video side, little endian
1503 set CHIPNAME video
1504 set ENDIAN little
1505 source [find target/pxa270.cfg]
1506 # on return: _TARGETNAME = video.cpu
1507 # other commands can refer to the "video.cpu" target.
1508 $_TARGETNAME configure .... events for this CPU..
1510 # Chip #3: Xilinx FPGA for glue logic
1511 set CHIPNAME xilinx
1512 unset ENDIAN
1513 source [find target/spartan3.cfg]
1514 @end example
1516 That example is oversimplified because it doesn't show any flash memory,
1517 or the @code{reset-init} event handlers to initialize external DRAM
1518 or (assuming it needs it) load a configuration into the FPGA.
1519 Such features are usually needed for low-level work with many boards,
1520 where ``low level'' implies that the board initialization software may
1521 not be working. (That's a common reason to need JTAG tools. Another
1522 is to enable working with microcontroller-based systems, which often
1523 have no debugging support except a JTAG connector.)
1525 Target config files may also export utility functions to board and user
1526 config files. Such functions should use name prefixes, to help avoid
1527 naming collisions.
1529 Board files could also accept input variables from user config files.
1530 For example, there might be a @code{J4_JUMPER} setting used to identify
1531 what kind of flash memory a development board is using, or how to set
1532 up other clocks and peripherals.
1534 @subsection Variable Naming Convention
1535 @cindex variable names
1537 Most boards have only one instance of a chip.
1538 However, it should be easy to create a board with more than
1539 one such chip (as shown above).
1540 Accordingly, we encourage these conventions for naming
1541 variables associated with different @file{target.cfg} files,
1542 to promote consistency and
1543 so that board files can override target defaults.
1545 Inputs to target config files include:
1547 @itemize @bullet
1548 @item @code{CHIPNAME} ...
1549 This gives a name to the overall chip, and is used as part of
1550 tap identifier dotted names.
1551 While the default is normally provided by the chip manufacturer,
1552 board files may need to distinguish between instances of a chip.
1553 @item @code{ENDIAN} ...
1554 By default @option{little} - although chips may hard-wire @option{big}.
1555 Chips that can't change endianness don't need to use this variable.
1556 @item @code{CPUTAPID} ...
1557 When OpenOCD examines the JTAG chain, it can be told verify the
1558 chips against the JTAG IDCODE register.
1559 The target file will hold one or more defaults, but sometimes the
1560 chip in a board will use a different ID (perhaps a newer revision).
1561 @end itemize
1563 Outputs from target config files include:
1565 @itemize @bullet
1566 @item @code{_TARGETNAME} ...
1567 By convention, this variable is created by the target configuration
1568 script. The board configuration file may make use of this variable to
1569 configure things like a ``reset init'' script, or other things
1570 specific to that board and that target.
1571 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1572 @code{_TARGETNAME1}, ... etc.
1573 @end itemize
1575 @subsection The reset-init Event Handler
1576 @cindex event, reset-init
1577 @cindex reset-init handler
1579 Board config files run in the OpenOCD configuration stage;
1580 they can't use TAPs or targets, since they haven't been
1581 fully set up yet.
1582 This means you can't write memory or access chip registers;
1583 you can't even verify that a flash chip is present.
1584 That's done later in event handlers, of which the target @code{reset-init}
1585 handler is one of the most important.
1587 Except on microcontrollers, the basic job of @code{reset-init} event
1588 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1589 Microcontrollers rarely use boot loaders; they run right out of their
1590 on-chip flash and SRAM memory. But they may want to use one of these
1591 handlers too, if just for developer convenience.
1593 @quotation Note
1594 Because this is so very board-specific, and chip-specific, no examples
1595 are included here.
1596 Instead, look at the board config files distributed with OpenOCD.
1597 If you have a boot loader, its source code will help; so will
1598 configuration files for other JTAG tools
1599 (@pxref{Translating Configuration Files}).
1600 @end quotation
1602 Some of this code could probably be shared between different boards.
1603 For example, setting up a DRAM controller often doesn't differ by
1604 much except the bus width (16 bits or 32?) and memory timings, so a
1605 reusable TCL procedure loaded by the @file{target.cfg} file might take
1606 those as parameters.
1607 Similarly with oscillator, PLL, and clock setup;
1608 and disabling the watchdog.
1609 Structure the code cleanly, and provide comments to help
1610 the next developer doing such work.
1611 (@emph{You might be that next person} trying to reuse init code!)
1613 The last thing normally done in a @code{reset-init} handler is probing
1614 whatever flash memory was configured. For most chips that needs to be
1615 done while the associated target is halted, either because JTAG memory
1616 access uses the CPU or to prevent conflicting CPU access.
1618 @subsection JTAG Clock Rate
1620 Before your @code{reset-init} handler has set up
1621 the PLLs and clocking, you may need to run with
1622 a low JTAG clock rate.
1623 @xref{JTAG Speed}.
1624 Then you'd increase that rate after your handler has
1625 made it possible to use the faster JTAG clock.
1626 When the initial low speed is board-specific, for example
1627 because it depends on a board-specific oscillator speed, then
1628 you should probably set it up in the board config file;
1629 if it's target-specific, it belongs in the target config file.
1631 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1632 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1633 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1634 Consult chip documentation to determine the peak JTAG clock rate,
1635 which might be less than that.
1637 @quotation Warning
1638 On most ARMs, JTAG clock detection is coupled to the core clock, so
1639 software using a @option{wait for interrupt} operation blocks JTAG access.
1640 Adaptive clocking provides a partial workaround, but a more complete
1641 solution just avoids using that instruction with JTAG debuggers.
1642 @end quotation
1644 If both the chip and the board support adaptive clocking,
1645 use the @command{jtag_rclk}
1646 command, in case your board is used with JTAG adapter which
1647 also supports it. Otherwise use @command{adapter_khz}.
1648 Set the slow rate at the beginning of the reset sequence,
1649 and the faster rate as soon as the clocks are at full speed.
1651 @anchor{The init_board procedure}
1652 @subsection The init_board procedure
1653 @cindex init_board procedure
1655 The concept of @code{init_board} procedure is very similar to @code{init_targets} (@xref{The init_targets procedure}.)
1656 - it's a replacement of ``linear'' configuration scripts. This procedure is meant to be executed when OpenOCD enters run
1657 stage (@xref{Entering the Run Stage},) after @code{init_targets}. The idea to have spearate @code{init_targets} and
1658 @code{init_board} procedures is to allow the first one to configure everything target specific (internal flash,
1659 internal RAM, etc.) and the second one to configure everything board specific (reset signals, chip frequency,
1660 reset-init event handler, external memory, etc.). Additionally ``linear'' board config file will most likely fail when
1661 target config file uses @code{init_targets} scheme (``linear'' script is executed before @code{init} and
1662 @code{init_targets} - after), so separating these two configuration stages is very convenient, as the easiest way to
1663 overcome this problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1664 need to override @code{init_targets} defined in target config files when they only need to to add some specifics.
1666 Just as @code{init_targets}, the @code{init_board} procedure can be overriden by ``next level'' script (which sources
1667 the original), allowing greater code reuse.
1669 @example
1670 ### board_file.cfg ###
1672 # source target file that does most of the config in init_targets
1673 source [find target/target.cfg]
1675 proc enable_fast_clock @{@} @{
1676 # enables fast on-board clock source
1677 # configures the chip to use it
1678 @}
1680 # initialize only board specifics - reset, clock, adapter frequency
1681 proc init_board @{@} @{
1682 reset_config trst_and_srst trst_pulls_srst
1684 $_TARGETNAME configure -event reset-init @{
1685 adapter_khz 1
1686 enable_fast_clock
1687 adapter_khz 10000
1688 @}
1689 @}
1690 @end example
1692 @section Target Config Files
1693 @cindex config file, target
1694 @cindex target config file
1696 Board config files communicate with target config files using
1697 naming conventions as described above, and may source one or
1698 more target config files like this:
1700 @example
1701 source [find target/FOOBAR.cfg]
1702 @end example
1704 The point of a target config file is to package everything
1705 about a given chip that board config files need to know.
1706 In summary the target files should contain
1708 @enumerate
1709 @item Set defaults
1710 @item Add TAPs to the scan chain
1711 @item Add CPU targets (includes GDB support)
1712 @item CPU/Chip/CPU-Core specific features
1713 @item On-Chip flash
1714 @end enumerate
1716 As a rule of thumb, a target file sets up only one chip.
1717 For a microcontroller, that will often include a single TAP,
1718 which is a CPU needing a GDB target, and its on-chip flash.
1720 More complex chips may include multiple TAPs, and the target
1721 config file may need to define them all before OpenOCD
1722 can talk to the chip.
1723 For example, some phone chips have JTAG scan chains that include
1724 an ARM core for operating system use, a DSP,
1725 another ARM core embedded in an image processing engine,
1726 and other processing engines.
1728 @subsection Default Value Boiler Plate Code
1730 All target configuration files should start with code like this,
1731 letting board config files express environment-specific
1732 differences in how things should be set up.
1734 @example
1735 # Boards may override chip names, perhaps based on role,
1736 # but the default should match what the vendor uses
1737 if @{ [info exists CHIPNAME] @} @{
1739 @} else @{
1740 set _CHIPNAME sam7x256
1741 @}
1743 # ONLY use ENDIAN with targets that can change it.
1744 if @{ [info exists ENDIAN] @} @{
1745 set _ENDIAN $ENDIAN
1746 @} else @{
1747 set _ENDIAN little
1748 @}
1750 # TAP identifiers may change as chips mature, for example with
1751 # new revision fields (the "3" here). Pick a good default; you
1752 # can pass several such identifiers to the "jtag newtap" command.
1753 if @{ [info exists CPUTAPID ] @} @{
1755 @} else @{
1756 set _CPUTAPID 0x3f0f0f0f
1757 @}
1758 @end example
1759 @c but 0x3f0f0f0f is for an str73x part ...
1761 @emph{Remember:} Board config files may include multiple target
1762 config files, or the same target file multiple times
1763 (changing at least @code{CHIPNAME}).
1765 Likewise, the target configuration file should define
1766 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1767 use it later on when defining debug targets:
1769 @example
1771 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1772 @end example
1774 @subsection Adding TAPs to the Scan Chain
1775 After the ``defaults'' are set up,
1776 add the TAPs on each chip to the JTAG scan chain.
1777 @xref{TAP Declaration}, and the naming convention
1778 for taps.
1780 In the simplest case the chip has only one TAP,
1781 probably for a CPU or FPGA.
1782 The config file for the Atmel AT91SAM7X256
1783 looks (in part) like this:
1785 @example
1786 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1787 @end example
1789 A board with two such at91sam7 chips would be able
1790 to source such a config file twice, with different
1791 values for @code{CHIPNAME}, so
1792 it adds a different TAP each time.
1794 If there are nonzero @option{-expected-id} values,
1795 OpenOCD attempts to verify the actual tap id against those values.
1796 It will issue error messages if there is mismatch, which
1797 can help to pinpoint problems in OpenOCD configurations.
1799 @example
1800 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1801 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1802 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1803 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1804 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1805 @end example
1807 There are more complex examples too, with chips that have
1808 multiple TAPs. Ones worth looking at include:
1810 @itemize
1811 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1812 plus a JRC to enable them
1813 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1814 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1815 is not currently used)
1816 @end itemize
1818 @subsection Add CPU targets
1820 After adding a TAP for a CPU, you should set it up so that
1821 GDB and other commands can use it.
1822 @xref{CPU Configuration}.
1823 For the at91sam7 example above, the command can look like this;
1824 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1825 to little endian, and this chip doesn't support changing that.
1827 @example
1829 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1830 @end example
1832 Work areas are small RAM areas associated with CPU targets.
1833 They are used by OpenOCD to speed up downloads,
1834 and to download small snippets of code to program flash chips.
1835 If the chip includes a form of ``on-chip-ram'' - and many do - define
1836 a work area if you can.
1837 Again using the at91sam7 as an example, this can look like:
1839 @example
1840 $_TARGETNAME configure -work-area-phys 0x00200000 \
1841 -work-area-size 0x4000 -work-area-backup 0
1842 @end example
1844 @anchor{Define CPU targets working in SMP}
1845 @subsection Define CPU targets working in SMP
1846 @cindex SMP
1847 After setting targets, you can define a list of targets working in SMP.
1849 @example
1850 set _TARGETNAME_1 $_CHIPNAME.cpu1
1851 set _TARGETNAME_2 $_CHIPNAME.cpu2
1852 target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap \
1853 -coreid 0 -dbgbase $_DAP_DBG1
1854 target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap \
1855 -coreid 1 -dbgbase $_DAP_DBG2
1856 #define 2 targets working in smp.
1857 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1858 @end example
1859 In the above example on cortex_a8, 2 cpus are working in SMP.
1860 In SMP only one GDB instance is created and :
1861 @itemize @bullet
1862 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1863 @item halt command triggers the halt of all targets in the list.
1864 @item resume command triggers the write context and the restart of all targets in the list.
1865 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1866 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1867 displayed by the GDB session @pxref{Using openocd SMP with GDB}.
1868 @end itemize
1870 The SMP behaviour can be disabled/enabled dynamically. On cortex_a8 following
1871 command have been implemented.
1872 @itemize @bullet
1873 @item cortex_a8 smp_on : enable SMP mode, behaviour is as described above.
1874 @item cortex_a8 smp_off : disable SMP mode, the current target is the one
1875 displayed in the GDB session, only this target is now controlled by GDB
1876 session. This behaviour is useful during system boot up.
1877 @item cortex_a8 smp_gdb : display/fix the core id displayed in GDB session see
1878 following example.
1879 @end itemize
1881 @example
1882 >cortex_a8 smp_gdb
1883 gdb coreid 0 -> -1
1884 #0 : coreid 0 is displayed to GDB ,
1885 #-> -1 : next resume triggers a real resume
1886 > cortex_a8 smp_gdb 1
1887 gdb coreid 0 -> 1
1888 #0 :coreid 0 is displayed to GDB ,
1889 #->1 : next resume displays coreid 1 to GDB
1890 > resume
1891 > cortex_a8 smp_gdb
1892 gdb coreid 1 -> 1
1893 #1 :coreid 1 is displayed to GDB ,
1894 #->1 : next resume displays coreid 1 to GDB
1895 > cortex_a8 smp_gdb -1
1896 gdb coreid 1 -> -1
1897 #1 :coreid 1 is displayed to GDB,
1898 #->-1 : next resume triggers a real resume
1899 @end example
1902 @subsection Chip Reset Setup
1904 As a rule, you should put the @command{reset_config} command
1905 into the board file. Most things you think you know about a
1906 chip can be tweaked by the board.
1908 Some chips have specific ways the TRST and SRST signals are
1909 managed. In the unusual case that these are @emph{chip specific}
1910 and can never be changed by board wiring, they could go here.
1911 For example, some chips can't support JTAG debugging without
1912 both signals.
1914 Provide a @code{reset-assert} event handler if you can.
1915 Such a handler uses JTAG operations to reset the target,
1916 letting this target config be used in systems which don't
1917 provide the optional SRST signal, or on systems where you
1918 don't want to reset all targets at once.
1919 Such a handler might write to chip registers to force a reset,
1920 use a JRC to do that (preferable -- the target may be wedged!),
1921 or force a watchdog timer to trigger.
1922 (For Cortex-M3 targets, this is not necessary. The target
1923 driver knows how to use trigger an NVIC reset when SRST is
1924 not available.)
1926 Some chips need special attention during reset handling if
1927 they're going to be used with JTAG.
1928 An example might be needing to send some commands right
1929 after the target's TAP has been reset, providing a
1930 @code{reset-deassert-post} event handler that writes a chip
1931 register to report that JTAG debugging is being done.
1932 Another would be reconfiguring the watchdog so that it stops
1933 counting while the core is halted in the debugger.
1935 JTAG clocking constraints often change during reset, and in
1936 some cases target config files (rather than board config files)
1937 are the right places to handle some of those issues.
1938 For example, immediately after reset most chips run using a
1939 slower clock than they will use later.
1940 That means that after reset (and potentially, as OpenOCD
1941 first starts up) they must use a slower JTAG clock rate
1942 than they will use later.
1943 @xref{JTAG Speed}.
1945 @quotation Important
1946 When you are debugging code that runs right after chip
1947 reset, getting these issues right is critical.
1948 In particular, if you see intermittent failures when
1949 OpenOCD verifies the scan chain after reset,
1950 look at how you are setting up JTAG clocking.
1951 @end quotation
1953 @anchor{The init_targets procedure}
1954 @subsection The init_targets procedure
1955 @cindex init_targets procedure
1957 Target config files can either be ``linear'' (script executed line-by-line when parsed in configuration stage,
1958 @xref{Configuration Stage},) or they can contain a special procedure called @code{init_targets}, which will be executed
1959 when entering run stage (after parsing all config files or after @code{init} command, @xref{Entering the Run Stage}.)
1960 Such procedure can be overriden by ``next level'' script (which sources the original). This concept faciliates code
1961 reuse when basic target config files provide generic configuration procedures and @code{init_targets} procedure, which
1962 can then be sourced and enchanced or changed in a ``more specific'' target config file. This is not possible with
1963 ``linear'' config scripts, because sourcing them executes every initialization commands they provide.
1965 @example
1966 ### generic_file.cfg ###
1968 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1969 # basic initialization procedure ...
1970 @}
1972 proc init_targets @{@} @{
1973 # initializes generic chip with 4kB of flash and 1kB of RAM
1974 setup_my_chip MY_GENERIC_CHIP 4096 1024
1975 @}
1977 ### specific_file.cfg ###
1979 source [find target/generic_file.cfg]
1981 proc init_targets @{@} @{
1982 # initializes specific chip with 128kB of flash and 64kB of RAM
1983 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1984 @}
1985 @end example
1987 The easiest way to convert ``linear'' config files to @code{init_targets} version is to enclose every line of ``code''
1988 (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1990 For an example of this scheme see LPC2000 target config files.
1992 The @code{init_boards} procedure is a similar concept concerning board config files (@xref{The init_board procedure}.)
1994 @subsection ARM Core Specific Hacks
1996 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1997 special high speed download features - enable it.
1999 If present, the MMU, the MPU and the CACHE should be disabled.
2001 Some ARM cores are equipped with trace support, which permits
2002 examination of the instruction and data bus activity. Trace
2003 activity is controlled through an ``Embedded Trace Module'' (ETM)
2004 on one of the core's scan chains. The ETM emits voluminous data
2005 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
2006 If you are using an external trace port,
2007 configure it in your board config file.
2008 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2009 configure it in your target config file.
2011 @example
2012 etm config $_TARGETNAME 16 normal full etb
2013 etb config $_TARGETNAME $_CHIPNAME.etb
2014 @end example
2016 @subsection Internal Flash Configuration
2018 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2020 @b{Never ever} in the ``target configuration file'' define any type of
2021 flash that is external to the chip. (For example a BOOT flash on
2022 Chip Select 0.) Such flash information goes in a board file - not
2023 the TARGET (chip) file.
2025 Examples:
2026 @itemize @bullet
2027 @item at91sam7x256 - has 256K flash YES enable it.
2028 @item str912 - has flash internal YES enable it.
2029 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2030 @item pxa270 - again - CS0 flash - it goes in the board file.
2031 @end itemize
2033 @anchor{Translating Configuration Files}
2034 @section Translating Configuration Files
2035 @cindex translation
2036 If you have a configuration file for another hardware debugger
2037 or toolset (Abatron, BDI2000, BDI3000, CCS,
2038 Lauterbach, Segger, Macraigor, etc.), translating
2039 it into OpenOCD syntax is often quite straightforward. The most tricky
2040 part of creating a configuration script is oftentimes the reset init
2041 sequence where e.g. PLLs, DRAM and the like is set up.
2043 One trick that you can use when translating is to write small
2044 Tcl procedures to translate the syntax into OpenOCD syntax. This
2045 can avoid manual translation errors and make it easier to
2046 convert other scripts later on.
2048 Example of transforming quirky arguments to a simple search and
2049 replace job:
2051 @example
2052 # Lauterbach syntax(?)
2053 #
2054 # Data.Set c15:0x042f %long 0x40000015
2055 #
2056 # OpenOCD syntax when using procedure below.
2057 #
2058 # setc15 0x01 0x00050078
2060 proc setc15 @{regs value@} @{
2061 global TARGETNAME
2063 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2065 arm mcr 15 [expr ($regs>>12)&0x7] \
2066 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2067 [expr ($regs>>8)&0x7] $value
2068 @}
2069 @end example
2073 @node Daemon Configuration
2074 @chapter Daemon Configuration
2075 @cindex initialization
2076 The commands here are commonly found in the openocd.cfg file and are
2077 used to specify what TCP/IP ports are used, and how GDB should be
2078 supported.
2080 @anchor{Configuration Stage}
2081 @section Configuration Stage
2082 @cindex configuration stage
2083 @cindex config command
2085 When the OpenOCD server process starts up, it enters a
2086 @emph{configuration stage} which is the only time that
2087 certain commands, @emph{configuration commands}, may be issued.
2088 Normally, configuration commands are only available
2089 inside startup scripts.
2091 In this manual, the definition of a configuration command is
2092 presented as a @emph{Config Command}, not as a @emph{Command}
2093 which may be issued interactively.
2094 The runtime @command{help} command also highlights configuration
2095 commands, and those which may be issued at any time.
2097 Those configuration commands include declaration of TAPs,
2098 flash banks,
2099 the interface used for JTAG communication,
2100 and other basic setup.
2101 The server must leave the configuration stage before it
2102 may access or activate TAPs.
2103 After it leaves this stage, configuration commands may no
2104 longer be issued.
2106 @anchor{Entering the Run Stage}
2107 @section Entering the Run Stage
2109 The first thing OpenOCD does after leaving the configuration
2110 stage is to verify that it can talk to the scan chain
2111 (list of TAPs) which has been configured.
2112 It will warn if it doesn't find TAPs it expects to find,
2113 or finds TAPs that aren't supposed to be there.
2114 You should see no errors at this point.
2115 If you see errors, resolve them by correcting the
2116 commands you used to configure the server.
2117 Common errors include using an initial JTAG speed that's too
2118 fast, and not providing the right IDCODE values for the TAPs
2119 on the scan chain.
2121 Once OpenOCD has entered the run stage, a number of commands
2122 become available.
2123 A number of these relate to the debug targets you may have declared.
2124 For example, the @command{mww} command will not be available until
2125 a target has been successfuly instantiated.
2126 If you want to use those commands, you may need to force
2127 entry to the run stage.
2129 @deffn {Config Command} init
2130 This command terminates the configuration stage and
2131 enters the run stage. This helps when you need to have
2132 the startup scripts manage tasks such as resetting the target,
2133 programming flash, etc. To reset the CPU upon startup, add "init" and
2134 "reset" at the end of the config script or at the end of the OpenOCD
2135 command line using the @option{-c} command line switch.
2137 If this command does not appear in any startup/configuration file
2138 OpenOCD executes the command for you after processing all
2139 configuration files and/or command line options.
2141 @b{NOTE:} This command normally occurs at or near the end of your
2142 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2143 targets ready. For example: If your openocd.cfg file needs to
2144 read/write memory on your target, @command{init} must occur before
2145 the memory read/write commands. This includes @command{nand probe}.
2146 @end deffn
2148 @deffn {Overridable Procedure} jtag_init
2149 This is invoked at server startup to verify that it can talk
2150 to the scan chain (list of TAPs) which has been configured.
2152 The default implementation first tries @command{jtag arp_init},
2153 which uses only a lightweight JTAG reset before examining the
2154 scan chain.
2155 If that fails, it tries again, using a harder reset
2156 from the overridable procedure @command{init_reset}.
2158 Implementations must have verified the JTAG scan chain before
2159 they return.
2160 This is done by calling @command{jtag arp_init}
2161 (or @command{jtag arp_init-reset}).
2162 @end deffn
2164 @anchor{TCP/IP Ports}
2165 @section TCP/IP Ports
2166 @cindex TCP port
2167 @cindex server
2168 @cindex port
2169 @cindex security
2170 The OpenOCD server accepts remote commands in several syntaxes.
2171 Each syntax uses a different TCP/IP port, which you may specify
2172 only during configuration (before those ports are opened).
2174 For reasons including security, you may wish to prevent remote
2175 access using one or more of these ports.
2176 In such cases, just specify the relevant port number as zero.
2177 If you disable all access through TCP/IP, you will need to
2178 use the command line @option{-pipe} option.
2180 @deffn {Command} gdb_port [number]
2181 @cindex GDB server
2182 Normally gdb listens to a TCP/IP port, but GDB can also
2183 communicate via pipes(stdin/out or named pipes). The name
2184 "gdb_port" stuck because it covers probably more than 90% of
2185 the normal use cases.
2187 No arguments reports GDB port. "pipe" means listen to stdin
2188 output to stdout, an integer is base port number, "disable"
2189 disables the gdb server.
2191 When using "pipe", also use log_output to redirect the log
2192 output to a file so as not to flood the stdin/out pipes.
2194 The -p/--pipe option is deprecated and a warning is printed
2195 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2197 Any other string is interpreted as named pipe to listen to.
2198 Output pipe is the same name as input pipe, but with 'o' appended,
2199 e.g. /var/gdb, /var/gdbo.
2201 The GDB port for the first target will be the base port, the
2202 second target will listen on gdb_port + 1, and so on.
2203 When not specified during the configuration stage,
2204 the port @var{number} defaults to 3333.
2205 @end deffn
2207 @deffn {Command} tcl_port [number]
2208 Specify or query the port used for a simplified RPC
2209 connection that can be used by clients to issue TCL commands and get the
2210 output from the Tcl engine.
2211 Intended as a machine interface.
2212 When not specified during the configuration stage,
2213 the port @var{number} defaults to 6666.
2215 @end deffn
2217 @deffn {Command} telnet_port [number]
2218 Specify or query the
2219 port on which to listen for incoming telnet connections.
2220 This port is intended for interaction with one human through TCL commands.
2221 When not specified during the configuration stage,
2222 the port @var{number} defaults to 4444.
2223 When specified as zero, this port is not activated.
2224 @end deffn
2226 @anchor{GDB Configuration}
2227 @section GDB Configuration
2228 @cindex GDB
2229 @cindex GDB configuration
2230 You can reconfigure some GDB behaviors if needed.
2231 The ones listed here are static and global.
2232 @xref{Target Configuration}, about configuring individual targets.
2233 @xref{Target Events}, about configuring target-specific event handling.
2235 @anchor{gdb_breakpoint_override}
2236 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2237 Force breakpoint type for gdb @command{break} commands.
2238 This option supports GDB GUIs which don't
2239 distinguish hard versus soft breakpoints, if the default OpenOCD and
2240 GDB behaviour is not sufficient. GDB normally uses hardware
2241 breakpoints if the memory map has been set up for flash regions.
2242 @end deffn
2244 @anchor{gdb_flash_program}
2245 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2246 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2247 vFlash packet is received.
2248 The default behaviour is @option{enable}.
2249 @end deffn
2251 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2252 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2253 requested. GDB will then know when to set hardware breakpoints, and program flash
2254 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2255 for flash programming to work.
2256 Default behaviour is @option{enable}.
2257 @xref{gdb_flash_program}.
2258 @end deffn
2260 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2261 Specifies whether data aborts cause an error to be reported
2262 by GDB memory read packets.
2263 The default behaviour is @option{disable};
2264 use @option{enable} see these errors reported.
2265 @end deffn
2267 @anchor{Event Polling}
2268 @section Event Polling
2270 Hardware debuggers are parts of asynchronous systems,
2271 where significant events can happen at any time.
2272 The OpenOCD server needs to detect some of these events,
2273 so it can report them to through TCL command line
2274 or to GDB.
2276 Examples of such events include:
2278 @itemize
2279 @item One of the targets can stop running ... maybe it triggers
2280 a code breakpoint or data watchpoint, or halts itself.
2281 @item Messages may be sent over ``debug message'' channels ... many
2282 targets support such messages sent over JTAG,
2283 for receipt by the person debugging or tools.
2284 @item Loss of power ... some adapters can detect these events.
2285 @item Resets not issued through JTAG ... such reset sources
2286 can include button presses or other system hardware, sometimes
2287 including the target itself (perhaps through a watchdog).
2288 @item Debug instrumentation sometimes supports event triggering
2289 such as ``trace buffer full'' (so it can quickly be emptied)
2290 or other signals (to correlate with code behavior).
2291 @end itemize
2293 None of those events are signaled through standard JTAG signals.
2294 However, most conventions for JTAG connectors include voltage
2295 level and system reset (SRST) signal detection.
2296 Some connectors also include instrumentation signals, which
2297 can imply events when those signals are inputs.
2299 In general, OpenOCD needs to periodically check for those events,
2300 either by looking at the status of signals on the JTAG connector
2301 or by sending synchronous ``tell me your status'' JTAG requests
2302 to the various active targets.
2303 There is a command to manage and monitor that polling,
2304 which is normally done in the background.
2306 @deffn Command poll [@option{on}|@option{off}]
2307 Poll the current target for its current state.
2308 (Also, @pxref{target curstate}.)
2309 If that target is in debug mode, architecture
2310 specific information about the current state is printed.
2311 An optional parameter
2312 allows background polling to be enabled and disabled.
2314 You could use this from the TCL command shell, or
2315 from GDB using @command{monitor poll} command.
2316 Leave background polling enabled while you're using GDB.
2317 @example
2318 > poll
2319 background polling: on
2320 target state: halted
2321 target halted in ARM state due to debug-request, \
2322 current mode: Supervisor
2323 cpsr: 0x800000d3 pc: 0x11081bfc
2324 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2325 >
2326 @end example
2327 @end deffn
2329 @node Debug Adapter Configuration
2330 @chapter Debug Adapter Configuration
2331 @cindex config file, interface
2332 @cindex interface config file
2334 Correctly installing OpenOCD includes making your operating system give
2335 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2336 are used to select which one is used, and to configure how it is used.
2338 @quotation Note
2339 Because OpenOCD started out with a focus purely on JTAG, you may find
2340 places where it wrongly presumes JTAG is the only transport protocol
2341 in use. Be aware that recent versions of OpenOCD are removing that
2342 limitation. JTAG remains more functional than most other transports.
2343 Other transports do not support boundary scan operations, or may be
2344 specific to a given chip vendor. Some might be usable only for
2345 programming flash memory, instead of also for debugging.
2346 @end quotation
2348 Debug Adapters/Interfaces/Dongles are normally configured
2349 through commands in an interface configuration
2350 file which is sourced by your @file{openocd.cfg} file, or
2351 through a command line @option{-f interface/....cfg} option.
2353 @example
2354 source [find interface/olimex-jtag-tiny.cfg]
2355 @end example
2357 These commands tell
2358 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2359 A few cases are so simple that you only need to say what driver to use:
2361 @example
2362 # jlink interface
2363 interface jlink
2364 @end example
2366 Most adapters need a bit more configuration than that.
2369 @section Interface Configuration
2371 The interface command tells OpenOCD what type of debug adapter you are
2372 using. Depending on the type of adapter, you may need to use one or
2373 more additional commands to further identify or configure the adapter.
2375 @deffn {Config Command} {interface} name
2376 Use the interface driver @var{name} to connect to the
2377 target.
2378 @end deffn
2380 @deffn Command {interface_list}
2381 List the debug adapter drivers that have been built into
2382 the running copy of OpenOCD.
2383 @end deffn
2384 @deffn Command {interface transports} transport_name+
2385 Specifies the transports supported by this debug adapter.
2386 The adapter driver builds-in similar knowledge; use this only
2387 when external configuration (such as jumpering) changes what
2388 the hardware can support.
2389 @end deffn
2393 @deffn Command {adapter_name}
2394 Returns the name of the debug adapter driver being used.
2395 @end deffn
2397 @section Interface Drivers
2399 Each of the interface drivers listed here must be explicitly
2400 enabled when OpenOCD is configured, in order to be made
2401 available at run time.
2403 @deffn {Interface Driver} {amt_jtagaccel}
2404 Amontec Chameleon in its JTAG Accelerator configuration,
2405 connected to a PC's EPP mode parallel port.
2406 This defines some driver-specific commands:
2408 @deffn {Config Command} {parport_port} number
2409 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2410 the number of the @file{/dev/parport} device.
2411 @end deffn
2413 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2414 Displays status of RTCK option.
2415 Optionally sets that option first.
2416 @end deffn
2417 @end deffn
2419 @deffn {Interface Driver} {arm-jtag-ew}
2420 Olimex ARM-JTAG-EW USB adapter
2421 This has one driver-specific command:
2423 @deffn Command {armjtagew_info}
2424 Logs some status
2425 @end deffn
2426 @end deffn
2428 @deffn {Interface Driver} {at91rm9200}
2429 Supports bitbanged JTAG from the local system,
2430 presuming that system is an Atmel AT91rm9200
2431 and a specific set of GPIOs is used.
2432 @c command: at91rm9200_device NAME
2433 @c chooses among list of bit configs ... only one option
2434 @end deffn
2436 @deffn {Interface Driver} {dummy}
2437 A dummy software-only driver for debugging.
2438 @end deffn
2440 @deffn {Interface Driver} {ep93xx}
2441 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2442 @end deffn
2444 @deffn {Interface Driver} {ft2232}
2445 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2446 These interfaces have several commands, used to configure the driver
2447 before initializing the JTAG scan chain:
2449 @deffn {Config Command} {ft2232_device_desc} description
2450 Provides the USB device description (the @emph{iProduct string})
2451 of the FTDI FT2232 device. If not
2452 specified, the FTDI default value is used. This setting is only valid
2453 if compiled with FTD2XX support.
2454 @end deffn
2456 @deffn {Config Command} {ft2232_serial} serial-number
2457 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2458 in case the vendor provides unique IDs and more than one FT2232 device
2459 is connected to the host.
2460 If not specified, serial numbers are not considered.
2461 (Note that USB serial numbers can be arbitrary Unicode strings,
2462 and are not restricted to containing only decimal digits.)
2463 @end deffn
2465 @deffn {Config Command} {ft2232_layout} name
2466 Each vendor's FT2232 device can use different GPIO signals
2467 to control output-enables, reset signals, and LEDs.
2468 Currently valid layout @var{name} values include:
2469 @itemize @minus
2470 @item @b{axm0432_jtag} Axiom AXM-0432
2471 @item @b{comstick} Hitex STR9 comstick
2472 @item @b{cortino} Hitex Cortino JTAG interface
2473 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
2474 either for the local Cortex-M3 (SRST only)
2475 or in a passthrough mode (neither SRST nor TRST)
2476 This layout can not support the SWO trace mechanism, and should be
2477 used only for older boards (before rev C).
2478 @item @b{luminary_icdi} This layout should be used with most Luminary
2479 eval boards, including Rev C LM3S811 eval boards and the eponymous
2480 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2481 to debug some other target. It can support the SWO trace mechanism.
2482 @item @b{flyswatter} Tin Can Tools Flyswatter
2483 @item @b{icebear} ICEbear JTAG adapter from Section 5
2484 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2485 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2486 @item @b{m5960} American Microsystems M5960
2487 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2488 @item @b{oocdlink} OOCDLink
2489 @c oocdlink ~= jtagkey_prototype_v1
2490 @item @b{redbee-econotag} Integrated with a Redbee development board.
2491 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2492 @item @b{sheevaplug} Marvell Sheevaplug development kit
2493 @item @b{signalyzer} Xverve Signalyzer
2494 @item @b{stm32stick} Hitex STM32 Performance Stick
2495 @item @b{turtelizer2} egnite Software turtelizer2
2496 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2497 @end itemize
2498 @end deffn
2500 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2501 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2502 default values are used.
2503 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2504 @example
2505 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2506 @end example
2507 @end deffn
2509 @deffn {Config Command} {ft2232_latency} ms
2510 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2511 ft2232_read() fails to return the expected number of bytes. This can be caused by
2512 USB communication delays and has proved hard to reproduce and debug. Setting the
2513 FT2232 latency timer to a larger value increases delays for short USB packets but it
2514 also reduces the risk of timeouts before receiving the expected number of bytes.
2515 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2516 @end deffn
2518 For example, the interface config file for a
2519 Turtelizer JTAG Adapter looks something like this:
2521 @example
2522 interface ft2232
2523 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2524 ft2232_layout turtelizer2
2525 ft2232_vid_pid 0x0403 0xbdc8
2526 @end example
2527 @end deffn
2529 @deffn {Interface Driver} {remote_bitbang}
2530 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2531 with a remote process and sends ASCII encoded bitbang requests to that process
2532 instead of directly driving JTAG.
2534 The remote_bitbang driver is useful for debugging software running on
2535 processors which are being simulated.
2537 @deffn {Config Command} {remote_bitbang_port} number
2538 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2539 sockets instead of TCP.
2540 @end deffn
2542 @deffn {Config Command} {remote_bitbang_host} hostname
2543 Specifies the hostname of the remote process to connect to using TCP, or the
2544 name of the UNIX socket to use if remote_bitbang_port is 0.
2545 @end deffn
2547 For example, to connect remotely via TCP to the host foobar you might have
2548 something like:
2550 @example
2551 interface remote_bitbang
2552 remote_bitbang_port 3335
2553 remote_bitbang_host foobar
2554 @end example
2556 To connect to another process running locally via UNIX sockets with socket
2557 named mysocket:
2559 @example
2560 interface remote_bitbang
2561 remote_bitbang_port 0
2562 remote_bitbang_host mysocket
2563 @end example
2564 @end deffn
2566 @deffn {Interface Driver} {usb_blaster}
2567 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2568 for FTDI chips. These interfaces have several commands, used to
2569 configure the driver before initializing the JTAG scan chain:
2571 @deffn {Config Command} {usb_blaster_device_desc} description
2572 Provides the USB device description (the @emph{iProduct string})
2573 of the FTDI FT245 device. If not
2574 specified, the FTDI default value is used. This setting is only valid
2575 if compiled with FTD2XX support.
2576 @end deffn
2578 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2579 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2580 default values are used.
2581 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2582 Altera USB-Blaster (default):
2583 @example
2584 usb_blaster_vid_pid 0x09FB 0x6001
2585 @end example
2586 The following VID/PID is for Kolja Waschk's USB JTAG:
2587 @example
2588 usb_blaster_vid_pid 0x16C0 0x06AD
2589 @end example
2590 @end deffn
2592 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2593 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2594 female JTAG header). These pins can be used as SRST and/or TRST provided the
2595 appropriate connections are made on the target board.
2597 For example, to use pin 6 as SRST (as with an AVR board):
2598 @example
2599 $_TARGETNAME configure -event reset-assert \
2600 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2601 @end example
2602 @end deffn
2604 @end deffn
2606 @deffn {Interface Driver} {gw16012}
2607 Gateworks GW16012 JTAG programmer.
2608 This has one driver-specific command:
2610 @deffn {Config Command} {parport_port} [port_number]
2611 Display either the address of the I/O port
2612 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2613 If a parameter is provided, first switch to use that port.
2614 This is a write-once setting.
2615 @end deffn
2616 @end deffn
2618 @deffn {Interface Driver} {jlink}
2619 Segger jlink USB adapter
2620 @c command: jlink caps
2621 @c dumps jlink capabilities
2622 @c command: jlink config
2623 @c access J-Link configurationif no argument this will dump the config
2624 @c command: jlink config kickstart [val]
2625 @c set Kickstart power on JTAG-pin 19.
2626 @c command: jlink config mac_address [ff:ff:ff:ff:ff:ff]
2627 @c set the MAC Address
2628 @c command: jlink config ip [A.B.C.D[/E] [F.G.H.I]]
2629 @c set the ip address of the J-Link Pro, "
2630 @c where A.B.C.D is the ip,
2631 @c E the bit of the subnet mask
2632 @c F.G.H.I the subnet mask
2633 @c command: jlink config reset
2634 @c reset the current config
2635 @c command: jlink config save
2636 @c save the current config
2637 @c command: jlink config usb_address [0x00 to 0x03 or 0xff]
2638 @c set the USB-Address,
2639 @c This will change the product id
2640 @c command: jlink info
2641 @c dumps status
2642 @c command: jlink hw_jtag (2|3)
2643 @c sets version 2 or 3
2644 @c command: jlink pid
2645 @c set the pid of the interface we want to use
2646 @end deffn
2648 @deffn {Interface Driver} {parport}
2649 Supports PC parallel port bit-banging cables:
2650 Wigglers, PLD download cable, and more.
2651 These interfaces have several commands, used to configure the driver
2652 before initializing the JTAG scan chain:
2654 @deffn {Config Command} {parport_cable} name
2655 Set the layout of the parallel port cable used to connect to the target.
2656 This is a write-once setting.
2657 Currently valid cable @var{name} values include:
2659 @itemize @minus
2660 @item @b{altium} Altium Universal JTAG cable.
2661 @item @b{arm-jtag} Same as original wiggler except SRST and
2662 TRST connections reversed and TRST is also inverted.
2663 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2664 in configuration mode. This is only used to
2665 program the Chameleon itself, not a connected target.
2666 @item @b{dlc5} The Xilinx Parallel cable III.
2667 @item @b{flashlink} The ST Parallel cable.
2668 @item @b{lattice} Lattice ispDOWNLOAD Cable
2669 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2670 some versions of
2671 Amontec's Chameleon Programmer. The new version available from
2672 the website uses the original Wiggler layout ('@var{wiggler}')
2673 @item @b{triton} The parallel port adapter found on the
2674 ``Karo Triton 1 Development Board''.
2675 This is also the layout used by the HollyGates design
2676 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2677 @item @b{wiggler} The original Wiggler layout, also supported by
2678 several clones, such as the Olimex ARM-JTAG
2679 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2680 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2681 @end itemize
2682 @end deffn
2684 @deffn {Config Command} {parport_port} [port_number]
2685 Display either the address of the I/O port
2686 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2687 If a parameter is provided, first switch to use that port.
2688 This is a write-once setting.
2690 When using PPDEV to access the parallel port, use the number of the parallel port:
2691 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2692 you may encounter a problem.
2693 @end deffn
2695 @deffn Command {parport_toggling_time} [nanoseconds]
2696 Displays how many nanoseconds the hardware needs to toggle TCK;
2697 the parport driver uses this value to obey the
2698 @command{adapter_khz} configuration.
2699 When the optional @var{nanoseconds} parameter is given,
2700 that setting is changed before displaying the current value.
2702 The default setting should work reasonably well on commodity PC hardware.
2703 However, you may want to calibrate for your specific hardware.
2704 @quotation Tip
2705 To measure the toggling time with a logic analyzer or a digital storage
2706 oscilloscope, follow the procedure below:
2707 @example
2708 > parport_toggling_time 1000
2709 > adapter_khz 500
2710 @end example
2711 This sets the maximum JTAG clock speed of the hardware, but
2712 the actual speed probably deviates from the requested 500 kHz.
2713 Now, measure the time between the two closest spaced TCK transitions.
2714 You can use @command{runtest 1000} or something similar to generate a
2715 large set of samples.
2716 Update the setting to match your measurement:
2717 @example
2718 > parport_toggling_time <measured nanoseconds>
2719 @end example
2720 Now the clock speed will be a better match for @command{adapter_khz rate}
2721 commands given in OpenOCD scripts and event handlers.
2723 You can do something similar with many digital multimeters, but note
2724 that you'll probably need to run the clock continuously for several
2725 seconds before it decides what clock rate to show. Adjust the
2726 toggling time up or down until the measured clock rate is a good
2727 match for the adapter_khz rate you specified; be conservative.
2728 @end quotation
2729 @end deffn
2731 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2732 This will configure the parallel driver to write a known
2733 cable-specific value to the parallel interface on exiting OpenOCD.
2734 @end deffn
2736 For example, the interface configuration file for a
2737 classic ``Wiggler'' cable on LPT2 might look something like this:
2739 @example
2740 interface parport
2741 parport_port 0x278
2742 parport_cable wiggler
2743 @end example
2744 @end deffn
2746 @deffn {Interface Driver} {presto}
2747 ASIX PRESTO USB JTAG programmer.
2748 @deffn {Config Command} {presto_serial} serial_string
2749 Configures the USB serial number of the Presto device to use.
2750 @end deffn
2751 @end deffn
2753 @deffn {Interface Driver} {rlink}
2754 Raisonance RLink USB adapter
2755 @end deffn
2757 @deffn {Interface Driver} {usbprog}
2758 usbprog is a freely programmable USB adapter.
2759 @end deffn
2761 @deffn {Interface Driver} {vsllink}
2762 vsllink is part of Versaloon which is a versatile USB programmer.
2764 @quotation Note
2765 This defines quite a few driver-specific commands,
2766 which are not currently documented here.
2767 @end quotation
2768 @end deffn
2770 @deffn {Interface Driver} {stlink}
2771 ST Micro ST-LINK adapter.
2773 @deffn {Config Command} {stlink_device_desc} description
2774 Currently Not Supported.
2775 @end deffn
2777 @deffn {Config Command} {stlink_serial} serial
2778 Currently Not Supported.
2779 @end deffn
2781 @deffn {Config Command} {stlink_layout} (@option{sg}|@option{usb})
2782 Specifies the stlink layout to use.
2783 @end deffn
2785 @deffn {Config Command} {stlink_vid_pid} vid pid
2786 The vendor ID and product ID of the STLINK device.
2787 @end deffn
2789 @deffn {Config Command} {stlink_api} api_level
2790 Manually sets the stlink api used, valid options are 1 or 2.
2791 @end deffn
2792 @end deffn
2794 @deffn {Interface Driver} {opendous}
2795 opendous-jtag is a freely programmable USB adapter.
2796 @end deffn
2798 @deffn {Interface Driver} {ZY1000}
2799 This is the Zylin ZY1000 JTAG debugger.
2800 @end deffn
2802 @quotation Note
2803 This defines some driver-specific commands,
2804 which are not currently documented here.
2805 @end quotation
2807 @deffn Command power [@option{on}|@option{off}]
2808 Turn power switch to target on/off.
2809 No arguments: print status.
2810 @end deffn
2812 @section Transport Configuration
2813 @cindex Transport
2814 As noted earlier, depending on the version of OpenOCD you use,
2815 and the debug adapter you are using,
2816 several transports may be available to
2817 communicate with debug targets (or perhaps to program flash memory).
2818 @deffn Command {transport list}
2819 displays the names of the transports supported by this
2820 version of OpenOCD.
2821 @end deffn
2823 @deffn Command {transport select} transport_name
2824 Select which of the supported transports to use in this OpenOCD session.
2825 The transport must be supported by the debug adapter hardware and by the
2826 version of OPenOCD you are using (including the adapter's driver).
2827 No arguments: returns name of session's selected transport.
2828 @end deffn
2830 @subsection JTAG Transport
2831 @cindex JTAG
2832 JTAG is the original transport supported by OpenOCD, and most
2833 of the OpenOCD commands support it.
2834 JTAG transports expose a chain of one or more Test Access Points (TAPs),
2835 each of which must be explicitly declared.
2836 JTAG supports both debugging and boundary scan testing.
2837 Flash programming support is built on top of debug support.
2838 @subsection SWD Transport
2839 @cindex SWD
2840 @cindex Serial Wire Debug
2841 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
2842 Debug Access Point (DAP, which must be explicitly declared.
2843 (SWD uses fewer signal wires than JTAG.)
2844 SWD is debug-oriented, and does not support boundary scan testing.
2845 Flash programming support is built on top of debug support.
2846 (Some processors support both JTAG and SWD.)
2847 @deffn Command {swd newdap} ...
2848 Declares a single DAP which uses SWD transport.
2849 Parameters are currently the same as "jtag newtap" but this is
2850 expected to change.
2851 @end deffn
2852 @deffn Command {swd wcr trn prescale}
2853 Updates TRN (turnaraound delay) and prescaling.fields of the
2854 Wire Control Register (WCR).
2855 No parameters: displays current settings.
2856 @end deffn
2858 @subsection SPI Transport
2859 @cindex SPI
2860 @cindex Serial Peripheral Interface
2861 The Serial Peripheral Interface (SPI) is a general purpose transport
2862 which uses four wire signaling. Some processors use it as part of a
2863 solution for flash programming.
2865 @anchor{JTAG Speed}
2866 @section JTAG Speed
2867 JTAG clock setup is part of system setup.
2868 It @emph{does not belong with interface setup} since any interface
2869 only knows a few of the constraints for the JTAG clock speed.
2870 Sometimes the JTAG speed is
2871 changed during the target initialization process: (1) slow at
2872 reset, (2) program the CPU clocks, (3) run fast.
2873 Both the "slow" and "fast" clock rates are functions of the
2874 oscillators used, the chip, the board design, and sometimes
2875 power management software that may be active.
2877 The speed used during reset, and the scan chain verification which
2878 follows reset, can be adjusted using a @code{reset-start}
2879 target event handler.
2880 It can then be reconfigured to a faster speed by a
2881 @code{reset-init} target event handler after it reprograms those
2882 CPU clocks, or manually (if something else, such as a boot loader,
2883 sets up those clocks).
2884 @xref{Target Events}.
2885 When the initial low JTAG speed is a chip characteristic, perhaps
2886 because of a required oscillator speed, provide such a handler
2887 in the target config file.
2888 When that speed is a function of a board-specific characteristic
2889 such as which speed oscillator is used, it belongs in the board
2890 config file instead.
2891 In both cases it's safest to also set the initial JTAG clock rate
2892 to that same slow speed, so that OpenOCD never starts up using a
2893 clock speed that's faster than the scan chain can support.
2895 @example
2896 jtag_rclk 3000
2897 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
2898 @end example
2900 If your system supports adaptive clocking (RTCK), configuring
2901 JTAG to use that is probably the most robust approach.
2902 However, it introduces delays to synchronize clocks; so it
2903 may not be the fastest solution.
2905 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
2906 instead of @command{adapter_khz}, but only for (ARM) cores and boards
2907 which support adaptive clocking.
2909 @deffn {Command} adapter_khz max_speed_kHz
2910 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
2911 JTAG interfaces usually support a limited number of
2912 speeds. The speed actually used won't be faster
2913 than the speed specified.
2915 Chip data sheets generally include a top JTAG clock rate.
2916 The actual rate is often a function of a CPU core clock,
2917 and is normally less than that peak rate.
2918 For example, most ARM cores accept at most one sixth of the CPU clock.
2920 Speed 0 (khz) selects RTCK method.
2921 @xref{FAQ RTCK}.
2922 If your system uses RTCK, you won't need to change the
2923 JTAG clocking after setup.
2924 Not all interfaces, boards, or targets support ``rtck''.
2925 If the interface device can not
2926 support it, an error is returned when you try to use RTCK.
2927 @end deffn
2929 @defun jtag_rclk fallback_speed_kHz
2930 @cindex adaptive clocking
2931 @cindex RTCK
2932 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
2933 If that fails (maybe the interface, board, or target doesn't
2934 support it), falls back to the specified frequency.
2935 @example
2936 # Fall back to 3mhz if RTCK is not supported
2937 jtag_rclk 3000
2938 @end example
2939 @end defun
2941 @node Reset Configuration
2942 @chapter Reset Configuration
2943 @cindex Reset Configuration
2945 Every system configuration may require a different reset
2946 configuration. This can also be quite confusing.
2947 Resets also interact with @var{reset-init} event handlers,
2948 which do things like setting up clocks and DRAM, and
2949 JTAG clock rates. (@xref{JTAG Speed}.)
2950 They can also interact with JTAG routers.
2951 Please see the various board files for examples.
2953 @quotation Note
2954 To maintainers and integrators:
2955 Reset configuration touches several things at once.
2956 Normally the board configuration file
2957 should define it and assume that the JTAG adapter supports
2958 everything that's wired up to the board's JTAG connector.
2960 However, the target configuration file could also make note
2961 of something the silicon vendor has done inside the chip,
2962 which will be true for most (or all) boards using that chip.
2963 And when the JTAG adapter doesn't support everything, the
2964 user configuration file will need to override parts of
2965 the reset configuration provided by other files.
2966 @end quotation
2968 @section Types of Reset
2970 There are many kinds of reset possible through JTAG, but
2971 they may not all work with a given board and adapter.
2972 That's part of why reset configuration can be error prone.
2974 @itemize @bullet
2975 @item
2976 @emph{System Reset} ... the @emph{SRST} hardware signal
2977 resets all chips connected to the JTAG adapter, such as processors,
2978 power management chips, and I/O controllers. Normally resets triggered
2979 with this signal behave exactly like pressing a RESET button.
2980 @item
2981 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
2982 just the TAP controllers connected to the JTAG adapter.
2983 Such resets should not be visible to the rest of the system; resetting a
2984 device's TAP controller just puts that controller into a known state.
2985 @item
2986 @emph{Emulation Reset} ... many devices can be reset through JTAG
2987 commands. These resets are often distinguishable from system
2988 resets, either explicitly (a "reset reason" register says so)
2989 or implicitly (not all parts of the chip get reset).
2990 @item
2991 @emph{Other Resets} ... system-on-chip devices often support
2992 several other types of reset.
2993 You may need to arrange that a watchdog timer stops
2994 while debugging, preventing a watchdog reset.
2995 There may be individual module resets.
2996 @end itemize
2998 In the best case, OpenOCD can hold SRST, then reset
2999 the TAPs via TRST and send commands through JTAG to halt the
3000 CPU at the reset vector before the 1st instruction is executed.
3001 Then when it finally releases the SRST signal, the system is
3002 halted under debugger control before any code has executed.
3003 This is the behavior required to support the @command{reset halt}
3004 and @command{reset init} commands; after @command{reset init} a
3005 board-specific script might do things like setting up DRAM.
3006 (@xref{Reset Command}.)
3008 @anchor{SRST and TRST Issues}
3009 @section SRST and TRST Issues
3011 Because SRST and TRST are hardware signals, they can have a
3012 variety of system-specific constraints. Some of the most
3013 common issues are:
3015 @itemize @bullet
3017 @item @emph{Signal not available} ... Some boards don't wire
3018 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3019 support such signals even if they are wired up.
3020 Use the @command{reset_config} @var{signals} options to say
3021 when either of those signals is not connected.
3022 When SRST is not available, your code might not be able to rely
3023 on controllers having been fully reset during code startup.
3024 Missing TRST is not a problem, since JTAG-level resets can
3025 be triggered using with TMS signaling.
3027 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3028 adapter will connect SRST to TRST, instead of keeping them separate.
3029 Use the @command{reset_config} @var{combination} options to say
3030 when those signals aren't properly independent.
3032 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3033 delay circuit, reset supervisor, or on-chip features can extend
3034 the effect of a JTAG adapter's reset for some time after the adapter
3035 stops issuing the reset. For example, there may be chip or board
3036 requirements that all reset pulses last for at least a
3037 certain amount of time; and reset buttons commonly have
3038 hardware debouncing.
3039 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3040 commands to say when extra delays are needed.
3042 @item @emph{Drive type} ... Reset lines often have a pullup
3043 resistor, letting the JTAG interface treat them as open-drain
3044 signals. But that's not a requirement, so the adapter may need
3045 to use push/pull output drivers.
3046 Also, with weak pullups it may be advisable to drive
3047 signals to both levels (push/pull) to minimize rise times.
3048 Use the @command{reset_config} @var{trst_type} and
3049 @var{srst_type} parameters to say how to drive reset signals.
3051 @item @emph{Special initialization} ... Targets sometimes need
3052 special JTAG initialization sequences to handle chip-specific
3053 issues (not limited to errata).
3054 For example, certain JTAG commands might need to be issued while
3055 the system as a whole is in a reset state (SRST active)
3056 but the JTAG scan chain is usable (TRST inactive).
3057 Many systems treat combined assertion of SRST and TRST as a
3058 trigger for a harder reset than SRST alone.
3059 Such custom reset handling is discussed later in this chapter.
3060 @end itemize
3062 There can also be other issues.
3063 Some devices don't fully conform to the JTAG specifications.
3064 Trivial system-specific differences are common, such as
3065 SRST and TRST using slightly different names.
3066 There are also vendors who distribute key JTAG documentation for
3067 their chips only to developers who have signed a Non-Disclosure
3068 Agreement (NDA).
3070 Sometimes there are chip-specific extensions like a requirement to use
3071 the normally-optional TRST signal (precluding use of JTAG adapters which
3072 don't pass TRST through), or needing extra steps to complete a TAP reset.
3074 In short, SRST and especially TRST handling may be very finicky,
3075 needing to cope with both architecture and board specific constraints.
3077 @section Commands for Handling Resets
3079 @deffn {Command} adapter_nsrst_assert_width milliseconds
3080 Minimum amount of time (in milliseconds) OpenOCD should wait
3081 after asserting nSRST (active-low system reset) before
3082 allowing it to be deasserted.
3083 @end deffn
3085 @deffn {Command} adapter_nsrst_delay milliseconds
3086 How long (in milliseconds) OpenOCD should wait after deasserting
3087 nSRST (active-low system reset) before starting new JTAG operations.
3088 When a board has a reset button connected to SRST line it will
3089 probably have hardware debouncing, implying you should use this.
3090 @end deffn
3092 @deffn {Command} jtag_ntrst_assert_width milliseconds
3093 Minimum amount of time (in milliseconds) OpenOCD should wait
3094 after asserting nTRST (active-low JTAG TAP reset) before
3095 allowing it to be deasserted.
3096 @end deffn
3098 @deffn {Command} jtag_ntrst_delay milliseconds
3099 How long (in milliseconds) OpenOCD should wait after deasserting
3100 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3101 @end deffn
3103 @deffn {Command} reset_config mode_flag ...
3104 This command displays or modifies the reset configuration
3105 of your combination of JTAG board and target in target
3106 configuration scripts.
3108 Information earlier in this section describes the kind of problems
3109 the command is intended to address (@pxref{SRST and TRST Issues}).
3110 As a rule this command belongs only in board config files,
3111 describing issues like @emph{board doesn't connect TRST};
3112 or in user config files, addressing limitations derived
3113 from a particular combination of interface and board.
3114 (An unlikely example would be using a TRST-only adapter
3115 with a board that only wires up SRST.)
3117 The @var{mode_flag} options can be specified in any order, but only one
3118 of each type -- @var{signals}, @var{combination},
3119 @var{gates},
3120 @var{trst_type},
3121 and @var{srst_type} -- may be specified at a time.
3122 If you don't provide a new value for a given type, its previous
3123 value (perhaps the default) is unchanged.
3124 For example, this means that you don't need to say anything at all about
3125 TRST just to declare that if the JTAG adapter should want to drive SRST,
3126 it must explicitly be driven high (@option{srst_push_pull}).
3128 @itemize
3129 @item
3130 @var{signals} can specify which of the reset signals are connected.
3131 For example, If the JTAG interface provides SRST, but the board doesn't
3132 connect that signal properly, then OpenOCD can't use it.
3133 Possible values are @option{none} (the default), @option{trst_only},
3134 @option{srst_only} and @option{trst_and_srst}.
3136 @quotation Tip
3137 If your board provides SRST and/or TRST through the JTAG connector,
3138 you must declare that so those signals can be used.
3139 @end quotation
3141 @item
3142 The @var{combination} is an optional value specifying broken reset
3143 signal implementations.
3144 The default behaviour if no option given is @option{separate},
3145 indicating everything behaves normally.
3146 @option{srst_pulls_trst} states that the
3147 test logic is reset together with the reset of the system (e.g. NXP
3148 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3149 the system is reset together with the test logic (only hypothetical, I
3150 haven't seen hardware with such a bug, and can be worked around).
3151 @option{combined} implies both @option{srst_pulls_trst} and
3152 @option{trst_pulls_srst}.
3154 @item
3155 The @var{gates} tokens control flags that describe some cases where
3156 JTAG may be unvailable during reset.
3157 @option{srst_gates_jtag} (default)
3158 indicates that asserting SRST gates the
3159 JTAG clock. This means that no communication can happen on JTAG
3160 while SRST is asserted.
3161 Its converse is @option{srst_nogate}, indicating that JTAG commands
3162 can safely be issued while SRST is active.
3163 @end itemize
3165 The optional @var{trst_type} and @var{srst_type} parameters allow the
3166 driver mode of each reset line to be specified. These values only affect
3167 JTAG interfaces with support for different driver modes, like the Amontec
3168 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3169 relevant signal (TRST or SRST) is not connected.
3171 @itemize
3172 @item
3173 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3174 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3175 Most boards connect this signal to a pulldown, so the JTAG TAPs
3176 never leave reset unless they are hooked up to a JTAG adapter.
3178 @item
3179 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3180 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3181 Most boards connect this signal to a pullup, and allow the
3182 signal to be pulled low by various events including system
3183 powerup and pressing a reset button.
3184 @end itemize
3185 @end deffn
3187 @section Custom Reset Handling
3188 @cindex events
3190 OpenOCD has several ways to help support the various reset
3191 mechanisms provided by chip and board vendors.
3192 The commands shown in the previous section give standard parameters.
3193 There are also @emph{event handlers} associated with TAPs or Targets.
3194 Those handlers are Tcl procedures you can provide, which are invoked
3195 at particular points in the reset sequence.
3197 @emph{When SRST is not an option} you must set
3198 up a @code{reset-assert} event handler for your target.
3199 For example, some JTAG adapters don't include the SRST signal;
3200 and some boards have multiple targets, and you won't always
3201 want to reset everything at once.
3203 After configuring those mechanisms, you might still
3204 find your board doesn't start up or reset correctly.
3205 For example, maybe it needs a slightly different sequence
3206 of SRST and/or TRST manipulations, because of quirks that
3207 the @command{reset_config} mechanism doesn't address;
3208 or asserting both might trigger a stronger reset, which
3209 needs special attention.
3211 Experiment with lower level operations, such as @command{jtag_reset}
3212 and the @command{jtag arp_*} operations shown here,
3213 to find a sequence of operations that works.
3214 @xref{JTAG Commands}.
3215 When you find a working sequence, it can be used to override
3216 @command{jtag_init}, which fires during OpenOCD startup
3217 (@pxref{Configuration Stage});
3218 or @command{init_reset}, which fires during reset processing.
3220 You might also want to provide some project-specific reset
3221 schemes. For example, on a multi-target board the standard
3222 @command{reset} command would reset all targets, but you
3223 may need the ability to reset only one target at time and
3224 thus want to avoid using the board-wide SRST signal.
3226 @deffn {Overridable Procedure} init_reset mode
3227 This is invoked near the beginning of the @command{reset} command,
3228 usually to provide as much of a cold (power-up) reset as practical.
3229 By default it is also invoked from @command{jtag_init} if
3230 the scan chain does not respond to pure JTAG operations.
3231 The @var{mode} parameter is the parameter given to the
3232 low level reset command (@option{halt},
3233 @option{init}, or @option{run}), @option{setup},
3234 or potentially some other value.
3236 The default implementation just invokes @command{jtag arp_init-reset}.
3237 Replacements will normally build on low level JTAG
3238 operations such as @command{jtag_reset}.
3239 Operations here must not address individual TAPs
3240 (or their associated targets)
3241 until the JTAG scan chain has first been verified to work.
3243 Implementations must have verified the JTAG scan chain before
3244 they return.
3245 This is done by calling @command{jtag arp_init}
3246 (or @command{jtag arp_init-reset}).
3247 @end deffn
3249 @deffn Command {jtag arp_init}
3250 This validates the scan chain using just the four
3251 standard JTAG signals (TMS, TCK, TDI, TDO).
3252 It starts by issuing a JTAG-only reset.
3253 Then it performs checks to verify that the scan chain configuration
3254 matches the TAPs it can observe.
3255 Those checks include checking IDCODE values for each active TAP,
3256 and verifying the length of their instruction registers using
3257 TAP @code{-ircapture} and @code{-irmask} values.
3258 If these tests all pass, TAP @code{setup} events are
3259 issued to all TAPs with handlers for that event.
3260 @end deffn
3262 @deffn Command {jtag arp_init-reset}
3263 This uses TRST and SRST to try resetting
3264 everything on the JTAG scan chain
3265 (and anything else connected to SRST).
3266 It then invokes the logic of @command{jtag arp_init}.
3267 @end deffn
3270 @node TAP Declaration
3271 @chapter TAP Declaration
3272 @cindex TAP declaration
3273 @cindex TAP configuration
3275 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3276 TAPs serve many roles, including:
3278 @itemize @bullet
3279 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
3280 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
3281 Others do it indirectly, making a CPU do it.
3282 @item @b{Program Download} Using the same CPU support GDB uses,
3283 you can initialize a DRAM controller, download code to DRAM, and then
3284 start running that code.
3285 @item @b{Boundary Scan} Most chips support boundary scan, which
3286 helps test for board assembly problems like solder bridges
3287 and missing connections
3288 @end itemize
3290 OpenOCD must know about the active TAPs on your board(s).
3291 Setting up the TAPs is the core task of your configuration files.
3292 Once those TAPs are set up, you can pass their names to code
3293 which sets up CPUs and exports them as GDB targets,
3294 probes flash memory, performs low-level JTAG operations, and more.
3296 @section Scan Chains
3297 @cindex scan chain
3299 TAPs are part of a hardware @dfn{scan chain},
3300 which is daisy chain of TAPs.
3301 They also need to be added to
3302 OpenOCD's software mirror of that hardware list,
3303 giving each member a name and associating other data with it.
3304 Simple scan chains, with a single TAP, are common in
3305 systems with a single microcontroller or microprocessor.
3306 More complex chips may have several TAPs internally.
3307 Very complex scan chains might have a dozen or more TAPs:
3308 several in one chip, more in the next, and connecting
3309 to other boards with their own chips and TAPs.
3311 You can display the list with the @command{scan_chain} command.
3312 (Don't confuse this with the list displayed by the @command{targets}
3313 command, presented in the next chapter.
3314 That only displays TAPs for CPUs which are configured as
3315 debugging targets.)
3316 Here's what the scan chain might look like for a chip more than one TAP:
3318 @verbatim
3319 TapName Enabled IdCode Expected IrLen IrCap IrMask
3320 -- ------------------ ------- ---------- ---------- ----- ----- ------
3321 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3322 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3323 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3324 @end verbatim
3326 OpenOCD can detect some of that information, but not all
3327 of it. @xref{Autoprobing}.
3328 Unfortunately those TAPs can't always be autoconfigured,
3329 because not all devices provide good support for that.
3330 JTAG doesn't require supporting IDCODE instructions, and
3331 chips with JTAG routers may not link TAPs into the chain
3332 until they are told to do so.
3334 The configuration mechanism currently supported by OpenOCD
3335 requires explicit configuration of all TAP devices using
3336 @command{jtag newtap} commands, as detailed later in this chapter.
3337 A command like this would declare one tap and name it @code{chip1.cpu}:
3339 @example
3340 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3341 @end example
3343 Each target configuration file lists the TAPs provided
3344 by a given chip.
3345 Board configuration files combine all the targets on a board,
3346 and so forth.
3347 Note that @emph{the order in which TAPs are declared is very important.}
3348 It must match the order in the JTAG scan chain, both inside
3349 a single chip and between them.
3350 @xref{FAQ TAP Order}.
3352 For example, the ST Microsystems STR912 chip has
3353 three separate TAPs@footnote{See the ST
3354 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3355 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3356 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3357 To configure those taps, @file{target/str912.cfg}
3358 includes commands something like this:
3360 @example
3361 jtag newtap str912 flash ... params ...
3362 jtag newtap str912 cpu ... params ...
3363 jtag newtap str912 bs ... params ...
3364 @end example
3366 Actual config files use a variable instead of literals like
3367 @option{str912}, to support more than one chip of each type.
3368 @xref{Config File Guidelines}.
3370 @deffn Command {jtag names}
3371 Returns the names of all current TAPs in the scan chain.
3372 Use @command{jtag cget} or @command{jtag tapisenabled}
3373 to examine attributes and state of each TAP.
3374 @example
3375 foreach t [jtag names] @{
3376 puts [format "TAP: %s\n" $t]
3377 @}
3378 @end example
3379 @end deffn
3381 @deffn Command {scan_chain}
3382 Displays the TAPs in the scan chain configuration,
3383 and their status.
3384 The set of TAPs listed by this command is fixed by
3385 exiting the OpenOCD configuration stage,
3386 but systems with a JTAG router can
3387 enable or disable TAPs dynamically.
3388 @end deffn
3390 @c FIXME! "jtag cget" should be able to return all TAP
3391 @c attributes, like "$target_name cget" does for targets.
3393 @c Probably want "jtag eventlist", and a "tap-reset" event
3394 @c (on entry to RESET state).
3396 @section TAP Names
3397 @cindex dotted name
3399 When TAP objects are declared with @command{jtag newtap},
3400 a @dfn{dotted.name} is created for the TAP, combining the
3401 name of a module (usually a chip) and a label for the TAP.
3402 For example: @code{xilinx.tap}, @code{str912.flash},
3403 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3404 Many other commands use that dotted.name to manipulate or
3405 refer to the TAP. For example, CPU configuration uses the
3406 name, as does declaration of NAND or NOR flash banks.
3408 The components of a dotted name should follow ``C'' symbol
3409 name rules: start with an alphabetic character, then numbers
3410 and underscores are OK; while others (including dots!) are not.
3412 @quotation Tip
3413 In older code, JTAG TAPs were numbered from 0..N.
3414 This feature is still present.
3415 However its use is highly discouraged, and
3416 should not be relied on; it will be removed by mid-2010.
3417 Update all of your scripts to use TAP names rather than numbers,
3418 by paying attention to the runtime warnings they trigger.
3419 Using TAP numbers in target configuration scripts prevents
3420 reusing those scripts on boards with multiple targets.
3421 @end quotation
3423 @section TAP Declaration Commands
3425 @c shouldn't this be(come) a {Config Command}?
3426 @anchor{jtag newtap}
3427 @deffn Command {jtag newtap} chipname tapname configparams...
3428 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3429 and configured according to the various @var{configparams}.
3431 The @var{chipname} is a symbolic name for the chip.
3432 Conventionally target config files use @code{$_CHIPNAME},
3433 defaulting to the model name given by the chip vendor but
3434 overridable.
3436 @cindex TAP naming convention
3437 The @var{tapname} reflects the role of that TAP,
3438 and should follow this convention:
3440 @itemize @bullet
3441 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3442 @item @code{cpu} -- The main CPU of the chip, alternatively
3443 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3444 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3445 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3446 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3447 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3448 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3449 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3450 with a single TAP;
3451 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3452 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3453 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3454 a JTAG TAP; that TAP should be named @code{sdma}.
3455 @end itemize
3457 Every TAP requires at least the following @var{configparams}:
3459 @itemize @bullet
3460 @item @code{-irlen} @var{NUMBER}
3461 @*The length in bits of the
3462 instruction register, such as 4 or 5 bits.
3463 @end itemize
3465 A TAP may also provide optional @var{configparams}:
3467 @itemize @bullet
3468 @item @code{-disable} (or @code{-enable})
3469 @*Use the @code{-disable} parameter to flag a TAP which is not
3470 linked in to the scan chain after a reset using either TRST
3471 or the JTAG state machine's @sc{reset} state.
3472 You may use @code{-enable} to highlight the default state
3473 (the TAP is linked in).
3474 @xref{Enabling and Disabling TAPs}.
3475 @item @code{-expected-id} @var{number}
3476 @*A non-zero @var{number} represents a 32-bit IDCODE
3477 which you expect to find when the scan chain is examined.
3478 These codes are not required by all JTAG devices.
3479 @emph{Repeat the option} as many times as required if more than one
3480 ID code could appear (for example, multiple versions).
3481 Specify @var{number} as zero to suppress warnings about IDCODE
3482 values that were found but not included in the list.
3484 Provide this value if at all possible, since it lets OpenOCD
3485 tell when the scan chain it sees isn't right. These values
3486 are provided in vendors' chip documentation, usually a technical
3487 reference manual. Sometimes you may need to probe the JTAG
3488 hardware to find these values.
3489 @xref{Autoprobing}.
3490 @item @code{-ignore-version}
3491 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3492 option. When vendors put out multiple versions of a chip, or use the same
3493 JTAG-level ID for several largely-compatible chips, it may be more practical
3494 to ignore the version field than to update config files to handle all of
3495 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3496 @item @code{-ircapture} @var{NUMBER}
3497 @*The bit pattern loaded by the TAP into the JTAG shift register
3498 on entry to the @sc{ircapture} state, such as 0x01.
3499 JTAG requires the two LSBs of this value to be 01.
3500 By default, @code{-ircapture} and @code{-irmask} are set
3501 up to verify that two-bit value. You may provide
3502 additional bits, if you know them, or indicate that
3503 a TAP doesn't conform to the JTAG specification.
3504 @item @code{-irmask} @var{NUMBER}
3505 @*A mask used with @code{-ircapture}
3506 to verify that instruction scans work correctly.
3507 Such scans are not used by OpenOCD except to verify that
3508 there seems to be no problems with JTAG scan chain operations.
3509 @end itemize
3510 @end deffn
3512 @section Other TAP commands
3514 @deffn Command {jtag cget} dotted.name @option{-event} name
3515 @deffnx Command {jtag configure} dotted.name @option{-event} name string
3516 At this writing this TAP attribute
3517 mechanism is used only for event handling.
3518 (It is not a direct analogue of the @code{cget}/@code{configure}
3519 mechanism for debugger targets.)
3520 See the next section for information about the available events.
3522 The @code{configure} subcommand assigns an event handler,
3523 a TCL string which is evaluated when the event is triggered.
3524 The @code{cget} subcommand returns that handler.
3525 @end deffn
3527 @anchor{TAP Events}
3528 @section TAP Events
3529 @cindex events
3530 @cindex TAP events
3532 OpenOCD includes two event mechanisms.
3533 The one presented here applies to all JTAG TAPs.
3534 The other applies to debugger targets,
3535 which are associated with certain TAPs.
3537 The TAP events currently defined are:
3539 @itemize @bullet
3540 @item @b{post-reset}
3541 @* The TAP has just completed a JTAG reset.
3542 The tap may still be in the JTAG @sc{reset} state.
3543 Handlers for these events might perform initialization sequences
3544 such as issuing TCK cycles, TMS sequences to ensure
3545 exit from the ARM SWD mode, and more.
3547 Because the scan chain has not yet been verified, handlers for these events
3548 @emph{should not issue commands which scan the JTAG IR or DR registers}
3549 of any particular target.
3550 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3551 @item @b{setup}
3552 @* The scan chain has been reset and verified.
3553 This handler may enable TAPs as needed.
3554 @item @b{tap-disable}
3555 @* The TAP needs to be disabled. This handler should
3556 implement @command{jtag tapdisable}
3557 by issuing the relevant JTAG commands.
3558 @item @b{tap-enable}
3559 @* The TAP needs to be enabled. This handler should
3560 implement @command{jtag tapenable}
3561 by issuing the relevant JTAG commands.
3562 @end itemize
3564 If you need some action after each JTAG reset, which isn't actually
3565 specific to any TAP (since you can't yet trust the scan chain's
3566 contents to be accurate), you might:
3568 @example
3569 jtag configure CHIP.jrc -event post-reset @{
3570 echo "JTAG Reset done"
3571 ... non-scan jtag operations to be done after reset
3572 @}
3573 @end example
3576 @anchor{Enabling and Disabling TAPs}
3577 @section Enabling and Disabling TAPs
3578 @cindex JTAG Route Controller
3579 @cindex jrc
3581 In some systems, a @dfn{JTAG Route Controller} (JRC)
3582 is used to enable and/or disable specific JTAG TAPs.
3583 Many ARM based chips from Texas Instruments include
3584 an ``ICEpick'' module, which is a JRC.
3585 Such chips include DaVinci and OMAP3 processors.
3587 A given TAP may not be visible until the JRC has been
3588 told to link it into the scan chain; and if the JRC
3589 has been told to unlink that TAP, it will no longer
3590 be visible.
3591 Such routers address problems that JTAG ``bypass mode''
3592 ignores, such as:
3594 @itemize
3595 @item The scan chain can only go as fast as its slowest TAP.
3596 @item Having many TAPs slows instruction scans, since all
3597 TAPs receive new instructions.
3598 @item TAPs in the scan chain must be powered up, which wastes
3599 power and prevents debugging some power management mechanisms.
3600 @end itemize
3602 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3603 as implied by the existence of JTAG routers.
3604 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3605 does include a kind of JTAG router functionality.
3607 @c (a) currently the event handlers don't seem to be able to
3608 @c fail in a way that could lead to no-change-of-state.
3610 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3611 shown below, and is implemented using TAP event handlers.
3612 So for example, when defining a TAP for a CPU connected to
3613 a JTAG router, your @file{target.cfg} file
3614 should define TAP event handlers using
3615 code that looks something like this:
3617 @example
3618 jtag configure CHIP.cpu -event tap-enable @{
3619 ... jtag operations using CHIP.jrc
3620 @}
3621 jtag configure CHIP.cpu -event tap-disable @{
3622 ... jtag operations using CHIP.jrc
3623 @}
3624 @end example
3626 Then you might want that CPU's TAP enabled almost all the time:
3628 @example
3629 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3630 @end example
3632 Note how that particular setup event handler declaration
3633 uses quotes to evaluate @code{$CHIP} when the event is configured.
3634 Using brackets @{ @} would cause it to be evaluated later,
3635 at runtime, when it might have a different value.
3637 @deffn Command {jtag tapdisable} dotted.name
3638 If necessary, disables the tap
3639 by sending it a @option{tap-disable} event.
3640 Returns the string "1" if the tap
3641 specified by @var{dotted.name} is enabled,
3642 and "0" if it is disabled.
3643 @end deffn
3645 @deffn Command {jtag tapenable} dotted.name
3646 If necessary, enables the tap
3647 by sending it a @option{tap-enable} event.
3648 Returns the string "1" if the tap
3649 specified by @var{dotted.name} is enabled,
3650 and "0" if it is disabled.
3651 @end deffn
3653 @deffn Command {jtag tapisenabled} dotted.name
3654 Returns the string "1" if the tap
3655 specified by @var{dotted.name} is enabled,
3656 and "0" if it is disabled.
3658 @quotation Note
3659 Humans will find the @command{scan_chain} command more helpful
3660 for querying the state of the JTAG taps.
3661 @end quotation
3662 @end deffn
3664 @anchor{Autoprobing}
3665 @section Autoprobing
3666 @cindex autoprobe
3667 @cindex JTAG autoprobe
3669 TAP configuration is the first thing that needs to be done
3670 after interface and reset configuration. Sometimes it's
3671 hard finding out what TAPs exist, or how they are identified.
3672 Vendor documentation is not always easy to find and use.
3674 To help you get past such problems, OpenOCD has a limited
3675 @emph{autoprobing} ability to look at the scan chain, doing
3676 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3677 To use this mechanism, start the OpenOCD server with only data
3678 that configures your JTAG interface, and arranges to come up
3679 with a slow clock (many devices don't support fast JTAG clocks
3680 right when they come out of reset).
3682 For example, your @file{openocd.cfg} file might have:
3684 @example
3685 source [find interface/olimex-arm-usb-tiny-h.cfg]
3686 reset_config trst_and_srst
3687 jtag_rclk 8
3688 @end example
3690 When you start the server without any TAPs configured, it will
3691 attempt to autoconfigure the TAPs. There are two parts to this:
3693 @enumerate
3694 @item @emph{TAP discovery} ...
3695 After a JTAG reset (sometimes a system reset may be needed too),
3696 each TAP's data registers will hold the contents of either the
3697 IDCODE or BYPASS register.
3698 If JTAG communication is working, OpenOCD will see each TAP,
3699 and report what @option{-expected-id} to use with it.
3700 @item @emph{IR Length discovery} ...
3701 Unfortunately JTAG does not provide a reliable way to find out
3702 the value of the @option{-irlen} parameter to use with a TAP
3703 that is discovered.
3704 If OpenOCD can discover the length of a TAP's instruction
3705 register, it will report it.
3706 Otherwise you may need to consult vendor documentation, such
3707 as chip data sheets or BSDL files.
3708 @end enumerate
3710 In many cases your board will have a simple scan chain with just
3711 a single device. Here's what OpenOCD reported with one board
3712 that's a bit more complex:
3714 @example
3715 clock speed 8 kHz
3716 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3717 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3718 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3719 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3720 AUTO auto0.tap - use "... -irlen 4"
3721 AUTO auto1.tap - use "... -irlen 4"
3722 AUTO auto2.tap - use "... -irlen 6"
3723 no gdb ports allocated as no target has been specified
3724 @end example
3726 Given that information, you should be able to either find some existing
3727 config files to use, or create your own. If you create your own, you
3728 would configure from the bottom up: first a @file{target.cfg} file
3729 with these TAPs, any targets associated with them, and any on-chip
3730 resources; then a @file{board.cfg} with off-chip resources, clocking,
3731 and so forth.
3733 @node CPU Configuration
3734 @chapter CPU Configuration
3735 @cindex GDB target
3737 This chapter discusses how to set up GDB debug targets for CPUs.
3738 You can also access these targets without GDB
3739 (@pxref{Architecture and Core Commands},
3740 and @ref{Target State handling}) and
3741 through various kinds of NAND and NOR flash commands.
3742 If you have multiple CPUs you can have multiple such targets.
3744 We'll start by looking at how to examine the targets you have,
3745 then look at how to add one more target and how to configure it.
3747 @section Target List
3748 @cindex target, current
3749 @cindex target, list
3751 All targets that have been set up are part of a list,
3752 where each member has a name.
3753 That name should normally be the same as the TAP name.
3754 You can display the list with the @command{targets}
3755 (plural!) command.
3756 This display often has only one CPU; here's what it might
3757 look like with more than one:
3758 @verbatim
3759 TargetName Type Endian TapName State
3760 -- ------------------ ---------- ------ ------------------ ------------
3761 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
3762 1 MyTarget cortex_m3 little mychip.foo tap-disabled
3763 @end verbatim
3765 One member of that list is the @dfn{current target}, which
3766 is implicitly referenced by many commands.
3767 It's the one marked with a @code{*} near the target name.
3768 In particular, memory addresses often refer to the address
3769 space seen by that current target.
3770 Commands like @command{mdw} (memory display words)
3771 and @command{flash erase_address} (erase NOR flash blocks)
3772 are examples; and there are many more.
3774 Several commands let you examine the list of targets:
3776 @deffn Command {target count}
3777 @emph{Note: target numbers are deprecated; don't use them.
3778 They will be removed shortly after August 2010, including this command.
3779 Iterate target using @command{target names}, not by counting.}
3781 Returns the number of targets, @math{N}.
3782 The highest numbered target is @math{N - 1}.
3783 @example
3784 set c [target count]
3785 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
3786 # Assuming you have created this function
3787 print_target_details $x
3788 @}
3789 @end example
3790 @end deffn
3792 @deffn Command {target current}
3793 Returns the name of the current target.
3794 @end deffn
3796 @deffn Command {target names}
3797 Lists the names of all current targets in the list.
3798 @example
3799 foreach t [target names] @{
3800 puts [format "Target: %s\n" $t]
3801 @}
3802 @end example
3803 @end deffn
3805 @deffn Command {target number} number
3806 @emph{Note: target numbers are deprecated; don't use them.
3807 They will be removed shortly after August 2010, including this command.}
3809 The list of targets is numbered starting at zero.
3810 This command returns the name of the target at index @var{number}.
3811 @example
3812 set thename [target number $x]
3813 puts [format "Target %d is: %s\n" $x $thename]
3814 @end example
3815 @end deffn
3817 @c yep, "target list" would have been better.
3818 @c plus maybe "target setdefault".
3820 @deffn Command targets [name]
3821 @emph{Note: the name of this command is plural. Other target
3822 command names are singular.}
3824 With no parameter, this command displays a table of all known
3825 targets in a user friendly form.
3827 With a parameter, this command sets the current target to
3828 the given target with the given @var{name}; this is
3829 only relevant on boards which have more than one target.
3830 @end deffn
3832 @section Target CPU Types and Variants
3833 @cindex target type
3834 @cindex CPU type
3835 @cindex CPU variant
3837 Each target has a @dfn{CPU type}, as shown in the output of
3838 the @command{targets} command. You need to specify that type
3839 when calling @command{target create}.
3840 The CPU type indicates more than just the instruction set.
3841 It also indicates how that instruction set is implemented,
3842 what kind of debug support it integrates,
3843 whether it has an MMU (and if so, what kind),
3844 what core-specific commands may be available
3845 (@pxref{Architecture and Core Commands}),
3846 and more.
3848 For some CPU types, OpenOCD also defines @dfn{variants} which
3849 indicate differences that affect their handling.
3850 For example, a particular implementation bug might need to be
3851 worked around in some chip versions.
3853 It's easy to see what target types are supported,
3854 since there's a command to list them.
3855 However, there is currently no way to list what target variants
3856 are supported (other than by reading the OpenOCD source code).
3858 @anchor{target types}
3859 @deffn Command {target types}
3860 Lists all supported target types.
3861 At this writing, the supported CPU types and variants are:
3863 @itemize @bullet
3864 @item @code{arm11} -- this is a generation of ARMv6 cores
3865 @item @code{arm720t} -- this is an ARMv4 core with an MMU
3866 @item @code{arm7tdmi} -- this is an ARMv4 core
3867 @item @code{arm920t} -- this is an ARMv4 core with an MMU
3868 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
3869 @item @code{arm966e} -- this is an ARMv5 core
3870 @item @code{arm9tdmi} -- this is an ARMv4 core
3871 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
3872 (Support for this is preliminary and incomplete.)
3873 @item @code{cortex_a8} -- this is an ARMv7 core with an MMU
3874 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
3875 compact Thumb2 instruction set.
3876 @item @code{dragonite} -- resembles arm966e
3877 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
3878 (Support for this is still incomplete.)
3879 @item @code{fa526} -- resembles arm920 (w/o Thumb)
3880 @item @code{feroceon} -- resembles arm926
3881 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
3882 @item @code{xscale} -- this is actually an architecture,
3883 not a CPU type. It is based on the ARMv5 architecture.
3884 There are several variants defined:
3885 @itemize @minus
3886 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
3887 @code{pxa27x} ... instruction register length is 7 bits
3888 @item @code{pxa250}, @code{pxa255},
3889 @code{pxa26x} ... instruction register length is 5 bits
3890 @item @code{pxa3xx} ... instruction register length is 11 bits
3891 @end itemize
3892 @end itemize
3893 @end deffn
3895 To avoid being confused by the variety of ARM based cores, remember
3896 this key point: @emph{ARM is a technology licencing company}.
3897 (See: @url{http://www.arm.com}.)
3898 The CPU name used by OpenOCD will reflect the CPU design that was
3899 licenced, not a vendor brand which incorporates that design.
3900 Name prefixes like arm7, arm9, arm11, and cortex
3901 reflect design generations;
3902 while names like ARMv4, ARMv5, ARMv6, and ARMv7
3903 reflect an architecture version implemented by a CPU design.
3905 @anchor{Target Configuration}
3906 @section Target Configuration
3908 Before creating a ``target'', you must have added its TAP to the scan chain.
3909 When you've added that TAP, you will have a @code{dotted.name}
3910 which is used to set up the CPU support.
3911 The chip-specific configuration file will normally configure its CPU(s)
3912 right after it adds all of the chip's TAPs to the scan chain.
3914 Although you can set up a target in one step, it's often clearer if you
3915 use shorter commands and do it in two steps: create it, then configure
3916 optional parts.
3917 All operations on the target after it's created will use a new
3918 command, created as part of target creation.
3920 The two main things to configure after target creation are
3921 a work area, which usually has target-specific defaults even
3922 if the board setup code overrides them later;
3923 and event handlers (@pxref{Target Events}), which tend
3924 to be much more board-specific.
3925 The key steps you use might look something like this
3927 @example
3928 target create MyTarget cortex_m3 -chain-position mychip.cpu
3929 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
3930 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
3931 $MyTarget configure -event reset-init @{ myboard_reinit @}
3932 @end example
3934 You should specify a working area if you can; typically it uses some
3935 on-chip SRAM.
3936 Such a working area can speed up many things, including bulk
3937 writes to target memory;
3938 flash operations like checking to see if memory needs to be erased;
3939 GDB memory checksumming;
3940 and more.
3942 @quotation Warning
3943 On more complex chips, the work area can become
3944 inaccessible when application code
3945 (such as an operating system)
3946 enables or disables the MMU.
3947 For example, the particular MMU context used to acess the virtual
3948 address will probably matter ... and that context might not have
3949 easy access to other addresses needed.
3950 At this writing, OpenOCD doesn't have much MMU intelligence.
3951 @end quotation
3953 It's often very useful to define a @code{reset-init} event handler.
3954 For systems that are normally used with a boot loader,
3955 common tasks include updating clocks and initializing memory
3956 controllers.
3957 That may be needed to let you write the boot loader into flash,
3958 in order to ``de-brick'' your board; or to load programs into
3959 external DDR memory without having run the boot loader.
3961 @deffn Command {target create} target_name type configparams...
3962 This command creates a GDB debug target that refers to a specific JTAG tap.
3963 It enters that target into a list, and creates a new
3964 command (@command{@var{target_name}}) which is used for various
3965 purposes including additional configuration.
3967 @itemize @bullet
3968 @item @var{target_name} ... is the name of the debug target.
3969 By convention this should be the same as the @emph{dotted.name}
3970 of the TAP associated with this target, which must be specified here
3971 using the @code{-chain-position @var{dotted.name}} configparam.
3973 This name is also used to create the target object command,
3974 referred to here as @command{$target_name},
3975 and in other places the target needs to be identified.
3976 @item @var{type} ... specifies the target type. @xref{target types}.
3977 @item @var{configparams} ... all parameters accepted by
3978 @command{$target_name configure} are permitted.
3979 If the target is big-endian, set it here with @code{-endian big}.
3980 If the variant matters, set it here with @code{-variant}.
3982 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
3983 @end itemize
3984 @end deffn
3986 @deffn Command {$target_name configure} configparams...
3987 The options accepted by this command may also be
3988 specified as parameters to @command{target create}.
3989 Their values can later be queried one at a time by
3990 using the @command{$target_name cget} command.
3992 @emph{Warning:} changing some of these after setup is dangerous.
3993 For example, moving a target from one TAP to another;
3994 and changing its endianness or variant.
3996 @itemize @bullet
3998 @item @code{-chain-position} @var{dotted.name} -- names the TAP
3999 used to access this target.
4001 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4002 whether the CPU uses big or little endian conventions
4004 @item @code{-event} @var{event_name} @var{event_body} --
4005 @xref{Target Events}.
4006 Note that this updates a list of named event handlers.
4007 Calling this twice with two different event names assigns
4008 two different handlers, but calling it twice with the
4009 same event name assigns only one handler.
4011 @item @code{-variant} @var{name} -- specifies a variant of the target,
4012 which OpenOCD needs to know about.
4014 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4015 whether the work area gets backed up; by default,
4016 @emph{it is not backed up.}
4017 When possible, use a working_area that doesn't need to be backed up,
4018 since performing a backup slows down operations.
4019 For example, the beginning of an SRAM block is likely to
4020 be used by most build systems, but the end is often unused.
4022 @item @code{-work-area-size} @var{size} -- specify work are size,
4023 in bytes. The same size applies regardless of whether its physical
4024 or virtual address is being used.
4026 @item @code{-work-area-phys} @var{address} -- set the work area
4027 base @var{address} to be used when no MMU is active.
4029 @item @code{-work-area-virt} @var{address} -- set the work area
4030 base @var{address} to be used when an MMU is active.
4031 @emph{Do not specify a value for this except on targets with an MMU.}
4032 The value should normally correspond to a static mapping for the
4033 @code{-work-area-phys} address, set up by the current operating system.
4035 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4036 @var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}|
4037 @option{FreeRTOS}|@option{linux}.
4039 @end itemize
4040 @end deffn
4042 @section Other $target_name Commands
4043 @cindex object command
4045 The Tcl/Tk language has the concept of object commands,
4046 and OpenOCD adopts that same model for targets.
4048 A good Tk example is a on screen button.
4049 Once a button is created a button
4050 has a name (a path in Tk terms) and that name is useable as a first
4051 class command. For example in Tk, one can create a button and later
4052 configure it like this:
4054 @example
4055 # Create
4056 button .foobar -background red -command @{ foo @}
4057 # Modify
4058 .foobar configure -foreground blue
4059 # Query
4060 set x [.foobar cget -background]
4061 # Report
4062 puts [format "The button is %s" $x]
4063 @end example
4065 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4066 button, and its object commands are invoked the same way.
4068 @example
4069 str912.cpu mww 0x1234 0x42
4070 omap3530.cpu mww 0x5555 123
4071 @end example
4073 The commands supported by OpenOCD target objects are:
4075 @deffn Command {$target_name arp_examine}
4076 @deffnx Command {$target_name arp_halt}
4077 @deffnx Command {$target_name arp_poll}
4078 @deffnx Command {$target_name arp_reset}
4079 @deffnx Command {$target_name arp_waitstate}
4080 Internal OpenOCD scripts (most notably @file{startup.tcl})
4081 use these to deal with specific reset cases.
4082 They are not otherwise documented here.
4083 @end deffn
4085 @deffn Command {$target_name array2mem} arrayname width address count
4086 @deffnx Command {$target_name mem2array} arrayname width address count
4087 These provide an efficient script-oriented interface to memory.
4088 The @code{array2mem} primitive writes bytes, halfwords, or words;
4089 while @code{mem2array} reads them.
4090 In both cases, the TCL side uses an array, and
4091 the target side uses raw memory.
4093 The efficiency comes from enabling the use of
4094 bulk JTAG data transfer operations.
4095 The script orientation comes from working with data
4096 values that are packaged for use by TCL scripts;
4097 @command{mdw} type primitives only print data they retrieve,
4098 and neither store nor return those values.
4100 @itemize
4101 @item @var{arrayname} ... is the name of an array variable
4102 @item @var{width} ... is 8/16/32 - indicating the memory access size
4103 @item @var{address} ... is the target memory address
4104 @item @var{count} ... is the number of elements to process
4105 @end itemize
4106 @end deffn
4108 @deffn Command {$target_name cget} queryparm
4109 Each configuration parameter accepted by
4110 @command{$target_name configure}
4111 can be individually queried, to return its current value.
4112 The @var{queryparm} is a parameter name
4113 accepted by that command, such as @code{-work-area-phys}.
4114 There are a few special cases:
4116 @itemize @bullet
4117 @item @code{-event} @var{event_name} -- returns the handler for the
4118 event named @var{event_name}.
4119 This is a special case because setting a handler requires
4120 two parameters.
4121 @item @code{-type} -- returns the target type.
4122 This is a special case because this is set using
4123 @command{target create} and can't be changed
4124 using @command{$target_name configure}.
4125 @end itemize
4127 For example, if you wanted to summarize information about
4128 all the targets you might use something like this:
4130 @example
4131 foreach name [target names] @{
4132 set y [$name cget -endian]
4133 set z [$name cget -type]
4134 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4135 $x $name $y $z]
4136 @}
4137 @end example
4138 @end deffn
4140 @anchor{target curstate}
4141 @deffn Command {$target_name curstate}
4142 Displays the current target state:
4143 @code{debug-running},
4144 @code{halted},
4145 @code{reset},
4146 @code{running}, or @code{unknown}.
4147 (Also, @pxref{Event Polling}.)
4148 @end deffn
4150 @deffn Command {$target_name eventlist}
4151 Displays a table listing all event handlers
4152 currently associated with this target.
4153 @xref{Target Events}.
4154 @end deffn
4156 @deffn Command {$target_name invoke-event} event_name
4157 Invokes the handler for the event named @var{event_name}.
4158 (This is primarily intended for use by OpenOCD framework
4159 code, for example by the reset code in @file{startup.tcl}.)
4160 @end deffn
4162 @deffn Command {$target_name mdw} addr [count]
4163 @deffnx Command {$target_name mdh} addr [count]
4164 @deffnx Command {$target_name mdb} addr [count]
4165 Display contents of address @var{addr}, as
4166 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4167 or 8-bit bytes (@command{mdb}).
4168 If @var{count} is specified, displays that many units.
4169 (If you want to manipulate the data instead of displaying it,
4170 see the @code{mem2array} primitives.)
4171 @end deffn
4173 @deffn Command {$target_name mww} addr word
4174 @deffnx Command {$target_name mwh} addr halfword
4175 @deffnx Command {$target_name mwb} addr byte
4176 Writes the specified @var{word} (32 bits),
4177 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4178 at the specified address @var{addr}.
4179 @end deffn
4181 @anchor{Target Events}
4182 @section Target Events
4183 @cindex target events
4184 @cindex events
4185 At various times, certain things can happen, or you want them to happen.
4186 For example:
4187 @itemize @bullet
4188 @item What should happen when GDB connects? Should your target reset?
4189 @item When GDB tries to flash the target, do you need to enable the flash via a special command?