8e1d1a8f60614d51c9d70fbc74d128f100dd4cd7
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
11
12 @include version.texi
13
14 @copying
15
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
20
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009 David Brownell
27 @end itemize
28
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
38
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
45
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
50
51 @summarycontents
52 @contents
53
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
57
58 @insertcopying
59 @end ifnottex
60
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developers
64 * JTAG Hardware Dongles:: JTAG Hardware Dongles
65 * About JIM-Tcl:: About JIM-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Interface - Dongle Configuration:: Interface - Dongle Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * TFTP:: TFTP
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * Upgrading:: Deprecated/Removed Commands
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
88
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
95 @end menu
96
97 @node About
98 @unnumbered About
99 @cindex about
100
101 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
102 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
105 around the world.
106
107 @section What is OpenOCD?
108 @cindex TAP
109 @cindex JTAG
110
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
113 devices.
114
115 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
116 with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
117 A @dfn{TAP} is a ``Test Access Port'', a module which processes
118 special instructions and data. TAPs are daisy-chained within and
119 between chips and boards.
120
121 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
122 based, parallel port based, and other standalone boxes that run
123 OpenOCD internally. @xref{JTAG Hardware Dongles}.
124
125 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
126 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
127 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
128 debugged via the GDB protocol.
129
130 @b{Flash Programing:} Flash writing is supported for external CFI
131 compatible NOR flashes (Intel and AMD/Spansion command set) and several
132 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
133 STM32x). Preliminary support for various NAND flash controllers
134 (LPC3180, Orion, S3C24xx, more) controller is included.
135
136 @section OpenOCD Web Site
137
138 The OpenOCD web site provides the latest public news from the community:
139
140 @uref{http://openocd.berlios.de/web/}
141
142 @section Latest User's Guide:
143
144 The user's guide you are now reading may not be the latest one
145 available. A version for more recent code may be available.
146 Its HTML form is published irregularly at:
147
148 @uref{http://openocd.berlios.de/doc/html/index.html}
149
150 PDF form is likewise published at:
151
152 @uref{http://openocd.berlios.de/doc/pdf/openocd.pdf}
153
154 @section OpenOCD User's Forum
155
156 There is an OpenOCD forum (phpBB) hosted by SparkFun:
157
158 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
159
160
161 @node Developers
162 @chapter OpenOCD Developer Resources
163 @cindex developers
164
165 If you are interested in improving the state of OpenOCD's debugging and
166 testing support, new contributions will be welcome. Motivated developers
167 can produce new target, flash or interface drivers, improve the
168 documentation, as well as more conventional bug fixes and enhancements.
169
170 The resources in this chapter are available for developers wishing to explore
171 or expand the OpenOCD source code.
172
173 @section OpenOCD GIT Repository
174
175 During the 0.3.x release cycle, OpenOCD switched from Subversion to
176 a GIT repository hosted at SourceForge. The repository URL is:
177
178 @uref{git://openocd.git.sourceforge.net/gitroot/openocd/openocd}
179
180 You may prefer to use a mirror and the HTTP protocol:
181
182 @uref{http://repo.or.cz/r/openocd.git}
183
184 With standard GIT tools, use @command{git clone} to initialize
185 a local repository, and @command{git pull} to update it.
186 There are also gitweb pages letting you browse the repository
187 with a web browser, or download arbitrary snapshots without
188 needing a GIT client:
189
190 @uref{http://openocd.git.sourceforge.net/git/gitweb.cgi?p=openocd/openocd}
191
192 @uref{http://repo.or.cz/w/openocd.git}
193
194 The @file{README} file contains the instructions for building the project
195 from the repository or a snapshot.
196
197 Developers that want to contribute patches to the OpenOCD system are
198 @b{strongly} encouraged to work against mainline.
199 Patches created against older versions may require additional
200 work from their submitter in order to be updated for newer releases.
201
202 @section Doxygen Developer Manual
203
204 During the 0.2.x release cycle, the OpenOCD project began
205 providing a Doxygen reference manual. This document contains more
206 technical information about the software internals, development
207 processes, and similar documentation:
208
209 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
210
211 This document is a work-in-progress, but contributions would be welcome
212 to fill in the gaps. All of the source files are provided in-tree,
213 listed in the Doxyfile configuration in the top of the source tree.
214
215 @section OpenOCD Developer Mailing List
216
217 The OpenOCD Developer Mailing List provides the primary means of
218 communication between developers:
219
220 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
221
222 Discuss and submit patches to this list.
223 The @file{PATCHES} file contains basic information about how
224 to prepare patches.
225
226
227 @node JTAG Hardware Dongles
228 @chapter JTAG Hardware Dongles
229 @cindex dongles
230 @cindex FTDI
231 @cindex wiggler
232 @cindex zy1000
233 @cindex printer port
234 @cindex USB Adapter
235 @cindex RTCK
236
237 Defined: @b{dongle}: A small device that plugins into a computer and serves as
238 an adapter .... [snip]
239
240 In the OpenOCD case, this generally refers to @b{a small adapater} one
241 attaches to your computer via USB or the Parallel Printer Port. The
242 execption being the Zylin ZY1000 which is a small box you attach via
243 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
244 require any drivers to be installed on the developer PC. It also has
245 a built in web interface. It supports RTCK/RCLK or adaptive clocking
246 and has a built in relay to power cycle targets remotely.
247
248
249 @section Choosing a Dongle
250
251 There are several things you should keep in mind when choosing a dongle.
252
253 @enumerate
254 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
255 Does your dongle support it? You might need a level converter.
256 @item @b{Pinout} What pinout does your target board use?
257 Does your dongle support it? You may be able to use jumper
258 wires, or an "octopus" connector, to convert pinouts.
259 @item @b{Connection} Does your computer have the USB, printer, or
260 Ethernet port needed?
261 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
262 @end enumerate
263
264 @section Stand alone Systems
265
266 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
267 dongle, but a standalone box. The ZY1000 has the advantage that it does
268 not require any drivers installed on the developer PC. It also has
269 a built in web interface. It supports RTCK/RCLK or adaptive clocking
270 and has a built in relay to power cycle targets remotely.
271
272 @section USB FT2232 Based
273
274 There are many USB JTAG dongles on the market, many of them are based
275 on a chip from ``Future Technology Devices International'' (FTDI)
276 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
277 See: @url{http://www.ftdichip.com} for more information.
278 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
279 chips are starting to become available in JTAG adapters.
280
281 @itemize @bullet
282 @item @b{usbjtag}
283 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
284 @item @b{jtagkey}
285 @* See: @url{http://www.amontec.com/jtagkey.shtml}
286 @item @b{jtagkey2}
287 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
288 @item @b{oocdlink}
289 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
290 @item @b{signalyzer}
291 @* See: @url{http://www.signalyzer.com}
292 @item @b{evb_lm3s811}
293 @* See: @url{http://www.luminarymicro.com} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
294 @item @b{luminary_icdi}
295 @* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug Interface (ICDI) Board, included in the Stellaris LM3S9B90 and LM3S9B92 Evaluation Kits.
296 @item @b{olimex-jtag}
297 @* See: @url{http://www.olimex.com}
298 @item @b{flyswatter}
299 @* See: @url{http://www.tincantools.com}
300 @item @b{turtelizer2}
301 @* See:
302 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
303 @url{http://www.ethernut.de}
304 @item @b{comstick}
305 @* Link: @url{http://www.hitex.com/index.php?id=383}
306 @item @b{stm32stick}
307 @* Link @url{http://www.hitex.com/stm32-stick}
308 @item @b{axm0432_jtag}
309 @* Axiom AXM-0432 Link @url{http://www.axman.com}
310 @item @b{cortino}
311 @* Link @url{http://www.hitex.com/index.php?id=cortino}
312 @end itemize
313
314 @section USB JLINK based
315 There are several OEM versions of the Segger @b{JLINK} adapter. It is
316 an example of a micro controller based JTAG adapter, it uses an
317 AT91SAM764 internally.
318
319 @itemize @bullet
320 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
321 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
322 @item @b{SEGGER JLINK}
323 @* Link: @url{http://www.segger.com/jlink.html}
324 @item @b{IAR J-Link}
325 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
326 @end itemize
327
328 @section USB RLINK based
329 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
330
331 @itemize @bullet
332 @item @b{Raisonance RLink}
333 @* Link: @url{http://www.raisonance.com/products/RLink.php}
334 @item @b{STM32 Primer}
335 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
336 @item @b{STM32 Primer2}
337 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
338 @end itemize
339
340 @section USB Other
341 @itemize @bullet
342 @item @b{USBprog}
343 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
344
345 @item @b{USB - Presto}
346 @* Link: @url{http://tools.asix.net/prg_presto.htm}
347
348 @item @b{Versaloon-Link}
349 @* Link: @url{http://www.simonqian.com/en/Versaloon}
350
351 @item @b{ARM-JTAG-EW}
352 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
353 @end itemize
354
355 @section IBM PC Parallel Printer Port Based
356
357 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
358 and the MacGraigor Wiggler. There are many clones and variations of
359 these on the market.
360
361 Note that parallel ports are becoming much less common, so if you
362 have the choice you should probably avoid these adapters in favor
363 of USB-based ones.
364
365 @itemize @bullet
366
367 @item @b{Wiggler} - There are many clones of this.
368 @* Link: @url{http://www.macraigor.com/wiggler.htm}
369
370 @item @b{DLC5} - From XILINX - There are many clones of this
371 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
372 produced, PDF schematics are easily found and it is easy to make.
373
374 @item @b{Amontec - JTAG Accelerator}
375 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
376
377 @item @b{GW16402}
378 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
379
380 @item @b{Wiggler2}
381 @*@uref{http://www.ccac.rwth-aachen.de/@/~michaels/@/index.php/hardware/@/armjtag,
382 Improved parallel-port wiggler-style JTAG adapter}
383
384 @item @b{Wiggler_ntrst_inverted}
385 @* Yet another variation - See the source code, src/jtag/parport.c
386
387 @item @b{old_amt_wiggler}
388 @* Unknown - probably not on the market today
389
390 @item @b{arm-jtag}
391 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
392
393 @item @b{chameleon}
394 @* Link: @url{http://www.amontec.com/chameleon.shtml}
395
396 @item @b{Triton}
397 @* Unknown.
398
399 @item @b{Lattice}
400 @* ispDownload from Lattice Semiconductor
401 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
402
403 @item @b{flashlink}
404 @* From ST Microsystems;
405 @uref{http://www.st.com/stonline/@/products/literature/um/7889.pdf,
406 FlashLINK JTAG programing cable for PSD and uPSD}
407
408 @end itemize
409
410 @section Other...
411 @itemize @bullet
412
413 @item @b{ep93xx}
414 @* An EP93xx based Linux machine using the GPIO pins directly.
415
416 @item @b{at91rm9200}
417 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
418
419 @end itemize
420
421 @node About JIM-Tcl
422 @chapter About JIM-Tcl
423 @cindex JIM Tcl
424 @cindex tcl
425
426 OpenOCD includes a small ``Tcl Interpreter'' known as JIM-Tcl.
427 This programming language provides a simple and extensible
428 command interpreter.
429
430 All commands presented in this Guide are extensions to JIM-Tcl.
431 You can use them as simple commands, without needing to learn
432 much of anything about Tcl.
433 Alternatively, can write Tcl programs with them.
434
435 You can learn more about JIM at its website, @url{http://jim.berlios.de}.
436
437 @itemize @bullet
438 @item @b{JIM vs. Tcl}
439 @* JIM-TCL is a stripped down version of the well known Tcl language,
440 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
441 fewer features. JIM-Tcl is a single .C file and a single .H file and
442 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
443 4.2 MB .zip file containing 1540 files.
444
445 @item @b{Missing Features}
446 @* Our practice has been: Add/clone the real Tcl feature if/when
447 needed. We welcome JIM Tcl improvements, not bloat.
448
449 @item @b{Scripts}
450 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
451 command interpreter today is a mixture of (newer)
452 JIM-Tcl commands, and (older) the orginal command interpreter.
453
454 @item @b{Commands}
455 @* At the OpenOCD telnet command line (or via the GDB mon command) one
456 can type a Tcl for() loop, set variables, etc.
457 Some of the commands documented in this guide are implemented
458 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
459
460 @item @b{Historical Note}
461 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
462
463 @item @b{Need a crash course in Tcl?}
464 @*@xref{Tcl Crash Course}.
465 @end itemize
466
467 @node Running
468 @chapter Running
469 @cindex command line options
470 @cindex logfile
471 @cindex directory search
472
473 The @option{--help} option shows:
474 @verbatim
475 bash$ openocd --help
476
477 --help | -h display this help
478 --version | -v display OpenOCD version
479 --file | -f use configuration file <name>
480 --search | -s dir to search for config files and scripts
481 --debug | -d set debug level <0-3>
482 --log_output | -l redirect log output to file <name>
483 --command | -c run <command>
484 --pipe | -p use pipes when talking to gdb
485 @end verbatim
486
487 By default OpenOCD reads the file configuration file @file{openocd.cfg}
488 in the current directory. To specify a different (or multiple)
489 configuration file, you can use the ``-f'' option. For example:
490
491 @example
492 openocd -f config1.cfg -f config2.cfg -f config3.cfg
493 @end example
494
495 OpenOCD starts by processing the configuration commands provided
496 on the command line or in @file{openocd.cfg}.
497 @xref{Configuration Stage}.
498 At the end of the configuration stage it verifies the JTAG scan
499 chain defined using those commands; your configuration should
500 ensure that this always succeeds.
501 Normally, OpenOCD then starts running as a daemon.
502 Alternatively, commands may be used to terminate the configuration
503 stage early, perform work (such as updating some flash memory),
504 and then shut down without acting as a daemon.
505
506 Once OpenOCD starts running as a daemon, it waits for connections from
507 clients (Telnet, GDB, Other) and processes the commands issued through
508 those channels.
509
510 If you are having problems, you can enable internal debug messages via
511 the ``-d'' option.
512
513 Also it is possible to interleave JIM-Tcl commands w/config scripts using the
514 @option{-c} command line switch.
515
516 To enable debug output (when reporting problems or working on OpenOCD
517 itself), use the @option{-d} command line switch. This sets the
518 @option{debug_level} to "3", outputting the most information,
519 including debug messages. The default setting is "2", outputting only
520 informational messages, warnings and errors. You can also change this
521 setting from within a telnet or gdb session using @command{debug_level
522 <n>} (@pxref{debug_level}).
523
524 You can redirect all output from the daemon to a file using the
525 @option{-l <logfile>} switch.
526
527 Search paths for config/script files can be added to OpenOCD by using
528 the @option{-s <search>} switch. The current directory and the OpenOCD
529 target library is in the search path by default.
530
531 For details on the @option{-p} option. @xref{Connecting to GDB}.
532
533 Note! OpenOCD will launch the GDB & telnet server even if it can not
534 establish a connection with the target. In general, it is possible for
535 the JTAG controller to be unresponsive until the target is set up
536 correctly via e.g. GDB monitor commands in a GDB init script.
537
538 @node OpenOCD Project Setup
539 @chapter OpenOCD Project Setup
540
541 To use OpenOCD with your development projects, you need to do more than
542 just connecting the JTAG adapter hardware (dongle) to your development board
543 and then starting the OpenOCD server.
544 You also need to configure that server so that it knows
545 about that adapter and board, and helps your work.
546
547 @section Hooking up the JTAG Adapter
548
549 Today's most common case is a dongle with a JTAG cable on one side
550 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
551 and a USB cable on the other.
552 Instead of USB, some cables use Ethernet;
553 older ones may use a PC parallel port, or even a serial port.
554
555 @enumerate
556 @item @emph{Start with power to your target board turned off},
557 and nothing connected to your JTAG adapter.
558 If you're particularly paranoid, unplug power to the board.
559 It's important to have the ground signal properly set up,
560 unless you are using a JTAG adapter which provides
561 galvanic isolation between the target board and the
562 debugging host.
563
564 @item @emph{Be sure it's the right kind of JTAG connector.}
565 If your dongle has a 20-pin ARM connector, you need some kind
566 of adapter (or octopus, see below) to hook it up to
567 boards using 14-pin or 10-pin connectors ... or to 20-pin
568 connectors which don't use ARM's pinout.
569
570 In the same vein, make sure the voltage levels are compatible.
571 Not all JTAG adapters have the level shifters needed to work
572 with 1.2 Volt boards.
573
574 @item @emph{Be certain the cable is properly oriented} or you might
575 damage your board. In most cases there are only two possible
576 ways to connect the cable.
577 Connect the JTAG cable from your adapter to the board.
578 Be sure it's firmly connected.
579
580 In the best case, the connector is keyed to physically
581 prevent you from inserting it wrong.
582 This is most often done using a slot on the board's male connector
583 housing, which must match a key on the JTAG cable's female connector.
584 If there's no housing, then you must look carefully and
585 make sure pin 1 on the cable hooks up to pin 1 on the board.
586 Ribbon cables are frequently all grey except for a wire on one
587 edge, which is red. The red wire is pin 1.
588
589 Sometimes dongles provide cables where one end is an ``octopus'' of
590 color coded single-wire connectors, instead of a connector block.
591 These are great when converting from one JTAG pinout to another,
592 but are tedious to set up.
593 Use these with connector pinout diagrams to help you match up the
594 adapter signals to the right board pins.
595
596 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
597 A USB, parallel, or serial port connector will go to the host which
598 you are using to run OpenOCD.
599 For Ethernet, consult the documentation and your network administrator.
600
601 For USB based JTAG adapters you have an easy sanity check at this point:
602 does the host operating system see the JTAG adapter?
603
604 @item @emph{Connect the adapter's power supply, if needed.}
605 This step is primarily for non-USB adapters,
606 but sometimes USB adapters need extra power.
607
608 @item @emph{Power up the target board.}
609 Unless you just let the magic smoke escape,
610 you're now ready to set up the OpenOCD server
611 so you can use JTAG to work with that board.
612
613 @end enumerate
614
615 Talk with the OpenOCD server using
616 telnet (@code{telnet localhost 4444} on many systems) or GDB.
617 @xref{GDB and OpenOCD}.
618
619 @section Project Directory
620
621 There are many ways you can configure OpenOCD and start it up.
622
623 A simple way to organize them all involves keeping a
624 single directory for your work with a given board.
625 When you start OpenOCD from that directory,
626 it searches there first for configuration files, scripts,
627 and for code you upload to the target board.
628 It is also the natural place to write files,
629 such as log files and data you download from the board.
630
631 @section Configuration Basics
632
633 There are two basic ways of configuring OpenOCD, and
634 a variety of ways you can mix them.
635 Think of the difference as just being how you start the server:
636
637 @itemize
638 @item Many @option{-f file} or @option{-c command} options on the command line
639 @item No options, but a @dfn{user config file}
640 in the current directory named @file{openocd.cfg}
641 @end itemize
642
643 Here is an example @file{openocd.cfg} file for a setup
644 using a Signalyzer FT2232-based JTAG adapter to talk to
645 a board with an Atmel AT91SAM7X256 microcontroller:
646
647 @example
648 source [find interface/signalyzer.cfg]
649
650 # GDB can also flash my flash!
651 gdb_memory_map enable
652 gdb_flash_program enable
653
654 source [find target/sam7x256.cfg]
655 @end example
656
657 Here is the command line equivalent of that configuration:
658
659 @example
660 openocd -f interface/signalyzer.cfg \
661 -c "gdb_memory_map enable" \
662 -c "gdb_flash_program enable" \
663 -f target/sam7x256.cfg
664 @end example
665
666 You could wrap such long command lines in shell scripts,
667 each supporting a different development task.
668 One might re-flash the board with a specific firmware version.
669 Another might set up a particular debugging or run-time environment.
670
671 @quotation Important
672 At this writing (October 2009) the command line method has
673 problems with how it treats variables.
674 For example, after @option{-c "set VAR value"}, or doing the
675 same in a script, the variable @var{VAR} will have no value
676 that can be tested in a later script.
677 @end quotation
678
679 Here we will focus on the simpler solution: one user config
680 file, including basic configuration plus any TCL procedures
681 to simplify your work.
682
683 @section User Config Files
684 @cindex config file, user
685 @cindex user config file
686 @cindex config file, overview
687
688 A user configuration file ties together all the parts of a project
689 in one place.
690 One of the following will match your situation best:
691
692 @itemize
693 @item Ideally almost everything comes from configuration files
694 provided by someone else.
695 For example, OpenOCD distributes a @file{scripts} directory
696 (probably in @file{/usr/share/openocd/scripts} on Linux).
697 Board and tool vendors can provide these too, as can individual
698 user sites; the @option{-s} command line option lets you say
699 where to find these files. (@xref{Running}.)
700 The AT91SAM7X256 example above works this way.
701
702 Three main types of non-user configuration file each have their
703 own subdirectory in the @file{scripts} directory:
704
705 @enumerate
706 @item @b{interface} -- one for each kind of JTAG adapter/dongle
707 @item @b{board} -- one for each different board
708 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
709 @end enumerate
710
711 Best case: include just two files, and they handle everything else.
712 The first is an interface config file.
713 The second is board-specific, and it sets up the JTAG TAPs and
714 their GDB targets (by deferring to some @file{target.cfg} file),
715 declares all flash memory, and leaves you nothing to do except
716 meet your deadline:
717
718 @example
719 source [find interface/olimex-jtag-tiny.cfg]
720 source [find board/csb337.cfg]
721 @end example
722
723 Boards with a single microcontroller often won't need more
724 than the target config file, as in the AT91SAM7X256 example.
725 That's because there is no external memory (flash, DDR RAM), and
726 the board differences are encapsulated by application code.
727
728 @item Maybe you don't know yet what your board looks like to JTAG.
729 Once you know the @file{interface.cfg} file to use, you may
730 need help from OpenOCD to discover what's on the board.
731 Once you find the TAPs, you can just search for appropriate
732 configuration files ... or write your own, from the bottom up.
733 @xref{Autoprobing}.
734
735 @item You can often reuse some standard config files but
736 need to write a few new ones, probably a @file{board.cfg} file.
737 You will be using commands described later in this User's Guide,
738 and working with the guidelines in the next chapter.
739
740 For example, there may be configuration files for your JTAG adapter
741 and target chip, but you need a new board-specific config file
742 giving access to your particular flash chips.
743 Or you might need to write another target chip configuration file
744 for a new chip built around the Cortex M3 core.
745
746 @quotation Note
747 When you write new configuration files, please submit
748 them for inclusion in the next OpenOCD release.
749 For example, a @file{board/newboard.cfg} file will help the
750 next users of that board, and a @file{target/newcpu.cfg}
751 will help support users of any board using that chip.
752 @end quotation
753
754 @item
755 You may may need to write some C code.
756 It may be as simple as a supporting a new ft2232 or parport
757 based dongle; a bit more involved, like a NAND or NOR flash
758 controller driver; or a big piece of work like supporting
759 a new chip architecture.
760 @end itemize
761
762 Reuse the existing config files when you can.
763 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
764 You may find a board configuration that's a good example to follow.
765
766 When you write config files, separate the reusable parts
767 (things every user of that interface, chip, or board needs)
768 from ones specific to your environment and debugging approach.
769 @itemize
770
771 @item
772 For example, a @code{gdb-attach} event handler that invokes
773 the @command{reset init} command will interfere with debugging
774 early boot code, which performs some of the same actions
775 that the @code{reset-init} event handler does.
776
777 @item
778 Likewise, the @command{arm9 vector_catch} command (or
779 @cindex vector_catch
780 its siblings @command{xscale vector_catch}
781 and @command{cortex_m3 vector_catch}) can be a timesaver
782 during some debug sessions, but don't make everyone use that either.
783 Keep those kinds of debugging aids in your user config file,
784 along with messaging and tracing setup.
785 (@xref{Software Debug Messages and Tracing}.)
786
787 @item
788 You might need to override some defaults.
789 For example, you might need to move, shrink, or back up the target's
790 work area if your application needs much SRAM.
791
792 @item
793 TCP/IP port configuration is another example of something which
794 is environment-specific, and should only appear in
795 a user config file. @xref{TCP/IP Ports}.
796 @end itemize
797
798 @section Project-Specific Utilities
799
800 A few project-specific utility
801 routines may well speed up your work.
802 Write them, and keep them in your project's user config file.
803
804 For example, if you are making a boot loader work on a
805 board, it's nice to be able to debug the ``after it's
806 loaded to RAM'' parts separately from the finicky early
807 code which sets up the DDR RAM controller and clocks.
808 A script like this one, or a more GDB-aware sibling,
809 may help:
810
811 @example
812 proc ramboot @{ @} @{
813 # Reset, running the target's "reset-init" scripts
814 # to initialize clocks and the DDR RAM controller.
815 # Leave the CPU halted.
816 reset init
817
818 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
819 load_image u-boot.bin 0x20000000
820
821 # Start running.
822 resume 0x20000000
823 @}
824 @end example
825
826 Then once that code is working you will need to make it
827 boot from NOR flash; a different utility would help.
828 Alternatively, some developers write to flash using GDB.
829 (You might use a similar script if you're working with a flash
830 based microcontroller application instead of a boot loader.)
831
832 @example
833 proc newboot @{ @} @{
834 # Reset, leaving the CPU halted. The "reset-init" event
835 # proc gives faster access to the CPU and to NOR flash;
836 # "reset halt" would be slower.
837 reset init
838
839 # Write standard version of U-Boot into the first two
840 # sectors of NOR flash ... the standard version should
841 # do the same lowlevel init as "reset-init".
842 flash protect 0 0 1 off
843 flash erase_sector 0 0 1
844 flash write_bank 0 u-boot.bin 0x0
845 flash protect 0 0 1 on
846
847 # Reboot from scratch using that new boot loader.
848 reset run
849 @}
850 @end example
851
852 You may need more complicated utility procedures when booting
853 from NAND.
854 That often involves an extra bootloader stage,
855 running from on-chip SRAM to perform DDR RAM setup so it can load
856 the main bootloader code (which won't fit into that SRAM).
857
858 Other helper scripts might be used to write production system images,
859 involving considerably more than just a three stage bootloader.
860
861 @section Target Software Changes
862
863 Sometimes you may want to make some small changes to the software
864 you're developing, to help make JTAG debugging work better.
865 For example, in C or assembly language code you might
866 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
867 handling issues like:
868
869 @itemize @bullet
870
871 @item @b{ARM Wait-For-Interrupt}...
872 Many ARM chips synchronize the JTAG clock using the core clock.
873 Low power states which stop that core clock thus prevent JTAG access.
874 Idle loops in tasking environments often enter those low power states
875 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
876
877 You may want to @emph{disable that instruction} in source code,
878 or otherwise prevent using that state,
879 to ensure you can get JTAG access at any time.
880 For example, the OpenOCD @command{halt} command may not
881 work for an idle processor otherwise.
882
883 @item @b{Delay after reset}...
884 Not all chips have good support for debugger access
885 right after reset; many LPC2xxx chips have issues here.
886 Similarly, applications that reconfigure pins used for
887 JTAG access as they start will also block debugger access.
888
889 To work with boards like this, @emph{enable a short delay loop}
890 the first thing after reset, before "real" startup activities.
891 For example, one second's delay is usually more than enough
892 time for a JTAG debugger to attach, so that
893 early code execution can be debugged
894 or firmware can be replaced.
895
896 @item @b{Debug Communications Channel (DCC)}...
897 Some processors include mechanisms to send messages over JTAG.
898 Many ARM cores support these, as do some cores from other vendors.
899 (OpenOCD may be able to use this DCC internally, speeding up some
900 operations like writing to memory.)
901
902 Your application may want to deliver various debugging messages
903 over JTAG, by @emph{linking with a small library of code}
904 provided with OpenOCD and using the utilities there to send
905 various kinds of message.
906 @xref{Software Debug Messages and Tracing}.
907
908 @end itemize
909
910 @node Config File Guidelines
911 @chapter Config File Guidelines
912
913 This chapter is aimed at any user who needs to write a config file,
914 including developers and integrators of OpenOCD and any user who
915 needs to get a new board working smoothly.
916 It provides guidelines for creating those files.
917
918 You should find the following directories under @t{$(INSTALLDIR)/scripts},
919 with files including the ones listed here.
920 Use them as-is where you can; or as models for new files.
921 @itemize @bullet
922 @item @file{interface} ...
923 think JTAG Dongle. Files that configure JTAG adapters go here.
924 @example
925 $ ls interface
926 arm-jtag-ew.cfg hitex_str9-comstick.cfg oocdlink.cfg
927 arm-usb-ocd.cfg icebear.cfg openocd-usb.cfg
928 at91rm9200.cfg jlink.cfg parport.cfg
929 axm0432.cfg jtagkey2.cfg parport_dlc5.cfg
930 calao-usb-a9260-c01.cfg jtagkey.cfg rlink.cfg
931 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg sheevaplug.cfg
932 calao-usb-a9260.cfg luminary.cfg signalyzer.cfg
933 chameleon.cfg luminary-icdi.cfg stm32-stick.cfg
934 cortino.cfg luminary-lm3s811.cfg turtelizer2.cfg
935 dummy.cfg olimex-arm-usb-ocd.cfg usbprog.cfg
936 flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
937 $
938 @end example
939 @item @file{board} ...
940 think Circuit Board, PWA, PCB, they go by many names. Board files
941 contain initialization items that are specific to a board.
942 They reuse target configuration files, since the same
943 microprocessor chips are used on many boards,
944 but support for external parts varies widely. For
945 example, the SDRAM initialization sequence for the board, or the type
946 of external flash and what address it uses. Any initialization
947 sequence to enable that external flash or SDRAM should be found in the
948 board file. Boards may also contain multiple targets: two CPUs; or
949 a CPU and an FPGA.
950 @example
951 $ ls board
952 arm_evaluator7t.cfg keil_mcb1700.cfg
953 at91rm9200-dk.cfg keil_mcb2140.cfg
954 at91sam9g20-ek.cfg linksys_nslu2.cfg
955 atmel_at91sam7s-ek.cfg logicpd_imx27.cfg
956 atmel_at91sam9260-ek.cfg mini2440.cfg
957 atmel_sam3u_ek.cfg olimex_LPC2378STK.cfg
958 crossbow_tech_imote2.cfg olimex_lpc_h2148.cfg
959 csb337.cfg olimex_sam7_ex256.cfg
960 csb732.cfg olimex_sam9_l9260.cfg
961 digi_connectcore_wi-9c.cfg olimex_stm32_h103.cfg
962 dm355evm.cfg omap2420_h4.cfg
963 dm365evm.cfg osk5912.cfg
964 dm6446evm.cfg pic-p32mx.cfg
965 eir.cfg propox_mmnet1001.cfg
966 ek-lm3s1968.cfg pxa255_sst.cfg
967 ek-lm3s3748.cfg sheevaplug.cfg
968 ek-lm3s811.cfg stm3210e_eval.cfg
969 ek-lm3s9b9x.cfg stm32f10x_128k_eval.cfg
970 hammer.cfg str910-eval.cfg
971 hitex_lpc2929.cfg telo.cfg
972 hitex_stm32-performancestick.cfg ti_beagleboard.cfg
973 hitex_str9-comstick.cfg topas910.cfg
974 iar_str912_sk.cfg topasa900.cfg
975 imx27ads.cfg unknown_at91sam9260.cfg
976 imx27lnst.cfg x300t.cfg
977 imx31pdk.cfg zy1000.cfg
978 $
979 @end example
980 @item @file{target} ...
981 think chip. The ``target'' directory represents the JTAG TAPs
982 on a chip
983 which OpenOCD should control, not a board. Two common types of targets
984 are ARM chips and FPGA or CPLD chips.
985 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
986 the target config file defines all of them.
987 @example
988 $ ls target
989 aduc702x.cfg imx27.cfg pxa255.cfg
990 ar71xx.cfg imx31.cfg pxa270.cfg
991 at91eb40a.cfg imx35.cfg readme.txt
992 at91r40008.cfg is5114.cfg sam7se512.cfg
993 at91rm9200.cfg ixp42x.cfg sam7x256.cfg
994 at91sam3u1c.cfg lm3s1968.cfg samsung_s3c2410.cfg
995 at91sam3u1e.cfg lm3s3748.cfg samsung_s3c2440.cfg
996 at91sam3u2c.cfg lm3s6965.cfg samsung_s3c2450.cfg
997 at91sam3u2e.cfg lm3s811.cfg samsung_s3c4510.cfg
998 at91sam3u4c.cfg lm3s9b9x.cfg samsung_s3c6410.cfg
999 at91sam3u4e.cfg lpc1768.cfg sharp_lh79532.cfg
1000 at91sam3uXX.cfg lpc2103.cfg smdk6410.cfg
1001 at91sam7sx.cfg lpc2124.cfg smp8634.cfg
1002 at91sam9260.cfg lpc2129.cfg stm32.cfg
1003 c100.cfg lpc2148.cfg str710.cfg
1004 c100config.tcl lpc2294.cfg str730.cfg
1005 c100helper.tcl lpc2378.cfg str750.cfg
1006 c100regs.tcl lpc2478.cfg str912.cfg
1007 cs351x.cfg lpc2900.cfg telo.cfg
1008 davinci.cfg mega128.cfg ti_dm355.cfg
1009 dragonite.cfg netx500.cfg ti_dm365.cfg
1010 epc9301.cfg omap2420.cfg ti_dm6446.cfg
1011 feroceon.cfg omap3530.cfg tmpa900.cfg
1012 icepick.cfg omap5912.cfg tmpa910.cfg
1013 imx21.cfg pic32mx.cfg xba_revA3.cfg
1014 $
1015 @end example
1016 @item @emph{more} ... browse for other library files which may be useful.
1017 For example, there are various generic and CPU-specific utilities.
1018 @end itemize
1019
1020 The @file{openocd.cfg} user config
1021 file may override features in any of the above files by
1022 setting variables before sourcing the target file, or by adding
1023 commands specific to their situation.
1024
1025 @section Interface Config Files
1026
1027 The user config file
1028 should be able to source one of these files with a command like this:
1029
1030 @example
1031 source [find interface/FOOBAR.cfg]
1032 @end example
1033
1034 A preconfigured interface file should exist for every interface in use
1035 today, that said, perhaps some interfaces have only been used by the
1036 sole developer who created it.
1037
1038 A separate chapter gives information about how to set these up.
1039 @xref{Interface - Dongle Configuration}.
1040 Read the OpenOCD source code if you have a new kind of hardware interface
1041 and need to provide a driver for it.
1042
1043 @section Board Config Files
1044 @cindex config file, board
1045 @cindex board config file
1046
1047 The user config file
1048 should be able to source one of these files with a command like this:
1049
1050 @example
1051 source [find board/FOOBAR.cfg]
1052 @end example
1053
1054 The point of a board config file is to package everything
1055 about a given board that user config files need to know.
1056 In summary the board files should contain (if present)
1057
1058 @enumerate
1059 @item One or more @command{source [target/...cfg]} statements
1060 @item NOR flash configuration (@pxref{NOR Configuration})
1061 @item NAND flash configuration (@pxref{NAND Configuration})
1062 @item Target @code{reset} handlers for SDRAM and I/O configuration
1063 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1064 @item All things that are not ``inside a chip''
1065 @end enumerate
1066
1067 Generic things inside target chips belong in target config files,
1068 not board config files. So for example a @code{reset-init} event
1069 handler should know board-specific oscillator and PLL parameters,
1070 which it passes to target-specific utility code.
1071
1072 The most complex task of a board config file is creating such a
1073 @code{reset-init} event handler.
1074 Define those handlers last, after you verify the rest of the board
1075 configuration works.
1076
1077 @subsection Communication Between Config files
1078
1079 In addition to target-specific utility code, another way that
1080 board and target config files communicate is by following a
1081 convention on how to use certain variables.
1082
1083 The full Tcl/Tk language supports ``namespaces'', but JIM-Tcl does not.
1084 Thus the rule we follow in OpenOCD is this: Variables that begin with
1085 a leading underscore are temporary in nature, and can be modified and
1086 used at will within a target configuration file.
1087
1088 Complex board config files can do the things like this,
1089 for a board with three chips:
1090
1091 @example
1092 # Chip #1: PXA270 for network side, big endian
1093 set CHIPNAME network
1094 set ENDIAN big
1095 source [find target/pxa270.cfg]
1096 # on return: _TARGETNAME = network.cpu
1097 # other commands can refer to the "network.cpu" target.
1098 $_TARGETNAME configure .... events for this CPU..
1099
1100 # Chip #2: PXA270 for video side, little endian
1101 set CHIPNAME video
1102 set ENDIAN little
1103 source [find target/pxa270.cfg]
1104 # on return: _TARGETNAME = video.cpu
1105 # other commands can refer to the "video.cpu" target.
1106 $_TARGETNAME configure .... events for this CPU..
1107
1108 # Chip #3: Xilinx FPGA for glue logic
1109 set CHIPNAME xilinx
1110 unset ENDIAN
1111 source [find target/spartan3.cfg]
1112 @end example
1113
1114 That example is oversimplified because it doesn't show any flash memory,
1115 or the @code{reset-init} event handlers to initialize external DRAM
1116 or (assuming it needs it) load a configuration into the FPGA.
1117 Such features are usually needed for low-level work with many boards,
1118 where ``low level'' implies that the board initialization software may
1119 not be working. (That's a common reason to need JTAG tools. Another
1120 is to enable working with microcontroller-based systems, which often
1121 have no debugging support except a JTAG connector.)
1122
1123 Target config files may also export utility functions to board and user
1124 config files. Such functions should use name prefixes, to help avoid
1125 naming collisions.
1126
1127 Board files could also accept input variables from user config files.
1128 For example, there might be a @code{J4_JUMPER} setting used to identify
1129 what kind of flash memory a development board is using, or how to set
1130 up other clocks and peripherals.
1131
1132 @subsection Variable Naming Convention
1133 @cindex variable names
1134
1135 Most boards have only one instance of a chip.
1136 However, it should be easy to create a board with more than
1137 one such chip (as shown above).
1138 Accordingly, we encourage these conventions for naming
1139 variables associated with different @file{target.cfg} files,
1140 to promote consistency and
1141 so that board files can override target defaults.
1142
1143 Inputs to target config files include:
1144
1145 @itemize @bullet
1146 @item @code{CHIPNAME} ...
1147 This gives a name to the overall chip, and is used as part of
1148 tap identifier dotted names.
1149 While the default is normally provided by the chip manufacturer,
1150 board files may need to distinguish between instances of a chip.
1151 @item @code{ENDIAN} ...
1152 By default @option{little} - although chips may hard-wire @option{big}.
1153 Chips that can't change endianness don't need to use this variable.
1154 @item @code{CPUTAPID} ...
1155 When OpenOCD examines the JTAG chain, it can be told verify the
1156 chips against the JTAG IDCODE register.
1157 The target file will hold one or more defaults, but sometimes the
1158 chip in a board will use a different ID (perhaps a newer revision).
1159 @end itemize
1160
1161 Outputs from target config files include:
1162
1163 @itemize @bullet
1164 @item @code{_TARGETNAME} ...
1165 By convention, this variable is created by the target configuration
1166 script. The board configuration file may make use of this variable to
1167 configure things like a ``reset init'' script, or other things
1168 specific to that board and that target.
1169 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1170 @code{_TARGETNAME1}, ... etc.
1171 @end itemize
1172
1173 @subsection The reset-init Event Handler
1174 @cindex event, reset-init
1175 @cindex reset-init handler
1176
1177 Board config files run in the OpenOCD configuration stage;
1178 they can't use TAPs or targets, since they haven't been
1179 fully set up yet.
1180 This means you can't write memory or access chip registers;
1181 you can't even verify that a flash chip is present.
1182 That's done later in event handlers, of which the target @code{reset-init}
1183 handler is one of the most important.
1184
1185 Except on microcontrollers, the basic job of @code{reset-init} event
1186 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1187 Microcontrollers rarely use boot loaders; they run right out of their
1188 on-chip flash and SRAM memory. But they may want to use one of these
1189 handlers too, if just for developer convenience.
1190
1191 @quotation Note
1192 Because this is so very board-specific, and chip-specific, no examples
1193 are included here.
1194 Instead, look at the board config files distributed with OpenOCD.
1195 If you have a boot loader, its source code will help; so will
1196 configuration files for other JTAG tools
1197 (@pxref{Translating Configuration Files}).
1198 @end quotation
1199
1200 Some of this code could probably be shared between different boards.
1201 For example, setting up a DRAM controller often doesn't differ by
1202 much except the bus width (16 bits or 32?) and memory timings, so a
1203 reusable TCL procedure loaded by the @file{target.cfg} file might take
1204 those as parameters.
1205 Similarly with oscillator, PLL, and clock setup;
1206 and disabling the watchdog.
1207 Structure the code cleanly, and provide comments to help
1208 the next developer doing such work.
1209 (@emph{You might be that next person} trying to reuse init code!)
1210
1211 The last thing normally done in a @code{reset-init} handler is probing
1212 whatever flash memory was configured. For most chips that needs to be
1213 done while the associated target is halted, either because JTAG memory
1214 access uses the CPU or to prevent conflicting CPU access.
1215
1216 @subsection JTAG Clock Rate
1217
1218 Before your @code{reset-init} handler has set up
1219 the PLLs and clocking, you may need to run with
1220 a low JTAG clock rate.
1221 @xref{JTAG Speed}.
1222 Then you'd increase that rate after your handler has
1223 made it possible to use the faster JTAG clock.
1224 When the initial low speed is board-specific, for example
1225 because it depends on a board-specific oscillator speed, then
1226 you should probably set it up in the board config file;
1227 if it's target-specific, it belongs in the target config file.
1228
1229 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1230 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1231 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1232 Consult chip documentation to determine the peak JTAG clock rate,
1233 which might be less than that.
1234
1235 @quotation Warning
1236 On most ARMs, JTAG clock detection is coupled to the core clock, so
1237 software using a @option{wait for interrupt} operation blocks JTAG access.
1238 Adaptive clocking provides a partial workaround, but a more complete
1239 solution just avoids using that instruction with JTAG debuggers.
1240 @end quotation
1241
1242 If the board supports adaptive clocking, use the @command{jtag_rclk}
1243 command, in case your board is used with JTAG adapter which
1244 also supports it. Otherwise use @command{jtag_khz}.
1245 Set the slow rate at the beginning of the reset sequence,
1246 and the faster rate as soon as the clocks are at full speed.
1247
1248 @section Target Config Files
1249 @cindex config file, target
1250 @cindex target config file
1251
1252 Board config files communicate with target config files using
1253 naming conventions as described above, and may source one or
1254 more target config files like this:
1255
1256 @example
1257 source [find target/FOOBAR.cfg]
1258 @end example
1259
1260 The point of a target config file is to package everything
1261 about a given chip that board config files need to know.
1262 In summary the target files should contain
1263
1264 @enumerate
1265 @item Set defaults
1266 @item Add TAPs to the scan chain
1267 @item Add CPU targets (includes GDB support)
1268 @item CPU/Chip/CPU-Core specific features
1269 @item On-Chip flash
1270 @end enumerate
1271
1272 As a rule of thumb, a target file sets up only one chip.
1273 For a microcontroller, that will often include a single TAP,
1274 which is a CPU needing a GDB target, and its on-chip flash.
1275
1276 More complex chips may include multiple TAPs, and the target
1277 config file may need to define them all before OpenOCD
1278 can talk to the chip.
1279 For example, some phone chips have JTAG scan chains that include
1280 an ARM core for operating system use, a DSP,
1281 another ARM core embedded in an image processing engine,
1282 and other processing engines.
1283
1284 @subsection Default Value Boiler Plate Code
1285
1286 All target configuration files should start with code like this,
1287 letting board config files express environment-specific
1288 differences in how things should be set up.
1289
1290 @example
1291 # Boards may override chip names, perhaps based on role,
1292 # but the default should match what the vendor uses
1293 if @{ [info exists CHIPNAME] @} @{
1294 set _CHIPNAME $CHIPNAME
1295 @} else @{
1296 set _CHIPNAME sam7x256
1297 @}
1298
1299 # ONLY use ENDIAN with targets that can change it.
1300 if @{ [info exists ENDIAN] @} @{
1301 set _ENDIAN $ENDIAN
1302 @} else @{
1303 set _ENDIAN little
1304 @}
1305
1306 # TAP identifiers may change as chips mature, for example with
1307 # new revision fields (the "3" here). Pick a good default; you
1308 # can pass several such identifiers to the "jtag newtap" command.
1309 if @{ [info exists CPUTAPID ] @} @{
1310 set _CPUTAPID $CPUTAPID
1311 @} else @{
1312 set _CPUTAPID 0x3f0f0f0f
1313 @}
1314 @end example
1315 @c but 0x3f0f0f0f is for an str73x part ...
1316
1317 @emph{Remember:} Board config files may include multiple target
1318 config files, or the same target file multiple times
1319 (changing at least @code{CHIPNAME}).
1320
1321 Likewise, the target configuration file should define
1322 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1323 use it later on when defining debug targets:
1324
1325 @example
1326 set _TARGETNAME $_CHIPNAME.cpu
1327 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1328 @end example
1329
1330 @subsection Adding TAPs to the Scan Chain
1331 After the ``defaults'' are set up,
1332 add the TAPs on each chip to the JTAG scan chain.
1333 @xref{TAP Declaration}, and the naming convention
1334 for taps.
1335
1336 In the simplest case the chip has only one TAP,
1337 probably for a CPU or FPGA.
1338 The config file for the Atmel AT91SAM7X256
1339 looks (in part) like this:
1340
1341 @example
1342 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1343 @end example
1344
1345 A board with two such at91sam7 chips would be able
1346 to source such a config file twice, with different
1347 values for @code{CHIPNAME}, so
1348 it adds a different TAP each time.
1349
1350 If there are nonzero @option{-expected-id} values,
1351 OpenOCD attempts to verify the actual tap id against those values.
1352 It will issue error messages if there is mismatch, which
1353 can help to pinpoint problems in OpenOCD configurations.
1354
1355 @example
1356 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1357 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1358 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1359 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1360 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1361 @end example
1362
1363 There are more complex examples too, with chips that have
1364 multiple TAPs. Ones worth looking at include:
1365
1366 @itemize
1367 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1368 plus a JRC to enable them
1369 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1370 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1371 is not currently used)
1372 @end itemize
1373
1374 @subsection Add CPU targets
1375
1376 After adding a TAP for a CPU, you should set it up so that
1377 GDB and other commands can use it.
1378 @xref{CPU Configuration}.
1379 For the at91sam7 example above, the command can look like this;
1380 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1381 to little endian, and this chip doesn't support changing that.
1382
1383 @example
1384 set _TARGETNAME $_CHIPNAME.cpu
1385 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1386 @end example
1387
1388 Work areas are small RAM areas associated with CPU targets.
1389 They are used by OpenOCD to speed up downloads,
1390 and to download small snippets of code to program flash chips.
1391 If the chip includes a form of ``on-chip-ram'' - and many do - define
1392 a work area if you can.
1393 Again using the at91sam7 as an example, this can look like:
1394
1395 @example
1396 $_TARGETNAME configure -work-area-phys 0x00200000 \
1397 -work-area-size 0x4000 -work-area-backup 0
1398 @end example
1399
1400 @subsection Chip Reset Setup
1401
1402 As a rule, you should put the @command{reset_config} command
1403 into the board file. Most things you think you know about a
1404 chip can be tweaked by the board.
1405
1406 Some chips have specific ways the TRST and SRST signals are
1407 managed. In the unusual case that these are @emph{chip specific}
1408 and can never be changed by board wiring, they could go here.
1409
1410 Some chips need special attention during reset handling if
1411 they're going to be used with JTAG.
1412 An example might be needing to send some commands right
1413 after the target's TAP has been reset, providing a
1414 @code{reset-deassert-post} event handler that writes a chip
1415 register to report that JTAG debugging is being done.
1416
1417 JTAG clocking constraints often change during reset, and in
1418 some cases target config files (rather than board config files)
1419 are the right places to handle some of those issues.
1420 For example, immediately after reset most chips run using a
1421 slower clock than they will use later.
1422 That means that after reset (and potentially, as OpenOCD
1423 first starts up) they must use a slower JTAG clock rate
1424 than they will use later.
1425 @xref{JTAG Speed}.
1426
1427 @quotation Important
1428 When you are debugging code that runs right after chip
1429 reset, getting these issues right is critical.
1430 In particular, if you see intermittent failures when
1431 OpenOCD verifies the scan chain after reset,
1432 look at how you are setting up JTAG clocking.
1433 @end quotation
1434
1435 @subsection ARM Core Specific Hacks
1436
1437 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1438 special high speed download features - enable it.
1439
1440 If present, the MMU, the MPU and the CACHE should be disabled.
1441
1442 Some ARM cores are equipped with trace support, which permits
1443 examination of the instruction and data bus activity. Trace
1444 activity is controlled through an ``Embedded Trace Module'' (ETM)
1445 on one of the core's scan chains. The ETM emits voluminous data
1446 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
1447 If you are using an external trace port,
1448 configure it in your board config file.
1449 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1450 configure it in your target config file.
1451
1452 @example
1453 etm config $_TARGETNAME 16 normal full etb
1454 etb config $_TARGETNAME $_CHIPNAME.etb
1455 @end example
1456
1457 @subsection Internal Flash Configuration
1458
1459 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1460
1461 @b{Never ever} in the ``target configuration file'' define any type of
1462 flash that is external to the chip. (For example a BOOT flash on
1463 Chip Select 0.) Such flash information goes in a board file - not
1464 the TARGET (chip) file.
1465
1466 Examples:
1467 @itemize @bullet
1468 @item at91sam7x256 - has 256K flash YES enable it.
1469 @item str912 - has flash internal YES enable it.
1470 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1471 @item pxa270 - again - CS0 flash - it goes in the board file.
1472 @end itemize
1473
1474 @anchor{Translating Configuration Files}
1475 @section Translating Configuration Files
1476 @cindex translation
1477 If you have a configuration file for another hardware debugger
1478 or toolset (Abatron, BDI2000, BDI3000, CCS,
1479 Lauterbach, Segger, Macraigor, etc.), translating
1480 it into OpenOCD syntax is often quite straightforward. The most tricky
1481 part of creating a configuration script is oftentimes the reset init
1482 sequence where e.g. PLLs, DRAM and the like is set up.
1483
1484 One trick that you can use when translating is to write small
1485 Tcl procedures to translate the syntax into OpenOCD syntax. This
1486 can avoid manual translation errors and make it easier to
1487 convert other scripts later on.
1488
1489 Example of transforming quirky arguments to a simple search and
1490 replace job:
1491
1492 @example
1493 # Lauterbach syntax(?)
1494 #
1495 # Data.Set c15:0x042f %long 0x40000015
1496 #
1497 # OpenOCD syntax when using procedure below.
1498 #
1499 # setc15 0x01 0x00050078
1500
1501 proc setc15 @{regs value@} @{
1502 global TARGETNAME
1503
1504 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
1505
1506 arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] \
1507 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
1508 [expr ($regs>>8)&0x7] $value
1509 @}
1510 @end example
1511
1512
1513
1514 @node Daemon Configuration
1515 @chapter Daemon Configuration
1516 @cindex initialization
1517 The commands here are commonly found in the openocd.cfg file and are
1518 used to specify what TCP/IP ports are used, and how GDB should be
1519 supported.
1520
1521 @anchor{Configuration Stage}
1522 @section Configuration Stage
1523 @cindex configuration stage
1524 @cindex config command
1525
1526 When the OpenOCD server process starts up, it enters a
1527 @emph{configuration stage} which is the only time that
1528 certain commands, @emph{configuration commands}, may be issued.
1529 In this manual, the definition of a configuration command is
1530 presented as a @emph{Config Command}, not as a @emph{Command}
1531 which may be issued interactively.
1532
1533 Those configuration commands include declaration of TAPs,
1534 flash banks,
1535 the interface used for JTAG communication,
1536 and other basic setup.
1537 The server must leave the configuration stage before it
1538 may access or activate TAPs.
1539 After it leaves this stage, configuration commands may no
1540 longer be issued.
1541
1542 @section Entering the Run Stage
1543
1544 The first thing OpenOCD does after leaving the configuration
1545 stage is to verify that it can talk to the scan chain
1546 (list of TAPs) which has been configured.
1547 It will warn if it doesn't find TAPs it expects to find,
1548 or finds TAPs that aren't supposed to be there.
1549 You should see no errors at this point.
1550 If you see errors, resolve them by correcting the
1551 commands you used to configure the server.
1552 Common errors include using an initial JTAG speed that's too
1553 fast, and not providing the right IDCODE values for the TAPs
1554 on the scan chain.
1555
1556 Once OpenOCD has entered the run stage, a number of commands
1557 become available.
1558 A number of these relate to the debug targets you may have declared.
1559 For example, the @command{mww} command will not be available until
1560 a target has been successfuly instantiated.
1561 If you want to use those commands, you may need to force
1562 entry to the run stage.
1563
1564 @deffn {Config Command} init
1565 This command terminates the configuration stage and
1566 enters the run stage. This helps when you need to have
1567 the startup scripts manage tasks such as resetting the target,
1568 programming flash, etc. To reset the CPU upon startup, add "init" and
1569 "reset" at the end of the config script or at the end of the OpenOCD
1570 command line using the @option{-c} command line switch.
1571
1572 If this command does not appear in any startup/configuration file
1573 OpenOCD executes the command for you after processing all
1574 configuration files and/or command line options.
1575
1576 @b{NOTE:} This command normally occurs at or near the end of your
1577 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1578 targets ready. For example: If your openocd.cfg file needs to
1579 read/write memory on your target, @command{init} must occur before
1580 the memory read/write commands. This includes @command{nand probe}.
1581 @end deffn
1582
1583 @deffn {Overridable Procedure} jtag_init
1584 This is invoked at server startup to verify that it can talk
1585 to the scan chain (list of TAPs) which has been configured.
1586
1587 The default implementation first tries @command{jtag arp_init},
1588 which uses only a lightweight JTAG reset before examining the
1589 scan chain.
1590 If that fails, it tries again, using a harder reset
1591 from the overridable procedure @command{init_reset}.
1592
1593 Implementations must have verified the JTAG scan chain before
1594 they return.
1595 This is done by calling @command{jtag arp_init}
1596 (or @command{jtag arp_init-reset}).
1597 @end deffn
1598
1599 @anchor{TCP/IP Ports}
1600 @section TCP/IP Ports
1601 @cindex TCP port
1602 @cindex server
1603 @cindex port
1604 @cindex security
1605 The OpenOCD server accepts remote commands in several syntaxes.
1606 Each syntax uses a different TCP/IP port, which you may specify
1607 only during configuration (before those ports are opened).
1608
1609 For reasons including security, you may wish to prevent remote
1610 access using one or more of these ports.
1611 In such cases, just specify the relevant port number as zero.
1612 If you disable all access through TCP/IP, you will need to
1613 use the command line @option{-pipe} option.
1614
1615 @deffn {Command} gdb_port (number)
1616 @cindex GDB server
1617 Specify or query the first port used for incoming GDB connections.
1618 The GDB port for the
1619 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1620 When not specified during the configuration stage,
1621 the port @var{number} defaults to 3333.
1622 When specified as zero, this port is not activated.
1623 @end deffn
1624
1625 @deffn {Command} tcl_port (number)
1626 Specify or query the port used for a simplified RPC
1627 connection that can be used by clients to issue TCL commands and get the
1628 output from the Tcl engine.
1629 Intended as a machine interface.
1630 When not specified during the configuration stage,
1631 the port @var{number} defaults to 6666.
1632 When specified as zero, this port is not activated.
1633 @end deffn
1634
1635 @deffn {Command} telnet_port (number)
1636 Specify or query the
1637 port on which to listen for incoming telnet connections.
1638 This port is intended for interaction with one human through TCL commands.
1639 When not specified during the configuration stage,
1640 the port @var{number} defaults to 4444.
1641 When specified as zero, this port is not activated.
1642 @end deffn
1643
1644 @anchor{GDB Configuration}
1645 @section GDB Configuration
1646 @cindex GDB
1647 @cindex GDB configuration
1648 You can reconfigure some GDB behaviors if needed.
1649 The ones listed here are static and global.
1650 @xref{Target Configuration}, about configuring individual targets.
1651 @xref{Target Events}, about configuring target-specific event handling.
1652
1653 @anchor{gdb_breakpoint_override}
1654 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
1655 Force breakpoint type for gdb @command{break} commands.
1656 This option supports GDB GUIs which don't
1657 distinguish hard versus soft breakpoints, if the default OpenOCD and
1658 GDB behaviour is not sufficient. GDB normally uses hardware
1659 breakpoints if the memory map has been set up for flash regions.
1660 @end deffn
1661
1662 @anchor{gdb_flash_program}
1663 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
1664 Set to @option{enable} to cause OpenOCD to program the flash memory when a
1665 vFlash packet is received.
1666 The default behaviour is @option{enable}.
1667 @end deffn
1668
1669 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
1670 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
1671 requested. GDB will then know when to set hardware breakpoints, and program flash
1672 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1673 for flash programming to work.
1674 Default behaviour is @option{enable}.
1675 @xref{gdb_flash_program}.
1676 @end deffn
1677
1678 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
1679 Specifies whether data aborts cause an error to be reported
1680 by GDB memory read packets.
1681 The default behaviour is @option{disable};
1682 use @option{enable} see these errors reported.
1683 @end deffn
1684
1685 @anchor{Event Polling}
1686 @section Event Polling
1687
1688 Hardware debuggers are parts of asynchronous systems,
1689 where significant events can happen at any time.
1690 The OpenOCD server needs to detect some of these events,
1691 so it can report them to through TCL command line
1692 or to GDB.
1693
1694 Examples of such events include:
1695
1696 @itemize
1697 @item One of the targets can stop running ... maybe it triggers
1698 a code breakpoint or data watchpoint, or halts itself.
1699 @item Messages may be sent over ``debug message'' channels ... many
1700 targets support such messages sent over JTAG,
1701 for receipt by the person debugging or tools.
1702 @item Loss of power ... some adapters can detect these events.
1703 @item Resets not issued through JTAG ... such reset sources
1704 can include button presses or other system hardware, sometimes
1705 including the target itself (perhaps through a watchdog).
1706 @item Debug instrumentation sometimes supports event triggering
1707 such as ``trace buffer full'' (so it can quickly be emptied)
1708 or other signals (to correlate with code behavior).
1709 @end itemize
1710
1711 None of those events are signaled through standard JTAG signals.
1712 However, most conventions for JTAG connectors include voltage
1713 level and system reset (SRST) signal detection.
1714 Some connectors also include instrumentation signals, which
1715 can imply events when those signals are inputs.
1716
1717 In general, OpenOCD needs to periodically check for those events,
1718 either by looking at the status of signals on the JTAG connector
1719 or by sending synchronous ``tell me your status'' JTAG requests
1720 to the various active targets.
1721 There is a command to manage and monitor that polling,
1722 which is normally done in the background.
1723
1724 @deffn Command poll [@option{on}|@option{off}]
1725 Poll the current target for its current state.
1726 (Also, @pxref{target curstate}.)
1727 If that target is in debug mode, architecture
1728 specific information about the current state is printed.
1729 An optional parameter
1730 allows background polling to be enabled and disabled.
1731
1732 You could use this from the TCL command shell, or
1733 from GDB using @command{monitor poll} command.
1734 @example
1735 > poll
1736 background polling: on
1737 target state: halted
1738 target halted in ARM state due to debug-request, \
1739 current mode: Supervisor
1740 cpsr: 0x800000d3 pc: 0x11081bfc
1741 MMU: disabled, D-Cache: disabled, I-Cache: enabled
1742 >
1743 @end example
1744 @end deffn
1745
1746 @node Interface - Dongle Configuration
1747 @chapter Interface - Dongle Configuration
1748 @cindex config file, interface
1749 @cindex interface config file
1750
1751 JTAG Adapters/Interfaces/Dongles are normally configured
1752 through commands in an interface configuration
1753 file which is sourced by your @file{openocd.cfg} file, or
1754 through a command line @option{-f interface/....cfg} option.
1755
1756 @example
1757 source [find interface/olimex-jtag-tiny.cfg]
1758 @end example
1759
1760 These commands tell
1761 OpenOCD what type of JTAG adapter you have, and how to talk to it.
1762 A few cases are so simple that you only need to say what driver to use:
1763
1764 @example
1765 # jlink interface
1766 interface jlink
1767 @end example
1768
1769 Most adapters need a bit more configuration than that.
1770
1771
1772 @section Interface Configuration
1773
1774 The interface command tells OpenOCD what type of JTAG dongle you are
1775 using. Depending on the type of dongle, you may need to have one or
1776 more additional commands.
1777
1778 @deffn {Config Command} {interface} name
1779 Use the interface driver @var{name} to connect to the
1780 target.
1781 @end deffn
1782
1783 @deffn Command {interface_list}
1784 List the interface drivers that have been built into
1785 the running copy of OpenOCD.
1786 @end deffn
1787
1788 @deffn Command {jtag interface}
1789 Returns the name of the interface driver being used.
1790 @end deffn
1791
1792 @section Interface Drivers
1793
1794 Each of the interface drivers listed here must be explicitly
1795 enabled when OpenOCD is configured, in order to be made
1796 available at run time.
1797
1798 @deffn {Interface Driver} {amt_jtagaccel}
1799 Amontec Chameleon in its JTAG Accelerator configuration,
1800 connected to a PC's EPP mode parallel port.
1801 This defines some driver-specific commands:
1802
1803 @deffn {Config Command} {parport_port} number
1804 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1805 the number of the @file{/dev/parport} device.
1806 @end deffn
1807
1808 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
1809 Displays status of RTCK option.
1810 Optionally sets that option first.
1811 @end deffn
1812 @end deffn
1813
1814 @deffn {Interface Driver} {arm-jtag-ew}
1815 Olimex ARM-JTAG-EW USB adapter
1816 This has one driver-specific command:
1817
1818 @deffn Command {armjtagew_info}
1819 Logs some status
1820 @end deffn
1821 @end deffn
1822
1823 @deffn {Interface Driver} {at91rm9200}
1824 Supports bitbanged JTAG from the local system,
1825 presuming that system is an Atmel AT91rm9200
1826 and a specific set of GPIOs is used.
1827 @c command: at91rm9200_device NAME
1828 @c chooses among list of bit configs ... only one option
1829 @end deffn
1830
1831 @deffn {Interface Driver} {dummy}
1832 A dummy software-only driver for debugging.
1833 @end deffn
1834
1835 @deffn {Interface Driver} {ep93xx}
1836 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1837 @end deffn
1838
1839 @deffn {Interface Driver} {ft2232}
1840 FTDI FT2232 (USB) based devices over one of the userspace libraries.
1841 These interfaces have several commands, used to configure the driver
1842 before initializing the JTAG scan chain:
1843
1844 @deffn {Config Command} {ft2232_device_desc} description
1845 Provides the USB device description (the @emph{iProduct string})
1846 of the FTDI FT2232 device. If not
1847 specified, the FTDI default value is used. This setting is only valid
1848 if compiled with FTD2XX support.
1849 @end deffn
1850
1851 @deffn {Config Command} {ft2232_serial} serial-number
1852 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
1853 in case the vendor provides unique IDs and more than one FT2232 device
1854 is connected to the host.
1855 If not specified, serial numbers are not considered.
1856 (Note that USB serial numbers can be arbitrary Unicode strings,
1857 and are not restricted to containing only decimal digits.)
1858 @end deffn
1859
1860 @deffn {Config Command} {ft2232_layout} name
1861 Each vendor's FT2232 device can use different GPIO signals
1862 to control output-enables, reset signals, and LEDs.
1863 Currently valid layout @var{name} values include:
1864 @itemize @minus
1865 @item @b{axm0432_jtag} Axiom AXM-0432
1866 @item @b{comstick} Hitex STR9 comstick
1867 @item @b{cortino} Hitex Cortino JTAG interface
1868 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
1869 either for the local Cortex-M3 (SRST only)
1870 or in a passthrough mode (neither SRST nor TRST)
1871 @item @b{luminary_icdi} Luminary In-Circuit Debug Interface (ICDI) Board
1872 @item @b{flyswatter} Tin Can Tools Flyswatter
1873 @item @b{icebear} ICEbear JTAG adapter from Section 5
1874 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
1875 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
1876 @item @b{m5960} American Microsystems M5960
1877 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
1878 @item @b{oocdlink} OOCDLink
1879 @c oocdlink ~= jtagkey_prototype_v1
1880 @item @b{sheevaplug} Marvell Sheevaplug development kit
1881 @item @b{signalyzer} Xverve Signalyzer
1882 @item @b{stm32stick} Hitex STM32 Performance Stick
1883 @item @b{turtelizer2} egnite Software turtelizer2
1884 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
1885 @end itemize
1886 @end deffn
1887
1888 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
1889 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1890 default values are used.
1891 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
1892 @example
1893 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1894 @end example
1895 @end deffn
1896
1897 @deffn {Config Command} {ft2232_latency} ms
1898 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1899 ft2232_read() fails to return the expected number of bytes. This can be caused by
1900 USB communication delays and has proved hard to reproduce and debug. Setting the
1901 FT2232 latency timer to a larger value increases delays for short USB packets but it
1902 also reduces the risk of timeouts before receiving the expected number of bytes.
1903 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1904 @end deffn
1905
1906 For example, the interface config file for a
1907 Turtelizer JTAG Adapter looks something like this:
1908
1909 @example
1910 interface ft2232
1911 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
1912 ft2232_layout turtelizer2
1913 ft2232_vid_pid 0x0403 0xbdc8
1914 @end example
1915 @end deffn
1916
1917 @deffn {Interface Driver} {gw16012}
1918 Gateworks GW16012 JTAG programmer.
1919 This has one driver-specific command:
1920
1921 @deffn {Config Command} {parport_port} number
1922 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1923 the number of the @file{/dev/parport} device.
1924 @end deffn
1925 @end deffn
1926
1927 @deffn {Interface Driver} {jlink}
1928 Segger jlink USB adapter
1929 @c command: jlink_info
1930 @c dumps status
1931 @c command: jlink_hw_jtag (2|3)
1932 @c sets version 2 or 3
1933 @end deffn
1934
1935 @deffn {Interface Driver} {parport}
1936 Supports PC parallel port bit-banging cables:
1937 Wigglers, PLD download cable, and more.
1938 These interfaces have several commands, used to configure the driver
1939 before initializing the JTAG scan chain:
1940
1941 @deffn {Config Command} {parport_cable} name
1942 The layout of the parallel port cable used to connect to the target.
1943 Currently valid cable @var{name} values include:
1944
1945 @itemize @minus
1946 @item @b{altium} Altium Universal JTAG cable.
1947 @item @b{arm-jtag} Same as original wiggler except SRST and
1948 TRST connections reversed and TRST is also inverted.
1949 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
1950 in configuration mode. This is only used to
1951 program the Chameleon itself, not a connected target.
1952 @item @b{dlc5} The Xilinx Parallel cable III.
1953 @item @b{flashlink} The ST Parallel cable.
1954 @item @b{lattice} Lattice ispDOWNLOAD Cable
1955 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
1956 some versions of
1957 Amontec's Chameleon Programmer. The new version available from
1958 the website uses the original Wiggler layout ('@var{wiggler}')
1959 @item @b{triton} The parallel port adapter found on the
1960 ``Karo Triton 1 Development Board''.
1961 This is also the layout used by the HollyGates design
1962 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1963 @item @b{wiggler} The original Wiggler layout, also supported by
1964 several clones, such as the Olimex ARM-JTAG
1965 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
1966 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
1967 @end itemize
1968 @end deffn
1969
1970 @deffn {Config Command} {parport_port} number
1971 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1972 the @file{/dev/parport} device
1973
1974 When using PPDEV to access the parallel port, use the number of the parallel port:
1975 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1976 you may encounter a problem.
1977 @end deffn
1978
1979 @deffn {Config Command} {parport_write_on_exit} (on|off)
1980 This will configure the parallel driver to write a known
1981 cable-specific value to the parallel interface on exiting OpenOCD
1982 @end deffn
1983
1984 For example, the interface configuration file for a
1985 classic ``Wiggler'' cable might look something like this:
1986
1987 @example
1988 interface parport
1989 parport_port 0xc8b8
1990 parport_cable wiggler
1991 @end example
1992 @end deffn
1993
1994 @deffn {Interface Driver} {presto}
1995 ASIX PRESTO USB JTAG programmer.
1996 @c command: presto_serial str
1997 @c sets serial number
1998 @end deffn
1999
2000 @deffn {Interface Driver} {rlink}
2001 Raisonance RLink USB adapter
2002 @end deffn
2003
2004 @deffn {Interface Driver} {usbprog}
2005 usbprog is a freely programmable USB adapter.
2006 @end deffn
2007
2008 @deffn {Interface Driver} {vsllink}
2009 vsllink is part of Versaloon which is a versatile USB programmer.
2010
2011 @quotation Note
2012 This defines quite a few driver-specific commands,
2013 which are not currently documented here.
2014 @end quotation
2015 @end deffn
2016
2017 @deffn {Interface Driver} {ZY1000}
2018 This is the Zylin ZY1000 JTAG debugger.
2019
2020 @quotation Note
2021 This defines some driver-specific commands,
2022 which are not currently documented here.
2023 @end quotation
2024
2025 @deffn Command power [@option{on}|@option{off}]
2026 Turn power switch to target on/off.
2027 No arguments: print status.
2028 @end deffn
2029
2030 @end deffn
2031
2032 @anchor{JTAG Speed}
2033 @section JTAG Speed
2034 JTAG clock setup is part of system setup.
2035 It @emph{does not belong with interface setup} since any interface
2036 only knows a few of the constraints for the JTAG clock speed.
2037 Sometimes the JTAG speed is
2038 changed during the target initialization process: (1) slow at
2039 reset, (2) program the CPU clocks, (3) run fast.
2040 Both the "slow" and "fast" clock rates are functions of the
2041 oscillators used, the chip, the board design, and sometimes
2042 power management software that may be active.
2043
2044 The speed used during reset, and the scan chain verification which
2045 follows reset, can be adjusted using a @code{reset-start}
2046 target event handler.
2047 It can then be reconfigured to a faster speed by a
2048 @code{reset-init} target event handler after it reprograms those
2049 CPU clocks, or manually (if something else, such as a boot loader,
2050 sets up those clocks).
2051 @xref{Target Events}.
2052 When the initial low JTAG speed is a chip characteristic, perhaps
2053 because of a required oscillator speed, provide such a handler
2054 in the target config file.
2055 When that speed is a function of a board-specific characteristic
2056 such as which speed oscillator is used, it belongs in the board
2057 config file instead.
2058 In both cases it's safest to also set the initial JTAG clock rate
2059 to that same slow speed, so that OpenOCD never starts up using a
2060 clock speed that's faster than the scan chain can support.
2061
2062 @example
2063 jtag_rclk 3000
2064 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
2065 @end example
2066
2067 If your system supports adaptive clocking (RTCK), configuring
2068 JTAG to use that is probably the most robust approach.
2069 However, it introduces delays to synchronize clocks; so it
2070 may not be the fastest solution.
2071
2072 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
2073 instead of @command{jtag_khz}.
2074
2075 @deffn {Command} jtag_khz max_speed_kHz
2076 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
2077 JTAG interfaces usually support a limited number of
2078 speeds. The speed actually used won't be faster
2079 than the speed specified.
2080
2081 Chip data sheets generally include a top JTAG clock rate.
2082 The actual rate is often a function of a CPU core clock,
2083 and is normally less than that peak rate.
2084 For example, most ARM cores accept at most one sixth of the CPU clock.
2085
2086 Speed 0 (khz) selects RTCK method.
2087 @xref{FAQ RTCK}.
2088 If your system uses RTCK, you won't need to change the
2089 JTAG clocking after setup.
2090 Not all interfaces, boards, or targets support ``rtck''.
2091 If the interface device can not
2092 support it, an error is returned when you try to use RTCK.
2093 @end deffn
2094
2095 @defun jtag_rclk fallback_speed_kHz
2096 @cindex adaptive clocking
2097 @cindex RTCK
2098 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
2099 If that fails (maybe the interface, board, or target doesn't
2100 support it), falls back to the specified frequency.
2101 @example
2102 # Fall back to 3mhz if RTCK is not supported
2103 jtag_rclk 3000
2104 @end example
2105 @end defun
2106
2107 @node Reset Configuration
2108 @chapter Reset Configuration
2109 @cindex Reset Configuration
2110
2111 Every system configuration may require a different reset
2112 configuration. This can also be quite confusing.
2113 Resets also interact with @var{reset-init} event handlers,
2114 which do things like setting up clocks and DRAM, and
2115 JTAG clock rates. (@xref{JTAG Speed}.)
2116 They can also interact with JTAG routers.
2117 Please see the various board files for examples.
2118
2119 @quotation Note
2120 To maintainers and integrators:
2121 Reset configuration touches several things at once.
2122 Normally the board configuration file
2123 should define it and assume that the JTAG adapter supports
2124 everything that's wired up to the board's JTAG connector.
2125
2126 However, the target configuration file could also make note
2127 of something the silicon vendor has done inside the chip,
2128 which will be true for most (or all) boards using that chip.
2129 And when the JTAG adapter doesn't support everything, the
2130 user configuration file will need to override parts of
2131 the reset configuration provided by other files.
2132 @end quotation
2133
2134 @section Types of Reset
2135
2136 There are many kinds of reset possible through JTAG, but
2137 they may not all work with a given board and adapter.
2138 That's part of why reset configuration can be error prone.
2139
2140 @itemize @bullet
2141 @item
2142 @emph{System Reset} ... the @emph{SRST} hardware signal
2143 resets all chips connected to the JTAG adapter, such as processors,
2144 power management chips, and I/O controllers. Normally resets triggered
2145 with this signal behave exactly like pressing a RESET button.
2146 @item
2147 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
2148 just the TAP controllers connected to the JTAG adapter.
2149 Such resets should not be visible to the rest of the system; resetting a
2150 device's the TAP controller just puts that controller into a known state.
2151 @item
2152 @emph{Emulation Reset} ... many devices can be reset through JTAG
2153 commands. These resets are often distinguishable from system
2154 resets, either explicitly (a "reset reason" register says so)
2155 or implicitly (not all parts of the chip get reset).
2156 @item
2157 @emph{Other Resets} ... system-on-chip devices often support
2158 several other types of reset.
2159 You may need to arrange that a watchdog timer stops
2160 while debugging, preventing a watchdog reset.
2161 There may be individual module resets.
2162 @end itemize
2163
2164 In the best case, OpenOCD can hold SRST, then reset
2165 the TAPs via TRST and send commands through JTAG to halt the
2166 CPU at the reset vector before the 1st instruction is executed.
2167 Then when it finally releases the SRST signal, the system is
2168 halted under debugger control before any code has executed.
2169 This is the behavior required to support the @command{reset halt}
2170 and @command{reset init} commands; after @command{reset init} a
2171 board-specific script might do things like setting up DRAM.
2172 (@xref{Reset Command}.)
2173
2174 @anchor{SRST and TRST Issues}
2175 @section SRST and TRST Issues
2176
2177 Because SRST and TRST are hardware signals, they can have a
2178 variety of system-specific constraints. Some of the most
2179 common issues are:
2180
2181 @itemize @bullet
2182
2183 @item @emph{Signal not available} ... Some boards don't wire
2184 SRST or TRST to the JTAG connector. Some JTAG adapters don't
2185 support such signals even if they are wired up.
2186 Use the @command{reset_config} @var{signals} options to say
2187 when either of those signals is not connected.
2188 When SRST is not available, your code might not be able to rely
2189 on controllers having been fully reset during code startup.
2190 Missing TRST is not a problem, since JTAG level resets can
2191 be triggered using with TMS signaling.
2192
2193 @item @emph{Signals shorted} ... Sometimes a chip, board, or
2194 adapter will connect SRST to TRST, instead of keeping them separate.
2195 Use the @command{reset_config} @var{combination} options to say
2196 when those signals aren't properly independent.
2197
2198 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
2199 delay circuit, reset supervisor, or on-chip features can extend
2200 the effect of a JTAG adapter's reset for some time after the adapter
2201 stops issuing the reset. For example, there may be chip or board
2202 requirements that all reset pulses last for at least a
2203 certain amount of time; and reset buttons commonly have
2204 hardware debouncing.
2205 Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
2206 commands to say when extra delays are needed.
2207
2208 @item @emph{Drive type} ... Reset lines often have a pullup
2209 resistor, letting the JTAG interface treat them as open-drain
2210 signals. But that's not a requirement, so the adapter may need
2211 to use push/pull output drivers.
2212 Also, with weak pullups it may be advisable to drive
2213 signals to both levels (push/pull) to minimize rise times.
2214 Use the @command{reset_config} @var{trst_type} and
2215 @var{srst_type} parameters to say how to drive reset signals.
2216
2217 @item @emph{Special initialization} ... Targets sometimes need
2218 special JTAG initialization sequences to handle chip-specific
2219 issues (not limited to errata).
2220 For example, certain JTAG commands might need to be issued while
2221 the system as a whole is in a reset state (SRST active)
2222 but the JTAG scan chain is usable (TRST inactive).
2223 Many systems treat combined assertion of SRST and TRST as a
2224 trigger for a harder reset than SRST alone.
2225 Such custom reset handling is discussed later in this chapter.
2226 @end itemize
2227
2228 There can also be other issues.
2229 Some devices don't fully conform to the JTAG specifications.
2230 Trivial system-specific differences are common, such as
2231 SRST and TRST using slightly different names.
2232 There are also vendors who distribute key JTAG documentation for
2233 their chips only to developers who have signed a Non-Disclosure
2234 Agreement (NDA).
2235
2236 Sometimes there are chip-specific extensions like a requirement to use
2237 the normally-optional TRST signal (precluding use of JTAG adapters which
2238 don't pass TRST through), or needing extra steps to complete a TAP reset.
2239
2240 In short, SRST and especially TRST handling may be very finicky,
2241 needing to cope with both architecture and board specific constraints.
2242
2243 @section Commands for Handling Resets
2244
2245 @deffn {Command} jtag_nsrst_assert_width milliseconds
2246 Minimum amount of time (in milliseconds) OpenOCD should wait
2247 after asserting nSRST (active-low system reset) before
2248 allowing it to be deasserted.
2249 @end deffn
2250
2251 @deffn {Command} jtag_nsrst_delay milliseconds
2252 How long (in milliseconds) OpenOCD should wait after deasserting
2253 nSRST (active-low system reset) before starting new JTAG operations.
2254 When a board has a reset button connected to SRST line it will
2255 probably have hardware debouncing, implying you should use this.
2256 @end deffn
2257
2258 @deffn {Command} jtag_ntrst_assert_width milliseconds
2259 Minimum amount of time (in milliseconds) OpenOCD should wait
2260 after asserting nTRST (active-low JTAG TAP reset) before
2261 allowing it to be deasserted.
2262 @end deffn
2263
2264 @deffn {Command} jtag_ntrst_delay milliseconds
2265 How long (in milliseconds) OpenOCD should wait after deasserting
2266 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
2267 @end deffn
2268
2269 @deffn {Command} reset_config mode_flag ...
2270 This command displays or modifies the reset configuration
2271 of your combination of JTAG board and target in target
2272 configuration scripts.
2273
2274 Information earlier in this section describes the kind of problems
2275 the command is intended to address (@pxref{SRST and TRST Issues}).
2276 As a rule this command belongs only in board config files,
2277 describing issues like @emph{board doesn't connect TRST};
2278 or in user config files, addressing limitations derived
2279 from a particular combination of interface and board.
2280 (An unlikely example would be using a TRST-only adapter
2281 with a board that only wires up SRST.)
2282
2283 The @var{mode_flag} options can be specified in any order, but only one
2284 of each type -- @var{signals}, @var{combination},
2285 @var{gates},
2286 @var{trst_type},
2287 and @var{srst_type} -- may be specified at a time.
2288 If you don't provide a new value for a given type, its previous
2289 value (perhaps the default) is unchanged.
2290 For example, this means that you don't need to say anything at all about
2291 TRST just to declare that if the JTAG adapter should want to drive SRST,
2292 it must explicitly be driven high (@option{srst_push_pull}).
2293
2294 @itemize
2295 @item
2296 @var{signals} can specify which of the reset signals are connected.
2297 For example, If the JTAG interface provides SRST, but the board doesn't
2298 connect that signal properly, then OpenOCD can't use it.
2299 Possible values are @option{none} (the default), @option{trst_only},
2300 @option{srst_only} and @option{trst_and_srst}.
2301
2302 @quotation Tip
2303 If your board provides SRST and/or TRST through the JTAG connector,
2304 you must declare that so those signals can be used.
2305 @end quotation
2306
2307 @item
2308 The @var{combination} is an optional value specifying broken reset
2309 signal implementations.
2310 The default behaviour if no option given is @option{separate},
2311 indicating everything behaves normally.
2312 @option{srst_pulls_trst} states that the
2313 test logic is reset together with the reset of the system (e.g. Philips
2314 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
2315 the system is reset together with the test logic (only hypothetical, I
2316 haven't seen hardware with such a bug, and can be worked around).
2317 @option{combined} implies both @option{srst_pulls_trst} and
2318 @option{trst_pulls_srst}.
2319
2320 @item
2321 The @var{gates} tokens control flags that describe some cases where
2322 JTAG may be unvailable during reset.
2323 @option{srst_gates_jtag} (default)
2324 indicates that asserting SRST gates the
2325 JTAG clock. This means that no communication can happen on JTAG
2326 while SRST is asserted.
2327 Its converse is @option{srst_nogate}, indicating that JTAG commands
2328 can safely be issued while SRST is active.
2329 @end itemize
2330
2331 The optional @var{trst_type} and @var{srst_type} parameters allow the
2332 driver mode of each reset line to be specified. These values only affect
2333 JTAG interfaces with support for different driver modes, like the Amontec
2334 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
2335 relevant signal (TRST or SRST) is not connected.
2336
2337 @itemize
2338 @item
2339 Possible @var{trst_type} driver modes for the test reset signal (TRST)
2340 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
2341 Most boards connect this signal to a pulldown, so the JTAG TAPs
2342 never leave reset unless they are hooked up to a JTAG adapter.
2343
2344 @item
2345 Possible @var{srst_type} driver modes for the system reset signal (SRST)
2346 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
2347 Most boards connect this signal to a pullup, and allow the
2348 signal to be pulled low by various events including system
2349 powerup and pressing a reset button.
2350 @end itemize
2351 @end deffn
2352
2353 @section Custom Reset Handling
2354 @cindex events
2355
2356 OpenOCD has several ways to help support the various reset
2357 mechanisms provided by chip and board vendors.
2358 The commands shown in the previous section give standard parameters.
2359 There are also @emph{event handlers} associated with TAPs or Targets.
2360 Those handlers are Tcl procedures you can provide, which are invoked
2361 at particular points in the reset sequence.
2362
2363 After configuring those mechanisms, you might still
2364 find your board doesn't start up or reset correctly.
2365 For example, maybe it needs a slightly different sequence
2366 of SRST and/or TRST manipulations, because of quirks that
2367 the @command{reset_config} mechanism doesn't address;
2368 or asserting both might trigger a stronger reset, which
2369 needs special attention.
2370
2371 Experiment with lower level operations, such as @command{jtag_reset}
2372 and the @command{jtag arp_*} operations shown here,
2373 to find a sequence of operations that works.
2374 @xref{JTAG Commands}.
2375 When you find a working sequence, it can be used to override
2376 @command{jtag_init}, which fires during OpenOCD startup
2377 (@pxref{Configuration Stage});
2378 or @command{init_reset}, which fires during reset processing.
2379
2380 You might also want to provide some project-specific reset
2381 schemes. For example, on a multi-target board the standard
2382 @command{reset} command would reset all targets, but you
2383 may need the ability to reset only one target at time and
2384 thus want to avoid using the board-wide SRST signal.
2385
2386 @deffn {Overridable Procedure} init_reset mode
2387 This is invoked near the beginning of the @command{reset} command,
2388 usually to provide as much of a cold (power-up) reset as practical.
2389 By default it is also invoked from @command{jtag_init} if
2390 the scan chain does not respond to pure JTAG operations.
2391 The @var{mode} parameter is the parameter given to the
2392 low level reset command (@option{halt},
2393 @option{init}, or @option{run}), @option{setup},
2394 or potentially some other value.
2395
2396 The default implementation just invokes @command{jtag arp_init-reset}.
2397 Replacements will normally build on low level JTAG
2398 operations such as @command{jtag_reset}.
2399 Operations here must not address individual TAPs
2400 (or their associated targets)
2401 until the JTAG scan chain has first been verified to work.
2402
2403 Implementations must have verified the JTAG scan chain before
2404 they return.
2405 This is done by calling @command{jtag arp_init}
2406 (or @command{jtag arp_init-reset}).
2407 @end deffn
2408
2409 @deffn Command {jtag arp_init}
2410 This validates the scan chain using just the four
2411 standard JTAG signals (TMS, TCK, TDI, TDO).
2412 It starts by issuing a JTAG-only reset.
2413 Then it performs checks to verify that the scan chain configuration
2414 matches the TAPs it can observe.
2415 Those checks include checking IDCODE values for each active TAP,
2416 and verifying the length of their instruction registers using
2417 TAP @code{-ircapture} and @code{-irmask} values.
2418 If these tests all pass, TAP @code{setup} events are
2419 issued to all TAPs with handlers for that event.
2420 @end deffn
2421
2422 @deffn Command {jtag arp_init-reset}
2423 This uses TRST and SRST to try resetting
2424 everything on the JTAG scan chain
2425 (and anything else connected to SRST).
2426 It then invokes the logic of @command{jtag arp_init}.
2427 @end deffn
2428
2429
2430 @node TAP Declaration
2431 @chapter TAP Declaration
2432 @cindex TAP declaration
2433 @cindex TAP configuration
2434
2435 @emph{Test Access Ports} (TAPs) are the core of JTAG.
2436 TAPs serve many roles, including:
2437
2438 @itemize @bullet
2439 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
2440 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
2441 Others do it indirectly, making a CPU do it.
2442 @item @b{Program Download} Using the same CPU support GDB uses,
2443 you can initialize a DRAM controller, download code to DRAM, and then
2444 start running that code.
2445 @item @b{Boundary Scan} Most chips support boundary scan, which
2446 helps test for board assembly problems like solder bridges
2447 and missing connections
2448 @end itemize
2449
2450 OpenOCD must know about the active TAPs on your board(s).
2451 Setting up the TAPs is the core task of your configuration files.
2452 Once those TAPs are set up, you can pass their names to code
2453 which sets up CPUs and exports them as GDB targets,
2454 probes flash memory, performs low-level JTAG operations, and more.
2455
2456 @section Scan Chains
2457 @cindex scan chain
2458
2459 TAPs are part of a hardware @dfn{scan chain},
2460 which is daisy chain of TAPs.
2461 They also need to be added to
2462 OpenOCD's software mirror of that hardware list,
2463 giving each member a name and associating other data with it.
2464 Simple scan chains, with a single TAP, are common in
2465 systems with a single microcontroller or microprocessor.
2466 More complex chips may have several TAPs internally.
2467 Very complex scan chains might have a dozen or more TAPs:
2468 several in one chip, more in the next, and connecting
2469 to other boards with their own chips and TAPs.
2470
2471 You can display the list with the @command{scan_chain} command.
2472 (Don't confuse this with the list displayed by the @command{targets}
2473 command, presented in the next chapter.
2474 That only displays TAPs for CPUs which are configured as
2475 debugging targets.)
2476 Here's what the scan chain might look like for a chip more than one TAP:
2477
2478 @verbatim
2479 TapName Enabled IdCode Expected IrLen IrCap IrMask Instr
2480 -- ------------------ ------- ---------- ---------- ----- ----- ------ -----
2481 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0 0 0x...
2482 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x1 0 0xc
2483 2 omap5912.unknown Y 0x00000000 0x00000000 8 0 0 0xff
2484 @end verbatim
2485
2486 Unfortunately those TAPs can't always be autoconfigured,
2487 because not all devices provide good support for that.
2488 JTAG doesn't require supporting IDCODE instructions, and
2489 chips with JTAG routers may not link TAPs into the chain
2490 until they are told to do so.
2491
2492 The configuration mechanism currently supported by OpenOCD
2493 requires explicit configuration of all TAP devices using
2494 @command{jtag newtap} commands, as detailed later in this chapter.
2495 A command like this would declare one tap and name it @code{chip1.cpu}:
2496
2497 @example
2498 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
2499 @end example
2500
2501 Each target configuration file lists the TAPs provided
2502 by a given chip.
2503 Board configuration files combine all the targets on a board,
2504 and so forth.
2505 Note that @emph{the order in which TAPs are declared is very important.}
2506 It must match the order in the JTAG scan chain, both inside
2507 a single chip and between them.
2508 @xref{FAQ TAP Order}.
2509
2510 For example, the ST Microsystems STR912 chip has
2511 three separate TAPs@footnote{See the ST
2512 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
2513 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
2514 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
2515 To configure those taps, @file{target/str912.cfg}
2516 includes commands something like this:
2517
2518 @example
2519 jtag newtap str912 flash ... params ...
2520 jtag newtap str912 cpu ... params ...
2521 jtag newtap str912 bs ... params ...
2522 @end example
2523
2524 Actual config files use a variable instead of literals like
2525 @option{str912}, to support more than one chip of each type.
2526 @xref{Config File Guidelines}.
2527
2528 @deffn Command {jtag names}
2529 Returns the names of all current TAPs in the scan chain.
2530 Use @command{jtag cget} or @command{jtag tapisenabled}
2531 to examine attributes and state of each TAP.
2532 @example
2533 foreach t [jtag names] @{
2534 puts [format "TAP: %s\n" $t]
2535 @}
2536 @end example
2537 @end deffn
2538
2539 @deffn Command {scan_chain}
2540 Displays the TAPs in the scan chain configuration,
2541 and their status.
2542 The set of TAPs listed by this command is fixed by
2543 exiting the OpenOCD configuration stage,
2544 but systems with a JTAG router can
2545 enable or disable TAPs dynamically.
2546 In addition to the enable/disable status, the contents of
2547 each TAP's instruction register can also change.
2548 @end deffn
2549
2550 @c FIXME! "jtag cget" should be able to return all TAP
2551 @c attributes, like "$target_name cget" does for targets.
2552
2553 @c Probably want "jtag eventlist", and a "tap-reset" event
2554 @c (on entry to RESET state).
2555
2556 @section TAP Names
2557 @cindex dotted name
2558
2559 When TAP objects are declared with @command{jtag newtap},
2560 a @dfn{dotted.name} is created for the TAP, combining the
2561 name of a module (usually a chip) and a label for the TAP.
2562 For example: @code{xilinx.tap}, @code{str912.flash},
2563 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
2564 Many other commands use that dotted.name to manipulate or
2565 refer to the TAP. For example, CPU configuration uses the
2566 name, as does declaration of NAND or NOR flash banks.
2567
2568 The components of a dotted name should follow ``C'' symbol
2569 name rules: start with an alphabetic character, then numbers
2570 and underscores are OK; while others (including dots!) are not.
2571
2572 @quotation Tip
2573 In older code, JTAG TAPs were numbered from 0..N.
2574 This feature is still present.
2575 However its use is highly discouraged, and
2576 should not be relied on; it will be removed by mid-2010.
2577 Update all of your scripts to use TAP names rather than numbers,
2578 by paying attention to the runtime warnings they trigger.
2579 Using TAP numbers in target configuration scripts prevents
2580 reusing those scripts on boards with multiple targets.
2581 @end quotation
2582
2583 @section TAP Declaration Commands
2584
2585 @c shouldn't this be(come) a {Config Command}?
2586 @anchor{jtag newtap}
2587 @deffn Command {jtag newtap} chipname tapname configparams...
2588 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
2589 and configured according to the various @var{configparams}.
2590
2591 The @var{chipname} is a symbolic name for the chip.
2592 Conventionally target config files use @code{$_CHIPNAME},
2593 defaulting to the model name given by the chip vendor but
2594 overridable.
2595
2596 @cindex TAP naming convention
2597 The @var{tapname} reflects the role of that TAP,
2598 and should follow this convention:
2599
2600 @itemize @bullet
2601 @item @code{bs} -- For boundary scan if this is a seperate TAP;
2602 @item @code{cpu} -- The main CPU of the chip, alternatively
2603 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
2604 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
2605 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
2606 @item @code{flash} -- If the chip has a flash TAP, like the str912;
2607 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
2608 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
2609 @item @code{tap} -- Should be used only FPGA or CPLD like devices
2610 with a single TAP;
2611 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
2612 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
2613 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
2614 a JTAG TAP; that TAP should be named @code{sdma}.
2615 @end itemize
2616
2617 Every TAP requires at least the following @var{configparams}:
2618
2619 @itemize @bullet
2620 @item @code{-irlen} @var{NUMBER}
2621 @*The length in bits of the
2622 instruction register, such as 4 or 5 bits.
2623 @end itemize
2624
2625 A TAP may also provide optional @var{configparams}:
2626
2627 @itemize @bullet
2628 @item @code{-disable} (or @code{-enable})
2629 @*Use the @code{-disable} parameter to flag a TAP which is not
2630 linked in to the scan chain after a reset using either TRST
2631 or the JTAG state machine's @sc{reset} state.
2632 You may use @code{-enable} to highlight the default state
2633 (the TAP is linked in).
2634 @xref{Enabling and Disabling TAPs}.
2635 @item @code{-expected-id} @var{number}
2636 @*A non-zero @var{number} represents a 32-bit IDCODE
2637 which you expect to find when the scan chain is examined.
2638 These codes are not required by all JTAG devices.
2639 @emph{Repeat the option} as many times as required if more than one
2640 ID code could appear (for example, multiple versions).
2641 Specify @var{number} as zero to suppress warnings about IDCODE
2642 values that were found but not included in the list.
2643
2644 Provide this value if at all possible, since it lets OpenOCD
2645 tell when the scan chain it sees isn't right. These values
2646 are provided in vendors' chip documentation, usually a technical
2647 reference manual. Sometimes you may need to probe the JTAG
2648 hardware to find these values.
2649 @xref{Autoprobing}.
2650 @item @code{-ircapture} @var{NUMBER}
2651 @*The bit pattern loaded by the TAP into the JTAG shift register
2652 on entry to the @sc{ircapture} state, such as 0x01.
2653 JTAG requires the two LSBs of this value to be 01.
2654 By default, @code{-ircapture} and @code{-irmask} are set
2655 up to verify that two-bit value. You may provide
2656 additional bits, if you know them, or indicate that
2657 a TAP doesn't conform to the JTAG specification.
2658 @item @code{-irmask} @var{NUMBER}
2659 @*A mask used with @code{-ircapture}
2660 to verify that instruction scans work correctly.
2661 Such scans are not used by OpenOCD except to verify that
2662 there seems to be no problems with JTAG scan chain operations.
2663 @end itemize
2664 @end deffn
2665
2666 @section Other TAP commands
2667
2668 @deffn Command {jtag cget} dotted.name @option{-event} name
2669 @deffnx Command {jtag configure} dotted.name @option{-event} name string
2670 At this writing this TAP attribute
2671 mechanism is used only for event handling.
2672 (It is not a direct analogue of the @code{cget}/@code{configure}
2673 mechanism for debugger targets.)
2674 See the next section for information about the available events.
2675
2676 The @code{configure} subcommand assigns an event handler,
2677 a TCL string which is evaluated when the event is triggered.
2678 The @code{cget} subcommand returns that handler.
2679 @end deffn
2680
2681 @anchor{TAP Events}
2682 @section TAP Events
2683 @cindex events
2684 @cindex TAP events
2685
2686 OpenOCD includes two event mechanisms.
2687 The one presented here applies to all JTAG TAPs.
2688 The other applies to debugger targets,
2689 which are associated with certain TAPs.
2690
2691 The TAP events currently defined are:
2692
2693 @itemize @bullet
2694 @item @b{post-reset}
2695 @* The TAP has just completed a JTAG reset.
2696 The tap may still be in the JTAG @sc{reset} state.
2697 Handlers for these events might perform initialization sequences
2698 such as issuing TCK cycles, TMS sequences to ensure
2699 exit from the ARM SWD mode, and more.
2700
2701 Because the scan chain has not yet been verified, handlers for these events
2702 @emph{should not issue commands which scan the JTAG IR or DR registers}
2703 of any particular target.
2704 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
2705 @item @b{setup}
2706 @* The scan chain has been reset and verified.
2707 This handler may enable TAPs as needed.
2708 @item @b{tap-disable}
2709 @* The TAP needs to be disabled. This handler should
2710 implement @command{jtag tapdisable}
2711 by issuing the relevant JTAG commands.
2712 @item @b{tap-enable}
2713 @* The TAP needs to be enabled. This handler should
2714 implement @command{jtag tapenable}
2715 by issuing the relevant JTAG commands.
2716 @end itemize
2717
2718 If you need some action after each JTAG reset, which isn't actually
2719 specific to any TAP (since you can't yet trust the scan chain's
2720 contents to be accurate), you might:
2721
2722 @example
2723 jtag configure CHIP.jrc -event post-reset @{
2724 echo "JTAG Reset done"
2725 ... non-scan jtag operations to be done after reset
2726 @}
2727 @end example
2728
2729
2730 @anchor{Enabling and Disabling TAPs}
2731 @section Enabling and Disabling TAPs
2732 @cindex JTAG Route Controller
2733 @cindex jrc
2734
2735 In some systems, a @dfn{JTAG Route Controller} (JRC)
2736 is used to enable and/or disable specific JTAG TAPs.
2737 Many ARM based chips from Texas Instruments include
2738 an ``ICEpick'' module, which is a JRC.
2739 Such chips include DaVinci and OMAP3 processors.
2740
2741 A given TAP may not be visible until the JRC has been
2742 told to link it into the scan chain; and if the JRC
2743 has been told to unlink that TAP, it will no longer
2744 be visible.
2745 Such routers address problems that JTAG ``bypass mode''
2746 ignores, such as:
2747
2748 @itemize
2749 @item The scan chain can only go as fast as its slowest TAP.
2750 @item Having many TAPs slows instruction scans, since all
2751 TAPs receive new instructions.
2752 @item TAPs in the scan chain must be powered up, which wastes
2753 power and prevents debugging some power management mechanisms.
2754 @end itemize
2755
2756 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
2757 as implied by the existence of JTAG routers.
2758 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
2759 does include a kind of JTAG router functionality.
2760
2761 @c (a) currently the event handlers don't seem to be able to
2762 @c fail in a way that could lead to no-change-of-state.
2763
2764 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
2765 shown below, and is implemented using TAP event handlers.
2766 So for example, when defining a TAP for a CPU connected to
2767 a JTAG router, your @file{target.cfg} file
2768 should define TAP event handlers using
2769 code that looks something like this:
2770
2771 @example
2772 jtag configure CHIP.cpu -event tap-enable @{
2773 ... jtag operations using CHIP.jrc
2774 @}
2775 jtag configure CHIP.cpu -event tap-disable @{
2776 ... jtag operations using CHIP.jrc
2777 @}
2778 @end example
2779
2780 Then you might want that CPU's TAP enabled almost all the time:
2781
2782 @example
2783 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
2784 @end example
2785
2786 Note how that particular setup event handler declaration
2787 uses quotes to evaluate @code{$CHIP} when the event is configured.
2788 Using brackets @{ @} would cause it to be evaluated later,
2789 at runtime, when it might have a different value.
2790
2791 @deffn Command {jtag tapdisable} dotted.name
2792 If necessary, disables the tap
2793 by sending it a @option{tap-disable} event.
2794 Returns the string "1" if the tap
2795 specified by @var{dotted.name} is enabled,
2796 and "0" if it is disabled.
2797 @end deffn
2798
2799 @deffn Command {jtag tapenable} dotted.name
2800 If necessary, enables the tap
2801 by sending it a @option{tap-enable} event.
2802 Returns the string "1" if the tap
2803 specified by @var{dotted.name} is enabled,
2804 and "0" if it is disabled.
2805 @end deffn
2806
2807 @deffn Command {jtag tapisenabled} dotted.name
2808 Returns the string "1" if the tap
2809 specified by @var{dotted.name} is enabled,
2810 and "0" if it is disabled.
2811
2812 @quotation Note
2813 Humans will find the @command{scan_chain} command more helpful
2814 for querying the state of the JTAG taps.
2815 @end quotation
2816 @end deffn
2817
2818 @anchor{Autoprobing}
2819 @section Autoprobing
2820 @cindex autoprobe
2821 @cindex JTAG autoprobe
2822
2823 TAP configuration is the first thing that needs to be done
2824 after interface and reset configuration. Sometimes it's
2825 hard finding out what TAPs exist, or how they are identified.
2826 Vendor documentation is not always easy to find and use.
2827
2828 To help you get past such problems, OpenOCD has a limited
2829 @emph{autoprobing} ability to look at the scan chain, doing
2830 a @dfn{blind interrogation} and then reporting the TAPs it finds.
2831 To use this mechanism, start the OpenOCD server with only data
2832 that configures your JTAG interface, and arranges to come up
2833 with a slow clock (many devices don't support fast JTAG clocks
2834 right when they come out of reset).
2835
2836 For example, your @file{openocd.cfg} file might have:
2837
2838 @example
2839 source [find interface/olimex-arm-usb-tiny-h.cfg]
2840 reset_config trst_and_srst
2841 jtag_rclk 8
2842 @end example
2843
2844 When you start the server without any TAPs configured, it will
2845 attempt to autoconfigure the TAPs. There are two parts to this:
2846
2847 @enumerate
2848 @item @emph{TAP discovery} ...
2849 After a JTAG reset (sometimes a system reset may be needed too),
2850 each TAP's data registers will hold the contents of either the
2851 IDCODE or BYPASS register.
2852 If JTAG communication is working, OpenOCD will see each TAP,
2853 and report what @option{-expected-id} to use with it.
2854 @item @emph{IR Length discovery} ...
2855 Unfortunately JTAG does not provide a reliable way to find out
2856 the value of the @option{-irlen} parameter to use with a TAP
2857 that is discovered.
2858 If OpenOCD can discover the length of a TAP's instruction
2859 register, it will report it.
2860 Otherwise you may need to consult vendor documentation, such
2861 as chip data sheets or BSDL files.
2862 @end enumerate
2863
2864 In many cases your board will have a simple scan chain with just
2865 a single device. Here's what OpenOCD reported with one board
2866 that's a bit more complex:
2867
2868 @example
2869 clock speed 8 kHz
2870 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
2871 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
2872 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
2873 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
2874 AUTO auto0.tap - use "... -irlen 4"
2875 AUTO auto1.tap - use "... -irlen 4"
2876 AUTO auto2.tap - use "... -irlen 6"
2877 no gdb ports allocated as no target has been specified
2878 @end example
2879
2880 Given that information, you should be able to either find some existing
2881 config files to use, or create your own. If you create your own, you
2882 would configure from the bottom up: first a @file{target.cfg} file
2883 with these TAPs, any targets associated with them, and any on-chip
2884 resources; then a @file{board.cfg} with off-chip resources, clocking,
2885 and so forth.
2886
2887 @node CPU Configuration
2888 @chapter CPU Configuration
2889 @cindex GDB target
2890
2891 This chapter discusses how to set up GDB debug targets for CPUs.
2892 You can also access these targets without GDB
2893 (@pxref{Architecture and Core Commands},
2894 and @ref{Target State handling}) and
2895 through various kinds of NAND and NOR flash commands.
2896 If you have multiple CPUs you can have multiple such targets.
2897
2898 We'll start by looking at how to examine the targets you have,
2899 then look at how to add one more target and how to configure it.
2900
2901 @section Target List
2902 @cindex target, current
2903 @cindex target, list
2904
2905 All targets that have been set up are part of a list,
2906 where each member has a name.
2907 That name should normally be the same as the TAP name.
2908 You can display the list with the @command{targets}
2909 (plural!) command.
2910 This display often has only one CPU; here's what it might
2911 look like with more than one:
2912 @verbatim
2913 TargetName Type Endian TapName State
2914 -- ------------------ ---------- ------ ------------------ ------------
2915 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
2916 1 MyTarget cortex_m3 little mychip.foo tap-disabled
2917 @end verbatim
2918
2919 One member of that list is the @dfn{current target}, which
2920 is implicitly referenced by many commands.
2921 It's the one marked with a @code{*} near the target name.
2922 In particular, memory addresses often refer to the address
2923 space seen by that current target.
2924 Commands like @command{mdw} (memory display words)
2925 and @command{flash erase_address} (erase NOR flash blocks)
2926 are examples; and there are many more.
2927
2928 Several commands let you examine the list of targets:
2929
2930 @deffn Command {target count}
2931 @emph{Note: target numbers are deprecated; don't use them.
2932 They will be removed shortly after August 2010, including this command.
2933 Iterate target using @command{target names}, not by counting.}
2934
2935 Returns the number of targets, @math{N}.
2936 The highest numbered target is @math{N - 1}.
2937 @example
2938 set c [target count]
2939 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
2940 # Assuming you have created this function
2941 print_target_details $x
2942 @}
2943 @end example
2944 @end deffn
2945
2946 @deffn Command {target current}
2947 Returns the name of the current target.
2948 @end deffn
2949
2950 @deffn Command {target names}
2951 Lists the names of all current targets in the list.
2952 @example
2953 foreach t [target names] @{
2954 puts [format "Target: %s\n" $t]
2955 @}
2956 @end example
2957 @end deffn
2958
2959 @deffn Command {target number} number
2960 @emph{Note: target numbers are deprecated; don't use them.
2961 They will be removed shortly after August 2010, including this command.}
2962
2963 The list of targets is numbered starting at zero.
2964 This command returns the name of the target at index @var{number}.
2965 @example
2966 set thename [target number $x]
2967 puts [format "Target %d is: %s\n" $x $thename]
2968 @end example
2969 @end deffn
2970
2971 @c yep, "target list" would have been better.
2972 @c plus maybe "target setdefault".
2973
2974 @deffn Command targets [name]
2975 @emph{Note: the name of this command is plural. Other target
2976 command names are singular.}
2977
2978 With no parameter, this command displays a table of all known
2979 targets in a user friendly form.
2980
2981 With a parameter, this command sets the current target to
2982 the given target with the given @var{name}; this is
2983 only relevant on boards which have more than one target.
2984 @end deffn
2985
2986 @section Target CPU Types and Variants
2987 @cindex target type
2988 @cindex CPU type
2989 @cindex CPU variant
2990
2991 Each target has a @dfn{CPU type}, as shown in the output of
2992 the @command{targets} command. You need to specify that type
2993 when calling @command{target create}.
2994 The CPU type indicates more than just the instruction set.
2995 It also indicates how that instruction set is implemented,
2996 what kind of debug support it integrates,
2997 whether it has an MMU (and if so, what kind),
2998 what core-specific commands may be available
2999 (@pxref{Architecture and Core Commands}),
3000 and more.
3001
3002 For some CPU types, OpenOCD also defines @dfn{variants} which
3003 indicate differences that affect their handling.
3004 For example, a particular implementation bug might need to be
3005 worked around in some chip versions.
3006
3007 It's easy to see what target types are supported,
3008 since there's a command to list them.
3009 However, there is currently no way to list what target variants
3010 are supported (other than by reading the OpenOCD source code).
3011
3012 @anchor{target types}
3013 @deffn Command {target types}
3014 Lists all supported target types.
3015 At this writing, the supported CPU types and variants are:
3016
3017 @itemize @bullet
3018 @item @code{arm11} -- this is a generation of ARMv6 cores
3019 @item @code{arm720t} -- this is an ARMv4 core with an MMU
3020 @item @code{arm7tdmi} -- this is an ARMv4 core
3021 @item @code{arm920t} -- this is an ARMv5 core with an MMU
3022 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
3023 @item @code{arm966e} -- this is an ARMv5 core
3024 @item @code{arm9tdmi} -- this is an ARMv4 core
3025 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
3026 (Support for this is preliminary and incomplete.)
3027 @item @code{cortex_a8} -- this is an ARMv7 core with an MMU
3028 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
3029 compact Thumb2 instruction set. It supports one variant:
3030 @itemize @minus
3031 @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
3032 This will cause OpenOCD to use a software reset rather than asserting
3033 SRST, to avoid a issue with clearing the debug registers.
3034 This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
3035 be detected and the normal reset behaviour used.
3036 @end itemize
3037 @item @code{dragonite} -- resembles arm966e
3038 @item @code{fa526} -- resembles arm920 (w/o Thumb)
3039 @item @code{feroceon} -- resembles arm926
3040 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
3041 @itemize @minus
3042 @item @code{ejtag_srst} ... Use this when debugging targets that do not
3043 provide a functional SRST line on the EJTAG connector. This causes
3044 OpenOCD to instead use an EJTAG software reset command to reset the
3045 processor.
3046 You still need to enable @option{srst} on the @command{reset_config}
3047 command to enable OpenOCD hardware reset functionality.
3048 @end itemize
3049 @item @code{xscale} -- this is actually an architecture,
3050 not a CPU type. It is based on the ARMv5 architecture.
3051 There are several variants defined:
3052 @itemize @minus
3053 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
3054 @code{pxa27x} ... instruction register length is 7 bits
3055 @item @code{pxa250}, @code{pxa255},
3056 @code{pxa26x} ... instruction register length is 5 bits
3057 @end itemize
3058 @end itemize
3059 @end deffn
3060
3061 To avoid being confused by the variety of ARM based cores, remember
3062 this key point: @emph{ARM is a technology licencing company}.
3063 (See: @url{http://www.arm.com}.)
3064 The CPU name used by OpenOCD will reflect the CPU design that was
3065 licenced, not a vendor brand which incorporates that design.
3066 Name prefixes like arm7, arm9, arm11, and cortex
3067 reflect design generations;
3068 while names like ARMv4, ARMv5, ARMv6, and ARMv7
3069 reflect an architecture version implemented by a CPU design.
3070
3071 @anchor{Target Configuration}
3072 @section Target Configuration
3073
3074 Before creating a ``target'', you must have added its TAP to the scan chain.
3075 When you've added that TAP, you will have a @code{dotted.name}
3076 which is used to set up the CPU support.
3077 The chip-specific configuration file will normally configure its CPU(s)
3078 right after it adds all of the chip's TAPs to the scan chain.
3079
3080 Although you can set up a target in one step, it's often clearer if you
3081 use shorter commands and do it in two steps: create it, then configure
3082 optional parts.
3083 All operations on the target after it's created will use a new
3084 command, created as part of target creation.
3085
3086 The two main things to configure after target creation are
3087 a work area, which usually has target-specific defaults even
3088 if the board setup code overrides them later;
3089 and event handlers (@pxref{Target Events}), which tend
3090 to be much more board-specific.
3091 The key steps you use might look something like this
3092
3093 @example
3094 target create MyTarget cortex_m3 -chain-position mychip.cpu
3095 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
3096 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
3097 $MyTarget configure -event reset-init @{ myboard_reinit @}
3098 @end example
3099
3100 You should specify a working area if you can; typically it uses some
3101 on-chip SRAM.
3102 Such a working area can speed up many things, including bulk
3103 writes to target memory;
3104 flash operations like checking to see if memory needs to be erased;
3105 GDB memory checksumming;
3106 and more.
3107
3108 @quotation Warning
3109 On more complex chips, the work area can become
3110 inaccessible when application code
3111 (such as an operating system)
3112 enables or disables the MMU.
3113 For example, the particular MMU context used to acess the virtual
3114 address will probably matter ... and that context might not have
3115 easy access to other addresses needed.
3116 At this writing, OpenOCD doesn't have much MMU intelligence.
3117 @end quotation
3118
3119 It's often very useful to define a @code{reset-init} event handler.
3120 For systems that are normally used with a boot loader,
3121 common tasks include updating clocks and initializing memory
3122 controllers.
3123 That may be needed to let you write the boot loader into flash,
3124 in order to ``de-brick'' your board; or to load programs into
3125 external DDR memory without having run the boot loader.
3126
3127 @deffn Command {target create} target_name type configparams...
3128 This command creates a GDB debug target that refers to a specific JTAG tap.
3129 It enters that target into a list, and creates a new
3130 command (@command{@var{target_name}}) which is used for various
3131 purposes including additional configuration.
3132
3133 @itemize @bullet
3134 @item @var{target_name} ... is the name of the debug target.
3135 By convention this should be the same as the @emph{dotted.name}
3136 of the TAP associated with this target, which must be specified here
3137 using the @code{-chain-position @var{dotted.name}} configparam.
3138
3139 This name is also used to create the target object command,
3140 referred to here as @command{$target_name},
3141 and in other places the target needs to be identified.
3142 @item @var{type} ... specifies the target type. @xref{target types}.
3143 @item @var{configparams} ... all parameters accepted by
3144 @command{$target_name configure} are permitted.
3145 If the target is big-endian, set it here with @code{-endian big}.
3146 If the variant matters, set it here with @code{-variant}.
3147
3148 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
3149 @end itemize
3150 @end deffn
3151
3152 @deffn Command {$target_name configure} configparams...
3153 The options accepted by this command may also be
3154 specified as parameters to @command{target create}.
3155 Their values can later be queried one at a time by
3156 using the @command{$target_name cget} command.
3157
3158 @emph{Warning:} changing some of these after setup is dangerous.
3159 For example, moving a target from one TAP to another;
3160 and changing its endianness or variant.
3161
3162 @itemize @bullet
3163
3164 @item @code{-chain-position} @var{dotted.name} -- names the TAP
3165 used to access this target.
3166
3167 @item @code{-endian} (@option{big}|@option{little}) -- specifies
3168 whether the CPU uses big or little endian conventions
3169
3170 @item @code{-event} @var{event_name} @var{event_body} --
3171 @xref{Target Events}.
3172 Note that this updates a list of named event handlers.
3173 Calling this twice with two different event names assigns
3174 two different handlers, but calling it twice with the
3175 same event name assigns only one handler.
3176
3177 @item @code{-variant} @var{name} -- specifies a variant of the target,
3178 which OpenOCD needs to know about.
3179
3180 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
3181 whether the work area gets backed up; by default,
3182 @emph{it is not backed up.}
3183 When possible, use a working_area that doesn't need to be backed up,
3184 since performing a backup slows down operations.
3185 For example, the beginning of an SRAM block is likely to
3186 be used by most build systems, but the end is often unused.
3187
3188 @item @code{-work-area-size} @var{size} -- specify work are size,
3189 in bytes. The same size applies regardless of whether its physical
3190 or virtual address is being used.
3191
3192 @item @code{-work-area-phys} @var{address} -- set the work area
3193 base @var{address} to be used when no MMU is active.
3194
3195 @item @code{-work-area-virt} @var{address} -- set the work area
3196 base @var{address} to be used when an MMU is active.
3197 @emph{Do not specify a value for this except on targets with an MMU.}
3198 The value should normally correspond to a static mapping for the
3199 @code{-work-area-phys} address, set up by the current operating system.
3200
3201 @end itemize
3202 @end deffn
3203
3204 @section Other $target_name Commands
3205 @cindex object command
3206
3207 The Tcl/Tk language has the concept of object commands,
3208 and OpenOCD adopts that same model for targets.
3209
3210 A good Tk example is a on screen button.
3211 Once a button is created a button
3212 has a name (a path in Tk terms) and that name is useable as a first
3213 class command. For example in Tk, one can create a button and later
3214 configure it like this:
3215
3216 @example
3217 # Create
3218 button .foobar -background red -command @{ foo @}
3219 # Modify
3220 .foobar configure -foreground blue
3221 # Query
3222 set x [.foobar cget -background]
3223 # Report
3224 puts [format "The button is %s" $x]
3225 @end example
3226
3227 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
3228 button, and its object commands are invoked the same way.
3229
3230 @example
3231 str912.cpu mww 0x1234 0x42
3232 omap3530.cpu mww 0x5555 123
3233 @end example
3234
3235 The commands supported by OpenOCD target objects are:
3236
3237 @deffn Command {$target_name arp_examine}
3238 @deffnx Command {$target_name arp_halt}
3239 @deffnx Command {$target_name arp_poll}
3240 @deffnx Command {$target_name arp_reset}
3241 @deffnx Command {$target_name arp_waitstate}
3242 Internal OpenOCD scripts (most notably @file{startup.tcl})
3243 use these to deal with specific reset cases.
3244 They are not otherwise documented here.
3245 @end deffn
3246
3247 @deffn Command {$target_name array2mem} arrayname width address count
3248 @deffnx Command {$target_name mem2array} arrayname width address count
3249 These provide an efficient script-oriented interface to memory.
3250 The @code{array2mem} primitive writes bytes, halfwords, or words;
3251 while @code{mem2array} reads them.
3252 In both cases, the TCL side uses an array, and
3253 the target side uses raw memory.
3254
3255 The efficiency comes from enabling the use of
3256 bulk JTAG data transfer operations.
3257 The script orientation comes from working with data
3258 values that are packaged for use by TCL scripts;
3259 @command{mdw} type primitives only print data they retrieve,
3260 and neither store nor return those values.
3261
3262 @itemize
3263 @item @var{arrayname} ... is the name of an array variable
3264 @item @var{width} ... is 8/16/32 - indicating the memory access size
3265 @item @var{address} ... is the target memory address
3266 @item @var{count} ... is the number of elements to process
3267 @end itemize
3268 @end deffn
3269
3270 @deffn Command {$target_name cget} queryparm
3271 Each configuration parameter accepted by
3272 @command{$target_name configure}
3273 can be individually queried, to return its current value.
3274 The @var{queryparm} is a parameter name
3275 accepted by that command, such as @code{-work-area-phys}.
3276 There are a few special cases:
3277
3278 @itemize @bullet
3279 @item @code{-event} @var{event_name} -- returns the handler for the
3280 event named @var{event_name}.
3281 This is a special case because setting a handler requires
3282 two parameters.
3283 @item @code{-type} -- returns the target type.
3284 This is a special case because this is set using
3285 @command{target create} and can't be changed
3286 using @command{$target_name configure}.
3287 @end itemize
3288
3289 For example, if you wanted to summarize information about
3290 all the targets you might use something like this:
3291
3292 @example
3293 foreach name [target names] @{
3294 set y [$name cget -endian]
3295 set z [$name cget -type]
3296 puts [format "Chip %d is %s, Endian: %s, type: %s" \
3297 $x $name $y $z]
3298 @}
3299 @end example
3300 @end deffn
3301
3302 @anchor{target curstate}
3303 @deffn Command {$target_name curstate}
3304 Displays the current target state:
3305 @code{debug-running},
3306 @code{halted},
3307 @code{reset},
3308 @code{running}, or @code{unknown}.
3309 (Also, @pxref{Event Polling}.)
3310 @end deffn
3311
3312 @deffn Command {$target_name eventlist}
3313 Displays a table listing all event handlers
3314 currently associated with this target.
3315 @xref{Target Events}.
3316 @end deffn
3317
3318 @deffn Command {$target_name invoke-event} event_name
3319 Invokes the handler for the event named @var{event_name}.
3320 (This is primarily intended for use by OpenOCD framework
3321 code, for example by the reset code in @file{startup.tcl}.)
3322 @end deffn
3323
3324 @deffn Command {$target_name mdw} addr [count]
3325 @deffnx Command {$target_name mdh} addr [count]
3326 @deffnx Command {$target_name mdb} addr [count]
3327 Display contents of address @var{addr}, as
3328 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
3329 or 8-bit bytes (@command{mdb}).
3330 If @var{count} is specified, displays that many units.
3331 (If you want to manipulate the data instead of displaying it,
3332 see the @code{mem2array} primitives.)
3333 @end deffn
3334
3335 @deffn Command {$target_name mww} addr word
3336 @deffnx Command {$target_name mwh} addr halfword
3337 @deffnx Command {$target_name mwb} addr byte
3338 Writes the specified @var{word} (32 bits),
3339 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3340 at the specified address @var{addr}.
3341 @end deffn
3342
3343 @anchor{Target Events}
3344 @section Target Events
3345 @cindex target events
3346 @cindex events
3347 At various times, certain things can happen, or you want them to happen.
3348 For example:
3349 @itemize @bullet
3350 @item What should happen when GDB connects? Should your target reset?
3351 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
3352 @item During reset, do you need to write to certain memory locations
3353 to set up system clocks or
3354 to reconfigure the SDRAM?
3355 @end itemize
3356
3357 All of the above items can be addressed by target event handlers.
3358 These are set up by @command{$target_name configure -event} or
3359 @command{target create ... -event}.
3360
3361 The programmer's model matches the @code{-command} option used in Tcl/Tk
3362 buttons and events. The two examples below act the same, but one creates
3363 and invokes a small procedure while the other inlines it.
3364
3365 @example
3366 proc my_attach_proc @{ @} @{
3367 echo "Reset..."
3368 reset halt
3369 @}
3370 mychip.cpu configure -event gdb-attach my_attach_proc
3371 mychip.cpu configure -event gdb-attach @{
3372 echo "Reset..."
3373 reset halt
3374 @}
3375 @end example
3376
3377 The following target events are defined:
3378
3379 @itemize @bullet
3380 @item @b{debug-halted}
3381 @* The target has halted for debug reasons (i.e.: breakpoint)
3382 @item @b{debug-resumed}
3383 @* The target has resumed (i.e.: gdb said run)
3384 @item @b{early-halted}
3385 @* Occurs early in the halt process
3386 @ignore
3387 @item @b{examine-end}
3388 @* Currently not used (goal: when JTAG examine completes)
3389 @item @b{examine-start}
3390 @* Currently not used (goal: when JTAG examine starts)
3391 @end ignore
3392 @item @b{gdb-attach}
3393 @* When GDB connects
3394 @item @b{gdb-detach}
3395 @* When GDB disconnects
3396 @item @b{gdb-end}
3397 @* When the target has halted and GDB is not doing anything (see early halt)
3398 @item @b{gdb-flash-erase-start}
3399 @* Before the GDB flash process tries to erase the flash
3400 @item @b{gdb-flash-erase-end}
3401 @* After the GDB flash process has finished erasing the flash
3402 @item @b{gdb-flash-write-start}
3403 @* Before GDB writes to the flash
3404 @item @b{gdb-flash-write-end}
3405 @* After GDB writes to the flash
3406 @item @b{gdb-start}
3407 @* Before the target steps, gdb is trying to start/resume the target
3408 @item @b{halted}
3409 @* The target has halted
3410 @ignore
3411 @item @b{old-gdb_program_config}
3412 @* DO NOT USE THIS: Used internally
3413 @item @b{old-pre_resume}
3414 @* DO NOT USE THIS: Used internally
3415 @end ignore
3416 @item @b{reset-assert-pre}
3417 @* Issued as part of @command{reset} processing
3418 after @command{reset_init} was triggered
3419 but before SRST alone is re-asserted on the tap.
3420 @item @b{reset-assert-post}
3421 @* Issued as part of @command{reset} processing
3422 when SRST is asserted on the tap.
3423 @item @b{reset-deassert-pre}
3424 @* Issued as part of @command{reset} processing
3425 when SRST is about to be released on the tap.
3426 @item @b{reset-deassert-post}
3427 @* Issued as part of @command{reset} processing
3428 when SRST has been released on the tap.
3429 @item @b{reset-end}
3430 @* Issued as the final step in @command{reset} processing.
3431 @ignore
3432 @item @b{reset-halt-post}
3433 @* Currently not used
3434 @item @b{reset-halt-pre}
3435 @* Currently not used
3436 @end ignore
3437 @item @b{reset-init}
3438 @* Used by @b{reset init} command for board-specific initialization.
3439 This event fires after @emph{reset-deassert-post}.
3440
3441 This is where you would configure PLLs and clocking, set up DRAM so
3442 you can download programs that don't fit in on-chip SRAM, set up pin
3443 multiplexing, and so on.
3444 (You may be able to switch to a fast JTAG clock rate here, after
3445 the target clocks are fully set up.)
3446 @item @b{reset-start}
3447 @* Issued as part of @command{reset} processing
3448 before @command{reset_init} is called.
3449
3450 This is the most robust place to use @command{jtag_rclk}
3451 or @command{jtag_khz} to switch to a low JTAG clock rate,
3452 when reset disables PLLs needed to use a fast clock.
3453 @ignore
3454 @item @b{reset-wait-pos}
3455 @* Currently not used
3456 @item @b{reset-wait-pre}
3457 @* Currently not used
3458 @end ignore
3459 @item @b{resume-start}
3460 @* Before any target is resumed
3461 @item @b{resume-end}
3462 @* After all targets have resumed
3463 @item @b{resume-ok}
3464 @* Success
3465 @item @b{resumed}
3466 @* Target has resumed
3467 @end itemize
3468
3469
3470 @node Flash Commands
3471 @chapter Flash Commands
3472
3473 OpenOCD has different commands for NOR and NAND flash;
3474 the ``flash'' command works with NOR flash, while
3475 the ``nand'' command works with NAND flash.
3476 This partially reflects different hardware technologies:
3477 NOR flash usually supports direct CPU instruction and data bus access,
3478 while data from a NAND flash must be copied to memory before it can be
3479 used. (SPI flash must also be copied to memory before use.)
3480 However, the documentation also uses ``flash'' as a generic term;
3481 for example, ``Put flash configuration in board-specific files''.
3482
3483 Flash Steps:
3484 @enumerate
3485 @item Configure via the command @command{flash bank}
3486 @* Do this in a board-specific configuration file,
3487 passing parameters as needed by the driver.
3488 @item Operate on the flash via @command{flash subcommand}
3489 @* Often commands to manipulate the flash are typed by a human, or run
3490 via a script in some automated way. Common tasks include writing a
3491 boot loader, operating system, or other data.
3492 @item GDB Flashing
3493 @* Flashing via GDB requires the flash be configured via ``flash
3494 bank'', and the GDB flash features be enabled.
3495 @xref{GDB Configuration}.
3496 @end enumerate
3497
3498 Many CPUs have the ablity to ``boot'' from the first flash bank.
3499 This means that misprogramming that bank can ``brick'' a system,
3500 so that it can't boot.
3501 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
3502 board by (re)installing working boot firmware.
3503
3504 @anchor{NOR Configuration}
3505 @section Flash Configuration Commands
3506 @cindex flash configuration
3507
3508 @deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
3509 Configures a flash bank which provides persistent storage
3510 for addresses from @math{base} to @math{base + size - 1}.
3511 These banks will often be visible to GDB through the target's memory map.
3512 In some cases, configuring a flash bank will activate extra commands;
3513 see the driver-specific documentation.
3514
3515 @itemize @bullet
3516 @item @var{driver} ... identifies the controller driver
3517 associated with the flash bank being declared.
3518 This is usually @code{cfi} for external flash, or else
3519 the name of a microcontroller with embedded flash memory.
3520 @xref{Flash Driver List}.
3521 @item @var{base} ... Base address of the flash chip.
3522 @item @var{size} ... Size of the chip, in bytes.
3523 For some drivers, this value is detected from the hardware.
3524 @item @var{chip_width} ... Width of the flash chip, in bytes;
3525 ignored for most microcontroller drivers.
3526 @item @var{bus_width} ... Width of the data bus used to access the
3527 chip, in bytes; ignored for most microcontroller drivers.
3528 @item @var{target} ... Names the target used to issue
3529 commands to the flash controller.
3530 @comment Actually, it's currently a controller-specific parameter...
3531 @item @var{driver_options} ... drivers may support, or require,
3532 additional parameters. See the driver-specific documentation
3533 for more information.
3534 @end itemize
3535 @quotation Note
3536 This command is not available after OpenOCD initialization has completed.
3537 Use it in board specific configuration files, not interactively.
3538 @end quotation
3539 @end deffn
3540
3541 @comment the REAL name for this command is "ocd_flash_banks"
3542 @comment less confusing would be: "flash list" (like "nand list")
3543 @deffn Command {flash banks}
3544 Prints a one-line summary of each device declared
3545 using @command{flash bank}, numbered from zero.
3546 Note that this is the @emph{plural} form;
3547 the @emph{singular} form is a very different command.
3548 @end deffn
3549
3550 @deffn Command {flash probe} num
3551 Identify the flash, or validate the parameters of the configured flash. Operation
3552 depends on the flash type.
3553 The @var{num} parameter is a value shown by @command{flash banks}.
3554 Most flash commands will implicitly @emph{autoprobe} the bank;
3555 flash drivers can distinguish between probing and autoprobing,
3556 but most don't bother.
3557 @end deffn
3558
3559 @section Erasing, Reading, Writing to Flash
3560 @cindex flash erasing
3561 @cindex flash reading
3562 @cindex flash writing
3563 @cindex flash programming
3564
3565 One feature distinguishing NOR flash from NAND or serial flash technologies
3566 is that for read access, it acts exactly like any other addressible memory.
3567 This means you can use normal memory read commands like @command{mdw} or
3568 @command{dump_image} with it, with no special @command{flash} subcommands.
3569 @xref{Memory access}, and @ref{Image access}.
3570
3571 Write access works differently. Flash memory normally needs to be erased
3572 before it's written. Erasing a sector turns all of its bits to ones, and
3573 writing can turn ones into zeroes. This is why there are special commands
3574 for interactive erasing and writing, and why GDB needs to know which parts
3575 of the address space hold NOR flash memory.
3576
3577 @quotation Note
3578 Most of these erase and write commands leverage the fact that NOR flash
3579 chips consume target address space. They implicitly refer to the current
3580 JTAG target, and map from an address in that target's address space
3581 back to a flash bank.
3582 @comment In May 2009, those mappings may fail if any bank associated
3583 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
3584 A few commands use abstract addressing based on bank and sector numbers,
3585 and don't depend on searching the current target and its address space.
3586 Avoid confusing the two command models.
3587 @end quotation
3588
3589 Some flash chips implement software protection against accidental writes,
3590 since such buggy writes could in some cases ``brick'' a system.
3591 For such systems, erasing and writing may require sector protection to be
3592 disabled first.
3593 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
3594 and AT91SAM7 on-chip flash.
3595 @xref{flash protect}.
3596
3597 @anchor{flash erase_sector}
3598 @deffn Command {flash erase_sector} num first last
3599 Erase sectors in bank @var{num}, starting at sector @var{first}
3600 up to and including @var{last}.
3601 Sector numbering starts at 0.
3602 Providing a @var{last} sector of @option{last}
3603 specifies "to the end of the flash bank".
3604 The @var{num} parameter is a value shown by @command{flash banks}.
3605 @end deffn
3606
3607 @deffn Command {flash erase_address} address length
3608 Erase sectors starting at @var{address} for @var{length} bytes.
3609 The flash bank to use is inferred from the @var{address}, and
3610 the specified length must stay within that bank.
3611 As a special case, when @var{length} is zero and @var{address} is
3612 the start of the bank, the whole flash is erased.
3613 @end deffn
3614
3615 @deffn Command {flash fillw} address word length
3616 @deffnx Command {flash fillh} address halfword length
3617 @deffnx Command {flash fillb} address byte length
3618 Fills flash memory with the specified @var{word} (32 bits),
3619 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3620 starting at @var{address} and continuing
3621 for @var{length} units (word/halfword/byte).
3622 No erasure is done before writing; when needed, that must be done
3623 before issuing this command.
3624 Writes are done in blocks of up to 1024 bytes, and each write is
3625 verified by reading back the data and comparing it to what was written.
3626 The flash bank to use is inferred from the @var{address} of
3627 each block, and the specified length must stay within that bank.
3628 @end deffn
3629 @comment no current checks for errors if fill blocks touch multiple banks!
3630
3631 @anchor{flash write_bank}
3632 @deffn Command {flash write_bank} num filename offset
3633 Write the binary @file{filename} to flash bank @var{num},
3634 starting at @var{offset} bytes from the beginning of the bank.
3635 The @var{num} parameter is a value shown by @command{flash banks}.
3636 @end deffn
3637
3638 @anchor{flash write_image}
3639 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
3640 Write the image @file{filename} to the current target's flash bank(s).
3641 A relocation @var{offset} may be specified, in which case it is added
3642 to the base address for each section in the image.
3643 The file [@var{type}] can be specified
3644 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
3645 @option{elf} (ELF file), @option{s19} (Motorola s19).
3646 @option{mem}, or @option{builder}.
3647 The relevant flash sectors will be erased prior to programming
3648 if the @option{erase} parameter is given. If @option{unlock} is
3649 provided, then the flash banks are unlocked before erase and
3650 program. The flash bank to use is inferred from the @var{address} of
3651 each image segment.
3652 @end deffn
3653
3654 @section Other Flash commands
3655 @cindex flash protection
3656
3657 @deffn Command {flash erase_check} num
3658 Check erase state of sectors in flash bank @var{num},
3659 and display that status.
3660 The @var{num} parameter is a value shown by @command{flash banks}.
3661 This is the only operation that
3662 updates the erase state information displayed by @option{flash info}. That means you have
3663 to issue a @command{flash erase_check} command after erasing or programming the device
3664 to get updated information.
3665 (Code execution may have invalidated any state records kept by OpenOCD.)
3666 @end deffn
3667
3668 @deffn Command {flash info} num
3669 Print info about flash bank @var{num}
3670 The @var{num} parameter is a value shown by @command{flash banks}.
3671 The information includes per-sector protect status.
3672 @end deffn
3673
3674 @anchor{flash protect}
3675 @deffn Command {flash protect} num first last (@option{on}|@option{off})
3676 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
3677 in flash bank @var{num}, starting at sector @var{first}
3678 and continuing up to and including @var{last}.
3679 Providing a @var{last} sector of @option{last}
3680 specifies "to the end of the flash bank".
3681 The @var{num} parameter is a value shown by @command{flash banks}.
3682 @end deffn
3683
3684 @deffn Command {flash protect_check} num
3685 Check protection state of sectors in flash bank @var{num}.
3686 The @var{num} parameter is a value shown by @command{flash banks}.
3687 @comment @option{flash erase_sector} using the same syntax.
3688 @end deffn
3689
3690 @anchor{Flash Driver List}
3691 @section Flash Driver List
3692 As noted above, the @command{flash bank} command requires a driver name,
3693 and allows driver-specific options and behaviors.
3694 Some drivers also activate driver-specific commands.
3695
3696 @subsection External Flash
3697
3698 @deffn {Flash Driver} cfi
3699 @cindex Common Flash Interface
3700 @cindex CFI
3701 The ``Common Flash Interface'' (CFI) is the main standard for
3702 external NOR flash chips, each of which connects to a
3703 specific external chip select on the CPU.
3704 Frequently the first such chip is used to boot the system.
3705 Your board's @code{reset-init} handler might need to
3706 configure additional chip selects using other commands (like: @command{mww} to
3707 configure a bus and its timings), or
3708 perhaps configure a GPIO pin that controls the ``write protect'' pin
3709 on the flash chip.
3710 The CFI driver can use a target-specific working area to significantly
3711 speed up operation.
3712
3713 The CFI driver can accept the following optional parameters, in any order:
3714
3715 @itemize
3716 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
3717 like AM29LV010 and similar types.
3718 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
3719 @end itemize
3720
3721 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
3722 wide on a sixteen bit bus:
3723
3724 @example
3725 flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
3726 flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
3727 @end example
3728
3729 To configure one bank of 32 MBytes
3730 built from two sixteen bit (two byte) wide parts wired in parallel
3731 to create a thirty-two bit (four byte) bus with doubled throughput:
3732
3733 @example
3734 flash bank cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
3735 @end example
3736
3737 @c "cfi part_id" disabled
3738 @end deffn
3739
3740 @subsection Internal Flash (Microcontrollers)
3741
3742 @deffn {Flash Driver} aduc702x
3743 The ADUC702x analog microcontrollers from Analog Devices
3744 include internal flash and use ARM7TDMI cores.
3745 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
3746 The setup command only requires the @var{target} argument
3747 since all devices in this family have the same memory layout.
3748
3749 @example
3750 flash bank aduc702x 0 0 0 0 $_TARGETNAME
3751 @end example
3752 @end deffn
3753
3754 @deffn {Flash Driver} at91sam3
3755 @cindex at91sam3
3756 All members of the AT91SAM3 microcontroller family from
3757 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
3758 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
3759 that the driver was orginaly developed and tested using the
3760 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
3761 the family was cribbed from the data sheet. @emph{Note to future
3762 readers/updaters: Please remove this worrysome comment after other
3763 chips are confirmed.}
3764
3765 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
3766 have one flash bank. In all cases the flash banks are at
3767 the following fixed locations:
3768
3769 @example
3770 # Flash bank 0 - all chips
3771 flash bank at91sam3 0x00080000 0 1 1 $_TARGETNAME
3772 # Flash bank 1 - only 256K chips
3773 flash bank at91sam3 0x00100000 0 1 1 $_TARGETNAME
3774 @end example
3775
3776 Internally, the AT91SAM3 flash memory is organized as follows.
3777 Unlike the AT91SAM7 chips, these are not used as parameters
3778 to the @command{flash bank} command:
3779
3780 @itemize
3781 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
3782 @item @emph{Bank Size:} 128K/64K Per flash bank
3783 @item @emph{Sectors:} 16 or 8 per bank
3784 @item @emph{SectorSize:} 8K Per Sector
3785 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
3786 @end itemize
3787
3788 The AT91SAM3 driver adds some additional commands:
3789
3790 @deffn Command {at91sam3 gpnvm}
3791 @deffnx Command {at91sam3 gpnvm clear} number
3792 @deffnx Command {at91sam3 gpnvm set} number
3793 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
3794 With no parameters, @command{show} or @command{show all},
3795 shows the status of all GPNVM bits.
3796 With @command{show} @var{number}, displays that bit.
3797
3798 With @command{set} @var{number} or @command{clear} @var{number},
3799 modifies that GPNVM bit.
3800 @end deffn
3801
3802 @deffn Command {at91sam3 info}
3803 This command attempts to display information about the AT91SAM3
3804 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
3805 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
3806 document id: doc6430A] and decodes the values. @emph{Second} it reads the
3807 various clock configuration registers and attempts to display how it
3808 believes the chip is configured. By default, the SLOWCLK is assumed to
3809 be 32768 Hz, see the command @command{at91sam3 slowclk}.
3810 @end deffn
3811
3812 @deffn Command {at91sam3 slowclk} [value]
3813 This command shows/sets the slow clock frequency used in the
3814 @command{at91sam3 info} command calculations above.
3815 @end deffn
3816 @end deffn
3817
3818 @deffn {Flash Driver} at91sam7
3819 All members of the AT91SAM7 microcontroller family from Atmel include
3820 internal flash and use ARM7TDMI cores. The driver automatically
3821 recognizes a number of these chips using the chip identification
3822 register, and autoconfigures itself.
3823
3824 @example
3825 flash bank at91sam7 0 0 0 0 $_TARGETNAME
3826 @end example
3827
3828 For chips which are not recognized by the controller driver, you must
3829 provide additional parameters in the following order:
3830
3831 @itemize
3832 @item @var{chip_model} ... label used with @command{flash info}
3833 @item @var{banks}
3834 @item @var{sectors_per_bank}
3835 @item @var{pages_per_sector}
3836 @item @var{pages_size}
3837 @item @var{num_nvm_bits}
3838 @item @var{freq_khz} ... required if an external clock is provided,
3839 optional (but recommended) when the oscillator frequency is known
3840 @end itemize
3841
3842 It is recommended that you provide zeroes for all of those values
3843 except the clock frequency, so that everything except that frequency
3844 will be autoconfigured.
3845 Knowing the frequency helps ensure correct timings for flash access.
3846
3847 The flash controller handles erases automatically on a page (128/256 byte)
3848 basis, so explicit erase commands are not necessary for flash programming.
3849 However, there is an ``EraseAll`` command that can erase an entire flash
3850 plane (of up to 256KB), and it will be used automatically when you issue
3851 @command{flash erase_sector} or @command{flash erase_address} commands.
3852
3853 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
3854 Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
3855 bit for the processor. Each processor has a number of such bits,
3856 used for controlling features such as brownout detection (so they
3857 are not truly general purpose).
3858 @quotation Note
3859 This assumes that the first flash bank (number 0) is associated with
3860 the appropriate at91sam7 target.
3861 @end quotation
3862 @end deffn
3863 @end deffn
3864
3865 @deffn {Flash Driver} avr
3866 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
3867 @emph{The current implementation is incomplete.}
3868 @comment - defines mass_erase ... pointless given flash_erase_address
3869 @end deffn
3870
3871 @deffn {Flash Driver} ecosflash
3872 @emph{No idea what this is...}
3873 The @var{ecosflash} driver defines one mandatory parameter,
3874 the name of a modules of target code which is downloaded
3875 and executed.
3876 @end deffn
3877
3878 @deffn {Flash Driver} lpc2000
3879 Most members of the LPC1700 and LPC2000 microcontroller families from NXP
3880 include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
3881
3882 @quotation Note
3883 There are LPC2000 devices which are not supported by the @var{lpc2000}
3884 driver:
3885 The LPC2888 is supported by the @var{lpc288x} driver.
3886 The LPC29xx family is supported by the @var{lpc2900} driver.
3887 @end quotation
3888
3889 The @var{lpc2000} driver defines two mandatory and one optional parameters,
3890 which must appear in the following order:
3891
3892 @itemize
3893 @item @var{variant} ... required, may be
3894 @var{lpc2000_v1} (older LPC21xx and LPC22xx)
3895 @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
3896 or @var{lpc1700} (LPC175x and LPC176x)
3897 @item @var{clock_kHz} ... the frequency, in kiloHertz,
3898 at which the core is running
3899 @item @var{calc_checksum} ... optional (but you probably want to provide this!),
3900 telling the driver to calculate a valid checksum for the exception vector table.
3901 @end itemize
3902
3903 LPC flashes don't require the chip and bus width to be specified.
3904
3905 @example
3906 flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
3907 lpc2000_v2 14765 calc_checksum
3908 @end example
3909
3910 @deffn {Command} {lpc2000 part_id} bank
3911 Displays the four byte part identifier associated with
3912 the specified flash @var{bank}.
3913 @end deffn
3914 @end deffn
3915
3916 @deffn {Flash Driver} lpc288x
3917 The LPC2888 microcontroller from NXP needs slightly different flash
3918 support from its lpc2000 siblings.
3919 The @var{lpc288x} driver defines one mandatory parameter,
3920 the programming clock rate in Hz.
3921 LPC flashes don't require the chip and bus width to be specified.
3922
3923 @example
3924 flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
3925 @end example
3926 @end deffn
3927
3928 @deffn {Flash Driver} lpc2900
3929 This driver supports the LPC29xx ARM968E based microcontroller family
3930 from NXP.
3931
3932 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
3933 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
3934 sector layout are auto-configured by the driver.
3935 The driver has one additional mandatory parameter: The CPU clock rate
3936 (in kHz) at the time the flash operations will take place. Most of the time this
3937 will not be the crystal frequency, but a higher PLL frequency. The
3938 @code{reset-init} event handler in the board script is usually the place where
3939 you start the PLL.
3940
3941 The driver rejects flashless devices (currently the LPC2930).
3942
3943 The EEPROM in LPC2900 devices is not mapped directly into the address space.
3944 It must be handled much more like NAND flash memory, and will therefore be
3945 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
3946
3947 Sector protection in terms of the LPC2900 is handled transparently. Every time a
3948 sector needs to be erased or programmed, it is automatically unprotected.
3949 What is shown as protection status in the @code{flash info} command, is
3950 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
3951 sector from ever being erased or programmed again. As this is an irreversible
3952 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
3953 and not by the standard @code{flash protect} command.
3954
3955 Example for a 125 MHz clock frequency:
3956 @example
3957 flash bank lpc2900 0 0 0 0 $_TARGETNAME 125000
3958 @end example
3959
3960 Some @code{lpc2900}-specific commands are defined. In the following command list,
3961 the @var{bank} parameter is the bank number as obtained by the
3962 @code{flash banks} command.
3963
3964 @deffn Command {lpc2900 signature} bank
3965 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
3966 content. This is a hardware feature of the flash block, hence the calculation is
3967 very fast. You may use this to verify the content of a programmed device against
3968 a known signature.
3969 Example:
3970 @example
3971 lpc2900 signature 0
3972 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
3973 @end example
3974 @end deffn
3975
3976 @deffn Command {lpc2900 read_custom} bank filename
3977 Reads the 912 bytes of customer information from the flash index sector, and
3978 saves it to a file in binary format.
3979 Example:
3980 @example
3981 lpc2900 read_custom 0 /path_to/customer_info.bin
3982 @end example
3983 @end deffn
3984
3985 The index sector of the flash is a @emph{write-only} sector. It cannot be
3986 erased! In order to guard against unintentional write access, all following
3987 commands need to be preceeded by a successful call to the @code{password}
3988 command:
3989
3990 @deffn Command {lpc2900 password} bank password
3991 You need to use this command right before each of the following commands:
3992 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
3993 @code{lpc2900 secure_jtag}.
3994
3995 The password string is fixed to "I_know_what_I_am_doing".
3996 Example:
3997 @example
3998 lpc2900 password 0 I_know_what_I_am_doing
3999 Potentially dangerous operation allowed in next command!
4000 @end example
4001 @end deffn
4002
4003 @deffn Command {lpc2900 write_custom} bank filename type
4004 Writes the content of the file into the customer info space of the flash index
4005 sector. The filetype can be specified with the @var{type} field. Possible values
4006 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
4007 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
4008 contain a single section, and the contained data length must be exactly
4009 912 bytes.
4010 @quotation Attention
4011 This cannot be reverted! Be careful!
4012 @end quotation
4013 Example:
4014 @example
4015 lpc2900 write_custom 0 /path_to/customer_info.bin bin
4016 @end example
4017 @end deffn
4018
4019 @deffn Command {lpc2900 secure_sector} bank first last
4020 Secures the sector range from @var{first} to @var{last} (including) against
4021 further program and erase operations. The sector security will be effective
4022 after the next power cycle.
4023 @quotation Attention
4024 This cannot be reverted! Be careful!
4025 @end quotation
4026 Secured sectors appear as @emph{protected} in the @code{flash info} command.
4027 Example:
4028 @example
4029 lpc2900 secure_sector 0 1 1
4030 flash info 0
4031 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
4032 # 0: 0x00000000 (0x2000 8kB) not protected
4033 # 1: 0x00002000 (0x2000 8kB) protected
4034 # 2: 0x00004000 (0x2000 8kB) not protected
4035 @end example
4036 @end deffn
4037
4038 @deffn Command {lpc2900 secure_jtag} bank
4039 Irreversibly disable the JTAG port. The new JTAG security setting will be
4040 effective after the next power cycle.
4041 @quotation Attention
4042 This cannot be reverted! Be careful!
4043 @end quotation
4044 Examples:
4045 @example
4046 lpc2900 secure_jtag 0
4047 @end example
4048 @end deffn
4049 @end deffn
4050
4051 @deffn {Flash Driver} ocl
4052 @emph{No idea what this is, other than using some arm7/arm9 core.}
4053
4054 @example
4055 flash bank ocl 0 0 0 0 $_TARGETNAME
4056 @end example
4057 @end deffn
4058
4059 @deffn {Flash Driver} pic32mx
4060 The PIC32MX microcontrollers are based on the MIPS 4K cores,
4061 and integrate flash memory.
4062 @emph{The current implementation is incomplete.}
4063
4064 @example
4065 flash bank pix32mx 0 0 0 0 $_TARGETNAME
4066 @end example
4067
4068 @comment numerous *disabled* commands are defined:
4069 @comment - chip_erase ... pointless given flash_erase_address
4070 @comment - lock, unlock ... pointless given protect on/off (yes?)
4071 @comment - pgm_word ... shouldn't bank be deduced from address??
4072 Some pic32mx-specific commands are defined:
4073 @deffn Command {pic32mx pgm_word} address value bank
4074 Programs the specified 32-bit @var{value} at the given @var{address}
4075 in the specified chip @var{bank}.
4076 @end deffn
4077 @end deffn
4078
4079 @deffn {Flash Driver} stellaris
4080 All members of the Stellaris LM3Sxxx microcontroller family from
4081 Texas Instruments
4082 include internal flash and use ARM Cortex M3 cores.
4083 The driver automatically recognizes a number of these chips using
4084 the chip identification register, and autoconfigures itself.
4085 @footnote{Currently there is a @command{stellaris mass_erase} command.
4086 That seems pointless since the same effect can be had using the
4087 standard @command{flash erase_address} command.}
4088
4089 @example
4090 flash bank stellaris 0 0 0 0 $_TARGETNAME
4091 @end example
4092 @end deffn
4093
4094 @deffn {Flash Driver} stm32x
4095 All members of the STM32 microcontroller family from ST Microelectronics
4096 include internal flash and use ARM Cortex M3 cores.
4097 The driver automatically recognizes a number of these chips using
4098 the chip identification register, and autoconfigures itself.
4099
4100 @example
4101 flash bank stm32x 0 0 0 0 $_TARGETNAME
4102 @end example
4103
4104 Some stm32x-specific commands
4105 @footnote{Currently there is a @command{stm32x mass_erase} command.
4106 That seems pointless since the same effect can be had using the
4107 standard @command{flash erase_address} command.}
4108 are defined:
4109
4110 @deffn Command {stm32x lock} num
4111 Locks the entire stm32 device.
4112 The @var{num} parameter is a value shown by @command{flash banks}.
4113 @end deffn
4114
4115 @deffn Command {stm32x unlock} num
4116 Unlocks the entire stm32 device.
4117 The @var{num} parameter is a value shown by @command{flash banks}.
4118 @end deffn
4119
4120 @deffn Command {stm32x options_read} num
4121 Read and display the stm32 option bytes written by
4122 the @command{stm32x options_write} command.
4123 The @var{num} parameter is a value shown by @command{flash banks}.
4124 @end deffn
4125
4126 @deffn Command {stm32x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
4127 Writes the stm32 option byte with the specified values.
4128 The @var{num} parameter is a value shown by @command{flash banks}.
4129 @end deffn
4130 @end deffn
4131
4132 @deffn {Flash Driver} str7x
4133 All members of the STR7 microcontroller family from ST Microelectronics
4134 include internal flash and use ARM7TDMI cores.
4135 The @var{str7x} driver defines one mandatory parameter, @var{variant},
4136 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
4137
4138 @example
4139 flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
4140 @end example
4141
4142 @deffn Command {str7x disable_jtag} bank
4143 Activate the Debug/Readout protection mechanism
4144 for the specified flash bank.
4145 @end deffn
4146 @end deffn
4147
4148 @deffn {Flash Driver} str9x
4149 Most members of the STR9 microcontroller family from ST Microelectronics
4150 include internal flash and use ARM966E cores.
4151 The str9 needs the flash controller to be configured using
4152 the @command{str9x flash_config} command prior to Flash programming.
4153
4154 @example
4155 flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
4156 str9x flash_config 0 4 2 0 0x80000
4157 @end example
4158
4159 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
4160 Configures the str9 flash controller.
4161 The @var{num} parameter is a value shown by @command{flash banks}.
4162
4163 @itemize @bullet
4164 @item @var{bbsr} - Boot Bank Size register
4165 @item @var{nbbsr} - Non Boot Bank Size register
4166 @item @var{bbadr} - Boot Bank Start Address register
4167 @item @var{nbbadr} - Boot Bank Start Address register
4168 @end itemize
4169 @end deffn
4170
4171 @end deffn
4172
4173 @deffn {Flash Driver} tms470
4174 Most members of the TMS470 microcontroller family from Texas Instruments
4175 include internal flash and use ARM7TDMI cores.
4176 This driver doesn't require the chip and bus width to be specified.
4177
4178 Some tms470-specific commands are defined:
4179
4180 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
4181 Saves programming keys in a register, to enable flash erase and write commands.
4182 @end deffn
4183
4184 @deffn Command {tms470 osc_mhz} clock_mhz
4185 Reports the clock speed, which is used to calculate timings.
4186 @end deffn
4187
4188 @deffn Command {tms470 plldis} (0|1)
4189 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
4190 the flash clock.
4191 @end deffn
4192 @end deffn
4193
4194 @subsection str9xpec driver
4195 @cindex str9xpec
4196
4197 Here is some background info to help
4198 you better understand how this driver works. OpenOCD has two flash drivers for
4199 the str9:
4200 @enumerate
4201 @item
4202 Standard driver @option{str9x} programmed via the str9 core. Normally used for
4203 flash programming as it is faster than the @option{str9xpec} driver.
4204 @item
4205 Direct programming @option{str9xpec} using the flash controller. This is an
4206 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
4207 core does not need to be running to program using this flash driver. Typical use
4208 for this driver is locking/unlocking the target and programming the option bytes.
4209 @end enumerate
4210
4211 Before we run any commands using the @option{str9xpec} driver we must first disable
4212 the str9 core. This example assumes the @option{str9xpec} driver has been
4213 configured for flash bank 0.
4214 @example
4215 # assert srst, we do not want core running
4216 # while accessing str9xpec flash driver
4217 jtag_reset 0 1
4218 # turn off target polling
4219 poll off
4220 # disable str9 core
4221 str9xpec enable_turbo 0
4222 # read option bytes
4223 str9xpec options_read 0
4224 # re-enable str9 core
4225 str9xpec disable_turbo 0
4226 poll on
4227 reset halt
4228 @end example
4229 The above example will read the str9 option bytes.
4230 When performing a unlock remember that you will not be able to halt the str9 - it
4231 has been locked. Halting the core is not required for the @option{str9xpec} driver
4232 as mentioned above, just issue the commands above manually or from a telnet prompt.
4233
4234 @deffn {Flash Driver} str9xpec
4235 Only use this driver for locking/unlocking the device or configuring the option bytes.
4236 Use the standard str9 driver for programming.
4237 Before using the flash commands the turbo mode must be enabled using the
4238 @command{str9xpec enable_turbo} command.
4239
4240 Several str9xpec-specific commands are defined:
4241
4242 @deffn Command {str9xpec disable_turbo} num
4243 Restore the str9 into JTAG chain.
4244 @end deffn
4245
4246 @deffn Command {str9xpec enable_turbo} num
4247 Enable turbo mode, will simply remove the str9 from the chain and talk
4248 directly to the embedded flash controller.
4249 @end deffn
4250
4251 @deffn Command {str9xpec lock} num
4252 Lock str9 device. The str9 will only respond to an unlock command that will
4253 erase the device.
4254 @end deffn
4255
4256 @deffn Command {str9xpec part_id} num
4257 Prints the part identifier for bank @var{num}.
4258 @end deffn
4259
4260 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
4261 Configure str9 boot bank.
4262 @end deffn
4263
4264 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
4265 Configure str9 lvd source.
4266 @end deffn
4267
4268 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
4269 Configure str9 lvd threshold.
4270 @end deffn
4271
4272 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
4273 Configure str9 lvd reset warning source.
4274 @end deffn
4275
4276 @deffn Command {str9xpec options_read} num
4277 Read str9 option bytes.
4278 @end deffn
4279
4280 @deffn Command {str9xpec options_write} num
4281 Write str9 option bytes.
4282 @end deffn
4283
4284 @deffn Command {str9xpec unlock} num
4285 unlock str9 device.
4286 @end deffn
4287
4288 @end deffn
4289
4290
4291 @section mFlash
4292
4293 @subsection mFlash Configuration
4294 @cindex mFlash Configuration
4295
4296 @deffn {Config Command} {mflash bank} soc base RST_pin target
4297 Configures a mflash for @var{soc} host bank at
4298 address @var{base}.
4299 The pin number format depends on the host GPIO naming convention.
4300 Currently, the mflash driver supports s3c2440 and pxa270.
4301
4302 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
4303
4304 @example
4305 mflash bank s3c2440 0x10000000 1b 0
4306 @end example
4307
4308 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
4309
4310 @example
4311 mflash bank pxa270 0x08000000 43 0
4312 @end example
4313 @end deffn
4314
4315 @subsection mFlash commands
4316 @cindex mFlash commands
4317
4318 @deffn Command {mflash config pll} frequency
4319 Configure mflash PLL.
4320 The @var{frequency} is the mflash input frequency, in Hz.
4321 Issuing this command will erase mflash's whole internal nand and write new pll.
4322 After this command, mflash needs power-on-reset for normal operation.
4323 If pll was newly configured, storage and boot(optional) info also need to be update.
4324 @end deffn
4325
4326 @deffn Command {mflash config boot}
4327 Configure bootable option.
4328 If bootable option is set, mflash offer the first 8 sectors
4329 (4kB) for boot.
4330 @end deffn
4331
4332 @deffn Command {mflash config storage}
4333 Configure storage information.
4334 For the normal storage operation, this information must be
4335 written.
4336 @end deffn
4337
4338 @deffn Command {mflash dump} num filename offset size
4339 Dump @var{size} bytes, starting at @var{offset} bytes from the
4340 beginning of the bank @var{num}, to the file named @var{filename}.
4341 @end deffn
4342
4343 @deffn Command {mflash probe}
4344 Probe mflash.
4345 @end deffn
4346
4347 @deffn Command {mflash write} num filename offset
4348 Write the binary file @var{filename} to mflash bank @var{num}, starting at
4349 @var{offset} bytes from the beginning of the bank.
4350 @end deffn
4351
4352 @node NAND Flash Commands
4353 @chapter NAND Flash Commands
4354 @cindex NAND
4355
4356 Compared to NOR or SPI flash, NAND devices are inexpensive
4357 and high density. Today's NAND chips, and multi-chip modules,
4358 commonly hold multiple GigaBytes of data.
4359
4360 NAND chips consist of a number of ``erase blocks'' of a given
4361 size (such as 128 KBytes), each of which is divided into a
4362 number of pages (of perhaps 512 or 2048 bytes each). Each
4363 page of a NAND flash has an ``out of band'' (OOB) area to hold
4364 Error Correcting Code (ECC) and other metadata, usually 16 bytes
4365 of OOB for every 512 bytes of page data.
4366
4367 One key characteristic of NAND flash is that its error rate
4368 is higher than that of NOR flash. In normal operation, that
4369 ECC is used to correct and detect errors. However, NAND
4370 blocks can also wear out and become unusable; those blocks
4371 are then marked "bad". NAND chips are even shipped from the
4372 manufacturer with a few bad blocks. The highest density chips
4373 use a technology (MLC) that wears out more quickly, so ECC
4374 support is increasingly important as a way to detect blocks
4375 that have begun to fail, and help to preserve data integrity
4376 with techniques such as wear leveling.
4377
4378 Software is used to manage the ECC. Some controllers don't
4379 support ECC directly; in those cases, software ECC is used.
4380 Other controllers speed up the ECC calculations with hardware.
4381 Single-bit error correction hardware is routine. Controllers
4382 geared for newer MLC chips may correct 4 or more errors for
4383 every 512 bytes of data.
4384
4385 You will need to make sure that any data you write using
4386 OpenOCD includes the apppropriate kind of ECC. For example,
4387 that may mean passing the @code{oob_softecc} flag when
4388 writing NAND data, or ensuring that the correct hardware
4389 ECC mode is used.
4390
4391 The basic steps for using NAND devices include:
4392 @enumerate
4393 @item Declare via the command @command{nand device}
4394 @* Do this in a board-specific configuration file,
4395 passing parameters as needed by the controller.
4396 @item Configure each device using @command{nand probe}.
4397 @* Do this only after the associated target is set up,
4398 such as in its reset-init script or in procures defined
4399 to access that device.
4400 @item Operate on the flash via @command{nand subcommand}
4401 @* Often commands to manipulate the flash are typed by a human, or run
4402 via a script in some automated way. Common task include writing a
4403 boot loader, operating system, or other data needed to initialize or
4404 de-brick a board.
4405 @end enumerate
4406
4407 @b{NOTE:} At the time this text was written, the largest NAND
4408 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
4409 This is because the variables used to hold offsets and lengths
4410 are only 32 bits wide.
4411 (Larger chips may work in some cases, unless an offset or length
4412 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
4413 Some larger devices will work, since they are actually multi-chip
4414 modules with two smaller chips and individual chipselect lines.
4415
4416 @anchor{NAND Configuration}
4417 @section NAND Configuration Commands
4418 @cindex NAND configuration
4419
4420 NAND chips must be declared in configuration scripts,
4421 plus some additional configuration that's done after
4422 OpenOCD has initialized.
4423
4424 @deffn {Config Command} {nand device} controller target [configparams...]
4425 Declares a NAND device, which can be read and written to
4426 after it has been configured through @command{nand probe}.
4427 In OpenOCD, devices are single chips; this is unlike some
4428 operating systems, which may manage multiple chips as if
4429 they were a single (larger) device.
4430 In some cases, configuring a device will activate extra
4431 commands; see the controller-specific documentation.
4432
4433 @b{NOTE:} This command is not available after OpenOCD
4434 initialization has completed. Use it in board specific
4435 configuration files, not interactively.
4436
4437 @itemize @bullet
4438 @item @var{controller} ... identifies the controller driver
4439 associated with the NAND device being declared.
4440 @xref{NAND Driver List}.
4441 @item @var{target} ... names the target used when issuing
4442 commands to the NAND controller.
4443 @comment Actually, it's currently a controller-specific parameter...
4444 @item @var{configparams} ... controllers may support, or require,
4445 additional parameters. See the controller-specific documentation
4446 for more information.
4447 @end itemize
4448 @end deffn
4449
4450 @deffn Command {nand list}
4451 Prints a summary of each device declared
4452 using @command{nand device}, numbered from zero.
4453 Note that un-probed devices show no details.
4454 @example
4455 > nand list
4456 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
4457 blocksize: 131072, blocks: 8192
4458 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
4459 blocksize: 131072, blocks: 8192
4460 >
4461 @end example
4462 @end deffn
4463
4464 @deffn Command {nand probe} num
4465 Probes the specified device to determine key characteristics
4466 like its page and block sizes, and how many blocks it has.
4467 The @var{num} parameter is the value shown by @command{nand list}.
4468 You must (successfully) probe a device before you can use
4469 it with most other NAND commands.
4470 @end deffn
4471
4472 @section Erasing, Reading, Writing to NAND Flash
4473
4474 @deffn Command {nand dump} num filename offset length [oob_option]
4475 @cindex NAND reading
4476 Reads binary data from the NAND device and writes it to the file,
4477 starting at the specified offset.
4478 The @var{num} parameter is the value shown by @command{nand list}.
4479
4480 Use a complete path name for @var{filename}, so you don't depend
4481 on the directory used to start the OpenOCD server.
4482
4483 The @var{offset} and @var{length} must be exact multiples of the
4484 device's page size. They describe a data region; the OOB data
4485 associated with each such page may also be accessed.
4486
4487 @b{NOTE:} At the time this text was written, no error correction
4488 was done on the data that's read, unless raw access was disabled
4489 and the underlying NAND controller driver had a @code{read_page}
4490 method which handled that error correction.
4491
4492 By default, only page data is saved to the specified file.
4493 Use an @var{oob_option} parameter to save OOB data:
4494 @itemize @bullet
4495 @item no oob_* parameter
4496 @*Output file holds only page data; OOB is discarded.
4497 @item @code{oob_raw}
4498 @*Output file interleaves page data and OOB data;
4499 the file will be longer than "length" by the size of the
4500 spare areas associated with each data page.
4501 Note that this kind of "raw" access is different from
4502 what's implied by @command{nand raw_access}, which just
4503 controls whether a hardware-aware access method is used.
4504 @item @code{oob_only}
4505 @*Output file has only raw OOB data, and will
4506 be smaller than "length" since it will contain only the
4507 spare areas associated with each data page.
4508 @end itemize
4509 @end deffn
4510
4511 @deffn Command {nand erase} num [offset length]
4512 @cindex NAND erasing
4513 @cindex NAND programming
4514 Erases blocks on the specified NAND device, starting at the
4515 specified @var{offset} and continuing for @var{length} bytes.
4516 Both of those values must be exact multiples of the device's
4517 block size, and the region they specify must fit entirely in the chip.
4518 If those parameters are not specified,
4519 the whole NAND chip will be erased.
4520 The @var{num} parameter is the value shown by @command{nand list}.
4521
4522 @b{NOTE:} This command will try to erase bad blocks, when told
4523 to do so, which will probably invalidate the manufacturer's bad
4524 block marker.
4525 For the remainder of the current server session, @command{nand info}
4526 will still report that the block ``is'' bad.
4527 @end deffn
4528
4529 @deffn Command {nand write} num filename offset [option...]
4530 @cindex NAND writing
4531 @cindex NAND programming
4532 Writes binary data from the file into the specified NAND device,
4533 starting at the specified offset. Those pages should already
4534 have been erased; you can't change zero bits to one bits.
4535 The @var{num} parameter is the value shown by @command{nand list}.
4536
4537 Use a complete path name for @var{filename}, so you don't depend
4538 on the directory used to start the OpenOCD server.
4539
4540 The @var{offset} must be an exact multiple of the device's page size.
4541 All data in the file will be written, assuming it doesn't run
4542 past the end of the device.
4543 Only full pages are written, and any extra space in the last
4544 page will be filled with 0xff bytes. (That includes OOB data,
4545 if that's being written.)
4546
4547 @b{NOTE:} At the time this text was written, bad blocks are
4548 ignored. That is, this routine will not skip bad blocks,
4549 but will instead try to write them. This can cause problems.
4550
4551 Provide at most one @var{option} parameter. With some
4552 NAND drivers, the meanings of these parameters may change
4553 if @command{nand raw_access} was used to disable hardware ECC.
4554 @itemize @bullet
4555 @item no oob_* parameter
4556 @*File has only page data, which is written.
4557 If raw acccess is in use, the OOB area will not be written.
4558 Otherwise, if the underlying NAND controller driver has
4559 a @code{write_page} routine, that routine may write the OOB
4560 with hardware-computed ECC data.
4561 @item @code{oob_only}
4562 @*File has only raw OOB data, which is written to the OOB area.
4563 Each page's data area stays untouched. @i{This can be a dangerous
4564 option}, since it can invalidate the ECC data.
4565 You may need to force raw access to use this mode.
4566 @item @code{oob_raw}
4567 @*File interleaves data and OOB data, both of which are written
4568 If raw access is enabled, the data is written first, then the
4569 un-altered OOB.
4570 Otherwise, if the underlying NAND controller driver has
4571 a @code{write_page} routine, that routine may modify the OOB
4572 before it's written, to include hardware-computed ECC data.
4573 @item @code{oob_softecc}
4574 @*File has only page data, which is written.
4575 The OOB area is filled with 0xff, except for a standard 1-bit
4576 software ECC code stored in conventional locations.
4577 You might need to force raw access to use this mode, to prevent
4578 the underlying driver from applying hardware ECC.
4579 @item @code{oob_softecc_kw}
4580 @*File has only page data, which is written.
4581 The OOB area is filled with 0xff, except for a 4-bit software ECC
4582 specific to the boot ROM in Marvell Kirkwood SoCs.
4583 You might need to force raw access to use this mode, to prevent
4584 the underlying driver from applying hardware ECC.
4585 @end itemize
4586 @end deffn
4587
4588 @section Other NAND commands
4589 @cindex NAND other commands
4590
4591 @deffn Command {nand check_bad_blocks} [offset length]
4592 Checks for manufacturer bad block markers on the specified NAND
4593 device. If no parameters are provided, checks the whole
4594 device; otherwise, starts at the specified @var{offset} and
4595 continues for @var{length} bytes.
4596 Both of those values must be exact multiples of the device's
4597 block size, and the region they specify must fit entirely in the chip.
4598 The @var{num} parameter is the value shown by @command{nand list}.
4599
4600 @b{NOTE:} Before using this command you should force raw access
4601 with @command{nand raw_access enable} to ensure that the underlying
4602 driver will not try to apply hardware ECC.
4603 @end deffn
4604
4605 @deffn Command {nand info} num
4606 The @var{num} parameter is the value shown by @command{nand list}.
4607 This prints the one-line summary from "nand list", plus for
4608 devices which have been probed this also prints any known
4609 status for each block.
4610 @end deffn
4611
4612 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
4613 Sets or clears an flag affecting how page I/O is done.
4614 The @var{num} parameter is the value shown by @command{nand list}.
4615
4616 This flag is cleared (disabled) by default, but changing that
4617 value won't affect all NAND devices. The key factor is whether
4618 the underlying driver provides @code{read_page} or @code{write_page}
4619 methods. If it doesn't provide those methods, the setting of
4620 this flag is irrelevant; all access is effectively ``raw''.
4621
4622 When those methods exist, they are normally used when reading
4623 data (@command{nand dump} or reading bad block markers) or
4624 writing it (@command{nand write}). However, enabling
4625 raw access (setting the flag) prevents use of those methods,
4626 bypassing hardware ECC logic.
4627 @i{This can be a dangerous option}, since writing blocks
4628 with the wrong ECC data can cause them to be marked as bad.
4629 @end deffn
4630
4631 @anchor{NAND Driver List}
4632 @section NAND Driver List
4633 As noted above, the @command{nand device} command allows
4634 driver-specific options and behaviors.
4635 Some controllers also activate controller-specific commands.
4636
4637 @deffn {NAND Driver} davinci
4638 This driver handles the NAND controllers found on DaVinci family
4639 chips from Texas Instruments.
4640 It takes three extra parameters:
4641 address of the NAND chip;
4642 hardware ECC mode to use (@option{hwecc1},
4643 @option{hwecc4}, @option{hwecc4_infix});
4644 address of the AEMIF controller on this processor.
4645 @example
4646 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
4647 @end example
4648 All DaVinci processors support the single-bit ECC hardware,
4649 and newer ones also support the four-bit ECC hardware.
4650 The @code{write_page} and @code{read_page} methods are used
4651 to implement those ECC modes, unless they are disabled using
4652 the @command{nand raw_access} command.
4653 @end deffn
4654
4655 @deffn {NAND Driver} lpc3180
4656 These controllers require an extra @command{nand device}
4657 parameter: the clock rate used by the controller.
4658 @deffn Command {lpc3180 select} num [mlc|slc]
4659 Configures use of the MLC or SLC controller mode.
4660 MLC implies use of hardware ECC.
4661 The @var{num} parameter is the value shown by @command{nand list}.
4662 @end deffn
4663
4664 At this writing, this driver includes @code{write_page}
4665 and @code{read_page} methods. Using @command{nand raw_access}
4666 to disable those methods will prevent use of hardware ECC
4667 in the MLC controller mode, but won't change SLC behavior.
4668 @end deffn
4669 @comment current lpc3180 code won't issue 5-byte address cycles
4670
4671 @deffn {NAND Driver} orion
4672 These controllers require an extra @command{nand device}
4673 parameter: the address of the controller.
4674 @example
4675 nand device orion 0xd8000000
4676 @end example
4677 These controllers don't define any specialized commands.
4678 At this writing, their drivers don't include @code{write_page}
4679 or @code{read_page} methods, so @command{nand raw_access} won't
4680 change any behavior.
4681 @end deffn
4682
4683 @deffn {NAND Driver} s3c2410
4684 @deffnx {NAND Driver} s3c2412
4685 @deffnx {NAND Driver} s3c2440
4686 @deffnx {NAND Driver} s3c2443
4687 These S3C24xx family controllers don't have any special
4688 @command{nand device} options, and don't define any
4689 specialized commands.
4690 At this writing, their drivers don't include @code{write_page}
4691 or @code{read_page} methods, so @command{nand raw_access} won't
4692 change any behavior.
4693 @end deffn
4694
4695 @node PLD/FPGA Commands
4696 @chapter PLD/FPGA Commands
4697 @cindex PLD
4698 @cindex FPGA
4699
4700 Programmable Logic Devices (PLDs) and the more flexible
4701 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
4702 OpenOCD can support programming them.
4703 Although PLDs are generally restrictive (cells are less functional, and
4704 there are no special purpose cells for memory or computational tasks),
4705 they share the same OpenOCD infrastructure.
4706 Accordingly, both are called PLDs here.
4707
4708 @section PLD/FPGA Configuration and Commands
4709
4710 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
4711 OpenOCD maintains a list of PLDs available for use in various commands.
4712 Also, each such PLD requires a driver.
4713
4714 They are referenced by the number shown by the @command{pld devices} command,
4715 and new PLDs are defined by @command{pld device driver_name}.
4716
4717 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
4718 Defines a new PLD device, supported by driver @var{driver_name},
4719 using the TAP named @var{tap_name}.
4720 The driver may make use of any @var{driver_options} to configure its
4721 behavior.
4722 @end deffn
4723
4724 @deffn {Command} {pld devices}
4725 Lists the PLDs and their numbers.
4726 @end deffn
4727
4728 @deffn {Command} {pld load} num filename
4729 Loads the file @file{filename} into the PLD identified by @var{num}.
4730 The file format must be inferred by the driver.
4731 @end deffn
4732
4733 @section PLD/FPGA Drivers, Options, and Commands
4734
4735 Drivers may support PLD-specific options to the @command{pld device}
4736 definition command, and may also define commands usable only with
4737 that particular type of PLD.
4738
4739 @deffn {FPGA Driver} virtex2
4740 Virtex-II is a family of FPGAs sold by Xilinx.
4741 It supports the IEEE 1532 standard for In-System Configuration (ISC).
4742 No driver-specific PLD definition options are used,
4743 and one driver-specific command is defined.
4744
4745 @deffn {Command} {virtex2 read_stat} num
4746 Reads and displays the Virtex-II status register (STAT)
4747 for FPGA @var{num}.
4748 @end deffn
4749 @end deffn
4750
4751 @node General Commands
4752 @chapter General Commands
4753 @cindex commands
4754
4755 The commands documented in this chapter here are common commands that
4756 you, as a human, may want to type and see the output of. Configuration type
4757 commands are documented elsewhere.
4758
4759 Intent:
4760 @itemize @bullet
4761 @item @b{Source Of Commands}
4762 @* OpenOCD commands can occur in a configuration script (discussed
4763 elsewhere) or typed manually by a human or supplied programatically,
4764 or via one of several TCP/IP Ports.
4765
4766 @item @b{From the human}
4767 @* A human should interact with the telnet interface (default port: 4444)
4768 or via GDB (default port 3333).
4769
4770 To issue commands from within a GDB session, use the @option{monitor}
4771 command, e.g. use @option{monitor poll} to issue the @option{poll}
4772 command. All output is relayed through the GDB session.
4773
4774 @item @b{Machine Interface}
4775 The Tcl interface's intent is to be a machine interface. The default Tcl
4776 port is 5555.
4777 @end itemize
4778
4779
4780 @section Daemon Commands
4781
4782 @deffn {Command} exit
4783 Exits the current telnet session.
4784 @end deffn
4785
4786 @c note EXTREMELY ANNOYING word wrap at column 75
4787 @c even when lines are e.g. 100+ columns ...
4788 @c coded in startup.tcl
4789 @deffn {Command} help [string]
4790 With no parameters, prints help text for all commands.
4791 Otherwise, prints each helptext containing @var{string}.
4792 Not every command provides helptext.
4793 @end deffn
4794
4795 @deffn Command sleep msec [@option{busy}]
4796 Wait for at least @var{msec} milliseconds before resuming.
4797 If @option{busy} is passed, busy-wait instead of sleeping.
4798 (This option is strongly discouraged.)
4799 Useful in connection with script files
4800 (@command{script} command and @command{target_name} configuration).
4801 @end deffn
4802
4803 @deffn Command shutdown
4804 Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
4805 @end deffn
4806
4807 @anchor{debug_level}
4808 @deffn Command debug_level [n]
4809 @cindex message level
4810 Display debug level.
4811 If @var{n} (from 0..3) is provided, then set it to that level.
4812 This affects the kind of messages sent to the server log.
4813 Level 0 is error messages only;
4814 level 1 adds warnings;
4815 level 2 adds informational messages;
4816 and level 3 adds debugging messages.
4817 The default is level 2, but that can be overridden on
4818 the command line along with the location of that log
4819 file (which is normally the server's standard output).
4820 @xref{Running}.
4821 @end deffn
4822
4823 @deffn Command fast (@option{enable}|@option{disable})
4824 Default disabled.
4825 Set default behaviour of OpenOCD to be "fast and dangerous".
4826
4827 At this writing, this only affects the defaults for two ARM7/ARM9 parameters:
4828 fast memory access, and DCC downloads. Those parameters may still be
4829 individually overridden.
4830
4831 The target specific "dangerous" optimisation tweaking options may come and go
4832 as more robust and user friendly ways are found to ensure maximum throughput
4833 and robustness with a minimum of configuration.
4834
4835 Typically the "fast enable" is specified first on the command line:
4836
4837 @example
4838 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
4839 @end example
4840 @end deffn
4841
4842 @deffn Command echo message
4843 Logs a message at "user" priority.
4844 Output @var{message} to stdout.
4845 @example
4846 echo "Downloading kernel -- please wait"
4847 @end example
4848 @end deffn
4849
4850 @deffn Command log_output [filename]
4851 Redirect logging to @var{filename};
4852 the initial log output channel is stderr.
4853 @end deffn
4854
4855 @anchor{Target State handling}
4856 @section Target State handling
4857 @cindex reset
4858 @cindex halt
4859 @cindex target initialization
4860
4861 In this section ``target'' refers to a CPU configured as
4862 shown earlier (@pxref{CPU Configuration}).
4863 These commands, like many, implicitly refer to
4864 a current target which is used to perform the
4865 various operations. The current target may be changed
4866 by using @command{targets} command with the name of the
4867 target which should become current.
4868
4869 @deffn Command reg [(number|name) [value]]
4870 Access a single register by @var{number} or by its @var{name}.
4871
4872 @emph{With no arguments}:
4873 list all available registers for the current target,
4874 showing number, name, size, value, and cache status.
4875
4876 @emph{With number/name}: display that register's value.
4877
4878 @emph{With both number/name and value}: set register's value.
4879
4880 Cores may have surprisingly many registers in their
4881 Debug and trace infrastructure:
4882
4883 @example
4884 > reg
4885 (0) r0 (/32): 0x0000D3C2 (dirty: 1, valid: 1)
4886 (1) r1 (/32): 0xFD61F31C (dirty: 0, valid: 1)
4887 (2) r2 (/32): 0x00022551 (dirty: 0, valid: 1)
4888 ...
4889 (164) ETM_CONTEXTID_COMPARATOR_MASK (/32): \
4890 0x00000000 (dirty: 0, valid: 0)
4891 >
4892 @end example
4893 @end deffn
4894
4895 @deffn Command halt [ms]
4896 @deffnx Command wait_halt [ms]
4897 The @command{halt} command first sends a halt request to the target,
4898 which @command{wait_halt} doesn't.
4899 Otherwise these behave the same: wait up to @var{ms} milliseconds,
4900 or 5 seconds if there is no parameter, for the target to halt
4901 (and enter debug mode).
4902 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
4903
4904 @quotation Warning
4905 On ARM cores, software using the @emph{wait for interrupt} operation
4906 often blocks the JTAG access needed by a @command{halt} command.
4907 This is because that operation also puts the core into a low
4908 power mode by gating the core clock;
4909 but the core clock is needed to detect JTAG clock transitions.
4910
4911 One partial workaround uses adaptive clocking: when the core is
4912 interrupted the operation completes, then JTAG clocks are accepted
4913 at least until the interrupt handler completes.
4914 However, this workaround is often unusable since the processor, board,
4915 and JTAG adapter must all support adaptive JTAG clocking.
4916 Also, it can't work until an interrupt is issued.
4917
4918 A more complete workaround is to not use that operation while you
4919 work with a JTAG debugger.
4920 Tasking environments generaly have idle loops where the body is the
4921 @emph{wait for interrupt} operation.
4922 (On older cores, it is a coprocessor action;
4923 newer cores have a @option{wfi} instruction.)
4924 Such loops can just remove that operation, at the cost of higher
4925 power consumption (because the CPU is needlessly clocked).
4926 @end quotation
4927
4928 @end deffn
4929
4930 @deffn Command resume [address]
4931 Resume the target at its current code position,
4932 or the optional @var{address} if it is provided.
4933 OpenOCD will wait 5 seconds for the target to resume.
4934 @end deffn
4935
4936 @deffn Command step [address]
4937 Single-step the target at its current code position,
4938 or the optional @var{address} if it is provided.
4939 @end deffn
4940
4941 @anchor{Reset Command}
4942 @deffn Command reset
4943 @deffnx Command {reset run}
4944 @deffnx Command {reset halt}
4945 @deffnx Command {reset init}
4946 Perform as hard a reset as possible, using SRST if possible.
4947 @emph{All defined targets will be reset, and target
4948 events will fire during the reset sequence.}
4949
4950 The optional parameter specifies what should
4951 happen after the reset.
4952 If there is no parameter, a @command{reset run} is executed.
4953 The other options will not work on all systems.
4954 @xref{Reset Configuration}.
4955
4956 @itemize @minus
4957 @item @b{run} Let the target run
4958 @item @b{halt} Immediately halt the target
4959 @item @b{init} Immediately halt the target, and execute the reset-init script
4960 @end itemize
4961 @end deffn
4962
4963 @deffn Command soft_reset_halt
4964 Requesting target halt and executing a soft reset. This is often used
4965 when a target cannot be reset and halted. The target, after reset is
4966 released begins to execute code. OpenOCD attempts to stop the CPU and
4967 then sets the program counter back to the reset vector. Unfortunately
4968 the code that was executed may have left the hardware in an unknown
4969 state.
4970 @end deffn
4971
4972 @section I/O Utilities
4973
4974 These commands are available when
4975 OpenOCD is built with @option{--enable-ioutil}.
4976 They are mainly useful on embedded targets,
4977 notably the ZY1000.
4978 Hosts with operating systems have complementary tools.
4979
4980 @emph{Note:} there are several more such commands.
4981
4982 @deffn Command append_file filename [string]*
4983 Appends the @var{string} parameters to
4984 the text file @file{filename}.
4985 Each string except the last one is followed by one space.
4986 The last string is followed by a newline.
4987 @end deffn
4988
4989 @deffn Command cat filename
4990 Reads and displays the text file @file{filename}.
4991 @end deffn
4992
4993 @deffn Command cp src_filename dest_filename
4994 Copies contents from the file @file{src_filename}
4995 into @file{dest_filename}.
4996 @end deffn
4997
4998 @deffn Command ip
4999 @emph{No description provided.}
5000 @end deffn
5001
5002 @deffn Command ls
5003 @emph{No description provided.}
5004 @end deffn
5005
5006 @deffn Command mac
5007 @emph{No description provided.}
5008 @end deffn
5009
5010 @deffn Command meminfo
5011 Display available RAM memory on OpenOCD host.
5012 Used in OpenOCD regression testing scripts.
5013 @end deffn
5014
5015 @deffn Command peek
5016 @emph{No description provided.}
5017 @end deffn
5018
5019 @deffn Command poke
5020 @emph{No description provided.}
5021 @end deffn
5022
5023 @deffn Command rm filename
5024 @c "rm" has both normal and Jim-level versions??
5025 Unlinks the file @file{filename}.
5026 @end deffn
5027
5028 @deffn Command trunc filename
5029 Removes all data in the file @file{filename}.
5030 @end deffn
5031
5032 @anchor{Memory access}
5033 @section Memory access commands
5034 @cindex memory access
5035
5036 These commands allow accesses of a specific size to the memory
5037 system. Often these are used to configure the current target in some
5038 special way. For example - one may need to write certain values to the
5039 SDRAM controller to enable SDRAM.
5040
5041 @enumerate
5042 @item Use the @command{targets} (plural) command
5043 to change the current target.
5044 @item In system level scripts these commands are deprecated.
5045 Please use their TARGET object siblings to avoid making assumptions
5046 about what TAP is the current target, or about MMU configuration.
5047 @end enumerate
5048
5049 @deffn Command mdw [phys] addr [count]
5050 @deffnx Command mdh [phys] addr [count]
5051 @deffnx Command mdb [phys] addr [count]
5052 Display contents of address @var{addr}, as
5053 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
5054 or 8-bit bytes (@command{mdb}).
5055 If @var{count} is specified, displays that many units.
5056 @var{phys} is an optional flag to indicate to use
5057 physical address and bypass MMU
5058 (If you want to manipulate the data instead of displaying it,
5059 see the @code{mem2array} primitives.)
5060 @end deffn
5061
5062 @deffn Command mww [phys] addr word
5063 @deffnx Command mwh [phys] addr halfword
5064 @deffnx Command mwb [phys] addr byte
5065 Writes the specified @var{word} (32 bits),
5066 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5067 at the specified address @var{addr}.
5068 @var{phys} is an optional flag to indicate to use
5069 physical address and bypass MMU
5070 @end deffn
5071
5072
5073 @anchor{Image access}
5074 @section Image loading commands
5075 @cindex image loading
5076 @cindex image dumping
5077
5078 @anchor{dump_image}
5079 @deffn Command {dump_image} filename address size
5080 Dump @var{size} bytes of target memory starting at @var{address} to the
5081 binary file named @var{filename}.
5082 @end deffn
5083
5084 @deffn Command {fast_load}
5085 Loads an image stored in memory by @command{fast_load_image} to the
5086 current target. Must be preceeded by fast_load_image.
5087 @end deffn
5088
5089 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
5090 Normally you should be using @command{load_image} or GDB load. However, for
5091 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
5092 host), storing the image in memory and uploading the image to the target
5093 can be a way to upload e.g. multiple debug sessions when the binary does not change.
5094 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
5095 memory, i.e. does not affect target. This approach is also useful when profiling
5096 target programming performance as I/O and target programming can easily be profiled
5097 separately.
5098 @end deffn
5099
5100 @anchor{load_image}
5101 @deffn Command {load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
5102 Load image from file @var{filename} to target memory at @var{address}.
5103 The file format may optionally be specified
5104 (@option{bin}, @option{ihex}, or @option{elf})
5105 @end deffn
5106
5107 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
5108 Displays image section sizes and addresses
5109 as if @var{filename} were loaded into target memory
5110 starting at @var{address} (defaults to zero).
5111 The file format may optionally be specified
5112 (@option{bin}, @option{ihex}, or @option{elf})
5113 @end deffn
5114
5115 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
5116 Verify @var{filename} against target memory starting at @var{address}.
5117 The file format may optionally be specified