[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * NAND Flash Commands:: NAND Flash Commands
77 * PLD/FPGA Commands:: PLD/FPGA Commands
78 * General Commands:: General Commands
79 * Architecture and Core Commands:: Architecture and Core Commands
80 * JTAG Commands:: JTAG Commands
81 * Boundary Scan Commands:: Boundary Scan Commands
82 * TFTP:: TFTP
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
95 @end menu
97 @node About
98 @unnumbered About
99 @cindex about
101 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
102 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
105 around the world.
107 @section What is OpenOCD?
108 @cindex TAP
109 @cindex JTAG
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
113 devices.
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board can be directly connected to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
140 scan operations.
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD only supports
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
154 based, parallel port based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
159 Cortex-M3 (Stellaris LM3, ST STM32 and Energy Micro EFM32) based cores to be
160 debugged via the GDB protocol.
162 @b{Flash Programing:} Flash writing is supported for external CFI
163 compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) controller is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{http://openocd.sourceforge.net/}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{http://openocd.sourceforge.net/doc/html/index.html}
182 PDF form is likewise published at:
184 @uref{http://openocd.sourceforge.net/doc/pdf/openocd.pdf}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
203 @section OpenOCD IRC
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
208 @node Developers
209 @chapter OpenOCD Developer Resources
210 @cindex developers
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD GIT Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a GIT repository hosted at SourceForge. The repository URL is:
225 @uref{git://git.code.sf.net/p/openocd/code}
227 or via http
229 @uref{http://git.code.sf.net/p/openocd/code}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{http://repo.or.cz/r/openocd.git}
235 With standard GIT tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a GIT client:
241 @uref{http://repo.or.cz/w/openocd.git}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{http://openocd.sourceforge.net/doc/doxygen/html/index.html}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration in the top of the source tree.
264 @section OpenOCD Developer Mailing List
266 The OpenOCD Developer Mailing List provides the primary means of
267 communication between developers:
269 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
271 Discuss and submit patches to this list.
272 The @file{HACKING} file contains basic information about how
273 to prepare patches.
275 @section OpenOCD Bug Database
277 During the 0.4.x release cycle the OpenOCD project team began
278 using Trac for its bug database:
280 @uref{https://sourceforge.net/apps/trac/openocd}
283 @node Debug Adapter Hardware
284 @chapter Debug Adapter Hardware
285 @cindex dongles
286 @cindex FTDI
287 @cindex wiggler
288 @cindex zy1000
289 @cindex printer port
290 @cindex USB Adapter
291 @cindex RTCK
293 Defined: @b{dongle}: A small device that plugins into a computer and serves as
294 an adapter .... [snip]
296 In the OpenOCD case, this generally refers to @b{a small adapter} that
297 attaches to your computer via USB or the Parallel Printer Port. One
298 exception is the Zylin ZY1000, packaged as a small box you attach via
299 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
300 require any drivers to be installed on the developer PC. It also has
301 a built in web interface. It supports RTCK/RCLK or adaptive clocking
302 and has a built in relay to power cycle targets remotely.
305 @section Choosing a Dongle
307 There are several things you should keep in mind when choosing a dongle.
309 @enumerate
310 @item @b{Transport} Does it support the kind of communication that you need?
311 OpenOCD focusses mostly on JTAG. Your version may also support
312 other ways to communicate with target devices.
313 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
314 Does your dongle support it? You might need a level converter.
315 @item @b{Pinout} What pinout does your target board use?
316 Does your dongle support it? You may be able to use jumper
317 wires, or an "octopus" connector, to convert pinouts.
318 @item @b{Connection} Does your computer have the USB, printer, or
319 Ethernet port needed?
320 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
321 RTCK support? Also known as ``adaptive clocking''
322 @end enumerate
324 @section Stand-alone JTAG Probe
326 The ZY1000 from Ultimate Solutions is technically not a dongle but a
327 stand-alone JTAG probe that unlikemost dongles doesn’t require any drivers
328 running on the developers host computer.
329 Once installed on a network using DHCP or a static IP assignment, users can
330 access the ZY1000 probe locally or remotely from any host with access to the
331 IP address assigned to the probe.
332 The ZY1000 provides an intuitive web interface with direct access to the
333 OpenOCD debugger.
334 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
335 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
336 the target.
337 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
338 to power cycle the target remotely.
340 For more information, visit:
342 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/33-zylin-zy1000-jtag-probe}
344 @section USB FT2232 Based
346 There are many USB JTAG dongles on the market, many of them are based
347 on a chip from ``Future Technology Devices International'' (FTDI)
348 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
349 See: @url{http://www.ftdichip.com} for more information.
350 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
351 chips are starting to become available in JTAG adapters. Around 2012 a new
352 variant appeared - FT232H - this is a single-channel version of FT2232H.
353 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
354 clocking.)
356 The FT2232 chips are flexible enough to support some other
357 transport options, such as SWD or the SPI variants used to
358 program some chips. They have two communications channels,
359 and one can be used for a UART adapter at the same time the
360 other one is used to provide a debug adapter.
362 Also, some development boards integrate an FT2232 chip to serve as
363 a built-in low cost debug adapter and usb-to-serial solution.
365 @itemize @bullet
366 @item @b{usbjtag}
367 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
368 @item @b{jtagkey}
369 @* See: @url{http://www.amontec.com/jtagkey.shtml}
370 @item @b{jtagkey2}
371 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
372 @item @b{oocdlink}
373 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
374 @item @b{signalyzer}
375 @* See: @url{http://www.signalyzer.com}
376 @item @b{Stellaris Eval Boards}
377 @* See: @url{http://www.ti.com} - The Stellaris eval boards
378 bundle FT2232-based JTAG and SWD support, which can be used to debug
379 the Stellaris chips. Using separate JTAG adapters is optional.
380 These boards can also be used in a "pass through" mode as JTAG adapters
381 to other target boards, disabling the Stellaris chip.
382 @item @b{TI/Luminary ICDI}
383 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
384 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
385 Evaluation Kits. Like the non-detachable FT2232 support on the other
386 Stellaris eval boards, they can be used to debug other target boards.
387 @item @b{olimex-jtag}
388 @* See: @url{http://www.olimex.com}
389 @item @b{Flyswatter/Flyswatter2}
390 @* See: @url{http://www.tincantools.com}
391 @item @b{turtelizer2}
392 @* See:
393 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
394 @url{http://www.ethernut.de}
395 @item @b{comstick}
396 @* Link: @url{http://www.hitex.com/index.php?id=383}
397 @item @b{stm32stick}
398 @* Link @url{http://www.hitex.com/stm32-stick}
399 @item @b{axm0432_jtag}
400 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
401 to be available anymore as of April 2012.
402 @item @b{cortino}
403 @* Link @url{http://www.hitex.com/index.php?id=cortino}
404 @item @b{dlp-usb1232h}
405 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
406 @item @b{digilent-hs1}
407 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
408 @item @b{opendous}
409 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
410 (OpenHardware).
411 @item @b{JTAG-lock-pick Tiny 2}
412 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
413 @end itemize
415 @section USB-JTAG / Altera USB-Blaster compatibles
417 These devices also show up as FTDI devices, but are not
418 protocol-compatible with the FT2232 devices. They are, however,
419 protocol-compatible among themselves. USB-JTAG devices typically consist
420 of a FT245 followed by a CPLD that understands a particular protocol,
421 or emulate this protocol using some other hardware.
423 They may appear under different USB VID/PID depending on the particular
424 product. The driver can be configured to search for any VID/PID pair
425 (see the section on driver commands).
427 @itemize
428 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
429 @* Link: @url{http://ixo-jtag.sourceforge.net/}
430 @item @b{Altera USB-Blaster}
431 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
432 @end itemize
434 @section USB JLINK based
435 There are several OEM versions of the Segger @b{JLINK} adapter. It is
436 an example of a micro controller based JTAG adapter, it uses an
437 AT91SAM764 internally.
439 @itemize @bullet
440 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
441 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
442 @item @b{SEGGER JLINK}
443 @* Link: @url{http://www.segger.com/jlink.html}
444 @item @b{IAR J-Link}
445 @* Link: @url{http://www.iar.com/en/products/hardware-debug-probes/iar-j-link/}
446 @end itemize
448 @section USB RLINK based
449 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
450 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
451 SWD and not JTAG, thus not supported.
453 @itemize @bullet
454 @item @b{Raisonance RLink}
455 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
456 @item @b{STM32 Primer}
457 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
458 @item @b{STM32 Primer2}
459 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
460 @end itemize
462 @section USB ST-LINK based
463 ST Micro has an adapter called @b{ST-LINK}.
464 They only work with ST Micro chips, notably STM32 and STM8.
466 @itemize @bullet
467 @item @b{ST-LINK}
468 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
469 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
470 @item @b{ST-LINK/V2}
471 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
472 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
473 @end itemize
475 For info the original ST-LINK enumerates using the mass storage usb class, however
476 it's implementation is completely broken. The result is this causes issues under linux.
477 The simplest solution is to get linux to ignore the ST-LINK using one of the following methods:
478 @itemize @bullet
479 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
480 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
481 @end itemize
483 @section USB TI/Stellaris ICDI based
484 Texas Instruments has an adapter called @b{ICDI}.
485 It is not to be confused with the FTDI based adapters that were originally fitted to their
486 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
488 @section USB Other
489 @itemize @bullet
490 @item @b{USBprog}
491 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
493 @item @b{USB - Presto}
494 @* Link: @url{http://tools.asix.net/prg_presto.htm}
496 @item @b{Versaloon-Link}
497 @* Link: @url{http://www.versaloon.com}
499 @item @b{ARM-JTAG-EW}
500 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
502 @item @b{Buspirate}
503 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
505 @item @b{opendous}
506 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
508 @item @b{estick}
509 @* Link: @url{http://code.google.com/p/estick-jtag/}
511 @item @b{Keil ULINK v1}
512 @* Link: @url{http://www.keil.com/ulink1/}
513 @end itemize
515 @section IBM PC Parallel Printer Port Based
517 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
518 and the Macraigor Wiggler. There are many clones and variations of
519 these on the market.
521 Note that parallel ports are becoming much less common, so if you
522 have the choice you should probably avoid these adapters in favor
523 of USB-based ones.
525 @itemize @bullet
527 @item @b{Wiggler} - There are many clones of this.
528 @* Link: @url{http://www.macraigor.com/wiggler.htm}
530 @item @b{DLC5} - From XILINX - There are many clones of this
531 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
532 produced, PDF schematics are easily found and it is easy to make.
534 @item @b{Amontec - JTAG Accelerator}
535 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
537 @item @b{GW16402}
538 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
540 @item @b{Wiggler2}
541 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
543 @item @b{Wiggler_ntrst_inverted}
544 @* Yet another variation - See the source code, src/jtag/parport.c
546 @item @b{old_amt_wiggler}
547 @* Unknown - probably not on the market today
549 @item @b{arm-jtag}
550 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
552 @item @b{chameleon}
553 @* Link: @url{http://www.amontec.com/chameleon.shtml}
555 @item @b{Triton}
556 @* Unknown.
558 @item @b{Lattice}
559 @* ispDownload from Lattice Semiconductor
560 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
562 @item @b{flashlink}
563 @* From ST Microsystems;
564 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
566 @end itemize
568 @section Other...
569 @itemize @bullet
571 @item @b{ep93xx}
572 @* An EP93xx based Linux machine using the GPIO pins directly.
574 @item @b{at91rm9200}
575 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
577 @end itemize
579 @node About Jim-Tcl
580 @chapter About Jim-Tcl
581 @cindex Jim-Tcl
582 @cindex tcl
584 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
585 This programming language provides a simple and extensible
586 command interpreter.
588 All commands presented in this Guide are extensions to Jim-Tcl.
589 You can use them as simple commands, without needing to learn
590 much of anything about Tcl.
591 Alternatively, can write Tcl programs with them.
593 You can learn more about Jim at its website, @url{http://jim.berlios.de}.
594 There is an active and responsive community, get on the mailing list
595 if you have any questions. Jim-Tcl maintainers also lurk on the
596 OpenOCD mailing list.
598 @itemize @bullet
599 @item @b{Jim vs. Tcl}
600 @* Jim-Tcl is a stripped down version of the well known Tcl language,
601 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
602 fewer features. Jim-Tcl is several dozens of .C files and .H files and
603 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
604 4.2 MB .zip file containing 1540 files.
606 @item @b{Missing Features}
607 @* Our practice has been: Add/clone the real Tcl feature if/when
608 needed. We welcome Jim-Tcl improvements, not bloat. Also there
609 are a large number of optional Jim-Tcl features that are not
610 enabled in OpenOCD.
612 @item @b{Scripts}
613 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
614 command interpreter today is a mixture of (newer)
615 Jim-Tcl commands, and (older) the orginal command interpreter.
617 @item @b{Commands}
618 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
619 can type a Tcl for() loop, set variables, etc.
620 Some of the commands documented in this guide are implemented
621 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
623 @item @b{Historical Note}
624 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
625 before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
626 as a git submodule, which greatly simplified upgrading Jim Tcl
627 to benefit from new features and bugfixes in Jim Tcl.
629 @item @b{Need a crash course in Tcl?}
630 @*@xref{Tcl Crash Course}.
631 @end itemize
633 @node Running
634 @chapter Running
635 @cindex command line options
636 @cindex logfile
637 @cindex directory search
639 Properly installing OpenOCD sets up your operating system to grant it access
640 to the debug adapters. On Linux, this usually involves installing a file
641 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
642 complex and confusing driver configuration for every peripheral. Such issues
643 are unique to each operating system, and are not detailed in this User's Guide.
645 Then later you will invoke the OpenOCD server, with various options to
646 tell it how each debug session should work.
647 The @option{--help} option shows:
648 @verbatim
649 bash$ openocd --help
651 --help | -h display this help
652 --version | -v display OpenOCD version
653 --file | -f use configuration file <name>
654 --search | -s dir to search for config files and scripts
655 --debug | -d set debug level <0-3>
656 --log_output | -l redirect log output to file <name>
657 --command | -c run <command>
658 @end verbatim
660 If you don't give any @option{-f} or @option{-c} options,
661 OpenOCD tries to read the configuration file @file{openocd.cfg}.
662 To specify one or more different
663 configuration files, use @option{-f} options. For example:
665 @example
666 openocd -f config1.cfg -f config2.cfg -f config3.cfg
667 @end example
669 Configuration files and scripts are searched for in
670 @enumerate
671 @item the current directory,
672 @item any search dir specified on the command line using the @option{-s} option,
673 @item any search dir specified using the @command{add_script_search_dir} command,
674 @item @file{$HOME/.openocd} (not on Windows),
675 @item the site wide script library @file{$pkgdatadir/site} and
676 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
677 @end enumerate
678 The first found file with a matching file name will be used.
680 @quotation Note
681 Don't try to use configuration script names or paths which
682 include the "#" character. That character begins Tcl comments.
683 @end quotation
685 @section Simple setup, no customization
687 In the best case, you can use two scripts from one of the script
688 libraries, hook up your JTAG adapter, and start the server ... and
689 your JTAG setup will just work "out of the box". Always try to
690 start by reusing those scripts, but assume you'll need more
691 customization even if this works. @xref{OpenOCD Project Setup}.
693 If you find a script for your JTAG adapter, and for your board or
694 target, you may be able to hook up your JTAG adapter then start
695 the server like:
697 @example
698 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
699 @end example
701 You might also need to configure which reset signals are present,
702 using @option{-c 'reset_config trst_and_srst'} or something similar.
703 If all goes well you'll see output something like
705 @example
706 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
707 For bug reports, read
708 http://openocd.sourceforge.net/doc/doxygen/bugs.html
709 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
710 (mfg: 0x23b, part: 0xba00, ver: 0x3)
711 @end example
713 Seeing that "tap/device found" message, and no warnings, means
714 the JTAG communication is working. That's a key milestone, but
715 you'll probably need more project-specific setup.
717 @section What OpenOCD does as it starts
719 OpenOCD starts by processing the configuration commands provided
720 on the command line or, if there were no @option{-c command} or
721 @option{-f file.cfg} options given, in @file{openocd.cfg}.
722 @xref{configurationstage,,Configuration Stage}.
723 At the end of the configuration stage it verifies the JTAG scan
724 chain defined using those commands; your configuration should
725 ensure that this always succeeds.
726 Normally, OpenOCD then starts running as a daemon.
727 Alternatively, commands may be used to terminate the configuration
728 stage early, perform work (such as updating some flash memory),
729 and then shut down without acting as a daemon.
731 Once OpenOCD starts running as a daemon, it waits for connections from
732 clients (Telnet, GDB, Other) and processes the commands issued through
733 those channels.
735 If you are having problems, you can enable internal debug messages via
736 the @option{-d} option.
738 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
739 @option{-c} command line switch.
741 To enable debug output (when reporting problems or working on OpenOCD
742 itself), use the @option{-d} command line switch. This sets the
743 @option{debug_level} to "3", outputting the most information,
744 including debug messages. The default setting is "2", outputting only
745 informational messages, warnings and errors. You can also change this
746 setting from within a telnet or gdb session using @command{debug_level<n>}
747 (@pxref{debuglevel,,debug_level}).
749 You can redirect all output from the daemon to a file using the
750 @option{-l <logfile>} switch.
752 Note! OpenOCD will launch the GDB & telnet server even if it can not
753 establish a connection with the target. In general, it is possible for
754 the JTAG controller to be unresponsive until the target is set up
755 correctly via e.g. GDB monitor commands in a GDB init script.
757 @node OpenOCD Project Setup
758 @chapter OpenOCD Project Setup
760 To use OpenOCD with your development projects, you need to do more than
761 just connecting the JTAG adapter hardware (dongle) to your development board
762 and then starting the OpenOCD server.
763 You also need to configure that server so that it knows
764 about that adapter and board, and helps your work.
765 You may also want to connect OpenOCD to GDB, possibly
766 using Eclipse or some other GUI.
768 @section Hooking up the JTAG Adapter
770 Today's most common case is a dongle with a JTAG cable on one side
771 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
772 and a USB cable on the other.
773 Instead of USB, some cables use Ethernet;
774 older ones may use a PC parallel port, or even a serial port.
776 @enumerate
777 @item @emph{Start with power to your target board turned off},
778 and nothing connected to your JTAG adapter.
779 If you're particularly paranoid, unplug power to the board.
780 It's important to have the ground signal properly set up,
781 unless you are using a JTAG adapter which provides
782 galvanic isolation between the target board and the
783 debugging host.
785 @item @emph{Be sure it's the right kind of JTAG connector.}
786 If your dongle has a 20-pin ARM connector, you need some kind
787 of adapter (or octopus, see below) to hook it up to
788 boards using 14-pin or 10-pin connectors ... or to 20-pin
789 connectors which don't use ARM's pinout.
791 In the same vein, make sure the voltage levels are compatible.
792 Not all JTAG adapters have the level shifters needed to work
793 with 1.2 Volt boards.
795 @item @emph{Be certain the cable is properly oriented} or you might
796 damage your board. In most cases there are only two possible
797 ways to connect the cable.
798 Connect the JTAG cable from your adapter to the board.
799 Be sure it's firmly connected.
801 In the best case, the connector is keyed to physically
802 prevent you from inserting it wrong.
803 This is most often done using a slot on the board's male connector
804 housing, which must match a key on the JTAG cable's female connector.
805 If there's no housing, then you must look carefully and
806 make sure pin 1 on the cable hooks up to pin 1 on the board.
807 Ribbon cables are frequently all grey except for a wire on one
808 edge, which is red. The red wire is pin 1.
810 Sometimes dongles provide cables where one end is an ``octopus'' of
811 color coded single-wire connectors, instead of a connector block.
812 These are great when converting from one JTAG pinout to another,
813 but are tedious to set up.
814 Use these with connector pinout diagrams to help you match up the
815 adapter signals to the right board pins.
817 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
818 A USB, parallel, or serial port connector will go to the host which
819 you are using to run OpenOCD.
820 For Ethernet, consult the documentation and your network administrator.
822 For USB based JTAG adapters you have an easy sanity check at this point:
823 does the host operating system see the JTAG adapter? If that host is an
824 MS-Windows host, you'll need to install a driver before OpenOCD works.
826 @item @emph{Connect the adapter's power supply, if needed.}
827 This step is primarily for non-USB adapters,
828 but sometimes USB adapters need extra power.
830 @item @emph{Power up the target board.}
831 Unless you just let the magic smoke escape,
832 you're now ready to set up the OpenOCD server
833 so you can use JTAG to work with that board.
835 @end enumerate
837 Talk with the OpenOCD server using
838 telnet (@code{telnet localhost 4444} on many systems) or GDB.
839 @xref{GDB and OpenOCD}.
841 @section Project Directory
843 There are many ways you can configure OpenOCD and start it up.
845 A simple way to organize them all involves keeping a
846 single directory for your work with a given board.
847 When you start OpenOCD from that directory,
848 it searches there first for configuration files, scripts,
849 files accessed through semihosting,
850 and for code you upload to the target board.
851 It is also the natural place to write files,
852 such as log files and data you download from the board.
854 @section Configuration Basics
856 There are two basic ways of configuring OpenOCD, and
857 a variety of ways you can mix them.
858 Think of the difference as just being how you start the server:
860 @itemize
861 @item Many @option{-f file} or @option{-c command} options on the command line
862 @item No options, but a @dfn{user config file}
863 in the current directory named @file{openocd.cfg}
864 @end itemize
866 Here is an example @file{openocd.cfg} file for a setup
867 using a Signalyzer FT2232-based JTAG adapter to talk to
868 a board with an Atmel AT91SAM7X256 microcontroller:
870 @example
871 source [find interface/signalyzer.cfg]
873 # GDB can also flash my flash!
874 gdb_memory_map enable
875 gdb_flash_program enable
877 source [find target/sam7x256.cfg]
878 @end example
880 Here is the command line equivalent of that configuration:
882 @example
883 openocd -f interface/signalyzer.cfg \
884 -c "gdb_memory_map enable" \
885 -c "gdb_flash_program enable" \
886 -f target/sam7x256.cfg
887 @end example
889 You could wrap such long command lines in shell scripts,
890 each supporting a different development task.
891 One might re-flash the board with a specific firmware version.
892 Another might set up a particular debugging or run-time environment.
894 @quotation Important
895 At this writing (October 2009) the command line method has
896 problems with how it treats variables.
897 For example, after @option{-c "set VAR value"}, or doing the
898 same in a script, the variable @var{VAR} will have no value
899 that can be tested in a later script.
900 @end quotation
902 Here we will focus on the simpler solution: one user config
903 file, including basic configuration plus any TCL procedures
904 to simplify your work.
906 @section User Config Files
907 @cindex config file, user
908 @cindex user config file
909 @cindex config file, overview
911 A user configuration file ties together all the parts of a project
912 in one place.
913 One of the following will match your situation best:
915 @itemize
916 @item Ideally almost everything comes from configuration files
917 provided by someone else.
918 For example, OpenOCD distributes a @file{scripts} directory
919 (probably in @file{/usr/share/openocd/scripts} on Linux).
920 Board and tool vendors can provide these too, as can individual
921 user sites; the @option{-s} command line option lets you say
922 where to find these files. (@xref{Running}.)
923 The AT91SAM7X256 example above works this way.
925 Three main types of non-user configuration file each have their
926 own subdirectory in the @file{scripts} directory:
928 @enumerate
929 @item @b{interface} -- one for each different debug adapter;
930 @item @b{board} -- one for each different board
931 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
932 @end enumerate
934 Best case: include just two files, and they handle everything else.
935 The first is an interface config file.
936 The second is board-specific, and it sets up the JTAG TAPs and
937 their GDB targets (by deferring to some @file{target.cfg} file),
938 declares all flash memory, and leaves you nothing to do except
939 meet your deadline:
941 @example
942 source [find interface/olimex-jtag-tiny.cfg]
943 source [find board/csb337.cfg]
944 @end example
946 Boards with a single microcontroller often won't need more
947 than the target config file, as in the AT91SAM7X256 example.
948 That's because there is no external memory (flash, DDR RAM), and
949 the board differences are encapsulated by application code.
951 @item Maybe you don't know yet what your board looks like to JTAG.
952 Once you know the @file{interface.cfg} file to use, you may
953 need help from OpenOCD to discover what's on the board.
954 Once you find the JTAG TAPs, you can just search for appropriate
955 target and board
956 configuration files ... or write your own, from the bottom up.
957 @xref{autoprobing,,Autoprobing}.
959 @item You can often reuse some standard config files but
960 need to write a few new ones, probably a @file{board.cfg} file.
961 You will be using commands described later in this User's Guide,
962 and working with the guidelines in the next chapter.
964 For example, there may be configuration files for your JTAG adapter
965 and target chip, but you need a new board-specific config file
966 giving access to your particular flash chips.
967 Or you might need to write another target chip configuration file
968 for a new chip built around the Cortex M3 core.
970 @quotation Note
971 When you write new configuration files, please submit
972 them for inclusion in the next OpenOCD release.
973 For example, a @file{board/newboard.cfg} file will help the
974 next users of that board, and a @file{target/newcpu.cfg}
975 will help support users of any board using that chip.
976 @end quotation
978 @item
979 You may may need to write some C code.
980 It may be as simple as a supporting a new ft2232 or parport
981 based adapter; a bit more involved, like a NAND or NOR flash
982 controller driver; or a big piece of work like supporting
983 a new chip architecture.
984 @end itemize
986 Reuse the existing config files when you can.
987 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
988 You may find a board configuration that's a good example to follow.
990 When you write config files, separate the reusable parts
991 (things every user of that interface, chip, or board needs)
992 from ones specific to your environment and debugging approach.
993 @itemize
995 @item
996 For example, a @code{gdb-attach} event handler that invokes
997 the @command{reset init} command will interfere with debugging
998 early boot code, which performs some of the same actions
999 that the @code{reset-init} event handler does.
1001 @item
1002 Likewise, the @command{arm9 vector_catch} command (or
1003 @cindex vector_catch
1004 its siblings @command{xscale vector_catch}
1005 and @command{cortex_m vector_catch}) can be a timesaver
1006 during some debug sessions, but don't make everyone use that either.
1007 Keep those kinds of debugging aids in your user config file,
1008 along with messaging and tracing setup.
1009 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1011 @item
1012 You might need to override some defaults.
1013 For example, you might need to move, shrink, or back up the target's
1014 work area if your application needs much SRAM.
1016 @item
1017 TCP/IP port configuration is another example of something which
1018 is environment-specific, and should only appear in
1019 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1020 @end itemize
1022 @section Project-Specific Utilities
1024 A few project-specific utility
1025 routines may well speed up your work.
1026 Write them, and keep them in your project's user config file.
1028 For example, if you are making a boot loader work on a
1029 board, it's nice to be able to debug the ``after it's
1030 loaded to RAM'' parts separately from the finicky early
1031 code which sets up the DDR RAM controller and clocks.
1032 A script like this one, or a more GDB-aware sibling,
1033 may help:
1035 @example
1036 proc ramboot @{ @} @{
1037 # Reset, running the target's "reset-init" scripts
1038 # to initialize clocks and the DDR RAM controller.
1039 # Leave the CPU halted.
1040 reset init
1042 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1043 load_image u-boot.bin 0x20000000
1045 # Start running.
1046 resume 0x20000000
1047 @}
1048 @end example
1050 Then once that code is working you will need to make it
1051 boot from NOR flash; a different utility would help.
1052 Alternatively, some developers write to flash using GDB.
1053 (You might use a similar script if you're working with a flash
1054 based microcontroller application instead of a boot loader.)
1056 @example
1057 proc newboot @{ @} @{
1058 # Reset, leaving the CPU halted. The "reset-init" event
1059 # proc gives faster access to the CPU and to NOR flash;
1060 # "reset halt" would be slower.
1061 reset init
1063 # Write standard version of U-Boot into the first two
1064 # sectors of NOR flash ... the standard version should
1065 # do the same lowlevel init as "reset-init".
1066 flash protect 0 0 1 off
1067 flash erase_sector 0 0 1
1068 flash write_bank 0 u-boot.bin 0x0
1069 flash protect 0 0 1 on
1071 # Reboot from scratch using that new boot loader.
1072 reset run
1073 @}
1074 @end example
1076 You may need more complicated utility procedures when booting
1077 from NAND.
1078 That often involves an extra bootloader stage,
1079 running from on-chip SRAM to perform DDR RAM setup so it can load
1080 the main bootloader code (which won't fit into that SRAM).
1082 Other helper scripts might be used to write production system images,
1083 involving considerably more than just a three stage bootloader.
1085 @section Target Software Changes
1087 Sometimes you may want to make some small changes to the software
1088 you're developing, to help make JTAG debugging work better.
1089 For example, in C or assembly language code you might
1090 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1091 handling issues like:
1093 @itemize @bullet
1095 @item @b{Watchdog Timers}...
1096 Watchog timers are typically used to automatically reset systems if
1097 some application task doesn't periodically reset the timer. (The
1098 assumption is that the system has locked up if the task can't run.)
1099 When a JTAG debugger halts the system, that task won't be able to run
1100 and reset the timer ... potentially causing resets in the middle of
1101 your debug sessions.
1103 It's rarely a good idea to disable such watchdogs, since their usage
1104 needs to be debugged just like all other parts of your firmware.
1105 That might however be your only option.
1107 Look instead for chip-specific ways to stop the watchdog from counting
1108 while the system is in a debug halt state. It may be simplest to set
1109 that non-counting mode in your debugger startup scripts. You may however
1110 need a different approach when, for example, a motor could be physically
1111 damaged by firmware remaining inactive in a debug halt state. That might
1112 involve a type of firmware mode where that "non-counting" mode is disabled
1113 at the beginning then re-enabled at the end; a watchdog reset might fire
1114 and complicate the debug session, but hardware (or people) would be
1115 protected.@footnote{Note that many systems support a "monitor mode" debug
1116 that is a somewhat cleaner way to address such issues. You can think of
1117 it as only halting part of the system, maybe just one task,
1118 instead of the whole thing.
1119 At this writing, January 2010, OpenOCD based debugging does not support
1120 monitor mode debug, only "halt mode" debug.}
1122 @item @b{ARM Semihosting}...
1123 @cindex ARM semihosting
1124 When linked with a special runtime library provided with many
1125 toolchains@footnote{See chapter 8 "Semihosting" in
1126 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1127 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1128 The CodeSourcery EABI toolchain also includes a semihosting library.},
1129 your target code can use I/O facilities on the debug host. That library
1130 provides a small set of system calls which are handled by OpenOCD.
1131 It can let the debugger provide your system console and a file system,
1132 helping with early debugging or providing a more capable environment
1133 for sometimes-complex tasks like installing system firmware onto
1134 NAND or SPI flash.
1136 @item @b{ARM Wait-For-Interrupt}...
1137 Many ARM chips synchronize the JTAG clock using the core clock.
1138 Low power states which stop that core clock thus prevent JTAG access.
1139 Idle loops in tasking environments often enter those low power states
1140 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1142 You may want to @emph{disable that instruction} in source code,
1143 or otherwise prevent using that state,
1144 to ensure you can get JTAG access at any time.@footnote{As a more
1145 polite alternative, some processors have special debug-oriented
1146 registers which can be used to change various features including
1147 how the low power states are clocked while debugging.
1148 The STM32 DBGMCU_CR register is an example; at the cost of extra
1149 power consumption, JTAG can be used during low power states.}
1150 For example, the OpenOCD @command{halt} command may not
1151 work for an idle processor otherwise.
1153 @item @b{Delay after reset}...
1154 Not all chips have good support for debugger access
1155 right after reset; many LPC2xxx chips have issues here.
1156 Similarly, applications that reconfigure pins used for
1157 JTAG access as they start will also block debugger access.
1159 To work with boards like this, @emph{enable a short delay loop}
1160 the first thing after reset, before "real" startup activities.
1161 For example, one second's delay is usually more than enough
1162 time for a JTAG debugger to attach, so that
1163 early code execution can be debugged
1164 or firmware can be replaced.
1166 @item @b{Debug Communications Channel (DCC)}...
1167 Some processors include mechanisms to send messages over JTAG.
1168 Many ARM cores support these, as do some cores from other vendors.
1169 (OpenOCD may be able to use this DCC internally, speeding up some
1170 operations like writing to memory.)
1172 Your application may want to deliver various debugging messages
1173 over JTAG, by @emph{linking with a small library of code}
1174 provided with OpenOCD and using the utilities there to send
1175 various kinds of message.
1176 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1178 @end itemize
1180 @section Target Hardware Setup
1182 Chip vendors often provide software development boards which
1183 are highly configurable, so that they can support all options
1184 that product boards may require. @emph{Make sure that any
1185 jumpers or switches match the system configuration you are
1186 working with.}
1188 Common issues include:
1190 @itemize @bullet
1192 @item @b{JTAG setup} ...
1193 Boards may support more than one JTAG configuration.
1194 Examples include jumpers controlling pullups versus pulldowns
1195 on the nTRST and/or nSRST signals, and choice of connectors
1196 (e.g. which of two headers on the base board,
1197 or one from a daughtercard).
1198 For some Texas Instruments boards, you may need to jumper the
1199 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1201 @item @b{Boot Modes} ...
1202 Complex chips often support multiple boot modes, controlled
1203 by external jumpers. Make sure this is set up correctly.
1204 For example many i.MX boards from NXP need to be jumpered
1205 to "ATX mode" to start booting using the on-chip ROM, when
1206 using second stage bootloader code stored in a NAND flash chip.
1208 Such explicit configuration is common, and not limited to
1209 booting from NAND. You might also need to set jumpers to
1210 start booting using code loaded from an MMC/SD card; external
1211 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1212 flash; some external host; or various other sources.
1215 @item @b{Memory Addressing} ...
1216 Boards which support multiple boot modes may also have jumpers
1217 to configure memory addressing. One board, for example, jumpers
1218 external chipselect 0 (used for booting) to address either
1219 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1220 or NAND flash. When it's jumpered to address NAND flash, that
1221 board must also be told to start booting from on-chip ROM.
1223 Your @file{board.cfg} file may also need to be told this jumper
1224 configuration, so that it can know whether to declare NOR flash
1225 using @command{flash bank} or instead declare NAND flash with
1226 @command{nand device}; and likewise which probe to perform in
1227 its @code{reset-init} handler.
1229 A closely related issue is bus width. Jumpers might need to
1230 distinguish between 8 bit or 16 bit bus access for the flash
1231 used to start booting.
1233 @item @b{Peripheral Access} ...
1234 Development boards generally provide access to every peripheral
1235 on the chip, sometimes in multiple modes (such as by providing
1236 multiple audio codec chips).
1237 This interacts with software
1238 configuration of pin multiplexing, where for example a
1239 given pin may be routed either to the MMC/SD controller
1240 or the GPIO controller. It also often interacts with
1241 configuration jumpers. One jumper may be used to route
1242 signals to an MMC/SD card slot or an expansion bus (which
1243 might in turn affect booting); others might control which
1244 audio or video codecs are used.
1246 @end itemize
1248 Plus you should of course have @code{reset-init} event handlers
1249 which set up the hardware to match that jumper configuration.
1250 That includes in particular any oscillator or PLL used to clock
1251 the CPU, and any memory controllers needed to access external
1252 memory and peripherals. Without such handlers, you won't be
1253 able to access those resources without working target firmware
1254 which can do that setup ... this can be awkward when you're
1255 trying to debug that target firmware. Even if there's a ROM
1256 bootloader which handles a few issues, it rarely provides full
1257 access to all board-specific capabilities.
1260 @node Config File Guidelines
1261 @chapter Config File Guidelines
1263 This chapter is aimed at any user who needs to write a config file,
1264 including developers and integrators of OpenOCD and any user who
1265 needs to get a new board working smoothly.
1266 It provides guidelines for creating those files.
1268 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1269 with files including the ones listed here.
1270 Use them as-is where you can; or as models for new files.
1271 @itemize @bullet
1272 @item @file{interface} ...
1273 These are for debug adapters.
1274 Files that configure JTAG adapters go here.
1275 @example
1276 $ ls interface -R
1277 interface/:
1278 altera-usb-blaster.cfg hilscher_nxhx50_re.cfg openocd-usb-hs.cfg
1279 arm-jtag-ew.cfg hitex_str9-comstick.cfg openrd.cfg
1280 at91rm9200.cfg icebear.cfg osbdm.cfg
1281 axm0432.cfg jlink.cfg parport.cfg
1282 busblaster.cfg jtagkey2.cfg parport_dlc5.cfg
1283 buspirate.cfg jtagkey2p.cfg redbee-econotag.cfg
1284 calao-usb-a9260-c01.cfg jtagkey.cfg redbee-usb.cfg
1285 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg rlink.cfg
1286 calao-usb-a9260.cfg jtag-lock-pick_tiny_2.cfg sheevaplug.cfg
1287 chameleon.cfg kt-link.cfg signalyzer.cfg
1288 cortino.cfg lisa-l.cfg signalyzer-h2.cfg
1289 digilent-hs1.cfg luminary.cfg signalyzer-h4.cfg
1290 dlp-usb1232h.cfg luminary-icdi.cfg signalyzer-lite.cfg
1291 dummy.cfg luminary-lm3s811.cfg stlink-v1.cfg
1292 estick.cfg minimodule.cfg stlink-v2.cfg
1293 flashlink.cfg neodb.cfg stm32-stick.cfg
1294 flossjtag.cfg ngxtech.cfg sysfsgpio-raspberrypi.cfg
1295 flossjtag-noeeprom.cfg olimex-arm-usb-ocd.cfg ti-icdi.cfg
1296 flyswatter2.cfg olimex-arm-usb-ocd-h.cfg turtelizer2.cfg
1297 flyswatter.cfg olimex-arm-usb-tiny-h.cfg ulink.cfg
1298 ftdi olimex-jtag-tiny.cfg usb-jtag.cfg
1299 hilscher_nxhx10_etm.cfg oocdlink.cfg usbprog.cfg
1300 hilscher_nxhx500_etm.cfg opendous.cfg vpaclink.cfg
1301 hilscher_nxhx500_re.cfg opendous_ftdi.cfg vsllink.cfg
1302 hilscher_nxhx50_etm.cfg openocd-usb.cfg xds100v2.cfg
1304 interface/ftdi:
1305 axm0432.cfg icebear.cfg oocdlink.cfg
1306 calao-usb-a9260-c01.cfg jtagkey2.cfg opendous_ftdi.cfg
1307 calao-usb-a9260-c02.cfg jtagkey2p.cfg openocd-usb.cfg
1308 cortino.cfg jtagkey.cfg openocd-usb-hs.cfg
1309 dlp-usb1232h.cfg jtag-lock-pick_tiny_2.cfg openrd.cfg
1310 dp_busblaster.cfg kt-link.cfg redbee-econotag.cfg
1311 flossjtag.cfg lisa-l.cfg redbee-usb.cfg
1312 flossjtag-noeeprom.cfg luminary.cfg sheevaplug.cfg
1313 flyswatter2.cfg luminary-icdi.cfg signalyzer.cfg
1314 flyswatter.cfg luminary-lm3s811.cfg signalyzer-lite.cfg
1315 hilscher_nxhx10_etm.cfg minimodule.cfg stm32-stick.cfg
1316 hilscher_nxhx500_etm.cfg neodb.cfg turtelizer2-revB.cfg
1317 hilscher_nxhx500_re.cfg ngxtech.cfg turtelizer2-revC.cfg
1318 hilscher_nxhx50_etm.cfg olimex-arm-usb-ocd.cfg vpaclink.cfg
1319 hilscher_nxhx50_re.cfg olimex-arm-usb-ocd-h.cfg xds100v2.cfg
1320 hitex_lpc1768stick.cfg olimex-arm-usb-tiny-h.cfg
1321 hitex_str9-comstick.cfg olimex-jtag-tiny.cfg
1322 $
1323 @end example
1324 @item @file{board} ...
1325 think Circuit Board, PWA, PCB, they go by many names. Board files
1326 contain initialization items that are specific to a board.
1327 They reuse target configuration files, since the same
1328 microprocessor chips are used on many boards,
1329 but support for external parts varies widely. For
1330 example, the SDRAM initialization sequence for the board, or the type
1331 of external flash and what address it uses. Any initialization
1332 sequence to enable that external flash or SDRAM should be found in the
1333 board file. Boards may also contain multiple targets: two CPUs; or
1334 a CPU and an FPGA.
1335 @example
1336 $ ls board
1337 actux3.cfg lpc1850_spifi_generic.cfg
1338 am3517evm.cfg lpc4350_spifi_generic.cfg
1339 arm_evaluator7t.cfg lubbock.cfg
1340 at91cap7a-stk-sdram.cfg mcb1700.cfg
1341 at91eb40a.cfg microchip_explorer16.cfg
1342 at91rm9200-dk.cfg mini2440.cfg
1343 at91rm9200-ek.cfg mini6410.cfg
1344 at91sam9261-ek.cfg netgear-dg834v3.cfg
1345 at91sam9263-ek.cfg olimex_LPC2378STK.cfg
1346 at91sam9g20-ek.cfg olimex_lpc_h2148.cfg
1347 atmel_at91sam7s-ek.cfg olimex_sam7_ex256.cfg
1348 atmel_at91sam9260-ek.cfg olimex_sam9_l9260.cfg
1349 atmel_at91sam9rl-ek.cfg olimex_stm32_h103.cfg
1350 atmel_sam3n_ek.cfg olimex_stm32_h107.cfg
1351 atmel_sam3s_ek.cfg olimex_stm32_p107.cfg
1352 atmel_sam3u_ek.cfg omap2420_h4.cfg
1353 atmel_sam3x_ek.cfg open-bldc.cfg
1354 atmel_sam4s_ek.cfg openrd.cfg
1355 balloon3-cpu.cfg osk5912.cfg
1356 colibri.cfg phone_se_j100i.cfg
1357 crossbow_tech_imote2.cfg phytec_lpc3250.cfg
1358 csb337.cfg pic-p32mx.cfg
1359 csb732.cfg propox_mmnet1001.cfg
1360 da850evm.cfg pxa255_sst.cfg
1361 digi_connectcore_wi-9c.cfg redbee.cfg
1362 diolan_lpc4350-db1.cfg rsc-w910.cfg
1363 dm355evm.cfg sheevaplug.cfg
1364 dm365evm.cfg smdk6410.cfg
1365 dm6446evm.cfg spear300evb.cfg
1366 efikamx.cfg spear300evb_mod.cfg
1367 eir.cfg spear310evb20.cfg
1368 ek-lm3s1968.cfg spear310evb20_mod.cfg
1369 ek-lm3s3748.cfg spear320cpu.cfg
1370 ek-lm3s6965.cfg spear320cpu_mod.cfg
1371 ek-lm3s811.cfg steval_pcc010.cfg
1372 ek-lm3s811-revb.cfg stm320518_eval_stlink.cfg
1373 ek-lm3s8962.cfg stm32100b_eval.cfg
1374 ek-lm3s9b9x.cfg stm3210b_eval.cfg
1375 ek-lm3s9d92.cfg stm3210c_eval.cfg
1376 ek-lm4f120xl.cfg stm3210e_eval.cfg
1377 ek-lm4f232.cfg stm3220g_eval.cfg
1378 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1379 ethernut3.cfg stm3241g_eval.cfg
1380 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1381 hammer.cfg stm32f0discovery.cfg
1382 hilscher_nxdb500sys.cfg stm32f3discovery.cfg
1383 hilscher_nxeb500hmi.cfg stm32f4discovery.cfg
1384 hilscher_nxhx10.cfg stm32ldiscovery.cfg
1385 hilscher_nxhx500.cfg stm32vldiscovery.cfg
1386 hilscher_nxhx50.cfg str910-eval.cfg
1387 hilscher_nxsb100.cfg telo.cfg
1388 hitex_lpc1768stick.cfg ti_am335xevm.cfg
1389 hitex_lpc2929.cfg ti_beagleboard.cfg
1390 hitex_stm32-performancestick.cfg ti_beagleboard_xm.cfg
1391 hitex_str9-comstick.cfg ti_beaglebone.cfg
1392 iar_lpc1768.cfg ti_blaze.cfg
1393 iar_str912_sk.cfg ti_pandaboard.cfg
1394 icnova_imx53_sodimm.cfg ti_pandaboard_es.cfg
1395 icnova_sam9g45_sodimm.cfg topas910.cfg
1396 imx27ads.cfg topasa900.cfg
1397 imx27lnst.cfg twr-k60f120m.cfg
1398 imx28evk.cfg twr-k60n512.cfg
1399 imx31pdk.cfg tx25_stk5.cfg
1400 imx35pdk.cfg tx27_stk5.cfg
1401 imx53loco.cfg unknown_at91sam9260.cfg
1402 keil_mcb1700.cfg uptech_2410.cfg
1403 keil_mcb2140.cfg verdex.cfg
1404 kwikstik.cfg voipac.cfg
1405 linksys_nslu2.cfg voltcraft_dso-3062c.cfg
1406 lisa-l.cfg x300t.cfg
1407 logicpd_imx27.cfg zy1000.cfg
1408 $
1409 @end example
1410 @item @file{target} ...
1411 think chip. The ``target'' directory represents the JTAG TAPs
1412 on a chip
1413 which OpenOCD should control, not a board. Two common types of targets
1414 are ARM chips and FPGA or CPLD chips.
1415 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1416 the target config file defines all of them.
1417 @example
1418 $ ls target
1419 aduc702x.cfg lpc1763.cfg
1420 am335x.cfg lpc1764.cfg
1421 amdm37x.cfg lpc1765.cfg
1422 ar71xx.cfg lpc1766.cfg
1423 at32ap7000.cfg lpc1767.cfg
1424 at91r40008.cfg lpc1768.cfg
1425 at91rm9200.cfg lpc1769.cfg
1426 at91sam3ax_4x.cfg lpc1788.cfg
1427 at91sam3ax_8x.cfg lpc17xx.cfg
1428 at91sam3ax_xx.cfg lpc1850.cfg
1429 at91sam3nXX.cfg lpc2103.cfg
1430 at91sam3sXX.cfg lpc2124.cfg
1431 at91sam3u1c.cfg lpc2129.cfg
1432 at91sam3u1e.cfg lpc2148.cfg
1433 at91sam3u2c.cfg lpc2294.cfg
1434 at91sam3u2e.cfg lpc2378.cfg
1435 at91sam3u4c.cfg lpc2460.cfg
1436 at91sam3u4e.cfg lpc2478.cfg
1437 at91sam3uxx.cfg lpc2900.cfg
1438 at91sam3XXX.cfg lpc2xxx.cfg
1439 at91sam4sd32x.cfg lpc3131.cfg
1440 at91sam4sXX.cfg lpc3250.cfg
1441 at91sam4XXX.cfg lpc4350.cfg
1442 at91sam7se512.cfg lpc4350.cfg.orig
1443 at91sam7sx.cfg mc13224v.cfg
1444 at91sam7x256.cfg nuc910.cfg
1445 at91sam7x512.cfg omap2420.cfg
1446 at91sam9260.cfg omap3530.cfg
1447 at91sam9260_ext_RAM_ext_flash.cfg omap4430.cfg
1448 at91sam9261.cfg omap4460.cfg
1449 at91sam9263.cfg omap5912.cfg
1450 at91sam9.cfg omapl138.cfg
1451 at91sam9g10.cfg pic32mx.cfg
1452 at91sam9g20.cfg pxa255.cfg
1453 at91sam9g45.cfg pxa270.cfg
1454 at91sam9rl.cfg pxa3xx.cfg
1455 atmega128.cfg readme.txt
1456 avr32.cfg samsung_s3c2410.cfg
1457 c100.cfg samsung_s3c2440.cfg
1458 c100config.tcl samsung_s3c2450.cfg
1459 c100helper.tcl samsung_s3c4510.cfg
1460 c100regs.tcl samsung_s3c6410.cfg
1461 cs351x.cfg sharp_lh79532.cfg
1462 davinci.cfg smp8634.cfg
1463 dragonite.cfg spear3xx.cfg
1464 dsp56321.cfg stellaris.cfg
1465 dsp568013.cfg stellaris_icdi.cfg
1466 dsp568037.cfg stm32f0x_stlink.cfg
1467 efm32_stlink.cfg stm32f1x.cfg
1468 epc9301.cfg stm32f1x_stlink.cfg
1469 faux.cfg stm32f2x.cfg
1470 feroceon.cfg stm32f2x_stlink.cfg
1471 fm3.cfg stm32f3x.cfg
1472 hilscher_netx10.cfg stm32f3x_stlink.cfg
1473 hilscher_netx500.cfg stm32f4x.cfg
1474 hilscher_netx50.cfg stm32f4x_stlink.cfg
1475 icepick.cfg stm32l.cfg
1476 imx21.cfg stm32lx_dual_bank.cfg
1477 imx25.cfg stm32lx_stlink.cfg
1478 imx27.cfg stm32_stlink.cfg
1479 imx28.cfg stm32w108_stlink.cfg
1480 imx31.cfg stm32xl.cfg
1481 imx35.cfg str710.cfg
1482 imx51.cfg str730.cfg
1483 imx53.cfg str750.cfg
1484 imx6.cfg str912.cfg
1485 imx.cfg swj-dp.tcl
1486 is5114.cfg test_reset_syntax_error.cfg
1487 ixp42x.cfg test_syntax_error.cfg
1488 k40.cfg ti-ar7.cfg
1489 k60.cfg ti_calypso.cfg
1490 lpc1751.cfg ti_dm355.cfg
1491 lpc1752.cfg ti_dm365.cfg
1492 lpc1754.cfg ti_dm6446.cfg
1493 lpc1756.cfg tmpa900.cfg
1494 lpc1758.cfg tmpa910.cfg
1495 lpc1759.cfg u8500.cfg
1496 @end example
1497 @item @emph{more} ... browse for other library files which may be useful.
1498 For example, there are various generic and CPU-specific utilities.
1499 @end itemize
1501 The @file{openocd.cfg} user config
1502 file may override features in any of the above files by
1503 setting variables before sourcing the target file, or by adding
1504 commands specific to their situation.
1506 @section Interface Config Files
1508 The user config file
1509 should be able to source one of these files with a command like this:
1511 @example
1512 source [find interface/FOOBAR.cfg]
1513 @end example
1515 A preconfigured interface file should exist for every debug adapter
1516 in use today with OpenOCD.
1517 That said, perhaps some of these config files
1518 have only been used by the developer who created it.
1520 A separate chapter gives information about how to set these up.
1521 @xref{Debug Adapter Configuration}.
1522 Read the OpenOCD source code (and Developer's Guide)
1523 if you have a new kind of hardware interface
1524 and need to provide a driver for it.
1526 @section Board Config Files
1527 @cindex config file, board
1528 @cindex board config file
1530 The user config file
1531 should be able to source one of these files with a command like this:
1533 @example
1534 source [find board/FOOBAR.cfg]
1535 @end example
1537 The point of a board config file is to package everything
1538 about a given board that user config files need to know.
1539 In summary the board files should contain (if present)
1541 @enumerate
1542 @item One or more @command{source [target/...cfg]} statements
1543 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1544 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1545 @item Target @code{reset} handlers for SDRAM and I/O configuration
1546 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1547 @item All things that are not ``inside a chip''
1548 @end enumerate
1550 Generic things inside target chips belong in target config files,
1551 not board config files. So for example a @code{reset-init} event
1552 handler should know board-specific oscillator and PLL parameters,
1553 which it passes to target-specific utility code.
1555 The most complex task of a board config file is creating such a
1556 @code{reset-init} event handler.
1557 Define those handlers last, after you verify the rest of the board
1558 configuration works.
1560 @subsection Communication Between Config files
1562 In addition to target-specific utility code, another way that
1563 board and target config files communicate is by following a
1564 convention on how to use certain variables.
1566 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1567 Thus the rule we follow in OpenOCD is this: Variables that begin with
1568 a leading underscore are temporary in nature, and can be modified and
1569 used at will within a target configuration file.
1571 Complex board config files can do the things like this,
1572 for a board with three chips:
1574 @example
1575 # Chip #1: PXA270 for network side, big endian
1576 set CHIPNAME network
1577 set ENDIAN big
1578 source [find target/pxa270.cfg]
1579 # on return: _TARGETNAME = network.cpu
1580 # other commands can refer to the "network.cpu" target.
1581 $_TARGETNAME configure .... events for this CPU..
1583 # Chip #2: PXA270 for video side, little endian
1584 set CHIPNAME video
1585 set ENDIAN little
1586 source [find target/pxa270.cfg]
1587 # on return: _TARGETNAME = video.cpu
1588 # other commands can refer to the "video.cpu" target.
1589 $_TARGETNAME configure .... events for this CPU..
1591 # Chip #3: Xilinx FPGA for glue logic
1592 set CHIPNAME xilinx
1593 unset ENDIAN
1594 source [find target/spartan3.cfg]
1595 @end example
1597 That example is oversimplified because it doesn't show any flash memory,
1598 or the @code{reset-init} event handlers to initialize external DRAM
1599 or (assuming it needs it) load a configuration into the FPGA.
1600 Such features are usually needed for low-level work with many boards,
1601 where ``low level'' implies that the board initialization software may
1602 not be working. (That's a common reason to need JTAG tools. Another
1603 is to enable working with microcontroller-based systems, which often
1604 have no debugging support except a JTAG connector.)
1606 Target config files may also export utility functions to board and user
1607 config files. Such functions should use name prefixes, to help avoid
1608 naming collisions.
1610 Board files could also accept input variables from user config files.
1611 For example, there might be a @code{J4_JUMPER} setting used to identify
1612 what kind of flash memory a development board is using, or how to set
1613 up other clocks and peripherals.
1615 @subsection Variable Naming Convention
1616 @cindex variable names
1618 Most boards have only one instance of a chip.
1619 However, it should be easy to create a board with more than
1620 one such chip (as shown above).
1621 Accordingly, we encourage these conventions for naming
1622 variables associated with different @file{target.cfg} files,
1623 to promote consistency and
1624 so that board files can override target defaults.
1626 Inputs to target config files include:
1628 @itemize @bullet
1629 @item @code{CHIPNAME} ...
1630 This gives a name to the overall chip, and is used as part of
1631 tap identifier dotted names.
1632 While the default is normally provided by the chip manufacturer,
1633 board files may need to distinguish between instances of a chip.
1634 @item @code{ENDIAN} ...
1635 By default @option{little} - although chips may hard-wire @option{big}.
1636 Chips that can't change endianness don't need to use this variable.
1637 @item @code{CPUTAPID} ...
1638 When OpenOCD examines the JTAG chain, it can be told verify the
1639 chips against the JTAG IDCODE register.
1640 The target file will hold one or more defaults, but sometimes the
1641 chip in a board will use a different ID (perhaps a newer revision).
1642 @end itemize
1644 Outputs from target config files include:
1646 @itemize @bullet
1647 @item @code{_TARGETNAME} ...
1648 By convention, this variable is created by the target configuration
1649 script. The board configuration file may make use of this variable to
1650 configure things like a ``reset init'' script, or other things
1651 specific to that board and that target.
1652 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1653 @code{_TARGETNAME1}, ... etc.
1654 @end itemize
1656 @subsection The reset-init Event Handler
1657 @cindex event, reset-init
1658 @cindex reset-init handler
1660 Board config files run in the OpenOCD configuration stage;
1661 they can't use TAPs or targets, since they haven't been
1662 fully set up yet.
1663 This means you can't write memory or access chip registers;
1664 you can't even verify that a flash chip is present.
1665 That's done later in event handlers, of which the target @code{reset-init}
1666 handler is one of the most important.
1668 Except on microcontrollers, the basic job of @code{reset-init} event
1669 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1670 Microcontrollers rarely use boot loaders; they run right out of their
1671 on-chip flash and SRAM memory. But they may want to use one of these
1672 handlers too, if just for developer convenience.
1674 @quotation Note
1675 Because this is so very board-specific, and chip-specific, no examples
1676 are included here.
1677 Instead, look at the board config files distributed with OpenOCD.
1678 If you have a boot loader, its source code will help; so will
1679 configuration files for other JTAG tools
1680 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1681 @end quotation
1683 Some of this code could probably be shared between different boards.
1684 For example, setting up a DRAM controller often doesn't differ by
1685 much except the bus width (16 bits or 32?) and memory timings, so a
1686 reusable TCL procedure loaded by the @file{target.cfg} file might take
1687 those as parameters.
1688 Similarly with oscillator, PLL, and clock setup;
1689 and disabling the watchdog.
1690 Structure the code cleanly, and provide comments to help
1691 the next developer doing such work.
1692 (@emph{You might be that next person} trying to reuse init code!)
1694 The last thing normally done in a @code{reset-init} handler is probing
1695 whatever flash memory was configured. For most chips that needs to be
1696 done while the associated target is halted, either because JTAG memory
1697 access uses the CPU or to prevent conflicting CPU access.
1699 @subsection JTAG Clock Rate
1701 Before your @code{reset-init} handler has set up
1702 the PLLs and clocking, you may need to run with
1703 a low JTAG clock rate.
1704 @xref{jtagspeed,,JTAG Speed}.
1705 Then you'd increase that rate after your handler has
1706 made it possible to use the faster JTAG clock.
1707 When the initial low speed is board-specific, for example
1708 because it depends on a board-specific oscillator speed, then
1709 you should probably set it up in the board config file;
1710 if it's target-specific, it belongs in the target config file.
1712 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1713 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1714 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1715 Consult chip documentation to determine the peak JTAG clock rate,
1716 which might be less than that.
1718 @quotation Warning
1719 On most ARMs, JTAG clock detection is coupled to the core clock, so
1720 software using a @option{wait for interrupt} operation blocks JTAG access.
1721 Adaptive clocking provides a partial workaround, but a more complete
1722 solution just avoids using that instruction with JTAG debuggers.
1723 @end quotation
1725 If both the chip and the board support adaptive clocking,
1726 use the @command{jtag_rclk}
1727 command, in case your board is used with JTAG adapter which
1728 also supports it. Otherwise use @command{adapter_khz}.
1729 Set the slow rate at the beginning of the reset sequence,
1730 and the faster rate as soon as the clocks are at full speed.
1732 @anchor{theinitboardprocedure}
1733 @subsection The init_board procedure
1734 @cindex init_board procedure
1736 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1737 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1738 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1739 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1740 spearate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1741 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1742 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1743 Additionally ``linear'' board config file will most likely fail when target config file uses
1744 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1745 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1746 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1747 need to override @code{init_targets} defined in target config files when they only need to to add some specifics.
1749 Just as @code{init_targets}, the @code{init_board} procedure can be overriden by ``next level'' script (which sources
1750 the original), allowing greater code reuse.
1752 @example
1753 ### board_file.cfg ###
1755 # source target file that does most of the config in init_targets
1756 source [find target/target.cfg]
1758 proc enable_fast_clock @{@} @{
1759 # enables fast on-board clock source
1760 # configures the chip to use it
1761 @}
1763 # initialize only board specifics - reset, clock, adapter frequency
1764 proc init_board @{@} @{
1765 reset_config trst_and_srst trst_pulls_srst
1767 $_TARGETNAME configure -event reset-init @{
1768 adapter_khz 1
1769 enable_fast_clock
1770 adapter_khz 10000
1771 @}
1772 @}
1773 @end example
1775 @section Target Config Files
1776 @cindex config file, target
1777 @cindex target config file
1779 Board config files communicate with target config files using
1780 naming conventions as described above, and may source one or
1781 more target config files like this:
1783 @example
1784 source [find target/FOOBAR.cfg]
1785 @end example
1787 The point of a target config file is to package everything
1788 about a given chip that board config files need to know.
1789 In summary the target files should contain
1791 @enumerate
1792 @item Set defaults
1793 @item Add TAPs to the scan chain
1794 @item Add CPU targets (includes GDB support)
1795 @item CPU/Chip/CPU-Core specific features
1796 @item On-Chip flash
1797 @end enumerate
1799 As a rule of thumb, a target file sets up only one chip.
1800 For a microcontroller, that will often include a single TAP,
1801 which is a CPU needing a GDB target, and its on-chip flash.
1803 More complex chips may include multiple TAPs, and the target
1804 config file may need to define them all before OpenOCD
1805 can talk to the chip.
1806 For example, some phone chips have JTAG scan chains that include
1807 an ARM core for operating system use, a DSP,
1808 another ARM core embedded in an image processing engine,
1809 and other processing engines.
1811 @subsection Default Value Boiler Plate Code
1813 All target configuration files should start with code like this,
1814 letting board config files express environment-specific
1815 differences in how things should be set up.
1817 @example
1818 # Boards may override chip names, perhaps based on role,
1819 # but the default should match what the vendor uses
1820 if @{ [info exists CHIPNAME] @} @{
1822 @} else @{
1823 set _CHIPNAME sam7x256
1824 @}
1826 # ONLY use ENDIAN with targets that can change it.
1827 if @{ [info exists ENDIAN] @} @{
1828 set _ENDIAN $ENDIAN
1829 @} else @{
1830 set _ENDIAN little
1831 @}
1833 # TAP identifiers may change as chips mature, for example with
1834 # new revision fields (the "3" here). Pick a good default; you
1835 # can pass several such identifiers to the "jtag newtap" command.
1836 if @{ [info exists CPUTAPID ] @} @{
1838 @} else @{
1839 set _CPUTAPID 0x3f0f0f0f
1840 @}
1841 @end example
1842 @c but 0x3f0f0f0f is for an str73x part ...
1844 @emph{Remember:} Board config files may include multiple target
1845 config files, or the same target file multiple times
1846 (changing at least @code{CHIPNAME}).
1848 Likewise, the target configuration file should define
1849 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1850 use it later on when defining debug targets:
1852 @example
1854 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1855 @end example
1857 @subsection Adding TAPs to the Scan Chain
1858 After the ``defaults'' are set up,
1859 add the TAPs on each chip to the JTAG scan chain.
1860 @xref{TAP Declaration}, and the naming convention
1861 for taps.
1863 In the simplest case the chip has only one TAP,
1864 probably for a CPU or FPGA.
1865 The config file for the Atmel AT91SAM7X256
1866 looks (in part) like this:
1868 @example
1869 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1870 @end example
1872 A board with two such at91sam7 chips would be able
1873 to source such a config file twice, with different
1874 values for @code{CHIPNAME}, so
1875 it adds a different TAP each time.
1877 If there are nonzero @option{-expected-id} values,
1878 OpenOCD attempts to verify the actual tap id against those values.
1879 It will issue error messages if there is mismatch, which
1880 can help to pinpoint problems in OpenOCD configurations.
1882 @example
1883 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1884 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1885 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1886 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1887 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1888 @end example
1890 There are more complex examples too, with chips that have
1891 multiple TAPs. Ones worth looking at include:
1893 @itemize
1894 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1895 plus a JRC to enable them
1896 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1897 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1898 is not currently used)
1899 @end itemize
1901 @subsection Add CPU targets
1903 After adding a TAP for a CPU, you should set it up so that
1904 GDB and other commands can use it.
1905 @xref{CPU Configuration}.
1906 For the at91sam7 example above, the command can look like this;
1907 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1908 to little endian, and this chip doesn't support changing that.
1910 @example
1912 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1913 @end example
1915 Work areas are small RAM areas associated with CPU targets.
1916 They are used by OpenOCD to speed up downloads,
1917 and to download small snippets of code to program flash chips.
1918 If the chip includes a form of ``on-chip-ram'' - and many do - define
1919 a work area if you can.
1920 Again using the at91sam7 as an example, this can look like:
1922 @example
1923 $_TARGETNAME configure -work-area-phys 0x00200000 \
1924 -work-area-size 0x4000 -work-area-backup 0
1925 @end example
1927 @anchor{definecputargetsworkinginsmp}
1928 @subsection Define CPU targets working in SMP
1929 @cindex SMP
1930 After setting targets, you can define a list of targets working in SMP.
1932 @example
1933 set _TARGETNAME_1 $_CHIPNAME.cpu1
1934 set _TARGETNAME_2 $_CHIPNAME.cpu2
1935 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1936 -coreid 0 -dbgbase $_DAP_DBG1
1937 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1938 -coreid 1 -dbgbase $_DAP_DBG2
1939 #define 2 targets working in smp.
1940 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1941 @end example
1942 In the above example on cortex_a, 2 cpus are working in SMP.
1943 In SMP only one GDB instance is created and :
1944 @itemize @bullet
1945 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1946 @item halt command triggers the halt of all targets in the list.
1947 @item resume command triggers the write context and the restart of all targets in the list.
1948 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1949 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1950 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1951 @end itemize
1953 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1954 command have been implemented.
1955 @itemize @bullet
1956 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1957 @item cortex_a smp_off : disable SMP mode, the current target is the one
1958 displayed in the GDB session, only this target is now controlled by GDB
1959 session. This behaviour is useful during system boot up.
1960 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1961 following example.
1962 @end itemize
1964 @example
1965 >cortex_a smp_gdb
1966 gdb coreid 0 -> -1
1967 #0 : coreid 0 is displayed to GDB ,
1968 #-> -1 : next resume triggers a real resume
1969 > cortex_a smp_gdb 1
1970 gdb coreid 0 -> 1
1971 #0 :coreid 0 is displayed to GDB ,
1972 #->1 : next resume displays coreid 1 to GDB
1973 > resume
1974 > cortex_a smp_gdb
1975 gdb coreid 1 -> 1
1976 #1 :coreid 1 is displayed to GDB ,
1977 #->1 : next resume displays coreid 1 to GDB
1978 > cortex_a smp_gdb -1
1979 gdb coreid 1 -> -1
1980 #1 :coreid 1 is displayed to GDB,
1981 #->-1 : next resume triggers a real resume
1982 @end example
1985 @subsection Chip Reset Setup
1987 As a rule, you should put the @command{reset_config} command
1988 into the board file. Most things you think you know about a
1989 chip can be tweaked by the board.
1991 Some chips have specific ways the TRST and SRST signals are
1992 managed. In the unusual case that these are @emph{chip specific}
1993 and can never be changed by board wiring, they could go here.
1994 For example, some chips can't support JTAG debugging without
1995 both signals.
1997 Provide a @code{reset-assert} event handler if you can.
1998 Such a handler uses JTAG operations to reset the target,
1999 letting this target config be used in systems which don't
2000 provide the optional SRST signal, or on systems where you
2001 don't want to reset all targets at once.
2002 Such a handler might write to chip registers to force a reset,
2003 use a JRC to do that (preferable -- the target may be wedged!),
2004 or force a watchdog timer to trigger.
2005 (For Cortex-M targets, this is not necessary. The target
2006 driver knows how to use trigger an NVIC reset when SRST is
2007 not available.)
2009 Some chips need special attention during reset handling if
2010 they're going to be used with JTAG.
2011 An example might be needing to send some commands right
2012 after the target's TAP has been reset, providing a
2013 @code{reset-deassert-post} event handler that writes a chip
2014 register to report that JTAG debugging is being done.
2015 Another would be reconfiguring the watchdog so that it stops
2016 counting while the core is halted in the debugger.
2018 JTAG clocking constraints often change during reset, and in
2019 some cases target config files (rather than board config files)
2020 are the right places to handle some of those issues.
2021 For example, immediately after reset most chips run using a
2022 slower clock than they will use later.
2023 That means that after reset (and potentially, as OpenOCD
2024 first starts up) they must use a slower JTAG clock rate
2025 than they will use later.
2026 @xref{jtagspeed,,JTAG Speed}.
2028 @quotation Important
2029 When you are debugging code that runs right after chip
2030 reset, getting these issues right is critical.
2031 In particular, if you see intermittent failures when
2032 OpenOCD verifies the scan chain after reset,
2033 look at how you are setting up JTAG clocking.
2034 @end quotation
2036 @anchor{theinittargetsprocedure}
2037 @subsection The init_targets procedure
2038 @cindex init_targets procedure
2040 Target config files can either be ``linear'' (script executed line-by-line when parsed in
2041 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
2042 procedure called @code{init_targets}, which will be executed when entering run stage
2043 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
2044 Such procedure can be overriden by ``next level'' script (which sources the original).
2045 This concept faciliates code reuse when basic target config files provide generic configuration
2046 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
2047 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
2048 because sourcing them executes every initialization commands they provide.
2050 @example
2051 ### generic_file.cfg ###
2053 proc setup_my_chip @{chip_name flash_size ram_size@} @{
2054 # basic initialization procedure ...
2055 @}
2057 proc init_targets @{@} @{
2058 # initializes generic chip with 4kB of flash and 1kB of RAM
2059 setup_my_chip MY_GENERIC_CHIP 4096 1024
2060 @}
2062 ### specific_file.cfg ###
2064 source [find target/generic_file.cfg]
2066 proc init_targets @{@} @{
2067 # initializes specific chip with 128kB of flash and 64kB of RAM
2068 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
2069 @}
2070 @end example
2072 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
2073 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
2075 For an example of this scheme see LPC2000 target config files.
2077 The @code{init_boards} procedure is a similar concept concerning board config files
2078 (@xref{theinitboardprocedure,,The init_board procedure}.)
2080 @subsection ARM Core Specific Hacks
2082 If the chip has a DCC, enable it. If the chip is an ARM9 with some
2083 special high speed download features - enable it.
2085 If present, the MMU, the MPU and the CACHE should be disabled.
2087 Some ARM cores are equipped with trace support, which permits
2088 examination of the instruction and data bus activity. Trace
2089 activity is controlled through an ``Embedded Trace Module'' (ETM)
2090 on one of the core's scan chains. The ETM emits voluminous data
2091 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
2092 If you are using an external trace port,
2093 configure it in your board config file.
2094 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2095 configure it in your target config file.
2097 @example
2098 etm config $_TARGETNAME 16 normal full etb
2099 etb config $_TARGETNAME $_CHIPNAME.etb
2100 @end example
2102 @subsection Internal Flash Configuration
2104 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2106 @b{Never ever} in the ``target configuration file'' define any type of
2107 flash that is external to the chip. (For example a BOOT flash on
2108 Chip Select 0.) Such flash information goes in a board file - not
2109 the TARGET (chip) file.
2111 Examples:
2112 @itemize @bullet
2113 @item at91sam7x256 - has 256K flash YES enable it.
2114 @item str912 - has flash internal YES enable it.
2115 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2116 @item pxa270 - again - CS0 flash - it goes in the board file.
2117 @end itemize
2119 @anchor{translatingconfigurationfiles}
2120 @section Translating Configuration Files
2121 @cindex translation
2122 If you have a configuration file for another hardware debugger
2123 or toolset (Abatron, BDI2000, BDI3000, CCS,
2124 Lauterbach, Segger, Macraigor, etc.), translating
2125 it into OpenOCD syntax is often quite straightforward. The most tricky
2126 part of creating a configuration script is oftentimes the reset init
2127 sequence where e.g. PLLs, DRAM and the like is set up.
2129 One trick that you can use when translating is to write small
2130 Tcl procedures to translate the syntax into OpenOCD syntax. This
2131 can avoid manual translation errors and make it easier to
2132 convert other scripts later on.
2134 Example of transforming quirky arguments to a simple search and
2135 replace job:
2137 @example
2138 # Lauterbach syntax(?)
2139 #
2140 # Data.Set c15:0x042f %long 0x40000015
2141 #
2142 # OpenOCD syntax when using procedure below.
2143 #
2144 # setc15 0x01 0x00050078
2146 proc setc15 @{regs value@} @{
2147 global TARGETNAME
2149 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2151 arm mcr 15 [expr ($regs>>12)&0x7] \
2152 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2153 [expr ($regs>>8)&0x7] $value
2154 @}
2155 @end example
2159 @node Daemon Configuration
2160 @chapter Daemon Configuration
2161 @cindex initialization
2162 The commands here are commonly found in the openocd.cfg file and are
2163 used to specify what TCP/IP ports are used, and how GDB should be
2164 supported.
2166 @anchor{configurationstage}
2167 @section Configuration Stage
2168 @cindex configuration stage
2169 @cindex config command
2171 When the OpenOCD server process starts up, it enters a
2172 @emph{configuration stage} which is the only time that
2173 certain commands, @emph{configuration commands}, may be issued.
2174 Normally, configuration commands are only available
2175 inside startup scripts.
2177 In this manual, the definition of a configuration command is
2178 presented as a @emph{Config Command}, not as a @emph{Command}
2179 which may be issued interactively.
2180 The runtime @command{help} command also highlights configuration
2181 commands, and those which may be issued at any time.
2183 Those configuration commands include declaration of TAPs,
2184 flash banks,
2185 the interface used for JTAG communication,
2186 and other basic setup.
2187 The server must leave the configuration stage before it
2188 may access or activate TAPs.
2189 After it leaves this stage, configuration commands may no
2190 longer be issued.
2192 @anchor{enteringtherunstage}
2193 @section Entering the Run Stage
2195 The first thing OpenOCD does after leaving the configuration
2196 stage is to verify that it can talk to the scan chain
2197 (list of TAPs) which has been configured.
2198 It will warn if it doesn't find TAPs it expects to find,
2199 or finds TAPs that aren't supposed to be there.
2200 You should see no errors at this point.
2201 If you see errors, resolve them by correcting the
2202 commands you used to configure the server.
2203 Common errors include using an initial JTAG speed that's too
2204 fast, and not providing the right IDCODE values for the TAPs
2205 on the scan chain.
2207 Once OpenOCD has entered the run stage, a number of commands
2208 become available.
2209 A number of these relate to the debug targets you may have declared.
2210 For example, the @command{mww} command will not be available until
2211 a target has been successfuly instantiated.
2212 If you want to use those commands, you may need to force
2213 entry to the run stage.
2215 @deffn {Config Command} init
2216 This command terminates the configuration stage and
2217 enters the run stage. This helps when you need to have
2218 the startup scripts manage tasks such as resetting the target,
2219 programming flash, etc. To reset the CPU upon startup, add "init" and
2220 "reset" at the end of the config script or at the end of the OpenOCD
2221 command line using the @option{-c} command line switch.
2223 If this command does not appear in any startup/configuration file
2224 OpenOCD executes the command for you after processing all
2225 configuration files and/or command line options.
2227 @b{NOTE:} This command normally occurs at or near the end of your
2228 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2229 targets ready. For example: If your openocd.cfg file needs to
2230 read/write memory on your target, @command{init} must occur before
2231 the memory read/write commands. This includes @command{nand probe}.
2232 @end deffn
2234 @deffn {Overridable Procedure} jtag_init
2235 This is invoked at server startup to verify that it can talk
2236 to the scan chain (list of TAPs) which has been configured.
2238 The default implementation first tries @command{jtag arp_init},
2239 which uses only a lightweight JTAG reset before examining the
2240 scan chain.
2241 If that fails, it tries again, using a harder reset
2242 from the overridable procedure @command{init_reset}.
2244 Implementations must have verified the JTAG scan chain before
2245 they return.
2246 This is done by calling @command{jtag arp_init}
2247 (or @command{jtag arp_init-reset}).
2248 @end deffn
2250 @anchor{tcpipports}
2251 @section TCP/IP Ports
2252 @cindex TCP port
2253 @cindex server
2254 @cindex port
2255 @cindex security
2256 The OpenOCD server accepts remote commands in several syntaxes.
2257 Each syntax uses a different TCP/IP port, which you may specify
2258 only during configuration (before those ports are opened).
2260 For reasons including security, you may wish to prevent remote
2261 access using one or more of these ports.
2262 In such cases, just specify the relevant port number as zero.
2263 If you disable all access through TCP/IP, you will need to
2264 use the command line @option{-pipe} option.
2266 @deffn {Command} gdb_port [number]
2267 @cindex GDB server
2268 Normally gdb listens to a TCP/IP port, but GDB can also
2269 communicate via pipes(stdin/out or named pipes). The name
2270 "gdb_port" stuck because it covers probably more than 90% of
2271 the normal use cases.
2273 No arguments reports GDB port. "pipe" means listen to stdin
2274 output to stdout, an integer is base port number, "disable"
2275 disables the gdb server.
2277 When using "pipe", also use log_output to redirect the log
2278 output to a file so as not to flood the stdin/out pipes.
2280 The -p/--pipe option is deprecated and a warning is printed
2281 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2283 Any other string is interpreted as named pipe to listen to.
2284 Output pipe is the same name as input pipe, but with 'o' appended,
2285 e.g. /var/gdb, /var/gdbo.
2287 The GDB port for the first target will be the base port, the
2288 second target will listen on gdb_port + 1, and so on.
2289 When not specified during the configuration stage,
2290 the port @var{number} defaults to 3333.
2291 @end deffn
2293 @deffn {Command} tcl_port [number]
2294 Specify or query the port used for a simplified RPC
2295 connection that can be used by clients to issue TCL commands and get the
2296 output from the Tcl engine.
2297 Intended as a machine interface.
2298 When not specified during the configuration stage,
2299 the port @var{number} defaults to 6666.
2301 @end deffn
2303 @deffn {Command} telnet_port [number]
2304 Specify or query the
2305 port on which to listen for incoming telnet connections.
2306 This port is intended for interaction with one human through TCL commands.
2307 When not specified during the configuration stage,
2308 the port @var{number} defaults to 4444.
2309 When specified as zero, this port is not activated.
2310 @end deffn
2312 @anchor{gdbconfiguration}
2313 @section GDB Configuration
2314 @cindex GDB
2315 @cindex GDB configuration
2316 You can reconfigure some GDB behaviors if needed.
2317 The ones listed here are static and global.
2318 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2319 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2321 @anchor{gdbbreakpointoverride}
2322 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2323 Force breakpoint type for gdb @command{break} commands.
2324 This option supports GDB GUIs which don't
2325 distinguish hard versus soft breakpoints, if the default OpenOCD and
2326 GDB behaviour is not sufficient. GDB normally uses hardware
2327 breakpoints if the memory map has been set up for flash regions.
2328 @end deffn
2330 @anchor{gdbflashprogram}
2331 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2332 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2333 vFlash packet is received.
2334 The default behaviour is @option{enable}.
2335 @end deffn
2337 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2338 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2339 requested. GDB will then know when to set hardware breakpoints, and program flash
2340 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2341 for flash programming to work.
2342 Default behaviour is @option{enable}.
2343 @xref{gdbflashprogram,,gdb_flash_program}.
2344 @end deffn
2346 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2347 Specifies whether data aborts cause an error to be reported
2348 by GDB memory read packets.
2349 The default behaviour is @option{disable};
2350 use @option{enable} see these errors reported.
2351 @end deffn
2353 @anchor{eventpolling}
2354 @section Event Polling
2356 Hardware debuggers are parts of asynchronous systems,
2357 where significant events can happen at any time.
2358 The OpenOCD server needs to detect some of these events,
2359 so it can report them to through TCL command line
2360 or to GDB.
2362 Examples of such events include:
2364 @itemize
2365 @item One of the targets can stop running ... maybe it triggers
2366 a code breakpoint or data watchpoint, or halts itself.
2367 @item Messages may be sent over ``debug message'' channels ... many
2368 targets support such messages sent over JTAG,
2369 for receipt by the person debugging or tools.
2370 @item Loss of power ... some adapters can detect these events.
2371 @item Resets not issued through JTAG ... such reset sources
2372 can include button presses or other system hardware, sometimes
2373 including the target itself (perhaps through a watchdog).
2374 @item Debug instrumentation sometimes supports event triggering
2375 such as ``trace buffer full'' (so it can quickly be emptied)
2376 or other signals (to correlate with code behavior).
2377 @end itemize
2379 None of those events are signaled through standard JTAG signals.
2380 However, most conventions for JTAG connectors include voltage
2381 level and system reset (SRST) signal detection.
2382 Some connectors also include instrumentation signals, which
2383 can imply events when those signals are inputs.
2385 In general, OpenOCD needs to periodically check for those events,
2386 either by looking at the status of signals on the JTAG connector
2387 or by sending synchronous ``tell me your status'' JTAG requests
2388 to the various active targets.
2389 There is a command to manage and monitor that polling,
2390 which is normally done in the background.
2392 @deffn Command poll [@option{on}|@option{off}]
2393 Poll the current target for its current state.
2394 (Also, @pxref{targetcurstate,,target curstate}.)
2395 If that target is in debug mode, architecture
2396 specific information about the current state is printed.
2397 An optional parameter
2398 allows background polling to be enabled and disabled.
2400 You could use this from the TCL command shell, or
2401 from GDB using @command{monitor poll} command.
2402 Leave background polling enabled while you're using GDB.
2403 @example
2404 > poll
2405 background polling: on
2406 target state: halted
2407 target halted in ARM state due to debug-request, \
2408 current mode: Supervisor
2409 cpsr: 0x800000d3 pc: 0x11081bfc
2410 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2411 >
2412 @end example
2413 @end deffn
2415 @node Debug Adapter Configuration
2416 @chapter Debug Adapter Configuration
2417 @cindex config file, interface
2418 @cindex interface config file
2420 Correctly installing OpenOCD includes making your operating system give
2421 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2422 are used to select which one is used, and to configure how it is used.
2424 @quotation Note
2425 Because OpenOCD started out with a focus purely on JTAG, you may find
2426 places where it wrongly presumes JTAG is the only transport protocol
2427 in use. Be aware that recent versions of OpenOCD are removing that
2428 limitation. JTAG remains more functional than most other transports.
2429 Other transports do not support boundary scan operations, or may be
2430 specific to a given chip vendor. Some might be usable only for
2431 programming flash memory, instead of also for debugging.
2432 @end quotation
2434 Debug Adapters/Interfaces/Dongles are normally configured
2435 through commands in an interface configuration
2436 file which is sourced by your @file{openocd.cfg} file, or
2437 through a command line @option{-f interface/....cfg} option.
2439 @example
2440 source [find interface/olimex-jtag-tiny.cfg]
2441 @end example
2443 These commands tell
2444 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2445 A few cases are so simple that you only need to say what driver to use:
2447 @example
2448 # jlink interface
2449 interface jlink
2450 @end example
2452 Most adapters need a bit more configuration than that.
2455 @section Interface Configuration
2457 The interface command tells OpenOCD what type of debug adapter you are
2458 using. Depending on the type of adapter, you may need to use one or
2459 more additional commands to further identify or configure the adapter.
2461 @deffn {Config Command} {interface} name
2462 Use the interface driver @var{name} to connect to the
2463 target.
2464 @end deffn
2466 @deffn Command {interface_list}
2467 List the debug adapter drivers that have been built into
2468 the running copy of OpenOCD.
2469 @end deffn
2470 @deffn Command {interface transports} transport_name+
2471 Specifies the transports supported by this debug adapter.
2472 The adapter driver builds-in similar knowledge; use this only
2473 when external configuration (such as jumpering) changes what
2474 the hardware can support.
2475 @end deffn
2479 @deffn Command {adapter_name}
2480 Returns the name of the debug adapter driver being used.
2481 @end deffn
2483 @section Interface Drivers
2485 Each of the interface drivers listed here must be explicitly
2486 enabled when OpenOCD is configured, in order to be made
2487 available at run time.
2489 @deffn {Interface Driver} {amt_jtagaccel}
2490 Amontec Chameleon in its JTAG Accelerator configuration,
2491 connected to a PC's EPP mode parallel port.
2492 This defines some driver-specific commands:
2494 @deffn {Config Command} {parport_port} number
2495 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2496 the number of the @file{/dev/parport} device.
2497 @end deffn
2499 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2500 Displays status of RTCK option.
2501 Optionally sets that option first.
2502 @end deffn
2503 @end deffn
2505 @deffn {Interface Driver} {arm-jtag-ew}
2506 Olimex ARM-JTAG-EW USB adapter
2507 This has one driver-specific command:
2509 @deffn Command {armjtagew_info}
2510 Logs some status
2511 @end deffn
2512 @end deffn
2514 @deffn {Interface Driver} {at91rm9200}
2515 Supports bitbanged JTAG from the local system,
2516 presuming that system is an Atmel AT91rm9200
2517 and a specific set of GPIOs is used.
2518 @c command: at91rm9200_device NAME
2519 @c chooses among list of bit configs ... only one option
2520 @end deffn
2522 @deffn {Interface Driver} {dummy}
2523 A dummy software-only driver for debugging.
2524 @end deffn
2526 @deffn {Interface Driver} {ep93xx}
2527 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2528 @end deffn
2530 @deffn {Interface Driver} {ft2232}
2531 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2533 Note that this driver has several flaws and the @command{ftdi} driver is
2534 recommended as its replacement.
2536 These interfaces have several commands, used to configure the driver
2537 before initializing the JTAG scan chain:
2539 @deffn {Config Command} {ft2232_device_desc} description
2540 Provides the USB device description (the @emph{iProduct string})
2541 of the FTDI FT2232 device. If not
2542 specified, the FTDI default value is used. This setting is only valid
2543 if compiled with FTD2XX support.
2544 @end deffn
2546 @deffn {Config Command} {ft2232_serial} serial-number
2547 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2548 in case the vendor provides unique IDs and more than one FT2232 device
2549 is connected to the host.
2550 If not specified, serial numbers are not considered.
2551 (Note that USB serial numbers can be arbitrary Unicode strings,
2552 and are not restricted to containing only decimal digits.)
2553 @end deffn
2555 @deffn {Config Command} {ft2232_layout} name
2556 Each vendor's FT2232 device can use different GPIO signals
2557 to control output-enables, reset signals, and LEDs.
2558 Currently valid layout @var{name} values include:
2559 @itemize @minus
2560 @item @b{axm0432_jtag} Axiom AXM-0432
2561 @item @b{comstick} Hitex STR9 comstick
2562 @item @b{cortino} Hitex Cortino JTAG interface
2563 @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
2564 either for the local Cortex-M3 (SRST only)
2565 or in a passthrough mode (neither SRST nor TRST)
2566 This layout can not support the SWO trace mechanism, and should be
2567 used only for older boards (before rev C).
2568 @item @b{luminary_icdi} This layout should be used with most TI/Luminary
2569 eval boards, including Rev C LM3S811 eval boards and the eponymous
2570 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2571 to debug some other target. It can support the SWO trace mechanism.
2572 @item @b{flyswatter} Tin Can Tools Flyswatter
2573 @item @b{icebear} ICEbear JTAG adapter from Section 5
2574 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2575 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2576 @item @b{m5960} American Microsystems M5960
2577 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2578 @item @b{oocdlink} OOCDLink
2579 @c oocdlink ~= jtagkey_prototype_v1
2580 @item @b{redbee-econotag} Integrated with a Redbee development board.
2581 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2582 @item @b{sheevaplug} Marvell Sheevaplug development kit
2583 @item @b{signalyzer} Xverve Signalyzer
2584 @item @b{stm32stick} Hitex STM32 Performance Stick
2585 @item @b{turtelizer2} egnite Software turtelizer2
2586 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2587 @end itemize
2588 @end deffn
2590 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2591 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2592 default values are used.
2593 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2594 @example
2595 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2596 @end example
2597 @end deffn
2599 @deffn {Config Command} {ft2232_latency} ms
2600 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2601 ft2232_read() fails to return the expected number of bytes. This can be caused by
2602 USB communication delays and has proved hard to reproduce and debug. Setting the
2603 FT2232 latency timer to a larger value increases delays for short USB packets but it
2604 also reduces the risk of timeouts before receiving the expected number of bytes.
2605 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2606 @end deffn
2608 @deffn {Config Command} {ft2232_channel} channel
2609 Used to select the channel of the ft2232 chip to use (between 1 and 4).
2610 The default value is 1.
2611 @end deffn
2613 For example, the interface config file for a
2614 Turtelizer JTAG Adapter looks something like this:
2616 @example
2617 interface ft2232
2618 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2619 ft2232_layout turtelizer2
2620 ft2232_vid_pid 0x0403 0xbdc8
2621 @end example
2622 @end deffn
2624 @deffn {Interface Driver} {ftdi}
2625 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2626 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2627 It is a complete rewrite to address a large number of problems with the ft2232
2628 interface driver.
2630 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2631 bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
2632 consistently faster than the ft2232 driver, sometimes several times faster.
2634 A major improvement of this driver is that support for new FTDI based adapters
2635 can be added competely through configuration files, without the need to patch
2636 and rebuild OpenOCD.
2638 The driver uses a signal abstraction to enable Tcl configuration files to
2639 define outputs for one or several FTDI GPIO. These outputs can then be
2640 controlled using the @command{ftdi_set_signal} command. Special signal names
2641 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2642 will be used for their customary purpose.
2644 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2645 be controlled differently. In order to support tristateable signals such as
2646 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2647 signal. The following output buffer configurations are supported:
2649 @itemize @minus
2650 @item Push-pull with one FTDI output as (non-)inverted data line
2651 @item Open drain with one FTDI output as (non-)inverted output-enable
2652 @item Tristate with one FTDI output as (non-)inverted data line and another
2653 FTDI output as (non-)inverted output-enable
2654 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2655 switching data and direction as necessary
2656 @end itemize
2658 These interfaces have several commands, used to configure the driver
2659 before initializing the JTAG scan chain:
2661 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2662 The vendor ID and product ID of the adapter. If not specified, the FTDI
2663 default values are used.
2664 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2665 @example
2666 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2667 @end example
2668 @end deffn
2670 @deffn {Config Command} {ftdi_device_desc} description
2671 Provides the USB device description (the @emph{iProduct string})
2672 of the adapter. If not specified, the device description is ignored
2673 during device selection.
2674 @end deffn
2676 @deffn {Config Command} {ftdi_serial} serial-number
2677 Specifies the @var{serial-number} of the adapter to use,
2678 in case the vendor provides unique IDs and more than one adapter
2679 is connected to the host.
2680 If not specified, serial numbers are not considered.
2681 (Note that USB serial numbers can be arbitrary Unicode strings,
2682 and are not restricted to containing only decimal digits.)
2683 @end deffn
2685 @deffn {Config Command} {ftdi_channel} channel
2686 Selects the channel of the FTDI device to use for MPSSE operations. Most
2687 adapters use the default, channel 0, but there are exceptions.
2688 @end deffn
2690 @deffn {Config Command} {ftdi_layout_init} data direction
2691 Specifies the initial values of the FTDI GPIO data and direction registers.
2692 Each value is a 16-bit number corresponding to the concatenation of the high
2693 and low FTDI GPIO registers. The values should be selected based on the
2694 schematics of the adapter, such that all signals are set to safe levels with
2695 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2696 and initially asserted reset signals.
2697 @end deffn
2699 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask]
2700 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2701 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2702 register bitmasks to tell the driver the connection and type of the output
2703 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2704 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2705 used with inverting data inputs and @option{-data} with non-inverting inputs.
2706 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2707 not-output-enable) input to the output buffer is connected.
2709 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2710 simple open-collector transistor driver would be specified with @option{-oe}
2711 only. In that case the signal can only be set to drive low or to Hi-Z and the
2712 driver will complain if the signal is set to drive high. Which means that if
2713 it's a reset signal, @command{reset_config} must be specified as
2714 @option{srst_open_drain}, not @option{srst_push_pull}.
2716 A special case is provided when @option{-data} and @option{-oe} is set to the
2717 same bitmask. Then the FTDI pin is considered being connected straight to the
2718 target without any buffer. The FTDI pin is then switched between output and
2719 input as necessary to provide the full set of low, high and Hi-Z
2720 characteristics. In all other cases, the pins specified in a signal definition
2721 are always driven by the FTDI.
2722 @end deffn
2724 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2725 Set a previously defined signal to the specified level.
2726 @itemize @minus
2727 @item @option{0}, drive low
2728 @item @option{1}, drive high
2729 @item @option{z}, set to high-impedance
2730 @end itemize
2731 @end deffn
2733 For example adapter definitions, see the configuration files shipped in the
2734 @file{interface/ftdi} directory.
2735 @end deffn
2737 @deffn {Interface Driver} {remote_bitbang}
2738 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2739 with a remote process and sends ASCII encoded bitbang requests to that process
2740 instead of directly driving JTAG.
2742 The remote_bitbang driver is useful for debugging software running on
2743 processors which are being simulated.
2745 @deffn {Config Command} {remote_bitbang_port} number
2746 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2747 sockets instead of TCP.
2748 @end deffn
2750 @deffn {Config Command} {remote_bitbang_host} hostname
2751 Specifies the hostname of the remote process to connect to using TCP, or the
2752 name of the UNIX socket to use if remote_bitbang_port is 0.
2753 @end deffn
2755 For example, to connect remotely via TCP to the host foobar you might have
2756 something like:
2758 @example
2759 interface remote_bitbang
2760 remote_bitbang_port 3335
2761 remote_bitbang_host foobar
2762 @end example
2764 To connect to another process running locally via UNIX sockets with socket
2765 named mysocket:
2767 @example
2768 interface remote_bitbang
2769 remote_bitbang_port 0
2770 remote_bitbang_host mysocket
2771 @end example
2772 @end deffn
2774 @deffn {Interface Driver} {usb_blaster}
2775 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2776 for FTDI chips. These interfaces have several commands, used to
2777 configure the driver before initializing the JTAG scan chain:
2779 @deffn {Config Command} {usb_blaster_device_desc} description
2780 Provides the USB device description (the @emph{iProduct string})
2781 of the FTDI FT245 device. If not
2782 specified, the FTDI default value is used. This setting is only valid
2783 if compiled with FTD2XX support.
2784 @end deffn
2786 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2787 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2788 default values are used.
2789 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2790 Altera USB-Blaster (default):
2791 @example
2792 usb_blaster_vid_pid 0x09FB 0x6001
2793 @end example
2794 The following VID/PID is for Kolja Waschk's USB JTAG:
2795 @example
2796 usb_blaster_vid_pid 0x16C0 0x06AD
2797 @end example
2798 @end deffn
2800 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2801 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2802 female JTAG header). These pins can be used as SRST and/or TRST provided the
2803 appropriate connections are made on the target board.
2805 For example, to use pin 6 as SRST (as with an AVR board):
2806 @example
2807 $_TARGETNAME configure -event reset-assert \
2808 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2809 @end example
2810 @end deffn
2812 @end deffn
2814 @deffn {Interface Driver} {gw16012}
2815 Gateworks GW16012 JTAG programmer.
2816 This has one driver-specific command:
2818 @deffn {Config Command} {parport_port} [port_number]
2819 Display either the address of the I/O port
2820 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2821 If a parameter is provided, first switch to use that port.
2822 This is a write-once setting.
2823 @end deffn
2824 @end deffn
2826 @deffn {Interface Driver} {jlink}
2827 Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
2829 @quotation Compatibility Note
2830 Segger released many firmware versions for the many harware versions they
2831 produced. OpenOCD was extensively tested and intended to run on all of them,
2832 but some combinations were reported as incompatible. As a general
2833 recommendation, it is advisable to use the latest firmware version
2834 available for each hardware version. However the current V8 is a moving
2835 target, and Segger firmware versions released after the OpenOCD was
2836 released may not be compatible. In such cases it is recommended to
2837 revert to the last known functional version. For 0.5.0, this is from
2838 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2839 version is from "May 3 2012 18:36:22", packed with 4.46f.
2840 @end quotation
2842 @deffn {Command} {jlink caps}
2843 Display the device firmware capabilities.
2844 @end deffn
2845 @deffn {Command} {jlink info}
2846 Display various device information, like hardware version, firmware version, current bus status.
2847 @end deffn
2848 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2849 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2850 @end deffn
2851 @deffn {Command} {jlink config}
2852 Display the J-Link configuration.
2853 @end deffn
2854 @deffn {Command} {jlink config kickstart} [val]
2855 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2856 @end deffn
2857 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2858 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2859 @end deffn
2860 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2861 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2862 E the bit of the subnet mask and
2863 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2864 @end deffn
2865 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2866 Set the USB address; this will also change the product id. Without argument, show the USB address.
2867 @end deffn
2868 @deffn {Command} {jlink config reset}
2869 Reset the current configuration.
2870 @end deffn
2871 @deffn {Command} {jlink config save}
2872 Save the current configuration to the internal persistent storage.
2873 @end deffn
2874 @deffn {Config} {jlink pid} val
2875 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2876 @end deffn
2877 @end deffn
2879 @deffn {Interface Driver} {parport}
2880 Supports PC parallel port bit-banging cables:
2881 Wigglers, PLD download cable, and more.
2882 These interfaces have several commands, used to configure the driver
2883 before initializing the JTAG scan chain:
2885 @deffn {Config Command} {parport_cable} name
2886 Set the layout of the parallel port cable used to connect to the target.
2887 This is a write-once setting.
2888 Currently valid cable @var{name} values include:
2890 @itemize @minus
2891 @item @b{altium} Altium Universal JTAG cable.
2892 @item @b{arm-jtag} Same as original wiggler except SRST and
2893 TRST connections reversed and TRST is also inverted.
2894 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2895 in configuration mode. This is only used to
2896 program the Chameleon itself, not a connected target.
2897 @item @b{dlc5} The Xilinx Parallel cable III.
2898 @item @b{flashlink} The ST Parallel cable.
2899 @item @b{lattice} Lattice ispDOWNLOAD Cable
2900 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2901 some versions of
2902 Amontec's Chameleon Programmer. The new version available from
2903 the website uses the original Wiggler layout ('@var{wiggler}')
2904 @item @b{triton} The parallel port adapter found on the
2905 ``Karo Triton 1 Development Board''.
2906 This is also the layout used by the HollyGates design
2907 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2908 @item @b{wiggler} The original Wiggler layout, also supported by
2909 several clones, such as the Olimex ARM-JTAG
2910 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2911 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2912 @end itemize
2913 @end deffn
2915 @deffn {Config Command} {parport_port} [port_number]
2916 Display either the address of the I/O port
2917 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2918 If a parameter is provided, first switch to use that port.
2919 This is a write-once setting.
2921 When using PPDEV to access the parallel port, use the number of the parallel port:
2922 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2923 you may encounter a problem.
2924 @end deffn
2926 @deffn Command {parport_toggling_time} [nanoseconds]
2927 Displays how many nanoseconds the hardware needs to toggle TCK;
2928 the parport driver uses this value to obey the
2929 @command{adapter_khz} configuration.
2930 When the optional @var{nanoseconds} parameter is given,
2931 that setting is changed before displaying the current value.
2933 The default setting should work reasonably well on commodity PC hardware.
2934 However, you may want to calibrate for your specific hardware.
2935 @quotation Tip
2936 To measure the toggling time with a logic analyzer or a digital storage
2937 oscilloscope, follow the procedure below:
2938 @example
2939 > parport_toggling_time 1000
2940 > adapter_khz 500
2941 @end example
2942 This sets the maximum JTAG clock speed of the hardware, but
2943 the actual speed probably deviates from the requested 500 kHz.
2944 Now, measure the time between the two closest spaced TCK transitions.
2945 You can use @command{runtest 1000} or something similar to generate a
2946 large set of samples.
2947 Update the setting to match your measurement:
2948 @example
2949 > parport_toggling_time <measured nanoseconds>
2950 @end example
2951 Now the clock speed will be a better match for @command{adapter_khz rate}
2952 commands given in OpenOCD scripts and event handlers.
2954 You can do something similar with many digital multimeters, but note
2955 that you'll probably need to run the clock continuously for several
2956 seconds before it decides what clock rate to show. Adjust the
2957 toggling time up or down until the measured clock rate is a good
2958 match for the adapter_khz rate you specified; be conservative.
2959 @end quotation
2960 @end deffn
2962 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2963 This will configure the parallel driver to write a known
2964 cable-specific value to the parallel interface on exiting OpenOCD.
2965 @end deffn
2967 For example, the interface configuration file for a
2968 classic ``Wiggler'' cable on LPT2 might look something like this:
2970 @example
2971 interface parport
2972 parport_port 0x278
2973 parport_cable wiggler
2974 @end example
2975 @end deffn
2977 @deffn {Interface Driver} {presto}
2978 ASIX PRESTO USB JTAG programmer.
2979 @deffn {Config Command} {presto_serial} serial_string
2980 Configures the USB serial number of the Presto device to use.
2981 @end deffn
2982 @end deffn
2984 @deffn {Interface Driver} {rlink}
2985 Raisonance RLink USB adapter
2986 @end deffn
2988 @deffn {Interface Driver} {usbprog}
2989 usbprog is a freely programmable USB adapter.
2990 @end deffn
2992 @deffn {Interface Driver} {vsllink}
2993 vsllink is part of Versaloon which is a versatile USB programmer.
2995 @quotation Note
2996 This defines quite a few driver-specific commands,
2997 which are not currently documented here.
2998 @end quotation
2999 @end deffn
3001 @deffn {Interface Driver} {hla}
3002 This is a driver that supports multiple High Level Adapters.
3003 This type of adapter does not expose some of the lower level api's
3004 that OpenOCD would normally use to access the target.
3006 Currently supported adapters include the ST STLINK and TI ICDI.
3008 @deffn {Config Command} {hla_device_desc} description
3009 Currently Not Supported.
3010 @end deffn
3012 @deffn {Config Command} {hla_serial} serial
3013 Currently Not Supported.
3014 @end deffn
3016 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
3017 Specifies the adapter layout to use.
3018 @end deffn
3020 @deffn {Config Command} {hla_vid_pid} vid pid
3021 The vendor ID and product ID of the device.
3022 @end deffn
3024 @deffn {Config Command} {stlink_api} api_level
3025 Manually sets the stlink api used, valid options are 1 or 2. (@b{STLINK Only}).
3026 @end deffn
3027 @end deffn
3029 @deffn {Interface Driver} {opendous}
3030 opendous-jtag is a freely programmable USB adapter.
3031 @end deffn
3033 @deffn {Interface Driver} {ulink}
3034 This is the Keil ULINK v1 JTAG debugger.
3035 @end deffn
3037 @deffn {Interface Driver} {ZY1000}
3038 This is the Zylin ZY1000 JTAG debugger.
3039 @end deffn
3041 @quotation Note
3042 This defines some driver-specific commands,
3043 which are not currently documented here.
3044 @end quotation
3046 @deffn Command power [@option{on}|@option{off}]
3047 Turn power switch to target on/off.
3048 No arguments: print status.
3049 @end deffn
3051 @section Transport Configuration
3052 @cindex Transport
3053 As noted earlier, depending on the version of OpenOCD you use,
3054 and the debug adapter you are using,
3055 several transports may be available to
3056 communicate with debug targets (or perhaps to program flash memory).
3057 @deffn Command {transport list}
3058 displays the names of the transports supported by this
3059 version of OpenOCD.
3060 @end deffn
3062 @deffn Command {transport select} transport_name
3063 Select which of the supported transports to use in this OpenOCD session.
3064 The transport must be supported by the debug adapter hardware and by the
3065 version of OPenOCD you are using (including the adapter's driver).
3066 No arguments: returns name of session's selected transport.
3067 @end deffn
3069 @subsection JTAG Transport
3070 @cindex JTAG
3071 JTAG is the original transport supported by OpenOCD, and most
3072 of the OpenOCD commands support it.
3073 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3074 each of which must be explicitly declared.
3075 JTAG supports both debugging and boundary scan testing.
3076 Flash programming support is built on top of debug support.
3077 @subsection SWD Transport
3078 @cindex SWD
3079 @cindex Serial Wire Debug
3080 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3081 Debug Access Point (DAP, which must be explicitly declared.
3082 (SWD uses fewer signal wires than JTAG.)
3083 SWD is debug-oriented, and does not support boundary scan testing.
3084 Flash programming support is built on top of debug support.
3085 (Some processors support both JTAG and SWD.)
3086 @deffn Command {swd newdap} ...
3087 Declares a single DAP which uses SWD transport.
3088 Parameters are currently the same as "jtag newtap" but this is
3089 expected to change.
3090 @end deffn
3091 @deffn Command {swd wcr trn prescale}
3092 Updates TRN (turnaraound delay) and prescaling.fields of the
3093 Wire Control Register (WCR).
3094 No parameters: displays current settings.
3095 @end deffn
3097 @subsection SPI Transport
3098 @cindex SPI
3099 @cindex Serial Peripheral Interface
3100 The Serial Peripheral Interface (SPI) is a general purpose transport
3101 which uses four wire signaling. Some processors use it as part of a
3102 solution for flash programming.
3104 @anchor{jtagspeed}
3105 @section JTAG Speed
3106 JTAG clock setup is part of system setup.
3107 It @emph{does not belong with interface setup} since any interface
3108 only knows a few of the constraints for the JTAG clock speed.
3109 Sometimes the JTAG speed is
3110 changed during the target initialization process: (1) slow at
3111 reset, (2) program the CPU clocks, (3) run fast.
3112 Both the "slow" and "fast" clock rates are functions of the
3113 oscillators used, the chip, the board design, and sometimes
3114 power management software that may be active.
3116 The speed used during reset, and the scan chain verification which
3117 follows reset, can be adjusted using a @code{reset-start}
3118 target event handler.
3119 It can then be reconfigured to a faster speed by a
3120 @code{reset-init} target event handler after it reprograms those
3121 CPU clocks, or manually (if something else, such as a boot loader,
3122 sets up those clocks).
3123 @xref{targetevents,,Target Events}.
3124 When the initial low JTAG speed is a chip characteristic, perhaps
3125 because of a required oscillator speed, provide such a handler
3126 in the target config file.
3127 When that speed is a function of a board-specific characteristic
3128 such as which speed oscillator is used, it belongs in the board
3129 config file instead.
3130 In both cases it's safest to also set the initial JTAG clock rate
3131 to that same slow speed, so that OpenOCD never starts up using a
3132 clock speed that's faster than the scan chain can support.
3134 @example
3135 jtag_rclk 3000
3136 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3137 @end example
3139 If your system supports adaptive clocking (RTCK), configuring
3140 JTAG to use that is probably the most robust approach.
3141 However, it introduces delays to synchronize clocks; so it
3142 may not be the fastest solution.
3144 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3145 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3146 which support adaptive clocking.
3148 @deffn {Command} adapter_khz max_speed_kHz
3149 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3150 JTAG interfaces usually support a limited number of
3151 speeds. The speed actually used won't be faster
3152 than the speed specified.
3154 Chip data sheets generally include a top JTAG clock rate.
3155 The actual rate is often a function of a CPU core clock,
3156 and is normally less than that peak rate.
3157 For example, most ARM cores accept at most one sixth of the CPU clock.
3159 Speed 0 (khz) selects RTCK method.
3160 @xref{faqrtck,,FAQ RTCK}.
3161 If your system uses RTCK, you won't need to change the
3162 JTAG clocking after setup.
3163 Not all interfaces, boards, or targets support ``rtck''.
3164 If the interface device can not
3165 support it, an error is returned when you try to use RTCK.
3166 @end deffn
3168 @defun jtag_rclk fallback_speed_kHz
3169 @cindex adaptive clocking
3170 @cindex RTCK
3171 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3172 If that fails (maybe the interface, board, or target doesn't
3173 support it), falls back to the specified frequency.
3174 @example
3175 # Fall back to 3mhz if RTCK is not supported
3176 jtag_rclk 3000
3177 @end example
3178 @end defun
3180 @node Reset Configuration
3181 @chapter Reset Configuration
3182 @cindex Reset Configuration
3184 Every system configuration may require a different reset
3185 configuration. This can also be quite confusing.
3186 Resets also interact with @var{reset-init} event handlers,
3187 which do things like setting up clocks and DRAM, and
3188 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3189 They can also interact with JTAG routers.
3190 Please see the various board files for examples.
3192 @quotation Note
3193 To maintainers and integrators:
3194 Reset configuration touches several things at once.
3195 Normally the board configuration file
3196 should define it and assume that the JTAG adapter supports
3197 everything that's wired up to the board's JTAG connector.
3199 However, the target configuration file could also make note
3200 of something the silicon vendor has done inside the chip,
3201 which will be true for most (or all) boards using that chip.
3202 And when the JTAG adapter doesn't support everything, the
3203 user configuration file will need to override parts of
3204 the reset configuration provided by other files.
3205 @end quotation
3207 @section Types of Reset
3209 There are many kinds of reset possible through JTAG, but
3210 they may not all work with a given board and adapter.
3211 That's part of why reset configuration can be error prone.
3213 @itemize @bullet
3214 @item
3215 @emph{System Reset} ... the @emph{SRST} hardware signal
3216 resets all chips connected to the JTAG adapter, such as processors,
3217 power management chips, and I/O controllers. Normally resets triggered
3218 with this signal behave exactly like pressing a RESET button.
3219 @item
3220 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3221 just the TAP controllers connected to the JTAG adapter.
3222 Such resets should not be visible to the rest of the system; resetting a
3223 device's TAP controller just puts that controller into a known state.
3224 @item
3225 @emph{Emulation Reset} ... many devices can be reset through JTAG
3226 commands. These resets are often distinguishable from system
3227 resets, either explicitly (a "reset reason" register says so)
3228 or implicitly (not all parts of the chip get reset).
3229 @item
3230 @emph{Other Resets} ... system-on-chip devices often support
3231 several other types of reset.
3232 You may need to arrange that a watchdog timer stops
3233 while debugging, preventing a watchdog reset.
3234 There may be individual module resets.
3235 @end itemize
3237 In the best case, OpenOCD can hold SRST, then reset
3238 the TAPs via TRST and send commands through JTAG to halt the
3239 CPU at the reset vector before the 1st instruction is executed.
3240 Then when it finally releases the SRST signal, the system is
3241 halted under debugger control before any code has executed.
3242 This is the behavior required to support the @command{reset halt}
3243 and @command{reset init} commands; after @command{reset init} a
3244 board-specific script might do things like setting up DRAM.
3245 (@xref{resetcommand,,Reset Command}.)
3247 @anchor{srstandtrstissues}
3248 @section SRST and TRST Issues
3250 Because SRST and TRST are hardware signals, they can have a
3251 variety of system-specific constraints. Some of the most
3252 common issues are:
3254 @itemize @bullet
3256 @item @emph{Signal not available} ... Some boards don't wire
3257 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3258 support such signals even if they are wired up.
3259 Use the @command{reset_config} @var{signals} options to say
3260 when either of those signals is not connected.
3261 When SRST is not available, your code might not be able to rely
3262 on controllers having been fully reset during code startup.
3263 Missing TRST is not a problem, since JTAG-level resets can
3264 be triggered using with TMS signaling.
3266 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3267 adapter will connect SRST to TRST, instead of keeping them separate.
3268 Use the @command{reset_config} @var{combination} options to say
3269 when those signals aren't properly independent.
3271 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3272 delay circuit, reset supervisor, or on-chip features can extend
3273 the effect of a JTAG adapter's reset for some time after the adapter
3274 stops issuing the reset. For example, there may be chip or board
3275 requirements that all reset pulses last for at least a
3276 certain amount of time; and reset buttons commonly have
3277 hardware debouncing.
3278 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3279 commands to say when extra delays are needed.
3281 @item @emph{Drive type} ... Reset lines often have a pullup
3282 resistor, letting the JTAG interface treat them as open-drain
3283 signals. But that's not a requirement, so the adapter may need
3284 to use push/pull output drivers.
3285 Also, with weak pullups it may be advisable to drive
3286 signals to both levels (push/pull) to minimize rise times.
3287 Use the @command{reset_config} @var{trst_type} and
3288 @var{srst_type} parameters to say how to drive reset signals.
3290 @item @emph{Special initialization} ... Targets sometimes need
3291 special JTAG initialization sequences to handle chip-specific
3292 issues (not limited to errata).
3293 For example, certain JTAG commands might need to be issued while
3294 the system as a whole is in a reset state (SRST active)
3295 but the JTAG scan chain is usable (TRST inactive).
3296 Many systems treat combined assertion of SRST and TRST as a
3297 trigger for a harder reset than SRST alone.
3298 Such custom reset handling is discussed later in this chapter.
3299 @end itemize
3301 There can also be other issues.
3302 Some devices don't fully conform to the JTAG specifications.
3303 Trivial system-specific differences are common, such as
3304 SRST and TRST using slightly different names.
3305 There are also vendors who distribute key JTAG documentation for
3306 their chips only to developers who have signed a Non-Disclosure
3307 Agreement (NDA).
3309 Sometimes there are chip-specific extensions like a requirement to use
3310 the normally-optional TRST signal (precluding use of JTAG adapters which
3311 don't pass TRST through), or needing extra steps to complete a TAP reset.
3313 In short, SRST and especially TRST handling may be very finicky,
3314 needing to cope with both architecture and board specific constraints.
3316 @section Commands for Handling Resets
3318 @deffn {Command} adapter_nsrst_assert_width milliseconds
3319 Minimum amount of time (in milliseconds) OpenOCD should wait
3320 after asserting nSRST (active-low system reset) before
3321 allowing it to be deasserted.
3322 @end deffn
3324 @deffn {Command} adapter_nsrst_delay milliseconds
3325 How long (in milliseconds) OpenOCD should wait after deasserting
3326 nSRST (active-low system reset) before starting new JTAG operations.
3327 When a board has a reset button connected to SRST line it will
3328 probably have hardware debouncing, implying you should use this.
3329 @end deffn
3331 @deffn {Command} jtag_ntrst_assert_width milliseconds
3332 Minimum amount of time (in milliseconds) OpenOCD should wait
3333 after asserting nTRST (active-low JTAG TAP reset) before
3334 allowing it to be deasserted.
3335 @end deffn
3337 @deffn {Command} jtag_ntrst_delay milliseconds
3338 How long (in milliseconds) OpenOCD should wait after deasserting
3339 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3340 @end deffn
3342 @deffn {Command} reset_config mode_flag ...
3343 This command displays or modifies the reset configuration
3344 of your combination of JTAG board and target in target
3345 configuration scripts.
3347 Information earlier in this section describes the kind of problems
3348 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3349 As a rule this command belongs only in board config files,
3350 describing issues like @emph{board doesn't connect TRST};
3351 or in user config files, addressing limitations derived
3352 from a particular combination of interface and board.
3353 (An unlikely example would be using a TRST-only adapter
3354 with a board that only wires up SRST.)
3356 The @var{mode_flag} options can be specified in any order, but only one
3357 of each type -- @var{signals}, @var{combination}, @var{gates},
3358 @var{trst_type}, @var{srst_type} and @var{connect_type}
3359 -- may be specified at a time.
3360 If you don't provide a new value for a given type, its previous
3361 value (perhaps the default) is unchanged.
3362 For example, this means that you don't need to say anything at all about
3363 TRST just to declare that if the JTAG adapter should want to drive SRST,
3364 it must explicitly be driven high (@option{srst_push_pull}).
3366 @itemize
3367 @item
3368 @var{signals} can specify which of the reset signals are connected.
3369 For example, If the JTAG interface provides SRST, but the board doesn't
3370 connect that signal properly, then OpenOCD can't use it.
3371 Possible values are @option{none} (the default), @option{trst_only},
3372 @option{srst_only} and @option{trst_and_srst}.
3374 @quotation Tip
3375 If your board provides SRST and/or TRST through the JTAG connector,
3376 you must declare that so those signals can be used.
3377 @end quotation
3379 @item
3380 The @var{combination} is an optional value specifying broken reset
3381 signal implementations.
3382 The default behaviour if no option given is @option{separate},
3383 indicating everything behaves normally.
3384 @option{srst_pulls_trst} states that the
3385 test logic is reset together with the reset of the system (e.g. NXP
3386 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3387 the system is reset together with the test logic (only hypothetical, I
3388 haven't seen hardware with such a bug, and can be worked around).
3389 @option{combined} implies both @option{srst_pulls_trst} and
3390 @option{trst_pulls_srst}.
3392 @item
3393 The @var{gates} tokens control flags that describe some cases where
3394 JTAG may be unvailable during reset.
3395 @option{srst_gates_jtag} (default)
3396 indicates that asserting SRST gates the
3397 JTAG clock. This means that no communication can happen on JTAG
3398 while SRST is asserted.
3399 Its converse is @option{srst_nogate}, indicating that JTAG commands
3400 can safely be issued while SRST is active.
3402 @item
3403 The @var{connect_type} tokens control flags that describe some cases where
3404 SRST is asserted while connecting to the target. @option{srst_nogate}
3405 is required to use this option.
3406 @option{connect_deassert_srst} (default)
3407 indicates that SRST will not be asserted while connecting to the target.
3408 Its converse is @option{connect_assert_srst}, indicating that SRST will
3409 be asserted before any target connection.
3410 Only some targets support this feature, STM32 and STR9 are examples.
3411 This feature is useful if you are unable to connect to your target due
3412 to incorrect options byte config or illegal program execution.
3413 @end itemize
3415 The optional @var{trst_type} and @var{srst_type} parameters allow the
3416 driver mode of each reset line to be specified. These values only affect
3417 JTAG interfaces with support for different driver modes, like the Amontec
3418 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3419 relevant signal (TRST or SRST) is not connected.
3421 @itemize
3422 @item
3423 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3424 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3425 Most boards connect this signal to a pulldown, so the JTAG TAPs
3426 never leave reset unless they are hooked up to a JTAG adapter.
3428 @item
3429 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3430 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3431 Most boards connect this signal to a pullup, and allow the
3432 signal to be pulled low by various events including system
3433 powerup and pressing a reset button.
3434 @end itemize
3435 @end deffn
3437 @section Custom Reset Handling
3438 @cindex events
3440 OpenOCD has several ways to help support the various reset
3441 mechanisms provided by chip and board vendors.
3442 The commands shown in the previous section give standard parameters.
3443 There are also @emph{event handlers} associated with TAPs or Targets.
3444 Those handlers are Tcl procedures you can provide, which are invoked
3445 at particular points in the reset sequence.
3447 @emph{When SRST is not an option} you must set
3448 up a @code{reset-assert} event handler for your target.
3449 For example, some JTAG adapters don't include the SRST signal;
3450 and some boards have multiple targets, and you won't always
3451 want to reset everything at once.
3453 After configuring those mechanisms, you might still
3454 find your board doesn't start up or reset correctly.
3455 For example, maybe it needs a slightly different sequence
3456 of SRST and/or TRST manipulations, because of quirks that
3457 the @command{reset_config} mechanism doesn't address;
3458 or asserting both might trigger a stronger reset, which
3459 needs special attention.
3461 Experiment with lower level operations, such as @command{jtag_reset}
3462 and the @command{jtag arp_*} operations shown here,
3463 to find a sequence of operations that works.
3464 @xref{JTAG Commands}.
3465 When you find a working sequence, it can be used to override
3466 @command{jtag_init}, which fires during OpenOCD startup
3467 (@pxref{configurationstage,,Configuration Stage});
3468 or @command{init_reset}, which fires during reset processing.
3470 You might also want to provide some project-specific reset
3471 schemes. For example, on a multi-target board the standard
3472 @command{reset} command would reset all targets, but you
3473 may need the ability to reset only one target at time and
3474 thus want to avoid using the board-wide SRST signal.
3476 @deffn {Overridable Procedure} init_reset mode
3477 This is invoked near the beginning of the @command{reset} command,
3478 usually to provide as much of a cold (power-up) reset as practical.
3479 By default it is also invoked from @command{jtag_init} if
3480 the scan chain does not respond to pure JTAG operations.
3481 The @var{mode} parameter is the parameter given to the
3482 low level reset command (@option{halt},
3483 @option{init}, or @option{run}), @option{setup},
3484 or potentially some other value.
3486 The default implementation just invokes @command{jtag arp_init-reset}.
3487 Replacements will normally build on low level JTAG
3488 operations such as @command{jtag_reset}.
3489 Operations here must not address individual TAPs
3490 (or their associated targets)
3491 until the JTAG scan chain has first been verified to work.
3493 Implementations must have verified the JTAG scan chain before
3494 they return.
3495 This is done by calling @command{jtag arp_init}
3496 (or @command{jtag arp_init-reset}).
3497 @end deffn
3499 @deffn Command {jtag arp_init}
3500 This validates the scan chain using just the four
3501 standard JTAG signals (TMS, TCK, TDI, TDO).
3502 It starts by issuing a JTAG-only reset.
3503 Then it performs checks to verify that the scan chain configuration
3504 matches the TAPs it can observe.
3505 Those checks include checking IDCODE values for each active TAP,
3506 and verifying the length of their instruction registers using
3507 TAP @code{-ircapture} and @code{-irmask} values.
3508 If these tests all pass, TAP @code{setup} events are
3509 issued to all TAPs with handlers for that event.
3510 @end deffn
3512 @deffn Command {jtag arp_init-reset}
3513 This uses TRST and SRST to try resetting
3514 everything on the JTAG scan chain
3515 (and anything else connected to SRST).
3516 It then invokes the logic of @command{jtag arp_init}.
3517 @end deffn
3520 @node TAP Declaration
3521 @chapter TAP Declaration
3522 @cindex TAP declaration
3523 @cindex TAP configuration
3525 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3526 TAPs serve many roles, including:
3528 @itemize @bullet
3529 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
3530 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
3531 Others do it indirectly, making a CPU do it.
3532 @item @b{Program Download} Using the same CPU support GDB uses,
3533 you can initialize a DRAM controller, download code to DRAM, and then
3534 start running that code.
3535 @item @b{Boundary Scan} Most chips support boundary scan, which
3536 helps test for board assembly problems like solder bridges
3537 and missing connections
3538 @end itemize
3540 OpenOCD must know about the active TAPs on your board(s).
3541 Setting up the TAPs is the core task of your configuration files.
3542 Once those TAPs are set up, you can pass their names to code
3543 which sets up CPUs and exports them as GDB targets,
3544 probes flash memory, performs low-level JTAG operations, and more.
3546 @section Scan Chains
3547 @cindex scan chain
3549 TAPs are part of a hardware @dfn{scan chain},
3550 which is daisy chain of TAPs.
3551 They also need to be added to
3552 OpenOCD's software mirror of that hardware list,
3553 giving each member a name and associating other data with it.
3554 Simple scan chains, with a single TAP, are common in
3555 systems with a single microcontroller or microprocessor.
3556 More complex chips may have several TAPs internally.
3557 Very complex scan chains might have a dozen or more TAPs:
3558 several in one chip, more in the next, and connecting
3559 to other boards with their own chips and TAPs.
3561 You can display the list with the @command{scan_chain} command.
3562 (Don't confuse this with the list displayed by the @command{targets}
3563 command, presented in the next chapter.
3564 That only displays TAPs for CPUs which are configured as
3565 debugging targets.)
3566 Here's what the scan chain might look like for a chip more than one TAP:
3568 @verbatim
3569 TapName Enabled IdCode Expected IrLen IrCap IrMask
3570 -- ------------------ ------- ---------- ---------- ----- ----- ------
3571 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3572 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3573 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3574 @end verbatim
3576 OpenOCD can detect some of that information, but not all
3577 of it. @xref{autoprobing,,Autoprobing}.
3578 Unfortunately those TAPs can't always be autoconfigured,
3579 because not all devices provide good support for that.
3580 JTAG doesn't require supporting IDCODE instructions, and
3581 chips with JTAG routers may not link TAPs into the chain
3582 until they are told to do so.
3584 The configuration mechanism currently supported by OpenOCD
3585 requires explicit configuration of all TAP devices using
3586 @command{jtag newtap} commands, as detailed later in this chapter.
3587 A command like this would declare one tap and name it @code{chip1.cpu}:
3589 @example
3590 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3591 @end example
3593 Each target configuration file lists the TAPs provided
3594 by a given chip.
3595 Board configuration files combine all the targets on a board,
3596 and so forth.
3597 Note that @emph{the order in which TAPs are declared is very important.}
3598 It must match the order in the JTAG scan chain, both inside
3599 a single chip and between them.
3600 @xref{faqtaporder,,FAQ TAP Order}.
3602 For example, the ST Microsystems STR912 chip has
3603 three separate TAPs@footnote{See the ST
3604 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3605 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3606 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3607 To configure those taps, @file{target/str912.cfg}
3608 includes commands something like this:
3610 @example
3611 jtag newtap str912 flash ... params ...
3612 jtag newtap str912 cpu ... params ...
3613 jtag newtap str912 bs ... params ...
3614 @end example
3616 Actual config files use a variable instead of literals like
3617 @option{str912}, to support more than one chip of each type.
3618 @xref{Config File Guidelines}.
3620 @deffn Command {jtag names}
3621 Returns the names of all current TAPs in the scan chain.
3622 Use @command{jtag cget} or @command{jtag tapisenabled}
3623 to examine attributes and state of each TAP.
3624 @example
3625 foreach t [jtag names] @{
3626 puts [format "TAP: %s\n" $t]
3627 @}
3628 @end example
3629 @end deffn
3631 @deffn Command {scan_chain}
3632 Displays the TAPs in the scan chain configuration,
3633 and their status.
3634 The set of TAPs listed by this command is fixed by
3635 exiting the OpenOCD configuration stage,
3636 but systems with a JTAG router can
3637 enable or disable TAPs dynamically.
3638 @end deffn
3640 @c FIXME! "jtag cget" should be able to return all TAP
3641 @c attributes, like "$target_name cget" does for targets.
3643 @c Probably want "jtag eventlist", and a "tap-reset" event
3644 @c (on entry to RESET state).
3646 @section TAP Names
3647 @cindex dotted name
3649 When TAP objects are declared with @command{jtag newtap},
3650 a @dfn{dotted.name} is created for the TAP, combining the
3651 name of a module (usually a chip) and a label for the TAP.
3652 For example: @code{xilinx.tap}, @code{str912.flash},
3653 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3654 Many other commands use that dotted.name to manipulate or
3655 refer to the TAP. For example, CPU configuration uses the
3656 name, as does declaration of NAND or NOR flash banks.
3658 The components of a dotted name should follow ``C'' symbol
3659 name rules: start with an alphabetic character, then numbers
3660 and underscores are OK; while others (including dots!) are not.
3662 @quotation Tip
3663 In older code, JTAG TAPs were numbered from 0..N.
3664 This feature is still present.
3665 However its use is highly discouraged, and
3666 should not be relied on; it will be removed by mid-2010.
3667 Update all of your scripts to use TAP names rather than numbers,
3668 by paying attention to the runtime warnings they trigger.
3669 Using TAP numbers in target configuration scripts prevents
3670 reusing those scripts on boards with multiple targets.
3671 @end quotation
3673 @section TAP Declaration Commands
3675 @c shouldn't this be(come) a {Config Command}?
3676 @deffn Command {jtag newtap} chipname tapname configparams...
3677 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3678 and configured according to the various @var{configparams}.
3680 The @var{chipname} is a symbolic name for the chip.
3681 Conventionally target config files use @code{$_CHIPNAME},
3682 defaulting to the model name given by the chip vendor but
3683 overridable.
3685 @cindex TAP naming convention
3686 The @var{tapname} reflects the role of that TAP,
3687 and should follow this convention:
3689 @itemize @bullet
3690 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3691 @item @code{cpu} -- The main CPU of the chip, alternatively
3692 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3693 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3694 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3695 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3696 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3697 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3698 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3699 with a single TAP;
3700 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3701 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3702 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3703 a JTAG TAP; that TAP should be named @code{sdma}.
3704 @end itemize
3706 Every TAP requires at least the following @var{configparams}:
3708 @itemize @bullet
3709 @item @code{-irlen} @var{NUMBER}
3710 @*The length in bits of the
3711 instruction register, such as 4 or 5 bits.
3712 @end itemize
3714 A TAP may also provide optional @var{configparams}:
3716 @itemize @bullet
3717 @item @code{-disable} (or @code{-enable})
3718 @*Use the @code{-disable} parameter to flag a TAP which is not
3719 linked in to the scan chain after a reset using either TRST
3720 or the JTAG state machine's @sc{reset} state.
3721 You may use @code{-enable} to highlight the default state
3722 (the TAP is linked in).
3723 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3724 @item @code{-expected-id} @var{number}
3725 @*A non-zero @var{number} represents a 32-bit IDCODE
3726 which you expect to find when the scan chain is examined.
3727 These codes are not required by all JTAG devices.
3728 @emph{Repeat the option} as many times as required if more than one
3729 ID code could appear (for example, multiple versions).
3730 Specify @var{number} as zero to suppress warnings about IDCODE
3731 values that were found but not included in the list.
3733 Provide this value if at all possible, since it lets OpenOCD
3734 tell when the scan chain it sees isn't right. These values
3735 are provided in vendors' chip documentation, usually a technical
3736 reference manual. Sometimes you may need to probe the JTAG
3737 hardware to find these values.
3738 @xref{autoprobing,,Autoprobing}.
3739 @item @code{-ignore-version}
3740 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3741 option. When vendors put out multiple versions of a chip, or use the same
3742 JTAG-level ID for several largely-compatible chips, it may be more practical
3743 to ignore the version field than to update config files to handle all of
3744 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3745 @item @code{-ircapture} @var{NUMBER}
3746 @*The bit pattern loaded by the TAP into the JTAG shift register
3747 on entry to the @sc{ircapture} state, such as 0x01.
3748 JTAG requires the two LSBs of this value to be 01.
3749 By default, @code{-ircapture} and @code{-irmask} are set
3750 up to verify that two-bit value. You may provide
3751 additional bits, if you know them, or indicate that
3752 a TAP doesn't conform to the JTAG specification.
3753 @item @code{-irmask} @var{NUMBER}
3754 @*A mask used with @code{-ircapture}
3755 to verify that instruction scans work correctly.
3756 Such scans are not used by OpenOCD except to verify that
3757 there seems to be no problems with JTAG scan chain operations.
3758 @end itemize
3759 @end deffn
3761 @section Other TAP commands
3763 @deffn Command {jtag cget} dotted.name @option{-event} name
3764 @deffnx Command {jtag configure} dotted.name @option{-event} name string
3765 At this writing this TAP attribute
3766 mechanism is used only for event handling.
3767 (It is not a direct analogue of the @code{cget}/@code{configure}
3768 mechanism for debugger targets.)
3769 See the next section for information about the available events.
3771 The @code{configure} subcommand assigns an event handler,
3772 a TCL string which is evaluated when the event is triggered.
3773 The @code{cget} subcommand returns that handler.
3774 @end deffn
3776 @section TAP Events
3777 @cindex events
3778 @cindex TAP events
3780 OpenOCD includes two event mechanisms.
3781 The one presented here applies to all JTAG TAPs.
3782 The other applies to debugger targets,
3783 which are associated with certain TAPs.
3785 The TAP events currently defined are:
3787 @itemize @bullet
3788 @item @b{post-reset}
3789 @* The TAP has just completed a JTAG reset.
3790 The tap may still be in the JTAG @sc{reset} state.
3791 Handlers for these events might perform initialization sequences
3792 such as issuing TCK cycles, TMS sequences to ensure
3793 exit from the ARM SWD mode, and more.
3795 Because the scan chain has not yet been verified, handlers for these events
3796 @emph{should not issue commands which scan the JTAG IR or DR registers}
3797 of any particular target.
3798 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3799 @item @b{setup}
3800 @* The scan chain has been reset and verified.
3801 This handler may enable TAPs as needed.
3802 @item @b{tap-disable}
3803 @* The TAP needs to be disabled. This handler should
3804 implement @command{jtag tapdisable}
3805 by issuing the relevant JTAG commands.
3806 @item @b{tap-enable}
3807 @* The TAP needs to be enabled. This handler should
3808 implement @command{jtag tapenable}
3809 by issuing the relevant JTAG commands.
3810 @end itemize
3812 If you need some action after each JTAG reset, which isn't actually
3813 specific to any TAP (since you can't yet trust the scan chain's
3814 contents to be accurate), you might:
3816 @example
3817 jtag configure CHIP.jrc -event post-reset @{
3818 echo "JTAG Reset done"
3819 ... non-scan jtag operations to be done after reset
3820 @}
3821 @end example
3824 @anchor{enablinganddisablingtaps}
3825 @section Enabling and Disabling TAPs
3826 @cindex JTAG Route Controller
3827 @cindex jrc
3829 In some systems, a @dfn{JTAG Route Controller} (JRC)
3830 is used to enable and/or disable specific JTAG TAPs.
3831 Many ARM based chips from Texas Instruments include
3832 an ``ICEpick'' module, which is a JRC.
3833 Such chips include DaVinci and OMAP3 processors.
3835 A given TAP may not be visible until the JRC has been
3836 told to link it into the scan chain; and if the JRC
3837 has been told to unlink that TAP, it will no longer
3838 be visible.
3839 Such routers address problems that JTAG ``bypass mode''
3840 ignores, such as:
3842 @itemize
3843 @item The scan chain can only go as fast as its slowest TAP.
3844 @item Having many TAPs slows instruction scans, since all
3845 TAPs receive new instructions.
3846 @item TAPs in the scan chain must be powered up, which wastes
3847 power and prevents debugging some power management mechanisms.
3848 @end itemize
3850 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3851 as implied by the existence of JTAG routers.
3852 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3853 does include a kind of JTAG router functionality.
3855 @c (a) currently the event handlers don't seem to be able to
3856 @c fail in a way that could lead to no-change-of-state.
3858 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3859 shown below, and is implemented using TAP event handlers.
3860 So for example, when defining a TAP for a CPU connected to
3861 a JTAG router, your @file{target.cfg} file
3862 should define TAP event handlers using
3863 code that looks something like this:
3865 @example
3866 jtag configure CHIP.cpu -event tap-enable @{
3867 ... jtag operations using CHIP.jrc
3868 @}
3869 jtag configure CHIP.cpu -event tap-disable @{
3870 ... jtag operations using CHIP.jrc
3871 @}
3872 @end example
3874 Then you might want that CPU's TAP enabled almost all the time:
3876 @example
3877 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3878 @end example
3880 Note how that particular setup event handler declaration
3881 uses quotes to evaluate @code{$CHIP} when the event is configured.
3882 Using brackets @{ @} would cause it to be evaluated later,
3883 at runtime, when it might have a different value.
3885 @deffn Command {jtag tapdisable} dotted.name
3886 If necessary, disables the tap
3887 by sending it a @option{tap-disable} event.
3888 Returns the string "1" if the tap
3889 specified by @var{dotted.name} is enabled,
3890 and "0" if it is disabled.
3891 @end deffn
3893 @deffn Command {jtag tapenable} dotted.name
3894 If necessary, enables the tap
3895 by sending it a @option{tap-enable} event.
3896 Returns the string "1" if the tap
3897 specified by @var{dotted.name} is enabled,
3898 and "0" if it is disabled.
3899 @end deffn
3901 @deffn Command {jtag tapisenabled} dotted.name
3902 Returns the string "1" if the tap
3903 specified by @var{dotted.name} is enabled,
3904 and "0" if it is disabled.
3906 @quotation Note
3907 Humans will find the @command{scan_chain} command more helpful
3908 for querying the state of the JTAG taps.
3909 @end quotation
3910 @end deffn
3912 @anchor{autoprobing}
3913 @section Autoprobing
3914 @cindex autoprobe
3915 @cindex JTAG autoprobe
3917 TAP configuration is the first thing that needs to be done
3918 after interface and reset configuration. Sometimes it's
3919 hard finding out what TAPs exist, or how they are identified.
3920 Vendor documentation is not always easy to find and use.
3922 To help you get past such problems, OpenOCD has a limited
3923 @emph{autoprobing} ability to look at the scan chain, doing
3924 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3925 To use this mechanism, start the OpenOCD server with only data
3926 that configures your JTAG interface, and arranges to come up
3927 with a slow clock (many devices don't support fast JTAG clocks
3928 right when they come out of reset).
3930 For example, your @file{openocd.cfg} file might have:
3932 @example
3933 source [find interface/olimex-arm-usb-tiny-h.cfg]
3934 reset_config trst_and_srst
3935 jtag_rclk 8
3936 @end example
3938 When you start the server without any TAPs configured, it will
3939 attempt to autoconfigure the TAPs. There are two parts to this:
3941 @enumerate
3942 @item @emph{TAP discovery} ...
3943 After a JTAG reset (sometimes a system reset may be needed too),
3944 each TAP's data registers will hold the contents of either the
3945 IDCODE or BYPASS register.
3946 If JTAG communication is working, OpenOCD will see each TAP,
3947 and report what @option{-expected-id} to use with it.
3948 @item @emph{IR Length discovery} ...
3949 Unfortunately JTAG does not provide a reliable way to find out
3950 the value of the @option{-irlen} parameter to use with a TAP
3951 that is discovered.
3952 If OpenOCD can discover the length of a TAP's instruction
3953 register, it will report it.
3954 Otherwise you may need to consult vendor documentation, such
3955 as chip data sheets or BSDL files.
3956 @end enumerate
3958 In many cases your board will have a simple scan chain with just
3959 a single device. Here's what OpenOCD reported with one board
3960 that's a bit more complex:
3962 @example
3963 clock speed 8 kHz
3964 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3965 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3966 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3967 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3968 AUTO auto0.tap - use "... -irlen 4"
3969 AUTO auto1.tap - use "... -irlen 4"
3970 AUTO auto2.tap - use "... -irlen 6"
3971 no gdb ports allocated as no target has been specified
3972 @end example
3974 Given that information, you should be able to either find some existing
3975 config files to use, or create your own. If you create your own, you
3976 would configure from the bottom up: first a @file{target.cfg} file
3977 with these TAPs, any targets associated with them, and any on-chip
3978 resources; then a @file{board.cfg} with off-chip resources, clocking,
3979 and so forth.
3981 @node CPU Configuration
3982 @chapter CPU Configuration
3983 @cindex GDB target
3985 This chapter discusses how to set up GDB debug targets for CPUs.
3986 You can also access these targets without GDB
3987 (@pxref{Architecture and Core Commands},
3988 and @ref{targetstatehandling,,Target State handling}) and
3989 through various kinds of NAND and NOR flash commands.
3990 If you have multiple CPUs you can have multiple such targets.
3992 We'll start by looking at how to examine the targets you have,
3993 then look at how to add one more target and how to configure it.
3995 @section Target List
3996 @cindex target, current
3997 @cindex target, list
3999 All targets that have been set up are part of a list,
4000 where each member has a name.
4001 That name should normally be the same as the TAP name.
4002 You can display the list with the @command{targets}
4003 (plural!) command.
4004 This display often has only one CPU; here's what it might
4005 look like with more than one:
4006 @verbatim
4007 TargetName Type Endian TapName State
4008 -- ------------------ ---------- ------ ------------------ ------------
4009 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4010 1 MyTarget cortex_m little mychip.foo tap-disabled
4011 @end verbatim
4013 One member of that list is the @dfn{current target}, which
4014 is implicitly referenced by many commands.
4015 It's the one marked with a @code{*} near the target name.
4016 In particular, memory addresses often refer to the address
4017 space seen by that current target.
4018 Commands like @command{mdw} (memory display words)
4019 and @command{flash erase_address} (erase NOR flash blocks)
4020 are examples; and there are many more.
4022 Several commands let you examine the list of targets:
4024 @deffn Command {target count}
4025 @emph{Note: target numbers are deprecated; don't use them.
4026 They will be removed shortly after August 2010, including this command.
4027 Iterate target using @command{target names}, not by counting.}
4029 Returns the number of targets, @math{N}.
4030 The highest numbered target is @math{N - 1}.
4031 @example
4032 set c [target count]
4033 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
4034 # Assuming you have created this function
4035 print_target_details $x
4036 @}
4037 @end example
4038 @end deffn
4040 @deffn Command {target current}
4041 Returns the name of the current target.
4042 @end deffn
4044 @deffn Command {target names}
4045 Lists the names of all current targets in the list.
4046 @example
4047 foreach t [target names] @{
4048 puts [format "Target: %s\n" $t]
4049 @}
4050 @end example
4051 @end deffn
4053 @deffn Command {target number} number
4054 @emph{Note: target numbers are deprecated; don't use them.
4055 They will be removed shortly after August 2010, including this command.}
4057 The list of targets is numbered starting at zero.
4058 This command returns the name of the target at index @var{number}.
4059 @example
4060 set thename [target number $x]
4061 puts [format "Target %d is: %s\n" $x $thename]
4062 @end example
4063 @end deffn
4065 @c yep, "target list" would have been better.
4066 @c plus maybe "target setdefault".
4068 @deffn Command targets [name]
4069 @emph{Note: the name of this command is plural. Other target
4070 command names are singular.}
4072 With no parameter, this command displays a table of all known
4073 targets in a user friendly form.
4075 With a parameter, this command sets the current target to
4076 the given target with the given @var{name}; this is
4077 only relevant on boards which have more than one target.
4078 @end deffn
4080 @section Target CPU Types and Variants
4081 @cindex target type
4082 @cindex CPU type
4083 @cindex CPU variant
4085 Each target has a @dfn{CPU type}, as shown in the output of
4086 the @command{targets} command. You need to specify that type
4087 when calling @command{target create}.
4088 The CPU type indicates more than just the instruction set.
4089 It also indicates how that instruction set is implemented,
4090 what kind of debug support it integrates,
4091 whether it has an MMU (and if so, what kind),
4092 what core-specific commands may be available
4093 (@pxref{Architecture and Core Commands}),
4094 and more.
4096 For some CPU types, OpenOCD also defines @dfn{variants} which
4097 indicate differences that affect their handling.
4098 For example, a particular implementation bug might need to be
4099 worked around in some chip versions.
4101 It's easy to see what target types are supported,
4102 since there's a command to list them.
4103 However, there is currently no way to list what target variants
4104 are supported (other than by reading the OpenOCD source code).
4106 @anchor{targettypes}
4107 @deffn Command {target types}
4108 Lists all supported target types.
4109 At this writing, the supported CPU types and variants are:
4111 @itemize @bullet
4112 @item @code{arm11} -- this is a generation of ARMv6 cores
4113 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4114 @item @code{arm7tdmi} -- this is an ARMv4 core
4115 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4116 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4117 @item @code{arm966e} -- this is an ARMv5 core
4118 @item @code{arm9tdmi} -- this is an ARMv4 core
4119 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4120 (Support for this is preliminary and incomplete.)
4121 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4122 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4123 compact Thumb2 instruction set.
4124 @item @code{dragonite} -- resembles arm966e
4125 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4126 (Support for this is still incomplete.)
4127 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4128 @item @code{feroceon} -- resembles arm926
4129 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
4130 @item @code{xscale} -- this is actually an architecture,
4131 not a CPU type. It is based on the ARMv5 architecture.
4132 There are several variants defined:
4133 @itemize @minus
4134 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
4135 @code{pxa27x} ... instruction register length is 7 bits
4136 @item @code{pxa250}, @code{pxa255},
4137 @code{pxa26x} ... instruction register length is 5 bits
4138 @item @code{pxa3xx} ... instruction register length is 11 bits
4139 @end itemize
4140 @end itemize
4141 @end deffn
4143 To avoid being confused by the variety of ARM based cores, remember
4144 this key point: @emph{ARM is a technology licencing company}.
4145 (See: @url{http://www.arm.com}.)
4146 The CPU name used by OpenOCD will reflect the CPU design that was
4147 licenced, not a vendor brand which incorporates that design.
4148 Name prefixes like arm7, arm9, arm11, and cortex
4149 reflect design generations;
4150 while names like ARMv4, ARMv5, ARMv6, and ARMv7
4151 reflect an architecture version implemented by a CPU design.
4153 @anchor{targetconfiguration}
4154 @section Target Configuration
4156 Before creating a ``target'', you must have added its TAP to the scan chain.
4157 When you've added that TAP, you will have a @code{dotted.name}
4158 which is used to set up the CPU support.
4159 The chip-specific configuration file will normally configure its CPU(s)
4160 right after it adds all of the chip's TAPs to the scan chain.
4162 Although you can set up a target in one step, it's often clearer if you
4163 use shorter commands and do it in two steps: create it, then configure
4164 optional parts.
4165 All operations on the target after it's created will use a new
4166 command, created as part of target creation.
4168 The two main things to configure after target creation are
4169 a work area, which usually has target-specific defaults even
4170 if the board setup code overrides them later;
4171 and event handlers (@pxref{targetevents,,Target Events}), which tend
4172 to be much more board-specific.
4173 The key steps you use might look something like this
4175 @example
4176 target create MyTarget cortex_m -chain-position mychip.cpu
4177 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096