[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * NAND Flash Commands:: NAND Flash Commands
77 * PLD/FPGA Commands:: PLD/FPGA Commands
78 * General Commands:: General Commands
79 * Architecture and Core Commands:: Architecture and Core Commands
80 * JTAG Commands:: JTAG Commands
81 * Boundary Scan Commands:: Boundary Scan Commands
82 * TFTP:: TFTP
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
95 @end menu
97 @node About
98 @unnumbered About
99 @cindex about
101 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
102 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
105 around the world.
107 @section What is OpenOCD?
108 @cindex TAP
109 @cindex JTAG
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
113 devices.
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board can be directly connected to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
140 scan operations.
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD only supports
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
154 based, parallel port based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
159 Cortex-M3 (Stellaris LM3, ST STM32 and Energy Micro EFM32) based cores to be
160 debugged via the GDB protocol.
162 @b{Flash Programing:} Flash writing is supported for external CFI
163 compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3,
165 STM32x and EFM32). Preliminary support for various NAND flash controllers
166 (LPC3180, Orion, S3C24xx, more) controller is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{http://openocd.sourceforge.net/}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{http://openocd.sourceforge.net/doc/html/index.html}
182 PDF form is likewise published at:
184 @uref{http://openocd.sourceforge.net/doc/pdf/openocd.pdf}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
203 @section OpenOCD IRC
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
208 @node Developers
209 @chapter OpenOCD Developer Resources
210 @cindex developers
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD GIT Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a GIT repository hosted at SourceForge. The repository URL is:
225 @uref{git://openocd.git.sourceforge.net/gitroot/openocd/openocd}
227 You may prefer to use a mirror and the HTTP protocol:
229 @uref{http://repo.or.cz/r/openocd.git}
231 With standard GIT tools, use @command{git clone} to initialize
232 a local repository, and @command{git pull} to update it.
233 There are also gitweb pages letting you browse the repository
234 with a web browser, or download arbitrary snapshots without
235 needing a GIT client:
237 @uref{http://openocd.git.sourceforge.net/git/gitweb.cgi?p=openocd/openocd}
239 @uref{http://repo.or.cz/w/openocd.git}
241 The @file{README} file contains the instructions for building the project
242 from the repository or a snapshot.
244 Developers that want to contribute patches to the OpenOCD system are
245 @b{strongly} encouraged to work against mainline.
246 Patches created against older versions may require additional
247 work from their submitter in order to be updated for newer releases.
249 @section Doxygen Developer Manual
251 During the 0.2.x release cycle, the OpenOCD project began
252 providing a Doxygen reference manual. This document contains more
253 technical information about the software internals, development
254 processes, and similar documentation:
256 @uref{http://openocd.sourceforge.net/doc/doxygen/html/index.html}
258 This document is a work-in-progress, but contributions would be welcome
259 to fill in the gaps. All of the source files are provided in-tree,
260 listed in the Doxyfile configuration in the top of the source tree.
262 @section OpenOCD Developer Mailing List
264 The OpenOCD Developer Mailing List provides the primary means of
265 communication between developers:
267 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
269 Discuss and submit patches to this list.
270 The @file{HACKING} file contains basic information about how
271 to prepare patches.
273 @section OpenOCD Bug Database
275 During the 0.4.x release cycle the OpenOCD project team began
276 using Trac for its bug database:
278 @uref{https://sourceforge.net/apps/trac/openocd}
281 @node Debug Adapter Hardware
282 @chapter Debug Adapter Hardware
283 @cindex dongles
284 @cindex FTDI
285 @cindex wiggler
286 @cindex zy1000
287 @cindex printer port
288 @cindex USB Adapter
289 @cindex RTCK
291 Defined: @b{dongle}: A small device that plugins into a computer and serves as
292 an adapter .... [snip]
294 In the OpenOCD case, this generally refers to @b{a small adapter} that
295 attaches to your computer via USB or the Parallel Printer Port. One
296 exception is the Zylin ZY1000, packaged as a small box you attach via
297 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
298 require any drivers to be installed on the developer PC. It also has
299 a built in web interface. It supports RTCK/RCLK or adaptive clocking
300 and has a built in relay to power cycle targets remotely.
303 @section Choosing a Dongle
305 There are several things you should keep in mind when choosing a dongle.
307 @enumerate
308 @item @b{Transport} Does it support the kind of communication that you need?
309 OpenOCD focusses mostly on JTAG. Your version may also support
310 other ways to communicate with target devices.
311 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
312 Does your dongle support it? You might need a level converter.
313 @item @b{Pinout} What pinout does your target board use?
314 Does your dongle support it? You may be able to use jumper
315 wires, or an "octopus" connector, to convert pinouts.
316 @item @b{Connection} Does your computer have the USB, printer, or
317 Ethernet port needed?
318 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
319 RTCK support? Also known as ``adaptive clocking''
320 @end enumerate
322 @section Stand alone Systems
324 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/33-zylin-zy1000-jtag-probe} Technically, not a
325 dongle, but a standalone box. The ZY1000 has the advantage that it does
326 not require any drivers installed on the developer PC. It also has
327 a built in web interface. It supports RTCK/RCLK or adaptive clocking
328 and has a built in relay to power cycle targets remotely.
330 @section USB FT2232 Based
332 There are many USB JTAG dongles on the market, many of them are based
333 on a chip from ``Future Technology Devices International'' (FTDI)
334 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
335 See: @url{http://www.ftdichip.com} for more information.
336 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
337 chips are starting to become available in JTAG adapters. (Adapters
338 using those high speed FT2232H chips may support adaptive clocking.)
340 The FT2232 chips are flexible enough to support some other
341 transport options, such as SWD or the SPI variants used to
342 program some chips. They have two communications channels,
343 and one can be used for a UART adapter at the same time the
344 other one is used to provide a debug adapter.
346 Also, some development boards integrate an FT2232 chip to serve as
347 a built-in low cost debug adapter and usb-to-serial solution.
349 @itemize @bullet
350 @item @b{usbjtag}
351 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
352 @item @b{jtagkey}
353 @* See: @url{http://www.amontec.com/jtagkey.shtml}
354 @item @b{jtagkey2}
355 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
356 @item @b{oocdlink}
357 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
358 @item @b{signalyzer}
359 @* See: @url{http://www.signalyzer.com}
360 @item @b{Stellaris Eval Boards}
361 @* See: @url{http://www.ti.com} - The Stellaris eval boards
362 bundle FT2232-based JTAG and SWD support, which can be used to debug
363 the Stellaris chips. Using separate JTAG adapters is optional.
364 These boards can also be used in a "pass through" mode as JTAG adapters
365 to other target boards, disabling the Stellaris chip.
366 @item @b{TI/Luminary ICDI}
367 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
368 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
369 Evaluation Kits. Like the non-detachable FT2232 support on the other
370 Stellaris eval boards, they can be used to debug other target boards.
371 @item @b{olimex-jtag}
372 @* See: @url{http://www.olimex.com}
373 @item @b{Flyswatter/Flyswatter2}
374 @* See: @url{http://www.tincantools.com}
375 @item @b{turtelizer2}
376 @* See:
377 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
378 @url{http://www.ethernut.de}
379 @item @b{comstick}
380 @* Link: @url{http://www.hitex.com/index.php?id=383}
381 @item @b{stm32stick}
382 @* Link @url{http://www.hitex.com/stm32-stick}
383 @item @b{axm0432_jtag}
384 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
385 to be available anymore as of April 2012.
386 @item @b{cortino}
387 @* Link @url{http://www.hitex.com/index.php?id=cortino}
388 @item @b{dlp-usb1232h}
389 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
390 @item @b{digilent-hs1}
391 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
392 @end itemize
394 @section USB-JTAG / Altera USB-Blaster compatibles
396 These devices also show up as FTDI devices, but are not
397 protocol-compatible with the FT2232 devices. They are, however,
398 protocol-compatible among themselves. USB-JTAG devices typically consist
399 of a FT245 followed by a CPLD that understands a particular protocol,
400 or emulate this protocol using some other hardware.
402 They may appear under different USB VID/PID depending on the particular
403 product. The driver can be configured to search for any VID/PID pair
404 (see the section on driver commands).
406 @itemize
407 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
408 @* Link: @url{http://ixo-jtag.sourceforge.net/}
409 @item @b{Altera USB-Blaster}
410 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
411 @end itemize
413 @section USB JLINK based
414 There are several OEM versions of the Segger @b{JLINK} adapter. It is
415 an example of a micro controller based JTAG adapter, it uses an
416 AT91SAM764 internally.
418 @itemize @bullet
419 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
420 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
421 @item @b{SEGGER JLINK}
422 @* Link: @url{http://www.segger.com/jlink.html}
423 @item @b{IAR J-Link}
424 @* Link: @url{http://www.iar.com/en/products/hardware-debug-probes/iar-j-link/}
425 @end itemize
427 @section USB RLINK based
428 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
430 @itemize @bullet
431 @item @b{Raisonance RLink}
432 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
433 @item @b{STM32 Primer}
434 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
435 @item @b{STM32 Primer2}
436 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
437 @end itemize
439 @section USB ST-LINK based
440 ST Micro has an adapter called @b{ST-LINK}.
441 They only work with ST Micro chips, notably STM32 and STM8.
443 @itemize @bullet
444 @item @b{ST-LINK}
445 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
446 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
447 @item @b{ST-LINK/V2}
448 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
449 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
450 @end itemize
452 For info the original ST-LINK enumerates using the mass storage usb class, however
453 it's implementation is completely broken. The result is this causes issues under linux.
454 The simplest solution is to get linux to ignore the ST-LINK using one of the following methods:
455 @itemize @bullet
456 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
457 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
458 @end itemize
460 @section USB TI/Stellaris ICDI based
461 Texas Instruments has an adapter called @b{ICDI}.
462 It is not to be confused with the FTDI based adapters that were originally fitted to their
463 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
465 @section USB Other
466 @itemize @bullet
467 @item @b{USBprog}
468 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
470 @item @b{USB - Presto}
471 @* Link: @url{http://tools.asix.net/prg_presto.htm}
473 @item @b{Versaloon-Link}
474 @* Link: @url{http://www.versaloon.com}
476 @item @b{ARM-JTAG-EW}
477 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
479 @item @b{Buspirate}
480 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
482 @item @b{opendous}
483 @* Link: @url{http://code.google.com/p/opendous-jtag/}
485 @item @b{estick}
486 @* Link: @url{http://code.google.com/p/estick-jtag/}
488 @item @b{Keil ULINK v1}
489 @* Link: @url{http://www.keil.com/ulink1/}
490 @end itemize
492 @section IBM PC Parallel Printer Port Based
494 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
495 and the Macraigor Wiggler. There are many clones and variations of
496 these on the market.
498 Note that parallel ports are becoming much less common, so if you
499 have the choice you should probably avoid these adapters in favor
500 of USB-based ones.
502 @itemize @bullet
504 @item @b{Wiggler} - There are many clones of this.
505 @* Link: @url{http://www.macraigor.com/wiggler.htm}
507 @item @b{DLC5} - From XILINX - There are many clones of this
508 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
509 produced, PDF schematics are easily found and it is easy to make.
511 @item @b{Amontec - JTAG Accelerator}
512 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
514 @item @b{GW16402}
515 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
517 @item @b{Wiggler2}
518 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
520 @item @b{Wiggler_ntrst_inverted}
521 @* Yet another variation - See the source code, src/jtag/parport.c
523 @item @b{old_amt_wiggler}
524 @* Unknown - probably not on the market today
526 @item @b{arm-jtag}
527 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
529 @item @b{chameleon}
530 @* Link: @url{http://www.amontec.com/chameleon.shtml}
532 @item @b{Triton}
533 @* Unknown.
535 @item @b{Lattice}
536 @* ispDownload from Lattice Semiconductor
537 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
539 @item @b{flashlink}
540 @* From ST Microsystems;
541 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
543 @end itemize
545 @section Other...
546 @itemize @bullet
548 @item @b{ep93xx}
549 @* An EP93xx based Linux machine using the GPIO pins directly.
551 @item @b{at91rm9200}
552 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
554 @end itemize
556 @node About Jim-Tcl
557 @chapter About Jim-Tcl
558 @cindex Jim-Tcl
559 @cindex tcl
561 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
562 This programming language provides a simple and extensible
563 command interpreter.
565 All commands presented in this Guide are extensions to Jim-Tcl.
566 You can use them as simple commands, without needing to learn
567 much of anything about Tcl.
568 Alternatively, can write Tcl programs with them.
570 You can learn more about Jim at its website, @url{http://jim.berlios.de}.
571 There is an active and responsive community, get on the mailing list
572 if you have any questions. Jim-Tcl maintainers also lurk on the
573 OpenOCD mailing list.
575 @itemize @bullet
576 @item @b{Jim vs. Tcl}
577 @* Jim-Tcl is a stripped down version of the well known Tcl language,
578 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
579 fewer features. Jim-Tcl is several dozens of .C files and .H files and
580 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
581 4.2 MB .zip file containing 1540 files.
583 @item @b{Missing Features}
584 @* Our practice has been: Add/clone the real Tcl feature if/when
585 needed. We welcome Jim-Tcl improvements, not bloat. Also there
586 are a large number of optional Jim-Tcl features that are not
587 enabled in OpenOCD.
589 @item @b{Scripts}
590 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
591 command interpreter today is a mixture of (newer)
592 Jim-Tcl commands, and (older) the orginal command interpreter.
594 @item @b{Commands}
595 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
596 can type a Tcl for() loop, set variables, etc.
597 Some of the commands documented in this guide are implemented
598 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
600 @item @b{Historical Note}
601 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
602 before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
603 as a git submodule, which greatly simplified upgrading Jim Tcl
604 to benefit from new features and bugfixes in Jim Tcl.
606 @item @b{Need a crash course in Tcl?}
607 @*@xref{Tcl Crash Course}.
608 @end itemize
610 @node Running
611 @chapter Running
612 @cindex command line options
613 @cindex logfile
614 @cindex directory search
616 Properly installing OpenOCD sets up your operating system to grant it access
617 to the debug adapters. On Linux, this usually involves installing a file
618 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
619 complex and confusing driver configuration for every peripheral. Such issues
620 are unique to each operating system, and are not detailed in this User's Guide.
622 Then later you will invoke the OpenOCD server, with various options to
623 tell it how each debug session should work.
624 The @option{--help} option shows:
625 @verbatim
626 bash$ openocd --help
628 --help | -h display this help
629 --version | -v display OpenOCD version
630 --file | -f use configuration file <name>
631 --search | -s dir to search for config files and scripts
632 --debug | -d set debug level <0-3>
633 --log_output | -l redirect log output to file <name>
634 --command | -c run <command>
635 @end verbatim
637 If you don't give any @option{-f} or @option{-c} options,
638 OpenOCD tries to read the configuration file @file{openocd.cfg}.
639 To specify one or more different
640 configuration files, use @option{-f} options. For example:
642 @example
643 openocd -f config1.cfg -f config2.cfg -f config3.cfg
644 @end example
646 Configuration files and scripts are searched for in
647 @enumerate
648 @item the current directory,
649 @item any search dir specified on the command line using the @option{-s} option,
650 @item any search dir specified using the @command{add_script_search_dir} command,
651 @item @file{$HOME/.openocd} (not on Windows),
652 @item the site wide script library @file{$pkgdatadir/site} and
653 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
654 @end enumerate
655 The first found file with a matching file name will be used.
657 @quotation Note
658 Don't try to use configuration script names or paths which
659 include the "#" character. That character begins Tcl comments.
660 @end quotation
662 @section Simple setup, no customization
664 In the best case, you can use two scripts from one of the script
665 libraries, hook up your JTAG adapter, and start the server ... and
666 your JTAG setup will just work "out of the box". Always try to
667 start by reusing those scripts, but assume you'll need more
668 customization even if this works. @xref{OpenOCD Project Setup}.
670 If you find a script for your JTAG adapter, and for your board or
671 target, you may be able to hook up your JTAG adapter then start
672 the server like:
674 @example
675 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
676 @end example
678 You might also need to configure which reset signals are present,
679 using @option{-c 'reset_config trst_and_srst'} or something similar.
680 If all goes well you'll see output something like
682 @example
683 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
684 For bug reports, read
685 http://openocd.sourceforge.net/doc/doxygen/bugs.html
686 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
687 (mfg: 0x23b, part: 0xba00, ver: 0x3)
688 @end example
690 Seeing that "tap/device found" message, and no warnings, means
691 the JTAG communication is working. That's a key milestone, but
692 you'll probably need more project-specific setup.
694 @section What OpenOCD does as it starts
696 OpenOCD starts by processing the configuration commands provided
697 on the command line or, if there were no @option{-c command} or
698 @option{-f file.cfg} options given, in @file{openocd.cfg}.
699 @xref{Configuration Stage}.
700 At the end of the configuration stage it verifies the JTAG scan
701 chain defined using those commands; your configuration should
702 ensure that this always succeeds.
703 Normally, OpenOCD then starts running as a daemon.
704 Alternatively, commands may be used to terminate the configuration
705 stage early, perform work (such as updating some flash memory),
706 and then shut down without acting as a daemon.
708 Once OpenOCD starts running as a daemon, it waits for connections from
709 clients (Telnet, GDB, Other) and processes the commands issued through
710 those channels.
712 If you are having problems, you can enable internal debug messages via
713 the @option{-d} option.
715 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
716 @option{-c} command line switch.
718 To enable debug output (when reporting problems or working on OpenOCD
719 itself), use the @option{-d} command line switch. This sets the
720 @option{debug_level} to "3", outputting the most information,
721 including debug messages. The default setting is "2", outputting only
722 informational messages, warnings and errors. You can also change this
723 setting from within a telnet or gdb session using @command{debug_level
724 <n>} (@pxref{debug_level}).
726 You can redirect all output from the daemon to a file using the
727 @option{-l <logfile>} switch.
729 Note! OpenOCD will launch the GDB & telnet server even if it can not
730 establish a connection with the target. In general, it is possible for
731 the JTAG controller to be unresponsive until the target is set up
732 correctly via e.g. GDB monitor commands in a GDB init script.
734 @node OpenOCD Project Setup
735 @chapter OpenOCD Project Setup
737 To use OpenOCD with your development projects, you need to do more than
738 just connecting the JTAG adapter hardware (dongle) to your development board
739 and then starting the OpenOCD server.
740 You also need to configure that server so that it knows
741 about that adapter and board, and helps your work.
742 You may also want to connect OpenOCD to GDB, possibly
743 using Eclipse or some other GUI.
745 @section Hooking up the JTAG Adapter
747 Today's most common case is a dongle with a JTAG cable on one side
748 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
749 and a USB cable on the other.
750 Instead of USB, some cables use Ethernet;
751 older ones may use a PC parallel port, or even a serial port.
753 @enumerate
754 @item @emph{Start with power to your target board turned off},
755 and nothing connected to your JTAG adapter.
756 If you're particularly paranoid, unplug power to the board.
757 It's important to have the ground signal properly set up,
758 unless you are using a JTAG adapter which provides
759 galvanic isolation between the target board and the
760 debugging host.
762 @item @emph{Be sure it's the right kind of JTAG connector.}
763 If your dongle has a 20-pin ARM connector, you need some kind
764 of adapter (or octopus, see below) to hook it up to
765 boards using 14-pin or 10-pin connectors ... or to 20-pin
766 connectors which don't use ARM's pinout.
768 In the same vein, make sure the voltage levels are compatible.
769 Not all JTAG adapters have the level shifters needed to work
770 with 1.2 Volt boards.
772 @item @emph{Be certain the cable is properly oriented} or you might
773 damage your board. In most cases there are only two possible
774 ways to connect the cable.
775 Connect the JTAG cable from your adapter to the board.
776 Be sure it's firmly connected.
778 In the best case, the connector is keyed to physically
779 prevent you from inserting it wrong.
780 This is most often done using a slot on the board's male connector
781 housing, which must match a key on the JTAG cable's female connector.
782 If there's no housing, then you must look carefully and
783 make sure pin 1 on the cable hooks up to pin 1 on the board.
784 Ribbon cables are frequently all grey except for a wire on one
785 edge, which is red. The red wire is pin 1.
787 Sometimes dongles provide cables where one end is an ``octopus'' of
788 color coded single-wire connectors, instead of a connector block.
789 These are great when converting from one JTAG pinout to another,
790 but are tedious to set up.
791 Use these with connector pinout diagrams to help you match up the
792 adapter signals to the right board pins.
794 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
795 A USB, parallel, or serial port connector will go to the host which
796 you are using to run OpenOCD.
797 For Ethernet, consult the documentation and your network administrator.
799 For USB based JTAG adapters you have an easy sanity check at this point:
800 does the host operating system see the JTAG adapter? If that host is an
801 MS-Windows host, you'll need to install a driver before OpenOCD works.
803 @item @emph{Connect the adapter's power supply, if needed.}
804 This step is primarily for non-USB adapters,
805 but sometimes USB adapters need extra power.
807 @item @emph{Power up the target board.}
808 Unless you just let the magic smoke escape,
809 you're now ready to set up the OpenOCD server
810 so you can use JTAG to work with that board.
812 @end enumerate
814 Talk with the OpenOCD server using
815 telnet (@code{telnet localhost 4444} on many systems) or GDB.
816 @xref{GDB and OpenOCD}.
818 @section Project Directory
820 There are many ways you can configure OpenOCD and start it up.
822 A simple way to organize them all involves keeping a
823 single directory for your work with a given board.
824 When you start OpenOCD from that directory,
825 it searches there first for configuration files, scripts,
826 files accessed through semihosting,
827 and for code you upload to the target board.
828 It is also the natural place to write files,
829 such as log files and data you download from the board.
831 @section Configuration Basics
833 There are two basic ways of configuring OpenOCD, and
834 a variety of ways you can mix them.
835 Think of the difference as just being how you start the server:
837 @itemize
838 @item Many @option{-f file} or @option{-c command} options on the command line
839 @item No options, but a @dfn{user config file}
840 in the current directory named @file{openocd.cfg}
841 @end itemize
843 Here is an example @file{openocd.cfg} file for a setup
844 using a Signalyzer FT2232-based JTAG adapter to talk to
845 a board with an Atmel AT91SAM7X256 microcontroller:
847 @example
848 source [find interface/signalyzer.cfg]
850 # GDB can also flash my flash!
851 gdb_memory_map enable
852 gdb_flash_program enable
854 source [find target/sam7x256.cfg]
855 @end example
857 Here is the command line equivalent of that configuration:
859 @example
860 openocd -f interface/signalyzer.cfg \
861 -c "gdb_memory_map enable" \
862 -c "gdb_flash_program enable" \
863 -f target/sam7x256.cfg
864 @end example
866 You could wrap such long command lines in shell scripts,
867 each supporting a different development task.
868 One might re-flash the board with a specific firmware version.
869 Another might set up a particular debugging or run-time environment.
871 @quotation Important
872 At this writing (October 2009) the command line method has
873 problems with how it treats variables.
874 For example, after @option{-c "set VAR value"}, or doing the
875 same in a script, the variable @var{VAR} will have no value
876 that can be tested in a later script.
877 @end quotation
879 Here we will focus on the simpler solution: one user config
880 file, including basic configuration plus any TCL procedures
881 to simplify your work.
883 @section User Config Files
884 @cindex config file, user
885 @cindex user config file
886 @cindex config file, overview
888 A user configuration file ties together all the parts of a project
889 in one place.
890 One of the following will match your situation best:
892 @itemize
893 @item Ideally almost everything comes from configuration files
894 provided by someone else.
895 For example, OpenOCD distributes a @file{scripts} directory
896 (probably in @file{/usr/share/openocd/scripts} on Linux).
897 Board and tool vendors can provide these too, as can individual
898 user sites; the @option{-s} command line option lets you say
899 where to find these files. (@xref{Running}.)
900 The AT91SAM7X256 example above works this way.
902 Three main types of non-user configuration file each have their
903 own subdirectory in the @file{scripts} directory:
905 @enumerate
906 @item @b{interface} -- one for each different debug adapter;
907 @item @b{board} -- one for each different board
908 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
909 @end enumerate
911 Best case: include just two files, and they handle everything else.
912 The first is an interface config file.
913 The second is board-specific, and it sets up the JTAG TAPs and
914 their GDB targets (by deferring to some @file{target.cfg} file),
915 declares all flash memory, and leaves you nothing to do except
916 meet your deadline:
918 @example
919 source [find interface/olimex-jtag-tiny.cfg]
920 source [find board/csb337.cfg]
921 @end example
923 Boards with a single microcontroller often won't need more
924 than the target config file, as in the AT91SAM7X256 example.
925 That's because there is no external memory (flash, DDR RAM), and
926 the board differences are encapsulated by application code.
928 @item Maybe you don't know yet what your board looks like to JTAG.
929 Once you know the @file{interface.cfg} file to use, you may
930 need help from OpenOCD to discover what's on the board.
931 Once you find the JTAG TAPs, you can just search for appropriate
932 target and board
933 configuration files ... or write your own, from the bottom up.
934 @xref{Autoprobing}.
936 @item You can often reuse some standard config files but
937 need to write a few new ones, probably a @file{board.cfg} file.
938 You will be using commands described later in this User's Guide,
939 and working with the guidelines in the next chapter.
941 For example, there may be configuration files for your JTAG adapter
942 and target chip, but you need a new board-specific config file
943 giving access to your particular flash chips.
944 Or you might need to write another target chip configuration file
945 for a new chip built around the Cortex M3 core.
947 @quotation Note
948 When you write new configuration files, please submit
949 them for inclusion in the next OpenOCD release.
950 For example, a @file{board/newboard.cfg} file will help the
951 next users of that board, and a @file{target/newcpu.cfg}
952 will help support users of any board using that chip.
953 @end quotation
955 @item
956 You may may need to write some C code.
957 It may be as simple as a supporting a new ft2232 or parport
958 based adapter; a bit more involved, like a NAND or NOR flash
959 controller driver; or a big piece of work like supporting
960 a new chip architecture.
961 @end itemize
963 Reuse the existing config files when you can.
964 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
965 You may find a board configuration that's a good example to follow.
967 When you write config files, separate the reusable parts
968 (things every user of that interface, chip, or board needs)
969 from ones specific to your environment and debugging approach.
970 @itemize
972 @item
973 For example, a @code{gdb-attach} event handler that invokes
974 the @command{reset init} command will interfere with debugging
975 early boot code, which performs some of the same actions
976 that the @code{reset-init} event handler does.
978 @item
979 Likewise, the @command{arm9 vector_catch} command (or
980 @cindex vector_catch
981 its siblings @command{xscale vector_catch}
982 and @command{cortex_m3 vector_catch}) can be a timesaver
983 during some debug sessions, but don't make everyone use that either.
984 Keep those kinds of debugging aids in your user config file,
985 along with messaging and tracing setup.
986 (@xref{Software Debug Messages and Tracing}.)
988 @item
989 You might need to override some defaults.
990 For example, you might need to move, shrink, or back up the target's
991 work area if your application needs much SRAM.
993 @item
994 TCP/IP port configuration is another example of something which
995 is environment-specific, and should only appear in
996 a user config file. @xref{TCP/IP Ports}.
997 @end itemize
999 @section Project-Specific Utilities
1001 A few project-specific utility
1002 routines may well speed up your work.
1003 Write them, and keep them in your project's user config file.
1005 For example, if you are making a boot loader work on a
1006 board, it's nice to be able to debug the ``after it's
1007 loaded to RAM'' parts separately from the finicky early
1008 code which sets up the DDR RAM controller and clocks.
1009 A script like this one, or a more GDB-aware sibling,
1010 may help:
1012 @example
1013 proc ramboot @{ @} @{
1014 # Reset, running the target's "reset-init" scripts
1015 # to initialize clocks and the DDR RAM controller.
1016 # Leave the CPU halted.
1017 reset init
1019 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1020 load_image u-boot.bin 0x20000000
1022 # Start running.
1023 resume 0x20000000
1024 @}
1025 @end example
1027 Then once that code is working you will need to make it
1028 boot from NOR flash; a different utility would help.
1029 Alternatively, some developers write to flash using GDB.
1030 (You might use a similar script if you're working with a flash
1031 based microcontroller application instead of a boot loader.)
1033 @example
1034 proc newboot @{ @} @{
1035 # Reset, leaving the CPU halted. The "reset-init" event
1036 # proc gives faster access to the CPU and to NOR flash;
1037 # "reset halt" would be slower.
1038 reset init
1040 # Write standard version of U-Boot into the first two
1041 # sectors of NOR flash ... the standard version should
1042 # do the same lowlevel init as "reset-init".
1043 flash protect 0 0 1 off
1044 flash erase_sector 0 0 1
1045 flash write_bank 0 u-boot.bin 0x0
1046 flash protect 0 0 1 on
1048 # Reboot from scratch using that new boot loader.
1049 reset run
1050 @}
1051 @end example
1053 You may need more complicated utility procedures when booting
1054 from NAND.
1055 That often involves an extra bootloader stage,
1056 running from on-chip SRAM to perform DDR RAM setup so it can load
1057 the main bootloader code (which won't fit into that SRAM).
1059 Other helper scripts might be used to write production system images,
1060 involving considerably more than just a three stage bootloader.
1062 @section Target Software Changes
1064 Sometimes you may want to make some small changes to the software
1065 you're developing, to help make JTAG debugging work better.
1066 For example, in C or assembly language code you might
1067 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1068 handling issues like:
1070 @itemize @bullet
1072 @item @b{Watchdog Timers}...
1073 Watchog timers are typically used to automatically reset systems if
1074 some application task doesn't periodically reset the timer. (The
1075 assumption is that the system has locked up if the task can't run.)
1076 When a JTAG debugger halts the system, that task won't be able to run
1077 and reset the timer ... potentially causing resets in the middle of
1078 your debug sessions.
1080 It's rarely a good idea to disable such watchdogs, since their usage
1081 needs to be debugged just like all other parts of your firmware.
1082 That might however be your only option.
1084 Look instead for chip-specific ways to stop the watchdog from counting
1085 while the system is in a debug halt state. It may be simplest to set
1086 that non-counting mode in your debugger startup scripts. You may however
1087 need a different approach when, for example, a motor could be physically
1088 damaged by firmware remaining inactive in a debug halt state. That might
1089 involve a type of firmware mode where that "non-counting" mode is disabled
1090 at the beginning then re-enabled at the end; a watchdog reset might fire
1091 and complicate the debug session, but hardware (or people) would be
1092 protected.@footnote{Note that many systems support a "monitor mode" debug
1093 that is a somewhat cleaner way to address such issues. You can think of
1094 it as only halting part of the system, maybe just one task,
1095 instead of the whole thing.
1096 At this writing, January 2010, OpenOCD based debugging does not support
1097 monitor mode debug, only "halt mode" debug.}
1099 @item @b{ARM Semihosting}...
1100 @cindex ARM semihosting
1101 When linked with a special runtime library provided with many
1102 toolchains@footnote{See chapter 8 "Semihosting" in
1103 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1104 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1105 The CodeSourcery EABI toolchain also includes a semihosting library.},
1106 your target code can use I/O facilities on the debug host. That library
1107 provides a small set of system calls which are handled by OpenOCD.
1108 It can let the debugger provide your system console and a file system,
1109 helping with early debugging or providing a more capable environment
1110 for sometimes-complex tasks like installing system firmware onto
1111 NAND or SPI flash.
1113 @item @b{ARM Wait-For-Interrupt}...
1114 Many ARM chips synchronize the JTAG clock using the core clock.
1115 Low power states which stop that core clock thus prevent JTAG access.
1116 Idle loops in tasking environments often enter those low power states
1117 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1119 You may want to @emph{disable that instruction} in source code,
1120 or otherwise prevent using that state,
1121 to ensure you can get JTAG access at any time.@footnote{As a more
1122 polite alternative, some processors have special debug-oriented
1123 registers which can be used to change various features including
1124 how the low power states are clocked while debugging.
1125 The STM32 DBGMCU_CR register is an example; at the cost of extra
1126 power consumption, JTAG can be used during low power states.}
1127 For example, the OpenOCD @command{halt} command may not
1128 work for an idle processor otherwise.
1130 @item @b{Delay after reset}...
1131 Not all chips have good support for debugger access
1132 right after reset; many LPC2xxx chips have issues here.
1133 Similarly, applications that reconfigure pins used for
1134 JTAG access as they start will also block debugger access.
1136 To work with boards like this, @emph{enable a short delay loop}
1137 the first thing after reset, before "real" startup activities.
1138 For example, one second's delay is usually more than enough
1139 time for a JTAG debugger to attach, so that
1140 early code execution can be debugged
1141 or firmware can be replaced.
1143 @item @b{Debug Communications Channel (DCC)}...
1144 Some processors include mechanisms to send messages over JTAG.
1145 Many ARM cores support these, as do some cores from other vendors.
1146 (OpenOCD may be able to use this DCC internally, speeding up some
1147 operations like writing to memory.)
1149 Your application may want to deliver various debugging messages
1150 over JTAG, by @emph{linking with a small library of code}
1151 provided with OpenOCD and using the utilities there to send
1152 various kinds of message.
1153 @xref{Software Debug Messages and Tracing}.
1155 @end itemize
1157 @section Target Hardware Setup
1159 Chip vendors often provide software development boards which
1160 are highly configurable, so that they can support all options
1161 that product boards may require. @emph{Make sure that any
1162 jumpers or switches match the system configuration you are
1163 working with.}
1165 Common issues include:
1167 @itemize @bullet
1169 @item @b{JTAG setup} ...
1170 Boards may support more than one JTAG configuration.
1171 Examples include jumpers controlling pullups versus pulldowns
1172 on the nTRST and/or nSRST signals, and choice of connectors
1173 (e.g. which of two headers on the base board,
1174 or one from a daughtercard).
1175 For some Texas Instruments boards, you may need to jumper the
1176 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1178 @item @b{Boot Modes} ...
1179 Complex chips often support multiple boot modes, controlled
1180 by external jumpers. Make sure this is set up correctly.
1181 For example many i.MX boards from NXP need to be jumpered
1182 to "ATX mode" to start booting using the on-chip ROM, when
1183 using second stage bootloader code stored in a NAND flash chip.
1185 Such explicit configuration is common, and not limited to
1186 booting from NAND. You might also need to set jumpers to
1187 start booting using code loaded from an MMC/SD card; external
1188 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1189 flash; some external host; or various other sources.
1192 @item @b{Memory Addressing} ...
1193 Boards which support multiple boot modes may also have jumpers
1194 to configure memory addressing. One board, for example, jumpers
1195 external chipselect 0 (used for booting) to address either
1196 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1197 or NAND flash. When it's jumpered to address NAND flash, that
1198 board must also be told to start booting from on-chip ROM.
1200 Your @file{board.cfg} file may also need to be told this jumper
1201 configuration, so that it can know whether to declare NOR flash
1202 using @command{flash bank} or instead declare NAND flash with
1203 @command{nand device}; and likewise which probe to perform in
1204 its @code{reset-init} handler.
1206 A closely related issue is bus width. Jumpers might need to
1207 distinguish between 8 bit or 16 bit bus access for the flash
1208 used to start booting.
1210 @item @b{Peripheral Access} ...
1211 Development boards generally provide access to every peripheral
1212 on the chip, sometimes in multiple modes (such as by providing
1213 multiple audio codec chips).
1214 This interacts with software
1215 configuration of pin multiplexing, where for example a
1216 given pin may be routed either to the MMC/SD controller
1217 or the GPIO controller. It also often interacts with
1218 configuration jumpers. One jumper may be used to route
1219 signals to an MMC/SD card slot or an expansion bus (which
1220 might in turn affect booting); others might control which
1221 audio or video codecs are used.
1223 @end itemize
1225 Plus you should of course have @code{reset-init} event handlers
1226 which set up the hardware to match that jumper configuration.
1227 That includes in particular any oscillator or PLL used to clock
1228 the CPU, and any memory controllers needed to access external
1229 memory and peripherals. Without such handlers, you won't be
1230 able to access those resources without working target firmware
1231 which can do that setup ... this can be awkward when you're
1232 trying to debug that target firmware. Even if there's a ROM
1233 bootloader which handles a few issues, it rarely provides full
1234 access to all board-specific capabilities.
1237 @node Config File Guidelines
1238 @chapter Config File Guidelines
1240 This chapter is aimed at any user who needs to write a config file,
1241 including developers and integrators of OpenOCD and any user who
1242 needs to get a new board working smoothly.
1243 It provides guidelines for creating those files.
1245 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1246 with files including the ones listed here.
1247 Use them as-is where you can; or as models for new files.
1248 @itemize @bullet
1249 @item @file{interface} ...
1250 These are for debug adapters.
1251 Files that configure JTAG adapters go here.
1252 @example
1253 $ ls interface
1254 altera-usb-blaster.cfg hilscher_nxhx50_etm.cfg openrd.cfg
1255 arm-jtag-ew.cfg hilscher_nxhx50_re.cfg osbdm.cfg
1256 arm-usb-ocd.cfg hitex_str9-comstick.cfg parport.cfg
1257 at91rm9200.cfg icebear.cfg parport_dlc5.cfg
1258 axm0432.cfg jlink.cfg redbee-econotag.cfg
1259 busblaster.cfg jtagkey2.cfg redbee-usb.cfg
1260 buspirate.cfg jtagkey2p.cfg rlink.cfg
1261 calao-usb-a9260-c01.cfg jtagkey.cfg sheevaplug.cfg
1262 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg signalyzer.cfg
1263 calao-usb-a9260.cfg kt-link.cfg signalyzer-h2.cfg
1264 chameleon.cfg lisa-l.cfg signalyzer-h4.cfg
1265 cortino.cfg luminary.cfg signalyzer-lite.cfg
1266 digilent-hs1.cfg luminary-icdi.cfg stlink-v1.cfg
1267 dlp-usb1232h.cfg luminary-lm3s811.cfg stlink-v2.cfg
1268 dummy.cfg minimodule.cfg stm32-stick.cfg
1269 estick.cfg neodb.cfg turtelizer2.cfg
1270 flashlink.cfg ngxtech.cfg ulink.cfg
1271 flossjtag.cfg olimex-arm-usb-ocd.cfg usb-jtag.cfg
1272 flossjtag-noeeprom.cfg olimex-arm-usb-ocd-h.cfg usbprog.cfg
1273 flyswatter2.cfg olimex-arm-usb-tiny-h.cfg vpaclink.cfg
1274 flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
1275 hilscher_nxhx10_etm.cfg oocdlink.cfg xds100v2.cfg
1276 hilscher_nxhx500_etm.cfg opendous.cfg
1277 hilscher_nxhx500_re.cfg openocd-usb.cfg
1278 $
1279 @end example
1280 @item @file{board} ...
1281 think Circuit Board, PWA, PCB, they go by many names. Board files
1282 contain initialization items that are specific to a board.
1283 They reuse target configuration files, since the same
1284 microprocessor chips are used on many boards,
1285 but support for external parts varies widely. For
1286 example, the SDRAM initialization sequence for the board, or the type
1287 of external flash and what address it uses. Any initialization
1288 sequence to enable that external flash or SDRAM should be found in the
1289 board file. Boards may also contain multiple targets: two CPUs; or
1290 a CPU and an FPGA.
1291 @example
1292 $ ls board
1293 actux3.cfg logicpd_imx27.cfg
1294 am3517evm.cfg lubbock.cfg
1295 arm_evaluator7t.cfg mcb1700.cfg
1296 at91cap7a-stk-sdram.cfg microchip_explorer16.cfg
1297 at91eb40a.cfg mini2440.cfg
1298 at91rm9200-dk.cfg mini6410.cfg
1299 at91rm9200-ek.cfg olimex_LPC2378STK.cfg
1300 at91sam9261-ek.cfg olimex_lpc_h2148.cfg
1301 at91sam9263-ek.cfg olimex_sam7_ex256.cfg
1302 at91sam9g20-ek.cfg olimex_sam9_l9260.cfg
1303 atmel_at91sam7s-ek.cfg olimex_stm32_h103.cfg
1304 atmel_at91sam9260-ek.cfg olimex_stm32_h107.cfg
1305 atmel_at91sam9rl-ek.cfg olimex_stm32_p107.cfg
1306 atmel_sam3n_ek.cfg omap2420_h4.cfg
1307 atmel_sam3s_ek.cfg open-bldc.cfg
1308 atmel_sam3u_ek.cfg openrd.cfg
1309 atmel_sam3x_ek.cfg osk5912.cfg
1310 atmel_sam4s_ek.cfg phytec_lpc3250.cfg
1311 balloon3-cpu.cfg pic-p32mx.cfg
1312 colibri.cfg propox_mmnet1001.cfg
1313 crossbow_tech_imote2.cfg pxa255_sst.cfg
1314 csb337.cfg redbee.cfg
1315 csb732.cfg rsc-w910.cfg
1316 da850evm.cfg sheevaplug.cfg
1317 digi_connectcore_wi-9c.cfg smdk6410.cfg
1318 diolan_lpc4350-db1.cfg spear300evb.cfg
1319 dm355evm.cfg spear300evb_mod.cfg
1320 dm365evm.cfg spear310evb20.cfg
1321 dm6446evm.cfg spear310evb20_mod.cfg
1322 efikamx.cfg spear320cpu.cfg
1323 eir.cfg spear320cpu_mod.cfg
1324 ek-lm3s1968.cfg steval_pcc010.cfg
1325 ek-lm3s3748.cfg stm320518_eval_stlink.cfg
1326 ek-lm3s6965.cfg stm32100b_eval.cfg
1327 ek-lm3s811.cfg stm3210b_eval.cfg
1328 ek-lm3s811-revb.cfg stm3210c_eval.cfg
1329 ek-lm3s9b9x.cfg stm3210e_eval.cfg
1330 ek-lm4f232.cfg stm3220g_eval.cfg
1331 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1332 ethernut3.cfg stm3241g_eval.cfg
1333 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1334 hammer.cfg stm32f0discovery.cfg
1335 hilscher_nxdb500sys.cfg stm32f4discovery.cfg
1336 hilscher_nxeb500hmi.cfg stm32ldiscovery.cfg
1337 hilscher_nxhx10.cfg stm32vldiscovery.cfg
1338 hilscher_nxhx500.cfg str910-eval.cfg
1339 hilscher_nxhx50.cfg telo.cfg
1340 hilscher_nxsb100.cfg ti_beagleboard.cfg
1341 hitex_lpc2929.cfg ti_beagleboard_xm.cfg
1342 hitex_stm32-performancestick.cfg ti_beaglebone.cfg
1343 hitex_str9-comstick.cfg ti_blaze.cfg
1344 iar_lpc1768.cfg ti_pandaboard.cfg
1345 iar_str912_sk.cfg ti_pandaboard_es.cfg
1346 icnova_imx53_sodimm.cfg topas910.cfg
1347 icnova_sam9g45_sodimm.cfg topasa900.cfg
1348 imx27ads.cfg twr-k60n512.cfg
1349 imx27lnst.cfg tx25_stk5.cfg
1350 imx28evk.cfg tx27_stk5.cfg
1351 imx31pdk.cfg unknown_at91sam9260.cfg
1352 imx35pdk.cfg uptech_2410.cfg
1353 imx53loco.cfg verdex.cfg
1354 keil_mcb1700.cfg voipac.cfg
1355 keil_mcb2140.cfg voltcraft_dso-3062c.cfg
1356 kwikstik.cfg x300t.cfg
1357 linksys_nslu2.cfg zy1000.cfg
1358 lisa-l.cfg
1359 $
1360 @end example
1361 @item @file{target} ...
1362 think chip. The ``target'' directory represents the JTAG TAPs
1363 on a chip
1364 which OpenOCD should control, not a board. Two common types of targets
1365 are ARM chips and FPGA or CPLD chips.
1366 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1367 the target config file defines all of them.
1368 @example
1369 $ ls target
1370 $duc702x.cfg ixp42x.cfg
1371 am335x.cfg k40.cfg
1372 amdm37x.cfg k60.cfg
1373 ar71xx.cfg lpc1768.cfg
1374 at32ap7000.cfg lpc2103.cfg
1375 at91r40008.cfg lpc2124.cfg
1376 at91rm9200.cfg lpc2129.cfg
1377 at91sam3ax_4x.cfg lpc2148.cfg
1378 at91sam3ax_8x.cfg lpc2294.cfg
1379 at91sam3ax_xx.cfg lpc2378.cfg
1380 at91sam3nXX.cfg lpc2460.cfg
1381 at91sam3sXX.cfg lpc2478.cfg
1382 at91sam3u1c.cfg lpc2900.cfg
1383 at91sam3u1e.cfg lpc2xxx.cfg
1384 at91sam3u2c.cfg lpc3131.cfg
1385 at91sam3u2e.cfg lpc3250.cfg
1386 at91sam3u4c.cfg lpc4350.cfg
1387 at91sam3u4e.cfg mc13224v.cfg
1388 at91sam3uxx.cfg nuc910.cfg
1389 at91sam3XXX.cfg omap2420.cfg
1390 at91sam4sXX.cfg omap3530.cfg
1391 at91sam4XXX.cfg omap4430.cfg
1392 at91sam7se512.cfg omap4460.cfg
1393 at91sam7sx.cfg omap5912.cfg
1394 at91sam7x256.cfg omapl138.cfg
1395 at91sam7x512.cfg pic32mx.cfg
1396 at91sam9260.cfg pxa255.cfg
1397 at91sam9260_ext_RAM_ext_flash.cfg pxa270.cfg
1398 at91sam9261.cfg pxa3xx.cfg
1399 at91sam9263.cfg readme.txt
1400 at91sam9.cfg samsung_s3c2410.cfg
1401 at91sam9g10.cfg samsung_s3c2440.cfg
1402 at91sam9g20.cfg samsung_s3c2450.cfg
1403 at91sam9g45.cfg samsung_s3c4510.cfg
1404 at91sam9rl.cfg samsung_s3c6410.cfg
1405 atmega128.cfg sharp_lh79532.cfg
1406 avr32.cfg smp8634.cfg
1407 c100.cfg spear3xx.cfg
1408 c100config.tcl stellaris.cfg
1409 c100helper.tcl stm32.cfg
1410 c100regs.tcl stm32f0x_stlink.cfg
1411 cs351x.cfg stm32f1x.cfg
1412 davinci.cfg stm32f1x_stlink.cfg
1413 dragonite.cfg stm32f2x.cfg
1414 dsp56321.cfg stm32f2x_stlink.cfg
1415 dsp568013.cfg stm32f2xxx.cfg
1416 dsp568037.cfg stm32f4x.cfg
1417 epc9301.cfg stm32f4x_stlink.cfg
1418 faux.cfg stm32l.cfg
1419 feroceon.cfg stm32lx_stlink.cfg
1420 fm3.cfg stm32_stlink.cfg
1421 hilscher_netx10.cfg stm32xl.cfg
1422 hilscher_netx500.cfg str710.cfg
1423 hilscher_netx50.cfg str730.cfg
1424 icepick.cfg str750.cfg
1425 imx21.cfg str912.cfg
1426 imx25.cfg swj-dp.tcl
1427 imx27.cfg test_reset_syntax_error.cfg
1428 imx28.cfg test_syntax_error.cfg
1429 imx31.cfg ti_dm355.cfg
1430 imx35.cfg ti_dm365.cfg
1431 imx51.cfg ti_dm6446.cfg
1432 imx53.cfg tmpa900.cfg
1433 imx.cfg tmpa910.cfg
1434 is5114.cfg u8500.cfg
1435 @end example
1436 @item @emph{more} ... browse for other library files which may be useful.
1437 For example, there are various generic and CPU-specific utilities.
1438 @end itemize
1440 The @file{openocd.cfg} user config
1441 file may override features in any of the above files by
1442 setting variables before sourcing the target file, or by adding
1443 commands specific to their situation.
1445 @section Interface Config Files
1447 The user config file
1448 should be able to source one of these files with a command like this:
1450 @example
1451 source [find interface/FOOBAR.cfg]
1452 @end example
1454 A preconfigured interface file should exist for every debug adapter
1455 in use today with OpenOCD.
1456 That said, perhaps some of these config files
1457 have only been used by the developer who created it.
1459 A separate chapter gives information about how to set these up.
1460 @xref{Debug Adapter Configuration}.
1461 Read the OpenOCD source code (and Developer's Guide)
1462 if you have a new kind of hardware interface
1463 and need to provide a driver for it.
1465 @section Board Config Files
1466 @cindex config file, board
1467 @cindex board config file
1469 The user config file
1470 should be able to source one of these files with a command like this:
1472 @example
1473 source [find board/FOOBAR.cfg]
1474 @end example
1476 The point of a board config file is to package everything
1477 about a given board that user config files need to know.
1478 In summary the board files should contain (if present)
1480 @enumerate
1481 @item One or more @command{source [target/...cfg]} statements
1482 @item NOR flash configuration (@pxref{NOR Configuration})
1483 @item NAND flash configuration (@pxref{NAND Configuration})
1484 @item Target @code{reset} handlers for SDRAM and I/O configuration
1485 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1486 @item All things that are not ``inside a chip''
1487 @end enumerate
1489 Generic things inside target chips belong in target config files,
1490 not board config files. So for example a @code{reset-init} event
1491 handler should know board-specific oscillator and PLL parameters,
1492 which it passes to target-specific utility code.
1494 The most complex task of a board config file is creating such a
1495 @code{reset-init} event handler.
1496 Define those handlers last, after you verify the rest of the board
1497 configuration works.
1499 @subsection Communication Between Config files
1501 In addition to target-specific utility code, another way that
1502 board and target config files communicate is by following a
1503 convention on how to use certain variables.
1505 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1506 Thus the rule we follow in OpenOCD is this: Variables that begin with
1507 a leading underscore are temporary in nature, and can be modified and
1508 used at will within a target configuration file.
1510 Complex board config files can do the things like this,
1511 for a board with three chips:
1513 @example
1514 # Chip #1: PXA270 for network side, big endian
1515 set CHIPNAME network
1516 set ENDIAN big
1517 source [find target/pxa270.cfg]
1518 # on return: _TARGETNAME = network.cpu
1519 # other commands can refer to the "network.cpu" target.
1520 $_TARGETNAME configure .... events for this CPU..
1522 # Chip #2: PXA270 for video side, little endian
1523 set CHIPNAME video
1524 set ENDIAN little
1525 source [find target/pxa270.cfg]
1526 # on return: _TARGETNAME = video.cpu
1527 # other commands can refer to the "video.cpu" target.
1528 $_TARGETNAME configure .... events for this CPU..
1530 # Chip #3: Xilinx FPGA for glue logic
1531 set CHIPNAME xilinx
1532 unset ENDIAN
1533 source [find target/spartan3.cfg]
1534 @end example
1536 That example is oversimplified because it doesn't show any flash memory,
1537 or the @code{reset-init} event handlers to initialize external DRAM
1538 or (assuming it needs it) load a configuration into the FPGA.
1539 Such features are usually needed for low-level work with many boards,
1540 where ``low level'' implies that the board initialization software may
1541 not be working. (That's a common reason to need JTAG tools. Another
1542 is to enable working with microcontroller-based systems, which often
1543 have no debugging support except a JTAG connector.)
1545 Target config files may also export utility functions to board and user
1546 config files. Such functions should use name prefixes, to help avoid
1547 naming collisions.
1549 Board files could also accept input variables from user config files.
1550 For example, there might be a @code{J4_JUMPER} setting used to identify
1551 what kind of flash memory a development board is using, or how to set
1552 up other clocks and peripherals.
1554 @subsection Variable Naming Convention
1555 @cindex variable names
1557 Most boards have only one instance of a chip.
1558 However, it should be easy to create a board with more than
1559 one such chip (as shown above).
1560 Accordingly, we encourage these conventions for naming
1561 variables associated with different @file{target.cfg} files,
1562 to promote consistency and
1563 so that board files can override target defaults.
1565 Inputs to target config files include:
1567 @itemize @bullet
1568 @item @code{CHIPNAME} ...
1569 This gives a name to the overall chip, and is used as part of
1570 tap identifier dotted names.
1571 While the default is normally provided by the chip manufacturer,
1572 board files may need to distinguish between instances of a chip.
1573 @item @code{ENDIAN} ...
1574 By default @option{little} - although chips may hard-wire @option{big}.
1575 Chips that can't change endianness don't need to use this variable.
1576 @item @code{CPUTAPID} ...
1577 When OpenOCD examines the JTAG chain, it can be told verify the
1578 chips against the JTAG IDCODE register.
1579 The target file will hold one or more defaults, but sometimes the
1580 chip in a board will use a different ID (perhaps a newer revision).
1581 @end itemize
1583 Outputs from target config files include:
1585 @itemize @bullet
1586 @item @code{_TARGETNAME} ...
1587 By convention, this variable is created by the target configuration
1588 script. The board configuration file may make use of this variable to
1589 configure things like a ``reset init'' script, or other things
1590 specific to that board and that target.
1591 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1592 @code{_TARGETNAME1}, ... etc.
1593 @end itemize
1595 @subsection The reset-init Event Handler
1596 @cindex event, reset-init
1597 @cindex reset-init handler
1599 Board config files run in the OpenOCD configuration stage;
1600 they can't use TAPs or targets, since they haven't been
1601 fully set up yet.
1602 This means you can't write memory or access chip registers;
1603 you can't even verify that a flash chip is present.
1604 That's done later in event handlers, of which the target @code{reset-init}
1605 handler is one of the most important.
1607 Except on microcontrollers, the basic job of @code{reset-init} event
1608 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1609 Microcontrollers rarely use boot loaders; they run right out of their
1610 on-chip flash and SRAM memory. But they may want to use one of these
1611 handlers too, if just for developer convenience.
1613 @quotation Note
1614 Because this is so very board-specific, and chip-specific, no examples
1615 are included here.
1616 Instead, look at the board config files distributed with OpenOCD.
1617 If you have a boot loader, its source code will help; so will
1618 configuration files for other JTAG tools
1619 (@pxref{Translating Configuration Files}).
1620 @end quotation
1622 Some of this code could probably be shared between different boards.
1623 For example, setting up a DRAM controller often doesn't differ by
1624 much except the bus width (16 bits or 32?) and memory timings, so a
1625 reusable TCL procedure loaded by the @file{target.cfg} file might take
1626 those as parameters.
1627 Similarly with oscillator, PLL, and clock setup;
1628 and disabling the watchdog.
1629 Structure the code cleanly, and provide comments to help
1630 the next developer doing such work.
1631 (@emph{You might be that next person} trying to reuse init code!)
1633 The last thing normally done in a @code{reset-init} handler is probing
1634 whatever flash memory was configured. For most chips that needs to be
1635 done while the associated target is halted, either because JTAG memory
1636 access uses the CPU or to prevent conflicting CPU access.
1638 @subsection JTAG Clock Rate
1640 Before your @code{reset-init} handler has set up
1641 the PLLs and clocking, you may need to run with
1642 a low JTAG clock rate.
1643 @xref{JTAG Speed}.
1644 Then you'd increase that rate after your handler has
1645 made it possible to use the faster JTAG clock.
1646 When the initial low speed is board-specific, for example
1647 because it depends on a board-specific oscillator speed, then
1648 you should probably set it up in the board config file;
1649 if it's target-specific, it belongs in the target config file.
1651 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1652 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1653 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1654 Consult chip documentation to determine the peak JTAG clock rate,
1655 which might be less than that.
1657 @quotation Warning
1658 On most ARMs, JTAG clock detection is coupled to the core clock, so
1659 software using a @option{wait for interrupt} operation blocks JTAG access.
1660 Adaptive clocking provides a partial workaround, but a more complete
1661 solution just avoids using that instruction with JTAG debuggers.
1662 @end quotation
1664 If both the chip and the board support adaptive clocking,
1665 use the @command{jtag_rclk}
1666 command, in case your board is used with JTAG adapter which
1667 also supports it. Otherwise use @command{adapter_khz}.
1668 Set the slow rate at the beginning of the reset sequence,
1669 and the faster rate as soon as the clocks are at full speed.
1671 @anchor{The init_board procedure}
1672 @subsection The init_board procedure
1673 @cindex init_board procedure
1675 The concept of @code{init_board} procedure is very similar to @code{init_targets} (@xref{The init_targets procedure}.)
1676 - it's a replacement of ``linear'' configuration scripts. This procedure is meant to be executed when OpenOCD enters run
1677 stage (@xref{Entering the Run Stage},) after @code{init_targets}. The idea to have spearate @code{init_targets} and
1678 @code{init_board} procedures is to allow the first one to configure everything target specific (internal flash,
1679 internal RAM, etc.) and the second one to configure everything board specific (reset signals, chip frequency,
1680 reset-init event handler, external memory, etc.). Additionally ``linear'' board config file will most likely fail when
1681 target config file uses @code{init_targets} scheme (``linear'' script is executed before @code{init} and
1682 @code{init_targets} - after), so separating these two configuration stages is very convenient, as the easiest way to
1683 overcome this problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1684 need to override @code{init_targets} defined in target config files when they only need to to add some specifics.
1686 Just as @code{init_targets}, the @code{init_board} procedure can be overriden by ``next level'' script (which sources
1687 the original), allowing greater code reuse.
1689 @example
1690 ### board_file.cfg ###
1692 # source target file that does most of the config in init_targets
1693 source [find target/target.cfg]
1695 proc enable_fast_clock @{@} @{
1696 # enables fast on-board clock source
1697 # configures the chip to use it
1698 @}
1700 # initialize only board specifics - reset, clock, adapter frequency
1701 proc init_board @{@} @{
1702 reset_config trst_and_srst trst_pulls_srst
1704 $_TARGETNAME configure -event reset-init @{
1705 adapter_khz 1
1706 enable_fast_clock
1707 adapter_khz 10000
1708 @}
1709 @}
1710 @end example
1712 @section Target Config Files
1713 @cindex config file, target
1714 @cindex target config file
1716 Board config files communicate with target config files using
1717 naming conventions as described above, and may source one or
1718 more target config files like this:
1720 @example
1721 source [find target/FOOBAR.cfg]
1722 @end example
1724 The point of a target config file is to package everything
1725 about a given chip that board config files need to know.
1726 In summary the target files should contain
1728 @enumerate
1729 @item Set defaults
1730 @item Add TAPs to the scan chain
1731 @item Add CPU targets (includes GDB support)
1732 @item CPU/Chip/CPU-Core specific features
1733 @item On-Chip flash
1734 @end enumerate
1736 As a rule of thumb, a target file sets up only one chip.
1737 For a microcontroller, that will often include a single TAP,
1738 which is a CPU needing a GDB target, and its on-chip flash.
1740 More complex chips may include multiple TAPs, and the target
1741 config file may need to define them all before OpenOCD
1742 can talk to the chip.
1743 For example, some phone chips have JTAG scan chains that include
1744 an ARM core for operating system use, a DSP,
1745 another ARM core embedded in an image processing engine,
1746 and other processing engines.
1748 @subsection Default Value Boiler Plate Code
1750 All target configuration files should start with code like this,
1751 letting board config files express environment-specific
1752 differences in how things should be set up.
1754 @example
1755 # Boards may override chip names, perhaps based on role,
1756 # but the default should match what the vendor uses
1757 if @{ [info exists CHIPNAME] @} @{
1759 @} else @{
1760 set _CHIPNAME sam7x256
1761 @}
1763 # ONLY use ENDIAN with targets that can change it.
1764 if @{ [info exists ENDIAN] @} @{
1765 set _ENDIAN $ENDIAN
1766 @} else @{
1767 set _ENDIAN little
1768 @}
1770 # TAP identifiers may change as chips mature, for example with
1771 # new revision fields (the "3" here). Pick a good default; you
1772 # can pass several such identifiers to the "jtag newtap" command.
1773 if @{ [info exists CPUTAPID ] @} @{
1775 @} else @{
1776 set _CPUTAPID 0x3f0f0f0f
1777 @}
1778 @end example
1779 @c but 0x3f0f0f0f is for an str73x part ...
1781 @emph{Remember:} Board config files may include multiple target
1782 config files, or the same target file multiple times
1783 (changing at least @code{CHIPNAME}).
1785 Likewise, the target configuration file should define
1786 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1787 use it later on when defining debug targets:
1789 @example
1791 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1792 @end example
1794 @subsection Adding TAPs to the Scan Chain
1795 After the ``defaults'' are set up,
1796 add the TAPs on each chip to the JTAG scan chain.
1797 @xref{TAP Declaration}, and the naming convention
1798 for taps.
1800 In the simplest case the chip has only one TAP,
1801 probably for a CPU or FPGA.
1802 The config file for the Atmel AT91SAM7X256
1803 looks (in part) like this:
1805 @example
1806 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1807 @end example
1809 A board with two such at91sam7 chips would be able
1810 to source such a config file twice, with different
1811 values for @code{CHIPNAME}, so
1812 it adds a different TAP each time.
1814 If there are nonzero @option{-expected-id} values,
1815 OpenOCD attempts to verify the actual tap id against those values.
1816 It will issue error messages if there is mismatch, which
1817 can help to pinpoint problems in OpenOCD configurations.
1819 @example
1820 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1821 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1822 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1823 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1824 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1825 @end example
1827 There are more complex examples too, with chips that have
1828 multiple TAPs. Ones worth looking at include:
1830 @itemize
1831 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1832 plus a JRC to enable them
1833 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1834 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1835 is not currently used)
1836 @end itemize
1838 @subsection Add CPU targets
1840 After adding a TAP for a CPU, you should set it up so that
1841 GDB and other commands can use it.
1842 @xref{CPU Configuration}.
1843 For the at91sam7 example above, the command can look like this;
1844 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1845 to little endian, and this chip doesn't support changing that.
1847 @example
1849 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1850 @end example
1852 Work areas are small RAM areas associated with CPU targets.
1853 They are used by OpenOCD to speed up downloads,
1854 and to download small snippets of code to program flash chips.
1855 If the chip includes a form of ``on-chip-ram'' - and many do - define
1856 a work area if you can.
1857 Again using the at91sam7 as an example, this can look like:
1859 @example
1860 $_TARGETNAME configure -work-area-phys 0x00200000 \
1861 -work-area-size 0x4000 -work-area-backup 0
1862 @end example
1864 @anchor{Define CPU targets working in SMP}
1865 @subsection Define CPU targets working in SMP
1866 @cindex SMP
1867 After setting targets, you can define a list of targets working in SMP.
1869 @example
1870 set _TARGETNAME_1 $_CHIPNAME.cpu1
1871 set _TARGETNAME_2 $_CHIPNAME.cpu2
1872 target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap \
1873 -coreid 0 -dbgbase $_DAP_DBG1
1874 target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap \
1875 -coreid 1 -dbgbase $_DAP_DBG2
1876 #define 2 targets working in smp.
1877 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1878 @end example
1879 In the above example on cortex_a8, 2 cpus are working in SMP.
1880 In SMP only one GDB instance is created and :
1881 @itemize @bullet
1882 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1883 @item halt command triggers the halt of all targets in the list.
1884 @item resume command triggers the write context and the restart of all targets in the list.
1885 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1886 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1887 displayed by the GDB session @pxref{Using openocd SMP with GDB}.
1888 @end itemize
1890 The SMP behaviour can be disabled/enabled dynamically. On cortex_a8 following
1891 command have been implemented.
1892 @itemize @bullet
1893 @item cortex_a8 smp_on : enable SMP mode, behaviour is as described above.
1894 @item cortex_a8 smp_off : disable SMP mode, the current target is the one
1895 displayed in the GDB session, only this target is now controlled by GDB
1896 session. This behaviour is useful during system boot up.
1897 @item cortex_a8 smp_gdb : display/fix the core id displayed in GDB session see
1898 following example.
1899 @end itemize
1901 @example
1902 >cortex_a8 smp_gdb
1903 gdb coreid 0 -> -1
1904 #0 : coreid 0 is displayed to GDB ,
1905 #-> -1 : next resume triggers a real resume
1906 > cortex_a8 smp_gdb 1
1907 gdb coreid 0 -> 1
1908 #0 :coreid 0 is displayed to GDB ,
1909 #->1 : next resume displays coreid 1 to GDB
1910 > resume
1911 > cortex_a8 smp_gdb
1912 gdb coreid 1 -> 1
1913 #1 :coreid 1 is displayed to GDB ,
1914 #->1 : next resume displays coreid 1 to GDB
1915 > cortex_a8 smp_gdb -1
1916 gdb coreid 1 -> -1
1917 #1 :coreid 1 is displayed to GDB,
1918 #->-1 : next resume triggers a real resume
1919 @end example
1922 @subsection Chip Reset Setup
1924 As a rule, you should put the @command{reset_config} command
1925 into the board file. Most things you think you know about a
1926 chip can be tweaked by the board.
1928 Some chips have specific ways the TRST and SRST signals are
1929 managed. In the unusual case that these are @emph{chip specific}
1930 and can never be changed by board wiring, they could go here.
1931 For example, some chips can't support JTAG debugging without
1932 both signals.
1934 Provide a @code{reset-assert} event handler if you can.
1935 Such a handler uses JTAG operations to reset the target,
1936 letting this target config be used in systems which don't
1937 provide the optional SRST signal, or on systems where you
1938 don't want to reset all targets at once.
1939 Such a handler might write to chip registers to force a reset,
1940 use a JRC to do that (preferable -- the target may be wedged!),
1941 or force a watchdog timer to trigger.
1942 (For Cortex-M3 targets, this is not necessary. The target
1943 driver knows how to use trigger an NVIC reset when SRST is
1944 not available.)
1946 Some chips need special attention during reset handling if
1947 they're going to be used with JTAG.
1948 An example might be needing to send some commands right
1949 after the target's TAP has been reset, providing a
1950 @code{reset-deassert-post} event handler that writes a chip
1951 register to report that JTAG debugging is being done.
1952 Another would be reconfiguring the watchdog so that it stops
1953 counting while the core is halted in the debugger.
1955 JTAG clocking constraints often change during reset, and in
1956 some cases target config files (rather than board config files)
1957 are the right places to handle some of those issues.
1958 For example, immediately after reset most chips run using a
1959 slower clock than they will use later.
1960 That means that after reset (and potentially, as OpenOCD
1961 first starts up) they must use a slower JTAG clock rate
1962 than they will use later.
1963 @xref{JTAG Speed}.
1965 @quotation Important
1966 When you are debugging code that runs right after chip
1967 reset, getting these issues right is critical.
1968 In particular, if you see intermittent failures when
1969 OpenOCD verifies the scan chain after reset,
1970 look at how you are setting up JTAG clocking.
1971 @end quotation
1973 @anchor{The init_targets procedure}
1974 @subsection The init_targets procedure
1975 @cindex init_targets procedure
1977 Target config files can either be ``linear'' (script executed line-by-line when parsed in configuration stage,
1978 @xref{Configuration Stage},) or they can contain a special procedure called @code{init_targets}, which will be executed
1979 when entering run stage (after parsing all config files or after @code{init} command, @xref{Entering the Run Stage}.)
1980 Such procedure can be overriden by ``next level'' script (which sources the original). This concept faciliates code
1981 reuse when basic target config files provide generic configuration procedures and @code{init_targets} procedure, which
1982 can then be sourced and enchanced or changed in a ``more specific'' target config file. This is not possible with
1983 ``linear'' config scripts, because sourcing them executes every initialization commands they provide.
1985 @example
1986 ### generic_file.cfg ###
1988 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1989 # basic initialization procedure ...
1990 @}
1992 proc init_targets @{@} @{
1993 # initializes generic chip with 4kB of flash and 1kB of RAM
1994 setup_my_chip MY_GENERIC_CHIP 4096 1024
1995 @}
1997 ### specific_file.cfg ###
1999 source [find target/generic_file.cfg]
2001 proc init_targets @{@} @{
2002 # initializes specific chip with 128kB of flash and 64kB of RAM
2003 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
2004 @}
2005 @end example
2007 The easiest way to convert ``linear'' config files to @code{init_targets} version is to enclose every line of ``code''
2008 (i.e. not @code{source} commands, procedures, etc.) in this procedure.
2010 For an example of this scheme see LPC2000 target config files.
2012 The @code{init_boards} procedure is a similar concept concerning board config files (@xref{The init_board procedure}.)
2014 @subsection ARM Core Specific Hacks
2016 If the chip has a DCC, enable it. If the chip is an ARM9 with some
2017 special high speed download features - enable it.
2019 If present, the MMU, the MPU and the CACHE should be disabled.
2021 Some ARM cores are equipped with trace support, which permits
2022 examination of the instruction and data bus activity. Trace
2023 activity is controlled through an ``Embedded Trace Module'' (ETM)
2024 on one of the core's scan chains. The ETM emits voluminous data
2025 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
2026 If you are using an external trace port,
2027 configure it in your board config file.
2028 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2029 configure it in your target config file.
2031 @example
2032 etm config $_TARGETNAME 16 normal full etb
2033 etb config $_TARGETNAME $_CHIPNAME.etb
2034 @end example
2036 @subsection Internal Flash Configuration
2038 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2040 @b{Never ever} in the ``target configuration file'' define any type of
2041 flash that is external to the chip. (For example a BOOT flash on
2042 Chip Select 0.) Such flash information goes in a board file - not
2043 the TARGET (chip) file.
2045 Examples:
2046 @itemize @bullet
2047 @item at91sam7x256 - has 256K flash YES enable it.
2048 @item str912 - has flash internal YES enable it.
2049 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2050 @item pxa270 - again - CS0 flash - it goes in the board file.
2051 @end itemize
2053 @anchor{Translating Configuration Files}
2054 @section Translating Configuration Files
2055 @cindex translation
2056 If you have a configuration file for another hardware debugger
2057 or toolset (Abatron, BDI2000, BDI3000, CCS,
2058 Lauterbach, Segger, Macraigor, etc.), translating
2059 it into OpenOCD syntax is often quite straightforward. The most tricky
2060 part of creating a configuration script is oftentimes the reset init
2061 sequence where e.g. PLLs, DRAM and the like is set up.
2063 One trick that you can use when translating is to write small
2064 Tcl procedures to translate the syntax into OpenOCD syntax. This
2065 can avoid manual translation errors and make it easier to
2066 convert other scripts later on.
2068 Example of transforming quirky arguments to a simple search and
2069 replace job:
2071 @example
2072 # Lauterbach syntax(?)
2073 #
2074 # Data.Set c15:0x042f %long 0x40000015
2075 #
2076 # OpenOCD syntax when using procedure below.
2077 #
2078 # setc15 0x01 0x00050078
2080 proc setc15 @{regs value@} @{
2081 global TARGETNAME
2083 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2085 arm mcr 15 [expr ($regs>>12)&0x7] \
2086 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2087 [expr ($regs>>8)&0x7] $value
2088 @}
2089 @end example
2093 @node Daemon Configuration
2094 @chapter Daemon Configuration
2095 @cindex initialization
2096 The commands here are commonly found in the openocd.cfg file and are
2097 used to specify what TCP/IP ports are used, and how GDB should be
2098 supported.
2100 @anchor{Configuration Stage}
2101 @section Configuration Stage
2102 @cindex configuration stage
2103 @cindex config command
2105 When the OpenOCD server process starts up, it enters a
2106 @emph{configuration stage} which is the only time that
2107 certain commands, @emph{configuration commands}, may be issued.
2108 Normally, configuration commands are only available
2109 inside startup scripts.
2111 In this manual, the definition of a configuration command is
2112 presented as a @emph{Config Command}, not as a @emph{Command}
2113 which may be issued interactively.
2114 The runtime @command{help} command also highlights configuration
2115 commands, and those which may be issued at any time.
2117 Those configuration commands include declaration of TAPs,
2118 flash banks,
2119 the interface used for JTAG communication,
2120 and other basic setup.
2121 The server must leave the configuration stage before it
2122 may access or activate TAPs.
2123 After it leaves this stage, configuration commands may no
2124 longer be issued.
2126 @anchor{Entering the Run Stage}
2127 @section Entering the Run Stage
2129 The first thing OpenOCD does after leaving the configuration
2130 stage is to verify that it can talk to the scan chain
2131 (list of TAPs) which has been configured.
2132 It will warn if it doesn't find TAPs it expects to find,
2133 or finds TAPs that aren't supposed to be there.
2134 You should see no errors at this point.
2135 If you see errors, resolve them by correcting the
2136 commands you used to configure the server.
2137 Common errors include using an initial JTAG speed that's too
2138 fast, and not providing the right IDCODE values for the TAPs
2139 on the scan chain.
2141 Once OpenOCD has entered the run stage, a number of commands
2142 become available.
2143 A number of these relate to the debug targets you may have declared.
2144 For example, the @command{mww} command will not be available until
2145 a target has been successfuly instantiated.
2146 If you want to use those commands, you may need to force
2147 entry to the run stage.
2149 @deffn {Config Command} init
2150 This command terminates the configuration stage and
2151 enters the run stage. This helps when you need to have
2152 the startup scripts manage tasks such as resetting the target,
2153 programming flash, etc. To reset the CPU upon startup, add "init" and
2154 "reset" at the end of the config script or at the end of the OpenOCD
2155 command line using the @option{-c} command line switch.
2157 If this command does not appear in any startup/configuration file
2158 OpenOCD executes the command for you after processing all
2159 configuration files and/or command line options.
2161 @b{NOTE:} This command normally occurs at or near the end of your
2162 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2163 targets ready. For example: If your openocd.cfg file needs to
2164 read/write memory on your target, @command{init} must occur before
2165 the memory read/write commands. This includes @command{nand probe}.
2166 @end deffn
2168 @deffn {Overridable Procedure} jtag_init
2169 This is invoked at server startup to verify that it can talk
2170 to the scan chain (list of TAPs) which has been configured.
2172 The default implementation first tries @command{jtag arp_init},
2173 which uses only a lightweight JTAG reset before examining the
2174 scan chain.
2175 If that fails, it tries again, using a harder reset
2176 from the overridable procedure @command{init_reset}.
2178 Implementations must have verified the JTAG scan chain before
2179 they return.
2180 This is done by calling @command{jtag arp_init}
2181 (or @command{jtag arp_init-reset}).
2182 @end deffn
2184 @anchor{TCP/IP Ports}
2185 @section TCP/IP Ports
2186 @cindex TCP port
2187 @cindex server
2188 @cindex port
2189 @cindex security
2190 The OpenOCD server accepts remote commands in several syntaxes.
2191 Each syntax uses a different TCP/IP port, which you may specify
2192 only during configuration (before those ports are opened).
2194 For reasons including security, you may wish to prevent remote
2195 access using one or more of these ports.
2196 In such cases, just specify the relevant port number as zero.
2197 If you disable all access through TCP/IP, you will need to
2198 use the command line @option{-pipe} option.
2200 @deffn {Command} gdb_port [number]
2201 @cindex GDB server
2202 Normally gdb listens to a TCP/IP port, but GDB can also
2203 communicate via pipes(stdin/out or named pipes). The name
2204 "gdb_port" stuck because it covers probably more than 90% of
2205 the normal use cases.
2207 No arguments reports GDB port. "pipe" means listen to stdin
2208 output to stdout, an integer is base port number, "disable"
2209 disables the gdb server.
2211 When using "pipe", also use log_output to redirect the log
2212 output to a file so as not to flood the stdin/out pipes.
2214 The -p/--pipe option is deprecated and a warning is printed
2215 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2217 Any other string is interpreted as named pipe to listen to.
2218 Output pipe is the same name as input pipe, but with 'o' appended,
2219 e.g. /var/gdb, /var/gdbo.
2221 The GDB port for the first target will be the base port, the
2222 second target will listen on gdb_port + 1, and so on.
2223 When not specified during the configuration stage,
2224 the port @var{number} defaults to 3333.
2225 @end deffn
2227 @deffn {Command} tcl_port [number]
2228 Specify or query the port used for a simplified RPC
2229 connection that can be used by clients to issue TCL commands and get the
2230 output from the Tcl engine.
2231 Intended as a machine interface.
2232 When not specified during the configuration stage,
2233 the port @var{number} defaults to 6666.
2235 @end deffn
2237 @deffn {Command} telnet_port [number]
2238 Specify or query the
2239 port on which to listen for incoming telnet connections.
2240 This port is intended for interaction with one human through TCL commands.
2241 When not specified during the configuration stage,
2242 the port @var{number} defaults to 4444.
2243 When specified as zero, this port is not activated.
2244 @end deffn
2246 @anchor{GDB Configuration}
2247 @section GDB Configuration
2248 @cindex GDB
2249 @cindex GDB configuration
2250 You can reconfigure some GDB behaviors if needed.
2251 The ones listed here are static and global.
2252 @xref{Target Configuration}, about configuring individual targets.
2253 @xref{Target Events}, about configuring target-specific event handling.
2255 @anchor{gdb_breakpoint_override}
2256 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2257 Force breakpoint type for gdb @command{break} commands.
2258 This option supports GDB GUIs which don't
2259 distinguish hard versus soft breakpoints, if the default OpenOCD and
2260 GDB behaviour is not sufficient. GDB normally uses hardware
2261 breakpoints if the memory map has been set up for flash regions.
2262 @end deffn
2264 @anchor{gdb_flash_program}
2265 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2266 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2267 vFlash packet is received.
2268 The default behaviour is @option{enable}.
2269 @end deffn
2271 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2272 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2273 requested. GDB will then know when to set hardware breakpoints, and program flash
2274 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2275 for flash programming to work.
2276 Default behaviour is @option{enable}.
2277 @xref{gdb_flash_program}.
2278 @end deffn
2280 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2281 Specifies whether data aborts cause an error to be reported
2282 by GDB memory read packets.
2283 The default behaviour is @option{disable};
2284 use @option{enable} see these errors reported.
2285 @end deffn
2287 @anchor{Event Polling}
2288 @section Event Polling
2290 Hardware debuggers are parts of asynchronous systems,
2291 where significant events can happen at any time.
2292 The OpenOCD server needs to detect some of these events,
2293 so it can report them to through TCL command line
2294 or to GDB.
2296 Examples of such events include:
2298 @itemize
2299 @item One of the targets can stop running ... maybe it triggers
2300 a code breakpoint or data watchpoint, or halts itself.
2301 @item Messages may be sent over ``debug message'' channels ... many
2302 targets support such messages sent over JTAG,
2303 for receipt by the person debugging or tools.
2304 @item Loss of power ... some adapters can detect these events.
2305 @item Resets not issued through JTAG ... such reset sources
2306 can include button presses or other system hardware, sometimes
2307 including the target itself (perhaps through a watchdog).
2308 @item Debug instrumentation sometimes supports event triggering
2309 such as ``trace buffer full'' (so it can quickly be emptied)
2310 or other signals (to correlate with code behavior).
2311 @end itemize
2313 None of those events are signaled through standard JTAG signals.
2314 However, most conventions for JTAG connectors include voltage
2315 level and system reset (SRST) signal detection.
2316 Some connectors also include instrumentation signals, which
2317 can imply events when those signals are inputs.
2319 In general, OpenOCD needs to periodically check for those events,
2320 either by looking at the status of signals on the JTAG connector
2321 or by sending synchronous ``tell me your status'' JTAG requests
2322 to the various active targets.
2323 There is a command to manage and monitor that polling,
2324 which is normally done in the background.
2326 @deffn Command poll [@option{on}|@option{off}]
2327 Poll the current target for its current state.
2328 (Also, @pxref{target curstate}.)
2329 If that target is in debug mode, architecture
2330 specific information about the current state is printed.
2331 An optional parameter
2332 allows background polling to be enabled and disabled.
2334 You could use this from the TCL command shell, or
2335 from GDB using @command{monitor poll} command.
2336 Leave background polling enabled while you're using GDB.
2337 @example
2338 > poll
2339 background polling: on
2340 target state: halted
2341 target halted in ARM state due to debug-request, \
2342 current mode: Supervisor
2343 cpsr: 0x800000d3 pc: 0x11081bfc
2344 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2345 >
2346 @end example
2347 @end deffn
2349 @node Debug Adapter Configuration
2350 @chapter Debug Adapter Configuration
2351 @cindex config file, interface
2352 @cindex interface config file
2354 Correctly installing OpenOCD includes making your operating system give
2355 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2356 are used to select which one is used, and to configure how it is used.
2358 @quotation Note
2359 Because OpenOCD started out with a focus purely on JTAG, you may find
2360 places where it wrongly presumes JTAG is the only transport protocol
2361 in use. Be aware that recent versions of OpenOCD are removing that
2362 limitation. JTAG remains more functional than most other transports.
2363 Other transports do not support boundary scan operations, or may be
2364 specific to a given chip vendor. Some might be usable only for
2365 programming flash memory, instead of also for debugging.
2366 @end quotation
2368 Debug Adapters/Interfaces/Dongles are normally configured
2369 through commands in an interface configuration
2370 file which is sourced by your @file{openocd.cfg} file, or
2371 through a command line @option{-f interface/....cfg} option.
2373 @example
2374 source [find interface/olimex-jtag-tiny.cfg]
2375 @end example
2377 These commands tell
2378 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2379 A few cases are so simple that you only need to say what driver to use:
2381 @example
2382 # jlink interface
2383 interface jlink
2384 @end example
2386 Most adapters need a bit more configuration than that.
2389 @section Interface Configuration
2391 The interface command tells OpenOCD what type of debug adapter you are
2392 using. Depending on the type of adapter, you may need to use one or
2393 more additional commands to further identify or configure the adapter.
2395 @deffn {Config Command} {interface} name
2396 Use the interface driver @var{name} to connect to the
2397 target.
2398 @end deffn
2400 @deffn Command {interface_list}
2401 List the debug adapter drivers that have been built into
2402 the running copy of OpenOCD.
2403 @end deffn
2404 @deffn Command {interface transports} transport_name+
2405 Specifies the transports supported by this debug adapter.
2406 The adapter driver builds-in similar knowledge; use this only
2407 when external configuration (such as jumpering) changes what
2408 the hardware can support.
2409 @end deffn
2413 @deffn Command {adapter_name}
2414 Returns the name of the debug adapter driver being used.
2415 @end deffn
2417 @section Interface Drivers
2419 Each of the interface drivers listed here must be explicitly
2420 enabled when OpenOCD is configured, in order to be made
2421 available at run time.
2423 @deffn {Interface Driver} {amt_jtagaccel}
2424 Amontec Chameleon in its JTAG Accelerator configuration,
2425 connected to a PC's EPP mode parallel port.
2426 This defines some driver-specific commands:
2428 @deffn {Config Command} {parport_port} number
2429 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2430 the number of the @file{/dev/parport} device.
2431 @end deffn
2433 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2434 Displays status of RTCK option.
2435 Optionally sets that option first.
2436 @end deffn
2437 @end deffn
2439 @deffn {Interface Driver} {arm-jtag-ew}
2440 Olimex ARM-JTAG-EW USB adapter
2441 This has one driver-specific command:
2443 @deffn Command {armjtagew_info}
2444 Logs some status
2445 @end deffn
2446 @end deffn
2448 @deffn {Interface Driver} {at91rm9200}
2449 Supports bitbanged JTAG from the local system,
2450 presuming that system is an Atmel AT91rm9200
2451 and a specific set of GPIOs is used.
2452 @c command: at91rm9200_device NAME
2453 @c chooses among list of bit configs ... only one option
2454 @end deffn
2456 @deffn {Interface Driver} {dummy}
2457 A dummy software-only driver for debugging.
2458 @end deffn
2460 @deffn {Interface Driver} {ep93xx}
2461 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2462 @end deffn
2464 @deffn {Interface Driver} {ft2232}
2465 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2467 Note that this driver has several flaws and the @command{ftdi} driver is
2468 recommended as its replacement.
2470 These interfaces have several commands, used to configure the driver
2471 before initializing the JTAG scan chain:
2473 @deffn {Config Command} {ft2232_device_desc} description
2474 Provides the USB device description (the @emph{iProduct string})
2475 of the FTDI FT2232 device. If not
2476 specified, the FTDI default value is used. This setting is only valid
2477 if compiled with FTD2XX support.
2478 @end deffn
2480 @deffn {Config Command} {ft2232_serial} serial-number
2481 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2482 in case the vendor provides unique IDs and more than one FT2232 device
2483 is connected to the host.
2484 If not specified, serial numbers are not considered.
2485 (Note that USB serial numbers can be arbitrary Unicode strings,
2486 and are not restricted to containing only decimal digits.)
2487 @end deffn
2489 @deffn {Config Command} {ft2232_layout} name
2490 Each vendor's FT2232 device can use different GPIO signals
2491 to control output-enables, reset signals, and LEDs.
2492 Currently valid layout @var{name} values include:
2493 @itemize @minus
2494 @item @b{axm0432_jtag} Axiom AXM-0432
2495 @item @b{comstick} Hitex STR9 comstick
2496 @item @b{cortino} Hitex Cortino JTAG interface
2497 @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
2498 either for the local Cortex-M3 (SRST only)
2499 or in a passthrough mode (neither SRST nor TRST)
2500 This layout can not support the SWO trace mechanism, and should be
2501 used only for older boards (before rev C).
2502 @item @b{luminary_icdi} This layout should be used with most TI/Luminary
2503 eval boards, including Rev C LM3S811 eval boards and the eponymous
2504 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2505 to debug some other target. It can support the SWO trace mechanism.
2506 @item @b{flyswatter} Tin Can Tools Flyswatter
2507 @item @b{icebear} ICEbear JTAG adapter from Section 5
2508 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2509 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2510 @item @b{m5960} American Microsystems M5960
2511 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2512 @item @b{oocdlink} OOCDLink
2513 @c oocdlink ~= jtagkey_prototype_v1
2514 @item @b{redbee-econotag} Integrated with a Redbee development board.
2515 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2516 @item @b{sheevaplug} Marvell Sheevaplug development kit
2517 @item @b{signalyzer} Xverve Signalyzer
2518 @item @b{stm32stick} Hitex STM32 Performance Stick
2519 @item @b{turtelizer2} egnite Software turtelizer2
2520 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2521 @end itemize
2522 @end deffn
2524 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2525 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2526 default values are used.
2527 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2528 @example
2529 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2530 @end example
2531 @end deffn
2533 @deffn {Config Command} {ft2232_latency} ms
2534 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2535 ft2232_read() fails to return the expected number of bytes. This can be caused by
2536 USB communication delays and has proved hard to reproduce and debug. Setting the
2537 FT2232 latency timer to a larger value increases delays for short USB packets but it
2538 also reduces the risk of timeouts before receiving the expected number of bytes.
2539 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2540 @end deffn
2542 For example, the interface config file for a
2543 Turtelizer JTAG Adapter looks something like this:
2545 @example
2546 interface ft2232
2547 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2548 ft2232_layout turtelizer2
2549 ft2232_vid_pid 0x0403 0xbdc8
2550 @end example
2551 @end deffn
2553 @deffn {Interface Driver} {ftdi}
2554 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2555 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2556 It is a complete rewrite to address a large number of problems with the ft2232
2557 interface driver.
2559 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2560 bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
2561 consistently faster than the ft2232 driver, sometimes several times faster.
2563 A major improvement of this driver is that support for new FTDI based adapters
2564 can be added competely through configuration files, without the need to patch
2565 and rebuild OpenOCD.
2567 The driver uses a signal abstraction to enable Tcl configuration files to
2568 define outputs for one or several FTDI GPIO. These outputs can then be
2569 controlled using the @command{ftdi_set_signal} command. Special signal names
2570 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2571 will be used for their customary purpose.
2573 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2574 be controlled differently. In order to support tristateable signals such as
2575 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2576 signal. The following output buffer configurations are supported:
2578 @itemize @minus
2579 @item Push-pull with one FTDI output as (non-)inverted data line
2580 @item Open drain with one FTDI output as (non-)inverted output-enable
2581 @item Tristate with one FTDI output as (non-)inverted data line and another
2582 FTDI output as (non-)inverted output-enable
2583 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2584 switching data and direction as necessary
2585 @end itemize
2587 These interfaces have several commands, used to configure the driver
2588 before initializing the JTAG scan chain:
2590 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2591 The vendor ID and product ID of the adapter. If not specified, the FTDI
2592 default values are used.
2593 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2594 @example
2595 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2596 @end example
2597 @end deffn
2599 @deffn {Config Command} {ftdi_device_desc} description
2600 Provides the USB device description (the @emph{iProduct string})
2601 of the adapter. If not specified, the device description is ignored
2602 during device selection.
2603 @end deffn
2605 @deffn {Config Command} {ftdi_serial} serial-number
2606 Specifies the @var{serial-number} of the adapter to use,
2607 in case the vendor provides unique IDs and more than one adapter
2608 is connected to the host.
2609 If not specified, serial numbers are not considered.
2610 (Note that USB serial numbers can be arbitrary Unicode strings,
2611 and are not restricted to containing only decimal digits.)
2612 @end deffn
2614 @deffn {Config Command} {ftdi_channel} channel
2615 Selects the channel of the FTDI device to use for MPSSE operations. Most
2616 adapters use the default, channel 0, but there are exceptions.
2617 @end deffn
2619 @deffn {Config Command} {ftdi_layout_init} data direction
2620 Specifies the initial values of the FTDI GPIO data and direction registers.
2621 Each value is a 16-bit number corresponding to the concatenation of the high
2622 and low FTDI GPIO registers. The values should be selected based on the
2623 schematics of the adapter, such that all signals are set to safe levels with
2624 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2625 and initially asserted reset signals.
2626 @end deffn
2628 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask]
2629 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2630 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2631 register bitmasks to tell the driver the connection and type of the output
2632 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2633 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2634 used with inverting data inputs and @option{-data} with non-inverting inputs.
2635 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2636 not-output-enable) input to the output buffer is connected.
2638 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2639 simple open-collector transistor driver would be specified with @option{-oe}
2640 only. In that case the signal can only be set to drive low or to Hi-Z and the
2641 driver will complain if the signal is set to drive high. Which means that if
2642 it's a reset signal, @command{reset_config} must be specified as
2643 @option{srst_open_drain}, not @option{srst_push_pull}.
2645 A special case is provided when @option{-data} and @option{-oe} is set to the
2646 same bitmask. Then the FTDI pin is considered being connected straight to the
2647 target without any buffer. The FTDI pin is then switched between output and
2648 input as necessary to provide the full set of low, high and Hi-Z
2649 characteristics. In all other cases, the pins specified in a signal definition
2650 are always driven by the FTDI.
2651 @end deffn
2653 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2654 Set a previously defined signal to the specified level.
2655 @itemize @minus
2656 @item @option{0}, drive low
2657 @item @option{1}, drive high
2658 @item @option{z}, set to high-impedance
2659 @end itemize
2660 @end deffn
2662 For example adapter definitions, see the configuration files shipped in the
2663 @file{interface/ftdi} directory.
2664 @end deffn
2666 @deffn {Interface Driver} {remote_bitbang}
2667 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2668 with a remote process and sends ASCII encoded bitbang requests to that process
2669 instead of directly driving JTAG.
2671 The remote_bitbang driver is useful for debugging software running on
2672 processors which are being simulated.
2674 @deffn {Config Command} {remote_bitbang_port} number
2675 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2676 sockets instead of TCP.
2677 @end deffn
2679 @deffn {Config Command} {remote_bitbang_host} hostname
2680 Specifies the hostname of the remote process to connect to using TCP, or the
2681 name of the UNIX socket to use if remote_bitbang_port is 0.
2682 @end deffn
2684 For example, to connect remotely via TCP to the host foobar you might have
2685 something like:
2687 @example
2688 interface remote_bitbang
2689 remote_bitbang_port 3335
2690 remote_bitbang_host foobar
2691 @end example
2693 To connect to another process running locally via UNIX sockets with socket
2694 named mysocket:
2696 @example
2697 interface remote_bitbang
2698 remote_bitbang_port 0
2699 remote_bitbang_host mysocket
2700 @end example
2701 @end deffn
2703 @deffn {Interface Driver} {usb_blaster}
2704 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2705 for FTDI chips. These interfaces have several commands, used to
2706 configure the driver before initializing the JTAG scan chain:
2708 @deffn {Config Command} {usb_blaster_device_desc} description
2709 Provides the USB device description (the @emph{iProduct string})
2710 of the FTDI FT245 device. If not
2711 specified, the FTDI default value is used. This setting is only valid
2712 if compiled with FTD2XX support.
2713 @end deffn
2715 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2716 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2717 default values are used.
2718 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2719 Altera USB-Blaster (default):
2720 @example
2721 usb_blaster_vid_pid 0x09FB 0x6001
2722 @end example
2723 The following VID/PID is for Kolja Waschk's USB JTAG:
2724 @example
2725 usb_blaster_vid_pid 0x16C0 0x06AD
2726 @end example
2727 @end deffn
2729 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2730 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2731 female JTAG header). These pins can be used as SRST and/or TRST provided the
2732 appropriate connections are made on the target board.
2734 For example, to use pin 6 as SRST (as with an AVR board):
2735 @example
2736 $_TARGETNAME configure -event reset-assert \
2737 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2738 @end example
2739 @end deffn
2741 @end deffn
2743 @deffn {Interface Driver} {gw16012}
2744 Gateworks GW16012 JTAG programmer.
2745 This has one driver-specific command:
2747 @deffn {Config Command} {parport_port} [port_number]
2748 Display either the address of the I/O port
2749 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2750 If a parameter is provided, first switch to use that port.
2751 This is a write-once setting.
2752 @end deffn
2753 @end deffn
2755 @deffn {Interface Driver} {jlink}
2756 Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
2758 @quotation Compatibility Note
2759 Segger released many firmware versions for the many harware versions they
2760 produced. OpenOCD was extensively tested and intended to run on all of them,
2761 but some combinations were reported as incompatible. As a general
2762 recommendation, it is advisable to use the latest firmware version
2763 available for each hardware version. However the current V8 is a moving
2764 target, and Segger firmware versions released after the OpenOCD was
2765 released may not be compatible. In such cases it is recommended to
2766 revert to the last known functional version. For 0.5.0, this is from
2767 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2768 version is from "May 3 2012 18:36:22", packed with 4.46f.
2769 @end quotation
2771 @deffn {Command} {jlink caps}
2772 Display the device firmware capabilities.
2773 @end deffn
2774 @deffn {Command} {jlink info}
2775 Display various device information, like hardware version, firmware version, current bus status.
2776 @end deffn
2777 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2778 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2779 @end deffn
2780 @deffn {Command} {jlink config}
2781 Display the J-Link configuration.
2782 @end deffn
2783 @deffn {Command} {jlink config kickstart} [val]
2784 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2785 @end deffn
2786 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2787 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2788 @end deffn
2789 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2790 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2791 E the bit of the subnet mask and
2792 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2793 @end deffn
2794 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2795 Set the USB address; this will also change the product id. Without argument, show the USB address.
2796 @end deffn
2797 @deffn {Command} {jlink config reset}
2798 Reset the current configuration.
2799 @end deffn
2800 @deffn {Command} {jlink config save}
2801 Save the current configuration to the internal persistent storage.
2802 @end deffn
2803 @deffn {Config} {jlink pid} val
2804 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2805 @end deffn
2806 @end deffn
2808 @deffn {Interface Driver} {parport}
2809 Supports PC parallel port bit-banging cables:
2810 Wigglers, PLD download cable, and more.
2811 These interfaces have several commands, used to configure the driver
2812 before initializing the JTAG scan chain:
2814 @deffn {Config Command} {parport_cable} name
2815 Set the layout of the parallel port cable used to connect to the target.
2816 This is a write-once setting.
2817 Currently valid cable @var{name} values include:
2819 @itemize @minus
2820 @item @b{altium} Altium Universal JTAG cable.
2821 @item @b{arm-jtag} Same as original wiggler except SRST and
2822 TRST connections reversed and TRST is also inverted.
2823 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2824 in configuration mode. This is only used to
2825 program the Chameleon itself, not a connected target.
2826 @item @b{dlc5} The Xilinx Parallel cable III.
2827 @item @b{flashlink} The ST Parallel cable.
2828 @item @b{lattice} Lattice ispDOWNLOAD Cable
2829 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2830 some versions of
2831 Amontec's Chameleon Programmer. The new version available from
2832 the website uses the original Wiggler layout ('@var{wiggler}')
2833 @item @b{triton} The parallel port adapter found on the
2834 ``Karo Triton 1 Development Board''.
2835 This is also the layout used by the HollyGates design
2836 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2837 @item @b{wiggler} The original Wiggler layout, also supported by
2838 several clones, such as the Olimex ARM-JTAG
2839 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2840 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2841 @end itemize
2842 @end deffn
2844 @deffn {Config Command} {parport_port} [port_number]
2845 Display either the address of the I/O port
2846 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2847 If a parameter is provided, first switch to use that port.
2848 This is a write-once setting.
2850 When using PPDEV to access the parallel port, use the number of the parallel port:
2851 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2852 you may encounter a problem.
2853 @end deffn
2855 @deffn Command {parport_toggling_time} [nanoseconds]
2856 Displays how many nanoseconds the hardware needs to toggle TCK;
2857 the parport driver uses this value to obey the
2858 @command{adapter_khz} configuration.
2859 When the optional @var{nanoseconds} parameter is given,
2860 that setting is changed before displaying the current value.
2862 The default setting should work reasonably well on commodity PC hardware.
2863 However, you may want to calibrate for your specific hardware.
2864 @quotation Tip
2865 To measure the toggling time with a logic analyzer or a digital storage
2866 oscilloscope, follow the procedure below:
2867 @example
2868 > parport_toggling_time 1000
2869 > adapter_khz 500
2870 @end example
2871 This sets the maximum JTAG clock speed of the hardware, but
2872 the actual speed probably deviates from the requested 500 kHz.
2873 Now, measure the time between the two closest spaced TCK transitions.
2874 You can use @command{runtest 1000} or something similar to generate a
2875 large set of samples.
2876 Update the setting to match your measurement:
2877 @example
2878 > parport_toggling_time <measured nanoseconds>
2879 @end example
2880 Now the clock speed will be a better match for @command{adapter_khz rate}
2881 commands given in OpenOCD scripts and event handlers.
2883 You can do something similar with many digital multimeters, but note
2884 that you'll probably need to run the clock continuously for several
2885 seconds before it decides what clock rate to show. Adjust the
2886 toggling time up or down until the measured clock rate is a good
2887 match for the adapter_khz rate you specified; be conservative.
2888 @end quotation
2889 @end deffn
2891 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2892 This will configure the parallel driver to write a known
2893 cable-specific value to the parallel interface on exiting OpenOCD.
2894 @end deffn
2896 For example, the interface configuration file for a
2897 classic ``Wiggler'' cable on LPT2 might look something like this:
2899 @example
2900 interface parport
2901 parport_port 0x278
2902 parport_cable wiggler
2903 @end example
2904 @end deffn
2906 @deffn {Interface Driver} {presto}
2907 ASIX PRESTO USB JTAG programmer.
2908 @deffn {Config Command} {presto_serial} serial_string
2909 Configures the USB serial number of the Presto device to use.
2910 @end deffn
2911 @end deffn
2913 @deffn {Interface Driver} {rlink}
2914 Raisonance RLink USB adapter
2915 @end deffn
2917 @deffn {Interface Driver} {usbprog}
2918 usbprog is a freely programmable USB adapter.
2919 @end deffn
2921 @deffn {Interface Driver} {vsllink}
2922 vsllink is part of Versaloon which is a versatile USB programmer.
2924 @quotation Note
2925 This defines quite a few driver-specific commands,
2926 which are not currently documented here.
2927 @end quotation
2928 @end deffn
2930 @deffn {Interface Driver} {hla}
2931 This is a driver that supports multiple High Level Adapters.
2932 This type of adapter does not expose some of the lower level api's
2933 that OpenOCD would normally use to access the target.
2935 Currently supported adapters include the ST STLINK and TI ICDI.
2937 @deffn {Config Command} {hla_device_desc} description
2938 Currently Not Supported.
2939 @end deffn
2941 @deffn {Config Command} {hla_serial} serial
2942 Currently Not Supported.
2943 @end deffn
2945 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
2946 Specifies the adapter layout to use.
2947 @end deffn
2949 @deffn {Config Command} {hla_vid_pid} vid pid
2950 The vendor ID and product ID of the device.
2951 @end deffn
2953 @deffn {Config Command} {stlink_api} api_level
2954 Manually sets the stlink api used, valid options are 1 or 2. (@b{STLINK Only}).
2955 @end deffn
2956 @end deffn
2958 @deffn {Interface Driver} {opendous}
2959 opendous-jtag is a freely programmable USB adapter.
2960 @end deffn
2962 @deffn {Interface Driver} {ulink}
2963 This is the Keil ULINK v1 JTAG debugger.
2964 @end deffn
2966 @deffn {Interface Driver} {ZY1000}
2967 This is the Zylin ZY1000 JTAG debugger.
2968 @end deffn
2970 @quotation Note
2971 This defines some driver-specific commands,
2972 which are not currently documented here.
2973 @end quotation
2975 @deffn Command power [@option{on}|@option{off}]
2976 Turn power switch to target on/off.
2977 No arguments: print status.
2978 @end deffn
2980 @section Transport Configuration
2981 @cindex Transport
2982 As noted earlier, depending on the version of OpenOCD you use,
2983 and the debug adapter you are using,
2984 several transports may be available to
2985 communicate with debug targets (or perhaps to program flash memory).
2986 @deffn Command {transport list}
2987 displays the names of the transports supported by this
2988 version of OpenOCD.
2989 @end deffn
2991 @deffn Command {transport select} transport_name
2992 Select which of the supported transports to use in this OpenOCD session.
2993 The transport must be supported by the debug adapter hardware and by the
2994 version of OPenOCD you are using (including the adapter's driver).
2995 No arguments: returns name of session's selected transport.
2996 @end deffn
2998 @subsection JTAG Transport
2999 @cindex JTAG
3000 JTAG is the original transport supported by OpenOCD, and most
3001 of the OpenOCD commands support it.
3002 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3003 each of which must be explicitly declared.
3004 JTAG supports both debugging and boundary scan testing.
3005 Flash programming support is built on top of debug support.
3006 @subsection SWD Transport
3007 @cindex SWD
3008 @cindex Serial Wire Debug
3009 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3010 Debug Access Point (DAP, which must be explicitly declared.
3011 (SWD uses fewer signal wires than JTAG.)
3012 SWD is debug-oriented, and does not support boundary scan testing.
3013 Flash programming support is built on top of debug support.
3014 (Some processors support both JTAG and SWD.)
3015 @deffn Command {swd newdap} ...
3016 Declares a single DAP which uses SWD transport.
3017 Parameters are currently the same as "jtag newtap" but this is
3018 expected to change.
3019 @end deffn
3020 @deffn Command {swd wcr trn prescale}
3021 Updates TRN (turnaraound delay) and prescaling.fields of the
3022 Wire Control Register (WCR).
3023 No parameters: displays current settings.
3024 @end deffn
3026 @subsection SPI Transport
3027 @cindex SPI
3028 @cindex Serial Peripheral Interface
3029 The Serial Peripheral Interface (SPI) is a general purpose transport
3030 which uses four wire signaling. Some processors use it as part of a
3031 solution for flash programming.
3033 @anchor{JTAG Speed}
3034 @section JTAG Speed
3035 JTAG clock setup is part of system setup.
3036 It @emph{does not belong with interface setup} since any interface
3037 only knows a few of the constraints for the JTAG clock speed.
3038 Sometimes the JTAG speed is
3039 changed during the target initialization process: (1) slow at
3040 reset, (2) program the CPU clocks, (3) run fast.
3041 Both the "slow" and "fast" clock rates are functions of the
3042 oscillators used, the chip, the board design, and sometimes
3043 power management software that may be active.
3045 The speed used during reset, and the scan chain verification which
3046 follows reset, can be adjusted using a @code{reset-start}
3047 target event handler.
3048 It can then be reconfigured to a faster speed by a
3049 @code{reset-init} target event handler after it reprograms those
3050 CPU clocks, or manually (if something else, such as a boot loader,
3051 sets up those clocks).
3052 @xref{Target Events}.
3053 When the initial low JTAG speed is a chip characteristic, perhaps
3054 because of a required oscillator speed, provide such a handler
3055 in the target config file.
3056 When that speed is a function of a board-specific characteristic
3057 such as which speed oscillator is used, it belongs in the board
3058 config file instead.
3059 In both cases it's safest to also set the initial JTAG clock rate
3060 to that same slow speed, so that OpenOCD never starts up using a
3061 clock speed that's faster than the scan chain can support.
3063 @example
3064 jtag_rclk 3000
3065 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3066 @end example
3068 If your system supports adaptive clocking (RTCK), configuring
3069 JTAG to use that is probably the most robust approach.
3070 However, it introduces delays to synchronize clocks; so it
3071 may not be the fastest solution.
3073 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3074 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3075 which support adaptive clocking.
3077 @deffn {Command} adapter_khz max_speed_kHz
3078 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3079 JTAG interfaces usually support a limited number of
3080 speeds. The speed actually used won't be faster
3081 than the speed specified.
3083 Chip data sheets generally include a top JTAG clock rate.
3084 The actual rate is often a function of a CPU core clock,
3085 and is normally less than that peak rate.
3086 For example, most ARM cores accept at most one sixth of the CPU clock.
3088 Speed 0 (khz) selects RTCK method.
3089 @xref{FAQ RTCK}.
3090 If your system uses RTCK, you won't need to change the
3091 JTAG clocking after setup.
3092 Not all interfaces, boards, or targets support ``rtck''.
3093 If the interface device can not
3094 support it, an error is returned when you try to use RTCK.
3095 @end deffn
3097 @defun jtag_rclk fallback_speed_kHz
3098 @cindex adaptive clocking
3099 @cindex RTCK
3100 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3101 If that fails (maybe the interface, board, or target doesn't
3102 support it), falls back to the specified frequency.
3103 @example
3104 # Fall back to 3mhz if RTCK is not supported
3105 jtag_rclk 3000
3106 @end example
3107 @end defun
3109 @node Reset Configuration
3110 @chapter Reset Configuration
3111 @cindex Reset Configuration
3113 Every system configuration may require a different reset
3114 configuration. This can also be quite confusing.
3115 Resets also interact with @var{reset-init} event handlers,
3116 which do things like setting up clocks and DRAM, and
3117 JTAG clock rates. (@xref{JTAG Speed}.)
3118 They can also interact with JTAG routers.
3119 Please see the various board files for examples.
3121 @quotation Note
3122 To maintainers and integrators:
3123 Reset configuration touches several things at once.
3124 Normally the board configuration file
3125 should define it and assume that the JTAG adapter supports
3126 everything that's wired up to the board's JTAG connector.
3128 However, the target configuration file could also make note
3129 of something the silicon vendor has done inside the chip,
3130 which will be true for most (or all) boards using that chip.
3131 And when the JTAG adapter doesn't support everything, the
3132 user configuration file will need to override parts of
3133 the reset configuration provided by other files.
3134 @end quotation
3136 @section Types of Reset
3138 There are many kinds of reset possible through JTAG, but
3139 they may not all work with a given board and adapter.
3140 That's part of why reset configuration can be error prone.
3142 @itemize @bullet
3143 @item
3144 @emph{System Reset} ... the @emph{SRST} hardware signal
3145 resets all chips connected to the JTAG adapter, such as processors,
3146 power management chips, and I/O controllers. Normally resets triggered
3147 with this signal behave exactly like pressing a RESET button.
3148 @item
3149 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3150 just the TAP controllers connected to the JTAG adapter.
3151 Such resets should not be visible to the rest of the system; resetting a
3152 device's TAP controller just puts that controller into a known state.
3153 @item
3154 @emph{Emulation Reset} ... many devices can be reset through JTAG
3155 commands. These resets are often distinguishable from system
3156 resets, either explicitly (a "reset reason" register says so)
3157 or implicitly (not all parts of the chip get reset).
3158 @item
3159 @emph{Other Resets} ... system-on-chip devices often support
3160 several other types of reset.
3161 You may need to arrange that a watchdog timer stops
3162 while debugging, preventing a watchdog reset.
3163 There may be individual module resets.
3164 @end itemize
3166 In the best case, OpenOCD can hold SRST, then reset
3167 the TAPs via TRST and send commands through JTAG to halt the
3168 CPU at the reset vector before the 1st instruction is executed.
3169 Then when it finally releases the SRST signal, the system is
3170 halted under debugger control before any code has executed.
3171 This is the behavior required to support the @command{reset halt}
3172 and @command{reset init} commands; after @command{reset init} a
3173 board-specific script might do things like setting up DRAM.
3174 (@xref{Reset Command}.)
3176 @anchor{SRST and TRST Issues}
3177 @section SRST and TRST Issues
3179 Because SRST and TRST are hardware signals, they can have a
3180 variety of system-specific constraints. Some of the most
3181 common issues are:
3183 @itemize @bullet
3185 @item @emph{Signal not available} ... Some boards don't wire
3186 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3187 support such signals even if they are wired up.
3188 Use the @command{reset_config} @var{signals} options to say
3189 when either of those signals is not connected.
3190 When SRST is not available, your code might not be able to rely
3191 on controllers having been fully reset during code startup.
3192 Missing TRST is not a problem, since JTAG-level resets can
3193 be triggered using with TMS signaling.
3195 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3196 adapter will connect SRST to TRST, instead of keeping them separate.
3197 Use the @command{reset_config} @var{combination} options to say
3198 when those signals aren't properly independent.
3200 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3201 delay circuit, reset supervisor, or on-chip features can extend
3202 the effect of a JTAG adapter's reset for some time after the adapter
3203 stops issuing the reset. For example, there may be chip or board
3204 requirements that all reset pulses last for at least a
3205 certain amount of time; and reset buttons commonly have
3206 hardware debouncing.
3207 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3208 commands to say when extra delays are needed.
3210 @item @emph{Drive type} ... Reset lines often have a pullup
3211 resistor, letting the JTAG interface treat them as open-drain
3212 signals. But that's not a requirement, so the adapter may need
3213 to use push/pull output drivers.
3214 Also, with weak pullups it may be advisable to drive
3215 signals to both levels (push/pull) to minimize rise times.
3216 Use the @command{reset_config} @var{trst_type} and
3217 @var{srst_type} parameters to say how to drive reset signals.
3219 @item @emph{Special initialization} ... Targets sometimes need
3220 special JTAG initialization sequences to handle chip-specific
3221 issues (not limited to errata).
3222 For example, certain JTAG commands might need to be issued while
3223 the system as a whole is in a reset state (SRST active)
3224 but the JTAG scan chain is usable (TRST inactive).
3225 Many systems treat combined assertion of SRST and TRST as a
3226 trigger for a harder reset than SRST alone.
3227 Such custom reset handling is discussed later in this chapter.
3228 @end itemize
3230 There can also be other issues.
3231 Some devices don't fully conform to the JTAG specifications.
3232 Trivial system-specific differences are common, such as
3233 SRST and TRST using slightly different names.
3234 There are also vendors who distribute key JTAG documentation for
3235 their chips only to developers who have signed a Non-Disclosure
3236 Agreement (NDA).
3238 Sometimes there are chip-specific extensions like a requirement to use
3239 the normally-optional TRST signal (precluding use of JTAG adapters which
3240 don't pass TRST through), or needing extra steps to complete a TAP reset.
3242 In short, SRST and especially TRST handling may be very finicky,
3243 needing to cope with both architecture and board specific constraints.
3245 @section Commands for Handling Resets
3247 @deffn {Command} adapter_nsrst_assert_width milliseconds
3248 Minimum amount of time (in milliseconds) OpenOCD should wait
3249 after asserting nSRST (active-low system reset) before
3250 allowing it to be deasserted.
3251 @end deffn
3253 @deffn {Command} adapter_nsrst_delay milliseconds
3254 How long (in milliseconds) OpenOCD should wait after deasserting
3255 nSRST (active-low system reset) before starting new JTAG operations.
3256 When a board has a reset button connected to SRST line it will
3257 probably have hardware debouncing, implying you should use this.
3258 @end deffn
3260 @deffn {Command} jtag_ntrst_assert_width milliseconds
3261 Minimum amount of time (in milliseconds) OpenOCD should wait
3262 after asserting nTRST (active-low JTAG TAP reset) before
3263 allowing it to be deasserted.
3264 @end deffn
3266 @deffn {Command} jtag_ntrst_delay milliseconds
3267 How long (in milliseconds) OpenOCD should wait after deasserting
3268 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3269 @end deffn
3271 @deffn {Command} reset_config mode_flag ...
3272 This command displays or modifies the reset configuration
3273 of your combination of JTAG board and target in target
3274 configuration scripts.
3276 Information earlier in this section describes the kind of problems
3277 the command is intended to address (@pxref{SRST and TRST Issues}).
3278 As a rule this command belongs only in board config files,
3279 describing issues like @emph{board doesn't connect TRST};
3280 or in user config files, addressing limitations derived
3281 from a particular combination of interface and board.
3282 (An unlikely example would be using a TRST-only adapter
3283 with a board that only wires up SRST.)
3285 The @var{mode_flag} options can be specified in any order, but only one
3286 of each type -- @var{signals}, @var{combination}, @var{gates},
3287 @var{trst_type}, @var{srst_type} and @var{connect_type}
3288 -- may be specified at a time.
3289 If you don't provide a new value for a given type, its previous
3290 value (perhaps the default) is unchanged.
3291 For example, this means that you don't need to say anything at all about
3292 TRST just to declare that if the JTAG adapter should want to drive SRST,
3293 it must explicitly be driven high (@option{srst_push_pull}).
3295 @itemize
3296 @item
3297 @var{signals} can specify which of the reset signals are connected.
3298 For example, If the JTAG interface provides SRST, but the board doesn't
3299 connect that signal properly, then OpenOCD can't use it.
3300 Possible values are @option{none} (the default), @option{trst_only},
3301 @option{srst_only} and @option{trst_and_srst}.
3303 @quotation Tip
3304 If your board provides SRST and/or TRST through the JTAG connector,
3305 you must declare that so those signals can be used.
3306 @end quotation
3308 @item
3309 The @var{combination} is an optional value specifying broken reset
3310 signal implementations.
3311 The default behaviour if no option given is @option{separate},
3312 indicating everything behaves normally.
3313 @option{srst_pulls_trst} states that the
3314 test logic is reset together with the reset of the system (e.g. NXP
3315 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3316 the system is reset together with the test logic (only hypothetical, I
3317 haven't seen hardware with such a bug, and can be worked around).
3318 @option{combined} implies both @option{srst_pulls_trst} and
3319 @option{trst_pulls_srst}.
3321 @item
3322 The @var{gates} tokens control flags that describe some cases where
3323 JTAG may be unvailable during reset.
3324 @option{srst_gates_jtag} (default)
3325 indicates that asserting SRST gates the
3326 JTAG clock. This means that no communication can happen on JTAG
3327 while SRST is asserted.
3328 Its converse is @option{srst_nogate}, indicating that JTAG commands
3329 can safely be issued while SRST is active.
3331 @item
3332 The @var{connect_type} tokens control flags that describe some cases where
3333 SRST is asserted while connecting to the target. @option{srst_nogate}
3334 is required to use this option.
3335 @option{connect_deassert_srst} (default)
3336 indicates that SRST will not be asserted while connecting to the target.
3337 Its converse is @option{connect_assert_srst}, indicating that SRST will
3338 be asserted before any target connection.
3339 Only some targets support this feature, STM32 and STR9 are examples.
3340 This feature is useful if you are unable to connect to your target due
3341 to incorrect options byte config or illegal program execution.
3342 @end itemize
3344 The optional @var{trst_type} and @var{srst_type} parameters allow the
3345 driver mode of each reset line to be specified. These values only affect
3346 JTAG interfaces with support for different driver modes, like the Amontec
3347 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3348 relevant signal (TRST or SRST) is not connected.
3350 @itemize
3351 @item
3352 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3353 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3354 Most boards connect this signal to a pulldown, so the JTAG TAPs
3355 never leave reset unless they are hooked up to a JTAG adapter.
3357 @item
3358 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3359 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3360 Most boards connect this signal to a pullup, and allow the
3361 signal to be pulled low by various events including system
3362 powerup and pressing a reset button.
3363 @end itemize
3364 @end deffn
3366 @section Custom Reset Handling
3367 @cindex events
3369 OpenOCD has several ways to help support the various reset
3370 mechanisms provided by chip and board vendors.
3371 The commands shown in the previous section give standard parameters.
3372 There are also @emph{event handlers} associated with TAPs or Targets.
3373 Those handlers are Tcl procedures you can provide, which are invoked
3374 at particular points in the reset sequence.
3376 @emph{When SRST is not an option} you must set
3377 up a @code{reset-assert} event handler for your target.
3378 For example, some JTAG adapters don't include the SRST signal;
3379 and some boards have multiple targets, and you won't always
3380 want to reset everything at once.
3382 After configuring those mechanisms, you might still
3383 find your board doesn't start up or reset correctly.
3384 For example, maybe it needs a slightly different sequence
3385 of SRST and/or TRST manipulations, because of quirks that
3386 the @command{reset_config} mechanism doesn't address;
3387 or asserting both might trigger a stronger reset, which
3388 needs special attention.
3390 Experiment with lower level operations, such as @command{jtag_reset}
3391 and the @command{jtag arp_*} operations shown here,
3392 to find a sequence of operations that works.
3393 @xref{JTAG Commands}.
3394 When you find a working sequence, it can be used to override
3395 @command{jtag_init}, which fires during OpenOCD startup
3396 (@pxref{Configuration Stage});
3397 or @command{init_reset}, which fires during reset processing.
3399 You might also want to provide some project-specific reset
3400 schemes. For example, on a multi-target board the standard
3401 @command{reset} command would reset all targets, but you
3402 may need the ability to reset only one target at time and
3403 thus want to avoid using the board-wide SRST signal.
3405 @deffn {Overridable Procedure} init_reset mode
3406 This is invoked near the beginning of the @command{reset} command,
3407 usually to provide as much of a cold (power-up) reset as practical.
3408 By default it is also invoked from @command{jtag_init} if
3409 the scan chain does not respond to pure JTAG operations.
3410 The @var{mode} parameter is the parameter given to the
3411 low level reset command (@option{halt},
3412 @option{init}, or @option{run}), @option{setup},
3413 or potentially some other value.
3415 The default implementation just invokes @command{jtag arp_init-reset}.
3416 Replacements will normally build on low level JTAG
3417 operations such as @command{jtag_reset}.
3418 Operations here must not address individual TAPs
3419 (or their associated targets)
3420 until the JTAG scan chain has first been verified to work.
3422 Implementations must have verified the JTAG scan chain before
3423 they return.
3424 This is done by calling @command{jtag arp_init}
3425 (or @command{jtag arp_init-reset}).
3426 @end deffn
3428 @deffn Command {jtag arp_init}
3429 This validates the scan chain using just the four
3430 standard JTAG signals (TMS, TCK, TDI, TDO).
3431 It starts by issuing a JTAG-only reset.
3432 Then it performs checks to verify that the scan chain configuration
3433 matches the TAPs it can observe.
3434 Those checks include checking IDCODE values for each active TAP,
3435 and verifying the length of their instruction registers using
3436 TAP @code{-ircapture} and @code{-irmask} values.
3437 If these tests all pass, TAP @code{setup} events are
3438 issued to all TAPs with handlers for that event.
3439 @end deffn
3441 @deffn Command {jtag arp_init-reset}
3442 This uses TRST and SRST to try resetting
3443 everything on the JTAG scan chain
3444 (and anything else connected to SRST).
3445 It then invokes the logic of @command{jtag arp_init}.
3446 @end deffn
3449 @node TAP Declaration
3450 @chapter TAP Declaration
3451 @cindex TAP declaration
3452 @cindex TAP configuration
3454 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3455 TAPs serve many roles, including:
3457 @itemize @bullet
3458 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
3459 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
3460 Others do it indirectly, making a CPU do it.
3461 @item @b{Program Download} Using the same CPU support GDB uses,
3462 you can initialize a DRAM controller, download code to DRAM, and then
3463 start running that code.
3464 @item @b{Boundary Scan} Most chips support boundary scan, which
3465 helps test for board assembly problems like solder bridges
3466 and missing connections
3467 @end itemize
3469 OpenOCD must know about the active TAPs on your board(s).
3470 Setting up the TAPs is the core task of your configuration files.
3471 Once those TAPs are set up, you can pass their names to code
3472 which sets up CPUs and exports them as GDB targets,
3473 probes flash memory, performs low-level JTAG operations, and more.
3475 @section Scan Chains
3476 @cindex scan chain
3478 TAPs are part of a hardware @dfn{scan chain},
3479 which is daisy chain of TAPs.
3480 They also need to be added to
3481 OpenOCD's software mirror of that hardware list,
3482 giving each member a name and associating other data with it.
3483 Simple scan chains, with a single TAP, are common in
3484 systems with a single microcontroller or microprocessor.
3485 More complex chips may have several TAPs internally.
3486 Very complex scan chains might have a dozen or more TAPs:
3487 several in one chip, more in the next, and connecting
3488 to other boards with their own chips and TAPs.
3490 You can display the list with the @command{scan_chain} command.
3491 (Don't confuse this with the list displayed by the @command{targets}
3492 command, presented in the next chapter.
3493 That only displays TAPs for CPUs which are configured as
3494 debugging targets.)
3495 Here's what the scan chain might look like for a chip more than one TAP:
3497 @verbatim
3498 TapName Enabled IdCode Expected IrLen IrCap IrMask
3499 -- ------------------ ------- ---------- ---------- ----- ----- ------
3500 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3501 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3502 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3503 @end verbatim
3505 OpenOCD can detect some of that information, but not all
3506 of it. @xref{Autoprobing}.
3507 Unfortunately those TAPs can't always be autoconfigured,
3508 because not all devices provide good support for that.
3509 JTAG doesn't require supporting IDCODE instructions, and
3510 chips with JTAG routers may not link TAPs into the chain
3511 until they are told to do so.
3513 The configuration mechanism currently supported by OpenOCD
3514 requires explicit configuration of all TAP devices using
3515 @command{jtag newtap} commands, as detailed later in this chapter.
3516 A command like this would declare one tap and name it @code{chip1.cpu}:
3518 @example
3519 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3520 @end example
3522 Each target configuration file lists the TAPs provided
3523 by a given chip.
3524 Board configuration files combine all the targets on a board,
3525 and so forth.
3526 Note that @emph{the order in which TAPs are declared is very important.}
3527 It must match the order in the JTAG scan chain, both inside
3528 a single chip and between them.
3529 @xref{FAQ TAP Order}.
3531 For example, the ST Microsystems STR912 chip has
3532 three separate TAPs@footnote{See the ST
3533 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3534 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3535 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3536 To configure those taps, @file{target/str912.cfg}
3537 includes commands something like this:
3539 @example
3540 jtag newtap str912 flash ... params ...
3541 jtag newtap str912 cpu ... params ...
3542 jtag newtap str912 bs ... params ...
3543 @end example
3545 Actual config files use a variable instead of literals like
3546 @option{str912}, to support more than one chip of each type.
3547 @xref{Config File Guidelines}.
3549 @deffn Command {jtag names}
3550 Returns the names of all current TAPs in the scan chain.
3551 Use @command{jtag cget} or @command{jtag tapisenabled}
3552 to examine attributes and state of each TAP.
3553 @example
3554 foreach t [jtag names] @{
3555 puts [format "TAP: %s\n" $t]
3556 @}
3557 @end example
3558 @end deffn
3560 @deffn Command {scan_chain}
3561 Displays the TAPs in the scan chain configuration,
3562 and their status.
3563 The set of TAPs listed by this command is fixed by
3564 exiting the OpenOCD configuration stage,
3565 but systems with a JTAG router can
3566 enable or disable TAPs dynamically.
3567 @end deffn
3569 @c FIXME! "jtag cget" should be able to return all TAP
3570 @c attributes, like "$target_name cget" does for targets.
3572 @c Probably want "jtag eventlist", and a "tap-reset" event
3573 @c (on entry to RESET state).
3575 @section TAP Names
3576 @cindex dotted name
3578 When TAP objects are declared with @command{jtag newtap},
3579 a @dfn{dotted.name} is created for the TAP, combining the
3580 name of a module (usually a chip) and a label for the TAP.
3581 For example: @code{xilinx.tap}, @code{str912.flash},
3582 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3583 Many other commands use that dotted.name to manipulate or
3584 refer to the TAP. For example, CPU configuration uses the
3585 name, as does declaration of NAND or NOR flash banks.
3587 The components of a dotted name should follow ``C'' symbol
3588 name rules: start with an alphabetic character, then numbers
3589 and underscores are OK; while others (including dots!) are not.
3591 @quotation Tip
3592 In older code, JTAG TAPs were numbered from 0..N.
3593 This feature is still present.
3594 However its use is highly discouraged, and
3595 should not be relied on; it will be removed by mid-2010.
3596 Update all of your scripts to use TAP names rather than numbers,
3597 by paying attention to the runtime warnings they trigger.
3598 Using TAP numbers in target configuration scripts prevents
3599 reusing those scripts on boards with multiple targets.
3600 @end quotation
3602 @section TAP Declaration Commands
3604 @c shouldn't this be(come) a {Config Command}?
3605 @anchor{jtag newtap}
3606 @deffn Command {jtag newtap} chipname tapname configparams...
3607 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3608 and configured according to the various @var{configparams}.
3610 The @var{chipname} is a symbolic name for the chip.
3611 Conventionally target config files use @code{$_CHIPNAME},
3612 defaulting to the model name given by the chip vendor but
3613 overridable.
3615 @cindex TAP naming convention
3616 The @var{tapname} reflects the role of that TAP,
3617 and should follow this convention:
3619 @itemize @bullet
3620 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3621 @item @code{cpu} -- The main CPU of the chip, alternatively
3622 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3623 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3624 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3625 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3626 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3627 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3628 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3629 with a single TAP;
3630 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3631 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3632 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3633 a JTAG TAP; that TAP should be named @code{sdma}.
3634 @end itemize
3636 Every TAP requires at least the following @var{configparams}:
3638 @itemize @bullet
3639 @item @code{-irlen} @var{NUMBER}
3640 @*The length in bits of the
3641 instruction register, such as 4 or 5 bits.
3642 @end itemize
3644 A TAP may also provide optional @var{configparams}:
3646 @itemize @bullet
3647 @item @code{-disable} (or @code{-enable})
3648 @*Use the @code{-disable} parameter to flag a TAP which is not
3649 linked in to the scan chain after a reset using either TRST
3650 or the JTAG state machine's @sc{reset} state.
3651 You may use @code{-enable} to highlight the default state
3652 (the TAP is linked in).
3653 @xref{Enabling and Disabling TAPs}.
3654 @item @code{-expected-id} @var{number}
3655 @*A non-zero @var{number} represents a 32-bit IDCODE
3656 which you expect to find when the scan chain is examined.
3657 These codes are not required by all JTAG devices.
3658 @emph{Repeat the option} as many times as required if more than one
3659 ID code could appear (for example, multiple versions).
3660 Specify @var{number} as zero to suppress warnings about IDCODE
3661 values that were found but not included in the list.
3663 Provide this value if at all possible, since it lets OpenOCD
3664 tell when the scan chain it sees isn't right. These values
3665 are provided in vendors' chip documentation, usually a technical
3666 reference manual. Sometimes you may need to probe the JTAG
3667 hardware to find these values.
3668 @xref{Autoprobing}.
3669 @item @code{-ignore-version}
3670 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3671 option. When vendors put out multiple versions of a chip, or use the same
3672 JTAG-level ID for several largely-compatible chips, it may be more practical
3673 to ignore the version field than to update config files to handle all of
3674 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3675 @item @code{-ircapture} @var{NUMBER}
3676 @*The bit pattern loaded by the TAP into the JTAG shift register
3677 on entry to the @sc{ircapture} state, such as 0x01.
3678 JTAG requires the two LSBs of this value to be 01.
3679 By default, @code{-ircapture} and @code{-irmask} are set
3680 up to verify that two-bit value. You may provide
3681 additional bits, if you know them, or indicate that
3682 a TAP doesn't conform to the JTAG specification.
3683 @item @code{-irmask} @var{NUMBER}
3684 @*A mask used with @code{-ircapture}
3685 to verify that instruction scans work correctly.
3686 Such scans are not used by OpenOCD except to verify that
3687 there seems to be no problems with JTAG scan chain operations.
3688 @end itemize
3689 @end deffn
3691 @section Other TAP commands
3693 @deffn Command {jtag cget} dotted.name @option{-event} name
3694 @deffnx Command {jtag configure} dotted.name @option{-event} name string
3695 At this writing this TAP attribute
3696 mechanism is used only for event handling.
3697 (It is not a direct analogue of the @code{cget}/@code{configure}
3698 mechanism for debugger targets.)
3699 See the next section for information about the available events.
3701 The @code{configure} subcommand assigns an event handler,
3702 a TCL string which is evaluated when the event is triggered.
3703 The @code{cget} subcommand returns that handler.
3704 @end deffn
3706 @anchor{TAP Events}
3707 @section TAP Events
3708 @cindex events
3709 @cindex TAP events
3711 OpenOCD includes two event mechanisms.
3712 The one presented here applies to all JTAG TAPs.
3713 The other applies to debugger targets,
3714 which are associated with certain TAPs.
3716 The TAP events currently defined are:
3718 @itemize @bullet
3719 @item @b{post-reset}
3720 @* The TAP has just completed a JTAG reset.
3721 The tap may still be in the JTAG @sc{reset} state.
3722 Handlers for these events might perform initialization sequences
3723 such as issuing TCK cycles, TMS sequences to ensure
3724 exit from the ARM SWD mode, and more.
3726 Because the scan chain has not yet been verified, handlers for these events
3727 @emph{should not issue commands which scan the JTAG IR or DR registers}
3728 of any particular target.
3729 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3730 @item @b{setup}
3731 @* The scan chain has been reset and verified.
3732 This handler may enable TAPs as needed.
3733 @item @b{tap-disable}
3734 @* The TAP needs to be disabled. This handler should
3735 implement @command{jtag tapdisable}
3736 by issuing the relevant JTAG commands.
3737 @item @b{tap-enable}
3738 @* The TAP needs to be enabled. This handler should
3739 implement @command{jtag tapenable}
3740 by issuing the relevant JTAG commands.
3741 @end itemize
3743 If you need some action after each JTAG reset, which isn't actually
3744 specific to any TAP (since you can't yet trust the scan chain's
3745 contents to be accurate), you might:
3747 @example
3748 jtag configure CHIP.jrc -event post-reset @{
3749 echo "JTAG Reset done"
3750 ... non-scan jtag operations to be done after reset
3751 @}
3752 @end example
3755 @anchor{Enabling and Disabling TAPs}
3756 @section Enabling and Disabling TAPs
3757 @cindex JTAG Route Controller
3758 @cindex jrc
3760 In some systems, a @dfn{JTAG Route Controller} (JRC)
3761 is used to enable and/or disable specific JTAG TAPs.
3762 Many ARM based chips from Texas Instruments include
3763 an ``ICEpick'' module, which is a JRC.
3764 Such chips include DaVinci and OMAP3 processors.
3766 A given TAP may not be visible until the JRC has been
3767 told to link it into the scan chain; and if the JRC
3768 has been told to unlink that TAP, it will no longer
3769 be visible.
3770 Such routers address problems that JTAG ``bypass mode''
3771 ignores, such as:
3773 @itemize
3774 @item The scan chain can only go as fast as its slowest TAP.
3775 @item Having many TAPs slows instruction scans, since all
3776 TAPs receive new instructions.
3777 @item TAPs in the scan chain must be powered up, which wastes
3778 power and prevents debugging some power management mechanisms.
3779 @end itemize
3781 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3782 as implied by the existence of JTAG routers.
3783 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3784 does include a kind of JTAG router functionality.
3786 @c (a) currently the event handlers don't seem to be able to
3787 @c fail in a way that could lead to no-change-of-state.
3789 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3790 shown below, and is implemented using TAP event handlers.
3791 So for example, when defining a TAP for a CPU connected to
3792 a JTAG router, your @file{target.cfg} file
3793 should define TAP event handlers using
3794 code that looks something like this:
3796 @example
3797 jtag configure CHIP.cpu -event tap-enable @{
3798 ... jtag operations using CHIP.jrc
3799 @}
3800 jtag configure CHIP.cpu -event tap-disable @{
3801 ... jtag operations using CHIP.jrc
3802 @}
3803 @end example
3805 Then you might want that CPU's TAP enabled almost all the time:
3807 @example
3808 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3809 @end example
3811 Note how that particular setup event handler declaration
3812 uses quotes to evaluate @code{$CHIP} when the event is configured.
3813 Using brackets @{ @} would cause it to be evaluated later,
3814 at runtime, when it might have a different value.
3816 @deffn Command {jtag tapdisable} dotted.name
3817 If necessary, disables the tap
3818 by sending it a @option{tap-disable} event.
3819 Returns the string "1" if the tap
3820 specified by @var{dotted.name} is enabled,
3821 and "0" if it is disabled.
3822 @end deffn
3824 @deffn Command {jtag tapenable} dotted.name
3825 If necessary, enables the tap
3826 by sending it a @option{tap-enable} event.
3827 Returns the string "1" if the tap
3828 specified by @var{dotted.name} is enabled,
3829 and "0" if it is disabled.
3830 @end deffn
3832 @deffn Command {jtag tapisenabled} dotted.name
3833 Returns the string "1" if the tap
3834 specified by @var{dotted.name} is enabled,
3835 and "0" if it is disabled.
3837 @quotation Note
3838 Humans will find the @command{scan_chain} command more helpful
3839 for querying the state of the JTAG taps.
3840 @end quotation
3841 @end deffn
3843 @anchor{Autoprobing}
3844 @section Autoprobing
3845 @cindex autoprobe
3846 @cindex JTAG autoprobe
3848 TAP configuration is the first thing that needs to be done
3849 after interface and reset configuration. Sometimes it's
3850 hard finding out what TAPs exist, or how they are identified.
3851 Vendor documentation is not always easy to find and use.
3853 To help you get past such problems, OpenOCD has a limited
3854 @emph{autoprobing} ability to look at the scan chain, doing
3855 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3856 To use this mechanism, start the OpenOCD server with only data
3857 that configures your JTAG interface, and arranges to come up
3858 with a slow clock (many devices don't support fast JTAG clocks
3859 right when they come out of reset).
3861 For example, your @file{openocd.cfg} file might have:
3863 @example
3864 source [find interface/olimex-arm-usb-tiny-h.cfg]
3865 reset_config trst_and_srst
3866 jtag_rclk 8
3867 @end example
3869 When you start the server without any TAPs configured, it will
3870 attempt to autoconfigure the TAPs. There are two parts to this:
3872 @enumerate
3873 @item @emph{TAP discovery} ...
3874 After a JTAG reset (sometimes a system reset may be needed too),
3875 each TAP's data registers will hold the contents of either the
3876 IDCODE or BYPASS register.
3877 If JTAG communication is working, OpenOCD will see each TAP,
3878 and report what @option{-expected-id} to use with it.
3879 @item @emph{IR Length discovery} ...
3880 Unfortunately JTAG does not provide a reliable way to find out
3881 the value of the @option{-irlen} parameter to use with a TAP
3882 that is discovered.
3883 If OpenOCD can discover the length of a TAP's instruction
3884 register, it will report it.
3885 Otherwise you may need to consult vendor documentation, such
3886 as chip data sheets or BSDL files.
3887 @end enumerate
3889 In many cases your board will have a simple scan chain with just
3890 a single device. Here's what OpenOCD reported with one board
3891 that's a bit more complex:
3893 @example
3894 clock speed 8 kHz
3895 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3896 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3897 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3898 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3899 AUTO auto0.tap - use "... -irlen 4"
3900 AUTO auto1.tap - use "... -irlen 4"
3901 AUTO auto2.tap - use "... -irlen 6"
3902 no gdb ports allocated as no target has been specified
3903 @end example
3905 Given that information, you should be able to either find some existing
3906 config files to use, or create your own. If you create your own, you
3907 would configure from the bottom up: first a @file{target.cfg} file
3908 with these TAPs, any targets associated with them, and any on-chip
3909 resources; then a @file{board.cfg} with off-chip resources, clocking,
3910 and so forth.
3912 @node CPU Configuration
3913 @chapter CPU Configuration
3914 @cindex GDB target
3916 This chapter discusses how to set up GDB debug targets for CPUs.
3917 You can also access these targets without GDB
3918 (@pxref{Architecture and Core Commands},
3919 and @ref{Target State handling}) and
3920 through various kinds of NAND and NOR flash commands.
3921 If you have multiple CPUs you can have multiple such targets.
3923 We'll start by looking at how to examine the targets you have,
3924 then look at how to add one more target and how to configure it.
3926 @section Target List
3927 @cindex target, current
3928 @cindex target, list
3930 All targets that have been set up are part of a list,
3931 where each member has a name.
3932 That name should normally be the same as the TAP name.
3933 You can display the list with the @command{targets}
3934 (plural!) command.
3935 This display often has only one CPU; here's what it might
3936 look like with more than one:
3937 @verbatim
3938 TargetName Type Endian TapName State
3939 -- ------------------ ---------- ------ ------------------ ------------
3940 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
3941 1 MyTarget cortex_m3 little mychip.foo tap-disabled
3942 @end verbatim
3944 One member of that list is the @dfn{current target}, which
3945 is implicitly referenced by many commands.
3946 It's the one marked with a @code{*} near the target name.
3947 In particular, memory addresses often refer to the address
3948 space seen by that current target.
3949 Commands like @command{mdw} (memory display words)
3950 and @command{flash erase_address} (erase NOR flash blocks)
3951 are examples; and there are many more.
3953 Several commands let you examine the list of targets:
3955 @deffn Command {target count}
3956 @emph{Note: target numbers are deprecated; don't use them.
3957 They will be removed shortly after August 2010, including this command.
3958 Iterate target using @command{target names}, not by counting.}
3960 Returns the number of targets, @math{N}.
3961 The highest numbered target is @math{N - 1}.
3962 @example
3963 set c [target count]
3964 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
3965 # Assuming you have created this function
3966 print_target_details $x
3967 @}
3968 @end example
3969 @end deffn
3971 @deffn Command {target current}
3972 Returns the name of the current target.
3973 @end deffn
3975 @deffn Command {target names}
3976 Lists the names of all current targets in the list.
3977 @example
3978 foreach t [target names] @{
3979 puts [format "Target: %s\n" $t]
3980 @}
3981 @end example
3982 @end deffn
3984 @deffn Command {target number} number
3985 @emph{Note: target numbers are deprecated; don't use them.
3986 They will be removed shortly after August 2010, including this command.}
3988 The list of targets is numbered starting at zero.
3989 This command returns the name of the target at index @var{number}.
3990 @example
3991 set thename [target number $x]
3992 puts [format "Target %d is: %s\n" $x $thename]
3993 @end example
3994 @end deffn
3996 @c yep, "target list" would have been better.
3997 @c plus maybe "target setdefault".
3999 @deffn Command targets [name]
4000 @emph{Note: the name of this command is plural. Other target
4001 command names are singular.}
4003 With no parameter, this command displays a table of all known
4004 targets in a user friendly form.
4006 With a parameter, this command sets the current target to
4007 the given target with the given @var{name}; this is
4008 only relevant on boards which have more than one target.
4009 @end deffn
4011 @section Target CPU Types and Variants
4012 @cindex target type
4013 @cindex CPU type
4014 @cindex CPU variant
4016 Each target has a @dfn{CPU type}, as shown in the output of
4017 the @command{targets} command. You need to specify that type
4018 when calling @command{target create}.
4019 The CPU type indicates more than just the instruction set.
4020 It also indicates how that instruction set is implemented,
4021 what kind of debug support it integrates,
4022 whether it has an MMU (and if so, what kind),
4023 what core-specific commands may be available
4024 (@pxref{Architecture and Core Commands}),
4025 and more.
4027 For some CPU types, OpenOCD also defines @dfn{variants} which
4028 indicate differences that affect their handling.
4029 For example, a particular implementation bug might need to be
4030 worked around in some chip versions.
4032 It's easy to see what target types are supported,
4033 since there's a command to list them.
4034 However, there is currently no way to list what target variants
4035 are supported (other than by reading the OpenOCD source code).
4037 @anchor{target types}
4038 @deffn Command {target types}
4039 Lists all supported target types.
4040 At this writing, the supported CPU types and variants are:
4042 @itemize @bullet
4043 @item @code{arm11} -- this is a generation of ARMv6 cores
4044 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4045 @item @code{arm7tdmi} -- this is an ARMv4 core
4046 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4047 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4048 @item @code{arm966e} -- this is an ARMv5 core
4049 @item @code{arm9tdmi} -- this is an ARMv4 core
4050 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4051 (Support for this is preliminary and incomplete.)
4052 @item @code{cortex_a8} -- this is an ARMv7 core with an MMU
4053 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
4054 compact Thumb2 instruction set.
4055 @item @code{dragonite} -- resembles arm966e
4056 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4057 (Support for this is still incomplete.)
4058 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4059 @item @code{feroceon} -- resembles arm926
4060 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
4061 @item @code{xscale} -- this is actually an architecture,
4062 not a CPU type. It is based on the ARMv5 architecture.
4063 There are several variants defined:
4064 @itemize @minus
4065 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
4066 @code{pxa27x} ... instruction register length is 7 bits
4067 @item @code{pxa250}, @code{pxa255},
4068 @code{pxa26x} ... instruction register length is 5 bits
4069 @item @code{pxa3xx} ... instruction register length is 11 bits
4070 @end itemize
4071 @end itemize
4072 @end deffn
4074 To avoid being confused by the variety of ARM based cores, remember
4075 this key point: @emph{ARM is a technology licencing company}.
4076 (See: @url{http://www.arm.com}.)
4077 The CPU name used by OpenOCD will reflect the CPU design that was
4078 licenced, not a vendor brand which incorporates that design.
4079 Name prefixes like arm7, arm9, arm11, and cortex
4080 reflect design generations;
4081 while names like ARMv4, ARMv5, ARMv6, and ARMv7
4082 reflect an architecture version implemented by a CPU design.
4084 @anchor{Target Configuration}
4085 @section Target Configuration
4087 Before creating a ``target'', you must have added its TAP to the scan chain.
4088 When you've added that TAP, you will have a @code{dotted.name}
4089 which is used to set up the CPU support.
4090 The chip-specific configuration file will normally configure its CPU(s)
4091 right after it adds all of the chip's TAPs to the scan chain.
4093 Although you can set up a target in one step, it's often clearer if you
4094 use shorter commands and do it in two steps: create it, then configure
4095 optional parts.
4096 All operations on the target after it's created will use a new
4097 command, created as part of target creation.
4099 The two main things to configure after target creation are
4100 a work area, which usually has target-specific defaults even
4101 if the board setup code overrides them later;
4102 and event handlers (@pxref{Target Events}), which tend
4103 to be much more board-specific.
4104 The key steps you use might look something like this
4106 @example
4107 target create MyTarget cortex_m3 -chain-position mychip.cpu
4108 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4109 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4110 $MyTarget configure -event reset-init @{ myboard_reinit @}
4111 @end example
4113 You should specify a working area if you can; typically it uses some
4114 on-chip SRAM.
4115 Such a working area can speed up many things, including bulk
4116 writes to target memory;
4117 flash operations like checking to see if memory needs to be erased;
4118 GDB memory checksumming;
4119 and more.
4121 @quotation Warning
4122 On more complex chips, the work area can become
4123 inaccessible when application code
4124 (such as an operating system)
4125 enables or disables the MMU.
4126 For example, the particular MMU context used to acess the virtual
4127 address will probably matter ... and that context might not have
4128 easy access to other addresses needed.
4129 At this writing, OpenOCD doesn't have much MMU intelligence.
4130 @end quotation
4132 It's often very useful to define a @code{reset-init} event handler.
4133 For systems that are normally used with a boot loader,
4134 common tasks include updating clocks and initializing memory
4135 controllers.
4136 That may be needed to let you write the boot loader into flash,
4137 in order to ``de-brick'' your board; or to load programs into
4138 external DDR memory without having run the boot loader.
4140 @deffn Command {target create} target_name type configparams...
4141 This command creates a GDB debug target that refers to a specific JTAG tap.
4142 It enters that target into a list, and creates a new
4143 command (@command{@var{target_name}}) which is used for various
4144 purposes including additional configuration.
4146 @itemize @bullet
4147 @item @var{target_name} ... is the name of the debug target.
4148 By convention this should be the same as the @emph{dotted.name}
4149 of the TAP associated with this target, which must be specified here
4150 using the @code{-chain-position @var{dotted.name}} configparam.
4152 This name is also used to create the target object command,
4153 referred to here as @command{$target_name},
4154 and in other places the target needs to be identified.
4155 @item @var{type} ... specifies the target type. @xref{target types}.
4156 @item @var{configparams} ... all parameters accepted by
4157 @command{$target_name configure} are permitted.
4158 If the target is big-endian, set it here with @code{-endian big}.
4159 If the variant matters, set it here with @code{-variant}.
4161 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
4162 @end itemize
4163 @end deffn
4165 @deffn Command {$target_name configure} configparams...
4166 The options accepted by this command may also be
4167 specified as parameters to @command{target create}.
4168 Their values can later be queried one at a time by
4169 using the @command{$target_name cget} command.
4171 @emph{Warning:} changing some of these after setup is dangerous.
4172 For example, moving a target from one TAP to another;
4173 and changing its endianness or variant.
4175 @itemize @bullet
4177 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4178 used to access this target.
4180 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4181 whether the CPU uses big or little endian conventions
4183 @item @code{-event} @var{event_name} @var{event_body} --
4184 @xref{Target Events}.
4185 Note that this updates a list of named event handlers.
4186 Calling this twice with two different event names assigns
4187 two different handlers, but calling it twice with the
4188 same event name assigns only one handler.
4190 @item @code{-variant} @var{name} -- specifies a variant of the target,
4191 which OpenOCD needs to know about.
4193 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4194 whether the work area gets backed up; by default,
4195 @emph{it is not backed up.}
4196 When possible, use a working_area that doesn't need to be backed up,
4197 since performing a backup slows down operations.
4198 For example, the beginning of an SRAM block is likely to
4199 be used by most build systems, but the end is often unused.
4201 @item @code{-work-area-size} @var{size} -- specify work are size,
4202 in bytes. The same size applies regardless of whether its physical
4203 or virtual address is being used.
4205 @item @code{-work-area-phys} @var{address} -- set the work area
4206 base @var{address} to be used when no MMU is active.
4208 @item @code{-work-area-virt} @var{address} -- set the work area
4209 base @var{address} to be used when an MMU is active.
4210 @emph{Do not specify a value for this except on targets with an MMU.}
4211 The value should normally correspond to a static mapping for the
4212 @code{-work-area-phys} address, set up by the current operating system.
4214 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4215 @var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}|
4216 @option{FreeRTOS}|@option{linux}|@option{ChibiOS}.
4218 @end itemize
4219 @end deffn
4221 @section Other $target_name Commands
4222 @cindex object command
4224 The Tcl/Tk language has the concept of object commands,
4225 and OpenOCD adopts that same model for targets.
4227 A good Tk example is a on screen button.
4228 Once a button is created a button
4229 has a name (a path in Tk terms) and that name is useable as a first
4230 class command. For example in Tk, one can create a button and later
4231 configure it like this:
4233 @example
4234 # Create
4235 button .foobar -background red -command @{ foo @}
4236 # Modify
4237 .foobar configure -foreground blue
4238 # Query
4239 set x [.foobar cget -background]
4240 # Report
4241 puts [format "The button is %s" $x]
4242 @end example
4244 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4245 button, and its object commands are invoked the same way.
4247 @example
4248 str912.cpu mww 0x1234 0x42
4249 omap3530.cpu mww 0x5555 123
4250 @end example
4252 The commands supported by OpenOCD target objects are:
4254 @deffn Command {$target_name arp_examine}
4255 @deffnx Command {$target_name arp_halt}
4256 @deffnx Command {$target_name arp_poll}
4257 @deffnx Command {$target_name arp_reset}
4258 @deffnx Command {$target_name arp_waitstate}
4259 Internal OpenOCD scripts (most notably @file{startup.tcl})
4260 use these to deal with specific reset cases.
4261 They are not otherwise documented here.
4262 @end deffn
4264 @deffn Command {$target_name array2mem} arrayname width address count
4265 @deffnx Command {$target_name mem2array} arrayname width address count
4266 These provide an efficient script-oriented interface to memory.
4267 The @code{array2mem} primitive writes bytes, halfwords, or words;
4268 while @code{mem2array} reads them.
4269 In both cases, the TCL side uses an array, and
4270 the target side uses raw memory.
4272 The efficiency comes from enabling the use of
4273 bulk JTAG data transfer operations.
4274 The script orientation comes from working with data
4275 values that are packaged for use by TCL scripts;
4276 @command{mdw} type primitives only print data they retrieve,
4277 and neither store nor return those values.
4279 @itemize
4280 @item @var{arrayname} ... is the name of an array variable
4281 @item @var{width} ... is 8/16/32 - indicating the memory access size
4282 @item @var{address} ... is the target memory address
4283 @item @var{count} ... is the number of elements to process
4284 @end itemize
4285 @end deffn
4287 @deffn Command {$target_name cget} queryparm
4288 Each configuration parameter accepted by
4289 @command{$target_name configure}
4290 can be individually queried, to return its current value.
4291 The @var{queryparm} is a parameter name
4292 accepted by that command, such as @code{-work-area-phys}.
4293 There are a few special cases:
4295 @itemize @bullet
4296 @item @code{-event} @var{event_name} -- returns the handler for the
4297 event named @var{event_name}.
4298 This is a special case because setting a handler requires
4299 two parameters.
4300 @item @code{-type} -- returns the target type.
4301 This is a special case because this is set using
4302 @command{target create} and can't be changed
4303 using @command{$target_name configure}.
4304 @end itemize
4306 For example, if you wanted to summarize information about
4307 all the targets you might use something like this:
4309 @example
4310 foreach name [target names] @{
4311 set y [$name cget -endian]
4312 set z [$name cget -type]
4313 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4314 $x $name $y $z]
4315 @}
4316 @end example
4317 @end deffn
4319 @anchor{target curstate}
4320 @deffn Command {$target_name curstate}
4321 Displays the current target state:
4322 @code{debug-running},
4323 @code{halted},
4324 @code{reset},
4325 @code{running}, or @code{unknown}.
4326 (Also, @pxref{Event Polling}.)
4327 @end deffn
4329 @deffn Command {$target_name eventlist}
4330 Displays a table listing all event handlers
4331 currently associated with this target.
4332 @xref{Target Events}.
4333 @end deffn
4335 @deffn Command {$target_name invoke-event} event_name
4336 Invokes the handler for the event named @var{event_name}.
4337 (This is primarily intended for use by OpenOCD framework
4338 code, for example by the reset code in @file{startup.tcl}.)
4339 @end deffn
4341 @deffn Command {$target_name mdw} addr [count]
4342 @deffnx Command {$target_name mdh} addr [count]
4343 @deffnx Command {$target_name mdb} addr [count]
4344 Display contents of address @var{addr}, as
4345 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4346 or 8-bit bytes (@command{mdb}).
4347 If @var{count} is specified, displays that many units.
4348 (If you want to manipulate the data instead of displaying it,
4349 see the @code{mem2array} primitives.)
4350 @end deffn
4352 @deffn Command {$target_name mww} addr word
4353 @deffnx Command {$target_name mwh} addr halfword
4354 @deffnx Command {$target_name mwb} addr byte
4355 Writes the specified @var{word} (32 bits),
4356 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4357 at the specified address @var{addr}.
4358 @end deffn
4360 @anchor{Target Events}
4361 @section Target Events
4362 @cindex target events
4363 @cindex events
4364 At various times, certain things can happen, or you want them to happen.
4365 For example:
4366 @itemize @bullet
4367 @item What should happen when GDB connects? Should your target reset?
4368 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4369 @item Is using SRST appropriate (and possible) on your system?
4370 Or instead of that, do you need to issue JTAG commands to trigger reset?
4371 SRST usually resets everything on the scan chain, which can be inappropriate.
4372 @item During reset, do you need to write to certain memory locations
4373 to set up system clocks or
4374 to reconfigure the SDRAM?
4375 How about configuring the watchdog timer, or other peripherals,
4376 to stop running while you hold the core stopped for debugging?
4377 @end itemize
4379 All of the above items can be addressed by target event handlers.
4380 These are set up by @command{$target_name configure -event} or
4381 @command{target create ... -event}.
4383 The programmer's model matches the @code{-command} option used in Tcl/Tk
4384 buttons and events. The two examples below act the same, but one creates
4385 and invokes a small procedure while the other inlines it.
4387 @example
4388 proc my_attach_proc @{ @} @{
4389 echo "Reset..."
4390 reset halt
4391 @}
4392 mychip.cpu configure -event gdb-attach my_attach_proc
4393 mychip.cpu configure -event gdb-attach @{
4394 echo "Reset..."
4395 # To make flash probe and gdb load to flash work we need a reset init.
4396 reset init
4397 @}
4398 @end example
4400 The following target events are defined:
4402 @itemize @bullet
4403 @item @b{debug-halted}
4404 @* The target has halted for debug reasons (i.e.: breakpoint)
4405 @item @b{debug-resumed}
4406 @* The target has resumed (i.e.: gdb said run)
4407 @item @b{early-halted}
4408 @* Occurs early in the halt process
4409 @item @b{examine-start}
4410 @* Before target examine is called.
4411 @item @b{examine-end}
4412 @* After target examine is called with no errors.
4413 @item @b{gdb-attach}
4414 @* When GDB connects. This is before any communication with the target, so this
4415 can be used to set up the target so it is possible to probe flash. Probing flash
4416 is necessary during gdb connect if gdb load is to write the image to flash. Another
4417 use of the flash memory map is for GDB to automatically hardware/software breakpoints
4418 depending on whether the breakpoint is in RAM or read only memory.
4419 @item @b{gdb-detach}
4420 @* When GDB disconnects
4421 @item @b{gdb-end}
4422 @* When the target has halted and GDB is not doing anything (see early halt)
4423 @item @b{gdb-flash-erase-start}
4424 @* Before the GDB flash process tries to erase the flash
4425 @item @b{gdb-flash-erase-end}
4426 @* After the GDB flash process has finished erasing the flash
4427 @item @b{gdb-flash-write-start}
4428 @* Before GDB writes to the flash
4429 @item @b{gdb-flash-write-end}
4430 @* After GDB writes to the flash
4431 @item @b{gdb-start}
4432 @* Before the target steps, gdb is trying to start/resume the target
4433 @item @b{halted}
4434 @* The target has halted
4435 @item @b{reset-assert-pre}
4436 @* Issued as part of @command{reset} processing
4437 after @command{reset_init} was triggered
4438 but before either SRST alone is re-asserted on the scan chain,
4439 or @code{reset-assert} is triggered.
4440 @item @b{reset-assert}
4441 @* Issued as part of @command{reset} processing
4442 after @command{reset-assert-pre} was triggered.
4443 When such a handler is present, cores which support this event will use
4444 it instead of asserting SRST.
4445 This support is essential for debugging with JTAG interfaces which
4446 don't include an SRST line (JTAG doesn't require SRST), and for
4447 selective reset on scan chains that have multiple targets.
4448 @item @b{reset-assert-post}
4449 @* Issued as part of @command{reset} processing
4450 after @code{reset-assert} has been triggered.
4451 or the target asserted SRST on the entire scan chain.
4452 @item @b{reset-deassert-pre}
4453 @* Issued as part of @command{reset} processing
4454 after @code{reset-assert-post} has been triggered.
4455 @item @b{reset-deassert-post}
4456 @* Issued as part of @command{reset} processing
4457 after @code{reset-deassert-pre} has been triggered
4458 and (if the target is using it) after SRST has been
4459 released on the scan chain.
4460 @item @b{reset-end}
4461 @* Issued as the final step in @command{reset} processing.
4462 @ignore
4463 @item @b{reset-halt-post}
4464 @* Currently not used
4465 @item @b{reset-halt-pre}
4466 @* Currently not used
4467 @end ignore
4468 @item @b{reset-init}
4469 @* Used by @b{reset init} command for board-specific initialization.
4470 This event fires after @emph{reset-deassert-post}.
4472 This is where you would configure PLLs and clocking, set up DRAM so
4473 you can download programs that don't fit in on-chip SRAM, set up pin
4474 multiplexing, and so on.
4475 (You may be able to switch to a fast JTAG clock rate here, after
4476 the target clocks are fully set up.)
4477 @item @b{reset-start}
4478 @* Issued as part of @command{reset} processing
4479 before @command{reset_init} is called.
4481 This is the most robust place to use @command{jtag_rclk}
4482 or @command{adapter_khz} to switch to a low JTAG clock rate,
4483 when reset disables PLLs needed to use a fast clock.
4484 @ignore
4485 @item @b{reset-wait-pos}
4486 @* Currently not used
4487 @item @b{reset-wait-pre}
4488 @* Currently not used
4489 @end ignore
4490 @item @b{resume-start}
4491 @* Before any target is resumed
4492 @item @b{resume-end}
4493 @* After all targets have resumed
4494 @item @b{resumed}
4495 @* Target has resumed
4496 @end itemize
4498 @node Flash Commands
4499 @chapter Flash Commands
4501 OpenOCD has different commands for NOR and NAND flash;
4502 the ``flash'' command works with NOR flash, while
4503 the ``nand'' command works with NAND flash.
4504 This partially reflects different hardware technologies:
4505 NOR flash usually supports direct CPU instruction and data bus access,
4506 while data from a NAND flash must be copied to memory before it can be
4507 used. (SPI flash must also be copied to memory before use.)
4508 However, the documentation also uses ``flash'' as a generic term;
4509 for example, ``Put flash configuration in board-specific files''.
4511 Flash Steps:
4512 @enumerate
4513 @item Configure via the command @command{flash bank}
4514 @* Do this in a board-specific configuration file,
4515 passing parameters as needed by the driver.
4516 @item Operate on the flash via @command{flash subcommand}
4517 @* Often commands to manipulate the flash are typed by a human, or run
4518 via a script in some automated way. Common tasks include writing a
4519 boot loader, operating system, or other data.
4520 @item GDB Flashing
4521 @* Flashing via GDB requires the flash be configured via ``flash
4522 bank'', and the GDB flash features be enabled.
4523 @xref{GDB Configuration}.
4524 @end enumerate
4526 Many CPUs have the ablity to ``boot'' from the first flash bank.
4527 This means that misprogramming that bank can ``brick'' a system,
4528 so that it can't boot.
4529 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4530 board by (re)installing working boot firmware.
4532 @anchor{NOR Configuration}
4533 @section Flash Configuration Commands
4534 @cindex flash configuration
4536 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4537 Configures a flash bank which provides persistent storage
4538 for addresses from @math{base} to @math{base + size - 1}.
4539 These banks will often be visible to GDB through the target's memory map.
4540 In some cases, configuring a flash bank will activate extra commands;
4541 see the driver-specific documentation.
4543 @itemize @bullet
4544 @item @var{name} ... may be used to reference the flash bank
4545 in other flash commands. A number is also available.
4546 @item @var{driver} ... identifies the controller driver
4547 associated with the flash bank being declared.
4548 This is usually @code{cfi} for external flash, or else
4549 the name of a microcontroller with embedded flash memory.
4550 @xref{Flash Driver List}.
4551 @item @var{base} ... Base address of the flash chip.
4552 @item @var{size} ... Size of the chip, in bytes.
4553 For some drivers, this value is detected from the hardware.
4554 @item @var{chip_width} ... Width of the flash chip, in bytes;
4555 ignored for most microcontroller drivers.
4556 @item @var{bus_width} ... Width of the data bus used to access the
4557 chip, in bytes; ignored for most microcontroller drivers.
4558 @item @var{target} ... Names the target used to issue
4559 commands to the flash controller.
4560 @comment Actually, it's currently a controller-specific parameter...
4561 @item @var{driver_options} ... drivers may support, or require,
4562 additional parameters. See the driver-specific documentation
4563 for more information.
4564 @end itemize
4565 @quotation Note
4566 This command is not available after OpenOCD initialization has completed.
4567 Use it in board specific configuration files, not interactively.
4568 @end quotation
4569 @end deffn
4571 @comment the REAL name for this command is "ocd_flash_banks"
4572 @comment less confusing would be: "flash list" (like "nand list")
4573 @deffn Command {flash banks}
4574 Prints a one-line summary of each device that was
4575 declared using @command{flash bank}, numbered from zero.
4576 Note that this is the @emph{plural} form;
4577 the @emph{singular} form is a very different command.
4578 @end deffn
4580 @deffn Command {flash list}
4581 Retrieves a list of associative arrays for each device that was
4582 declared using @command{flash bank}, numbered from zero.
4583 This returned list can be manipulated easily from within scripts.
4584 @end deffn
4586 @deffn Command {flash probe} num
4587 Identify the flash, or validate the parameters of the configured flash. Operation
4588 depends on the flash type.
4589 The @var{num} parameter is a value shown by @command{flash banks}.
4590 Most flash commands will implicitly @emph{autoprobe} the bank;
4591 flash drivers can distinguish between probing and autoprobing,
4592 but most don't bother.
4593 @end deffn
4595 @section Erasing, Reading, Writing to Flash
4596 @cindex flash erasing
4597 @cindex flash reading
4598 @cindex flash writing
4599 @cindex flash programming
4600 @anchor{Flash Programming Commands}
4602 One feature distinguishing NOR flash from NAND or serial flash technologies
4603 is that for read access, it acts exactly like any other addressible memory.
4604 This means you can use normal memory read commands like @command{mdw} or
4605 @command{dump_image} with it, with no special @command{flash} subcommands.
4606 @xref{Memory access}, and @ref{Image access}.
4608 Write access works differently. Flash memory normally needs to be erased
4609 before it's written. Erasing a sector turns all of its bits to ones, and
4610 writing can turn ones into zeroes. This is why there are special commands
4611 for interactive erasing and writing, and why GDB needs to know which parts
4612 of the address space hold NOR flash memory.
4614 @quotation Note
4615 Most of these erase and write commands leverage the fact that NOR flash
4616 chips consume target address space. They implicitly refer to the current
4617 JTAG target, and map from an address in that target's address space
4618 back to a flash bank.
4619 @comment In May 2009, those mappings may fail if any bank associated
4620 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
4621 A few commands use abstract addressing based on bank and sector numbers,
4622 and don't depend on searching the current target and its address space.
4623 Avoid confusing the two command models.
4624 @end quotation
4626 Some flash chips implement software protection against accidental writes,
4627 since such buggy writes could in some cases ``brick'' a system.
4628 For such systems, erasing and writing may require sector protection to be
4629 disabled first.
4630 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4631 and AT91SAM7 on-chip flash.
4632 @xref{flash protect}.
4634 @anchor{flash erase_sector}
4635 @deffn Command {flash erase_sector} num first last
4636 Erase sectors in bank @var{num}, starting at sector @var{first}
4637 up to and including @var{last}.
4638 Sector numbering starts at 0.
4639 Providing a @var{last} sector of @option{last}
4640 specifies "to the end of the flash bank".
4641 The @var{num} parameter is a value shown by @command{flash banks}.
4642 @end deffn
4644 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4645 Erase sectors starting at @var{address} for @var{length} bytes.
4646 Unless @option{pad} is specified, @math{address} must begin a
4647 flash sector, and @math{address + length - 1} must end a sector.
4648 Specifying @option{pad} erases extra data at the beginning and/or
4649 end of the specified region, as needed to erase only full sectors.
4650 The flash bank to use is inferred from the @var{address}, and
4651 the specified length must stay within that bank.
4652 As a special case, when @var{length} is zero and @var{address} is
4653 the start of the bank, the whole flash is erased.
4654 If @option{unlock} is specified, then the flash is unprotected
4655 before erase starts.
4656 @end deffn
4658 @deffn Command {flash fillw} address word length
4659 @deffnx Command {flash fillh} address halfword length
4660 @deffnx Command {flash fillb} address byte length
4661 Fills flash memory with the specified @var{word} (32 bits),
4662 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4663 starting at @var{address} and continuing
4664 for @var{length} units (word/halfword/byte).
4665 No erasure is done before writing; when needed, that must be done
4666 before issuing this command.
4667 Writes are done in blocks of up to 1024 bytes, and each write is
4668 verified by reading back the data and comparing it to what was written.
4669 The flash bank to use is inferred from the @var{address} of
4670 each block, and the specified length must stay within that bank.
4671 @end deffn
4672 @comment no current checks for errors if fill blocks touch multiple banks!
4674 @anchor{flash write_bank}
4675 @deffn Command {flash write_bank} num filename offset
4676 Write the binary @file{filename} to flash bank @var{num},
4677 starting at @var{offset} bytes from the beginning of the bank.
4678 The @var{num} parameter is a value shown by @command{flash banks}.
4679 @end deffn
4681 @anchor{flash write_image}
4682 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4683 Write the image @file{filename} to the current target's flash bank(s).
4684 A relocation @var{offset} may be specified, in which case it is added
4685 to the base address for each section in the image.
4686 The file [@var{type}] can be specified
4687 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4688 @option{elf} (ELF file), @option{s19} (Motorola s19).
4689 @option{mem}, or @option{builder}.
4690 The relevant flash sectors will be erased prior to programming
4691 if the @option{erase} parameter is given. If @option{unlock} is
4692 provided, then the flash banks are unlocked before erase and
4693 program. The flash bank to use is inferred from the address of
4694 each image section.
4696 @quotation Warning
4697 Be careful using the @option{erase} flag when the flash is holding
4698 data you want to preserve.
4699 Portions of the flash outside those described in the image's
4700 sections might be erased with no notice.
4701 @itemize
4702 @item
4703 When a section of the image being written does not fill out all the
4704 sectors it uses, the unwritten parts of those sectors are necessarily
4705 also erased, because sectors can't be partially erased.
4706 @item
4707 Data stored in sector "holes" between image sections are also affected.
4708 For example, "@command{flash write_image erase ...}" of an image with
4709 one byte at the beginning of a flash bank and one byte at the end
4710 erases the entire bank -- not just the two sectors being written.
4711 @end itemize
4712 Also, when flash protection is important, you must re-apply it after
4713 it has been removed by the @option{unlock} flag.
4714 @end quotation
4716 @end deffn
4718 @section Other Flash commands
4719 @cindex flash protection
4721 @deffn Command {flash erase_check} num
4722 Check erase state of sectors in flash bank @var{num},
4723 and display that status.
4724 The @var{num} parameter is a value shown by @command{flash banks}.
4725 @end deffn
4727 @deffn Command {flash info} num
4728 Print info about flash bank @var{num}
4729 The @var{num} parameter is a value shown by @command{flash banks}.
4730 This command will first query the hardware, it does not print cached
4731 and possibly stale information.
4732 @end deffn
4734 @anchor{flash protect}
4735 @deffn Command {flash protect} num first last (@option{on}|@option{off})
4736 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
4737 in flash bank @var{num}, starting at sector @var{first}
4738 and continuing up to and including @var{last}.
4739 Providing a @var{last} sector of @option{last}
4740 specifies "to the end of the flash bank".
4741 The @var{num} parameter is a value shown by @command{flash banks}.
4742 @end deffn
4744 @anchor{program}
4745 @deffn Command {program} filename [verify] [reset] [offset]
4746 This is a helper script that simplifies using OpenOCD as a standalone
4747 programmer. The only required parameter is @option{filename}, the others are optional.
4748 @xref{Flash Programming}.
4749 @end deffn
4751 @anchor{Flash Driver List}
4752 @section Flash Driver List
4753 As noted above, the @command{flash bank} command requires a driver name,
4754 and allows driver-specific options and behaviors.
4755 Some drivers also activate driver-specific commands.
4757 @subsection External Flash
4759 @deffn {Flash Driver} cfi
4760 @cindex Common Flash Interface
4761 @cindex CFI
4762 The ``Common Flash Interface'' (CFI) is the main standard for
4763 external NOR flash chips, each of which connects to a
4764 specific external chip select on the CPU.
4765 Frequently the first such chip is used to boot the system.
4766 Your board's @code{reset-init} handler might need to
4767 configure additional chip selects using other commands (like: @command{mww} to
4768 configure a bus and its timings), or
4769 perhaps configure a GPIO pin that controls the ``write protect'' pin
4770 on the flash chip.
4771 The CFI driver can use a target-specific working area to significantly
4772 speed up operation.
4774 The CFI driver can accept the following optional parameters, in any order:
4776 @itemize
4777 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
4778 like AM29LV010 and similar types.
4779 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
4780 @end itemize
4782 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
4783 wide on a sixteen bit bus:
4785 @example
4786 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
4787 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
4788 @end example
4790 To configure one bank of 32 MBytes
4791 built from two sixteen bit (two byte) wide parts wired in parallel
4792 to create a thirty-two bit (four byte) bus with doubled throughput:
4794 @example
4795 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
4796 @end example
4798 @c "cfi part_id" disabled
4799 @end deffn
4801 @deffn {Flash Driver} lpcspifi
4802 @cindex NXP SPI Flash Interface
4803 @cindex SPIFI
4804 @cindex lpcspifi
4805 NXP's LPC43xx and LPC18xx families include a proprietary SPI
4806 Flash Interface (SPIFI) peripheral that can drive and provide
4807 memory mapped access to external SPI flash devices.
4809 The lpcspifi driver initializes this interface and provides
4810 program and erase functionality for these serial flash devices.
4811 Use of this driver @b{requires} a working area of at least 1kB
4812 to be configured on the target device; more than this will
4813 significantly reduce flash programming times.
4815 The setup command only requires the @var{base} parameter. All
4816 other parameters are ignored, and the flash size and layout
4817 are configured by the driver.
4819 @example
4820 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
4821 @end example
4823 @end deffn
4825 @deffn {Flash Driver} stmsmi
4826 @cindex STMicroelectronics Serial Memory Interface
4827 @cindex SMI
4828 @cindex stmsmi
4829 Some devices form STMicroelectronics (e.g. STR75x MCU family,
4830 SPEAr MPU family) include a proprietary
4831 ``Serial Memory Interface'' (SMI) controller able to drive external
4832 SPI flash devices.
4833 Depending on specific device and board configuration, up to 4 external
4834 flash devices can be connected.
4836 SMI makes the flash content directly accessible in the CPU address
4837 space; each external device is mapped in a memory bank.
4838 CPU can directly read data, execute code and boot from SMI banks.
4839 Normal OpenOCD commands like @command{mdw} can be used to display
4840 the flash content.
4842 The setup command only requires the @var{base} parameter in order
4843 to identify the memory bank.
4844 All other parameters are ignored. Additional information, like
4845 flash size, are detected automatically.
4847 @example
4848 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
4849 @end example
4851 @end deffn
4853 @subsection Internal Flash (Microcontrollers)
4855 @deffn {Flash Driver} aduc702x
4856 The ADUC702x analog microcontrollers from Analog Devices
4857 include internal flash and use ARM7TDMI cores.
4858 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
4859 The setup command only requires the @var{target} argument
4860 since all devices in this family have the same memory layout.
4862 @example
4863 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
4864 @end example
4865 @end deffn
4867 @anchor{at91sam3}
4868 @deffn {Flash Driver} at91sam3
4869 @cindex at91sam3
4870 All members of the AT91SAM3 microcontroller family from
4871 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
4872 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
4873 that the driver was orginaly developed and tested using the
4874 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
4875 the family was cribbed from the data sheet. @emph{Note to future
4876 readers/updaters: Please remove this worrysome comment after other
4877 chips are confirmed.}
4879 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
4880 have one flash bank. In all cases the flash banks are at
4881 the following fixed locations:
4883 @example
4884 # Flash bank 0 - all chips
4885 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
4886 # Flash bank 1 - only 256K chips
4887 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
4888 @end example
4890 Internally, the AT91SAM3 flash memory is organized as follows.
4891 Unlike the AT91SAM7 chips, these are not used as parameters
4892 to the @command{flash bank} command:
4894 @itemize
4895 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
4896 @item @emph{Bank Size:} 128K/64K Per flash bank
4897 @item @emph{Sectors:} 16 or 8 per bank
4898 @item @emph{SectorSize:} 8K Per Sector
4899 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
4900 @end itemize
4902 The AT91SAM3 driver adds some additional commands:
4904 @deffn Command {at91sam3 gpnvm}
4905 @deffnx Command {at91sam3 gpnvm clear} number
4906 @deffnx Command {at91sam3 gpnvm set} number
4907 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
4908 With no parameters, @command{show} or @command{show all},
4909 shows the status of all GPNVM bits.
4910 With @command{show} @var{number}, displays that bit.
4912 With @command{set} @var{number} or @command{clear} @var{number},
4913 modifies that GPNVM bit.
4914 @end deffn
4916 @deffn Command {at91sam3 info}
4917 This command attempts to display information about the AT91SAM3
4918 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
4919 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
4920 document id: doc6430A] and decodes the values. @emph{Second} it reads the
4921 various clock configuration registers and attempts to display how it
4922 believes the chip is configured. By default, the SLOWCLK is assumed to
4923 be 32768 Hz, see the command @command{at91sam3 slowclk}.
4924 @end deffn
4926 @deffn Command {at91sam3 slowclk} [value]
4927 This command shows/sets the slow clock frequency used in the
4928 @command{at91sam3 info} command calculations above.
4929 @end deffn
4930 @end deffn
4932 @deffn {Flash Driver} at91sam4
4933 @cindex at91sam4
4934 All members of the AT91SAM4 microcontroller family from
4935 Atmel include internal flash and use ARM's Cortex-M4 core.
4936 This driver uses the same cmd names/syntax as @xref{at91sam3}.
4937 @end deffn
4939 @deffn {Flash Driver} at91sam7
4940 All members of the AT91SAM7 microcontroller family from Atmel include
4941 internal flash and use ARM7TDMI cores. The driver automatically
4942 recognizes a number of these chips using the chip identification
4943 register, and autoconfigures itself.
4945 @example
4946 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
4947 @end example
4949 For chips which are not recognized by the controller driver, you must
4950 provide additional parameters in the following order:
4952 @itemize
4953 @item @var{chip_model} ... label used with @command{flash info}
4954 @item @var{banks}
4955 @item @var{sectors_per_bank}
4956 @item @var{pages_per_sector}
4957 @item @var{pages_size}
4958 @item @var{num_nvm_bits}
4959 @item @var{freq_khz} ... required if an external clock is provided,
4960 optional (but recommended) when the oscillator frequency is known
4961 @end itemize
4963 It is recommended that you provide zeroes for all of those values
4964 except the clock frequency, so that everything except that frequency
4965 will be autoconfigured.
4966 Knowing the frequency helps ensure correct timings for flash access.
4968 The flash controller handles erases automatically on a page (128/256 byte)
4969 basis, so explicit erase commands are not necessary for flash programming.
4970 However, there is an ``EraseAll`` command that can erase an entire flash
4971 plane (of up to 256KB), and it will be used automatically when you issue
4972 @command{flash erase_sector} or @command{flash erase_address} commands.
4974 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
4975 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
4976 bit for the processor. Each processor has a number of such bits,
4977 used for controlling features such as brownout detection (so they
4978 are not truly general purpose).
4979 @quotation Note
4980 This assumes that the first flash bank (number 0) is associated with
4981 the appropriate at91sam7 target.
4982 @end quotation
4983 @end deffn
4984 @end deffn
4986 @deffn {Flash Driver} avr
4987 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
4988 @emph{The current implementation is incomplete.}
4989 @comment - defines mass_erase ... pointless given flash_erase_address
4990 @end deffn
4992 @deffn {Flash Driver} efm32
4993 All members of the EFM32 microcontroller family from Energy Micro include
4994 internal flash and use ARM Cortex M3 cores. The driver automatically recognizes
4995 a number of these chips using the chip identification register, and
4996 autoconfigures itself.
4997 @example
4998 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
4999 @end example
5000 @emph{The current implementation is incomplete. Unprotecting flash pages is not
5001 supported.}
5002 @end deffn
5004 @deffn {Flash Driver} lpc2000
5005 Most members of the LPC1700 and LPC2000 microcontroller families from NXP
5006 include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
5008 @quotation Note
5009 There are LPC2000 devices which are not supported by the @var{lpc2000}
5010 driver:
5011 The LPC2888 is supported by the @var{lpc288x} driver.
5012 The LPC29xx family is supported by the @var{lpc2900} driver.
5013 @end quotation
5015 The @var{lpc2000} driver defines two mandatory and one optional parameters,
5016 which must appear in the following order:
5018 @itemize
5019 @item @var{variant} ... required, may be
5020 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
5021 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
5022 or @option{lpc1700} (LPC175x and LPC176x)
5023 @item @var{clock_kHz} ... the frequency, in kiloHertz,
5024 at which the core is running
5025 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
5026 telling the driver to calculate a valid checksum for the exception vector table.
5027 @quotation Note
5028 If you don't provide @option{calc_checksum} when you're writing the vector
5029 table, the boot ROM will almost certainly ignore your flash image.
5030 However, if you do provide it,
5031 with most tool chains @command{verify_image} will fail.
5032 @end quotation
5033 @end itemize
5035 LPC flashes don't require the chip and bus width to be specified.
5037 @example
5038 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
5039 lpc2000_v2 14765 calc_checksum
5040 @end example
5042 @deffn {Command} {lpc2000 part_id} bank
5043 Displays the four byte part identifier associated with
5044 the specified flash @var{bank}.
5045 @end deffn
5046 @end deffn
5048 @deffn {Flash Driver} lpc288x
5049 The LPC2888 microcontroller from NXP needs slightly different flash
5050 support from its lpc2000 siblings.
5051 The @var{lpc288x} driver defines one mandatory parameter,
5052 the programming clock rate in Hz.
5053 LPC flashes don't require the chip and bus width to be specified.
5055 @example
5056 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
5057 @end example
5058 @end deffn
5060 @deffn {Flash Driver} lpc2900
5061 This driver supports the LPC29xx ARM968E based microcontroller family
5062 from NXP.
5064 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
5065 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
5066 sector layout are auto-configured by the driver.
5067 The driver has one additional mandatory parameter: The CPU clock rate
5068 (in kHz) at the time the flash operations will take place. Most of the time this
5069 will not be the crystal frequency, but a higher PLL frequency. The
5070 @code{reset-init} event handler in the board script is usually the place where