[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * TFTP:: TFTP
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
94 @end menu
96 @node About
97 @unnumbered About
98 @cindex about
100 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
101 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
104 around the world.
106 @section What is OpenOCD?
107 @cindex TAP
108 @cindex JTAG
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
112 devices.
114 It does so with the assistance of a @dfn{debug adapter}, which is
115 a small hardware module which helps provide the right kind of
116 electrical signaling to the target being debugged. These are
117 required since the debug host (on which OpenOCD runs) won't
118 usually have native support for such signaling, or the connector
119 needed to hook up to the target.
121 Such debug adapters support one or more @dfn{transport} protocols,
122 each of which involves different electrical signaling (and uses
123 different messaging protocols on top of that signaling). There
124 are many types of debug adapter, and little uniformity in what
125 they are called. (There are also product naming differences.)
127 These adapters are sometimes packaged as discrete dongles, which
128 may generically be called @dfn{hardware interface dongles}.
129 Some development boards also integrate them directly, which may
130 let the development board can be directly connected to the debug
131 host over USB (and sometimes also to power it over USB).
133 For example, a @dfn{JTAG Adapter} supports JTAG
134 signaling, and is used to communicate
135 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
136 A @dfn{TAP} is a ``Test Access Port'', a module which processes
137 special instructions and data. TAPs are daisy-chained within and
138 between chips and boards. JTAG supports debugging and boundary
139 scan operations.
141 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
142 signaling to communicate with some newer ARM cores, as well as debug
143 adapters which support both JTAG and SWD transports. SWD only supports
144 debugging, whereas JTAG also supports boundary scan operations.
146 For some chips, there are also @dfn{Programming Adapters} supporting
147 special transports used only to write code to flash memory, without
148 support for on-chip debugging or boundary scan.
149 (At this writing, OpenOCD does not support such non-debug adapters.)
152 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
153 based, parallel port based, and other standalone boxes that run
154 OpenOCD internally. @xref{Debug Adapter Hardware}.
156 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
157 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
158 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
159 debugged via the GDB protocol.
161 @b{Flash Programing:} Flash writing is supported for external CFI
162 compatible NOR flashes (Intel and AMD/Spansion command set) and several
163 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
164 STM32x). Preliminary support for various NAND flash controllers
165 (LPC3180, Orion, S3C24xx, more) controller is included.
167 @section OpenOCD Web Site
169 The OpenOCD web site provides the latest public news from the community:
171 @uref{http://openocd.sourceforge.net/}
173 @section Latest User's Guide:
175 The user's guide you are now reading may not be the latest one
176 available. A version for more recent code may be available.
177 Its HTML form is published irregularly at:
179 @uref{http://openocd.sourceforge.net/doc/html/index.html}
181 PDF form is likewise published at:
183 @uref{http://openocd.sourceforge.net/doc/pdf/openocd.pdf}
185 @section OpenOCD User's Forum
187 There is an OpenOCD forum (phpBB) hosted by SparkFun,
188 which might be helpful to you. Note that if you want
189 anything to come to the attention of developers, you
190 should post it to the OpenOCD Developer Mailing List
191 instead of this forum.
193 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @node Developers
197 @chapter OpenOCD Developer Resources
198 @cindex developers
200 If you are interested in improving the state of OpenOCD's debugging and
201 testing support, new contributions will be welcome. Motivated developers
202 can produce new target, flash or interface drivers, improve the
203 documentation, as well as more conventional bug fixes and enhancements.
205 The resources in this chapter are available for developers wishing to explore
206 or expand the OpenOCD source code.
208 @section OpenOCD GIT Repository
210 During the 0.3.x release cycle, OpenOCD switched from Subversion to
211 a GIT repository hosted at SourceForge. The repository URL is:
213 @uref{git://openocd.git.sourceforge.net/gitroot/openocd/openocd}
215 You may prefer to use a mirror and the HTTP protocol:
217 @uref{http://repo.or.cz/r/openocd.git}
219 With standard GIT tools, use @command{git clone} to initialize
220 a local repository, and @command{git pull} to update it.
221 There are also gitweb pages letting you browse the repository
222 with a web browser, or download arbitrary snapshots without
223 needing a GIT client:
225 @uref{http://openocd.git.sourceforge.net/git/gitweb.cgi?p=openocd/openocd}
227 @uref{http://repo.or.cz/w/openocd.git}
229 The @file{README} file contains the instructions for building the project
230 from the repository or a snapshot.
232 Developers that want to contribute patches to the OpenOCD system are
233 @b{strongly} encouraged to work against mainline.
234 Patches created against older versions may require additional
235 work from their submitter in order to be updated for newer releases.
237 @section Doxygen Developer Manual
239 During the 0.2.x release cycle, the OpenOCD project began
240 providing a Doxygen reference manual. This document contains more
241 technical information about the software internals, development
242 processes, and similar documentation:
244 @uref{http://openocd.sourceforge.net/doc/doxygen/html/index.html}
246 This document is a work-in-progress, but contributions would be welcome
247 to fill in the gaps. All of the source files are provided in-tree,
248 listed in the Doxyfile configuration in the top of the source tree.
250 @section OpenOCD Developer Mailing List
252 The OpenOCD Developer Mailing List provides the primary means of
253 communication between developers:
255 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
257 Discuss and submit patches to this list.
258 The @file{HACKING} file contains basic information about how
259 to prepare patches.
261 @section OpenOCD Bug Database
263 During the 0.4.x release cycle the OpenOCD project team began
264 using Trac for its bug database:
266 @uref{https://sourceforge.net/apps/trac/openocd}
269 @node Debug Adapter Hardware
270 @chapter Debug Adapter Hardware
271 @cindex dongles
272 @cindex FTDI
273 @cindex wiggler
274 @cindex zy1000
275 @cindex printer port
276 @cindex USB Adapter
277 @cindex RTCK
279 Defined: @b{dongle}: A small device that plugins into a computer and serves as
280 an adapter .... [snip]
282 In the OpenOCD case, this generally refers to @b{a small adapter} that
283 attaches to your computer via USB or the Parallel Printer Port. One
284 exception is the Zylin ZY1000, packaged as a small box you attach via
285 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
286 require any drivers to be installed on the developer PC. It also has
287 a built in web interface. It supports RTCK/RCLK or adaptive clocking
288 and has a built in relay to power cycle targets remotely.
291 @section Choosing a Dongle
293 There are several things you should keep in mind when choosing a dongle.
295 @enumerate
296 @item @b{Transport} Does it support the kind of communication that you need?
297 OpenOCD focusses mostly on JTAG. Your version may also support
298 other ways to communicate with target devices.
299 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
300 Does your dongle support it? You might need a level converter.
301 @item @b{Pinout} What pinout does your target board use?
302 Does your dongle support it? You may be able to use jumper
303 wires, or an "octopus" connector, to convert pinouts.
304 @item @b{Connection} Does your computer have the USB, printer, or
305 Ethernet port needed?
306 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
307 RTCK support? Also known as ``adaptive clocking''
308 @end enumerate
310 @section Stand alone Systems
312 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/33-zylin-zy1000-jtag-probe} Technically, not a
313 dongle, but a standalone box. The ZY1000 has the advantage that it does
314 not require any drivers installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built in relay to power cycle targets remotely.
318 @section USB FT2232 Based
320 There are many USB JTAG dongles on the market, many of them are based
321 on a chip from ``Future Technology Devices International'' (FTDI)
322 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
323 See: @url{http://www.ftdichip.com} for more information.
324 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
325 chips are starting to become available in JTAG adapters. (Adapters
326 using those high speed FT2232H chips may support adaptive clocking.)
328 The FT2232 chips are flexible enough to support some other
329 transport options, such as SWD or the SPI variants used to
330 program some chips. They have two communications channels,
331 and one can be used for a UART adapter at the same time the
332 other one is used to provide a debug adapter.
334 Also, some development boards integrate an FT2232 chip to serve as
335 a built-in low cost debug adapter and usb-to-serial solution.
337 @itemize @bullet
338 @item @b{usbjtag}
339 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
340 @item @b{jtagkey}
341 @* See: @url{http://www.amontec.com/jtagkey.shtml}
342 @item @b{jtagkey2}
343 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
344 @item @b{oocdlink}
345 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
346 @item @b{signalyzer}
347 @* See: @url{http://www.signalyzer.com}
348 @item @b{Stellaris Eval Boards}
349 @* See: @url{http://www.luminarymicro.com} - The Stellaris eval boards
350 bundle FT2232-based JTAG and SWD support, which can be used to debug
351 the Stellaris chips. Using separate JTAG adapters is optional.
352 These boards can also be used in a "pass through" mode as JTAG adapters
353 to other target boards, disabling the Stellaris chip.
354 @item @b{Luminary ICDI}
355 @* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug
356 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
357 Evaluation Kits. Like the non-detachable FT2232 support on the other
358 Stellaris eval boards, they can be used to debug other target boards.
359 @item @b{olimex-jtag}
360 @* See: @url{http://www.olimex.com}
361 @item @b{Flyswatter/Flyswatter2}
362 @* See: @url{http://www.tincantools.com}
363 @item @b{turtelizer2}
364 @* See:
365 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
366 @url{http://www.ethernut.de}
367 @item @b{comstick}
368 @* Link: @url{http://www.hitex.com/index.php?id=383}
369 @item @b{stm32stick}
370 @* Link @url{http://www.hitex.com/stm32-stick}
371 @item @b{axm0432_jtag}
372 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
373 to be available anymore as of April 2012.
374 @item @b{cortino}
375 @* Link @url{http://www.hitex.com/index.php?id=cortino}
376 @item @b{dlp-usb1232h}
377 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
378 @item @b{digilent-hs1}
379 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
380 @end itemize
382 @section USB-JTAG / Altera USB-Blaster compatibles
384 These devices also show up as FTDI devices, but are not
385 protocol-compatible with the FT2232 devices. They are, however,
386 protocol-compatible among themselves. USB-JTAG devices typically consist
387 of a FT245 followed by a CPLD that understands a particular protocol,
388 or emulate this protocol using some other hardware.
390 They may appear under different USB VID/PID depending on the particular
391 product. The driver can be configured to search for any VID/PID pair
392 (see the section on driver commands).
394 @itemize
395 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
396 @* Link: @url{http://ixo-jtag.sourceforge.net/}
397 @item @b{Altera USB-Blaster}
398 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
399 @end itemize
401 @section USB JLINK based
402 There are several OEM versions of the Segger @b{JLINK} adapter. It is
403 an example of a micro controller based JTAG adapter, it uses an
404 AT91SAM764 internally.
406 @itemize @bullet
407 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
408 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
409 @item @b{SEGGER JLINK}
410 @* Link: @url{http://www.segger.com/jlink.html}
411 @item @b{IAR J-Link}
412 @* Link: @url{http://www.iar.com/en/products/hardware-debug-probes/iar-j-link/}
413 @end itemize
415 @section USB RLINK based
416 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
418 @itemize @bullet
419 @item @b{Raisonance RLink}
420 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
421 @item @b{STM32 Primer}
422 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
423 @item @b{STM32 Primer2}
424 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
425 @end itemize
427 @section USB ST-LINK based
428 ST Micro has an adapter called @b{ST-LINK}.
429 They only work with ST Micro chips, notably STM32 and STM8.
431 @itemize @bullet
432 @item @b{ST-LINK}
433 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
434 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
435 @item @b{ST-LINK/V2}
436 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
437 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
438 @end itemize
440 For info the original ST-LINK enumerates using the mass storage usb class, however
441 it's implementation is completely broken. The result is this causes issues under linux.
442 The simplest solution is to get linux to ignore the ST-LINK using one of the following methods:
443 @itemize @bullet
444 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
445 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
446 @end itemize
448 @section USB Other
449 @itemize @bullet
450 @item @b{USBprog}
451 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
453 @item @b{USB - Presto}
454 @* Link: @url{http://tools.asix.net/prg_presto.htm}
456 @item @b{Versaloon-Link}
457 @* Link: @url{http://www.simonqian.com/en/Versaloon}
459 @item @b{ARM-JTAG-EW}
460 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
462 @item @b{Buspirate}
463 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
464 @end itemize
466 @section IBM PC Parallel Printer Port Based
468 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
469 and the Macraigor Wiggler. There are many clones and variations of
470 these on the market.
472 Note that parallel ports are becoming much less common, so if you
473 have the choice you should probably avoid these adapters in favor
474 of USB-based ones.
476 @itemize @bullet
478 @item @b{Wiggler} - There are many clones of this.
479 @* Link: @url{http://www.macraigor.com/wiggler.htm}
481 @item @b{DLC5} - From XILINX - There are many clones of this
482 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
483 produced, PDF schematics are easily found and it is easy to make.
485 @item @b{Amontec - JTAG Accelerator}
486 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
488 @item @b{GW16402}
489 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
491 @item @b{Wiggler2}
492 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
494 @item @b{Wiggler_ntrst_inverted}
495 @* Yet another variation - See the source code, src/jtag/parport.c
497 @item @b{old_amt_wiggler}
498 @* Unknown - probably not on the market today
500 @item @b{arm-jtag}
501 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
503 @item @b{chameleon}
504 @* Link: @url{http://www.amontec.com/chameleon.shtml}
506 @item @b{Triton}
507 @* Unknown.
509 @item @b{Lattice}
510 @* ispDownload from Lattice Semiconductor
511 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
513 @item @b{flashlink}
514 @* From ST Microsystems;
515 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
517 @end itemize
519 @section Other...
520 @itemize @bullet
522 @item @b{ep93xx}
523 @* An EP93xx based Linux machine using the GPIO pins directly.
525 @item @b{at91rm9200}
526 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
528 @end itemize
530 @node About Jim-Tcl
531 @chapter About Jim-Tcl
532 @cindex Jim-Tcl
533 @cindex tcl
535 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
536 This programming language provides a simple and extensible
537 command interpreter.
539 All commands presented in this Guide are extensions to Jim-Tcl.
540 You can use them as simple commands, without needing to learn
541 much of anything about Tcl.
542 Alternatively, can write Tcl programs with them.
544 You can learn more about Jim at its website, @url{http://jim.berlios.de}.
545 There is an active and responsive community, get on the mailing list
546 if you have any questions. Jim-Tcl maintainers also lurk on the
547 OpenOCD mailing list.
549 @itemize @bullet
550 @item @b{Jim vs. Tcl}
551 @* Jim-Tcl is a stripped down version of the well known Tcl language,
552 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
553 fewer features. Jim-Tcl is several dozens of .C files and .H files and
554 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
555 4.2 MB .zip file containing 1540 files.
557 @item @b{Missing Features}
558 @* Our practice has been: Add/clone the real Tcl feature if/when
559 needed. We welcome Jim-Tcl improvements, not bloat. Also there
560 are a large number of optional Jim-Tcl features that are not
561 enabled in OpenOCD.
563 @item @b{Scripts}
564 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
565 command interpreter today is a mixture of (newer)
566 Jim-Tcl commands, and (older) the orginal command interpreter.
568 @item @b{Commands}
569 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
570 can type a Tcl for() loop, set variables, etc.
571 Some of the commands documented in this guide are implemented
572 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
574 @item @b{Historical Note}
575 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
576 before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
577 as a git submodule, which greatly simplified upgrading Jim Tcl
578 to benefit from new features and bugfixes in Jim Tcl.
580 @item @b{Need a crash course in Tcl?}
581 @*@xref{Tcl Crash Course}.
582 @end itemize
584 @node Running
585 @chapter Running
586 @cindex command line options
587 @cindex logfile
588 @cindex directory search
590 Properly installing OpenOCD sets up your operating system to grant it access
591 to the debug adapters. On Linux, this usually involves installing a file
592 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
593 complex and confusing driver configuration for every peripheral. Such issues
594 are unique to each operating system, and are not detailed in this User's Guide.
596 Then later you will invoke the OpenOCD server, with various options to
597 tell it how each debug session should work.
598 The @option{--help} option shows:
599 @verbatim
600 bash$ openocd --help
602 --help | -h display this help
603 --version | -v display OpenOCD version
604 --file | -f use configuration file <name>
605 --search | -s dir to search for config files and scripts
606 --debug | -d set debug level <0-3>
607 --log_output | -l redirect log output to file <name>
608 --command | -c run <command>
609 @end verbatim
611 If you don't give any @option{-f} or @option{-c} options,
612 OpenOCD tries to read the configuration file @file{openocd.cfg}.
613 To specify one or more different
614 configuration files, use @option{-f} options. For example:
616 @example
617 openocd -f config1.cfg -f config2.cfg -f config3.cfg
618 @end example
620 Configuration files and scripts are searched for in
621 @enumerate
622 @item the current directory,
623 @item any search dir specified on the command line using the @option{-s} option,
624 @item any search dir specified using the @command{add_script_search_dir} command,
625 @item @file{$HOME/.openocd} (not on Windows),
626 @item the site wide script library @file{$pkgdatadir/site} and
627 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
628 @end enumerate
629 The first found file with a matching file name will be used.
631 @quotation Note
632 Don't try to use configuration script names or paths which
633 include the "#" character. That character begins Tcl comments.
634 @end quotation
636 @section Simple setup, no customization
638 In the best case, you can use two scripts from one of the script
639 libraries, hook up your JTAG adapter, and start the server ... and
640 your JTAG setup will just work "out of the box". Always try to
641 start by reusing those scripts, but assume you'll need more
642 customization even if this works. @xref{OpenOCD Project Setup}.
644 If you find a script for your JTAG adapter, and for your board or
645 target, you may be able to hook up your JTAG adapter then start
646 the server like:
648 @example
649 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
650 @end example
652 You might also need to configure which reset signals are present,
653 using @option{-c 'reset_config trst_and_srst'} or something similar.
654 If all goes well you'll see output something like
656 @example
657 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
658 For bug reports, read
659 http://openocd.sourceforge.net/doc/doxygen/bugs.html
660 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
661 (mfg: 0x23b, part: 0xba00, ver: 0x3)
662 @end example
664 Seeing that "tap/device found" message, and no warnings, means
665 the JTAG communication is working. That's a key milestone, but
666 you'll probably need more project-specific setup.
668 @section What OpenOCD does as it starts
670 OpenOCD starts by processing the configuration commands provided
671 on the command line or, if there were no @option{-c command} or
672 @option{-f file.cfg} options given, in @file{openocd.cfg}.
673 @xref{Configuration Stage}.
674 At the end of the configuration stage it verifies the JTAG scan
675 chain defined using those commands; your configuration should
676 ensure that this always succeeds.
677 Normally, OpenOCD then starts running as a daemon.
678 Alternatively, commands may be used to terminate the configuration
679 stage early, perform work (such as updating some flash memory),
680 and then shut down without acting as a daemon.
682 Once OpenOCD starts running as a daemon, it waits for connections from
683 clients (Telnet, GDB, Other) and processes the commands issued through
684 those channels.
686 If you are having problems, you can enable internal debug messages via
687 the @option{-d} option.
689 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
690 @option{-c} command line switch.
692 To enable debug output (when reporting problems or working on OpenOCD
693 itself), use the @option{-d} command line switch. This sets the
694 @option{debug_level} to "3", outputting the most information,
695 including debug messages. The default setting is "2", outputting only
696 informational messages, warnings and errors. You can also change this
697 setting from within a telnet or gdb session using @command{debug_level
698 <n>} (@pxref{debug_level}).
700 You can redirect all output from the daemon to a file using the
701 @option{-l <logfile>} switch.
703 Note! OpenOCD will launch the GDB & telnet server even if it can not
704 establish a connection with the target. In general, it is possible for
705 the JTAG controller to be unresponsive until the target is set up
706 correctly via e.g. GDB monitor commands in a GDB init script.
708 @node OpenOCD Project Setup
709 @chapter OpenOCD Project Setup
711 To use OpenOCD with your development projects, you need to do more than
712 just connecting the JTAG adapter hardware (dongle) to your development board
713 and then starting the OpenOCD server.
714 You also need to configure that server so that it knows
715 about that adapter and board, and helps your work.
716 You may also want to connect OpenOCD to GDB, possibly
717 using Eclipse or some other GUI.
719 @section Hooking up the JTAG Adapter
721 Today's most common case is a dongle with a JTAG cable on one side
722 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
723 and a USB cable on the other.
724 Instead of USB, some cables use Ethernet;
725 older ones may use a PC parallel port, or even a serial port.
727 @enumerate
728 @item @emph{Start with power to your target board turned off},
729 and nothing connected to your JTAG adapter.
730 If you're particularly paranoid, unplug power to the board.
731 It's important to have the ground signal properly set up,
732 unless you are using a JTAG adapter which provides
733 galvanic isolation between the target board and the
734 debugging host.
736 @item @emph{Be sure it's the right kind of JTAG connector.}
737 If your dongle has a 20-pin ARM connector, you need some kind
738 of adapter (or octopus, see below) to hook it up to
739 boards using 14-pin or 10-pin connectors ... or to 20-pin
740 connectors which don't use ARM's pinout.
742 In the same vein, make sure the voltage levels are compatible.
743 Not all JTAG adapters have the level shifters needed to work
744 with 1.2 Volt boards.
746 @item @emph{Be certain the cable is properly oriented} or you might
747 damage your board. In most cases there are only two possible
748 ways to connect the cable.
749 Connect the JTAG cable from your adapter to the board.
750 Be sure it's firmly connected.
752 In the best case, the connector is keyed to physically
753 prevent you from inserting it wrong.
754 This is most often done using a slot on the board's male connector
755 housing, which must match a key on the JTAG cable's female connector.
756 If there's no housing, then you must look carefully and
757 make sure pin 1 on the cable hooks up to pin 1 on the board.
758 Ribbon cables are frequently all grey except for a wire on one
759 edge, which is red. The red wire is pin 1.
761 Sometimes dongles provide cables where one end is an ``octopus'' of
762 color coded single-wire connectors, instead of a connector block.
763 These are great when converting from one JTAG pinout to another,
764 but are tedious to set up.
765 Use these with connector pinout diagrams to help you match up the
766 adapter signals to the right board pins.
768 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
769 A USB, parallel, or serial port connector will go to the host which
770 you are using to run OpenOCD.
771 For Ethernet, consult the documentation and your network administrator.
773 For USB based JTAG adapters you have an easy sanity check at this point:
774 does the host operating system see the JTAG adapter? If that host is an
775 MS-Windows host, you'll need to install a driver before OpenOCD works.
777 @item @emph{Connect the adapter's power supply, if needed.}
778 This step is primarily for non-USB adapters,
779 but sometimes USB adapters need extra power.
781 @item @emph{Power up the target board.}
782 Unless you just let the magic smoke escape,
783 you're now ready to set up the OpenOCD server
784 so you can use JTAG to work with that board.
786 @end enumerate
788 Talk with the OpenOCD server using
789 telnet (@code{telnet localhost 4444} on many systems) or GDB.
790 @xref{GDB and OpenOCD}.
792 @section Project Directory
794 There are many ways you can configure OpenOCD and start it up.
796 A simple way to organize them all involves keeping a
797 single directory for your work with a given board.
798 When you start OpenOCD from that directory,
799 it searches there first for configuration files, scripts,
800 files accessed through semihosting,
801 and for code you upload to the target board.
802 It is also the natural place to write files,
803 such as log files and data you download from the board.
805 @section Configuration Basics
807 There are two basic ways of configuring OpenOCD, and
808 a variety of ways you can mix them.
809 Think of the difference as just being how you start the server:
811 @itemize
812 @item Many @option{-f file} or @option{-c command} options on the command line
813 @item No options, but a @dfn{user config file}
814 in the current directory named @file{openocd.cfg}
815 @end itemize
817 Here is an example @file{openocd.cfg} file for a setup
818 using a Signalyzer FT2232-based JTAG adapter to talk to
819 a board with an Atmel AT91SAM7X256 microcontroller:
821 @example
822 source [find interface/signalyzer.cfg]
824 # GDB can also flash my flash!
825 gdb_memory_map enable
826 gdb_flash_program enable
828 source [find target/sam7x256.cfg]
829 @end example
831 Here is the command line equivalent of that configuration:
833 @example
834 openocd -f interface/signalyzer.cfg \
835 -c "gdb_memory_map enable" \
836 -c "gdb_flash_program enable" \
837 -f target/sam7x256.cfg
838 @end example
840 You could wrap such long command lines in shell scripts,
841 each supporting a different development task.
842 One might re-flash the board with a specific firmware version.
843 Another might set up a particular debugging or run-time environment.
845 @quotation Important
846 At this writing (October 2009) the command line method has
847 problems with how it treats variables.
848 For example, after @option{-c "set VAR value"}, or doing the
849 same in a script, the variable @var{VAR} will have no value
850 that can be tested in a later script.
851 @end quotation
853 Here we will focus on the simpler solution: one user config
854 file, including basic configuration plus any TCL procedures
855 to simplify your work.
857 @section User Config Files
858 @cindex config file, user
859 @cindex user config file
860 @cindex config file, overview
862 A user configuration file ties together all the parts of a project
863 in one place.
864 One of the following will match your situation best:
866 @itemize
867 @item Ideally almost everything comes from configuration files
868 provided by someone else.
869 For example, OpenOCD distributes a @file{scripts} directory
870 (probably in @file{/usr/share/openocd/scripts} on Linux).
871 Board and tool vendors can provide these too, as can individual
872 user sites; the @option{-s} command line option lets you say
873 where to find these files. (@xref{Running}.)
874 The AT91SAM7X256 example above works this way.
876 Three main types of non-user configuration file each have their
877 own subdirectory in the @file{scripts} directory:
879 @enumerate
880 @item @b{interface} -- one for each different debug adapter;
881 @item @b{board} -- one for each different board
882 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
883 @end enumerate
885 Best case: include just two files, and they handle everything else.
886 The first is an interface config file.
887 The second is board-specific, and it sets up the JTAG TAPs and
888 their GDB targets (by deferring to some @file{target.cfg} file),
889 declares all flash memory, and leaves you nothing to do except
890 meet your deadline:
892 @example
893 source [find interface/olimex-jtag-tiny.cfg]
894 source [find board/csb337.cfg]
895 @end example
897 Boards with a single microcontroller often won't need more
898 than the target config file, as in the AT91SAM7X256 example.
899 That's because there is no external memory (flash, DDR RAM), and
900 the board differences are encapsulated by application code.
902 @item Maybe you don't know yet what your board looks like to JTAG.
903 Once you know the @file{interface.cfg} file to use, you may
904 need help from OpenOCD to discover what's on the board.
905 Once you find the JTAG TAPs, you can just search for appropriate
906 target and board
907 configuration files ... or write your own, from the bottom up.
908 @xref{Autoprobing}.
910 @item You can often reuse some standard config files but
911 need to write a few new ones, probably a @file{board.cfg} file.
912 You will be using commands described later in this User's Guide,
913 and working with the guidelines in the next chapter.
915 For example, there may be configuration files for your JTAG adapter
916 and target chip, but you need a new board-specific config file
917 giving access to your particular flash chips.
918 Or you might need to write another target chip configuration file
919 for a new chip built around the Cortex M3 core.
921 @quotation Note
922 When you write new configuration files, please submit
923 them for inclusion in the next OpenOCD release.
924 For example, a @file{board/newboard.cfg} file will help the
925 next users of that board, and a @file{target/newcpu.cfg}
926 will help support users of any board using that chip.
927 @end quotation
929 @item
930 You may may need to write some C code.
931 It may be as simple as a supporting a new ft2232 or parport
932 based adapter; a bit more involved, like a NAND or NOR flash
933 controller driver; or a big piece of work like supporting
934 a new chip architecture.
935 @end itemize
937 Reuse the existing config files when you can.
938 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
939 You may find a board configuration that's a good example to follow.
941 When you write config files, separate the reusable parts
942 (things every user of that interface, chip, or board needs)
943 from ones specific to your environment and debugging approach.
944 @itemize
946 @item
947 For example, a @code{gdb-attach} event handler that invokes
948 the @command{reset init} command will interfere with debugging
949 early boot code, which performs some of the same actions
950 that the @code{reset-init} event handler does.
952 @item
953 Likewise, the @command{arm9 vector_catch} command (or
954 @cindex vector_catch
955 its siblings @command{xscale vector_catch}
956 and @command{cortex_m3 vector_catch}) can be a timesaver
957 during some debug sessions, but don't make everyone use that either.
958 Keep those kinds of debugging aids in your user config file,
959 along with messaging and tracing setup.
960 (@xref{Software Debug Messages and Tracing}.)
962 @item
963 You might need to override some defaults.
964 For example, you might need to move, shrink, or back up the target's
965 work area if your application needs much SRAM.
967 @item
968 TCP/IP port configuration is another example of something which
969 is environment-specific, and should only appear in
970 a user config file. @xref{TCP/IP Ports}.
971 @end itemize
973 @section Project-Specific Utilities
975 A few project-specific utility
976 routines may well speed up your work.
977 Write them, and keep them in your project's user config file.
979 For example, if you are making a boot loader work on a
980 board, it's nice to be able to debug the ``after it's
981 loaded to RAM'' parts separately from the finicky early
982 code which sets up the DDR RAM controller and clocks.
983 A script like this one, or a more GDB-aware sibling,
984 may help:
986 @example
987 proc ramboot @{ @} @{
988 # Reset, running the target's "reset-init" scripts
989 # to initialize clocks and the DDR RAM controller.
990 # Leave the CPU halted.
991 reset init
993 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
994 load_image u-boot.bin 0x20000000
996 # Start running.
997 resume 0x20000000
998 @}
999 @end example
1001 Then once that code is working you will need to make it
1002 boot from NOR flash; a different utility would help.
1003 Alternatively, some developers write to flash using GDB.
1004 (You might use a similar script if you're working with a flash
1005 based microcontroller application instead of a boot loader.)
1007 @example
1008 proc newboot @{ @} @{
1009 # Reset, leaving the CPU halted. The "reset-init" event
1010 # proc gives faster access to the CPU and to NOR flash;
1011 # "reset halt" would be slower.
1012 reset init
1014 # Write standard version of U-Boot into the first two
1015 # sectors of NOR flash ... the standard version should
1016 # do the same lowlevel init as "reset-init".
1017 flash protect 0 0 1 off
1018 flash erase_sector 0 0 1
1019 flash write_bank 0 u-boot.bin 0x0
1020 flash protect 0 0 1 on
1022 # Reboot from scratch using that new boot loader.
1023 reset run
1024 @}
1025 @end example
1027 You may need more complicated utility procedures when booting
1028 from NAND.
1029 That often involves an extra bootloader stage,
1030 running from on-chip SRAM to perform DDR RAM setup so it can load
1031 the main bootloader code (which won't fit into that SRAM).
1033 Other helper scripts might be used to write production system images,
1034 involving considerably more than just a three stage bootloader.
1036 @section Target Software Changes
1038 Sometimes you may want to make some small changes to the software
1039 you're developing, to help make JTAG debugging work better.
1040 For example, in C or assembly language code you might
1041 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1042 handling issues like:
1044 @itemize @bullet
1046 @item @b{Watchdog Timers}...
1047 Watchog timers are typically used to automatically reset systems if
1048 some application task doesn't periodically reset the timer. (The
1049 assumption is that the system has locked up if the task can't run.)
1050 When a JTAG debugger halts the system, that task won't be able to run
1051 and reset the timer ... potentially causing resets in the middle of
1052 your debug sessions.
1054 It's rarely a good idea to disable such watchdogs, since their usage
1055 needs to be debugged just like all other parts of your firmware.
1056 That might however be your only option.
1058 Look instead for chip-specific ways to stop the watchdog from counting
1059 while the system is in a debug halt state. It may be simplest to set
1060 that non-counting mode in your debugger startup scripts. You may however
1061 need a different approach when, for example, a motor could be physically
1062 damaged by firmware remaining inactive in a debug halt state. That might
1063 involve a type of firmware mode where that "non-counting" mode is disabled
1064 at the beginning then re-enabled at the end; a watchdog reset might fire
1065 and complicate the debug session, but hardware (or people) would be
1066 protected.@footnote{Note that many systems support a "monitor mode" debug
1067 that is a somewhat cleaner way to address such issues. You can think of
1068 it as only halting part of the system, maybe just one task,
1069 instead of the whole thing.
1070 At this writing, January 2010, OpenOCD based debugging does not support
1071 monitor mode debug, only "halt mode" debug.}
1073 @item @b{ARM Semihosting}...
1074 @cindex ARM semihosting
1075 When linked with a special runtime library provided with many
1076 toolchains@footnote{See chapter 8 "Semihosting" in
1077 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1078 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1079 The CodeSourcery EABI toolchain also includes a semihosting library.},
1080 your target code can use I/O facilities on the debug host. That library
1081 provides a small set of system calls which are handled by OpenOCD.
1082 It can let the debugger provide your system console and a file system,
1083 helping with early debugging or providing a more capable environment
1084 for sometimes-complex tasks like installing system firmware onto
1085 NAND or SPI flash.
1087 @item @b{ARM Wait-For-Interrupt}...
1088 Many ARM chips synchronize the JTAG clock using the core clock.
1089 Low power states which stop that core clock thus prevent JTAG access.
1090 Idle loops in tasking environments often enter those low power states
1091 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1093 You may want to @emph{disable that instruction} in source code,
1094 or otherwise prevent using that state,
1095 to ensure you can get JTAG access at any time.@footnote{As a more
1096 polite alternative, some processors have special debug-oriented
1097 registers which can be used to change various features including
1098 how the low power states are clocked while debugging.
1099 The STM32 DBGMCU_CR register is an example; at the cost of extra
1100 power consumption, JTAG can be used during low power states.}
1101 For example, the OpenOCD @command{halt} command may not
1102 work for an idle processor otherwise.
1104 @item @b{Delay after reset}...
1105 Not all chips have good support for debugger access
1106 right after reset; many LPC2xxx chips have issues here.
1107 Similarly, applications that reconfigure pins used for
1108 JTAG access as they start will also block debugger access.
1110 To work with boards like this, @emph{enable a short delay loop}
1111 the first thing after reset, before "real" startup activities.
1112 For example, one second's delay is usually more than enough
1113 time for a JTAG debugger to attach, so that
1114 early code execution can be debugged
1115 or firmware can be replaced.
1117 @item @b{Debug Communications Channel (DCC)}...
1118 Some processors include mechanisms to send messages over JTAG.
1119 Many ARM cores support these, as do some cores from other vendors.
1120 (OpenOCD may be able to use this DCC internally, speeding up some
1121 operations like writing to memory.)
1123 Your application may want to deliver various debugging messages
1124 over JTAG, by @emph{linking with a small library of code}
1125 provided with OpenOCD and using the utilities there to send
1126 various kinds of message.
1127 @xref{Software Debug Messages and Tracing}.
1129 @end itemize
1131 @section Target Hardware Setup
1133 Chip vendors often provide software development boards which
1134 are highly configurable, so that they can support all options
1135 that product boards may require. @emph{Make sure that any
1136 jumpers or switches match the system configuration you are
1137 working with.}
1139 Common issues include:
1141 @itemize @bullet
1143 @item @b{JTAG setup} ...
1144 Boards may support more than one JTAG configuration.
1145 Examples include jumpers controlling pullups versus pulldowns
1146 on the nTRST and/or nSRST signals, and choice of connectors
1147 (e.g. which of two headers on the base board,
1148 or one from a daughtercard).
1149 For some Texas Instruments boards, you may need to jumper the
1150 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1152 @item @b{Boot Modes} ...
1153 Complex chips often support multiple boot modes, controlled
1154 by external jumpers. Make sure this is set up correctly.
1155 For example many i.MX boards from NXP need to be jumpered
1156 to "ATX mode" to start booting using the on-chip ROM, when
1157 using second stage bootloader code stored in a NAND flash chip.
1159 Such explicit configuration is common, and not limited to
1160 booting from NAND. You might also need to set jumpers to
1161 start booting using code loaded from an MMC/SD card; external
1162 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1163 flash; some external host; or various other sources.
1166 @item @b{Memory Addressing} ...
1167 Boards which support multiple boot modes may also have jumpers
1168 to configure memory addressing. One board, for example, jumpers
1169 external chipselect 0 (used for booting) to address either
1170 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1171 or NAND flash. When it's jumpered to address NAND flash, that
1172 board must also be told to start booting from on-chip ROM.
1174 Your @file{board.cfg} file may also need to be told this jumper
1175 configuration, so that it can know whether to declare NOR flash
1176 using @command{flash bank} or instead declare NAND flash with
1177 @command{nand device}; and likewise which probe to perform in
1178 its @code{reset-init} handler.
1180 A closely related issue is bus width. Jumpers might need to
1181 distinguish between 8 bit or 16 bit bus access for the flash
1182 used to start booting.
1184 @item @b{Peripheral Access} ...
1185 Development boards generally provide access to every peripheral
1186 on the chip, sometimes in multiple modes (such as by providing
1187 multiple audio codec chips).
1188 This interacts with software
1189 configuration of pin multiplexing, where for example a
1190 given pin may be routed either to the MMC/SD controller
1191 or the GPIO controller. It also often interacts with
1192 configuration jumpers. One jumper may be used to route
1193 signals to an MMC/SD card slot or an expansion bus (which
1194 might in turn affect booting); others might control which
1195 audio or video codecs are used.
1197 @end itemize
1199 Plus you should of course have @code{reset-init} event handlers
1200 which set up the hardware to match that jumper configuration.
1201 That includes in particular any oscillator or PLL used to clock
1202 the CPU, and any memory controllers needed to access external
1203 memory and peripherals. Without such handlers, you won't be
1204 able to access those resources without working target firmware
1205 which can do that setup ... this can be awkward when you're
1206 trying to debug that target firmware. Even if there's a ROM
1207 bootloader which handles a few issues, it rarely provides full
1208 access to all board-specific capabilities.
1211 @node Config File Guidelines
1212 @chapter Config File Guidelines
1214 This chapter is aimed at any user who needs to write a config file,
1215 including developers and integrators of OpenOCD and any user who
1216 needs to get a new board working smoothly.
1217 It provides guidelines for creating those files.
1219 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1220 with files including the ones listed here.
1221 Use them as-is where you can; or as models for new files.
1222 @itemize @bullet
1223 @item @file{interface} ...
1224 These are for debug adapters.
1225 Files that configure JTAG adapters go here.
1226 @example
1227 $ ls interface
1228 arm-jtag-ew.cfg hitex_str9-comstick.cfg oocdlink.cfg
1229 arm-usb-ocd.cfg icebear.cfg openocd-usb.cfg
1230 at91rm9200.cfg jlink.cfg parport.cfg
1231 axm0432.cfg jtagkey2.cfg parport_dlc5.cfg
1232 calao-usb-a9260-c01.cfg jtagkey.cfg rlink.cfg
1233 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg sheevaplug.cfg
1234 calao-usb-a9260.cfg luminary.cfg signalyzer.cfg
1235 chameleon.cfg luminary-icdi.cfg stm32-stick.cfg
1236 cortino.cfg luminary-lm3s811.cfg turtelizer2.cfg
1237 dummy.cfg olimex-arm-usb-ocd.cfg usbprog.cfg
1238 flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
1239 $
1240 @end example
1241 @item @file{board} ...
1242 think Circuit Board, PWA, PCB, they go by many names. Board files
1243 contain initialization items that are specific to a board.
1244 They reuse target configuration files, since the same
1245 microprocessor chips are used on many boards,
1246 but support for external parts varies widely. For
1247 example, the SDRAM initialization sequence for the board, or the type
1248 of external flash and what address it uses. Any initialization
1249 sequence to enable that external flash or SDRAM should be found in the
1250 board file. Boards may also contain multiple targets: two CPUs; or
1251 a CPU and an FPGA.
1252 @example
1253 $ ls board
1254 arm_evaluator7t.cfg keil_mcb1700.cfg
1255 at91rm9200-dk.cfg keil_mcb2140.cfg
1256 at91sam9g20-ek.cfg linksys_nslu2.cfg
1257 atmel_at91sam7s-ek.cfg logicpd_imx27.cfg
1258 atmel_at91sam9260-ek.cfg mini2440.cfg
1259 atmel_sam3u_ek.cfg olimex_LPC2378STK.cfg
1260 crossbow_tech_imote2.cfg olimex_lpc_h2148.cfg
1261 csb337.cfg olimex_sam7_ex256.cfg
1262 csb732.cfg olimex_sam9_l9260.cfg
1263 digi_connectcore_wi-9c.cfg olimex_stm32_h103.cfg
1264 dm355evm.cfg omap2420_h4.cfg
1265 dm365evm.cfg osk5912.cfg
1266 dm6446evm.cfg pic-p32mx.cfg
1267 eir.cfg propox_mmnet1001.cfg
1268 ek-lm3s1968.cfg pxa255_sst.cfg
1269 ek-lm3s3748.cfg sheevaplug.cfg
1270 ek-lm3s811.cfg stm3210e_eval.cfg
1271 ek-lm3s9b9x.cfg stm32f10x_128k_eval.cfg
1272 hammer.cfg str910-eval.cfg
1273 hitex_lpc2929.cfg telo.cfg
1274 hitex_stm32-performancestick.cfg ti_beagleboard.cfg
1275 hitex_str9-comstick.cfg topas910.cfg
1276 iar_str912_sk.cfg topasa900.cfg
1277 imx27ads.cfg unknown_at91sam9260.cfg
1278 imx27lnst.cfg x300t.cfg
1279 imx31pdk.cfg zy1000.cfg
1280 $
1281 @end example
1282 @item @file{target} ...
1283 think chip. The ``target'' directory represents the JTAG TAPs
1284 on a chip
1285 which OpenOCD should control, not a board. Two common types of targets
1286 are ARM chips and FPGA or CPLD chips.
1287 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1288 the target config file defines all of them.
1289 @example
1290 $ ls target
1291 aduc702x.cfg imx27.cfg pxa255.cfg
1292 ar71xx.cfg imx31.cfg pxa270.cfg
1293 at91eb40a.cfg imx35.cfg readme.txt
1294 at91r40008.cfg is5114.cfg sam7se512.cfg
1295 at91rm9200.cfg ixp42x.cfg sam7x256.cfg
1296 at91sam3u1c.cfg lm3s1968.cfg samsung_s3c2410.cfg
1297 at91sam3u1e.cfg lm3s3748.cfg samsung_s3c2440.cfg
1298 at91sam3u2c.cfg lm3s6965.cfg samsung_s3c2450.cfg
1299 at91sam3u2e.cfg lm3s811.cfg samsung_s3c4510.cfg
1300 at91sam3u4c.cfg lm3s9b9x.cfg samsung_s3c6410.cfg
1301 at91sam3u4e.cfg lpc1768.cfg sharp_lh79532.cfg
1302 at91sam3uXX.cfg lpc2103.cfg smdk6410.cfg
1303 at91sam7sx.cfg lpc2124.cfg smp8634.cfg
1304 at91sam9260.cfg lpc2129.cfg stm32f1x.cfg
1305 c100.cfg lpc2148.cfg str710.cfg
1306 c100config.tcl lpc2294.cfg str730.cfg
1307 c100helper.tcl lpc2378.cfg str750.cfg
1308 c100regs.tcl lpc2478.cfg str912.cfg
1309 cs351x.cfg lpc2900.cfg telo.cfg
1310 davinci.cfg mega128.cfg ti_dm355.cfg
1311 dragonite.cfg netx500.cfg ti_dm365.cfg
1312 epc9301.cfg omap2420.cfg ti_dm6446.cfg
1313 feroceon.cfg omap3530.cfg tmpa900.cfg
1314 icepick.cfg omap5912.cfg tmpa910.cfg
1315 imx21.cfg pic32mx.cfg xba_revA3.cfg
1316 $
1317 @end example
1318 @item @emph{more} ... browse for other library files which may be useful.
1319 For example, there are various generic and CPU-specific utilities.
1320 @end itemize
1322 The @file{openocd.cfg} user config
1323 file may override features in any of the above files by
1324 setting variables before sourcing the target file, or by adding
1325 commands specific to their situation.
1327 @section Interface Config Files
1329 The user config file
1330 should be able to source one of these files with a command like this:
1332 @example
1333 source [find interface/FOOBAR.cfg]
1334 @end example
1336 A preconfigured interface file should exist for every debug adapter
1337 in use today with OpenOCD.
1338 That said, perhaps some of these config files
1339 have only been used by the developer who created it.
1341 A separate chapter gives information about how to set these up.
1342 @xref{Debug Adapter Configuration}.
1343 Read the OpenOCD source code (and Developer's Guide)
1344 if you have a new kind of hardware interface
1345 and need to provide a driver for it.
1347 @section Board Config Files
1348 @cindex config file, board
1349 @cindex board config file
1351 The user config file
1352 should be able to source one of these files with a command like this:
1354 @example
1355 source [find board/FOOBAR.cfg]
1356 @end example
1358 The point of a board config file is to package everything
1359 about a given board that user config files need to know.
1360 In summary the board files should contain (if present)
1362 @enumerate
1363 @item One or more @command{source [target/...cfg]} statements
1364 @item NOR flash configuration (@pxref{NOR Configuration})
1365 @item NAND flash configuration (@pxref{NAND Configuration})
1366 @item Target @code{reset} handlers for SDRAM and I/O configuration
1367 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1368 @item All things that are not ``inside a chip''
1369 @end enumerate
1371 Generic things inside target chips belong in target config files,
1372 not board config files. So for example a @code{reset-init} event
1373 handler should know board-specific oscillator and PLL parameters,
1374 which it passes to target-specific utility code.
1376 The most complex task of a board config file is creating such a
1377 @code{reset-init} event handler.
1378 Define those handlers last, after you verify the rest of the board
1379 configuration works.
1381 @subsection Communication Between Config files
1383 In addition to target-specific utility code, another way that
1384 board and target config files communicate is by following a
1385 convention on how to use certain variables.
1387 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1388 Thus the rule we follow in OpenOCD is this: Variables that begin with
1389 a leading underscore are temporary in nature, and can be modified and
1390 used at will within a target configuration file.
1392 Complex board config files can do the things like this,
1393 for a board with three chips:
1395 @example
1396 # Chip #1: PXA270 for network side, big endian
1397 set CHIPNAME network
1398 set ENDIAN big
1399 source [find target/pxa270.cfg]
1400 # on return: _TARGETNAME = network.cpu
1401 # other commands can refer to the "network.cpu" target.
1402 $_TARGETNAME configure .... events for this CPU..
1404 # Chip #2: PXA270 for video side, little endian
1405 set CHIPNAME video
1406 set ENDIAN little
1407 source [find target/pxa270.cfg]
1408 # on return: _TARGETNAME = video.cpu
1409 # other commands can refer to the "video.cpu" target.
1410 $_TARGETNAME configure .... events for this CPU..
1412 # Chip #3: Xilinx FPGA for glue logic
1413 set CHIPNAME xilinx
1414 unset ENDIAN
1415 source [find target/spartan3.cfg]
1416 @end example
1418 That example is oversimplified because it doesn't show any flash memory,
1419 or the @code{reset-init} event handlers to initialize external DRAM
1420 or (assuming it needs it) load a configuration into the FPGA.
1421 Such features are usually needed for low-level work with many boards,
1422 where ``low level'' implies that the board initialization software may
1423 not be working. (That's a common reason to need JTAG tools. Another
1424 is to enable working with microcontroller-based systems, which often
1425 have no debugging support except a JTAG connector.)
1427 Target config files may also export utility functions to board and user
1428 config files. Such functions should use name prefixes, to help avoid
1429 naming collisions.
1431 Board files could also accept input variables from user config files.
1432 For example, there might be a @code{J4_JUMPER} setting used to identify
1433 what kind of flash memory a development board is using, or how to set
1434 up other clocks and peripherals.
1436 @subsection Variable Naming Convention
1437 @cindex variable names
1439 Most boards have only one instance of a chip.
1440 However, it should be easy to create a board with more than
1441 one such chip (as shown above).
1442 Accordingly, we encourage these conventions for naming
1443 variables associated with different @file{target.cfg} files,
1444 to promote consistency and
1445 so that board files can override target defaults.
1447 Inputs to target config files include:
1449 @itemize @bullet
1450 @item @code{CHIPNAME} ...
1451 This gives a name to the overall chip, and is used as part of
1452 tap identifier dotted names.
1453 While the default is normally provided by the chip manufacturer,
1454 board files may need to distinguish between instances of a chip.
1455 @item @code{ENDIAN} ...
1456 By default @option{little} - although chips may hard-wire @option{big}.
1457 Chips that can't change endianness don't need to use this variable.
1458 @item @code{CPUTAPID} ...
1459 When OpenOCD examines the JTAG chain, it can be told verify the
1460 chips against the JTAG IDCODE register.
1461 The target file will hold one or more defaults, but sometimes the
1462 chip in a board will use a different ID (perhaps a newer revision).
1463 @end itemize
1465 Outputs from target config files include:
1467 @itemize @bullet
1468 @item @code{_TARGETNAME} ...
1469 By convention, this variable is created by the target configuration
1470 script. The board configuration file may make use of this variable to
1471 configure things like a ``reset init'' script, or other things
1472 specific to that board and that target.
1473 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1474 @code{_TARGETNAME1}, ... etc.
1475 @end itemize
1477 @subsection The reset-init Event Handler
1478 @cindex event, reset-init
1479 @cindex reset-init handler
1481 Board config files run in the OpenOCD configuration stage;
1482 they can't use TAPs or targets, since they haven't been
1483 fully set up yet.
1484 This means you can't write memory or access chip registers;
1485 you can't even verify that a flash chip is present.
1486 That's done later in event handlers, of which the target @code{reset-init}
1487 handler is one of the most important.
1489 Except on microcontrollers, the basic job of @code{reset-init} event
1490 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1491 Microcontrollers rarely use boot loaders; they run right out of their
1492 on-chip flash and SRAM memory. But they may want to use one of these
1493 handlers too, if just for developer convenience.
1495 @quotation Note
1496 Because this is so very board-specific, and chip-specific, no examples
1497 are included here.
1498 Instead, look at the board config files distributed with OpenOCD.
1499 If you have a boot loader, its source code will help; so will
1500 configuration files for other JTAG tools
1501 (@pxref{Translating Configuration Files}).
1502 @end quotation
1504 Some of this code could probably be shared between different boards.
1505 For example, setting up a DRAM controller often doesn't differ by
1506 much except the bus width (16 bits or 32?) and memory timings, so a
1507 reusable TCL procedure loaded by the @file{target.cfg} file might take
1508 those as parameters.
1509 Similarly with oscillator, PLL, and clock setup;
1510 and disabling the watchdog.
1511 Structure the code cleanly, and provide comments to help
1512 the next developer doing such work.
1513 (@emph{You might be that next person} trying to reuse init code!)
1515 The last thing normally done in a @code{reset-init} handler is probing
1516 whatever flash memory was configured. For most chips that needs to be
1517 done while the associated target is halted, either because JTAG memory
1518 access uses the CPU or to prevent conflicting CPU access.
1520 @subsection JTAG Clock Rate
1522 Before your @code{reset-init} handler has set up
1523 the PLLs and clocking, you may need to run with
1524 a low JTAG clock rate.
1525 @xref{JTAG Speed}.
1526 Then you'd increase that rate after your handler has
1527 made it possible to use the faster JTAG clock.
1528 When the initial low speed is board-specific, for example
1529 because it depends on a board-specific oscillator speed, then
1530 you should probably set it up in the board config file;
1531 if it's target-specific, it belongs in the target config file.
1533 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1534 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1535 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1536 Consult chip documentation to determine the peak JTAG clock rate,
1537 which might be less than that.
1539 @quotation Warning
1540 On most ARMs, JTAG clock detection is coupled to the core clock, so
1541 software using a @option{wait for interrupt} operation blocks JTAG access.
1542 Adaptive clocking provides a partial workaround, but a more complete
1543 solution just avoids using that instruction with JTAG debuggers.
1544 @end quotation
1546 If both the chip and the board support adaptive clocking,
1547 use the @command{jtag_rclk}
1548 command, in case your board is used with JTAG adapter which
1549 also supports it. Otherwise use @command{adapter_khz}.
1550 Set the slow rate at the beginning of the reset sequence,
1551 and the faster rate as soon as the clocks are at full speed.
1553 @anchor{The init_board procedure}
1554 @subsection The init_board procedure
1555 @cindex init_board procedure
1557 The concept of @code{init_board} procedure is very similar to @code{init_targets} (@xref{The init_targets procedure}.)
1558 - it's a replacement of ``linear'' configuration scripts. This procedure is meant to be executed when OpenOCD enters run
1559 stage (@xref{Entering the Run Stage},) after @code{init_targets}. The idea to have spearate @code{init_targets} and
1560 @code{init_board} procedures is to allow the first one to configure everything target specific (internal flash,
1561 internal RAM, etc.) and the second one to configure everything board specific (reset signals, chip frequency,
1562 reset-init event handler, external memory, etc.). Additionally ``linear'' board config file will most likely fail when
1563 target config file uses @code{init_targets} scheme (``linear'' script is executed before @code{init} and
1564 @code{init_targets} - after), so separating these two configuration stages is very convenient, as the easiest way to
1565 overcome this problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1566 need to override @code{init_targets} defined in target config files when they only need to to add some specifics.
1568 Just as @code{init_targets}, the @code{init_board} procedure can be overriden by ``next level'' script (which sources
1569 the original), allowing greater code reuse.
1571 @example
1572 ### board_file.cfg ###
1574 # source target file that does most of the config in init_targets
1575 source [find target/target.cfg]
1577 proc enable_fast_clock @{@} @{
1578 # enables fast on-board clock source
1579 # configures the chip to use it
1580 @}
1582 # initialize only board specifics - reset, clock, adapter frequency
1583 proc init_board @{@} @{
1584 reset_config trst_and_srst trst_pulls_srst
1586 $_TARGETNAME configure -event reset-init @{
1587 adapter_khz 1
1588 enable_fast_clock
1589 adapter_khz 10000
1590 @}
1591 @}
1592 @end example
1594 @section Target Config Files
1595 @cindex config file, target
1596 @cindex target config file
1598 Board config files communicate with target config files using
1599 naming conventions as described above, and may source one or
1600 more target config files like this:
1602 @example
1603 source [find target/FOOBAR.cfg]
1604 @end example
1606 The point of a target config file is to package everything
1607 about a given chip that board config files need to know.
1608 In summary the target files should contain
1610 @enumerate
1611 @item Set defaults
1612 @item Add TAPs to the scan chain
1613 @item Add CPU targets (includes GDB support)
1614 @item CPU/Chip/CPU-Core specific features
1615 @item On-Chip flash
1616 @end enumerate
1618 As a rule of thumb, a target file sets up only one chip.
1619 For a microcontroller, that will often include a single TAP,
1620 which is a CPU needing a GDB target, and its on-chip flash.
1622 More complex chips may include multiple TAPs, and the target
1623 config file may need to define them all before OpenOCD
1624 can talk to the chip.
1625 For example, some phone chips have JTAG scan chains that include
1626 an ARM core for operating system use, a DSP,
1627 another ARM core embedded in an image processing engine,
1628 and other processing engines.
1630 @subsection Default Value Boiler Plate Code
1632 All target configuration files should start with code like this,
1633 letting board config files express environment-specific
1634 differences in how things should be set up.
1636 @example
1637 # Boards may override chip names, perhaps based on role,
1638 # but the default should match what the vendor uses
1639 if @{ [info exists CHIPNAME] @} @{
1641 @} else @{
1642 set _CHIPNAME sam7x256
1643 @}
1645 # ONLY use ENDIAN with targets that can change it.
1646 if @{ [info exists ENDIAN] @} @{
1647 set _ENDIAN $ENDIAN
1648 @} else @{
1649 set _ENDIAN little
1650 @}
1652 # TAP identifiers may change as chips mature, for example with
1653 # new revision fields (the "3" here). Pick a good default; you
1654 # can pass several such identifiers to the "jtag newtap" command.
1655 if @{ [info exists CPUTAPID ] @} @{
1657 @} else @{
1658 set _CPUTAPID 0x3f0f0f0f
1659 @}
1660 @end example
1661 @c but 0x3f0f0f0f is for an str73x part ...
1663 @emph{Remember:} Board config files may include multiple target
1664 config files, or the same target file multiple times
1665 (changing at least @code{CHIPNAME}).
1667 Likewise, the target configuration file should define
1668 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1669 use it later on when defining debug targets:
1671 @example
1673 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1674 @end example
1676 @subsection Adding TAPs to the Scan Chain
1677 After the ``defaults'' are set up,
1678 add the TAPs on each chip to the JTAG scan chain.
1679 @xref{TAP Declaration}, and the naming convention
1680 for taps.
1682 In the simplest case the chip has only one TAP,
1683 probably for a CPU or FPGA.
1684 The config file for the Atmel AT91SAM7X256
1685 looks (in part) like this:
1687 @example
1688 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1689 @end example
1691 A board with two such at91sam7 chips would be able
1692 to source such a config file twice, with different
1693 values for @code{CHIPNAME}, so
1694 it adds a different TAP each time.
1696 If there are nonzero @option{-expected-id} values,
1697 OpenOCD attempts to verify the actual tap id against those values.
1698 It will issue error messages if there is mismatch, which
1699 can help to pinpoint problems in OpenOCD configurations.
1701 @example
1702 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1703 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1704 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1705 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1706 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1707 @end example
1709 There are more complex examples too, with chips that have
1710 multiple TAPs. Ones worth looking at include:
1712 @itemize
1713 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1714 plus a JRC to enable them
1715 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1716 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1717 is not currently used)
1718 @end itemize
1720 @subsection Add CPU targets
1722 After adding a TAP for a CPU, you should set it up so that
1723 GDB and other commands can use it.
1724 @xref{CPU Configuration}.
1725 For the at91sam7 example above, the command can look like this;
1726 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1727 to little endian, and this chip doesn't support changing that.
1729 @example
1731 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1732 @end example
1734 Work areas are small RAM areas associated with CPU targets.
1735 They are used by OpenOCD to speed up downloads,
1736 and to download small snippets of code to program flash chips.
1737 If the chip includes a form of ``on-chip-ram'' - and many do - define
1738 a work area if you can.
1739 Again using the at91sam7 as an example, this can look like:
1741 @example
1742 $_TARGETNAME configure -work-area-phys 0x00200000 \
1743 -work-area-size 0x4000 -work-area-backup 0
1744 @end example
1746 @anchor{Define CPU targets working in SMP}
1747 @subsection Define CPU targets working in SMP
1748 @cindex SMP
1749 After setting targets, you can define a list of targets working in SMP.
1751 @example
1752 set _TARGETNAME_1 $_CHIPNAME.cpu1
1753 set _TARGETNAME_2 $_CHIPNAME.cpu2
1754 target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap \
1755 -coreid 0 -dbgbase $_DAP_DBG1
1756 target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap \
1757 -coreid 1 -dbgbase $_DAP_DBG2
1758 #define 2 targets working in smp.
1759 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1760 @end example
1761 In the above example on cortex_a8, 2 cpus are working in SMP.
1762 In SMP only one GDB instance is created and :
1763 @itemize @bullet
1764 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1765 @item halt command triggers the halt of all targets in the list.
1766 @item resume command triggers the write context and the restart of all targets in the list.
1767 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1768 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1769 displayed by the GDB session @pxref{Using openocd SMP with GDB}.
1770 @end itemize
1772 The SMP behaviour can be disabled/enabled dynamically. On cortex_a8 following
1773 command have been implemented.
1774 @itemize @bullet
1775 @item cortex_a8 smp_on : enable SMP mode, behaviour is as described above.
1776 @item cortex_a8 smp_off : disable SMP mode, the current target is the one
1777 displayed in the GDB session, only this target is now controlled by GDB
1778 session. This behaviour is useful during system boot up.
1779 @item cortex_a8 smp_gdb : display/fix the core id displayed in GDB session see
1780 following example.
1781 @end itemize
1783 @example
1784 >cortex_a8 smp_gdb
1785 gdb coreid 0 -> -1
1786 #0 : coreid 0 is displayed to GDB ,
1787 #-> -1 : next resume triggers a real resume
1788 > cortex_a8 smp_gdb 1
1789 gdb coreid 0 -> 1
1790 #0 :coreid 0 is displayed to GDB ,
1791 #->1 : next resume displays coreid 1 to GDB
1792 > resume
1793 > cortex_a8 smp_gdb
1794 gdb coreid 1 -> 1
1795 #1 :coreid 1 is displayed to GDB ,
1796 #->1 : next resume displays coreid 1 to GDB
1797 > cortex_a8 smp_gdb -1
1798 gdb coreid 1 -> -1
1799 #1 :coreid 1 is displayed to GDB,
1800 #->-1 : next resume triggers a real resume
1801 @end example
1804 @subsection Chip Reset Setup
1806 As a rule, you should put the @command{reset_config} command
1807 into the board file. Most things you think you know about a
1808 chip can be tweaked by the board.
1810 Some chips have specific ways the TRST and SRST signals are
1811 managed. In the unusual case that these are @emph{chip specific}
1812 and can never be changed by board wiring, they could go here.
1813 For example, some chips can't support JTAG debugging without
1814 both signals.
1816 Provide a @code{reset-assert} event handler if you can.
1817 Such a handler uses JTAG operations to reset the target,
1818 letting this target config be used in systems which don't
1819 provide the optional SRST signal, or on systems where you
1820 don't want to reset all targets at once.
1821 Such a handler might write to chip registers to force a reset,
1822 use a JRC to do that (preferable -- the target may be wedged!),
1823 or force a watchdog timer to trigger.
1824 (For Cortex-M3 targets, this is not necessary. The target
1825 driver knows how to use trigger an NVIC reset when SRST is
1826 not available.)
1828 Some chips need special attention during reset handling if
1829 they're going to be used with JTAG.
1830 An example might be needing to send some commands right
1831 after the target's TAP has been reset, providing a
1832 @code{reset-deassert-post} event handler that writes a chip
1833 register to report that JTAG debugging is being done.
1834 Another would be reconfiguring the watchdog so that it stops
1835 counting while the core is halted in the debugger.
1837 JTAG clocking constraints often change during reset, and in
1838 some cases target config files (rather than board config files)
1839 are the right places to handle some of those issues.
1840 For example, immediately after reset most chips run using a
1841 slower clock than they will use later.
1842 That means that after reset (and potentially, as OpenOCD
1843 first starts up) they must use a slower JTAG clock rate
1844 than they will use later.
1845 @xref{JTAG Speed}.
1847 @quotation Important
1848 When you are debugging code that runs right after chip
1849 reset, getting these issues right is critical.
1850 In particular, if you see intermittent failures when
1851 OpenOCD verifies the scan chain after reset,
1852 look at how you are setting up JTAG clocking.
1853 @end quotation
1855 @anchor{The init_targets procedure}
1856 @subsection The init_targets procedure
1857 @cindex init_targets procedure
1859 Target config files can either be ``linear'' (script executed line-by-line when parsed in configuration stage,
1860 @xref{Configuration Stage},) or they can contain a special procedure called @code{init_targets}, which will be executed
1861 when entering run stage (after parsing all config files or after @code{init} command, @xref{Entering the Run Stage}.)
1862 Such procedure can be overriden by ``next level'' script (which sources the original). This concept faciliates code
1863 reuse when basic target config files provide generic configuration procedures and @code{init_targets} procedure, which
1864 can then be sourced and enchanced or changed in a ``more specific'' target config file. This is not possible with
1865 ``linear'' config scripts, because sourcing them executes every initialization commands they provide.
1867 @example
1868 ### generic_file.cfg ###
1870 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1871 # basic initialization procedure ...
1872 @}
1874 proc init_targets @{@} @{
1875 # initializes generic chip with 4kB of flash and 1kB of RAM
1876 setup_my_chip MY_GENERIC_CHIP 4096 1024
1877 @}
1879 ### specific_file.cfg ###
1881 source [find target/generic_file.cfg]
1883 proc init_targets @{@} @{
1884 # initializes specific chip with 128kB of flash and 64kB of RAM
1885 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1886 @}
1887 @end example
1889 The easiest way to convert ``linear'' config files to @code{init_targets} version is to enclose every line of ``code''
1890 (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1892 For an example of this scheme see LPC2000 target config files.
1894 The @code{init_boards} procedure is a similar concept concerning board config files (@xref{The init_board procedure}.)
1896 @subsection ARM Core Specific Hacks
1898 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1899 special high speed download features - enable it.
1901 If present, the MMU, the MPU and the CACHE should be disabled.
1903 Some ARM cores are equipped with trace support, which permits
1904 examination of the instruction and data bus activity. Trace
1905 activity is controlled through an ``Embedded Trace Module'' (ETM)
1906 on one of the core's scan chains. The ETM emits voluminous data
1907 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
1908 If you are using an external trace port,
1909 configure it in your board config file.
1910 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1911 configure it in your target config file.
1913 @example
1914 etm config $_TARGETNAME 16 normal full etb
1915 etb config $_TARGETNAME $_CHIPNAME.etb
1916 @end example
1918 @subsection Internal Flash Configuration
1920 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1922 @b{Never ever} in the ``target configuration file'' define any type of
1923 flash that is external to the chip. (For example a BOOT flash on
1924 Chip Select 0.) Such flash information goes in a board file - not
1925 the TARGET (chip) file.
1927 Examples:
1928 @itemize @bullet
1929 @item at91sam7x256 - has 256K flash YES enable it.
1930 @item str912 - has flash internal YES enable it.
1931 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1932 @item pxa270 - again - CS0 flash - it goes in the board file.
1933 @end itemize
1935 @anchor{Translating Configuration Files}
1936 @section Translating Configuration Files
1937 @cindex translation
1938 If you have a configuration file for another hardware debugger
1939 or toolset (Abatron, BDI2000, BDI3000, CCS,
1940 Lauterbach, Segger, Macraigor, etc.), translating
1941 it into OpenOCD syntax is often quite straightforward. The most tricky
1942 part of creating a configuration script is oftentimes the reset init
1943 sequence where e.g. PLLs, DRAM and the like is set up.
1945 One trick that you can use when translating is to write small
1946 Tcl procedures to translate the syntax into OpenOCD syntax. This
1947 can avoid manual translation errors and make it easier to
1948 convert other scripts later on.
1950 Example of transforming quirky arguments to a simple search and
1951 replace job:
1953 @example
1954 # Lauterbach syntax(?)
1955 #
1956 # Data.Set c15:0x042f %long 0x40000015
1957 #
1958 # OpenOCD syntax when using procedure below.
1959 #
1960 # setc15 0x01 0x00050078
1962 proc setc15 @{regs value@} @{
1963 global TARGETNAME
1965 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
1967 arm mcr 15 [expr ($regs>>12)&0x7] \
1968 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
1969 [expr ($regs>>8)&0x7] $value
1970 @}
1971 @end example
1975 @node Daemon Configuration
1976 @chapter Daemon Configuration
1977 @cindex initialization
1978 The commands here are commonly found in the openocd.cfg file and are
1979 used to specify what TCP/IP ports are used, and how GDB should be
1980 supported.
1982 @anchor{Configuration Stage}
1983 @section Configuration Stage
1984 @cindex configuration stage
1985 @cindex config command
1987 When the OpenOCD server process starts up, it enters a
1988 @emph{configuration stage} which is the only time that
1989 certain commands, @emph{configuration commands}, may be issued.
1990 Normally, configuration commands are only available
1991 inside startup scripts.
1993 In this manual, the definition of a configuration command is
1994 presented as a @emph{Config Command}, not as a @emph{Command}
1995 which may be issued interactively.
1996 The runtime @command{help} command also highlights configuration
1997 commands, and those which may be issued at any time.
1999 Those configuration commands include declaration of TAPs,
2000 flash banks,
2001 the interface used for JTAG communication,
2002 and other basic setup.
2003 The server must leave the configuration stage before it
2004 may access or activate TAPs.
2005 After it leaves this stage, configuration commands may no
2006 longer be issued.
2008 @anchor{Entering the Run Stage}
2009 @section Entering the Run Stage
2011 The first thing OpenOCD does after leaving the configuration
2012 stage is to verify that it can talk to the scan chain
2013 (list of TAPs) which has been configured.
2014 It will warn if it doesn't find TAPs it expects to find,
2015 or finds TAPs that aren't supposed to be there.
2016 You should see no errors at this point.
2017 If you see errors, resolve them by correcting the
2018 commands you used to configure the server.
2019 Common errors include using an initial JTAG speed that's too
2020 fast, and not providing the right IDCODE values for the TAPs
2021 on the scan chain.
2023 Once OpenOCD has entered the run stage, a number of commands
2024 become available.
2025 A number of these relate to the debug targets you may have declared.
2026 For example, the @command{mww} command will not be available until
2027 a target has been successfuly instantiated.
2028 If you want to use those commands, you may need to force
2029 entry to the run stage.
2031 @deffn {Config Command} init
2032 This command terminates the configuration stage and
2033 enters the run stage. This helps when you need to have
2034 the startup scripts manage tasks such as resetting the target,
2035 programming flash, etc. To reset the CPU upon startup, add "init" and
2036 "reset" at the end of the config script or at the end of the OpenOCD
2037 command line using the @option{-c} command line switch.
2039 If this command does not appear in any startup/configuration file
2040 OpenOCD executes the command for you after processing all
2041 configuration files and/or command line options.
2043 @b{NOTE:} This command normally occurs at or near the end of your
2044 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2045 targets ready. For example: If your openocd.cfg file needs to
2046 read/write memory on your target, @command{init} must occur before
2047 the memory read/write commands. This includes @command{nand probe}.
2048 @end deffn
2050 @deffn {Overridable Procedure} jtag_init
2051 This is invoked at server startup to verify that it can talk
2052 to the scan chain (list of TAPs) which has been configured.
2054 The default implementation first tries @command{jtag arp_init},
2055 which uses only a lightweight JTAG reset before examining the
2056 scan chain.
2057 If that fails, it tries again, using a harder reset
2058 from the overridable procedure @command{init_reset}.
2060 Implementations must have verified the JTAG scan chain before
2061 they return.
2062 This is done by calling @command{jtag arp_init}
2063 (or @command{jtag arp_init-reset}).
2064 @end deffn
2066 @anchor{TCP/IP Ports}
2067 @section TCP/IP Ports
2068 @cindex TCP port
2069 @cindex server
2070 @cindex port
2071 @cindex security
2072 The OpenOCD server accepts remote commands in several syntaxes.
2073 Each syntax uses a different TCP/IP port, which you may specify
2074 only during configuration (before those ports are opened).
2076 For reasons including security, you may wish to prevent remote
2077 access using one or more of these ports.
2078 In such cases, just specify the relevant port number as zero.
2079 If you disable all access through TCP/IP, you will need to
2080 use the command line @option{-pipe} option.
2082 @deffn {Command} gdb_port [number]
2083 @cindex GDB server
2084 Normally gdb listens to a TCP/IP port, but GDB can also
2085 communicate via pipes(stdin/out or named pipes). The name
2086 "gdb_port" stuck because it covers probably more than 90% of
2087 the normal use cases.
2089 No arguments reports GDB port. "pipe" means listen to stdin
2090 output to stdout, an integer is base port number, "disable"
2091 disables the gdb server.
2093 When using "pipe", also use log_output to redirect the log
2094 output to a file so as not to flood the stdin/out pipes.
2096 The -p/--pipe option is deprecated and a warning is printed
2097 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2099 Any other string is interpreted as named pipe to listen to.
2100 Output pipe is the same name as input pipe, but with 'o' appended,
2101 e.g. /var/gdb, /var/gdbo.
2103 The GDB port for the first target will be the base port, the
2104 second target will listen on gdb_port + 1, and so on.
2105 When not specified during the configuration stage,
2106 the port @var{number} defaults to 3333.
2107 @end deffn
2109 @deffn {Command} tcl_port [number]
2110 Specify or query the port used for a simplified RPC
2111 connection that can be used by clients to issue TCL commands and get the
2112 output from the Tcl engine.
2113 Intended as a machine interface.
2114 When not specified during the configuration stage,
2115 the port @var{number} defaults to 6666.
2117 @end deffn
2119 @deffn {Command} telnet_port [number]
2120 Specify or query the
2121 port on which to listen for incoming telnet connections.
2122 This port is intended for interaction with one human through TCL commands.
2123 When not specified during the configuration stage,
2124 the port @var{number} defaults to 4444.
2125 When specified as zero, this port is not activated.
2126 @end deffn
2128 @anchor{GDB Configuration}
2129 @section GDB Configuration
2130 @cindex GDB
2131 @cindex GDB configuration
2132 You can reconfigure some GDB behaviors if needed.
2133 The ones listed here are static and global.
2134 @xref{Target Configuration}, about configuring individual targets.
2135 @xref{Target Events}, about configuring target-specific event handling.
2137 @anchor{gdb_breakpoint_override}
2138 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2139 Force breakpoint type for gdb @command{break} commands.
2140 This option supports GDB GUIs which don't
2141 distinguish hard versus soft breakpoints, if the default OpenOCD and
2142 GDB behaviour is not sufficient. GDB normally uses hardware
2143 breakpoints if the memory map has been set up for flash regions.
2144 @end deffn
2146 @anchor{gdb_flash_program}
2147 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2148 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2149 vFlash packet is received.
2150 The default behaviour is @option{enable}.
2151 @end deffn
2153 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2154 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2155 requested. GDB will then know when to set hardware breakpoints, and program flash
2156 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2157 for flash programming to work.
2158 Default behaviour is @option{enable}.
2159 @xref{gdb_flash_program}.
2160 @end deffn
2162 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2163 Specifies whether data aborts cause an error to be reported
2164 by GDB memory read packets.
2165 The default behaviour is @option{disable};
2166 use @option{enable} see these errors reported.
2167 @end deffn
2169 @anchor{Event Polling}
2170 @section Event Polling
2172 Hardware debuggers are parts of asynchronous systems,
2173 where significant events can happen at any time.
2174 The OpenOCD server needs to detect some of these events,
2175 so it can report them to through TCL command line
2176 or to GDB.
2178 Examples of such events include:
2180 @itemize
2181 @item One of the targets can stop running ... maybe it triggers
2182 a code breakpoint or data watchpoint, or halts itself.
2183 @item Messages may be sent over ``debug message'' channels ... many
2184 targets support such messages sent over JTAG,
2185 for receipt by the person debugging or tools.
2186 @item Loss of power ... some adapters can detect these events.
2187 @item Resets not issued through JTAG ... such reset sources
2188 can include button presses or other system hardware, sometimes
2189 including the target itself (perhaps through a watchdog).
2190 @item Debug instrumentation sometimes supports event triggering
2191 such as ``trace buffer full'' (so it can quickly be emptied)
2192 or other signals (to correlate with code behavior).
2193 @end itemize
2195 None of those events are signaled through standard JTAG signals.
2196 However, most conventions for JTAG connectors include voltage
2197 level and system reset (SRST) signal detection.
2198 Some connectors also include instrumentation signals, which
2199 can imply events when those signals are inputs.
2201 In general, OpenOCD needs to periodically check for those events,
2202 either by looking at the status of signals on the JTAG connector
2203 or by sending synchronous ``tell me your status'' JTAG requests
2204 to the various active targets.
2205 There is a command to manage and monitor that polling,
2206 which is normally done in the background.
2208 @deffn Command poll [@option{on}|@option{off}]
2209 Poll the current target for its current state.
2210 (Also, @pxref{target curstate}.)
2211 If that target is in debug mode, architecture
2212 specific information about the current state is printed.
2213 An optional parameter
2214 allows background polling to be enabled and disabled.
2216 You could use this from the TCL command shell, or
2217 from GDB using @command{monitor poll} command.
2218 Leave background polling enabled while you're using GDB.
2219 @example
2220 > poll
2221 background polling: on
2222 target state: halted
2223 target halted in ARM state due to debug-request, \
2224 current mode: Supervisor
2225 cpsr: 0x800000d3 pc: 0x11081bfc
2226 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2227 >
2228 @end example
2229 @end deffn
2231 @node Debug Adapter Configuration
2232 @chapter Debug Adapter Configuration
2233 @cindex config file, interface
2234 @cindex interface config file
2236 Correctly installing OpenOCD includes making your operating system give
2237 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2238 are used to select which one is used, and to configure how it is used.
2240 @quotation Note
2241 Because OpenOCD started out with a focus purely on JTAG, you may find
2242 places where it wrongly presumes JTAG is the only transport protocol
2243 in use. Be aware that recent versions of OpenOCD are removing that
2244 limitation. JTAG remains more functional than most other transports.
2245 Other transports do not support boundary scan operations, or may be
2246 specific to a given chip vendor. Some might be usable only for
2247 programming flash memory, instead of also for debugging.
2248 @end quotation
2250 Debug Adapters/Interfaces/Dongles are normally configured
2251 through commands in an interface configuration
2252 file which is sourced by your @file{openocd.cfg} file, or
2253 through a command line @option{-f interface/....cfg} option.
2255 @example
2256 source [find interface/olimex-jtag-tiny.cfg]
2257 @end example
2259 These commands tell
2260 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2261 A few cases are so simple that you only need to say what driver to use:
2263 @example
2264 # jlink interface
2265 interface jlink
2266 @end example
2268 Most adapters need a bit more configuration than that.
2271 @section Interface Configuration
2273 The interface command tells OpenOCD what type of debug adapter you are
2274 using. Depending on the type of adapter, you may need to use one or
2275 more additional commands to further identify or configure the adapter.
2277 @deffn {Config Command} {interface} name
2278 Use the interface driver @var{name} to connect to the
2279 target.
2280 @end deffn
2282 @deffn Command {interface_list}
2283 List the debug adapter drivers that have been built into
2284 the running copy of OpenOCD.
2285 @end deffn
2286 @deffn Command {interface transports} transport_name+
2287 Specifies the transports supported by this debug adapter.
2288 The adapter driver builds-in similar knowledge; use this only
2289 when external configuration (such as jumpering) changes what
2290 the hardware can support.
2291 @end deffn
2295 @deffn Command {adapter_name}
2296 Returns the name of the debug adapter driver being used.
2297 @end deffn
2299 @section Interface Drivers
2301 Each of the interface drivers listed here must be explicitly
2302 enabled when OpenOCD is configured, in order to be made
2303 available at run time.
2305 @deffn {Interface Driver} {amt_jtagaccel}
2306 Amontec Chameleon in its JTAG Accelerator configuration,
2307 connected to a PC's EPP mode parallel port.
2308 This defines some driver-specific commands:
2310 @deffn {Config Command} {parport_port} number
2311 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2312 the number of the @file{/dev/parport} device.
2313 @end deffn
2315 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2316 Displays status of RTCK option.
2317 Optionally sets that option first.
2318 @end deffn
2319 @end deffn
2321 @deffn {Interface Driver} {arm-jtag-ew}
2322 Olimex ARM-JTAG-EW USB adapter
2323 This has one driver-specific command:
2325 @deffn Command {armjtagew_info}
2326 Logs some status
2327 @end deffn
2328 @end deffn
2330 @deffn {Interface Driver} {at91rm9200}
2331 Supports bitbanged JTAG from the local system,
2332 presuming that system is an Atmel AT91rm9200
2333 and a specific set of GPIOs is used.
2334 @c command: at91rm9200_device NAME
2335 @c chooses among list of bit configs ... only one option
2336 @end deffn
2338 @deffn {Interface Driver} {dummy}
2339 A dummy software-only driver for debugging.
2340 @end deffn
2342 @deffn {Interface Driver} {ep93xx}
2343 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2344 @end deffn
2346 @deffn {Interface Driver} {ft2232}
2347 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2348 These interfaces have several commands, used to configure the driver
2349 before initializing the JTAG scan chain:
2351 @deffn {Config Command} {ft2232_device_desc} description
2352 Provides the USB device description (the @emph{iProduct string})
2353 of the FTDI FT2232 device. If not
2354 specified, the FTDI default value is used. This setting is only valid
2355 if compiled with FTD2XX support.
2356 @end deffn
2358 @deffn {Config Command} {ft2232_serial} serial-number
2359 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2360 in case the vendor provides unique IDs and more than one FT2232 device
2361 is connected to the host.
2362 If not specified, serial numbers are not considered.
2363 (Note that USB serial numbers can be arbitrary Unicode strings,
2364 and are not restricted to containing only decimal digits.)
2365 @end deffn
2367 @deffn {Config Command} {ft2232_layout} name
2368 Each vendor's FT2232 device can use different GPIO signals
2369 to control output-enables, reset signals, and LEDs.
2370 Currently valid layout @var{name} values include:
2371 @itemize @minus
2372 @item @b{axm0432_jtag} Axiom AXM-0432
2373 @item @b{comstick} Hitex STR9 comstick
2374 @item @b{cortino} Hitex Cortino JTAG interface
2375 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
2376 either for the local Cortex-M3 (SRST only)
2377 or in a passthrough mode (neither SRST nor TRST)
2378 This layout can not support the SWO trace mechanism, and should be
2379 used only for older boards (before rev C).
2380 @item @b{luminary_icdi} This layout should be used with most Luminary
2381 eval boards, including Rev C LM3S811 eval boards and the eponymous
2382 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2383 to debug some other target. It can support the SWO trace mechanism.
2384 @item @b{flyswatter} Tin Can Tools Flyswatter
2385 @item @b{icebear} ICEbear JTAG adapter from Section 5
2386 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2387 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2388 @item @b{m5960} American Microsystems M5960
2389 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2390 @item @b{oocdlink} OOCDLink
2391 @c oocdlink ~= jtagkey_prototype_v1
2392 @item @b{redbee-econotag} Integrated with a Redbee development board.
2393 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2394 @item @b{sheevaplug} Marvell Sheevaplug development kit
2395 @item @b{signalyzer} Xverve Signalyzer
2396 @item @b{stm32stick} Hitex STM32 Performance Stick
2397 @item @b{turtelizer2} egnite Software turtelizer2
2398 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2399 @end itemize
2400 @end deffn
2402 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2403 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2404 default values are used.
2405 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2406 @example
2407 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2408 @end example
2409 @end deffn
2411 @deffn {Config Command} {ft2232_latency} ms
2412 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2413 ft2232_read() fails to return the expected number of bytes. This can be caused by
2414 USB communication delays and has proved hard to reproduce and debug. Setting the
2415 FT2232 latency timer to a larger value increases delays for short USB packets but it
2416 also reduces the risk of timeouts before receiving the expected number of bytes.
2417 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2418 @end deffn
2420 For example, the interface config file for a
2421 Turtelizer JTAG Adapter looks something like this:
2423 @example
2424 interface ft2232
2425 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2426 ft2232_layout turtelizer2
2427 ft2232_vid_pid 0x0403 0xbdc8
2428 @end example
2429 @end deffn
2431 @deffn {Interface Driver} {remote_bitbang}
2432 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2433 with a remote process and sends ASCII encoded bitbang requests to that process
2434 instead of directly driving JTAG.
2436 The remote_bitbang driver is useful for debugging software running on
2437 processors which are being simulated.
2439 @deffn {Config Command} {remote_bitbang_port} number
2440 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2441 sockets instead of TCP.
2442 @end deffn
2444 @deffn {Config Command} {remote_bitbang_host} hostname
2445 Specifies the hostname of the remote process to connect to using TCP, or the
2446 name of the UNIX socket to use if remote_bitbang_port is 0.
2447 @end deffn
2449 For example, to connect remotely via TCP to the host foobar you might have
2450 something like:
2452 @example
2453 interface remote_bitbang
2454 remote_bitbang_port 3335
2455 remote_bitbang_host foobar
2456 @end example
2458 To connect to another process running locally via UNIX sockets with socket
2459 named mysocket:
2461 @example
2462 interface remote_bitbang
2463 remote_bitbang_port 0
2464 remote_bitbang_host mysocket
2465 @end example
2466 @end deffn
2468 @deffn {Interface Driver} {usb_blaster}
2469 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2470 for FTDI chips. These interfaces have several commands, used to
2471 configure the driver before initializing the JTAG scan chain:
2473 @deffn {Config Command} {usb_blaster_device_desc} description
2474 Provides the USB device description (the @emph{iProduct string})
2475 of the FTDI FT245 device. If not
2476 specified, the FTDI default value is used. This setting is only valid
2477 if compiled with FTD2XX support.
2478 @end deffn
2480 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2481 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2482 default values are used.
2483 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2484 Altera USB-Blaster (default):
2485 @example
2486 usb_blaster_vid_pid 0x09FB 0x6001
2487 @end example
2488 The following VID/PID is for Kolja Waschk's USB JTAG:
2489 @example
2490 usb_blaster_vid_pid 0x16C0 0x06AD
2491 @end example
2492 @end deffn
2494 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2495 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2496 female JTAG header). These pins can be used as SRST and/or TRST provided the
2497 appropriate connections are made on the target board.
2499 For example, to use pin 6 as SRST (as with an AVR board):
2500 @example
2501 $_TARGETNAME configure -event reset-assert \
2502 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2503 @end example
2504 @end deffn
2506 @end deffn
2508 @deffn {Interface Driver} {gw16012}
2509 Gateworks GW16012 JTAG programmer.
2510 This has one driver-specific command:
2512 @deffn {Config Command} {parport_port} [port_number]
2513 Display either the address of the I/O port
2514 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2515 If a parameter is provided, first switch to use that port.
2516 This is a write-once setting.
2517 @end deffn
2518 @end deffn
2520 @deffn {Interface Driver} {jlink}
2521 Segger jlink USB adapter
2522 @c command: jlink caps
2523 @c dumps jlink capabilities
2524 @c command: jlink config
2525 @c access J-Link configurationif no argument this will dump the config
2526 @c command: jlink config kickstart [val]
2527 @c set Kickstart power on JTAG-pin 19.
2528 @c command: jlink config mac_address [ff:ff:ff:ff:ff:ff]
2529 @c set the MAC Address
2530 @c command: jlink config ip [A.B.C.D[/E] [F.G.H.I]]
2531 @c set the ip address of the J-Link Pro, "
2532 @c where A.B.C.D is the ip,
2533 @c E the bit of the subnet mask
2534 @c F.G.H.I the subnet mask
2535 @c command: jlink config reset
2536 @c reset the current config
2537 @c command: jlink config save
2538 @c save the current config
2539 @c command: jlink config usb_address [0x00 to 0x03 or 0xff]
2540 @c set the USB-Address,
2541 @c This will change the product id
2542 @c command: jlink info
2543 @c dumps status
2544 @c command: jlink hw_jtag (2|3)
2545 @c sets version 2 or 3
2546 @c command: jlink pid
2547 @c set the pid of the interface we want to use
2548 @end deffn
2550 @deffn {Interface Driver} {parport}
2551 Supports PC parallel port bit-banging cables:
2552 Wigglers, PLD download cable, and more.
2553 These interfaces have several commands, used to configure the driver
2554 before initializing the JTAG scan chain:
2556 @deffn {Config Command} {parport_cable} name
2557 Set the layout of the parallel port cable used to connect to the target.
2558 This is a write-once setting.
2559 Currently valid cable @var{name} values include:
2561 @itemize @minus
2562 @item @b{altium} Altium Universal JTAG cable.
2563 @item @b{arm-jtag} Same as original wiggler except SRST and
2564 TRST connections reversed and TRST is also inverted.
2565 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2566 in configuration mode. This is only used to
2567 program the Chameleon itself, not a connected target.
2568 @item @b{dlc5} The Xilinx Parallel cable III.
2569 @item @b{flashlink} The ST Parallel cable.
2570 @item @b{lattice} Lattice ispDOWNLOAD Cable
2571 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2572 some versions of
2573 Amontec's Chameleon Programmer. The new version available from
2574 the website uses the original Wiggler layout ('@var{wiggler}')
2575 @item @b{triton} The parallel port adapter found on the
2576 ``Karo Triton 1 Development Board''.
2577 This is also the layout used by the HollyGates design
2578 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2579 @item @b{wiggler} The original Wiggler layout, also supported by
2580 several clones, such as the Olimex ARM-JTAG
2581 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2582 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2583 @end itemize
2584 @end deffn
2586 @deffn {Config Command} {parport_port} [port_number]
2587 Display either the address of the I/O port
2588 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2589 If a parameter is provided, first switch to use that port.
2590 This is a write-once setting.
2592 When using PPDEV to access the parallel port, use the number of the parallel port:
2593 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2594 you may encounter a problem.
2595 @end deffn
2597 @deffn Command {parport_toggling_time} [nanoseconds]
2598 Displays how many nanoseconds the hardware needs to toggle TCK;
2599 the parport driver uses this value to obey the
2600 @command{adapter_khz} configuration.
2601 When the optional @var{nanoseconds} parameter is given,
2602 that setting is changed before displaying the current value.
2604 The default setting should work reasonably well on commodity PC hardware.
2605 However, you may want to calibrate for your specific hardware.
2606 @quotation Tip
2607 To measure the toggling time with a logic analyzer or a digital storage
2608 oscilloscope, follow the procedure below:
2609 @example
2610 > parport_toggling_time 1000
2611 > adapter_khz 500
2612 @end example
2613 This sets the maximum JTAG clock speed of the hardware, but
2614 the actual speed probably deviates from the requested 500 kHz.
2615 Now, measure the time between the two closest spaced TCK transitions.
2616 You can use @command{runtest 1000} or something similar to generate a
2617 large set of samples.
2618 Update the setting to match your measurement:
2619 @example
2620 > parport_toggling_time <measured nanoseconds>
2621 @end example
2622 Now the clock speed will be a better match for @command{adapter_khz rate}
2623 commands given in OpenOCD scripts and event handlers.
2625 You can do something similar with many digital multimeters, but note
2626 that you'll probably need to run the clock continuously for several
2627 seconds before it decides what clock rate to show. Adjust the
2628 toggling time up or down until the measured clock rate is a good
2629 match for the adapter_khz rate you specified; be conservative.
2630 @end quotation
2631 @end deffn
2633 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2634 This will configure the parallel driver to write a known
2635 cable-specific value to the parallel interface on exiting OpenOCD.
2636 @end deffn
2638 For example, the interface configuration file for a
2639 classic ``Wiggler'' cable on LPT2 might look something like this:
2641 @example
2642 interface parport
2643 parport_port 0x278
2644 parport_cable wiggler
2645 @end example
2646 @end deffn
2648 @deffn {Interface Driver} {presto}
2649 ASIX PRESTO USB JTAG programmer.
2650 @deffn {Config Command} {presto_serial} serial_string
2651 Configures the USB serial number of the Presto device to use.
2652 @end deffn
2653 @end deffn
2655 @deffn {Interface Driver} {rlink}
2656 Raisonance RLink USB adapter
2657 @end deffn
2659 @deffn {Interface Driver} {usbprog}
2660 usbprog is a freely programmable USB adapter.
2661 @end deffn
2663 @deffn {Interface Driver} {vsllink}
2664 vsllink is part of Versaloon which is a versatile USB programmer.
2666 @quotation Note
2667 This defines quite a few driver-specific commands,
2668 which are not currently documented here.
2669 @end quotation
2670 @end deffn
2672 @deffn {Interface Driver} {stlink}
2673 ST Micro ST-LINK adapter.
2674 @end deffn
2676 @deffn {Interface Driver} {ZY1000}
2677 This is the Zylin ZY1000 JTAG debugger.
2678 @end deffn
2680 @quotation Note
2681 This defines some driver-specific commands,
2682 which are not currently documented here.
2683 @end quotation
2685 @deffn Command power [@option{on}|@option{off}]
2686 Turn power switch to target on/off.
2687 No arguments: print status.
2688 @end deffn
2690 @section Transport Configuration
2691 @cindex Transport
2692 As noted earlier, depending on the version of OpenOCD you use,
2693 and the debug adapter you are using,
2694 several transports may be available to
2695 communicate with debug targets (or perhaps to program flash memory).
2696 @deffn Command {transport list}
2697 displays the names of the transports supported by this
2698 version of OpenOCD.
2699 @end deffn
2701 @deffn Command {transport select} transport_name
2702 Select which of the supported transports to use in this OpenOCD session.
2703 The transport must be supported by the debug adapter hardware and by the
2704 version of OPenOCD you are using (including the adapter's driver).
2705 No arguments: returns name of session's selected transport.
2706 @end deffn
2708 @subsection JTAG Transport
2709 @cindex JTAG
2710 JTAG is the original transport supported by OpenOCD, and most
2711 of the OpenOCD commands support it.
2712 JTAG transports expose a chain of one or more Test Access Points (TAPs),
2713 each of which must be explicitly declared.
2714 JTAG supports both debugging and boundary scan testing.
2715 Flash programming support is built on top of debug support.
2716 @subsection SWD Transport
2717 @cindex SWD
2718 @cindex Serial Wire Debug
2719 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
2720 Debug Access Point (DAP, which must be explicitly declared.
2721 (SWD uses fewer signal wires than JTAG.)
2722 SWD is debug-oriented, and does not support boundary scan testing.
2723 Flash programming support is built on top of debug support.
2724 (Some processors support both JTAG and SWD.)
2725 @deffn Command {swd newdap} ...
2726 Declares a single DAP which uses SWD transport.
2727 Parameters are currently the same as "jtag newtap" but this is
2728 expected to change.
2729 @end deffn
2730 @deffn Command {swd wcr trn prescale}
2731 Updates TRN (turnaraound delay) and prescaling.fields of the
2732 Wire Control Register (WCR).
2733 No parameters: displays current settings.
2734 @end deffn
2736 @subsection SPI Transport
2737 @cindex SPI
2738 @cindex Serial Peripheral Interface
2739 The Serial Peripheral Interface (SPI) is a general purpose transport
2740 which uses four wire signaling. Some processors use it as part of a
2741 solution for flash programming.
2743 @anchor{JTAG Speed}
2744 @section JTAG Speed
2745 JTAG clock setup is part of system setup.
2746 It @emph{does not belong with interface setup} since any interface
2747 only knows a few of the constraints for the JTAG clock speed.
2748 Sometimes the JTAG speed is
2749 changed during the target initialization process: (1) slow at
2750 reset, (2) program the CPU clocks, (3) run fast.
2751 Both the "slow" and "fast" clock rates are functions of the
2752 oscillators used, the chip, the board design, and sometimes
2753 power management software that may be active.
2755 The speed used during reset, and the scan chain verification which
2756 follows reset, can be adjusted using a @code{reset-start}
2757 target event handler.
2758 It can then be reconfigured to a faster speed by a
2759 @code{reset-init} target event handler after it reprograms those
2760 CPU clocks, or manually (if something else, such as a boot loader,
2761 sets up those clocks).
2762 @xref{Target Events}.
2763 When the initial low JTAG speed is a chip characteristic, perhaps
2764 because of a required oscillator speed, provide such a handler
2765 in the target config file.
2766 When that speed is a function of a board-specific characteristic
2767 such as which speed oscillator is used, it belongs in the board
2768 config file instead.
2769 In both cases it's safest to also set the initial JTAG clock rate
2770 to that same slow speed, so that OpenOCD never starts up using a
2771 clock speed that's faster than the scan chain can support.
2773 @example
2774 jtag_rclk 3000
2775 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
2776 @end example
2778 If your system supports adaptive clocking (RTCK), configuring
2779 JTAG to use that is probably the most robust approach.
2780 However, it introduces delays to synchronize clocks; so it
2781 may not be the fastest solution.
2783 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
2784 instead of @command{adapter_khz}, but only for (ARM) cores and boards
2785 which support adaptive clocking.
2787 @deffn {Command} adapter_khz max_speed_kHz
2788 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
2789 JTAG interfaces usually support a limited number of
2790 speeds. The speed actually used won't be faster
2791 than the speed specified.
2793 Chip data sheets generally include a top JTAG clock rate.
2794 The actual rate is often a function of a CPU core clock,
2795 and is normally less than that peak rate.
2796 For example, most ARM cores accept at most one sixth of the CPU clock.
2798 Speed 0 (khz) selects RTCK method.
2799 @xref{FAQ RTCK}.
2800 If your system uses RTCK, you won't need to change the
2801 JTAG clocking after setup.
2802 Not all interfaces, boards, or targets support ``rtck''.
2803 If the interface device can not
2804 support it, an error is returned when you try to use RTCK.
2805 @end deffn
2807 @defun jtag_rclk fallback_speed_kHz
2808 @cindex adaptive clocking
2809 @cindex RTCK
2810 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
2811 If that fails (maybe the interface, board, or target doesn't
2812 support it), falls back to the specified frequency.
2813 @example
2814 # Fall back to 3mhz if RTCK is not supported
2815 jtag_rclk 3000
2816 @end example
2817 @end defun
2819 @node Reset Configuration
2820 @chapter Reset Configuration
2821 @cindex Reset Configuration
2823 Every system configuration may require a different reset
2824 configuration. This can also be quite confusing.
2825 Resets also interact with @var{reset-init} event handlers,
2826 which do things like setting up clocks and DRAM, and
2827 JTAG clock rates. (@xref{JTAG Speed}.)
2828 They can also interact with JTAG routers.
2829 Please see the various board files for examples.
2831 @quotation Note
2832 To maintainers and integrators:
2833 Reset configuration touches several things at once.
2834 Normally the board configuration file
2835 should define it and assume that the JTAG adapter supports
2836 everything that's wired up to the board's JTAG connector.
2838 However, the target configuration file could also make note
2839 of something the silicon vendor has done inside the chip,
2840 which will be true for most (or all) boards using that chip.
2841 And when the JTAG adapter doesn't support everything, the
2842 user configuration file will need to override parts of
2843 the reset configuration provided by other files.
2844 @end quotation
2846 @section Types of Reset
2848 There are many kinds of reset possible through JTAG, but
2849 they may not all work with a given board and adapter.
2850 That's part of why reset configuration can be error prone.
2852 @itemize @bullet
2853 @item
2854 @emph{System Reset} ... the @emph{SRST} hardware signal
2855 resets all chips connected to the JTAG adapter, such as processors,
2856 power management chips, and I/O controllers. Normally resets triggered
2857 with this signal behave exactly like pressing a RESET button.
2858 @item
2859 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
2860 just the TAP controllers connected to the JTAG adapter.
2861 Such resets should not be visible to the rest of the system; resetting a
2862 device's TAP controller just puts that controller into a known state.
2863 @item
2864 @emph{Emulation Reset} ... many devices can be reset through JTAG
2865 commands. These resets are often distinguishable from system
2866 resets, either explicitly (a "reset reason" register says so)
2867 or implicitly (not all parts of the chip get reset).
2868 @item
2869 @emph{Other Resets} ... system-on-chip devices often support
2870 several other types of reset.
2871 You may need to arrange that a watchdog timer stops
2872 while debugging, preventing a watchdog reset.
2873 There may be individual module resets.
2874 @end itemize
2876 In the best case, OpenOCD can hold SRST, then reset
2877 the TAPs via TRST and send commands through JTAG to halt the
2878 CPU at the reset vector before the 1st instruction is executed.
2879 Then when it finally releases the SRST signal, the system is
2880 halted under debugger control before any code has executed.
2881 This is the behavior required to support the @command{reset halt}
2882 and @command{reset init} commands; after @command{reset init} a
2883 board-specific script might do things like setting up DRAM.
2884 (@xref{Reset Command}.)
2886 @anchor{SRST and TRST Issues}
2887 @section SRST and TRST Issues
2889 Because SRST and TRST are hardware signals, they can have a
2890 variety of system-specific constraints. Some of the most
2891 common issues are:
2893 @itemize @bullet
2895 @item @emph{Signal not available} ... Some boards don't wire
2896 SRST or TRST to the JTAG connector. Some JTAG adapters don't
2897 support such signals even if they are wired up.
2898 Use the @command{reset_config} @var{signals} options to say
2899 when either of those signals is not connected.
2900 When SRST is not available, your code might not be able to rely
2901 on controllers having been fully reset during code startup.
2902 Missing TRST is not a problem, since JTAG-level resets can
2903 be triggered using with TMS signaling.
2905 @item @emph{Signals shorted} ... Sometimes a chip, board, or
2906 adapter will connect SRST to TRST, instead of keeping them separate.
2907 Use the @command{reset_config} @var{combination} options to say
2908 when those signals aren't properly independent.
2910 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
2911 delay circuit, reset supervisor, or on-chip features can extend
2912 the effect of a JTAG adapter's reset for some time after the adapter
2913 stops issuing the reset. For example, there may be chip or board
2914 requirements that all reset pulses last for at least a
2915 certain amount of time; and reset buttons commonly have
2916 hardware debouncing.
2917 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
2918 commands to say when extra delays are needed.
2920 @item @emph{Drive type} ... Reset lines often have a pullup
2921 resistor, letting the JTAG interface treat them as open-drain
2922 signals. But that's not a requirement, so the adapter may need
2923 to use push/pull output drivers.
2924 Also, with weak pullups it may be advisable to drive
2925 signals to both levels (push/pull) to minimize rise times.
2926 Use the @command{reset_config} @var{trst_type} and
2927 @var{srst_type} parameters to say how to drive reset signals.
2929 @item @emph{Special initialization} ... Targets sometimes need
2930 special JTAG initialization sequences to handle chip-specific
2931 issues (not limited to errata).
2932 For example, certain JTAG commands might need to be issued while
2933 the system as a whole is in a reset state (SRST active)
2934 but the JTAG scan chain is usable (TRST inactive).
2935 Many systems treat combined assertion of SRST and TRST as a
2936 trigger for a harder reset than SRST alone.
2937 Such custom reset handling is discussed later in this chapter.
2938 @end itemize
2940 There can also be other issues.
2941 Some devices don't fully conform to the JTAG specifications.
2942 Trivial system-specific differences are common, such as
2943 SRST and TRST using slightly different names.
2944 There are also vendors who distribute key JTAG documentation for
2945 their chips only to developers who have signed a Non-Disclosure
2946 Agreement (NDA).
2948 Sometimes there are chip-specific extensions like a requirement to use
2949 the normally-optional TRST signal (precluding use of JTAG adapters which
2950 don't pass TRST through), or needing extra steps to complete a TAP reset.
2952 In short, SRST and especially TRST handling may be very finicky,
2953 needing to cope with both architecture and board specific constraints.
2955 @section Commands for Handling Resets
2957 @deffn {Command} adapter_nsrst_assert_width milliseconds
2958 Minimum amount of time (in milliseconds) OpenOCD should wait
2959 after asserting nSRST (active-low system reset) before
2960 allowing it to be deasserted.
2961 @end deffn
2963 @deffn {Command} adapter_nsrst_delay milliseconds
2964 How long (in milliseconds) OpenOCD should wait after deasserting
2965 nSRST (active-low system reset) before starting new JTAG operations.
2966 When a board has a reset button connected to SRST line it will
2967 probably have hardware debouncing, implying you should use this.
2968 @end deffn
2970 @deffn {Command} jtag_ntrst_assert_width milliseconds
2971 Minimum amount of time (in milliseconds) OpenOCD should wait
2972 after asserting nTRST (active-low JTAG TAP reset) before
2973 allowing it to be deasserted.
2974 @end deffn
2976 @deffn {Command} jtag_ntrst_delay milliseconds
2977 How long (in milliseconds) OpenOCD should wait after deasserting
2978 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
2979 @end deffn
2981 @deffn {Command} reset_config mode_flag ...
2982 This command displays or modifies the reset configuration
2983 of your combination of JTAG board and target in target
2984 configuration scripts.
2986 Information earlier in this section describes the kind of problems
2987 the command is intended to address (@pxref{SRST and TRST Issues}).
2988 As a rule this command belongs only in board config files,
2989 describing issues like @emph{board doesn't connect TRST};
2990 or in user config files, addressing limitations derived
2991 from a particular combination of interface and board.
2992 (An unlikely example would be using a TRST-only adapter
2993 with a board that only wires up SRST.)
2995 The @var{mode_flag} options can be specified in any order, but only one
2996 of each type -- @var{signals}, @var{combination},
2997 @var{gates},
2998 @var{trst_type},
2999 and @var{srst_type} -- may be specified at a time.
3000 If you don't provide a new value for a given type, its previous
3001 value (perhaps the default) is unchanged.
3002 For example, this means that you don't need to say anything at all about
3003 TRST just to declare that if the JTAG adapter should want to drive SRST,
3004 it must explicitly be driven high (@option{srst_push_pull}).
3006 @itemize
3007 @item
3008 @var{signals} can specify which of the reset signals are connected.
3009 For example, If the JTAG interface provides SRST, but the board doesn't
3010 connect that signal properly, then OpenOCD can't use it.
3011 Possible values are @option{none} (the default), @option{trst_only},
3012 @option{srst_only} and @option{trst_and_srst}.
3014 @quotation Tip
3015 If your board provides SRST and/or TRST through the JTAG connector,
3016 you must declare that so those signals can be used.
3017 @end quotation
3019 @item
3020 The @var{combination} is an optional value specifying broken reset
3021 signal implementations.
3022 The default behaviour if no option given is @option{separate},
3023 indicating everything behaves normally.
3024 @option{srst_pulls_trst} states that the
3025 test logic is reset together with the reset of the system (e.g. NXP
3026 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3027 the system is reset together with the test logic (only hypothetical, I
3028 haven't seen hardware with such a bug, and can be worked around).
3029 @option{combined} implies both @option{srst_pulls_trst} and
3030 @option{trst_pulls_srst}.
3032 @item
3033 The @var{gates} tokens control flags that describe some cases where
3034 JTAG may be unvailable during reset.
3035 @option{srst_gates_jtag} (default)
3036 indicates that asserting SRST gates the
3037 JTAG clock. This means that no communication can happen on JTAG
3038 while SRST is asserted.
3039 Its converse is @option{srst_nogate}, indicating that JTAG commands
3040 can safely be issued while SRST is active.
3041 @end itemize
3043 The optional @var{trst_type} and @var{srst_type} parameters allow the
3044 driver mode of each reset line to be specified. These values only affect
3045 JTAG interfaces with support for different driver modes, like the Amontec
3046 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3047 relevant signal (TRST or SRST) is not connected.
3049 @itemize
3050 @item
3051 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3052 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3053 Most boards connect this signal to a pulldown, so the JTAG TAPs
3054 never leave reset unless they are hooked up to a JTAG adapter.
3056 @item
3057 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3058 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3059 Most boards connect this signal to a pullup, and allow the
3060 signal to be pulled low by various events including system
3061 powerup and pressing a reset button.
3062 @end itemize
3063 @end deffn
3065 @section Custom Reset Handling
3066 @cindex events
3068 OpenOCD has several ways to help support the various reset
3069 mechanisms provided by chip and board vendors.
3070 The commands shown in the previous section give standard parameters.
3071 There are also @emph{event handlers} associated with TAPs or Targets.
3072 Those handlers are Tcl procedures you can provide, which are invoked
3073 at particular points in the reset sequence.
3075 @emph{When SRST is not an option} you must set
3076 up a @code{reset-assert} event handler for your target.
3077 For example, some JTAG adapters don't include the SRST signal;
3078 and some boards have multiple targets, and you won't always
3079 want to reset everything at once.
3081 After configuring those mechanisms, you might still
3082 find your board doesn't start up or reset correctly.
3083 For example, maybe it needs a slightly different sequence
3084 of SRST and/or TRST manipulations, because of quirks that
3085 the @command{reset_config} mechanism doesn't address;
3086 or asserting both might trigger a stronger reset, which
3087 needs special attention.
3089 Experiment with lower level operations, such as @command{jtag_reset}
3090 and the @command{jtag arp_*} operations shown here,
3091 to find a sequence of operations that works.
3092 @xref{JTAG Commands}.
3093 When you find a working sequence, it can be used to override
3094 @command{jtag_init}, which fires during OpenOCD startup
3095 (@pxref{Configuration Stage});
3096 or @command{init_reset}, which fires during reset processing.
3098 You might also want to provide some project-specific reset
3099 schemes. For example, on a multi-target board the standard
3100 @command{reset} command would reset all targets, but you
3101 may need the ability to reset only one target at time and
3102 thus want to avoid using the board-wide SRST signal.
3104 @deffn {Overridable Procedure} init_reset mode
3105 This is invoked near the beginning of the @command{reset} command,
3106 usually to provide as much of a cold (power-up) reset as practical.
3107 By default it is also invoked from @command{jtag_init} if
3108 the scan chain does not respond to pure JTAG operations.
3109 The @var{mode} parameter is the parameter given to the
3110 low level reset command (@option{halt},
3111 @option{init}, or @option{run}), @option{setup},
3112 or potentially some other value.
3114 The default implementation just invokes @command{jtag arp_init-reset}.
3115 Replacements will normally build on low level JTAG
3116 operations such as @command{jtag_reset}.
3117 Operations here must not address individual TAPs
3118 (or their associated targets)
3119 until the JTAG scan chain has first been verified to work.
3121 Implementations must have verified the JTAG scan chain before
3122 they return.
3123 This is done by calling @command{jtag arp_init}
3124 (or @command{jtag arp_init-reset}).
3125 @end deffn
3127 @deffn Command {jtag arp_init}
3128 This validates the scan chain using just the four
3129 standard JTAG signals (TMS, TCK, TDI, TDO).
3130 It starts by issuing a JTAG-only reset.
3131 Then it performs checks to verify that the scan chain configuration
3132 matches the TAPs it can observe.
3133 Those checks include checking IDCODE values for each active TAP,
3134 and verifying the length of their instruction registers using
3135 TAP @code{-ircapture} and @code{-irmask} values.
3136 If these tests all pass, TAP @code{setup} events are
3137 issued to all TAPs with handlers for that event.
3138 @end deffn
3140 @deffn Command {jtag arp_init-reset}
3141 This uses TRST and SRST to try resetting
3142 everything on the JTAG scan chain
3143 (and anything else connected to SRST).
3144 It then invokes the logic of @command{jtag arp_init}.
3145 @end deffn
3148 @node TAP Declaration
3149 @chapter TAP Declaration
3150 @cindex TAP declaration
3151 @cindex TAP configuration
3153 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3154 TAPs serve many roles, including:
3156 @itemize @bullet
3157 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
3158 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
3159 Others do it indirectly, making a CPU do it.
3160 @item @b{Program Download} Using the same CPU support GDB uses,
3161 you can initialize a DRAM controller, download code to DRAM, and then
3162 start running that code.
3163 @item @b{Boundary Scan} Most chips support boundary scan, which
3164 helps test for board assembly problems like solder bridges
3165 and missing connections
3166 @end itemize
3168 OpenOCD must know about the active TAPs on your board(s).
3169 Setting up the TAPs is the core task of your configuration files.
3170 Once those TAPs are set up, you can pass their names to code
3171 which sets up CPUs and exports them as GDB targets,
3172 probes flash memory, performs low-level JTAG operations, and more.
3174 @section Scan Chains
3175 @cindex scan chain
3177 TAPs are part of a hardware @dfn{scan chain},
3178 which is daisy chain of TAPs.
3179 They also need to be added to
3180 OpenOCD's software mirror of that hardware list,
3181 giving each member a name and associating other data with it.
3182 Simple scan chains, with a single TAP, are common in
3183 systems with a single microcontroller or microprocessor.
3184 More complex chips may have several TAPs internally.
3185 Very complex scan chains might have a dozen or more TAPs:
3186 several in one chip, more in the next, and connecting
3187 to other boards with their own chips and TAPs.
3189 You can display the list with the @command{scan_chain} command.
3190 (Don't confuse this with the list displayed by the @command{targets}
3191 command, presented in the next chapter.
3192 That only displays TAPs for CPUs which are configured as
3193 debugging targets.)
3194 Here's what the scan chain might look like for a chip more than one TAP:
3196 @verbatim
3197 TapName Enabled IdCode Expected IrLen IrCap IrMask
3198 -- ------------------ ------- ---------- ---------- ----- ----- ------
3199 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3200 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3201 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3202 @end verbatim
3204 OpenOCD can detect some of that information, but not all
3205 of it. @xref{Autoprobing}.
3206 Unfortunately those TAPs can't always be autoconfigured,
3207 because not all devices provide good support for that.
3208 JTAG doesn't require supporting IDCODE instructions, and
3209 chips with JTAG routers may not link TAPs into the chain
3210 until they are told to do so.
3212 The configuration mechanism currently supported by OpenOCD
3213 requires explicit configuration of all TAP devices using
3214 @command{jtag newtap} commands, as detailed later in this chapter.
3215 A command like this would declare one tap and name it @code{chip1.cpu}:
3217 @example
3218 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3219 @end example
3221 Each target configuration file lists the TAPs provided
3222 by a given chip.
3223 Board configuration files combine all the targets on a board,
3224 and so forth.
3225 Note that @emph{the order in which TAPs are declared is very important.}
3226 It must match the order in the JTAG scan chain, both inside
3227 a single chip and between them.
3228 @xref{FAQ TAP Order}.
3230 For example, the ST Microsystems STR912 chip has
3231 three separate TAPs@footnote{See the ST
3232 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3233 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3234 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3235 To configure those taps, @file{target/str912.cfg}
3236 includes commands something like this:
3238 @example
3239 jtag newtap str912 flash ... params ...
3240 jtag newtap str912 cpu ... params ...
3241 jtag newtap str912 bs ... params ...
3242 @end example
3244 Actual config files use a variable instead of literals like
3245 @option{str912}, to support more than one chip of each type.
3246 @xref{Config File Guidelines}.
3248 @deffn Command {jtag names}
3249 Returns the names of all current TAPs in the scan chain.
3250 Use @command{jtag cget} or @command{jtag tapisenabled}
3251 to examine attributes and state of each TAP.
3252 @example
3253 foreach t [jtag names] @{
3254 puts [format "TAP: %s\n" $t]
3255 @}
3256 @end example
3257 @end deffn
3259 @deffn Command {scan_chain}
3260 Displays the TAPs in the scan chain configuration,
3261 and their status.
3262 The set of TAPs listed by this command is fixed by
3263 exiting the OpenOCD configuration stage,
3264 but systems with a JTAG router can
3265 enable or disable TAPs dynamically.
3266 @end deffn
3268 @c FIXME! "jtag cget" should be able to return all TAP
3269 @c attributes, like "$target_name cget" does for targets.
3271 @c Probably want "jtag eventlist", and a "tap-reset" event
3272 @c (on entry to RESET state).
3274 @section TAP Names
3275 @cindex dotted name
3277 When TAP objects are declared with @command{jtag newtap},
3278 a @dfn{dotted.name} is created for the TAP, combining the
3279 name of a module (usually a chip) and a label for the TAP.
3280 For example: @code{xilinx.tap}, @code{str912.flash},
3281 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3282 Many other commands use that dotted.name to manipulate or
3283 refer to the TAP. For example, CPU configuration uses the
3284 name, as does declaration of NAND or NOR flash banks.
3286 The components of a dotted name should follow ``C'' symbol
3287 name rules: start with an alphabetic character, then numbers
3288 and underscores are OK; while others (including dots!) are not.
3290 @quotation Tip
3291 In older code, JTAG TAPs were numbered from 0..N.
3292 This feature is still present.
3293 However its use is highly discouraged, and
3294 should not be relied on; it will be removed by mid-2010.
3295 Update all of your scripts to use TAP names rather than numbers,
3296 by paying attention to the runtime warnings they trigger.
3297 Using TAP numbers in target configuration scripts prevents
3298 reusing those scripts on boards with multiple targets.
3299 @end quotation
3301 @section TAP Declaration Commands
3303 @c shouldn't this be(come) a {Config Command}?
3304 @anchor{jtag newtap}
3305 @deffn Command {jtag newtap} chipname tapname configparams...
3306 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3307 and configured according to the various @var{configparams}.
3309 The @var{chipname} is a symbolic name for the chip.
3310 Conventionally target config files use @code{$_CHIPNAME},
3311 defaulting to the model name given by the chip vendor but
3312 overridable.
3314 @cindex TAP naming convention
3315 The @var{tapname} reflects the role of that TAP,
3316 and should follow this convention:
3318 @itemize @bullet
3319 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3320 @item @code{cpu} -- The main CPU of the chip, alternatively
3321 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3322 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3323 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3324 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3325 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3326 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3327 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3328 with a single TAP;
3329 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3330 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3331 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3332 a JTAG TAP; that TAP should be named @code{sdma}.
3333 @end itemize
3335 Every TAP requires at least the following @var{configparams}:
3337 @itemize @bullet
3338 @item @code{-irlen} @var{NUMBER}
3339 @*The length in bits of the
3340 instruction register, such as 4 or 5 bits.
3341 @end itemize
3343 A TAP may also provide optional @var{configparams}:
3345 @itemize @bullet
3346 @item @code{-disable} (or @code{-enable})
3347 @*Use the @code{-disable} parameter to flag a TAP which is not
3348 linked in to the scan chain after a reset using either TRST
3349 or the JTAG state machine's @sc{reset} state.
3350 You may use @code{-enable} to highlight the default state
3351 (the TAP is linked in).
3352 @xref{Enabling and Disabling TAPs}.
3353 @item @code{-expected-id} @var{number}
3354 @*A non-zero @var{number} represents a 32-bit IDCODE
3355 which you expect to find when the scan chain is examined.
3356 These codes are not required by all JTAG devices.
3357 @emph{Repeat the option} as many times as required if more than one
3358 ID code could appear (for example, multiple versions).
3359 Specify @var{number} as zero to suppress warnings about IDCODE
3360 values that were found but not included in the list.
3362 Provide this value if at all possible, since it lets OpenOCD
3363 tell when the scan chain it sees isn't right. These values
3364 are provided in vendors' chip documentation, usually a technical
3365 reference manual. Sometimes you may need to probe the JTAG
3366 hardware to find these values.
3367 @xref{Autoprobing}.
3368 @item @code{-ignore-version}
3369 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3370 option. When vendors put out multiple versions of a chip, or use the same
3371 JTAG-level ID for several largely-compatible chips, it may be more practical
3372 to ignore the version field than to update config files to handle all of
3373 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3374 @item @code{-ircapture} @var{NUMBER}
3375 @*The bit pattern loaded by the TAP into the JTAG shift register
3376 on entry to the @sc{ircapture} state, such as 0x01.
3377 JTAG requires the two LSBs of this value to be 01.
3378 By default, @code{-ircapture} and @code{-irmask} are set
3379 up to verify that two-bit value. You may provide
3380 additional bits, if you know them, or indicate that
3381 a TAP doesn't conform to the JTAG specification.
3382 @item @code{-irmask} @var{NUMBER}
3383 @*A mask used with @code{-ircapture}
3384 to verify that instruction scans work correctly.
3385 Such scans are not used by OpenOCD except to verify that
3386 there seems to be no problems with JTAG scan chain operations.
3387 @end itemize
3388 @end deffn
3390 @section Other TAP commands
3392 @deffn Command {jtag cget} dotted.name @option{-event} name
3393 @deffnx Command {jtag configure} dotted.name @option{-event} name string
3394 At this writing this TAP attribute
3395 mechanism is used only for event handling.
3396 (It is not a direct analogue of the @code{cget}/@code{configure}
3397 mechanism for debugger targets.)
3398 See the next section for information about the available events.
3400 The @code{configure} subcommand assigns an event handler,
3401 a TCL string which is evaluated when the event is triggered.
3402 The @code{cget} subcommand returns that handler.
3403 @end deffn
3405 @anchor{TAP Events}
3406 @section TAP Events
3407 @cindex events
3408 @cindex TAP events
3410 OpenOCD includes two event mechanisms.
3411 The one presented here applies to all JTAG TAPs.
3412 The other applies to debugger targets,
3413 which are associated with certain TAPs.
3415 The TAP events currently defined are:
3417 @itemize @bullet
3418 @item @b{post-reset}
3419 @* The TAP has just completed a JTAG reset.
3420 The tap may still be in the JTAG @sc{reset} state.
3421 Handlers for these events might perform initialization sequences
3422 such as issuing TCK cycles, TMS sequences to ensure
3423 exit from the ARM SWD mode, and more.
3425 Because the scan chain has not yet been verified, handlers for these events
3426 @emph{should not issue commands which scan the JTAG IR or DR registers}
3427 of any particular target.
3428 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3429 @item @b{setup}
3430 @* The scan chain has been reset and verified.
3431 This handler may enable TAPs as needed.
3432 @item @b{tap-disable}
3433 @* The TAP needs to be disabled. This handler should
3434 implement @command{jtag tapdisable}
3435 by issuing the relevant JTAG commands.
3436 @item @b{tap-enable}
3437 @* The TAP needs to be enabled. This handler should
3438 implement @command{jtag tapenable}
3439 by issuing the relevant JTAG commands.
3440 @end itemize
3442 If you need some action after each JTAG reset, which isn't actually
3443 specific to any TAP (since you can't yet trust the scan chain's
3444 contents to be accurate), you might:
3446 @example
3447 jtag configure CHIP.jrc -event post-reset @{
3448 echo "JTAG Reset done"
3449 ... non-scan jtag operations to be done after reset
3450 @}
3451 @end example
3454 @anchor{Enabling and Disabling TAPs}
3455 @section Enabling and Disabling TAPs
3456 @cindex JTAG Route Controller
3457 @cindex jrc
3459 In some systems, a @dfn{JTAG Route Controller} (JRC)
3460 is used to enable and/or disable specific JTAG TAPs.
3461 Many ARM based chips from Texas Instruments include
3462 an ``ICEpick'' module, which is a JRC.
3463 Such chips include DaVinci and OMAP3 processors.
3465 A given TAP may not be visible until the JRC has been
3466 told to link it into the scan chain; and if the JRC
3467 has been told to unlink that TAP, it will no longer
3468 be visible.
3469 Such routers address problems that JTAG ``bypass mode''
3470 ignores, such as:
3472 @itemize
3473 @item The scan chain can only go as fast as its slowest TAP.
3474 @item Having many TAPs slows instruction scans, since all
3475 TAPs receive new instructions.
3476 @item TAPs in the scan chain must be powered up, which wastes
3477 power and prevents debugging some power management mechanisms.
3478 @end itemize
3480 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3481 as implied by the existence of JTAG routers.
3482 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3483 does include a kind of JTAG router functionality.
3485 @c (a) currently the event handlers don't seem to be able to
3486 @c fail in a way that could lead to no-change-of-state.
3488 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3489 shown below, and is implemented using TAP event handlers.
3490 So for example, when defining a TAP for a CPU connected to
3491 a JTAG router, your @file{target.cfg} file
3492 should define TAP event handlers using
3493 code that looks something like this:
3495 @example
3496 jtag configure CHIP.cpu -event tap-enable @{
3497 ... jtag operations using CHIP.jrc
3498 @}
3499 jtag configure CHIP.cpu -event tap-disable @{
3500 ... jtag operations using CHIP.jrc
3501 @}
3502 @end example
3504 Then you might want that CPU's TAP enabled almost all the time:
3506 @example
3507 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3508 @end example
3510 Note how that particular setup event handler declaration
3511 uses quotes to evaluate @code{$CHIP} when the event is configured.
3512 Using brackets @{ @} would cause it to be evaluated later,
3513 at runtime, when it might have a different value.
3515 @deffn Command {jtag tapdisable} dotted.name
3516 If necessary, disables the tap
3517 by sending it a @option{tap-disable} event.
3518 Returns the string "1" if the tap
3519 specified by @var{dotted.name} is enabled,
3520 and "0" if it is disabled.
3521 @end deffn
3523 @deffn Command {jtag tapenable} dotted.name
3524 If necessary, enables the tap
3525 by sending it a @option{tap-enable} event.
3526 Returns the string "1" if the tap
3527 specified by @var{dotted.name} is enabled,
3528 and "0" if it is disabled.
3529 @end deffn
3531 @deffn Command {jtag tapisenabled} dotted.name
3532 Returns the string "1" if the tap
3533 specified by @var{dotted.name} is enabled,
3534 and "0" if it is disabled.
3536 @quotation Note
3537 Humans will find the @command{scan_chain} command more helpful
3538 for querying the state of the JTAG taps.
3539 @end quotation
3540 @end deffn
3542 @anchor{Autoprobing}
3543 @section Autoprobing
3544 @cindex autoprobe
3545 @cindex JTAG autoprobe
3547 TAP configuration is the first thing that needs to be done
3548 after interface and reset configuration. Sometimes it's
3549 hard finding out what TAPs exist, or how they are identified.
3550 Vendor documentation is not always easy to find and use.
3552 To help you get past such problems, OpenOCD has a limited
3553 @emph{autoprobing} ability to look at the scan chain, doing
3554 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3555 To use this mechanism, start the OpenOCD server with only data
3556 that configures your JTAG interface, and arranges to come up
3557 with a slow clock (many devices don't support fast JTAG clocks
3558 right when they come out of reset).
3560 For example, your @file{openocd.cfg} file might have:
3562 @example
3563 source [find interface/olimex-arm-usb-tiny-h.cfg]
3564 reset_config trst_and_srst
3565 jtag_rclk 8
3566 @end example
3568 When you start the server without any TAPs configured, it will
3569 attempt to autoconfigure the TAPs. There are two parts to this:
3571 @enumerate
3572 @item @emph{TAP discovery} ...
3573 After a JTAG reset (sometimes a system reset may be needed too),
3574 each TAP's data registers will hold the contents of either the
3575 IDCODE or BYPASS register.
3576 If JTAG communication is working, OpenOCD will see each TAP,
3577 and report what @option{-expected-id} to use with it.
3578 @item @emph{IR Length discovery} ...
3579 Unfortunately JTAG does not provide a reliable way to find out
3580 the value of the @option{-irlen} parameter to use with a TAP
3581 that is discovered.
3582 If OpenOCD can discover the length of a TAP's instruction
3583 register, it will report it.
3584 Otherwise you may need to consult vendor documentation, such
3585 as chip data sheets or BSDL files.
3586 @end enumerate
3588 In many cases your board will have a simple scan chain with just
3589 a single device. Here's what OpenOCD reported with one board
3590 that's a bit more complex:
3592 @example
3593 clock speed 8 kHz
3594 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3595 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3596 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3597 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3598 AUTO auto0.tap - use "... -irlen 4"
3599 AUTO auto1.tap - use "... -irlen 4"
3600 AUTO auto2.tap - use "... -irlen 6"
3601 no gdb ports allocated as no target has been specified
3602 @end example
3604 Given that information, you should be able to either find some existing
3605 config files to use, or create your own. If you create your own, you
3606 would configure from the bottom up: first a @file{target.cfg} file
3607 with these TAPs, any targets associated with them, and any on-chip
3608 resources; then a @file{board.cfg} with off-chip resources, clocking,
3609 and so forth.
3611 @node CPU Configuration
3612 @chapter CPU Configuration
3613 @cindex GDB target
3615 This chapter discusses how to set up GDB debug targets for CPUs.
3616 You can also access these targets without GDB
3617 (@pxref{Architecture and Core Commands},
3618 and @ref{Target State handling}) and
3619 through various kinds of NAND and NOR flash commands.
3620 If you have multiple CPUs you can have multiple such targets.
3622 We'll start by looking at how to examine the targets you have,
3623 then look at how to add one more target and how to configure it.
3625 @section Target List
3626 @cindex target, current
3627 @cindex target, list
3629 All targets that have been set up are part of a list,
3630 where each member has a name.
3631 That name should normally be the same as the TAP name.
3632 You can display the list with the @command{targets}
3633 (plural!) command.
3634 This display often has only one CPU; here's what it might
3635 look like with more than one:
3636 @verbatim
3637 TargetName Type Endian TapName State
3638 -- ------------------ ---------- ------ ------------------ ------------
3639 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
3640 1 MyTarget cortex_m3 little mychip.foo tap-disabled
3641 @end verbatim
3643 One member of that list is the @dfn{current target}, which
3644 is implicitly referenced by many commands.
3645 It's the one marked with a @code{*} near the target name.
3646 In particular, memory addresses often refer to the address
3647 space seen by that current target.
3648 Commands like @command{mdw} (memory display words)
3649 and @command{flash erase_address} (erase NOR flash blocks)
3650 are examples; and there are many more.
3652 Several commands let you examine the list of targets:
3654 @deffn Command {target count}
3655 @emph{Note: target numbers are deprecated; don't use them.
3656 They will be removed shortly after August 2010, including this command.
3657 Iterate target using @command{target names}, not by counting.}
3659 Returns the number of targets, @math{N}.
3660 The highest numbered target is @math{N - 1}.
3661 @example
3662 set c [target count]
3663 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
3664 # Assuming you have created this function
3665 print_target_details $x
3666 @}
3667 @end example
3668 @end deffn
3670 @deffn Command {target current}
3671 Returns the name of the current target.
3672 @end deffn
3674 @deffn Command {target names}
3675 Lists the names of all current targets in the list.
3676 @example
3677 foreach t [target names] @{
3678 puts [format "Target: %s\n" $t]
3679 @}
3680 @end example
3681 @end deffn
3683 @deffn Command {target number} number
3684 @emph{Note: target numbers are deprecated; don't use them.
3685 They will be removed shortly after August 2010, including this command.}
3687 The list of targets is numbered starting at zero.
3688 This command returns the name of the target at index @var{number}.
3689 @example
3690 set thename [target number $x]
3691 puts [format "Target %d is: %s\n" $x $thename]
3692 @end example
3693 @end deffn
3695 @c yep, "target list" would have been better.
3696 @c plus maybe "target setdefault".
3698 @deffn Command targets [name]
3699 @emph{Note: the name of this command is plural. Other target
3700 command names are singular.}
3702 With no parameter, this command displays a table of all known
3703 targets in a user friendly form.
3705 With a parameter, this command sets the current target to
3706 the given target with the given @var{name}; this is
3707 only relevant on boards which have more than one target.
3708 @end deffn
3710 @section Target CPU Types and Variants
3711 @cindex target type
3712 @cindex CPU type
3713 @cindex CPU variant
3715 Each target has a @dfn{CPU type}, as shown in the output of
3716 the @command{targets} command. You need to specify that type
3717 when calling @command{target create}.
3718 The CPU type indicates more than just the instruction set.
3719 It also indicates how that instruction set is implemented,
3720 what kind of debug support it integrates,
3721 whether it has an MMU (and if so, what kind),
3722 what core-specific commands may be available
3723 (@pxref{Architecture and Core Commands}),
3724 and more.
3726 For some CPU types, OpenOCD also defines @dfn{variants} which
3727 indicate differences that affect their handling.
3728 For example, a particular implementation bug might need to be
3729 worked around in some chip versions.
3731 It's easy to see what target types are supported,
3732 since there's a command to list them.
3733 However, there is currently no way to list what target variants
3734 are supported (other than by reading the OpenOCD source code).
3736 @anchor{target types}
3737 @deffn Command {target types}
3738 Lists all supported target types.
3739 At this writing, the supported CPU types and variants are:
3741 @itemize @bullet
3742 @item @code{arm11} -- this is a generation of ARMv6 cores
3743 @item @code{arm720t} -- this is an ARMv4 core with an MMU
3744 @item @code{arm7tdmi} -- this is an ARMv4 core
3745 @item @code{arm920t} -- this is an ARMv4 core with an MMU
3746 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
3747 @item @code{arm966e} -- this is an ARMv5 core
3748 @item @code{arm9tdmi} -- this is an ARMv4 core
3749 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
3750 (Support for this is preliminary and incomplete.)
3751 @item @code{cortex_a8} -- this is an ARMv7 core with an MMU
3752 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
3753 compact Thumb2 instruction set.
3754 @item @code{dragonite} -- resembles arm966e
3755 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
3756 (Support for this is still incomplete.)
3757 @item @code{fa526} -- resembles arm920 (w/o Thumb)
3758 @item @code{feroceon} -- resembles arm926
3759 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
3760 @item @code{xscale} -- this is actually an architecture,
3761 not a CPU type. It is based on the ARMv5 architecture.
3762 There are several variants defined:
3763 @itemize @minus
3764 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
3765 @code{pxa27x} ... instruction register length is 7 bits
3766 @item @code{pxa250}, @code{pxa255},
3767 @code{pxa26x} ... instruction register length is 5 bits
3768 @item @code{pxa3xx} ... instruction register length is 11 bits
3769 @end itemize
3770 @end itemize
3771 @end deffn
3773 To avoid being confused by the variety of ARM based cores, remember
3774 this key point: @emph{ARM is a technology licencing company}.
3775 (See: @url{http://www.arm.com}.)
3776 The CPU name used by OpenOCD will reflect the CPU design that was
3777 licenced, not a vendor brand which incorporates that design.
3778 Name prefixes like arm7, arm9, arm11, and cortex
3779 reflect design generations;
3780 while names like ARMv4, ARMv5, ARMv6, and ARMv7
3781 reflect an architecture version implemented by a CPU design.
3783 @anchor{Target Configuration}
3784 @section Target Configuration
3786 Before creating a ``target'', you must have added its TAP to the scan chain.
3787 When you've added that TAP, you will have a @code{dotted.name}
3788 which is used to set up the CPU support.
3789 The chip-specific configuration file will normally configure its CPU(s)
3790 right after it adds all of the chip's TAPs to the scan chain.
3792 Although you can set up a target in one step, it's often clearer if you
3793 use shorter commands and do it in two steps: create it, then configure
3794 optional parts.
3795 All operations on the target after it's created will use a new
3796 command, created as part of target creation.
3798 The two main things to configure after target creation are
3799 a work area, which usually has target-specific defaults even
3800 if the board setup code overrides them later;
3801 and event handlers (@pxref{Target Events}), which tend
3802 to be much more board-specific.
3803 The key steps you use might look something like this
3805 @example
3806 target create MyTarget cortex_m3 -chain-position mychip.cpu
3807 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
3808 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
3809 $MyTarget configure -event reset-init @{ myboard_reinit @}
3810 @end example
3812 You should specify a working area if you can; typically it uses some
3813 on-chip SRAM.
3814 Such a working area can speed up many things, including bulk
3815 writes to target memory;
3816 flash operations like checking to see if memory needs to be erased;
3817 GDB memory checksumming;
3818 and more.
3820 @quotation Warning
3821 On more complex chips, the work area can become
3822 inaccessible when application code
3823 (such as an operating system)
3824 enables or disables the MMU.
3825 For example, the particular MMU context used to acess the virtual
3826 address will probably matter ... and that context might not have
3827 easy access to other addresses needed.
3828 At this writing, OpenOCD doesn't have much MMU intelligence.
3829 @end quotation
3831 It's often very useful to define a @code{reset-init} event handler.
3832 For systems that are normally used with a boot loader,
3833 common tasks include updating clocks and initializing memory
3834 controllers.
3835 That may be needed to let you write the boot loader into flash,
3836 in order to ``de-brick'' your board; or to load programs into
3837 external DDR memory without having run the boot loader.
3839 @deffn Command {target create} target_name type configparams...
3840 This command creates a GDB debug target that refers to a specific JTAG tap.
3841 It enters that target into a list, and creates a new
3842 command (@command{@var{target_name}}) which is used for various
3843 purposes including additional configuration.
3845 @itemize @bullet
3846 @item @var{target_name} ... is the name of the debug target.
3847 By convention this should be the same as the @emph{dotted.name}
3848 of the TAP associated with this target, which must be specified here
3849 using the @code{-chain-position @var{dotted.name}} configparam.
3851 This name is also used to create the target object command,
3852 referred to here as @command{$target_name},
3853 and in other places the target needs to be identified.
3854 @item @var{type} ... specifies the target type. @xref{target types}.
3855 @item @var{configparams} ... all parameters accepted by
3856 @command{$target_name configure} are permitted.
3857 If the target is big-endian, set it here with @code{-endian big}.
3858 If the variant matters, set it here with @code{-variant}.
3860 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
3861 @end itemize
3862 @end deffn
3864 @deffn Command {$target_name configure} configparams...
3865 The options accepted by this command may also be
3866 specified as parameters to @command{target create}.
3867 Their values can later be queried one at a time by
3868 using the @command{$target_name cget} command.
3870 @emph{Warning:} changing some of these after setup is dangerous.
3871 For example, moving a target from one TAP to another;
3872 and changing its endianness or variant.
3874 @itemize @bullet
3876 @item @code{-chain-position} @var{dotted.name} -- names the TAP
3877 used to access this target.
3879 @item @code{-endian} (@option{big}|@option{little}) -- specifies
3880 whether the CPU uses big or little endian conventions
3882 @item @code{-event} @var{event_name} @var{event_body} --
3883 @xref{Target Events}.
3884 Note that this updates a list of named event handlers.
3885 Calling this twice with two different event names assigns
3886 two different handlers, but calling it twice with the
3887 same event name assigns only one handler.
3889 @item @code{-variant} @var{name} -- specifies a variant of the target,
3890 which OpenOCD needs to know about.
3892 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
3893 whether the work area gets backed up; by default,
3894 @emph{it is not backed up.}
3895 When possible, use a working_area that doesn't need to be backed up,
3896 since performing a backup slows down operations.
3897 For example, the beginning of an SRAM block is likely to
3898 be used by most build systems, but the end is often unused.
3900 @item @code{-work-area-size} @var{size} -- specify work are size,
3901 in bytes. The same size applies regardless of whether its physical
3902 or virtual address is being used.
3904 @item @code{-work-area-phys} @var{address} -- set the work area
3905 base @var{address} to be used when no MMU is active.
3907 @item @code{-work-area-virt} @var{address} -- set the work area
3908 base @var{address} to be used when an MMU is active.
3909 @emph{Do not specify a value for this except on targets with an MMU.}
3910 The value should normally correspond to a static mapping for the
3911 @code{-work-area-phys} address, set up by the current operating system.
3913 @end itemize
3914 @end deffn
3916 @section Other $target_name Commands
3917 @cindex object command
3919 The Tcl/Tk language has the concept of object commands,
3920 and OpenOCD adopts that same model for targets.
3922 A good Tk example is a on screen button.
3923 Once a button is created a button
3924 has a name (a path in Tk terms) and that name is useable as a first
3925 class command. For example in Tk, one can create a button and later
3926 configure it like this:
3928 @example
3929 # Create
3930 button .foobar -background red -command @{ foo @}
3931 # Modify
3932 .foobar configure -foreground blue
3933 # Query
3934 set x [.foobar cget -background]
3935 # Report
3936 puts [format "The button is %s" $x]
3937 @end example
3939 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
3940 button, and its object commands are invoked the same way.
3942 @example
3943 str912.cpu mww 0x1234 0x42
3944 omap3530.cpu mww 0x5555 123
3945 @end example
3947 The commands supported by OpenOCD target objects are:
3949 @deffn Command {$target_name arp_examine}
3950 @deffnx Command {$target_name arp_halt}
3951 @deffnx Command {$target_name arp_poll}
3952 @deffnx Command {$target_name arp_reset}
3953 @deffnx Command {$target_name arp_waitstate}
3954 Internal OpenOCD scripts (most notably @file{startup.tcl})
3955 use these to deal with specific reset cases.
3956 They are not otherwise documented here.
3957 @end deffn
3959 @deffn Command {$target_name array2mem} arrayname width address count
3960 @deffnx Command {$target_name mem2array} arrayname width address count
3961 These provide an efficient script-oriented interface to memory.
3962 The @code{array2mem} primitive writes bytes, halfwords, or words;
3963 while @code{mem2array} reads them.
3964 In both cases, the TCL side uses an array, and
3965 the target side uses raw memory.
3967 The efficiency comes from enabling the use of
3968 bulk JTAG data transfer operations.
3969 The script orientation comes from working with data
3970 values that are packaged for use by TCL scripts;
3971 @command{mdw} type primitives only print data they retrieve,
3972 and neither store nor return those values.
3974 @itemize
3975 @item @var{arrayname} ... is the name of an array variable
3976 @item @var{width} ... is 8/16/32 - indicating the memory access size
3977 @item @var{address} ... is the target memory address
3978 @item @var{count} ... is the number of elements to process
3979 @end itemize
3980 @end deffn
3982 @deffn Command {$target_name cget} queryparm
3983 Each configuration parameter accepted by
3984 @command{$target_name configure}
3985 can be individually queried, to return its current value.
3986 The @var{queryparm} is a parameter name
3987 accepted by that command, such as @code{-work-area-phys}.
3988 There are a few special cases:
3990 @itemize @bullet
3991 @item @code{-event} @var{event_name} -- returns the handler for the
3992 event named @var{event_name}.
3993 This is a special case because setting a handler requires
3994 two parameters.
3995 @item @code{-type} -- returns the target type.
3996 This is a special case because this is set using
3997 @command{target create} and can't be changed
3998 using @command{$target_name configure}.
3999 @end itemize
4001 For example, if you wanted to summarize information about
4002 all the targets you might use something like this:
4004 @example
4005 foreach name [target names] @{
4006 set y [$name cget -endian]
4007 set z [$name cget -type]
4008 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4009 $x $name $y $z]
4010 @}
4011 @end example
4012 @end deffn
4014 @anchor{target curstate}
4015 @deffn Command {$target_name curstate}
4016 Displays the current target state:
4017 @code{debug-running},
4018 @code{halted},
4019 @code{reset},
4020 @code{running}, or @code{unknown}.
4021 (Also, @pxref{Event Polling}.)
4022 @end deffn
4024 @deffn Command {$target_name eventlist}
4025 Displays a table listing all event handlers
4026 currently associated with this target.
4027 @xref{Target Events}.
4028 @end deffn
4030 @deffn Command {$target_name invoke-event} event_name
4031 Invokes the handler for the event named @var{event_name}.
4032 (This is primarily intended for use by OpenOCD framework
4033 code, for example by the reset code in @file{startup.tcl}.)
4034 @end deffn
4036 @deffn Command {$target_name mdw} addr [count]
4037 @deffnx Command {$target_name mdh} addr [count]
4038 @deffnx Command {$target_name mdb} addr [count]
4039 Display contents of address @var{addr}, as
4040 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4041 or 8-bit bytes (@command{mdb}).
4042 If @var{count} is specified, displays that many units.
4043 (If you want to manipulate the data instead of displaying it,
4044 see the @code{mem2array} primitives.)
4045 @end deffn
4047 @deffn Command {$target_name mww} addr word
4048 @deffnx Command {$target_name mwh} addr halfword
4049 @deffnx Command {$target_name mwb} addr byte
4050 Writes the specified @var{word} (32 bits),
4051 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4052 at the specified address @var{addr}.
4053 @end deffn
4055 @anchor{Target Events}
4056 @section Target Events
4057 @cindex target events
4058 @cindex events
4059 At various times, certain things can happen, or you want them to happen.
4060 For example:
4061 @itemize @bullet
4062 @item What should happen when GDB connects? Should your target reset?
4063 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4064 @item Is using SRST appropriate (and possible) on your system?
4065 Or instead of that, do you need to issue JTAG commands to trigger reset?
4066 SRST usually resets everything on the scan chain, which can be inappropriate.
4067 @item During reset, do you need to write to certain memory locations
4068 to set up system clocks or
4069 to reconfigure the SDRAM?
4070 How about configuring the watchdog timer, or other peripherals,
4071 to stop running while you hold the core stopped for debugging?
4072 @end itemize
4074 All of the above items can be addressed by target event handlers.
4075 These are set up by @command{$target_name configure -event} or
4076 @command{target create ... -event}.
4078 The programmer's model matches the @code{-command} option used in Tcl/Tk
4079 buttons and events. The two examples below act the same, but one creates
4080 and invokes a small procedure while the other inlines it.
4082 @example
4083 proc my_attach_proc @{ @} @{
4084 echo "Reset..."
4085 reset halt
4086 @}
4087 mychip.cpu configure -event gdb-attach my_attach_proc
4088 mychip.cpu configure -event gdb-attach @{
4089 echo "Reset..."
4090 # To make flash probe and gdb load to flash work we need a reset init.
4091 reset init
4092 @}
4093 @end example
4095 The following target events are defined:
4097 @itemize @bullet
4098 @item @b{debug-halted}
4099 @* The target has halted for debug reasons (i.e.: breakpoint)
4100 @item @b{debug-resumed}
4101 @* The target has resumed (i.e.: gdb said run)
4102 @item @b{early-halted}
4103 @* Occurs early in the halt process
4104 @ignore
4105 @item @b{examine-end}
4106 @* Currently not used (goal: when JTAG examine completes)
4107 @item @b{examine-start}
4108 @* Currently not used (goal: when JTAG examine starts)
4109 @end ignore
4110 @item @b{gdb-attach}
4111 @* When GDB connects. This is before any communication with the target, so this
4112 can be used to set up the target so it is possible to probe flash. Probing flash
4113 is necessary during gdb connect if gdb load is to write the image to flash. Another
4114 use of the flash memory map is for GDB to automatically hardware/software breakpoints
4115 depending on whether the breakpoint is in RAM or read only memory.
4116 @item @b{gdb-detach}
4117 @* When GDB disconnects
4118 @item @b{gdb-end}
4119 @* When the target has halted and GDB is not doing anything (see early halt)
4120 @item @b{gdb-flash-erase-start}
4121 @* Before the GDB flash process tries to erase the flash
4122 @item @b{gdb-flash-erase-end}
4123 @* After the GDB flash process has finished erasing the flash
4124 @item @b{gdb-flash-write-start}
4125 @* Before GDB writes to the flash
4126 @item @b{gdb-flash-write-end}
4127 @* After GDB writes to the flash
4128 @item @b{gdb-start}
4129 @* Before the target steps, gdb is trying to start/resume the target
4130 @item @b{halted}
4131 @* The target has halted
4132 @ignore
4133 @item @b{old-gdb_program_config}
4134 @* DO NOT USE THIS: Used internally
4135 @item @b{old-pre_resume}
4136 @* DO NOT USE THIS: Used internally
4137 @end ignore
4138 @item @b{reset-assert-pre}
4139 @* Issued as part of @command{reset} processing
4140 after @command{reset_init} was triggered
4141 but before either SRST alone is re-asserted on the scan chain,
4142 or @code{reset-assert} is triggered.
4143 @item @b{reset-assert}
4144 @* Issued as part of @command{reset} processing
4145 after @command{reset-assert-pre} was triggered.
4146 When such a handler is present, cores which support this event will use
4147 it instead of asserting SRST.
4148 This support is essential for debugging with JTAG interfaces which
4149 don't include an SRST line (JTAG doesn't require SRST), and for
4150 selective reset on scan chains that have multiple targets.
4151 @item @b{reset-assert-post}
4152 @* Issued as part of @command{reset} processing
4153 after @code{reset-assert} has been triggered.
4154 or the target asserted SRST on the entire scan chain.
4155 @item @b{reset-deassert-pre}
4156 @* Issued as part of @command{reset} processing
4157 after @code{reset-assert-post} has been triggered.
4158 @item @b{reset-deassert-post}
4159 @* Issued as part of @command{reset} processing
4160 after @code{reset-deassert-pre} has been triggered
4161 and (if the target is using it) after SRST has been
4162 released on the scan chain.
4163 @item @b{reset-end}
4164 @* Issued as the final step in @command{reset} processing.
4165 @ignore
4166 @item @b{reset-halt-post}
4167 @* Currently not used
4168 @item @b{reset-halt-pre}
4169 @* Currently not used
4170 @end ignore
4171 @item @b{reset-init}
4172 @* Used by @b{reset init} command for board-specific initialization.
4173 This event fires after @emph{reset-deassert-post}.
4175 This is where you would configure PLLs and clocking, set up DRAM so
4176 you can download programs that don't fit in on-chip SRAM, set up pin
4177 multiplexing, and so on.
4178 (You may be able to switch to a fast JTAG clock rate here, after
4179 the target clocks are fully set up.)
4180 @item @b{reset-start}
4181 @* Issued as part of @command{reset} processing
4182 before @command{reset_init} is called.
4184 This is the most robust place to use @command{jtag_rclk}
4185 or @command{adapter_khz} to switch to a low JTAG clock rate,
4186 when reset disables PLLs needed to use a fast clock.
4187 @ignore
4188 @item @b{reset-wait-pos}
4189 @* Currently not used
4190 @item @b{reset-wait-pre}
4191 @* Currently not used
4192 @end ignore
4193 @item @b{resume-start}
4194 @* Before any target is resumed
4195 @item @b{resume-end}
4196 @* After all targets have resumed
4197 @item @b{resume-ok}
4198 @* Success
4199 @item @b{resumed}
4200 @* Target has resumed
4201 @end itemize
4204 @node Flash Commands
4205 @chapter Flash Commands
4207 OpenOCD has different commands for NOR and NAND flash;
4208 the ``flash'' command works with NOR flash, while
4209 the ``nand'' command works with NAND flash.
4210 This partially reflects different hardware technologies:
4211 NOR flash usually supports direct CPU instruction and data bus access,
4212 while data from a NAND flash must be copied to memory before it can be
4213 used. (SPI flash must also be copied to memory before use.)
4214 However, the documentation also uses ``flash'' as a generic term;
4215 for example, ``Put flash configuration in board-specific files''.
4217 Flash Steps:
4218 @enumerate
4219 @item Configure via the command @command{flash bank}
4220 @* Do this in a board-specific configuration file,
4221 passing parameters as needed by the driver.
4222 @item Operate on the flash via @command{flash subcommand}
4223 @* Often commands to manipulate the flash are typed by a human, or run
4224 via a script in some automated way. Common tasks include writing a
4225 boot loader, operating system, or other data.
4226 @item GDB Flashing
4227 @* Flashing via GDB requires the flash be configured via ``flash
4228 bank'', and the GDB flash features be enabled.
4229 @xref{GDB Configuration}.
4230 @end enumerate
4232 Many CPUs have the ablity to ``boot'' from the first flash bank.
4233 This means that misprogramming that bank can ``brick'' a system,
4234 so that it can't boot.
4235 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4236 board by (re)installing working boot firmware.
4238 @anchor{NOR Configuration}
4239 @section Flash Configuration Commands
4240 @cindex flash configuration
4242 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4243 Configures a flash bank which provides persistent storage
4244 for addresses from @math{base} to @math{base + size - 1}.
4245 These banks will often be visible to GDB through the target's memory map.
4246 In some cases, configuring a flash bank will activate extra commands;
4247 see the driver-specific documentation.
4249 @itemize @bullet
4250 @item @var{name} ... may be used to reference the flash bank
4251 in other flash commands. A number is also available.
4252 @item @var{driver} ... identifies the controller driver
4253 associated with the flash bank being declared.
4254 This is usually @code{cfi} for external flash, or else
4255 the name of a microcontroller with embedded flash memory.
4256 @xref{Flash Driver List}.
4257 @item @var{base} ... Base address of the flash chip.
4258 @item @var{size} ... Size of the chip, in bytes.
4259 For some drivers, this value is detected from the hardware.
4260 @item @var{chip_width} ... Width of the flash chip, in bytes;
4261 ignored for most microcontroller drivers.
4262 @item @var{bus_width} ... Width of the data bus used to access the
4263 chip, in bytes; ignored for most microcontroller drivers.
4264 @item @var{target} ... Names the target used to issue
4265 commands to the flash controller.
4266 @comment Actually, it's currently a controller-specific parameter...
4267 @item @var{driver_options} ... drivers may support, or require,
4268 additional parameters. See the driver-specific documentation
4269 for more information.
4270 @end itemize
4271 @quotation Note
4272 This command is not available after OpenOCD initialization has completed.
4273 Use it in board specific configuration files, not interactively.
4274 @end quotation
4275 @end deffn
4277 @comment the REAL name for this command is "ocd_flash_banks"
4278 @comment less confusing would be: "flash list" (like "nand list")
4279 @deffn Command {flash banks}
4280 Prints a one-line summary of each device that was
4281 declared using @command{flash bank}, numbered from zero.
4282 Note that this is the @emph{plural} form;
4283 the @emph{singular} form is a very different command.
4284 @end deffn
4286 @deffn Command {flash list}
4287 Retrieves a list of associative arrays for each device that was
4288 declared using @command{flash bank}, numbered from zero.
4289 This returned list can be manipulated easily from within scripts.
4290 @end deffn
4292 @deffn Command {flash probe} num
4293 Identify the flash, or validate the parameters of the configured flash. Operation
4294 depends on the flash type.
4295 The @var{num} parameter is a value shown by @command{flash banks}.
4296 Most flash commands will implicitly @emph{autoprobe} the bank;
4297 flash drivers can distinguish between probing and autoprobing,
4298 but most don't bother.
4299 @end deffn
4301 @section Erasing, Reading, Writing to Flash
4302 @cindex flash erasing
4303 @cindex flash reading
4304 @cindex flash writing
4305 @cindex flash programming
4307 One feature distinguishing NOR flash from NAND or serial flash technologies
4308 is that for read access, it acts exactly like any other addressible memory.
4309 This means you can use normal memory read commands like @command{mdw} or
4310 @command{dump_image} with it, with no special @command{flash} subcommands.
4311 @xref{Memory access}, and @ref{Image access}.
4313 Write access works differently. Flash memory normally needs to be erased
4314 before it's written. Erasing a sector turns all of its bits to ones, and
4315 writing can turn ones into zeroes. This is why there are special commands
4316 for interactive erasing and writing, and why GDB needs to know which parts
4317 of the address space hold NOR flash memory.
4319 @quotation Note
4320 Most of these erase and write commands leverage the fact that NOR flash
4321 chips consume target address space. They implicitly refer to the current
4322 JTAG target, and map from an address in that target's address space
4323 back to a flash bank.
4324 @comment In May 2009, those mappings may fail if any bank associated
4325 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
4326 A few commands use abstract addressing based on bank and sector numbers,
4327 and don't depend on searching the current target and its address space.
4328 Avoid confusing the two command models.
4329 @end quotation
4331 Some flash chips implement software protection against accidental writes,
4332 since such buggy writes could in some cases ``brick'' a system.
4333 For such systems, erasing and writing may require sector protection to be
4334 disabled first.
4335 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4336 and AT91SAM7 on-chip flash.
4337 @xref{flash protect}.
4339 @anchor{flash erase_sector}
4340 @deffn Command {flash erase_sector} num first last
4341 Erase sectors in bank @var{num}, starting at sector @var{first}
4342 up to and including @var{last}.
4343 Sector numbering starts at 0.
4344 Providing a @var{last} sector of @option{last}
4345 specifies "to the end of the flash bank".
4346 The @var{num} parameter is a value shown by @command{flash banks}.
4347 @end deffn
4349 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4350 Erase sectors starting at @var{address} for @var{length} bytes.
4351 Unless @option{pad} is specified, @math{address} must begin a
4352 flash sector, and @math{address + length - 1} must end a sector.
4353 Specifying @option{pad} erases extra data at the beginning and/or
4354 end of the specified region, as needed to erase only full sectors.
4355 The flash bank to use is inferred from the @var{address}, and
4356 the specified length must stay within that bank.
4357 As a special case, when @var{length} is zero and @var{address} is
4358 the start of the bank, the whole flash is erased.
4359 If @option{unlock} is specified, then the flash is unprotected
4360 before erase starts.
4361 @end deffn
4363 @deffn Command {flash fillw} address word length
4364 @deffnx Command {flash fillh} address halfword length
4365 @deffnx Command {flash fillb} address byte length
4366 Fills flash memory with the specified @var{word} (32 bits),
4367 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4368 starting at @var{address} and continuing
4369 for @var{length} units (word/halfword/byte).
4370 No erasure is done before writing; when needed, that must be done
4371 before issuing this command.
4372 Writes are done in blocks of up to 1024 bytes, and each write is
4373 verified by reading back the data and comparing it to what was written.
4374 The flash bank to use is inferred from the @var{address} of
4375 each block, and the specified length must stay within that bank.
4376 @end deffn
4377 @comment no current checks for errors if fill blocks touch multiple banks!
4379 @anchor{flash write_bank}
4380 @deffn Command {flash write_bank} num filename offset
4381 Write the binary @file{filename} to flash bank @var{num},
4382 starting at @var{offset} bytes from the beginning of the bank.
4383 The @var{num} parameter is a value shown by @command{flash banks}.
4384 @end deffn
4386 @anchor{flash write_image}
4387 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4388 Write the image @file{filename} to the current target's flash bank(s).
4389 A relocation @var{offset} may be specified, in which case it is added
4390 to the base address for each section in the image.
4391 The file [@var{type}] can be specified
4392 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4393 @option{elf} (ELF file), @option{s19} (Motorola s19).
4394 @option{mem}, or @option{builder}.
4395 The relevant flash sectors will be erased prior to programming
4396 if the @option{erase} parameter is given. If @option{unlock} is
4397 provided, then the flash banks are unlocked before erase and
4398 program. The flash bank to use is inferred from the address of
4399 each image section.
4401 @quotation Warning
4402 Be careful using the @option{erase} flag when the flash is holding
4403 data you want to preserve.
4404 Portions of the flash outside those described in the image's
4405 sections might be erased with no notice.
4406 @itemize
4407 @item
4408 When a section of the image being written does not fill out all the
4409 sectors it uses, the unwritten parts of those sectors are necessarily
4410 also erased, because sectors can't be partially erased.
4411 @item
4412 Data stored in sector "holes" between image sections are also affected.
4413 For example, "@command{flash write_image erase ...}" of an image with
4414 one byte at the beginning of a flash bank and one byte at the end
4415 erases the entire bank -- not just the two sectors being written.
4416 @end itemize
4417 Also, when flash protection is important, you must re-apply it after
4418 it has been removed by the @option{unlock} flag.
4419 @end quotation
4421 @end deffn
4423 @section Other Flash commands
4424 @cindex flash protection
4426 @deffn Command {flash erase_check} num
4427 Check erase state of sectors in flash bank @var{num},
4428 and display that status.
4429 The @var{num} parameter is a value shown by @command{flash banks}.
4430 @end deffn
4432 @deffn Command {flash info} num
4433 Print info about flash bank @var{num}
4434 The @var{num} parameter is a value shown by @command{flash banks}.
4435 This command will first query the hardware, it does not print cached
4436 and possibly stale information.
4437 @end deffn
4439 @anchor{flash protect}
4440 @deffn Command {flash protect} num first last (@option{on}|@option{off})
4441 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
4442 in flash bank @var{num}, starting at sector @var{first}
4443 and continuing up to and including @var{last}.
4444 Providing a @var{last} sector of @option{last}
4445 specifies "to the end of the flash bank".
4446 The @var{num} parameter is a value shown by @command{flash banks}.
4447 @end deffn
4449 @anchor{Flash Driver List}
4450 @section Flash Driver List
4451 As noted above, the @command{flash bank} command requires a driver name,
4452 and allows driver-specific options and behaviors.
4453 Some drivers also activate driver-specific commands.
4455 @subsection External Flash
4457 @deffn {Flash Driver} cfi
4458 @cindex Common Flash Interface
4459 @cindex CFI
4460 The ``Common Flash Interface'' (CFI) is the main standard for
4461 external NOR flash chips, each of which connects to a
4462 specific external chip select on the CPU.
4463 Frequently the first such chip is used to boot the system.
4464 Your board's @code{reset-init} handler might need to
4465 configure additional chip selects using other commands (like: @command{mww} to
4466 configure a bus and its timings), or
4467 perhaps configure a GPIO pin that controls the ``write protect'' pin
4468 on the flash chip.
4469 The CFI driver can use a target-specific working area to significantly
4470 speed up operation.
4472 The CFI driver can accept the following optional parameters, in any order:
4474 @itemize
4475 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
4476 like AM29LV010 and similar types.
4477 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
4478 @end itemize
4480 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
4481 wide on a sixteen bit bus:
4483 @example
4484 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
4485 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
4486 @end example
4488 To configure one bank of 32 MBytes
4489 built from two sixteen bit (two byte) wide parts wired in parallel
4490 to create a thirty-two bit (four byte) bus with doubled throughput:
4492 @example
4493 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
4494 @end example
4496 @c "cfi part_id" disabled
4497 @end deffn
4499 @deffn {Flash Driver} stmsmi
4500 @cindex STMicroelectronics Serial Memory Interface
4501 @cindex SMI
4502 @cindex stmsmi
4503 Some devices form STMicroelectronics (e.g. STR75x MCU family,
4504 SPEAr MPU family) include a proprietary
4505 ``Serial Memory Interface'' (SMI) controller able to drive external
4506 SPI flash devices.
4507 Depending on specific device and board configuration, up to 4 external
4508 flash devices can be connected.
4510 SMI makes the flash content directly accessible in the CPU address
4511 space; each external device is mapped in a memory bank.
4512 CPU can directly read data, execute code and boot from SMI banks.
4513 Normal OpenOCD commands like @command{mdw} can be used to display
4514 the flash content.
4516 The setup command only requires the @var{base} parameter in order
4517 to identify the memory bank.
4518 All other parameters are ignored. Additional information, like
4519 flash size, are detected automatically.
4521 @example
4522 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
4523 @end example
4525 @end deffn
4527 @subsection Internal Flash (Microcontrollers)
4529 @deffn {Flash Driver} aduc702x
4530 The ADUC702x analog microcontrollers from Analog Devices
4531 include internal flash and use ARM7TDMI cores.
4532 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
4533 The setup command only requires the @var{target} argument
4534 since all devices in this family have the same memory layout.
4536 @example
4537 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
4538 @end example
4539 @end deffn
4541 @deffn {Flash Driver} at91sam3
4542 @cindex at91sam3
4543 All members of the AT91SAM3 microcontroller family from
4544 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
4545 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
4546 that the driver was orginaly developed and tested using the
4547 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
4548 the family was cribbed from the data sheet. @emph{Note to future
4549 readers/updaters: Please remove this worrysome comment after other
4550 chips are confirmed.}
4552 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
4553 have one flash bank. In all cases the flash banks are at
4554 the following fixed locations:
4556 @example
4557 # Flash bank 0 - all chips
4558 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
4559 # Flash bank 1 - only 256K chips
4560 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
4561 @end example
4563 Internally, the AT91SAM3 flash memory is organized as follows.
4564 Unlike the AT91SAM7 chips, these are not used as parameters
4565 to the @command{flash bank} command:
4567 @itemize
4568 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
4569 @item @emph{Bank Size:} 128K/64K Per flash bank
4570 @item @emph{Sectors:} 16 or 8 per bank
4571 @item @emph{SectorSize:} 8K Per Sector
4572 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
4573 @end itemize
4575 The AT91SAM3 driver adds some additional commands:
4577 @deffn Command {at91sam3 gpnvm}
4578 @deffnx Command {at91sam3 gpnvm clear} number
4579 @deffnx Command {at91sam3 gpnvm set} number
4580 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
4581 With no parameters, @command{show} or @command{show all},
4582 shows the status of all GPNVM bits.
4583 With @command{show} @var{number}, displays that bit.
4585 With @command{set} @var{number} or @command{clear} @var{number},
4586 modifies that GPNVM bit.
4587 @end deffn
4589 @deffn Command {at91sam3 info}
4590 This command attempts to display information about the AT91SAM3
4591 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
4592 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
4593 document id: doc6430A] and decodes the values. @emph{Second} it reads the
4594 various clock configuration registers and attempts to display how it
4595 believes the chip is configured. By default, the SLOWCLK is assumed to
4596 be 32768 Hz, see the command @command{at91sam3 slowclk}.
4597 @end deffn
4599 @deffn Command {at91sam3 slowclk} [value]
4600 This command shows/sets the slow clock frequency used in the
4601 @command{at91sam3 info} command calculations above.
4602 @end deffn
4603 @end deffn
4605 @deffn {Flash Driver} at91sam7
4606 All members of the AT91SAM7 microcontroller family from Atmel include
4607 internal flash and use ARM7TDMI cores. The driver automatically
4608 recognizes a number of these chips using the chip identification
4609 register, and autoconfigures itself.
4611 @example
4612 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
4613 @end example
4615 For chips which are not recognized by the controller driver, you must
4616 provide additional parameters in the following order:
4618 @itemize
4619 @item @var{chip_model} ... label used with @command{flash info}
4620 @item @var{banks}
4621 @item @var{sectors_per_bank}
4622 @item @var{pages_per_sector}
4623 @item @var{pages_size}
4624 @item @var{num_nvm_bits}
4625 @item @var{freq_khz} ... required if an external clock is provided,
4626 optional (but recommended) when the oscillator frequency is known
4627 @end itemize
4629 It is recommended that you provide zeroes for all of those values
4630 except the clock frequency, so that everything except that frequency
4631 will be autoconfigured.
4632 Knowing the frequency helps ensure correct timings for flash access.
4634 The flash controller handles erases automatically on a page (128/256 byte)
4635 basis, so explicit erase commands are not necessary for flash programming.
4636 However, there is an ``EraseAll`` command that can erase an entire flash
4637 plane (of up to 256KB), and it will be used automatically when you issue
4638 @command{flash erase_sector} or @command{flash erase_address} commands.
4640 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
4641 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
4642 bit for the processor. Each processor has a number of such bits,
4643 used for controlling features such as brownout detection (so they
4644 are not truly general purpose).
4645 @quotation Note
4646 This assumes that the first flash bank (number 0) is associated with
4647 the appropriate at91sam7 target.
4648 @end quotation
4649 @end deffn
4650 @end deffn
4652 @deffn {Flash Driver} avr
4653 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
4654 @emph{The current implementation is incomplete.}
4655 @comment - defines mass_erase ... pointless given flash_erase_address
4656 @end deffn
4658 @deffn {Flash Driver} lpc2000
4659 Most members of the LPC1700 and LPC2000 microcontroller families from NXP
4660 include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
4662 @quotation Note
4663 There are LPC2000 devices which are not supported by the @var{lpc2000}
4664 driver:
4665 The LPC2888 is supported by the @var{lpc288x} driver.
4666 The LPC29xx family is supported by the @var{lpc2900} driver.
4667 @end quotation
4669 The @var{lpc2000} driver defines two mandatory and one optional parameters,
4670 which must appear in the following order:
4672 @itemize
4673 @item @var{variant} ... required, may be
4674 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
4675 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
4676 or @option{lpc1700} (LPC175x and LPC176x)
4677 @item @var{clock_kHz} ... the frequency, in kiloHertz,
4678 at which the core is running
4679 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
4680 telling the driver to calculate a valid checksum for the exception vector table.
4681 @quotation Note
4682 If you don't provide @option{calc_checksum} when you're writing the vector
4683 table, the boot ROM will almost certainly ignore your flash image.
4684 However, if you do provide it,
4685 with most tool chains @command{verify_image} will fail.
4686 @end quotation
4687 @end itemize
4689 LPC flashes don't require the chip and bus width to be specified.
4691 @example
4692 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
4693 lpc2000_v2 14765 calc_checksum
4694 @end example
4696 @deffn {Command} {lpc2000 part_id} bank
4697 Displays the four byte part identifier associated with
4698 the specified flash @var{bank}.
4699 @end deffn
4700 @end deffn
4702 @deffn {Flash Driver} lpc288x
4703 The LPC2888 microcontroller from NXP needs slightly different flash
4704 support from its lpc2000 siblings.
4705 The @var{lpc288x} driver defines one mandatory parameter,
4706 the programming clock rate in Hz.
4707 LPC flashes don't require the chip and bus width to be specified.
4709 @example
4710 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
4711 @end example
4712 @end deffn
4714 @deffn {Flash Driver} lpc2900
4715 This driver supports the LPC29xx ARM968E based microcontroller family
4716 from NXP.
4718 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
4719 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
4720 sector layout are auto-configured by the driver.
4721 The driver has one additional mandatory parameter: The CPU clock rate
4722 (in kHz) at the time the flash operations will take place. Most of the time this
4723 will not be the crystal frequency, but a higher PLL frequency. The
4724 @code{reset-init} event handler in the board script is usually the place where
4725 you start the PLL.
4727 The driver rejects flashless devices (currently the LPC2930).
4729 The EEPROM in LPC2900 devices is not mapped directly into the address space.
4730 It must be handled much more like NAND flash memory, and will therefore be
4731 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
4733 Sector protection in terms of the LPC2900 is handled transparently. Every time a
4734 sector needs to be erased or programmed, it is automatically unprotected.
4735 What is shown as protection status in the @code{flash info} command, is
4736 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
4737 sector from ever being erased or programmed again. As this is an irreversible
4738 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
4739 and not by the standard @code{flash protect} command.
4741 Example for a 125 MHz clock frequency:
4742 @example
4743 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
4744 @end example
4746 Some @code{lpc2900}-specific commands are defined. In the following command list,
4747 the @var{bank} parameter is the bank number as obtained by the
4748 @code{flash banks} command.
4750 @deffn Command {lpc2900 signature} bank
4751 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
4752 content. This is a hardware feature of the flash block, hence the calculation is
4753 very fast. You may use this to verify the content of a programmed device against
4754 a known signature.
4755 Example:
4756 @example
4757 lpc2900 signature 0
4758 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
4759 @end example
4760 @end deffn
4762 @deffn Command {lpc2900 read_custom} bank filename
4763 Reads the 912 bytes of customer information from the flash index sector, and
4764 saves it to a file in binary format.
4765 Example:
4766 @example
4767 lpc2900 read_custom 0 /path_to/customer_info.bin
4768 @end example
4769 @end deffn
4771 The index sector of the flash is a @emph{write-only} sector. It cannot be
4772 erased! In order to guard against unintentional write access, all following
4773 commands need to be preceeded by a successful call to the @code{password}
4774 command:
4776 @deffn Command {lpc2900 password} bank password
4777 You need to use this command right before each of the following commands:
4778 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
4779 @code{lpc2900 secure_jtag}.
4781 The password string is fixed to "I_know_what_I_am_doing".
4782 Example:
4783 @example
4784 lpc2900 password 0 I_know_what_I_am_doing
4785 Potentially dangerous operation allowed in next command!
4786 @end example
4787 @end deffn
4789 @deffn Command {lpc2900 write_custom} bank filename type
4790 Writes the content of the file into the customer info space of the flash index
4791 sector. The filetype can be specified with the @var{type} field. Possible values
4792 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
4793 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
4794 contain a single section, and the contained data length must be exactly
4795 912 bytes.
4796 @quotation Attention
4797 This cannot be reverted! Be careful!
4798 @end quotation
4799 Example:
4800 @example
4801 lpc2900 write_custom 0 /path_to/customer_info.bin bin
4802 @end example
4803 @end deffn
4805 @deffn Command {lpc2900 secure_sector} bank first last
4806 Secures the sector range from @var{first} to @var{last} (including) against
4807 further program and erase operations. The sector security will be effective
4808 after the next power cycle.
4809 @quotation Attention
4810 This cannot be reverted! Be careful!
4811 @end quotation
4812 Secured sectors appear as @emph{protected} in the @code{flash info} command.
4813 Example:
4814 @example
4815 lpc2900 secure_sector 0 1 1
4816 flash info 0
4817 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
4818 # 0: 0x00000000 (0x2000 8kB) not protected
4819 # 1: 0x00002000 (0x2000 8kB) protected
4820 # 2: 0x00004000 (0x2000 8kB) not protected
4821 @end example
4822 @end deffn
4824 @deffn Command {lpc2900 secure_jtag} bank
4825 Irreversibly disable the JTAG port. The new JTAG security setting will be
4826 effective after the next power cycle.
4827 @quotation Attention
4828 This cannot be reverted! Be careful!
4829 @end quotation
4830 Examples:
4831 @example
4832 lpc2900 secure_jtag 0
4833 @end example
4834 @end deffn
4835 @end deffn
4837 @deffn {Flash Driver} ocl
4838 @emph{No idea what this is, other than using some arm7/arm9 core.}
4840 @example
4841 flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
4842 @end example
4843 @end deffn
4845 @deffn {Flash Driver} pic32mx
4846 The PIC32MX microcontrollers are based on the MIPS 4K cores,
4847 and integrate flash memory.
4849 @example
4850 flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
4851 flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
4852 @end example
4854 @comment numerous *disabled* commands are defined:
4855 @comment - chip_erase ... pointless given flash_erase_address
4856 @comment - lock, unlock ... pointless given protect on/off (yes?)
4857 @comment - pgm_word ... shouldn't bank be deduced from address??
4858 Some pic32mx-specific commands are defined:
4859 @deffn Command {pic32mx pgm_word} address value bank
4860 Programs the specified 32-bit @var{value} at the given @var{address}
4861 in the specified chip @var{bank}.
4862 @end deffn
4863 @deffn Command {pic32mx unlock} bank
4864 Unlock and erase specified chip @var{bank}.
4865 This will remove any Code Protection.
4866 @end deffn
4867 @end deffn
4869 @deffn {Flash Driver} stellaris
4870 All members of the Stellaris LM3Sxxx microcontroller family from
4871 Texas Instruments
4872 include internal flash and use ARM Cortex M3 cores.
4873 The driver automatically recognizes a number of these chips using
4874 the chip identification register, and autoconfigures itself.
4875 @footnote{Currently there is a @command{stellaris mass_erase} command.
4876 That seems pointless since the same effect can be had using the
4877 standard @command{flash erase_address} command.}
4879 @example
4880 flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
4881 @end example
4882 @end deffn
4884 @deffn Command {stellaris recover bank_id}
4885 Performs the @emph{Recovering a "Locked" Device} procedure to
4886 restore the flash specified by @var{bank_id} and its associated
4887 nonvolatile registers to their factory default values (erased).
4888 This is the only way to remove flash protection or re-enable
4889 debugging if that capability has been disabled.
4891 Note that the final "power cycle the chip" step in this procedure
4892 must be performed by hand, since OpenOCD can't do it.
4893 @quotation Warning
4894 if more than one Stellaris chip is connected, the procedure is
4895 applied to all of them.
4896 @end quotation
4897 @end deffn
4899 @deffn {Flash Driver} stm32f1x
4900 All members of the STM32f1x microcontroller family from ST Microelectronics
4901 include internal flash and use ARM Cortex M3 cores.
4902 The driver automatically recognizes a number of these chips using
4903 the chip identification register, and autoconfigures itself.
4905 @example
4906 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
4907 @end example
4909 If you have a target with dual flash banks then define the second bank
4910 as per the following example.
4911 @example
4912 flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
4913 @end example
4915 Some stm32f1x-specific commands
4916 @footnote{Currently there is a @command{stm32f1x mass_erase} command.
4917 That seems pointless since the same effect can be had using the
4918 standard @command{flash erase_address} command.}
4919 are defined:
4921 @deffn Command {stm32f1x lock} num
4922 Locks the entire stm32 device.
4923 The @var{num} parameter is a value shown by @command{flash banks}.
4924 @end deffn
4926 @deffn Command {stm32f1x unlock} num
4927 Unlocks the entire stm32 device.
4928 The @var{num} parameter is a value shown by @command{flash banks}.
4929 @end deffn
4931 @deffn Command {stm32f1x options_read} num
4932 Read and display the stm32 option bytes written by
4933 the @command{stm32f1x options_write} command.
4934 The @var{num} parameter is a value shown by @command{flash banks}.
4935 @end deffn
4937 @deffn Command {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
4938 Writes the stm32 option byte with the specified values.
4939 The @var{num} parameter is a value shown by @command{flash banks}.
4940 @end deffn
4941 @end deffn
4943 @deffn {Flash Driver} stm32f2x
4944 All members of the STM32f2x microcontroller family from ST Microelectronics
4945 include internal flash and use ARM Cortex M3 cores.
4946 The driver automatically recognizes a number of these chips using
4947 the chip identification register, and autoconfigures itself.
4948 @end deffn
4950 @deffn {Flash Driver} str7x
4951 All members of the STR7 microcontroller family from ST Microelectronics
4952 include internal flash and use ARM7TDMI cores.
4953 The @var{str7x} driver defines one mandatory parameter, @var{variant},
4954 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
4956 @example
4957 flash bank $_FLASHNAME str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
4958 @end example
4960 @deffn Command {str7x disable_jtag} bank
4961 Activate the Debug/Readout protection mechanism
4962 for the specified flash bank.
4963 @end deffn
4964 @end deffn
4966 @deffn {Flash Driver} str9x
4967 Most members of the STR9 microcontroller family from ST Microelectronics
4968 include internal flash and use ARM966E cores.
4969 The str9 needs the flash controller to be configured using
4970 the @command{str9x flash_config} command prior to Flash programming.
4972 @example
4973 flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
4974 str9x flash_config 0 4 2 0 0x80000
4975 @end example
4977 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
4978 Configures the str9 flash controller.
4979 The @var{num} parameter is a value shown by @command{flash banks}.
4981 @itemize @bullet
4982 @item @var{bbsr} - Boot Bank Size register
4983 @item @var{nbbsr} - Non Boot Bank Size register
4984 @item @var{bbadr} - Boot Bank Start Address register
4985 @item @var{nbbadr} - Boot Bank Start Address register
4986 @end itemize
4987 @end deffn
4989 @end deffn
4991 @deffn {Flash Driver} tms470
4992 Most members of the TMS470 microcontroller family from Texas Instruments
4993 include internal flash and use ARM7TDMI cores.
4994 This driver doesn't require the chip and bus width to be specified.
4996 Some tms470-specific commands are defined:
4998 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
4999 Saves programming keys in a register, to enable flash erase and write commands.
5000 @end deffn
5002 @deffn Command {tms470 osc_mhz} clock_mhz
5003 Reports the clock speed, which is used to calculate timings.
5004 @end deffn
5006 @deffn Command {tms470 plldis} (0|1)
5007 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
5008 the flash clock.
5009 @end deffn
5010 @end deffn
5012 @deffn {Flash Driver} virtual
5013 This is a special driver that maps a previously defined bank to another
5014 address. All bank settings will be copied from the master physical bank.
5016 The @var{virtual} driver defines one mandatory parameters,
5018 @itemize
5019 @item @var{master_bank} The bank that this virtual address refers to.
5020 @end itemize
5022 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
5023 the flash bank defined at address 0x1fc00000. Any cmds executed on
5024 the virtual banks are actually performed on the physical banks.
5025 @example
5026 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
5027 flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
5028 flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
5029 @end example
5030 @end deffn
5032 @deffn {Flash Driver} fm3
5033 All members of the FM3 microcontroller family from Fujitsu
5034 include internal flash and use ARM Cortex M3 cores.
5035 The @var{fm3} driver uses the @var{target} parameter to select the
5036 correct bank config, it can currently be one of the following:
5037 @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
5038 @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
5040 @example
5041 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
5042 @end example
5043 @end deffn
5045 @subsection str9xpec driver
5046 @cindex str9xpec
5048 Here is some background info to help
5049 you better understand how this driver works. OpenOCD has two flash drivers for
5050 the str9:
5051 @enumerate
5052 @item
5053 Standard driver @option{str9x} programmed via the str9 core. Normally used for
5054 flash programming as it is faster than the @option{str9xpec} driver.
5055 @item
5056 Direct programming @option{str9xpec} using the flash controller. This is an
5057 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
5058 core does not need to be running to program using this flash driver. Typical use
5059 for this driver is locking/unlocking the target and programming the option bytes.
5060 @end enumerate
5062 Before we run any commands using the @option{str9xpec} driver we must first disable
5063 the str9 core. This example assumes the @option{str9xpec} driver has been
5064 configured for flash bank 0.
5065 @example
5066 # assert srst, we do not want core running
5067 # while accessing str9xpec flash driver
5068 jtag_reset 0 1
5069 # turn off target polling
5070 poll off
5071 # disable str9 core
5072 str9xpec enable_turbo 0
5073 # read option bytes
5074 str9xpec options_read 0
5075 # re-enable str9 core
5076 str9xpec disable_turbo 0
5077 poll on
5078 reset halt
5079 @end example
5080 The above example will read the str9 option bytes.
5081 When performing a unlock remember that you will not be able to halt the str9 - it
5082 has been locked. Halting the core is not required for the @option{str9xpec} driver
5083 as mentioned above, just issue the commands above manually or from a telnet prompt.
5085 @deffn {Flash Driver} str9xpec
5086 Only use this driver for locking/unlocking the device or configuring the option bytes.
5087 Use the standard str9 driver for programming.