tcl/target: make sure kex.cfg is not used for Kinetis KE1x families
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
11
12 @include version.texi
13
14 @copying
15
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
20
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
28
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
38
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
45
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
50
51 @summarycontents
52 @contents
53
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
57
58 @insertcopying
59 @end ifnottex
60
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
82 * TFTP:: TFTP
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
88
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
95 @end menu
96
97 @node About
98 @unnumbered About
99 @cindex about
100
101 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
102 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
105 around the world.
106
107 @section What is OpenOCD?
108 @cindex TAP
109 @cindex JTAG
110
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
113 devices.
114
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
121
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
127
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board connect directly to the debug
132 host over USB (and sometimes also to power it over USB).
133
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
140 scan operations.
141
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD supports only
145 debugging, whereas JTAG also supports boundary scan operations.
146
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
151
152
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
154 USB-based, parallel port-based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
156
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
159 (Stellaris LM3, ST STM32 and Energy Micro EFM32) and Intel Quark (x10xx)
160 based cores to be debugged via the GDB protocol.
161
162 @b{Flash Programming:} Flash writing is supported for external
163 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) is included.
167
168 @section OpenOCD Web Site
169
170 The OpenOCD web site provides the latest public news from the community:
171
172 @uref{http://openocd.org/}
173
174 @section Latest User's Guide:
175
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
179
180 @uref{http://openocd.org/doc/html/index.html}
181
182 PDF form is likewise published at:
183
184 @uref{http://openocd.org/doc/pdf/openocd.pdf}
185
186 @section OpenOCD User's Forum
187
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
193
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
195
196 @section OpenOCD User's Mailing List
197
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
200
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
202
203 @section OpenOCD IRC
204
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
207
208 @node Developers
209 @chapter OpenOCD Developer Resources
210 @cindex developers
211
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
216
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
219
220 @section OpenOCD Git Repository
221
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a Git repository hosted at SourceForge. The repository URL is:
224
225 @uref{git://git.code.sf.net/p/openocd/code}
226
227 or via http
228
229 @uref{http://git.code.sf.net/p/openocd/code}
230
231 You may prefer to use a mirror and the HTTP protocol:
232
233 @uref{http://repo.or.cz/r/openocd.git}
234
235 With standard Git tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a Git client:
240
241 @uref{http://repo.or.cz/w/openocd.git}
242
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
245
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
250
251 @section Doxygen Developer Manual
252
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
257
258 @uref{http://openocd.org/doc/doxygen/html/index.html}
259
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration at the top of the source tree.
263
264 @section Gerrit Review System
265
266 All changes in the OpenOCD Git repository go through the web-based Gerrit
267 Code Review System:
268
269 @uref{http://openocd.zylin.com/}
270
271 After a one-time registration and repository setup, anyone can push commits
272 from their local Git repository directly into Gerrit.
273 All users and developers are encouraged to review, test, discuss and vote
274 for changes in Gerrit. The feedback provides the basis for a maintainer to
275 eventually submit the change to the main Git repository.
276
277 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
278 Developer Manual, contains basic information about how to connect a
279 repository to Gerrit, prepare and push patches. Patch authors are expected to
280 maintain their changes while they're in Gerrit, respond to feedback and if
281 necessary rework and push improved versions of the change.
282
283 @section OpenOCD Developer Mailing List
284
285 The OpenOCD Developer Mailing List provides the primary means of
286 communication between developers:
287
288 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
289
290 @section OpenOCD Bug Tracker
291
292 The OpenOCD Bug Tracker is hosted on SourceForge:
293
294 @uref{http://bugs.openocd.org/}
295
296
297 @node Debug Adapter Hardware
298 @chapter Debug Adapter Hardware
299 @cindex dongles
300 @cindex FTDI
301 @cindex wiggler
302 @cindex zy1000
303 @cindex printer port
304 @cindex USB Adapter
305 @cindex RTCK
306
307 Defined: @b{dongle}: A small device that plugs into a computer and serves as
308 an adapter .... [snip]
309
310 In the OpenOCD case, this generally refers to @b{a small adapter} that
311 attaches to your computer via USB or the parallel port. One
312 exception is the Ultimate Solutions ZY1000, packaged as a small box you
313 attach via an ethernet cable. The ZY1000 has the advantage that it does not
314 require any drivers to be installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built-in relay to power cycle targets remotely.
317
318
319 @section Choosing a Dongle
320
321 There are several things you should keep in mind when choosing a dongle.
322
323 @enumerate
324 @item @b{Transport} Does it support the kind of communication that you need?
325 OpenOCD focusses mostly on JTAG. Your version may also support
326 other ways to communicate with target devices.
327 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
328 Does your dongle support it? You might need a level converter.
329 @item @b{Pinout} What pinout does your target board use?
330 Does your dongle support it? You may be able to use jumper
331 wires, or an "octopus" connector, to convert pinouts.
332 @item @b{Connection} Does your computer have the USB, parallel, or
333 Ethernet port needed?
334 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
335 RTCK support (also known as ``adaptive clocking'')?
336 @end enumerate
337
338 @section Stand-alone JTAG Probe
339
340 The ZY1000 from Ultimate Solutions is technically not a dongle but a
341 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
342 running on the developer's host computer.
343 Once installed on a network using DHCP or a static IP assignment, users can
344 access the ZY1000 probe locally or remotely from any host with access to the
345 IP address assigned to the probe.
346 The ZY1000 provides an intuitive web interface with direct access to the
347 OpenOCD debugger.
348 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
349 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
350 the target.
351 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
352 to power cycle the target remotely.
353
354 For more information, visit:
355
356 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/210-zylin-zy1000-main}
357
358 @section USB FT2232 Based
359
360 There are many USB JTAG dongles on the market, many of them based
361 on a chip from ``Future Technology Devices International'' (FTDI)
362 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
363 See: @url{http://www.ftdichip.com} for more information.
364 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
365 chips started to become available in JTAG adapters. Around 2012, a new
366 variant appeared - FT232H - this is a single-channel version of FT2232H.
367 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
368 clocking.)
369
370 The FT2232 chips are flexible enough to support some other
371 transport options, such as SWD or the SPI variants used to
372 program some chips. They have two communications channels,
373 and one can be used for a UART adapter at the same time the
374 other one is used to provide a debug adapter.
375
376 Also, some development boards integrate an FT2232 chip to serve as
377 a built-in low-cost debug adapter and USB-to-serial solution.
378
379 @itemize @bullet
380 @item @b{usbjtag}
381 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
382 @item @b{jtagkey}
383 @* See: @url{http://www.amontec.com/jtagkey.shtml}
384 @item @b{jtagkey2}
385 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
386 @item @b{oocdlink}
387 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
388 @item @b{signalyzer}
389 @* See: @url{http://www.signalyzer.com}
390 @item @b{Stellaris Eval Boards}
391 @* See: @url{http://www.ti.com} - The Stellaris eval boards
392 bundle FT2232-based JTAG and SWD support, which can be used to debug
393 the Stellaris chips. Using separate JTAG adapters is optional.
394 These boards can also be used in a "pass through" mode as JTAG adapters
395 to other target boards, disabling the Stellaris chip.
396 @item @b{TI/Luminary ICDI}
397 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
398 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
399 Evaluation Kits. Like the non-detachable FT2232 support on the other
400 Stellaris eval boards, they can be used to debug other target boards.
401 @item @b{olimex-jtag}
402 @* See: @url{http://www.olimex.com}
403 @item @b{Flyswatter/Flyswatter2}
404 @* See: @url{http://www.tincantools.com}
405 @item @b{turtelizer2}
406 @* See:
407 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
408 @url{http://www.ethernut.de}
409 @item @b{comstick}
410 @* Link: @url{http://www.hitex.com/index.php?id=383}
411 @item @b{stm32stick}
412 @* Link @url{http://www.hitex.com/stm32-stick}
413 @item @b{axm0432_jtag}
414 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
415 to be available anymore as of April 2012.
416 @item @b{cortino}
417 @* Link @url{http://www.hitex.com/index.php?id=cortino}
418 @item @b{dlp-usb1232h}
419 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
420 @item @b{digilent-hs1}
421 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
422 @item @b{opendous}
423 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
424 (OpenHardware).
425 @item @b{JTAG-lock-pick Tiny 2}
426 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
427
428 @item @b{GW16042}
429 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
430 FT2232H-based
431
432 @end itemize
433 @section USB-JTAG / Altera USB-Blaster compatibles
434
435 These devices also show up as FTDI devices, but are not
436 protocol-compatible with the FT2232 devices. They are, however,
437 protocol-compatible among themselves. USB-JTAG devices typically consist
438 of a FT245 followed by a CPLD that understands a particular protocol,
439 or emulates this protocol using some other hardware.
440
441 They may appear under different USB VID/PID depending on the particular
442 product. The driver can be configured to search for any VID/PID pair
443 (see the section on driver commands).
444
445 @itemize
446 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
447 @* Link: @url{http://ixo-jtag.sourceforge.net/}
448 @item @b{Altera USB-Blaster}
449 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
450 @end itemize
451
452 @section USB J-Link based
453 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
454 an example of a microcontroller based JTAG adapter, it uses an
455 AT91SAM764 internally.
456
457 @itemize @bullet
458 @item @b{SEGGER J-Link}
459 @* Link: @url{http://www.segger.com/jlink.html}
460 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
461 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
462 @item @b{IAR J-Link}
463 @end itemize
464
465 @section USB RLINK based
466 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
467 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
468 SWD and not JTAG, thus not supported.
469
470 @itemize @bullet
471 @item @b{Raisonance RLink}
472 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
473 @item @b{STM32 Primer}
474 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
475 @item @b{STM32 Primer2}
476 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
477 @end itemize
478
479 @section USB ST-LINK based
480 ST Micro has an adapter called @b{ST-LINK}.
481 They only work with ST Micro chips, notably STM32 and STM8.
482
483 @itemize @bullet
484 @item @b{ST-LINK}
485 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
486 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
487 @item @b{ST-LINK/V2}
488 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
489 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
490 @end itemize
491
492 For info the original ST-LINK enumerates using the mass storage usb class; however,
493 its implementation is completely broken. The result is this causes issues under Linux.
494 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
495 @itemize @bullet
496 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
497 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
498 @end itemize
499
500 @section USB TI/Stellaris ICDI based
501 Texas Instruments has an adapter called @b{ICDI}.
502 It is not to be confused with the FTDI based adapters that were originally fitted to their
503 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
504
505 @section USB CMSIS-DAP based
506 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
507 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
508
509 @section USB Other
510 @itemize @bullet
511 @item @b{USBprog}
512 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
513
514 @item @b{USB - Presto}
515 @* Link: @url{http://tools.asix.net/prg_presto.htm}
516
517 @item @b{Versaloon-Link}
518 @* Link: @url{http://www.versaloon.com}
519
520 @item @b{ARM-JTAG-EW}
521 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
522
523 @item @b{Buspirate}
524 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
525
526 @item @b{opendous}
527 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
528
529 @item @b{estick}
530 @* Link: @url{http://code.google.com/p/estick-jtag/}
531
532 @item @b{Keil ULINK v1}
533 @* Link: @url{http://www.keil.com/ulink1/}
534 @end itemize
535
536 @section IBM PC Parallel Printer Port Based
537
538 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
539 and the Macraigor Wiggler. There are many clones and variations of
540 these on the market.
541
542 Note that parallel ports are becoming much less common, so if you
543 have the choice you should probably avoid these adapters in favor
544 of USB-based ones.
545
546 @itemize @bullet
547
548 @item @b{Wiggler} - There are many clones of this.
549 @* Link: @url{http://www.macraigor.com/wiggler.htm}
550
551 @item @b{DLC5} - From XILINX - There are many clones of this
552 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
553 produced, PDF schematics are easily found and it is easy to make.
554
555 @item @b{Amontec - JTAG Accelerator}
556 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
557
558 @item @b{Wiggler2}
559 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
560
561 @item @b{Wiggler_ntrst_inverted}
562 @* Yet another variation - See the source code, src/jtag/parport.c
563
564 @item @b{old_amt_wiggler}
565 @* Unknown - probably not on the market today
566
567 @item @b{arm-jtag}
568 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
569
570 @item @b{chameleon}
571 @* Link: @url{http://www.amontec.com/chameleon.shtml}
572
573 @item @b{Triton}
574 @* Unknown.
575
576 @item @b{Lattice}
577 @* ispDownload from Lattice Semiconductor
578 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
579
580 @item @b{flashlink}
581 @* From ST Microsystems;
582 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
583
584 @end itemize
585
586 @section Other...
587 @itemize @bullet
588
589 @item @b{ep93xx}
590 @* An EP93xx based Linux machine using the GPIO pins directly.
591
592 @item @b{at91rm9200}
593 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
594
595 @item @b{bcm2835gpio}
596 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
597
598 @item @b{imx_gpio}
599 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
600
601 @item @b{jtag_vpi}
602 @* A JTAG driver acting as a client for the JTAG VPI server interface.
603 @* Link: @url{http://github.com/fjullien/jtag_vpi}
604
605 @end itemize
606
607 @node About Jim-Tcl
608 @chapter About Jim-Tcl
609 @cindex Jim-Tcl
610 @cindex tcl
611
612 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
613 This programming language provides a simple and extensible
614 command interpreter.
615
616 All commands presented in this Guide are extensions to Jim-Tcl.
617 You can use them as simple commands, without needing to learn
618 much of anything about Tcl.
619 Alternatively, you can write Tcl programs with them.
620
621 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
622 There is an active and responsive community, get on the mailing list
623 if you have any questions. Jim-Tcl maintainers also lurk on the
624 OpenOCD mailing list.
625
626 @itemize @bullet
627 @item @b{Jim vs. Tcl}
628 @* Jim-Tcl is a stripped down version of the well known Tcl language,
629 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
630 fewer features. Jim-Tcl is several dozens of .C files and .H files and
631 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
632 4.2 MB .zip file containing 1540 files.
633
634 @item @b{Missing Features}
635 @* Our practice has been: Add/clone the real Tcl feature if/when
636 needed. We welcome Jim-Tcl improvements, not bloat. Also there
637 are a large number of optional Jim-Tcl features that are not
638 enabled in OpenOCD.
639
640 @item @b{Scripts}
641 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
642 command interpreter today is a mixture of (newer)
643 Jim-Tcl commands, and the (older) original command interpreter.
644
645 @item @b{Commands}
646 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
647 can type a Tcl for() loop, set variables, etc.
648 Some of the commands documented in this guide are implemented
649 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
650
651 @item @b{Historical Note}
652 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
653 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
654 as a Git submodule, which greatly simplified upgrading Jim-Tcl
655 to benefit from new features and bugfixes in Jim-Tcl.
656
657 @item @b{Need a crash course in Tcl?}
658 @*@xref{Tcl Crash Course}.
659 @end itemize
660
661 @node Running
662 @chapter Running
663 @cindex command line options
664 @cindex logfile
665 @cindex directory search
666
667 Properly installing OpenOCD sets up your operating system to grant it access
668 to the debug adapters. On Linux, this usually involves installing a file
669 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
670 that works for many common adapters is shipped with OpenOCD in the
671 @file{contrib} directory. MS-Windows needs
672 complex and confusing driver configuration for every peripheral. Such issues
673 are unique to each operating system, and are not detailed in this User's Guide.
674
675 Then later you will invoke the OpenOCD server, with various options to
676 tell it how each debug session should work.
677 The @option{--help} option shows:
678 @verbatim
679 bash$ openocd --help
680
681 --help | -h display this help
682 --version | -v display OpenOCD version
683 --file | -f use configuration file <name>
684 --search | -s dir to search for config files and scripts
685 --debug | -d set debug level <0-3>
686 --log_output | -l redirect log output to file <name>
687 --command | -c run <command>
688 @end verbatim
689
690 If you don't give any @option{-f} or @option{-c} options,
691 OpenOCD tries to read the configuration file @file{openocd.cfg}.
692 To specify one or more different
693 configuration files, use @option{-f} options. For example:
694
695 @example
696 openocd -f config1.cfg -f config2.cfg -f config3.cfg
697 @end example
698
699 Configuration files and scripts are searched for in
700 @enumerate
701 @item the current directory,
702 @item any search dir specified on the command line using the @option{-s} option,
703 @item any search dir specified using the @command{add_script_search_dir} command,
704 @item @file{$HOME/.openocd} (not on Windows),
705 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
706 @item the site wide script library @file{$pkgdatadir/site} and
707 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
708 @end enumerate
709 The first found file with a matching file name will be used.
710
711 @quotation Note
712 Don't try to use configuration script names or paths which
713 include the "#" character. That character begins Tcl comments.
714 @end quotation
715
716 @section Simple setup, no customization
717
718 In the best case, you can use two scripts from one of the script
719 libraries, hook up your JTAG adapter, and start the server ... and
720 your JTAG setup will just work "out of the box". Always try to
721 start by reusing those scripts, but assume you'll need more
722 customization even if this works. @xref{OpenOCD Project Setup}.
723
724 If you find a script for your JTAG adapter, and for your board or
725 target, you may be able to hook up your JTAG adapter then start
726 the server with some variation of one of the following:
727
728 @example
729 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
730 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
731 @end example
732
733 You might also need to configure which reset signals are present,
734 using @option{-c 'reset_config trst_and_srst'} or something similar.
735 If all goes well you'll see output something like
736
737 @example
738 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
739 For bug reports, read
740 http://openocd.org/doc/doxygen/bugs.html
741 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
742 (mfg: 0x23b, part: 0xba00, ver: 0x3)
743 @end example
744
745 Seeing that "tap/device found" message, and no warnings, means
746 the JTAG communication is working. That's a key milestone, but
747 you'll probably need more project-specific setup.
748
749 @section What OpenOCD does as it starts
750
751 OpenOCD starts by processing the configuration commands provided
752 on the command line or, if there were no @option{-c command} or
753 @option{-f file.cfg} options given, in @file{openocd.cfg}.
754 @xref{configurationstage,,Configuration Stage}.
755 At the end of the configuration stage it verifies the JTAG scan
756 chain defined using those commands; your configuration should
757 ensure that this always succeeds.
758 Normally, OpenOCD then starts running as a server.
759 Alternatively, commands may be used to terminate the configuration
760 stage early, perform work (such as updating some flash memory),
761 and then shut down without acting as a server.
762
763 Once OpenOCD starts running as a server, it waits for connections from
764 clients (Telnet, GDB, RPC) and processes the commands issued through
765 those channels.
766
767 If you are having problems, you can enable internal debug messages via
768 the @option{-d} option.
769
770 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
771 @option{-c} command line switch.
772
773 To enable debug output (when reporting problems or working on OpenOCD
774 itself), use the @option{-d} command line switch. This sets the
775 @option{debug_level} to "3", outputting the most information,
776 including debug messages. The default setting is "2", outputting only
777 informational messages, warnings and errors. You can also change this
778 setting from within a telnet or gdb session using @command{debug_level<n>}
779 (@pxref{debuglevel,,debug_level}).
780
781 You can redirect all output from the server to a file using the
782 @option{-l <logfile>} switch.
783
784 Note! OpenOCD will launch the GDB & telnet server even if it can not
785 establish a connection with the target. In general, it is possible for
786 the JTAG controller to be unresponsive until the target is set up
787 correctly via e.g. GDB monitor commands in a GDB init script.
788
789 @node OpenOCD Project Setup
790 @chapter OpenOCD Project Setup
791
792 To use OpenOCD with your development projects, you need to do more than
793 just connect the JTAG adapter hardware (dongle) to your development board
794 and start the OpenOCD server.
795 You also need to configure your OpenOCD server so that it knows
796 about your adapter and board, and helps your work.
797 You may also want to connect OpenOCD to GDB, possibly
798 using Eclipse or some other GUI.
799
800 @section Hooking up the JTAG Adapter
801
802 Today's most common case is a dongle with a JTAG cable on one side
803 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
804 and a USB cable on the other.
805 Instead of USB, some cables use Ethernet;
806 older ones may use a PC parallel port, or even a serial port.
807
808 @enumerate
809 @item @emph{Start with power to your target board turned off},
810 and nothing connected to your JTAG adapter.
811 If you're particularly paranoid, unplug power to the board.
812 It's important to have the ground signal properly set up,
813 unless you are using a JTAG adapter which provides
814 galvanic isolation between the target board and the
815 debugging host.
816
817 @item @emph{Be sure it's the right kind of JTAG connector.}
818 If your dongle has a 20-pin ARM connector, you need some kind
819 of adapter (or octopus, see below) to hook it up to
820 boards using 14-pin or 10-pin connectors ... or to 20-pin
821 connectors which don't use ARM's pinout.
822
823 In the same vein, make sure the voltage levels are compatible.
824 Not all JTAG adapters have the level shifters needed to work
825 with 1.2 Volt boards.
826
827 @item @emph{Be certain the cable is properly oriented} or you might
828 damage your board. In most cases there are only two possible
829 ways to connect the cable.
830 Connect the JTAG cable from your adapter to the board.
831 Be sure it's firmly connected.
832
833 In the best case, the connector is keyed to physically
834 prevent you from inserting it wrong.
835 This is most often done using a slot on the board's male connector
836 housing, which must match a key on the JTAG cable's female connector.
837 If there's no housing, then you must look carefully and
838 make sure pin 1 on the cable hooks up to pin 1 on the board.
839 Ribbon cables are frequently all grey except for a wire on one
840 edge, which is red. The red wire is pin 1.
841
842 Sometimes dongles provide cables where one end is an ``octopus'' of
843 color coded single-wire connectors, instead of a connector block.
844 These are great when converting from one JTAG pinout to another,
845 but are tedious to set up.
846 Use these with connector pinout diagrams to help you match up the
847 adapter signals to the right board pins.
848
849 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
850 A USB, parallel, or serial port connector will go to the host which
851 you are using to run OpenOCD.
852 For Ethernet, consult the documentation and your network administrator.
853
854 For USB-based JTAG adapters you have an easy sanity check at this point:
855 does the host operating system see the JTAG adapter? If you're running
856 Linux, try the @command{lsusb} command. If that host is an
857 MS-Windows host, you'll need to install a driver before OpenOCD works.
858
859 @item @emph{Connect the adapter's power supply, if needed.}
860 This step is primarily for non-USB adapters,
861 but sometimes USB adapters need extra power.
862
863 @item @emph{Power up the target board.}
864 Unless you just let the magic smoke escape,
865 you're now ready to set up the OpenOCD server
866 so you can use JTAG to work with that board.
867
868 @end enumerate
869
870 Talk with the OpenOCD server using
871 telnet (@code{telnet localhost 4444} on many systems) or GDB.
872 @xref{GDB and OpenOCD}.
873
874 @section Project Directory
875
876 There are many ways you can configure OpenOCD and start it up.
877
878 A simple way to organize them all involves keeping a
879 single directory for your work with a given board.
880 When you start OpenOCD from that directory,
881 it searches there first for configuration files, scripts,
882 files accessed through semihosting,
883 and for code you upload to the target board.
884 It is also the natural place to write files,
885 such as log files and data you download from the board.
886
887 @section Configuration Basics
888
889 There are two basic ways of configuring OpenOCD, and
890 a variety of ways you can mix them.
891 Think of the difference as just being how you start the server:
892
893 @itemize
894 @item Many @option{-f file} or @option{-c command} options on the command line
895 @item No options, but a @dfn{user config file}
896 in the current directory named @file{openocd.cfg}
897 @end itemize
898
899 Here is an example @file{openocd.cfg} file for a setup
900 using a Signalyzer FT2232-based JTAG adapter to talk to
901 a board with an Atmel AT91SAM7X256 microcontroller:
902
903 @example
904 source [find interface/ftdi/signalyzer.cfg]
905
906 # GDB can also flash my flash!
907 gdb_memory_map enable
908 gdb_flash_program enable
909
910 source [find target/sam7x256.cfg]
911 @end example
912
913 Here is the command line equivalent of that configuration:
914
915 @example
916 openocd -f interface/ftdi/signalyzer.cfg \
917 -c "gdb_memory_map enable" \
918 -c "gdb_flash_program enable" \
919 -f target/sam7x256.cfg
920 @end example
921
922 You could wrap such long command lines in shell scripts,
923 each supporting a different development task.
924 One might re-flash the board with a specific firmware version.
925 Another might set up a particular debugging or run-time environment.
926
927 @quotation Important
928 At this writing (October 2009) the command line method has
929 problems with how it treats variables.
930 For example, after @option{-c "set VAR value"}, or doing the
931 same in a script, the variable @var{VAR} will have no value
932 that can be tested in a later script.
933 @end quotation
934
935 Here we will focus on the simpler solution: one user config
936 file, including basic configuration plus any TCL procedures
937 to simplify your work.
938
939 @section User Config Files
940 @cindex config file, user
941 @cindex user config file
942 @cindex config file, overview
943
944 A user configuration file ties together all the parts of a project
945 in one place.
946 One of the following will match your situation best:
947
948 @itemize
949 @item Ideally almost everything comes from configuration files
950 provided by someone else.
951 For example, OpenOCD distributes a @file{scripts} directory
952 (probably in @file{/usr/share/openocd/scripts} on Linux).
953 Board and tool vendors can provide these too, as can individual
954 user sites; the @option{-s} command line option lets you say
955 where to find these files. (@xref{Running}.)
956 The AT91SAM7X256 example above works this way.
957
958 Three main types of non-user configuration file each have their
959 own subdirectory in the @file{scripts} directory:
960
961 @enumerate
962 @item @b{interface} -- one for each different debug adapter;
963 @item @b{board} -- one for each different board
964 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
965 @end enumerate
966
967 Best case: include just two files, and they handle everything else.
968 The first is an interface config file.
969 The second is board-specific, and it sets up the JTAG TAPs and
970 their GDB targets (by deferring to some @file{target.cfg} file),
971 declares all flash memory, and leaves you nothing to do except
972 meet your deadline:
973
974 @example
975 source [find interface/olimex-jtag-tiny.cfg]
976 source [find board/csb337.cfg]
977 @end example
978
979 Boards with a single microcontroller often won't need more
980 than the target config file, as in the AT91SAM7X256 example.
981 That's because there is no external memory (flash, DDR RAM), and
982 the board differences are encapsulated by application code.
983
984 @item Maybe you don't know yet what your board looks like to JTAG.
985 Once you know the @file{interface.cfg} file to use, you may
986 need help from OpenOCD to discover what's on the board.
987 Once you find the JTAG TAPs, you can just search for appropriate
988 target and board
989 configuration files ... or write your own, from the bottom up.
990 @xref{autoprobing,,Autoprobing}.
991
992 @item You can often reuse some standard config files but
993 need to write a few new ones, probably a @file{board.cfg} file.
994 You will be using commands described later in this User's Guide,
995 and working with the guidelines in the next chapter.
996
997 For example, there may be configuration files for your JTAG adapter
998 and target chip, but you need a new board-specific config file
999 giving access to your particular flash chips.
1000 Or you might need to write another target chip configuration file
1001 for a new chip built around the Cortex-M3 core.
1002
1003 @quotation Note
1004 When you write new configuration files, please submit
1005 them for inclusion in the next OpenOCD release.
1006 For example, a @file{board/newboard.cfg} file will help the
1007 next users of that board, and a @file{target/newcpu.cfg}
1008 will help support users of any board using that chip.
1009 @end quotation
1010
1011 @item
1012 You may may need to write some C code.
1013 It may be as simple as supporting a new FT2232 or parport
1014 based adapter; a bit more involved, like a NAND or NOR flash
1015 controller driver; or a big piece of work like supporting
1016 a new chip architecture.
1017 @end itemize
1018
1019 Reuse the existing config files when you can.
1020 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1021 You may find a board configuration that's a good example to follow.
1022
1023 When you write config files, separate the reusable parts
1024 (things every user of that interface, chip, or board needs)
1025 from ones specific to your environment and debugging approach.
1026 @itemize
1027
1028 @item
1029 For example, a @code{gdb-attach} event handler that invokes
1030 the @command{reset init} command will interfere with debugging
1031 early boot code, which performs some of the same actions
1032 that the @code{reset-init} event handler does.
1033
1034 @item
1035 Likewise, the @command{arm9 vector_catch} command (or
1036 @cindex vector_catch
1037 its siblings @command{xscale vector_catch}
1038 and @command{cortex_m vector_catch}) can be a timesaver
1039 during some debug sessions, but don't make everyone use that either.
1040 Keep those kinds of debugging aids in your user config file,
1041 along with messaging and tracing setup.
1042 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1043
1044 @item
1045 You might need to override some defaults.
1046 For example, you might need to move, shrink, or back up the target's
1047 work area if your application needs much SRAM.
1048
1049 @item
1050 TCP/IP port configuration is another example of something which
1051 is environment-specific, and should only appear in
1052 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1053 @end itemize
1054
1055 @section Project-Specific Utilities
1056
1057 A few project-specific utility
1058 routines may well speed up your work.
1059 Write them, and keep them in your project's user config file.
1060
1061 For example, if you are making a boot loader work on a
1062 board, it's nice to be able to debug the ``after it's
1063 loaded to RAM'' parts separately from the finicky early
1064 code which sets up the DDR RAM controller and clocks.
1065 A script like this one, or a more GDB-aware sibling,
1066 may help:
1067
1068 @example
1069 proc ramboot @{ @} @{
1070 # Reset, running the target's "reset-init" scripts
1071 # to initialize clocks and the DDR RAM controller.
1072 # Leave the CPU halted.
1073 reset init
1074
1075 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1076 load_image u-boot.bin 0x20000000
1077
1078 # Start running.
1079 resume 0x20000000
1080 @}
1081 @end example
1082
1083 Then once that code is working you will need to make it
1084 boot from NOR flash; a different utility would help.
1085 Alternatively, some developers write to flash using GDB.
1086 (You might use a similar script if you're working with a flash
1087 based microcontroller application instead of a boot loader.)
1088
1089 @example
1090 proc newboot @{ @} @{
1091 # Reset, leaving the CPU halted. The "reset-init" event
1092 # proc gives faster access to the CPU and to NOR flash;
1093 # "reset halt" would be slower.
1094 reset init
1095
1096 # Write standard version of U-Boot into the first two
1097 # sectors of NOR flash ... the standard version should
1098 # do the same lowlevel init as "reset-init".
1099 flash protect 0 0 1 off
1100 flash erase_sector 0 0 1
1101 flash write_bank 0 u-boot.bin 0x0
1102 flash protect 0 0 1 on
1103
1104 # Reboot from scratch using that new boot loader.
1105 reset run
1106 @}
1107 @end example
1108
1109 You may need more complicated utility procedures when booting
1110 from NAND.
1111 That often involves an extra bootloader stage,
1112 running from on-chip SRAM to perform DDR RAM setup so it can load
1113 the main bootloader code (which won't fit into that SRAM).
1114
1115 Other helper scripts might be used to write production system images,
1116 involving considerably more than just a three stage bootloader.
1117
1118 @section Target Software Changes
1119
1120 Sometimes you may want to make some small changes to the software
1121 you're developing, to help make JTAG debugging work better.
1122 For example, in C or assembly language code you might
1123 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1124 handling issues like:
1125
1126 @itemize @bullet
1127
1128 @item @b{Watchdog Timers}...
1129 Watchog timers are typically used to automatically reset systems if
1130 some application task doesn't periodically reset the timer. (The
1131 assumption is that the system has locked up if the task can't run.)
1132 When a JTAG debugger halts the system, that task won't be able to run
1133 and reset the timer ... potentially causing resets in the middle of
1134 your debug sessions.
1135
1136 It's rarely a good idea to disable such watchdogs, since their usage
1137 needs to be debugged just like all other parts of your firmware.
1138 That might however be your only option.
1139
1140 Look instead for chip-specific ways to stop the watchdog from counting
1141 while the system is in a debug halt state. It may be simplest to set
1142 that non-counting mode in your debugger startup scripts. You may however
1143 need a different approach when, for example, a motor could be physically
1144 damaged by firmware remaining inactive in a debug halt state. That might
1145 involve a type of firmware mode where that "non-counting" mode is disabled
1146 at the beginning then re-enabled at the end; a watchdog reset might fire
1147 and complicate the debug session, but hardware (or people) would be
1148 protected.@footnote{Note that many systems support a "monitor mode" debug
1149 that is a somewhat cleaner way to address such issues. You can think of
1150 it as only halting part of the system, maybe just one task,
1151 instead of the whole thing.
1152 At this writing, January 2010, OpenOCD based debugging does not support
1153 monitor mode debug, only "halt mode" debug.}
1154
1155 @item @b{ARM Semihosting}...
1156 @cindex ARM semihosting
1157 When linked with a special runtime library provided with many
1158 toolchains@footnote{See chapter 8 "Semihosting" in
1159 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1160 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1161 The CodeSourcery EABI toolchain also includes a semihosting library.},
1162 your target code can use I/O facilities on the debug host. That library
1163 provides a small set of system calls which are handled by OpenOCD.
1164 It can let the debugger provide your system console and a file system,
1165 helping with early debugging or providing a more capable environment
1166 for sometimes-complex tasks like installing system firmware onto
1167 NAND or SPI flash.
1168
1169 @item @b{ARM Wait-For-Interrupt}...
1170 Many ARM chips synchronize the JTAG clock using the core clock.
1171 Low power states which stop that core clock thus prevent JTAG access.
1172 Idle loops in tasking environments often enter those low power states
1173 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1174
1175 You may want to @emph{disable that instruction} in source code,
1176 or otherwise prevent using that state,
1177 to ensure you can get JTAG access at any time.@footnote{As a more
1178 polite alternative, some processors have special debug-oriented
1179 registers which can be used to change various features including
1180 how the low power states are clocked while debugging.
1181 The STM32 DBGMCU_CR register is an example; at the cost of extra
1182 power consumption, JTAG can be used during low power states.}
1183 For example, the OpenOCD @command{halt} command may not
1184 work for an idle processor otherwise.
1185
1186 @item @b{Delay after reset}...
1187 Not all chips have good support for debugger access
1188 right after reset; many LPC2xxx chips have issues here.
1189 Similarly, applications that reconfigure pins used for
1190 JTAG access as they start will also block debugger access.
1191
1192 To work with boards like this, @emph{enable a short delay loop}
1193 the first thing after reset, before "real" startup activities.
1194 For example, one second's delay is usually more than enough
1195 time for a JTAG debugger to attach, so that
1196 early code execution can be debugged
1197 or firmware can be replaced.
1198
1199 @item @b{Debug Communications Channel (DCC)}...
1200 Some processors include mechanisms to send messages over JTAG.
1201 Many ARM cores support these, as do some cores from other vendors.
1202 (OpenOCD may be able to use this DCC internally, speeding up some
1203 operations like writing to memory.)
1204
1205 Your application may want to deliver various debugging messages
1206 over JTAG, by @emph{linking with a small library of code}
1207 provided with OpenOCD and using the utilities there to send
1208 various kinds of message.
1209 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1210
1211 @end itemize
1212
1213 @section Target Hardware Setup
1214
1215 Chip vendors often provide software development boards which
1216 are highly configurable, so that they can support all options
1217 that product boards may require. @emph{Make sure that any
1218 jumpers or switches match the system configuration you are
1219 working with.}
1220
1221 Common issues include:
1222
1223 @itemize @bullet
1224
1225 @item @b{JTAG setup} ...
1226 Boards may support more than one JTAG configuration.
1227 Examples include jumpers controlling pullups versus pulldowns
1228 on the nTRST and/or nSRST signals, and choice of connectors
1229 (e.g. which of two headers on the base board,
1230 or one from a daughtercard).
1231 For some Texas Instruments boards, you may need to jumper the
1232 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1233
1234 @item @b{Boot Modes} ...
1235 Complex chips often support multiple boot modes, controlled
1236 by external jumpers. Make sure this is set up correctly.
1237 For example many i.MX boards from NXP need to be jumpered
1238 to "ATX mode" to start booting using the on-chip ROM, when
1239 using second stage bootloader code stored in a NAND flash chip.
1240
1241 Such explicit configuration is common, and not limited to
1242 booting from NAND. You might also need to set jumpers to
1243 start booting using code loaded from an MMC/SD card; external
1244 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1245 flash; some external host; or various other sources.
1246
1247
1248 @item @b{Memory Addressing} ...
1249 Boards which support multiple boot modes may also have jumpers
1250 to configure memory addressing. One board, for example, jumpers
1251 external chipselect 0 (used for booting) to address either
1252 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1253 or NAND flash. When it's jumpered to address NAND flash, that
1254 board must also be told to start booting from on-chip ROM.
1255
1256 Your @file{board.cfg} file may also need to be told this jumper
1257 configuration, so that it can know whether to declare NOR flash
1258 using @command{flash bank} or instead declare NAND flash with
1259 @command{nand device}; and likewise which probe to perform in
1260 its @code{reset-init} handler.
1261
1262 A closely related issue is bus width. Jumpers might need to
1263 distinguish between 8 bit or 16 bit bus access for the flash
1264 used to start booting.
1265
1266 @item @b{Peripheral Access} ...
1267 Development boards generally provide access to every peripheral
1268 on the chip, sometimes in multiple modes (such as by providing
1269 multiple audio codec chips).
1270 This interacts with software
1271 configuration of pin multiplexing, where for example a
1272 given pin may be routed either to the MMC/SD controller
1273 or the GPIO controller. It also often interacts with
1274 configuration jumpers. One jumper may be used to route
1275 signals to an MMC/SD card slot or an expansion bus (which
1276 might in turn affect booting); others might control which
1277 audio or video codecs are used.
1278
1279 @end itemize
1280
1281 Plus you should of course have @code{reset-init} event handlers
1282 which set up the hardware to match that jumper configuration.
1283 That includes in particular any oscillator or PLL used to clock
1284 the CPU, and any memory controllers needed to access external
1285 memory and peripherals. Without such handlers, you won't be
1286 able to access those resources without working target firmware
1287 which can do that setup ... this can be awkward when you're
1288 trying to debug that target firmware. Even if there's a ROM
1289 bootloader which handles a few issues, it rarely provides full
1290 access to all board-specific capabilities.
1291
1292
1293 @node Config File Guidelines
1294 @chapter Config File Guidelines
1295
1296 This chapter is aimed at any user who needs to write a config file,
1297 including developers and integrators of OpenOCD and any user who
1298 needs to get a new board working smoothly.
1299 It provides guidelines for creating those files.
1300
1301 You should find the following directories under
1302 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1303 them as-is where you can; or as models for new files.
1304 @itemize @bullet
1305 @item @file{interface} ...
1306 These are for debug adapters. Files that specify configuration to use
1307 specific JTAG, SWD and other adapters go here.
1308 @item @file{board} ...
1309 Think Circuit Board, PWA, PCB, they go by many names. Board files
1310 contain initialization items that are specific to a board.
1311
1312 They reuse target configuration files, since the same
1313 microprocessor chips are used on many boards,
1314 but support for external parts varies widely. For
1315 example, the SDRAM initialization sequence for the board, or the type
1316 of external flash and what address it uses. Any initialization
1317 sequence to enable that external flash or SDRAM should be found in the
1318 board file. Boards may also contain multiple targets: two CPUs; or
1319 a CPU and an FPGA.
1320 @item @file{target} ...
1321 Think chip. The ``target'' directory represents the JTAG TAPs
1322 on a chip
1323 which OpenOCD should control, not a board. Two common types of targets
1324 are ARM chips and FPGA or CPLD chips.
1325 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1326 the target config file defines all of them.
1327 @item @emph{more} ... browse for other library files which may be useful.
1328 For example, there are various generic and CPU-specific utilities.
1329 @end itemize
1330
1331 The @file{openocd.cfg} user config
1332 file may override features in any of the above files by
1333 setting variables before sourcing the target file, or by adding
1334 commands specific to their situation.
1335
1336 @section Interface Config Files
1337
1338 The user config file
1339 should be able to source one of these files with a command like this:
1340
1341 @example
1342 source [find interface/FOOBAR.cfg]
1343 @end example
1344
1345 A preconfigured interface file should exist for every debug adapter
1346 in use today with OpenOCD.
1347 That said, perhaps some of these config files
1348 have only been used by the developer who created it.
1349
1350 A separate chapter gives information about how to set these up.
1351 @xref{Debug Adapter Configuration}.
1352 Read the OpenOCD source code (and Developer's Guide)
1353 if you have a new kind of hardware interface
1354 and need to provide a driver for it.
1355
1356 @section Board Config Files
1357 @cindex config file, board
1358 @cindex board config file
1359
1360 The user config file
1361 should be able to source one of these files with a command like this:
1362
1363 @example
1364 source [find board/FOOBAR.cfg]
1365 @end example
1366
1367 The point of a board config file is to package everything
1368 about a given board that user config files need to know.
1369 In summary the board files should contain (if present)
1370
1371 @enumerate
1372 @item One or more @command{source [find target/...cfg]} statements
1373 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1374 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1375 @item Target @code{reset} handlers for SDRAM and I/O configuration
1376 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1377 @item All things that are not ``inside a chip''
1378 @end enumerate
1379
1380 Generic things inside target chips belong in target config files,
1381 not board config files. So for example a @code{reset-init} event
1382 handler should know board-specific oscillator and PLL parameters,
1383 which it passes to target-specific utility code.
1384
1385 The most complex task of a board config file is creating such a
1386 @code{reset-init} event handler.
1387 Define those handlers last, after you verify the rest of the board
1388 configuration works.
1389
1390 @subsection Communication Between Config files
1391
1392 In addition to target-specific utility code, another way that
1393 board and target config files communicate is by following a
1394 convention on how to use certain variables.
1395
1396 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1397 Thus the rule we follow in OpenOCD is this: Variables that begin with
1398 a leading underscore are temporary in nature, and can be modified and
1399 used at will within a target configuration file.
1400
1401 Complex board config files can do the things like this,
1402 for a board with three chips:
1403
1404 @example
1405 # Chip #1: PXA270 for network side, big endian
1406 set CHIPNAME network
1407 set ENDIAN big
1408 source [find target/pxa270.cfg]
1409 # on return: _TARGETNAME = network.cpu
1410 # other commands can refer to the "network.cpu" target.
1411 $_TARGETNAME configure .... events for this CPU..
1412
1413 # Chip #2: PXA270 for video side, little endian
1414 set CHIPNAME video
1415 set ENDIAN little
1416 source [find target/pxa270.cfg]
1417 # on return: _TARGETNAME = video.cpu
1418 # other commands can refer to the "video.cpu" target.
1419 $_TARGETNAME configure .... events for this CPU..
1420
1421 # Chip #3: Xilinx FPGA for glue logic
1422 set CHIPNAME xilinx
1423 unset ENDIAN
1424 source [find target/spartan3.cfg]
1425 @end example
1426
1427 That example is oversimplified because it doesn't show any flash memory,
1428 or the @code{reset-init} event handlers to initialize external DRAM
1429 or (assuming it needs it) load a configuration into the FPGA.
1430 Such features are usually needed for low-level work with many boards,
1431 where ``low level'' implies that the board initialization software may
1432 not be working. (That's a common reason to need JTAG tools. Another
1433 is to enable working with microcontroller-based systems, which often
1434 have no debugging support except a JTAG connector.)
1435
1436 Target config files may also export utility functions to board and user
1437 config files. Such functions should use name prefixes, to help avoid
1438 naming collisions.
1439
1440 Board files could also accept input variables from user config files.
1441 For example, there might be a @code{J4_JUMPER} setting used to identify
1442 what kind of flash memory a development board is using, or how to set
1443 up other clocks and peripherals.
1444
1445 @subsection Variable Naming Convention
1446 @cindex variable names
1447
1448 Most boards have only one instance of a chip.
1449 However, it should be easy to create a board with more than
1450 one such chip (as shown above).
1451 Accordingly, we encourage these conventions for naming
1452 variables associated with different @file{target.cfg} files,
1453 to promote consistency and
1454 so that board files can override target defaults.
1455
1456 Inputs to target config files include:
1457
1458 @itemize @bullet
1459 @item @code{CHIPNAME} ...
1460 This gives a name to the overall chip, and is used as part of
1461 tap identifier dotted names.
1462 While the default is normally provided by the chip manufacturer,
1463 board files may need to distinguish between instances of a chip.
1464 @item @code{ENDIAN} ...
1465 By default @option{little} - although chips may hard-wire @option{big}.
1466 Chips that can't change endianness don't need to use this variable.
1467 @item @code{CPUTAPID} ...
1468 When OpenOCD examines the JTAG chain, it can be told verify the
1469 chips against the JTAG IDCODE register.
1470 The target file will hold one or more defaults, but sometimes the
1471 chip in a board will use a different ID (perhaps a newer revision).
1472 @end itemize
1473
1474 Outputs from target config files include:
1475
1476 @itemize @bullet
1477 @item @code{_TARGETNAME} ...
1478 By convention, this variable is created by the target configuration
1479 script. The board configuration file may make use of this variable to
1480 configure things like a ``reset init'' script, or other things
1481 specific to that board and that target.
1482 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1483 @code{_TARGETNAME1}, ... etc.
1484 @end itemize
1485
1486 @subsection The reset-init Event Handler
1487 @cindex event, reset-init
1488 @cindex reset-init handler
1489
1490 Board config files run in the OpenOCD configuration stage;
1491 they can't use TAPs or targets, since they haven't been
1492 fully set up yet.
1493 This means you can't write memory or access chip registers;
1494 you can't even verify that a flash chip is present.
1495 That's done later in event handlers, of which the target @code{reset-init}
1496 handler is one of the most important.
1497
1498 Except on microcontrollers, the basic job of @code{reset-init} event
1499 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1500 Microcontrollers rarely use boot loaders; they run right out of their
1501 on-chip flash and SRAM memory. But they may want to use one of these
1502 handlers too, if just for developer convenience.
1503
1504 @quotation Note
1505 Because this is so very board-specific, and chip-specific, no examples
1506 are included here.
1507 Instead, look at the board config files distributed with OpenOCD.
1508 If you have a boot loader, its source code will help; so will
1509 configuration files for other JTAG tools
1510 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1511 @end quotation
1512
1513 Some of this code could probably be shared between different boards.
1514 For example, setting up a DRAM controller often doesn't differ by
1515 much except the bus width (16 bits or 32?) and memory timings, so a
1516 reusable TCL procedure loaded by the @file{target.cfg} file might take
1517 those as parameters.
1518 Similarly with oscillator, PLL, and clock setup;
1519 and disabling the watchdog.
1520 Structure the code cleanly, and provide comments to help
1521 the next developer doing such work.
1522 (@emph{You might be that next person} trying to reuse init code!)
1523
1524 The last thing normally done in a @code{reset-init} handler is probing
1525 whatever flash memory was configured. For most chips that needs to be
1526 done while the associated target is halted, either because JTAG memory
1527 access uses the CPU or to prevent conflicting CPU access.
1528
1529 @subsection JTAG Clock Rate
1530
1531 Before your @code{reset-init} handler has set up
1532 the PLLs and clocking, you may need to run with
1533 a low JTAG clock rate.
1534 @xref{jtagspeed,,JTAG Speed}.
1535 Then you'd increase that rate after your handler has
1536 made it possible to use the faster JTAG clock.
1537 When the initial low speed is board-specific, for example
1538 because it depends on a board-specific oscillator speed, then
1539 you should probably set it up in the board config file;
1540 if it's target-specific, it belongs in the target config file.
1541
1542 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1543 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1544 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1545 Consult chip documentation to determine the peak JTAG clock rate,
1546 which might be less than that.
1547
1548 @quotation Warning
1549 On most ARMs, JTAG clock detection is coupled to the core clock, so
1550 software using a @option{wait for interrupt} operation blocks JTAG access.
1551 Adaptive clocking provides a partial workaround, but a more complete
1552 solution just avoids using that instruction with JTAG debuggers.
1553 @end quotation
1554
1555 If both the chip and the board support adaptive clocking,
1556 use the @command{jtag_rclk}
1557 command, in case your board is used with JTAG adapter which
1558 also supports it. Otherwise use @command{adapter_khz}.
1559 Set the slow rate at the beginning of the reset sequence,
1560 and the faster rate as soon as the clocks are at full speed.
1561
1562 @anchor{theinitboardprocedure}
1563 @subsection The init_board procedure
1564 @cindex init_board procedure
1565
1566 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1567 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1568 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1569 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1570 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1571 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1572 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1573 Additionally ``linear'' board config file will most likely fail when target config file uses
1574 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1575 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1576 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1577 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1578
1579 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1580 the original), allowing greater code reuse.
1581
1582 @example
1583 ### board_file.cfg ###
1584
1585 # source target file that does most of the config in init_targets
1586 source [find target/target.cfg]
1587
1588 proc enable_fast_clock @{@} @{
1589 # enables fast on-board clock source
1590 # configures the chip to use it
1591 @}
1592
1593 # initialize only board specifics - reset, clock, adapter frequency
1594 proc init_board @{@} @{
1595 reset_config trst_and_srst trst_pulls_srst
1596
1597 $_TARGETNAME configure -event reset-init @{
1598 adapter_khz 1
1599 enable_fast_clock
1600 adapter_khz 10000
1601 @}
1602 @}
1603 @end example
1604
1605 @section Target Config Files
1606 @cindex config file, target
1607 @cindex target config file
1608
1609 Board config files communicate with target config files using
1610 naming conventions as described above, and may source one or
1611 more target config files like this:
1612
1613 @example
1614 source [find target/FOOBAR.cfg]
1615 @end example
1616
1617 The point of a target config file is to package everything
1618 about a given chip that board config files need to know.
1619 In summary the target files should contain
1620
1621 @enumerate
1622 @item Set defaults
1623 @item Add TAPs to the scan chain
1624 @item Add CPU targets (includes GDB support)
1625 @item CPU/Chip/CPU-Core specific features
1626 @item On-Chip flash
1627 @end enumerate
1628
1629 As a rule of thumb, a target file sets up only one chip.
1630 For a microcontroller, that will often include a single TAP,
1631 which is a CPU needing a GDB target, and its on-chip flash.
1632
1633 More complex chips may include multiple TAPs, and the target
1634 config file may need to define them all before OpenOCD
1635 can talk to the chip.
1636 For example, some phone chips have JTAG scan chains that include
1637 an ARM core for operating system use, a DSP,
1638 another ARM core embedded in an image processing engine,
1639 and other processing engines.
1640
1641 @subsection Default Value Boiler Plate Code
1642
1643 All target configuration files should start with code like this,
1644 letting board config files express environment-specific
1645 differences in how things should be set up.
1646
1647 @example
1648 # Boards may override chip names, perhaps based on role,
1649 # but the default should match what the vendor uses
1650 if @{ [info exists CHIPNAME] @} @{
1651 set _CHIPNAME $CHIPNAME
1652 @} else @{
1653 set _CHIPNAME sam7x256
1654 @}
1655
1656 # ONLY use ENDIAN with targets that can change it.
1657 if @{ [info exists ENDIAN] @} @{
1658 set _ENDIAN $ENDIAN
1659 @} else @{
1660 set _ENDIAN little
1661 @}
1662
1663 # TAP identifiers may change as chips mature, for example with
1664 # new revision fields (the "3" here). Pick a good default; you
1665 # can pass several such identifiers to the "jtag newtap" command.
1666 if @{ [info exists CPUTAPID ] @} @{
1667 set _CPUTAPID $CPUTAPID
1668 @} else @{
1669 set _CPUTAPID 0x3f0f0f0f
1670 @}
1671 @end example
1672 @c but 0x3f0f0f0f is for an str73x part ...
1673
1674 @emph{Remember:} Board config files may include multiple target
1675 config files, or the same target file multiple times
1676 (changing at least @code{CHIPNAME}).
1677
1678 Likewise, the target configuration file should define
1679 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1680 use it later on when defining debug targets:
1681
1682 @example
1683 set _TARGETNAME $_CHIPNAME.cpu
1684 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1685 @end example
1686
1687 @subsection Adding TAPs to the Scan Chain
1688 After the ``defaults'' are set up,
1689 add the TAPs on each chip to the JTAG scan chain.
1690 @xref{TAP Declaration}, and the naming convention
1691 for taps.
1692
1693 In the simplest case the chip has only one TAP,
1694 probably for a CPU or FPGA.
1695 The config file for the Atmel AT91SAM7X256
1696 looks (in part) like this:
1697
1698 @example
1699 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1700 @end example
1701
1702 A board with two such at91sam7 chips would be able
1703 to source such a config file twice, with different
1704 values for @code{CHIPNAME}, so
1705 it adds a different TAP each time.
1706
1707 If there are nonzero @option{-expected-id} values,
1708 OpenOCD attempts to verify the actual tap id against those values.
1709 It will issue error messages if there is mismatch, which
1710 can help to pinpoint problems in OpenOCD configurations.
1711
1712 @example
1713 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1714 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1715 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1716 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1717 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1718 @end example
1719
1720 There are more complex examples too, with chips that have
1721 multiple TAPs. Ones worth looking at include:
1722
1723 @itemize
1724 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1725 plus a JRC to enable them
1726 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1727 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1728 is not currently used)
1729 @end itemize
1730
1731 @subsection Add CPU targets
1732
1733 After adding a TAP for a CPU, you should set it up so that
1734 GDB and other commands can use it.
1735 @xref{CPU Configuration}.
1736 For the at91sam7 example above, the command can look like this;
1737 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1738 to little endian, and this chip doesn't support changing that.
1739
1740 @example
1741 set _TARGETNAME $_CHIPNAME.cpu
1742 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1743 @end example
1744
1745 Work areas are small RAM areas associated with CPU targets.
1746 They are used by OpenOCD to speed up downloads,
1747 and to download small snippets of code to program flash chips.
1748 If the chip includes a form of ``on-chip-ram'' - and many do - define
1749 a work area if you can.
1750 Again using the at91sam7 as an example, this can look like:
1751
1752 @example
1753 $_TARGETNAME configure -work-area-phys 0x00200000 \
1754 -work-area-size 0x4000 -work-area-backup 0
1755 @end example
1756
1757 @anchor{definecputargetsworkinginsmp}
1758 @subsection Define CPU targets working in SMP
1759 @cindex SMP
1760 After setting targets, you can define a list of targets working in SMP.
1761
1762 @example
1763 set _TARGETNAME_1 $_CHIPNAME.cpu1
1764 set _TARGETNAME_2 $_CHIPNAME.cpu2
1765 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1766 -coreid 0 -dbgbase $_DAP_DBG1
1767 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1768 -coreid 1 -dbgbase $_DAP_DBG2
1769 #define 2 targets working in smp.
1770 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1771 @end example
1772 In the above example on cortex_a, 2 cpus are working in SMP.
1773 In SMP only one GDB instance is created and :
1774 @itemize @bullet
1775 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1776 @item halt command triggers the halt of all targets in the list.
1777 @item resume command triggers the write context and the restart of all targets in the list.
1778 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1779 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1780 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1781 @end itemize
1782
1783 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1784 command have been implemented.
1785 @itemize @bullet
1786 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1787 @item cortex_a smp_off : disable SMP mode, the current target is the one
1788 displayed in the GDB session, only this target is now controlled by GDB
1789 session. This behaviour is useful during system boot up.
1790 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1791 following example.
1792 @end itemize
1793
1794 @example
1795 >cortex_a smp_gdb
1796 gdb coreid 0 -> -1
1797 #0 : coreid 0 is displayed to GDB ,
1798 #-> -1 : next resume triggers a real resume
1799 > cortex_a smp_gdb 1
1800 gdb coreid 0 -> 1
1801 #0 :coreid 0 is displayed to GDB ,
1802 #->1 : next resume displays coreid 1 to GDB
1803 > resume
1804 > cortex_a smp_gdb
1805 gdb coreid 1 -> 1
1806 #1 :coreid 1 is displayed to GDB ,
1807 #->1 : next resume displays coreid 1 to GDB
1808 > cortex_a smp_gdb -1
1809 gdb coreid 1 -> -1
1810 #1 :coreid 1 is displayed to GDB,
1811 #->-1 : next resume triggers a real resume
1812 @end example
1813
1814
1815 @subsection Chip Reset Setup
1816
1817 As a rule, you should put the @command{reset_config} command
1818 into the board file. Most things you think you know about a
1819 chip can be tweaked by the board.
1820
1821 Some chips have specific ways the TRST and SRST signals are
1822 managed. In the unusual case that these are @emph{chip specific}
1823 and can never be changed by board wiring, they could go here.
1824 For example, some chips can't support JTAG debugging without
1825 both signals.
1826
1827 Provide a @code{reset-assert} event handler if you can.
1828 Such a handler uses JTAG operations to reset the target,
1829 letting this target config be used in systems which don't
1830 provide the optional SRST signal, or on systems where you
1831 don't want to reset all targets at once.
1832 Such a handler might write to chip registers to force a reset,
1833 use a JRC to do that (preferable -- the target may be wedged!),
1834 or force a watchdog timer to trigger.
1835 (For Cortex-M targets, this is not necessary. The target
1836 driver knows how to use trigger an NVIC reset when SRST is
1837 not available.)
1838
1839 Some chips need special attention during reset handling if
1840 they're going to be used with JTAG.
1841 An example might be needing to send some commands right
1842 after the target's TAP has been reset, providing a
1843 @code{reset-deassert-post} event handler that writes a chip
1844 register to report that JTAG debugging is being done.
1845 Another would be reconfiguring the watchdog so that it stops
1846 counting while the core is halted in the debugger.
1847
1848 JTAG clocking constraints often change during reset, and in
1849 some cases target config files (rather than board config files)
1850 are the right places to handle some of those issues.
1851 For example, immediately after reset most chips run using a
1852 slower clock than they will use later.
1853 That means that after reset (and potentially, as OpenOCD
1854 first starts up) they must use a slower JTAG clock rate
1855 than they will use later.
1856 @xref{jtagspeed,,JTAG Speed}.
1857
1858 @quotation Important
1859 When you are debugging code that runs right after chip
1860 reset, getting these issues right is critical.
1861 In particular, if you see intermittent failures when
1862 OpenOCD verifies the scan chain after reset,
1863 look at how you are setting up JTAG clocking.
1864 @end quotation
1865
1866 @anchor{theinittargetsprocedure}
1867 @subsection The init_targets procedure
1868 @cindex init_targets procedure
1869
1870 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1871 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1872 procedure called @code{init_targets}, which will be executed when entering run stage
1873 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1874 Such procedure can be overriden by ``next level'' script (which sources the original).
1875 This concept faciliates code reuse when basic target config files provide generic configuration
1876 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
1877 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1878 because sourcing them executes every initialization commands they provide.
1879
1880 @example
1881 ### generic_file.cfg ###
1882
1883 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1884 # basic initialization procedure ...
1885 @}
1886
1887 proc init_targets @{@} @{
1888 # initializes generic chip with 4kB of flash and 1kB of RAM
1889 setup_my_chip MY_GENERIC_CHIP 4096 1024
1890 @}
1891
1892 ### specific_file.cfg ###
1893
1894 source [find target/generic_file.cfg]
1895
1896 proc init_targets @{@} @{
1897 # initializes specific chip with 128kB of flash and 64kB of RAM
1898 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1899 @}
1900 @end example
1901
1902 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1903 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1904
1905 For an example of this scheme see LPC2000 target config files.
1906
1907 The @code{init_boards} procedure is a similar concept concerning board config files
1908 (@xref{theinitboardprocedure,,The init_board procedure}.)
1909
1910 @anchor{theinittargeteventsprocedure}
1911 @subsection The init_target_events procedure
1912 @cindex init_target_events procedure
1913
1914 A special procedure called @code{init_target_events} is run just after
1915 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1916 procedure}.) and before @code{init_board}
1917 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1918 to set up default target events for the targets that do not have those
1919 events already assigned.
1920
1921 @subsection ARM Core Specific Hacks
1922
1923 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1924 special high speed download features - enable it.
1925
1926 If present, the MMU, the MPU and the CACHE should be disabled.
1927
1928 Some ARM cores are equipped with trace support, which permits
1929 examination of the instruction and data bus activity. Trace
1930 activity is controlled through an ``Embedded Trace Module'' (ETM)
1931 on one of the core's scan chains. The ETM emits voluminous data
1932 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1933 If you are using an external trace port,
1934 configure it in your board config file.
1935 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1936 configure it in your target config file.
1937
1938 @example
1939 etm config $_TARGETNAME 16 normal full etb
1940 etb config $_TARGETNAME $_CHIPNAME.etb
1941 @end example
1942
1943 @subsection Internal Flash Configuration
1944
1945 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1946
1947 @b{Never ever} in the ``target configuration file'' define any type of
1948 flash that is external to the chip. (For example a BOOT flash on
1949 Chip Select 0.) Such flash information goes in a board file - not
1950 the TARGET (chip) file.
1951
1952 Examples:
1953 @itemize @bullet
1954 @item at91sam7x256 - has 256K flash YES enable it.
1955 @item str912 - has flash internal YES enable it.
1956 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1957 @item pxa270 - again - CS0 flash - it goes in the board file.
1958 @end itemize
1959
1960 @anchor{translatingconfigurationfiles}
1961 @section Translating Configuration Files
1962 @cindex translation
1963 If you have a configuration file for another hardware debugger
1964 or toolset (Abatron, BDI2000, BDI3000, CCS,
1965 Lauterbach, SEGGER, Macraigor, etc.), translating
1966 it into OpenOCD syntax is often quite straightforward. The most tricky
1967 part of creating a configuration script is oftentimes the reset init
1968 sequence where e.g. PLLs, DRAM and the like is set up.
1969
1970 One trick that you can use when translating is to write small
1971 Tcl procedures to translate the syntax into OpenOCD syntax. This
1972 can avoid manual translation errors and make it easier to
1973 convert other scripts later on.
1974
1975 Example of transforming quirky arguments to a simple search and
1976 replace job:
1977
1978 @example
1979 # Lauterbach syntax(?)
1980 #
1981 # Data.Set c15:0x042f %long 0x40000015
1982 #
1983 # OpenOCD syntax when using procedure below.
1984 #
1985 # setc15 0x01 0x00050078
1986
1987 proc setc15 @{regs value@} @{
1988 global TARGETNAME
1989
1990 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
1991
1992 arm mcr 15 [expr ($regs>>12)&0x7] \
1993 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
1994 [expr ($regs>>8)&0x7] $value
1995 @}
1996 @end example
1997
1998
1999
2000 @node Server Configuration
2001 @chapter Server Configuration
2002 @cindex initialization
2003 The commands here are commonly found in the openocd.cfg file and are
2004 used to specify what TCP/IP ports are used, and how GDB should be
2005 supported.
2006
2007 @anchor{configurationstage}
2008 @section Configuration Stage
2009 @cindex configuration stage
2010 @cindex config command
2011
2012 When the OpenOCD server process starts up, it enters a
2013 @emph{configuration stage} which is the only time that
2014 certain commands, @emph{configuration commands}, may be issued.
2015 Normally, configuration commands are only available
2016 inside startup scripts.
2017
2018 In this manual, the definition of a configuration command is
2019 presented as a @emph{Config Command}, not as a @emph{Command}
2020 which may be issued interactively.
2021 The runtime @command{help} command also highlights configuration
2022 commands, and those which may be issued at any time.
2023
2024 Those configuration commands include declaration of TAPs,
2025 flash banks,
2026 the interface used for JTAG communication,
2027 and other basic setup.
2028 The server must leave the configuration stage before it
2029 may access or activate TAPs.
2030 After it leaves this stage, configuration commands may no
2031 longer be issued.
2032
2033 @anchor{enteringtherunstage}
2034 @section Entering the Run Stage
2035
2036 The first thing OpenOCD does after leaving the configuration
2037 stage is to verify that it can talk to the scan chain
2038 (list of TAPs) which has been configured.
2039 It will warn if it doesn't find TAPs it expects to find,
2040 or finds TAPs that aren't supposed to be there.
2041 You should see no errors at this point.
2042 If you see errors, resolve them by correcting the
2043 commands you used to configure the server.
2044 Common errors include using an initial JTAG speed that's too
2045 fast, and not providing the right IDCODE values for the TAPs
2046 on the scan chain.
2047
2048 Once OpenOCD has entered the run stage, a number of commands
2049 become available.
2050 A number of these relate to the debug targets you may have declared.
2051 For example, the @command{mww} command will not be available until
2052 a target has been successfuly instantiated.
2053 If you want to use those commands, you may need to force
2054 entry to the run stage.
2055
2056 @deffn {Config Command} init
2057 This command terminates the configuration stage and
2058 enters the run stage. This helps when you need to have
2059 the startup scripts manage tasks such as resetting the target,
2060 programming flash, etc. To reset the CPU upon startup, add "init" and
2061 "reset" at the end of the config script or at the end of the OpenOCD
2062 command line using the @option{-c} command line switch.
2063
2064 If this command does not appear in any startup/configuration file
2065 OpenOCD executes the command for you after processing all
2066 configuration files and/or command line options.
2067
2068 @b{NOTE:} This command normally occurs at or near the end of your
2069 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2070 targets ready. For example: If your openocd.cfg file needs to
2071 read/write memory on your target, @command{init} must occur before
2072 the memory read/write commands. This includes @command{nand probe}.
2073 @end deffn
2074
2075 @deffn {Overridable Procedure} jtag_init
2076 This is invoked at server startup to verify that it can talk
2077 to the scan chain (list of TAPs) which has been configured.
2078
2079 The default implementation first tries @command{jtag arp_init},
2080 which uses only a lightweight JTAG reset before examining the
2081 scan chain.
2082 If that fails, it tries again, using a harder reset
2083 from the overridable procedure @command{init_reset}.
2084
2085 Implementations must have verified the JTAG scan chain before
2086 they return.
2087 This is done by calling @command{jtag arp_init}
2088 (or @command{jtag arp_init-reset}).
2089 @end deffn
2090
2091 @anchor{tcpipports}
2092 @section TCP/IP Ports
2093 @cindex TCP port
2094 @cindex server
2095 @cindex port
2096 @cindex security
2097 The OpenOCD server accepts remote commands in several syntaxes.
2098 Each syntax uses a different TCP/IP port, which you may specify
2099 only during configuration (before those ports are opened).
2100
2101 For reasons including security, you may wish to prevent remote
2102 access using one or more of these ports.
2103 In such cases, just specify the relevant port number as "disabled".
2104 If you disable all access through TCP/IP, you will need to
2105 use the command line @option{-pipe} option.
2106
2107 @deffn {Command} gdb_port [number]
2108 @cindex GDB server
2109 Normally gdb listens to a TCP/IP port, but GDB can also
2110 communicate via pipes(stdin/out or named pipes). The name
2111 "gdb_port" stuck because it covers probably more than 90% of
2112 the normal use cases.
2113
2114 No arguments reports GDB port. "pipe" means listen to stdin
2115 output to stdout, an integer is base port number, "disabled"
2116 disables the gdb server.
2117
2118 When using "pipe", also use log_output to redirect the log
2119 output to a file so as not to flood the stdin/out pipes.
2120
2121 The -p/--pipe option is deprecated and a warning is printed
2122 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2123
2124 Any other string is interpreted as named pipe to listen to.
2125 Output pipe is the same name as input pipe, but with 'o' appended,
2126 e.g. /var/gdb, /var/gdbo.
2127
2128 The GDB port for the first target will be the base port, the
2129 second target will listen on gdb_port + 1, and so on.
2130 When not specified during the configuration stage,
2131 the port @var{number} defaults to 3333.
2132
2133 Note: when using "gdb_port pipe", increasing the default remote timeout in
2134 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2135 cause initialization to fail with "Unknown remote qXfer reply: OK".
2136
2137 @end deffn
2138
2139 @deffn {Command} tcl_port [number]
2140 Specify or query the port used for a simplified RPC
2141 connection that can be used by clients to issue TCL commands and get the
2142 output from the Tcl engine.
2143 Intended as a machine interface.
2144 When not specified during the configuration stage,
2145 the port @var{number} defaults to 6666.
2146 When specified as "disabled", this service is not activated.
2147 @end deffn
2148
2149 @deffn {Command} telnet_port [number]
2150 Specify or query the
2151 port on which to listen for incoming telnet connections.
2152 This port is intended for interaction with one human through TCL commands.
2153 When not specified during the configuration stage,
2154 the port @var{number} defaults to 4444.
2155 When specified as "disabled", this service is not activated.
2156 @end deffn
2157
2158 @anchor{gdbconfiguration}
2159 @section GDB Configuration
2160 @cindex GDB
2161 @cindex GDB configuration
2162 You can reconfigure some GDB behaviors if needed.
2163 The ones listed here are static and global.
2164 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2165 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2166
2167 @anchor{gdbbreakpointoverride}
2168 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2169 Force breakpoint type for gdb @command{break} commands.
2170 This option supports GDB GUIs which don't
2171 distinguish hard versus soft breakpoints, if the default OpenOCD and
2172 GDB behaviour is not sufficient. GDB normally uses hardware
2173 breakpoints if the memory map has been set up for flash regions.
2174 @end deffn
2175
2176 @anchor{gdbflashprogram}
2177 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2178 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2179 vFlash packet is received.
2180 The default behaviour is @option{enable}.
2181 @end deffn
2182
2183 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2184 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2185 requested. GDB will then know when to set hardware breakpoints, and program flash
2186 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2187 for flash programming to work.
2188 Default behaviour is @option{enable}.
2189 @xref{gdbflashprogram,,gdb_flash_program}.
2190 @end deffn
2191
2192 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2193 Specifies whether data aborts cause an error to be reported
2194 by GDB memory read packets.
2195 The default behaviour is @option{disable};
2196 use @option{enable} see these errors reported.
2197 @end deffn
2198
2199 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2200 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2201 The default behaviour is @option{enable}.
2202 @end deffn
2203
2204 @deffn {Command} gdb_save_tdesc
2205 Saves the target descripton file to the local file system.
2206
2207 The file name is @i{target_name}.xml.
2208 @end deffn
2209
2210 @anchor{eventpolling}
2211 @section Event Polling
2212
2213 Hardware debuggers are parts of asynchronous systems,
2214 where significant events can happen at any time.
2215 The OpenOCD server needs to detect some of these events,
2216 so it can report them to through TCL command line
2217 or to GDB.
2218
2219 Examples of such events include:
2220
2221 @itemize
2222 @item One of the targets can stop running ... maybe it triggers
2223 a code breakpoint or data watchpoint, or halts itself.
2224 @item Messages may be sent over ``debug message'' channels ... many
2225 targets support such messages sent over JTAG,
2226 for receipt by the person debugging or tools.
2227 @item Loss of power ... some adapters can detect these events.
2228 @item Resets not issued through JTAG ... such reset sources
2229 can include button presses or other system hardware, sometimes
2230 including the target itself (perhaps through a watchdog).
2231 @item Debug instrumentation sometimes supports event triggering
2232 such as ``trace buffer full'' (so it can quickly be emptied)
2233 or other signals (to correlate with code behavior).
2234 @end itemize
2235
2236 None of those events are signaled through standard JTAG signals.
2237 However, most conventions for JTAG connectors include voltage
2238 level and system reset (SRST) signal detection.
2239 Some connectors also include instrumentation signals, which
2240 can imply events when those signals are inputs.
2241
2242 In general, OpenOCD needs to periodically check for those events,
2243 either by looking at the status of signals on the JTAG connector
2244 or by sending synchronous ``tell me your status'' JTAG requests
2245 to the various active targets.
2246 There is a command to manage and monitor that polling,
2247 which is normally done in the background.
2248
2249 @deffn Command poll [@option{on}|@option{off}]
2250 Poll the current target for its current state.
2251 (Also, @pxref{targetcurstate,,target curstate}.)
2252 If that target is in debug mode, architecture
2253 specific information about the current state is printed.
2254 An optional parameter
2255 allows background polling to be enabled and disabled.
2256
2257 You could use this from the TCL command shell, or
2258 from GDB using @command{monitor poll} command.
2259 Leave background polling enabled while you're using GDB.
2260 @example
2261 > poll
2262 background polling: on
2263 target state: halted
2264 target halted in ARM state due to debug-request, \
2265 current mode: Supervisor
2266 cpsr: 0x800000d3 pc: 0x11081bfc
2267 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2268 >
2269 @end example
2270 @end deffn
2271
2272 @node Debug Adapter Configuration
2273 @chapter Debug Adapter Configuration
2274 @cindex config file, interface
2275 @cindex interface config file
2276
2277 Correctly installing OpenOCD includes making your operating system give
2278 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2279 are used to select which one is used, and to configure how it is used.
2280
2281 @quotation Note
2282 Because OpenOCD started out with a focus purely on JTAG, you may find
2283 places where it wrongly presumes JTAG is the only transport protocol
2284 in use. Be aware that recent versions of OpenOCD are removing that
2285 limitation. JTAG remains more functional than most other transports.
2286 Other transports do not support boundary scan operations, or may be
2287 specific to a given chip vendor. Some might be usable only for
2288 programming flash memory, instead of also for debugging.
2289 @end quotation
2290
2291 Debug Adapters/Interfaces/Dongles are normally configured
2292 through commands in an interface configuration
2293 file which is sourced by your @file{openocd.cfg} file, or
2294 through a command line @option{-f interface/....cfg} option.
2295
2296 @example
2297 source [find interface/olimex-jtag-tiny.cfg]
2298 @end example
2299
2300 These commands tell
2301 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2302 A few cases are so simple that you only need to say what driver to use:
2303
2304 @example
2305 # jlink interface
2306 interface jlink
2307 @end example
2308
2309 Most adapters need a bit more configuration than that.
2310
2311
2312 @section Interface Configuration
2313
2314 The interface command tells OpenOCD what type of debug adapter you are
2315 using. Depending on the type of adapter, you may need to use one or
2316 more additional commands to further identify or configure the adapter.
2317
2318 @deffn {Config Command} {interface} name
2319 Use the interface driver @var{name} to connect to the
2320 target.
2321 @end deffn
2322
2323 @deffn Command {interface_list}
2324 List the debug adapter drivers that have been built into
2325 the running copy of OpenOCD.
2326 @end deffn
2327 @deffn Command {interface transports} transport_name+
2328 Specifies the transports supported by this debug adapter.
2329 The adapter driver builds-in similar knowledge; use this only
2330 when external configuration (such as jumpering) changes what
2331 the hardware can support.
2332 @end deffn
2333
2334
2335
2336 @deffn Command {adapter_name}
2337 Returns the name of the debug adapter driver being used.
2338 @end deffn
2339
2340 @section Interface Drivers
2341
2342 Each of the interface drivers listed here must be explicitly
2343 enabled when OpenOCD is configured, in order to be made
2344 available at run time.
2345
2346 @deffn {Interface Driver} {amt_jtagaccel}
2347 Amontec Chameleon in its JTAG Accelerator configuration,
2348 connected to a PC's EPP mode parallel port.
2349 This defines some driver-specific commands:
2350
2351 @deffn {Config Command} {parport_port} number
2352 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2353 the number of the @file{/dev/parport} device.
2354 @end deffn
2355
2356 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2357 Displays status of RTCK option.
2358 Optionally sets that option first.
2359 @end deffn
2360 @end deffn
2361
2362 @deffn {Interface Driver} {arm-jtag-ew}
2363 Olimex ARM-JTAG-EW USB adapter
2364 This has one driver-specific command:
2365
2366 @deffn Command {armjtagew_info}
2367 Logs some status
2368 @end deffn
2369 @end deffn
2370
2371 @deffn {Interface Driver} {at91rm9200}
2372 Supports bitbanged JTAG from the local system,
2373 presuming that system is an Atmel AT91rm9200
2374 and a specific set of GPIOs is used.
2375 @c command: at91rm9200_device NAME
2376 @c chooses among list of bit configs ... only one option
2377 @end deffn
2378
2379 @deffn {Interface Driver} {cmsis-dap}
2380 ARM CMSIS-DAP compliant based adapter.
2381
2382 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2383 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2384 the driver will attempt to auto detect the CMSIS-DAP device.
2385 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2386 @example
2387 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2388 @end example
2389 @end deffn
2390
2391 @deffn {Config Command} {cmsis_dap_serial} [serial]
2392 Specifies the @var{serial} of the CMSIS-DAP device to use.
2393 If not specified, serial numbers are not considered.
2394 @end deffn
2395
2396 @deffn {Command} {cmsis-dap info}
2397 Display various device information, like hardware version, firmware version, current bus status.
2398 @end deffn
2399 @end deffn
2400
2401 @deffn {Interface Driver} {dummy}
2402 A dummy software-only driver for debugging.
2403 @end deffn
2404
2405 @deffn {Interface Driver} {ep93xx}
2406 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2407 @end deffn
2408
2409 @deffn {Interface Driver} {ftdi}
2410 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2411 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2412
2413 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2414 bypassing intermediate libraries like libftdi or D2XX.
2415
2416 Support for new FTDI based adapters can be added competely through
2417 configuration files, without the need to patch and rebuild OpenOCD.
2418
2419 The driver uses a signal abstraction to enable Tcl configuration files to
2420 define outputs for one or several FTDI GPIO. These outputs can then be
2421 controlled using the @command{ftdi_set_signal} command. Special signal names
2422 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2423 will be used for their customary purpose. Inputs can be read using the
2424 @command{ftdi_get_signal} command.
2425
2426 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2427 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2428 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2429 required by the protocol, to tell the adapter to drive the data output onto
2430 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2431
2432 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2433 be controlled differently. In order to support tristateable signals such as
2434 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2435 signal. The following output buffer configurations are supported:
2436
2437 @itemize @minus
2438 @item Push-pull with one FTDI output as (non-)inverted data line
2439 @item Open drain with one FTDI output as (non-)inverted output-enable
2440 @item Tristate with one FTDI output as (non-)inverted data line and another
2441 FTDI output as (non-)inverted output-enable
2442 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2443 switching data and direction as necessary
2444 @end itemize
2445
2446 These interfaces have several commands, used to configure the driver
2447 before initializing the JTAG scan chain:
2448
2449 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2450 The vendor ID and product ID of the adapter. Up to eight
2451 [@var{vid}, @var{pid}] pairs may be given, e.g.
2452 @example
2453 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2454 @end example
2455 @end deffn
2456
2457 @deffn {Config Command} {ftdi_device_desc} description
2458 Provides the USB device description (the @emph{iProduct string})
2459 of the adapter. If not specified, the device description is ignored
2460 during device selection.
2461 @end deffn
2462
2463 @deffn {Config Command} {ftdi_serial} serial-number
2464 Specifies the @var{serial-number} of the adapter to use,
2465 in case the vendor provides unique IDs and more than one adapter
2466 is connected to the host.
2467 If not specified, serial numbers are not considered.
2468 (Note that USB serial numbers can be arbitrary Unicode strings,
2469 and are not restricted to containing only decimal digits.)
2470 @end deffn
2471
2472 @deffn {Config Command} {ftdi_location} <bus>:<port>[,<port>]...
2473 Specifies the physical USB port of the adapter to use. The path
2474 roots at @var{bus} and walks down the physical ports, with each
2475 @var{port} option specifying a deeper level in the bus topology, the last
2476 @var{port} denoting where the target adapter is actually plugged.
2477 The USB bus topology can be queried with the command @emph{lsusb -t}.
2478
2479 This command is only available if your libusb1 is at least version 1.0.16.
2480 @end deffn
2481
2482 @deffn {Config Command} {ftdi_channel} channel
2483 Selects the channel of the FTDI device to use for MPSSE operations. Most
2484 adapters use the default, channel 0, but there are exceptions.
2485 @end deffn
2486
2487 @deffn {Config Command} {ftdi_layout_init} data direction
2488 Specifies the initial values of the FTDI GPIO data and direction registers.
2489 Each value is a 16-bit number corresponding to the concatenation of the high
2490 and low FTDI GPIO registers. The values should be selected based on the
2491 schematics of the adapter, such that all signals are set to safe levels with
2492 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2493 and initially asserted reset signals.
2494 @end deffn
2495
2496 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2497 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2498 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2499 register bitmasks to tell the driver the connection and type of the output
2500 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2501 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2502 used with inverting data inputs and @option{-data} with non-inverting inputs.
2503 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2504 not-output-enable) input to the output buffer is connected. The options
2505 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2506 with the method @command{ftdi_get_signal}.
2507
2508 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2509 simple open-collector transistor driver would be specified with @option{-oe}
2510 only. In that case the signal can only be set to drive low or to Hi-Z and the
2511 driver will complain if the signal is set to drive high. Which means that if
2512 it's a reset signal, @command{reset_config} must be specified as
2513 @option{srst_open_drain}, not @option{srst_push_pull}.
2514
2515 A special case is provided when @option{-data} and @option{-oe} is set to the
2516 same bitmask. Then the FTDI pin is considered being connected straight to the
2517 target without any buffer. The FTDI pin is then switched between output and
2518 input as necessary to provide the full set of low, high and Hi-Z
2519 characteristics. In all other cases, the pins specified in a signal definition
2520 are always driven by the FTDI.
2521
2522 If @option{-alias} or @option{-nalias} is used, the signal is created
2523 identical (or with data inverted) to an already specified signal
2524 @var{name}.
2525 @end deffn
2526
2527 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2528 Set a previously defined signal to the specified level.
2529 @itemize @minus
2530 @item @option{0}, drive low
2531 @item @option{1}, drive high
2532 @item @option{z}, set to high-impedance
2533 @end itemize
2534 @end deffn
2535
2536 @deffn {Command} {ftdi_get_signal} name
2537 Get the value of a previously defined signal.
2538 @end deffn
2539
2540 @deffn {Command} {ftdi_tdo_sample_edge} @option{rising}|@option{falling}
2541 Configure TCK edge at which the adapter samples the value of the TDO signal
2542
2543 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2544 peculiar at high JTAG clock speeds. However, FTDI chips offer a possiblity to sample
2545 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2546 stability at higher JTAG clocks.
2547 @itemize @minus
2548 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2549 @item @option{falling}, sample TDO on falling edge of TCK
2550 @end itemize
2551 @end deffn
2552
2553 For example adapter definitions, see the configuration files shipped in the
2554 @file{interface/ftdi} directory.
2555
2556 @end deffn
2557
2558 @deffn {Interface Driver} {remote_bitbang}
2559 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2560 with a remote process and sends ASCII encoded bitbang requests to that process
2561 instead of directly driving JTAG.
2562
2563 The remote_bitbang driver is useful for debugging software running on
2564 processors which are being simulated.
2565
2566 @deffn {Config Command} {remote_bitbang_port} number
2567 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2568 sockets instead of TCP.
2569 @end deffn
2570
2571 @deffn {Config Command} {remote_bitbang_host} hostname
2572 Specifies the hostname of the remote process to connect to using TCP, or the
2573 name of the UNIX socket to use if remote_bitbang_port is 0.
2574 @end deffn
2575
2576 For example, to connect remotely via TCP to the host foobar you might have
2577 something like:
2578
2579 @example
2580 interface remote_bitbang
2581 remote_bitbang_port 3335
2582 remote_bitbang_host foobar
2583 @end example
2584
2585 To connect to another process running locally via UNIX sockets with socket
2586 named mysocket:
2587
2588 @example
2589 interface remote_bitbang
2590 remote_bitbang_port 0
2591 remote_bitbang_host mysocket
2592 @end example
2593 @end deffn
2594
2595 @deffn {Interface Driver} {usb_blaster}
2596 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2597 for FTDI chips. These interfaces have several commands, used to
2598 configure the driver before initializing the JTAG scan chain:
2599
2600 @deffn {Config Command} {usb_blaster_device_desc} description
2601 Provides the USB device description (the @emph{iProduct string})
2602 of the FTDI FT245 device. If not
2603 specified, the FTDI default value is used. This setting is only valid
2604 if compiled with FTD2XX support.
2605 @end deffn
2606
2607 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2608 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2609 default values are used.
2610 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2611 Altera USB-Blaster (default):
2612 @example
2613 usb_blaster_vid_pid 0x09FB 0x6001
2614 @end example
2615 The following VID/PID is for Kolja Waschk's USB JTAG:
2616 @example
2617 usb_blaster_vid_pid 0x16C0 0x06AD
2618 @end example
2619 @end deffn
2620
2621 @deffn {Command} {usb_blaster_pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2622 Sets the state or function of the unused GPIO pins on USB-Blasters
2623 (pins 6 and 8 on the female JTAG header). These pins can be used as
2624 SRST and/or TRST provided the appropriate connections are made on the
2625 target board.
2626
2627 For example, to use pin 6 as SRST:
2628 @example
2629 usb_blaster_pin pin6 s
2630 reset_config srst_only
2631 @end example
2632 @end deffn
2633
2634 @deffn {Command} {usb_blaster_lowlevel_driver} (@option{ftdi}|@option{ublast2})
2635 Chooses the low level access method for the adapter. If not specified,
2636 @option{ftdi} is selected unless it wasn't enabled during the
2637 configure stage. USB-Blaster II needs @option{ublast2}.
2638 @end deffn
2639
2640 @deffn {Command} {usb_blaster_firmware} @var{path}
2641 This command specifies @var{path} to access USB-Blaster II firmware
2642 image. To be used with USB-Blaster II only.
2643 @end deffn
2644
2645 @end deffn
2646
2647 @deffn {Interface Driver} {gw16012}
2648 Gateworks GW16012 JTAG programmer.
2649 This has one driver-specific command:
2650
2651 @deffn {Config Command} {parport_port} [port_number]
2652 Display either the address of the I/O port
2653 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2654 If a parameter is provided, first switch to use that port.
2655 This is a write-once setting.
2656 @end deffn
2657 @end deffn
2658
2659 @deffn {Interface Driver} {jlink}
2660 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2661 transports.
2662
2663 @quotation Compatibility Note
2664 SEGGER released many firmware versions for the many harware versions they
2665 produced. OpenOCD was extensively tested and intended to run on all of them,
2666 but some combinations were reported as incompatible. As a general
2667 recommendation, it is advisable to use the latest firmware version
2668 available for each hardware version. However the current V8 is a moving
2669 target, and SEGGER firmware versions released after the OpenOCD was
2670 released may not be compatible. In such cases it is recommended to
2671 revert to the last known functional version. For 0.5.0, this is from
2672 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2673 version is from "May 3 2012 18:36:22", packed with 4.46f.
2674 @end quotation
2675
2676 @deffn {Command} {jlink hwstatus}
2677 Display various hardware related information, for example target voltage and pin
2678 states.
2679 @end deffn
2680 @deffn {Command} {jlink freemem}
2681 Display free device internal memory.
2682 @end deffn
2683 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2684 Set the JTAG command version to be used. Without argument, show the actual JTAG
2685 command version.
2686 @end deffn
2687 @deffn {Command} {jlink config}
2688 Display the device configuration.
2689 @end deffn
2690 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2691 Set the target power state on JTAG-pin 19. Without argument, show the target
2692 power state.
2693 @end deffn
2694 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2695 Set the MAC address of the device. Without argument, show the MAC address.
2696 @end deffn
2697 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2698 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2699 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2700 IP configuration.
2701 @end deffn
2702 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2703 Set the USB address of the device. This will also change the USB Product ID
2704 (PID) of the device. Without argument, show the USB address.
2705 @end deffn
2706 @deffn {Command} {jlink config reset}
2707 Reset the current configuration.
2708 @end deffn
2709 @deffn {Command} {jlink config write}
2710 Write the current configuration to the internal persistent storage.
2711 @end deffn
2712 @deffn {Command} {jlink emucom write <channel> <data>}
2713 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2714 pairs.
2715
2716 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2717 the EMUCOM channel 0x10:
2718 @example
2719 > jlink emucom write 0x10 aa0b23
2720 @end example
2721 @end deffn
2722 @deffn {Command} {jlink emucom read <channel> <length>}
2723 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2724 pairs.
2725
2726 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2727 @example
2728 > jlink emucom read 0x0 4
2729 77a90000
2730 @end example
2731 @end deffn
2732 @deffn {Config} {jlink usb} <@option{0} to @option{3}>
2733 Set the USB address of the interface, in case more than one adapter is connected
2734 to the host. If not specified, USB addresses are not considered. Device
2735 selection via USB address is deprecated and the serial number should be used
2736 instead.
2737
2738 As a configuration command, it can be used only before 'init'.
2739 @end deffn
2740 @deffn {Config} {jlink serial} <serial number>
2741 Set the serial number of the interface, in case more than one adapter is
2742 connected to the host. If not specified, serial numbers are not considered.
2743
2744 As a configuration command, it can be used only before 'init'.
2745 @end deffn
2746 @end deffn
2747
2748 @deffn {Interface Driver} {kitprog}
2749 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2750 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2751 families, but it is possible to use it with some other devices. If you are using
2752 this adapter with a PSoC or a PRoC, you may need to add
2753 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2754 configuration script.
2755
2756 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2757 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2758 be used with this driver, and must either be used with the cmsis-dap driver or
2759 switched back to KitProg mode. See the Cypress KitProg User Guide for
2760 instructions on how to switch KitProg modes.
2761
2762 Known limitations:
2763 @itemize @bullet
2764 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2765 and 2.7 MHz.
2766 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2767 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2768 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2769 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2770 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2771 SWD sequence must be sent after every target reset in order to re-establish
2772 communications with the target.
2773 @item Due in part to the limitation above, KitProg devices with firmware below
2774 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
2775 communicate with PSoC 5LP devices. This is because, assuming debug is not
2776 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
2777 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
2778 could only be sent with an acquisition sequence.
2779 @end itemize
2780
2781 @deffn {Config Command} {kitprog_init_acquire_psoc}
2782 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
2783 Please be aware that the acquisition sequence hard-resets the target.
2784 @end deffn
2785
2786 @deffn {Config Command} {kitprog_serial} serial
2787 Select a KitProg device by its @var{serial}. If left unspecified, the first
2788 device detected by OpenOCD will be used.
2789 @end deffn
2790
2791 @deffn {Command} {kitprog acquire_psoc}
2792 Run a PSoC acquisition sequence immediately. Typically, this should not be used
2793 outside of the target-specific configuration scripts since it hard-resets the
2794 target as a side-effect.
2795 This is necessary for "reset halt" on some PSoC 4 series devices.
2796 @end deffn
2797
2798 @deffn {Command} {kitprog info}
2799 Display various adapter information, such as the hardware version, firmware
2800 version, and target voltage.
2801 @end deffn
2802 @end deffn
2803
2804 @deffn {Interface Driver} {parport}
2805 Supports PC parallel port bit-banging cables:
2806 Wigglers, PLD download cable, and more.
2807 These interfaces have several commands, used to configure the driver
2808 before initializing the JTAG scan chain:
2809
2810 @deffn {Config Command} {parport_cable} name
2811 Set the layout of the parallel port cable used to connect to the target.
2812 This is a write-once setting.
2813 Currently valid cable @var{name} values include:
2814
2815 @itemize @minus
2816 @item @b{altium} Altium Universal JTAG cable.
2817 @item @b{arm-jtag} Same as original wiggler except SRST and
2818 TRST connections reversed and TRST is also inverted.
2819 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2820 in configuration mode. This is only used to
2821 program the Chameleon itself, not a connected target.
2822 @item @b{dlc5} The Xilinx Parallel cable III.
2823 @item @b{flashlink} The ST Parallel cable.
2824 @item @b{lattice} Lattice ispDOWNLOAD Cable
2825 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2826 some versions of
2827 Amontec's Chameleon Programmer. The new version available from
2828 the website uses the original Wiggler layout ('@var{wiggler}')
2829 @item @b{triton} The parallel port adapter found on the
2830 ``Karo Triton 1 Development Board''.
2831 This is also the layout used by the HollyGates design
2832 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2833 @item @b{wiggler} The original Wiggler layout, also supported by
2834 several clones, such as the Olimex ARM-JTAG
2835 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2836 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2837 @end itemize
2838 @end deffn
2839
2840 @deffn {Config Command} {parport_port} [port_number]
2841 Display either the address of the I/O port
2842 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2843 If a parameter is provided, first switch to use that port.
2844 This is a write-once setting.
2845
2846 When using PPDEV to access the parallel port, use the number of the parallel port:
2847 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2848 you may encounter a problem.
2849 @end deffn
2850
2851 @deffn Command {parport_toggling_time} [nanoseconds]
2852 Displays how many nanoseconds the hardware needs to toggle TCK;
2853 the parport driver uses this value to obey the
2854 @command{adapter_khz} configuration.
2855 When the optional @var{nanoseconds} parameter is given,
2856 that setting is changed before displaying the current value.
2857
2858 The default setting should work reasonably well on commodity PC hardware.
2859 However, you may want to calibrate for your specific hardware.
2860 @quotation Tip
2861 To measure the toggling time with a logic analyzer or a digital storage
2862 oscilloscope, follow the procedure below:
2863 @example
2864 > parport_toggling_time 1000
2865 > adapter_khz 500
2866 @end example
2867 This sets the maximum JTAG clock speed of the hardware, but
2868 the actual speed probably deviates from the requested 500 kHz.
2869 Now, measure the time between the two closest spaced TCK transitions.
2870 You can use @command{runtest 1000} or something similar to generate a
2871 large set of samples.
2872 Update the setting to match your measurement:
2873 @example
2874 > parport_toggling_time <measured nanoseconds>
2875 @end example
2876 Now the clock speed will be a better match for @command{adapter_khz rate}
2877 commands given in OpenOCD scripts and event handlers.
2878
2879 You can do something similar with many digital multimeters, but note
2880 that you'll probably need to run the clock continuously for several
2881 seconds before it decides what clock rate to show. Adjust the
2882 toggling time up or down until the measured clock rate is a good
2883 match for the adapter_khz rate you specified; be conservative.
2884 @end quotation
2885 @end deffn
2886
2887 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2888 This will configure the parallel driver to write a known
2889 cable-specific value to the parallel interface on exiting OpenOCD.
2890 @end deffn
2891
2892 For example, the interface configuration file for a
2893 classic ``Wiggler'' cable on LPT2 might look something like this:
2894
2895 @example
2896 interface parport
2897 parport_port 0x278
2898 parport_cable wiggler
2899 @end example
2900 @end deffn
2901
2902 @deffn {Interface Driver} {presto}
2903 ASIX PRESTO USB JTAG programmer.
2904 @deffn {Config Command} {presto_serial} serial_string
2905 Configures the USB serial number of the Presto device to use.
2906 @end deffn
2907 @end deffn
2908
2909 @deffn {Interface Driver} {rlink}
2910 Raisonance RLink USB adapter
2911 @end deffn
2912
2913 @deffn {Interface Driver} {usbprog}
2914 usbprog is a freely programmable USB adapter.
2915 @end deffn
2916
2917 @deffn {Interface Driver} {vsllink}
2918 vsllink is part of Versaloon which is a versatile USB programmer.
2919
2920 @quotation Note
2921 This defines quite a few driver-specific commands,
2922 which are not currently documented here.
2923 @end quotation
2924 @end deffn
2925
2926 @anchor{hla_interface}
2927 @deffn {Interface Driver} {hla}
2928 This is a driver that supports multiple High Level Adapters.
2929 This type of adapter does not expose some of the lower level api's
2930 that OpenOCD would normally use to access the target.
2931
2932 Currently supported adapters include the ST STLINK and TI ICDI.
2933 STLINK firmware version >= V2.J21.S4 recommended due to issues with earlier
2934 versions of firmware where serial number is reset after first use. Suggest
2935 using ST firmware update utility to upgrade STLINK firmware even if current
2936 version reported is V2.J21.S4.
2937
2938 @deffn {Config Command} {hla_device_desc} description
2939 Currently Not Supported.
2940 @end deffn
2941
2942 @deffn {Config Command} {hla_serial} serial
2943 Specifies the serial number of the adapter.
2944 @end deffn
2945
2946 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
2947 Specifies the adapter layout to use.
2948 @end deffn
2949
2950 @deffn {Config Command} {hla_vid_pid} vid pid
2951 The vendor ID and product ID of the device.
2952 @end deffn
2953
2954 @deffn {Command} {hla_command} command
2955 Execute a custom adapter-specific command. The @var{command} string is
2956 passed as is to the underlying adapter layout handler.
2957 @end deffn
2958 @end deffn
2959
2960 @deffn {Interface Driver} {opendous}
2961 opendous-jtag is a freely programmable USB adapter.
2962 @end deffn
2963
2964 @deffn {Interface Driver} {ulink}
2965 This is the Keil ULINK v1 JTAG debugger.
2966 @end deffn
2967
2968 @deffn {Interface Driver} {ZY1000}
2969 This is the Zylin ZY1000 JTAG debugger.
2970 @end deffn
2971
2972 @quotation Note
2973 This defines some driver-specific commands,
2974 which are not currently documented here.
2975 @end quotation
2976
2977 @deffn Command power [@option{on}|@option{off}]
2978 Turn power switch to target on/off.
2979 No arguments: print status.
2980 @end deffn
2981
2982 @deffn {Interface Driver} {bcm2835gpio}
2983 This SoC is present in Raspberry Pi which is a cheap single-board computer
2984 exposing some GPIOs on its expansion header.
2985
2986 The driver accesses memory-mapped GPIO peripheral registers directly
2987 for maximum performance, but the only possible race condition is for
2988 the pins' modes/muxing (which is highly unlikely), so it should be
2989 able to coexist nicely with both sysfs bitbanging and various
2990 peripherals' kernel drivers. The driver restores the previous
2991 configuration on exit.
2992
2993 See @file{interface/raspberrypi-native.cfg} for a sample config and
2994 pinout.
2995
2996 @end deffn
2997
2998 @deffn {Interface Driver} {imx_gpio}
2999 i.MX SoC is present in many community boards. Wandboard is an example
3000 of the one which is most popular.
3001
3002 This driver is mostly the same as bcm2835gpio.
3003
3004 See @file{interface/imx-native.cfg} for a sample config and
3005 pinout.
3006
3007 @end deffn
3008
3009
3010 @deffn {Interface Driver} {openjtag}
3011 OpenJTAG compatible USB adapter.
3012 This defines some driver-specific commands:
3013
3014 @deffn {Config Command} {openjtag_variant} variant
3015 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
3016 Currently valid @var{variant} values include:
3017
3018 @itemize @minus
3019 @item @b{standard} Standard variant (default).
3020 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3021 (see @uref{http://www.cypress.com/?rID=82870}).
3022 @end itemize
3023 @end deffn
3024
3025 @deffn {Config Command} {openjtag_device_desc} string
3026 The USB device description string of the adapter.
3027 This value is only used with the standard variant.
3028 @end deffn
3029 @end deffn
3030
3031 @section Transport Configuration
3032 @cindex Transport
3033 As noted earlier, depending on the version of OpenOCD you use,
3034 and the debug adapter you are using,
3035 several transports may be available to
3036 communicate with debug targets (or perhaps to program flash memory).
3037 @deffn Command {transport list}
3038 displays the names of the transports supported by this
3039 version of OpenOCD.
3040 @end deffn
3041
3042 @deffn Command {transport select} @option{transport_name}
3043 Select which of the supported transports to use in this OpenOCD session.
3044
3045 When invoked with @option{transport_name}, attempts to select the named
3046 transport. The transport must be supported by the debug adapter
3047 hardware and by the version of OpenOCD you are using (including the
3048 adapter's driver).
3049
3050 If no transport has been selected and no @option{transport_name} is
3051 provided, @command{transport select} auto-selects the first transport
3052 supported by the debug adapter.
3053
3054 @command{transport select} always returns the name of the session's selected
3055 transport, if any.
3056 @end deffn
3057
3058 @subsection JTAG Transport
3059 @cindex JTAG
3060 JTAG is the original transport supported by OpenOCD, and most
3061 of the OpenOCD commands support it.
3062 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3063 each of which must be explicitly declared.
3064 JTAG supports both debugging and boundary scan testing.
3065 Flash programming support is built on top of debug support.
3066
3067 JTAG transport is selected with the command @command{transport select
3068 jtag}. Unless your adapter uses @ref{hla_interface,the hla interface
3069 driver}, in which case the command is @command{transport select
3070 hla_jtag}.
3071
3072 @subsection SWD Transport
3073 @cindex SWD
3074 @cindex Serial Wire Debug
3075 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3076 Debug Access Point (DAP, which must be explicitly declared.
3077 (SWD uses fewer signal wires than JTAG.)
3078 SWD is debug-oriented, and does not support boundary scan testing.
3079 Flash programming support is built on top of debug support.
3080 (Some processors support both JTAG and SWD.)
3081
3082 SWD transport is selected with the command @command{transport select
3083 swd}. Unless your adapter uses @ref{hla_interface,the hla interface
3084 driver}, in which case the command is @command{transport select
3085 hla_swd}.
3086
3087 @deffn Command {swd newdap} ...
3088 Declares a single DAP which uses SWD transport.
3089 Parameters are currently the same as "jtag newtap" but this is
3090 expected to change.
3091 @end deffn
3092 @deffn Command {swd wcr trn prescale}
3093 Updates TRN (turnaraound delay) and prescaling.fields of the
3094 Wire Control Register (WCR).
3095 No parameters: displays current settings.
3096 @end deffn
3097
3098 @subsection SPI Transport
3099 @cindex SPI
3100 @cindex Serial Peripheral Interface
3101 The Serial Peripheral Interface (SPI) is a general purpose transport
3102 which uses four wire signaling. Some processors use it as part of a
3103 solution for flash programming.
3104
3105 @anchor{jtagspeed}
3106 @section JTAG Speed
3107 JTAG clock setup is part of system setup.
3108 It @emph{does not belong with interface setup} since any interface
3109 only knows a few of the constraints for the JTAG clock speed.
3110 Sometimes the JTAG speed is
3111 changed during the target initialization process: (1) slow at
3112 reset, (2) program the CPU clocks, (3) run fast.
3113 Both the "slow" and "fast" clock rates are functions of the
3114 oscillators used, the chip, the board design, and sometimes
3115 power management software that may be active.
3116
3117 The speed used during reset, and the scan chain verification which
3118 follows reset, can be adjusted using a @code{reset-start}
3119 target event handler.
3120 It can then be reconfigured to a faster speed by a
3121 @code{reset-init} target event handler after it reprograms those
3122 CPU clocks, or manually (if something else, such as a boot loader,
3123 sets up those clocks).
3124 @xref{targetevents,,Target Events}.
3125 When the initial low JTAG speed is a chip characteristic, perhaps
3126 because of a required oscillator speed, provide such a handler
3127 in the target config file.
3128 When that speed is a function of a board-specific characteristic
3129 such as which speed oscillator is used, it belongs in the board
3130 config file instead.
3131 In both cases it's safest to also set the initial JTAG clock rate
3132 to that same slow speed, so that OpenOCD never starts up using a
3133 clock speed that's faster than the scan chain can support.
3134
3135 @example
3136 jtag_rclk 3000
3137 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3138 @end example
3139
3140 If your system supports adaptive clocking (RTCK), configuring
3141 JTAG to use that is probably the most robust approach.
3142 However, it introduces delays to synchronize clocks; so it
3143 may not be the fastest solution.
3144
3145 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3146 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3147 which support adaptive clocking.
3148
3149 @deffn {Command} adapter_khz max_speed_kHz
3150 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3151 JTAG interfaces usually support a limited number of
3152 speeds. The speed actually used won't be faster
3153 than the speed specified.
3154
3155 Chip data sheets generally include a top JTAG clock rate.
3156 The actual rate is often a function of a CPU core clock,
3157 and is normally less than that peak rate.
3158 For example, most ARM cores accept at most one sixth of the CPU clock.
3159
3160 Speed 0 (khz) selects RTCK method.
3161 @xref{faqrtck,,FAQ RTCK}.
3162 If your system uses RTCK, you won't need to change the
3163 JTAG clocking after setup.
3164 Not all interfaces, boards, or targets support ``rtck''.
3165 If the interface device can not
3166 support it, an error is returned when you try to use RTCK.
3167 @end deffn
3168
3169 @defun jtag_rclk fallback_speed_kHz
3170 @cindex adaptive clocking
3171 @cindex RTCK
3172 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3173 If that fails (maybe the interface, board, or target doesn't
3174 support it), falls back to the specified frequency.
3175 @example
3176 # Fall back to 3mhz if RTCK is not supported
3177 jtag_rclk 3000
3178 @end example
3179 @end defun
3180
3181 @node Reset Configuration
3182 @chapter Reset Configuration
3183 @cindex Reset Configuration
3184
3185 Every system configuration may require a different reset
3186 configuration. This can also be quite confusing.
3187 Resets also interact with @var{reset-init} event handlers,
3188 which do things like setting up clocks and DRAM, and
3189 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3190 They can also interact with JTAG routers.
3191 Please see the various board files for examples.
3192
3193 @quotation Note
3194 To maintainers and integrators:
3195 Reset configuration touches several things at once.
3196 Normally the board configuration file
3197 should define it and assume that the JTAG adapter supports
3198 everything that's wired up to the board's JTAG connector.
3199
3200 However, the target configuration file could also make note
3201 of something the silicon vendor has done inside the chip,
3202 which will be true for most (or all) boards using that chip.
3203 And when the JTAG adapter doesn't support everything, the
3204 user configuration file will need to override parts of
3205 the reset configuration provided by other files.
3206 @end quotation
3207
3208 @section Types of Reset
3209
3210 There are many kinds of reset possible through JTAG, but
3211 they may not all work with a given board and adapter.
3212 That's part of why reset configuration can be error prone.
3213
3214 @itemize @bullet
3215 @item
3216 @emph{System Reset} ... the @emph{SRST} hardware signal
3217 resets all chips connected to the JTAG adapter, such as processors,
3218 power management chips, and I/O controllers. Normally resets triggered
3219 with this signal behave exactly like pressing a RESET button.
3220 @item
3221 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3222 just the TAP controllers connected to the JTAG adapter.
3223 Such resets should not be visible to the rest of the system; resetting a
3224 device's TAP controller just puts that controller into a known state.
3225 @item
3226 @emph{Emulation Reset} ... many devices can be reset through JTAG
3227 commands. These resets are often distinguishable from system
3228 resets, either explicitly (a "reset reason" register says so)
3229 or implicitly (not all parts of the chip get reset).
3230 @item
3231 @emph{Other Resets} ... system-on-chip devices often support
3232 several other types of reset.
3233 You may need to arrange that a watchdog timer stops
3234 while debugging, preventing a watchdog reset.
3235 There may be individual module resets.
3236 @end itemize
3237
3238 In the best case, OpenOCD can hold SRST, then reset
3239 the TAPs via TRST and send commands through JTAG to halt the
3240 CPU at the reset vector before the 1st instruction is executed.
3241 Then when it finally releases the SRST signal, the system is
3242 halted under debugger control before any code has executed.
3243 This is the behavior required to support the @command{reset halt}
3244 and @command{reset init} commands; after @command{reset init} a
3245 board-specific script might do things like setting up DRAM.
3246 (@xref{resetcommand,,Reset Command}.)
3247
3248 @anchor{srstandtrstissues}
3249 @section SRST and TRST Issues
3250
3251 Because SRST and TRST are hardware signals, they can have a
3252 variety of system-specific constraints. Some of the most
3253 common issues are:
3254
3255 @itemize @bullet
3256
3257 @item @emph{Signal not available} ... Some boards don't wire
3258 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3259 support such signals even if they are wired up.
3260 Use the @command{reset_config} @var{signals} options to say
3261 when either of those signals is not connected.
3262 When SRST is not available, your code might not be able to rely
3263 on controllers having been fully reset during code startup.
3264 Missing TRST is not a problem, since JTAG-level resets can
3265 be triggered using with TMS signaling.
3266
3267 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3268 adapter will connect SRST to TRST, instead of keeping them separate.
3269 Use the @command{reset_config} @var{combination} options to say
3270 when those signals aren't properly independent.
3271
3272 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3273 delay circuit, reset supervisor, or on-chip features can extend
3274 the effect of a JTAG adapter's reset for some time after the adapter
3275 stops issuing the reset. For example, there may be chip or board
3276 requirements that all reset pulses last for at least a
3277 certain amount of time; and reset buttons commonly have
3278 hardware debouncing.
3279 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3280 commands to say when extra delays are needed.
3281
3282 @item @emph{Drive type} ... Reset lines often have a pullup
3283 resistor, letting the JTAG interface treat them as open-drain
3284 signals. But that's not a requirement, so the adapter may need
3285 to use push/pull output drivers.
3286 Also, with weak pullups it may be advisable to drive
3287 signals to both levels (push/pull) to minimize rise times.
3288 Use the @command{reset_config} @var{trst_type} and
3289 @var{srst_type} parameters to say how to drive reset signals.
3290
3291 @item @emph{Special initialization} ... Targets sometimes need
3292 special JTAG initialization sequences to handle chip-specific
3293 issues (not limited to errata).
3294 For example, certain JTAG commands might need to be issued while
3295 the system as a whole is in a reset state (SRST active)
3296 but the JTAG scan chain is usable (TRST inactive).
3297 Many systems treat combined assertion of SRST and TRST as a
3298 trigger for a harder reset than SRST alone.
3299 Such custom reset handling is discussed later in this chapter.
3300 @end itemize
3301
3302 There can also be other issues.
3303 Some devices don't fully conform to the JTAG specifications.
3304 Trivial system-specific differences are common, such as
3305 SRST and TRST using slightly different names.
3306 There are also vendors who distribute key JTAG documentation for
3307 their chips only to developers who have signed a Non-Disclosure
3308 Agreement (NDA).
3309
3310 Sometimes there are chip-specific extensions like a requirement to use
3311 the normally-optional TRST signal (precluding use of JTAG adapters which
3312 don't pass TRST through), or needing extra steps to complete a TAP reset.
3313
3314 In short, SRST and especially TRST handling may be very finicky,
3315 needing to cope with both architecture and board specific constraints.
3316
3317 @section Commands for Handling Resets
3318
3319 @deffn {Command} adapter_nsrst_assert_width milliseconds
3320 Minimum amount of time (in milliseconds) OpenOCD should wait
3321 after asserting nSRST (active-low system reset) before
3322 allowing it to be deasserted.
3323 @end deffn
3324
3325 @deffn {Command} adapter_nsrst_delay milliseconds
3326 How long (in milliseconds) OpenOCD should wait after deasserting
3327 nSRST (active-low system reset) before starting new JTAG operations.
3328 When a board has a reset button connected to SRST line it will
3329 probably have hardware debouncing, implying you should use this.
3330 @end deffn
3331
3332 @deffn {Command} jtag_ntrst_assert_width milliseconds
3333 Minimum amount of time (in milliseconds) OpenOCD should wait
3334 after asserting nTRST (active-low JTAG TAP reset) before
3335 allowing it to be deasserted.
3336 @end deffn
3337
3338 @deffn {Command} jtag_ntrst_delay milliseconds
3339 How long (in milliseconds) OpenOCD should wait after deasserting
3340 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3341 @end deffn
3342
3343 @deffn {Command} reset_config mode_flag ...
3344 This command displays or modifies the reset configuration
3345 of your combination of JTAG board and target in target
3346 configuration scripts.
3347
3348 Information earlier in this section describes the kind of problems
3349 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3350 As a rule this command belongs only in board config files,
3351 describing issues like @emph{board doesn't connect TRST};
3352 or in user config files, addressing limitations derived
3353 from a particular combination of interface and board.
3354 (An unlikely example would be using a TRST-only adapter
3355 with a board that only wires up SRST.)
3356
3357 The @var{mode_flag} options can be specified in any order, but only one
3358 of each type -- @var{signals}, @var{combination}, @var{gates},
3359 @var{trst_type}, @var{srst_type} and @var{connect_type}
3360 -- may be specified at a time.
3361 If you don't provide a new value for a given type, its previous
3362 value (perhaps the default) is unchanged.
3363 For example, this means that you don't need to say anything at all about
3364 TRST just to declare that if the JTAG adapter should want to drive SRST,
3365 it must explicitly be driven high (@option{srst_push_pull}).
3366
3367 @itemize
3368 @item
3369 @var{signals} can specify which of the reset signals are connected.
3370 For example, If the JTAG interface provides SRST, but the board doesn't
3371 connect that signal properly, then OpenOCD can't use it.
3372 Possible values are @option{none} (the default), @option{trst_only},
3373 @option{srst_only} and @option{trst_and_srst}.
3374
3375 @quotation Tip
3376 If your board provides SRST and/or TRST through the JTAG connector,
3377 you must declare that so those signals can be used.
3378 @end quotation
3379
3380 @item
3381 The @var{combination} is an optional value specifying broken reset
3382 signal implementations.
3383 The default behaviour if no option given is @option{separate},
3384 indicating everything behaves normally.
3385 @option{srst_pulls_trst} states that the
3386 test logic is reset together with the reset of the system (e.g. NXP
3387 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3388 the system is reset together with the test logic (only hypothetical, I
3389 haven't seen hardware with such a bug, and can be worked around).
3390 @option{combined} implies both @option{srst_pulls_trst} and
3391 @option{trst_pulls_srst}.
3392
3393 @item
3394 The @var{gates} tokens control flags that describe some cases where
3395 JTAG may be unvailable during reset.
3396 @option{srst_gates_jtag} (default)
3397 indicates that asserting SRST gates the
3398 JTAG clock. This means that no communication can happen on JTAG
3399 while SRST is asserted.
3400 Its converse is @option{srst_nogate}, indicating that JTAG commands
3401 can safely be issued while SRST is active.
3402
3403 @item
3404 The @var{connect_type} tokens control flags that describe some cases where
3405 SRST is asserted while connecting to the target. @option{srst_nogate}
3406 is required to use this option.
3407 @option{connect_deassert_srst} (default)
3408 indicates that SRST will not be asserted while connecting to the target.
3409 Its converse is @option{connect_assert_srst}, indicating that SRST will
3410 be asserted before any target connection.
3411 Only some targets support this feature, STM32 and STR9 are examples.
3412 This feature is useful if you are unable to connect to your target due
3413 to incorrect options byte config or illegal program execution.
3414 @end itemize
3415
3416 The optional @var{trst_type} and @var{srst_type} parameters allow the
3417 driver mode of each reset line to be specified. These values only affect
3418 JTAG interfaces with support for different driver modes, like the Amontec
3419 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3420 relevant signal (TRST or SRST) is not connected.
3421
3422 @itemize
3423 @item
3424 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3425 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3426 Most boards connect this signal to a pulldown, so the JTAG TAPs
3427 never leave reset unless they are hooked up to a JTAG adapter.
3428
3429 @item
3430 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3431 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3432 Most boards connect this signal to a pullup, and allow the
3433 signal to be pulled low by various events including system
3434 powerup and pressing a reset button.
3435 @end itemize
3436 @end deffn
3437
3438 @section Custom Reset Handling
3439 @cindex events
3440
3441 OpenOCD has several ways to help support the various reset
3442 mechanisms provided by chip and board vendors.
3443 The commands shown in the previous section give standard parameters.
3444 There are also @emph{event handlers} associated with TAPs or Targets.
3445 Those handlers are Tcl procedures you can provide, which are invoked
3446 at particular points in the reset sequence.
3447
3448 @emph{When SRST is not an option} you must set
3449 up a @code{reset-assert} event handler for your target.
3450 For example, some JTAG adapters don't include the SRST signal;
3451 and some boards have multiple targets, and you won't always
3452 want to reset everything at once.
3453
3454 After configuring those mechanisms, you might still
3455 find your board doesn't start up or reset correctly.
3456 For example, maybe it needs a slightly different sequence
3457 of SRST and/or TRST manipulations, because of quirks that
3458 the @command{reset_config} mechanism doesn't address;
3459 or asserting both might trigger a stronger reset, which
3460 needs special attention.
3461
3462 Experiment with lower level operations, such as @command{jtag_reset}
3463 and the @command{jtag arp_*} operations shown here,
3464 to find a sequence of operations that works.
3465 @xref{JTAG Commands}.
3466 When you find a working sequence, it can be used to override
3467 @command{jtag_init}, which fires during OpenOCD startup
3468 (@pxref{configurationstage,,Configuration Stage});
3469 or @command{init_reset}, which fires during reset processing.
3470
3471 You might also want to provide some project-specific reset
3472 schemes. For example, on a multi-target board the standard
3473 @command{reset} command would reset all targets, but you
3474 may need the ability to reset only one target at time and
3475 thus want to avoid using the board-wide SRST signal.
3476
3477 @deffn {Overridable Procedure} init_reset mode
3478 This is invoked near the beginning of the @command{reset} command,
3479 usually to provide as much of a cold (power-up) reset as practical.
3480 By default it is also invoked from @command{jtag_init} if
3481 the scan chain does not respond to pure JTAG operations.
3482 The @var{mode} parameter is the parameter given to the
3483 low level reset command (@option{halt},
3484 @option{init}, or @option{run}), @option{setup},
3485 or potentially some other value.
3486
3487 The default implementation just invokes @command{jtag arp_init-reset}.
3488 Replacements will normally build on low level JTAG
3489 operations such as @command{jtag_reset}.
3490 Operations here must not address individual TAPs
3491 (or their associated targets)
3492 until the JTAG scan chain has first been verified to work.
3493
3494 Implementations must have verified the JTAG scan chain before
3495 they return.
3496 This is done by calling @command{jtag arp_init}
3497 (or @command{jtag arp_init-reset}).
3498 @end deffn
3499
3500 @deffn Command {jtag arp_init}
3501 This validates the scan chain using just the four
3502 standard JTAG signals (TMS, TCK, TDI, TDO).
3503 It starts by issuing a JTAG-only reset.
3504 Then it performs checks to verify that the scan chain configuration
3505 matches the TAPs it can observe.
3506 Those checks include checking IDCODE values for each active TAP,
3507 and verifying the length of their instruction registers using
3508 TAP @code{-ircapture} and @code{-irmask} values.
3509 If these tests all pass, TAP @code{setup} events are
3510 issued to all TAPs with handlers for that event.
3511 @end deffn
3512
3513 @deffn Command {jtag arp_init-reset}
3514 This uses TRST and SRST to try resetting
3515 everything on the JTAG scan chain
3516 (and anything else connected to SRST).
3517 It then invokes the logic of @command{jtag arp_init}.
3518 @end deffn
3519
3520
3521 @node TAP Declaration
3522 @chapter TAP Declaration
3523 @cindex TAP declaration
3524 @cindex TAP configuration
3525
3526 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3527 TAPs serve many roles, including:
3528
3529 @itemize @bullet
3530 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3531 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3532 Others do it indirectly, making a CPU do it.
3533 @item @b{Program Download} Using the same CPU support GDB uses,
3534 you can initialize a DRAM controller, download code to DRAM, and then
3535 start running that code.
3536 @item @b{Boundary Scan} Most chips support boundary scan, which
3537 helps test for board assembly problems like solder bridges
3538 and missing connections.
3539 @end itemize
3540
3541 OpenOCD must know about the active TAPs on your board(s).
3542 Setting up the TAPs is the core task of your configuration files.
3543 Once those TAPs are set up, you can pass their names to code
3544 which sets up CPUs and exports them as GDB targets,
3545 probes flash memory, performs low-level JTAG operations, and more.
3546
3547 @section Scan Chains
3548 @cindex scan chain
3549
3550 TAPs are part of a hardware @dfn{scan chain},
3551 which is a daisy chain of TAPs.
3552 They also need to be added to
3553 OpenOCD's software mirror of that hardware list,
3554 giving each member a name and associating other data with it.
3555 Simple scan chains, with a single TAP, are common in
3556 systems with a single microcontroller or microprocessor.
3557 More complex chips may have several TAPs internally.
3558 Very complex scan chains might have a dozen or more TAPs:
3559 several in one chip, more in the next, and connecting
3560 to other boards with their own chips and TAPs.
3561
3562 You can display the list with the @command{scan_chain} command.
3563 (Don't confuse this with the list displayed by the @command{targets}
3564 command, presented in the next chapter.
3565 That only displays TAPs for CPUs which are configured as
3566 debugging targets.)
3567 Here's what the scan chain might look like for a chip more than one TAP:
3568
3569 @verbatim
3570 TapName Enabled IdCode Expected IrLen IrCap IrMask
3571 -- ------------------ ------- ---------- ---------- ----- ----- ------
3572 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3573 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3574 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3575 @end verbatim
3576
3577 OpenOCD can detect some of that information, but not all
3578 of it. @xref{autoprobing,,Autoprobing}.
3579 Unfortunately, those TAPs can't always be autoconfigured,
3580 because not all devices provide good support for that.
3581 JTAG doesn't require supporting IDCODE instructions, and
3582 chips with JTAG routers may not link TAPs into the chain
3583 until they are told to do so.
3584
3585 The configuration mechanism currently supported by OpenOCD
3586 requires explicit configuration of all TAP devices using
3587 @command{jtag newtap} commands, as detailed later in this chapter.
3588 A command like this would declare one tap and name it @code{chip1.cpu}:
3589
3590 @example
3591 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3592 @end example
3593
3594 Each target configuration file lists the TAPs provided
3595 by a given chip.
3596 Board configuration files combine all the targets on a board,
3597 and so forth.
3598 Note that @emph{the order in which TAPs are declared is very important.}
3599 That declaration order must match the order in the JTAG scan chain,
3600 both inside a single chip and between them.
3601 @xref{faqtaporder,,FAQ TAP Order}.
3602
3603 For example, the ST Microsystems STR912 chip has
3604 three separate TAPs@footnote{See the ST
3605 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3606 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3607 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3608 To configure those taps, @file{target/str912.cfg}
3609 includes commands something like this:
3610
3611 @example
3612 jtag newtap str912 flash ... params ...
3613 jtag newtap str912 cpu ... params ...
3614 jtag newtap str912 bs ... params ...
3615 @end example
3616
3617 Actual config files typically use a variable such as @code{$_CHIPNAME}
3618 instead of literals like @option{str912}, to support more than one chip
3619 of each type. @xref{Config File Guidelines}.
3620
3621 @deffn Command {jtag names}
3622 Returns the names of all current TAPs in the scan chain.
3623 Use @command{jtag cget} or @command{jtag tapisenabled}
3624 to examine attributes and state of each TAP.
3625 @example
3626 foreach t [jtag names] @{
3627 puts [format "TAP: %s\n" $t]
3628 @}
3629 @end example
3630 @end deffn
3631
3632 @deffn Command {scan_chain}
3633 Displays the TAPs in the scan chain configuration,
3634 and their status.
3635 The set of TAPs listed by this command is fixed by
3636 exiting the OpenOCD configuration stage,
3637 but systems with a JTAG router can
3638 enable or disable TAPs dynamically.
3639 @end deffn
3640
3641 @c FIXME! "jtag cget" should be able to return all TAP
3642 @c attributes, like "$target_name cget" does for targets.
3643
3644 @c Probably want "jtag eventlist", and a "tap-reset" event
3645 @c (on entry to RESET state).
3646
3647 @section TAP Names
3648 @cindex dotted name
3649
3650 When TAP objects are declared with @command{jtag newtap},
3651 a @dfn{dotted.name} is created for the TAP, combining the
3652 name of a module (usually a chip) and a label for the TAP.
3653 For example: @code{xilinx.tap}, @code{str912.flash},
3654 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3655 Many other commands use that dotted.name to manipulate or
3656 refer to the TAP. For example, CPU configuration uses the
3657 name, as does declaration of NAND or NOR flash banks.
3658
3659 The components of a dotted name should follow ``C'' symbol
3660 name rules: start with an alphabetic character, then numbers
3661 and underscores are OK; while others (including dots!) are not.
3662
3663 @section TAP Declaration Commands
3664
3665 @c shouldn't this be(come) a {Config Command}?
3666 @deffn Command {jtag newtap} chipname tapname configparams...
3667 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3668 and configured according to the various @var{configparams}.
3669
3670 The @var{chipname} is a symbolic name for the chip.
3671 Conventionally target config files use @code{$_CHIPNAME},
3672 defaulting to the model name given by the chip vendor but
3673 overridable.
3674
3675 @cindex TAP naming convention
3676 The @var{tapname} reflects the role of that TAP,
3677 and should follow this convention:
3678
3679 @itemize @bullet
3680 @item @code{bs} -- For boundary scan if this is a separate TAP;
3681 @item @code{cpu} -- The main CPU of the chip, alternatively
3682 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3683 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3684 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3685 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3686 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3687 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3688 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3689 with a single TAP;
3690 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3691 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3692 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3693 a JTAG TAP; that TAP should be named @code{sdma}.
3694 @end itemize
3695
3696 Every TAP requires at least the following @var{configparams}:
3697
3698 @itemize @bullet
3699 @item @code{-irlen} @var{NUMBER}
3700 @*The length in bits of the
3701 instruction register, such as 4 or 5 bits.
3702 @end itemize
3703
3704 A TAP may also provide optional @var{configparams}:
3705
3706 @itemize @bullet
3707 @item @code{-disable} (or @code{-enable})
3708 @*Use the @code{-disable} parameter to flag a TAP which is not
3709 linked into the scan chain after a reset using either TRST
3710 or the JTAG state machine's @sc{reset} state.
3711 You may use @code{-enable} to highlight the default state
3712 (the TAP is linked in).
3713 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3714 @item @code{-expected-id} @var{NUMBER}
3715 @*A non-zero @var{number} represents a 32-bit IDCODE
3716 which you expect to find when the scan chain is examined.
3717 These codes are not required by all JTAG devices.
3718 @emph{Repeat the option} as many times as required if more than one
3719 ID code could appear (for example, multiple versions).
3720 Specify @var{number} as zero to suppress warnings about IDCODE
3721 values that were found but not included in the list.
3722
3723 Provide this value if at all possible, since it lets OpenOCD
3724 tell when the scan chain it sees isn't right. These values
3725 are provided in vendors' chip documentation, usually a technical
3726 reference manual. Sometimes you may need to probe the JTAG
3727 hardware to find these values.
3728 @xref{autoprobing,,Autoprobing}.
3729 @item @code{-ignore-version}
3730 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3731 option. When vendors put out multiple versions of a chip, or use the same
3732 JTAG-level ID for several largely-compatible chips, it may be more practical
3733 to ignore the version field than to update config files to handle all of
3734 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3735 @item @code{-ircapture} @var{NUMBER}
3736 @*The bit pattern loaded by the TAP into the JTAG shift register
3737 on entry to the @sc{ircapture} state, such as 0x01.
3738 JTAG requires the two LSBs of this value to be 01.
3739 By default, @code{-ircapture} and @code{-irmask} are set
3740 up to verify that two-bit value. You may provide
3741 additional bits if you know them, or indicate that
3742 a TAP doesn't conform to the JTAG specification.
3743 @item @code{-irmask} @var{NUMBER}
3744 @*A mask used with @code{-ircapture}
3745 to verify that instruction scans work correctly.
3746 Such scans are not used by OpenOCD except to verify that
3747 there seems to be no problems with JTAG scan chain operations.
3748 @end itemize
3749 @end deffn
3750
3751 @section Other TAP commands
3752
3753 @deffn Command {jtag cget} dotted.name @option{-event} event_name
3754 @deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
3755 At this writing this TAP attribute
3756 mechanism is used only for event handling.
3757 (It is not a direct analogue of the @code{cget}/@code{configure}
3758 mechanism for debugger targets.)
3759 See the next section for information about the available events.
3760
3761 The @code{configure} subcommand assigns an event handler,
3762 a TCL string which is evaluated when the event is triggered.
3763 The @code{cget} subcommand returns that handler.
3764 @end deffn
3765
3766 @section TAP Events
3767 @cindex events
3768 @cindex TAP events
3769
3770 OpenOCD includes two event mechanisms.
3771 The one presented here applies to all JTAG TAPs.
3772 The other applies to debugger targets,
3773 which are associated with certain TAPs.
3774
3775 The TAP events currently defined are:
3776
3777 @itemize @bullet
3778 @item @b{post-reset}
3779 @* The TAP has just completed a JTAG reset.
3780 The tap may still be in the JTAG @sc{reset} state.
3781 Handlers for these events might perform initialization sequences
3782 such as issuing TCK cycles, TMS sequences to ensure
3783 exit from the ARM SWD mode, and more.
3784
3785 Because the scan chain has not yet been verified, handlers for these events
3786 @emph{should not issue commands which scan the JTAG IR or DR registers}
3787 of any particular target.
3788 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3789 @item @b{setup}
3790 @* The scan chain has been reset and verified.
3791 This handler may enable TAPs as needed.
3792 @item @b{tap-disable}
3793 @* The TAP needs to be disabled. This handler should
3794 implement @command{jtag tapdisable}
3795 by issuing the relevant JTAG commands.
3796 @item @b{tap-enable}
3797 @* The TAP needs to be enabled. This handler should
3798 implement @command{jtag tapenable}
3799 by issuing the relevant JTAG commands.
3800 @end itemize
3801
3802 If you need some action after each JTAG reset which isn't actually
3803 specific to any TAP (since you can't yet trust the scan chain's
3804 contents to be accurate), you might:
3805
3806 @example
3807 jtag configure CHIP.jrc -event post-reset @{
3808 echo "JTAG Reset done"
3809 ... non-scan jtag operations to be done after reset
3810 @}
3811 @end example
3812
3813
3814 @anchor{enablinganddisablingtaps}
3815 @section Enabling and Disabling TAPs
3816 @cindex JTAG Route Controller
3817 @cindex jrc
3818
3819 In some systems, a @dfn{JTAG Route Controller} (JRC)
3820 is used to enable and/or disable specific JTAG TAPs.
3821 Many ARM-based chips from Texas Instruments include
3822 an ``ICEPick'' module, which is a JRC.
3823 Such chips include DaVinci and OMAP3 processors.
3824
3825 A given TAP may not be visible until the JRC has been
3826 told to link it into the scan chain; and if the JRC
3827 has been told to unlink that TAP, it will no longer
3828 be visible.
3829 Such routers address problems that JTAG ``bypass mode''
3830 ignores, such as:
3831
3832 @itemize
3833 @item The scan chain can only go as fast as its slowest TAP.
3834 @item Having many TAPs slows instruction scans, since all
3835 TAPs receive new instructions.
3836 @item TAPs in the scan chain must be powered up, which wastes
3837 power and prevents debugging some power management mechanisms.
3838 @end itemize
3839
3840 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3841 as implied by the existence of JTAG routers.
3842 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3843 does include a kind of JTAG router functionality.
3844
3845 @c (a) currently the event handlers don't seem to be able to
3846 @c fail in a way that could lead to no-change-of-state.
3847
3848 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3849 shown below, and is implemented using TAP event handlers.
3850 So for example, when defining a TAP for a CPU connected to
3851 a JTAG router, your @file{target.cfg} file
3852 should define TAP event handlers using
3853 code that looks something like this:
3854
3855 @example
3856 jtag configure CHIP.cpu -event tap-enable @{
3857 ... jtag operations using CHIP.jrc
3858 @}
3859 jtag configure CHIP.cpu -event tap-disable @{
3860 ... jtag operations using CHIP.jrc
3861 @}
3862 @end example
3863
3864 Then you might want that CPU's TAP enabled almost all the time:
3865
3866 @example
3867 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3868 @end example
3869
3870 Note how that particular setup event handler declaration
3871 uses quotes to evaluate @code{$CHIP} when the event is configured.
3872 Using brackets @{ @} would cause it to be evaluated later,
3873 at runtime, when it might have a different value.
3874
3875 @deffn Command {jtag tapdisable} dotted.name
3876 If necessary, disables the tap
3877 by sending it a @option{tap-disable} event.
3878 Returns the string "1" if the tap
3879 specified by @var{dotted.name} is enabled,
3880 and "0" if it is disabled.
3881 @end deffn
3882
3883 @deffn Command {jtag tapenable} dotted.name
3884 If necessary, enables the tap
3885 by sending it a @option{tap-enable} event.
3886 Returns the string "1" if the tap
3887 specified by @var{dotted.name} is enabled,
3888 and "0" if it is disabled.
3889 @end deffn
3890
3891 @deffn Command {jtag tapisenabled} dotted.name
3892 Returns the string "1" if the tap
3893 specified by @var{dotted.name} is enabled,
3894 and "0" if it is disabled.
3895
3896 @quotation Note
3897 Humans will find the @command{scan_chain} command more helpful
3898 for querying the state of the JTAG taps.
3899 @end quotation
3900 @end deffn
3901
3902 @anchor{autoprobing}
3903 @section Autoprobing
3904 @cindex autoprobe
3905 @cindex JTAG autoprobe
3906
3907 TAP configuration is the first thing that needs to be done
3908 after interface and reset configuration. Sometimes it's
3909 hard finding out what TAPs exist, or how they are identified.
3910 Vendor documentation is not always easy to find and use.
3911
3912 To help you get past such problems, OpenOCD has a limited
3913 @emph{autoprobing} ability to look at the scan chain, doing
3914 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3915 To use this mechanism, start the OpenOCD server with only data
3916 that configures your JTAG interface, and arranges to come up
3917 with a slow clock (many devices don't support fast JTAG clocks
3918 right when they come out of reset).
3919
3920 For example, your @file{openocd.cfg} file might have:
3921
3922 @example
3923 source [find interface/olimex-arm-usb-tiny-h.cfg]
3924 reset_config trst_and_srst
3925 jtag_rclk 8
3926 @end example
3927
3928 When you start the server without any TAPs configured, it will
3929 attempt to autoconfigure the TAPs. There are two parts to this:
3930
3931 @enumerate
3932 @item @emph{TAP discovery} ...
3933 After a JTAG reset (sometimes a system reset may be needed too),
3934 each TAP's data registers will hold the contents of either the
3935 IDCODE or BYPASS register.
3936 If JTAG communication is working, OpenOCD will see each TAP,
3937 and report what @option{-expected-id} to use with it.
3938 @item @emph{IR Length discovery} ...
3939 Unfortunately JTAG does not provide a reliable way to find out
3940 the value of the @option{-irlen} parameter to use with a TAP
3941 that is discovered.
3942 If OpenOCD can discover the length of a TAP's instruction
3943 register, it will report it.
3944 Otherwise you may need to consult vendor documentation, such
3945 as chip data sheets or BSDL files.
3946 @end enumerate
3947
3948 In many cases your board will have a simple scan chain with just
3949 a single device. Here's what OpenOCD reported with one board
3950 that's a bit more complex:
3951
3952 @example
3953 clock speed 8 kHz
3954 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3955 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3956 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3957 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3958 AUTO auto0.tap - use "... -irlen 4"
3959 AUTO auto1.tap - use "... -irlen 4"
3960 AUTO auto2.tap - use "... -irlen 6"
3961 no gdb ports allocated as no target has been specified
3962 @end example
3963
3964 Given that information, you should be able to either find some existing
3965 config files to use, or create your own. If you create your own, you
3966 would configure from the bottom up: first a @file{target.cfg} file
3967 with these TAPs, any targets associated with them, and any on-chip
3968 resources; then a @file{board.cfg} with off-chip resources, clocking,
3969 and so forth.
3970
3971 @node CPU Configuration
3972 @chapter CPU Configuration
3973 @cindex GDB target
3974
3975 This chapter discusses how to set up GDB debug targets for CPUs.
3976 You can also access these targets without GDB
3977 (@pxref{Architecture and Core Commands},
3978 and @ref{targetstatehandling,,Target State handling}) and
3979 through various kinds of NAND and NOR flash commands.
3980 If you have multiple CPUs you can have multiple such targets.
3981
3982 We'll start by looking at how to examine the targets you have,
3983 then look at how to add one more target and how to configure it.
3984
3985 @section Target List
3986 @cindex target, current
3987 @cindex target, list
3988
3989 All targets that have been set up are part of a list,
3990 where each member has a name.
3991 That name should normally be the same as the TAP name.
3992 You can display the list with the @command{targets}
3993 (plural!) command.
3994 This display often has only one CPU; here's what it might
3995 look like with more than one:
3996 @verbatim
3997 TargetName Type Endian TapName State
3998 -- ------------------ ---------- ------ ------------------ ------------
3999 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4000 1 MyTarget cortex_m little mychip.foo tap-disabled
4001 @end verbatim
4002
4003 One member of that list is the @dfn{current target}, which
4004 is implicitly referenced by many commands.
4005 It's the one marked with a @code{*} near the target name.
4006 In particular, memory addresses often refer to the address
4007 space seen by that current target.
4008 Commands like @command{mdw} (memory display words)
4009 and @command{flash erase_address} (erase NOR flash blocks)
4010 are examples; and there are many more.
4011
4012 Several commands let you examine the list of targets:
4013
4014 @deffn Command {target current}
4015 Returns the name of the current target.
4016 @end deffn
4017
4018 @deffn Command {target names}
4019 Lists the names of all current targets in the list.
4020 @example
4021 foreach t [target names] @{
4022 puts [format "Target: %s\n" $t]
4023 @}
4024 @end example
4025 @end deffn
4026
4027 @c yep, "target list" would have been better.
4028 @c plus maybe "target setdefault".
4029
4030 @deffn Command targets [name]
4031 @emph{Note: the name of this command is plural. Other target
4032 command names are singular.}
4033
4034 With no parameter, this command displays a table of all known
4035 targets in a user friendly form.
4036
4037 With a parameter, this command sets the current target to
4038 the given target with the given @var{name}; this is
4039 only relevant on boards which have more than one target.
4040 @end deffn
4041
4042 @section Target CPU Types
4043 @cindex target type
4044 @cindex CPU type
4045
4046 Each target has a @dfn{CPU type}, as shown in the output of
4047 the @command{targets} command. You need to specify that type
4048 when calling @command{target create}.
4049 The CPU type indicates more than just the instruction set.
4050 It also indicates how that instruction set is implemented,
4051 what kind of debug support it integrates,
4052 whether it has an MMU (and if so, what kind),
4053 what core-specific commands may be available
4054 (@pxref{Architecture and Core Commands}),
4055 and more.
4056
4057 It's easy to see what target types are supported,
4058 since there's a command to list them.
4059
4060 @anchor{targettypes}
4061 @deffn Command {target types}
4062 Lists all supported target types.
4063 At this writing, the supported CPU types are:
4064
4065 @itemize @bullet
4066 @item @code{arm11} -- this is a generation of ARMv6 cores
4067 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4068 @item @code{arm7tdmi} -- this is an ARMv4 core
4069 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4070 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4071 @item @code{arm966e} -- this is an ARMv5 core
4072 @item @code{arm9tdmi} -- this is an ARMv4 core
4073 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4074 (Support for this is preliminary and incomplete.)
4075 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4076 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4077 compact Thumb2 instruction set.
4078 @item @code{aarch64} -- this is an ARMv8-A core with an MMU
4079 @item @code{dragonite} -- resembles arm966e
4080 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4081 (Support for this is still incomplete.)
4082 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4083 @item @code{feroceon} -- resembles arm926
4084 @item @code{mips_m4k} -- a MIPS core
4085 @item @code{xscale} -- this is actually an architecture,
4086 not a CPU type. It is based on the ARMv5 architecture.
4087 @item @code{openrisc} -- this is an OpenRISC 1000 core.
4088 The current implementation supports three JTAG TAP cores:
4089 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4090 allowing access to physical memory addresses independently of CPU cores.
4091 @itemize @minus
4092 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag})
4093 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4094 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4095 @end itemize
4096 And two debug interfaces cores:
4097 @itemize @minus
4098 @item @code{Advanced debug interface} (See: @url{http://opencores.org/project,adv_debug_sys})
4099 @item @code{SoC Debug Interface} (See: @url{http://opencores.org/project,dbg_interface})
4100 @end itemize
4101 @end itemize
4102 @end deffn
4103
4104 To avoid being confused by the variety of ARM based cores, remember
4105 this key point: @emph{ARM is a technology licencing company}.
4106 (See: @url{http://www.arm.com}.)
4107 The CPU name used by OpenOCD will reflect the CPU design that was
4108 licenced, not a vendor brand which incorporates that design.
4109 Name prefixes like arm7, arm9, arm11, and cortex
4110 reflect design generations;
4111 while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
4112 reflect an architecture version implemented by a CPU design.
4113
4114 @anchor{targetconfiguration}
4115 @section Target Configuration
4116
4117 Before creating a ``target'', you must have added its TAP to the scan chain.
4118 When you've added that TAP, you will have a @code{dotted.name}
4119 which is used to set up the CPU support.
4120 The chip-specific configuration file will normally configure its CPU(s)
4121 right after it adds all of the chip's TAPs to the scan chain.
4122
4123 Although you can set up a target in one step, it's often clearer if you
4124 use shorter commands and do it in two steps: create it, then configure
4125 optional parts.
4126 All operations on the target after it's created will use a new
4127 command, created as part of target creation.
4128
4129 The two main things to configure after target creation are
4130 a work area, which usually has target-specific defaults even
4131 if the board setup code overrides them later;
4132 and event handlers (@pxref{targetevents,,Target Events}), which tend
4133 to be much more board-specific.
4134 The key steps you use might look something like this
4135
4136 @example
4137 target create MyTarget cortex_m -chain-position mychip.cpu
4138 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4139 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4140 $MyTarget configure -event reset-init @{ myboard_reinit @}
4141 @end example
4142
4143 You should specify a working area if you can; typically it uses some
4144 on-chip SRAM.
4145 Such a working area can speed up many things, including bulk
4146 writes to target memory;
4147 flash operations like checking to see if memory needs to be erased;
4148 GDB memory checksumming;
4149 and more.
4150
4151 @quotation Warning
4152 On more complex chips, the work area can become
4153 inaccessible when application code
4154 (such as an operating system)
4155 enables or disables the MMU.
4156 For example, the particular MMU context used to acess the virtual
4157 address will probably matter ... and that context might not have
4158 easy access to other addresses needed.
4159 At this writing, OpenOCD doesn't have much MMU intelligence.
4160 @end quotation
4161
4162 It's often very useful to define a @code{reset-init} event handler.
4163 For systems that are normally used with a boot loader,
4164 common tasks include updating clocks and initializing memory
4165 controllers.
4166 That may be needed to let you write the boot loader into flash,
4167 in order to ``de-brick'' your board; or to load programs into
4168 external DDR memory without having run the boot loader.
4169
4170 @deffn Command {target create} target_name type configparams...
4171 This command creates a GDB debug target that refers to a specific JTAG tap.
4172 It enters that target into a list, and creates a new
4173 command (@command{@var{target_name}}) which is used for various
4174 purposes including additional configuration.
4175
4176 @itemize @bullet
4177 @item @var{target_name} ... is the name of the debug target.
4178 By convention this should be the same as the @emph{dotted.name}