doc: Add gdb target description commands
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * NAND Flash Commands:: NAND Flash Commands
77 * PLD/FPGA Commands:: PLD/FPGA Commands
78 * General Commands:: General Commands
79 * Architecture and Core Commands:: Architecture and Core Commands
80 * JTAG Commands:: JTAG Commands
81 * Boundary Scan Commands:: Boundary Scan Commands
82 * TFTP:: TFTP
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on:
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
95 @end menu
97 @node About
98 @unnumbered About
99 @cindex about
101 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
102 University of Applied Sciences Augsburg (@uref{}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
105 around the world.
107 @section What is OpenOCD?
108 @cindex TAP
109 @cindex JTAG
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
113 devices.
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board can be directly connected to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
140 scan operations.
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD only supports
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
154 based, parallel port based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
159 Cortex-M3 (Stellaris LM3, ST STM32 and Energy Micro EFM32) based cores to be
160 debugged via the GDB protocol.
162 @b{Flash Programing:} Flash writing is supported for external CFI
163 compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) controller is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{}
182 PDF form is likewise published at:
184 @uref{}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{}
203 @section OpenOCD IRC
205 Support can also be found on irc:
206 @uref{irc://}
208 @node Developers
209 @chapter OpenOCD Developer Resources
210 @cindex developers
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD GIT Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a GIT repository hosted at SourceForge. The repository URL is:
225 @uref{git://}
227 or via http
229 @uref{}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{}
235 With standard GIT tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a GIT client:
241 @uref{}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration in the top of the source tree.
264 @section OpenOCD Developer Mailing List
266 The OpenOCD Developer Mailing List provides the primary means of
267 communication between developers:
269 @uref{}
271 Discuss and submit patches to this list.
272 The @file{HACKING} file contains basic information about how
273 to prepare patches.
275 @section OpenOCD Bug Database
277 During the 0.4.x release cycle the OpenOCD project team began
278 using Trac for its bug database:
280 @uref{}
283 @node Debug Adapter Hardware
284 @chapter Debug Adapter Hardware
285 @cindex dongles
286 @cindex FTDI
287 @cindex wiggler
288 @cindex zy1000
289 @cindex printer port
290 @cindex USB Adapter
291 @cindex RTCK
293 Defined: @b{dongle}: A small device that plugins into a computer and serves as
294 an adapter .... [snip]
296 In the OpenOCD case, this generally refers to @b{a small adapter} that
297 attaches to your computer via USB or the Parallel Printer Port. One
298 exception is the Zylin ZY1000, packaged as a small box you attach via
299 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
300 require any drivers to be installed on the developer PC. It also has
301 a built in web interface. It supports RTCK/RCLK or adaptive clocking
302 and has a built in relay to power cycle targets remotely.
305 @section Choosing a Dongle
307 There are several things you should keep in mind when choosing a dongle.
309 @enumerate
310 @item @b{Transport} Does it support the kind of communication that you need?
311 OpenOCD focusses mostly on JTAG. Your version may also support
312 other ways to communicate with target devices.
313 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
314 Does your dongle support it? You might need a level converter.
315 @item @b{Pinout} What pinout does your target board use?
316 Does your dongle support it? You may be able to use jumper
317 wires, or an "octopus" connector, to convert pinouts.
318 @item @b{Connection} Does your computer have the USB, printer, or
319 Ethernet port needed?
320 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
321 RTCK support? Also known as ``adaptive clocking''
322 @end enumerate
324 @section Stand-alone JTAG Probe
326 The ZY1000 from Ultimate Solutions is technically not a dongle but a
327 stand-alone JTAG probe that unlikemost dongles doesn’t require any drivers
328 running on the developers host computer.
329 Once installed on a network using DHCP or a static IP assignment, users can
330 access the ZY1000 probe locally or remotely from any host with access to the
331 IP address assigned to the probe.
332 The ZY1000 provides an intuitive web interface with direct access to the
333 OpenOCD debugger.
334 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
335 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
336 the target.
337 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
338 to power cycle the target remotely.
340 For more information, visit:
342 @b{ZY1000} See: @url{}
344 @section USB FT2232 Based
346 There are many USB JTAG dongles on the market, many of them are based
347 on a chip from ``Future Technology Devices International'' (FTDI)
348 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
349 See: @url{} for more information.
350 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
351 chips are starting to become available in JTAG adapters. Around 2012 a new
352 variant appeared - FT232H - this is a single-channel version of FT2232H.
353 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
354 clocking.)
356 The FT2232 chips are flexible enough to support some other
357 transport options, such as SWD or the SPI variants used to
358 program some chips. They have two communications channels,
359 and one can be used for a UART adapter at the same time the
360 other one is used to provide a debug adapter.
362 Also, some development boards integrate an FT2232 chip to serve as
363 a built-in low cost debug adapter and usb-to-serial solution.
365 @itemize @bullet
366 @item @b{usbjtag}
367 @* Link @url{}
368 @item @b{jtagkey}
369 @* See: @url{}
370 @item @b{jtagkey2}
371 @* See: @url{}
372 @item @b{oocdlink}
373 @* See: @url{} By Joern Kaipf
374 @item @b{signalyzer}
375 @* See: @url{}
376 @item @b{Stellaris Eval Boards}
377 @* See: @url{} - The Stellaris eval boards
378 bundle FT2232-based JTAG and SWD support, which can be used to debug
379 the Stellaris chips. Using separate JTAG adapters is optional.
380 These boards can also be used in a "pass through" mode as JTAG adapters
381 to other target boards, disabling the Stellaris chip.
382 @item @b{TI/Luminary ICDI}
383 @* See: @url{} - TI/Luminary In-Circuit Debug
384 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
385 Evaluation Kits. Like the non-detachable FT2232 support on the other
386 Stellaris eval boards, they can be used to debug other target boards.
387 @item @b{olimex-jtag}
388 @* See: @url{}
389 @item @b{Flyswatter/Flyswatter2}
390 @* See: @url{}
391 @item @b{turtelizer2}
392 @* See:
393 @uref{, Turtelizer 2}, or
394 @url{}
395 @item @b{comstick}
396 @* Link: @url{}
397 @item @b{stm32stick}
398 @* Link @url{}
399 @item @b{axm0432_jtag}
400 @* Axiom AXM-0432 Link @url{} - NOTE: This JTAG does not appear
401 to be available anymore as of April 2012.
402 @item @b{cortino}
403 @* Link @url{}
404 @item @b{dlp-usb1232h}
405 @* Link @url{}
406 @item @b{digilent-hs1}
407 @* Link @url{}
408 @item @b{opendous}
409 @* Link @url{} FT2232H-based
410 (OpenHardware).
411 @item @b{JTAG-lock-pick Tiny 2}
412 @* Link @url{} FT232H-based
414 @item @b{GW16042}
415 @* Link: @url{}
416 FT2232H-based
418 @end itemize
419 @section USB-JTAG / Altera USB-Blaster compatibles
421 These devices also show up as FTDI devices, but are not
422 protocol-compatible with the FT2232 devices. They are, however,
423 protocol-compatible among themselves. USB-JTAG devices typically consist
424 of a FT245 followed by a CPLD that understands a particular protocol,
425 or emulate this protocol using some other hardware.
427 They may appear under different USB VID/PID depending on the particular
428 product. The driver can be configured to search for any VID/PID pair
429 (see the section on driver commands).
431 @itemize
432 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
433 @* Link: @url{}
434 @item @b{Altera USB-Blaster}
435 @* Link: @url{}
436 @end itemize
438 @section USB JLINK based
439 There are several OEM versions of the Segger @b{JLINK} adapter. It is
440 an example of a micro controller based JTAG adapter, it uses an
441 AT91SAM764 internally.
443 @itemize @bullet
444 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
445 @* Link: @url{}
446 @item @b{SEGGER JLINK}
447 @* Link: @url{}
448 @item @b{IAR J-Link}
449 @* Link: @url{}
450 @end itemize
452 @section USB RLINK based
453 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
454 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
455 SWD and not JTAG, thus not supported.
457 @itemize @bullet
458 @item @b{Raisonance RLink}
459 @* Link: @url{}
460 @item @b{STM32 Primer}
461 @* Link: @url{}
462 @item @b{STM32 Primer2}
463 @* Link: @url{}
464 @end itemize
466 @section USB ST-LINK based
467 ST Micro has an adapter called @b{ST-LINK}.
468 They only work with ST Micro chips, notably STM32 and STM8.
470 @itemize @bullet
471 @item @b{ST-LINK}
472 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
473 @* Link: @url{}
474 @item @b{ST-LINK/V2}
475 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
476 @* Link: @url{}
477 @end itemize
479 For info the original ST-LINK enumerates using the mass storage usb class, however
480 it's implementation is completely broken. The result is this causes issues under linux.
481 The simplest solution is to get linux to ignore the ST-LINK using one of the following methods:
482 @itemize @bullet
483 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
484 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
485 @end itemize
487 @section USB TI/Stellaris ICDI based
488 Texas Instruments has an adapter called @b{ICDI}.
489 It is not to be confused with the FTDI based adapters that were originally fitted to their
490 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
492 @section USB Other
493 @itemize @bullet
494 @item @b{USBprog}
495 @* Link: @url{} - which uses an Atmel MEGA32 and a UBN9604
497 @item @b{USB - Presto}
498 @* Link: @url{}
500 @item @b{Versaloon-Link}
501 @* Link: @url{}
503 @item @b{ARM-JTAG-EW}
504 @* Link: @url{}
506 @item @b{Buspirate}
507 @* Link: @url{}
509 @item @b{opendous}
510 @* Link: @url{} - which uses an AT90USB162
512 @item @b{estick}
513 @* Link: @url{}
515 @item @b{Keil ULINK v1}
516 @* Link: @url{}
517 @end itemize
519 @section IBM PC Parallel Printer Port Based
521 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
522 and the Macraigor Wiggler. There are many clones and variations of
523 these on the market.
525 Note that parallel ports are becoming much less common, so if you
526 have the choice you should probably avoid these adapters in favor
527 of USB-based ones.
529 @itemize @bullet
531 @item @b{Wiggler} - There are many clones of this.
532 @* Link: @url{}
534 @item @b{DLC5} - From XILINX - There are many clones of this
535 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
536 produced, PDF schematics are easily found and it is easy to make.
538 @item @b{Amontec - JTAG Accelerator}
539 @* Link: @url{}
541 @item @b{Wiggler2}
542 @* Link: @url{}
544 @item @b{Wiggler_ntrst_inverted}
545 @* Yet another variation - See the source code, src/jtag/parport.c
547 @item @b{old_amt_wiggler}
548 @* Unknown - probably not on the market today
550 @item @b{arm-jtag}
551 @* Link: Most likely @url{} [another wiggler clone]
553 @item @b{chameleon}
554 @* Link: @url{}
556 @item @b{Triton}
557 @* Unknown.
559 @item @b{Lattice}
560 @* ispDownload from Lattice Semiconductor
561 @url{}
563 @item @b{flashlink}
564 @* From ST Microsystems;
565 @* Link: @url{}
567 @end itemize
569 @section Other...
570 @itemize @bullet
572 @item @b{ep93xx}
573 @* An EP93xx based Linux machine using the GPIO pins directly.
575 @item @b{at91rm9200}
576 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
578 @item @b{bcm2835gpio}
579 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
581 @end itemize
583 @node About Jim-Tcl
584 @chapter About Jim-Tcl
585 @cindex Jim-Tcl
586 @cindex tcl
588 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
589 This programming language provides a simple and extensible
590 command interpreter.
592 All commands presented in this Guide are extensions to Jim-Tcl.
593 You can use them as simple commands, without needing to learn
594 much of anything about Tcl.
595 Alternatively, can write Tcl programs with them.
597 You can learn more about Jim at its website, @url{}.
598 There is an active and responsive community, get on the mailing list
599 if you have any questions. Jim-Tcl maintainers also lurk on the
600 OpenOCD mailing list.
602 @itemize @bullet
603 @item @b{Jim vs. Tcl}
604 @* Jim-Tcl is a stripped down version of the well known Tcl language,
605 which can be found here: @url{}. Jim-Tcl has far
606 fewer features. Jim-Tcl is several dozens of .C files and .H files and
607 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
608 4.2 MB .zip file containing 1540 files.
610 @item @b{Missing Features}
611 @* Our practice has been: Add/clone the real Tcl feature if/when
612 needed. We welcome Jim-Tcl improvements, not bloat. Also there
613 are a large number of optional Jim-Tcl features that are not
614 enabled in OpenOCD.
616 @item @b{Scripts}
617 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
618 command interpreter today is a mixture of (newer)
619 Jim-Tcl commands, and (older) the orginal command interpreter.
621 @item @b{Commands}
622 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
623 can type a Tcl for() loop, set variables, etc.
624 Some of the commands documented in this guide are implemented
625 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
627 @item @b{Historical Note}
628 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
629 before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
630 as a git submodule, which greatly simplified upgrading Jim Tcl
631 to benefit from new features and bugfixes in Jim Tcl.
633 @item @b{Need a crash course in Tcl?}
634 @*@xref{Tcl Crash Course}.
635 @end itemize
637 @node Running
638 @chapter Running
639 @cindex command line options
640 @cindex logfile
641 @cindex directory search
643 Properly installing OpenOCD sets up your operating system to grant it access
644 to the debug adapters. On Linux, this usually involves installing a file
645 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
646 complex and confusing driver configuration for every peripheral. Such issues
647 are unique to each operating system, and are not detailed in this User's Guide.
649 Then later you will invoke the OpenOCD server, with various options to
650 tell it how each debug session should work.
651 The @option{--help} option shows:
652 @verbatim
653 bash$ openocd --help
655 --help | -h display this help
656 --version | -v display OpenOCD version
657 --file | -f use configuration file <name>
658 --search | -s dir to search for config files and scripts
659 --debug | -d set debug level <0-3>
660 --log_output | -l redirect log output to file <name>
661 --command | -c run <command>
662 @end verbatim
664 If you don't give any @option{-f} or @option{-c} options,
665 OpenOCD tries to read the configuration file @file{openocd.cfg}.
666 To specify one or more different
667 configuration files, use @option{-f} options. For example:
669 @example
670 openocd -f config1.cfg -f config2.cfg -f config3.cfg
671 @end example
673 Configuration files and scripts are searched for in
674 @enumerate
675 @item the current directory,
676 @item any search dir specified on the command line using the @option{-s} option,
677 @item any search dir specified using the @command{add_script_search_dir} command,
678 @item @file{$HOME/.openocd} (not on Windows),
679 @item the site wide script library @file{$pkgdatadir/site} and
680 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
681 @end enumerate
682 The first found file with a matching file name will be used.
684 @quotation Note
685 Don't try to use configuration script names or paths which
686 include the "#" character. That character begins Tcl comments.
687 @end quotation
689 @section Simple setup, no customization
691 In the best case, you can use two scripts from one of the script
692 libraries, hook up your JTAG adapter, and start the server ... and
693 your JTAG setup will just work "out of the box". Always try to
694 start by reusing those scripts, but assume you'll need more
695 customization even if this works. @xref{OpenOCD Project Setup}.
697 If you find a script for your JTAG adapter, and for your board or
698 target, you may be able to hook up your JTAG adapter then start
699 the server like:
701 @example
702 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
703 @end example
705 You might also need to configure which reset signals are present,
706 using @option{-c 'reset_config trst_and_srst'} or something similar.
707 If all goes well you'll see output something like
709 @example
710 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
711 For bug reports, read
713 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
714 (mfg: 0x23b, part: 0xba00, ver: 0x3)
715 @end example
717 Seeing that "tap/device found" message, and no warnings, means
718 the JTAG communication is working. That's a key milestone, but
719 you'll probably need more project-specific setup.
721 @section What OpenOCD does as it starts
723 OpenOCD starts by processing the configuration commands provided
724 on the command line or, if there were no @option{-c command} or
725 @option{-f file.cfg} options given, in @file{openocd.cfg}.
726 @xref{configurationstage,,Configuration Stage}.
727 At the end of the configuration stage it verifies the JTAG scan
728 chain defined using those commands; your configuration should
729 ensure that this always succeeds.
730 Normally, OpenOCD then starts running as a daemon.
731 Alternatively, commands may be used to terminate the configuration
732 stage early, perform work (such as updating some flash memory),
733 and then shut down without acting as a daemon.
735 Once OpenOCD starts running as a daemon, it waits for connections from
736 clients (Telnet, GDB, Other) and processes the commands issued through
737 those channels.
739 If you are having problems, you can enable internal debug messages via
740 the @option{-d} option.
742 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
743 @option{-c} command line switch.
745 To enable debug output (when reporting problems or working on OpenOCD
746 itself), use the @option{-d} command line switch. This sets the
747 @option{debug_level} to "3", outputting the most information,
748 including debug messages. The default setting is "2", outputting only
749 informational messages, warnings and errors. You can also change this
750 setting from within a telnet or gdb session using @command{debug_level<n>}
751 (@pxref{debuglevel,,debug_level}).
753 You can redirect all output from the daemon to a file using the
754 @option{-l <logfile>} switch.
756 Note! OpenOCD will launch the GDB & telnet server even if it can not
757 establish a connection with the target. In general, it is possible for
758 the JTAG controller to be unresponsive until the target is set up
759 correctly via e.g. GDB monitor commands in a GDB init script.
761 @node OpenOCD Project Setup
762 @chapter OpenOCD Project Setup
764 To use OpenOCD with your development projects, you need to do more than
765 just connecting the JTAG adapter hardware (dongle) to your development board
766 and then starting the OpenOCD server.
767 You also need to configure that server so that it knows
768 about that adapter and board, and helps your work.
769 You may also want to connect OpenOCD to GDB, possibly
770 using Eclipse or some other GUI.
772 @section Hooking up the JTAG Adapter
774 Today's most common case is a dongle with a JTAG cable on one side
775 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
776 and a USB cable on the other.
777 Instead of USB, some cables use Ethernet;
778 older ones may use a PC parallel port, or even a serial port.
780 @enumerate
781 @item @emph{Start with power to your target board turned off},
782 and nothing connected to your JTAG adapter.
783 If you're particularly paranoid, unplug power to the board.
784 It's important to have the ground signal properly set up,
785 unless you are using a JTAG adapter which provides
786 galvanic isolation between the target board and the
787 debugging host.
789 @item @emph{Be sure it's the right kind of JTAG connector.}
790 If your dongle has a 20-pin ARM connector, you need some kind
791 of adapter (or octopus, see below) to hook it up to
792 boards using 14-pin or 10-pin connectors ... or to 20-pin
793 connectors which don't use ARM's pinout.
795 In the same vein, make sure the voltage levels are compatible.
796 Not all JTAG adapters have the level shifters needed to work
797 with 1.2 Volt boards.
799 @item @emph{Be certain the cable is properly oriented} or you might
800 damage your board. In most cases there are only two possible
801 ways to connect the cable.
802 Connect the JTAG cable from your adapter to the board.
803 Be sure it's firmly connected.
805 In the best case, the connector is keyed to physically
806 prevent you from inserting it wrong.
807 This is most often done using a slot on the board's male connector
808 housing, which must match a key on the JTAG cable's female connector.
809 If there's no housing, then you must look carefully and
810 make sure pin 1 on the cable hooks up to pin 1 on the board.
811 Ribbon cables are frequently all grey except for a wire on one
812 edge, which is red. The red wire is pin 1.
814 Sometimes dongles provide cables where one end is an ``octopus'' of
815 color coded single-wire connectors, instead of a connector block.
816 These are great when converting from one JTAG pinout to another,
817 but are tedious to set up.
818 Use these with connector pinout diagrams to help you match up the
819 adapter signals to the right board pins.
821 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
822 A USB, parallel, or serial port connector will go to the host which
823 you are using to run OpenOCD.
824 For Ethernet, consult the documentation and your network administrator.
826 For USB based JTAG adapters you have an easy sanity check at this point:
827 does the host operating system see the JTAG adapter? If that host is an
828 MS-Windows host, you'll need to install a driver before OpenOCD works.
830 @item @emph{Connect the adapter's power supply, if needed.}
831 This step is primarily for non-USB adapters,
832 but sometimes USB adapters need extra power.
834 @item @emph{Power up the target board.}
835 Unless you just let the magic smoke escape,
836 you're now ready to set up the OpenOCD server
837 so you can use JTAG to work with that board.
839 @end enumerate
841 Talk with the OpenOCD server using
842 telnet (@code{telnet localhost 4444} on many systems) or GDB.
843 @xref{GDB and OpenOCD}.
845 @section Project Directory
847 There are many ways you can configure OpenOCD and start it up.
849 A simple way to organize them all involves keeping a
850 single directory for your work with a given board.
851 When you start OpenOCD from that directory,
852 it searches there first for configuration files, scripts,
853 files accessed through semihosting,
854 and for code you upload to the target board.
855 It is also the natural place to write files,
856 such as log files and data you download from the board.
858 @section Configuration Basics
860 There are two basic ways of configuring OpenOCD, and
861 a variety of ways you can mix them.
862 Think of the difference as just being how you start the server:
864 @itemize
865 @item Many @option{-f file} or @option{-c command} options on the command line
866 @item No options, but a @dfn{user config file}
867 in the current directory named @file{openocd.cfg}
868 @end itemize
870 Here is an example @file{openocd.cfg} file for a setup
871 using a Signalyzer FT2232-based JTAG adapter to talk to
872 a board with an Atmel AT91SAM7X256 microcontroller:
874 @example
875 source [find interface/signalyzer.cfg]
877 # GDB can also flash my flash!
878 gdb_memory_map enable
879 gdb_flash_program enable
881 source [find target/sam7x256.cfg]
882 @end example
884 Here is the command line equivalent of that configuration:
886 @example
887 openocd -f interface/signalyzer.cfg \
888 -c "gdb_memory_map enable" \
889 -c "gdb_flash_program enable" \
890 -f target/sam7x256.cfg
891 @end example
893 You could wrap such long command lines in shell scripts,
894 each supporting a different development task.
895 One might re-flash the board with a specific firmware version.
896 Another might set up a particular debugging or run-time environment.
898 @quotation Important
899 At this writing (October 2009) the command line method has
900 problems with how it treats variables.
901 For example, after @option{-c "set VAR value"}, or doing the
902 same in a script, the variable @var{VAR} will have no value
903 that can be tested in a later script.
904 @end quotation
906 Here we will focus on the simpler solution: one user config
907 file, including basic configuration plus any TCL procedures
908 to simplify your work.
910 @section User Config Files
911 @cindex config file, user
912 @cindex user config file
913 @cindex config file, overview
915 A user configuration file ties together all the parts of a project
916 in one place.
917 One of the following will match your situation best:
919 @itemize
920 @item Ideally almost everything comes from configuration files
921 provided by someone else.
922 For example, OpenOCD distributes a @file{scripts} directory
923 (probably in @file{/usr/share/openocd/scripts} on Linux).
924 Board and tool vendors can provide these too, as can individual
925 user sites; the @option{-s} command line option lets you say
926 where to find these files. (@xref{Running}.)
927 The AT91SAM7X256 example above works this way.
929 Three main types of non-user configuration file each have their
930 own subdirectory in the @file{scripts} directory:
932 @enumerate
933 @item @b{interface} -- one for each different debug adapter;
934 @item @b{board} -- one for each different board
935 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
936 @end enumerate
938 Best case: include just two files, and they handle everything else.
939 The first is an interface config file.
940 The second is board-specific, and it sets up the JTAG TAPs and
941 their GDB targets (by deferring to some @file{target.cfg} file),
942 declares all flash memory, and leaves you nothing to do except
943 meet your deadline:
945 @example
946 source [find interface/olimex-jtag-tiny.cfg]
947 source [find board/csb337.cfg]
948 @end example
950 Boards with a single microcontroller often won't need more
951 than the target config file, as in the AT91SAM7X256 example.
952 That's because there is no external memory (flash, DDR RAM), and
953 the board differences are encapsulated by application code.
955 @item Maybe you don't know yet what your board looks like to JTAG.
956 Once you know the @file{interface.cfg} file to use, you may
957 need help from OpenOCD to discover what's on the board.
958 Once you find the JTAG TAPs, you can just search for appropriate
959 target and board
960 configuration files ... or write your own, from the bottom up.
961 @xref{autoprobing,,Autoprobing}.
963 @item You can often reuse some standard config files but
964 need to write a few new ones, probably a @file{board.cfg} file.
965 You will be using commands described later in this User's Guide,
966 and working with the guidelines in the next chapter.
968 For example, there may be configuration files for your JTAG adapter
969 and target chip, but you need a new board-specific config file
970 giving access to your particular flash chips.
971 Or you might need to write another target chip configuration file
972 for a new chip built around the Cortex M3 core.
974 @quotation Note
975 When you write new configuration files, please submit
976 them for inclusion in the next OpenOCD release.
977 For example, a @file{board/newboard.cfg} file will help the
978 next users of that board, and a @file{target/newcpu.cfg}
979 will help support users of any board using that chip.
980 @end quotation
982 @item
983 You may may need to write some C code.
984 It may be as simple as a supporting a new ft2232 or parport
985 based adapter; a bit more involved, like a NAND or NOR flash
986 controller driver; or a big piece of work like supporting
987 a new chip architecture.
988 @end itemize
990 Reuse the existing config files when you can.
991 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
992 You may find a board configuration that's a good example to follow.
994 When you write config files, separate the reusable parts
995 (things every user of that interface, chip, or board needs)
996 from ones specific to your environment and debugging approach.
997 @itemize
999 @item
1000 For example, a @code{gdb-attach} event handler that invokes
1001 the @command{reset init} command will interfere with debugging
1002 early boot code, which performs some of the same actions
1003 that the @code{reset-init} event handler does.
1005 @item
1006 Likewise, the @command{arm9 vector_catch} command (or
1007 @cindex vector_catch
1008 its siblings @command{xscale vector_catch}
1009 and @command{cortex_m vector_catch}) can be a timesaver
1010 during some debug sessions, but don't make everyone use that either.
1011 Keep those kinds of debugging aids in your user config file,
1012 along with messaging and tracing setup.
1013 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1015 @item
1016 You might need to override some defaults.
1017 For example, you might need to move, shrink, or back up the target's
1018 work area if your application needs much SRAM.
1020 @item
1021 TCP/IP port configuration is another example of something which
1022 is environment-specific, and should only appear in
1023 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1024 @end itemize
1026 @section Project-Specific Utilities
1028 A few project-specific utility
1029 routines may well speed up your work.
1030 Write them, and keep them in your project's user config file.
1032 For example, if you are making a boot loader work on a
1033 board, it's nice to be able to debug the ``after it's
1034 loaded to RAM'' parts separately from the finicky early
1035 code which sets up the DDR RAM controller and clocks.
1036 A script like this one, or a more GDB-aware sibling,
1037 may help:
1039 @example
1040 proc ramboot @{ @} @{
1041 # Reset, running the target's "reset-init" scripts
1042 # to initialize clocks and the DDR RAM controller.
1043 # Leave the CPU halted.
1044 reset init
1046 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1047 load_image u-boot.bin 0x20000000
1049 # Start running.
1050 resume 0x20000000
1051 @}
1052 @end example
1054 Then once that code is working you will need to make it
1055 boot from NOR flash; a different utility would help.
1056 Alternatively, some developers write to flash using GDB.
1057 (You might use a similar script if you're working with a flash
1058 based microcontroller application instead of a boot loader.)
1060 @example
1061 proc newboot @{ @} @{
1062 # Reset, leaving the CPU halted. The "reset-init" event
1063 # proc gives faster access to the CPU and to NOR flash;
1064 # "reset halt" would be slower.
1065 reset init
1067 # Write standard version of U-Boot into the first two
1068 # sectors of NOR flash ... the standard version should
1069 # do the same lowlevel init as "reset-init".
1070 flash protect 0 0 1 off
1071 flash erase_sector 0 0 1
1072 flash write_bank 0 u-boot.bin 0x0
1073 flash protect 0 0 1 on
1075 # Reboot from scratch using that new boot loader.
1076 reset run
1077 @}
1078 @end example
1080 You may need more complicated utility procedures when booting
1081 from NAND.
1082 That often involves an extra bootloader stage,
1083 running from on-chip SRAM to perform DDR RAM setup so it can load
1084 the main bootloader code (which won't fit into that SRAM).
1086 Other helper scripts might be used to write production system images,
1087 involving considerably more than just a three stage bootloader.
1089 @section Target Software Changes
1091 Sometimes you may want to make some small changes to the software
1092 you're developing, to help make JTAG debugging work better.
1093 For example, in C or assembly language code you might
1094 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1095 handling issues like:
1097 @itemize @bullet
1099 @item @b{Watchdog Timers}...
1100 Watchog timers are typically used to automatically reset systems if
1101 some application task doesn't periodically reset the timer. (The
1102 assumption is that the system has locked up if the task can't run.)
1103 When a JTAG debugger halts the system, that task won't be able to run
1104 and reset the timer ... potentially causing resets in the middle of
1105 your debug sessions.
1107 It's rarely a good idea to disable such watchdogs, since their usage
1108 needs to be debugged just like all other parts of your firmware.
1109 That might however be your only option.
1111 Look instead for chip-specific ways to stop the watchdog from counting
1112 while the system is in a debug halt state. It may be simplest to set
1113 that non-counting mode in your debugger startup scripts. You may however
1114 need a different approach when, for example, a motor could be physically
1115 damaged by firmware remaining inactive in a debug halt state. That might
1116 involve a type of firmware mode where that "non-counting" mode is disabled
1117 at the beginning then re-enabled at the end; a watchdog reset might fire
1118 and complicate the debug session, but hardware (or people) would be
1119 protected.@footnote{Note that many systems support a "monitor mode" debug
1120 that is a somewhat cleaner way to address such issues. You can think of
1121 it as only halting part of the system, maybe just one task,
1122 instead of the whole thing.
1123 At this writing, January 2010, OpenOCD based debugging does not support
1124 monitor mode debug, only "halt mode" debug.}
1126 @item @b{ARM Semihosting}...
1127 @cindex ARM semihosting
1128 When linked with a special runtime library provided with many
1129 toolchains@footnote{See chapter 8 "Semihosting" in
1130 @uref{,
1131 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1132 The CodeSourcery EABI toolchain also includes a semihosting library.},
1133 your target code can use I/O facilities on the debug host. That library
1134 provides a small set of system calls which are handled by OpenOCD.
1135 It can let the debugger provide your system console and a file system,
1136 helping with early debugging or providing a more capable environment
1137 for sometimes-complex tasks like installing system firmware onto
1138 NAND or SPI flash.
1140 @item @b{ARM Wait-For-Interrupt}...
1141 Many ARM chips synchronize the JTAG clock using the core clock.
1142 Low power states which stop that core clock thus prevent JTAG access.
1143 Idle loops in tasking environments often enter those low power states
1144 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1146 You may want to @emph{disable that instruction} in source code,
1147 or otherwise prevent using that state,
1148 to ensure you can get JTAG access at any time.@footnote{As a more
1149 polite alternative, some processors have special debug-oriented
1150 registers which can be used to change various features including
1151 how the low power states are clocked while debugging.
1152 The STM32 DBGMCU_CR register is an example; at the cost of extra
1153 power consumption, JTAG can be used during low power states.}
1154 For example, the OpenOCD @command{halt} command may not
1155 work for an idle processor otherwise.
1157 @item @b{Delay after reset}...
1158 Not all chips have good support for debugger access
1159 right after reset; many LPC2xxx chips have issues here.
1160 Similarly, applications that reconfigure pins used for
1161 JTAG access as they start will also block debugger access.
1163 To work with boards like this, @emph{enable a short delay loop}
1164 the first thing after reset, before "real" startup activities.
1165 For example, one second's delay is usually more than enough
1166 time for a JTAG debugger to attach, so that
1167 early code execution can be debugged
1168 or firmware can be replaced.
1170 @item @b{Debug Communications Channel (DCC)}...
1171 Some processors include mechanisms to send messages over JTAG.
1172 Many ARM cores support these, as do some cores from other vendors.
1173 (OpenOCD may be able to use this DCC internally, speeding up some
1174 operations like writing to memory.)
1176 Your application may want to deliver various debugging messages
1177 over JTAG, by @emph{linking with a small library of code}
1178 provided with OpenOCD and using the utilities there to send
1179 various kinds of message.
1180 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1182 @end itemize
1184 @section Target Hardware Setup
1186 Chip vendors often provide software development boards which
1187 are highly configurable, so that they can support all options
1188 that product boards may require. @emph{Make sure that any
1189 jumpers or switches match the system configuration you are
1190 working with.}
1192 Common issues include:
1194 @itemize @bullet
1196 @item @b{JTAG setup} ...
1197 Boards may support more than one JTAG configuration.
1198 Examples include jumpers controlling pullups versus pulldowns
1199 on the nTRST and/or nSRST signals, and choice of connectors
1200 (e.g. which of two headers on the base board,
1201 or one from a daughtercard).
1202 For some Texas Instruments boards, you may need to jumper the
1203 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1205 @item @b{Boot Modes} ...
1206 Complex chips often support multiple boot modes, controlled
1207 by external jumpers. Make sure this is set up correctly.
1208 For example many i.MX boards from NXP need to be jumpered
1209 to "ATX mode" to start booting using the on-chip ROM, when
1210 using second stage bootloader code stored in a NAND flash chip.
1212 Such explicit configuration is common, and not limited to
1213 booting from NAND. You might also need to set jumpers to
1214 start booting using code loaded from an MMC/SD card; external
1215 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1216 flash; some external host; or various other sources.
1219 @item @b{Memory Addressing} ...
1220 Boards which support multiple boot modes may also have jumpers
1221 to configure memory addressing. One board, for example, jumpers
1222 external chipselect 0 (used for booting) to address either
1223 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1224 or NAND flash. When it's jumpered to address NAND flash, that
1225 board must also be told to start booting from on-chip ROM.
1227 Your @file{board.cfg} file may also need to be told this jumper
1228 configuration, so that it can know whether to declare NOR flash
1229 using @command{flash bank} or instead declare NAND flash with
1230 @command{nand device}; and likewise which probe to perform in
1231 its @code{reset-init} handler.
1233 A closely related issue is bus width. Jumpers might need to
1234 distinguish between 8 bit or 16 bit bus access for the flash
1235 used to start booting.
1237 @item @b{Peripheral Access} ...
1238 Development boards generally provide access to every peripheral
1239 on the chip, sometimes in multiple modes (such as by providing
1240 multiple audio codec chips).
1241 This interacts with software
1242 configuration of pin multiplexing, where for example a
1243 given pin may be routed either to the MMC/SD controller
1244 or the GPIO controller. It also often interacts with
1245 configuration jumpers. One jumper may be used to route
1246 signals to an MMC/SD card slot or an expansion bus (which
1247 might in turn affect booting); others might control which
1248 audio or video codecs are used.
1250 @end itemize
1252 Plus you should of course have @code{reset-init} event handlers
1253 which set up the hardware to match that jumper configuration.
1254 That includes in particular any oscillator or PLL used to clock
1255 the CPU, and any memory controllers needed to access external
1256 memory and peripherals. Without such handlers, you won't be
1257 able to access those resources without working target firmware
1258 which can do that setup ... this can be awkward when you're
1259 trying to debug that target firmware. Even if there's a ROM
1260 bootloader which handles a few issues, it rarely provides full
1261 access to all board-specific capabilities.
1264 @node Config File Guidelines
1265 @chapter Config File Guidelines
1267 This chapter is aimed at any user who needs to write a config file,
1268 including developers and integrators of OpenOCD and any user who
1269 needs to get a new board working smoothly.
1270 It provides guidelines for creating those files.
1272 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1273 with files including the ones listed here.
1274 Use them as-is where you can; or as models for new files.
1275 @itemize @bullet
1276 @item @file{interface} ...
1277 These are for debug adapters.
1278 Files that configure JTAG adapters go here.
1279 @example
1280 $ ls interface -R
1281 interface/:
1282 altera-usb-blaster.cfg hilscher_nxhx50_re.cfg openocd-usb-hs.cfg
1283 arm-jtag-ew.cfg hitex_str9-comstick.cfg openrd.cfg
1284 at91rm9200.cfg icebear.cfg osbdm.cfg
1285 axm0432.cfg jlink.cfg parport.cfg
1286 busblaster.cfg jtagkey2.cfg parport_dlc5.cfg
1287 buspirate.cfg jtagkey2p.cfg redbee-econotag.cfg
1288 calao-usb-a9260-c01.cfg jtagkey.cfg redbee-usb.cfg
1289 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg rlink.cfg
1290 calao-usb-a9260.cfg jtag-lock-pick_tiny_2.cfg sheevaplug.cfg
1291 chameleon.cfg kt-link.cfg signalyzer.cfg
1292 cortino.cfg lisa-l.cfg signalyzer-h2.cfg
1293 digilent-hs1.cfg luminary.cfg signalyzer-h4.cfg
1294 dlp-usb1232h.cfg luminary-icdi.cfg signalyzer-lite.cfg
1295 dummy.cfg luminary-lm3s811.cfg stlink-v1.cfg
1296 estick.cfg minimodule.cfg stlink-v2.cfg
1297 flashlink.cfg neodb.cfg stm32-stick.cfg
1298 flossjtag.cfg ngxtech.cfg sysfsgpio-raspberrypi.cfg
1299 flossjtag-noeeprom.cfg olimex-arm-usb-ocd.cfg ti-icdi.cfg
1300 flyswatter2.cfg olimex-arm-usb-ocd-h.cfg turtelizer2.cfg
1301 flyswatter.cfg olimex-arm-usb-tiny-h.cfg ulink.cfg
1302 ftdi olimex-jtag-tiny.cfg usb-jtag.cfg
1303 hilscher_nxhx10_etm.cfg oocdlink.cfg usbprog.cfg
1304 hilscher_nxhx500_etm.cfg opendous.cfg vpaclink.cfg
1305 hilscher_nxhx500_re.cfg opendous_ftdi.cfg vsllink.cfg
1306 hilscher_nxhx50_etm.cfg openocd-usb.cfg xds100v2.cfg
1308 interface/ftdi:
1309 axm0432.cfg icebear.cfg oocdlink.cfg
1310 calao-usb-a9260-c01.cfg jtagkey2.cfg opendous_ftdi.cfg
1311 calao-usb-a9260-c02.cfg jtagkey2p.cfg openocd-usb.cfg
1312 cortino.cfg jtagkey.cfg openocd-usb-hs.cfg
1313 dlp-usb1232h.cfg jtag-lock-pick_tiny_2.cfg openrd.cfg
1314 dp_busblaster.cfg kt-link.cfg redbee-econotag.cfg
1315 flossjtag.cfg lisa-l.cfg redbee-usb.cfg
1316 flossjtag-noeeprom.cfg luminary.cfg sheevaplug.cfg
1317 flyswatter2.cfg luminary-icdi.cfg signalyzer.cfg
1318 flyswatter.cfg luminary-lm3s811.cfg signalyzer-lite.cfg
1319 hilscher_nxhx10_etm.cfg minimodule.cfg stm32-stick.cfg
1320 hilscher_nxhx500_etm.cfg neodb.cfg turtelizer2-revB.cfg
1321 hilscher_nxhx500_re.cfg ngxtech.cfg turtelizer2-revC.cfg
1322 hilscher_nxhx50_etm.cfg olimex-arm-usb-ocd.cfg vpaclink.cfg
1323 hilscher_nxhx50_re.cfg olimex-arm-usb-ocd-h.cfg xds100v2.cfg
1324 hitex_lpc1768stick.cfg olimex-arm-usb-tiny-h.cfg
1325 hitex_str9-comstick.cfg olimex-jtag-tiny.cfg
1326 $
1327 @end example
1328 @item @file{board} ...
1329 think Circuit Board, PWA, PCB, they go by many names. Board files
1330 contain initialization items that are specific to a board.
1331 They reuse target configuration files, since the same
1332 microprocessor chips are used on many boards,
1333 but support for external parts varies widely. For
1334 example, the SDRAM initialization sequence for the board, or the type
1335 of external flash and what address it uses. Any initialization
1336 sequence to enable that external flash or SDRAM should be found in the
1337 board file. Boards may also contain multiple targets: two CPUs; or
1338 a CPU and an FPGA.
1339 @example
1340 $ ls board
1341 actux3.cfg lpc1850_spifi_generic.cfg
1342 am3517evm.cfg lpc4350_spifi_generic.cfg
1343 arm_evaluator7t.cfg lubbock.cfg
1344 at91cap7a-stk-sdram.cfg mcb1700.cfg
1345 at91eb40a.cfg microchip_explorer16.cfg
1346 at91rm9200-dk.cfg mini2440.cfg
1347 at91rm9200-ek.cfg mini6410.cfg
1348 at91sam9261-ek.cfg netgear-dg834v3.cfg
1349 at91sam9263-ek.cfg olimex_LPC2378STK.cfg
1350 at91sam9g20-ek.cfg olimex_lpc_h2148.cfg
1351 atmel_at91sam7s-ek.cfg olimex_sam7_ex256.cfg
1352 atmel_at91sam9260-ek.cfg olimex_sam9_l9260.cfg
1353 atmel_at91sam9rl-ek.cfg olimex_stm32_h103.cfg
1354 atmel_sam3n_ek.cfg olimex_stm32_h107.cfg
1355 atmel_sam3s_ek.cfg olimex_stm32_p107.cfg
1356 atmel_sam3u_ek.cfg omap2420_h4.cfg
1357 atmel_sam3x_ek.cfg open-bldc.cfg
1358 atmel_sam4s_ek.cfg openrd.cfg
1359 balloon3-cpu.cfg osk5912.cfg
1360 colibri.cfg phone_se_j100i.cfg
1361 crossbow_tech_imote2.cfg phytec_lpc3250.cfg
1362 csb337.cfg pic-p32mx.cfg
1363 csb732.cfg propox_mmnet1001.cfg
1364 da850evm.cfg pxa255_sst.cfg
1365 digi_connectcore_wi-9c.cfg redbee.cfg
1366 diolan_lpc4350-db1.cfg rsc-w910.cfg
1367 dm355evm.cfg sheevaplug.cfg
1368 dm365evm.cfg smdk6410.cfg
1369 dm6446evm.cfg spear300evb.cfg
1370 efikamx.cfg spear300evb_mod.cfg
1371 eir.cfg spear310evb20.cfg
1372 ek-lm3s1968.cfg spear310evb20_mod.cfg
1373 ek-lm3s3748.cfg spear320cpu.cfg
1374 ek-lm3s6965.cfg spear320cpu_mod.cfg
1375 ek-lm3s811.cfg steval_pcc010.cfg
1376 ek-lm3s811-revb.cfg stm320518_eval_stlink.cfg
1377 ek-lm3s8962.cfg stm32100b_eval.cfg
1378 ek-lm3s9b9x.cfg stm3210b_eval.cfg
1379 ek-lm3s9d92.cfg stm3210c_eval.cfg
1380 ek-lm4f120xl.cfg stm3210e_eval.cfg
1381 ek-lm4f232.cfg stm3220g_eval.cfg
1382 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1383 ethernut3.cfg stm3241g_eval.cfg
1384 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1385 hammer.cfg stm32f0discovery.cfg
1386 hilscher_nxdb500sys.cfg stm32f3discovery.cfg
1387 hilscher_nxeb500hmi.cfg stm32f4discovery.cfg
1388 hilscher_nxhx10.cfg stm32ldiscovery.cfg
1389 hilscher_nxhx500.cfg stm32vldiscovery.cfg
1390 hilscher_nxhx50.cfg str910-eval.cfg
1391 hilscher_nxsb100.cfg telo.cfg
1392 hitex_lpc1768stick.cfg ti_am335xevm.cfg
1393 hitex_lpc2929.cfg ti_beagleboard.cfg
1394 hitex_stm32-performancestick.cfg ti_beagleboard_xm.cfg
1395 hitex_str9-comstick.cfg ti_beaglebone.cfg
1396 iar_lpc1768.cfg ti_blaze.cfg
1397 iar_str912_sk.cfg ti_pandaboard.cfg
1398 icnova_imx53_sodimm.cfg ti_pandaboard_es.cfg
1399 icnova_sam9g45_sodimm.cfg topas910.cfg
1400 imx27ads.cfg topasa900.cfg
1401 imx27lnst.cfg twr-k60f120m.cfg
1402 imx28evk.cfg twr-k60n512.cfg
1403 imx31pdk.cfg tx25_stk5.cfg
1404 imx35pdk.cfg tx27_stk5.cfg
1405 imx53loco.cfg unknown_at91sam9260.cfg
1406 keil_mcb1700.cfg uptech_2410.cfg
1407 keil_mcb2140.cfg verdex.cfg
1408 kwikstik.cfg voipac.cfg
1409 linksys_nslu2.cfg voltcraft_dso-3062c.cfg
1410 lisa-l.cfg x300t.cfg
1411 logicpd_imx27.cfg zy1000.cfg
1412 $
1413 @end example
1414 @item @file{target} ...
1415 think chip. The ``target'' directory represents the JTAG TAPs
1416 on a chip
1417 which OpenOCD should control, not a board. Two common types of targets
1418 are ARM chips and FPGA or CPLD chips.
1419 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1420 the target config file defines all of them.
1421 @example
1422 $ ls target
1423 aduc702x.cfg lpc1763.cfg
1424 am335x.cfg lpc1764.cfg
1425 amdm37x.cfg lpc1765.cfg
1426 ar71xx.cfg lpc1766.cfg
1427 at32ap7000.cfg lpc1767.cfg
1428 at91r40008.cfg lpc1768.cfg
1429 at91rm9200.cfg lpc1769.cfg
1430 at91sam3ax_4x.cfg lpc1788.cfg
1431 at91sam3ax_8x.cfg lpc17xx.cfg
1432 at91sam3ax_xx.cfg lpc1850.cfg
1433 at91sam3nXX.cfg lpc2103.cfg
1434 at91sam3sXX.cfg lpc2124.cfg
1435 at91sam3u1c.cfg lpc2129.cfg
1436 at91sam3u1e.cfg lpc2148.cfg
1437 at91sam3u2c.cfg lpc2294.cfg
1438 at91sam3u2e.cfg lpc2378.cfg
1439 at91sam3u4c.cfg lpc2460.cfg
1440 at91sam3u4e.cfg lpc2478.cfg
1441 at91sam3uxx.cfg lpc2900.cfg
1442 at91sam3XXX.cfg lpc2xxx.cfg
1443 at91sam4sd32x.cfg lpc3131.cfg
1444 at91sam4sXX.cfg lpc3250.cfg
1445 at91sam4XXX.cfg lpc4350.cfg
1446 at91sam7se512.cfg lpc4350.cfg.orig
1447 at91sam7sx.cfg mc13224v.cfg
1448 at91sam7x256.cfg nuc910.cfg
1449 at91sam7x512.cfg omap2420.cfg
1450 at91sam9260.cfg omap3530.cfg
1451 at91sam9260_ext_RAM_ext_flash.cfg omap4430.cfg
1452 at91sam9261.cfg omap4460.cfg
1453 at91sam9263.cfg omap5912.cfg
1454 at91sam9.cfg omapl138.cfg
1455 at91sam9g10.cfg pic32mx.cfg
1456 at91sam9g20.cfg pxa255.cfg
1457 at91sam9g45.cfg pxa270.cfg
1458 at91sam9rl.cfg pxa3xx.cfg
1459 atmega128.cfg readme.txt
1460 avr32.cfg samsung_s3c2410.cfg
1461 c100.cfg samsung_s3c2440.cfg
1462 c100config.tcl samsung_s3c2450.cfg
1463 c100helper.tcl samsung_s3c4510.cfg
1464 c100regs.tcl samsung_s3c6410.cfg
1465 cs351x.cfg sharp_lh79532.cfg
1466 davinci.cfg smp8634.cfg
1467 dragonite.cfg spear3xx.cfg
1468 dsp56321.cfg stellaris.cfg
1469 dsp568013.cfg stellaris_icdi.cfg
1470 dsp568037.cfg stm32f0x_stlink.cfg
1471 efm32_stlink.cfg stm32f1x.cfg
1472 epc9301.cfg stm32f1x_stlink.cfg
1473 faux.cfg stm32f2x.cfg
1474 feroceon.cfg stm32f2x_stlink.cfg
1475 fm3.cfg stm32f3x.cfg
1476 hilscher_netx10.cfg stm32f3x_stlink.cfg
1477 hilscher_netx500.cfg stm32f4x.cfg
1478 hilscher_netx50.cfg stm32f4x_stlink.cfg
1479 icepick.cfg stm32l.cfg
1480 imx21.cfg stm32lx_dual_bank.cfg
1481 imx25.cfg stm32lx_stlink.cfg
1482 imx27.cfg stm32_stlink.cfg
1483 imx28.cfg stm32w108_stlink.cfg
1484 imx31.cfg stm32xl.cfg
1485 imx35.cfg str710.cfg
1486 imx51.cfg str730.cfg
1487 imx53.cfg str750.cfg
1488 imx6.cfg str912.cfg
1489 imx.cfg swj-dp.tcl
1490 is5114.cfg test_reset_syntax_error.cfg
1491 ixp42x.cfg test_syntax_error.cfg
1492 k40.cfg ti-ar7.cfg
1493 k60.cfg ti_calypso.cfg
1494 lpc1751.cfg ti_dm355.cfg
1495 lpc1752.cfg ti_dm365.cfg
1496 lpc1754.cfg ti_dm6446.cfg
1497 lpc1756.cfg tmpa900.cfg
1498 lpc1758.cfg tmpa910.cfg
1499 lpc1759.cfg u8500.cfg
1500 @end example
1501 @item @emph{more} ... browse for other library files which may be useful.
1502 For example, there are various generic and CPU-specific utilities.
1503 @end itemize
1505 The @file{openocd.cfg} user config
1506 file may override features in any of the above files by
1507 setting variables before sourcing the target file, or by adding
1508 commands specific to their situation.
1510 @section Interface Config Files
1512 The user config file
1513 should be able to source one of these files with a command like this:
1515 @example
1516 source [find interface/FOOBAR.cfg]
1517 @end example
1519 A preconfigured interface file should exist for every debug adapter
1520 in use today with OpenOCD.
1521 That said, perhaps some of these config files
1522 have only been used by the developer who created it.
1524 A separate chapter gives information about how to set these up.
1525 @xref{Debug Adapter Configuration}.
1526 Read the OpenOCD source code (and Developer's Guide)
1527 if you have a new kind of hardware interface
1528 and need to provide a driver for it.
1530 @section Board Config Files
1531 @cindex config file, board
1532 @cindex board config file
1534 The user config file
1535 should be able to source one of these files with a command like this:
1537 @example
1538 source [find board/FOOBAR.cfg]
1539 @end example
1541 The point of a board config file is to package everything
1542 about a given board that user config files need to know.
1543 In summary the board files should contain (if present)
1545 @enumerate
1546 @item One or more @command{source [target/...cfg]} statements
1547 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1548 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1549 @item Target @code{reset} handlers for SDRAM and I/O configuration
1550 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1551 @item All things that are not ``inside a chip''
1552 @end enumerate
1554 Generic things inside target chips belong in target config files,
1555 not board config files. So for example a @code{reset-init} event
1556 handler should know board-specific oscillator and PLL parameters,
1557 which it passes to target-specific utility code.
1559 The most complex task of a board config file is creating such a
1560 @code{reset-init} event handler.
1561 Define those handlers last, after you verify the rest of the board
1562 configuration works.
1564 @subsection Communication Between Config files
1566 In addition to target-specific utility code, another way that
1567 board and target config files communicate is by following a
1568 convention on how to use certain variables.
1570 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1571 Thus the rule we follow in OpenOCD is this: Variables that begin with
1572 a leading underscore are temporary in nature, and can be modified and
1573 used at will within a target configuration file.
1575 Complex board config files can do the things like this,
1576 for a board with three chips:
1578 @example
1579 # Chip #1: PXA270 for network side, big endian
1580 set CHIPNAME network
1581 set ENDIAN big
1582 source [find target/pxa270.cfg]
1583 # on return: _TARGETNAME = network.cpu
1584 # other commands can refer to the "network.cpu" target.
1585 $_TARGETNAME configure .... events for this CPU..
1587 # Chip #2: PXA270 for video side, little endian
1588 set CHIPNAME video
1589 set ENDIAN little
1590 source [find target/pxa270.cfg]
1591 # on return: _TARGETNAME = video.cpu
1592 # other commands can refer to the "video.cpu" target.
1593 $_TARGETNAME configure .... events for this CPU..
1595 # Chip #3: Xilinx FPGA for glue logic
1596 set CHIPNAME xilinx
1597 unset ENDIAN
1598 source [find target/spartan3.cfg]
1599 @end example
1601 That example is oversimplified because it doesn't show any flash memory,
1602 or the @code{reset-init} event handlers to initialize external DRAM
1603 or (assuming it needs it) load a configuration into the FPGA.
1604 Such features are usually needed for low-level work with many boards,
1605 where ``low level'' implies that the board initialization software may
1606 not be working. (That's a common reason to need JTAG tools. Another
1607 is to enable working with microcontroller-based systems, which often
1608 have no debugging support except a JTAG connector.)
1610 Target config files may also export utility functions to board and user
1611 config files. Such functions should use name prefixes, to help avoid
1612 naming collisions.
1614 Board files could also accept input variables from user config files.
1615 For example, there might be a @code{J4_JUMPER} setting used to identify
1616 what kind of flash memory a development board is using, or how to set
1617 up other clocks and peripherals.
1619 @subsection Variable Naming Convention
1620 @cindex variable names
1622 Most boards have only one instance of a chip.
1623 However, it should be easy to create a board with more than
1624 one such chip (as shown above).
1625 Accordingly, we encourage these conventions for naming
1626 variables associated with different @file{target.cfg} files,
1627 to promote consistency and
1628 so that board files can override target defaults.
1630 Inputs to target config files include:
1632 @itemize @bullet
1633 @item @code{CHIPNAME} ...
1634 This gives a name to the overall chip, and is used as part of
1635 tap identifier dotted names.
1636 While the default is normally provided by the chip manufacturer,
1637 board files may need to distinguish between instances of a chip.
1638 @item @code{ENDIAN} ...
1639 By default @option{little} - although chips may hard-wire @option{big}.
1640 Chips that can't change endianness don't need to use this variable.
1641 @item @code{CPUTAPID} ...
1642 When OpenOCD examines the JTAG chain, it can be told verify the
1643 chips against the JTAG IDCODE register.
1644 The target file will hold one or more defaults, but sometimes the
1645 chip in a board will use a different ID (perhaps a newer revision).
1646 @end itemize
1648 Outputs from target config files include:
1650 @itemize @bullet
1651 @item @code{_TARGETNAME} ...
1652 By convention, this variable is created by the target configuration
1653 script. The board configuration file may make use of this variable to
1654 configure things like a ``reset init'' script, or other things
1655 specific to that board and that target.
1656 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1657 @code{_TARGETNAME1}, ... etc.
1658 @end itemize
1660 @subsection The reset-init Event Handler
1661 @cindex event, reset-init
1662 @cindex reset-init handler
1664 Board config files run in the OpenOCD configuration stage;
1665 they can't use TAPs or targets, since they haven't been
1666 fully set up yet.
1667 This means you can't write memory or access chip registers;
1668 you can't even verify that a flash chip is present.
1669 That's done later in event handlers, of which the target @code{reset-init}
1670 handler is one of the most important.
1672 Except on microcontrollers, the basic job of @code{reset-init} event
1673 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1674 Microcontrollers rarely use boot loaders; they run right out of their
1675 on-chip flash and SRAM memory. But they may want to use one of these
1676 handlers too, if just for developer convenience.
1678 @quotation Note
1679 Because this is so very board-specific, and chip-specific, no examples
1680 are included here.
1681 Instead, look at the board config files distributed with OpenOCD.
1682 If you have a boot loader, its source code will help; so will
1683 configuration files for other JTAG tools
1684 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1685 @end quotation
1687 Some of this code could probably be shared between different boards.
1688 For example, setting up a DRAM controller often doesn't differ by
1689 much except the bus width (16 bits or 32?) and memory timings, so a
1690 reusable TCL procedure loaded by the @file{target.cfg} file might take
1691 those as parameters.
1692 Similarly with oscillator, PLL, and clock setup;
1693 and disabling the watchdog.
1694 Structure the code cleanly, and provide comments to help
1695 the next developer doing such work.
1696 (@emph{You might be that next person} trying to reuse init code!)
1698 The last thing normally done in a @code{reset-init} handler is probing
1699 whatever flash memory was configured. For most chips that needs to be
1700 done while the associated target is halted, either because JTAG memory
1701 access uses the CPU or to prevent conflicting CPU access.
1703 @subsection JTAG Clock Rate
1705 Before your @code{reset-init} handler has set up
1706 the PLLs and clocking, you may need to run with
1707 a low JTAG clock rate.
1708 @xref{jtagspeed,,JTAG Speed}.
1709 Then you'd increase that rate after your handler has
1710 made it possible to use the faster JTAG clock.
1711 When the initial low speed is board-specific, for example
1712 because it depends on a board-specific oscillator speed, then
1713 you should probably set it up in the board config file;
1714 if it's target-specific, it belongs in the target config file.
1716 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1717 @uref{} gives details.}
1718 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1719 Consult chip documentation to determine the peak JTAG clock rate,
1720 which might be less than that.
1722 @quotation Warning
1723 On most ARMs, JTAG clock detection is coupled to the core clock, so
1724 software using a @option{wait for interrupt} operation blocks JTAG access.
1725 Adaptive clocking provides a partial workaround, but a more complete
1726 solution just avoids using that instruction with JTAG debuggers.
1727 @end quotation
1729 If both the chip and the board support adaptive clocking,
1730 use the @command{jtag_rclk}
1731 command, in case your board is used with JTAG adapter which
1732 also supports it. Otherwise use @command{adapter_khz}.
1733 Set the slow rate at the beginning of the reset sequence,
1734 and the faster rate as soon as the clocks are at full speed.
1736 @anchor{theinitboardprocedure}
1737 @subsection The init_board procedure
1738 @cindex init_board procedure
1740 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1741 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1742 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1743 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1744 spearate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1745 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1746 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1747 Additionally ``linear'' board config file will most likely fail when target config file uses
1748 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1749 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1750 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1751 need to override @code{init_targets} defined in target config files when they only need to to add some specifics.
1753 Just as @code{init_targets}, the @code{init_board} procedure can be overriden by ``next level'' script (which sources
1754 the original), allowing greater code reuse.
1756 @example
1757 ### board_file.cfg ###
1759 # source target file that does most of the config in init_targets
1760 source [find target/target.cfg]
1762 proc enable_fast_clock @{@} @{
1763 # enables fast on-board clock source
1764 # configures the chip to use it
1765 @}
1767 # initialize only board specifics - reset, clock, adapter frequency
1768 proc init_board @{@} @{
1769 reset_config trst_and_srst trst_pulls_srst
1771 $_TARGETNAME configure -event reset-init @{
1772 adapter_khz 1
1773 enable_fast_clock
1774 adapter_khz 10000
1775 @}
1776 @}
1777 @end example
1779 @section Target Config Files
1780 @cindex config file, target
1781 @cindex target config file
1783 Board config files communicate with target config files using
1784 naming conventions as described above, and may source one or
1785 more target config files like this:
1787 @example
1788 source [find target/FOOBAR.cfg]
1789 @end example
1791 The point of a target config file is to package everything
1792 about a given chip that board config files need to know.
1793 In summary the target files should contain
1795 @enumerate
1796 @item Set defaults
1797 @item Add TAPs to the scan chain
1798 @item Add CPU targets (includes GDB support)
1799 @item CPU/Chip/CPU-Core specific features
1800 @item On-Chip flash
1801 @end enumerate
1803 As a rule of thumb, a target file sets up only one chip.
1804 For a microcontroller, that will often include a single TAP,
1805 which is a CPU needing a GDB target, and its on-chip flash.
1807 More complex chips may include multiple TAPs, and the target
1808 config file may need to define them all before OpenOCD
1809 can talk to the chip.
1810 For example, some phone chips have JTAG scan chains that include
1811 an ARM core for operating system use, a DSP,
1812 another ARM core embedded in an image processing engine,
1813 and other processing engines.
1815 @subsection Default Value Boiler Plate Code
1817 All target configuration files should start with code like this,
1818 letting board config files express environment-specific
1819 differences in how things should be set up.
1821 @example
1822 # Boards may override chip names, perhaps based on role,
1823 # but the default should match what the vendor uses
1824 if @{ [info exists CHIPNAME] @} @{
1826 @} else @{
1827 set _CHIPNAME sam7x256
1828 @}
1830 # ONLY use ENDIAN with targets that can change it.
1831 if @{ [info exists ENDIAN] @} @{
1832 set _ENDIAN $ENDIAN
1833 @} else @{
1834 set _ENDIAN little
1835 @}
1837 # TAP identifiers may change as chips mature, for example with
1838 # new revision fields (the "3" here). Pick a good default; you
1839 # can pass several such identifiers to the "jtag newtap" command.
1840 if @{ [info exists CPUTAPID ] @} @{
1842 @} else @{
1843 set _CPUTAPID 0x3f0f0f0f
1844 @}
1845 @end example
1846 @c but 0x3f0f0f0f is for an str73x part ...
1848 @emph{Remember:} Board config files may include multiple target
1849 config files, or the same target file multiple times
1850 (changing at least @code{CHIPNAME}).
1852 Likewise, the target configuration file should define
1853 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1854 use it later on when defining debug targets:
1856 @example
1858 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1859 @end example
1861 @subsection Adding TAPs to the Scan Chain
1862 After the ``defaults'' are set up,
1863 add the TAPs on each chip to the JTAG scan chain.
1864 @xref{TAP Declaration}, and the naming convention
1865 for taps.
1867 In the simplest case the chip has only one TAP,
1868 probably for a CPU or FPGA.
1869 The config file for the Atmel AT91SAM7X256
1870 looks (in part) like this:
1872 @example
1873 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1874 @end example
1876 A board with two such at91sam7 chips would be able
1877 to source such a config file twice, with different
1878 values for @code{CHIPNAME}, so
1879 it adds a different TAP each time.
1881 If there are nonzero @option{-expected-id} values,
1882 OpenOCD attempts to verify the actual tap id against those values.
1883 It will issue error messages if there is mismatch, which
1884 can help to pinpoint problems in OpenOCD configurations.
1886 @example
1887 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1888 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1889 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1890 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1891 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1892 @end example
1894 There are more complex examples too, with chips that have
1895 multiple TAPs. Ones worth looking at include:
1897 @itemize
1898 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1899 plus a JRC to enable them
1900 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1901 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1902 is not currently used)
1903 @end itemize
1905 @subsection Add CPU targets
1907 After adding a TAP for a CPU, you should set it up so that
1908 GDB and other commands can use it.
1909 @xref{CPU Configuration}.
1910 For the at91sam7 example above, the command can look like this;
1911 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1912 to little endian, and this chip doesn't support changing that.
1914 @example
1916 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1917 @end example
1919 Work areas are small RAM areas associated with CPU targets.
1920 They are used by OpenOCD to speed up downloads,
1921 and to download small snippets of code to program flash chips.
1922 If the chip includes a form of ``on-chip-ram'' - and many do - define
1923 a work area if you can.
1924 Again using the at91sam7 as an example, this can look like:
1926 @example
1927 $_TARGETNAME configure -work-area-phys 0x00200000 \
1928 -work-area-size 0x4000 -work-area-backup 0
1929 @end example
1931 @anchor{definecputargetsworkinginsmp}
1932 @subsection Define CPU targets working in SMP
1933 @cindex SMP
1934 After setting targets, you can define a list of targets working in SMP.
1936 @example
1937 set _TARGETNAME_1 $_CHIPNAME.cpu1
1938 set _TARGETNAME_2 $_CHIPNAME.cpu2
1939 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1940 -coreid 0 -dbgbase $_DAP_DBG1
1941 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1942 -coreid 1 -dbgbase $_DAP_DBG2
1943 #define 2 targets working in smp.
1944 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1945 @end example
1946 In the above example on cortex_a, 2 cpus are working in SMP.
1947 In SMP only one GDB instance is created and :
1948 @itemize @bullet
1949 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1950 @item halt command triggers the halt of all targets in the list.
1951 @item resume command triggers the write context and the restart of all targets in the list.
1952 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1953 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1954 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1955 @end itemize
1957 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1958 command have been implemented.
1959 @itemize @bullet
1960 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1961 @item cortex_a smp_off : disable SMP mode, the current target is the one
1962 displayed in the GDB session, only this target is now controlled by GDB
1963 session. This behaviour is useful during system boot up.
1964 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1965 following example.
1966 @end itemize
1968 @example
1969 >cortex_a smp_gdb
1970 gdb coreid 0 -> -1
1971 #0 : coreid 0 is displayed to GDB ,
1972 #-> -1 : next resume triggers a real resume
1973 > cortex_a smp_gdb 1
1974 gdb coreid 0 -> 1
1975 #0 :coreid 0 is displayed to GDB ,
1976 #->1 : next resume displays coreid 1 to GDB
1977 > resume
1978 > cortex_a smp_gdb
1979 gdb coreid 1 -> 1
1980 #1 :coreid 1 is displayed to GDB ,
1981 #->1 : next resume displays coreid 1 to GDB
1982 > cortex_a smp_gdb -1
1983 gdb coreid 1 -> -1
1984 #1 :coreid 1 is displayed to GDB,
1985 #->-1 : next resume triggers a real resume
1986 @end example
1989 @subsection Chip Reset Setup
1991 As a rule, you should put the @command{reset_config} command
1992 into the board file. Most things you think you know about a
1993 chip can be tweaked by the board.
1995 Some chips have specific ways the TRST and SRST signals are
1996 managed. In the unusual case that these are @emph{chip specific}
1997 and can never be changed by board wiring, they could go here.
1998 For example, some chips can't support JTAG debugging without
1999 both signals.
2001 Provide a @code{reset-assert} event handler if you can.
2002 Such a handler uses JTAG operations to reset the target,
2003 letting this target config be used in systems which don't
2004 provide the optional SRST signal, or on systems where you
2005 don't want to reset all targets at once.
2006 Such a handler might write to chip registers to force a reset,
2007 use a JRC to do that (preferable -- the target may be wedged!),
2008 or force a watchdog timer to trigger.
2009 (For Cortex-M targets, this is not necessary. The target
2010 driver knows how to use trigger an NVIC reset when SRST is
2011 not available.)
2013 Some chips need special attention during reset handling if
2014 they're going to be used with JTAG.
2015 An example might be needing to send some commands right
2016 after the target's TAP has been reset, providing a
2017 @code{reset-deassert-post} event handler that writes a chip
2018 register to report that JTAG debugging is being done.
2019 Another would be reconfiguring the watchdog so that it stops
2020 counting while the core is halted in the debugger.
2022 JTAG clocking constraints often change during reset, and in
2023 some cases target config files (rather than board config files)
2024 are the right places to handle some of those issues.
2025 For example, immediately after reset most chips run using a
2026 slower clock than they will use later.
2027 That means that after reset (and potentially, as OpenOCD
2028 first starts up) they must use a slower JTAG clock rate
2029 than they will use later.
2030 @xref{jtagspeed,,JTAG Speed}.
2032 @quotation Important
2033 When you are debugging code that runs right after chip
2034 reset, getting these issues right is critical.
2035 In particular, if you see intermittent failures when
2036 OpenOCD verifies the scan chain after reset,
2037 look at how you are setting up JTAG clocking.
2038 @end quotation
2040 @anchor{theinittargetsprocedure}
2041 @subsection The init_targets procedure
2042 @cindex init_targets procedure
2044 Target config files can either be ``linear'' (script executed line-by-line when parsed in
2045 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
2046 procedure called @code{init_targets}, which will be executed when entering run stage
2047 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
2048 Such procedure can be overriden by ``next level'' script (which sources the original).
2049 This concept faciliates code reuse when basic target config files provide generic configuration
2050 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
2051 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
2052 because sourcing them executes every initialization commands they provide.
2054 @example
2055 ### generic_file.cfg ###
2057 proc setup_my_chip @{chip_name flash_size ram_size@} @{
2058 # basic initialization procedure ...
2059 @}
2061 proc init_targets @{@} @{
2062 # initializes generic chip with 4kB of flash and 1kB of RAM
2063 setup_my_chip MY_GENERIC_CHIP 4096 1024
2064 @}
2066 ### specific_file.cfg ###
2068 source [find target/generic_file.cfg]
2070 proc init_targets @{@} @{
2071 # initializes specific chip with 128kB of flash and 64kB of RAM
2072 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
2073 @}
2074 @end example
2076 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
2077 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
2079 For an example of this scheme see LPC2000 target config files.
2081 The @code{init_boards} procedure is a similar concept concerning board config files
2082 (@xref{theinitboardprocedure,,The init_board procedure}.)
2084 @subsection ARM Core Specific Hacks
2086 If the chip has a DCC, enable it. If the chip is an ARM9 with some
2087 special high speed download features - enable it.
2089 If present, the MMU, the MPU and the CACHE should be disabled.
2091 Some ARM cores are equipped with trace support, which permits
2092 examination of the instruction and data bus activity. Trace
2093 activity is controlled through an ``Embedded Trace Module'' (ETM)
2094 on one of the core's scan chains. The ETM emits voluminous data
2095 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
2096 If you are using an external trace port,
2097 configure it in your board config file.
2098 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2099 configure it in your target config file.
2101 @example
2102 etm config $_TARGETNAME 16 normal full etb
2103 etb config $_TARGETNAME $_CHIPNAME.etb
2104 @end example
2106 @subsection Internal Flash Configuration
2108 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2110 @b{Never ever} in the ``target configuration file'' define any type of
2111 flash that is external to the chip. (For example a BOOT flash on
2112 Chip Select 0.) Such flash information goes in a board file - not
2113 the TARGET (chip) file.
2115 Examples:
2116 @itemize @bullet
2117 @item at91sam7x256 - has 256K flash YES enable it.
2118 @item str912 - has flash internal YES enable it.
2119 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2120 @item pxa270 - again - CS0 flash - it goes in the board file.
2121 @end itemize
2123 @anchor{translatingconfigurationfiles}
2124 @section Translating Configuration Files
2125 @cindex translation
2126 If you have a configuration file for another hardware debugger
2127 or toolset (Abatron, BDI2000, BDI3000, CCS,
2128 Lauterbach, Segger, Macraigor, etc.), translating
2129 it into OpenOCD syntax is often quite straightforward. The most tricky
2130 part of creating a configuration script is oftentimes the reset init
2131 sequence where e.g. PLLs, DRAM and the like is set up.
2133 One trick that you can use when translating is to write small
2134 Tcl procedures to translate the syntax into OpenOCD syntax. This
2135 can avoid manual translation errors and make it easier to
2136 convert other scripts later on.
2138 Example of transforming quirky arguments to a simple search and
2139 replace job:
2141 @example
2142 # Lauterbach syntax(?)
2143 #
2144 # Data.Set c15:0x042f %long 0x40000015
2145 #
2146 # OpenOCD syntax when using procedure below.
2147 #
2148 # setc15 0x01 0x00050078
2150 proc setc15 @{regs value@} @{
2151 global TARGETNAME
2153 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2155 arm mcr 15 [expr ($regs>>12)&0x7] \
2156 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2157 [expr ($regs>>8)&0x7] $value
2158 @}
2159 @end example
2163 @node Daemon Configuration
2164 @chapter Daemon Configuration
2165 @cindex initialization
2166 The commands here are commonly found in the openocd.cfg file and are
2167 used to specify what TCP/IP ports are used, and how GDB should be
2168 supported.
2170 @anchor{configurationstage}
2171 @section Configuration Stage
2172 @cindex configuration stage
2173 @cindex config command
2175 When the OpenOCD server process starts up, it enters a
2176 @emph{configuration stage} which is the only time that
2177 certain commands, @emph{configuration commands}, may be issued.
2178 Normally, configuration commands are only available
2179 inside startup scripts.
2181 In this manual, the definition of a configuration command is
2182 presented as a @emph{Config Command}, not as a @emph{Command}
2183 which may be issued interactively.
2184 The runtime @command{help} command also highlights configuration
2185 commands, and those which may be issued at any time.
2187 Those configuration commands include declaration of TAPs,
2188 flash banks,
2189 the interface used for JTAG communication,
2190 and other basic setup.
2191 The server must leave the configuration stage before it
2192 may access or activate TAPs.
2193 After it leaves this stage, configuration commands may no
2194 longer be issued.
2196 @anchor{enteringtherunstage}
2197 @section Entering the Run Stage
2199 The first thing OpenOCD does after leaving the configuration
2200 stage is to verify that it can talk to the scan chain
2201 (list of TAPs) which has been configured.
2202 It will warn if it doesn't find TAPs it expects to find,
2203 or finds TAPs that aren't supposed to be there.
2204 You should see no errors at this point.
2205 If you see errors, resolve them by correcting the
2206 commands you used to configure the server.
2207 Common errors include using an initial JTAG speed that's too
2208 fast, and not providing the right IDCODE values for the TAPs
2209 on the scan chain.
2211 Once OpenOCD has entered the run stage, a number of commands
2212 become available.
2213 A number of these relate to the debug targets you may have declared.
2214 For example, the @command{mww} command will not be available until
2215 a target has been successfuly instantiated.
2216 If you want to use those commands, you may need to force
2217 entry to the run stage.
2219 @deffn {Config Command} init
2220 This command terminates the configuration stage and
2221 enters the run stage. This helps when you need to have
2222 the startup scripts manage tasks such as resetting the target,
2223 programming flash, etc. To reset the CPU upon startup, add "init" and
2224 "reset" at the end of the config script or at the end of the OpenOCD
2225 command line using the @option{-c} command line switch.
2227 If this command does not appear in any startup/configuration file
2228 OpenOCD executes the command for you after processing all
2229 configuration files and/or command line options.
2231 @b{NOTE:} This command normally occurs at or near the end of your
2232 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2233 targets ready. For example: If your openocd.cfg file needs to
2234 read/write memory on your target, @command{init} must occur before
2235 the memory read/write commands. This includes @command{nand probe}.
2236 @end deffn
2238 @deffn {Overridable Procedure} jtag_init
2239 This is invoked at server startup to verify that it can talk
2240 to the scan chain (list of TAPs) which has been configured.
2242 The default implementation first tries @command{jtag arp_init},
2243 which uses only a lightweight JTAG reset before examining the
2244 scan chain.
2245 If that fails, it tries again, using a harder reset
2246 from the overridable procedure @command{init_reset}.
2248 Implementations must have verified the JTAG scan chain before
2249 they return.
2250 This is done by calling @command{jtag arp_init}
2251 (or @command{jtag arp_init-reset}).
2252 @end deffn
2254 @anchor{tcpipports}
2255 @section TCP/IP Ports
2256 @cindex TCP port
2257 @cindex server
2258 @cindex port
2259 @cindex security
2260 The OpenOCD server accepts remote commands in several syntaxes.
2261 Each syntax uses a different TCP/IP port, which you may specify
2262 only during configuration (before those ports are opened).
2264 For reasons including security, you may wish to prevent remote
2265 access using one or more of these ports.
2266 In such cases, just specify the relevant port number as zero.
2267 If you disable all access through TCP/IP, you will need to
2268 use the command line @option{-pipe} option.
2270 @deffn {Command} gdb_port [number]
2271 @cindex GDB server
2272 Normally gdb listens to a TCP/IP port, but GDB can also
2273 communicate via pipes(stdin/out or named pipes). The name
2274 "gdb_port" stuck because it covers probably more than 90% of
2275 the normal use cases.
2277 No arguments reports GDB port. "pipe" means listen to stdin
2278 output to stdout, an integer is base port number, "disable"
2279 disables the gdb server.
2281 When using "pipe", also use log_output to redirect the log
2282 output to a file so as not to flood the stdin/out pipes.
2284 The -p/--pipe option is deprecated and a warning is printed
2285 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2287 Any other string is interpreted as named pipe to listen to.
2288 Output pipe is the same name as input pipe, but with 'o' appended,
2289 e.g. /var/gdb, /var/gdbo.
2291 The GDB port for the first target will be the base port, the
2292 second target will listen on gdb_port + 1, and so on.
2293 When not specified during the configuration stage,
2294 the port @var{number} defaults to 3333.
2295 @end deffn
2297 @deffn {Command} tcl_port [number]
2298 Specify or query the port used for a simplified RPC
2299 connection that can be used by clients to issue TCL commands and get the
2300 output from the Tcl engine.
2301 Intended as a machine interface.
2302 When not specified during the configuration stage,
2303 the port @var{number} defaults to 6666.
2305 @end deffn
2307 @deffn {Command} telnet_port [number]
2308 Specify or query the
2309 port on which to listen for incoming telnet connections.
2310 This port is intended for interaction with one human through TCL commands.
2311 When not specified during the configuration stage,
2312 the port @var{number} defaults to 4444.
2313 When specified as zero, this port is not activated.
2314 @end deffn
2316 @anchor{gdbconfiguration}
2317 @section GDB Configuration
2318 @cindex GDB
2319 @cindex GDB configuration
2320 You can reconfigure some GDB behaviors if needed.
2321 The ones listed here are static and global.
2322 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2323 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2325 @anchor{gdbbreakpointoverride}
2326 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2327 Force breakpoint type for gdb @command{break} commands.
2328 This option supports GDB GUIs which don't
2329 distinguish hard versus soft breakpoints, if the default OpenOCD and
2330 GDB behaviour is not sufficient. GDB normally uses hardware
2331 breakpoints if the memory map has been set up for flash regions.
2332 @end deffn
2334 @anchor{gdbflashprogram}
2335 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2336 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2337 vFlash packet is received.
2338 The default behaviour is @option{enable}.
2339 @end deffn
2341 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2342 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2343 requested. GDB will then know when to set hardware breakpoints, and program flash
2344 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2345 for flash programming to work.
2346 Default behaviour is @option{enable}.
2347 @xref{gdbflashprogram,,gdb_flash_program}.
2348 @end deffn
2350 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2351 Specifies whether data aborts cause an error to be reported
2352 by GDB memory read packets.
2353 The default behaviour is @option{disable};
2354 use @option{enable} see these errors reported.
2355 @end deffn
2357 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2358 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2359 The default behaviour is @option{disable}.
2360 @end deffn
2362 @deffn {Command} gdb_save_tdesc
2363 Saves the target descripton file to the local file system.
2365 The file name is @i{target_name}.xml.
2366 @end deffn
2368 @anchor{eventpolling}
2369 @section Event Polling
2371 Hardware debuggers are parts of asynchronous systems,
2372 where significant events can happen at any time.
2373 The OpenOCD server needs to detect some of these events,
2374 so it can report them to through TCL command line
2375 or to GDB.
2377 Examples of such events include:
2379 @itemize
2380 @item One of the targets can stop running ... maybe it triggers
2381 a code breakpoint or data watchpoint, or halts itself.
2382 @item Messages may be sent over ``debug message'' channels ... many
2383 targets support such messages sent over JTAG,
2384 for receipt by the person debugging or tools.
2385 @item Loss of power ... some adapters can detect these events.
2386 @item Resets not issued through JTAG ... such reset sources
2387 can include button presses or other system hardware, sometimes
2388 including the target itself (perhaps through a watchdog).
2389 @item Debug instrumentation sometimes supports event triggering
2390 such as ``trace buffer full'' (so it can quickly be emptied)
2391 or other signals (to correlate with code behavior).
2392 @end itemize
2394 None of those events are signaled through standard JTAG signals.
2395 However, most conventions for JTAG connectors include voltage
2396 level and system reset (SRST) signal detection.
2397 Some connectors also include instrumentation signals, which
2398 can imply events when those signals are inputs.
2400 In general, OpenOCD needs to periodically check for those events,
2401 either by looking at the status of signals on the JTAG connector
2402 or by sending synchronous ``tell me your status'' JTAG requests
2403 to the various active targets.
2404 There is a command to manage and monitor that polling,
2405 which is normally done in the background.
2407 @deffn Command poll [@option{on}|@option{off}]
2408 Poll the current target for its current state.
2409 (Also, @pxref{targetcurstate,,target curstate}.)
2410 If that target is in debug mode, architecture
2411 specific information about the current state is printed.
2412 An optional parameter
2413 allows background polling to be enabled and disabled.
2415 You could use this from the TCL command shell, or
2416 from GDB using @command{monitor poll} command.
2417 Leave background polling enabled while you're using GDB.
2418 @example
2419 > poll
2420 background polling: on
2421 target state: halted
2422 target halted in ARM state due to debug-request, \
2423 current mode: Supervisor
2424 cpsr: 0x800000d3 pc: 0x11081bfc
2425 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2426 >
2427 @end example
2428 @end deffn
2430 @node Debug Adapter Configuration
2431 @chapter Debug Adapter Configuration
2432 @cindex config file, interface
2433 @cindex interface config file
2435 Correctly installing OpenOCD includes making your operating system give
2436 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2437 are used to select which one is used, and to configure how it is used.
2439 @quotation Note
2440 Because OpenOCD started out with a focus purely on JTAG, you may find
2441 places where it wrongly presumes JTAG is the only transport protocol
2442 in use. Be aware that recent versions of OpenOCD are removing that
2443 limitation. JTAG remains more functional than most other transports.
2444 Other transports do not support boundary scan operations, or may be
2445 specific to a given chip vendor. Some might be usable only for
2446 programming flash memory, instead of also for debugging.
2447 @end quotation
2449 Debug Adapters/Interfaces/Dongles are normally configured
2450 through commands in an interface configuration
2451 file which is sourced by your @file{openocd.cfg} file, or
2452 through a command line @option{-f interface/....cfg} option.
2454 @example
2455 source [find interface/olimex-jtag-tiny.cfg]
2456 @end example
2458 These commands tell
2459 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2460 A few cases are so simple that you only need to say what driver to use:
2462 @example
2463 # jlink interface
2464 interface jlink
2465 @end example
2467 Most adapters need a bit more configuration than that.
2470 @section Interface Configuration
2472 The interface command tells OpenOCD what type of debug adapter you are
2473 using. Depending on the type of adapter, you may need to use one or
2474 more additional commands to further identify or configure the adapter.
2476 @deffn {Config Command} {interface} name
2477 Use the interface driver @var{name} to connect to the
2478 target.
2479 @end deffn
2481 @deffn Command {interface_list}
2482 List the debug adapter drivers that have been built into
2483 the running copy of OpenOCD.
2484 @end deffn
2485 @deffn Command {interface transports} transport_name+
2486 Specifies the transports supported by this debug adapter.
2487 The adapter driver builds-in similar knowledge; use this only
2488 when external configuration (such as jumpering) changes what
2489 the hardware can support.
2490 @end deffn
2494 @deffn Command {adapter_name}
2495 Returns the name of the debug adapter driver being used.
2496 @end deffn
2498 @section Interface Drivers
2500 Each of the interface drivers listed here must be explicitly
2501 enabled when OpenOCD is configured, in order to be made
2502 available at run time.
2504 @deffn {Interface Driver} {amt_jtagaccel}
2505 Amontec Chameleon in its JTAG Accelerator configuration,
2506 connected to a PC's EPP mode parallel port.
2507 This defines some driver-specific commands:
2509 @deffn {Config Command} {parport_port} number
2510 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2511 the number of the @file{/dev/parport} device.
2512 @end deffn
2514 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2515 Displays status of RTCK option.
2516 Optionally sets that option first.
2517 @end deffn
2518 @end deffn
2520 @deffn {Interface Driver} {arm-jtag-ew}
2521 Olimex ARM-JTAG-EW USB adapter
2522 This has one driver-specific command:
2524 @deffn Command {armjtagew_info}
2525 Logs some status
2526 @end deffn
2527 @end deffn
2529 @deffn {Interface Driver} {at91rm9200}
2530 Supports bitbanged JTAG from the local system,
2531 presuming that system is an Atmel AT91rm9200
2532 and a specific set of GPIOs is used.
2533 @c command: at91rm9200_device NAME
2534 @c chooses among list of bit configs ... only one option
2535 @end deffn
2537 @deffn {Interface Driver} {dummy}
2538 A dummy software-only driver for debugging.
2539 @end deffn
2541 @deffn {Interface Driver} {ep93xx}
2542 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2543 @end deffn
2545 @deffn {Interface Driver} {ft2232}
2546 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2548 Note that this driver has several flaws and the @command{ftdi} driver is
2549 recommended as its replacement.
2551 These interfaces have several commands, used to configure the driver
2552 before initializing the JTAG scan chain:
2554 @deffn {Config Command} {ft2232_device_desc} description
2555 Provides the USB device description (the @emph{iProduct string})
2556 of the FTDI FT2232 device. If not
2557 specified, the FTDI default value is used. This setting is only valid
2558 if compiled with FTD2XX support.
2559 @end deffn
2561 @deffn {Config Command} {ft2232_serial} serial-number
2562 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2563 in case the vendor provides unique IDs and more than one FT2232 device
2564 is connected to the host.
2565 If not specified, serial numbers are not considered.
2566 (Note that USB serial numbers can be arbitrary Unicode strings,
2567 and are not restricted to containing only decimal digits.)
2568 @end deffn
2570 @deffn {Config Command} {ft2232_layout} name
2571 Each vendor's FT2232 device can use different GPIO signals
2572 to control output-enables, reset signals, and LEDs.
2573 Currently valid layout @var{name} values include:
2574 @itemize @minus
2575 @item @b{axm0432_jtag} Axiom AXM-0432
2576 @item @b{comstick} Hitex STR9 comstick
2577 @item @b{cortino} Hitex Cortino JTAG interface
2578 @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
2579 either for the local Cortex-M3 (SRST only)
2580 or in a passthrough mode (neither SRST nor TRST)
2581 This layout can not support the SWO trace mechanism, and should be
2582 used only for older boards (before rev C).
2583 @item @b{luminary_icdi} This layout should be used with most TI/Luminary
2584 eval boards, including Rev C LM3S811 eval boards and the eponymous
2585 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2586 to debug some other target. It can support the SWO trace mechanism.
2587 @item @b{flyswatter} Tin Can Tools Flyswatter
2588 @item @b{icebear} ICEbear JTAG adapter from Section 5
2589 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2590 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2591 @item @b{m5960} American Microsystems M5960
2592 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2593 @item @b{oocdlink} OOCDLink
2594 @c oocdlink ~= jtagkey_prototype_v1
2595 @item @b{redbee-econotag} Integrated with a Redbee development board.
2596 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2597 @item @b{sheevaplug} Marvell Sheevaplug development kit
2598 @item @b{signalyzer} Xverve Signalyzer
2599 @item @b{stm32stick} Hitex STM32 Performance Stick
2600 @item @b{turtelizer2} egnite Software turtelizer2
2601 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2602 @end itemize
2603 @end deffn
2605 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2606 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2607 default values are used.
2608 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2609 @example
2610 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2611 @end example
2612 @end deffn
2614 @deffn {Config Command} {ft2232_latency} ms
2615 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2616 ft2232_read() fails to return the expected number of bytes. This can be caused by
2617 USB communication delays and has proved hard to reproduce and debug. Setting the
2618 FT2232 latency timer to a larger value increases delays for short USB packets but it
2619 also reduces the risk of timeouts before receiving the expected number of bytes.
2620 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2621 @end deffn
2623 @deffn {Config Command} {ft2232_channel} channel
2624 Used to select the channel of the ft2232 chip to use (between 1 and 4).
2625 The default value is 1.
2626 @end deffn
2628 For example, the interface config file for a
2629 Turtelizer JTAG Adapter looks something like this:
2631 @example
2632 interface ft2232
2633 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2634 ft2232_layout turtelizer2
2635 ft2232_vid_pid 0x0403 0xbdc8
2636 @end example
2637 @end deffn
2639 @deffn {Interface Driver} {ftdi}
2640 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2641 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2642 It is a complete rewrite to address a large number of problems with the ft2232
2643 interface driver.
2645 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2646 bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
2647 consistently faster than the ft2232 driver, sometimes several times faster.
2649 A major improvement of this driver is that support for new FTDI based adapters
2650 can be added competely through configuration files, without the need to patch
2651 and rebuild OpenOCD.
2653 The driver uses a signal abstraction to enable Tcl configuration files to
2654 define outputs for one or several FTDI GPIO. These outputs can then be
2655 controlled using the @command{ftdi_set_signal} command. Special signal names
2656 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2657 will be used for their customary purpose.
2659 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2660 be controlled differently. In order to support tristateable signals such as
2661 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2662 signal. The following output buffer configurations are supported:
2664 @itemize @minus
2665 @item Push-pull with one FTDI output as (non-)inverted data line
2666 @item Open drain with one FTDI output as (non-)inverted output-enable
2667 @item Tristate with one FTDI output as (non-)inverted data line and another
2668 FTDI output as (non-)inverted output-enable
2669 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2670 switching data and direction as necessary
2671 @end itemize
2673 These interfaces have several commands, used to configure the driver
2674 before initializing the JTAG scan chain:
2676 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2677 The vendor ID and product ID of the adapter. If not specified, the FTDI
2678 default values are used.
2679 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2680 @example
2681 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2682 @end example
2683 @end deffn
2685 @deffn {Config Command} {ftdi_device_desc} description
2686 Provides the USB device description (the @emph{iProduct string})
2687 of the adapter. If not specified, the device description is ignored
2688 during device selection.
2689 @end deffn
2691 @deffn {Config Command} {ftdi_serial} serial-number
2692 Specifies the @var{serial-number} of the adapter to use,
2693 in case the vendor provides unique IDs and more than one adapter
2694 is connected to the host.
2695 If not specified, serial numbers are not considered.
2696 (Note that USB serial numbers can be arbitrary Unicode strings,
2697 and are not restricted to containing only decimal digits.)
2698 @end deffn
2700 @deffn {Config Command} {ftdi_channel} channel
2701 Selects the channel of the FTDI device to use for MPSSE operations. Most
2702 adapters use the default, channel 0, but there are exceptions.
2703 @end deffn
2705 @deffn {Config Command} {ftdi_layout_init} data direction
2706 Specifies the initial values of the FTDI GPIO data and direction registers.
2707 Each value is a 16-bit number corresponding to the concatenation of the high
2708 and low FTDI GPIO registers. The values should be selected based on the
2709 schematics of the adapter, such that all signals are set to safe levels with
2710 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2711 and initially asserted reset signals.
2712 @end deffn
2714 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask]
2715 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2716 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2717 register bitmasks to tell the driver the connection and type of the output
2718 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2719 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2720 used with inverting data inputs and @option{-data} with non-inverting inputs.
2721 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2722 not-output-enable) input to the output buffer is connected.
2724 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2725 simple open-collector transistor driver would be specified with @option{-oe}
2726 only. In that case the signal can only be set to drive low or to Hi-Z and the
2727 driver will complain if the signal is set to drive high. Which means that if
2728 it's a reset signal, @command{reset_config} must be specified as
2729 @option{srst_open_drain}, not @option{srst_push_pull}.
2731 A special case is provided when @option{-data} and @option{-oe} is set to the
2732 same bitmask. Then the FTDI pin is considered being connected straight to the
2733 target without any buffer. The FTDI pin is then switched between output and
2734 input as necessary to provide the full set of low, high and Hi-Z
2735 characteristics. In all other cases, the pins specified in a signal definition
2736 are always driven by the FTDI.
2737 @end deffn
2739 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2740 Set a previously defined signal to the specified level.
2741 @itemize @minus
2742 @item @option{0}, drive low
2743 @item @option{1}, drive high
2744 @item @option{z}, set to high-impedance
2745 @end itemize
2746 @end deffn
2748 For example adapter definitions, see the configuration files shipped in the
2749 @file{interface/ftdi} directory.
2750 @end deffn
2752 @deffn {Interface Driver} {remote_bitbang}
2753 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2754 with a remote process and sends ASCII encoded bitbang requests to that process
2755 instead of directly driving JTAG.
2757 The remote_bitbang driver is useful for debugging software running on
2758 processors which are being simulated.
2760 @deffn {Config Command} {remote_bitbang_port} number
2761 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2762 sockets instead of TCP.
2763 @end deffn
2765 @deffn {Config Command} {remote_bitbang_host} hostname
2766 Specifies the hostname of the remote process to connect to using TCP, or the
2767 name of the UNIX socket to use if remote_bitbang_port is 0.
2768 @end deffn
2770 For example, to connect remotely via TCP to the host foobar you might have
2771 something like:
2773 @example
2774 interface remote_bitbang
2775 remote_bitbang_port 3335
2776 remote_bitbang_host foobar
2777 @end example
2779 To connect to another process running locally via UNIX sockets with socket
2780 named mysocket:
2782 @example
2783 interface remote_bitbang
2784 remote_bitbang_port 0
2785 remote_bitbang_host mysocket
2786 @end example
2787 @end deffn
2789 @deffn {Interface Driver} {usb_blaster}
2790 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2791 for FTDI chips. These interfaces have several commands, used to
2792 configure the driver before initializing the JTAG scan chain:
2794 @deffn {Config Command} {usb_blaster_device_desc} description
2795 Provides the USB device description (the @emph{iProduct string})
2796 of the FTDI FT245 device. If not
2797 specified, the FTDI default value is used. This setting is only valid
2798 if compiled with FTD2XX support.
2799 @end deffn
2801 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2802 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2803 default values are used.
2804 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2805 Altera USB-Blaster (default):
2806 @example
2807 usb_blaster_vid_pid 0x09FB 0x6001
2808 @end example
2809 The following VID/PID is for Kolja Waschk's USB JTAG:
2810 @example
2811 usb_blaster_vid_pid 0x16C0 0x06AD
2812 @end example
2813 @end deffn
2815 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2816 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2817 female JTAG header). These pins can be used as SRST and/or TRST provided the
2818 appropriate connections are made on the target board.
2820 For example, to use pin 6 as SRST (as with an AVR board):
2821 @example
2822 $_TARGETNAME configure -event reset-assert \
2823 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2824 @end example
2825 @end deffn
2827 @end deffn
2829 @deffn {Interface Driver} {gw16012}
2830 Gateworks GW16012 JTAG programmer.
2831 This has one driver-specific command:
2833 @deffn {Config Command} {parport_port} [port_number]
2834 Display either the address of the I/O port
2835 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2836 If a parameter is provided, first switch to use that port.
2837 This is a write-once setting.
2838 @end deffn
2839 @end deffn
2841 @deffn {Interface Driver} {jlink}
2842 Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
2844 @quotation Compatibility Note
2845 Segger released many firmware versions for the many harware versions they
2846 produced. OpenOCD was extensively tested and intended to run on all of them,
2847 but some combinations were reported as incompatible. As a general
2848 recommendation, it is advisable to use the latest firmware version
2849 available for each hardware version. However the current V8 is a moving
2850 target, and Segger firmware versions released after the OpenOCD was
2851 released may not be compatible. In such cases it is recommended to
2852 revert to the last known functional version. For 0.5.0, this is from
2853 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2854 version is from "May 3 2012 18:36:22", packed with 4.46f.
2855 @end quotation
2857 @deffn {Command} {jlink caps}
2858 Display the device firmware capabilities.
2859 @end deffn
2860 @deffn {Command} {jlink info}
2861 Display various device information, like hardware version, firmware version, current bus status.
2862 @end deffn
2863 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2864 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2865 @end deffn
2866 @deffn {Command} {jlink config}
2867 Display the J-Link configuration.
2868 @end deffn
2869 @deffn {Command} {jlink config kickstart} [val]
2870 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2871 @end deffn
2872 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2873 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2874 @end deffn
2875 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2876 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2877 E the bit of the subnet mask and
2878 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2879 @end deffn
2880 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2881 Set the USB address; this will also change the product id. Without argument, show the USB address.
2882 @end deffn
2883 @deffn {Command} {jlink config reset}
2884 Reset the current configuration.
2885 @end deffn
2886 @deffn {Command} {jlink config save}
2887 Save the current configuration to the internal persistent storage.
2888 @end deffn
2889 @deffn {Config} {jlink pid} val
2890 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2891 @end deffn
2892 @end deffn
2894 @deffn {Interface Driver} {parport}
2895 Supports PC parallel port bit-banging cables:
2896 Wigglers, PLD download cable, and more.
2897 These interfaces have several commands, used to configure the driver
2898 before initializing the JTAG scan chain:
2900 @deffn {Config Command} {parport_cable} name
2901 Set the layout of the parallel port cable used to connect to the target.
2902 This is a write-once setting.
2903 Currently valid cable @var{name} values include:
2905 @itemize @minus
2906 @item @b{altium} Altium Universal JTAG cable.
2907 @item @b{arm-jtag} Same as original wiggler except SRST and
2908 TRST connections reversed and TRST is also inverted.
2909 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2910 in configuration mode. This is only used to
2911 program the Chameleon itself, not a connected target.
2912 @item @b{dlc5} The Xilinx Parallel cable III.
2913 @item @b{flashlink} The ST Parallel cable.
2914 @item @b{lattice} Lattice ispDOWNLOAD Cable
2915 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2916 some versions of
2917 Amontec's Chameleon Programmer. The new version available from
2918 the website uses the original Wiggler layout ('@var{wiggler}')
2919 @item @b{triton} The parallel port adapter found on the
2920 ``Karo Triton 1 Development Board''.
2921 This is also the layout used by the HollyGates design
2922 (see @uref{}).
2923 @item @b{wiggler} The original Wiggler layout, also supported by
2924 several clones, such as the Olimex ARM-JTAG
2925 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2926 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2927 @end itemize
2928 @end deffn
2930 @deffn {Config Command} {parport_port} [port_number]
2931 Display either the address of the I/O port
2932 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2933 If a parameter is provided, first switch to use that port.
2934 This is a write-once setting.
2936 When using PPDEV to access the parallel port, use the number of the parallel port:
2937 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2938 you may encounter a problem.
2939 @end deffn
2941 @deffn Command {parport_toggling_time} [nanoseconds]
2942 Displays how many nanoseconds the hardware needs to toggle TCK;
2943 the parport driver uses this value to obey the
2944 @command{adapter_khz} configuration.
2945 When the optional @var{nanoseconds} parameter is given,
2946 that setting is changed before displaying the current value.
2948 The default setting should work reasonably well on commodity PC hardware.
2949 However, you may want to calibrate for your specific hardware.
2950 @quotation Tip
2951 To measure the toggling time with a logic analyzer or a digital storage
2952 oscilloscope, follow the procedure below:
2953 @example
2954 > parport_toggling_time 1000
2955 > adapter_khz 500
2956 @end example
2957 This sets the maximum JTAG clock speed of the hardware, but
2958 the actual speed probably deviates from the requested 500 kHz.
2959 Now, measure the time between the two closest spaced TCK transitions.
2960 You can use @command{runtest 1000} or something similar to generate a
2961 large set of samples.
2962 Update the setting to match your measurement:
2963 @example
2964 > parport_toggling_time <measured nanoseconds>
2965 @end example
2966 Now the clock speed will be a better match for @command{adapter_khz rate}
2967 commands given in OpenOCD scripts and event handlers.
2969 You can do something similar with many digital multimeters, but note
2970 that you'll probably need to run the clock continuously for several
2971 seconds before it decides what clock rate to show. Adjust the
2972 toggling time up or down until the measured clock rate is a good
2973 match for the adapter_khz rate you specified; be conservative.
2974 @end quotation
2975 @end deffn
2977 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2978 This will configure the parallel driver to write a known
2979 cable-specific value to the parallel interface on exiting OpenOCD.
2980 @end deffn
2982 For example, the interface configuration file for a
2983 classic ``Wiggler'' cable on LPT2 might look something like this:
2985 @example
2986 interface parport
2987 parport_port 0x278
2988 parport_cable wiggler
2989 @end example
2990 @end deffn
2992 @deffn {Interface Driver} {presto}
2993 ASIX PRESTO USB JTAG programmer.
2994 @deffn {Config Command} {presto_serial} serial_string
2995 Configures the USB serial number of the Presto device to use.
2996 @end deffn
2997 @end deffn
2999 @deffn {Interface Driver} {rlink}
3000 Raisonance RLink USB adapter
3001 @end deffn
3003 @deffn {Interface Driver} {usbprog}
3004 usbprog is a freely programmable USB adapter.
3005 @end deffn
3007 @deffn {Interface Driver} {vsllink}
3008 vsllink is part of Versaloon which is a versatile USB programmer.
3010 @quotation Note
3011 This defines quite a few driver-specific commands,
3012 which are not currently documented here.
3013 @end quotation
3014 @end deffn
3016 @deffn {Interface Driver} {hla}
3017 This is a driver that supports multiple High Level Adapters.
3018 This type of adapter does not expose some of the lower level api's
3019 that OpenOCD would normally use to access the target.
3021 Currently supported adapters include the ST STLINK and TI ICDI.
3023 @deffn {Config Command} {hla_device_desc} description
3024 Currently Not Supported.
3025 @end deffn
3027 @deffn {Config Command} {hla_serial} serial
3028 Currently Not Supported.
3029 @end deffn
3031 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
3032 Specifies the adapter layout to use.
3033 @end deffn
3035 @deffn {Config Command} {hla_vid_pid} vid pid
3036 The vendor ID and product ID of the device.
3037 @end deffn
3039 @deffn {Config Command} {stlink_api} api_level
3040 Manually sets the stlink api used, valid options are 1 or 2. (@b{STLINK Only}).
3041 @end deffn
3043 @deffn {Config Command} {trace} output_file_path source_clock_hz
3044 Enable SWO tracing (if supported), trace data is appended to the specified
3045 output file and the file is created if it does not exist. The source clock
3046 rate for the trace port must be specified, this is typically the CPU clock
3047 rate.
3048 @end deffn
3049 @end deffn
3051 @deffn {Interface Driver} {opendous}
3052 opendous-jtag is a freely programmable USB adapter.
3053 @end deffn
3055 @deffn {Interface Driver} {ulink}
3056 This is the Keil ULINK v1 JTAG debugger.
3057 @end deffn
3059 @deffn {Interface Driver} {ZY1000}
3060 This is the Zylin ZY1000 JTAG debugger.
3061 @end deffn
3063 @quotation Note
3064 This defines some driver-specific commands,
3065 which are not currently documented here.
3066 @end quotation
3068 @deffn Command power [@option{on}|@option{off}]
3069 Turn power switch to target on/off.
3070 No arguments: print status.
3071 @end deffn
3073 @deffn {Interface Driver} {bcm2835gpio}
3074 This SoC is present in Raspberry Pi which is a cheap single-board computer
3075 exposing some GPIOs on its expansion header.
3077 The driver accesses memory-mapped GPIO peripheral registers directly
3078 for maximum performance, but the only possible race condition is for
3079 the pins' modes/muxing (which is highly unlikely), so it should be
3080 able to coexist nicely with both sysfs bitbanging and various
3081 peripherals' kernel drivers. The driver restores the previous
3082 configuration on exit.
3084 See @file{interface/raspberrypi-native.cfg} for a sample config and
3085 pinout.
3087 @end deffn
3089 @section Transport Configuration
3090 @cindex Transport
3091 As noted earlier, depending on the version of OpenOCD you use,
3092 and the debug adapter you are using,
3093 several transports may be available to
3094 communicate with debug targets (or perhaps to program flash memory).
3095 @deffn Command {transport list}
3096 displays the names of the transports supported by this
3097 version of OpenOCD.
3098 @end deffn
3100 @deffn Command {transport select} transport_name
3101 Select which of the supported transports to use in this OpenOCD session.
3102 The transport must be supported by the debug adapter hardware and by the
3103 version of OpenOCD you are using (including the adapter's driver).
3104 No arguments: returns name of session's selected transport.
3105 @end deffn
3107 @subsection JTAG Transport
3108 @cindex JTAG
3109 JTAG is the original transport supported by OpenOCD, and most
3110 of the OpenOCD commands support it.
3111 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3112 each of which must be explicitly declared.
3113 JTAG supports both debugging and boundary scan testing.
3114 Flash programming support is built on top of debug support.
3115 @subsection SWD Transport
3116 @cindex SWD
3117 @cindex Serial Wire Debug
3118 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3119 Debug Access Point (DAP, which must be explicitly declared.
3120 (SWD uses fewer signal wires than JTAG.)
3121 SWD is debug-oriented, and does not support boundary scan testing.
3122 Flash programming support is built on top of debug support.
3123 (Some processors support both JTAG and SWD.)
3124 @deffn Command {swd newdap} ...
3125 Declares a single DAP which uses SWD transport.
3126 Parameters are currently the same as "jtag newtap" but this is
3127 expected to change.
3128 @end deffn
3129 @deffn Command {swd wcr trn prescale}
3130 Updates TRN (turnaraound delay) and prescaling.fields of the
3131 Wire Control Register (WCR).
3132 No parameters: displays current settings.
3133 @end deffn
3135 @subsection SPI Transport
3136 @cindex SPI
3137 @cindex Serial Peripheral Interface
3138 The Serial Peripheral Interface (SPI) is a general purpose transport
3139 which uses four wire signaling. Some processors use it as part of a
3140 solution for flash programming.
3142 @anchor{jtagspeed}
3143 @section JTAG Speed
3144 JTAG clock setup is part of system setup.
3145 It @emph{does not belong with interface setup} since any interface
3146 only knows a few of the constraints for the JTAG clock speed.
3147 Sometimes the JTAG speed is
3148 changed during the target initialization process: (1) slow at
3149 reset, (2) program the CPU clocks, (3) run fast.
3150 Both the "slow" and "fast" clock rates are functions of the
3151 oscillators used, the chip, the board design, and sometimes
3152 power management software that may be active.
3154 The speed used during reset, and the scan chain verification which
3155 follows reset, can be adjusted using a @code{reset-start}
3156 target event handler.
3157 It can then be reconfigured to a faster speed by a
3158 @code{reset-init} target event handler after it reprograms those
3159 CPU clocks, or manually (if something else, such as a boot loader,
3160 sets up those clocks).
3161 @xref{targetevents,,Target Events}.
3162 When the initial low JTAG speed is a chip characteristic, perhaps
3163 because of a required oscillator speed, provide such a handler
3164 in the target config file.
3165 When that speed is a function of a board-specific characteristic
3166 such as which speed oscillator is used, it belongs in the board
3167 config file instead.
3168 In both cases it's safest to also set the initial JTAG clock rate
3169 to that same slow speed, so that OpenOCD never starts up using a
3170 clock speed that's faster than the scan chain can support.
3172 @example
3173 jtag_rclk 3000
3174 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3175 @end example
3177 If your system supports adaptive clocking (RTCK), configuring
3178 JTAG to use that is probably the most robust approach.
3179 However, it introduces delays to synchronize clocks; so it
3180 may not be the fastest solution.
3182 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3183 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3184 which support adaptive clocking.
3186 @deffn {Command} adapter_khz max_speed_kHz
3187 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3188 JTAG interfaces usually support a limited number of
3189 speeds. The speed actually used won't be faster
3190 than the speed specified.
3192 Chip data sheets generally include a top JTAG clock rate.
3193 The actual rate is often a function of a CPU core clock,
3194 and is normally less than that peak rate.
3195 For example, most ARM cores accept at most one sixth of the CPU clock.
3197 Speed 0 (khz) selects RTCK method.
3198 @xref{faqrtck,,FAQ RTCK}.
3199 If your system uses RTCK, you won't need to change the
3200 JTAG clocking after setup.
3201 Not all interfaces, boards, or targets support ``rtck''.
3202 If the interface device can not
3203 support it, an error is returned when you try to use RTCK.
3204 @end deffn
3206 @defun jtag_rclk fallback_speed_kHz
3207 @cindex adaptive clocking
3208 @cindex RTCK
3209 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3210 If that fails (maybe the interface, board, or target doesn't
3211 support it), falls back to the specified frequency.
3212 @example
3213 # Fall back to 3mhz if RTCK is not supported
3214 jtag_rclk 3000
3215 @end example
3216 @end defun
3218 @node Reset Configuration
3219 @chapter Reset Configuration
3220 @cindex Reset Configuration
3222 Every system configuration may require a different reset
3223 configuration. This can also be quite confusing.
3224 Resets also interact with @var{reset-init} event handlers,
3225 which do things like setting up clocks and DRAM, and
3226 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3227 They can also interact with JTAG routers.
3228 Please see the various board files for examples.
3230 @quotation Note
3231 To maintainers and integrators:
3232 Reset configuration touches several things at once.
3233 Normally the board configuration file
3234 should define it and assume that the JTAG adapter supports
3235 everything that's wired up to the board's JTAG connector.
3237 However, the target configuration file could also make note
3238 of something the silicon vendor has done inside the chip,
3239 which will be true for most (or all) boards using that chip.
3240 And when the JTAG adapter doesn't support everything, the
3241 user configuration file will need to override parts of
3242 the reset configuration provided by other files.
3243 @end quotation
3245 @section Types of Reset
3247 There are many kinds of reset possible through JTAG, but
3248 they may not all work with a given board and adapter.
3249 That's part of why reset configuration can be error prone.
3251 @itemize @bullet
3252 @item
3253 @emph{System Reset} ... the @emph{SRST} hardware signal
3254 resets all chips connected to the JTAG adapter, such as processors,
3255 power management chips, and I/O controllers. Normally resets triggered
3256 with this signal behave exactly like pressing a RESET button.
3257 @item
3258 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3259 just the TAP controllers connected to the JTAG adapter.
3260 Such resets should not be visible to the rest of the system; resetting a
3261 device's TAP controller just puts that controller into a known state.
3262 @item
3263 @emph{Emulation Reset} ... many devices can be reset through JTAG
3264 commands. These resets are often distinguishable from system
3265 resets, either explicitly (a "reset reason" register says so)
3266 or implicitly (not all parts of the chip get reset).
3267 @item
3268 @emph{Other Resets} ... system-on-chip devices often support
3269 several other types of reset.
3270 You may need to arrange that a watchdog timer stops
3271 while debugging, preventing a watchdog reset.
3272 There may be individual module resets.
3273 @end itemize
3275 In the best case, OpenOCD can hold SRST, then reset
3276 the TAPs via TRST and send commands through JTAG to halt the
3277 CPU at the reset vector before the 1st instruction is executed.
3278 Then when it finally releases the SRST signal, the system is
3279 halted under debugger control before any code has executed.
3280 This is the behavior required to support the @command{reset halt}
3281 and @command{reset init} commands; after @command{reset init} a
3282 board-specific script might do things like setting up DRAM.
3283 (@xref{resetcommand,,Reset Command}.)
3285 @anchor{srstandtrstissues}
3286 @section SRST and TRST Issues
3288 Because SRST and TRST are hardware signals, they can have a
3289 variety of system-specific constraints. Some of the most
3290 common issues are:
3292 @itemize @bullet
3294 @item @emph{Signal not available} ... Some boards don't wire
3295 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3296 support such signals even if they are wired up.
3297 Use the @command{reset_config} @var{signals} options to say
3298 when either of those signals is not connected.
3299 When SRST is not available, your code might not be able to rely
3300 on controllers having been fully reset during code startup.
3301 Missing TRST is not a problem, since JTAG-level resets can
3302 be triggered using with TMS signaling.
3304 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3305 adapter will connect SRST to TRST, instead of keeping them separate.
3306 Use the @command{reset_config} @var{combination} options to say
3307 when those signals aren't properly independent.
3309 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3310 delay circuit, reset supervisor, or on-chip features can extend
3311 the effect of a JTAG adapter's reset for some time after the adapter
3312 stops issuing the reset. For example, there may be chip or board
3313 requirements that all reset pulses last for at least a
3314 certain amount of time; and reset buttons commonly have
3315 hardware debouncing.
3316 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3317 commands to say when extra delays are needed.
3319 @item @emph{Drive type} ... Reset lines often have a pullup
3320 resistor, letting the JTAG interface treat them as open-drain
3321 signals. But that's not a requirement, so the adapter may need
3322 to use push/pull output drivers.
3323 Also, with weak pullups it may be advisable to drive
3324 signals to both levels (push/pull) to minimize rise times.
3325 Use the @command{reset_config} @var{trst_type} and
3326 @var{srst_type} parameters to say how to drive reset signals.
3328 @item @emph{Special initialization} ... Targets sometimes need
3329 special JTAG initialization sequences to handle chip-specific
3330 issues (not limited to errata).
3331 For example, certain JTAG commands might need to be issued while
3332 the system as a whole is in a reset state (SRST active)
3333 but the JTAG scan chain is usable (TRST inactive).
3334 Many systems treat combined assertion of SRST and TRST as a
3335 trigger for a harder reset than SRST alone.
3336 Such custom reset handling is discussed later in this chapter.
3337 @end itemize
3339 There can also be other issues.
3340 Some devices don't fully conform to the JTAG specifications.
3341 Trivial system-specific differences are common, such as
3342 SRST and TRST using slightly different names.
3343 There are also vendors who distribute key JTAG documentation for
3344 their chips only to developers who have signed a Non-Disclosure
3345 Agreement (NDA).
3347 Sometimes there are chip-specific extensions like a requirement to use
3348 the normally-optional TRST signal (precluding use of JTAG adapters which
3349 don't pass TRST through), or needing extra steps to complete a TAP reset.
3351 In short, SRST and especially TRST handling may be very finicky,
3352 needing to cope with both architecture and board specific constraints.
3354 @section Commands for Handling Resets
3356 @deffn {Command} adapter_nsrst_assert_width milliseconds
3357 Minimum amount of time (in milliseconds) OpenOCD should wait
3358 after asserting nSRST (active-low system reset) before
3359 allowing it to be deasserted.
3360 @end deffn
3362 @deffn {Command} adapter_nsrst_delay milliseconds
3363 How long (in milliseconds) OpenOCD should wait after deasserting
3364 nSRST (active-low system reset) before starting new JTAG operations.
3365 When a board has a reset button connected to SRST line it will
3366 probably have hardware debouncing, implying you should use this.
3367 @end deffn
3369 @deffn {Command} jtag_ntrst_assert_width milliseconds
3370 Minimum amount of time (in milliseconds) OpenOCD should wait
3371 after asserting nTRST (active-low JTAG TAP reset) before
3372 allowing it to be deasserted.
3373 @end deffn
3375 @deffn {Command} jtag_ntrst_delay milliseconds
3376 How long (in milliseconds) OpenOCD should wait after deasserting
3377 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3378 @end deffn
3380 @deffn {Command} reset_config mode_flag ...
3381 This command displays or modifies the reset configuration
3382 of your combination of JTAG board and target in target
3383 configuration scripts.
3385 Information earlier in this section describes the kind of problems
3386 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3387 As a rule this command belongs only in board config files,
3388 describing issues like @emph{board doesn't connect TRST};
3389 or in user config files, addressing limitations derived
3390 from a particular combination of interface and board.
3391 (An unlikely example would be using a TRST-only adapter
3392 with a board that only wires up SRST.)
3394 The @var{mode_flag} options can be specified in any order, but only one
3395 of each type -- @var{signals}, @var{combination}, @var{gates},
3396 @var{trst_type}, @var{srst_type} and @var{connect_type}
3397 -- may be specified at a time.
3398 If you don't provide a new value for a given type, its previous
3399 value (perhaps the default) is unchanged.
3400 For example, this means that you don't need to say anything at all about
3401 TRST just to declare that if the JTAG adapter should want to drive SRST,
3402 it must explicitly be driven high (@option{srst_push_pull}).
3404 @itemize
3405 @item
3406 @var{signals} can specify which of the reset signals are connected.
3407 For example, If the JTAG interface provides SRST, but the board doesn't
3408 connect that signal properly, then OpenOCD can't use it.
3409 Possible values are @option{none} (the default), @option{trst_only},
3410 @option{srst_only} and @option{trst_and_srst}.
3412 @quotation Tip
3413 If your board provides SRST and/or TRST through the JTAG connector,
3414 you must declare that so those signals can be used.
3415 @end quotation
3417 @item
3418 The @var{combination} is an optional value specifying broken reset
3419 signal implementations.
3420 The default behaviour if no option given is @option{separate},
3421 indicating everything behaves normally.
3422 @option{srst_pulls_trst} states that the
3423 test logic is reset together with the reset of the system (e.g. NXP
3424 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3425 the system is reset together with the test logic (only hypothetical, I
3426 haven't seen hardware with such a bug, and can be worked around).
3427 @option{combined} implies both @option{srst_pulls_trst} and
3428 @option{trst_pulls_srst}.
3430 @item
3431 The @var{gates} tokens control flags that describe some cases where
3432 JTAG may be unvailable during reset.
3433 @option{srst_gates_jtag} (default)
3434 indicates that asserting SRST gates the
3435 JTAG clock. This means that no communication can happen on JTAG
3436 while SRST is asserted.
3437 Its converse is @option{srst_nogate}, indicating that JTAG commands
3438 can safely be issued while SRST is active.
3440 @item
3441 The @var{connect_type} tokens control flags that describe some cases where
3442 SRST is asserted while connecting to the target. @option{srst_nogate}
3443 is required to use this option.
3444 @option{connect_deassert_srst} (default)
3445 indicates that SRST will not be asserted while connecting to the target.
3446 Its converse is @option{connect_assert_srst}, indicating that SRST will
3447 be asserted before any target connection.
3448 Only some targets support this feature, STM32 and STR9 are examples.
3449 This feature is useful if you are unable to connect to your target due
3450 to incorrect options byte config or illegal program execution.
3451 @end itemize
3453 The optional @var{trst_type} and @var{srst_type} parameters allow the
3454 driver mode of each reset line to be specified. These values only affect
3455 JTAG interfaces with support for different driver modes, like the Amontec
3456 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3457 relevant signal (TRST or SRST) is not connected.
3459 @itemize
3460 @item
3461 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3462 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3463 Most boards connect this signal to a pulldown, so the JTAG TAPs
3464 never leave reset unless they are hooked up to a JTAG adapter.
3466 @item
3467 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3468 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3469 Most boards connect this signal to a pullup, and allow the
3470 signal to be pulled low by various events including system
3471 powerup and pressing a reset button.
3472 @end itemize
3473 @end deffn
3475 @section Custom Reset Handling
3476 @cindex events
3478 OpenOCD has several ways to help support the various reset
3479 mechanisms provided by chip and board vendors.
3480 The commands shown in the previous section give standard parameters.
3481 There are also @emph{event handlers} associated with TAPs or Targets.
3482 Those handlers are Tcl procedures you can provide, which are invoked
3483 at particular points in the reset sequence.
3485 @emph{When SRST is not an option} you must set
3486 up a @code{reset-assert} event handler for your target.
3487 For example, some JTAG adapters don't include the SRST signal;
3488 and some boards have multiple targets, and you won't always
3489 want to reset everything at once.
3491 After configuring those mechanisms, you might still
3492 find your board doesn't start up or reset correctly.
3493 For example, maybe it needs a slightly different sequence
3494 of SRST and/or TRST manipulations, because of quirks that
3495 the @command{reset_config} mechanism doesn't address;
3496 or asserting both might trigger a stronger reset, which
3497 needs special attention.
3499 Experiment with lower level operations, such as @command{jtag_reset}
3500 and the @command{jtag arp_*} operations shown here,
3501 to find a sequence of operations that works.
3502 @xref{JTAG Commands}.
3503 When you find a working sequence, it can be used to override
3504 @command{jtag_init}, which fires during OpenOCD startup
3505 (@pxref{configurationstage,,Configuration Stage});
3506 or @command{init_reset}, which fires during reset processing.
3508 You might also want to provide some project-specific reset
3509 schemes. For example, on a multi-target board the standard
3510 @command{reset} command would reset all targets, but you
3511 may need the ability to reset only one target at time and
3512 thus want to avoid using the board-wide SRST signal.
3514 @deffn {Overridable Procedure} init_reset mode
3515 This is invoked near the beginning of the @command{reset} command,
3516 usually to provide as much of a cold (power-up) reset as practical.
3517 By default it is also invoked from @command{jtag_init} if
3518 the scan chain does not respond to pure JTAG operations.
3519 The @var{mode} parameter is the parameter given to the
3520 low level reset command (@option{halt},
3521 @option{init}, or @option{run}), @option{setup},
3522 or potentially some other value.
3524 The default implementation just invokes @command{jtag arp_init-reset}.
3525 Replacements will normally build on low level JTAG
3526 operations such as @command{jtag_reset}.
3527 Operations here must not address individual TAPs
3528 (or their associated targets)
3529 until the JTAG scan chain has first been verified to work.
3531 Implementations must have verified the JTAG scan chain before
3532 they return.
3533 This is done by calling @command{jtag arp_init}
3534 (or @command{jtag arp_init-reset}).
3535 @end deffn
3537 @deffn Command {jtag arp_init}
3538 This validates the scan chain using just the four
3539 standard JTAG signals (TMS, TCK, TDI, TDO).
3540 It starts by issuing a JTAG-only reset.
3541 Then it performs checks to verify that the scan chain configuration
3542 matches the TAPs it can observe.
3543 Those checks include checking IDCODE values for each active TAP,
3544 and verifying the length of their instruction registers using
3545 TAP @code{-ircapture} and @code{-irmask} values.
3546 If these tests all pass, TAP @code{setup} events are
3547 issued to all TAPs with handlers for that event.
3548 @end deffn
3550 @deffn Command {jtag arp_init-reset}
3551 This uses TRST and SRST to try resetting
3552 everything on the JTAG scan chain
3553 (and anything else connected to SRST).
3554 It then invokes the logic of @command{jtag arp_init}.
3555 @end deffn
3558 @node TAP Declaration
3559 @chapter TAP Declaration
3560 @cindex TAP declaration
3561 @cindex TAP configuration
3563 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3564 TAPs serve many roles, including:
3566 @itemize @bullet
3567 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
3568 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
3569 Others do it indirectly, making a CPU do it.
3570 @item @b{Program Download} Using the same CPU support GDB uses,
3571 you can initialize a DRAM controller, download code to DRAM, and then
3572 start running that code.
3573 @item @b{Boundary Scan} Most chips support boundary scan, which
3574 helps test for board assembly problems like solder bridges
3575 and missing connections
3576 @end itemize
3578 OpenOCD must know about the active TAPs on your board(s).
3579 Setting up the TAPs is the core task of your configuration files.
3580 Once those TAPs are set up, you can pass their names to code
3581 which sets up CPUs and exports them as GDB targets,
3582 probes flash memory, performs low-level JTAG operations, and more.
3584 @section Scan Chains
3585 @cindex scan chain
3587 TAPs are part of a hardware @dfn{scan chain},
3588 which is daisy chain of TAPs.
3589 They also need to be added to
3590 OpenOCD's software mirror of that hardware list,
3591 giving each member a name and associating other data with it.
3592 Simple scan chains, with a single TAP, are common in
3593 systems with a single microcontroller or microprocessor.
3594 More complex chips may have several TAPs internally.
3595 Very complex scan chains might have a dozen or more TAPs:
3596 several in one chip, more in the next, and connecting
3597 to other boards with their own chips and TAPs.
3599 You can display the list with the @command{scan_chain} command.
3600 (Don't confuse this with the list displayed by the @command{targets}
3601 command, presented in the next chapter.
3602 That only displays TAPs for CPUs which are configured as
3603 debugging targets.)
3604 Here's what the scan chain might look like for a chip more than one TAP:
3606 @verbatim
3607 TapName Enabled IdCode Expected IrLen IrCap IrMask
3608 -- ------------------ ------- ---------- ---------- ----- ----- ------
3609 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3610 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3611 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3612 @end verbatim
3614 OpenOCD can detect some of that information, but not all
3615 of it. @xref{autoprobing,,Autoprobing}.
3616 Unfortunately those TAPs can't always be autoconfigured,
3617 because not all devices provide good support for that.
3618 JTAG doesn't require supporting IDCODE instructions, and
3619 chips with JTAG routers may not link TAPs into the chain
3620 until they are told to do so.
3622 The configuration mechanism currently supported by OpenOCD
3623 requires explicit configuration of all TAP devices using
3624 @command{jtag newtap} commands, as detailed later in this chapter.
3625 A command like this would declare one tap and name it @code{chip1.cpu}:
3627 @example
3628 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3629 @end example
3631 Each target configuration file lists the TAPs provided
3632 by a given chip.
3633 Board configuration files combine all the targets on a board,
3634 and so forth.
3635 Note that @emph{the order in which TAPs are declared is very important.}
3636 It must match the order in the JTAG scan chain, both inside
3637 a single chip and between them.
3638 @xref{faqtaporder,,FAQ TAP Order}.
3640 For example, the ST Microsystems STR912 chip has
3641 three separate TAPs@footnote{See the ST
3642 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3643 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3644 @url{}}.
3645 To configure those taps, @file{target/str912.cfg}
3646 includes commands something like this:
3648 @example
3649 jtag newtap str912 flash ... params ...
3650 jtag newtap str912 cpu ... params ...
3651 jtag newtap str912 bs ... params ...
3652 @end example
3654 Actual config files use a variable instead of literals like
3655 @option{str912}, to support more than one chip of each type.
3656 @xref{Config File Guidelines}.
3658 @deffn Command {jtag names}
3659 Returns the names of all current TAPs in the scan chain.
3660 Use @command{jtag cget} or @command{jtag tapisenabled}
3661 to examine attributes and state of each TAP.
3662 @example
3663 foreach t [jtag names] @{
3664 puts [format "TAP: %s\n" $t]
3665 @}
3666 @end example
3667 @end deffn
3669 @deffn Command {scan_chain}
3670 Displays the TAPs in the scan chain configuration,
3671 and their status.
3672 The set of TAPs listed by this command is fixed by
3673 exiting the OpenOCD configuration stage,
3674 but systems with a JTAG router can
3675 enable or disable TAPs dynamically.
3676 @end deffn
3678 @c FIXME! "jtag cget" should be able to return all TAP
3679 @c attributes, like "$target_name cget" does for targets.
3681 @c Probably want "jtag eventlist", and a "tap-reset" event
3682 @c (on entry to RESET state).
3684 @section TAP Names
3685 @cindex dotted name
3687 When TAP objects are declared with @command{jtag newtap},
3688 a @dfn{} is created for the TAP, combining the
3689 name of a module (usually a chip) and a label for the TAP.
3690 For example: @code{xilinx.tap}, @code{str912.flash},
3691 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3692 Many other commands use that to manipulate or
3693 refer to the TAP. For example, CPU configuration uses the
3694 name, as does declaration of NAND or NOR flash banks.
3696 The components of a dotted name should follow ``C'' symbol
3697 name rules: start with an alphabetic character, then numbers
3698 and underscores are OK; while others (including dots!) are not.
3700 @quotation Tip
3701 In older code, JTAG TAPs were numbered from 0..N.
3702 This feature is still present.
3703 However its use is highly discouraged, and
3704 should not be relied on; it will be removed by mid-2010.
3705 Update all of your scripts to use TAP names rather than numbers,
3706 by paying attention to the runtime warnings they trigger.
3707 Using TAP numbers in target configuration scripts prevents
3708 reusing those scripts on boards with multiple targets.
3709 @end quotation
3711 @section TAP Declaration Commands
3713 @c shouldn't this be(come) a {Config Command}?
3714 @deffn Command {jtag newtap} chipname tapname configparams...
3715 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3716 and configured according to the various @var{configparams}.
3718 The @var{chipname} is a symbolic name for the chip.
3719 Conventionally target config files use @code{$_CHIPNAME},
3720 defaulting to the model name given by the chip vendor but
3721 overridable.
3723 @cindex TAP naming convention
3724 The @var{tapname} reflects the role of that TAP,
3725 and should follow this convention:
3727 @itemize @bullet
3728 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3729 @item @code{cpu} -- The main CPU of the chip, alternatively
3730 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3731 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3732 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3733 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3734 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3735 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3736 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3737 with a single TAP;
3738 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3739 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3740 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3741 a JTAG TAP; that TAP should be named @code{sdma}.
3742 @end itemize
3744 Every TAP requires at least the following @var{configparams}:
3746 @itemize @bullet
3747 @item @code{-irlen} @var{NUMBER}
3748 @*The length in bits of the
3749 instruction register, such as 4 or 5 bits.
3750 @end itemize
3752 A TAP may also provide optional @var{configparams}:
3754 @itemize @bullet
3755 @item @code{-disable} (or @code{-enable})
3756 @*Use the @code{-disable} parameter to flag a TAP which is not
3757 linked in to the scan chain after a reset using either TRST
3758 or the JTAG state machine's @sc{reset} state.
3759 You may use @code{-enable} to highlight the default state
3760 (the TAP is linked in).
3761 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3762 @item @code{-expected-id} @var{number}
3763 @*A non-zero @var{number} represents a 32-bit IDCODE
3764 which you expect to find when the scan chain is examined.
3765 These codes are not required by all JTAG devices.
3766 @emph{Repeat the option} as many times as required if more than one
3767 ID code could appear (for example, multiple versions).
3768 Specify @var{number} as zero to suppress warnings about IDCODE
3769 values that were found but not included in the list.
3771 Provide this value if at all possible, since it lets OpenOCD
3772 tell when the scan chain it sees isn't right. These values
3773 are provided in vendors' chip documentation, usually a technical
3774 reference manual. Sometimes you may need to probe the JTAG
3775 hardware to find these values.
3776 @xref{autoprobing,,Autoprobing}.
3777 @item @code{-ignore-version}
3778 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3779 option. When vendors put out multiple versions of a chip, or use the same
3780 JTAG-level ID for several largely-compatible chips, it may be more practical
3781 to ignore the version field than to update config files to handle all of
3782 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3783 @item @code{-ircapture} @var{NUMBER}
3784 @*The bit pattern loaded by the TAP into the JTAG shift register
3785 on entry to the @sc{ircapture} state, such as 0x01.
3786 JTAG requires the two LSBs of this value to be 01.
3787 By default, @code{-ircapture} and @code{-irmask} are set
3788 up to verify that two-bit value. You may provide
3789 additional bits, if you know them, or indicate that
3790 a TAP doesn't conform to the JTAG specification.
3791 @item @code{-irmask} @var{NUMBER}
3792 @*A mask used with @code{-ircapture}
3793 to verify that instruction scans work correctly.
3794 Such scans are not used by OpenOCD except to verify that
3795 there seems to be no problems with JTAG scan chain operations.
3796 @end itemize
3797 @end deffn
3799 @section Other TAP commands
3801 @deffn Command {jtag cget} @option{-event} name
3802 @deffnx Command {jtag configure} @option{-event} name string
3803 At this writing this TAP attribute
3804 mechanism is used only for event handling.
3805 (It is not a direct analogue of the @code{cget}/@code{configure}
3806 mechanism for debugger targets.)
3807 See the next section for information about the available events.
3809 The @code{configure} subcommand assigns an event handler,
3810 a TCL string which is evaluated when the event is triggered.
3811 The @code{cget} subcommand returns that handler.
3812 @end deffn
3814 @section TAP Events
3815 @cindex events
3816 @cindex TAP events
3818 OpenOCD includes two event mechanisms.
3819 The one presented here applies to all JTAG TAPs.
3820 The other applies to debugger targets,
3821 which are associated with certain TAPs.
3823 The TAP events currently defined are:
3825 @itemize @bullet
3826 @item @b{post-reset}
3827 @* The TAP has just completed a JTAG reset.
3828 The tap may still be in the JTAG @sc{reset} state.
3829 Handlers for these events might perform initialization sequences
3830 such as issuing TCK cycles, TMS sequences to ensure
3831 exit from the ARM SWD mode, and more.
3833 Because the scan chain has not yet been verified, handlers for these events
3834 @emph{should not issue commands which scan the JTAG IR or DR registers}
3835 of any particular target.
3836 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3837 @item @b{setup}
3838 @* The scan chain has been reset and verified.
3839 This handler may enable TAPs as needed.
3840 @item @b{tap-disable}
3841 @* The TAP needs to be disabled. This handler should
3842 implement @command{jtag tapdisable}
3843 by issuing the relevant JTAG commands.
3844 @item @b{tap-enable}
3845 @* The TAP needs to be enabled. This handler should
3846 implement @command{jtag tapenable}
3847 by issuing the relevant JTAG commands.
3848 @end itemize
3850 If you need some action after each JTAG reset, which isn't actually
3851 specific to any TAP (since you can't yet trust the scan chain's
3852 contents to be accurate), you might:
3854 @example
3855 jtag configure CHIP.jrc -event post-reset @{
3856 echo "JTAG Reset done"
3857 ... non-scan jtag operations to be done after reset
3858 @}
3859 @end example
3862 @anchor{enablinganddisablingtaps}
3863 @section Enabling and Disabling TAPs
3864 @cindex JTAG Route Controller
3865 @cindex jrc
3867 In some systems, a @dfn{JTAG Route Controller} (JRC)
3868 is used to enable and/or disable specific JTAG TAPs.
3869 Many ARM based chips from Texas Instruments include
3870 an ``ICEpick'' module, which is a JRC.
3871 Such chips include DaVinci and OMAP3 processors.
3873 A given TAP may not be visible until the JRC has been
3874 told to link it into the scan chain; and if the JRC
3875 has been told to unlink that TAP, it will no longer
3876 be visible.
3877 Such routers address problems that JTAG ``bypass mode''
3878 ignores, such as:
3880 @itemize
3881 @item The scan chain can only go as fast as its slowest TAP.
3882 @item Having many TAPs slows instruction scans, since all
3883 TAPs receive new instructions.
3884 @item TAPs in the scan chain must be powered up, which wastes
3885 power and prevents debugging some power management mechanisms.
3886 @end itemize
3888 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3889 as implied by the existence of JTAG routers.
3890 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3891 does include a kind of JTAG router functionality.
3893 @c (a) currently the event handlers don't seem to be able to
3894 @c fail in a way that could lead to no-change-of-state.
3896 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3897 shown below, and is implemented using TAP event handlers.
3898 So for example, when defining a TAP for a CPU connected to
3899 a JTAG router, your @file{target.cfg} file
3900 should define TAP event handlers using
3901 code that looks something like this:
3903 @example
3904 jtag configure CHIP.cpu -event tap-enable @{
3905 ... jtag operations using CHIP.jrc
3906 @}
3907 jtag configure CHIP.cpu -event tap-disable @{
3908 ... jtag operations using CHIP.jrc
3909 @}
3910 @end example
3912 Then you might want that CPU's TAP enabled almost all the time:
3914 @example
3915 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3916 @end example
3918 Note how that particular setup event handler declaration
3919 uses quotes to evaluate @code{$CHIP} when the event is configured.
3920 Using brackets @{ @} would cause it to be evaluated later,
3921 at runtime, when it might have a different value.
3923 @deffn Command {jtag tapdisable}
3924 If necessary, disables the tap
3925 by sending it a @option{tap-disable} event.
3926 Returns the string "1" if the tap
3927 specified by @var{} is enabled,
3928 and "0" if it is disabled.
3929 @end deffn
3931 @deffn Command {jtag tapenable}
3932 If necessary, enables the tap
3933 by sending it a @option{tap-enable} event.
3934 Returns the string "1" if the tap
3935 specified by @var{} is enabled,
3936 and "0" if it is disabled.
3937 @end deffn
3939 @deffn Command {jtag tapisenabled}
3940 Returns the string "1" if the tap
3941 specified by @var{} is enabled,
3942 and "0" if it is disabled.
3944 @quotation Note
3945 Humans will find the @command{scan_chain} command more helpful
3946 for querying the state of the JTAG taps.
3947 @end quotation
3948 @end deffn
3950 @anchor{autoprobing}
3951 @section Autoprobing
3952 @cindex autoprobe
3953 @cindex JTAG autoprobe
3955 TAP configuration is the first thing that needs to be done
3956 after interface and reset configuration. Sometimes it's
3957 hard finding out what TAPs exist, or how they are identified.
3958 Vendor documentation is not always easy to find and use.
3960 To help you get past such problems, OpenOCD has a limited
3961 @emph{autoprobing} ability to look at the scan chain, doing
3962 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3963 To use this mechanism, start the OpenOCD server with only data
3964 that configures your JTAG interface, and arranges to come up
3965 with a slow clock (many devices don't support fast JTAG clocks
3966 right when they come out of reset).
3968 For example, your @file{openocd.cfg} file might have:
3970 @example
3971 source [find interface/olimex-arm-usb-tiny-h.cfg]
3972 reset_config trst_and_srst
3973 jtag_rclk 8
3974 @end example
3976 When you start the server without any TAPs configured, it will
3977 attempt to autoconfigure the TAPs. There are two parts to this:
3979 @enumerate
3980 @item @emph{TAP discovery} ...
3981 After a JTAG reset (sometimes a system reset may be needed too),
3982 each TAP's data registers will hold the contents of either the
3983 IDCODE or BYPASS register.
3984 If JTAG communication is working, OpenOCD will see each TAP,
3985 and report what @option{-expected-id} to use with it.
3986 @item @emph{IR Length discovery} ...
3987 Unfortunately JTAG does not provide a reliable way to find out
3988 the value of the @option{-irlen} parameter to use with a TAP
3989 that is discovered.
3990 If OpenOCD can discover the length of a TAP's instruction
3991 register, it will report it.
3992 Otherwise you may need to consult vendor documentation, such
3993 as chip data sheets or BSDL files.
3994 @end enumerate
3996 In many cases your board will have a simple scan chain with just
3997 a single device. Here's what OpenOCD reported with one board
3998 that's a bit more complex:
4000 @example
4001 clock speed 8 kHz
4002 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4003 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4004 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4005 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4006 AUTO auto0.tap - use "... -irlen 4"
4007 AUTO auto1.tap - use "... -irlen 4"
4008 AUTO auto2.tap - use "... -irlen 6"
4009 no gdb ports allocated as no target has been specified
4010 @end example
4012 Given that information, you should be able to either find some existing
4013 config files to use, or create your own. If you create your own, you
4014 would configure from the bottom up: first a @file{target.cfg} file
4015 with these TAPs, any targets associated with them, and any on-chip
4016 resources; then a @file{board.cfg} with off-chip resources, clocking,
4017 and so forth.
4019 @node CPU Configuration
4020 @chapter CPU Configuration
4021 @cindex GDB target
4023 This chapter discusses how to set up GDB debug targets for CPUs.
4024 You can also access these targets without GDB
4025 (@pxref{Architecture and Core Commands},
4026 and @ref{targetstatehandling,,Target State handling}) and
4027 through various kinds of NAND and NOR flash commands.
4028 If you have multiple CPUs you can have multiple such targets.
4030 We'll start by looking at how to examine the targets you have,
4031 then look at how to add one more target and how to configure it.
4033 @section Target List
4034 @cindex target, current
4035 @cindex target, list
4037 All targets that have been set up are part of a list,
4038 where each member has a name.
4039 That name should normally be the same as the TAP name.
4040 You can display the list with the @command{targets}
4041 (plural!) command.
4042 This display often has only one CPU; here's what it might
4043 look like with more than one:
4044 @verbatim
4045 TargetName Type Endian TapName State
4046 -- ------------------ ---------- ------ ------------------ ------------
4047 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4048 1 MyTarget cortex_m little tap-disabled
4049 @end verbatim
4051 One member of that list is the @dfn{current target}, which
4052 is implicitly referenced by many commands.
4053 It's the one marked with a @code{*} near the target name.
4054 In particular, memory addresses often refer to the address
4055 space seen by that current target.
4056 Commands like @command{mdw} (memory display words)
4057 and @command{flash erase_address} (erase NOR flash blocks)
4058 are examples; and there are many more.
4060 Several commands let you examine the list of targets:
4062 @deffn Command {target count}
4063 @emph{Note: target numbers are deprecated; don't use them.
4064 They will be removed shortly after August 2010, including this command.
4065 Iterate target using @command{target names}, not by counting.}
4067 Returns the number of targets, @math{N}.
4068 The highest numbered target is @math{N - 1}.
4069 @example
4070 set c [target count]
4071 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
4072 # Assuming you have created this function
4073 print_target_details $x
4074 @}
4075 @end example
4076 @end deffn
4078 @deffn Command {target current}
4079 Returns the name of the current target.
4080 @end deffn
4082 @deffn Command {target names}
4083 Lists the names of all current targets in the list.
4084 @example
4085 foreach t [target names] @{
4086 puts [format "Target: %s\n" $t]
4087 @}
4088 @end example
4089 @end deffn
4091 @deffn Command {target number} number
4092 @emph{Note: target numbers are deprecated; don't use them.
4093 They will be removed shortly after August 2010, including this command.}
4095 The list of targets is numbered starting at zero.
4096 This command returns the name of the target at index @var{number}.
4097 @example
4098 set thename [target number $x]
4099 puts [format "Target %d is: %s\n" $x $thename]
4100 @end example
4101 @end deffn
4103 @c yep, "target list" would have been better.
4104 @c plus maybe "target setdefault".
4106 @deffn Command targets [name]
4107 @emph{Note: the name of this command is plural. Other target
4108 command names are singular.}
4110 With no parameter, this command displays a table of all known
4111 targets in a user friendly form.
4113 With a parameter, this command sets the current target to
4114 the given target with the given @var{name}; this is
4115 only relevant on boards which have more than one target.
4116 @end deffn
4118 @section Target CPU Types and Variants
4119 @cindex target type
4120 @cindex CPU type
4121 @cindex CPU variant
4123 Each target has a @dfn{CPU type}, as shown in the output of
4124 the @command{targets} command. You need to specify that type
4125 when calling @command{target create}.
4126 The CPU type indicates more than just the instruction set.
4127 It also indicates how that instruction set is implemented,
4128 what kind of debug support it integrates,
4129 whether it has an MMU (and if so, what kind),
4130 what core-specific commands may be available
4131 (@pxref{Architecture and Core Commands}),
4132 and more.
4134 For some CPU types, OpenOCD also defines @dfn{variants} which
4135 indicate differences that affect their handling.
4136 For example, a particular implementation bug might need to be
4137 worked around in some chip versions.
4139 It's easy to see what target types are supported,
4140 since there's a command to list them.
4141 However, there is currently no way to list what target variants
4142 are supported (other than by reading the OpenOCD source code).
4144 @anchor{targettypes}
4145 @deffn Command {target types}
4146 Lists all supported target types.
4147 At this writing, the supported CPU types and variants are:
4149 @itemize @bullet
4150 @item @code{arm11} -- this is a generation of ARMv6 cores
4151 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4152 @item @code{arm7tdmi} -- this is an ARMv4 core
4153 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4154 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4155 @item @code{arm966e} -- this is an ARMv5 core
4156 @item @code{arm9tdmi} -- this is an ARMv4 core
4157 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4158 (Support for this is preliminary and incomplete.)
4159 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4160 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4161 compact Thumb2 instruction set.
4162 @item @code{dragonite} -- resembles arm966e
4163 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4164 (Support for this is still incomplete.)
4165 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4166 @item @code{feroceon} -- resembles arm926
4167 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
4168 @item @code{xscale} -- this is actually an architecture,
4169 not a CPU type. It is based on the ARMv5 architecture.
4170 There are several variants defined:
4171 @itemize @minus
4172 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
4173 @code{pxa27x} ... instruction register length is 7 bits
4174 @item @code{pxa250}, @code{pxa255},<