c9e48bfa9bcf75eb858d1c2c9d4eff6027f676d5
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
11
12 @include version.texi
13
14 @copying
15
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
20
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009 David Brownell
27 @end itemize
28
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
38
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
45
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
50
51 @summarycontents
52 @contents
53
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
57
58 @insertcopying
59 @end ifnottex
60
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developers
64 * JTAG Hardware Dongles:: JTAG Hardware Dongles
65 * About JIM-Tcl:: About JIM-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Interface - Dongle Configuration:: Interface - Dongle Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * TFTP:: TFTP
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * Upgrading:: Deprecated/Removed Commands
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
88
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
95 @end menu
96
97 @node About
98 @unnumbered About
99 @cindex about
100
101 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
102 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
105 around the world.
106
107 @section What is OpenOCD?
108 @cindex TAP
109 @cindex JTAG
110
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
113 devices.
114
115 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
116 with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
117 A @dfn{TAP} is a ``Test Access Port'', a module which processes
118 special instructions and data. TAPs are daisy-chained within and
119 between chips and boards.
120
121 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
122 based, parallel port based, and other standalone boxes that run
123 OpenOCD internally. @xref{JTAG Hardware Dongles}.
124
125 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
126 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
127 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
128 debugged via the GDB protocol.
129
130 @b{Flash Programing:} Flash writing is supported for external CFI
131 compatible NOR flashes (Intel and AMD/Spansion command set) and several
132 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
133 STM32x). Preliminary support for various NAND flash controllers
134 (LPC3180, Orion, S3C24xx, more) controller is included.
135
136 @section OpenOCD Web Site
137
138 The OpenOCD web site provides the latest public news from the community:
139
140 @uref{http://openocd.berlios.de/web/}
141
142 @section Latest User's Guide:
143
144 The user's guide you are now reading may not be the latest one
145 available. A version for more recent code may be available.
146 Its HTML form is published irregularly at:
147
148 @uref{http://openocd.berlios.de/doc/html/index.html}
149
150 PDF form is likewise published at:
151
152 @uref{http://openocd.berlios.de/doc/pdf/openocd.pdf}
153
154 @section OpenOCD User's Forum
155
156 There is an OpenOCD forum (phpBB) hosted by SparkFun:
157
158 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
159
160
161 @node Developers
162 @chapter OpenOCD Developer Resources
163 @cindex developers
164
165 If you are interested in improving the state of OpenOCD's debugging and
166 testing support, new contributions will be welcome. Motivated developers
167 can produce new target, flash or interface drivers, improve the
168 documentation, as well as more conventional bug fixes and enhancements.
169
170 The resources in this chapter are available for developers wishing to explore
171 or expand the OpenOCD source code.
172
173 @section OpenOCD GIT Repository
174
175 During the 0.3.x release cycle, OpenOCD switched from Subversion to
176 a GIT repository hosted at SourceForge. The repository URL is:
177
178 @uref{git://openocd.git.sourceforge.net/gitroot/openocd/openocd}
179
180 You may prefer to use a mirror and the HTTP protocol:
181
182 @uref{http://repo.or.cz/r/openocd.git}
183
184 With standard GIT tools, use @command{git clone} to initialize
185 a local repository, and @command{git pull} to update it.
186 There are also gitweb pages letting you browse the repository
187 with a web browser, or download arbitrary snapshots without
188 needing a GIT client:
189
190 @uref{http://openocd.git.sourceforge.net/git/gitweb.cgi?p=openocd/openocd}
191
192 @uref{http://repo.or.cz/w/openocd.git}
193
194 The @file{README} file contains the instructions for building the project
195 from the repository or a snapshot.
196
197 Developers that want to contribute patches to the OpenOCD system are
198 @b{strongly} encouraged to work against mainline.
199 Patches created against older versions may require additional
200 work from their submitter in order to be updated for newer releases.
201
202 @section Doxygen Developer Manual
203
204 During the 0.2.x release cycle, the OpenOCD project began
205 providing a Doxygen reference manual. This document contains more
206 technical information about the software internals, development
207 processes, and similar documentation:
208
209 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
210
211 This document is a work-in-progress, but contributions would be welcome
212 to fill in the gaps. All of the source files are provided in-tree,
213 listed in the Doxyfile configuration in the top of the source tree.
214
215 @section OpenOCD Developer Mailing List
216
217 The OpenOCD Developer Mailing List provides the primary means of
218 communication between developers:
219
220 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
221
222 Discuss and submit patches to this list.
223 The @file{PATCHES} file contains basic information about how
224 to prepare patches.
225
226
227 @node JTAG Hardware Dongles
228 @chapter JTAG Hardware Dongles
229 @cindex dongles
230 @cindex FTDI
231 @cindex wiggler
232 @cindex zy1000
233 @cindex printer port
234 @cindex USB Adapter
235 @cindex RTCK
236
237 Defined: @b{dongle}: A small device that plugins into a computer and serves as
238 an adapter .... [snip]
239
240 In the OpenOCD case, this generally refers to @b{a small adapater} one
241 attaches to your computer via USB or the Parallel Printer Port. The
242 execption being the Zylin ZY1000 which is a small box you attach via
243 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
244 require any drivers to be installed on the developer PC. It also has
245 a built in web interface. It supports RTCK/RCLK or adaptive clocking
246 and has a built in relay to power cycle targets remotely.
247
248
249 @section Choosing a Dongle
250
251 There are several things you should keep in mind when choosing a dongle.
252
253 @enumerate
254 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
255 Does your dongle support it? You might need a level converter.
256 @item @b{Pinout} What pinout does your target board use?
257 Does your dongle support it? You may be able to use jumper
258 wires, or an "octopus" connector, to convert pinouts.
259 @item @b{Connection} Does your computer have the USB, printer, or
260 Ethernet port needed?
261 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
262 @end enumerate
263
264 @section Stand alone Systems
265
266 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
267 dongle, but a standalone box. The ZY1000 has the advantage that it does
268 not require any drivers installed on the developer PC. It also has
269 a built in web interface. It supports RTCK/RCLK or adaptive clocking
270 and has a built in relay to power cycle targets remotely.
271
272 @section USB FT2232 Based
273
274 There are many USB JTAG dongles on the market, many of them are based
275 on a chip from ``Future Technology Devices International'' (FTDI)
276 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
277 See: @url{http://www.ftdichip.com} for more information.
278 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
279 chips are starting to become available in JTAG adapters.
280
281 @itemize @bullet
282 @item @b{usbjtag}
283 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
284 @item @b{jtagkey}
285 @* See: @url{http://www.amontec.com/jtagkey.shtml}
286 @item @b{jtagkey2}
287 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
288 @item @b{oocdlink}
289 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
290 @item @b{signalyzer}
291 @* See: @url{http://www.signalyzer.com}
292 @item @b{evb_lm3s811}
293 @* See: @url{http://www.luminarymicro.com} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
294 @item @b{luminary_icdi}
295 @* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug Interface (ICDI) Board, included in the Stellaris LM3S9B90 and LM3S9B92 Evaluation Kits.
296 @item @b{olimex-jtag}
297 @* See: @url{http://www.olimex.com}
298 @item @b{flyswatter}
299 @* See: @url{http://www.tincantools.com}
300 @item @b{turtelizer2}
301 @* See:
302 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
303 @url{http://www.ethernut.de}
304 @item @b{comstick}
305 @* Link: @url{http://www.hitex.com/index.php?id=383}
306 @item @b{stm32stick}
307 @* Link @url{http://www.hitex.com/stm32-stick}
308 @item @b{axm0432_jtag}
309 @* Axiom AXM-0432 Link @url{http://www.axman.com}
310 @item @b{cortino}
311 @* Link @url{http://www.hitex.com/index.php?id=cortino}
312 @end itemize
313
314 @section USB JLINK based
315 There are several OEM versions of the Segger @b{JLINK} adapter. It is
316 an example of a micro controller based JTAG adapter, it uses an
317 AT91SAM764 internally.
318
319 @itemize @bullet
320 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
321 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
322 @item @b{SEGGER JLINK}
323 @* Link: @url{http://www.segger.com/jlink.html}
324 @item @b{IAR J-Link}
325 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
326 @end itemize
327
328 @section USB RLINK based
329 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
330
331 @itemize @bullet
332 @item @b{Raisonance RLink}
333 @* Link: @url{http://www.raisonance.com/products/RLink.php}
334 @item @b{STM32 Primer}
335 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
336 @item @b{STM32 Primer2}
337 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
338 @end itemize
339
340 @section USB Other
341 @itemize @bullet
342 @item @b{USBprog}
343 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
344
345 @item @b{USB - Presto}
346 @* Link: @url{http://tools.asix.net/prg_presto.htm}
347
348 @item @b{Versaloon-Link}
349 @* Link: @url{http://www.simonqian.com/en/Versaloon}
350
351 @item @b{ARM-JTAG-EW}
352 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
353 @end itemize
354
355 @section IBM PC Parallel Printer Port Based
356
357 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
358 and the MacGraigor Wiggler. There are many clones and variations of
359 these on the market.
360
361 Note that parallel ports are becoming much less common, so if you
362 have the choice you should probably avoid these adapters in favor
363 of USB-based ones.
364
365 @itemize @bullet
366
367 @item @b{Wiggler} - There are many clones of this.
368 @* Link: @url{http://www.macraigor.com/wiggler.htm}
369
370 @item @b{DLC5} - From XILINX - There are many clones of this
371 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
372 produced, PDF schematics are easily found and it is easy to make.
373
374 @item @b{Amontec - JTAG Accelerator}
375 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
376
377 @item @b{GW16402}
378 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
379
380 @item @b{Wiggler2}
381 @*@uref{http://www.ccac.rwth-aachen.de/@/~michaels/@/index.php/hardware/@/armjtag,
382 Improved parallel-port wiggler-style JTAG adapter}
383
384 @item @b{Wiggler_ntrst_inverted}
385 @* Yet another variation - See the source code, src/jtag/parport.c
386
387 @item @b{old_amt_wiggler}
388 @* Unknown - probably not on the market today
389
390 @item @b{arm-jtag}
391 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
392
393 @item @b{chameleon}
394 @* Link: @url{http://www.amontec.com/chameleon.shtml}
395
396 @item @b{Triton}
397 @* Unknown.
398
399 @item @b{Lattice}
400 @* ispDownload from Lattice Semiconductor
401 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
402
403 @item @b{flashlink}
404 @* From ST Microsystems;
405 @uref{http://www.st.com/stonline/@/products/literature/um/7889.pdf,
406 FlashLINK JTAG programing cable for PSD and uPSD}
407
408 @end itemize
409
410 @section Other...
411 @itemize @bullet
412
413 @item @b{ep93xx}
414 @* An EP93xx based Linux machine using the GPIO pins directly.
415
416 @item @b{at91rm9200}
417 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
418
419 @end itemize
420
421 @node About JIM-Tcl
422 @chapter About JIM-Tcl
423 @cindex JIM Tcl
424 @cindex tcl
425
426 OpenOCD includes a small ``Tcl Interpreter'' known as JIM-Tcl.
427 This programming language provides a simple and extensible
428 command interpreter.
429
430 All commands presented in this Guide are extensions to JIM-Tcl.
431 You can use them as simple commands, without needing to learn
432 much of anything about Tcl.
433 Alternatively, can write Tcl programs with them.
434
435 You can learn more about JIM at its website, @url{http://jim.berlios.de}.
436
437 @itemize @bullet
438 @item @b{JIM vs. Tcl}
439 @* JIM-TCL is a stripped down version of the well known Tcl language,
440 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
441 fewer features. JIM-Tcl is a single .C file and a single .H file and
442 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
443 4.2 MB .zip file containing 1540 files.
444
445 @item @b{Missing Features}
446 @* Our practice has been: Add/clone the real Tcl feature if/when
447 needed. We welcome JIM Tcl improvements, not bloat.
448
449 @item @b{Scripts}
450 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
451 command interpreter today is a mixture of (newer)
452 JIM-Tcl commands, and (older) the orginal command interpreter.
453
454 @item @b{Commands}
455 @* At the OpenOCD telnet command line (or via the GDB mon command) one
456 can type a Tcl for() loop, set variables, etc.
457 Some of the commands documented in this guide are implemented
458 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
459
460 @item @b{Historical Note}
461 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
462
463 @item @b{Need a crash course in Tcl?}
464 @*@xref{Tcl Crash Course}.
465 @end itemize
466
467 @node Running
468 @chapter Running
469 @cindex command line options
470 @cindex logfile
471 @cindex directory search
472
473 The @option{--help} option shows:
474 @verbatim
475 bash$ openocd --help
476
477 --help | -h display this help
478 --version | -v display OpenOCD version
479 --file | -f use configuration file <name>
480 --search | -s dir to search for config files and scripts
481 --debug | -d set debug level <0-3>
482 --log_output | -l redirect log output to file <name>
483 --command | -c run <command>
484 --pipe | -p use pipes when talking to gdb
485 @end verbatim
486
487 By default OpenOCD reads the file configuration file @file{openocd.cfg}
488 in the current directory. To specify a different (or multiple)
489 configuration file, you can use the ``-f'' option. For example:
490
491 @example
492 openocd -f config1.cfg -f config2.cfg -f config3.cfg
493 @end example
494
495 OpenOCD starts by processing the configuration commands provided
496 on the command line or in @file{openocd.cfg}.
497 @xref{Configuration Stage}.
498 At the end of the configuration stage it verifies the JTAG scan
499 chain defined using those commands; your configuration should
500 ensure that this always succeeds.
501 Normally, OpenOCD then starts running as a daemon.
502 Alternatively, commands may be used to terminate the configuration
503 stage early, perform work (such as updating some flash memory),
504 and then shut down without acting as a daemon.
505
506 Once OpenOCD starts running as a daemon, it waits for connections from
507 clients (Telnet, GDB, Other) and processes the commands issued through
508 those channels.
509
510 If you are having problems, you can enable internal debug messages via
511 the ``-d'' option.
512
513 Also it is possible to interleave JIM-Tcl commands w/config scripts using the
514 @option{-c} command line switch.
515
516 To enable debug output (when reporting problems or working on OpenOCD
517 itself), use the @option{-d} command line switch. This sets the
518 @option{debug_level} to "3", outputting the most information,
519 including debug messages. The default setting is "2", outputting only
520 informational messages, warnings and errors. You can also change this
521 setting from within a telnet or gdb session using @command{debug_level
522 <n>} (@pxref{debug_level}).
523
524 You can redirect all output from the daemon to a file using the
525 @option{-l <logfile>} switch.
526
527 Search paths for config/script files can be added to OpenOCD by using
528 the @option{-s <search>} switch. The current directory and the OpenOCD
529 target library is in the search path by default.
530
531 For details on the @option{-p} option. @xref{Connecting to GDB}.
532
533 Note! OpenOCD will launch the GDB & telnet server even if it can not
534 establish a connection with the target. In general, it is possible for
535 the JTAG controller to be unresponsive until the target is set up
536 correctly via e.g. GDB monitor commands in a GDB init script.
537
538 @node OpenOCD Project Setup
539 @chapter OpenOCD Project Setup
540
541 To use OpenOCD with your development projects, you need to do more than
542 just connecting the JTAG adapter hardware (dongle) to your development board
543 and then starting the OpenOCD server.
544 You also need to configure that server so that it knows
545 about that adapter and board, and helps your work.
546
547 @section Hooking up the JTAG Adapter
548
549 Today's most common case is a dongle with a JTAG cable on one side
550 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
551 and a USB cable on the other.
552 Instead of USB, some cables use Ethernet;
553 older ones may use a PC parallel port, or even a serial port.
554
555 @enumerate
556 @item @emph{Start with power to your target board turned off},
557 and nothing connected to your JTAG adapter.
558 If you're particularly paranoid, unplug power to the board.
559 It's important to have the ground signal properly set up,
560 unless you are using a JTAG adapter which provides
561 galvanic isolation between the target board and the
562 debugging host.
563
564 @item @emph{Be sure it's the right kind of JTAG connector.}
565 If your dongle has a 20-pin ARM connector, you need some kind
566 of adapter (or octopus, see below) to hook it up to
567 boards using 14-pin or 10-pin connectors ... or to 20-pin
568 connectors which don't use ARM's pinout.
569
570 In the same vein, make sure the voltage levels are compatible.
571 Not all JTAG adapters have the level shifters needed to work
572 with 1.2 Volt boards.
573
574 @item @emph{Be certain the cable is properly oriented} or you might
575 damage your board. In most cases there are only two possible
576 ways to connect the cable.
577 Connect the JTAG cable from your adapter to the board.
578 Be sure it's firmly connected.
579
580 In the best case, the connector is keyed to physically
581 prevent you from inserting it wrong.
582 This is most often done using a slot on the board's male connector
583 housing, which must match a key on the JTAG cable's female connector.
584 If there's no housing, then you must look carefully and
585 make sure pin 1 on the cable hooks up to pin 1 on the board.
586 Ribbon cables are frequently all grey except for a wire on one
587 edge, which is red. The red wire is pin 1.
588
589 Sometimes dongles provide cables where one end is an ``octopus'' of
590 color coded single-wire connectors, instead of a connector block.
591 These are great when converting from one JTAG pinout to another,
592 but are tedious to set up.
593 Use these with connector pinout diagrams to help you match up the
594 adapter signals to the right board pins.
595
596 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
597 A USB, parallel, or serial port connector will go to the host which
598 you are using to run OpenOCD.
599 For Ethernet, consult the documentation and your network administrator.
600
601 For USB based JTAG adapters you have an easy sanity check at this point:
602 does the host operating system see the JTAG adapter?
603
604 @item @emph{Connect the adapter's power supply, if needed.}
605 This step is primarily for non-USB adapters,
606 but sometimes USB adapters need extra power.
607
608 @item @emph{Power up the target board.}
609 Unless you just let the magic smoke escape,
610 you're now ready to set up the OpenOCD server
611 so you can use JTAG to work with that board.
612
613 @end enumerate
614
615 Talk with the OpenOCD server using
616 telnet (@code{telnet localhost 4444} on many systems) or GDB.
617 @xref{GDB and OpenOCD}.
618
619 @section Project Directory
620
621 There are many ways you can configure OpenOCD and start it up.
622
623 A simple way to organize them all involves keeping a
624 single directory for your work with a given board.
625 When you start OpenOCD from that directory,
626 it searches there first for configuration files, scripts,
627 and for code you upload to the target board.
628 It is also the natural place to write files,
629 such as log files and data you download from the board.
630
631 @section Configuration Basics
632
633 There are two basic ways of configuring OpenOCD, and
634 a variety of ways you can mix them.
635 Think of the difference as just being how you start the server:
636
637 @itemize
638 @item Many @option{-f file} or @option{-c command} options on the command line
639 @item No options, but a @dfn{user config file}
640 in the current directory named @file{openocd.cfg}
641 @end itemize
642
643 Here is an example @file{openocd.cfg} file for a setup
644 using a Signalyzer FT2232-based JTAG adapter to talk to
645 a board with an Atmel AT91SAM7X256 microcontroller:
646
647 @example
648 source [find interface/signalyzer.cfg]
649
650 # GDB can also flash my flash!
651 gdb_memory_map enable
652 gdb_flash_program enable
653
654 source [find target/sam7x256.cfg]
655 @end example
656
657 Here is the command line equivalent of that configuration:
658
659 @example
660 openocd -f interface/signalyzer.cfg \
661 -c "gdb_memory_map enable" \
662 -c "gdb_flash_program enable" \
663 -f target/sam7x256.cfg
664 @end example
665
666 You could wrap such long command lines in shell scripts,
667 each supporting a different development task.
668 One might re-flash the board with a specific firmware version.
669 Another might set up a particular debugging or run-time environment.
670
671 @quotation Important
672 At this writing (October 2009) the command line method has
673 problems with how it treats variables.
674 For example, after @option{-c "set VAR value"}, or doing the
675 same in a script, the variable @var{VAR} will have no value
676 that can be tested in a later script.
677 @end quotation
678
679 Here we will focus on the simpler solution: one user config
680 file, including basic configuration plus any TCL procedures
681 to simplify your work.
682
683 @section User Config Files
684 @cindex config file, user
685 @cindex user config file
686 @cindex config file, overview
687
688 A user configuration file ties together all the parts of a project
689 in one place.
690 One of the following will match your situation best:
691
692 @itemize
693 @item Ideally almost everything comes from configuration files
694 provided by someone else.
695 For example, OpenOCD distributes a @file{scripts} directory
696 (probably in @file{/usr/share/openocd/scripts} on Linux).
697 Board and tool vendors can provide these too, as can individual
698 user sites; the @option{-s} command line option lets you say
699 where to find these files. (@xref{Running}.)
700 The AT91SAM7X256 example above works this way.
701
702 Three main types of non-user configuration file each have their
703 own subdirectory in the @file{scripts} directory:
704
705 @enumerate
706 @item @b{interface} -- one for each kind of JTAG adapter/dongle
707 @item @b{board} -- one for each different board
708 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
709 @end enumerate
710
711 Best case: include just two files, and they handle everything else.
712 The first is an interface config file.
713 The second is board-specific, and it sets up the JTAG TAPs and
714 their GDB targets (by deferring to some @file{target.cfg} file),
715 declares all flash memory, and leaves you nothing to do except
716 meet your deadline:
717
718 @example
719 source [find interface/olimex-jtag-tiny.cfg]
720 source [find board/csb337.cfg]
721 @end example
722
723 Boards with a single microcontroller often won't need more
724 than the target config file, as in the AT91SAM7X256 example.
725 That's because there is no external memory (flash, DDR RAM), and
726 the board differences are encapsulated by application code.
727
728 @item You can often reuse some standard config files but
729 need to write a few new ones, probably a @file{board.cfg} file.
730 You will be using commands described later in this User's Guide,
731 and working with the guidelines in the next chapter.
732
733 For example, there may be configuration files for your JTAG adapter
734 and target chip, but you need a new board-specific config file
735 giving access to your particular flash chips.
736 Or you might need to write another target chip configuration file
737 for a new chip built around the Cortex M3 core.
738
739 @quotation Note
740 When you write new configuration files, please submit
741 them for inclusion in the next OpenOCD release.
742 For example, a @file{board/newboard.cfg} file will help the
743 next users of that board, and a @file{target/newcpu.cfg}
744 will help support users of any board using that chip.
745 @end quotation
746
747 @item
748 You may may need to write some C code.
749 It may be as simple as a supporting a new ft2232 or parport
750 based dongle; a bit more involved, like a NAND or NOR flash
751 controller driver; or a big piece of work like supporting
752 a new chip architecture.
753 @end itemize
754
755 Reuse the existing config files when you can.
756 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
757 You may find a board configuration that's a good example to follow.
758
759 When you write config files, separate the reusable parts
760 (things every user of that interface, chip, or board needs)
761 from ones specific to your environment and debugging approach.
762 @itemize
763
764 @item
765 For example, a @code{gdb-attach} event handler that invokes
766 the @command{reset init} command will interfere with debugging
767 early boot code, which performs some of the same actions
768 that the @code{reset-init} event handler does.
769
770 @item
771 Likewise, the @command{arm9tdmi vector_catch} command (or
772 @cindex vector_catch
773 its siblings @command{xscale vector_catch}
774 and @command{cortex_m3 vector_catch}) can be a timesaver
775 during some debug sessions, but don't make everyone use that either.
776 Keep those kinds of debugging aids in your user config file,
777 along with messaging and tracing setup.
778 (@xref{Software Debug Messages and Tracing}.)
779
780 @item
781 You might need to override some defaults.
782 For example, you might need to move, shrink, or back up the target's
783 work area if your application needs much SRAM.
784
785 @item
786 TCP/IP port configuration is another example of something which
787 is environment-specific, and should only appear in
788 a user config file. @xref{TCP/IP Ports}.
789 @end itemize
790
791 @section Project-Specific Utilities
792
793 A few project-specific utility
794 routines may well speed up your work.
795 Write them, and keep them in your project's user config file.
796
797 For example, if you are making a boot loader work on a
798 board, it's nice to be able to debug the ``after it's
799 loaded to RAM'' parts separately from the finicky early
800 code which sets up the DDR RAM controller and clocks.
801 A script like this one, or a more GDB-aware sibling,
802 may help:
803
804 @example
805 proc ramboot @{ @} @{
806 # Reset, running the target's "reset-init" scripts
807 # to initialize clocks and the DDR RAM controller.
808 # Leave the CPU halted.
809 reset init
810
811 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
812 load_image u-boot.bin 0x20000000
813
814 # Start running.
815 resume 0x20000000
816 @}
817 @end example
818
819 Then once that code is working you will need to make it
820 boot from NOR flash; a different utility would help.
821 Alternatively, some developers write to flash using GDB.
822 (You might use a similar script if you're working with a flash
823 based microcontroller application instead of a boot loader.)
824
825 @example
826 proc newboot @{ @} @{
827 # Reset, leaving the CPU halted. The "reset-init" event
828 # proc gives faster access to the CPU and to NOR flash;
829 # "reset halt" would be slower.
830 reset init
831
832 # Write standard version of U-Boot into the first two
833 # sectors of NOR flash ... the standard version should
834 # do the same lowlevel init as "reset-init".
835 flash protect 0 0 1 off
836 flash erase_sector 0 0 1
837 flash write_bank 0 u-boot.bin 0x0
838 flash protect 0 0 1 on
839
840 # Reboot from scratch using that new boot loader.
841 reset run
842 @}
843 @end example
844
845 You may need more complicated utility procedures when booting
846 from NAND.
847 That often involves an extra bootloader stage,
848 running from on-chip SRAM to perform DDR RAM setup so it can load
849 the main bootloader code (which won't fit into that SRAM).
850
851 Other helper scripts might be used to write production system images,
852 involving considerably more than just a three stage bootloader.
853
854 @section Target Software Changes
855
856 Sometimes you may want to make some small changes to the software
857 you're developing, to help make JTAG debugging work better.
858 For example, in C or assembly language code you might
859 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
860 handling issues like:
861
862 @itemize @bullet
863
864 @item @b{ARM Wait-For-Interrupt}...
865 Many ARM chips synchronize the JTAG clock using the core clock.
866 Low power states which stop that core clock thus prevent JTAG access.
867 Idle loops in tasking environments often enter those low power states
868 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
869
870 You may want to @emph{disable that instruction} in source code,
871 or otherwise prevent using that state,
872 to ensure you can get JTAG access at any time.
873 For example, the OpenOCD @command{halt} command may not
874 work for an idle processor otherwise.
875
876 @item @b{Delay after reset}...
877 Not all chips have good support for debugger access
878 right after reset; many LPC2xxx chips have issues here.
879 Similarly, applications that reconfigure pins used for
880 JTAG access as they start will also block debugger access.
881
882 To work with boards like this, @emph{enable a short delay loop}
883 the first thing after reset, before "real" startup activities.
884 For example, one second's delay is usually more than enough
885 time for a JTAG debugger to attach, so that
886 early code execution can be debugged
887 or firmware can be replaced.
888
889 @item @b{Debug Communications Channel (DCC)}...
890 Some processors include mechanisms to send messages over JTAG.
891 Many ARM cores support these, as do some cores from other vendors.
892 (OpenOCD may be able to use this DCC internally, speeding up some
893 operations like writing to memory.)
894
895 Your application may want to deliver various debugging messages
896 over JTAG, by @emph{linking with a small library of code}
897 provided with OpenOCD and using the utilities there to send
898 various kinds of message.
899 @xref{Software Debug Messages and Tracing}.
900
901 @end itemize
902
903 @node Config File Guidelines
904 @chapter Config File Guidelines
905
906 This chapter is aimed at any user who needs to write a config file,
907 including developers and integrators of OpenOCD and any user who
908 needs to get a new board working smoothly.
909 It provides guidelines for creating those files.
910
911 You should find the following directories under @t{$(INSTALLDIR)/scripts},
912 with files including the ones listed here.
913 Use them as-is where you can; or as models for new files.
914 @itemize @bullet
915 @item @file{interface} ...
916 think JTAG Dongle. Files that configure JTAG adapters go here.
917 @example
918 $ ls interface
919 arm-jtag-ew.cfg hitex_str9-comstick.cfg oocdlink.cfg
920 arm-usb-ocd.cfg icebear.cfg openocd-usb.cfg
921 at91rm9200.cfg jlink.cfg parport.cfg
922 axm0432.cfg jtagkey2.cfg parport_dlc5.cfg
923 calao-usb-a9260-c01.cfg jtagkey.cfg rlink.cfg
924 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg sheevaplug.cfg
925 calao-usb-a9260.cfg luminary.cfg signalyzer.cfg
926 chameleon.cfg luminary-icdi.cfg stm32-stick.cfg
927 cortino.cfg luminary-lm3s811.cfg turtelizer2.cfg
928 dummy.cfg olimex-arm-usb-ocd.cfg usbprog.cfg
929 flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
930 $
931 @end example
932 @item @file{board} ...
933 think Circuit Board, PWA, PCB, they go by many names. Board files
934 contain initialization items that are specific to a board.
935 They reuse target configuration files, since the same
936 microprocessor chips are used on many boards,
937 but support for external parts varies widely. For
938 example, the SDRAM initialization sequence for the board, or the type
939 of external flash and what address it uses. Any initialization
940 sequence to enable that external flash or SDRAM should be found in the
941 board file. Boards may also contain multiple targets: two CPUs; or
942 a CPU and an FPGA.
943 @example
944 $ ls board
945 arm_evaluator7t.cfg keil_mcb1700.cfg
946 at91rm9200-dk.cfg keil_mcb2140.cfg
947 at91sam9g20-ek.cfg linksys_nslu2.cfg
948 atmel_at91sam7s-ek.cfg logicpd_imx27.cfg
949 atmel_at91sam9260-ek.cfg mini2440.cfg
950 atmel_sam3u_ek.cfg olimex_LPC2378STK.cfg
951 crossbow_tech_imote2.cfg olimex_lpc_h2148.cfg
952 csb337.cfg olimex_sam7_ex256.cfg
953 csb732.cfg olimex_sam9_l9260.cfg
954 digi_connectcore_wi-9c.cfg olimex_stm32_h103.cfg
955 dm355evm.cfg omap2420_h4.cfg
956 dm365evm.cfg osk5912.cfg
957 dm6446evm.cfg pic-p32mx.cfg
958 eir.cfg propox_mmnet1001.cfg
959 ek-lm3s1968.cfg pxa255_sst.cfg
960 ek-lm3s3748.cfg sheevaplug.cfg
961 ek-lm3s811.cfg stm3210e_eval.cfg
962 ek-lm3s9b9x.cfg stm32f10x_128k_eval.cfg
963 hammer.cfg str910-eval.cfg
964 hitex_lpc2929.cfg telo.cfg
965 hitex_stm32-performancestick.cfg ti_beagleboard.cfg
966 hitex_str9-comstick.cfg topas910.cfg
967 iar_str912_sk.cfg topasa900.cfg
968 imx27ads.cfg unknown_at91sam9260.cfg
969 imx27lnst.cfg x300t.cfg
970 imx31pdk.cfg zy1000.cfg
971 $
972 @end example
973 @item @file{target} ...
974 think chip. The ``target'' directory represents the JTAG TAPs
975 on a chip
976 which OpenOCD should control, not a board. Two common types of targets
977 are ARM chips and FPGA or CPLD chips.
978 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
979 the target config file defines all of them.
980 @example
981 $ ls target
982 aduc702x.cfg imx27.cfg pxa255.cfg
983 ar71xx.cfg imx31.cfg pxa270.cfg
984 at91eb40a.cfg imx35.cfg readme.txt
985 at91r40008.cfg is5114.cfg sam7se512.cfg
986 at91rm9200.cfg ixp42x.cfg sam7x256.cfg
987 at91sam3u1c.cfg lm3s1968.cfg samsung_s3c2410.cfg
988 at91sam3u1e.cfg lm3s3748.cfg samsung_s3c2440.cfg
989 at91sam3u2c.cfg lm3s6965.cfg samsung_s3c2450.cfg
990 at91sam3u2e.cfg lm3s811.cfg samsung_s3c4510.cfg
991 at91sam3u4c.cfg lm3s9b9x.cfg samsung_s3c6410.cfg
992 at91sam3u4e.cfg lpc1768.cfg sharp_lh79532.cfg
993 at91sam3uXX.cfg lpc2103.cfg smdk6410.cfg
994 at91sam7sx.cfg lpc2124.cfg smp8634.cfg
995 at91sam9260.cfg lpc2129.cfg stm32.cfg
996 c100.cfg lpc2148.cfg str710.cfg
997 c100config.tcl lpc2294.cfg str730.cfg
998 c100helper.tcl lpc2378.cfg str750.cfg
999 c100regs.tcl lpc2478.cfg str912.cfg
1000 cs351x.cfg lpc2900.cfg telo.cfg
1001 davinci.cfg mega128.cfg ti_dm355.cfg
1002 dragonite.cfg netx500.cfg ti_dm365.cfg
1003 epc9301.cfg omap2420.cfg ti_dm6446.cfg
1004 feroceon.cfg omap3530.cfg tmpa900.cfg
1005 icepick.cfg omap5912.cfg tmpa910.cfg
1006 imx21.cfg pic32mx.cfg xba_revA3.cfg
1007 $
1008 @end example
1009 @item @emph{more} ... browse for other library files which may be useful.
1010 For example, there are various generic and CPU-specific utilities.
1011 @end itemize
1012
1013 The @file{openocd.cfg} user config
1014 file may override features in any of the above files by
1015 setting variables before sourcing the target file, or by adding
1016 commands specific to their situation.
1017
1018 @section Interface Config Files
1019
1020 The user config file
1021 should be able to source one of these files with a command like this:
1022
1023 @example
1024 source [find interface/FOOBAR.cfg]
1025 @end example
1026
1027 A preconfigured interface file should exist for every interface in use
1028 today, that said, perhaps some interfaces have only been used by the
1029 sole developer who created it.
1030
1031 A separate chapter gives information about how to set these up.
1032 @xref{Interface - Dongle Configuration}.
1033 Read the OpenOCD source code if you have a new kind of hardware interface
1034 and need to provide a driver for it.
1035
1036 @section Board Config Files
1037 @cindex config file, board
1038 @cindex board config file
1039
1040 The user config file
1041 should be able to source one of these files with a command like this:
1042
1043 @example
1044 source [find board/FOOBAR.cfg]
1045 @end example
1046
1047 The point of a board config file is to package everything
1048 about a given board that user config files need to know.
1049 In summary the board files should contain (if present)
1050
1051 @enumerate
1052 @item One or more @command{source [target/...cfg]} statements
1053 @item NOR flash configuration (@pxref{NOR Configuration})
1054 @item NAND flash configuration (@pxref{NAND Configuration})
1055 @item Target @code{reset} handlers for SDRAM and I/O configuration
1056 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1057 @item All things that are not ``inside a chip''
1058 @end enumerate
1059
1060 Generic things inside target chips belong in target config files,
1061 not board config files. So for example a @code{reset-init} event
1062 handler should know board-specific oscillator and PLL parameters,
1063 which it passes to target-specific utility code.
1064
1065 The most complex task of a board config file is creating such a
1066 @code{reset-init} event handler.
1067 Define those handlers last, after you verify the rest of the board
1068 configuration works.
1069
1070 @subsection Communication Between Config files
1071
1072 In addition to target-specific utility code, another way that
1073 board and target config files communicate is by following a
1074 convention on how to use certain variables.
1075
1076 The full Tcl/Tk language supports ``namespaces'', but JIM-Tcl does not.
1077 Thus the rule we follow in OpenOCD is this: Variables that begin with
1078 a leading underscore are temporary in nature, and can be modified and
1079 used at will within a target configuration file.
1080
1081 Complex board config files can do the things like this,
1082 for a board with three chips:
1083
1084 @example
1085 # Chip #1: PXA270 for network side, big endian
1086 set CHIPNAME network
1087 set ENDIAN big
1088 source [find target/pxa270.cfg]
1089 # on return: _TARGETNAME = network.cpu
1090 # other commands can refer to the "network.cpu" target.
1091 $_TARGETNAME configure .... events for this CPU..
1092
1093 # Chip #2: PXA270 for video side, little endian
1094 set CHIPNAME video
1095 set ENDIAN little
1096 source [find target/pxa270.cfg]
1097 # on return: _TARGETNAME = video.cpu
1098 # other commands can refer to the "video.cpu" target.
1099 $_TARGETNAME configure .... events for this CPU..
1100
1101 # Chip #3: Xilinx FPGA for glue logic
1102 set CHIPNAME xilinx
1103 unset ENDIAN
1104 source [find target/spartan3.cfg]
1105 @end example
1106
1107 That example is oversimplified because it doesn't show any flash memory,
1108 or the @code{reset-init} event handlers to initialize external DRAM
1109 or (assuming it needs it) load a configuration into the FPGA.
1110 Such features are usually needed for low-level work with many boards,
1111 where ``low level'' implies that the board initialization software may
1112 not be working. (That's a common reason to need JTAG tools. Another
1113 is to enable working with microcontroller-based systems, which often
1114 have no debugging support except a JTAG connector.)
1115
1116 Target config files may also export utility functions to board and user
1117 config files. Such functions should use name prefixes, to help avoid
1118 naming collisions.
1119
1120 Board files could also accept input variables from user config files.
1121 For example, there might be a @code{J4_JUMPER} setting used to identify
1122 what kind of flash memory a development board is using, or how to set
1123 up other clocks and peripherals.
1124
1125 @subsection Variable Naming Convention
1126 @cindex variable names
1127
1128 Most boards have only one instance of a chip.
1129 However, it should be easy to create a board with more than
1130 one such chip (as shown above).
1131 Accordingly, we encourage these conventions for naming
1132 variables associated with different @file{target.cfg} files,
1133 to promote consistency and
1134 so that board files can override target defaults.
1135
1136 Inputs to target config files include:
1137
1138 @itemize @bullet
1139 @item @code{CHIPNAME} ...
1140 This gives a name to the overall chip, and is used as part of
1141 tap identifier dotted names.
1142 While the default is normally provided by the chip manufacturer,
1143 board files may need to distinguish between instances of a chip.
1144 @item @code{ENDIAN} ...
1145 By default @option{little} - although chips may hard-wire @option{big}.
1146 Chips that can't change endianness don't need to use this variable.
1147 @item @code{CPUTAPID} ...
1148 When OpenOCD examines the JTAG chain, it can be told verify the
1149 chips against the JTAG IDCODE register.
1150 The target file will hold one or more defaults, but sometimes the
1151 chip in a board will use a different ID (perhaps a newer revision).
1152 @end itemize
1153
1154 Outputs from target config files include:
1155
1156 @itemize @bullet
1157 @item @code{_TARGETNAME} ...
1158 By convention, this variable is created by the target configuration
1159 script. The board configuration file may make use of this variable to
1160 configure things like a ``reset init'' script, or other things
1161 specific to that board and that target.
1162 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1163 @code{_TARGETNAME1}, ... etc.
1164 @end itemize
1165
1166 @subsection The reset-init Event Handler
1167 @cindex event, reset-init
1168 @cindex reset-init handler
1169
1170 Board config files run in the OpenOCD configuration stage;
1171 they can't use TAPs or targets, since they haven't been
1172 fully set up yet.
1173 This means you can't write memory or access chip registers;
1174 you can't even verify that a flash chip is present.
1175 That's done later in event handlers, of which the target @code{reset-init}
1176 handler is one of the most important.
1177
1178 Except on microcontrollers, the basic job of @code{reset-init} event
1179 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1180 Microcontrollers rarely use boot loaders; they run right out of their
1181 on-chip flash and SRAM memory. But they may want to use one of these
1182 handlers too, if just for developer convenience.
1183
1184 @quotation Note
1185 Because this is so very board-specific, and chip-specific, no examples
1186 are included here.
1187 Instead, look at the board config files distributed with OpenOCD.
1188 If you have a boot loader, its source code will help; so will
1189 configuration files for other JTAG tools
1190 (@pxref{Translating Configuration Files}).
1191 @end quotation
1192
1193 Some of this code could probably be shared between different boards.
1194 For example, setting up a DRAM controller often doesn't differ by
1195 much except the bus width (16 bits or 32?) and memory timings, so a
1196 reusable TCL procedure loaded by the @file{target.cfg} file might take
1197 those as parameters.
1198 Similarly with oscillator, PLL, and clock setup;
1199 and disabling the watchdog.
1200 Structure the code cleanly, and provide comments to help
1201 the next developer doing such work.
1202 (@emph{You might be that next person} trying to reuse init code!)
1203
1204 The last thing normally done in a @code{reset-init} handler is probing
1205 whatever flash memory was configured. For most chips that needs to be
1206 done while the associated target is halted, either because JTAG memory
1207 access uses the CPU or to prevent conflicting CPU access.
1208
1209 @subsection JTAG Clock Rate
1210
1211 Before your @code{reset-init} handler has set up
1212 the PLLs and clocking, you may need to run with
1213 a low JTAG clock rate.
1214 @xref{JTAG Speed}.
1215 Then you'd increase that rate after your handler has
1216 made it possible to use the faster JTAG clock.
1217 When the initial low speed is board-specific, for example
1218 because it depends on a board-specific oscillator speed, then
1219 you should probably set it up in the board config file;
1220 if it's target-specific, it belongs in the target config file.
1221
1222 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1223 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1224 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1225 Consult chip documentation to determine the peak JTAG clock rate,
1226 which might be less than that.
1227
1228 @quotation Warning
1229 On most ARMs, JTAG clock detection is coupled to the core clock, so
1230 software using a @option{wait for interrupt} operation blocks JTAG access.
1231 Adaptive clocking provides a partial workaround, but a more complete
1232 solution just avoids using that instruction with JTAG debuggers.
1233 @end quotation
1234
1235 If the board supports adaptive clocking, use the @command{jtag_rclk}
1236 command, in case your board is used with JTAG adapter which
1237 also supports it. Otherwise use @command{jtag_khz}.
1238 Set the slow rate at the beginning of the reset sequence,
1239 and the faster rate as soon as the clocks are at full speed.
1240
1241 @section Target Config Files
1242 @cindex config file, target
1243 @cindex target config file
1244
1245 Board config files communicate with target config files using
1246 naming conventions as described above, and may source one or
1247 more target config files like this:
1248
1249 @example
1250 source [find target/FOOBAR.cfg]
1251 @end example
1252
1253 The point of a target config file is to package everything
1254 about a given chip that board config files need to know.
1255 In summary the target files should contain
1256
1257 @enumerate
1258 @item Set defaults
1259 @item Add TAPs to the scan chain
1260 @item Add CPU targets (includes GDB support)
1261 @item CPU/Chip/CPU-Core specific features
1262 @item On-Chip flash
1263 @end enumerate
1264
1265 As a rule of thumb, a target file sets up only one chip.
1266 For a microcontroller, that will often include a single TAP,
1267 which is a CPU needing a GDB target, and its on-chip flash.
1268
1269 More complex chips may include multiple TAPs, and the target
1270 config file may need to define them all before OpenOCD
1271 can talk to the chip.
1272 For example, some phone chips have JTAG scan chains that include
1273 an ARM core for operating system use, a DSP,
1274 another ARM core embedded in an image processing engine,
1275 and other processing engines.
1276
1277 @subsection Default Value Boiler Plate Code
1278
1279 All target configuration files should start with code like this,
1280 letting board config files express environment-specific
1281 differences in how things should be set up.
1282
1283 @example
1284 # Boards may override chip names, perhaps based on role,
1285 # but the default should match what the vendor uses
1286 if @{ [info exists CHIPNAME] @} @{
1287 set _CHIPNAME $CHIPNAME
1288 @} else @{
1289 set _CHIPNAME sam7x256
1290 @}
1291
1292 # ONLY use ENDIAN with targets that can change it.
1293 if @{ [info exists ENDIAN] @} @{
1294 set _ENDIAN $ENDIAN
1295 @} else @{
1296 set _ENDIAN little
1297 @}
1298
1299 # TAP identifiers may change as chips mature, for example with
1300 # new revision fields (the "3" here). Pick a good default; you
1301 # can pass several such identifiers to the "jtag newtap" command.
1302 if @{ [info exists CPUTAPID ] @} @{
1303 set _CPUTAPID $CPUTAPID
1304 @} else @{
1305 set _CPUTAPID 0x3f0f0f0f
1306 @}
1307 @end example
1308 @c but 0x3f0f0f0f is for an str73x part ...
1309
1310 @emph{Remember:} Board config files may include multiple target
1311 config files, or the same target file multiple times
1312 (changing at least @code{CHIPNAME}).
1313
1314 Likewise, the target configuration file should define
1315 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1316 use it later on when defining debug targets:
1317
1318 @example
1319 set _TARGETNAME $_CHIPNAME.cpu
1320 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1321 @end example
1322
1323 @subsection Adding TAPs to the Scan Chain
1324 After the ``defaults'' are set up,
1325 add the TAPs on each chip to the JTAG scan chain.
1326 @xref{TAP Declaration}, and the naming convention
1327 for taps.
1328
1329 In the simplest case the chip has only one TAP,
1330 probably for a CPU or FPGA.
1331 The config file for the Atmel AT91SAM7X256
1332 looks (in part) like this:
1333
1334 @example
1335 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
1336 -expected-id $_CPUTAPID
1337 @end example
1338
1339 A board with two such at91sam7 chips would be able
1340 to source such a config file twice, with different
1341 values for @code{CHIPNAME}, so
1342 it adds a different TAP each time.
1343
1344 If there are nonzero @option{-expected-id} values,
1345 OpenOCD attempts to verify the actual tap id against those values.
1346 It will issue error messages if there is mismatch, which
1347 can help to pinpoint problems in OpenOCD configurations.
1348
1349 @example
1350 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1351 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1352 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1353 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1354 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1355 @end example
1356
1357 There are more complex examples too, with chips that have
1358 multiple TAPs. Ones worth looking at include:
1359
1360 @itemize
1361 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1362 plus a JRC to enable them
1363 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1364 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1365 is not currently used)
1366 @end itemize
1367
1368 @subsection Add CPU targets
1369
1370 After adding a TAP for a CPU, you should set it up so that
1371 GDB and other commands can use it.
1372 @xref{CPU Configuration}.
1373 For the at91sam7 example above, the command can look like this;
1374 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1375 to little endian, and this chip doesn't support changing that.
1376
1377 @example
1378 set _TARGETNAME $_CHIPNAME.cpu
1379 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1380 @end example
1381
1382 Work areas are small RAM areas associated with CPU targets.
1383 They are used by OpenOCD to speed up downloads,
1384 and to download small snippets of code to program flash chips.
1385 If the chip includes a form of ``on-chip-ram'' - and many do - define
1386 a work area if you can.
1387 Again using the at91sam7 as an example, this can look like:
1388
1389 @example
1390 $_TARGETNAME configure -work-area-phys 0x00200000 \
1391 -work-area-size 0x4000 -work-area-backup 0
1392 @end example
1393
1394 @subsection Chip Reset Setup
1395
1396 As a rule, you should put the @command{reset_config} command
1397 into the board file. Most things you think you know about a
1398 chip can be tweaked by the board.
1399
1400 Some chips have specific ways the TRST and SRST signals are
1401 managed. In the unusual case that these are @emph{chip specific}
1402 and can never be changed by board wiring, they could go here.
1403
1404 Some chips need special attention during reset handling if
1405 they're going to be used with JTAG.
1406 An example might be needing to send some commands right
1407 after the target's TAP has been reset, providing a
1408 @code{reset-deassert-post} event handler that writes a chip
1409 register to report that JTAG debugging is being done.
1410
1411 JTAG clocking constraints often change during reset, and in
1412 some cases target config files (rather than board config files)
1413 are the right places to handle some of those issues.
1414 For example, immediately after reset most chips run using a
1415 slower clock than they will use later.
1416 That means that after reset (and potentially, as OpenOCD
1417 first starts up) they must use a slower JTAG clock rate
1418 than they will use later.
1419 @xref{JTAG Speed}.
1420
1421 @quotation Important
1422 When you are debugging code that runs right after chip
1423 reset, getting these issues right is critical.
1424 In particular, if you see intermittent failures when
1425 OpenOCD verifies the scan chain after reset,
1426 look at how you are setting up JTAG clocking.
1427 @end quotation
1428
1429 @subsection ARM Core Specific Hacks
1430
1431 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1432 special high speed download features - enable it.
1433
1434 If present, the MMU, the MPU and the CACHE should be disabled.
1435
1436 Some ARM cores are equipped with trace support, which permits
1437 examination of the instruction and data bus activity. Trace
1438 activity is controlled through an ``Embedded Trace Module'' (ETM)
1439 on one of the core's scan chains. The ETM emits voluminous data
1440 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
1441 If you are using an external trace port,
1442 configure it in your board config file.
1443 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1444 configure it in your target config file.
1445
1446 @example
1447 etm config $_TARGETNAME 16 normal full etb
1448 etb config $_TARGETNAME $_CHIPNAME.etb
1449 @end example
1450
1451 @subsection Internal Flash Configuration
1452
1453 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1454
1455 @b{Never ever} in the ``target configuration file'' define any type of
1456 flash that is external to the chip. (For example a BOOT flash on
1457 Chip Select 0.) Such flash information goes in a board file - not
1458 the TARGET (chip) file.
1459
1460 Examples:
1461 @itemize @bullet
1462 @item at91sam7x256 - has 256K flash YES enable it.
1463 @item str912 - has flash internal YES enable it.
1464 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1465 @item pxa270 - again - CS0 flash - it goes in the board file.
1466 @end itemize
1467
1468 @anchor{Translating Configuration Files}
1469 @section Translating Configuration Files
1470 @cindex translation
1471 If you have a configuration file for another hardware debugger
1472 or toolset (Abatron, BDI2000, BDI3000, CCS,
1473 Lauterbach, Segger, Macraigor, etc.), translating
1474 it into OpenOCD syntax is often quite straightforward. The most tricky
1475 part of creating a configuration script is oftentimes the reset init
1476 sequence where e.g. PLLs, DRAM and the like is set up.
1477
1478 One trick that you can use when translating is to write small
1479 Tcl procedures to translate the syntax into OpenOCD syntax. This
1480 can avoid manual translation errors and make it easier to
1481 convert other scripts later on.
1482
1483 Example of transforming quirky arguments to a simple search and
1484 replace job:
1485
1486 @example
1487 # Lauterbach syntax(?)
1488 #
1489 # Data.Set c15:0x042f %long 0x40000015
1490 #
1491 # OpenOCD syntax when using procedure below.
1492 #
1493 # setc15 0x01 0x00050078
1494
1495 proc setc15 @{regs value@} @{
1496 global TARGETNAME
1497
1498 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
1499
1500 arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] \
1501 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
1502 [expr ($regs>>8)&0x7] $value
1503 @}
1504 @end example
1505
1506
1507
1508 @node Daemon Configuration
1509 @chapter Daemon Configuration
1510 @cindex initialization
1511 The commands here are commonly found in the openocd.cfg file and are
1512 used to specify what TCP/IP ports are used, and how GDB should be
1513 supported.
1514
1515 @anchor{Configuration Stage}
1516 @section Configuration Stage
1517 @cindex configuration stage
1518 @cindex config command
1519
1520 When the OpenOCD server process starts up, it enters a
1521 @emph{configuration stage} which is the only time that
1522 certain commands, @emph{configuration commands}, may be issued.
1523 In this manual, the definition of a configuration command is
1524 presented as a @emph{Config Command}, not as a @emph{Command}
1525 which may be issued interactively.
1526
1527 Those configuration commands include declaration of TAPs,
1528 flash banks,
1529 the interface used for JTAG communication,
1530 and other basic setup.
1531 The server must leave the configuration stage before it
1532 may access or activate TAPs.
1533 After it leaves this stage, configuration commands may no
1534 longer be issued.
1535
1536 The first thing OpenOCD does after leaving the configuration
1537 stage is to verify that it can talk to the scan chain
1538 (list of TAPs) which has been configured.
1539 It will warn if it doesn't find TAPs it expects to find,
1540 or finds TAPs that aren't supposed to be there.
1541 You should see no errors at this point.
1542 If you see errors, resolve them by correcting the
1543 commands you used to configure the server.
1544 Common errors include using an initial JTAG speed that's too
1545 fast, and not providing the right IDCODE values for the TAPs
1546 on the scan chain.
1547
1548 @deffn {Config Command} init
1549 This command terminates the configuration stage and
1550 enters the normal command mode. This can be useful to add commands to
1551 the startup scripts and commands such as resetting the target,
1552 programming flash, etc. To reset the CPU upon startup, add "init" and
1553 "reset" at the end of the config script or at the end of the OpenOCD
1554 command line using the @option{-c} command line switch.
1555
1556 If this command does not appear in any startup/configuration file
1557 OpenOCD executes the command for you after processing all
1558 configuration files and/or command line options.
1559
1560 @b{NOTE:} This command normally occurs at or near the end of your
1561 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1562 targets ready. For example: If your openocd.cfg file needs to
1563 read/write memory on your target, @command{init} must occur before
1564 the memory read/write commands. This includes @command{nand probe}.
1565 @end deffn
1566
1567 @deffn {Overridable Procedure} jtag_init
1568 This is invoked at server startup to verify that it can talk
1569 to the scan chain (list of TAPs) which has been configured.
1570
1571 The default implementation first tries @command{jtag arp_init},
1572 which uses only a lightweight JTAG reset before examining the
1573 scan chain.
1574 If that fails, it tries again, using a harder reset
1575 from the overridable procedure @command{init_reset}.
1576
1577 Implementations must have verified the JTAG scan chain before
1578 they return.
1579 This is done by calling @command{jtag arp_init}
1580 (or @command{jtag arp_init-reset}).
1581 @end deffn
1582
1583 @anchor{TCP/IP Ports}
1584 @section TCP/IP Ports
1585 @cindex TCP port
1586 @cindex server
1587 @cindex port
1588 @cindex security
1589 The OpenOCD server accepts remote commands in several syntaxes.
1590 Each syntax uses a different TCP/IP port, which you may specify
1591 only during configuration (before those ports are opened).
1592
1593 For reasons including security, you may wish to prevent remote
1594 access using one or more of these ports.
1595 In such cases, just specify the relevant port number as zero.
1596 If you disable all access through TCP/IP, you will need to
1597 use the command line @option{-pipe} option.
1598
1599 @deffn {Command} gdb_port (number)
1600 @cindex GDB server
1601 Specify or query the first port used for incoming GDB connections.
1602 The GDB port for the
1603 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1604 When not specified during the configuration stage,
1605 the port @var{number} defaults to 3333.
1606 When specified as zero, this port is not activated.
1607 @end deffn
1608
1609 @deffn {Command} tcl_port (number)
1610 Specify or query the port used for a simplified RPC
1611 connection that can be used by clients to issue TCL commands and get the
1612 output from the Tcl engine.
1613 Intended as a machine interface.
1614 When not specified during the configuration stage,
1615 the port @var{number} defaults to 6666.
1616 When specified as zero, this port is not activated.
1617 @end deffn
1618
1619 @deffn {Command} telnet_port (number)
1620 Specify or query the
1621 port on which to listen for incoming telnet connections.
1622 This port is intended for interaction with one human through TCL commands.
1623 When not specified during the configuration stage,
1624 the port @var{number} defaults to 4444.
1625 When specified as zero, this port is not activated.
1626 @end deffn
1627
1628 @anchor{GDB Configuration}
1629 @section GDB Configuration
1630 @cindex GDB
1631 @cindex GDB configuration
1632 You can reconfigure some GDB behaviors if needed.
1633 The ones listed here are static and global.
1634 @xref{Target Configuration}, about configuring individual targets.
1635 @xref{Target Events}, about configuring target-specific event handling.
1636
1637 @anchor{gdb_breakpoint_override}
1638 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
1639 Force breakpoint type for gdb @command{break} commands.
1640 This option supports GDB GUIs which don't
1641 distinguish hard versus soft breakpoints, if the default OpenOCD and
1642 GDB behaviour is not sufficient. GDB normally uses hardware
1643 breakpoints if the memory map has been set up for flash regions.
1644 @end deffn
1645
1646 @anchor{gdb_flash_program}
1647 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
1648 Set to @option{enable} to cause OpenOCD to program the flash memory when a
1649 vFlash packet is received.
1650 The default behaviour is @option{enable}.
1651 @end deffn
1652
1653 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
1654 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
1655 requested. GDB will then know when to set hardware breakpoints, and program flash
1656 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1657 for flash programming to work.
1658 Default behaviour is @option{enable}.
1659 @xref{gdb_flash_program}.
1660 @end deffn
1661
1662 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
1663 Specifies whether data aborts cause an error to be reported
1664 by GDB memory read packets.
1665 The default behaviour is @option{disable};
1666 use @option{enable} see these errors reported.
1667 @end deffn
1668
1669 @anchor{Event Polling}
1670 @section Event Polling
1671
1672 Hardware debuggers are parts of asynchronous systems,
1673 where significant events can happen at any time.
1674 The OpenOCD server needs to detect some of these events,
1675 so it can report them to through TCL command line
1676 or to GDB.
1677
1678 Examples of such events include:
1679
1680 @itemize
1681 @item One of the targets can stop running ... maybe it triggers
1682 a code breakpoint or data watchpoint, or halts itself.
1683 @item Messages may be sent over ``debug message'' channels ... many
1684 targets support such messages sent over JTAG,
1685 for receipt by the person debugging or tools.
1686 @item Loss of power ... some adapters can detect these events.
1687 @item Resets not issued through JTAG ... such reset sources
1688 can include button presses or other system hardware, sometimes
1689 including the target itself (perhaps through a watchdog).
1690 @item Debug instrumentation sometimes supports event triggering
1691 such as ``trace buffer full'' (so it can quickly be emptied)
1692 or other signals (to correlate with code behavior).
1693 @end itemize
1694
1695 None of those events are signaled through standard JTAG signals.
1696 However, most conventions for JTAG connectors include voltage
1697 level and system reset (SRST) signal detection.
1698 Some connectors also include instrumentation signals, which
1699 can imply events when those signals are inputs.
1700
1701 In general, OpenOCD needs to periodically check for those events,
1702 either by looking at the status of signals on the JTAG connector
1703 or by sending synchronous ``tell me your status'' JTAG requests
1704 to the various active targets.
1705 There is a command to manage and monitor that polling,
1706 which is normally done in the background.
1707
1708 @deffn Command poll [@option{on}|@option{off}]
1709 Poll the current target for its current state.
1710 (Also, @pxref{target curstate}.)
1711 If that target is in debug mode, architecture
1712 specific information about the current state is printed.
1713 An optional parameter
1714 allows background polling to be enabled and disabled.
1715
1716 You could use this from the TCL command shell, or
1717 from GDB using @command{monitor poll} command.
1718 @example
1719 > poll
1720 background polling: on
1721 target state: halted
1722 target halted in ARM state due to debug-request, \
1723 current mode: Supervisor
1724 cpsr: 0x800000d3 pc: 0x11081bfc
1725 MMU: disabled, D-Cache: disabled, I-Cache: enabled
1726 >
1727 @end example
1728 @end deffn
1729
1730 @node Interface - Dongle Configuration
1731 @chapter Interface - Dongle Configuration
1732 @cindex config file, interface
1733 @cindex interface config file
1734
1735 JTAG Adapters/Interfaces/Dongles are normally configured
1736 through commands in an interface configuration
1737 file which is sourced by your @file{openocd.cfg} file, or
1738 through a command line @option{-f interface/....cfg} option.
1739
1740 @example
1741 source [find interface/olimex-jtag-tiny.cfg]
1742 @end example
1743
1744 These commands tell
1745 OpenOCD what type of JTAG adapter you have, and how to talk to it.
1746 A few cases are so simple that you only need to say what driver to use:
1747
1748 @example
1749 # jlink interface
1750 interface jlink
1751 @end example
1752
1753 Most adapters need a bit more configuration than that.
1754
1755
1756 @section Interface Configuration
1757
1758 The interface command tells OpenOCD what type of JTAG dongle you are
1759 using. Depending on the type of dongle, you may need to have one or
1760 more additional commands.
1761
1762 @deffn {Config Command} {interface} name
1763 Use the interface driver @var{name} to connect to the
1764 target.
1765 @end deffn
1766
1767 @deffn Command {interface_list}
1768 List the interface drivers that have been built into
1769 the running copy of OpenOCD.
1770 @end deffn
1771
1772 @deffn Command {jtag interface}
1773 Returns the name of the interface driver being used.
1774 @end deffn
1775
1776 @section Interface Drivers
1777
1778 Each of the interface drivers listed here must be explicitly
1779 enabled when OpenOCD is configured, in order to be made
1780 available at run time.
1781
1782 @deffn {Interface Driver} {amt_jtagaccel}
1783 Amontec Chameleon in its JTAG Accelerator configuration,
1784 connected to a PC's EPP mode parallel port.
1785 This defines some driver-specific commands:
1786
1787 @deffn {Config Command} {parport_port} number
1788 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1789 the number of the @file{/dev/parport} device.
1790 @end deffn
1791
1792 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
1793 Displays status of RTCK option.
1794 Optionally sets that option first.
1795 @end deffn
1796 @end deffn
1797
1798 @deffn {Interface Driver} {arm-jtag-ew}
1799 Olimex ARM-JTAG-EW USB adapter
1800 This has one driver-specific command:
1801
1802 @deffn Command {armjtagew_info}
1803 Logs some status
1804 @end deffn
1805 @end deffn
1806
1807 @deffn {Interface Driver} {at91rm9200}
1808 Supports bitbanged JTAG from the local system,
1809 presuming that system is an Atmel AT91rm9200
1810 and a specific set of GPIOs is used.
1811 @c command: at91rm9200_device NAME
1812 @c chooses among list of bit configs ... only one option
1813 @end deffn
1814
1815 @deffn {Interface Driver} {dummy}
1816 A dummy software-only driver for debugging.
1817 @end deffn
1818
1819 @deffn {Interface Driver} {ep93xx}
1820 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1821 @end deffn
1822
1823 @deffn {Interface Driver} {ft2232}
1824 FTDI FT2232 (USB) based devices over one of the userspace libraries.
1825 These interfaces have several commands, used to configure the driver
1826 before initializing the JTAG scan chain:
1827
1828 @deffn {Config Command} {ft2232_device_desc} description
1829 Provides the USB device description (the @emph{iProduct string})
1830 of the FTDI FT2232 device. If not
1831 specified, the FTDI default value is used. This setting is only valid
1832 if compiled with FTD2XX support.
1833 @end deffn
1834
1835 @deffn {Config Command} {ft2232_serial} serial-number
1836 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
1837 in case the vendor provides unique IDs and more than one FT2232 device
1838 is connected to the host.
1839 If not specified, serial numbers are not considered.
1840 (Note that USB serial numbers can be arbitrary Unicode strings,
1841 and are not restricted to containing only decimal digits.)
1842 @end deffn
1843
1844 @deffn {Config Command} {ft2232_layout} name
1845 Each vendor's FT2232 device can use different GPIO signals
1846 to control output-enables, reset signals, and LEDs.
1847 Currently valid layout @var{name} values include:
1848 @itemize @minus
1849 @item @b{axm0432_jtag} Axiom AXM-0432
1850 @item @b{comstick} Hitex STR9 comstick
1851 @item @b{cortino} Hitex Cortino JTAG interface
1852 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
1853 either for the local Cortex-M3 (SRST only)
1854 or in a passthrough mode (neither SRST nor TRST)
1855 @item @b{luminary_icdi} Luminary In-Circuit Debug Interface (ICDI) Board
1856 @item @b{flyswatter} Tin Can Tools Flyswatter
1857 @item @b{icebear} ICEbear JTAG adapter from Section 5
1858 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
1859 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
1860 @item @b{m5960} American Microsystems M5960
1861 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
1862 @item @b{oocdlink} OOCDLink
1863 @c oocdlink ~= jtagkey_prototype_v1
1864 @item @b{sheevaplug} Marvell Sheevaplug development kit
1865 @item @b{signalyzer} Xverve Signalyzer
1866 @item @b{stm32stick} Hitex STM32 Performance Stick
1867 @item @b{turtelizer2} egnite Software turtelizer2
1868 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
1869 @end itemize
1870 @end deffn
1871
1872 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
1873 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1874 default values are used.
1875 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
1876 @example
1877 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1878 @end example
1879 @end deffn
1880
1881 @deffn {Config Command} {ft2232_latency} ms
1882 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1883 ft2232_read() fails to return the expected number of bytes. This can be caused by
1884 USB communication delays and has proved hard to reproduce and debug. Setting the
1885 FT2232 latency timer to a larger value increases delays for short USB packets but it
1886 also reduces the risk of timeouts before receiving the expected number of bytes.
1887 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1888 @end deffn
1889
1890 For example, the interface config file for a
1891 Turtelizer JTAG Adapter looks something like this:
1892
1893 @example
1894 interface ft2232
1895 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
1896 ft2232_layout turtelizer2
1897 ft2232_vid_pid 0x0403 0xbdc8
1898 @end example
1899 @end deffn
1900
1901 @deffn {Interface Driver} {gw16012}
1902 Gateworks GW16012 JTAG programmer.
1903 This has one driver-specific command:
1904
1905 @deffn {Config Command} {parport_port} number
1906 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1907 the number of the @file{/dev/parport} device.
1908 @end deffn
1909 @end deffn
1910
1911 @deffn {Interface Driver} {jlink}
1912 Segger jlink USB adapter
1913 @c command: jlink_info
1914 @c dumps status
1915 @c command: jlink_hw_jtag (2|3)
1916 @c sets version 2 or 3
1917 @end deffn
1918
1919 @deffn {Interface Driver} {parport}
1920 Supports PC parallel port bit-banging cables:
1921 Wigglers, PLD download cable, and more.
1922 These interfaces have several commands, used to configure the driver
1923 before initializing the JTAG scan chain:
1924
1925 @deffn {Config Command} {parport_cable} name
1926 The layout of the parallel port cable used to connect to the target.
1927 Currently valid cable @var{name} values include:
1928
1929 @itemize @minus
1930 @item @b{altium} Altium Universal JTAG cable.
1931 @item @b{arm-jtag} Same as original wiggler except SRST and
1932 TRST connections reversed and TRST is also inverted.
1933 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
1934 in configuration mode. This is only used to
1935 program the Chameleon itself, not a connected target.
1936 @item @b{dlc5} The Xilinx Parallel cable III.
1937 @item @b{flashlink} The ST Parallel cable.
1938 @item @b{lattice} Lattice ispDOWNLOAD Cable
1939 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
1940 some versions of
1941 Amontec's Chameleon Programmer. The new version available from
1942 the website uses the original Wiggler layout ('@var{wiggler}')
1943 @item @b{triton} The parallel port adapter found on the
1944 ``Karo Triton 1 Development Board''.
1945 This is also the layout used by the HollyGates design
1946 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1947 @item @b{wiggler} The original Wiggler layout, also supported by
1948 several clones, such as the Olimex ARM-JTAG
1949 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
1950 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
1951 @end itemize
1952 @end deffn
1953
1954 @deffn {Config Command} {parport_port} number
1955 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1956 the @file{/dev/parport} device
1957
1958 When using PPDEV to access the parallel port, use the number of the parallel port:
1959 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1960 you may encounter a problem.
1961 @end deffn
1962
1963 @deffn {Config Command} {parport_write_on_exit} (on|off)
1964 This will configure the parallel driver to write a known
1965 cable-specific value to the parallel interface on exiting OpenOCD
1966 @end deffn
1967
1968 For example, the interface configuration file for a
1969 classic ``Wiggler'' cable might look something like this:
1970
1971 @example
1972 interface parport
1973 parport_port 0xc8b8
1974 parport_cable wiggler
1975 @end example
1976 @end deffn
1977
1978 @deffn {Interface Driver} {presto}
1979 ASIX PRESTO USB JTAG programmer.
1980 @c command: presto_serial str
1981 @c sets serial number
1982 @end deffn
1983
1984 @deffn {Interface Driver} {rlink}
1985 Raisonance RLink USB adapter
1986 @end deffn
1987
1988 @deffn {Interface Driver} {usbprog}
1989 usbprog is a freely programmable USB adapter.
1990 @end deffn
1991
1992 @deffn {Interface Driver} {vsllink}
1993 vsllink is part of Versaloon which is a versatile USB programmer.
1994
1995 @quotation Note
1996 This defines quite a few driver-specific commands,
1997 which are not currently documented here.
1998 @end quotation
1999 @end deffn
2000
2001 @deffn {Interface Driver} {ZY1000}
2002 This is the Zylin ZY1000 JTAG debugger.
2003
2004 @quotation Note
2005 This defines some driver-specific commands,
2006 which are not currently documented here.
2007 @end quotation
2008
2009 @deffn Command power [@option{on}|@option{off}]
2010 Turn power switch to target on/off.
2011 No arguments: print status.
2012 @end deffn
2013
2014 @end deffn
2015
2016 @anchor{JTAG Speed}
2017 @section JTAG Speed
2018 JTAG clock setup is part of system setup.
2019 It @emph{does not belong with interface setup} since any interface
2020 only knows a few of the constraints for the JTAG clock speed.
2021 Sometimes the JTAG speed is
2022 changed during the target initialization process: (1) slow at
2023 reset, (2) program the CPU clocks, (3) run fast.
2024 Both the "slow" and "fast" clock rates are functions of the
2025 oscillators used, the chip, the board design, and sometimes
2026 power management software that may be active.
2027
2028 The speed used during reset, and the scan chain verification which
2029 follows reset, can be adjusted using a @code{reset-start}
2030 target event handler.
2031 It can then be reconfigured to a faster speed by a
2032 @code{reset-init} target event handler after it reprograms those
2033 CPU clocks, or manually (if something else, such as a boot loader,
2034 sets up those clocks).
2035 @xref{Target Events}.
2036 When the initial low JTAG speed is a chip characteristic, perhaps
2037 because of a required oscillator speed, provide such a handler
2038 in the target config file.
2039 When that speed is a function of a board-specific characteristic
2040 such as which speed oscillator is used, it belongs in the board
2041 config file instead.
2042 In both cases it's safest to also set the initial JTAG clock rate
2043 to that same slow speed, so that OpenOCD never starts up using a
2044 clock speed that's faster than the scan chain can support.
2045
2046 @example
2047 jtag_rclk 3000
2048 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
2049 @end example
2050
2051 If your system supports adaptive clocking (RTCK), configuring
2052 JTAG to use that is probably the most robust approach.
2053 However, it introduces delays to synchronize clocks; so it
2054 may not be the fastest solution.
2055
2056 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
2057 instead of @command{jtag_khz}.
2058
2059 @deffn {Command} jtag_khz max_speed_kHz
2060 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
2061 JTAG interfaces usually support a limited number of
2062 speeds. The speed actually used won't be faster
2063 than the speed specified.
2064
2065 Chip data sheets generally include a top JTAG clock rate.
2066 The actual rate is often a function of a CPU core clock,
2067 and is normally less than that peak rate.
2068 For example, most ARM cores accept at most one sixth of the CPU clock.
2069
2070 Speed 0 (khz) selects RTCK method.
2071 @xref{FAQ RTCK}.
2072 If your system uses RTCK, you won't need to change the
2073 JTAG clocking after setup.
2074 Not all interfaces, boards, or targets support ``rtck''.
2075 If the interface device can not
2076 support it, an error is returned when you try to use RTCK.
2077 @end deffn
2078
2079 @defun jtag_rclk fallback_speed_kHz
2080 @cindex adaptive clocking
2081 @cindex RTCK
2082 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
2083 If that fails (maybe the interface, board, or target doesn't
2084 support it), falls back to the specified frequency.
2085 @example
2086 # Fall back to 3mhz if RTCK is not supported
2087 jtag_rclk 3000
2088 @end example
2089 @end defun
2090
2091 @node Reset Configuration
2092 @chapter Reset Configuration
2093 @cindex Reset Configuration
2094
2095 Every system configuration may require a different reset
2096 configuration. This can also be quite confusing.
2097 Resets also interact with @var{reset-init} event handlers,
2098 which do things like setting up clocks and DRAM, and
2099 JTAG clock rates. (@xref{JTAG Speed}.)
2100 They can also interact with JTAG routers.
2101 Please see the various board files for examples.
2102
2103 @quotation Note
2104 To maintainers and integrators:
2105 Reset configuration touches several things at once.
2106 Normally the board configuration file
2107 should define it and assume that the JTAG adapter supports
2108 everything that's wired up to the board's JTAG connector.
2109
2110 However, the target configuration file could also make note
2111 of something the silicon vendor has done inside the chip,
2112 which will be true for most (or all) boards using that chip.
2113 And when the JTAG adapter doesn't support everything, the
2114 user configuration file will need to override parts of
2115 the reset configuration provided by other files.
2116 @end quotation
2117
2118 @section Types of Reset
2119
2120 There are many kinds of reset possible through JTAG, but
2121 they may not all work with a given board and adapter.
2122 That's part of why reset configuration can be error prone.
2123
2124 @itemize @bullet
2125 @item
2126 @emph{System Reset} ... the @emph{SRST} hardware signal
2127 resets all chips connected to the JTAG adapter, such as processors,
2128 power management chips, and I/O controllers. Normally resets triggered
2129 with this signal behave exactly like pressing a RESET button.
2130 @item
2131 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
2132 just the TAP controllers connected to the JTAG adapter.
2133 Such resets should not be visible to the rest of the system; resetting a
2134 device's the TAP controller just puts that controller into a known state.
2135 @item
2136 @emph{Emulation Reset} ... many devices can be reset through JTAG
2137 commands. These resets are often distinguishable from system
2138 resets, either explicitly (a "reset reason" register says so)
2139 or implicitly (not all parts of the chip get reset).
2140 @item
2141 @emph{Other Resets} ... system-on-chip devices often support
2142 several other types of reset.
2143 You may need to arrange that a watchdog timer stops
2144 while debugging, preventing a watchdog reset.
2145 There may be individual module resets.
2146 @end itemize
2147
2148 In the best case, OpenOCD can hold SRST, then reset
2149 the TAPs via TRST and send commands through JTAG to halt the
2150 CPU at the reset vector before the 1st instruction is executed.
2151 Then when it finally releases the SRST signal, the system is
2152 halted under debugger control before any code has executed.
2153 This is the behavior required to support the @command{reset halt}
2154 and @command{reset init} commands; after @command{reset init} a
2155 board-specific script might do things like setting up DRAM.
2156 (@xref{Reset Command}.)
2157
2158 @anchor{SRST and TRST Issues}
2159 @section SRST and TRST Issues
2160
2161 Because SRST and TRST are hardware signals, they can have a
2162 variety of system-specific constraints. Some of the most
2163 common issues are:
2164
2165 @itemize @bullet
2166
2167 @item @emph{Signal not available} ... Some boards don't wire
2168 SRST or TRST to the JTAG connector. Some JTAG adapters don't
2169 support such signals even if they are wired up.
2170 Use the @command{reset_config} @var{signals} options to say
2171 when either of those signals is not connected.
2172 When SRST is not available, your code might not be able to rely
2173 on controllers having been fully reset during code startup.
2174 Missing TRST is not a problem, since JTAG level resets can
2175 be triggered using with TMS signaling.
2176
2177 @item @emph{Signals shorted} ... Sometimes a chip, board, or
2178 adapter will connect SRST to TRST, instead of keeping them separate.
2179 Use the @command{reset_config} @var{combination} options to say
2180 when those signals aren't properly independent.
2181
2182 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
2183 delay circuit, reset supervisor, or on-chip features can extend
2184 the effect of a JTAG adapter's reset for some time after the adapter
2185 stops issuing the reset. For example, there may be chip or board
2186 requirements that all reset pulses last for at least a
2187 certain amount of time; and reset buttons commonly have
2188 hardware debouncing.
2189 Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
2190 commands to say when extra delays are needed.
2191
2192 @item @emph{Drive type} ... Reset lines often have a pullup
2193 resistor, letting the JTAG interface treat them as open-drain
2194 signals. But that's not a requirement, so the adapter may need
2195 to use push/pull output drivers.
2196 Also, with weak pullups it may be advisable to drive
2197 signals to both levels (push/pull) to minimize rise times.
2198 Use the @command{reset_config} @var{trst_type} and
2199 @var{srst_type} parameters to say how to drive reset signals.
2200
2201 @item @emph{Special initialization} ... Targets sometimes need
2202 special JTAG initialization sequences to handle chip-specific
2203 issues (not limited to errata).
2204 For example, certain JTAG commands might need to be issued while
2205 the system as a whole is in a reset state (SRST active)
2206 but the JTAG scan chain is usable (TRST inactive).
2207 Many systems treat combined assertion of SRST and TRST as a
2208 trigger for a harder reset than SRST alone.
2209 Such custom reset handling is discussed later in this chapter.
2210 @end itemize
2211
2212 There can also be other issues.
2213 Some devices don't fully conform to the JTAG specifications.
2214 Trivial system-specific differences are common, such as
2215 SRST and TRST using slightly different names.
2216 There are also vendors who distribute key JTAG documentation for
2217 their chips only to developers who have signed a Non-Disclosure
2218 Agreement (NDA).
2219
2220 Sometimes there are chip-specific extensions like a requirement to use
2221 the normally-optional TRST signal (precluding use of JTAG adapters which
2222 don't pass TRST through), or needing extra steps to complete a TAP reset.
2223
2224 In short, SRST and especially TRST handling may be very finicky,
2225 needing to cope with both architecture and board specific constraints.
2226
2227 @section Commands for Handling Resets
2228
2229 @deffn {Command} jtag_nsrst_assert_width milliseconds
2230 Minimum amount of time (in milliseconds) OpenOCD should wait
2231 after asserting nSRST (active-low system reset) before
2232 allowing it to be deasserted.
2233 @end deffn
2234
2235 @deffn {Command} jtag_nsrst_delay milliseconds
2236 How long (in milliseconds) OpenOCD should wait after deasserting
2237 nSRST (active-low system reset) before starting new JTAG operations.
2238 When a board has a reset button connected to SRST line it will
2239 probably have hardware debouncing, implying you should use this.
2240 @end deffn
2241
2242 @deffn {Command} jtag_ntrst_assert_width milliseconds
2243 Minimum amount of time (in milliseconds) OpenOCD should wait
2244 after asserting nTRST (active-low JTAG TAP reset) before
2245 allowing it to be deasserted.
2246 @end deffn
2247
2248 @deffn {Command} jtag_ntrst_delay milliseconds
2249 How long (in milliseconds) OpenOCD should wait after deasserting
2250 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
2251 @end deffn
2252
2253 @deffn {Command} reset_config mode_flag ...
2254 This command displays or modifies the reset configuration
2255 of your combination of JTAG board and target in target
2256 configuration scripts.
2257
2258 Information earlier in this section describes the kind of problems
2259 the command is intended to address (@pxref{SRST and TRST Issues}).
2260 As a rule this command belongs only in board config files,
2261 describing issues like @emph{board doesn't connect TRST};
2262 or in user config files, addressing limitations derived
2263 from a particular combination of interface and board.
2264 (An unlikely example would be using a TRST-only adapter
2265 with a board that only wires up SRST.)
2266
2267 The @var{mode_flag} options can be specified in any order, but only one
2268 of each type -- @var{signals}, @var{combination},
2269 @var{gates},
2270 @var{trst_type},
2271 and @var{srst_type} -- may be specified at a time.
2272 If you don't provide a new value for a given type, its previous
2273 value (perhaps the default) is unchanged.
2274 For example, this means that you don't need to say anything at all about
2275 TRST just to declare that if the JTAG adapter should want to drive SRST,
2276 it must explicitly be driven high (@option{srst_push_pull}).
2277
2278 @itemize
2279 @item
2280 @var{signals} can specify which of the reset signals are connected.
2281 For example, If the JTAG interface provides SRST, but the board doesn't
2282 connect that signal properly, then OpenOCD can't use it.
2283 Possible values are @option{none} (the default), @option{trst_only},
2284 @option{srst_only} and @option{trst_and_srst}.
2285
2286 @quotation Tip
2287 If your board provides SRST and/or TRST through the JTAG connector,
2288 you must declare that so those signals can be used.
2289 @end quotation
2290
2291 @item
2292 The @var{combination} is an optional value specifying broken reset
2293 signal implementations.
2294 The default behaviour if no option given is @option{separate},
2295 indicating everything behaves normally.
2296 @option{srst_pulls_trst} states that the
2297 test logic is reset together with the reset of the system (e.g. Philips
2298 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
2299 the system is reset together with the test logic (only hypothetical, I
2300 haven't seen hardware with such a bug, and can be worked around).
2301 @option{combined} implies both @option{srst_pulls_trst} and
2302 @option{trst_pulls_srst}.
2303
2304 @item
2305 The @var{gates} tokens control flags that describe some cases where
2306 JTAG may be unvailable during reset.
2307 @option{srst_gates_jtag} (default)
2308 indicates that asserting SRST gates the
2309 JTAG clock. This means that no communication can happen on JTAG
2310 while SRST is asserted.
2311 Its converse is @option{srst_nogate}, indicating that JTAG commands
2312 can safely be issued while SRST is active.
2313 @end itemize
2314
2315 The optional @var{trst_type} and @var{srst_type} parameters allow the
2316 driver mode of each reset line to be specified. These values only affect
2317 JTAG interfaces with support for different driver modes, like the Amontec
2318 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
2319 relevant signal (TRST or SRST) is not connected.
2320
2321 @itemize
2322 @item
2323 Possible @var{trst_type} driver modes for the test reset signal (TRST)
2324 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
2325 Most boards connect this signal to a pulldown, so the JTAG TAPs
2326 never leave reset unless they are hooked up to a JTAG adapter.
2327
2328 @item
2329 Possible @var{srst_type} driver modes for the system reset signal (SRST)
2330 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
2331 Most boards connect this signal to a pullup, and allow the
2332 signal to be pulled low by various events including system
2333 powerup and pressing a reset button.
2334 @end itemize
2335 @end deffn
2336
2337 @section Custom Reset Handling
2338 @cindex events
2339
2340 OpenOCD has several ways to help support the various reset
2341 mechanisms provided by chip and board vendors.
2342 The commands shown in the previous section give standard parameters.
2343 There are also @emph{event handlers} associated with TAPs or Targets.
2344 Those handlers are Tcl procedures you can provide, which are invoked
2345 at particular points in the reset sequence.
2346
2347 After configuring those mechanisms, you might still
2348 find your board doesn't start up or reset correctly.
2349 For example, maybe it needs a slightly different sequence
2350 of SRST and/or TRST manipulations, because of quirks that
2351 the @command{reset_config} mechanism doesn't address;
2352 or asserting both might trigger a stronger reset, which
2353 needs special attention.
2354
2355 Experiment with lower level operations, such as @command{jtag_reset}
2356 and the @command{jtag arp_*} operations shown here,
2357 to find a sequence of operations that works.
2358 @xref{JTAG Commands}.
2359 When you find a working sequence, it can be used to override
2360 @command{jtag_init}, which fires during OpenOCD startup
2361 (@pxref{Configuration Stage});
2362 or @command{init_reset}, which fires during reset processing.
2363
2364 You might also want to provide some project-specific reset
2365 schemes. For example, on a multi-target board the standard
2366 @command{reset} command would reset all targets, but you
2367 may need the ability to reset only one target at time and
2368 thus want to avoid using the board-wide SRST signal.
2369
2370 @deffn {Overridable Procedure} init_reset mode
2371 This is invoked near the beginning of the @command{reset} command,
2372 usually to provide as much of a cold (power-up) reset as practical.
2373 By default it is also invoked from @command{jtag_init} if
2374 the scan chain does not respond to pure JTAG operations.
2375 The @var{mode} parameter is the parameter given to the
2376 low level reset command (@option{halt},
2377 @option{init}, or @option{run}), @option{setup},
2378 or potentially some other value.
2379
2380 The default implementation just invokes @command{jtag arp_init-reset}.
2381 Replacements will normally build on low level JTAG
2382 operations such as @command{jtag_reset}.
2383 Operations here must not address individual TAPs
2384 (or their associated targets)
2385 until the JTAG scan chain has first been verified to work.
2386
2387 Implementations must have verified the JTAG scan chain before
2388 they return.
2389 This is done by calling @command{jtag arp_init}
2390 (or @command{jtag arp_init-reset}).
2391 @end deffn
2392
2393 @deffn Command {jtag arp_init}
2394 This validates the scan chain using just the four
2395 standard JTAG signals (TMS, TCK, TDI, TDO).
2396 It starts by issuing a JTAG-only reset.
2397 Then it performs checks to verify that the scan chain configuration
2398 matches the TAPs it can observe.
2399 Those checks include checking IDCODE values for each active TAP,
2400 and verifying the length of their instruction registers using
2401 TAP @code{-ircapture} and @code{-irmask} values.
2402 If these tests all pass, TAP @code{setup} events are
2403 issued to all TAPs with handlers for that event.
2404 @end deffn
2405
2406 @deffn Command {jtag arp_init-reset}
2407 This uses TRST and SRST to try resetting
2408 everything on the JTAG scan chain
2409 (and anything else connected to SRST).
2410 It then invokes the logic of @command{jtag arp_init}.
2411 @end deffn
2412
2413
2414 @node TAP Declaration
2415 @chapter TAP Declaration
2416 @cindex TAP declaration
2417 @cindex TAP configuration
2418
2419 @emph{Test Access Ports} (TAPs) are the core of JTAG.
2420 TAPs serve many roles, including:
2421
2422 @itemize @bullet
2423 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
2424 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
2425 Others do it indirectly, making a CPU do it.
2426 @item @b{Program Download} Using the same CPU support GDB uses,
2427 you can initialize a DRAM controller, download code to DRAM, and then
2428 start running that code.
2429 @item @b{Boundary Scan} Most chips support boundary scan, which
2430 helps test for board assembly problems like solder bridges
2431 and missing connections
2432 @end itemize
2433
2434 OpenOCD must know about the active TAPs on your board(s).
2435 Setting up the TAPs is the core task of your configuration files.
2436 Once those TAPs are set up, you can pass their names to code
2437 which sets up CPUs and exports them as GDB targets,
2438 probes flash memory, performs low-level JTAG operations, and more.
2439
2440 @section Scan Chains
2441 @cindex scan chain
2442
2443 TAPs are part of a hardware @dfn{scan chain},
2444 which is daisy chain of TAPs.
2445 They also need to be added to
2446 OpenOCD's software mirror of that hardware list,
2447 giving each member a name and associating other data with it.
2448 Simple scan chains, with a single TAP, are common in
2449 systems with a single microcontroller or microprocessor.
2450 More complex chips may have several TAPs internally.
2451 Very complex scan chains might have a dozen or more TAPs:
2452 several in one chip, more in the next, and connecting
2453 to other boards with their own chips and TAPs.
2454
2455 You can display the list with the @command{scan_chain} command.
2456 (Don't confuse this with the list displayed by the @command{targets}
2457 command, presented in the next chapter.
2458 That only displays TAPs for CPUs which are configured as
2459 debugging targets.)
2460 Here's what the scan chain might look like for a chip more than one TAP:
2461
2462 @verbatim
2463 TapName Enabled IdCode Expected IrLen IrCap IrMask Instr
2464 -- ------------------ ------- ---------- ---------- ----- ----- ------ -----
2465 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0 0 0x...
2466 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x1 0 0xc
2467 2 omap5912.unknown Y 0x00000000 0x00000000 8 0 0 0xff
2468 @end verbatim
2469
2470 Unfortunately those TAPs can't always be autoconfigured,
2471 because not all devices provide good support for that.
2472 JTAG doesn't require supporting IDCODE instructions, and
2473 chips with JTAG routers may not link TAPs into the chain
2474 until they are told to do so.
2475
2476 The configuration mechanism currently supported by OpenOCD
2477 requires explicit configuration of all TAP devices using
2478 @command{jtag newtap} commands, as detailed later in this chapter.
2479 A command like this would declare one tap and name it @code{chip1.cpu}:
2480
2481 @example
2482 jtag newtap chip1 cpu -irlen 7 -ircapture 0x01 -irmask 0x55
2483 @end example
2484
2485 Each target configuration file lists the TAPs provided
2486 by a given chip.
2487 Board configuration files combine all the targets on a board,
2488 and so forth.
2489 Note that @emph{the order in which TAPs are declared is very important.}
2490 It must match the order in the JTAG scan chain, both inside
2491 a single chip and between them.
2492 @xref{FAQ TAP Order}.
2493
2494 For example, the ST Microsystems STR912 chip has
2495 three separate TAPs@footnote{See the ST
2496 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
2497 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
2498 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
2499 To configure those taps, @file{target/str912.cfg}
2500 includes commands something like this:
2501
2502 @example
2503 jtag newtap str912 flash ... params ...
2504 jtag newtap str912 cpu ... params ...
2505 jtag newtap str912 bs ... params ...
2506 @end example
2507
2508 Actual config files use a variable instead of literals like
2509 @option{str912}, to support more than one chip of each type.
2510 @xref{Config File Guidelines}.
2511
2512 @deffn Command {jtag names}
2513 Returns the names of all current TAPs in the scan chain.
2514 Use @command{jtag cget} or @command{jtag tapisenabled}
2515 to examine attributes and state of each TAP.
2516 @example
2517 foreach t [jtag names] @{
2518 puts [format "TAP: %s\n" $t]
2519 @}
2520 @end example
2521 @end deffn
2522
2523 @deffn Command {scan_chain}
2524 Displays the TAPs in the scan chain configuration,
2525 and their status.
2526 The set of TAPs listed by this command is fixed by
2527 exiting the OpenOCD configuration stage,
2528 but systems with a JTAG router can
2529 enable or disable TAPs dynamically.
2530 In addition to the enable/disable status, the contents of
2531 each TAP's instruction register can also change.
2532 @end deffn
2533
2534 @c FIXME! "jtag cget" should be able to return all TAP
2535 @c attributes, like "$target_name cget" does for targets.
2536
2537 @c Probably want "jtag eventlist", and a "tap-reset" event
2538 @c (on entry to RESET state).
2539
2540 @section TAP Names
2541 @cindex dotted name
2542
2543 When TAP objects are declared with @command{jtag newtap},
2544 a @dfn{dotted.name} is created for the TAP, combining the
2545 name of a module (usually a chip) and a label for the TAP.
2546 For example: @code{xilinx.tap}, @code{str912.flash},
2547 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
2548 Many other commands use that dotted.name to manipulate or
2549 refer to the TAP. For example, CPU configuration uses the
2550 name, as does declaration of NAND or NOR flash banks.
2551
2552 The components of a dotted name should follow ``C'' symbol
2553 name rules: start with an alphabetic character, then numbers
2554 and underscores are OK; while others (including dots!) are not.
2555
2556 @quotation Tip
2557 In older code, JTAG TAPs were numbered from 0..N.
2558 This feature is still present.
2559 However its use is highly discouraged, and
2560 should not be relied on; it will be removed by mid-2010.
2561 Update all of your scripts to use TAP names rather than numbers,
2562 by paying attention to the runtime warnings they trigger.
2563 Using TAP numbers in target configuration scripts prevents
2564 reusing those scripts on boards with multiple targets.
2565 @end quotation
2566
2567 @section TAP Declaration Commands
2568
2569 @c shouldn't this be(come) a {Config Command}?
2570 @anchor{jtag newtap}
2571 @deffn Command {jtag newtap} chipname tapname configparams...
2572 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
2573 and configured according to the various @var{configparams}.
2574
2575 The @var{chipname} is a symbolic name for the chip.
2576 Conventionally target config files use @code{$_CHIPNAME},
2577 defaulting to the model name given by the chip vendor but
2578 overridable.
2579
2580 @cindex TAP naming convention
2581 The @var{tapname} reflects the role of that TAP,
2582 and should follow this convention:
2583
2584 @itemize @bullet
2585 @item @code{bs} -- For boundary scan if this is a seperate TAP;
2586 @item @code{cpu} -- The main CPU of the chip, alternatively
2587 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
2588 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
2589 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
2590 @item @code{flash} -- If the chip has a flash TAP, like the str912;
2591 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
2592 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
2593 @item @code{tap} -- Should be used only FPGA or CPLD like devices
2594 with a single TAP;
2595 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
2596 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
2597 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
2598 a JTAG TAP; that TAP should be named @code{sdma}.
2599 @end itemize
2600
2601 Every TAP requires at least the following @var{configparams}:
2602
2603 @itemize @bullet
2604 @item @code{-irlen} @var{NUMBER}
2605 @*The length in bits of the
2606 instruction register, such as 4 or 5 bits.
2607 @end itemize
2608
2609 A TAP may also provide optional @var{configparams}:
2610
2611 @itemize @bullet
2612 @item @code{-disable} (or @code{-enable})
2613 @*Use the @code{-disable} parameter to flag a TAP which is not
2614 linked in to the scan chain after a reset using either TRST
2615 or the JTAG state machine's @sc{reset} state.
2616 You may use @code{-enable} to highlight the default state
2617 (the TAP is linked in).
2618 @xref{Enabling and Disabling TAPs}.
2619 @item @code{-expected-id} @var{number}
2620 @*A non-zero @var{number} represents a 32-bit IDCODE
2621 which you expect to find when the scan chain is examined.
2622 These codes are not required by all JTAG devices.
2623 @emph{Repeat the option} as many times as required if more than one
2624 ID code could appear (for example, multiple versions).
2625 Specify @var{number} as zero to suppress warnings about IDCODE
2626 values that were found but not included in the list.
2627 @item @code{-ircapture} @var{NUMBER}
2628 @*The bit pattern loaded by the TAP into the JTAG shift register
2629 on entry to the @sc{ircapture} state, such as 0x01.
2630 JTAG requires the two LSBs of this value to be 01.
2631 By default, @code{-ircapture} and @code{-irmask} are set
2632 up to verify that two-bit value; but you may provide
2633 additional bits, if you know them.
2634 @item @code{-irmask} @var{NUMBER}
2635 @*A mask used with @code{-ircapture}
2636 to verify that instruction scans work correctly.
2637 Such scans are not used by OpenOCD except to verify that
2638 there seems to be no problems with JTAG scan chain operations.
2639 @end itemize
2640 @end deffn
2641
2642 @section Other TAP commands
2643
2644 @deffn Command {jtag cget} dotted.name @option{-event} name
2645 @deffnx Command {jtag configure} dotted.name @option{-event} name string
2646 At this writing this TAP attribute
2647 mechanism is used only for event handling.
2648 (It is not a direct analogue of the @code{cget}/@code{configure}
2649 mechanism for debugger targets.)
2650 See the next section for information about the available events.
2651
2652 The @code{configure} subcommand assigns an event handler,
2653 a TCL string which is evaluated when the event is triggered.
2654 The @code{cget} subcommand returns that handler.
2655 @end deffn
2656
2657 @anchor{TAP Events}
2658 @section TAP Events
2659 @cindex events
2660 @cindex TAP events
2661
2662 OpenOCD includes two event mechanisms.
2663 The one presented here applies to all JTAG TAPs.
2664 The other applies to debugger targets,
2665 which are associated with certain TAPs.
2666
2667 The TAP events currently defined are:
2668
2669 @itemize @bullet
2670 @item @b{post-reset}
2671 @* The TAP has just completed a JTAG reset.
2672 The tap may still be in the JTAG @sc{reset} state.
2673 Handlers for these events might perform initialization sequences
2674 such as issuing TCK cycles, TMS sequences to ensure
2675 exit from the ARM SWD mode, and more.
2676
2677 Because the scan chain has not yet been verified, handlers for these events
2678 @emph{should not issue commands which scan the JTAG IR or DR registers}
2679 of any particular target.
2680 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
2681 @item @b{setup}
2682 @* The scan chain has been reset and verified.
2683 This handler may enable TAPs as needed.
2684 @item @b{tap-disable}
2685 @* The TAP needs to be disabled. This handler should
2686 implement @command{jtag tapdisable}
2687 by issuing the relevant JTAG commands.
2688 @item @b{tap-enable}
2689 @* The TAP needs to be enabled. This handler should
2690 implement @command{jtag tapenable}
2691 by issuing the relevant JTAG commands.
2692 @end itemize
2693
2694 If you need some action after each JTAG reset, which isn't actually
2695 specific to any TAP (since you can't yet trust the scan chain's
2696 contents to be accurate), you might:
2697
2698 @example
2699 jtag configure CHIP.jrc -event post-reset @{
2700 echo "JTAG Reset done"
2701 ... non-scan jtag operations to be done after reset
2702 @}
2703 @end example
2704
2705
2706 @anchor{Enabling and Disabling TAPs}
2707 @section Enabling and Disabling TAPs
2708 @cindex JTAG Route Controller
2709 @cindex jrc
2710
2711 In some systems, a @dfn{JTAG Route Controller} (JRC)
2712 is used to enable and/or disable specific JTAG TAPs.
2713 Many ARM based chips from Texas Instruments include
2714 an ``ICEpick'' module, which is a JRC.
2715 Such chips include DaVinci and OMAP3 processors.
2716
2717 A given TAP may not be visible until the JRC has been
2718 told to link it into the scan chain; and if the JRC
2719 has been told to unlink that TAP, it will no longer
2720 be visible.
2721 Such routers address problems that JTAG ``bypass mode''
2722 ignores, such as:
2723
2724 @itemize
2725 @item The scan chain can only go as fast as its slowest TAP.
2726 @item Having many TAPs slows instruction scans, since all
2727 TAPs receive new instructions.
2728 @item TAPs in the scan chain must be powered up, which wastes
2729 power and prevents debugging some power management mechanisms.
2730 @end itemize
2731
2732 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
2733 as implied by the existence of JTAG routers.
2734 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
2735 does include a kind of JTAG router functionality.
2736
2737 @c (a) currently the event handlers don't seem to be able to
2738 @c fail in a way that could lead to no-change-of-state.
2739
2740 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
2741 shown below, and is implemented using TAP event handlers.
2742 So for example, when defining a TAP for a CPU connected to
2743 a JTAG router, your @file{target.cfg} file
2744 should define TAP event handlers using
2745 code that looks something like this:
2746
2747 @example
2748 jtag configure CHIP.cpu -event tap-enable @{
2749 ... jtag operations using CHIP.jrc
2750 @}
2751 jtag configure CHIP.cpu -event tap-disable @{
2752 ... jtag operations using CHIP.jrc
2753 @}
2754 @end example
2755
2756 Then you might want that CPU's TAP enabled almost all the time:
2757
2758 @example
2759 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
2760 @end example
2761
2762 Note how that particular setup event handler declaration
2763 uses quotes to evaluate @code{$CHIP} when the event is configured.
2764 Using brackets @{ @} would cause it to be evaluated later,
2765 at runtime, when it might have a different value.
2766
2767 @deffn Command {jtag tapdisable} dotted.name
2768 If necessary, disables the tap
2769 by sending it a @option{tap-disable} event.
2770 Returns the string "1" if the tap
2771 specified by @var{dotted.name} is enabled,
2772 and "0" if it is disabled.
2773 @end deffn
2774
2775 @deffn Command {jtag tapenable} dotted.name
2776 If necessary, enables the tap
2777 by sending it a @option{tap-enable} event.
2778 Returns the string "1" if the tap
2779 specified by @var{dotted.name} is enabled,
2780 and "0" if it is disabled.
2781 @end deffn
2782
2783 @deffn Command {jtag tapisenabled} dotted.name
2784 Returns the string "1" if the tap
2785 specified by @var{dotted.name} is enabled,
2786 and "0" if it is disabled.
2787
2788 @quotation Note
2789 Humans will find the @command{scan_chain} command more helpful
2790 for querying the state of the JTAG taps.
2791 @end quotation
2792 @end deffn
2793
2794 @node CPU Configuration
2795 @chapter CPU Configuration
2796 @cindex GDB target
2797
2798 This chapter discusses how to set up GDB debug targets for CPUs.
2799 You can also access these targets without GDB
2800 (@pxref{Architecture and Core Commands},
2801 and @ref{Target State handling}) and
2802 through various kinds of NAND and NOR flash commands.
2803 If you have multiple CPUs you can have multiple such targets.
2804
2805 We'll start by looking at how to examine the targets you have,
2806 then look at how to add one more target and how to configure it.
2807
2808 @section Target List
2809 @cindex target, current
2810 @cindex target, list
2811
2812 All targets that have been set up are part of a list,
2813 where each member has a name.
2814 That name should normally be the same as the TAP name.
2815 You can display the list with the @command{targets}
2816 (plural!) command.
2817 This display often has only one CPU; here's what it might
2818 look like with more than one:
2819 @verbatim
2820 TargetName Type Endian TapName State
2821 -- ------------------ ---------- ------ ------------------ ------------
2822 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
2823 1 MyTarget cortex_m3 little mychip.foo tap-disabled
2824 @end verbatim
2825
2826 One member of that list is the @dfn{current target}, which
2827 is implicitly referenced by many commands.
2828 It's the one marked with a @code{*} near the target name.
2829 In particular, memory addresses often refer to the address
2830 space seen by that current target.
2831 Commands like @command{mdw} (memory display words)
2832 and @command{flash erase_address} (erase NOR flash blocks)
2833 are examples; and there are many more.
2834
2835 Several commands let you examine the list of targets:
2836
2837 @deffn Command {target count}
2838 @emph{Note: target numbers are deprecated; don't use them.
2839 They will be removed shortly after August 2010, including this command.
2840 Iterate target using @command{target names}, not by counting.}
2841
2842 Returns the number of targets, @math{N}.
2843 The highest numbered target is @math{N - 1}.
2844 @example
2845 set c [target count]
2846 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
2847 # Assuming you have created this function
2848 print_target_details $x
2849 @}
2850 @end example
2851 @end deffn
2852
2853 @deffn Command {target current}
2854 Returns the name of the current target.
2855 @end deffn
2856
2857 @deffn Command {target names}
2858 Lists the names of all current targets in the list.
2859 @example
2860 foreach t [target names] @{
2861 puts [format "Target: %s\n" $t]
2862 @}
2863 @end example
2864 @end deffn
2865
2866 @deffn Command {target number} number
2867 @emph{Note: target numbers are deprecated; don't use them.
2868 They will be removed shortly after August 2010, including this command.}
2869
2870 The list of targets is numbered starting at zero.
2871 This command returns the name of the target at index @var{number}.
2872 @example
2873 set thename [target number $x]
2874 puts [format "Target %d is: %s\n" $x $thename]
2875 @end example
2876 @end deffn
2877
2878 @c yep, "target list" would have been better.
2879 @c plus maybe "target setdefault".
2880
2881 @deffn Command targets [name]
2882 @emph{Note: the name of this command is plural. Other target
2883 command names are singular.}
2884
2885 With no parameter, this command displays a table of all known
2886 targets in a user friendly form.
2887
2888 With a parameter, this command sets the current target to
2889 the given target with the given @var{name}; this is
2890 only relevant on boards which have more than one target.
2891 @end deffn
2892
2893 @section Target CPU Types and Variants
2894 @cindex target type
2895 @cindex CPU type
2896 @cindex CPU variant
2897
2898 Each target has a @dfn{CPU type}, as shown in the output of
2899 the @command{targets} command. You need to specify that type
2900 when calling @command{target create}.
2901 The CPU type indicates more than just the instruction set.
2902 It also indicates how that instruction set is implemented,
2903 what kind of debug support it integrates,
2904 whether it has an MMU (and if so, what kind),
2905 what core-specific commands may be available
2906 (@pxref{Architecture and Core Commands}),
2907 and more.
2908
2909 For some CPU types, OpenOCD also defines @dfn{variants} which
2910 indicate differences that affect their handling.
2911 For example, a particular implementation bug might need to be
2912 worked around in some chip versions.
2913
2914 It's easy to see what target types are supported,
2915 since there's a command to list them.
2916 However, there is currently no way to list what target variants
2917 are supported (other than by reading the OpenOCD source code).
2918
2919 @anchor{target types}
2920 @deffn Command {target types}
2921 Lists all supported target types.
2922 At this writing, the supported CPU types and variants are:
2923
2924 @itemize @bullet
2925 @item @code{arm11} -- this is a generation of ARMv6 cores
2926 @item @code{arm720t} -- this is an ARMv4 core
2927 @item @code{arm7tdmi} -- this is an ARMv4 core
2928 @item @code{arm920t} -- this is an ARMv5 core
2929 @item @code{arm926ejs} -- this is an ARMv5 core
2930 @item @code{arm966e} -- this is an ARMv5 core
2931 @item @code{arm9tdmi} -- this is an ARMv4 core
2932 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
2933 (Support for this is preliminary and incomplete.)
2934 @item @code{cortex_a8} -- this is an ARMv7 core
2935 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
2936 compact Thumb2 instruction set. It supports one variant:
2937 @itemize @minus
2938 @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
2939 This will cause OpenOCD to use a software reset rather than asserting
2940 SRST, to avoid a issue with clearing the debug registers.
2941 This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
2942 be detected and the normal reset behaviour used.
2943 @end itemize
2944 @item @code{fa526} -- resembles arm920 (w/o Thumb)
2945 @item @code{feroceon} -- resembles arm926
2946 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
2947 @itemize @minus
2948 @item @code{ejtag_srst} ... Use this when debugging targets that do not
2949 provide a functional SRST line on the EJTAG connector. This causes
2950 OpenOCD to instead use an EJTAG software reset command to reset the
2951 processor.
2952 You still need to enable @option{srst} on the @command{reset_config}
2953 command to enable OpenOCD hardware reset functionality.
2954 @end itemize
2955 @item @code{xscale} -- this is actually an architecture,
2956 not a CPU type. It is based on the ARMv5 architecture.
2957 There are several variants defined:
2958 @itemize @minus
2959 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
2960 @code{pxa27x} ... instruction register length is 7 bits
2961 @item @code{pxa250}, @code{pxa255},
2962 @code{pxa26x} ... instruction register length is 5 bits
2963 @end itemize
2964 @end itemize
2965 @end deffn
2966
2967 To avoid being confused by the variety of ARM based cores, remember
2968 this key point: @emph{ARM is a technology licencing company}.
2969 (See: @url{http://www.arm.com}.)
2970 The CPU name used by OpenOCD will reflect the CPU design that was
2971 licenced, not a vendor brand which incorporates that design.
2972 Name prefixes like arm7, arm9, arm11, and cortex
2973 reflect design generations;
2974 while names like ARMv4, ARMv5, ARMv6, and ARMv7
2975 reflect an architecture version implemented by a CPU design.
2976
2977 @anchor{Target Configuration}
2978 @section Target Configuration
2979
2980 Before creating a ``target'', you must have added its TAP to the scan chain.
2981 When you've added that TAP, you will have a @code{dotted.name}
2982 which is used to set up the CPU support.
2983 The chip-specific configuration file will normally configure its CPU(s)
2984 right after it adds all of the chip's TAPs to the scan chain.
2985
2986 Although you can set up a target in one step, it's often clearer if you
2987 use shorter commands and do it in two steps: create it, then configure
2988 optional parts.
2989 All operations on the target after it's created will use a new
2990 command, created as part of target creation.
2991
2992 The two main things to configure after target creation are
2993 a work area, which usually has target-specific defaults even
2994 if the board setup code overrides them later;
2995 and event handlers (@pxref{Target Events}), which tend
2996 to be much more board-specific.
2997 The key steps you use might look something like this
2998
2999 @example
3000 target create MyTarget cortex_m3 -chain-position mychip.cpu
3001 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
3002 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
3003 $MyTarget configure -event reset-init @{ myboard_reinit @}
3004 @end example
3005
3006 You should specify a working area if you can; typically it uses some
3007 on-chip SRAM.
3008 Such a working area can speed up many things, including bulk
3009 writes to target memory;
3010 flash operations like checking to see if memory needs to be erased;
3011 GDB memory checksumming;
3012 and more.
3013
3014 @quotation Warning
3015 On more complex chips, the work area can become
3016 inaccessible when application code
3017 (such as an operating system)
3018 enables or disables the MMU.
3019 For example, the particular MMU context used to acess the virtual
3020 address will probably matter ... and that context might not have
3021 easy access to other addresses needed.
3022 At this writing, OpenOCD doesn't have much MMU intelligence.
3023 @end quotation
3024
3025 It's often very useful to define a @code{reset-init} event handler.
3026 For systems that are normally used with a boot loader,
3027 common tasks include updating clocks and initializing memory
3028 controllers.
3029 That may be needed to let you write the boot loader into flash,
3030 in order to ``de-brick'' your board; or to load programs into
3031 external DDR memory without having run the boot loader.
3032
3033 @deffn Command {target create} target_name type configparams...
3034 This command creates a GDB debug target that refers to a specific JTAG tap.
3035 It enters that target into a list, and creates a new
3036 command (@command{@var{target_name}}) which is used for various
3037 purposes including additional configuration.
3038
3039 @itemize @bullet
3040 @item @var{target_name} ... is the name of the debug target.
3041 By convention this should be the same as the @emph{dotted.name}
3042 of the TAP associated with this target, which must be specified here
3043 using the @code{-chain-position @var{dotted.name}} configparam.
3044
3045 This name is also used to create the target object command,
3046 referred to here as @command{$target_name},
3047 and in other places the target needs to be identified.
3048 @item @var{type} ... specifies the target type. @xref{target types}.
3049 @item @var{configparams} ... all parameters accepted by
3050 @command{$target_name configure} are permitted.
3051 If the target is big-endian, set it here with @code{-endian big}.
3052 If the variant matters, set it here with @code{-variant}.
3053
3054 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
3055 @end itemize
3056 @end deffn
3057
3058 @deffn Command {$target_name configure} configparams...
3059 The options accepted by this command may also be
3060 specified as parameters to @command{target create}.
3061 Their values can later be queried one at a time by
3062 using the @command{$target_name cget} command.
3063
3064 @emph{Warning:} changing some of these after setup is dangerous.
3065 For example, moving a target from one TAP to another;
3066 and changing its endianness or variant.
3067
3068 @itemize @bullet
3069
3070 @item @code{-chain-position} @var{dotted.name} -- names the TAP
3071 used to access this target.
3072
3073 @item @code{-endian} (@option{big}|@option{little}) -- specifies
3074 whether the CPU uses big or little endian conventions
3075
3076 @item @code{-event} @var{event_name} @var{event_body} --
3077 @xref{Target Events}.
3078 Note that this updates a list of named event handlers.
3079 Calling this twice with two different event names assigns
3080 two different handlers, but calling it twice with the
3081 same event name assigns only one handler.
3082
3083 @item @code{-variant} @var{name} -- specifies a variant of the target,
3084 which OpenOCD needs to know about.
3085
3086 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
3087 whether the work area gets backed up; by default,
3088 @emph{it is not backed up.}
3089 When possible, use a working_area that doesn't need to be backed up,
3090 since performing a backup slows down operations.
3091 For example, the beginning of an SRAM block is likely to
3092 be used by most build systems, but the end is often unused.
3093
3094 @item @code{-work-area-size} @var{size} -- specify/set the work area
3095
3096 @item @code{-work-area-phys} @var{address} -- set the work area
3097 base @var{address} to be used when no MMU is active.
3098
3099 @item @code{-work-area-virt} @var{address} -- set the work area
3100 base @var{address} to be used when an MMU is active.
3101
3102 @end itemize
3103 @end deffn
3104
3105 @section Other $target_name Commands
3106 @cindex object command
3107
3108 The Tcl/Tk language has the concept of object commands,
3109 and OpenOCD adopts that same model for targets.
3110
3111 A good Tk example is a on screen button.
3112 Once a button is created a button
3113 has a name (a path in Tk terms) and that name is useable as a first
3114 class command. For example in Tk, one can create a button and later
3115 configure it like this:
3116
3117 @example
3118 # Create
3119 button .foobar -background red -command @{ foo @}
3120 # Modify
3121 .foobar configure -foreground blue
3122 # Query
3123 set x [.foobar cget -background]
3124 # Report
3125 puts [format "The button is %s" $x]
3126 @end example
3127
3128 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
3129 button, and its object commands are invoked the same way.
3130
3131 @example
3132 str912.cpu mww 0x1234 0x42
3133 omap3530.cpu mww 0x5555 123
3134 @end example
3135
3136 The commands supported by OpenOCD target objects are:
3137
3138 @deffn Command {$target_name arp_examine}
3139 @deffnx Command {$target_name arp_halt}
3140 @deffnx Command {$target_name arp_poll}
3141 @deffnx Command {$target_name arp_reset}
3142 @deffnx Command {$target_name arp_waitstate}
3143 Internal OpenOCD scripts (most notably @file{startup.tcl})
3144 use these to deal with specific reset cases.
3145 They are not otherwise documented here.
3146 @end deffn
3147
3148 @deffn Command {$target_name array2mem} arrayname width address count
3149 @deffnx Command {$target_name mem2array} arrayname width address count
3150 These provide an efficient script-oriented interface to memory.
3151 The @code{array2mem} primitive writes bytes, halfwords, or words;
3152 while @code{mem2array} reads them.
3153 In both cases, the TCL side uses an array, and
3154 the target side uses raw memory.
3155
3156 The efficiency comes from enabling the use of
3157 bulk JTAG data transfer operations.
3158 The script orientation comes from working with data
3159 values that are packaged for use by TCL scripts;
3160 @command{mdw} type primitives only print data they retrieve,
3161 and neither store nor return those values.
3162
3163 @itemize
3164 @item @var{arrayname} ... is the name of an array variable
3165 @item @var{width} ... is 8/16/32 - indicating the memory access size
3166 @item @var{address} ... is the target memory address
3167 @item @var{count} ... is the number of elements to process
3168 @end itemize
3169 @end deffn
3170
3171 @deffn Command {$target_name cget} queryparm
3172 Each configuration parameter accepted by
3173 @command{$target_name configure}
3174 can be individually queried, to return its current value.
3175 The @var{queryparm} is a parameter name
3176 accepted by that command, such as @code{-work-area-phys}.
3177 There are a few special cases:
3178
3179 @itemize @bullet
3180 @item @code{-event} @var{event_name} -- returns the handler for the
3181 event named @var{event_name}.
3182 This is a special case because setting a handler requires
3183 two parameters.
3184 @item @code{-type} -- returns the target type.
3185 This is a special case because this is set using
3186 @command{target create} and can't be changed
3187 using @command{$target_name configure}.
3188 @end itemize
3189
3190 For example, if you wanted to summarize information about
3191 all the targets you might use something like this:
3192
3193 @example
3194 foreach name [target names] @{
3195 set y [$name cget -endian]
3196 set z [$name cget -type]
3197 puts [format "Chip %d is %s, Endian: %s, type: %s" \
3198 $x $name $y $z]
3199 @}
3200 @end example
3201 @end deffn
3202
3203 @anchor{target curstate}
3204 @deffn Command {$target_name curstate}
3205 Displays the current target state:
3206 @code{debug-running},
3207 @code{halted},
3208 @code{reset},
3209 @code{running}, or @code{unknown}.
3210 (Also, @pxref{Event Polling}.)
3211 @end deffn
3212
3213 @deffn Command {$target_name eventlist}
3214 Displays a table listing all event handlers
3215 currently associated with this target.
3216 @xref{Target Events}.
3217 @end deffn
3218
3219 @deffn Command {$target_name invoke-event} event_name
3220 Invokes the handler for the event named @var{event_name}.
3221 (This is primarily intended for use by OpenOCD framework
3222 code, for example by the reset code in @file{startup.tcl}.)
3223 @end deffn
3224
3225 @deffn Command {$target_name mdw} addr [count]
3226 @deffnx Command {$target_name mdh} addr [count]
3227 @deffnx Command {$target_name mdb} addr [count]
3228 Display contents of address @var{addr}, as
3229 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
3230 or 8-bit bytes (@command{mdb}).
3231 If @var{count} is specified, displays that many units.
3232 (If you want to manipulate the data instead of displaying it,
3233 see the @code{mem2array} primitives.)
3234 @end deffn
3235
3236 @deffn Command {$target_name mww} addr word
3237 @deffnx Command {$target_name mwh} addr halfword
3238 @deffnx Command {$target_name mwb} addr byte
3239 Writes the specified @var{word} (32 bits),
3240 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3241 at the specified address @var{addr}.
3242 @end deffn
3243
3244 @anchor{Target Events}
3245 @section Target Events
3246 @cindex target events
3247 @cindex events
3248 At various times, certain things can happen, or you want them to happen.
3249 For example:
3250 @itemize @bullet
3251 @item What should happen when GDB connects? Should your target reset?
3252 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
3253 @item During reset, do you need to write to certain memory locations
3254 to set up system clocks or
3255 to reconfigure the SDRAM?
3256 @end itemize
3257
3258 All of the above items can be addressed by target event handlers.
3259 These are set up by @command{$target_name configure -event} or
3260 @command{target create ... -event}.
3261
3262 The programmer's model matches the @code{-command} option used in Tcl/Tk
3263 buttons and events. The two examples below act the same, but one creates
3264 and invokes a small procedure while the other inlines it.
3265
3266 @example
3267 proc my_attach_proc @{ @} @{
3268 echo "Reset..."
3269 reset halt
3270 @}
3271 mychip.cpu configure -event gdb-attach my_attach_proc
3272 mychip.cpu configure -event gdb-attach @{
3273 echo "Reset..."
3274 reset halt
3275 @}
3276 @end example
3277
3278 The following target events are defined:
3279
3280 @itemize @bullet
3281 @item @b{debug-halted}
3282 @* The target has halted for debug reasons (i.e.: breakpoint)
3283 @item @b{debug-resumed}
3284 @* The target has resumed (i.e.: gdb said run)
3285 @item @b{early-halted}
3286 @* Occurs early in the halt process
3287 @ignore
3288 @item @b{examine-end}
3289 @* Currently not used (goal: when JTAG examine completes)
3290 @item @b{examine-start}
3291 @* Currently not used (goal: when JTAG examine starts)
3292 @end ignore
3293 @item @b{gdb-attach}
3294 @* When GDB connects
3295 @item @b{gdb-detach}
3296 @* When GDB disconnects
3297 @item @b{gdb-end}
3298 @* When the target has halted and GDB is not doing anything (see early halt)
3299 @item @b{gdb-flash-erase-start}
3300 @* Before the GDB flash process tries to erase the flash
3301 @item @b{gdb-flash-erase-end}
3302 @* After the GDB flash process has finished erasing the flash
3303 @item @b{gdb-flash-write-start}
3304 @* Before GDB writes to the flash
3305 @item @b{gdb-flash-write-end}
3306 @* After GDB writes to the flash
3307 @item @b{gdb-start}
3308 @* Before the target steps, gdb is trying to start/resume the target
3309 @item @b{halted}
3310 @* The target has halted
3311 @ignore
3312 @item @b{old-gdb_program_config}
3313 @* DO NOT USE THIS: Used internally
3314 @item @b{old-pre_resume}
3315 @* DO NOT USE THIS: Used internally
3316 @end ignore
3317 @item @b{reset-assert-pre}
3318 @* Issued as part of @command{reset} processing
3319 after @command{reset_init} was triggered
3320 but before SRST alone is re-asserted on the tap.
3321 @item @b{reset-assert-post}
3322 @* Issued as part of @command{reset} processing
3323 when SRST is asserted on the tap.
3324 @item @b{reset-deassert-pre}
3325 @* Issued as part of @command{reset} processing
3326 when SRST is about to be released on the tap.
3327 @item @b{reset-deassert-post}
3328 @* Issued as part of @command{reset} processing
3329 when SRST has been released on the tap.
3330 @item @b{reset-end}
3331 @* Issued as the final step in @command{reset} processing.
3332 @ignore
3333 @item @b{reset-halt-post}
3334 @* Currently not used
3335 @item @b{reset-halt-pre}
3336 @* Currently not used
3337 @end ignore
3338 @item @b{reset-init}
3339 @* Used by @b{reset init} command for board-specific initialization.
3340 This event fires after @emph{reset-deassert-post}.
3341
3342 This is where you would configure PLLs and clocking, set up DRAM so
3343 you can download programs that don't fit in on-chip SRAM, set up pin
3344 multiplexing, and so on.
3345 (You may be able to switch to a fast JTAG clock rate here, after
3346 the target clocks are fully set up.)
3347 @item @b{reset-start}
3348 @* Issued as part of @command{reset} processing
3349 before @command{reset_init} is called.
3350
3351 This is the most robust place to use @command{jtag_rclk}
3352 or @command{jtag_khz} to switch to a low JTAG clock rate,
3353 when reset disables PLLs needed to use a fast clock.
3354 @ignore
3355 @item @b{reset-wait-pos}
3356 @* Currently not used
3357 @item @b{reset-wait-pre}
3358 @* Currently not used
3359 @end ignore
3360 @item @b{resume-start}
3361 @* Before any target is resumed
3362 @item @b{resume-end}
3363 @* After all targets have resumed
3364 @item @b{resume-ok}
3365 @* Success
3366 @item @b{resumed}
3367 @* Target has resumed
3368 @end itemize
3369
3370
3371 @node Flash Commands
3372 @chapter Flash Commands
3373
3374 OpenOCD has different commands for NOR and NAND flash;
3375 the ``flash'' command works with NOR flash, while
3376 the ``nand'' command works with NAND flash.
3377 This partially reflects different hardware technologies:
3378 NOR flash usually supports direct CPU instruction and data bus access,
3379 while data from a NAND flash must be copied to memory before it can be
3380 used. (SPI flash must also be copied to memory before use.)
3381 However, the documentation also uses ``flash'' as a generic term;
3382 for example, ``Put flash configuration in board-specific files''.
3383
3384 Flash Steps:
3385 @enumerate
3386 @item Configure via the command @command{flash bank}
3387 @* Do this in a board-specific configuration file,
3388 passing parameters as needed by the driver.
3389 @item Operate on the flash via @command{flash subcommand}
3390 @* Often commands to manipulate the flash are typed by a human, or run
3391 via a script in some automated way. Common tasks include writing a
3392 boot loader, operating system, or other data.
3393 @item GDB Flashing
3394 @* Flashing via GDB requires the flash be configured via ``flash
3395 bank'', and the GDB flash features be enabled.
3396 @xref{GDB Configuration}.
3397 @end enumerate
3398
3399 Many CPUs have the ablity to ``boot'' from the first flash bank.
3400 This means that misprogramming that bank can ``brick'' a system,
3401 so that it can't boot.
3402 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
3403 board by (re)installing working boot firmware.
3404
3405 @anchor{NOR Configuration}
3406 @section Flash Configuration Commands
3407 @cindex flash configuration
3408
3409 @deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
3410 Configures a flash bank which provides persistent storage
3411 for addresses from @math{base} to @math{base + size - 1}.
3412 These banks will often be visible to GDB through the target's memory map.
3413 In some cases, configuring a flash bank will activate extra commands;
3414 see the driver-specific documentation.
3415
3416 @itemize @bullet
3417 @item @var{driver} ... identifies the controller driver
3418 associated with the flash bank being declared.
3419 This is usually @code{cfi} for external flash, or else
3420 the name of a microcontroller with embedded flash memory.
3421 @xref{Flash Driver List}.
3422 @item @var{base} ... Base address of the flash chip.
3423 @item @var{size} ... Size of the chip, in bytes.
3424 For some drivers, this value is detected from the hardware.
3425 @item @var{chip_width} ... Width of the flash chip, in bytes;
3426 ignored for most microcontroller drivers.
3427 @item @var{bus_width} ... Width of the data bus used to access the
3428 chip, in bytes; ignored for most microcontroller drivers.
3429 @item @var{target} ... Names the target used to issue
3430 commands to the flash controller.
3431 @comment Actually, it's currently a controller-specific parameter...
3432 @item @var{driver_options} ... drivers may support, or require,
3433 additional parameters. See the driver-specific documentation
3434 for more information.
3435 @end itemize
3436 @quotation Note
3437 This command is not available after OpenOCD initialization has completed.
3438 Use it in board specific configuration files, not interactively.
3439 @end quotation
3440 @end deffn
3441
3442 @comment the REAL name for this command is "ocd_flash_banks"
3443 @comment less confusing would be: "flash list" (like "nand list")
3444 @deffn Command {flash banks}
3445 Prints a one-line summary of each device declared
3446 using @command{flash bank}, numbered from zero.
3447 Note that this is the @emph{plural} form;
3448 the @emph{singular} form is a very different command.
3449 @end deffn
3450
3451 @deffn Command {flash probe} num
3452 Identify the flash, or validate the parameters of the configured flash. Operation
3453 depends on the flash type.
3454 The @var{num} parameter is a value shown by @command{flash banks}.
3455 Most flash commands will implicitly @emph{autoprobe} the bank;
3456 flash drivers can distinguish between probing and autoprobing,
3457 but most don't bother.
3458 @end deffn
3459
3460 @section Erasing, Reading, Writing to Flash
3461 @cindex flash erasing
3462 @cindex flash reading
3463 @cindex flash writing
3464 @cindex flash programming
3465
3466 One feature distinguishing NOR flash from NAND or serial flash technologies
3467 is that for read access, it acts exactly like any other addressible memory.
3468 This means you can use normal memory read commands like @command{mdw} or
3469 @command{dump_image} with it, with no special @command{flash} subcommands.
3470 @xref{Memory access}, and @ref{Image access}.
3471
3472 Write access works differently. Flash memory normally needs to be erased
3473 before it's written. Erasing a sector turns all of its bits to ones, and
3474 writing can turn ones into zeroes. This is why there are special commands
3475 for interactive erasing and writing, and why GDB needs to know which parts
3476 of the address space hold NOR flash memory.
3477
3478 @quotation Note
3479 Most of these erase and write commands leverage the fact that NOR flash
3480 chips consume target address space. They implicitly refer to the current
3481 JTAG target, and map from an address in that target's address space
3482 back to a flash bank.
3483 @comment In May 2009, those mappings may fail if any bank associated
3484 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
3485 A few commands use abstract addressing based on bank and sector numbers,
3486 and don't depend on searching the current target and its address space.
3487 Avoid confusing the two command models.
3488 @end quotation
3489
3490 Some flash chips implement software protection against accidental writes,
3491 since such buggy writes could in some cases ``brick'' a system.
3492 For such systems, erasing and writing may require sector protection to be
3493 disabled first.
3494 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
3495 and AT91SAM7 on-chip flash.
3496 @xref{flash protect}.
3497
3498 @anchor{flash erase_sector}
3499 @deffn Command {flash erase_sector} num first last
3500 Erase sectors in bank @var{num}, starting at sector @var{first}
3501 up to and including @var{last}.
3502 Sector numbering starts at 0.
3503 Providing a @var{last} sector of @option{last}
3504 specifies "to the end of the flash bank".
3505 The @var{num} parameter is a value shown by @command{flash banks}.
3506 @end deffn
3507
3508 @deffn Command {flash erase_address} address length
3509 Erase sectors starting at @var{address} for @var{length} bytes.
3510 The flash bank to use is inferred from the @var{address}, and
3511 the specified length must stay within that bank.
3512 As a special case, when @var{length} is zero and @var{address} is
3513 the start of the bank, the whole flash is erased.
3514 @end deffn
3515
3516 @deffn Command {flash fillw} address word length
3517 @deffnx Command {flash fillh} address halfword length
3518 @deffnx Command {flash fillb} address byte length
3519 Fills flash memory with the specified @var{word} (32 bits),
3520 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3521 starting at @var{address} and continuing
3522 for @var{length} units (word/halfword/byte).
3523 No erasure is done before writing; when needed, that must be done
3524 before issuing this command.
3525 Writes are done in blocks of up to 1024 bytes, and each write is
3526 verified by reading back the data and comparing it to what was written.
3527 The flash bank to use is inferred from the @var{address} of
3528 each block, and the specified length must stay within that bank.
3529 @end deffn
3530 @comment no current checks for errors if fill blocks touch multiple banks!
3531
3532 @anchor{flash write_bank}
3533 @deffn Command {flash write_bank} num filename offset
3534 Write the binary @file{filename} to flash bank @var{num},
3535 starting at @var{offset} bytes from the beginning of the bank.
3536 The @var{num} parameter is a value shown by @command{flash banks}.
3537 @end deffn
3538
3539 @anchor{flash write_image}
3540 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
3541 Write the image @file{filename} to the current target's flash bank(s).
3542 A relocation @var{offset} may be specified, in which case it is added
3543 to the base address for each section in the image.
3544 The file [@var{type}] can be specified
3545 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
3546 @option{elf} (ELF file), @option{s19} (Motorola s19).
3547 @option{mem}, or @option{builder}.
3548 The relevant flash sectors will be erased prior to programming
3549 if the @option{erase} parameter is given. If @option{unlock} is
3550 provided, then the flash banks are unlocked before erase and
3551 program. The flash bank to use is inferred from the @var{address} of
3552 each image segment.
3553 @end deffn
3554
3555 @section Other Flash commands
3556 @cindex flash protection
3557
3558 @deffn Command {flash erase_check} num
3559 Check erase state of sectors in flash bank @var{num},
3560 and display that status.
3561 The @var{num} parameter is a value shown by @command{flash banks}.
3562 This is the only operation that
3563 updates the erase state information displayed by @option{flash info}. That means you have
3564 to issue a @command{flash erase_check} command after erasing or programming the device
3565 to get updated information.
3566 (Code execution may have invalidated any state records kept by OpenOCD.)
3567 @end deffn
3568
3569 @deffn Command {flash info} num
3570 Print info about flash bank @var{num}
3571 The @var{num} parameter is a value shown by @command{flash banks}.
3572 The information includes per-sector protect status.
3573 @end deffn
3574
3575 @anchor{flash protect}
3576 @deffn Command {flash protect} num first last (@option{on}|@option{off})
3577 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
3578 in flash bank @var{num}, starting at sector @var{first}
3579 and continuing up to and including @var{last}.
3580 Providing a @var{last} sector of @option{last}
3581 specifies "to the end of the flash bank".
3582 The @var{num} parameter is a value shown by @command{flash banks}.
3583 @end deffn
3584
3585 @deffn Command {flash protect_check} num
3586 Check protection state of sectors in flash bank @var{num}.
3587 The @var{num} parameter is a value shown by @command{flash banks}.
3588 @comment @option{flash erase_sector} using the same syntax.
3589 @end deffn
3590
3591 @anchor{Flash Driver List}
3592 @section Flash Drivers, Options, and Commands
3593 As noted above, the @command{flash bank} command requires a driver name,
3594 and allows driver-specific options and behaviors.
3595 Some drivers also activate driver-specific commands.
3596
3597 @subsection External Flash
3598
3599 @deffn {Flash Driver} cfi
3600 @cindex Common Flash Interface
3601 @cindex CFI
3602 The ``Common Flash Interface'' (CFI) is the main standard for
3603 external NOR flash chips, each of which connects to a
3604 specific external chip select on the CPU.
3605 Frequently the first such chip is used to boot the system.
3606 Your board's @code{reset-init} handler might need to
3607 configure additional chip selects using other commands (like: @command{mww} to
3608 configure a bus and its timings) , or
3609 perhaps configure a GPIO pin that controls the ``write protect'' pin
3610 on the flash chip.
3611 The CFI driver can use a target-specific working area to significantly
3612 speed up operation.
3613
3614 The CFI driver can accept the following optional parameters, in any order:
3615
3616 @itemize
3617 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
3618 like AM29LV010 and similar types.
3619 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
3620 @end itemize
3621
3622 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
3623 wide on a sixteen bit bus:
3624
3625 @example
3626 flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
3627 flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
3628 @end example
3629 @c "cfi part_id" disabled
3630 @end deffn
3631
3632 @subsection Internal Flash (Microcontrollers)
3633
3634 @deffn {Flash Driver} aduc702x
3635 The ADUC702x analog microcontrollers from Analog Devices
3636 include internal flash and use ARM7TDMI cores.
3637 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
3638 The setup command only requires the @var{target} argument
3639 since all devices in this family have the same memory layout.
3640
3641 @example
3642 flash bank aduc702x 0 0 0 0 $_TARGETNAME
3643 @end example
3644 @end deffn
3645
3646 @deffn {Flash Driver} at91sam3
3647 @cindex at91sam3
3648 All members of the AT91SAM3 microcontroller family from
3649 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
3650 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
3651 that the driver was orginaly developed and tested using the
3652 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
3653 the family was cribbed from the data sheet. @emph{Note to future
3654 readers/updaters: Please remove this worrysome comment after other
3655 chips are confirmed.}
3656
3657 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
3658 have one flash bank. In all cases the flash banks are at
3659 the following fixed locations:
3660
3661 @example
3662 # Flash bank 0 - all chips
3663 flash bank at91sam3 0x00080000 0 1 1 $_TARGETNAME
3664 # Flash bank 1 - only 256K chips
3665 flash bank at91sam3 0x00100000 0 1 1 $_TARGETNAME
3666 @end example
3667
3668 Internally, the AT91SAM3 flash memory is organized as follows.
3669 Unlike the AT91SAM7 chips, these are not used as parameters
3670 to the @command{flash bank} command:
3671
3672 @itemize
3673 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
3674 @item @emph{Bank Size:} 128K/64K Per flash bank
3675 @item @emph{Sectors:} 16 or 8 per bank
3676 @item @emph{SectorSize:} 8K Per Sector
3677 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
3678 @end itemize
3679
3680 The AT91SAM3 driver adds some additional commands:
3681
3682 @deffn Command {at91sam3 gpnvm}
3683 @deffnx Command {at91sam3 gpnvm clear} number
3684 @deffnx Command {at91sam3 gpnvm set} number
3685 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
3686 With no parameters, @command{show} or @command{show all},
3687 shows the status of all GPNVM bits.
3688 With @command{show} @var{number}, displays that bit.
3689
3690 With @command{set} @var{number} or @command{clear} @var{number},
3691 modifies that GPNVM bit.
3692 @end deffn
3693
3694 @deffn Command {at91sam3 info}
3695 This command attempts to display information about the AT91SAM3
3696 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
3697 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
3698 document id: doc6430A] and decodes the values. @emph{Second} it reads the
3699 various clock configuration registers and attempts to display how it
3700 believes the chip is configured. By default, the SLOWCLK is assumed to
3701 be 32768 Hz, see the command @command{at91sam3 slowclk}.
3702 @end deffn
3703
3704 @deffn Command {at91sam3 slowclk} [value]
3705 This command shows/sets the slow clock frequency used in the
3706 @command{at91sam3 info} command calculations above.
3707 @end deffn
3708 @end deffn
3709
3710 @deffn {Flash Driver} at91sam7
3711 All members of the AT91SAM7 microcontroller family from Atmel include
3712 internal flash and use ARM7TDMI cores. The driver automatically
3713 recognizes a number of these chips using the chip identification
3714 register, and autoconfigures itself.
3715
3716 @example
3717 flash bank at91sam7 0 0 0 0 $_TARGETNAME
3718 @end example
3719
3720 For chips which are not recognized by the controller driver, you must
3721 provide additional parameters in the following order:
3722
3723 @itemize
3724 @item @var{chip_model} ... label used with @command{flash info}
3725 @item @var{banks}
3726 @item @var{sectors_per_bank}
3727 @item @var{pages_per_sector}
3728 @item @var{pages_size}
3729 @item @var{num_nvm_bits}
3730 @item @var{freq_khz} ... required if an external clock is provided,
3731 optional (but recommended) when the oscillator frequency is known
3732 @end itemize
3733
3734 It is recommended that you provide zeroes for all of those values
3735 except the clock frequency, so that everything except that frequency
3736 will be autoconfigured.
3737 Knowing the frequency helps ensure correct timings for flash access.
3738
3739 The flash controller handles erases automatically on a page (128/256 byte)
3740 basis, so explicit erase commands are not necessary for flash programming.
3741 However, there is an ``EraseAll`` command that can erase an entire flash
3742 plane (of up to 256KB), and it will be used automatically when you issue
3743 @command{flash erase_sector} or @command{flash erase_address} commands.
3744
3745 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
3746 Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
3747 bit for the processor. Each processor has a number of such bits,
3748 used for controlling features such as brownout detection (so they
3749 are not truly general purpose).
3750 @quotation Note
3751 This assumes that the first flash bank (number 0) is associated with
3752 the appropriate at91sam7 target.
3753 @end quotation
3754 @end deffn
3755 @end deffn
3756
3757 @deffn {Flash Driver} avr
3758 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
3759 @emph{The current implementation is incomplete.}
3760 @comment - defines mass_erase ... pointless given flash_erase_address
3761 @end deffn
3762
3763 @deffn {Flash Driver} ecosflash
3764 @emph{No idea what this is...}
3765 The @var{ecosflash} driver defines one mandatory parameter,
3766 the name of a modules of target code which is downloaded
3767 and executed.
3768 @end deffn
3769
3770 @deffn {Flash Driver} lpc2000
3771 Most members of the LPC1700 and LPC2000 microcontroller families from NXP
3772 include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
3773
3774 @quotation Note
3775 There are LPC2000 devices which are not supported by the @var{lpc2000}
3776 driver:
3777 The LPC2888 is supported by the @var{lpc288x} driver.
3778 The LPC29xx family is supported by the @var{lpc2900} driver.
3779 @end quotation
3780
3781 The @var{lpc2000} driver defines two mandatory and one optional parameters,
3782 which must appear in the following order:
3783
3784 @itemize
3785 @item @var{variant} ... required, may be
3786 @var{lpc2000_v1} (older LPC21xx and LPC22xx)
3787 @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
3788 or @var{lpc1700} (LPC175x and LPC176x)
3789 @item @var{clock_kHz} ... the frequency, in kiloHertz,
3790 at which the core is running
3791 @item @var{calc_checksum} ... optional (but you probably want to provide this!),
3792 telling the driver to calculate a valid checksum for the exception vector table.
3793 @end itemize
3794
3795 LPC flashes don't require the chip and bus width to be specified.
3796
3797 @example
3798 flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
3799 lpc2000_v2 14765 calc_checksum
3800 @end example
3801
3802 @deffn {Command} {lpc2000 part_id} bank
3803 Displays the four byte part identifier associated with
3804 the specified flash @var{bank}.
3805 @end deffn
3806 @end deffn
3807
3808 @deffn {Flash Driver} lpc288x
3809 The LPC2888 microcontroller from NXP needs slightly different flash
3810 support from its lpc2000 siblings.
3811 The @var{lpc288x} driver defines one mandatory parameter,
3812 the programming clock rate in Hz.
3813 LPC flashes don't require the chip and bus width to be specified.
3814
3815 @example
3816 flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
3817 @end example
3818 @end deffn
3819
3820 @deffn {Flash Driver} lpc2900
3821 This driver supports the LPC29xx ARM968E based microcontroller family
3822 from NXP.
3823
3824 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
3825 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
3826 sector layout are auto-configured by the driver.
3827 The driver has one additional mandatory parameter: The CPU clock rate
3828 (in kHz) at the time the flash operations will take place. Most of the time this
3829 will not be the crystal frequency, but a higher PLL frequency. The
3830 @code{reset-init} event handler in the board script is usually the place where
3831 you start the PLL.
3832
3833 The driver rejects flashless devices (currently the LPC2930).
3834
3835 The EEPROM in LPC2900 devices is not mapped directly into the address space.
3836 It must be handled much more like NAND flash memory, and will therefore be
3837 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
3838
3839 Sector protection in terms of the LPC2900 is handled transparently. Every time a
3840 sector needs to be erased or programmed, it is automatically unprotected.
3841 What is shown as protection status in the @code{flash info} command, is
3842 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
3843 sector from ever being erased or programmed again. As this is an irreversible
3844 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
3845 and not by the standard @code{flash protect} command.
3846
3847 Example for a 125 MHz clock frequency:
3848 @example
3849 flash bank lpc2900 0 0 0 0 $_TARGETNAME 125000
3850 @end example
3851
3852 Some @code{lpc2900}-specific commands are defined. In the following command list,
3853 the @var{bank} parameter is the bank number as obtained by the
3854 @code{flash banks} command.
3855
3856 @deffn Command {lpc2900 signature} bank
3857 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
3858 content. This is a hardware feature of the flash block, hence the calculation is
3859 very fast. You may use this to verify the content of a programmed device against
3860 a known signature.
3861 Example:
3862 @example
3863 lpc2900 signature 0
3864 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
3865 @end example
3866 @end deffn
3867
3868 @deffn Command {lpc2900 read_custom} bank filename
3869 Reads the 912 bytes of customer information from the flash index sector, and
3870 saves it to a file in binary format.
3871 Example:
3872 @example
3873 lpc2900 read_custom 0 /path_to/customer_info.bin
3874 @end example
3875 @end deffn
3876
3877 The index sector of the flash is a @emph{write-only} sector. It cannot be
3878 erased! In order to guard against unintentional write access, all following
3879 commands need to be preceeded by a successful call to the @code{password}
3880 command:
3881
3882 @deffn Command {lpc2900 password} bank password
3883 You need to use this command right before each of the following commands:
3884 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
3885 @code{lpc2900 secure_jtag}.
3886
3887 The password string is fixed to "I_know_what_I_am_doing".
3888 Example:
3889 @example
3890 lpc2900 password 0 I_know_what_I_am_doing
3891 Potentially dangerous operation allowed in next command!
3892 @end example
3893 @end deffn
3894
3895 @deffn Command {lpc2900 write_custom} bank filename type
3896 Writes the content of the file into the customer info space of the flash index
3897 sector. The filetype can be specified with the @var{type} field. Possible values
3898 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
3899 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
3900 contain a single section, and the contained data length must be exactly
3901 912 bytes.
3902 @quotation Attention
3903 This cannot be reverted! Be careful!
3904 @end quotation
3905 Example:
3906 @example
3907 lpc2900 write_custom 0 /path_to/customer_info.bin bin
3908 @end example
3909 @end deffn
3910
3911 @deffn Command {lpc2900 secure_sector} bank first last
3912 Secures the sector range from @var{first} to @var{last} (including) against
3913 further program and erase operations. The sector security will be effective
3914 after the next power cycle.
3915 @quotation Attention
3916 This cannot be reverted! Be careful!
3917 @end quotation
3918 Secured sectors appear as @emph{protected} in the @code{flash info} command.
3919 Example:
3920 @example
3921 lpc2900 secure_sector 0 1 1
3922 flash info 0
3923 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
3924 # 0: 0x00000000 (0x2000 8kB) not protected
3925 # 1: 0x00002000 (0x2000 8kB) protected
3926 # 2: 0x00004000 (0x2000 8kB) not protected
3927 @end example
3928 @end deffn
3929
3930 @deffn Command {lpc2900 secure_jtag} bank
3931 Irreversibly disable the JTAG port. The new JTAG security setting will be
3932 effective after the next power cycle.
3933 @quotation Attention
3934 This cannot be reverted! Be careful!
3935 @end quotation
3936 Examples:
3937 @example
3938 lpc2900 secure_jtag 0
3939 @end example
3940 @end deffn
3941 @end deffn
3942
3943 @deffn {Flash Driver} ocl
3944 @emph{No idea what this is, other than using some arm7/arm9 core.}
3945
3946 @example
3947 flash bank ocl 0 0 0 0 $_TARGETNAME
3948 @end example
3949 @end deffn
3950
3951 @deffn {Flash Driver} pic32mx
3952 The PIC32MX microcontrollers are based on the MIPS 4K cores,
3953 and integrate flash memory.
3954 @emph{The current implementation is incomplete.}
3955
3956 @example
3957 flash bank pix32mx 0 0 0 0 $_TARGETNAME
3958 @end example
3959
3960 @comment numerous *disabled* commands are defined:
3961 @comment - chip_erase ... pointless given flash_erase_address
3962 @comment - lock, unlock ... pointless given protect on/off (yes?)
3963 @comment - pgm_word ... shouldn't bank be deduced from address??
3964 Some pic32mx-specific commands are defined:
3965 @deffn Command {pic32mx pgm_word} address value bank
3966 Programs the specified 32-bit @var{value} at the given @var{address}
3967 in the specified chip @var{bank}.
3968 @end deffn
3969 @end deffn
3970
3971 @deffn {Flash Driver} stellaris
3972 All members of the Stellaris LM3Sxxx microcontroller family from
3973 Texas Instruments
3974 include internal flash and use ARM Cortex M3 cores.
3975 The driver automatically recognizes a number of these chips using
3976 the chip identification register, and autoconfigures itself.
3977 @footnote{Currently there is a @command{stellaris mass_erase} command.
3978 That seems pointless since the same effect can be had using the
3979 standard @command{flash erase_address} command.}
3980
3981 @example
3982 flash bank stellaris 0 0 0 0 $_TARGETNAME
3983 @end example
3984 @end deffn
3985
3986 @deffn {Flash Driver} stm32x
3987 All members of the STM32 microcontroller family from ST Microelectronics
3988 include internal flash and use ARM Cortex M3 cores.
3989 The driver automatically recognizes a number of these chips using
3990 the chip identification register, and autoconfigures itself.
3991
3992 @example
3993 flash bank stm32x 0 0 0 0 $_TARGETNAME
3994 @end example
3995
3996 Some stm32x-specific commands
3997 @footnote{Currently there is a @command{stm32x mass_erase} command.
3998 That seems pointless since the same effect can be had using the
3999 standard @command{flash erase_address} command.}
4000 are defined:
4001
4002 @deffn Command {stm32x lock} num
4003 Locks the entire stm32 device.
4004 The @var{num} parameter is a value shown by @command{flash banks}.
4005 @end deffn
4006
4007 @deffn Command {stm32x unlock} num
4008 Unlocks the entire stm32 device.
4009 The @var{num} parameter is a value shown by @command{flash banks}.
4010 @end deffn
4011
4012 @deffn Command {stm32x options_read} num
4013 Read and display the stm32 option bytes written by
4014 the @command{stm32x options_write} command.
4015 The @var{num} parameter is a value shown by @command{flash banks}.
4016 @end deffn
4017
4018 @deffn Command {stm32x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
4019 Writes the stm32 option byte with the specified values.
4020 The @var{num} parameter is a value shown by @command{flash banks}.
4021 @end deffn
4022 @end deffn
4023
4024 @deffn {Flash Driver} str7x
4025 All members of the STR7 microcontroller family from ST Microelectronics
4026 include internal flash and use ARM7TDMI cores.
4027 The @var{str7x} driver defines one mandatory parameter, @var{variant},
4028 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
4029
4030 @example
4031 flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
4032 @end example
4033
4034 @deffn Command {str7x disable_jtag} bank
4035 Activate the Debug/Readout protection mechanism
4036 for the specified flash bank.
4037 @end deffn
4038 @end deffn
4039
4040 @deffn {Flash Driver} str9x
4041 Most members of the STR9 microcontroller family from ST Microelectronics
4042 include internal flash and use ARM966E cores.
4043 The str9 needs the flash controller to be configured using
4044 the @command{str9x flash_config} command prior to Flash programming.
4045
4046 @example
4047 flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
4048 str9x flash_config 0 4 2 0 0x80000
4049 @end example
4050
4051 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
4052 Configures the str9 flash controller.
4053 The @var{num} parameter is a value shown by @command{flash banks}.
4054
4055 @itemize @bullet
4056 @item @var{bbsr} - Boot Bank Size register
4057 @item @var{nbbsr} - Non Boot Bank Size register
4058 @item @var{bbadr} - Boot Bank Start Address register
4059 @item @var{nbbadr} - Boot Bank Start Address register
4060 @end itemize
4061 @end deffn
4062
4063 @end deffn
4064
4065 @deffn {Flash Driver} tms470
4066 Most members of the TMS470 microcontroller family from Texas Instruments
4067 include internal flash and use ARM7TDMI cores.
4068 This driver doesn't require the chip and bus width to be specified.
4069
4070 Some tms470-specific commands are defined:
4071
4072 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
4073 Saves programming keys in a register, to enable flash erase and write commands.
4074 @end deffn
4075
4076 @deffn Command {tms470 osc_mhz} clock_mhz
4077 Reports the clock speed, which is used to calculate timings.
4078 @end deffn
4079
4080 @deffn Command {tms470 plldis} (0|1)
4081 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
4082 the flash clock.
4083 @end deffn
4084 @end deffn
4085
4086 @subsection str9xpec driver
4087 @cindex str9xpec
4088
4089 Here is some background info to help
4090 you better understand how this driver works. OpenOCD has two flash drivers for
4091 the str9:
4092 @enumerate
4093 @item
4094 Standard driver @option{str9x} programmed via the str9 core. Normally used for
4095 flash programming as it is faster than the @option{str9xpec} driver.
4096 @item
4097 Direct programming @option{str9xpec} using the flash controller. This is an
4098 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
4099 core does not need to be running to program using this flash driver. Typical use
4100 for this driver is locking/unlocking the target and programming the option bytes.
4101 @end enumerate
4102
4103 Before we run any commands using the @option{str9xpec} driver we must first disable
4104 the str9 core. This example assumes the @option{str9xpec} driver has been
4105 configured for flash bank 0.
4106 @example
4107 # assert srst, we do not want core running
4108 # while accessing str9xpec flash driver
4109 jtag_reset 0 1
4110 # turn off target polling
4111 poll off
4112 # disable str9 core
4113 str9xpec enable_turbo 0
4114 # read option bytes
4115 str9xpec options_read 0
4116 # re-enable str9 core
4117 str9xpec disable_turbo 0
4118 poll on
4119 reset halt
4120 @end example
4121 The above example will read the str9 option bytes.
4122 When performing a unlock remember that you will not be able to halt the str9 - it
4123 has been locked. Halting the core is not required for the @option{str9xpec} driver
4124 as mentioned above, just issue the commands above manually or from a telnet prompt.
4125
4126 @deffn {Flash Driver} str9xpec
4127 Only use this driver for locking/unlocking the device or configuring the option bytes.
4128 Use the standard str9 driver for programming.
4129 Before using the flash commands the turbo mode must be enabled using the
4130 @command{str9xpec enable_turbo} command.
4131
4132 Several str9xpec-specific commands are defined:
4133
4134 @deffn Command {str9xpec disable_turbo} num
4135 Restore the str9 into JTAG chain.
4136 @end deffn
4137
4138 @deffn Command {str9xpec enable_turbo} num
4139 Enable turbo mode, will simply remove the str9 from the chain and talk
4140 directly to the embedded flash controller.
4141 @end deffn
4142
4143 @deffn Command {str9xpec lock} num
4144 Lock str9 device. The str9 will only respond to an unlock command that will
4145 erase the device.
4146 @end deffn
4147
4148 @deffn Command {str9xpec part_id} num
4149 Prints the part identifier for bank @var{num}.
4150 @end deffn
4151
4152 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
4153 Configure str9 boot bank.
4154 @end deffn
4155
4156 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
4157 Configure str9 lvd source.
4158 @end deffn
4159
4160 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
4161 Configure str9 lvd threshold.
4162 @end deffn
4163
4164 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
4165 Configure str9 lvd reset warning source.
4166 @end deffn
4167
4168 @deffn Command {str9xpec options_read} num
4169 Read str9 option bytes.
4170 @end deffn
4171
4172 @deffn Command {str9xpec options_write} num
4173 Write str9 option bytes.
4174 @end deffn
4175
4176 @deffn Command {str9xpec unlock} num
4177 unlock str9 device.
4178 @end deffn
4179
4180 @end deffn
4181
4182
4183 @section mFlash
4184
4185 @subsection mFlash Configuration
4186 @cindex mFlash Configuration
4187
4188 @deffn {Config Command} {mflash bank} soc base RST_pin target
4189 Configures a mflash for @var{soc} host bank at
4190 address @var{base}.
4191 The pin number format depends on the host GPIO naming convention.
4192 Currently, the mflash driver supports s3c2440 and pxa270.
4193
4194 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
4195
4196 @example
4197 mflash bank s3c2440 0x10000000 1b 0
4198 @end example
4199
4200 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
4201
4202 @example
4203 mflash bank pxa270 0x08000000 43 0
4204 @end example
4205 @end deffn
4206
4207 @subsection mFlash commands
4208 @cindex mFlash commands
4209
4210 @deffn Command {mflash config pll} frequency
4211 Configure mflash PLL.
4212 The @var{frequency} is the mflash input frequency, in Hz.
4213 Issuing this command will erase mflash's whole internal nand and write new pll.
4214 After this command, mflash needs power-on-reset for normal operation.
4215 If pll was newly configured, storage and boot(optional) info also need to be update.
4216 @end deffn
4217
4218 @deffn Command {mflash config boot}
4219 Configure bootable option.
4220 If bootable option is set, mflash offer the first 8 sectors
4221 (4kB) for boot.
4222 @end deffn
4223
4224 @deffn Command {mflash config storage}
4225 Configure storage information.
4226 For the normal storage operation, this information must be
4227 written.
4228 @end deffn
4229
4230 @deffn Command {mflash dump} num filename offset size
4231 Dump @var{size} bytes, starting at @var{offset} bytes from the
4232 beginning of the bank @var{num}, to the file named @var{filename}.
4233 @end deffn
4234
4235 @deffn Command {mflash probe}
4236 Probe mflash.
4237 @end deffn
4238
4239 @deffn Command {mflash write} num filename offset
4240 Write the binary file @var{filename} to mflash bank @var{num}, starting at
4241 @var{offset} bytes from the beginning of the bank.
4242 @end deffn
4243
4244 @node NAND Flash Commands
4245 @chapter NAND Flash Commands
4246 @cindex NAND
4247
4248 Compared to NOR or SPI flash, NAND devices are inexpensive
4249 and high density. Today's NAND chips, and multi-chip modules,
4250 commonly hold multiple GigaBytes of data.
4251
4252 NAND chips consist of a number of ``erase blocks'' of a given
4253 size (such as 128 KBytes), each of which is divided into a
4254 number of pages (of perhaps 512 or 2048 bytes each). Each
4255 page of a NAND flash has an ``out of band'' (OOB) area to hold
4256 Error Correcting Code (ECC) and other metadata, usually 16 bytes
4257 of OOB for every 512 bytes of page data.
4258
4259 One key characteristic of NAND flash is that its error rate
4260 is higher than that of NOR flash. In normal operation, that
4261 ECC is used to correct and detect errors. However, NAND
4262 blocks can also wear out and become unusable; those blocks
4263 are then marked "bad". NAND chips are even shipped from the
4264 manufacturer with a few bad blocks. The highest density chips
4265 use a technology (MLC) that wears out more quickly, so ECC
4266 support is increasingly important as a way to detect blocks
4267 that have begun to fail, and help to preserve data integrity
4268 with techniques such as wear leveling.
4269
4270 Software is used to manage the ECC. Some controllers don't
4271 support ECC directly; in those cases, software ECC is used.
4272 Other controllers speed up the ECC calculations with hardware.
4273 Single-bit error correction hardware is routine. Controllers
4274 geared for newer MLC chips may correct 4 or more errors for
4275 every 512 bytes of data.
4276
4277 You will need to make sure that any data you write using
4278 OpenOCD includes the apppropriate kind of ECC. For example,
4279 that may mean passing the @code{oob_softecc} flag when
4280 writing NAND data, or ensuring that the correct hardware
4281 ECC mode is used.
4282
4283 The basic steps for using NAND devices include:
4284 @enumerate
4285 @item Declare via the command @command{nand device}
4286 @* Do this in a board-specific configuration file,
4287 passing parameters as needed by the controller.
4288 @item Configure each device using @command{nand probe}.
4289 @* Do this only after the associated target is set up,
4290 such as in its reset-init script or in procures defined
4291 to access that device.
4292 @item Operate on the flash via @command{nand subcommand}
4293 @* Often commands to manipulate the flash are typed by a human, or run
4294 via a script in some automated way. Common task include writing a
4295 boot loader, operating system, or other data needed to initialize or
4296 de-brick a board.
4297 @end enumerate
4298
4299 @b{NOTE:} At the time this text was written, the largest NAND
4300 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
4301 This is because the variables used to hold offsets and lengths
4302 are only 32 bits wide.
4303 (Larger chips may work in some cases, unless an offset or length
4304 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
4305 Some larger devices will work, since they are actually multi-chip
4306 modules with two smaller chips and individual chipselect lines.
4307
4308 @anchor{NAND Configuration}
4309 @section NAND Configuration Commands
4310 @cindex NAND configuration
4311
4312 NAND chips must be declared in configuration scripts,
4313 plus some additional configuration that's done after
4314 OpenOCD has initialized.
4315
4316 @deffn {Config Command} {nand device} controller target [configparams...]
4317 Declares a NAND device, which can be read and written to
4318 after it has been configured through @command{nand probe}.
4319 In OpenOCD, devices are single chips; this is unlike some
4320 operating systems, which may manage multiple chips as if
4321 they were a single (larger) device.
4322 In some cases, configuring a device will activate extra
4323 commands; see the controller-specific documentation.
4324
4325 @b{NOTE:} This command is not available after OpenOCD
4326 initialization has completed. Use it in board specific
4327 configuration files, not interactively.
4328
4329 @itemize @bullet
4330 @item @var{controller} ... identifies the controller driver
4331 associated with the NAND device being declared.
4332 @xref{NAND Driver List}.
4333 @item @var{target} ... names the target used when issuing
4334 commands to the NAND controller.
4335 @comment Actually, it's currently a controller-specific parameter...
4336 @item @var{configparams} ... controllers may support, or require,
4337 additional parameters. See the controller-specific documentation
4338 for more information.
4339 @end itemize
4340 @end deffn
4341
4342 @deffn Command {nand list}
4343 Prints a summary of each device declared
4344 using @command{nand device}, numbered from zero.
4345 Note that un-probed devices show no details.
4346 @example
4347 > nand list
4348 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
4349 blocksize: 131072, blocks: 8192
4350 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
4351 blocksize: 131072, blocks: 8192
4352 >
4353 @end example
4354 @end deffn
4355
4356 @deffn Command {nand probe} num
4357 Probes the specified device to determine key characteristics
4358 like its page and block sizes, and how many blocks it has.
4359 The @var{num} parameter is the value shown by @command{nand list}.
4360 You must (successfully) probe a device before you can use
4361 it with most other NAND commands.
4362 @end deffn
4363
4364 @section Erasing, Reading, Writing to NAND Flash
4365
4366 @deffn Command {nand dump} num filename offset length [oob_option]
4367 @cindex NAND reading
4368 Reads binary data from the NAND device and writes it to the file,
4369 starting at the specified offset.
4370 The @var{num} parameter is the value shown by @command{nand list}.
4371
4372 Use a complete path name for @var{filename}, so you don't depend
4373 on the directory used to start the OpenOCD server.
4374
4375 The @var{offset} and @var{length} must be exact multiples of the
4376 device's page size. They describe a data region; the OOB data
4377 associated with each such page may also be accessed.
4378
4379 @b{NOTE:} At the time this text was written, no error correction
4380 was done on the data that's read, unless raw access was disabled
4381 and the underlying NAND controller driver had a @code{read_page}
4382 method which handled that error correction.
4383
4384 By default, only page data is saved to the specified file.
4385 Use an @var{oob_option} parameter to save OOB data:
4386 @itemize @bullet
4387 @item no oob_* parameter
4388 @*Output file holds only page data; OOB is discarded.
4389 @item @code{oob_raw}
4390 @*Output file interleaves page data and OOB data;
4391 the file will be longer than "length" by the size of the
4392 spare areas associated with each data page.
4393 Note that this kind of "raw" access is different from
4394 what's implied by @command{nand raw_access}, which just
4395 controls whether a hardware-aware access method is used.
4396 @item @code{oob_only}
4397 @*Output file has only raw OOB data, and will
4398 be smaller than "length" since it will contain only the
4399 spare areas associated with each data page.
4400 @end itemize
4401 @end deffn
4402
4403 @deffn Command {nand erase} num [offset length]
4404 @cindex NAND erasing
4405 @cindex NAND programming
4406 Erases blocks on the specified NAND device, starting at the
4407 specified @var{offset} and continuing for @var{length} bytes.
4408 Both of those values must be exact multiples of the device's
4409 block size, and the region they specify must fit entirely in the chip.
4410 If those parameters are not specified,
4411 the whole NAND chip will be erased.
4412 The @var{num} parameter is the value shown by @command{nand list}.
4413
4414 @b{NOTE:} This command will try to erase bad blocks, when told
4415 to do so, which will probably invalidate the manufacturer's bad
4416 block marker.
4417 For the remainder of the current server session, @command{nand info}
4418 will still report that the block ``is'' bad.
4419 @end deffn
4420
4421 @deffn Command {nand write} num filename offset [option...]
4422 @cindex NAND writing
4423 @cindex NAND programming
4424 Writes binary data from the file into the specified NAND device,
4425 starting at the specified offset. Those pages should already
4426 have been erased; you can't change zero bits to one bits.
4427 The @var{num} parameter is the value shown by @command{nand list}.
4428
4429 Use a complete path name for @var{filename}, so you don't depend
4430 on the directory used to start the OpenOCD server.
4431
4432 The @var{offset} must be an exact multiple of the device's page size.
4433 All data in the file will be written, assuming it doesn't run
4434 past the end of the device.
4435 Only full pages are written, and any extra space in the last
4436 page will be filled with 0xff bytes. (That includes OOB data,
4437 if that's being written.)
4438
4439 @b{NOTE:} At the time this text was written, bad blocks are
4440 ignored. That is, this routine will not skip bad blocks,
4441 but will instead try to write them. This can cause problems.
4442
4443 Provide at most one @var{option} parameter. With some
4444 NAND drivers, the meanings of these parameters may change
4445 if @command{nand raw_access} was used to disable hardware ECC.
4446 @itemize @bullet
4447 @item no oob_* parameter
4448 @*File has only page data, which is written.
4449 If raw acccess is in use, the OOB area will not be written.
4450 Otherwise, if the underlying NAND controller driver has
4451 a @code{write_page} routine, that routine may write the OOB
4452 with hardware-computed ECC data.
4453 @item @code{oob_only}
4454 @*File has only raw OOB data, which is written to the OOB area.
4455 Each page's data area stays untouched. @i{This can be a dangerous
4456 option}, since it can invalidate the ECC data.
4457 You may need to force raw access to use this mode.
4458 @item @code{oob_raw}
4459 @*File interleaves data and OOB data, both of which are written
4460 If raw access is enabled, the data is written first, then the
4461 un-altered OOB.
4462 Otherwise, if the underlying NAND controller driver has
4463 a @code{write_page} routine, that routine may modify the OOB
4464 before it's written, to include hardware-computed ECC data.
4465 @item @code{oob_softecc}
4466 @*File has only page data, which is written.
4467 The OOB area is filled with 0xff, except for a standard 1-bit
4468 software ECC code stored in conventional locations.
4469 You might need to force raw access to use this mode, to prevent
4470 the underlying driver from applying hardware ECC.
4471 @item @code{oob_softecc_kw}
4472 @*File has only page data, which is written.
4473 The OOB area is filled with 0xff, except for a 4-bit software ECC
4474 specific to the boot ROM in Marvell Kirkwood SoCs.
4475 You might need to force raw access to use this mode, to prevent
4476 the underlying driver from applying hardware ECC.
4477 @end itemize
4478 @end deffn
4479
4480 @section Other NAND commands
4481 @cindex NAND other commands
4482
4483 @deffn Command {nand check_bad_blocks} [offset length]
4484 Checks for manufacturer bad block markers on the specified NAND
4485 device. If no parameters are provided, checks the whole
4486 device; otherwise, starts at the specified @var{offset} and
4487 continues for @var{length} bytes.
4488 Both of those values must be exact multiples of the device's
4489 block size, and the region they specify must fit entirely in the chip.
4490 The @var{num} parameter is the value shown by @command{nand list}.
4491
4492 @b{NOTE:} Before using this command you should force raw access
4493 with @command{nand raw_access enable} to ensure that the underlying
4494 driver will not try to apply hardware ECC.
4495 @end deffn
4496
4497 @deffn Command {nand info} num
4498 The @var{num} parameter is the value shown by @command{nand list}.
4499 This prints the one-line summary from "nand list", plus for
4500 devices which have been probed this also prints any known
4501 status for each block.
4502 @end deffn
4503
4504 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
4505 Sets or clears an flag affecting how page I/O is done.
4506 The @var{num} parameter is the value shown by @command{nand list}.
4507
4508 This flag is cleared (disabled) by default, but changing that
4509 value won't affect all NAND devices. The key factor is whether
4510 the underlying driver provides @code{read_page} or @code{write_page}
4511 methods. If it doesn't provide those methods, the setting of
4512 this flag is irrelevant; all access is effectively ``raw''.
4513
4514 When those methods exist, they are normally used when reading
4515 data (@command{nand dump} or reading bad block markers) or
4516 writing it (@command{nand write}). However, enabling
4517 raw access (setting the flag) prevents use of those methods,
4518 bypassing hardware ECC logic.
4519 @i{This can be a dangerous option}, since writing blocks
4520 with the wrong ECC data can cause them to be marked as bad.
4521 @end deffn
4522
4523 @anchor{NAND Driver List}
4524 @section NAND Drivers, Options, and Commands
4525 As noted above, the @command{nand device} command allows
4526 driver-specific options and behaviors.
4527 Some controllers also activate controller-specific commands.
4528
4529 @deffn {NAND Driver} davinci
4530 This driver handles the NAND controllers found on DaVinci family
4531 chips from Texas Instruments.
4532 It takes three extra parameters:
4533 address of the NAND chip;
4534 hardware ECC mode to use (@option{hwecc1},
4535 @option{hwecc4}, @option{hwecc4_infix});
4536 address of the AEMIF controller on this processor.
4537 @example
4538 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
4539 @end example
4540 All DaVinci processors support the single-bit ECC hardware,
4541 and newer ones also support the four-bit ECC hardware.
4542 The @code{write_page} and @code{read_page} methods are used
4543 to implement those ECC modes, unless they are disabled using
4544 the @command{nand raw_access} command.
4545 @end deffn
4546
4547 @deffn {NAND Driver} lpc3180
4548 These controllers require an extra @command{nand device}
4549 parameter: the clock rate used by the controller.
4550 @deffn Command {lpc3180 select} num [mlc|slc]
4551 Configures use of the MLC or SLC controller mode.
4552 MLC implies use of hardware ECC.
4553 The @var{num} parameter is the value shown by @command{nand list}.
4554 @end deffn
4555
4556 At this writing, this driver includes @code{write_page}
4557 and @code{read_page} methods. Using @command{nand raw_access}
4558 to disable those methods will prevent use of hardware ECC
4559 in the MLC controller mode, but won't change SLC behavior.
4560 @end deffn
4561 @comment current lpc3180 code won't issue 5-byte address cycles
4562
4563 @deffn {NAND Driver} orion
4564 These controllers require an extra @command{nand device}
4565 parameter: the address of the controller.
4566 @example
4567 nand device orion 0xd8000000
4568 @end example
4569 These controllers don't define any specialized commands.
4570 At this writing, their drivers don't include @code{write_page}
4571 or @code{read_page} methods, so @command{nand raw_access} won't
4572 change any behavior.
4573 @end deffn
4574
4575 @deffn {NAND Driver} s3c2410
4576 @deffnx {NAND Driver} s3c2412
4577 @deffnx {NAND Driver} s3c2440
4578 @deffnx {NAND Driver} s3c2443
4579 These S3C24xx family controllers don't have any special
4580 @command{nand device} options, and don't define any
4581 specialized commands.
4582 At this writing, their drivers don't include @code{write_page}
4583 or @code{read_page} methods, so @command{nand raw_access} won't
4584 change any behavior.
4585 @end deffn
4586
4587 @node PLD/FPGA Commands
4588 @chapter PLD/FPGA Commands
4589 @cindex PLD
4590 @cindex FPGA
4591
4592 Programmable Logic Devices (PLDs) and the more flexible
4593 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
4594 OpenOCD can support programming them.
4595 Although PLDs are generally restrictive (cells are less functional, and
4596 there are no special purpose cells for memory or computational tasks),
4597 they share the same OpenOCD infrastructure.
4598 Accordingly, both are called PLDs here.
4599
4600 @section PLD/FPGA Configuration and Commands
4601
4602 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
4603 OpenOCD maintains a list of PLDs available for use in various commands.
4604 Also, each such PLD requires a driver.
4605
4606 They are referenced by the number shown by the @command{pld devices} command,
4607 and new PLDs are defined by @command{pld device driver_name}.
4608
4609 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
4610 Defines a new PLD device, supported by driver @var{driver_name},
4611 using the TAP named @var{tap_name}.
4612 The driver may make use of any @var{driver_options} to configure its
4613 behavior.
4614 @end deffn
4615
4616 @deffn {Command} {pld devices}
4617 Lists the PLDs and their numbers.
4618 @end deffn
4619
4620 @deffn {Command} {pld load} num filename
4621 Loads the file @file{filename} into the PLD identified by @var{num}.
4622 The file format must be inferred by the driver.
4623 @end deffn
4624
4625 @section PLD/FPGA Drivers, Options, and Commands
4626
4627 Drivers may support PLD-specific options to the @command{pld device}
4628 definition command, and may also define commands usable only with
4629 that particular type of PLD.
4630
4631 @deffn {FPGA Driver} virtex2
4632 Virtex-II is a family of FPGAs sold by Xilinx.
4633 It supports the IEEE 1532 standard for In-System Configuration (ISC).
4634 No driver-specific PLD definition options are used,
4635 and one driver-specific command is defined.
4636
4637 @deffn {Command} {virtex2 read_stat} num
4638 Reads and displays the Virtex-II status register (STAT)
4639 for FPGA @var{num}.
4640 @end deffn
4641 @end deffn
4642
4643 @node General Commands
4644 @chapter General Commands
4645 @cindex commands
4646
4647 The commands documented in this chapter here are common commands that
4648 you, as a human, may want to type and see the output of. Configuration type
4649 commands are documented elsewhere.
4650
4651 Intent:
4652 @itemize @bullet
4653 @item @b{Source Of Commands}
4654 @* OpenOCD commands can occur in a configuration script (discussed
4655 elsewhere) or typed manually by a human or supplied programatically,
4656 or via one of several TCP/IP Ports.
4657
4658 @item @b{From the human}
4659 @* A human should interact with the telnet interface (default port: 4444)
4660 or via GDB (default port 3333).
4661
4662 To issue commands from within a GDB session, use the @option{monitor}
4663 command, e.g. use @option{monitor poll} to issue the @option{poll}
4664 command. All output is relayed through the GDB session.
4665
4666 @item @b{Machine Interface}
4667 The Tcl interface's intent is to be a machine interface. The default Tcl
4668 port is 5555.
4669 @end itemize
4670
4671
4672 @section Daemon Commands
4673
4674 @deffn {Command} exit
4675 Exits the current telnet session.
4676 @end deffn
4677
4678 @c note EXTREMELY ANNOYING word wrap at column 75
4679 @c even when lines are e.g. 100+ columns ...
4680 @c coded in startup.tcl
4681 @deffn {Command} help [string]
4682 With no parameters, prints help text for all commands.
4683 Otherwise, prints each helptext containing @var{string}.
4684 Not every command provides helptext.
4685 @end deffn
4686
4687 @deffn Command sleep msec [@option{busy}]
4688 Wait for at least @var{msec} milliseconds before resuming.
4689 If @option{busy} is passed, busy-wait instead of sleeping.
4690 (This option is strongly discouraged.)
4691 Useful in connection with script files
4692 (@command{script} command and @command{target_name} configuration).
4693 @end deffn
4694
4695 @deffn Command shutdown
4696 Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
4697 @end deffn
4698
4699 @anchor{debug_level}
4700 @deffn Command debug_level [n]
4701 @cindex message level
4702 Display debug level.
4703 If @var{n} (from 0..3) is provided, then set it to that level.
4704 This affects the kind of messages sent to the server log.
4705 Level 0 is error messages only;
4706 level 1 adds warnings;
4707 level 2 adds informational messages;
4708 and level 3 adds debugging messages.
4709 The default is level 2, but that can be overridden on
4710 the command line along with the location of that log
4711 file (which is normally the server's standard output).
4712 @xref{Running}.
4713 @end deffn
4714
4715 @deffn Command fast (@option{enable}|@option{disable})
4716 Default disabled.
4717 Set default behaviour of OpenOCD to be "fast and dangerous".
4718
4719 At this writing, this only affects the defaults for two ARM7/ARM9 parameters:
4720 fast memory access, and DCC downloads. Those parameters may still be
4721 individually overridden.
4722
4723 The target specific "dangerous" optimisation tweaking options may come and go
4724 as more robust and user friendly ways are found to ensure maximum throughput
4725 and robustness with a minimum of configuration.
4726
4727 Typically the "fast enable" is specified first on the command line:
4728
4729 @example
4730 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
4731 @end example
4732 @end deffn
4733
4734 @deffn Command echo message
4735 Logs a message at "user" priority.
4736 Output @var{message} to stdout.
4737 @example
4738 echo "Downloading kernel -- please wait"
4739 @end example
4740 @end deffn
4741
4742 @deffn Command log_output [filename]
4743 Redirect logging to @var{filename};
4744 the initial log output channel is stderr.
4745 @end deffn
4746
4747 @anchor{Target State handling}
4748 @section Target State handling
4749 @cindex reset
4750 @cindex halt
4751 @cindex target initialization
4752
4753 In this section ``target'' refers to a CPU configured as
4754 shown earlier (@pxref{CPU Configuration}).
4755 These commands, like many, implicitly refer to
4756 a current target which is used to perform the
4757 various operations. The current target may be changed
4758 by using @command{targets} command with the name of the
4759 target which should become current.
4760
4761 @deffn Command reg [(number|name) [value]]
4762 Access a single register by @var{number} or by its @var{name}.
4763
4764 @emph{With no arguments}:
4765 list all available registers for the current target,
4766 showing number, name, size, value, and cache status.
4767
4768 @emph{With number/name}: display that register's value.
4769
4770 @emph{With both number/name and value}: set register's value.
4771
4772 Cores may have surprisingly many registers in their
4773 Debug and trace infrastructure:
4774
4775 @example
4776 > reg
4777 (0) r0 (/32): 0x0000D3C2 (dirty: 1, valid: 1)
4778 (1) r1 (/32): 0xFD61F31C (dirty: 0, valid: 1)
4779 (2) r2 (/32): 0x00022551 (dirty: 0, valid: 1)
4780 ...
4781 (164) ETM_CONTEXTID_COMPARATOR_MASK (/32): \
4782 0x00000000 (dirty: 0, valid: 0)
4783 >
4784 @end example
4785 @end deffn
4786
4787 @deffn Command halt [ms]
4788 @deffnx Command wait_halt [ms]
4789 The @command{halt} command first sends a halt request to the target,
4790 which @command{wait_halt} doesn't.
4791 Otherwise these behave the same: wait up to @var{ms} milliseconds,
4792 or 5 seconds if there is no parameter, for the target to halt
4793 (and enter debug mode).
4794 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
4795
4796 @quotation Warning
4797 On ARM cores, software using the @emph{wait for interrupt} operation
4798 often blocks the JTAG access needed by a @command{halt} command.
4799 This is because that operation also puts the core into a low
4800 power mode by gating the core clock;
4801 but the core clock is needed to detect JTAG clock transitions.
4802
4803 One partial workaround uses adaptive clocking: when the core is
4804 interrupted the operation completes, then JTAG clocks are accepted
4805 at least until the interrupt handler completes.
4806 However, this workaround is often unusable since the processor, board,
4807 and JTAG adapter must all support adaptive JTAG clocking.
4808 Also, it can't work until an interrupt is issued.
4809
4810 A more complete workaround is to not use that operation while you
4811 work with a JTAG debugger.
4812 Tasking environments generaly have idle loops where the body is the
4813 @emph{wait for interrupt} operation.
4814 (On older cores, it is a coprocessor action;
4815 newer cores have a @option{wfi} instruction.)
4816 Such loops can just remove that operation, at the cost of higher
4817 power consumption (because the CPU is needlessly clocked).
4818 @end quotation
4819
4820 @end deffn
4821
4822 @deffn Command resume [address]
4823 Resume the target at its current code position,
4824 or the optional @var{address} if it is provided.
4825 OpenOCD will wait 5 seconds for the target to resume.
4826 @end deffn
4827
4828 @deffn Command step [address]
4829 Single-step the target at its current code position,
4830 or the optional @var{address} if it is provided.
4831 @end deffn
4832
4833 @anchor{Reset Command}
4834 @deffn Command reset
4835 @deffnx Command {reset run}
4836 @deffnx Command {reset halt}
4837 @deffnx Command {reset init}
4838 Perform as hard a reset as possible, using SRST if possible.
4839 @emph{All defined targets will be reset, and target
4840 events will fire during the reset sequence.}
4841
4842 The optional parameter specifies what should
4843 happen after the reset.
4844 If there is no parameter, a @command{reset run} is executed.
4845 The other options will not work on all systems.
4846 @xref{Reset Configuration}.
4847
4848 @itemize @minus
4849 @item @b{run} Let the target run
4850 @item @b{halt} Immediately halt the target
4851 @item @b{init} Immediately halt the target, and execute the reset-init script
4852 @end itemize
4853 @end deffn
4854
4855 @deffn Command soft_reset_halt
4856 Requesting target halt and executing a soft reset. This is often used
4857 when a target cannot be reset and halted. The target, after reset is
4858 released begins to execute code. OpenOCD attempts to stop the CPU and
4859 then sets the program counter back to the reset vector. Unfortunately
4860 the code that was executed may have left the hardware in an unknown
4861 state.
4862 @end deffn
4863
4864 @section I/O Utilities
4865
4866 These commands are available when
4867 OpenOCD is built with @option{--enable-ioutil}.
4868 They are mainly useful on embedded targets,
4869 notably the ZY1000.
4870 Hosts with operating systems have complementary tools.
4871
4872 @emph{Note:} there are several more such commands.
4873
4874 @deffn Command append_file filename [string]*
4875 Appends the @var{string} parameters to
4876 the text file @file{filename}.
4877 Each string except the last one is followed by one space.
4878 The last string is followed by a newline.
4879 @end deffn
4880
4881 @deffn Command cat filename
4882 Reads and displays the text file @file{filename}.
4883 @end deffn
4884
4885 @deffn Command cp src_filename dest_filename
4886 Copies contents from the file @file{src_filename}
4887 into @file{dest_filename}.
4888 @end deffn
4889
4890 @deffn Command ip
4891 @emph{No description provided.}
4892 @end deffn
4893
4894 @deffn Command ls
4895 @emph{No description provided.}
4896 @end deffn
4897
4898 @deffn Command mac
4899 @emph{No description provided.}
4900 @end deffn
4901
4902 @deffn Command meminfo
4903 Display available RAM memory on OpenOCD host.
4904 Used in OpenOCD regression testing scripts.
4905 @end deffn
4906
4907 @deffn Command peek
4908 @emph{No description provided.}
4909 @end deffn
4910
4911 @deffn Command poke
4912 @emph{No description provided.}
4913 @end deffn
4914
4915 @deffn Command rm filename
4916 @c "rm" has both normal and Jim-level versions??
4917 Unlinks the file @file{filename}.
4918 @end deffn
4919
4920 @deffn Command trunc filename
4921 Removes all data in the file @file{filename}.
4922 @end deffn
4923
4924 @anchor{Memory access}
4925 @section Memory access commands
4926 @cindex memory access
4927
4928 These commands allow accesses of a specific size to the memory
4929 system. Often these are used to configure the current target in some
4930 special way. For example - one may need to write certain values to the
4931 SDRAM controller to enable SDRAM.
4932
4933 @enumerate
4934 @item Use the @command{targets} (plural) command
4935 to change the current target.
4936 @item In system level scripts these commands are deprecated.
4937 Please use their TARGET object siblings to avoid making assumptions
4938 about what TAP is the current target, or about MMU configuration.
4939 @end enumerate
4940
4941 @deffn Command mdw [phys] addr [count]
4942 @deffnx Command mdh [phys] addr [count]
4943 @deffnx Command mdb [phys] addr [count]
4944 Display contents of address @var{addr}, as
4945 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4946 or 8-bit bytes (@command{mdb}).
4947 If @var{count} is specified, displays that many units.
4948 @var{phys} is an optional flag to indicate to use
4949 physical address and bypass MMU
4950 (If you want to manipulate the data instead of displaying it,
4951 see the @code{mem2array} primitives.)
4952 @end deffn
4953
4954 @deffn Command mww [phys] addr word
4955 @deffnx Command mwh [phys] addr halfword
4956 @deffnx Command mwb [phys] addr byte
4957 Writes the specified @var{word} (32 bits),
4958 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4959 at the specified address @var{addr}.
4960 @var{phys} is an optional flag to indicate to use
4961 physical address and bypass MMU
4962 @end deffn
4963
4964
4965 @anchor{Image access}
4966 @section Image loading commands
4967 @cindex image loading
4968 @cindex image dumping
4969
4970 @anchor{dump_image}
4971 @deffn Command {dump_image} filename address size
4972 Dump @var{size} bytes of target memory starting at @var{address} to the
4973 binary file named @var{filename}.
4974 @end deffn
4975
4976 @deffn Command {fast_load}
4977 Loads an image stored in memory by @command{fast_load_image} to the
4978 current target. Must be preceeded by fast_load_image.
4979 @end deffn
4980
4981 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4982 Normally you should be using @command{load_image} or GDB load. However, for
4983 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
4984 host), storing the image in memory and uploading the image to the target
4985 can be a way to upload e.g. multiple debug sessions when the binary does not change.
4986 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
4987 memory, i.e. does not affect target. This approach is also useful when profiling
4988 target programming performance as I/O and target programming can easily be profiled
4989 separately.
4990 @end deffn
4991
4992 @anchor{load_image}
4993 @deffn Command {load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4994 Load image from file @var{filename} to target memory at @var{address}.
4995 The file format may optionally be specified
4996 (@option{bin}, @option{ihex}, or @option{elf})
4997 @end deffn
4998
4999 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
5000 Displays image section sizes and addresses
5001 as if @var{filename} were loaded into target memory
5002 starting at @var{address} (defaults to zero).
5003 The file format may optionally be specified
5004 (@option{bin}, @option{ihex}, or @option{elf})
5005 @end deffn
5006
5007 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
5008 Verify @var{filename} against target memory starting at @var{address}.
5009 The file format may optionally be specified
5010 (@option{bin}, @option{ihex}, or @option{elf})
5011 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
5012 @end deffn
5013
5014
5015 @section Breakpoint and Watchpoint commands
5016 @cindex breakpoint
5017 @cindex watchpoint
5018
5019 CPUs often make debug modules accessible through JTAG, with
5020 hardware support for a handful of code breakpoints and data
5021 watchpoints.
5022 In addition, CPUs almost always support software breakpoints.
5023
5024 @deffn Command {bp} [address len [@option{hw}]]
5025 With no parameters, lists all active breakpoints.
5026 Else sets a breakpoint on code execution starting
5027 at @var{address} for @var{length} bytes.
5028 This is a software breakpoint, unless @option{hw} is specified
5029 in which case it will be a hardware breakpoint.
5030
5031 (@xref{arm9tdmi vector_catch}, or @pxref{xscale vector_catch},
5032 for similar mechanisms that do not consume hardware breakpoints.)
5033 @end deffn
5034
5035 @deffn Command {rbp} address
5036 Remove the breakpoint at @var{address}.
5037 @end deffn
5038
5039 @deffn Command {rwp} address
5040 Remove data watchpoint on @var{address}
5041 @end deffn
5042
5043 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
5044 With no parameters, lists all active watchpoints.
5045 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
5046 The watch point is an "access" watchpoint unless
5047 the @option{r} or @option{w} parameter is provided,
5048 defining it as respectively a read or write watchpoint.
5049 If a @var{value} is provided, that value is used when determining if
5050 the watchpoint should trigger. The value may be first be masked
5051 using @var{mask} to mark ``don't care'' fields.
5052 @end deffn
5053
5054 @section Misc Commands
5055
5056 @cindex profiling
5057 @deffn Command {profile} seconds filename
5058 Profiling samples the CPU's program counter as quickly as possible,
5059 which is useful for non-intrusive stochastic profiling.
5060 Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
5061 @end deffn
5062
5063 @deffn Command {version}
5064 Displays a string identifying the version of this OpenOCD server.
5065 @end deffn
5066
5067 @deffn Command {virt2phys} virtual_address
5068 Requests the current target to map the specified @var{virtual_address}
5069 to its corresponding physical address, and displays the result.
5070 @end deffn
5071
5072 @node Architecture and Core Commands
5073 @chapter Architecture and Core Commands
5074 @cindex Architecture Specific Commands
5075 @cindex Core Specific Commands
5076
5077 Most CPUs have specialized JTAG operations to support debugging.
5078 OpenOCD packages most such operations in its standard command framework.
5079 Some of those operations don't fit well in that framework, so they are
5080 exposed here as architecture or implementation (core) specific commands.
5081
5082 @anchor{ARM Hardware Tracing}
5083 @section ARM Hardware Tracing
5084 @cindex tracing
5085 @cindex ETM
5086 @cindex ETB
5087
5088 CPUs based on ARM cores may include standard tracing interfaces,
5089 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
5090 address and data bus trace records to a ``Trace Port''.
5091
5092 @itemize
5093 @item
5094 Development-oriented boards will sometimes provide a high speed
5095 trace connector for collecting that data, when the particular CPU
5096 supports such an interface.
5097 (The standard connector is a 38-pin Mictor, with both JTAG
5098 and trace port support.)
5099 Those trace connectors are supported by higher end JTAG adapters
5100 and some logic analyzer modules; frequently those modules can
5101 buffer several megabytes of trace data.
5102 Configuring an ETM coupled to such an external trace port belongs
5103 in the board-specific configuration file.
5104 @item
5105 If the CPU doesn't provide an external interface, it probably
5106 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
5107 dedicated SRAM. 4KBytes is one common ETB size.
5108 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
5109 (target) configuration file, since it works the same on all boards.
5110 @end itemize
5111
5112 ETM support in OpenOCD doesn't seem to be widely used yet.
5113
5114 @quotation Issues
5115 ETM support may be buggy, and at least some @command{etm config}
5116 parameters should be detected by asking the ETM for them.
5117
5118 ETM trigger events could also implement a kind of complex
5119 hardware break