[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * NAND Flash Commands:: NAND Flash Commands
77 * PLD/FPGA Commands:: PLD/FPGA Commands
78 * General Commands:: General Commands
79 * Architecture and Core Commands:: Architecture and Core Commands
80 * JTAG Commands:: JTAG Commands
81 * Boundary Scan Commands:: Boundary Scan Commands
82 * TFTP:: TFTP
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
95 @end menu
97 @node About
98 @unnumbered About
99 @cindex about
101 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
102 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
105 around the world.
107 @section What is OpenOCD?
108 @cindex TAP
109 @cindex JTAG
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
113 devices.
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board can be directly connected to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
140 scan operations.
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD only supports
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
154 based, parallel port based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
159 Cortex-M3 (Stellaris LM3, ST STM32 and Energy Micro EFM32) based cores to be
160 debugged via the GDB protocol.
162 @b{Flash Programing:} Flash writing is supported for external CFI
163 compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3,
165 STM32x and EFM32). Preliminary support for various NAND flash controllers
166 (LPC3180, Orion, S3C24xx, more) controller is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{http://openocd.sourceforge.net/}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{http://openocd.sourceforge.net/doc/html/index.html}
182 PDF form is likewise published at:
184 @uref{http://openocd.sourceforge.net/doc/pdf/openocd.pdf}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
203 @section OpenOCD IRC
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
208 @node Developers
209 @chapter OpenOCD Developer Resources
210 @cindex developers
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD GIT Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a GIT repository hosted at SourceForge. The repository URL is:
225 @uref{git://git.code.sf.net/p/openocd/code}
227 or via http
229 @uref{http://git.code.sf.net/p/openocd/code}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{http://repo.or.cz/r/openocd.git}
235 With standard GIT tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a GIT client:
241 @uref{http://repo.or.cz/w/openocd.git}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{http://openocd.sourceforge.net/doc/doxygen/html/index.html}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration in the top of the source tree.
264 @section OpenOCD Developer Mailing List
266 The OpenOCD Developer Mailing List provides the primary means of
267 communication between developers:
269 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
271 Discuss and submit patches to this list.
272 The @file{HACKING} file contains basic information about how
273 to prepare patches.
275 @section OpenOCD Bug Database
277 During the 0.4.x release cycle the OpenOCD project team began
278 using Trac for its bug database:
280 @uref{https://sourceforge.net/apps/trac/openocd}
283 @node Debug Adapter Hardware
284 @chapter Debug Adapter Hardware
285 @cindex dongles
286 @cindex FTDI
287 @cindex wiggler
288 @cindex zy1000
289 @cindex printer port
290 @cindex USB Adapter
291 @cindex RTCK
293 Defined: @b{dongle}: A small device that plugins into a computer and serves as
294 an adapter .... [snip]
296 In the OpenOCD case, this generally refers to @b{a small adapter} that
297 attaches to your computer via USB or the Parallel Printer Port. One
298 exception is the Zylin ZY1000, packaged as a small box you attach via
299 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
300 require any drivers to be installed on the developer PC. It also has
301 a built in web interface. It supports RTCK/RCLK or adaptive clocking
302 and has a built in relay to power cycle targets remotely.
305 @section Choosing a Dongle
307 There are several things you should keep in mind when choosing a dongle.
309 @enumerate
310 @item @b{Transport} Does it support the kind of communication that you need?
311 OpenOCD focusses mostly on JTAG. Your version may also support
312 other ways to communicate with target devices.
313 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
314 Does your dongle support it? You might need a level converter.
315 @item @b{Pinout} What pinout does your target board use?
316 Does your dongle support it? You may be able to use jumper
317 wires, or an "octopus" connector, to convert pinouts.
318 @item @b{Connection} Does your computer have the USB, printer, or
319 Ethernet port needed?
320 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
321 RTCK support? Also known as ``adaptive clocking''
322 @end enumerate
324 @section Stand alone Systems
326 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/33-zylin-zy1000-jtag-probe}
327 Technically, not a dongle, but a standalone box. The ZY1000 has the advantage that it does
328 not require any drivers installed on the developer PC. It also has
329 a built in web interface. It supports RTCK/RCLK or adaptive clocking
330 and has a built in relay to power cycle targets remotely.
332 @section USB FT2232 Based
334 There are many USB JTAG dongles on the market, many of them are based
335 on a chip from ``Future Technology Devices International'' (FTDI)
336 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
337 See: @url{http://www.ftdichip.com} for more information.
338 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
339 chips are starting to become available in JTAG adapters. (Adapters
340 using those high speed FT2232H chips may support adaptive clocking.)
342 The FT2232 chips are flexible enough to support some other
343 transport options, such as SWD or the SPI variants used to
344 program some chips. They have two communications channels,
345 and one can be used for a UART adapter at the same time the
346 other one is used to provide a debug adapter.
348 Also, some development boards integrate an FT2232 chip to serve as
349 a built-in low cost debug adapter and usb-to-serial solution.
351 @itemize @bullet
352 @item @b{usbjtag}
353 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
354 @item @b{jtagkey}
355 @* See: @url{http://www.amontec.com/jtagkey.shtml}
356 @item @b{jtagkey2}
357 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
358 @item @b{oocdlink}
359 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
360 @item @b{signalyzer}
361 @* See: @url{http://www.signalyzer.com}
362 @item @b{Stellaris Eval Boards}
363 @* See: @url{http://www.ti.com} - The Stellaris eval boards
364 bundle FT2232-based JTAG and SWD support, which can be used to debug
365 the Stellaris chips. Using separate JTAG adapters is optional.
366 These boards can also be used in a "pass through" mode as JTAG adapters
367 to other target boards, disabling the Stellaris chip.
368 @item @b{TI/Luminary ICDI}
369 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
370 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
371 Evaluation Kits. Like the non-detachable FT2232 support on the other
372 Stellaris eval boards, they can be used to debug other target boards.
373 @item @b{olimex-jtag}
374 @* See: @url{http://www.olimex.com}
375 @item @b{Flyswatter/Flyswatter2}
376 @* See: @url{http://www.tincantools.com}
377 @item @b{turtelizer2}
378 @* See:
379 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
380 @url{http://www.ethernut.de}
381 @item @b{comstick}
382 @* Link: @url{http://www.hitex.com/index.php?id=383}
383 @item @b{stm32stick}
384 @* Link @url{http://www.hitex.com/stm32-stick}
385 @item @b{axm0432_jtag}
386 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
387 to be available anymore as of April 2012.
388 @item @b{cortino}
389 @* Link @url{http://www.hitex.com/index.php?id=cortino}
390 @item @b{dlp-usb1232h}
391 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
392 @item @b{digilent-hs1}
393 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
394 @item @b{opendous}
395 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
396 (OpenHardware).
397 @end itemize
399 @section USB-JTAG / Altera USB-Blaster compatibles
401 These devices also show up as FTDI devices, but are not
402 protocol-compatible with the FT2232 devices. They are, however,
403 protocol-compatible among themselves. USB-JTAG devices typically consist
404 of a FT245 followed by a CPLD that understands a particular protocol,
405 or emulate this protocol using some other hardware.
407 They may appear under different USB VID/PID depending on the particular
408 product. The driver can be configured to search for any VID/PID pair
409 (see the section on driver commands).
411 @itemize
412 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
413 @* Link: @url{http://ixo-jtag.sourceforge.net/}
414 @item @b{Altera USB-Blaster}
415 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
416 @end itemize
418 @section USB JLINK based
419 There are several OEM versions of the Segger @b{JLINK} adapter. It is
420 an example of a micro controller based JTAG adapter, it uses an
421 AT91SAM764 internally.
423 @itemize @bullet
424 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
425 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
426 @item @b{SEGGER JLINK}
427 @* Link: @url{http://www.segger.com/jlink.html}
428 @item @b{IAR J-Link}
429 @* Link: @url{http://www.iar.com/en/products/hardware-debug-probes/iar-j-link/}
430 @end itemize
432 @section USB RLINK based
433 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
434 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
435 SWD and not JTAG, thus not supported.
437 @itemize @bullet
438 @item @b{Raisonance RLink}
439 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
440 @item @b{STM32 Primer}
441 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
442 @item @b{STM32 Primer2}
443 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
444 @end itemize
446 @section USB ST-LINK based
447 ST Micro has an adapter called @b{ST-LINK}.
448 They only work with ST Micro chips, notably STM32 and STM8.
450 @itemize @bullet
451 @item @b{ST-LINK}
452 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
453 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
454 @item @b{ST-LINK/V2}
455 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
456 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
457 @end itemize
459 For info the original ST-LINK enumerates using the mass storage usb class, however
460 it's implementation is completely broken. The result is this causes issues under linux.
461 The simplest solution is to get linux to ignore the ST-LINK using one of the following methods:
462 @itemize @bullet
463 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
464 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
465 @end itemize
467 @section USB TI/Stellaris ICDI based
468 Texas Instruments has an adapter called @b{ICDI}.
469 It is not to be confused with the FTDI based adapters that were originally fitted to their
470 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
472 @section USB Other
473 @itemize @bullet
474 @item @b{USBprog}
475 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
477 @item @b{USB - Presto}
478 @* Link: @url{http://tools.asix.net/prg_presto.htm}
480 @item @b{Versaloon-Link}
481 @* Link: @url{http://www.versaloon.com}
483 @item @b{ARM-JTAG-EW}
484 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
486 @item @b{Buspirate}
487 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
489 @item @b{opendous}
490 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
492 @item @b{estick}
493 @* Link: @url{http://code.google.com/p/estick-jtag/}
495 @item @b{Keil ULINK v1}
496 @* Link: @url{http://www.keil.com/ulink1/}
497 @end itemize
499 @section IBM PC Parallel Printer Port Based
501 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
502 and the Macraigor Wiggler. There are many clones and variations of
503 these on the market.
505 Note that parallel ports are becoming much less common, so if you
506 have the choice you should probably avoid these adapters in favor
507 of USB-based ones.
509 @itemize @bullet
511 @item @b{Wiggler} - There are many clones of this.
512 @* Link: @url{http://www.macraigor.com/wiggler.htm}
514 @item @b{DLC5} - From XILINX - There are many clones of this
515 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
516 produced, PDF schematics are easily found and it is easy to make.
518 @item @b{Amontec - JTAG Accelerator}
519 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
521 @item @b{GW16402}
522 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
524 @item @b{Wiggler2}
525 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
527 @item @b{Wiggler_ntrst_inverted}
528 @* Yet another variation - See the source code, src/jtag/parport.c
530 @item @b{old_amt_wiggler}
531 @* Unknown - probably not on the market today
533 @item @b{arm-jtag}
534 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
536 @item @b{chameleon}
537 @* Link: @url{http://www.amontec.com/chameleon.shtml}
539 @item @b{Triton}
540 @* Unknown.
542 @item @b{Lattice}
543 @* ispDownload from Lattice Semiconductor
544 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
546 @item @b{flashlink}
547 @* From ST Microsystems;
548 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
550 @end itemize
552 @section Other...
553 @itemize @bullet
555 @item @b{ep93xx}
556 @* An EP93xx based Linux machine using the GPIO pins directly.
558 @item @b{at91rm9200}
559 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
561 @end itemize
563 @node About Jim-Tcl
564 @chapter About Jim-Tcl
565 @cindex Jim-Tcl
566 @cindex tcl
568 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
569 This programming language provides a simple and extensible
570 command interpreter.
572 All commands presented in this Guide are extensions to Jim-Tcl.
573 You can use them as simple commands, without needing to learn
574 much of anything about Tcl.
575 Alternatively, can write Tcl programs with them.
577 You can learn more about Jim at its website, @url{http://jim.berlios.de}.
578 There is an active and responsive community, get on the mailing list
579 if you have any questions. Jim-Tcl maintainers also lurk on the
580 OpenOCD mailing list.
582 @itemize @bullet
583 @item @b{Jim vs. Tcl}
584 @* Jim-Tcl is a stripped down version of the well known Tcl language,
585 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
586 fewer features. Jim-Tcl is several dozens of .C files and .H files and
587 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
588 4.2 MB .zip file containing 1540 files.
590 @item @b{Missing Features}
591 @* Our practice has been: Add/clone the real Tcl feature if/when
592 needed. We welcome Jim-Tcl improvements, not bloat. Also there
593 are a large number of optional Jim-Tcl features that are not
594 enabled in OpenOCD.
596 @item @b{Scripts}
597 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
598 command interpreter today is a mixture of (newer)
599 Jim-Tcl commands, and (older) the orginal command interpreter.
601 @item @b{Commands}
602 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
603 can type a Tcl for() loop, set variables, etc.
604 Some of the commands documented in this guide are implemented
605 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
607 @item @b{Historical Note}
608 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
609 before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
610 as a git submodule, which greatly simplified upgrading Jim Tcl
611 to benefit from new features and bugfixes in Jim Tcl.
613 @item @b{Need a crash course in Tcl?}
614 @*@xref{Tcl Crash Course}.
615 @end itemize
617 @node Running
618 @chapter Running
619 @cindex command line options
620 @cindex logfile
621 @cindex directory search
623 Properly installing OpenOCD sets up your operating system to grant it access
624 to the debug adapters. On Linux, this usually involves installing a file
625 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
626 complex and confusing driver configuration for every peripheral. Such issues
627 are unique to each operating system, and are not detailed in this User's Guide.
629 Then later you will invoke the OpenOCD server, with various options to
630 tell it how each debug session should work.
631 The @option{--help} option shows:
632 @verbatim
633 bash$ openocd --help
635 --help | -h display this help
636 --version | -v display OpenOCD version
637 --file | -f use configuration file <name>
638 --search | -s dir to search for config files and scripts
639 --debug | -d set debug level <0-3>
640 --log_output | -l redirect log output to file <name>
641 --command | -c run <command>
642 @end verbatim
644 If you don't give any @option{-f} or @option{-c} options,
645 OpenOCD tries to read the configuration file @file{openocd.cfg}.
646 To specify one or more different
647 configuration files, use @option{-f} options. For example:
649 @example
650 openocd -f config1.cfg -f config2.cfg -f config3.cfg
651 @end example
653 Configuration files and scripts are searched for in
654 @enumerate
655 @item the current directory,
656 @item any search dir specified on the command line using the @option{-s} option,
657 @item any search dir specified using the @command{add_script_search_dir} command,
658 @item @file{$HOME/.openocd} (not on Windows),
659 @item the site wide script library @file{$pkgdatadir/site} and
660 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
661 @end enumerate
662 The first found file with a matching file name will be used.
664 @quotation Note
665 Don't try to use configuration script names or paths which
666 include the "#" character. That character begins Tcl comments.
667 @end quotation
669 @section Simple setup, no customization
671 In the best case, you can use two scripts from one of the script
672 libraries, hook up your JTAG adapter, and start the server ... and
673 your JTAG setup will just work "out of the box". Always try to
674 start by reusing those scripts, but assume you'll need more
675 customization even if this works. @xref{OpenOCD Project Setup}.
677 If you find a script for your JTAG adapter, and for your board or
678 target, you may be able to hook up your JTAG adapter then start
679 the server like:
681 @example
682 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
683 @end example
685 You might also need to configure which reset signals are present,
686 using @option{-c 'reset_config trst_and_srst'} or something similar.
687 If all goes well you'll see output something like
689 @example
690 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
691 For bug reports, read
692 http://openocd.sourceforge.net/doc/doxygen/bugs.html
693 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
694 (mfg: 0x23b, part: 0xba00, ver: 0x3)
695 @end example
697 Seeing that "tap/device found" message, and no warnings, means
698 the JTAG communication is working. That's a key milestone, but
699 you'll probably need more project-specific setup.
701 @section What OpenOCD does as it starts
703 OpenOCD starts by processing the configuration commands provided
704 on the command line or, if there were no @option{-c command} or
705 @option{-f file.cfg} options given, in @file{openocd.cfg}.
706 @xref{configurationstage,,Configuration Stage}.
707 At the end of the configuration stage it verifies the JTAG scan
708 chain defined using those commands; your configuration should
709 ensure that this always succeeds.
710 Normally, OpenOCD then starts running as a daemon.
711 Alternatively, commands may be used to terminate the configuration
712 stage early, perform work (such as updating some flash memory),
713 and then shut down without acting as a daemon.
715 Once OpenOCD starts running as a daemon, it waits for connections from
716 clients (Telnet, GDB, Other) and processes the commands issued through
717 those channels.
719 If you are having problems, you can enable internal debug messages via
720 the @option{-d} option.
722 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
723 @option{-c} command line switch.
725 To enable debug output (when reporting problems or working on OpenOCD
726 itself), use the @option{-d} command line switch. This sets the
727 @option{debug_level} to "3", outputting the most information,
728 including debug messages. The default setting is "2", outputting only
729 informational messages, warnings and errors. You can also change this
730 setting from within a telnet or gdb session using @command{debug_level<n>}
731 (@pxref{debuglevel,,debug_level}).
733 You can redirect all output from the daemon to a file using the
734 @option{-l <logfile>} switch.
736 Note! OpenOCD will launch the GDB & telnet server even if it can not
737 establish a connection with the target. In general, it is possible for
738 the JTAG controller to be unresponsive until the target is set up
739 correctly via e.g. GDB monitor commands in a GDB init script.
741 @node OpenOCD Project Setup
742 @chapter OpenOCD Project Setup
744 To use OpenOCD with your development projects, you need to do more than
745 just connecting the JTAG adapter hardware (dongle) to your development board
746 and then starting the OpenOCD server.
747 You also need to configure that server so that it knows
748 about that adapter and board, and helps your work.
749 You may also want to connect OpenOCD to GDB, possibly
750 using Eclipse or some other GUI.
752 @section Hooking up the JTAG Adapter
754 Today's most common case is a dongle with a JTAG cable on one side
755 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
756 and a USB cable on the other.
757 Instead of USB, some cables use Ethernet;
758 older ones may use a PC parallel port, or even a serial port.
760 @enumerate
761 @item @emph{Start with power to your target board turned off},
762 and nothing connected to your JTAG adapter.
763 If you're particularly paranoid, unplug power to the board.
764 It's important to have the ground signal properly set up,
765 unless you are using a JTAG adapter which provides
766 galvanic isolation between the target board and the
767 debugging host.
769 @item @emph{Be sure it's the right kind of JTAG connector.}
770 If your dongle has a 20-pin ARM connector, you need some kind
771 of adapter (or octopus, see below) to hook it up to
772 boards using 14-pin or 10-pin connectors ... or to 20-pin
773 connectors which don't use ARM's pinout.
775 In the same vein, make sure the voltage levels are compatible.
776 Not all JTAG adapters have the level shifters needed to work
777 with 1.2 Volt boards.
779 @item @emph{Be certain the cable is properly oriented} or you might
780 damage your board. In most cases there are only two possible
781 ways to connect the cable.
782 Connect the JTAG cable from your adapter to the board.
783 Be sure it's firmly connected.
785 In the best case, the connector is keyed to physically
786 prevent you from inserting it wrong.
787 This is most often done using a slot on the board's male connector
788 housing, which must match a key on the JTAG cable's female connector.
789 If there's no housing, then you must look carefully and
790 make sure pin 1 on the cable hooks up to pin 1 on the board.
791 Ribbon cables are frequently all grey except for a wire on one
792 edge, which is red. The red wire is pin 1.
794 Sometimes dongles provide cables where one end is an ``octopus'' of
795 color coded single-wire connectors, instead of a connector block.
796 These are great when converting from one JTAG pinout to another,
797 but are tedious to set up.
798 Use these with connector pinout diagrams to help you match up the
799 adapter signals to the right board pins.
801 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
802 A USB, parallel, or serial port connector will go to the host which
803 you are using to run OpenOCD.
804 For Ethernet, consult the documentation and your network administrator.
806 For USB based JTAG adapters you have an easy sanity check at this point:
807 does the host operating system see the JTAG adapter? If that host is an
808 MS-Windows host, you'll need to install a driver before OpenOCD works.
810 @item @emph{Connect the adapter's power supply, if needed.}
811 This step is primarily for non-USB adapters,
812 but sometimes USB adapters need extra power.
814 @item @emph{Power up the target board.}
815 Unless you just let the magic smoke escape,
816 you're now ready to set up the OpenOCD server
817 so you can use JTAG to work with that board.
819 @end enumerate
821 Talk with the OpenOCD server using
822 telnet (@code{telnet localhost 4444} on many systems) or GDB.
823 @xref{GDB and OpenOCD}.
825 @section Project Directory
827 There are many ways you can configure OpenOCD and start it up.
829 A simple way to organize them all involves keeping a
830 single directory for your work with a given board.
831 When you start OpenOCD from that directory,
832 it searches there first for configuration files, scripts,
833 files accessed through semihosting,
834 and for code you upload to the target board.
835 It is also the natural place to write files,
836 such as log files and data you download from the board.
838 @section Configuration Basics
840 There are two basic ways of configuring OpenOCD, and
841 a variety of ways you can mix them.
842 Think of the difference as just being how you start the server:
844 @itemize
845 @item Many @option{-f file} or @option{-c command} options on the command line
846 @item No options, but a @dfn{user config file}
847 in the current directory named @file{openocd.cfg}
848 @end itemize
850 Here is an example @file{openocd.cfg} file for a setup
851 using a Signalyzer FT2232-based JTAG adapter to talk to
852 a board with an Atmel AT91SAM7X256 microcontroller:
854 @example
855 source [find interface/signalyzer.cfg]
857 # GDB can also flash my flash!
858 gdb_memory_map enable
859 gdb_flash_program enable
861 source [find target/sam7x256.cfg]
862 @end example
864 Here is the command line equivalent of that configuration:
866 @example
867 openocd -f interface/signalyzer.cfg \
868 -c "gdb_memory_map enable" \
869 -c "gdb_flash_program enable" \
870 -f target/sam7x256.cfg
871 @end example
873 You could wrap such long command lines in shell scripts,
874 each supporting a different development task.
875 One might re-flash the board with a specific firmware version.
876 Another might set up a particular debugging or run-time environment.
878 @quotation Important
879 At this writing (October 2009) the command line method has
880 problems with how it treats variables.
881 For example, after @option{-c "set VAR value"}, or doing the
882 same in a script, the variable @var{VAR} will have no value
883 that can be tested in a later script.
884 @end quotation
886 Here we will focus on the simpler solution: one user config
887 file, including basic configuration plus any TCL procedures
888 to simplify your work.
890 @section User Config Files
891 @cindex config file, user
892 @cindex user config file
893 @cindex config file, overview
895 A user configuration file ties together all the parts of a project
896 in one place.
897 One of the following will match your situation best:
899 @itemize
900 @item Ideally almost everything comes from configuration files
901 provided by someone else.
902 For example, OpenOCD distributes a @file{scripts} directory
903 (probably in @file{/usr/share/openocd/scripts} on Linux).
904 Board and tool vendors can provide these too, as can individual
905 user sites; the @option{-s} command line option lets you say
906 where to find these files. (@xref{Running}.)
907 The AT91SAM7X256 example above works this way.
909 Three main types of non-user configuration file each have their
910 own subdirectory in the @file{scripts} directory:
912 @enumerate
913 @item @b{interface} -- one for each different debug adapter;
914 @item @b{board} -- one for each different board
915 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
916 @end enumerate
918 Best case: include just two files, and they handle everything else.
919 The first is an interface config file.
920 The second is board-specific, and it sets up the JTAG TAPs and
921 their GDB targets (by deferring to some @file{target.cfg} file),
922 declares all flash memory, and leaves you nothing to do except
923 meet your deadline:
925 @example
926 source [find interface/olimex-jtag-tiny.cfg]
927 source [find board/csb337.cfg]
928 @end example
930 Boards with a single microcontroller often won't need more
931 than the target config file, as in the AT91SAM7X256 example.
932 That's because there is no external memory (flash, DDR RAM), and
933 the board differences are encapsulated by application code.
935 @item Maybe you don't know yet what your board looks like to JTAG.
936 Once you know the @file{interface.cfg} file to use, you may
937 need help from OpenOCD to discover what's on the board.
938 Once you find the JTAG TAPs, you can just search for appropriate
939 target and board
940 configuration files ... or write your own, from the bottom up.
941 @xref{autoprobing,,Autoprobing}.
943 @item You can often reuse some standard config files but
944 need to write a few new ones, probably a @file{board.cfg} file.
945 You will be using commands described later in this User's Guide,
946 and working with the guidelines in the next chapter.
948 For example, there may be configuration files for your JTAG adapter
949 and target chip, but you need a new board-specific config file
950 giving access to your particular flash chips.
951 Or you might need to write another target chip configuration file
952 for a new chip built around the Cortex M3 core.
954 @quotation Note
955 When you write new configuration files, please submit
956 them for inclusion in the next OpenOCD release.
957 For example, a @file{board/newboard.cfg} file will help the
958 next users of that board, and a @file{target/newcpu.cfg}
959 will help support users of any board using that chip.
960 @end quotation
962 @item
963 You may may need to write some C code.
964 It may be as simple as a supporting a new ft2232 or parport
965 based adapter; a bit more involved, like a NAND or NOR flash
966 controller driver; or a big piece of work like supporting
967 a new chip architecture.
968 @end itemize
970 Reuse the existing config files when you can.
971 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
972 You may find a board configuration that's a good example to follow.
974 When you write config files, separate the reusable parts
975 (things every user of that interface, chip, or board needs)
976 from ones specific to your environment and debugging approach.
977 @itemize
979 @item
980 For example, a @code{gdb-attach} event handler that invokes
981 the @command{reset init} command will interfere with debugging
982 early boot code, which performs some of the same actions
983 that the @code{reset-init} event handler does.
985 @item
986 Likewise, the @command{arm9 vector_catch} command (or
987 @cindex vector_catch
988 its siblings @command{xscale vector_catch}
989 and @command{cortex_m3 vector_catch}) can be a timesaver
990 during some debug sessions, but don't make everyone use that either.
991 Keep those kinds of debugging aids in your user config file,
992 along with messaging and tracing setup.
993 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
995 @item
996 You might need to override some defaults.
997 For example, you might need to move, shrink, or back up the target's
998 work area if your application needs much SRAM.
1000 @item
1001 TCP/IP port configuration is another example of something which
1002 is environment-specific, and should only appear in
1003 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1004 @end itemize
1006 @section Project-Specific Utilities
1008 A few project-specific utility
1009 routines may well speed up your work.
1010 Write them, and keep them in your project's user config file.
1012 For example, if you are making a boot loader work on a
1013 board, it's nice to be able to debug the ``after it's
1014 loaded to RAM'' parts separately from the finicky early
1015 code which sets up the DDR RAM controller and clocks.
1016 A script like this one, or a more GDB-aware sibling,
1017 may help:
1019 @example
1020 proc ramboot @{ @} @{
1021 # Reset, running the target's "reset-init" scripts
1022 # to initialize clocks and the DDR RAM controller.
1023 # Leave the CPU halted.
1024 reset init
1026 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1027 load_image u-boot.bin 0x20000000
1029 # Start running.
1030 resume 0x20000000
1031 @}
1032 @end example
1034 Then once that code is working you will need to make it
1035 boot from NOR flash; a different utility would help.
1036 Alternatively, some developers write to flash using GDB.
1037 (You might use a similar script if you're working with a flash
1038 based microcontroller application instead of a boot loader.)
1040 @example
1041 proc newboot @{ @} @{
1042 # Reset, leaving the CPU halted. The "reset-init" event
1043 # proc gives faster access to the CPU and to NOR flash;
1044 # "reset halt" would be slower.
1045 reset init
1047 # Write standard version of U-Boot into the first two
1048 # sectors of NOR flash ... the standard version should
1049 # do the same lowlevel init as "reset-init".
1050 flash protect 0 0 1 off
1051 flash erase_sector 0 0 1
1052 flash write_bank 0 u-boot.bin 0x0
1053 flash protect 0 0 1 on
1055 # Reboot from scratch using that new boot loader.
1056 reset run
1057 @}
1058 @end example
1060 You may need more complicated utility procedures when booting
1061 from NAND.
1062 That often involves an extra bootloader stage,
1063 running from on-chip SRAM to perform DDR RAM setup so it can load
1064 the main bootloader code (which won't fit into that SRAM).
1066 Other helper scripts might be used to write production system images,
1067 involving considerably more than just a three stage bootloader.
1069 @section Target Software Changes
1071 Sometimes you may want to make some small changes to the software
1072 you're developing, to help make JTAG debugging work better.
1073 For example, in C or assembly language code you might
1074 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1075 handling issues like:
1077 @itemize @bullet
1079 @item @b{Watchdog Timers}...
1080 Watchog timers are typically used to automatically reset systems if
1081 some application task doesn't periodically reset the timer. (The
1082 assumption is that the system has locked up if the task can't run.)
1083 When a JTAG debugger halts the system, that task won't be able to run
1084 and reset the timer ... potentially causing resets in the middle of
1085 your debug sessions.
1087 It's rarely a good idea to disable such watchdogs, since their usage
1088 needs to be debugged just like all other parts of your firmware.
1089 That might however be your only option.
1091 Look instead for chip-specific ways to stop the watchdog from counting
1092 while the system is in a debug halt state. It may be simplest to set
1093 that non-counting mode in your debugger startup scripts. You may however
1094 need a different approach when, for example, a motor could be physically
1095 damaged by firmware remaining inactive in a debug halt state. That might
1096 involve a type of firmware mode where that "non-counting" mode is disabled
1097 at the beginning then re-enabled at the end; a watchdog reset might fire
1098 and complicate the debug session, but hardware (or people) would be
1099 protected.@footnote{Note that many systems support a "monitor mode" debug
1100 that is a somewhat cleaner way to address such issues. You can think of
1101 it as only halting part of the system, maybe just one task,
1102 instead of the whole thing.
1103 At this writing, January 2010, OpenOCD based debugging does not support
1104 monitor mode debug, only "halt mode" debug.}
1106 @item @b{ARM Semihosting}...
1107 @cindex ARM semihosting
1108 When linked with a special runtime library provided with many
1109 toolchains@footnote{See chapter 8 "Semihosting" in
1110 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1111 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1112 The CodeSourcery EABI toolchain also includes a semihosting library.},
1113 your target code can use I/O facilities on the debug host. That library
1114 provides a small set of system calls which are handled by OpenOCD.
1115 It can let the debugger provide your system console and a file system,
1116 helping with early debugging or providing a more capable environment
1117 for sometimes-complex tasks like installing system firmware onto
1118 NAND or SPI flash.
1120 @item @b{ARM Wait-For-Interrupt}...
1121 Many ARM chips synchronize the JTAG clock using the core clock.
1122 Low power states which stop that core clock thus prevent JTAG access.
1123 Idle loops in tasking environments often enter those low power states
1124 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1126 You may want to @emph{disable that instruction} in source code,
1127 or otherwise prevent using that state,
1128 to ensure you can get JTAG access at any time.@footnote{As a more
1129 polite alternative, some processors have special debug-oriented
1130 registers which can be used to change various features including
1131 how the low power states are clocked while debugging.
1132 The STM32 DBGMCU_CR register is an example; at the cost of extra
1133 power consumption, JTAG can be used during low power states.}
1134 For example, the OpenOCD @command{halt} command may not
1135 work for an idle processor otherwise.
1137 @item @b{Delay after reset}...
1138 Not all chips have good support for debugger access
1139 right after reset; many LPC2xxx chips have issues here.
1140 Similarly, applications that reconfigure pins used for
1141 JTAG access as they start will also block debugger access.
1143 To work with boards like this, @emph{enable a short delay loop}
1144 the first thing after reset, before "real" startup activities.
1145 For example, one second's delay is usually more than enough
1146 time for a JTAG debugger to attach, so that
1147 early code execution can be debugged
1148 or firmware can be replaced.
1150 @item @b{Debug Communications Channel (DCC)}...
1151 Some processors include mechanisms to send messages over JTAG.
1152 Many ARM cores support these, as do some cores from other vendors.
1153 (OpenOCD may be able to use this DCC internally, speeding up some
1154 operations like writing to memory.)
1156 Your application may want to deliver various debugging messages
1157 over JTAG, by @emph{linking with a small library of code}
1158 provided with OpenOCD and using the utilities there to send
1159 various kinds of message.
1160 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1162 @end itemize
1164 @section Target Hardware Setup
1166 Chip vendors often provide software development boards which
1167 are highly configurable, so that they can support all options
1168 that product boards may require. @emph{Make sure that any
1169 jumpers or switches match the system configuration you are
1170 working with.}
1172 Common issues include:
1174 @itemize @bullet
1176 @item @b{JTAG setup} ...
1177 Boards may support more than one JTAG configuration.
1178 Examples include jumpers controlling pullups versus pulldowns
1179 on the nTRST and/or nSRST signals, and choice of connectors
1180 (e.g. which of two headers on the base board,
1181 or one from a daughtercard).
1182 For some Texas Instruments boards, you may need to jumper the
1183 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1185 @item @b{Boot Modes} ...
1186 Complex chips often support multiple boot modes, controlled
1187 by external jumpers. Make sure this is set up correctly.
1188 For example many i.MX boards from NXP need to be jumpered
1189 to "ATX mode" to start booting using the on-chip ROM, when
1190 using second stage bootloader code stored in a NAND flash chip.
1192 Such explicit configuration is common, and not limited to
1193 booting from NAND. You might also need to set jumpers to
1194 start booting using code loaded from an MMC/SD card; external
1195 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1196 flash; some external host; or various other sources.
1199 @item @b{Memory Addressing} ...
1200 Boards which support multiple boot modes may also have jumpers
1201 to configure memory addressing. One board, for example, jumpers
1202 external chipselect 0 (used for booting) to address either
1203 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1204 or NAND flash. When it's jumpered to address NAND flash, that
1205 board must also be told to start booting from on-chip ROM.
1207 Your @file{board.cfg} file may also need to be told this jumper
1208 configuration, so that it can know whether to declare NOR flash
1209 using @command{flash bank} or instead declare NAND flash with
1210 @command{nand device}; and likewise which probe to perform in
1211 its @code{reset-init} handler.
1213 A closely related issue is bus width. Jumpers might need to
1214 distinguish between 8 bit or 16 bit bus access for the flash
1215 used to start booting.
1217 @item @b{Peripheral Access} ...
1218 Development boards generally provide access to every peripheral
1219 on the chip, sometimes in multiple modes (such as by providing
1220 multiple audio codec chips).
1221 This interacts with software
1222 configuration of pin multiplexing, where for example a
1223 given pin may be routed either to the MMC/SD controller
1224 or the GPIO controller. It also often interacts with
1225 configuration jumpers. One jumper may be used to route
1226 signals to an MMC/SD card slot or an expansion bus (which
1227 might in turn affect booting); others might control which
1228 audio or video codecs are used.
1230 @end itemize
1232 Plus you should of course have @code{reset-init} event handlers
1233 which set up the hardware to match that jumper configuration.
1234 That includes in particular any oscillator or PLL used to clock
1235 the CPU, and any memory controllers needed to access external
1236 memory and peripherals. Without such handlers, you won't be
1237 able to access those resources without working target firmware
1238 which can do that setup ... this can be awkward when you're
1239 trying to debug that target firmware. Even if there's a ROM
1240 bootloader which handles a few issues, it rarely provides full
1241 access to all board-specific capabilities.
1244 @node Config File Guidelines
1245 @chapter Config File Guidelines
1247 This chapter is aimed at any user who needs to write a config file,
1248 including developers and integrators of OpenOCD and any user who
1249 needs to get a new board working smoothly.
1250 It provides guidelines for creating those files.
1252 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1253 with files including the ones listed here.
1254 Use them as-is where you can; or as models for new files.
1255 @itemize @bullet
1256 @item @file{interface} ...
1257 These are for debug adapters.
1258 Files that configure JTAG adapters go here.
1259 @example
1260 $ ls interface
1261 altera-usb-blaster.cfg hilscher_nxhx50_etm.cfg openrd.cfg
1262 arm-jtag-ew.cfg hilscher_nxhx50_re.cfg osbdm.cfg
1263 arm-usb-ocd.cfg hitex_str9-comstick.cfg parport.cfg
1264 at91rm9200.cfg icebear.cfg parport_dlc5.cfg
1265 axm0432.cfg jlink.cfg redbee-econotag.cfg
1266 busblaster.cfg jtagkey2.cfg redbee-usb.cfg
1267 buspirate.cfg jtagkey2p.cfg rlink.cfg
1268 calao-usb-a9260-c01.cfg jtagkey.cfg sheevaplug.cfg
1269 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg signalyzer.cfg
1270 calao-usb-a9260.cfg kt-link.cfg signalyzer-h2.cfg
1271 chameleon.cfg lisa-l.cfg signalyzer-h4.cfg
1272 cortino.cfg luminary.cfg signalyzer-lite.cfg
1273 digilent-hs1.cfg luminary-icdi.cfg stlink-v1.cfg
1274 dlp-usb1232h.cfg luminary-lm3s811.cfg stlink-v2.cfg
1275 dummy.cfg minimodule.cfg stm32-stick.cfg
1276 estick.cfg neodb.cfg turtelizer2.cfg
1277 flashlink.cfg ngxtech.cfg ulink.cfg
1278 flossjtag.cfg olimex-arm-usb-ocd.cfg usb-jtag.cfg
1279 flossjtag-noeeprom.cfg olimex-arm-usb-ocd-h.cfg usbprog.cfg
1280 flyswatter2.cfg olimex-arm-usb-tiny-h.cfg vpaclink.cfg
1281 flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
1282 hilscher_nxhx10_etm.cfg oocdlink.cfg xds100v2.cfg
1283 hilscher_nxhx500_etm.cfg opendous.cfg
1284 hilscher_nxhx500_re.cfg openocd-usb.cfg
1285 $
1286 @end example
1287 @item @file{board} ...
1288 think Circuit Board, PWA, PCB, they go by many names. Board files
1289 contain initialization items that are specific to a board.
1290 They reuse target configuration files, since the same
1291 microprocessor chips are used on many boards,
1292 but support for external parts varies widely. For
1293 example, the SDRAM initialization sequence for the board, or the type
1294 of external flash and what address it uses. Any initialization
1295 sequence to enable that external flash or SDRAM should be found in the
1296 board file. Boards may also contain multiple targets: two CPUs; or
1297 a CPU and an FPGA.
1298 @example
1299 $ ls board
1300 actux3.cfg logicpd_imx27.cfg
1301 am3517evm.cfg lubbock.cfg
1302 arm_evaluator7t.cfg mcb1700.cfg
1303 at91cap7a-stk-sdram.cfg microchip_explorer16.cfg
1304 at91eb40a.cfg mini2440.cfg
1305 at91rm9200-dk.cfg mini6410.cfg
1306 at91rm9200-ek.cfg olimex_LPC2378STK.cfg
1307 at91sam9261-ek.cfg olimex_lpc_h2148.cfg
1308 at91sam9263-ek.cfg olimex_sam7_ex256.cfg
1309 at91sam9g20-ek.cfg olimex_sam9_l9260.cfg
1310 atmel_at91sam7s-ek.cfg olimex_stm32_h103.cfg
1311 atmel_at91sam9260-ek.cfg olimex_stm32_h107.cfg
1312 atmel_at91sam9rl-ek.cfg olimex_stm32_p107.cfg
1313 atmel_sam3n_ek.cfg omap2420_h4.cfg
1314 atmel_sam3s_ek.cfg open-bldc.cfg
1315 atmel_sam3u_ek.cfg openrd.cfg
1316 atmel_sam3x_ek.cfg osk5912.cfg
1317 atmel_sam4s_ek.cfg phytec_lpc3250.cfg
1318 balloon3-cpu.cfg pic-p32mx.cfg
1319 colibri.cfg propox_mmnet1001.cfg
1320 crossbow_tech_imote2.cfg pxa255_sst.cfg
1321 csb337.cfg redbee.cfg
1322 csb732.cfg rsc-w910.cfg
1323 da850evm.cfg sheevaplug.cfg
1324 digi_connectcore_wi-9c.cfg smdk6410.cfg
1325 diolan_lpc4350-db1.cfg spear300evb.cfg
1326 dm355evm.cfg spear300evb_mod.cfg
1327 dm365evm.cfg spear310evb20.cfg
1328 dm6446evm.cfg spear310evb20_mod.cfg
1329 efikamx.cfg spear320cpu.cfg
1330 eir.cfg spear320cpu_mod.cfg
1331 ek-lm3s1968.cfg steval_pcc010.cfg
1332 ek-lm3s3748.cfg stm320518_eval_stlink.cfg
1333 ek-lm3s6965.cfg stm32100b_eval.cfg
1334 ek-lm3s811.cfg stm3210b_eval.cfg
1335 ek-lm3s811-revb.cfg stm3210c_eval.cfg
1336 ek-lm3s9b9x.cfg stm3210e_eval.cfg
1337 ek-lm4f232.cfg stm3220g_eval.cfg
1338 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1339 ethernut3.cfg stm3241g_eval.cfg
1340 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1341 hammer.cfg stm32f0discovery.cfg
1342 hilscher_nxdb500sys.cfg stm32f4discovery.cfg
1343 hilscher_nxeb500hmi.cfg stm32ldiscovery.cfg
1344 hilscher_nxhx10.cfg stm32vldiscovery.cfg
1345 hilscher_nxhx500.cfg str910-eval.cfg
1346 hilscher_nxhx50.cfg telo.cfg
1347 hilscher_nxsb100.cfg ti_beagleboard.cfg
1348 hitex_lpc2929.cfg ti_beagleboard_xm.cfg
1349 hitex_stm32-performancestick.cfg ti_beaglebone.cfg
1350 hitex_str9-comstick.cfg ti_blaze.cfg
1351 iar_lpc1768.cfg ti_pandaboard.cfg
1352 iar_str912_sk.cfg ti_pandaboard_es.cfg
1353 icnova_imx53_sodimm.cfg topas910.cfg
1354 icnova_sam9g45_sodimm.cfg topasa900.cfg
1355 imx27ads.cfg twr-k60n512.cfg
1356 imx27lnst.cfg tx25_stk5.cfg
1357 imx28evk.cfg tx27_stk5.cfg
1358 imx31pdk.cfg unknown_at91sam9260.cfg
1359 imx35pdk.cfg uptech_2410.cfg
1360 imx53loco.cfg verdex.cfg
1361 keil_mcb1700.cfg voipac.cfg
1362 keil_mcb2140.cfg voltcraft_dso-3062c.cfg
1363 kwikstik.cfg x300t.cfg
1364 linksys_nslu2.cfg zy1000.cfg
1365 lisa-l.cfg
1366 $
1367 @end example
1368 @item @file{target} ...
1369 think chip. The ``target'' directory represents the JTAG TAPs
1370 on a chip
1371 which OpenOCD should control, not a board. Two common types of targets
1372 are ARM chips and FPGA or CPLD chips.
1373 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1374 the target config file defines all of them.
1375 @example
1376 $ ls target
1377 $duc702x.cfg ixp42x.cfg
1378 am335x.cfg k40.cfg
1379 amdm37x.cfg k60.cfg
1380 ar71xx.cfg lpc1768.cfg
1381 at32ap7000.cfg lpc2103.cfg
1382 at91r40008.cfg lpc2124.cfg
1383 at91rm9200.cfg lpc2129.cfg
1384 at91sam3ax_4x.cfg lpc2148.cfg
1385 at91sam3ax_8x.cfg lpc2294.cfg
1386 at91sam3ax_xx.cfg lpc2378.cfg
1387 at91sam3nXX.cfg lpc2460.cfg
1388 at91sam3sXX.cfg lpc2478.cfg
1389 at91sam3u1c.cfg lpc2900.cfg
1390 at91sam3u1e.cfg lpc2xxx.cfg
1391 at91sam3u2c.cfg lpc3131.cfg
1392 at91sam3u2e.cfg lpc3250.cfg
1393 at91sam3u4c.cfg lpc4350.cfg
1394 at91sam3u4e.cfg mc13224v.cfg
1395 at91sam3uxx.cfg nuc910.cfg
1396 at91sam3XXX.cfg omap2420.cfg
1397 at91sam4sXX.cfg omap3530.cfg
1398 at91sam4XXX.cfg omap4430.cfg
1399 at91sam7se512.cfg omap4460.cfg
1400 at91sam7sx.cfg omap5912.cfg
1401 at91sam7x256.cfg omapl138.cfg
1402 at91sam7x512.cfg pic32mx.cfg
1403 at91sam9260.cfg pxa255.cfg
1404 at91sam9260_ext_RAM_ext_flash.cfg pxa270.cfg
1405 at91sam9261.cfg pxa3xx.cfg
1406 at91sam9263.cfg readme.txt
1407 at91sam9.cfg samsung_s3c2410.cfg
1408 at91sam9g10.cfg samsung_s3c2440.cfg
1409 at91sam9g20.cfg samsung_s3c2450.cfg
1410 at91sam9g45.cfg samsung_s3c4510.cfg
1411 at91sam9rl.cfg samsung_s3c6410.cfg
1412 atmega128.cfg sharp_lh79532.cfg
1413 avr32.cfg smp8634.cfg
1414 c100.cfg spear3xx.cfg
1415 c100config.tcl stellaris.cfg
1416 c100helper.tcl stm32.cfg
1417 c100regs.tcl stm32f0x_stlink.cfg
1418 cs351x.cfg stm32f1x.cfg
1419 davinci.cfg stm32f1x_stlink.cfg
1420 dragonite.cfg stm32f2x.cfg
1421 dsp56321.cfg stm32f2x_stlink.cfg
1422 dsp568013.cfg stm32f2xxx.cfg
1423 dsp568037.cfg stm32f4x.cfg
1424 epc9301.cfg stm32f4x_stlink.cfg
1425 faux.cfg stm32l.cfg
1426 feroceon.cfg stm32lx_stlink.cfg
1427 fm3.cfg stm32_stlink.cfg
1428 hilscher_netx10.cfg stm32xl.cfg
1429 hilscher_netx500.cfg str710.cfg
1430 hilscher_netx50.cfg str730.cfg
1431 icepick.cfg str750.cfg
1432 imx21.cfg str912.cfg
1433 imx25.cfg swj-dp.tcl
1434 imx27.cfg test_reset_syntax_error.cfg
1435 imx28.cfg test_syntax_error.cfg
1436 imx31.cfg ti_dm355.cfg
1437 imx35.cfg ti_dm365.cfg
1438 imx51.cfg ti_dm6446.cfg
1439 imx53.cfg tmpa900.cfg
1440 imx.cfg tmpa910.cfg
1441 is5114.cfg u8500.cfg
1442 @end example
1443 @item @emph{more} ... browse for other library files which may be useful.
1444 For example, there are various generic and CPU-specific utilities.
1445 @end itemize
1447 The @file{openocd.cfg} user config
1448 file may override features in any of the above files by
1449 setting variables before sourcing the target file, or by adding
1450 commands specific to their situation.
1452 @section Interface Config Files
1454 The user config file
1455 should be able to source one of these files with a command like this:
1457 @example
1458 source [find interface/FOOBAR.cfg]
1459 @end example
1461 A preconfigured interface file should exist for every debug adapter
1462 in use today with OpenOCD.
1463 That said, perhaps some of these config files
1464 have only been used by the developer who created it.
1466 A separate chapter gives information about how to set these up.
1467 @xref{Debug Adapter Configuration}.
1468 Read the OpenOCD source code (and Developer's Guide)
1469 if you have a new kind of hardware interface
1470 and need to provide a driver for it.
1472 @section Board Config Files
1473 @cindex config file, board
1474 @cindex board config file
1476 The user config file
1477 should be able to source one of these files with a command like this:
1479 @example
1480 source [find board/FOOBAR.cfg]
1481 @end example
1483 The point of a board config file is to package everything
1484 about a given board that user config files need to know.
1485 In summary the board files should contain (if present)
1487 @enumerate
1488 @item One or more @command{source [target/...cfg]} statements
1489 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1490 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1491 @item Target @code{reset} handlers for SDRAM and I/O configuration
1492 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1493 @item All things that are not ``inside a chip''
1494 @end enumerate
1496 Generic things inside target chips belong in target config files,
1497 not board config files. So for example a @code{reset-init} event
1498 handler should know board-specific oscillator and PLL parameters,
1499 which it passes to target-specific utility code.
1501 The most complex task of a board config file is creating such a
1502 @code{reset-init} event handler.
1503 Define those handlers last, after you verify the rest of the board
1504 configuration works.
1506 @subsection Communication Between Config files
1508 In addition to target-specific utility code, another way that
1509 board and target config files communicate is by following a
1510 convention on how to use certain variables.
1512 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1513 Thus the rule we follow in OpenOCD is this: Variables that begin with
1514 a leading underscore are temporary in nature, and can be modified and
1515 used at will within a target configuration file.
1517 Complex board config files can do the things like this,
1518 for a board with three chips:
1520 @example
1521 # Chip #1: PXA270 for network side, big endian
1522 set CHIPNAME network
1523 set ENDIAN big
1524 source [find target/pxa270.cfg]
1525 # on return: _TARGETNAME = network.cpu
1526 # other commands can refer to the "network.cpu" target.
1527 $_TARGETNAME configure .... events for this CPU..
1529 # Chip #2: PXA270 for video side, little endian
1530 set CHIPNAME video
1531 set ENDIAN little
1532 source [find target/pxa270.cfg]
1533 # on return: _TARGETNAME = video.cpu
1534 # other commands can refer to the "video.cpu" target.
1535 $_TARGETNAME configure .... events for this CPU..
1537 # Chip #3: Xilinx FPGA for glue logic
1538 set CHIPNAME xilinx
1539 unset ENDIAN
1540 source [find target/spartan3.cfg]
1541 @end example
1543 That example is oversimplified because it doesn't show any flash memory,
1544 or the @code{reset-init} event handlers to initialize external DRAM
1545 or (assuming it needs it) load a configuration into the FPGA.
1546 Such features are usually needed for low-level work with many boards,
1547 where ``low level'' implies that the board initialization software may
1548 not be working. (That's a common reason to need JTAG tools. Another
1549 is to enable working with microcontroller-based systems, which often
1550 have no debugging support except a JTAG connector.)
1552 Target config files may also export utility functions to board and user
1553 config files. Such functions should use name prefixes, to help avoid
1554 naming collisions.
1556 Board files could also accept input variables from user config files.
1557 For example, there might be a @code{J4_JUMPER} setting used to identify
1558 what kind of flash memory a development board is using, or how to set
1559 up other clocks and peripherals.
1561 @subsection Variable Naming Convention
1562 @cindex variable names
1564 Most boards have only one instance of a chip.
1565 However, it should be easy to create a board with more than
1566 one such chip (as shown above).
1567 Accordingly, we encourage these conventions for naming
1568 variables associated with different @file{target.cfg} files,
1569 to promote consistency and
1570 so that board files can override target defaults.
1572 Inputs to target config files include:
1574 @itemize @bullet
1575 @item @code{CHIPNAME} ...
1576 This gives a name to the overall chip, and is used as part of
1577 tap identifier dotted names.
1578 While the default is normally provided by the chip manufacturer,
1579 board files may need to distinguish between instances of a chip.
1580 @item @code{ENDIAN} ...
1581 By default @option{little} - although chips may hard-wire @option{big}.
1582 Chips that can't change endianness don't need to use this variable.
1583 @item @code{CPUTAPID} ...
1584 When OpenOCD examines the JTAG chain, it can be told verify the
1585 chips against the JTAG IDCODE register.
1586 The target file will hold one or more defaults, but sometimes the
1587 chip in a board will use a different ID (perhaps a newer revision).
1588 @end itemize
1590 Outputs from target config files include:
1592 @itemize @bullet
1593 @item @code{_TARGETNAME} ...
1594 By convention, this variable is created by the target configuration
1595 script. The board configuration file may make use of this variable to
1596 configure things like a ``reset init'' script, or other things
1597 specific to that board and that target.
1598 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1599 @code{_TARGETNAME1}, ... etc.
1600 @end itemize
1602 @subsection The reset-init Event Handler
1603 @cindex event, reset-init
1604 @cindex reset-init handler
1606 Board config files run in the OpenOCD configuration stage;
1607 they can't use TAPs or targets, since they haven't been
1608 fully set up yet.
1609 This means you can't write memory or access chip registers;
1610 you can't even verify that a flash chip is present.
1611 That's done later in event handlers, of which the target @code{reset-init}
1612 handler is one of the most important.
1614 Except on microcontrollers, the basic job of @code{reset-init} event
1615 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1616 Microcontrollers rarely use boot loaders; they run right out of their
1617 on-chip flash and SRAM memory. But they may want to use one of these
1618 handlers too, if just for developer convenience.
1620 @quotation Note
1621 Because this is so very board-specific, and chip-specific, no examples
1622 are included here.
1623 Instead, look at the board config files distributed with OpenOCD.
1624 If you have a boot loader, its source code will help; so will
1625 configuration files for other JTAG tools
1626 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1627 @end quotation
1629 Some of this code could probably be shared between different boards.
1630 For example, setting up a DRAM controller often doesn't differ by
1631 much except the bus width (16 bits or 32?) and memory timings, so a
1632 reusable TCL procedure loaded by the @file{target.cfg} file might take
1633 those as parameters.
1634 Similarly with oscillator, PLL, and clock setup;
1635 and disabling the watchdog.
1636 Structure the code cleanly, and provide comments to help
1637 the next developer doing such work.
1638 (@emph{You might be that next person} trying to reuse init code!)
1640 The last thing normally done in a @code{reset-init} handler is probing
1641 whatever flash memory was configured. For most chips that needs to be
1642 done while the associated target is halted, either because JTAG memory
1643 access uses the CPU or to prevent conflicting CPU access.
1645 @subsection JTAG Clock Rate
1647 Before your @code{reset-init} handler has set up
1648 the PLLs and clocking, you may need to run with
1649 a low JTAG clock rate.
1650 @xref{jtagspeed,,JTAG Speed}.
1651 Then you'd increase that rate after your handler has
1652 made it possible to use the faster JTAG clock.
1653 When the initial low speed is board-specific, for example
1654 because it depends on a board-specific oscillator speed, then
1655 you should probably set it up in the board config file;
1656 if it's target-specific, it belongs in the target config file.
1658 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1659 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1660 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1661 Consult chip documentation to determine the peak JTAG clock rate,
1662 which might be less than that.
1664 @quotation Warning
1665 On most ARMs, JTAG clock detection is coupled to the core clock, so
1666 software using a @option{wait for interrupt} operation blocks JTAG access.
1667 Adaptive clocking provides a partial workaround, but a more complete
1668 solution just avoids using that instruction with JTAG debuggers.
1669 @end quotation
1671 If both the chip and the board support adaptive clocking,
1672 use the @command{jtag_rclk}
1673 command, in case your board is used with JTAG adapter which
1674 also supports it. Otherwise use @command{adapter_khz}.
1675 Set the slow rate at the beginning of the reset sequence,
1676 and the faster rate as soon as the clocks are at full speed.
1678 @anchor{theinitboardprocedure}
1679 @subsection The init_board procedure
1680 @cindex init_board procedure
1682 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1683 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1684 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1685 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1686 spearate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1687 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1688 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1689 Additionally ``linear'' board config file will most likely fail when target config file uses
1690 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1691 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1692 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1693 need to override @code{init_targets} defined in target config files when they only need to to add some specifics.
1695 Just as @code{init_targets}, the @code{init_board} procedure can be overriden by ``next level'' script (which sources
1696 the original), allowing greater code reuse.
1698 @example
1699 ### board_file.cfg ###
1701 # source target file that does most of the config in init_targets
1702 source [find target/target.cfg]
1704 proc enable_fast_clock @{@} @{
1705 # enables fast on-board clock source
1706 # configures the chip to use it
1707 @}
1709 # initialize only board specifics - reset, clock, adapter frequency
1710 proc init_board @{@} @{
1711 reset_config trst_and_srst trst_pulls_srst
1713 $_TARGETNAME configure -event reset-init @{
1714 adapter_khz 1
1715 enable_fast_clock
1716 adapter_khz 10000
1717 @}
1718 @}
1719 @end example
1721 @section Target Config Files
1722 @cindex config file, target
1723 @cindex target config file
1725 Board config files communicate with target config files using
1726 naming conventions as described above, and may source one or
1727 more target config files like this:
1729 @example
1730 source [find target/FOOBAR.cfg]
1731 @end example
1733 The point of a target config file is to package everything
1734 about a given chip that board config files need to know.
1735 In summary the target files should contain
1737 @enumerate
1738 @item Set defaults
1739 @item Add TAPs to the scan chain
1740 @item Add CPU targets (includes GDB support)
1741 @item CPU/Chip/CPU-Core specific features
1742 @item On-Chip flash
1743 @end enumerate
1745 As a rule of thumb, a target file sets up only one chip.
1746 For a microcontroller, that will often include a single TAP,
1747 which is a CPU needing a GDB target, and its on-chip flash.
1749 More complex chips may include multiple TAPs, and the target
1750 config file may need to define them all before OpenOCD
1751 can talk to the chip.
1752 For example, some phone chips have JTAG scan chains that include
1753 an ARM core for operating system use, a DSP,
1754 another ARM core embedded in an image processing engine,
1755 and other processing engines.
1757 @subsection Default Value Boiler Plate Code
1759 All target configuration files should start with code like this,
1760 letting board config files express environment-specific
1761 differences in how things should be set up.
1763 @example
1764 # Boards may override chip names, perhaps based on role,
1765 # but the default should match what the vendor uses
1766 if @{ [info exists CHIPNAME] @} @{
1768 @} else @{
1769 set _CHIPNAME sam7x256
1770 @}
1772 # ONLY use ENDIAN with targets that can change it.
1773 if @{ [info exists ENDIAN] @} @{
1774 set _ENDIAN $ENDIAN
1775 @} else @{
1776 set _ENDIAN little
1777 @}
1779 # TAP identifiers may change as chips mature, for example with
1780 # new revision fields (the "3" here). Pick a good default; you
1781 # can pass several such identifiers to the "jtag newtap" command.
1782 if @{ [info exists CPUTAPID ] @} @{
1784 @} else @{
1785 set _CPUTAPID 0x3f0f0f0f
1786 @}
1787 @end example
1788 @c but 0x3f0f0f0f is for an str73x part ...
1790 @emph{Remember:} Board config files may include multiple target
1791 config files, or the same target file multiple times
1792 (changing at least @code{CHIPNAME}).
1794 Likewise, the target configuration file should define
1795 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1796 use it later on when defining debug targets:
1798 @example
1800 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1801 @end example
1803 @subsection Adding TAPs to the Scan Chain
1804 After the ``defaults'' are set up,
1805 add the TAPs on each chip to the JTAG scan chain.
1806 @xref{TAP Declaration}, and the naming convention
1807 for taps.
1809 In the simplest case the chip has only one TAP,
1810 probably for a CPU or FPGA.
1811 The config file for the Atmel AT91SAM7X256
1812 looks (in part) like this:
1814 @example
1815 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1816 @end example
1818 A board with two such at91sam7 chips would be able
1819 to source such a config file twice, with different
1820 values for @code{CHIPNAME}, so
1821 it adds a different TAP each time.
1823 If there are nonzero @option{-expected-id} values,
1824 OpenOCD attempts to verify the actual tap id against those values.
1825 It will issue error messages if there is mismatch, which
1826 can help to pinpoint problems in OpenOCD configurations.
1828 @example
1829 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1830 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1831 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1832 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1833 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1834 @end example
1836 There are more complex examples too, with chips that have
1837 multiple TAPs. Ones worth looking at include:
1839 @itemize
1840 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1841 plus a JRC to enable them
1842 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1843 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1844 is not currently used)
1845 @end itemize
1847 @subsection Add CPU targets
1849 After adding a TAP for a CPU, you should set it up so that
1850 GDB and other commands can use it.
1851 @xref{CPU Configuration}.
1852 For the at91sam7 example above, the command can look like this;
1853 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1854 to little endian, and this chip doesn't support changing that.
1856 @example
1858 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1859 @end example
1861 Work areas are small RAM areas associated with CPU targets.
1862 They are used by OpenOCD to speed up downloads,
1863 and to download small snippets of code to program flash chips.
1864 If the chip includes a form of ``on-chip-ram'' - and many do - define
1865 a work area if you can.
1866 Again using the at91sam7 as an example, this can look like:
1868 @example
1869 $_TARGETNAME configure -work-area-phys 0x00200000 \
1870 -work-area-size 0x4000 -work-area-backup 0
1871 @end example
1873 @anchor{definecputargetsworkinginsmp}
1874 @subsection Define CPU targets working in SMP
1875 @cindex SMP
1876 After setting targets, you can define a list of targets working in SMP.
1878 @example
1879 set _TARGETNAME_1 $_CHIPNAME.cpu1
1880 set _TARGETNAME_2 $_CHIPNAME.cpu2
1881 target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap \
1882 -coreid 0 -dbgbase $_DAP_DBG1
1883 target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap \
1884 -coreid 1 -dbgbase $_DAP_DBG2
1885 #define 2 targets working in smp.
1886 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1887 @end example
1888 In the above example on cortex_a8, 2 cpus are working in SMP.
1889 In SMP only one GDB instance is created and :
1890 @itemize @bullet
1891 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1892 @item halt command triggers the halt of all targets in the list.
1893 @item resume command triggers the write context and the restart of all targets in the list.
1894 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1895 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1896 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1897 @end itemize
1899 The SMP behaviour can be disabled/enabled dynamically. On cortex_a8 following
1900 command have been implemented.
1901 @itemize @bullet
1902 @item cortex_a8 smp_on : enable SMP mode, behaviour is as described above.
1903 @item cortex_a8 smp_off : disable SMP mode, the current target is the one
1904 displayed in the GDB session, only this target is now controlled by GDB
1905 session. This behaviour is useful during system boot up.
1906 @item cortex_a8 smp_gdb : display/fix the core id displayed in GDB session see
1907 following example.
1908 @end itemize
1910 @example
1911 >cortex_a8 smp_gdb
1912 gdb coreid 0 -> -1
1913 #0 : coreid 0 is displayed to GDB ,
1914 #-> -1 : next resume triggers a real resume
1915 > cortex_a8 smp_gdb 1
1916 gdb coreid 0 -> 1
1917 #0 :coreid 0 is displayed to GDB ,
1918 #->1 : next resume displays coreid 1 to GDB
1919 > resume
1920 > cortex_a8 smp_gdb
1921 gdb coreid 1 -> 1
1922 #1 :coreid 1 is displayed to GDB ,
1923 #->1 : next resume displays coreid 1 to GDB
1924 > cortex_a8 smp_gdb -1
1925 gdb coreid 1 -> -1
1926 #1 :coreid 1 is displayed to GDB,
1927 #->-1 : next resume triggers a real resume
1928 @end example
1931 @subsection Chip Reset Setup
1933 As a rule, you should put the @command{reset_config} command
1934 into the board file. Most things you think you know about a
1935 chip can be tweaked by the board.
1937 Some chips have specific ways the TRST and SRST signals are
1938 managed. In the unusual case that these are @emph{chip specific}
1939 and can never be changed by board wiring, they could go here.
1940 For example, some chips can't support JTAG debugging without
1941 both signals.
1943 Provide a @code{reset-assert} event handler if you can.
1944 Such a handler uses JTAG operations to reset the target,
1945 letting this target config be used in systems which don't
1946 provide the optional SRST signal, or on systems where you
1947 don't want to reset all targets at once.
1948 Such a handler might write to chip registers to force a reset,
1949 use a JRC to do that (preferable -- the target may be wedged!),
1950 or force a watchdog timer to trigger.
1951 (For Cortex-M3 targets, this is not necessary. The target
1952 driver knows how to use trigger an NVIC reset when SRST is
1953 not available.)
1955 Some chips need special attention during reset handling if
1956 they're going to be used with JTAG.
1957 An example might be needing to send some commands right
1958 after the target's TAP has been reset, providing a
1959 @code{reset-deassert-post} event handler that writes a chip
1960 register to report that JTAG debugging is being done.
1961 Another would be reconfiguring the watchdog so that it stops
1962 counting while the core is halted in the debugger.
1964 JTAG clocking constraints often change during reset, and in
1965 some cases target config files (rather than board config files)
1966 are the right places to handle some of those issues.
1967 For example, immediately after reset most chips run using a
1968 slower clock than they will use later.
1969 That means that after reset (and potentially, as OpenOCD
1970 first starts up) they must use a slower JTAG clock rate
1971 than they will use later.
1972 @xref{jtagspeed,,JTAG Speed}.
1974 @quotation Important
1975 When you are debugging code that runs right after chip
1976 reset, getting these issues right is critical.
1977 In particular, if you see intermittent failures when
1978 OpenOCD verifies the scan chain after reset,
1979 look at how you are setting up JTAG clocking.
1980 @end quotation
1982 @anchor{theinittargetsprocedure}
1983 @subsection The init_targets procedure
1984 @cindex init_targets procedure
1986 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1987 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1988 procedure called @code{init_targets}, which will be executed when entering run stage
1989 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1990 Such procedure can be overriden by ``next level'' script (which sources the original).
1991 This concept faciliates code reuse when basic target config files provide generic configuration
1992 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
1993 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1994 because sourcing them executes every initialization commands they provide.
1996 @example
1997 ### generic_file.cfg ###
1999 proc setup_my_chip @{chip_name flash_size ram_size@} @{
2000 # basic initialization procedure ...
2001 @}
2003 proc init_targets @{@} @{
2004 # initializes generic chip with 4kB of flash and 1kB of RAM
2005 setup_my_chip MY_GENERIC_CHIP 4096 1024
2006 @}
2008 ### specific_file.cfg ###
2010 source [find target/generic_file.cfg]
2012 proc init_targets @{@} @{
2013 # initializes specific chip with 128kB of flash and 64kB of RAM
2014 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
2015 @}
2016 @end example
2018 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
2019 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
2021 For an example of this scheme see LPC2000 target config files.
2023 The @code{init_boards} procedure is a similar concept concerning board config files
2024 (@xref{theinitboardprocedure,,The init_board procedure}.)
2026 @subsection ARM Core Specific Hacks
2028 If the chip has a DCC, enable it. If the chip is an ARM9 with some
2029 special high speed download features - enable it.
2031 If present, the MMU, the MPU and the CACHE should be disabled.
2033 Some ARM cores are equipped with trace support, which permits
2034 examination of the instruction and data bus activity. Trace
2035 activity is controlled through an ``Embedded Trace Module'' (ETM)
2036 on one of the core's scan chains. The ETM emits voluminous data
2037 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
2038 If you are using an external trace port,
2039 configure it in your board config file.
2040 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2041 configure it in your target config file.
2043 @example
2044 etm config $_TARGETNAME 16 normal full etb
2045 etb config $_TARGETNAME $_CHIPNAME.etb
2046 @end example
2048 @subsection Internal Flash Configuration
2050 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2052 @b{Never ever} in the ``target configuration file'' define any type of
2053 flash that is external to the chip. (For example a BOOT flash on
2054 Chip Select 0.) Such flash information goes in a board file - not
2055 the TARGET (chip) file.
2057 Examples:
2058 @itemize @bullet
2059 @item at91sam7x256 - has 256K flash YES enable it.
2060 @item str912 - has flash internal YES enable it.
2061 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2062 @item pxa270 - again - CS0 flash - it goes in the board file.
2063 @end itemize
2065 @anchor{translatingconfigurationfiles}
2066 @section Translating Configuration Files
2067 @cindex translation
2068 If you have a configuration file for another hardware debugger
2069 or toolset (Abatron, BDI2000, BDI3000, CCS,
2070 Lauterbach, Segger, Macraigor, etc.), translating
2071 it into OpenOCD syntax is often quite straightforward. The most tricky
2072 part of creating a configuration script is oftentimes the reset init
2073 sequence where e.g. PLLs, DRAM and the like is set up.
2075 One trick that you can use when translating is to write small
2076 Tcl procedures to translate the syntax into OpenOCD syntax. This
2077 can avoid manual translation errors and make it easier to
2078 convert other scripts later on.
2080 Example of transforming quirky arguments to a simple search and
2081 replace job:
2083 @example
2084 # Lauterbach syntax(?)
2085 #
2086 # Data.Set c15:0x042f %long 0x40000015
2087 #
2088 # OpenOCD syntax when using procedure below.
2089 #
2090 # setc15 0x01 0x00050078
2092 proc setc15 @{regs value@} @{
2093 global TARGETNAME
2095 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2097 arm mcr 15 [expr ($regs>>12)&0x7] \
2098 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2099 [expr ($regs>>8)&0x7] $value
2100 @}
2101 @end example
2105 @node Daemon Configuration
2106 @chapter Daemon Configuration
2107 @cindex initialization
2108 The commands here are commonly found in the openocd.cfg file and are
2109 used to specify what TCP/IP ports are used, and how GDB should be
2110 supported.
2112 @anchor{configurationstage}
2113 @section Configuration Stage
2114 @cindex configuration stage
2115 @cindex config command
2117 When the OpenOCD server process starts up, it enters a
2118 @emph{configuration stage} which is the only time that
2119 certain commands, @emph{configuration commands}, may be issued.
2120 Normally, configuration commands are only available
2121 inside startup scripts.
2123 In this manual, the definition of a configuration command is
2124 presented as a @emph{Config Command}, not as a @emph{Command}
2125 which may be issued interactively.
2126 The runtime @command{help} command also highlights configuration
2127 commands, and those which may be issued at any time.
2129 Those configuration commands include declaration of TAPs,
2130 flash banks,
2131 the interface used for JTAG communication,
2132 and other basic setup.
2133 The server must leave the configuration stage before it
2134 may access or activate TAPs.
2135 After it leaves this stage, configuration commands may no
2136 longer be issued.
2138 @anchor{enteringtherunstage}
2139 @section Entering the Run Stage
2141 The first thing OpenOCD does after leaving the configuration
2142 stage is to verify that it can talk to the scan chain
2143 (list of TAPs) which has been configured.
2144 It will warn if it doesn't find TAPs it expects to find,
2145 or finds TAPs that aren't supposed to be there.
2146 You should see no errors at this point.
2147 If you see errors, resolve them by correcting the
2148 commands you used to configure the server.
2149 Common errors include using an initial JTAG speed that's too
2150 fast, and not providing the right IDCODE values for the TAPs
2151 on the scan chain.
2153 Once OpenOCD has entered the run stage, a number of commands
2154 become available.
2155 A number of these relate to the debug targets you may have declared.
2156 For example, the @command{mww} command will not be available until
2157 a target has been successfuly instantiated.
2158 If you want to use those commands, you may need to force
2159 entry to the run stage.
2161 @deffn {Config Command} init
2162 This command terminates the configuration stage and
2163 enters the run stage. This helps when you need to have
2164 the startup scripts manage tasks such as resetting the target,
2165 programming flash, etc. To reset the CPU upon startup, add "init" and
2166 "reset" at the end of the config script or at the end of the OpenOCD
2167 command line using the @option{-c} command line switch.
2169 If this command does not appear in any startup/configuration file
2170 OpenOCD executes the command for you after processing all
2171 configuration files and/or command line options.
2173 @b{NOTE:} This command normally occurs at or near the end of your
2174 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2175 targets ready. For example: If your openocd.cfg file needs to
2176 read/write memory on your target, @command{init} must occur before
2177 the memory read/write commands. This includes @command{nand probe}.
2178 @end deffn
2180 @deffn {Overridable Procedure} jtag_init
2181 This is invoked at server startup to verify that it can talk
2182 to the scan chain (list of TAPs) which has been configured.
2184 The default implementation first tries @command{jtag arp_init},
2185 which uses only a lightweight JTAG reset before examining the
2186 scan chain.
2187 If that fails, it tries again, using a harder reset
2188 from the overridable procedure @command{init_reset}.
2190 Implementations must have verified the JTAG scan chain before
2191 they return.
2192 This is done by calling @command{jtag arp_init}
2193 (or @command{jtag arp_init-reset}).
2194 @end deffn
2196 @anchor{tcpipports}
2197 @section TCP/IP Ports
2198 @cindex TCP port
2199 @cindex server
2200 @cindex port
2201 @cindex security
2202 The OpenOCD server accepts remote commands in several syntaxes.
2203 Each syntax uses a different TCP/IP port, which you may specify
2204 only during configuration (before those ports are opened).
2206 For reasons including security, you may wish to prevent remote
2207 access using one or more of these ports.
2208 In such cases, just specify the relevant port number as zero.
2209 If you disable all access through TCP/IP, you will need to
2210 use the command line @option{-pipe} option.
2212 @deffn {Command} gdb_port [number]
2213 @cindex GDB server
2214 Normally gdb listens to a TCP/IP port, but GDB can also
2215 communicate via pipes(stdin/out or named pipes). The name
2216 "gdb_port" stuck because it covers probably more than 90% of
2217 the normal use cases.
2219 No arguments reports GDB port. "pipe" means listen to stdin
2220 output to stdout, an integer is base port number, "disable"
2221 disables the gdb server.
2223 When using "pipe", also use log_output to redirect the log
2224 output to a file so as not to flood the stdin/out pipes.
2226 The -p/--pipe option is deprecated and a warning is printed
2227 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2229 Any other string is interpreted as named pipe to listen to.
2230 Output pipe is the same name as input pipe, but with 'o' appended,
2231 e.g. /var/gdb, /var/gdbo.
2233 The GDB port for the first target will be the base port, the
2234 second target will listen on gdb_port + 1, and so on.
2235 When not specified during the configuration stage,
2236 the port @var{number} defaults to 3333.
2237 @end deffn
2239 @deffn {Command} tcl_port [number]
2240 Specify or query the port used for a simplified RPC
2241 connection that can be used by clients to issue TCL commands and get the
2242 output from the Tcl engine.
2243 Intended as a machine interface.
2244 When not specified during the configuration stage,
2245 the port @var{number} defaults to 6666.
2247 @end deffn
2249 @deffn {Command} telnet_port [number]
2250 Specify or query the
2251 port on which to listen for incoming telnet connections.
2252 This port is intended for interaction with one human through TCL commands.
2253 When not specified during the configuration stage,
2254 the port @var{number} defaults to 4444.
2255 When specified as zero, this port is not activated.
2256 @end deffn
2258 @anchor{gdbconfiguration}
2259 @section GDB Configuration
2260 @cindex GDB
2261 @cindex GDB configuration
2262 You can reconfigure some GDB behaviors if needed.
2263 The ones listed here are static and global.
2264 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2265 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2267 @anchor{gdbbreakpointoverride}
2268 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2269 Force breakpoint type for gdb @command{break} commands.
2270 This option supports GDB GUIs which don't
2271 distinguish hard versus soft breakpoints, if the default OpenOCD and
2272 GDB behaviour is not sufficient. GDB normally uses hardware
2273 breakpoints if the memory map has been set up for flash regions.
2274 @end deffn
2276 @anchor{gdbflashprogram}
2277 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2278 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2279 vFlash packet is received.
2280 The default behaviour is @option{enable}.
2281 @end deffn
2283 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2284 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2285 requested. GDB will then know when to set hardware breakpoints, and program flash
2286 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2287 for flash programming to work.
2288 Default behaviour is @option{enable}.
2289 @xref{gdbflashprogram,,gdb_flash_program}.
2290 @end deffn
2292 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2293 Specifies whether data aborts cause an error to be reported
2294 by GDB memory read packets.
2295 The default behaviour is @option{disable};
2296 use @option{enable} see these errors reported.
2297 @end deffn
2299 @anchor{eventpolling}
2300 @section Event Polling
2302 Hardware debuggers are parts of asynchronous systems,
2303 where significant events can happen at any time.
2304 The OpenOCD server needs to detect some of these events,
2305 so it can report them to through TCL command line
2306 or to GDB.
2308 Examples of such events include:
2310 @itemize
2311 @item One of the targets can stop running ... maybe it triggers
2312 a code breakpoint or data watchpoint, or halts itself.
2313 @item Messages may be sent over ``debug message'' channels ... many
2314 targets support such messages sent over JTAG,
2315 for receipt by the person debugging or tools.
2316 @item Loss of power ... some adapters can detect these events.
2317 @item Resets not issued through JTAG ... such reset sources
2318 can include button presses or other system hardware, sometimes
2319 including the target itself (perhaps through a watchdog).
2320 @item Debug instrumentation sometimes supports event triggering
2321 such as ``trace buffer full'' (so it can quickly be emptied)
2322 or other signals (to correlate with code behavior).
2323 @end itemize
2325 None of those events are signaled through standard JTAG signals.
2326 However, most conventions for JTAG connectors include voltage
2327 level and system reset (SRST) signal detection.
2328 Some connectors also include instrumentation signals, which
2329 can imply events when those signals are inputs.
2331 In general, OpenOCD needs to periodically check for those events,
2332 either by looking at the status of signals on the JTAG connector
2333 or by sending synchronous ``tell me your status'' JTAG requests
2334 to the various active targets.
2335 There is a command to manage and monitor that polling,
2336 which is normally done in the background.
2338 @deffn Command poll [@option{on}|@option{off}]
2339 Poll the current target for its current state.
2340 (Also, @pxref{targetcurstate,,target curstate}.)
2341 If that target is in debug mode, architecture
2342 specific information about the current state is printed.
2343 An optional parameter
2344 allows background polling to be enabled and disabled.
2346 You could use this from the TCL command shell, or
2347 from GDB using @command{monitor poll} command.
2348 Leave background polling enabled while you're using GDB.
2349 @example
2350 > poll
2351 background polling: on
2352 target state: halted
2353 target halted in ARM state due to debug-request, \
2354 current mode: Supervisor
2355 cpsr: 0x800000d3 pc: 0x11081bfc
2356 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2357 >
2358 @end example
2359 @end deffn
2361 @node Debug Adapter Configuration
2362 @chapter Debug Adapter Configuration
2363 @cindex config file, interface
2364 @cindex interface config file
2366 Correctly installing OpenOCD includes making your operating system give
2367 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2368 are used to select which one is used, and to configure how it is used.
2370 @quotation Note
2371 Because OpenOCD started out with a focus purely on JTAG, you may find
2372 places where it wrongly presumes JTAG is the only transport protocol
2373 in use. Be aware that recent versions of OpenOCD are removing that
2374 limitation. JTAG remains more functional than most other transports.
2375 Other transports do not support boundary scan operations, or may be
2376 specific to a given chip vendor. Some might be usable only for
2377 programming flash memory, instead of also for debugging.
2378 @end quotation
2380 Debug Adapters/Interfaces/Dongles are normally configured
2381 through commands in an interface configuration
2382 file which is sourced by your @file{openocd.cfg} file, or
2383 through a command line @option{-f interface/....cfg} option.
2385 @example
2386 source [find interface/olimex-jtag-tiny.cfg]
2387 @end example
2389 These commands tell
2390 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2391 A few cases are so simple that you only need to say what driver to use:
2393 @example
2394 # jlink interface
2395 interface jlink
2396 @end example
2398 Most adapters need a bit more configuration than that.
2401 @section Interface Configuration
2403 The interface command tells OpenOCD what type of debug adapter you are
2404 using. Depending on the type of adapter, you may need to use one or
2405 more additional commands to further identify or configure the adapter.
2407 @deffn {Config Command} {interface} name
2408 Use the interface driver @var{name} to connect to the
2409 target.
2410 @end deffn
2412 @deffn Command {interface_list}
2413 List the debug adapter drivers that have been built into
2414 the running copy of OpenOCD.
2415 @end deffn
2416 @deffn Command {interface transports} transport_name+
2417 Specifies the transports supported by this debug adapter.
2418 The adapter driver builds-in similar knowledge; use this only
2419 when external configuration (such as jumpering) changes what
2420 the hardware can support.
2421 @end deffn
2425 @deffn Command {adapter_name}
2426 Returns the name of the debug adapter driver being used.
2427 @end deffn
2429 @section Interface Drivers
2431 Each of the interface drivers listed here must be explicitly
2432 enabled when OpenOCD is configured, in order to be made
2433 available at run time.
2435 @deffn {Interface Driver} {amt_jtagaccel}
2436 Amontec Chameleon in its JTAG Accelerator configuration,
2437 connected to a PC's EPP mode parallel port.
2438 This defines some driver-specific commands:
2440 @deffn {Config Command} {parport_port} number
2441 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2442 the number of the @file{/dev/parport} device.
2443 @end deffn
2445 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2446 Displays status of RTCK option.
2447 Optionally sets that option first.
2448 @end deffn
2449 @end deffn
2451 @deffn {Interface Driver} {arm-jtag-ew}
2452 Olimex ARM-JTAG-EW USB adapter
2453 This has one driver-specific command:
2455 @deffn Command {armjtagew_info}
2456 Logs some status
2457 @end deffn
2458 @end deffn
2460 @deffn {Interface Driver} {at91rm9200}
2461 Supports bitbanged JTAG from the local system,
2462 presuming that system is an Atmel AT91rm9200
2463 and a specific set of GPIOs is used.
2464 @c command: at91rm9200_device NAME
2465 @c chooses among list of bit configs ... only one option
2466 @end deffn
2468 @deffn {Interface Driver} {dummy}
2469 A dummy software-only driver for debugging.
2470 @end deffn
2472 @deffn {Interface Driver} {ep93xx}
2473 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2474 @end deffn
2476 @deffn {Interface Driver} {ft2232}
2477 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2479 Note that this driver has several flaws and the @command{ftdi} driver is
2480 recommended as its replacement.
2482 These interfaces have several commands, used to configure the driver
2483 before initializing the JTAG scan chain:
2485 @deffn {Config Command} {ft2232_device_desc} description
2486 Provides the USB device description (the @emph{iProduct string})
2487 of the FTDI FT2232 device. If not
2488 specified, the FTDI default value is used. This setting is only valid
2489 if compiled with FTD2XX support.
2490 @end deffn
2492 @deffn {Config Command} {ft2232_serial} serial-number
2493 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2494 in case the vendor provides unique IDs and more than one FT2232 device
2495 is connected to the host.
2496 If not specified, serial numbers are not considered.
2497 (Note that USB serial numbers can be arbitrary Unicode strings,
2498 and are not restricted to containing only decimal digits.)
2499 @end deffn
2501 @deffn {Config Command} {ft2232_layout} name
2502 Each vendor's FT2232 device can use different GPIO signals
2503 to control output-enables, reset signals, and LEDs.
2504 Currently valid layout @var{name} values include:
2505 @itemize @minus
2506 @item @b{axm0432_jtag} Axiom AXM-0432
2507 @item @b{comstick} Hitex STR9 comstick
2508 @item @b{cortino} Hitex Cortino JTAG interface
2509 @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
2510 either for the local Cortex-M3 (SRST only)
2511 or in a passthrough mode (neither SRST nor TRST)
2512 This layout can not support the SWO trace mechanism, and should be
2513 used only for older boards (before rev C).
2514 @item @b{luminary_icdi} This layout should be used with most TI/Luminary
2515 eval boards, including Rev C LM3S811 eval boards and the eponymous
2516 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2517 to debug some other target. It can support the SWO trace mechanism.
2518 @item @b{flyswatter} Tin Can Tools Flyswatter
2519 @item @b{icebear} ICEbear JTAG adapter from Section 5
2520 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2521 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2522 @item @b{m5960} American Microsystems M5960
2523 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2524 @item @b{oocdlink} OOCDLink
2525 @c oocdlink ~= jtagkey_prototype_v1
2526 @item @b{redbee-econotag} Integrated with a Redbee development board.
2527 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2528 @item @b{sheevaplug} Marvell Sheevaplug development kit
2529 @item @b{signalyzer} Xverve Signalyzer
2530 @item @b{stm32stick} Hitex STM32 Performance Stick
2531 @item @b{turtelizer2} egnite Software turtelizer2
2532 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2533 @end itemize
2534 @end deffn
2536 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2537 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2538 default values are used.
2539 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2540 @example
2541 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2542 @end example
2543 @end deffn
2545 @deffn {Config Command} {ft2232_latency} ms
2546 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2547 ft2232_read() fails to return the expected number of bytes. This can be caused by
2548 USB communication delays and has proved hard to reproduce and debug. Setting the
2549 FT2232 latency timer to a larger value increases delays for short USB packets but it
2550 also reduces the risk of timeouts before receiving the expected number of bytes.
2551 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2552 @end deffn
2554 @deffn {Config Command} {ft2232_channel} channel
2555 Used to select the channel of the ft2232 chip to use (between 1 and 4).
2556 The default value is 1.
2557 @end deffn
2559 For example, the interface config file for a
2560 Turtelizer JTAG Adapter looks something like this:
2562 @example
2563 interface ft2232
2564 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2565 ft2232_layout turtelizer2
2566 ft2232_vid_pid 0x0403 0xbdc8
2567 @end example
2568 @end deffn
2570 @deffn {Interface Driver} {ftdi}
2571 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2572 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2573 It is a complete rewrite to address a large number of problems with the ft2232
2574 interface driver.
2576 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2577 bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
2578 consistently faster than the ft2232 driver, sometimes several times faster.
2580 A major improvement of this driver is that support for new FTDI based adapters
2581 can be added competely through configuration files, without the need to patch
2582 and rebuild OpenOCD.
2584 The driver uses a signal abstraction to enable Tcl configuration files to
2585 define outputs for one or several FTDI GPIO. These outputs can then be
2586 controlled using the @command{ftdi_set_signal} command. Special signal names
2587 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2588 will be used for their customary purpose.
2590 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2591 be controlled differently. In order to support tristateable signals such as
2592 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2593 signal. The following output buffer configurations are supported:
2595 @itemize @minus
2596 @item Push-pull with one FTDI output as (non-)inverted data line
2597 @item Open drain with one FTDI output as (non-)inverted output-enable
2598 @item Tristate with one FTDI output as (non-)inverted data line and another
2599 FTDI output as (non-)inverted output-enable
2600 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2601 switching data and direction as necessary
2602 @end itemize
2604 These interfaces have several commands, used to configure the driver
2605 before initializing the JTAG scan chain:
2607 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2608 The vendor ID and product ID of the adapter. If not specified, the FTDI
2609 default values are used.
2610 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2611 @example
2612 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2613 @end example
2614 @end deffn
2616 @deffn {Config Command} {ftdi_device_desc} description
2617 Provides the USB device description (the @emph{iProduct string})
2618 of the adapter. If not specified, the device description is ignored
2619 during device selection.
2620 @end deffn
2622 @deffn {Config Command} {ftdi_serial} serial-number
2623 Specifies the @var{serial-number} of the adapter to use,
2624 in case the vendor provides unique IDs and more than one adapter
2625 is connected to the host.
2626 If not specified, serial numbers are not considered.
2627 (Note that USB serial numbers can be arbitrary Unicode strings,
2628 and are not restricted to containing only decimal digits.)
2629 @end deffn
2631 @deffn {Config Command} {ftdi_channel} channel
2632 Selects the channel of the FTDI device to use for MPSSE operations. Most
2633 adapters use the default, channel 0, but there are exceptions.
2634 @end deffn
2636 @deffn {Config Command} {ftdi_layout_init} data direction
2637 Specifies the initial values of the FTDI GPIO data and direction registers.
2638 Each value is a 16-bit number corresponding to the concatenation of the high
2639 and low FTDI GPIO registers. The values should be selected based on the
2640 schematics of the adapter, such that all signals are set to safe levels with
2641 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2642 and initially asserted reset signals.
2643 @end deffn
2645 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask]
2646 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2647 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2648 register bitmasks to tell the driver the connection and type of the output
2649 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2650 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2651 used with inverting data inputs and @option{-data} with non-inverting inputs.
2652 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2653 not-output-enable) input to the output buffer is connected.
2655 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2656 simple open-collector transistor driver would be specified with @option{-oe}
2657 only. In that case the signal can only be set to drive low or to Hi-Z and the
2658 driver will complain if the signal is set to drive high. Which means that if
2659 it's a reset signal, @command{reset_config} must be specified as
2660 @option{srst_open_drain}, not @option{srst_push_pull}.
2662 A special case is provided when @option{-data} and @option{-oe} is set to the
2663 same bitmask. Then the FTDI pin is considered being connected straight to the
2664 target without any buffer. The FTDI pin is then switched between output and
2665 input as necessary to provide the full set of low, high and Hi-Z
2666 characteristics. In all other cases, the pins specified in a signal definition
2667 are always driven by the FTDI.
2668 @end deffn
2670 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2671 Set a previously defined signal to the specified level.
2672 @itemize @minus
2673 @item @option{0}, drive low
2674 @item @option{1}, drive high
2675 @item @option{z}, set to high-impedance
2676 @end itemize
2677 @end deffn
2679 For example adapter definitions, see the configuration files shipped in the
2680 @file{interface/ftdi} directory.
2681 @end deffn
2683 @deffn {Interface Driver} {remote_bitbang}
2684 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2685 with a remote process and sends ASCII encoded bitbang requests to that process
2686 instead of directly driving JTAG.
2688 The remote_bitbang driver is useful for debugging software running on
2689 processors which are being simulated.
2691 @deffn {Config Command} {remote_bitbang_port} number
2692 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2693 sockets instead of TCP.
2694 @end deffn
2696 @deffn {Config Command} {remote_bitbang_host} hostname
2697 Specifies the hostname of the remote process to connect to using TCP, or the
2698 name of the UNIX socket to use if remote_bitbang_port is 0.
2699 @end deffn
2701 For example, to connect remotely via TCP to the host foobar you might have
2702 something like:
2704 @example
2705 interface remote_bitbang
2706 remote_bitbang_port 3335
2707 remote_bitbang_host foobar
2708 @end example
2710 To connect to another process running locally via UNIX sockets with socket
2711 named mysocket:
2713 @example
2714 interface remote_bitbang
2715 remote_bitbang_port 0
2716 remote_bitbang_host mysocket
2717 @end example
2718 @end deffn
2720 @deffn {Interface Driver} {usb_blaster}
2721 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2722 for FTDI chips. These interfaces have several commands, used to
2723 configure the driver before initializing the JTAG scan chain:
2725 @deffn {Config Command} {usb_blaster_device_desc} description
2726 Provides the USB device description (the @emph{iProduct string})
2727 of the FTDI FT245 device. If not
2728 specified, the FTDI default value is used. This setting is only valid
2729 if compiled with FTD2XX support.
2730 @end deffn
2732 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2733 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2734 default values are used.
2735 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2736 Altera USB-Blaster (default):
2737 @example
2738 usb_blaster_vid_pid 0x09FB 0x6001
2739 @end example
2740 The following VID/PID is for Kolja Waschk's USB JTAG:
2741 @example
2742 usb_blaster_vid_pid 0x16C0 0x06AD
2743 @end example
2744 @end deffn
2746 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2747 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2748 female JTAG header). These pins can be used as SRST and/or TRST provided the
2749 appropriate connections are made on the target board.
2751 For example, to use pin 6 as SRST (as with an AVR board):
2752 @example
2753 $_TARGETNAME configure -event reset-assert \
2754 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2755 @end example
2756 @end deffn
2758 @end deffn
2760 @deffn {Interface Driver} {gw16012}
2761 Gateworks GW16012 JTAG programmer.
2762 This has one driver-specific command:
2764 @deffn {Config Command} {parport_port} [port_number]
2765 Display either the address of the I/O port
2766 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2767 If a parameter is provided, first switch to use that port.
2768 This is a write-once setting.
2769 @end deffn
2770 @end deffn
2772 @deffn {Interface Driver} {jlink}
2773 Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
2775 @quotation Compatibility Note
2776 Segger released many firmware versions for the many harware versions they
2777 produced. OpenOCD was extensively tested and intended to run on all of them,
2778 but some combinations were reported as incompatible. As a general
2779 recommendation, it is advisable to use the latest firmware version
2780 available for each hardware version. However the current V8 is a moving
2781 target, and Segger firmware versions released after the OpenOCD was
2782 released may not be compatible. In such cases it is recommended to
2783 revert to the last known functional version. For 0.5.0, this is from
2784 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2785 version is from "May 3 2012 18:36:22", packed with 4.46f.
2786 @end quotation
2788 @deffn {Command} {jlink caps}
2789 Display the device firmware capabilities.
2790 @end deffn
2791 @deffn {Command} {jlink info}
2792 Display various device information, like hardware version, firmware version, current bus status.
2793 @end deffn
2794 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2795 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2796 @end deffn
2797 @deffn {Command} {jlink config}
2798 Display the J-Link configuration.
2799 @end deffn
2800 @deffn {Command} {jlink config kickstart} [val]
2801 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2802 @end deffn
2803 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2804 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2805 @end deffn
2806 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2807 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2808 E the bit of the subnet mask and
2809 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2810 @end deffn
2811 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2812 Set the USB address; this will also change the product id. Without argument, show the USB address.
2813 @end deffn
2814 @deffn {Command} {jlink config reset}
2815 Reset the current configuration.
2816 @end deffn
2817 @deffn {Command} {jlink config save}
2818 Save the current configuration to the internal persistent storage.
2819 @end deffn
2820 @deffn {Config} {jlink pid} val
2821 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2822 @end deffn
2823 @end deffn
2825 @deffn {Interface Driver} {parport}
2826 Supports PC parallel port bit-banging cables:
2827 Wigglers, PLD download cable, and more.
2828 These interfaces have several commands, used to configure the driver
2829 before initializing the JTAG scan chain:
2831 @deffn {Config Command} {parport_cable} name
2832 Set the layout of the parallel port cable used to connect to the target.
2833 This is a write-once setting.
2834 Currently valid cable @var{name} values include:
2836 @itemize @minus
2837 @item @b{altium} Altium Universal JTAG cable.
2838 @item @b{arm-jtag} Same as original wiggler except SRST and
2839 TRST connections reversed and TRST is also inverted.
2840 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2841 in configuration mode. This is only used to
2842 program the Chameleon itself, not a connected target.
2843 @item @b{dlc5} The Xilinx Parallel cable III.
2844 @item @b{flashlink} The ST Parallel cable.
2845 @item @b{lattice} Lattice ispDOWNLOAD Cable
2846 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2847 some versions of
2848 Amontec's Chameleon Programmer. The new version available from
2849 the website uses the original Wiggler layout ('@var{wiggler}')
2850 @item @b{triton} The parallel port adapter found on the
2851 ``Karo Triton 1 Development Board''.
2852 This is also the layout used by the HollyGates design
2853 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2854 @item @b{wiggler} The original Wiggler layout, also supported by
2855 several clones, such as the Olimex ARM-JTAG
2856 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2857 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2858 @end itemize
2859 @end deffn
2861 @deffn {Config Command} {parport_port} [port_number]
2862 Display either the address of the I/O port
2863 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2864 If a parameter is provided, first switch to use that port.
2865 This is a write-once setting.
2867 When using PPDEV to access the parallel port, use the number of the parallel port:
2868 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2869 you may encounter a problem.
2870 @end deffn
2872 @deffn Command {parport_toggling_time} [nanoseconds]
2873 Displays how many nanoseconds the hardware needs to toggle TCK;
2874 the parport driver uses this value to obey the
2875 @command{adapter_khz} configuration.
2876 When the optional @var{nanoseconds} parameter is given,
2877 that setting is changed before displaying the current value.
2879 The default setting should work reasonably well on commodity PC hardware.
2880 However, you may want to calibrate for your specific hardware.
2881 @quotation Tip
2882 To measure the toggling time with a logic analyzer or a digital storage
2883 oscilloscope, follow the procedure below:
2884 @example
2885 > parport_toggling_time 1000
2886 > adapter_khz 500
2887 @end example
2888 This sets the maximum JTAG clock speed of the hardware, but
2889 the actual speed probably deviates from the requested 500 kHz.
2890 Now, measure the time between the two closest spaced TCK transitions.
2891 You can use @command{runtest 1000} or something similar to generate a
2892 large set of samples.
2893 Update the setting to match your measurement:
2894 @example
2895 > parport_toggling_time <measured nanoseconds>
2896 @end example
2897 Now the clock speed will be a better match for @command{adapter_khz rate}
2898 commands given in OpenOCD scripts and event handlers.
2900 You can do something similar with many digital multimeters, but note
2901 that you'll probably need to run the clock continuously for several
2902 seconds before it decides what clock rate to show. Adjust the
2903 toggling time up or down until the measured clock rate is a good
2904 match for the adapter_khz rate you specified; be conservative.
2905 @end quotation
2906 @end deffn
2908 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2909 This will configure the parallel driver to write a known
2910 cable-specific value to the parallel interface on exiting OpenOCD.
2911 @end deffn
2913 For example, the interface configuration file for a
2914 classic ``Wiggler'' cable on LPT2 might look something like this:
2916 @example
2917 interface parport
2918 parport_port 0x278
2919 parport_cable wiggler
2920 @end example
2921 @end deffn
2923 @deffn {Interface Driver} {presto}
2924 ASIX PRESTO USB JTAG programmer.
2925 @deffn {Config Command} {presto_serial} serial_string
2926 Configures the USB serial number of the Presto device to use.
2927 @end deffn
2928 @end deffn
2930 @deffn {Interface Driver} {rlink}
2931 Raisonance RLink USB adapter
2932 @end deffn
2934 @deffn {Interface Driver} {usbprog}
2935 usbprog is a freely programmable USB adapter.
2936 @end deffn
2938 @deffn {Interface Driver} {vsllink}
2939 vsllink is part of Versaloon which is a versatile USB programmer.
2941 @quotation Note
2942 This defines quite a few driver-specific commands,
2943 which are not currently documented here.
2944 @end quotation
2945 @end deffn
2947 @deffn {Interface Driver} {hla}
2948 This is a driver that supports multiple High Level Adapters.
2949 This type of adapter does not expose some of the lower level api's
2950 that OpenOCD would normally use to access the target.
2952 Currently supported adapters include the ST STLINK and TI ICDI.
2954 @deffn {Config Command} {hla_device_desc} description
2955 Currently Not Supported.
2956 @end deffn
2958 @deffn {Config Command} {hla_serial} serial
2959 Currently Not Supported.
2960 @end deffn
2962 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
2963 Specifies the adapter layout to use.
2964 @end deffn
2966 @deffn {Config Command} {hla_vid_pid} vid pid
2967 The vendor ID and product ID of the device.
2968 @end deffn
2970 @deffn {Config Command} {stlink_api} api_level
2971 Manually sets the stlink api used, valid options are 1 or 2. (@b{STLINK Only}).
2972 @end deffn
2973 @end deffn
2975 @deffn {Interface Driver} {opendous}
2976 opendous-jtag is a freely programmable USB adapter.
2977 @end deffn
2979 @deffn {Interface Driver} {ulink}
2980 This is the Keil ULINK v1 JTAG debugger.
2981 @end deffn
2983 @deffn {Interface Driver} {ZY1000}
2984 This is the Zylin ZY1000 JTAG debugger.
2985 @end deffn
2987 @quotation Note
2988 This defines some driver-specific commands,
2989 which are not currently documented here.
2990 @end quotation
2992 @deffn Command power [@option{on}|@option{off}]
2993 Turn power switch to target on/off.
2994 No arguments: print status.
2995 @end deffn
2997 @section Transport Configuration
2998 @cindex Transport
2999 As noted earlier, depending on the version of OpenOCD you use,
3000 and the debug adapter you are using,
3001 several transports may be available to
3002 communicate with debug targets (or perhaps to program flash memory).
3003 @deffn Command {transport list}
3004 displays the names of the transports supported by this
3005 version of OpenOCD.
3006 @end deffn
3008 @deffn Command {transport select} transport_name
3009 Select which of the supported transports to use in this OpenOCD session.
3010 The transport must be supported by the debug adapter hardware and by the
3011 version of OPenOCD you are using (including the adapter's driver).
3012 No arguments: returns name of session's selected transport.
3013 @end deffn
3015 @subsection JTAG Transport
3016 @cindex JTAG
3017 JTAG is the original transport supported by OpenOCD, and most
3018 of the OpenOCD commands support it.
3019 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3020 each of which must be explicitly declared.
3021 JTAG supports both debugging and boundary scan testing.
3022 Flash programming support is built on top of debug support.
3023 @subsection SWD Transport
3024 @cindex SWD
3025 @cindex Serial Wire Debug
3026 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3027 Debug Access Point (DAP, which must be explicitly declared.
3028 (SWD uses fewer signal wires than JTAG.)
3029 SWD is debug-oriented, and does not support boundary scan testing.
3030 Flash programming support is built on top of debug support.
3031 (Some processors support both JTAG and SWD.)
3032 @deffn Command {swd newdap} ...
3033 Declares a single DAP which uses SWD transport.
3034 Parameters are currently the same as "jtag newtap" but this is
3035 expected to change.
3036 @end deffn
3037 @deffn Command {swd wcr trn prescale}
3038 Updates TRN (turnaraound delay) and prescaling.fields of the
3039 Wire Control Register (WCR).
3040 No parameters: displays current settings.
3041 @end deffn
3043 @subsection SPI Transport
3044 @cindex SPI
3045 @cindex Serial Peripheral Interface
3046 The Serial Peripheral Interface (SPI) is a general purpose transport
3047 which uses four wire signaling. Some processors use it as part of a
3048 solution for flash programming.
3050 @anchor{jtagspeed}
3051 @section JTAG Speed
3052 JTAG clock setup is part of system setup.
3053 It @emph{does not belong with interface setup} since any interface
3054 only knows a few of the constraints for the JTAG clock speed.
3055 Sometimes the JTAG speed is
3056 changed during the target initialization process: (1) slow at
3057 reset, (2) program the CPU clocks, (3) run fast.
3058 Both the "slow" and "fast" clock rates are functions of the
3059 oscillators used, the chip, the board design, and sometimes
3060 power management software that may be active.
3062 The speed used during reset, and the scan chain verification which
3063 follows reset, can be adjusted using a @code{reset-start}
3064 target event handler.
3065 It can then be reconfigured to a faster speed by a
3066 @code{reset-init} target event handler after it reprograms those
3067 CPU clocks, or manually (if something else, such as a boot loader,
3068 sets up those clocks).
3069 @xref{targetevents,,Target Events}.
3070 When the initial low JTAG speed is a chip characteristic, perhaps
3071 because of a required oscillator speed, provide such a handler
3072 in the target config file.
3073 When that speed is a function of a board-specific characteristic
3074 such as which speed oscillator is used, it belongs in the board
3075 config file instead.
3076 In both cases it's safest to also set the initial JTAG clock rate
3077 to that same slow speed, so that OpenOCD never starts up using a
3078 clock speed that's faster than the scan chain can support.
3080 @example
3081 jtag_rclk 3000
3082 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3083 @end example
3085 If your system supports adaptive clocking (RTCK), configuring
3086 JTAG to use that is probably the most robust approach.
3087 However, it introduces delays to synchronize clocks; so it
3088 may not be the fastest solution.
3090 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3091 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3092 which support adaptive clocking.
3094 @deffn {Command} adapter_khz max_speed_kHz
3095 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3096 JTAG interfaces usually support a limited number of
3097 speeds. The speed actually used won't be faster
3098 than the speed specified.
3100 Chip data sheets generally include a top JTAG clock rate.
3101 The actual rate is often a function of a CPU core clock,
3102 and is normally less than that peak rate.
3103 For example, most ARM cores accept at most one sixth of the CPU clock.
3105 Speed 0 (khz) selects RTCK method.
3106 @xref{faqrtck,,FAQ RTCK}.
3107 If your system uses RTCK, you won't need to change the
3108 JTAG clocking after setup.
3109 Not all interfaces, boards, or targets support ``rtck''.
3110 If the interface device can not
3111 support it, an error is returned when you try to use RTCK.
3112 @end deffn
3114 @defun jtag_rclk fallback_speed_kHz
3115 @cindex adaptive clocking
3116 @cindex RTCK
3117 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3118 If that fails (maybe the interface, board, or target doesn't
3119 support it), falls back to the specified frequency.
3120 @example
3121 # Fall back to 3mhz if RTCK is not supported
3122 jtag_rclk 3000
3123 @end example
3124 @end defun
3126 @node Reset Configuration
3127 @chapter Reset Configuration
3128 @cindex Reset Configuration
3130 Every system configuration may require a different reset
3131 configuration. This can also be quite confusing.
3132 Resets also interact with @var{reset-init} event handlers,
3133 which do things like setting up clocks and DRAM, and
3134 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3135 They can also interact with JTAG routers.
3136 Please see the various board files for examples.
3138 @quotation Note
3139 To maintainers and integrators:
3140 Reset configuration touches several things at once.
3141 Normally the board configuration file
3142 should define it and assume that the JTAG adapter supports
3143 everything that's wired up to the board's JTAG connector.
3145 However, the target configuration file could also make note
3146 of something the silicon vendor has done inside the chip,
3147 which will be true for most (or all) boards using that chip.
3148 And when the JTAG adapter doesn't support everything, the
3149 user configuration file will need to override parts of
3150 the reset configuration provided by other files.
3151 @end quotation
3153 @section Types of Reset
3155 There are many kinds of reset possible through JTAG, but
3156 they may not all work with a given board and adapter.
3157 That's part of why reset configuration can be error prone.
3159 @itemize @bullet
3160 @item
3161 @emph{System Reset} ... the @emph{SRST} hardware signal
3162 resets all chips connected to the JTAG adapter, such as processors,
3163 power management chips, and I/O controllers. Normally resets triggered
3164 with this signal behave exactly like pressing a RESET button.
3165 @item
3166 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3167 just the TAP controllers connected to the JTAG adapter.
3168 Such resets should not be visible to the rest of the system; resetting a
3169 device's TAP controller just puts that controller into a known state.
3170 @item
3171 @emph{Emulation Reset} ... many devices can be reset through JTAG
3172 commands. These resets are often distinguishable from system
3173 resets, either explicitly (a "reset reason" register says so)
3174 or implicitly (not all parts of the chip get reset).
3175 @item
3176 @emph{Other Resets} ... system-on-chip devices often support
3177 several other types of reset.
3178 You may need to arrange that a watchdog timer stops
3179 while debugging, preventing a watchdog reset.
3180 There may be individual module resets.
3181 @end itemize
3183 In the best case, OpenOCD can hold SRST, then reset
3184 the TAPs via TRST and send commands through JTAG to halt the
3185 CPU at the reset vector before the 1st instruction is executed.
3186 Then when it finally releases the SRST signal, the system is
3187 halted under debugger control before any code has executed.
3188 This is the behavior required to support the @command{reset halt}
3189 and @command{reset init} commands; after @command{reset init} a
3190 board-specific script might do things like setting up DRAM.
3191 (@xref{resetcommand,,Reset Command}.)
3193 @anchor{srstandtrstissues}
3194 @section SRST and TRST Issues
3196 Because SRST and TRST are hardware signals, they can have a
3197 variety of system-specific constraints. Some of the most
3198 common issues are:
3200 @itemize @bullet
3202 @item @emph{Signal not available} ... Some boards don't wire
3203 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3204 support such signals even if they are wired up.
3205 Use the @command{reset_config} @var{signals} options to say
3206 when either of those signals is not connected.
3207 When SRST is not available, your code might not be able to rely
3208 on controllers having been fully reset during code startup.
3209 Missing TRST is not a problem, since JTAG-level resets can
3210 be triggered using with TMS signaling.
3212 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3213 adapter will connect SRST to TRST, instead of keeping them separate.
3214 Use the @command{reset_config} @var{combination} options to say
3215 when those signals aren't properly independent.
3217 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3218 delay circuit, reset supervisor, or on-chip features can extend
3219 the effect of a JTAG adapter's reset for some time after the adapter
3220 stops issuing the reset. For example, there may be chip or board
3221 requirements that all reset pulses last for at least a
3222 certain amount of time; and reset buttons commonly have
3223 hardware debouncing.
3224 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3225 commands to say when extra delays are needed.
3227 @item @emph{Drive type} ... Reset lines often have a pullup
3228 resistor, letting the JTAG interface treat them as open-drain
3229 signals. But that's not a requirement, so the adapter may need
3230 to use push/pull output drivers.
3231 Also, with weak pullups it may be advisable to drive
3232 signals to both levels (push/pull) to minimize rise times.
3233 Use the @command{reset_config} @var{trst_type} and
3234 @var{srst_type} parameters to say how to drive reset signals.
3236 @item @emph{Special initialization} ... Targets sometimes need
3237 special JTAG initialization sequences to handle chip-specific
3238 issues (not limited to errata).
3239 For example, certain JTAG commands might need to be issued while
3240 the system as a whole is in a reset state (SRST active)
3241 but the JTAG scan chain is usable (TRST inactive).
3242 Many systems treat combined assertion of SRST and TRST as a
3243 trigger for a harder reset than SRST alone.
3244 Such custom reset handling is discussed later in this chapter.
3245 @end itemize
3247 There can also be other issues.
3248 Some devices don't fully conform to the JTAG specifications.
3249 Trivial system-specific differences are common, such as
3250 SRST and TRST using slightly different names.
3251 There are also vendors who distribute key JTAG documentation for
3252 their chips only to developers who have signed a Non-Disclosure
3253 Agreement (NDA).
3255 Sometimes there are chip-specific extensions like a requirement to use
3256 the normally-optional TRST signal (precluding use of JTAG adapters which
3257 don't pass TRST through), or needing extra steps to complete a TAP reset.
3259 In short, SRST and especially TRST handling may be very finicky,
3260 needing to cope with both architecture and board specific constraints.
3262 @section Commands for Handling Resets
3264 @deffn {Command} adapter_nsrst_assert_width milliseconds
3265 Minimum amount of time (in milliseconds) OpenOCD should wait
3266 after asserting nSRST (active-low system reset) before
3267 allowing it to be deasserted.
3268 @end deffn
3270 @deffn {Command} adapter_nsrst_delay milliseconds
3271 How long (in milliseconds) OpenOCD should wait after deasserting
3272 nSRST (active-low system reset) before starting new JTAG operations.
3273 When a board has a reset button connected to SRST line it will
3274 probably have hardware debouncing, implying you should use this.
3275 @end deffn
3277 @deffn {Command} jtag_ntrst_assert_width milliseconds
3278 Minimum amount of time (in milliseconds) OpenOCD should wait
3279 after asserting nTRST (active-low JTAG TAP reset) before
3280 allowing it to be deasserted.
3281 @end deffn
3283 @deffn {Command} jtag_ntrst_delay milliseconds
3284 How long (in milliseconds) OpenOCD should wait after deasserting
3285 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3286 @end deffn
3288 @deffn {Command} reset_config mode_flag ...
3289 This command displays or modifies the reset configuration
3290 of your combination of JTAG board and target in target
3291 configuration scripts.
3293 Information earlier in this section describes the kind of problems
3294 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3295 As a rule this command belongs only in board config files,
3296 describing issues like @emph{board doesn't connect TRST};
3297 or in user config files, addressing limitations derived
3298 from a particular combination of interface and board.
3299 (An unlikely example would be using a TRST-only adapter
3300 with a board that only wires up SRST.)
3302 The @var{mode_flag} options can be specified in any order, but only one
3303 of each type -- @var{signals}, @var{combination}, @var{gates},
3304 @var{trst_type}, @var{srst_type} and @var{connect_type}
3305 -- may be specified at a time.
3306 If you don't provide a new value for a given type, its previous
3307 value (perhaps the default) is unchanged.
3308 For example, this means that you don't need to say anything at all about
3309 TRST just to declare that if the JTAG adapter should want to drive SRST,
3310 it must explicitly be driven high (@option{srst_push_pull}).
3312 @itemize
3313 @item
3314 @var{signals} can specify which of the reset signals are connected.
3315 For example, If the JTAG interface provides SRST, but the board doesn't
3316 connect that signal properly, then OpenOCD can't use it.
3317 Possible values are @option{none} (the default), @option{trst_only},
3318 @option{srst_only} and @option{trst_and_srst}.
3320 @quotation Tip
3321 If your board provides SRST and/or TRST through the JTAG connector,
3322 you must declare that so those signals can be used.
3323 @end quotation
3325 @item
3326 The @var{combination} is an optional value specifying broken reset
3327 signal implementations.
3328 The default behaviour if no option given is @option{separate},
3329 indicating everything behaves normally.
3330 @option{srst_pulls_trst} states that the
3331 test logic is reset together with the reset of the system (e.g. NXP
3332 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3333 the system is reset together with the test logic (only hypothetical, I
3334 haven't seen hardware with such a bug, and can be worked around).
3335 @option{combined} implies both @option{srst_pulls_trst} and
3336 @option{trst_pulls_srst}.
3338 @item
3339 The @var{gates} tokens control flags that describe some cases where
3340 JTAG may be unvailable during reset.
3341 @option{srst_gates_jtag} (default)
3342 indicates that asserting SRST gates the
3343 JTAG clock. This means that no communication can happen on JTAG
3344 while SRST is asserted.
3345 Its converse is @option{srst_nogate}, indicating that JTAG commands
3346 can safely be issued while SRST is active.
3348 @item
3349 The @var{connect_type} tokens control flags that describe some cases where
3350 SRST is asserted while connecting to the target. @option{srst_nogate}
3351 is required to use this option.
3352 @option{connect_deassert_srst} (default)
3353 indicates that SRST will not be asserted while connecting to the target.
3354 Its converse is @option{connect_assert_srst}, indicating that SRST will
3355 be asserted before any target connection.
3356 Only some targets support this feature, STM32 and STR9 are examples.
3357 This feature is useful if you are unable to connect to your target due
3358 to incorrect options byte config or illegal program execution.
3359 @end itemize
3361 The optional @var{trst_type} and @var{srst_type} parameters allow the
3362 driver mode of each reset line to be specified. These values only affect
3363 JTAG interfaces with support for different driver modes, like the Amontec
3364 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3365 relevant signal (TRST or SRST) is not connected.
3367 @itemize
3368 @item
3369 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3370 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3371 Most boards connect this signal to a pulldown, so the JTAG TAPs
3372 never leave reset unless they are hooked up to a JTAG adapter.
3374 @item
3375 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3376 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3377 Most boards connect this signal to a pullup, and allow the
3378 signal to be pulled low by various events including system
3379 powerup and pressing a reset button.
3380 @end itemize
3381 @end deffn
3383 @section Custom Reset Handling
3384 @cindex events
3386 OpenOCD has several ways to help support the various reset
3387 mechanisms provided by chip and board vendors.
3388 The commands shown in the previous section give standard parameters.
3389 There are also @emph{event handlers} associated with TAPs or Targets.
3390 Those handlers are Tcl procedures you can provide, which are invoked
3391 at particular points in the reset sequence.
3393 @emph{When SRST is not an option} you must set
3394 up a @code{reset-assert} event handler for your target.
3395 For example, some JTAG adapters don't include the SRST signal;
3396 and some boards have multiple targets, and you won't always
3397 want to reset everything at once.
3399 After configuring those mechanisms, you might still
3400 find your board doesn't start up or reset correctly.
3401 For example, maybe it needs a slightly different sequence
3402 of SRST and/or TRST manipulations, because of quirks that
3403 the @command{reset_config} mechanism doesn't address;
3404 or asserting both might trigger a stronger reset, which
3405 needs special attention.
3407 Experiment with lower level operations, such as @command{jtag_reset}
3408 and the @command{jtag arp_*} operations shown here,
3409 to find a sequence of operations that works.
3410 @xref{JTAG Commands}.
3411 When you find a working sequence, it can be used to override
3412 @command{jtag_init}, which fires during OpenOCD startup
3413 (@pxref{configurationstage,,Configuration Stage});
3414 or @command{init_reset}, which fires during reset processing.
3416 You might also want to provide some project-specific reset
3417 schemes. For example, on a multi-target board the standard
3418 @command{reset} command would reset all targets, but you
3419 may need the ability to reset only one target at time and
3420 thus want to avoid using the board-wide SRST signal.
3422 @deffn {Overridable Procedure} init_reset mode
3423 This is invoked near the beginning of the @command{reset} command,
3424 usually to provide as much of a cold (power-up) reset as practical.
3425 By default it is also invoked from @command{jtag_init} if
3426 the scan chain does not respond to pure JTAG operations.
3427 The @var{mode} parameter is the parameter given to the
3428 low level reset command (@option{halt},
3429 @option{init}, or @option{run}), @option{setup},
3430 or potentially some other value.
3432 The default implementation just invokes @command{jtag arp_init-reset}.
3433 Replacements will normally build on low level JTAG
3434 operations such as @command{jtag_reset}.
3435 Operations here must not address individual TAPs
3436 (or their associated targets)
3437 until the JTAG scan chain has first been verified to work.
3439 Implementations must have verified the JTAG scan chain before
3440 they return.
3441 This is done by calling @command{jtag arp_init}
3442 (or @command{jtag arp_init-reset}).
3443 @end deffn
3445 @deffn Command {jtag arp_init}
3446 This validates the scan chain using just the four
3447 standard JTAG signals (TMS, TCK, TDI, TDO).
3448 It starts by issuing a JTAG-only reset.
3449 Then it performs checks to verify that the scan chain configuration
3450 matches the TAPs it can observe.
3451 Those checks include checking IDCODE values for each active TAP,
3452 and verifying the length of their instruction registers using
3453 TAP @code{-ircapture} and @code{-irmask} values.
3454 If these tests all pass, TAP @code{setup} events are
3455 issued to all TAPs with handlers for that event.
3456 @end deffn
3458 @deffn Command {jtag arp_init-reset}
3459 This uses TRST and SRST to try resetting
3460 everything on the JTAG scan chain
3461 (and anything else connected to SRST).
3462 It then invokes the logic of @command{jtag arp_init}.
3463 @end deffn
3466 @node TAP Declaration
3467 @chapter TAP Declaration
3468 @cindex TAP declaration
3469 @cindex TAP configuration
3471 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3472 TAPs serve many roles, including:
3474 @itemize @bullet
3475 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
3476 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
3477 Others do it indirectly, making a CPU do it.
3478 @item @b{Program Download} Using the same CPU support GDB uses,
3479 you can initialize a DRAM controller, download code to DRAM, and then
3480 start running that code.
3481 @item @b{Boundary Scan} Most chips support boundary scan, which
3482 helps test for board assembly problems like solder bridges
3483 and missing connections
3484 @end itemize
3486 OpenOCD must know about the active TAPs on your board(s).
3487 Setting up the TAPs is the core task of your configuration files.
3488 Once those TAPs are set up, you can pass their names to code
3489 which sets up CPUs and exports them as GDB targets,
3490 probes flash memory, performs low-level JTAG operations, and more.
3492 @section Scan Chains
3493 @cindex scan chain
3495 TAPs are part of a hardware @dfn{scan chain},
3496 which is daisy chain of TAPs.
3497 They also need to be added to
3498 OpenOCD's software mirror of that hardware list,
3499 giving each member a name and associating other data with it.
3500 Simple scan chains, with a single TAP, are common in
3501 systems with a single microcontroller or microprocessor.
3502 More complex chips may have several TAPs internally.
3503 Very complex scan chains might have a dozen or more TAPs:
3504 several in one chip, more in the next, and connecting
3505 to other boards with their own chips and TAPs.
3507 You can display the list with the @command{scan_chain} command.
3508 (Don't confuse this with the list displayed by the @command{targets}
3509 command, presented in the next chapter.
3510 That only displays TAPs for CPUs which are configured as
3511 debugging targets.)
3512 Here's what the scan chain might look like for a chip more than one TAP:
3514 @verbatim
3515 TapName Enabled IdCode Expected IrLen IrCap IrMask
3516 -- ------------------ ------- ---------- ---------- ----- ----- ------
3517 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3518 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3519 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3520 @end verbatim
3522 OpenOCD can detect some of that information, but not all
3523 of it. @xref{autoprobing,,Autoprobing}.
3524 Unfortunately those TAPs can't always be autoconfigured,
3525 because not all devices provide good support for that.
3526 JTAG doesn't require supporting IDCODE instructions, and
3527 chips with JTAG routers may not link TAPs into the chain
3528 until they are told to do so.
3530 The configuration mechanism currently supported by OpenOCD
3531 requires explicit configuration of all TAP devices using
3532 @command{jtag newtap} commands, as detailed later in this chapter.
3533 A command like this would declare one tap and name it @code{chip1.cpu}:
3535 @example
3536 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3537 @end example
3539 Each target configuration file lists the TAPs provided
3540 by a given chip.
3541 Board configuration files combine all the targets on a board,
3542 and so forth.
3543 Note that @emph{the order in which TAPs are declared is very important.}
3544 It must match the order in the JTAG scan chain, both inside
3545 a single chip and between them.
3546 @xref{faqtaporder,,FAQ TAP Order}.
3548 For example, the ST Microsystems STR912 chip has
3549 three separate TAPs@footnote{See the ST
3550 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3551 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3552 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3553 To configure those taps, @file{target/str912.cfg}
3554 includes commands something like this:
3556 @example
3557 jtag newtap str912 flash ... params ...
3558 jtag newtap str912 cpu ... params ...
3559 jtag newtap str912 bs ... params ...
3560 @end example
3562 Actual config files use a variable instead of literals like
3563 @option{str912}, to support more than one chip of each type.
3564 @xref{Config File Guidelines}.
3566 @deffn Command {jtag names}
3567 Returns the names of all current TAPs in the scan chain.
3568 Use @command{jtag cget} or @command{jtag tapisenabled}
3569 to examine attributes and state of each TAP.
3570 @example
3571 foreach t [jtag names] @{
3572 puts [format "TAP: %s\n" $t]
3573 @}
3574 @end example
3575 @end deffn
3577 @deffn Command {scan_chain}
3578 Displays the TAPs in the scan chain configuration,
3579 and their status.
3580 The set of TAPs listed by this command is fixed by
3581 exiting the OpenOCD configuration stage,
3582 but systems with a JTAG router can
3583 enable or disable TAPs dynamically.
3584 @end deffn
3586 @c FIXME! "jtag cget" should be able to return all TAP
3587 @c attributes, like "$target_name cget" does for targets.
3589 @c Probably want "jtag eventlist", and a "tap-reset" event
3590 @c (on entry to RESET state).
3592 @section TAP Names
3593 @cindex dotted name
3595 When TAP objects are declared with @command{jtag newtap},
3596 a @dfn{dotted.name} is created for the TAP, combining the
3597 name of a module (usually a chip) and a label for the TAP.
3598 For example: @code{xilinx.tap}, @code{str912.flash},
3599 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3600 Many other commands use that dotted.name to manipulate or
3601 refer to the TAP. For example, CPU configuration uses the
3602 name, as does declaration of NAND or NOR flash banks.
3604 The components of a dotted name should follow ``C'' symbol
3605 name rules: start with an alphabetic character, then numbers
3606 and underscores are OK; while others (including dots!) are not.
3608 @quotation Tip
3609 In older code, JTAG TAPs were numbered from 0..N.
3610 This feature is still present.
3611 However its use is highly discouraged, and
3612 should not be relied on; it will be removed by mid-2010.
3613 Update all of your scripts to use TAP names rather than numbers,
3614 by paying attention to the runtime warnings they trigger.
3615 Using TAP numbers in target configuration scripts prevents
3616 reusing those scripts on boards with multiple targets.
3617 @end quotation
3619 @section TAP Declaration Commands
3621 @c shouldn't this be(come) a {Config Command}?
3622 @deffn Command {jtag newtap} chipname tapname configparams...
3623 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3624 and configured according to the various @var{configparams}.
3626 The @var{chipname} is a symbolic name for the chip.
3627 Conventionally target config files use @code{$_CHIPNAME},
3628 defaulting to the model name given by the chip vendor but
3629 overridable.
3631 @cindex TAP naming convention
3632 The @var{tapname} reflects the role of that TAP,
3633 and should follow this convention:
3635 @itemize @bullet
3636 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3637 @item @code{cpu} -- The main CPU of the chip, alternatively
3638 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3639 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3640 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3641 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3642 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3643 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3644 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3645 with a single TAP;
3646 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3647 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3648 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3649 a JTAG TAP; that TAP should be named @code{sdma}.
3650 @end itemize
3652 Every TAP requires at least the following @var{configparams}:
3654 @itemize @bullet
3655 @item @code{-irlen} @var{NUMBER}
3656 @*The length in bits of the
3657 instruction register, such as 4 or 5 bits.
3658 @end itemize
3660 A TAP may also provide optional @var{configparams}:
3662 @itemize @bullet
3663 @item @code{-disable} (or @code{-enable})
3664 @*Use the @code{-disable} parameter to flag a TAP which is not
3665 linked in to the scan chain after a reset using either TRST
3666 or the JTAG state machine's @sc{reset} state.
3667 You may use @code{-enable} to highlight the default state
3668 (the TAP is linked in).
3669 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3670 @item @code{-expected-id} @var{number}
3671 @*A non-zero @var{number} represents a 32-bit IDCODE
3672 which you expect to find when the scan chain is examined.
3673 These codes are not required by all JTAG devices.
3674 @emph{Repeat the option} as many times as required if more than one
3675 ID code could appear (for example, multiple versions).
3676 Specify @var{number} as zero to suppress warnings about IDCODE
3677 values that were found but not included in the list.
3679 Provide this value if at all possible, since it lets OpenOCD
3680 tell when the scan chain it sees isn't right. These values
3681 are provided in vendors' chip documentation, usually a technical
3682 reference manual. Sometimes you may need to probe the JTAG
3683 hardware to find these values.
3684 @xref{autoprobing,,Autoprobing}.
3685 @item @code{-ignore-version}
3686 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3687 option. When vendors put out multiple versions of a chip, or use the same
3688 JTAG-level ID for several largely-compatible chips, it may be more practical
3689 to ignore the version field than to update config files to handle all of
3690 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3691 @item @code{-ircapture} @var{NUMBER}
3692 @*The bit pattern loaded by the TAP into the JTAG shift register
3693 on entry to the @sc{ircapture} state, such as 0x01.
3694 JTAG requires the two LSBs of this value to be 01.
3695 By default, @code{-ircapture} and @code{-irmask} are set
3696 up to verify that two-bit value. You may provide
3697 additional bits, if you know them, or indicate that
3698 a TAP doesn't conform to the JTAG specification.
3699 @item @code{-irmask} @var{NUMBER}
3700 @*A mask used with @code{-ircapture}
3701 to verify that instruction scans work correctly.
3702 Such scans are not used by OpenOCD except to verify that
3703 there seems to be no problems with JTAG scan chain operations.
3704 @end itemize
3705 @end deffn
3707 @section Other TAP commands
3709 @deffn Command {jtag cget} dotted.name @option{-event} name
3710 @deffnx Command {jtag configure} dotted.name @option{-event} name string
3711 At this writing this TAP attribute
3712 mechanism is used only for event handling.
3713 (It is not a direct analogue of the @code{cget}/@code{configure}
3714 mechanism for debugger targets.)
3715 See the next section for information about the available events.
3717 The @code{configure} subcommand assigns an event handler,
3718 a TCL string which is evaluated when the event is triggered.
3719 The @code{cget} subcommand returns that handler.
3720 @end deffn
3722 @section TAP Events
3723 @cindex events
3724 @cindex TAP events
3726 OpenOCD includes two event mechanisms.
3727 The one presented here applies to all JTAG TAPs.
3728 The other applies to debugger targets,
3729 which are associated with certain TAPs.
3731 The TAP events currently defined are:
3733 @itemize @bullet
3734 @item @b{post-reset}
3735 @* The TAP has just completed a JTAG reset.
3736 The tap may still be in the JTAG @sc{reset} state.
3737 Handlers for these events might perform initialization sequences
3738 such as issuing TCK cycles, TMS sequences to ensure
3739 exit from the ARM SWD mode, and more.
3741 Because the scan chain has not yet been verified, handlers for these events
3742 @emph{should not issue commands which scan the JTAG IR or DR registers}
3743 of any particular target.
3744 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3745 @item @b{setup}
3746 @* The scan chain has been reset and verified.
3747 This handler may enable TAPs as needed.
3748 @item @b{tap-disable}
3749 @* The TAP needs to be disabled. This handler should
3750 implement @command{jtag tapdisable}
3751 by issuing the relevant JTAG commands.
3752 @item @b{tap-enable}
3753 @* The TAP needs to be enabled. This handler should
3754 implement @command{jtag tapenable}
3755 by issuing the relevant JTAG commands.
3756 @end itemize
3758 If you need some action after each JTAG reset, which isn't actually
3759 specific to any TAP (since you can't yet trust the scan chain's
3760 contents to be accurate), you might:
3762 @example
3763 jtag configure CHIP.jrc -event post-reset @{
3764 echo "JTAG Reset done"
3765 ... non-scan jtag operations to be done after reset
3766 @}
3767 @end example
3770 @anchor{enablinganddisablingtaps}
3771 @section Enabling and Disabling TAPs
3772 @cindex JTAG Route Controller
3773 @cindex jrc
3775 In some systems, a @dfn{JTAG Route Controller} (JRC)
3776 is used to enable and/or disable specific JTAG TAPs.
3777 Many ARM based chips from Texas Instruments include
3778 an ``ICEpick'' module, which is a JRC.
3779 Such chips include DaVinci and OMAP3 processors.
3781 A given TAP may not be visible until the JRC has been
3782 told to link it into the scan chain; and if the JRC
3783 has been told to unlink that TAP, it will no longer
3784 be visible.
3785 Such routers address problems that JTAG ``bypass mode''
3786 ignores, such as:
3788 @itemize
3789 @item The scan chain can only go as fast as its slowest TAP.
3790 @item Having many TAPs slows instruction scans, since all
3791 TAPs receive new instructions.
3792 @item TAPs in the scan chain must be powered up, which wastes
3793 power and prevents debugging some power management mechanisms.
3794 @end itemize
3796 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3797 as implied by the existence of JTAG routers.
3798 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3799 does include a kind of JTAG router functionality.
3801 @c (a) currently the event handlers don't seem to be able to
3802 @c fail in a way that could lead to no-change-of-state.
3804 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3805 shown below, and is implemented using TAP event handlers.
3806 So for example, when defining a TAP for a CPU connected to
3807 a JTAG router, your @file{target.cfg} file
3808 should define TAP event handlers using
3809 code that looks something like this:
3811 @example
3812 jtag configure CHIP.cpu -event tap-enable @{
3813 ... jtag operations using CHIP.jrc
3814 @}
3815 jtag configure CHIP.cpu -event tap-disable @{
3816 ... jtag operations using CHIP.jrc
3817 @}
3818 @end example
3820 Then you might want that CPU's TAP enabled almost all the time:
3822 @example
3823 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3824 @end example
3826 Note how that particular setup event handler declaration
3827 uses quotes to evaluate @code{$CHIP} when the event is configured.
3828 Using brackets @{ @} would cause it to be evaluated later,
3829 at runtime, when it might have a different value.
3831 @deffn Command {jtag tapdisable} dotted.name
3832 If necessary, disables the tap
3833 by sending it a @option{tap-disable} event.
3834 Returns the string "1" if the tap
3835 specified by @var{dotted.name} is enabled,
3836 and "0" if it is disabled.
3837 @end deffn
3839 @deffn Command {jtag tapenable} dotted.name
3840 If necessary, enables the tap
3841 by sending it a @option{tap-enable} event.
3842 Returns the string "1" if the tap
3843 specified by @var{dotted.name} is enabled,
3844 and "0" if it is disabled.
3845 @end deffn
3847 @deffn Command {jtag tapisenabled} dotted.name
3848 Returns the string "1" if the tap
3849 specified by @var{dotted.name} is enabled,
3850 and "0" if it is disabled.
3852 @quotation Note
3853 Humans will find the @command{scan_chain} command more helpful
3854 for querying the state of the JTAG taps.
3855 @end quotation
3856 @end deffn
3858 @anchor{autoprobing}
3859 @section Autoprobing
3860 @cindex autoprobe
3861 @cindex JTAG autoprobe
3863 TAP configuration is the first thing that needs to be done
3864 after interface and reset configuration. Sometimes it's
3865 hard finding out what TAPs exist, or how they are identified.
3866 Vendor documentation is not always easy to find and use.
3868 To help you get past such problems, OpenOCD has a limited
3869 @emph{autoprobing} ability to look at the scan chain, doing
3870 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3871 To use this mechanism, start the OpenOCD server with only data
3872 that configures your JTAG interface, and arranges to come up
3873 with a slow clock (many devices don't support fast JTAG clocks
3874 right when they come out of reset).
3876 For example, your @file{openocd.cfg} file might have:
3878 @example
3879 source [find interface/olimex-arm-usb-tiny-h.cfg]
3880 reset_config trst_and_srst
3881 jtag_rclk 8
3882 @end example
3884 When you start the server without any TAPs configured, it will
3885 attempt to autoconfigure the TAPs. There are two parts to this:
3887 @enumerate
3888 @item @emph{TAP discovery} ...
3889 After a JTAG reset (sometimes a system reset may be needed too),
3890 each TAP's data registers will hold the contents of either the
3891 IDCODE or BYPASS register.
3892 If JTAG communication is working, OpenOCD will see each TAP,
3893 and report what @option{-expected-id} to use with it.
3894 @item @emph{IR Length discovery} ...
3895 Unfortunately JTAG does not provide a reliable way to find out
3896 the value of the @option{-irlen} parameter to use with a TAP
3897 that is discovered.
3898 If OpenOCD can discover the length of a TAP's instruction
3899 register, it will report it.
3900 Otherwise you may need to consult vendor documentation, such
3901 as chip data sheets or BSDL files.
3902 @end enumerate
3904 In many cases your board will have a simple scan chain with just
3905 a single device. Here's what OpenOCD reported with one board
3906 that's a bit more complex:
3908 @example
3909 clock speed 8 kHz
3910 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3911 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3912 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3913 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3914 AUTO auto0.tap - use "... -irlen 4"
3915 AUTO auto1.tap - use "... -irlen 4"
3916 AUTO auto2.tap - use "... -irlen 6"
3917 no gdb ports allocated as no target has been specified
3918 @end example
3920 Given that information, you should be able to either find some existing
3921 config files to use, or create your own. If you create your own, you
3922 would configure from the bottom up: first a @file{target.cfg} file
3923 with these TAPs, any targets associated with them, and any on-chip
3924 resources; then a @file{board.cfg} with off-chip resources, clocking,
3925 and so forth.
3927 @node CPU Configuration
3928 @chapter CPU Configuration
3929 @cindex GDB target
3931 This chapter discusses how to set up GDB debug targets for CPUs.
3932 You can also access these targets without GDB
3933 (@pxref{Architecture and Core Commands},
3934 and @ref{targetstatehandling,,Target State handling}) and
3935 through various kinds of NAND and NOR flash commands.
3936 If you have multiple CPUs you can have multiple such targets.
3938 We'll start by looking at how to examine the targets you have,
3939 then look at how to add one more target and how to configure it.
3941 @section Target List
3942 @cindex target, current
3943 @cindex target, list
3945 All targets that have been set up are part of a list,
3946 where each member has a name.
3947 That name should normally be the same as the TAP name.
3948 You can display the list with the @command{targets}
3949 (plural!) command.
3950 This display often has only one CPU; here's what it might
3951 look like with more than one:
3952 @verbatim
3953 TargetName Type Endian TapName State
3954 -- ------------------ ---------- ------ ------------------ ------------
3955 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
3956 1 MyTarget cortex_m3 little mychip.foo tap-disabled
3957 @end verbatim
3959 One member of that list is the @dfn{current target}, which
3960 is implicitly referenced by many commands.
3961 It's the one marked with a @code{*} near the target name.
3962 In particular, memory addresses often refer to the address
3963 space seen by that current target.
3964 Commands like @command{mdw} (memory display words)
3965 and @command{flash erase_address} (erase NOR flash blocks)
3966 are examples; and there are many more.
3968 Several commands let you examine the list of targets:
3970 @deffn Command {target count}
3971 @emph{Note: target numbers are deprecated; don't use them.
3972 They will be removed shortly after August 2010, including this command.
3973 Iterate target using @command{target names}, not by counting.}
3975 Returns the number of targets, @math{N}.
3976 The highest numbered target is @math{N - 1}.
3977 @example
3978 set c [target count]
3979 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
3980 # Assuming you have created this function
3981 print_target_details $x
3982 @}
3983 @end example
3984 @end deffn
3986 @deffn Command {target current}
3987 Returns the name of the current target.
3988 @end deffn
3990 @deffn Command {target names}
3991 Lists the names of all current targets in the list.
3992 @example
3993 foreach t [target names] @{
3994 puts [format "Target: %s\n" $t]
3995 @}
3996 @end example
3997 @end deffn
3999 @deffn Command {target number} number
4000 @emph{Note: target numbers are deprecated; don't use them.
4001 They will be removed shortly after August 2010, including this command.}
4003 The list of targets is numbered starting at zero.
4004 This command returns the name of the target at index @var{number}.
4005 @example
4006 set thename [target number $x]
4007 puts [format "Target %d is: %s\n" $x $thename]
4008 @end example
4009 @end deffn
4011 @c yep, "target list" would have been better.
4012 @c plus maybe "target setdefault".
4014 @deffn Command targets [name]
4015 @emph{Note: the name of this command is plural. Other target
4016 command names are singular.}
4018 With no parameter, this command displays a table of all known
4019 targets in a user friendly form.
4021 With a parameter, this command sets the current target to
4022 the given target with the given @var{name}; this is
4023 only relevant on boards which have more than one target.
4024 @end deffn
4026 @section Target CPU Types and Variants
4027 @cindex target type
4028 @cindex CPU type
4029 @cindex CPU variant
4031 Each target has a @dfn{CPU type}, as shown in the output of
4032 the @command{targets} command. You need to specify that type
4033 when calling @command{target create}.
4034 The CPU type indicates more than just the instruction set.
4035 It also indicates how that instruction set is implemented,
4036 what kind of debug support it integrates,
4037 whether it has an MMU (and if so, what kind),
4038 what core-specific commands may be available
4039 (@pxref{Architecture and Core Commands}),
4040 and more.
4042 For some CPU types, OpenOCD also defines @dfn{variants} which
4043 indicate differences that affect their handling.
4044 For example, a particular implementation bug might need to be
4045 worked around in some chip versions.
4047 It's easy to see what target types are supported,
4048 since there's a command to list them.
4049 However, there is currently no way to list what target variants
4050 are supported (other than by reading the OpenOCD source code).
4052 @anchor{targettypes}
4053 @deffn Command {target types}
4054 Lists all supported target types.
4055 At this writing, the supported CPU types and variants are:
4057 @itemize @bullet
4058 @item @code{arm11} -- this is a generation of ARMv6 cores
4059 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4060 @item @code{arm7tdmi} -- this is an ARMv4 core
4061 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4062 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4063 @item @code{arm966e} -- this is an ARMv5 core
4064 @item @code{arm9tdmi} -- this is an ARMv4 core
4065 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4066 (Support for this is preliminary and incomplete.)
4067 @item @code{cortex_a8} -- this is an ARMv7 core with an MMU
4068 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
4069 compact Thumb2 instruction set.
4070 @item @code{dragonite} -- resembles arm966e
4071 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4072 (Support for this is still incomplete.)
4073 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4074 @item @code{feroceon} -- resembles arm926
4075 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
4076 @item @code{xscale} -- this is actually an architecture,
4077 not a CPU type. It is based on the ARMv5 architecture.
4078 There are several variants defined:
4079 @itemize @minus
4080 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
4081 @code{pxa27x} ... instruction register length is 7 bits
4082 @item @code{pxa250}, @code{pxa255},
4083 @code{pxa26x} ... instruction register length is 5 bits
4084 @item @code{pxa3xx} ... instruction register length is 11 bits
4085 @end itemize
4086 @end itemize
4087 @end deffn
4089 To avoid being confused by the variety of ARM based cores, remember
4090 this key point: @emph{ARM is a technology licencing company}.
4091 (See: @url{http://www.arm.com}.)
4092 The CPU name used by OpenOCD will reflect the CPU design that was
4093 licenced, not a vendor brand which incorporates that design.
4094 Name prefixes like arm7, arm9, arm11, and cortex
4095 reflect design generations;
4096 while names like ARMv4, ARMv5, ARMv6, and ARMv7
4097 reflect an architecture version implemented by a CPU design.
4099 @anchor{targetconfiguration}
4100 @section Target Configuration
4102 Before creating a ``target'', you must have added its TAP to the scan chain.
4103 When you've added that TAP, you will have a @code{dotted.name}
4104 which is used to set up the CPU support.
4105 The chip-specific configuration file will normally configure its CPU(s)
4106 right after it adds all of the chip's TAPs to the scan chain.
4108 Although you can set up a target in one step, it's often clearer if you
4109 use shorter commands and do it in two steps: create it, then configure
4110 optional parts.
4111 All operations on the target after it's created will use a new
4112 command, created as part of target creation.
4114 The two main things to configure after target creation are
4115 a work area, which usually has target-specific defaults even
4116 if the board setup code overrides them later;
4117 and event handlers (@pxref{targetevents,,Target Events}), which tend
4118 to be much more board-specific.
4119 The key steps you use might look something like this
4121 @example
4122 target create MyTarget cortex_m3 -chain-position mychip.cpu
4123 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4124 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4125 $MyTarget configure -event reset-init @{ myboard_reinit @}
4126 @end example
4128 You should specify a working area if you can; typically it uses some
4129 on-chip SRAM.
4130 Such a working area can speed up many things, including bulk
4131 writes to target memory;
4132 flash operations like checking to see if memory needs to be erased;
4133 GDB memory checksumming;
4134 and more.
4136 @quotation Warning
4137 On more complex chips, the work area can become
4138 inaccessible when application code
4139 (such as an operating system)
4140 enables or disables the MMU.
4141 For example, the particular MMU context used to acess the virtual
4142 address will probably matter ... and that context might not have
4143 easy access to other addresses needed.
4144 At this writing, OpenOCD doesn't have much MMU intelligence.
4145 @end quotation
4147 It's often very useful to define a @code{reset-init} event handler.
4148 For systems that are normally used with a boot loader,
4149 common tasks include updating clocks and initializing memory
4150 controllers.
4151 That may be needed to let you write the boot loader into flash,
4152 in order to ``de-brick'' your board; or to load programs into
4153 external DDR memory without having run the boot loader.
4155 @deffn Command {target create} target_name type configparams...
4156 This command creates a GDB debug target that refers to a specific JTAG tap.
4157 It enters that target into a list, and creates a new
4158 command (@command{@var{target_name}}) which is used for various
4159 purposes including additional configuration.
4161 @itemize @bullet
4162 @item @var{target_name} ... is the name of the debug target.
4163 By convention this should be the same as the @emph{dotted.name}
4164 of the TAP associated with this target, which must be specified here
4165 using the @code{-chain-position @var{dotted.name}} configparam.
4167 This name is also used to create the target object command,
4168 referred to here as @command{$target_name},
4169 and in other places the target needs to be identified.
4170 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4171 @item @var{configparams} ... all parameters accepted by
4172 @command{$target_name configure} are permitted.
4173 If the target is big-endian, set it here with @code{-endian big}.
4174 If the variant matters, set it here with @code{-variant}.
4176 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
4177 @end itemize
4178 @end deffn
4180 @deffn Command {$target_name configure} configparams...
4181 The options accepted by this command may also be
4182 specified as parameters to @command{target create}.
4183 Their values can later be queried one at a time by
4184 using the @command{$target_name cget} command.
4186 @emph{Warning:} changing some of these after setup is dangerous.
4187 For example, moving a target from one TAP to another;
4188 and changing its endianness or variant.
4190 @itemize @bullet
4192 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4193 used to access this target.
4195 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4196 whether the CPU uses big or little endian conventions
4198 @item @code{-event} @var{event_name} @var{event_body} --
4199 @xref{targetevents,,Target Events}.
4200 Note that this updates a list of named event handlers.
4201 Calling this twice with two different event names assigns
4202 two different handlers, but calling it twice with the
4203 same event name assigns only one handler.
4205 @item @code{-variant} @var{name} -- specifies a variant of the target,
4206 which OpenOCD needs to know about.
4208 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4209 whether the work area gets backed up; by default,
4210 @emph{it is not backed up.}
4211 When possible, use a working_area that doesn't need to be backed up,
4212 since performing a backup slows down operations.
4213 For example, the beginning of an SRAM block is likely to
4214 be used by most build systems, but the end is often unused.
4216 @item @code{-work-area-size} @var{size} -- specify work are size,
4217 in bytes. The same size applies regardless of whether its physical
4218 or virtual address is being used.
4220 @item @code{-work-area-phys} @var{address} -- set the work area
4221 base @var{address} to be used when no MMU is active.
4223 @item @code{-work-area-virt} @var{address} -- set the work area
4224 base @var{address} to be used when an MMU is active.
4225 @emph{Do not specify a value for this except on targets with an MMU.}
4226 The value should normally correspond to a static mapping for the
4227 @code{-work-area-phys} address, set up by the current operating system.
4229 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4230 @var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}|
4231 @option{FreeRTOS}|@option{linux}|@option{ChibiOS}.
4233 @end itemize
4234 @end deffn
4236 @section Other $target_name Commands
4237 @cindex object command
4239 The Tcl/Tk language has the concept of object commands,
4240 and OpenOCD adopts that same model for targets.
4242 A good Tk example is a on screen button.
4243 Once a button is created a button
4244 has a name (a path in Tk terms) and that name is useable as a first
4245 class command. For example in Tk, one can create a button and later
4246 configure it like this:
4248 @example
4249 # Create
4250 button .foobar -background red -command @{ foo @}
4251 # Modify
4252 .foobar configure -foreground blue
4253 # Query
4254 set x [.foobar cget -background]
4255 # Report
4256 puts [format "The button is %s" $x]
4257 @end example
4259 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4260 button, and its object commands are invoked the same way.
4262 @example
4263 str912.cpu mww 0x1234 0x42
4264 omap3530.cpu mww 0x5555 123
4265 @end example
4267 The commands supported by OpenOCD target objects are:
4269 @deffn Command {$target_name arp_examine}
4270 @deffnx Command {$target_name arp_halt}
4271 @deffnx Command {$target_name arp_poll}
4272 @deffnx Command {$target_name arp_reset}
4273 @deffnx Command {$target_name arp_waitstate}
4274 Internal OpenOCD scripts (most notably @file{startup.tcl})
4275 use these to deal with specific reset cases.
4276 They are not otherwise documented here.
4277 @end deffn
4279 @deffn Command {$target_name array2mem} arrayname width address count
4280 @deffnx Command {$target_name mem2array} arrayname width address count
4281 These provide an efficient script-oriented interface to memory.
4282 The @code{array2mem} primitive writes bytes, halfwords, or words;
4283 while @code{mem2array} reads them.
4284 In both cases, the TCL side uses an array, and
4285 the target side uses raw memory.
4287 The efficiency comes from enabling the use of
4288 bulk JTAG data transfer operations.
4289 The script orientation comes from working with data
4290 values that are packaged for use by TCL scripts;
4291 @command{mdw} type primitives only print data they retrieve,
4292 and neither store nor return those values.
4294 @itemize
4295 @item @var{arrayname} ... is the name of an array variable
4296 @item @var{width} ... is 8/16/32 - indicating the memory access size
4297 @item @var{address} ... is the target memory address
4298 @item @var{count} ... is the number of elements to process
4299 @end itemize
4300 @end deffn
4302 @deffn Command {$target_name cget} queryparm
4303 Each configuration parameter accepted by
4304 @command{$target_name configure}
4305 can be individually queried, to return its current value.
4306 The @var{queryparm} is a parameter name
4307 accepted by that command, such as @code{-work-area-phys}.
4308 There are a few special cases:
4310 @itemize @bullet
4311 @item @code{-event} @var{event_name} -- returns the handler for the
4312 event named @var{event_name}.
4313 This is a special case because setting a handler requires
4314 two parameters.
4315 @item @code{-type} -- returns the target type.
4316 This is a special case because this is set using
4317 @command{target create} and can't be changed
4318 using @command{$target_name configure}.
4319 @end itemize
4321 For example, if you wanted to summarize information about
4322 all the targets you might use something like this:
4324 @example
4325 foreach name [target names] @{
4326 set y [$name cget -endian]
4327 set z [$name cget -type]
4328 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4329 $x $name $y $z]
4330 @}
4331 @end example
4332 @end deffn
4334 @anchor{targetcurstate}
4335 @deffn Command {$target_name curstate}
4336 Displays the current target state:
4337 @code{debug-running},
4338 @code{halted},
4339 @code{reset},
4340 @code{running}, or @code{unknown}.
4341 (Also, @pxref{eventpolling,,Event Polling}.)
4342 @end deffn
4344 @deffn Command {$target_name eventlist}
4345 Displays a table listing all event handlers
4346 currently associated with this target.
4347 @xref{targetevents,,Target Events}.
4348 @end deffn
4350 @deffn Command {$target_name invoke-event} event_name
4351 Invokes the handler for the event named @var{event_name}.
4352 (This is primarily intended for use by OpenOCD framework
4353 code, for example by the reset code in @file{startup.tcl}.)
4354 @end deffn
4356 @deffn Command {$target_name mdw} addr [count]
4357 @deffnx Command {$target_name mdh} addr [count]
4358 @deffnx Command {$target_name mdb} addr [count]
4359 Display contents of address @var{addr}, as
4360 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4361 or 8-bit bytes (@command{mdb}).
4362 If @var{count} is specified, displays that many units.
4363 (If you want to manipulate the data instead of displaying it,
4364 see the @code{mem2array} primitives.)
4365 @end deffn
4367 @deffn Command {$target_name mww} addr word
4368 @deffnx Command {$target_name mwh} addr halfword
4369 @deffnx Command {$target_name mwb} addr byte
4370 Writes the specified @var{word} (32 bits),
4371 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4372 at the specified address @var{addr}.
4373 @end deffn
4375 @anchor{targetevents}
4376 @section Target Events
4377 @cindex target events
4378 @cindex events
4379 At various times, certain things can happen, or you want them to happen.
4380 For example:
4381 @itemize @bullet
4382 @item What should happen when GDB connects? Should your target reset?
4383 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4384 @item Is using SRST appropriate (and possible) on your system?
4385 Or instead of that, do you need to issue JTAG commands to trigger reset?
4386 SRST usually resets everything on the scan chain, which can be inappropriate.
4387 @item During reset, do you need to write to certain memory locations
4388 to set up system clocks or
4389 to reconfigure the SDRAM?
4390 How about configuring the watchdog timer, or other peripherals,
4391 to stop running while you hold the core stopped for debugging?
4392 @end itemize
4394 All of the above items can be addressed by target event handlers.
4395 These are set up by @command{$target_name configure -event} or
4396 @command{target create ... -event}.
4398 The programmer's model matches the @code{-command} option used in Tcl/Tk
4399 buttons and events. The two examples below act the same, but one creates
4400 and invokes a small procedure while the other inlines it.
4402 @example
4403 proc my_attach_proc @{ @} @{
4404 echo "Reset..."
4405 reset halt
4406 @}
4407 mychip.cpu configure -event gdb-attach my_attach_proc
4408 mychip.cpu configure -event gdb-attach @{
4409 echo "Reset..."
4410 # To make flash probe and gdb load to flash work we need a reset init.
4411 reset init
4412 @}
4413 @end example
4415 The following target events are defined:
4417 @itemize @bullet
4418 @item @b{debug-halted}
4419 @* The target has halted for debug reasons (i.e.: breakpoint)
4420 @item @b{debug-resumed}
4421 @* The target has resumed (i.e.: gdb said run)
4422 @item @b{early-halted}
4423 @* Occurs early in the halt process
4424 @item @b{examine-start}
4425 @* Before target examine is called.
4426 @item @b{examine-end}
4427 @* After target examine is called with no errors.
4428 @item @b{gdb-attach}
4429 @* When GDB connects. This is before any communication with the target, so this
4430 can be used to set up the target so it is possible to probe flash. Probing flash
4431 is necessary during gdb connect if gdb load is to write the image to flash. Another
4432 use of the flash memory map is for GDB to automatically hardware/software breakpoints
4433 depending on whether the breakpoint is in RAM or read only memory.
4434 @item @b{gdb-detach}
4435 @* When GDB disconnects
4436 @item @b{gdb-end}
4437 @* When the target has halted and GDB is not doing anything (see early halt)
4438 @item @b{gdb-flash-erase-start}
4439 @* Before the GDB flash process tries to erase the flash
4440 @item @b{gdb-flash-erase-end}
4441 @* After the GDB flash process has finished erasing the flash
4442 @item @b{gdb-flash-write-start}
4443 @* Before GDB writes to the flash
4444 @item @b{gdb-flash-write-end}
4445 @* After GDB writes to the flash
4446 @item @b{gdb-start}
4447 @* Before the target steps, gdb is trying to start/resume the target
4448 @item @b{halted}
4449 @* The target has halted
4450 @item @b{reset-assert-pre}
4451 @* Issued as part of @command{reset} processing
4452 after @command{reset_init} was triggered
4453 but before either SRST alone is re-asserted on the scan chain,
4454 or @code{reset-assert} is triggered.
4455 @item @b{reset-assert}
4456 @* Issued as part of @command{reset} processing
4457 after @command{reset-assert-pre} was triggered.
4458 When such a handler is present, cores which support this event will use
4459 it instead of asserting SRST.
4460 This support is essential for debugging with JTAG interfaces which
4461 don't include an SRST line (JTAG doesn't require SRST), and for
4462 selective reset on scan chains that have multiple targets.
4463 @item @b{reset-assert-post}
4464 @* Issued as part of @command{reset} processing
4465 after @code{reset-assert} has been triggered.
4466 or the target asserted SRST on the entire scan chain.
4467 @item @b{reset-deassert-pre}
4468 @* Issued as part of @command{reset} processing
4469 after @code{reset-assert-post} has been triggered.
4470 @item @b{reset-deassert-post}
4471 @* Issued as part of @command{reset} processing
4472 after @code{reset-deassert-pre} has been triggered
4473 and (if the target is using it) after SRST has been
4474 released on the scan chain.
4475 @item @b{reset-end}
4476 @* Issued as the final step in @command{reset} processing.
4477 @ignore
4478 @item @b{reset-halt-post}
4479 @* Currently not used
4480 @item @b{reset-halt-pre}
4481 @* Currently not used
4482 @end ignore
4483 @item @b{reset-init}
4484 @* Used by @b{reset init} command for board-specific initialization.
4485 This event fires after @emph{reset-deassert-post}.
4487 This is where you would configure PLLs and clocking, set up DRAM so
4488 you can download programs that don't fit in on-chip SRAM, set up pin
4489 multiplexing, and so on.
4490 (You may be able to switch to a fast JTAG clock rate here, after
4491 the target clocks are fully set up.)
4492 @item @b{reset-start}
4493 @* Issued as part of @command{reset} processing
4494 before @command{reset_init} is called.
4496 This is the most robust place to use @command{jtag_rclk}
4497 or @command{adapter_khz} to switch to a low JTAG clock rate,
4498 when reset disables PLLs needed to use a fast clock.
4499 @ignore
4500 @item @b{reset-wait-pos}
4501 @* Currently not used
4502 @item @b{reset-wait-pre}
4503 @* Currently not used
4504 @end ignore
4505 @item @b{resume-start}
4506 @* Before any target is resumed
4507 @item @b{resume-end}
4508 @* After all targets have resumed
4509 @item @b{resumed}
4510 @* Target has resumed
4511 @end itemize
4513 @node Flash Commands
4514 @chapter Flash Commands
4516 OpenOCD has different commands for NOR and NAND flash;
4517 the ``flash'' command works with NOR flash, while
4518 the ``nand'' command works with NAND flash.
4519 This partially reflects different hardware technologies:
4520 NOR flash usually supports direct CPU instruction and data bus access,
4521 while data from a NAND flash must be copied to memory before it can be
4522 used. (SPI flash must also be copied to memory before use.)
4523 However, the documentation also uses ``flash'' as a generic term;
4524 for example, ``Put flash configuration in board-specific files''.
4526 Flash Steps:
4527 @enumerate
4528 @item Configure via the command @command{flash bank}
4529 @* Do this in a board-specific configuration file,
4530 passing parameters as needed by the driver.
4531 @item Operate on the flash via @command{flash subcommand}
4532 @* Often commands to manipulate the flash are typed by a human, or run
4533 via a script in some automated way. Common tasks include writing a
4534 boot loader, operating system, or other data.
4535 @item GDB Flashing
4536 @* Flashing via GDB requires the flash be configured via ``flash
4537 bank'', and the GDB flash features be enabled.
4538 @xref{gdbconfiguration,,GDB Configuration}.
4539 @end enumerate
4541 Many CPUs have the ablity to ``boot'' from the first flash bank.
4542 This means that misprogramming that bank can ``brick'' a system,
4543 so that it can't boot.
4544 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4545 board by (re)installing working boot firmware.
4547 @anchor{norconfiguration}
4548 @section Flash Configuration Commands
4549 @cindex flash configuration
4551 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4552 Configures a flash bank which provides persistent storage
4553 for addresses from @math{base} to @math{base + size - 1}.
4554 These banks will often be visible to GDB through the target's memory map.
4555 In some cases, configuring a flash bank will activate extra commands;
4556 see the driver-specific documentation.
4558 @itemize @bullet
4559 @item @var{name} ... may be used to reference the flash bank
4560 in other flash commands. A number is also available.
4561 @item @var{driver} ... identifies the controller driver
4562 associated with the flash bank being declared.
4563 This is usually @code{cfi} for external flash, or else
4564 the name of a microcontroller with embedded flash memory.
4565 @xref{flashdriverlist,,Flash Driver List}.
4566 @item @var{base} ... Base address of the flash chip.
4567 @item @var{size} ... Size of the chip, in bytes.
4568 For some drivers, this value is detected from the hardware.
4569 @item @var{chip_width} ... Width of the flash chip, in bytes;
4570 ignored for most microcontroller drivers.
4571 @item @var{bus_width} ... Width of the data bus used to access the
4572 chip, in bytes; ignored for most microcontroller drivers.
4573 @item @var{target} ... Names the target used to issue
4574 commands to the flash controller.
4575 @comment Actually, it's currently a controller-specific parameter...
4576 @item @var{driver_options} ... drivers may support, or require,
4577 additional parameters. See the driver-specific documentation
4578 for more information.
4579 @end itemize
4580 @quotation Note
4581 This command is not available after OpenOCD initialization has completed.
4582 Use it in board specific configuration files, not interactively.
4583 @end quotation
4584 @end deffn
4586 @comment the REAL name for this command is "ocd_flash_banks"
4587 @comment less confusing would be: "flash list" (like "nand list")
4588 @deffn Command {flash banks}
4589 Prints a one-line summary of each device that was
4590 declared using @command{flash bank}, numbered from zero.
4591 Note that this is the @emph{plural} form;
4592 the @emph{singular} form is a very different command.
4593 @end deffn
4595 @deffn Command {flash list}
4596 Retrieves a list of associative arrays for each device that was
4597 declared using @command{flash bank}, numbered from zero.
4598 This returned list can be manipulated easily from within scripts.
4599 @end deffn
4601 @deffn Command {flash probe} num
4602 Identify the flash, or validate the parameters of the configured flash. Operation
4603 depends on the flash type.
4604 The @var{num} parameter is a value shown by @command{flash banks}.
4605 Most flash commands will implicitly @emph{autoprobe} the bank;
4606 flash drivers can distinguish between probing and autoprobing,
4607 but most don't bother.
4608 @end deffn
4610 @section Erasing, Reading, Writing to Flash
4611 @cindex flash erasing
4612 @cindex flash reading
4613 @cindex flash writing
4614 @cindex flash programming
4615 @anchor{flashprogrammingcommands}
4617 One feature distinguishing NOR flash from NAND or serial flash technologies
4618 is that for read access, it acts exactly like any other addressible memory.
4619 This means you can use normal memory read commands like @command{mdw} or
4620 @command{dump_image} with it, with no special @command{flash} subcommands.
4621 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
4623 Write access works differently. Flash memory normally needs to be erased
4624 before it's written. Erasing a sector turns all of its bits to ones, and
4625 writing can turn ones into zeroes. This is why there are special commands
4626 for interactive erasing and writing, and why GDB needs to know which parts
4627 of the address space hold NOR flash memory.
4629 @quotation Note
4630 Most of these erase and write commands leverage the fact that NOR flash
4631 chips consume target address space. They implicitly refer to the current
4632 JTAG target, and map from an address in that target's address space
4633 back to a flash bank.
4634 @comment In May 2009, those mappings may fail if any bank associated
4635 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
4636 A few commands use abstract addressing based on bank and sector numbers,
4637 and don't depend on searching the current target and its address space.
4638 Avoid confusing the two command models.
4639 @end quotation
4641 Some flash chips implement software protection against accidental writes,
4642 since such buggy writes could in some cases ``brick'' a system.
4643 For such systems, erasing and writing may require sector protection to be
4644 disabled first.
4645 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4646 and AT91SAM7 on-chip flash.
4647 @xref{flashprotect,,flash protect}.
4649 @deffn Command {flash erase_sector} num first last
4650 Erase sectors in bank @var{num}, starting at sector @var{first}
4651 up to and including @var{last}.
4652 Sector numbering starts at 0.
4653 Providing a @var{last} sector of @option{last}
4654 specifies "to the end of the flash bank".
4655 The @var{num} parameter is a value shown by @command{flash banks}.
4656 @end deffn
4658 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4659 Erase sectors starting at @var{address} for @var{length} bytes.
4660 Unless @option{pad} is specified, @math{address} must begin a
4661 flash sector, and @math{address + length - 1} must end a sector.
4662 Specifying @option{pad} erases extra data at the beginning and/or
4663 end of the specified region, as needed to erase only full sectors.
4664 The flash bank to use is inferred from the @var{address}, and
4665 the specified length must stay within that bank.
4666 As a special case, when @var{length} is zero and @var{address} is
4667 the start of the bank, the whole flash is erased.
4668 If @option{unlock} is specified, then the flash is unprotected
4669 before erase starts.
4670 @end deffn
4672 @deffn Command {flash fillw} address word length
4673 @deffnx Command {flash fillh} address halfword length
4674 @deffnx Command {flash fillb} address byte length
4675 Fills flash memory with the specified @var{word} (32 bits),
4676 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4677 starting at @var{address} and continuing
4678 for @var{length} units (word/halfword/byte).
4679 No erasure is done before writing; when needed, that must be done
4680 before issuing this command.
4681 Writes are done in blocks of up to 1024 bytes, and each write is
4682 verified by reading back the data and comparing it to what was written.
4683 The flash bank to use is inferred from the @var{address} of
4684 each block, and the specified length must stay within that bank.
4685 @end deffn
4686 @comment no current checks for errors if fill blocks touch multiple banks!
4688 @deffn Command {flash write_bank} num filename offset
4689 Write the binary @file{filename} to flash bank @var{num},
4690 starting at @var{offset} bytes from the beginning of the bank.
4691 The @var{num} parameter is a value shown by @command{flash banks}.
4692 @end deffn
4694 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4695 Write the image @file{filename} to the current target's flash bank(s).
4696 A relocation @var{offset} may be specified, in which case it is added
4697 to the base address for each section in the image.
4698 The file [@var{type}] can be specified
4699 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4700 @option{elf} (ELF file), @option{s19} (Motorola s19).
4701 @option{mem}, or @option{builder}.
4702 The relevant flash sectors will be erased prior to programming
4703 if the @option{erase} parameter is given. If @option{unlock} is
4704 provided, then the flash banks are unlocked before erase and
4705 program. The flash bank to use is inferred from the address of
4706 each image section.
4708 @quotation Warning
4709 Be careful using the @option{erase} flag when the flash is holding
4710 data you want to preserve.
4711 Portions of the flash outside those described in the image's
4712 sections might be erased with no notice.
4713 @itemize
4714 @item
4715 When a section of the image being written does not fill out all the
4716 sectors it uses, the unwritten parts of those sectors are necessarily
4717 also erased, because sectors can't be partially erased.
4718 @item
4719 Data stored in sector "holes" between image sections are also affected.
4720 For example, "@command{flash write_image erase ...}" of an image with
4721 one byte at the beginning of a flash bank and one byte at the end
4722 erases the entire bank -- not just the two sectors being written.
4723 @end itemize
4724 Also, when flash protection is important, you must re-apply it after
4725 it has been removed by the @option{unlock} flag.
4726 @end quotation
4728 @end deffn
4730 @section Other Flash commands
4731 @cindex flash protection
4733 @deffn Command {flash erase_check} num
4734 Check erase state of sectors in flash bank @var{num},
4735 and display that status.
4736 The @var{num} parameter is a value shown by @command{flash banks}.
4737 @end deffn
4739 @deffn Command {flash info} num
4740 Print info about flash bank @var{num}
4741 The @var{num} parameter is a value shown by @command{flash banks}.
4742 This command will first query the hardware, it does not print cached
4743 and possibly stale information.
4744 @end deffn
4746 @anchor{flashprotect}
4747 @deffn Command {flash protect} num first last (@option{on}|@option{off})
4748 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
4749 in flash bank @var{num}, starting at sector @var{first}
4750 and continuing up to and including @var{last}.
4751 Providing a @var{last} sector of @option{last}
4752 specifies "to the end of the flash bank".
4753 The @var{num} parameter is a value shown by @command{flash banks}.
4754 @end deffn
4756 @anchor{program}
4757 @deffn Command {program} filename [verify] [reset] [offset]
4758 This is a helper script that simplifies using OpenOCD as a standalone
4759 programmer. The only required parameter is @option{filename}, the others are optional.
4760 @xref{Flash Programming}.
4761 @end deffn
4763 @anchor{flashdriverlist}
4764 @section Flash Driver List
4765 As noted above, the @command{flash bank} command requires a driver name,
4766 and allows driver-specific options and behaviors.
4767 Some drivers also activate driver-specific commands.
4769 @subsection External Flash
4771 @deffn {Flash Driver} cfi
4772 @cindex Common Flash Interface
4773 @cindex CFI
4774 The ``Common Flash Interface'' (CFI) is the main standard for
4775 external NOR flash chips, each of which connects to a
4776 specific external chip select on the CPU.
4777 Frequently the first such chip is used to boot the system.
4778 Your board's @code{reset-init} handler might need to
4779 configure additional chip selects using other commands (like: @command{mww} to
4780 configure a bus and its timings), or
4781 perhaps configure a GPIO pin that controls the ``write protect'' pin
4782 on the flash chip.
4783 The CFI driver can use a target-specific working area to significantly
4784 speed up operation.
4786 The CFI driver can accept the following optional parameters, in any order:
4788 @itemize
4789 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
4790 like AM29LV010 and similar types.
4791 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
4792 @end itemize
4794 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
4795 wide on a sixteen bit bus:
4797 @example
4798 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
4799 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
4800 @end example
4802 To configure one bank of 32 MBytes
4803 built from two sixteen bit (two byte) wide parts wired in parallel
4804 to create a thirty-two bit (four byte) bus with doubled throughput:
4806 @example
4807 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
4808 @end example
4810 @c "cfi part_id" disabled
4811 @end deffn
4813 @deffn {Flash Driver} lpcspifi
4814 @cindex NXP SPI Flash Interface
4815 @cindex SPIFI
4816 @cindex lpcspifi
4817 NXP's LPC43xx and LPC18xx families include a proprietary SPI
4818 Flash Interface (SPIFI) peripheral that can drive and provide
4819 memory mapped access to external SPI flash devices.
4821 The lpcspifi driver initializes this interface and provides
4822 program and erase functionality for these serial flash devices.
4823 Use of this driver @b{requires} a working area of at least 1kB
4824 to be configured on the target device; more than this will
4825 significantly reduce flash programming times.
4827 The setup command only requires the @var{base} parameter. All
4828 other parameters are ignored, and the flash size and layout
4829 are configured by the driver.
4831 @example
4832 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
4833 @end example
4835 @end deffn
4837 @deffn {Flash Driver} stmsmi
4838 @cindex STMicroelectronics Serial Memory Interface
4839 @cindex SMI
4840 @cindex stmsmi
4841 Some devices form STMicroelectronics (e.g. STR75x MCU family,
4842 SPEAr MPU family) include a proprietary
4843 ``Serial Memory Interface'' (SMI) controller able to drive external
4844 SPI flash devices.
4845 Depending on specific device and board configuration, up to 4 external
4846 flash devices can be connected.
4848 SMI makes the flash content directly accessible in the CPU address
4849 space; each external device is mapped in a memory bank.
4850 CPU can directly read data, execute code and boot from SMI banks.
4851 Normal OpenOCD commands like @command{mdw} can be used to display
4852 the flash content.
4854 The setup command only requires the @var{base} parameter in order
4855 to identify the memory bank.
4856 All other parameters are ignored. Additional information, like
4857 flash size, are detected automatically.
4859 @example
4860 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
4861 @end example
4863 @end deffn
4865 @subsection Internal Flash (Microcontrollers)
4867 @deffn {Flash Driver} aduc702x
4868 The ADUC702x analog microcontrollers from Analog Devices
4869 include internal flash and use ARM7TDMI cores.
4870 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
4871 The setup command only requires the @var{target} argument
4872 since all devices in this family have the same memory layout.
4874 @example
4875 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
4876 @end example
4877 @end deffn
4879 @anchor{at91sam3}
4880 @deffn {Flash Driver} at91sam3
4881 @cindex at91sam3
4882 All members of the AT91SAM3 microcontroller family from
4883 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
4884 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
4885 that the driver was orginaly developed and tested using the
4886 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
4887 the family was cribbed from the data sheet. @emph{Note to future
4888 readers/updaters: Please remove this worrysome comment after other
4889 chips are confirmed.}
4891 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
4892 have one flash bank. In all cases the flash banks are at
4893 the following fixed locations:
4895 @example
4896 # Flash bank 0 - all chips
4897 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
4898 # Flash bank 1 - only 256K chips
4899 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
4900 @end example
4902 Internally, the AT91SAM3 flash memory is organized as follows.
4903 Unlike the AT91SAM7 chips, these are not used as parameters
4904 to the @command{flash bank} command:
4906 @itemize
4907 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
4908 @item @emph{Bank Size:} 128K/64K Per flash bank
4909 @item @emph{Sectors:} 16 or 8 per bank
4910 @item @emph{SectorSize:} 8K Per Sector
4911 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
4912 @end itemize
4914 The AT91SAM3 driver adds some additional commands:
4916 @deffn Command {at91sam3 gpnvm}
4917 @deffnx Command {at91sam3 gpnvm clear} number
4918 @deffnx Command {at91sam3 gpnvm set} number
4919 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
4920 With no parameters, @command{show} or @command{show all},
4921 shows the status of all GPNVM bits.
4922 With @command{show} @var{number}, displays that bit.
4924 With @command{set} @var{number} or @command{clear} @var{number},
4925 modifies that GPNVM bit.
4926 @end deffn
4928 @deffn Command {at91sam3 info}
4929 This command attempts to display information about the AT91SAM3
4930 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
4931 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
4932 document id: doc6430A] and decodes the values. @emph{Second} it reads the
4933 various clock configuration registers and attempts to display how it
4934 believes the chip is configured. By default, the SLOWCLK is assumed to
4935 be 32768 Hz, see the command @command{at91sam3 slowclk}.
4936 @end deffn
4938 @deffn Command {at91sam3 slowclk} [value]
4939 This command shows/sets the slow clock frequency used in the
4940 @command{at91sam3 info} command calculations above.
4941 @end deffn
4942 @end deffn
4944 @deffn {Flash Driver} at91sam4
4945 @cindex at91sam4
4946 All members of the AT91SAM4 microcontroller family from
4947 Atmel include internal flash and use ARM's Cortex-M4 core.
4948 This driver uses the same cmd names/syntax as @xref{at91sam3}.
4949 @end deffn
4951 @deffn {Flash Driver} at91sam7
4952 All members of the AT91SAM7 microcontroller family from Atmel include
4953 internal flash and use ARM7TDMI cores. The driver automatically
4954 recognizes a number of these chips using the chip identification
4955 register, and autoconfigures itself.
4957 @example
4958 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
4959 @end example
4961 For chips which are not recognized by the controller driver, you must
4962 provide additional parameters in the following order:
4964 @itemize
4965 @item @var{chip_model} ... label used with @command{flash info}
4966 @item @var{banks}
4967 @item @var{sectors_per_bank}
4968 @item @var{pages_per_sector}
4969 @item @var{pages_size}
4970 @item @var{num_nvm_bits}
4971 @item @var{freq_khz} ... required if an external clock is provided,
4972 optional (but recommended) when the oscillator frequency is known
4973 @end itemize
4975 It is recommended that you provide zeroes for all of those values
4976 except the clock frequency, so that everything except that frequency
4977 will be autoconfigured.
4978 Knowing the frequency helps ensure correct timings for flash access.
4980 The flash controller handles erases automatically on a page (128/256 byte)
4981 basis, so explicit erase commands are not necessary for flash programming.
4982 However, there is an ``EraseAll`` command that can erase an entire flash
4983 plane (of up to 256KB), and it will be used automatically when you issue
4984 @command{flash erase_sector} or @command{flash erase_address} commands.
4986 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
4987 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
4988 bit for the processor. Each processor has a number of such bits,
4989 used for controlling features such as brownout detection (so they
4990 are not truly general purpose).
4991 @quotation Note
4992 This assumes that the first flash bank (number 0) is associated with
4993 the appropriate at91sam7 target.
4994 @end quotation
4995 @end deffn
4996 @end deffn
4998 @deffn {Flash Driver} avr
4999 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
5000 @emph{The current implementation is incomplete.}
5001 @comment - defines mass_erase ... pointless given flash_erase_address
5002 @end deffn
5004 @deffn {Flash Driver} efm32
5005 All members of the EFM32 microcontroller family from Energy Micro include
5006 internal flash and use ARM Cortex M3 cores. The driver automatically recognizes
5007 a number of these chips using the chip identification register, and
5008 autoconfigures itself.
5009 @example
5010 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
5011 @end example
5012 @emph{The current implementation is incomplete. Unprotecting flash pages is not
5013 supported.}
5014 @end deffn
5016 @deffn {Flash Driver} lpc2000
5017 Most members of the LPC1700 and LPC2000 microcontroller families from NXP
5018 include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
5020 @quotation Note
5021 There are LPC2000 devices which are not supported by the @var{lpc2000}
5022 driver:
5023 The LPC2888 is supported by the @var{lpc288x} driver.
5024 The LPC29xx family is supported by the @var{lpc2900} driver.
5025 @end quotation
5027 The @var{lpc2000} driver defines two mandatory and one optional parameters,
5028 which must appear in the following order:
5030 @itemize
5031 @item @var{variant} ... required, may be
5032 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
5033 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
5034 or @option{lpc1700} (LPC175x and LPC176x)
5035 @item @var{clock_kHz} ... the frequency, in kiloHertz,
5036 at which the core is running
5037 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
5038 telling the driver to calculate a valid checksum for the exception vector table.
5039 @quotation Note
5040 If you don't provide @option{calc_checksum} when you're writing the vector
5041 table, the boot ROM will almost certainly ignore your flash image.
5042 However, if you do provide it,
5043 with most tool chains @command{verify_image} will fail.
5044 @end quotation
5045 @end itemize
5047 LPC flashes don't require the chip and bus width to be specified.
5049 @example
5050 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
5051 lpc2000_v2 14765 calc_checksum
5052 @end example
5054 @deffn {Command} {lpc2000 part_id} bank
5055 Displays the four byte part identifier associated with
5056 the specified flash @var{bank}.
5057 @end deffn
5058 @end deffn
5060 @deffn {Flash Driver} lpc288x
5061 The LPC2888 microcontroller from NXP needs slightly different flash
5062 support from its lpc2000 siblings.
5063 The @var{lpc288x} driver defines one mandatory parameter,
5064 the programming clock rate in Hz.
5065 LPC flashes don't require the chip and bus width to be specified.
5067 @example
5068 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
5069 @end example
5070 @end deffn