Numerous pedantic fixes to the User's Guide, including typo fixes,
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * NAND Flash Commands:: NAND Flash Commands
77 * PLD/FPGA Commands:: PLD/FPGA Commands
78 * General Commands:: General Commands
79 * Architecture and Core Commands:: Architecture and Core Commands
80 * JTAG Commands:: JTAG Commands
81 * Boundary Scan Commands:: Boundary Scan Commands
82 * Utility Commands:: Utility Commands
83 * TFTP:: TFTP
84 * GDB and OpenOCD:: Using GDB and OpenOCD
85 * Tcl Scripting API:: Tcl Scripting API
86 * FAQ:: Frequently Asked Questions
87 * Tcl Crash Course:: Tcl Crash Course
88 * License:: GNU Free Documentation License
90 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
91 @comment case issue with ``Index.html'' and ``index.html''
92 @comment Occurs when creating ``--html --no-split'' output
93 @comment This fix is based on:
94 * OpenOCD Concept Index:: Concept Index
95 * Command and Driver Index:: Command and Driver Index
96 @end menu
98 @node About
99 @unnumbered About
100 @cindex about
102 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
103 at the University of Applied Sciences Augsburg (@uref{}).
104 Since that time, the project has grown into an active open-source project,
105 supported by a diverse community of software and hardware developers from
106 around the world.
108 @section What is OpenOCD?
109 @cindex TAP
110 @cindex JTAG
112 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
113 in-system programming and boundary-scan testing for embedded target
114 devices.
116 It does so with the assistance of a @dfn{debug adapter}, which is
117 a small hardware module which helps provide the right kind of
118 electrical signaling to the target being debugged. These are
119 required since the debug host (on which OpenOCD runs) won't
120 usually have native support for such signaling, or the connector
121 needed to hook up to the target.
123 Such debug adapters support one or more @dfn{transport} protocols,
124 each of which involves different electrical signaling (and uses
125 different messaging protocols on top of that signaling). There
126 are many types of debug adapter, and little uniformity in what
127 they are called. (There are also product naming differences.)
129 These adapters are sometimes packaged as discrete dongles, which
130 may generically be called @dfn{hardware interface dongles}.
131 Some development boards also integrate them directly, which may
132 let the development board connect directly to the debug
133 host over USB (and sometimes also to power it over USB).
135 For example, a @dfn{JTAG Adapter} supports JTAG
136 signaling, and is used to communicate
137 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
138 A @dfn{TAP} is a ``Test Access Port'', a module which processes
139 special instructions and data. TAPs are daisy-chained within and
140 between chips and boards. JTAG supports debugging and boundary
141 scan operations.
143 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
144 signaling to communicate with some newer ARM cores, as well as debug
145 adapters which support both JTAG and SWD transports. SWD supports only
146 debugging, whereas JTAG also supports boundary scan operations.
148 For some chips, there are also @dfn{Programming Adapters} supporting
149 special transports used only to write code to flash memory, without
150 support for on-chip debugging or boundary scan.
151 (At this writing, OpenOCD does not support such non-debug adapters.)
154 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
155 USB-based, parallel port-based, and other standalone boxes that run
156 OpenOCD internally. @xref{Debug Adapter Hardware}.
158 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
159 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
160 Cortex-M3 (Stellaris LM3, ST STM32 and Energy Micro EFM32) based cores to be
161 debugged via the GDB protocol.
163 @b{Flash Programming:} Flash writing is supported for external
164 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
165 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
166 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
167 controllers (LPC3180, Orion, S3C24xx, more) is included.
169 @section OpenOCD Web Site
171 The OpenOCD web site provides the latest public news from the community:
173 @uref{}
175 @section Latest User's Guide:
177 The user's guide you are now reading may not be the latest one
178 available. A version for more recent code may be available.
179 Its HTML form is published regularly at:
181 @uref{}
183 PDF form is likewise published at:
185 @uref{}
187 @section OpenOCD User's Forum
189 There is an OpenOCD forum (phpBB) hosted by SparkFun,
190 which might be helpful to you. Note that if you want
191 anything to come to the attention of developers, you
192 should post it to the OpenOCD Developer Mailing List
193 instead of this forum.
195 @uref{}
197 @section OpenOCD User's Mailing List
199 The OpenOCD User Mailing List provides the primary means of
200 communication between users:
202 @uref{}
204 @section OpenOCD IRC
206 Support can also be found on irc:
207 @uref{irc://}
209 @node Developers
210 @chapter OpenOCD Developer Resources
211 @cindex developers
213 If you are interested in improving the state of OpenOCD's debugging and
214 testing support, new contributions will be welcome. Motivated developers
215 can produce new target, flash or interface drivers, improve the
216 documentation, as well as more conventional bug fixes and enhancements.
218 The resources in this chapter are available for developers wishing to explore
219 or expand the OpenOCD source code.
221 @section OpenOCD Git Repository
223 During the 0.3.x release cycle, OpenOCD switched from Subversion to
224 a Git repository hosted at SourceForge. The repository URL is:
226 @uref{git://}
228 or via http
230 @uref{}
232 You may prefer to use a mirror and the HTTP protocol:
234 @uref{}
236 With standard Git tools, use @command{git clone} to initialize
237 a local repository, and @command{git pull} to update it.
238 There are also gitweb pages letting you browse the repository
239 with a web browser, or download arbitrary snapshots without
240 needing a Git client:
242 @uref{}
244 The @file{README} file contains the instructions for building the project
245 from the repository or a snapshot.
247 Developers that want to contribute patches to the OpenOCD system are
248 @b{strongly} encouraged to work against mainline.
249 Patches created against older versions may require additional
250 work from their submitter in order to be updated for newer releases.
252 @section Doxygen Developer Manual
254 During the 0.2.x release cycle, the OpenOCD project began
255 providing a Doxygen reference manual. This document contains more
256 technical information about the software internals, development
257 processes, and similar documentation:
259 @uref{}
261 This document is a work-in-progress, but contributions would be welcome
262 to fill in the gaps. All of the source files are provided in-tree,
263 listed in the Doxyfile configuration at the top of the source tree.
265 @section OpenOCD Developer Mailing List
267 The OpenOCD Developer Mailing List provides the primary means of
268 communication between developers:
270 @uref{}
272 Discuss and submit patches to this list.
273 The @file{HACKING} file contains basic information about how
274 to prepare patches.
276 @section OpenOCD Bug Database
278 During the 0.4.x release cycle the OpenOCD project team began
279 using Trac for its bug database:
281 @uref{}
284 @node Debug Adapter Hardware
285 @chapter Debug Adapter Hardware
286 @cindex dongles
287 @cindex FTDI
288 @cindex wiggler
289 @cindex zy1000
290 @cindex printer port
291 @cindex USB Adapter
292 @cindex RTCK
294 Defined: @b{dongle}: A small device that plugs into a computer and serves as
295 an adapter .... [snip]
297 In the OpenOCD case, this generally refers to @b{a small adapter} that
298 attaches to your computer via USB or the parallel port. One
299 exception is the Ultimate Solutions ZY1000, packaged as a small box you
300 attach via an ethernet cable. The ZY1000 has the advantage that it does not
301 require any drivers to be installed on the developer PC. It also has
302 a built in web interface. It supports RTCK/RCLK or adaptive clocking
303 and has a built-in relay to power cycle targets remotely.
306 @section Choosing a Dongle
308 There are several things you should keep in mind when choosing a dongle.
310 @enumerate
311 @item @b{Transport} Does it support the kind of communication that you need?
312 OpenOCD focusses mostly on JTAG. Your version may also support
313 other ways to communicate with target devices.
314 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
315 Does your dongle support it? You might need a level converter.
316 @item @b{Pinout} What pinout does your target board use?
317 Does your dongle support it? You may be able to use jumper
318 wires, or an "octopus" connector, to convert pinouts.
319 @item @b{Connection} Does your computer have the USB, parallel, or
320 Ethernet port needed?
321 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
322 RTCK support (also known as ``adaptive clocking'')?
323 @end enumerate
325 @section Stand-alone JTAG Probe
327 The ZY1000 from Ultimate Solutions is technically not a dongle but a
328 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
329 running on the developer's host computer.
330 Once installed on a network using DHCP or a static IP assignment, users can
331 access the ZY1000 probe locally or remotely from any host with access to the
332 IP address assigned to the probe.
333 The ZY1000 provides an intuitive web interface with direct access to the
334 OpenOCD debugger.
335 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
336 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
337 the target.
338 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
339 to power cycle the target remotely.
341 For more information, visit:
343 @b{ZY1000} See: @url{}
345 @section USB FT2232 Based
347 There are many USB JTAG dongles on the market, many of them based
348 on a chip from ``Future Technology Devices International'' (FTDI)
349 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
350 See: @url{} for more information.
351 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
352 chips started to become available in JTAG adapters. Around 2012, a new
353 variant appeared - FT232H - this is a single-channel version of FT2232H.
354 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
355 clocking.)
357 The FT2232 chips are flexible enough to support some other
358 transport options, such as SWD or the SPI variants used to
359 program some chips. They have two communications channels,
360 and one can be used for a UART adapter at the same time the
361 other one is used to provide a debug adapter.
363 Also, some development boards integrate an FT2232 chip to serve as
364 a built-in low-cost debug adapter and USB-to-serial solution.
366 @itemize @bullet
367 @item @b{usbjtag}
368 @* Link @url{}
369 @item @b{jtagkey}
370 @* See: @url{}
371 @item @b{jtagkey2}
372 @* See: @url{}
373 @item @b{oocdlink}
374 @* See: @url{} By Joern Kaipf
375 @item @b{signalyzer}
376 @* See: @url{}
377 @item @b{Stellaris Eval Boards}
378 @* See: @url{} - The Stellaris eval boards
379 bundle FT2232-based JTAG and SWD support, which can be used to debug
380 the Stellaris chips. Using separate JTAG adapters is optional.
381 These boards can also be used in a "pass through" mode as JTAG adapters
382 to other target boards, disabling the Stellaris chip.
383 @item @b{TI/Luminary ICDI}
384 @* See: @url{} - TI/Luminary In-Circuit Debug
385 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
386 Evaluation Kits. Like the non-detachable FT2232 support on the other
387 Stellaris eval boards, they can be used to debug other target boards.
388 @item @b{olimex-jtag}
389 @* See: @url{}
390 @item @b{Flyswatter/Flyswatter2}
391 @* See: @url{}
392 @item @b{turtelizer2}
393 @* See:
394 @uref{, Turtelizer 2}, or
395 @url{}
396 @item @b{comstick}
397 @* Link: @url{}
398 @item @b{stm32stick}
399 @* Link @url{}
400 @item @b{axm0432_jtag}
401 @* Axiom AXM-0432 Link @url{} - NOTE: This JTAG does not appear
402 to be available anymore as of April 2012.
403 @item @b{cortino}
404 @* Link @url{}
405 @item @b{dlp-usb1232h}
406 @* Link @url{}
407 @item @b{digilent-hs1}
408 @* Link @url{}
409 @item @b{opendous}
410 @* Link @url{} FT2232H-based
411 (OpenHardware).
412 @item @b{JTAG-lock-pick Tiny 2}
413 @* Link @url{} FT232H-based
415 @item @b{GW16042}
416 @* Link: @url{}
417 FT2232H-based
419 @end itemize
420 @section USB-JTAG / Altera USB-Blaster compatibles
422 These devices also show up as FTDI devices, but are not
423 protocol-compatible with the FT2232 devices. They are, however,
424 protocol-compatible among themselves. USB-JTAG devices typically consist
425 of a FT245 followed by a CPLD that understands a particular protocol,
426 or emulates this protocol using some other hardware.
428 They may appear under different USB VID/PID depending on the particular
429 product. The driver can be configured to search for any VID/PID pair
430 (see the section on driver commands).
432 @itemize
433 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
434 @* Link: @url{}
435 @item @b{Altera USB-Blaster}
436 @* Link: @url{}
437 @end itemize
439 @section USB JLINK based
440 There are several OEM versions of the Segger @b{JLINK} adapter. It is
441 an example of a micro controller based JTAG adapter, it uses an
442 AT91SAM764 internally.
444 @itemize @bullet
445 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
446 @* Link: @url{}
447 @item @b{SEGGER JLINK}
448 @* Link: @url{}
449 @item @b{IAR J-Link}
450 @* Link: @url{}
451 @end itemize
453 @section USB RLINK based
454 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
455 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
456 SWD and not JTAG, thus not supported.
458 @itemize @bullet
459 @item @b{Raisonance RLink}
460 @* Link: @url{}
461 @item @b{STM32 Primer}
462 @* Link: @url{}
463 @item @b{STM32 Primer2}
464 @* Link: @url{}
465 @end itemize
467 @section USB ST-LINK based
468 ST Micro has an adapter called @b{ST-LINK}.
469 They only work with ST Micro chips, notably STM32 and STM8.
471 @itemize @bullet
472 @item @b{ST-LINK}
473 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
474 @* Link: @url{}
475 @item @b{ST-LINK/V2}
476 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
477 @* Link: @url{}
478 @end itemize
480 For info the original ST-LINK enumerates using the mass storage usb class; however,
481 its implementation is completely broken. The result is this causes issues under Linux.
482 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
483 @itemize @bullet
484 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
485 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
486 @end itemize
488 @section USB TI/Stellaris ICDI based
489 Texas Instruments has an adapter called @b{ICDI}.
490 It is not to be confused with the FTDI based adapters that were originally fitted to their
491 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
493 @section USB Other
494 @itemize @bullet
495 @item @b{USBprog}
496 @* Link: @url{} - which uses an Atmel MEGA32 and a UBN9604
498 @item @b{USB - Presto}
499 @* Link: @url{}
501 @item @b{Versaloon-Link}
502 @* Link: @url{}
504 @item @b{ARM-JTAG-EW}
505 @* Link: @url{}
507 @item @b{Buspirate}
508 @* Link: @url{}
510 @item @b{opendous}
511 @* Link: @url{} - which uses an AT90USB162
513 @item @b{estick}
514 @* Link: @url{}
516 @item @b{Keil ULINK v1}
517 @* Link: @url{}
518 @end itemize
520 @section IBM PC Parallel Printer Port Based
522 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
523 and the Macraigor Wiggler. There are many clones and variations of
524 these on the market.
526 Note that parallel ports are becoming much less common, so if you
527 have the choice you should probably avoid these adapters in favor
528 of USB-based ones.
530 @itemize @bullet
532 @item @b{Wiggler} - There are many clones of this.
533 @* Link: @url{}
535 @item @b{DLC5} - From XILINX - There are many clones of this
536 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
537 produced, PDF schematics are easily found and it is easy to make.
539 @item @b{Amontec - JTAG Accelerator}
540 @* Link: @url{}
542 @item @b{Wiggler2}
543 @* Link: @url{}
545 @item @b{Wiggler_ntrst_inverted}
546 @* Yet another variation - See the source code, src/jtag/parport.c
548 @item @b{old_amt_wiggler}
549 @* Unknown - probably not on the market today
551 @item @b{arm-jtag}
552 @* Link: Most likely @url{} [another wiggler clone]
554 @item @b{chameleon}
555 @* Link: @url{}
557 @item @b{Triton}
558 @* Unknown.
560 @item @b{Lattice}
561 @* ispDownload from Lattice Semiconductor
562 @url{}
564 @item @b{flashlink}
565 @* From ST Microsystems;
566 @* Link: @url{}
568 @end itemize
570 @section Other...
571 @itemize @bullet
573 @item @b{ep93xx}
574 @* An EP93xx based Linux machine using the GPIO pins directly.
576 @item @b{at91rm9200}
577 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
579 @item @b{bcm2835gpio}
580 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
582 @item @b{jtag_vpi}
583 @* A JTAG driver acting as a client for the JTAG VPI server interface.
584 @* Link: @url{}
586 @end itemize
588 @node About Jim-Tcl
589 @chapter About Jim-Tcl
590 @cindex Jim-Tcl
591 @cindex tcl
593 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
594 This programming language provides a simple and extensible
595 command interpreter.
597 All commands presented in this Guide are extensions to Jim-Tcl.
598 You can use them as simple commands, without needing to learn
599 much of anything about Tcl.
600 Alternatively, you can write Tcl programs with them.
602 You can learn more about Jim at its website, @url{}.
603 There is an active and responsive community, get on the mailing list
604 if you have any questions. Jim-Tcl maintainers also lurk on the
605 OpenOCD mailing list.
607 @itemize @bullet
608 @item @b{Jim vs. Tcl}
609 @* Jim-Tcl is a stripped down version of the well known Tcl language,
610 which can be found here: @url{}. Jim-Tcl has far
611 fewer features. Jim-Tcl is several dozens of .C files and .H files and
612 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
613 4.2 MB .zip file containing 1540 files.
615 @item @b{Missing Features}
616 @* Our practice has been: Add/clone the real Tcl feature if/when
617 needed. We welcome Jim-Tcl improvements, not bloat. Also there
618 are a large number of optional Jim-Tcl features that are not
619 enabled in OpenOCD.
621 @item @b{Scripts}
622 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
623 command interpreter today is a mixture of (newer)
624 Jim-Tcl commands, and the (older) original command interpreter.
626 @item @b{Commands}
627 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
628 can type a Tcl for() loop, set variables, etc.
629 Some of the commands documented in this guide are implemented
630 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
632 @item @b{Historical Note}
633 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
634 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
635 as a Git submodule, which greatly simplified upgrading Jim-Tcl
636 to benefit from new features and bugfixes in Jim-Tcl.
638 @item @b{Need a crash course in Tcl?}
639 @*@xref{Tcl Crash Course}.
640 @end itemize
642 @node Running
643 @chapter Running
644 @cindex command line options
645 @cindex logfile
646 @cindex directory search
648 Properly installing OpenOCD sets up your operating system to grant it access
649 to the debug adapters. On Linux, this usually involves installing a file
650 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
651 complex and confusing driver configuration for every peripheral. Such issues
652 are unique to each operating system, and are not detailed in this User's Guide.
654 Then later you will invoke the OpenOCD server, with various options to
655 tell it how each debug session should work.
656 The @option{--help} option shows:
657 @verbatim
658 bash$ openocd --help
660 --help | -h display this help
661 --version | -v display OpenOCD version
662 --file | -f use configuration file <name>
663 --search | -s dir to search for config files and scripts
664 --debug | -d set debug level <0-3>
665 --log_output | -l redirect log output to file <name>
666 --command | -c run <command>
667 @end verbatim
669 If you don't give any @option{-f} or @option{-c} options,
670 OpenOCD tries to read the configuration file @file{openocd.cfg}.
671 To specify one or more different
672 configuration files, use @option{-f} options. For example:
674 @example
675 openocd -f config1.cfg -f config2.cfg -f config3.cfg
676 @end example
678 Configuration files and scripts are searched for in
679 @enumerate
680 @item the current directory,
681 @item any search dir specified on the command line using the @option{-s} option,
682 @item any search dir specified using the @command{add_script_search_dir} command,
683 @item @file{$HOME/.openocd} (not on Windows),
684 @item the site wide script library @file{$pkgdatadir/site} and
685 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
686 @end enumerate
687 The first found file with a matching file name will be used.
689 @quotation Note
690 Don't try to use configuration script names or paths which
691 include the "#" character. That character begins Tcl comments.
692 @end quotation
694 @section Simple setup, no customization
696 In the best case, you can use two scripts from one of the script
697 libraries, hook up your JTAG adapter, and start the server ... and
698 your JTAG setup will just work "out of the box". Always try to
699 start by reusing those scripts, but assume you'll need more
700 customization even if this works. @xref{OpenOCD Project Setup}.
702 If you find a script for your JTAG adapter, and for your board or
703 target, you may be able to hook up your JTAG adapter then start
704 the server with some variation of one of the following:
706 @example
707 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
708 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
709 @end example
711 You might also need to configure which reset signals are present,
712 using @option{-c 'reset_config trst_and_srst'} or something similar.
713 If all goes well you'll see output something like
715 @example
716 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
717 For bug reports, read
719 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
720 (mfg: 0x23b, part: 0xba00, ver: 0x3)
721 @end example
723 Seeing that "tap/device found" message, and no warnings, means
724 the JTAG communication is working. That's a key milestone, but
725 you'll probably need more project-specific setup.
727 @section What OpenOCD does as it starts
729 OpenOCD starts by processing the configuration commands provided
730 on the command line or, if there were no @option{-c command} or
731 @option{-f file.cfg} options given, in @file{openocd.cfg}.
732 @xref{configurationstage,,Configuration Stage}.
733 At the end of the configuration stage it verifies the JTAG scan
734 chain defined using those commands; your configuration should
735 ensure that this always succeeds.
736 Normally, OpenOCD then starts running as a daemon.
737 Alternatively, commands may be used to terminate the configuration
738 stage early, perform work (such as updating some flash memory),
739 and then shut down without acting as a daemon.
741 Once OpenOCD starts running as a daemon, it waits for connections from
742 clients (Telnet, GDB, Other) and processes the commands issued through
743 those channels.
745 If you are having problems, you can enable internal debug messages via
746 the @option{-d} option.
748 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
749 @option{-c} command line switch.
751 To enable debug output (when reporting problems or working on OpenOCD
752 itself), use the @option{-d} command line switch. This sets the
753 @option{debug_level} to "3", outputting the most information,
754 including debug messages. The default setting is "2", outputting only
755 informational messages, warnings and errors. You can also change this
756 setting from within a telnet or gdb session using @command{debug_level<n>}
757 (@pxref{debuglevel,,debug_level}).
759 You can redirect all output from the daemon to a file using the
760 @option{-l <logfile>} switch.
762 Note! OpenOCD will launch the GDB & telnet server even if it can not
763 establish a connection with the target. In general, it is possible for
764 the JTAG controller to be unresponsive until the target is set up
765 correctly via e.g. GDB monitor commands in a GDB init script.
767 @node OpenOCD Project Setup
768 @chapter OpenOCD Project Setup
770 To use OpenOCD with your development projects, you need to do more than
771 just connect the JTAG adapter hardware (dongle) to your development board
772 and start the OpenOCD server.
773 You also need to configure your OpenOCD server so that it knows
774 about your adapter and board, and helps your work.
775 You may also want to connect OpenOCD to GDB, possibly
776 using Eclipse or some other GUI.
778 @section Hooking up the JTAG Adapter
780 Today's most common case is a dongle with a JTAG cable on one side
781 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
782 and a USB cable on the other.
783 Instead of USB, some cables use Ethernet;
784 older ones may use a PC parallel port, or even a serial port.
786 @enumerate
787 @item @emph{Start with power to your target board turned off},
788 and nothing connected to your JTAG adapter.
789 If you're particularly paranoid, unplug power to the board.
790 It's important to have the ground signal properly set up,
791 unless you are using a JTAG adapter which provides
792 galvanic isolation between the target board and the
793 debugging host.
795 @item @emph{Be sure it's the right kind of JTAG connector.}
796 If your dongle has a 20-pin ARM connector, you need some kind
797 of adapter (or octopus, see below) to hook it up to
798 boards using 14-pin or 10-pin connectors ... or to 20-pin
799 connectors which don't use ARM's pinout.
801 In the same vein, make sure the voltage levels are compatible.
802 Not all JTAG adapters have the level shifters needed to work
803 with 1.2 Volt boards.
805 @item @emph{Be certain the cable is properly oriented} or you might
806 damage your board. In most cases there are only two possible
807 ways to connect the cable.
808 Connect the JTAG cable from your adapter to the board.
809 Be sure it's firmly connected.
811 In the best case, the connector is keyed to physically
812 prevent you from inserting it wrong.
813 This is most often done using a slot on the board's male connector
814 housing, which must match a key on the JTAG cable's female connector.
815 If there's no housing, then you must look carefully and
816 make sure pin 1 on the cable hooks up to pin 1 on the board.
817 Ribbon cables are frequently all grey except for a wire on one
818 edge, which is red. The red wire is pin 1.
820 Sometimes dongles provide cables where one end is an ``octopus'' of
821 color coded single-wire connectors, instead of a connector block.
822 These are great when converting from one JTAG pinout to another,
823 but are tedious to set up.
824 Use these with connector pinout diagrams to help you match up the
825 adapter signals to the right board pins.
827 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
828 A USB, parallel, or serial port connector will go to the host which
829 you are using to run OpenOCD.
830 For Ethernet, consult the documentation and your network administrator.
832 For USB-based JTAG adapters you have an easy sanity check at this point:
833 does the host operating system see the JTAG adapter? If you're running
834 Linux, try the @command{lsusb} command. If that host is an
835 MS-Windows host, you'll need to install a driver before OpenOCD works.
837 @item @emph{Connect the adapter's power supply, if needed.}
838 This step is primarily for non-USB adapters,
839 but sometimes USB adapters need extra power.
841 @item @emph{Power up the target board.}
842 Unless you just let the magic smoke escape,
843 you're now ready to set up the OpenOCD server
844 so you can use JTAG to work with that board.
846 @end enumerate
848 Talk with the OpenOCD server using
849 telnet (@code{telnet localhost 4444} on many systems) or GDB.
850 @xref{GDB and OpenOCD}.
852 @section Project Directory
854 There are many ways you can configure OpenOCD and start it up.
856 A simple way to organize them all involves keeping a
857 single directory for your work with a given board.
858 When you start OpenOCD from that directory,
859 it searches there first for configuration files, scripts,
860 files accessed through semihosting,
861 and for code you upload to the target board.
862 It is also the natural place to write files,
863 such as log files and data you download from the board.
865 @section Configuration Basics
867 There are two basic ways of configuring OpenOCD, and
868 a variety of ways you can mix them.
869 Think of the difference as just being how you start the server:
871 @itemize
872 @item Many @option{-f file} or @option{-c command} options on the command line
873 @item No options, but a @dfn{user config file}
874 in the current directory named @file{openocd.cfg}
875 @end itemize
877 Here is an example @file{openocd.cfg} file for a setup
878 using a Signalyzer FT2232-based JTAG adapter to talk to
879 a board with an Atmel AT91SAM7X256 microcontroller:
881 @example
882 source [find interface/signalyzer.cfg]
884 # GDB can also flash my flash!
885 gdb_memory_map enable
886 gdb_flash_program enable
888 source [find target/sam7x256.cfg]
889 @end example
891 Here is the command line equivalent of that configuration:
893 @example
894 openocd -f interface/signalyzer.cfg \
895 -c "gdb_memory_map enable" \
896 -c "gdb_flash_program enable" \
897 -f target/sam7x256.cfg
898 @end example
900 You could wrap such long command lines in shell scripts,
901 each supporting a different development task.
902 One might re-flash the board with a specific firmware version.
903 Another might set up a particular debugging or run-time environment.
905 @quotation Important
906 At this writing (October 2009) the command line method has
907 problems with how it treats variables.
908 For example, after @option{-c "set VAR value"}, or doing the
909 same in a script, the variable @var{VAR} will have no value
910 that can be tested in a later script.
911 @end quotation
913 Here we will focus on the simpler solution: one user config
914 file, including basic configuration plus any TCL procedures
915 to simplify your work.
917 @section User Config Files
918 @cindex config file, user
919 @cindex user config file
920 @cindex config file, overview
922 A user configuration file ties together all the parts of a project
923 in one place.
924 One of the following will match your situation best:
926 @itemize
927 @item Ideally almost everything comes from configuration files
928 provided by someone else.
929 For example, OpenOCD distributes a @file{scripts} directory
930 (probably in @file{/usr/share/openocd/scripts} on Linux).
931 Board and tool vendors can provide these too, as can individual
932 user sites; the @option{-s} command line option lets you say
933 where to find these files. (@xref{Running}.)
934 The AT91SAM7X256 example above works this way.
936 Three main types of non-user configuration file each have their
937 own subdirectory in the @file{scripts} directory:
939 @enumerate
940 @item @b{interface} -- one for each different debug adapter;
941 @item @b{board} -- one for each different board
942 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
943 @end enumerate
945 Best case: include just two files, and they handle everything else.
946 The first is an interface config file.
947 The second is board-specific, and it sets up the JTAG TAPs and
948 their GDB targets (by deferring to some @file{target.cfg} file),
949 declares all flash memory, and leaves you nothing to do except
950 meet your deadline:
952 @example
953 source [find interface/olimex-jtag-tiny.cfg]
954 source [find board/csb337.cfg]
955 @end example
957 Boards with a single microcontroller often won't need more
958 than the target config file, as in the AT91SAM7X256 example.
959 That's because there is no external memory (flash, DDR RAM), and
960 the board differences are encapsulated by application code.
962 @item Maybe you don't know yet what your board looks like to JTAG.
963 Once you know the @file{interface.cfg} file to use, you may
964 need help from OpenOCD to discover what's on the board.
965 Once you find the JTAG TAPs, you can just search for appropriate
966 target and board
967 configuration files ... or write your own, from the bottom up.
968 @xref{autoprobing,,Autoprobing}.
970 @item You can often reuse some standard config files but
971 need to write a few new ones, probably a @file{board.cfg} file.
972 You will be using commands described later in this User's Guide,
973 and working with the guidelines in the next chapter.
975 For example, there may be configuration files for your JTAG adapter
976 and target chip, but you need a new board-specific config file
977 giving access to your particular flash chips.
978 Or you might need to write another target chip configuration file
979 for a new chip built around the Cortex M3 core.
981 @quotation Note
982 When you write new configuration files, please submit
983 them for inclusion in the next OpenOCD release.
984 For example, a @file{board/newboard.cfg} file will help the
985 next users of that board, and a @file{target/newcpu.cfg}
986 will help support users of any board using that chip.
987 @end quotation
989 @item
990 You may may need to write some C code.
991 It may be as simple as supporting a new FT2232 or parport
992 based adapter; a bit more involved, like a NAND or NOR flash
993 controller driver; or a big piece of work like supporting
994 a new chip architecture.
995 @end itemize
997 Reuse the existing config files when you can.
998 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
999 You may find a board configuration that's a good example to follow.
1001 When you write config files, separate the reusable parts
1002 (things every user of that interface, chip, or board needs)
1003 from ones specific to your environment and debugging approach.
1004 @itemize
1006 @item
1007 For example, a @code{gdb-attach} event handler that invokes
1008 the @command{reset init} command will interfere with debugging
1009 early boot code, which performs some of the same actions
1010 that the @code{reset-init} event handler does.
1012 @item
1013 Likewise, the @command{arm9 vector_catch} command (or
1014 @cindex vector_catch
1015 its siblings @command{xscale vector_catch}
1016 and @command{cortex_m vector_catch}) can be a timesaver
1017 during some debug sessions, but don't make everyone use that either.
1018 Keep those kinds of debugging aids in your user config file,
1019 along with messaging and tracing setup.
1020 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1022 @item
1023 You might need to override some defaults.
1024 For example, you might need to move, shrink, or back up the target's
1025 work area if your application needs much SRAM.
1027 @item
1028 TCP/IP port configuration is another example of something which
1029 is environment-specific, and should only appear in
1030 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1031 @end itemize
1033 @section Project-Specific Utilities
1035 A few project-specific utility
1036 routines may well speed up your work.
1037 Write them, and keep them in your project's user config file.
1039 For example, if you are making a boot loader work on a
1040 board, it's nice to be able to debug the ``after it's
1041 loaded to RAM'' parts separately from the finicky early
1042 code which sets up the DDR RAM controller and clocks.
1043 A script like this one, or a more GDB-aware sibling,
1044 may help:
1046 @example
1047 proc ramboot @{ @} @{
1048 # Reset, running the target's "reset-init" scripts
1049 # to initialize clocks and the DDR RAM controller.
1050 # Leave the CPU halted.
1051 reset init
1053 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1054 load_image u-boot.bin 0x20000000
1056 # Start running.
1057 resume 0x20000000
1058 @}
1059 @end example
1061 Then once that code is working you will need to make it
1062 boot from NOR flash; a different utility would help.
1063 Alternatively, some developers write to flash using GDB.
1064 (You might use a similar script if you're working with a flash
1065 based microcontroller application instead of a boot loader.)
1067 @example
1068 proc newboot @{ @} @{
1069 # Reset, leaving the CPU halted. The "reset-init" event
1070 # proc gives faster access to the CPU and to NOR flash;
1071 # "reset halt" would be slower.
1072 reset init
1074 # Write standard version of U-Boot into the first two
1075 # sectors of NOR flash ... the standard version should
1076 # do the same lowlevel init as "reset-init".
1077 flash protect 0 0 1 off
1078 flash erase_sector 0 0 1
1079 flash write_bank 0 u-boot.bin 0x0
1080 flash protect 0 0 1 on
1082 # Reboot from scratch using that new boot loader.
1083 reset run
1084 @}
1085 @end example
1087 You may need more complicated utility procedures when booting
1088 from NAND.
1089 That often involves an extra bootloader stage,
1090 running from on-chip SRAM to perform DDR RAM setup so it can load
1091 the main bootloader code (which won't fit into that SRAM).
1093 Other helper scripts might be used to write production system images,
1094 involving considerably more than just a three stage bootloader.
1096 @section Target Software Changes
1098 Sometimes you may want to make some small changes to the software
1099 you're developing, to help make JTAG debugging work better.
1100 For example, in C or assembly language code you might
1101 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1102 handling issues like:
1104 @itemize @bullet
1106 @item @b{Watchdog Timers}...
1107 Watchog timers are typically used to automatically reset systems if
1108 some application task doesn't periodically reset the timer. (The
1109 assumption is that the system has locked up if the task can't run.)
1110 When a JTAG debugger halts the system, that task won't be able to run
1111 and reset the timer ... potentially causing resets in the middle of
1112 your debug sessions.
1114 It's rarely a good idea to disable such watchdogs, since their usage
1115 needs to be debugged just like all other parts of your firmware.
1116 That might however be your only option.
1118 Look instead for chip-specific ways to stop the watchdog from counting
1119 while the system is in a debug halt state. It may be simplest to set
1120 that non-counting mode in your debugger startup scripts. You may however
1121 need a different approach when, for example, a motor could be physically
1122 damaged by firmware remaining inactive in a debug halt state. That might
1123 involve a type of firmware mode where that "non-counting" mode is disabled
1124 at the beginning then re-enabled at the end; a watchdog reset might fire
1125 and complicate the debug session, but hardware (or people) would be
1126 protected.@footnote{Note that many systems support a "monitor mode" debug
1127 that is a somewhat cleaner way to address such issues. You can think of
1128 it as only halting part of the system, maybe just one task,
1129 instead of the whole thing.
1130 At this writing, January 2010, OpenOCD based debugging does not support
1131 monitor mode debug, only "halt mode" debug.}
1133 @item @b{ARM Semihosting}...
1134 @cindex ARM semihosting
1135 When linked with a special runtime library provided with many
1136 toolchains@footnote{See chapter 8 "Semihosting" in
1137 @uref{,
1138 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1139 The CodeSourcery EABI toolchain also includes a semihosting library.},
1140 your target code can use I/O facilities on the debug host. That library
1141 provides a small set of system calls which are handled by OpenOCD.
1142 It can let the debugger provide your system console and a file system,
1143 helping with early debugging or providing a more capable environment
1144 for sometimes-complex tasks like installing system firmware onto
1145 NAND or SPI flash.
1147 @item @b{ARM Wait-For-Interrupt}...
1148 Many ARM chips synchronize the JTAG clock using the core clock.
1149 Low power states which stop that core clock thus prevent JTAG access.
1150 Idle loops in tasking environments often enter those low power states
1151 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1153 You may want to @emph{disable that instruction} in source code,
1154 or otherwise prevent using that state,
1155 to ensure you can get JTAG access at any time.@footnote{As a more
1156 polite alternative, some processors have special debug-oriented
1157 registers which can be used to change various features including
1158 how the low power states are clocked while debugging.
1159 The STM32 DBGMCU_CR register is an example; at the cost of extra
1160 power consumption, JTAG can be used during low power states.}
1161 For example, the OpenOCD @command{halt} command may not
1162 work for an idle processor otherwise.
1164 @item @b{Delay after reset}...
1165 Not all chips have good support for debugger access
1166 right after reset; many LPC2xxx chips have issues here.
1167 Similarly, applications that reconfigure pins used for
1168 JTAG access as they start will also block debugger access.
1170 To work with boards like this, @emph{enable a short delay loop}
1171 the first thing after reset, before "real" startup activities.
1172 For example, one second's delay is usually more than enough
1173 time for a JTAG debugger to attach, so that
1174 early code execution can be debugged
1175 or firmware can be replaced.
1177 @item @b{Debug Communications Channel (DCC)}...
1178 Some processors include mechanisms to send messages over JTAG.
1179 Many ARM cores support these, as do some cores from other vendors.
1180 (OpenOCD may be able to use this DCC internally, speeding up some
1181 operations like writing to memory.)
1183 Your application may want to deliver various debugging messages
1184 over JTAG, by @emph{linking with a small library of code}
1185 provided with OpenOCD and using the utilities there to send
1186 various kinds of message.
1187 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1189 @end itemize
1191 @section Target Hardware Setup
1193 Chip vendors often provide software development boards which
1194 are highly configurable, so that they can support all options
1195 that product boards may require. @emph{Make sure that any
1196 jumpers or switches match the system configuration you are
1197 working with.}
1199 Common issues include:
1201 @itemize @bullet
1203 @item @b{JTAG setup} ...
1204 Boards may support more than one JTAG configuration.
1205 Examples include jumpers controlling pullups versus pulldowns
1206 on the nTRST and/or nSRST signals, and choice of connectors
1207 (e.g. which of two headers on the base board,
1208 or one from a daughtercard).
1209 For some Texas Instruments boards, you may need to jumper the
1210 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1212 @item @b{Boot Modes} ...
1213 Complex chips often support multiple boot modes, controlled
1214 by external jumpers. Make sure this is set up correctly.
1215 For example many i.MX boards from NXP need to be jumpered
1216 to "ATX mode" to start booting using the on-chip ROM, when
1217 using second stage bootloader code stored in a NAND flash chip.
1219 Such explicit configuration is common, and not limited to
1220 booting from NAND. You might also need to set jumpers to
1221 start booting using code loaded from an MMC/SD card; external
1222 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1223 flash; some external host; or various other sources.
1226 @item @b{Memory Addressing} ...
1227 Boards which support multiple boot modes may also have jumpers
1228 to configure memory addressing. One board, for example, jumpers
1229 external chipselect 0 (used for booting) to address either
1230 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1231 or NAND flash. When it's jumpered to address NAND flash, that
1232 board must also be told to start booting from on-chip ROM.
1234 Your @file{board.cfg} file may also need to be told this jumper
1235 configuration, so that it can know whether to declare NOR flash
1236 using @command{flash bank} or instead declare NAND flash with
1237 @command{nand device}; and likewise which probe to perform in
1238 its @code{reset-init} handler.
1240 A closely related issue is bus width. Jumpers might need to
1241 distinguish between 8 bit or 16 bit bus access for the flash
1242 used to start booting.
1244 @item @b{Peripheral Access} ...
1245 Development boards generally provide access to every peripheral
1246 on the chip, sometimes in multiple modes (such as by providing
1247 multiple audio codec chips).
1248 This interacts with software
1249 configuration of pin multiplexing, where for example a
1250 given pin may be routed either to the MMC/SD controller
1251 or the GPIO controller. It also often interacts with
1252 configuration jumpers. One jumper may be used to route
1253 signals to an MMC/SD card slot or an expansion bus (which
1254 might in turn affect booting); others might control which
1255 audio or video codecs are used.
1257 @end itemize
1259 Plus you should of course have @code{reset-init} event handlers
1260 which set up the hardware to match that jumper configuration.
1261 That includes in particular any oscillator or PLL used to clock
1262 the CPU, and any memory controllers needed to access external
1263 memory and peripherals. Without such handlers, you won't be
1264 able to access those resources without working target firmware
1265 which can do that setup ... this can be awkward when you're
1266 trying to debug that target firmware. Even if there's a ROM
1267 bootloader which handles a few issues, it rarely provides full
1268 access to all board-specific capabilities.
1271 @node Config File Guidelines
1272 @chapter Config File Guidelines
1274 This chapter is aimed at any user who needs to write a config file,
1275 including developers and integrators of OpenOCD and any user who
1276 needs to get a new board working smoothly.
1277 It provides guidelines for creating those files.
1279 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1280 with files including the ones listed here.
1281 Use them as-is where you can; or as models for new files.
1282 @itemize @bullet
1283 @item @file{interface} ...
1284 These are for debug adapters.
1285 Files that configure JTAG adapters go here.
1286 @example
1287 $ ls interface -R
1288 interface/:
1289 altera-usb-blaster.cfg hilscher_nxhx50_re.cfg openocd-usb-hs.cfg
1290 arm-jtag-ew.cfg hitex_str9-comstick.cfg openrd.cfg
1291 at91rm9200.cfg icebear.cfg osbdm.cfg
1292 axm0432.cfg jlink.cfg parport.cfg
1293 busblaster.cfg jtagkey2.cfg parport_dlc5.cfg
1294 buspirate.cfg jtagkey2p.cfg redbee-econotag.cfg
1295 calao-usb-a9260-c01.cfg jtagkey.cfg redbee-usb.cfg
1296 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg rlink.cfg
1297 calao-usb-a9260.cfg jtag-lock-pick_tiny_2.cfg sheevaplug.cfg
1298 chameleon.cfg kt-link.cfg signalyzer.cfg
1299 cortino.cfg lisa-l.cfg signalyzer-h2.cfg
1300 digilent-hs1.cfg luminary.cfg signalyzer-h4.cfg
1301 dlp-usb1232h.cfg luminary-icdi.cfg signalyzer-lite.cfg
1302 dummy.cfg luminary-lm3s811.cfg stlink-v1.cfg
1303 estick.cfg minimodule.cfg stlink-v2.cfg
1304 flashlink.cfg neodb.cfg stm32-stick.cfg
1305 flossjtag.cfg ngxtech.cfg sysfsgpio-raspberrypi.cfg
1306 flossjtag-noeeprom.cfg olimex-arm-usb-ocd.cfg ti-icdi.cfg
1307 flyswatter2.cfg olimex-arm-usb-ocd-h.cfg turtelizer2.cfg
1308 flyswatter.cfg olimex-arm-usb-tiny-h.cfg ulink.cfg
1309 ftdi olimex-jtag-tiny.cfg usb-jtag.cfg
1310 hilscher_nxhx10_etm.cfg oocdlink.cfg usbprog.cfg
1311 hilscher_nxhx500_etm.cfg opendous.cfg vpaclink.cfg
1312 hilscher_nxhx500_re.cfg opendous_ftdi.cfg vsllink.cfg
1313 hilscher_nxhx50_etm.cfg openocd-usb.cfg xds100v2.cfg
1315 interface/ftdi:
1316 axm0432.cfg hitex_str9-comstick.cfg olimex-jtag-tiny.cfg
1317 calao-usb-a9260-c01.cfg icebear.cfg oocdlink.cfg
1318 calao-usb-a9260-c02.cfg jtagkey2.cfg opendous_ftdi.cfg
1319 cortino.cfg jtagkey2p.cfg openocd-usb.cfg
1320 dlp-usb1232h.cfg jtagkey.cfg openocd-usb-hs.cfg
1321 dp_busblaster.cfg jtag-lock-pick_tiny_2.cfg openrd.cfg
1322 flossjtag.cfg kt-link.cfg redbee-econotag.cfg
1323 flossjtag-noeeprom.cfg lisa-l.cfg redbee-usb.cfg
1324 flyswatter2.cfg luminary.cfg sheevaplug.cfg
1325 flyswatter.cfg luminary-icdi.cfg signalyzer.cfg
1326 gw16042.cfg luminary-lm3s811.cfg signalyzer-lite.cfg
1327 hilscher_nxhx10_etm.cfg minimodule.cfg stm32-stick.cfg
1328 hilscher_nxhx500_etm.cfg neodb.cfg turtelizer2-revB.cfg
1329 hilscher_nxhx500_re.cfg ngxtech.cfg turtelizer2-revC.cfg
1330 hilscher_nxhx50_etm.cfg olimex-arm-usb-ocd.cfg vpaclink.cfg
1331 hilscher_nxhx50_re.cfg olimex-arm-usb-ocd-h.cfg xds100v2.cfg
1332 hitex_lpc1768stick.cfg olimex-arm-usb-tiny-h.cfg
1333 $
1334 @end example
1335 @item @file{board} ...
1336 think Circuit Board, PWA, PCB, they go by many names. Board files
1337 contain initialization items that are specific to a board.
1338 They reuse target configuration files, since the same
1339 microprocessor chips are used on many boards,
1340 but support for external parts varies widely. For
1341 example, the SDRAM initialization sequence for the board, or the type
1342 of external flash and what address it uses. Any initialization
1343 sequence to enable that external flash or SDRAM should be found in the
1344 board file. Boards may also contain multiple targets: two CPUs; or
1345 a CPU and an FPGA.
1346 @example
1347 $ ls board
1348 actux3.cfg lpc1850_spifi_generic.cfg
1349 am3517evm.cfg lpc4350_spifi_generic.cfg
1350 arm_evaluator7t.cfg lubbock.cfg
1351 at91cap7a-stk-sdram.cfg mcb1700.cfg
1352 at91eb40a.cfg microchip_explorer16.cfg
1353 at91rm9200-dk.cfg mini2440.cfg
1354 at91rm9200-ek.cfg mini6410.cfg
1355 at91sam9261-ek.cfg netgear-dg834v3.cfg
1356 at91sam9263-ek.cfg olimex_LPC2378STK.cfg
1357 at91sam9g20-ek.cfg olimex_lpc_h2148.cfg
1358 atmel_at91sam7s-ek.cfg olimex_sam7_ex256.cfg
1359 atmel_at91sam9260-ek.cfg olimex_sam9_l9260.cfg
1360 atmel_at91sam9rl-ek.cfg olimex_stm32_h103.cfg
1361 atmel_sam3n_ek.cfg olimex_stm32_h107.cfg
1362 atmel_sam3s_ek.cfg olimex_stm32_p107.cfg
1363 atmel_sam3u_ek.cfg omap2420_h4.cfg
1364 atmel_sam3x_ek.cfg open-bldc.cfg
1365 atmel_sam4s_ek.cfg openrd.cfg
1366 balloon3-cpu.cfg osk5912.cfg
1367 colibri.cfg phone_se_j100i.cfg
1368 crossbow_tech_imote2.cfg phytec_lpc3250.cfg
1369 csb337.cfg pic-p32mx.cfg
1370 csb732.cfg propox_mmnet1001.cfg
1371 da850evm.cfg pxa255_sst.cfg
1372 digi_connectcore_wi-9c.cfg redbee.cfg
1373 diolan_lpc4350-db1.cfg rsc-w910.cfg
1374 dm355evm.cfg sheevaplug.cfg
1375 dm365evm.cfg smdk6410.cfg
1376 dm6446evm.cfg spear300evb.cfg
1377 efikamx.cfg spear300evb_mod.cfg
1378 eir.cfg spear310evb20.cfg
1379 ek-lm3s1968.cfg spear310evb20_mod.cfg
1380 ek-lm3s3748.cfg spear320cpu.cfg
1381 ek-lm3s6965.cfg spear320cpu_mod.cfg
1382 ek-lm3s811.cfg steval_pcc010.cfg
1383 ek-lm3s811-revb.cfg stm320518_eval_stlink.cfg
1384 ek-lm3s8962.cfg stm32100b_eval.cfg
1385 ek-lm3s9b9x.cfg stm3210b_eval.cfg
1386 ek-lm3s9d92.cfg stm3210c_eval.cfg
1387 ek-lm4f120xl.cfg stm3210e_eval.cfg
1388 ek-lm4f232.cfg stm3220g_eval.cfg
1389 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1390 ethernut3.cfg stm3241g_eval.cfg
1391 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1392 hammer.cfg stm32f0discovery.cfg
1393 hilscher_nxdb500sys.cfg stm32f3discovery.cfg
1394 hilscher_nxeb500hmi.cfg stm32f4discovery.cfg
1395 hilscher_nxhx10.cfg stm32ldiscovery.cfg
1396 hilscher_nxhx500.cfg stm32vldiscovery.cfg
1397 hilscher_nxhx50.cfg str910-eval.cfg
1398 hilscher_nxsb100.cfg telo.cfg
1399 hitex_lpc1768stick.cfg ti_am335xevm.cfg
1400 hitex_lpc2929.cfg ti_beagleboard.cfg
1401 hitex_stm32-performancestick.cfg ti_beagleboard_xm.cfg
1402 hitex_str9-comstick.cfg ti_beaglebone.cfg
1403 iar_lpc1768.cfg ti_blaze.cfg
1404 iar_str912_sk.cfg ti_pandaboard.cfg
1405 icnova_imx53_sodimm.cfg ti_pandaboard_es.cfg
1406 icnova_sam9g45_sodimm.cfg topas910.cfg
1407 imx27ads.cfg topasa900.cfg
1408 imx27lnst.cfg twr-k60f120m.cfg
1409 imx28evk.cfg twr-k60n512.cfg
1410 imx31pdk.cfg tx25_stk5.cfg
1411 imx35pdk.cfg tx27_stk5.cfg
1412 imx53loco.cfg unknown_at91sam9260.cfg
1413 keil_mcb1700.cfg uptech_2410.cfg
1414 keil_mcb2140.cfg verdex.cfg
1415 kwikstik.cfg voipac.cfg
1416 linksys_nslu2.cfg voltcraft_dso-3062c.cfg
1417 lisa-l.cfg x300t.cfg
1418 logicpd_imx27.cfg zy1000.cfg
1419 $
1420 @end example
1421 @item @file{target} ...
1422 think chip. The ``target'' directory represents the JTAG TAPs
1423 on a chip
1424 which OpenOCD should control, not a board. Two common types of targets
1425 are ARM chips and FPGA or CPLD chips.
1426 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1427 the target config file defines all of them.
1428 @example
1429 $ ls target
1430 aduc702x.cfg lpc1763.cfg
1431 am335x.cfg lpc1764.cfg
1432 amdm37x.cfg lpc1765.cfg
1433 ar71xx.cfg lpc1766.cfg
1434 at32ap7000.cfg lpc1767.cfg
1435 at91r40008.cfg lpc1768.cfg
1436 at91rm9200.cfg lpc1769.cfg
1437 at91sam3ax_4x.cfg lpc1788.cfg
1438 at91sam3ax_8x.cfg lpc17xx.cfg
1439 at91sam3ax_xx.cfg lpc1850.cfg
1440 at91sam3nXX.cfg lpc2103.cfg
1441 at91sam3sXX.cfg lpc2124.cfg
1442 at91sam3u1c.cfg lpc2129.cfg
1443 at91sam3u1e.cfg lpc2148.cfg
1444 at91sam3u2c.cfg lpc2294.cfg
1445 at91sam3u2e.cfg lpc2378.cfg
1446 at91sam3u4c.cfg lpc2460.cfg
1447 at91sam3u4e.cfg lpc2478.cfg
1448 at91sam3uxx.cfg lpc2900.cfg
1449 at91sam3XXX.cfg lpc2xxx.cfg
1450 at91sam4sd32x.cfg lpc3131.cfg
1451 at91sam4sXX.cfg lpc3250.cfg
1452 at91sam4XXX.cfg lpc4350.cfg
1453 at91sam7se512.cfg lpc4350.cfg.orig
1454 at91sam7sx.cfg mc13224v.cfg
1455 at91sam7x256.cfg nuc910.cfg
1456 at91sam7x512.cfg omap2420.cfg
1457 at91sam9260.cfg omap3530.cfg
1458 at91sam9260_ext_RAM_ext_flash.cfg omap4430.cfg
1459 at91sam9261.cfg omap4460.cfg
1460 at91sam9263.cfg omap5912.cfg
1461 at91sam9.cfg omapl138.cfg
1462 at91sam9g10.cfg pic32mx.cfg
1463 at91sam9g20.cfg pxa255.cfg
1464 at91sam9g45.cfg pxa270.cfg
1465 at91sam9rl.cfg pxa3xx.cfg
1466 atmega128.cfg readme.txt
1467 avr32.cfg samsung_s3c2410.cfg
1468 c100.cfg samsung_s3c2440.cfg
1469 c100config.tcl samsung_s3c2450.cfg
1470 c100helper.tcl samsung_s3c4510.cfg
1471 c100regs.tcl samsung_s3c6410.cfg
1472 cs351x.cfg sharp_lh79532.cfg
1473 davinci.cfg smp8634.cfg
1474 dragonite.cfg spear3xx.cfg
1475 dsp56321.cfg stellaris.cfg
1476 dsp568013.cfg stellaris_icdi.cfg
1477 dsp568037.cfg stm32f0x_stlink.cfg
1478 efm32_stlink.cfg stm32f1x.cfg
1479 epc9301.cfg stm32f1x_stlink.cfg
1480 faux.cfg stm32f2x.cfg
1481 feroceon.cfg stm32f2x_stlink.cfg
1482 fm3.cfg stm32f3x.cfg
1483 hilscher_netx10.cfg stm32f3x_stlink.cfg
1484 hilscher_netx500.cfg stm32f4x.cfg
1485 hilscher_netx50.cfg stm32f4x_stlink.cfg
1486 icepick.cfg stm32l.cfg
1487 imx21.cfg stm32lx_dual_bank.cfg
1488 imx25.cfg stm32lx_stlink.cfg
1489 imx27.cfg stm32_stlink.cfg
1490 imx28.cfg stm32w108_stlink.cfg
1491 imx31.cfg stm32xl.cfg
1492 imx35.cfg str710.cfg
1493 imx51.cfg str730.cfg
1494 imx53.cfg str750.cfg
1495 imx6.cfg str912.cfg
1496 imx.cfg swj-dp.tcl
1497 is5114.cfg test_reset_syntax_error.cfg
1498 ixp42x.cfg test_syntax_error.cfg
1499 k40.cfg ti-ar7.cfg
1500 k60.cfg ti_calypso.cfg
1501 lpc1751.cfg ti_dm355.cfg
1502 lpc1752.cfg ti_dm365.cfg
1503 lpc1754.cfg ti_dm6446.cfg
1504 lpc1756.cfg tmpa900.cfg
1505 lpc1758.cfg tmpa910.cfg
1506 lpc1759.cfg u8500.cfg
1507 @end example
1508 @item @emph{more} ... browse for other library files which may be useful.
1509 For example, there are various generic and CPU-specific utilities.
1510 @end itemize
1512 The @file{openocd.cfg} user config
1513 file may override features in any of the above files by
1514 setting variables before sourcing the target file, or by adding
1515 commands specific to their situation.
1517 @section Interface Config Files
1519 The user config file
1520 should be able to source one of these files with a command like this:
1522 @example
1523 source [find interface/FOOBAR.cfg]
1524 @end example
1526 A preconfigured interface file should exist for every debug adapter
1527 in use today with OpenOCD.
1528 That said, perhaps some of these config files
1529 have only been used by the developer who created it.
1531 A separate chapter gives information about how to set these up.
1532 @xref{Debug Adapter Configuration}.
1533 Read the OpenOCD source code (and Developer's Guide)
1534 if you have a new kind of hardware interface
1535 and need to provide a driver for it.
1537 @section Board Config Files
1538 @cindex config file, board
1539 @cindex board config file
1541 The user config file
1542 should be able to source one of these files with a command like this:
1544 @example
1545 source [find board/FOOBAR.cfg]
1546 @end example
1548 The point of a board config file is to package everything
1549 about a given board that user config files need to know.
1550 In summary the board files should contain (if present)
1552 @enumerate
1553 @item One or more @command{source [find target/...cfg]} statements
1554 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1555 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1556 @item Target @code{reset} handlers for SDRAM and I/O configuration
1557 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1558 @item All things that are not ``inside a chip''
1559 @end enumerate
1561 Generic things inside target chips belong in target config files,
1562 not board config files. So for example a @code{reset-init} event
1563 handler should know board-specific oscillator and PLL parameters,
1564 which it passes to target-specific utility code.
1566 The most complex task of a board config file is creating such a
1567 @code{reset-init} event handler.
1568 Define those handlers last, after you verify the rest of the board
1569 configuration works.
1571 @subsection Communication Between Config files
1573 In addition to target-specific utility code, another way that
1574 board and target config files communicate is by following a
1575 convention on how to use certain variables.
1577 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1578 Thus the rule we follow in OpenOCD is this: Variables that begin with
1579 a leading underscore are temporary in nature, and can be modified and
1580 used at will within a target configuration file.
1582 Complex board config files can do the things like this,
1583 for a board with three chips:
1585 @example
1586 # Chip #1: PXA270 for network side, big endian
1587 set CHIPNAME network
1588 set ENDIAN big
1589 source [find target/pxa270.cfg]
1590 # on return: _TARGETNAME = network.cpu
1591 # other commands can refer to the "network.cpu" target.
1592 $_TARGETNAME configure .... events for this CPU..
1594 # Chip #2: PXA270 for video side, little endian
1595 set CHIPNAME video
1596 set ENDIAN little
1597 source [find target/pxa270.cfg]
1598 # on return: _TARGETNAME = video.cpu
1599 # other commands can refer to the "video.cpu" target.
1600 $_TARGETNAME configure .... events for this CPU..
1602 # Chip #3: Xilinx FPGA for glue logic
1603 set CHIPNAME xilinx
1604 unset ENDIAN
1605 source [find target/spartan3.cfg]
1606 @end example
1608 That example is oversimplified because it doesn't show any flash memory,
1609 or the @code{reset-init} event handlers to initialize external DRAM
1610 or (assuming it needs it) load a configuration into the FPGA.
1611 Such features are usually needed for low-level work with many boards,
1612 where ``low level'' implies that the board initialization software may
1613 not be working. (That's a common reason to need JTAG tools. Another
1614 is to enable working with microcontroller-based systems, which often
1615 have no debugging support except a JTAG connector.)
1617 Target config files may also export utility functions to board and user
1618 config files. Such functions should use name prefixes, to help avoid
1619 naming collisions.
1621 Board files could also accept input variables from user config files.
1622 For example, there might be a @code{J4_JUMPER} setting used to identify
1623 what kind of flash memory a development board is using, or how to set
1624 up other clocks and peripherals.
1626 @subsection Variable Naming Convention
1627 @cindex variable names
1629 Most boards have only one instance of a chip.
1630 However, it should be easy to create a board with more than
1631 one such chip (as shown above).
1632 Accordingly, we encourage these conventions for naming
1633 variables associated with different @file{target.cfg} files,
1634 to promote consistency and
1635 so that board files can override target defaults.
1637 Inputs to target config files include:
1639 @itemize @bullet
1640 @item @code{CHIPNAME} ...
1641 This gives a name to the overall chip, and is used as part of
1642 tap identifier dotted names.
1643 While the default is normally provided by the chip manufacturer,
1644 board files may need to distinguish between instances of a chip.
1645 @item @code{ENDIAN} ...
1646 By default @option{little} - although chips may hard-wire @option{big}.
1647 Chips that can't change endianness don't need to use this variable.
1648 @item @code{CPUTAPID} ...
1649 When OpenOCD examines the JTAG chain, it can be told verify the
1650 chips against the JTAG IDCODE register.
1651 The target file will hold one or more defaults, but sometimes the
1652 chip in a board will use a different ID (perhaps a newer revision).
1653 @end itemize
1655 Outputs from target config files include:
1657 @itemize @bullet
1658 @item @code{_TARGETNAME} ...
1659 By convention, this variable is created by the target configuration
1660 script. The board configuration file may make use of this variable to
1661 configure things like a ``reset init'' script, or other things
1662 specific to that board and that target.
1663 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1664 @code{_TARGETNAME1}, ... etc.
1665 @end itemize
1667 @subsection The reset-init Event Handler
1668 @cindex event, reset-init
1669 @cindex reset-init handler
1671 Board config files run in the OpenOCD configuration stage;
1672 they can't use TAPs or targets, since they haven't been
1673 fully set up yet.
1674 This means you can't write memory or access chip registers;
1675 you can't even verify that a flash chip is present.
1676 That's done later in event handlers, of which the target @code{reset-init}
1677 handler is one of the most important.
1679 Except on microcontrollers, the basic job of @code{reset-init} event
1680 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1681 Microcontrollers rarely use boot loaders; they run right out of their
1682 on-chip flash and SRAM memory. But they may want to use one of these
1683 handlers too, if just for developer convenience.
1685 @quotation Note
1686 Because this is so very board-specific, and chip-specific, no examples
1687 are included here.
1688 Instead, look at the board config files distributed with OpenOCD.
1689 If you have a boot loader, its source code will help; so will
1690 configuration files for other JTAG tools
1691 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1692 @end quotation
1694 Some of this code could probably be shared between different boards.
1695 For example, setting up a DRAM controller often doesn't differ by
1696 much except the bus width (16 bits or 32?) and memory timings, so a
1697 reusable TCL procedure loaded by the @file{target.cfg} file might take
1698 those as parameters.
1699 Similarly with oscillator, PLL, and clock setup;
1700 and disabling the watchdog.
1701 Structure the code cleanly, and provide comments to help
1702 the next developer doing such work.
1703 (@emph{You might be that next person} trying to reuse init code!)
1705 The last thing normally done in a @code{reset-init} handler is probing
1706 whatever flash memory was configured. For most chips that needs to be
1707 done while the associated target is halted, either because JTAG memory
1708 access uses the CPU or to prevent conflicting CPU access.
1710 @subsection JTAG Clock Rate
1712 Before your @code{reset-init} handler has set up
1713 the PLLs and clocking, you may need to run with
1714 a low JTAG clock rate.
1715 @xref{jtagspeed,,JTAG Speed}.
1716 Then you'd increase that rate after your handler has
1717 made it possible to use the faster JTAG clock.
1718 When the initial low speed is board-specific, for example
1719 because it depends on a board-specific oscillator speed, then
1720 you should probably set it up in the board config file;
1721 if it's target-specific, it belongs in the target config file.
1723 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1724 @uref{} gives details.}
1725 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1726 Consult chip documentation to determine the peak JTAG clock rate,
1727 which might be less than that.
1729 @quotation Warning
1730 On most ARMs, JTAG clock detection is coupled to the core clock, so
1731 software using a @option{wait for interrupt} operation blocks JTAG access.
1732 Adaptive clocking provides a partial workaround, but a more complete
1733 solution just avoids using that instruction with JTAG debuggers.
1734 @end quotation
1736 If both the chip and the board support adaptive clocking,
1737 use the @command{jtag_rclk}
1738 command, in case your board is used with JTAG adapter which
1739 also supports it. Otherwise use @command{adapter_khz}.
1740 Set the slow rate at the beginning of the reset sequence,
1741 and the faster rate as soon as the clocks are at full speed.
1743 @anchor{theinitboardprocedure}
1744 @subsection The init_board procedure
1745 @cindex init_board procedure
1747 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1748 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1749 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1750 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1751 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1752 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1753 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1754 Additionally ``linear'' board config file will most likely fail when target config file uses
1755 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1756 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1757 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1758 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1760 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1761 the original), allowing greater code reuse.
1763 @example
1764 ### board_file.cfg ###
1766 # source target file that does most of the config in init_targets
1767 source [find target/target.cfg]
1769 proc enable_fast_clock @{@} @{
1770 # enables fast on-board clock source
1771 # configures the chip to use it
1772 @}
1774 # initialize only board specifics - reset, clock, adapter frequency
1775 proc init_board @{@} @{
1776 reset_config trst_and_srst trst_pulls_srst
1778 $_TARGETNAME configure -event reset-init @{
1779 adapter_khz 1
1780 enable_fast_clock
1781 adapter_khz 10000
1782 @}
1783 @}
1784 @end example
1786 @section Target Config Files
1787 @cindex config file, target
1788 @cindex target config file
1790 Board config files communicate with target config files using
1791 naming conventions as described above, and may source one or
1792 more target config files like this:
1794 @example
1795 source [find target/FOOBAR.cfg]
1796 @end example
1798 The point of a target config file is to package everything
1799 about a given chip that board config files need to know.
1800 In summary the target files should contain
1802 @enumerate
1803 @item Set defaults
1804 @item Add TAPs to the scan chain
1805 @item Add CPU targets (includes GDB support)
1806 @item CPU/Chip/CPU-Core specific features
1807 @item On-Chip flash
1808 @end enumerate
1810 As a rule of thumb, a target file sets up only one chip.
1811 For a microcontroller, that will often include a single TAP,
1812 which is a CPU needing a GDB target, and its on-chip flash.
1814 More complex chips may include multiple TAPs, and the target
1815 config file may need to define them all before OpenOCD
1816 can talk to the chip.
1817 For example, some phone chips have JTAG scan chains that include
1818 an ARM core for operating system use, a DSP,
1819 another ARM core embedded in an image processing engine,
1820 and other processing engines.
1822 @subsection Default Value Boiler Plate Code
1824 All target configuration files should start with code like this,
1825 letting board config files express environment-specific
1826 differences in how things should be set up.
1828 @example
1829 # Boards may override chip names, perhaps based on role,
1830 # but the default should match what the vendor uses
1831 if @{ [info exists CHIPNAME] @} @{
1833 @} else @{
1834 set _CHIPNAME sam7x256
1835 @}
1837 # ONLY use ENDIAN with targets that can change it.
1838 if @{ [info exists ENDIAN] @} @{
1839 set _ENDIAN $ENDIAN
1840 @} else @{
1841 set _ENDIAN little
1842 @}
1844 # TAP identifiers may change as chips mature, for example with
1845 # new revision fields (the "3" here). Pick a good default; you
1846 # can pass several such identifiers to the "jtag newtap" command.
1847 if @{ [info exists CPUTAPID ] @} @{
1849 @} else @{
1850 set _CPUTAPID 0x3f0f0f0f
1851 @}
1852 @end example
1853 @c but 0x3f0f0f0f is for an str73x part ...
1855 @emph{Remember:} Board config files may include multiple target
1856 config files, or the same target file multiple times
1857 (changing at least @code{CHIPNAME}).
1859 Likewise, the target configuration file should define
1860 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1861 use it later on when defining debug targets:
1863 @example
1865 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1866 @end example
1868 @subsection Adding TAPs to the Scan Chain
1869 After the ``defaults'' are set up,
1870 add the TAPs on each chip to the JTAG scan chain.
1871 @xref{TAP Declaration}, and the naming convention
1872 for taps.
1874 In the simplest case the chip has only one TAP,
1875 probably for a CPU or FPGA.
1876 The config file for the Atmel AT91SAM7X256
1877 looks (in part) like this:
1879 @example
1880 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1881 @end example
1883 A board with two such at91sam7 chips would be able
1884 to source such a config file twice, with different
1885 values for @code{CHIPNAME}, so
1886 it adds a different TAP each time.
1888 If there are nonzero @option{-expected-id} values,
1889 OpenOCD attempts to verify the actual tap id against those values.
1890 It will issue error messages if there is mismatch, which
1891 can help to pinpoint problems in OpenOCD configurations.
1893 @example
1894 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1895 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1896 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1897 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1898 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1899 @end example
1901 There are more complex examples too, with chips that have
1902 multiple TAPs. Ones worth looking at include:
1904 @itemize
1905 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1906 plus a JRC to enable them
1907 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1908 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1909 is not currently used)
1910 @end itemize
1912 @subsection Add CPU targets
1914 After adding a TAP for a CPU, you should set it up so that
1915 GDB and other commands can use it.
1916 @xref{CPU Configuration}.
1917 For the at91sam7 example above, the command can look like this;
1918 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1919 to little endian, and this chip doesn't support changing that.
1921 @example
1923 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1924 @end example
1926 Work areas are small RAM areas associated with CPU targets.
1927 They are used by OpenOCD to speed up downloads,
1928 and to download small snippets of code to program flash chips.
1929 If the chip includes a form of ``on-chip-ram'' - and many do - define
1930 a work area if you can.
1931 Again using the at91sam7 as an example, this can look like:
1933 @example
1934 $_TARGETNAME configure -work-area-phys 0x00200000 \
1935 -work-area-size 0x4000 -work-area-backup 0
1936 @end example
1938 @anchor{definecputargetsworkinginsmp}
1939 @subsection Define CPU targets working in SMP
1940 @cindex SMP
1941 After setting targets, you can define a list of targets working in SMP.
1943 @example
1944 set _TARGETNAME_1 $_CHIPNAME.cpu1
1945 set _TARGETNAME_2 $_CHIPNAME.cpu2
1946 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1947 -coreid 0 -dbgbase $_DAP_DBG1
1948 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1949 -coreid 1 -dbgbase $_DAP_DBG2
1950 #define 2 targets working in smp.
1951 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1952 @end example
1953 In the above example on cortex_a, 2 cpus are working in SMP.
1954 In SMP only one GDB instance is created and :
1955 @itemize @bullet
1956 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1957 @item halt command triggers the halt of all targets in the list.
1958 @item resume command triggers the write context and the restart of all targets in the list.
1959 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1960 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1961 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1962 @end itemize
1964 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1965 command have been implemented.
1966 @itemize @bullet
1967 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1968 @item cortex_a smp_off : disable SMP mode, the current target is the one
1969 displayed in the GDB session, only this target is now controlled by GDB
1970 session. This behaviour is useful during system boot up.
1971 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1972 following example.
1973 @end itemize
1975 @example
1976 >cortex_a smp_gdb
1977 gdb coreid 0 -> -1
1978 #0 : coreid 0 is displayed to GDB ,
1979 #-> -1 : next resume triggers a real resume
1980 > cortex_a smp_gdb 1
1981 gdb coreid 0 -> 1
1982 #0 :coreid 0 is displayed to GDB ,
1983 #->1 : next resume displays coreid 1 to GDB
1984 > resume
1985 > cortex_a smp_gdb
1986 gdb coreid 1 -> 1
1987 #1 :coreid 1 is displayed to GDB ,
1988 #->1 : next resume displays coreid 1 to GDB
1989 > cortex_a smp_gdb -1
1990 gdb coreid 1 -> -1
1991 #1 :coreid 1 is displayed to GDB,
1992 #->-1 : next resume triggers a real resume
1993 @end example
1996 @subsection Chip Reset Setup
1998 As a rule, you should put the @command{reset_config} command
1999 into the board file. Most things you think you know about a
2000 chip can be tweaked by the board.
2002 Some chips have specific ways the TRST and SRST signals are
2003 managed. In the unusual case that these are @emph{chip specific}
2004 and can never be changed by board wiring, they could go here.
2005 For example, some chips can't support JTAG debugging without
2006 both signals.
2008 Provide a @code{reset-assert} event handler if you can.
2009 Such a handler uses JTAG operations to reset the target,
2010 letting this target config be used in systems which don't
2011 provide the optional SRST signal, or on systems where you
2012 don't want to reset all targets at once.
2013 Such a handler might write to chip registers to force a reset,
2014 use a JRC to do that (preferable -- the target may be wedged!),
2015 or force a watchdog timer to trigger.
2016 (For Cortex-M targets, this is not necessary. The target
2017 driver knows how to use trigger an NVIC reset when SRST is
2018 not available.)
2020 Some chips need special attention during reset handling if
2021 they're going to be used with JTAG.
2022 An example might be needing to send some commands right
2023 after the target's TAP has been reset, providing a
2024 @code{reset-deassert-post} event handler that writes a chip
2025 register to report that JTAG debugging is being done.
2026 Another would be reconfiguring the watchdog so that it stops
2027 counting while the core is halted in the debugger.
2029 JTAG clocking constraints often change during reset, and in
2030 some cases target config files (rather than board config files)
2031 are the right places to handle some of those issues.
2032 For example, immediately after reset most chips run using a
2033 slower clock than they will use later.
2034 That means that after reset (and potentially, as OpenOCD
2035 first starts up) they must use a slower JTAG clock rate
2036 than they will use later.
2037 @xref{jtagspeed,,JTAG Speed}.
2039 @quotation Important
2040 When you are debugging code that runs right after chip
2041 reset, getting these issues right is critical.
2042 In particular, if you see intermittent failures when
2043 OpenOCD verifies the scan chain after reset,
2044 look at how you are setting up JTAG clocking.
2045 @end quotation
2047 @anchor{theinittargetsprocedure}
2048 @subsection The init_targets procedure
2049 @cindex init_targets procedure
2051 Target config files can either be ``linear'' (script executed line-by-line when parsed in
2052 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
2053 procedure called @code{init_targets}, which will be executed when entering run stage
2054 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
2055 Such procedure can be overriden by ``next level'' script (which sources the original).
2056 This concept faciliates code reuse when basic target config files provide generic configuration
2057 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
2058 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
2059 because sourcing them executes every initialization commands they provide.
2061 @example
2062 ### generic_file.cfg ###
2064 proc setup_my_chip @{chip_name flash_size ram_size@} @{
2065 # basic initialization procedure ...
2066 @}
2068 proc init_targets @{@} @{
2069 # initializes generic chip with 4kB of flash and 1kB of RAM
2070 setup_my_chip MY_GENERIC_CHIP 4096 1024
2071 @}
2073 ### specific_file.cfg ###
2075 source [find target/generic_file.cfg]
2077 proc init_targets @{@} @{
2078 # initializes specific chip with 128kB of flash and 64kB of RAM
2079 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
2080 @}
2081 @end example
2083 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
2084 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
2086 For an example of this scheme see LPC2000 target config files.
2088 The @code{init_boards} procedure is a similar concept concerning board config files
2089 (@xref{theinitboardprocedure,,The init_board procedure}.)
2091 @subsection ARM Core Specific Hacks
2093 If the chip has a DCC, enable it. If the chip is an ARM9 with some
2094 special high speed download features - enable it.
2096 If present, the MMU, the MPU and the CACHE should be disabled.
2098 Some ARM cores are equipped with trace support, which permits
2099 examination of the instruction and data bus activity. Trace
2100 activity is controlled through an ``Embedded Trace Module'' (ETM)
2101 on one of the core's scan chains. The ETM emits voluminous data
2102 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
2103 If you are using an external trace port,
2104 configure it in your board config file.
2105 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2106 configure it in your target config file.
2108 @example
2109 etm config $_TARGETNAME 16 normal full etb
2110 etb config $_TARGETNAME $_CHIPNAME.etb
2111 @end example
2113 @subsection Internal Flash Configuration
2115 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2117 @b{Never ever} in the ``target configuration file'' define any type of
2118 flash that is external to the chip. (For example a BOOT flash on
2119 Chip Select 0.) Such flash information goes in a board file - not
2120 the TARGET (chip) file.
2122 Examples:
2123 @itemize @bullet
2124 @item at91sam7x256 - has 256K flash YES enable it.
2125 @item str912 - has flash internal YES enable it.
2126 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2127 @item pxa270 - again - CS0 flash - it goes in the board file.
2128 @end itemize
2130 @anchor{translatingconfigurationfiles}
2131 @section Translating Configuration Files
2132 @cindex translation
2133 If you have a configuration file for another hardware debugger
2134 or toolset (Abatron, BDI2000, BDI3000, CCS,
2135 Lauterbach, Segger, Macraigor, etc.), translating
2136 it into OpenOCD syntax is often quite straightforward. The most tricky
2137 part of creating a configuration script is oftentimes the reset init
2138 sequence where e.g. PLLs, DRAM and the like is set up.
2140 One trick that you can use when translating is to write small
2141 Tcl procedures to translate the syntax into OpenOCD syntax. This
2142 can avoid manual translation errors and make it easier to
2143 convert other scripts later on.
2145 Example of transforming quirky arguments to a simple search and
2146 replace job:
2148 @example
2149 # Lauterbach syntax(?)
2150 #
2151 # Data.Set c15:0x042f %long 0x40000015
2152 #
2153 # OpenOCD syntax when using procedure below.
2154 #
2155 # setc15 0x01 0x00050078
2157 proc setc15 @{regs value@} @{
2158 global TARGETNAME
2160 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2162 arm mcr 15 [expr ($regs>>12)&0x7] \
2163 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2164 [expr ($regs>>8)&0x7] $value
2165 @}
2166 @end example
2170 @node Daemon Configuration
2171 @chapter Daemon Configuration
2172 @cindex initialization
2173 The commands here are commonly found in the openocd.cfg file and are
2174 used to specify what TCP/IP ports are used, and how GDB should be
2175 supported.
2177 @anchor{configurationstage}
2178 @section Configuration Stage
2179 @cindex configuration stage
2180 @cindex config command
2182 When the OpenOCD server process starts up, it enters a
2183 @emph{configuration stage} which is the only time that
2184 certain commands, @emph{configuration commands}, may be issued.
2185 Normally, configuration commands are only available
2186 inside startup scripts.
2188 In this manual, the definition of a configuration command is
2189 presented as a @emph{Config Command}, not as a @emph{Command}
2190 which may be issued interactively.
2191 The runtime @command{help} command also highlights configuration
2192 commands, and those which may be issued at any time.
2194 Those configuration commands include declaration of TAPs,
2195 flash banks,
2196 the interface used for JTAG communication,
2197 and other basic setup.
2198 The server must leave the configuration stage before it
2199 may access or activate TAPs.
2200 After it leaves this stage, configuration commands may no
2201 longer be issued.
2203 @anchor{enteringtherunstage}
2204 @section Entering the Run Stage
2206 The first thing OpenOCD does after leaving the configuration
2207 stage is to verify that it can talk to the scan chain
2208 (list of TAPs) which has been configured.
2209 It will warn if it doesn't find TAPs it expects to find,
2210 or finds TAPs that aren't supposed to be there.
2211 You should see no errors at this point.
2212 If you see errors, resolve them by correcting the
2213 commands you used to configure the server.
2214 Common errors include using an initial JTAG speed that's too
2215 fast, and not providing the right IDCODE values for the TAPs
2216 on the scan chain.
2218 Once OpenOCD has entered the run stage, a number of commands
2219 become available.
2220 A number of these relate to the debug targets you may have declared.
2221 For example, the @command{mww} command will not be available until
2222 a target has been successfuly instantiated.
2223 If you want to use those commands, you may need to force
2224 entry to the run stage.
2226 @deffn {Config Command} init
2227 This command terminates the configuration stage and
2228 enters the run stage. This helps when you need to have
2229 the startup scripts manage tasks such as resetting the target,
2230 programming flash, etc. To reset the CPU upon startup, add "init" and
2231 "reset" at the end of the config script or at the end of the OpenOCD
2232 command line using the @option{-c} command line switch.
2234 If this command does not appear in any startup/configuration file
2235 OpenOCD executes the command for you after processing all
2236 configuration files and/or command line options.
2238 @b{NOTE:} This command normally occurs at or near the end of your
2239 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2240 targets ready. For example: If your openocd.cfg file needs to
2241 read/write memory on your target, @command{init} must occur before
2242 the memory read/write commands. This includes @command{nand probe}.
2243 @end deffn
2245 @deffn {Overridable Procedure} jtag_init
2246 This is invoked at server startup to verify that it can talk
2247 to the scan chain (list of TAPs) which has been configured.
2249 The default implementation first tries @command{jtag arp_init},
2250 which uses only a lightweight JTAG reset before examining the
2251 scan chain.
2252 If that fails, it tries again, using a harder reset
2253 from the overridable procedure @command{init_reset}.
2255 Implementations must have verified the JTAG scan chain before
2256 they return.
2257 This is done by calling @command{jtag arp_init}
2258 (or @command{jtag arp_init-reset}).
2259 @end deffn
2261 @anchor{tcpipports}
2262 @section TCP/IP Ports
2263 @cindex TCP port
2264 @cindex server
2265 @cindex port
2266 @cindex security
2267 The OpenOCD server accepts remote commands in several syntaxes.
2268 Each syntax uses a different TCP/IP port, which you may specify
2269 only during configuration (before those ports are opened).
2271 For reasons including security, you may wish to prevent remote
2272 access using one or more of these ports.
2273 In such cases, just specify the relevant port number as zero.
2274 If you disable all access through TCP/IP, you will need to
2275 use the command line @option{-pipe} option.
2277 @deffn {Command} gdb_port [number]
2278 @cindex GDB server
2279 Normally gdb listens to a TCP/IP port, but GDB can also
2280 communicate via pipes(stdin/out or named pipes). The name
2281 "gdb_port" stuck because it covers probably more than 90% of
2282 the normal use cases.
2284 No arguments reports GDB port. "pipe" means listen to stdin
2285 output to stdout, an integer is base port number, "disable"
2286 disables the gdb server.
2288 When using "pipe", also use log_output to redirect the log
2289 output to a file so as not to flood the stdin/out pipes.
2291 The -p/--pipe option is deprecated and a warning is printed
2292 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2294 Any other string is interpreted as named pipe to listen to.
2295 Output pipe is the same name as input pipe, but with 'o' appended,
2296 e.g. /var/gdb, /var/gdbo.
2298 The GDB port for the first target will be the base port, the
2299 second target will listen on gdb_port + 1, and so on.
2300 When not specified during the configuration stage,
2301 the port @var{number} defaults to 3333.
2302 @end deffn
2304 @deffn {Command} tcl_port [number]
2305 Specify or query the port used for a simplified RPC
2306 connection that can be used by clients to issue TCL commands and get the
2307 output from the Tcl engine.
2308 Intended as a machine interface.
2309 When not specified during the configuration stage,
2310 the port @var{number} defaults to 6666.
2312 @end deffn
2314 @deffn {Command} telnet_port [number]
2315 Specify or query the
2316 port on which to listen for incoming telnet connections.
2317 This port is intended for interaction with one human through TCL commands.
2318 When not specified during the configuration stage,
2319 the port @var{number} defaults to 4444.
2320 When specified as zero, this port is not activated.
2321 @end deffn
2323 @anchor{gdbconfiguration}
2324 @section GDB Configuration
2325 @cindex GDB
2326 @cindex GDB configuration
2327 You can reconfigure some GDB behaviors if needed.
2328 The ones listed here are static and global.
2329 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2330 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2332 @anchor{gdbbreakpointoverride}
2333 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2334 Force breakpoint type for gdb @command{break} commands.
2335 This option supports GDB GUIs which don't
2336 distinguish hard versus soft breakpoints, if the default OpenOCD and
2337 GDB behaviour is not sufficient. GDB normally uses hardware
2338 breakpoints if the memory map has been set up for flash regions.
2339 @end deffn
2341 @anchor{gdbflashprogram}
2342 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2343 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2344 vFlash packet is received.
2345 The default behaviour is @option{enable}.
2346 @end deffn
2348 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2349 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2350 requested. GDB will then know when to set hardware breakpoints, and program flash
2351 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2352 for flash programming to work.
2353 Default behaviour is @option{enable}.
2354 @xref{gdbflashprogram,,gdb_flash_program}.
2355 @end deffn
2357 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2358 Specifies whether data aborts cause an error to be reported
2359 by GDB memory read packets.
2360 The default behaviour is @option{disable};
2361 use @option{enable} see these errors reported.
2362 @end deffn
2364 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2365 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2366 The default behaviour is @option{disable}.
2367 @end deffn
2369 @deffn {Command} gdb_save_tdesc
2370 Saves the target descripton file to the local file system.
2372 The file name is @i{target_name}.xml.
2373 @end deffn
2375 @anchor{eventpolling}
2376 @section Event Polling
2378 Hardware debuggers are parts of asynchronous systems,
2379 where significant events can happen at any time.
2380 The OpenOCD server needs to detect some of these events,
2381 so it can report them to through TCL command line
2382 or to GDB.
2384 Examples of such events include:
2386 @itemize
2387 @item One of the targets can stop running ... maybe it triggers
2388 a code breakpoint or data watchpoint, or halts itself.
2389 @item Messages may be sent over ``debug message'' channels ... many
2390 targets support such messages sent over JTAG,
2391 for receipt by the person debugging or tools.
2392 @item Loss of power ... some adapters can detect these events.
2393 @item Resets not issued through JTAG ... such reset sources
2394 can include button presses or other system hardware, sometimes
2395 including the target itself (perhaps through a watchdog).
2396 @item Debug instrumentation sometimes supports event triggering
2397 such as ``trace buffer full'' (so it can quickly be emptied)
2398 or other signals (to correlate with code behavior).
2399 @end itemize
2401 None of those events are signaled through standard JTAG signals.
2402 However, most conventions for JTAG connectors include voltage
2403 level and system reset (SRST) signal detection.
2404 Some connectors also include instrumentation signals, which
2405 can imply events when those signals are inputs.
2407 In general, OpenOCD needs to periodically check for those events,
2408 either by looking at the status of signals on the JTAG connector
2409 or by sending synchronous ``tell me your status'' JTAG requests
2410 to the various active targets.
2411 There is a command to manage and monitor that polling,
2412 which is normally done in the background.
2414 @deffn Command poll [@option{on}|@option{off}]
2415 Poll the current target for its current state.
2416 (Also, @pxref{targetcurstate,,target curstate}.)
2417 If that target is in debug mode, architecture
2418 specific information about the current state is printed.
2419 An optional parameter
2420 allows background polling to be enabled and disabled.
2422 You could use this from the TCL command shell, or
2423 from GDB using @command{monitor poll} command.
2424 Leave background polling enabled while you're using GDB.
2425 @example
2426 > poll
2427 background polling: on
2428 target state: halted
2429 target halted in ARM state due to debug-request, \
2430 current mode: Supervisor
2431 cpsr: 0x800000d3 pc: 0x11081bfc
2432 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2433 >
2434 @end example
2435 @end deffn
2437 @node Debug Adapter Configuration
2438 @chapter Debug Adapter Configuration
2439 @cindex config file, interface
2440 @cindex interface config file
2442 Correctly installing OpenOCD includes making your operating system give
2443 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2444 are used to select which one is used, and to configure how it is used.
2446 @quotation Note
2447 Because OpenOCD started out with a focus purely on JTAG, you may find
2448 places where it wrongly presumes JTAG is the only transport protocol
2449 in use. Be aware that recent versions of OpenOCD are removing that
2450 limitation. JTAG remains more functional than most other transports.
2451 Other transports do not support boundary scan operations, or may be
2452 specific to a given chip vendor. Some might be usable only for
2453 programming flash memory, instead of also for debugging.
2454 @end quotation
2456 Debug Adapters/Interfaces/Dongles are normally configured
2457 through commands in an interface configuration
2458 file which is sourced by your @file{openocd.cfg} file, or
2459 through a command line @option{-f interface/....cfg} option.
2461 @example
2462 source [find interface/olimex-jtag-tiny.cfg]
2463 @end example
2465 These commands tell
2466 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2467 A few cases are so simple that you only need to say what driver to use:
2469 @example
2470 # jlink interface
2471 interface jlink
2472 @end example
2474 Most adapters need a bit more configuration than that.
2477 @section Interface Configuration
2479 The interface command tells OpenOCD what type of debug adapter you are
2480 using. Depending on the type of adapter, you may need to use one or
2481 more additional commands to further identify or configure the adapter.
2483 @deffn {Config Command} {interface} name
2484 Use the interface driver @var{name} to connect to the
2485 target.
2486 @end deffn
2488 @deffn Command {interface_list}
2489 List the debug adapter drivers that have been built into
2490 the running copy of OpenOCD.
2491 @end deffn
2492 @deffn Command {interface transports} transport_name+
2493 Specifies the transports supported by this debug adapter.
2494 The adapter driver builds-in similar knowledge; use this only
2495 when external configuration (such as jumpering) changes what
2496 the hardware can support.
2497 @end deffn
2501 @deffn Command {adapter_name}
2502 Returns the name of the debug adapter driver being used.
2503 @end deffn
2505 @section Interface Drivers
2507 Each of the interface drivers listed here must be explicitly
2508 enabled when OpenOCD is configured, in order to be made
2509 available at run time.
2511 @deffn {Interface Driver} {amt_jtagaccel}
2512 Amontec Chameleon in its JTAG Accelerator configuration,
2513 connected to a PC's EPP mode parallel port.
2514 This defines some driver-specific commands:
2516 @deffn {Config Command} {parport_port} number
2517 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2518 the number of the @file{/dev/parport} device.
2519 @end deffn
2521 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2522 Displays status of RTCK option.
2523 Optionally sets that option first.
2524 @end deffn
2525 @end deffn
2527 @deffn {Interface Driver} {arm-jtag-ew}
2528 Olimex ARM-JTAG-EW USB adapter
2529 This has one driver-specific command:
2531 @deffn Command {armjtagew_info}
2532 Logs some status
2533 @end deffn
2534 @end deffn
2536 @deffn {Interface Driver} {at91rm9200}
2537 Supports bitbanged JTAG from the local system,
2538 presuming that system is an Atmel AT91rm9200
2539 and a specific set of GPIOs is used.
2540 @c command: at91rm9200_device NAME
2541 @c chooses among list of bit configs ... only one option
2542 @end deffn
2544 @deffn {Interface Driver} {dummy}
2545 A dummy software-only driver for debugging.
2546 @end deffn
2548 @deffn {Interface Driver} {ep93xx}
2549 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2550 @end deffn
2552 @deffn {Interface Driver} {ft2232}
2553 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2555 Note that this driver has several flaws and the @command{ftdi} driver is
2556 recommended as its replacement.
2558 These interfaces have several commands, used to configure the driver
2559 before initializing the JTAG scan chain:
2561 @deffn {Config Command} {ft2232_device_desc} description
2562 Provides the USB device description (the @emph{iProduct string})
2563 of the FTDI FT2232 device. If not
2564 specified, the FTDI default value is used. This setting is only valid
2565 if compiled with FTD2XX support.
2566 @end deffn
2568 @deffn {Config Command} {ft2232_serial} serial-number
2569 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2570 in case the vendor provides unique IDs and more than one FT2232 device
2571 is connected to the host.
2572 If not specified, serial numbers are not considered.
2573 (Note that USB serial numbers can be arbitrary Unicode strings,
2574 and are not restricted to containing only decimal digits.)
2575 @end deffn
2577 @deffn {Config Command} {ft2232_layout} name
2578 Each vendor's FT2232 device can use different GPIO signals
2579 to control output-enables, reset signals, and LEDs.
2580 Currently valid layout @var{name} values include:
2581 @itemize @minus
2582 @item @b{axm0432_jtag} Axiom AXM-0432
2583 @item @b{comstick} Hitex STR9 comstick
2584 @item @b{cortino} Hitex Cortino JTAG interface
2585 @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
2586 either for the local Cortex-M3 (SRST only)
2587 or in a passthrough mode (neither SRST nor TRST)
2588 This layout can not support the SWO trace mechanism, and should be
2589 used only for older boards (before rev C).
2590 @item @b{luminary_icdi} This layout should be used with most TI/Luminary
2591 eval boards, including Rev C LM3S811 eval boards and the eponymous
2592 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2593 to debug some other target. It can support the SWO trace mechanism.
2594 @item @b{flyswatter} Tin Can Tools Flyswatter
2595 @item @b{icebear} ICEbear JTAG adapter from Section 5
2596 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2597 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2598 @item @b{m5960} American Microsystems M5960
2599 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2600 @item @b{oocdlink} OOCDLink
2601 @c oocdlink ~= jtagkey_prototype_v1
2602 @item @b{redbee-econotag} Integrated with a Redbee development board.
2603 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2604 @item @b{sheevaplug} Marvell Sheevaplug development kit
2605 @item @b{signalyzer} Xverve Signalyzer
2606 @item @b{stm32stick} Hitex STM32 Performance Stick
2607 @item @b{turtelizer2} egnite Software turtelizer2
2608 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2609 @end itemize
2610 @end deffn
2612 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2613 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2614 default values are used.
2615 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2616 @example
2617 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2618 @end example
2619 @end deffn
2621 @deffn {Config Command} {ft2232_latency} ms
2622 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2623 ft2232_read() fails to return the expected number of bytes. This can be caused by
2624 USB communication delays and has proved hard to reproduce and debug. Setting the
2625 FT2232 latency timer to a larger value increases delays for short USB packets but it
2626 also reduces the risk of timeouts before receiving the expected number of bytes.
2627 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2628 @end deffn
2630 @deffn {Config Command} {ft2232_channel} channel
2631 Used to select the channel of the ft2232 chip to use (between 1 and 4).
2632 The default value is 1.
2633 @end deffn
2635 For example, the interface config file for a
2636 Turtelizer JTAG Adapter looks something like this:
2638 @example
2639 interface ft2232
2640 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2641 ft2232_layout turtelizer2
2642 ft2232_vid_pid 0x0403 0xbdc8
2643 @end example
2644 @end deffn
2646 @deffn {Interface Driver} {ftdi}
2647 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2648 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2649 It is a complete rewrite to address a large number of problems with the ft2232
2650 interface driver.
2652 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2653 bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
2654 consistently faster than the ft2232 driver, sometimes several times faster.
2656 A major improvement of this driver is that support for new FTDI based adapters
2657 can be added competely through configuration files, without the need to patch
2658 and rebuild OpenOCD.
2660 The driver uses a signal abstraction to enable Tcl configuration files to
2661 define outputs for one or several FTDI GPIO. These outputs can then be
2662 controlled using the @command{ftdi_set_signal} command. Special signal names
2663 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2664 will be used for their customary purpose.
2666 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2667 be controlled differently. In order to support tristateable signals such as
2668 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2669 signal. The following output buffer configurations are supported:
2671 @itemize @minus
2672 @item Push-pull with one FTDI output as (non-)inverted data line
2673 @item Open drain with one FTDI output as (non-)inverted output-enable
2674 @item Tristate with one FTDI output as (non-)inverted data line and another
2675 FTDI output as (non-)inverted output-enable
2676 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2677 switching data and direction as necessary
2678 @end itemize
2680 These interfaces have several commands, used to configure the driver
2681 before initializing the JTAG scan chain:
2683 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2684 The vendor ID and product ID of the adapter. If not specified, the FTDI
2685 default values are used.
2686 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2687 @example
2688 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2689 @end example
2690 @end deffn
2692 @deffn {Config Command} {ftdi_device_desc} description
2693 Provides the USB device description (the @emph{iProduct string})
2694 of the adapter. If not specified, the device description is ignored
2695 during device selection.
2696 @end deffn
2698 @deffn {Config Command} {ftdi_serial} serial-number
2699 Specifies the @var{serial-number} of the adapter to use,
2700 in case the vendor provides unique IDs and more than one adapter
2701 is connected to the host.
2702 If not specified, serial numbers are not considered.
2703 (Note that USB serial numbers can be arbitrary Unicode strings,
2704 and are not restricted to containing only decimal digits.)
2705 @end deffn
2707 @deffn {Config Command} {ftdi_channel} channel
2708 Selects the channel of the FTDI device to use for MPSSE operations. Most
2709 adapters use the default, channel 0, but there are exceptions.
2710 @end deffn
2712 @deffn {Config Command} {ftdi_layout_init} data direction
2713 Specifies the initial values of the FTDI GPIO data and direction registers.
2714 Each value is a 16-bit number corresponding to the concatenation of the high
2715 and low FTDI GPIO registers. The values should be selected based on the
2716 schematics of the adapter, such that all signals are set to safe levels with
2717 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2718 and initially asserted reset signals.
2719 @end deffn
2721 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask]
2722 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2723 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2724 register bitmasks to tell the driver the connection and type of the output
2725 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2726 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2727 used with inverting data inputs and @option{-data} with non-inverting inputs.
2728 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2729 not-output-enable) input to the output buffer is connected.
2731 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2732 simple open-collector transistor driver would be specified with @option{-oe}
2733 only. In that case the signal can only be set to drive low or to Hi-Z and the
2734 driver will complain if the signal is set to drive high. Which means that if
2735 it's a reset signal, @command{reset_config} must be specified as
2736 @option{srst_open_drain}, not @option{srst_push_pull}.
2738 A special case is provided when @option{-data} and @option{-oe} is set to the
2739 same bitmask. Then the FTDI pin is considered being connected straight to the
2740 target without any buffer. The FTDI pin is then switched between output and
2741 input as necessary to provide the full set of low, high and Hi-Z
2742 characteristics. In all other cases, the pins specified in a signal definition
2743 are always driven by the FTDI.
2744 @end deffn
2746 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2747 Set a previously defined signal to the specified level.
2748 @itemize @minus
2749 @item @option{0}, drive low
2750 @item @option{1}, drive high
2751 @item @option{z}, set to high-impedance
2752 @end itemize
2753 @end deffn
2755 For example adapter definitions, see the configuration files shipped in the
2756 @file{interface/ftdi} directory.
2757 @end deffn
2759 @deffn {Interface Driver} {remote_bitbang}
2760 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2761 with a remote process and sends ASCII encoded bitbang requests to that process
2762 instead of directly driving JTAG.
2764 The remote_bitbang driver is useful for debugging software running on
2765 processors which are being simulated.
2767 @deffn {Config Command} {remote_bitbang_port} number
2768 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2769 sockets instead of TCP.
2770 @end deffn
2772 @deffn {Config Command} {remote_bitbang_host} hostname
2773 Specifies the hostname of the remote process to connect to using TCP, or the
2774 name of the UNIX socket to use if remote_bitbang_port is 0.
2775 @end deffn
2777 For example, to connect remotely via TCP to the host foobar you might have
2778 something like:
2780 @example
2781 interface remote_bitbang
2782 remote_bitbang_port 3335
2783 remote_bitbang_host foobar
2784 @end example
2786 To connect to another process running locally via UNIX sockets with socket
2787 named mysocket:
2789 @example
2790 interface remote_bitbang
2791 remote_bitbang_port 0
2792 remote_bitbang_host mysocket
2793 @end example
2794 @end deffn
2796 @deffn {Interface Driver} {usb_blaster}
2797 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2798 for FTDI chips. These interfaces have several commands, used to
2799 configure the driver before initializing the JTAG scan chain:
2801 @deffn {Config Command} {usb_blaster_device_desc} description
2802 Provides the USB device description (the @emph{iProduct string})
2803 of the FTDI FT245 device. If not
2804 specified, the FTDI default value is used. This setting is only valid
2805 if compiled with FTD2XX support.
2806 @end deffn
2808 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2809 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2810 default values are used.
2811 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2812 Altera USB-Blaster (default):
2813 @example
2814 usb_blaster_vid_pid 0x09FB 0x6001
2815 @end example
2816 The following VID/PID is for Kolja Waschk's USB JTAG:
2817 @example
2818 usb_blaster_vid_pid 0x16C0 0x06AD
2819 @end example
2820 @end deffn
2822 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2823 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2824 female JTAG header). These pins can be used as SRST and/or TRST provided the
2825 appropriate connections are made on the target board.
2827 For example, to use pin 6 as SRST (as with an AVR board):
2828 @example
2829 $_TARGETNAME configure -event reset-assert \
2830 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2831 @end example
2832 @end deffn
2834 @end deffn
2836 @deffn {Interface Driver} {gw16012}
2837 Gateworks GW16012 JTAG programmer.
2838 This has one driver-specific command:
2840 @deffn {Config Command} {parport_port} [port_number]
2841 Display either the address of the I/O port
2842 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2843 If a parameter is provided, first switch to use that port.
2844 This is a write-once setting.
2845 @end deffn
2846 @end deffn
2848 @deffn {Interface Driver} {jlink}
2849 Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
2851 @quotation Compatibility Note
2852 Segger released many firmware versions for the many harware versions they
2853 produced. OpenOCD was extensively tested and intended to run on all of them,
2854 but some combinations were reported as incompatible. As a general
2855 recommendation, it is advisable to use the latest firmware version
2856 available for each hardware version. However the current V8 is a moving
2857 target, and Segger firmware versions released after the OpenOCD was
2858 released may not be compatible. In such cases it is recommended to
2859 revert to the last known functional version. For 0.5.0, this is from
2860 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2861 version is from "May 3 2012 18:36:22", packed with 4.46f.
2862 @end quotation
2864 @deffn {Command} {jlink caps}
2865 Display the device firmware capabilities.
2866 @end deffn
2867 @deffn {Command} {jlink info}
2868 Display various device information, like hardware version, firmware version, current bus status.
2869 @end deffn
2870 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2871 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2872 @end deffn
2873 @deffn {Command} {jlink config}
2874 Display the J-Link configuration.
2875 @end deffn
2876 @deffn {Command} {jlink config kickstart} [val]
2877 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2878 @end deffn
2879 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2880 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2881 @end deffn
2882 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2883 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2884 E the bit of the subnet mask and
2885 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2886 @end deffn
2887 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2888 Set the USB address; this will also change the product id. Without argument, show the USB address.
2889 @end deffn
2890 @deffn {Command} {jlink config reset}
2891 Reset the current configuration.
2892 @end deffn
2893 @deffn {Command} {jlink config save}
2894 Save the current configuration to the internal persistent storage.
2895 @end deffn
2896 @deffn {Config} {jlink pid} val
2897 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2898 @end deffn
2899 @end deffn
2901 @deffn {Interface Driver} {parport}
2902 Supports PC parallel port bit-banging cables:
2903 Wigglers, PLD download cable, and more.
2904 These interfaces have several commands, used to configure the driver
2905 before initializing the JTAG scan chain:
2907 @deffn {Config Command} {parport_cable} name
2908 Set the layout of the parallel port cable used to connect to the target.
2909 This is a write-once setting.
2910 Currently valid cable @var{name} values include:
2912 @itemize @minus
2913 @item @b{altium} Altium Universal JTAG cable.
2914 @item @b{arm-jtag} Same as original wiggler except SRST and
2915 TRST connections reversed and TRST is also inverted.
2916 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2917 in configuration mode. This is only used to
2918 program the Chameleon itself, not a connected target.
2919 @item @b{dlc5} The Xilinx Parallel cable III.
2920 @item @b{flashlink} The ST Parallel cable.
2921 @item @b{lattice} Lattice ispDOWNLOAD Cable
2922 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2923 some versions of
2924 Amontec's Chameleon Programmer. The new version available from
2925 the website uses the original Wiggler layout ('@var{wiggler}')
2926 @item @b{triton} The parallel port adapter found on the
2927 ``Karo Triton 1 Development Board''.
2928 This is also the layout used by the HollyGates design
2929 (see @uref{}).
2930 @item @b{wiggler} The original Wiggler layout, also supported by
2931 several clones, such as the Olimex ARM-JTAG
2932 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2933 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2934 @end itemize
2935 @end deffn
2937 @deffn {Config Command} {parport_port} [port_number]
2938 Display either the address of the I/O port
2939 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2940 If a parameter is provided, first switch to use that port.
2941 This is a write-once setting.
2943 When using PPDEV to access the parallel port, use the number of the parallel port:
2944 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2945 you may encounter a problem.
2946 @end deffn
2948 @deffn Command {parport_toggling_time} [nanoseconds]
2949 Displays how many nanoseconds the hardware needs to toggle TCK;
2950 the parport driver uses this value to obey the
2951 @command{adapter_khz} configuration.
2952 When the optional @var{nanoseconds} parameter is given,
2953 that setting is changed before displaying the current value.
2955 The default setting should work reasonably well on commodity PC hardware.
2956 However, you may want to calibrate for your specific hardware.
2957 @quotation Tip
2958 To measure the toggling time with a logic analyzer or a digital storage
2959 oscilloscope, follow the procedure below:
2960 @example
2961 > parport_toggling_time 1000
2962 > adapter_khz 500
2963 @end example
2964 This sets the maximum JTAG clock speed of the hardware, but
2965 the actual speed probably deviates from the requested 500 kHz.
2966 Now, measure the time between the two closest spaced TCK transitions.
2967 You can use @command{runtest 1000} or something similar to generate a
2968 large set of samples.
2969 Update the setting to match your measurement:
2970 @example
2971 > parport_toggling_time <measured nanoseconds>
2972 @end example
2973 Now the clock speed will be a better match for @command{adapter_khz rate}
2974 commands given in OpenOCD scripts and event handlers.
2976 You can do something similar with many digital multimeters, but note
2977 that you'll probably need to run the clock continuously for several
2978 seconds before it decides what clock rate to show. Adjust the
2979 toggling time up or down until the measured clock rate is a good
2980 match for the adapter_khz rate you specified; be conservative.
2981 @end quotation
2982 @end deffn
2984 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2985 This will configure the parallel driver to write a known
2986 cable-specific value to the parallel interface on exiting OpenOCD.
2987 @end deffn
2989 For example, the interface configuration file for a
2990 classic ``Wiggler'' cable on LPT2 might look something like this:
2992 @example
2993 interface parport
2994 parport_port 0x278
2995 parport_cable wiggler
2996 @end example
2997 @end deffn
2999 @deffn {Interface Driver} {presto}
3000 ASIX PRESTO USB JTAG programmer.
3001 @deffn {Config Command} {presto_serial} serial_string
3002 Configures the USB serial number of the Presto device to use.
3003 @end deffn
3004 @end deffn
3006 @deffn {Interface Driver} {rlink}
3007 Raisonance RLink USB adapter
3008 @end deffn
3010 @deffn {Interface Driver} {usbprog}
3011 usbprog is a freely programmable USB adapter.
3012 @end deffn
3014 @deffn {Interface Driver} {vsllink}
3015 vsllink is part of Versaloon which is a versatile USB programmer.
3017 @quotation Note
3018 This defines quite a few driver-specific commands,
3019 which are not currently documented here.
3020 @end quotation
3021 @end deffn
3023 @deffn {Interface Driver} {hla}
3024 This is a driver that supports multiple High Level Adapters.
3025 This type of adapter does not expose some of the lower level api's
3026 that OpenOCD would normally use to access the target.
3028 Currently supported adapters include the ST STLINK and TI ICDI.
3030 @deffn {Config Command} {hla_device_desc} description
3031 Currently Not Supported.
3032 @end deffn
3034 @deffn {Config Command} {hla_serial} serial
3035 Currently Not Supported.
3036 @end deffn
3038 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
3039 Specifies the adapter layout to use.
3040 @end deffn
3042 @deffn {Config Command} {hla_vid_pid} vid pid
3043 The vendor ID and product ID of the device.
3044 @end deffn
3046 @deffn {Config Command} {trace} source_clock_hz [output_file_path]
3047 Enable SWO tracing (if supported). The source clock rate for the
3048 trace port must be specified, this is typically the CPU clock rate. If
3049 the optional output file is specified then raw trace data is appended
3050 to the file, and the file is created if it does not exist.
3051 @end deffn
3052 @end deffn
3054 @deffn {Interface Driver} {opendous}
3055 opendous-jtag is a freely programmable USB adapter.
3056 @end deffn
3058 @deffn {Interface Driver} {ulink}
3059 This is the Keil ULINK v1 JTAG debugger.
3060 @end deffn
3062 @deffn {Interface Driver} {ZY1000}
3063 This is the Zylin ZY1000 JTAG debugger.
3064 @end deffn
3066 @quotation Note
3067 This defines some driver-specific commands,
3068 which are not currently documented here.
3069 @end quotation
3071 @deffn Command power [@option{on}|@option{off}]
3072 Turn power switch to target on/off.
3073 No arguments: print status.
3074 @end deffn
3076 @deffn {Interface Driver} {bcm2835gpio}
3077 This SoC is present in Raspberry Pi which is a cheap single-board computer
3078 exposing some GPIOs on its expansion header.
3080 The driver accesses memory-mapped GPIO peripheral registers directly
3081 for maximum performance, but the only possible race condition is for
3082 the pins' modes/muxing (which is highly unlikely), so it should be
3083 able to coexist nicely with both sysfs bitbanging and various
3084 peripherals' kernel drivers. The driver restores the previous
3085 configuration on exit.
3087 See @file{interface/raspberrypi-native.cfg} for a sample config and
3088 pinout.
3090 @end deffn
3092 @section Transport Configuration
3093 @cindex Transport
3094 As noted earlier, depending on the version of OpenOCD you use,
3095 and the debug adapter you are using,
3096 several transports may be available to
3097 communicate with debug targets (or perhaps to program flash memory).
3098 @deffn Command {transport list}
3099 displays the names of the transports supported by this
3100 version of OpenOCD.
3101 @end deffn
3103 @deffn Command {transport select} transport_name
3104 Select which of the supported transports to use in this OpenOCD session.
3105 The transport must be supported by the debug adapter hardware and by the
3106 version of OpenOCD you are using (including the adapter's driver).
3107 No arguments: returns name of session's selected transport.
3108 @end deffn
3110 @subsection JTAG Transport
3111 @cindex JTAG
3112 JTAG is the original transport supported by OpenOCD, and most
3113 of the OpenOCD commands support it.
3114 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3115 each of which must be explicitly declared.
3116 JTAG supports both debugging and boundary scan testing.
3117 Flash programming support is built on top of debug support.
3118 @subsection SWD Transport
3119 @cindex SWD
3120 @cindex Serial Wire Debug
3121 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3122 Debug Access Point (DAP, which must be explicitly declared.
3123 (SWD uses fewer signal wires than JTAG.)
3124 SWD is debug-oriented, and does not support boundary scan testing.
3125 Flash programming support is built on top of debug support.
3126 (Some processors support both JTAG and SWD.)
3127 @deffn Command {swd newdap} ...
3128 Declares a single DAP which uses SWD transport.
3129 Parameters are currently the same as "jtag newtap" but this is
3130 expected to change.
3131 @end deffn
3132 @deffn Command {swd wcr trn prescale}
3133 Updates TRN (turnaraound delay) and prescaling.fields of the
3134 Wire Control Register (WCR).
3135 No parameters: displays current settings.
3136 @end deffn
3138 @subsection SPI Transport
3139 @cindex SPI
3140 @cindex Serial Peripheral Interface
3141 The Serial Peripheral Interface (SPI) is a general purpose transport
3142 which uses four wire signaling. Some processors use it as part of a
3143 solution for flash programming.
3145 @anchor{jtagspeed}
3146 @section JTAG Speed
3147 JTAG clock setup is part of system setup.
3148 It @emph{does not belong with interface setup} since any interface
3149 only knows a few of the constraints for the JTAG clock speed.
3150 Sometimes the JTAG speed is
3151 changed during the target initialization process: (1) slow at
3152 reset, (2) program the CPU clocks, (3) run fast.
3153 Both the "slow" and "fast" clock rates are functions of the
3154 oscillators used, the chip, the board design, and sometimes
3155 power management software that may be active.
3157 The speed used during reset, and the scan chain verification which
3158 follows reset, can be adjusted using a @code{reset-start}
3159 target event handler.
3160 It can then be reconfigured to a faster speed by a
3161 @code{reset-init} target event handler after it reprograms those
3162 CPU clocks, or manually (if something else, such as a boot loader,
3163 sets up those clocks).
3164 @xref{targetevents,,Target Events}.
3165 When the initial low JTAG speed is a chip characteristic, perhaps
3166 because of a required oscillator speed, provide such a handler
3167 in the target config file.
3168 When that speed is a function of a board-specific characteristic
3169 such as which speed oscillator is used, it belongs in the board
3170 config file instead.
3171 In both cases it's safest to also set the initial JTAG clock rate
3172 to that same slow speed, so that OpenOCD never starts up using a
3173 clock speed that's faster than the scan chain can support.
3175 @example
3176 jtag_rclk 3000
3177 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3178 @end example
3180 If your system supports adaptive clocking (RTCK), configuring
3181 JTAG to use that is probably the most robust approach.
3182 However, it introduces delays to synchronize clocks; so it
3183 may not be the fastest solution.
3185 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3186 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3187 which support adaptive clocking.
3189 @deffn {Command} adapter_khz max_speed_kHz
3190 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3191 JTAG interfaces usually support a limited number of
3192 speeds. The speed actually used won't be faster
3193 than the speed specified.
3195 Chip data sheets generally include a top JTAG clock rate.
3196 The actual rate is often a function of a CPU core clock,
3197 and is normally less than that peak rate.
3198 For example, most ARM cores accept at most one sixth of the CPU clock.
3200 Speed 0 (khz) selects RTCK method.
3201 @xref{faqrtck,,FAQ RTCK}.
3202 If your system uses RTCK, you won't need to change the
3203 JTAG clocking after setup.
3204 Not all interfaces, boards, or targets support ``rtck''.
3205 If the interface device can not
3206 support it, an error is returned when you try to use RTCK.
3207 @end deffn
3209 @defun jtag_rclk fallback_speed_kHz
3210 @cindex adaptive clocking
3211 @cindex RTCK
3212 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3213 If that fails (maybe the interface, board, or target doesn't
3214 support it), falls back to the specified frequency.
3215 @example
3216 # Fall back to 3mhz if RTCK is not supported
3217 jtag_rclk 3000
3218 @end example
3219 @end defun
3221 @node Reset Configuration
3222 @chapter Reset Configuration
3223 @cindex Reset Configuration
3225 Every system configuration may require a different reset
3226 configuration. This can also be quite confusing.
3227 Resets also interact with @var{reset-init} event handlers,
3228 which do things like setting up clocks and DRAM, and
3229 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3230 They can also interact with JTAG routers.
3231 Please see the various board files for examples.
3233 @quotation Note
3234 To maintainers and integrators:
3235 Reset configuration touches several things at once.
3236 Normally the board configuration file
3237 should define it and assume that the JTAG adapter supports
3238 everything that's wired up to the board's JTAG connector.
3240 However, the target configuration file could also make note
3241 of something the silicon vendor has done inside the chip,
3242 which will be true for most (or all) boards using that chip.
3243 And when the JTAG adapter doesn't support everything, the
3244 user configuration file will need to override parts of
3245 the reset configuration provided by other files.
3246 @end quotation
3248 @section Types of Reset
3250 There are many kinds of reset possible through JTAG, but
3251 they may not all work with a given board and adapter.
3252 That's part of why reset configuration can be error prone.
3254 @itemize @bullet
3255 @item
3256 @emph{System Reset} ... the @emph{SRST} hardware signal
3257 resets all chips connected to the JTAG adapter, such as processors,
3258 power management chips, and I/O controllers. Normally resets triggered
3259 with this signal behave exactly like pressing a RESET button.
3260 @item
3261 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3262 just the TAP controllers connected to the JTAG adapter.
3263 Such resets should not be visible to the rest of the system; resetting a
3264 device's TAP controller just puts that controller into a known state.
3265 @item
3266 @emph{Emulation Reset} ... many devices can be reset through JTAG
3267 commands. These resets are often distinguishable from system
3268 resets, either explicitly (a "reset reason" register says so)
3269 or implicitly (not all parts of the chip get reset).
3270 @item
3271 @emph{Other Resets} ... system-on-chip devices often support
3272 several other types of reset.
3273 You may need to arrange that a watchdog timer stops
3274 while debugging, preventing a watchdog reset.
3275 There may be individual module resets.
3276 @end itemize
3278 In the best case, OpenOCD can hold SRST, then reset
3279 the TAPs via TRST and send commands through JTAG to halt the
3280 CPU at the reset vector before the 1st instruction is executed.
3281 Then when it finally releases the SRST signal, the system is
3282 halted under debugger control before any code has executed.
3283 This is the behavior required to support the @command{reset halt}
3284 and @command{reset init} commands; after @command{reset init} a
3285 board-specific script might do things like setting up DRAM.
3286 (@xref{resetcommand,,Reset Command}.)
3288 @anchor{srstandtrstissues}
3289 @section SRST and TRST Issues
3291 Because SRST and TRST are hardware signals, they can have a
3292 variety of system-specific constraints. Some of the most
3293 common issues are:
3295 @itemize @bullet
3297 @item @emph{Signal not available} ... Some boards don't wire
3298 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3299 support such signals even if they are wired up.
3300 Use the @command{reset_config} @var{signals} options to say
3301 when either of those signals is not connected.
3302 When SRST is not available, your code might not be able to rely
3303 on controllers having been fully reset during code startup.
3304 Missing TRST is not a problem, since JTAG-level resets can
3305 be triggered using with TMS signaling.
3307 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3308 adapter will connect SRST to TRST, instead of keeping them separate.
3309 Use the @command{reset_config} @var{combination} options to say
3310 when those signals aren't properly independent.
3312 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3313 delay circuit, reset supervisor, or on-chip features can extend
3314 the effect of a JTAG adapter's reset for some time after the adapter
3315 stops issuing the reset. For example, there may be chip or board
3316 requirements that all reset pulses last for at least a
3317 certain amount of time; and reset buttons commonly have
3318 hardware debouncing.
3319 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3320 commands to say when extra delays are needed.
3322 @item @emph{Drive type} ... Reset lines often have a pullup
3323 resistor, letting the JTAG interface treat them as open-drain
3324 signals. But that's not a requirement, so the adapter may need
3325 to use push/pull output drivers.
3326 Also, with weak pullups it may be advisable to drive
3327 signals to both levels (push/pull) to minimize rise times.
3328 Use the @command{reset_config} @var{trst_type} and
3329 @var{srst_type} parameters to say how to drive reset signals.
3331 @item @emph{Special initialization} ... Targets sometimes need
3332 special JTAG initialization sequences to handle chip-specific
3333 issues (not limited to errata).
3334 For example, certain JTAG commands might need to be issued while
3335 the system as a whole is in a reset state (SRST active)
3336 but the JTAG scan chain is usable (TRST inactive).
3337 Many systems treat combined assertion of SRST and TRST as a
3338 trigger for a harder reset than SRST alone.
3339 Such custom reset handling is discussed later in this chapter.
3340 @end itemize
3342 There can also be other issues.
3343 Some devices don't fully conform to the JTAG specifications.
3344 Trivial system-specific differences are common, such as
3345 SRST and TRST using slightly different names.
3346 There are also vendors who distribute key JTAG documentation for
3347 their chips only to developers who have signed a Non-Disclosure
3348 Agreement (NDA).
3350 Sometimes there are chip-specific extensions like a requirement to use
3351 the normally-optional TRST signal (precluding use of JTAG adapters which
3352 don't pass TRST through), or needing extra steps to complete a TAP reset.
3354 In short, SRST and especially TRST handling may be very finicky,
3355 needing to cope with both architecture and board specific constraints.
3357 @section Commands for Handling Resets
3359 @deffn {Command} adapter_nsrst_assert_width milliseconds
3360 Minimum amount of time (in milliseconds) OpenOCD should wait
3361 after asserting nSRST (active-low system reset) before
3362 allowing it to be deasserted.
3363 @end deffn
3365 @deffn {Command} adapter_nsrst_delay milliseconds
3366 How long (in milliseconds) OpenOCD should wait after deasserting
3367 nSRST (active-low system reset) before starting new JTAG operations.
3368 When a board has a reset button connected to SRST line it will
3369 probably have hardware debouncing, implying you should use this.
3370 @end deffn
3372 @deffn {Command} jtag_ntrst_assert_width milliseconds
3373 Minimum amount of time (in milliseconds) OpenOCD should wait
3374 after asserting nTRST (active-low JTAG TAP reset) before
3375 allowing it to be deasserted.
3376 @end deffn
3378 @deffn {Command} jtag_ntrst_delay milliseconds
3379 How long (in milliseconds) OpenOCD should wait after deasserting
3380 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3381 @end deffn
3383 @deffn {Command} reset_config mode_flag ...
3384 This command displays or modifies the reset configuration
3385 of your combination of JTAG board and target in target
3386 configuration scripts.
3388 Information earlier in this section describes the kind of problems
3389 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3390 As a rule this command belongs only in board config files,
3391 describing issues like @emph{board doesn't connect TRST};
3392 or in user config files, addressing limitations derived
3393 from a particular combination of interface and board.
3394 (An unlikely example would be using a TRST-only adapter
3395 with a board that only wires up SRST.)
3397 The @var{mode_flag} options can be specified in any order, but only one
3398 of each type -- @var{signals}, @var{combination}, @var{gates},
3399 @var{trst_type}, @var{srst_type} and @var{connect_type}
3400 -- may be specified at a time.
3401 If you don't provide a new value for a given type, its previous
3402 value (perhaps the default) is unchanged.
3403 For example, this means that you don't need to say anything at all about
3404 TRST just to declare that if the JTAG adapter should want to drive SRST,
3405 it must explicitly be driven high (@option{srst_push_pull}).
3407 @itemize
3408 @item
3409 @var{signals} can specify which of the reset signals are connected.
3410 For example, If the JTAG interface provides SRST, but the board doesn't
3411 connect that signal properly, then OpenOCD can't use it.
3412 Possible values are @option{none} (the default), @option{trst_only},
3413 @option{srst_only} and @option{trst_and_srst}.
3415 @quotation Tip
3416 If your board provides SRST and/or TRST through the JTAG connector,
3417 you must declare that so those signals can be used.
3418 @end quotation
3420 @item
3421 The @var{combination} is an optional value specifying broken reset
3422 signal implementations.
3423 The default behaviour if no option given is @option{separate},
3424 indicating everything behaves normally.
3425 @option{srst_pulls_trst} states that the
3426 test logic is reset together with the reset of the system (e.g. NXP
3427 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3428 the system is reset together with the test logic (only hypothetical, I
3429 haven't seen hardware with such a bug, and can be worked around).
3430 @option{combined} implies both @option{srst_pulls_trst} and
3431 @option{trst_pulls_srst}.
3433 @item
3434 The @var{gates} tokens control flags that describe some cases where
3435 JTAG may be unvailable during reset.
3436 @option{srst_gates_jtag} (default)
3437 indicates that asserting SRST gates the
3438 JTAG clock. This means that no communication can happen on JTAG
3439 while SRST is asserted.
3440 Its converse is @option{srst_nogate}, indicating that JTAG commands
3441 can safely be issued while SRST is active.
3443 @item
3444 The @var{connect_type} tokens control flags that describe some cases where
3445 SRST is asserted while connecting to the target. @option{srst_nogate}
3446 is required to use this option.
3447 @option{connect_deassert_srst} (default)
3448 indicates that SRST will not be asserted while connecting to the target.
3449 Its converse is @option{connect_assert_srst}, indicating that SRST will
3450 be asserted before any target connection.
3451 Only some targets support this feature, STM32 and STR9 are examples.
3452 This feature is useful if you are unable to connect to your target due
3453 to incorrect options byte config or illegal program execution.
3454 @end itemize
3456 The optional @var{trst_type} and @var{srst_type} parameters allow the
3457 driver mode of each reset line to be specified. These values only affect
3458 JTAG interfaces with support for different driver modes, like the Amontec
3459 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3460 relevant signal (TRST or SRST) is not connected.
3462 @itemize
3463 @item
3464 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3465 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3466 Most boards connect this signal to a pulldown, so the JTAG TAPs
3467 never leave reset unless they are hooked up to a JTAG adapter.
3469 @item
3470 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3471 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3472 Most boards connect this signal to a pullup, and allow the
3473 signal to be pulled low by various events including system
3474 powerup and pressing a reset button.
3475 @end itemize
3476 @end deffn
3478 @section Custom Reset Handling
3479 @cindex events
3481 OpenOCD has several ways to help support the various reset
3482 mechanisms provided by chip and board vendors.
3483 The commands shown in the previous section give standard parameters.
3484 There are also @emph{event handlers} associated with TAPs or Targets.
3485 Those handlers are Tcl procedures you can provide, which are invoked
3486 at particular points in the reset sequence.
3488 @emph{When SRST is not an option} you must set
3489 up a @code{reset-assert} event handler for your target.
3490 For example, some JTAG adapters don't include the SRST signal;
3491 and some boards have multiple targets, and you won't always
3492 want to reset everything at once.
3494 After configuring those mechanisms, you might still
3495 find your board doesn't start up or reset correctly.
3496 For example, maybe it needs a slightly different sequence
3497 of SRST and/or TRST manipulations, because of quirks that
3498 the @command{reset_config} mechanism doesn't address;
3499 or asserting both might trigger a stronger reset, which
3500 needs special attention.
3502 Experiment with lower level operations, such as @command{jtag_reset}
3503 and the @command{jtag arp_*} operations shown here,
3504 to find a sequence of operations that works.
3505 @xref{JTAG Commands}.
3506 When you find a working sequence, it can be used to override
3507 @command{jtag_init}, which fires during OpenOCD startup
3508 (@pxref{configurationstage,,Configuration Stage});
3509 or @command{init_reset}, which fires during reset processing.
3511 You might also want to provide some project-specific reset
3512 schemes. For example, on a multi-target board the standard
3513 @command{reset} command would reset all targets, but you
3514 may need the ability to reset only one target at time and
3515 thus want to avoid using the board-wide SRST signal.
3517 @deffn {Overridable Procedure} init_reset mode
3518 This is invoked near the beginning of the @command{reset} command,
3519 usually to provide as much of a cold (power-up) reset as practical.
3520 By default it is also invoked from @command{jtag_init} if
3521 the scan chain does not respond to pure JTAG operations.
3522 The @var{mode} parameter is the parameter given to the
3523 low level reset command (@option{halt},
3524 @option{init}, or @option{run}), @option{setup},
3525 or potentially some other value.
3527 The default implementation just invokes @command{jtag arp_init-reset}.
3528 Replacements will normally build on low level JTAG
3529 operations such as @command{jtag_reset}.
3530 Operations here must not address individual TAPs
3531 (or their associated targets)
3532 until the JTAG scan chain has first been verified to work.
3534 Implementations must have verified the JTAG scan chain before
3535 they return.
3536 This is done by calling @command{jtag arp_init}
3537 (or @command{jtag arp_init-reset}).
3538 @end deffn
3540 @deffn Command {jtag arp_init}
3541 This validates the scan chain using just the four
3542 standard JTAG signals (TMS, TCK, TDI, TDO).
3543 It starts by issuing a JTAG-only reset.
3544 Then it performs checks to verify that the scan chain configuration
3545 matches the TAPs it can observe.
3546 Those checks include checking IDCODE values for each active TAP,
3547 and verifying the length of their instruction registers using
3548 TAP @code{-ircapture} and @code{-irmask} values.
3549 If these tests all pass, TAP @code{setup} events are
3550 issued to all TAPs with handlers for that event.
3551 @end deffn
3553 @deffn Command {jtag arp_init-reset}
3554 This uses TRST and SRST to try resetting
3555 everything on the JTAG scan chain
3556 (and anything else connected to SRST).
3557 It then invokes the logic of @command{jtag arp_init}.
3558 @end deffn
3561 @node TAP Declaration
3562 @chapter TAP Declaration
3563 @cindex TAP declaration
3564 @cindex TAP configuration
3566 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3567 TAPs serve many roles, including:
3569 @itemize @bullet
3570 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
3571 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3572 Others do it indirectly, making a CPU do it.
3573 @item @b{Program Download} Using the same CPU support GDB uses,
3574 you can initialize a DRAM controller, download code to DRAM, and then
3575 start running that code.
3576 @item @b{Boundary Scan} Most chips support boundary scan, which
3577 helps test for board assembly problems like solder bridges
3578 and missing connections
3579 @end itemize
3581 OpenOCD must know about the active TAPs on your board(s).
3582 Setting up the TAPs is the core task of your configuration files.
3583 Once those TAPs are set up, you can pass their names to code
3584 which sets up CPUs and exports them as GDB targets,
3585 probes flash memory, performs low-level JTAG operations, and more.
3587 @section Scan Chains
3588 @cindex scan chain
3590 TAPs are part of a hardware @dfn{scan chain},
3591 which is daisy chain of TAPs.
3592 They also need to be added to
3593 OpenOCD's software mirror of that hardware list,
3594 giving each member a name and associating other data with it.
3595 Simple scan chains, with a single TAP, are common in
3596 systems with a single microcontroller or microprocessor.
3597 More complex chips may have several TAPs internally.
3598 Very complex scan chains might have a dozen or more TAPs:
3599 several in one chip, more in the next, and connecting
3600 to other boards with their own chips and TAPs.
3602 You can display the list with the @command{scan_chain} command.
3603 (Don't confuse this with the list displayed by the @command{targets}
3604 command, presented in the next chapter.
3605 That only displays TAPs for CPUs which are configured as
3606 debugging targets.)
3607 Here's what the scan chain might look like for a chip more than one TAP:
3609 @verbatim
3610 TapName Enabled IdCode Expected IrLen IrCap IrMask
3611 -- ------------------ ------- ---------- ---------- ----- ----- ------
3612 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3613 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3614 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3615 @end verbatim
3617 OpenOCD can detect some of that information, but not all
3618 of it. @xref{autoprobing,,Autoprobing}.
3619 Unfortunately those TAPs can't always be autoconfigured,
3620 because not all devices provide good support for that.
3621 JTAG doesn't require supporting IDCODE instructions, and
3622 chips with JTAG routers may not link TAPs into the chain
3623 until they are told to do so.
3625 The configuration mechanism currently supported by OpenOCD
3626 requires explicit configuration of all TAP devices using
3627 @command{jtag newtap} commands, as detailed later in this chapter.
3628 A command like this would declare one tap and name it @code{chip1.cpu}:
3630 @example
3631 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3632 @end example
3634 Each target configuration file lists the TAPs provided
3635 by a given chip.
3636 Board configuration files combine all the targets on a board,
3637 and so forth.
3638 Note that @emph{the order in which TAPs are declared is very important.}
3639 It must match the order in the JTAG scan chain, both inside
3640 a single chip and between them.
3641 @xref{faqtaporder,,FAQ TAP Order}.
3643 For example, the ST Microsystems STR912 chip has
3644 three separate TAPs@footnote{See the ST
3645 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3646 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3647 @url{}}.
3648 To configure those taps, @file{target/str912.cfg}
3649 includes commands something like this:
3651 @example
3652 jtag newtap str912 flash ... params ...
3653 jtag newtap str912 cpu ... params ...
3654 jtag newtap str912 bs ... params ...
3655 @end example
3657 Actual config files use a variable instead of literals like
3658 @option{str912}, to support more than one chip of each type.
3659 @xref{Config File Guidelines}.
3661 @deffn Command {jtag names}
3662 Returns the names of all current TAPs in the scan chain.
3663 Use @command{jtag cget} or @command{jtag tapisenabled}
3664 to examine attributes and state of each TAP.
3665 @example
3666 foreach t [jtag names] @{
3667 puts [format "TAP: %s\n" $t]
3668 @}
3669 @end example
3670 @end deffn
3672 @deffn Command {scan_chain}
3673 Displays the TAPs in the scan chain configuration,
3674 and their status.
3675 The set of TAPs listed by this command is fixed by
3676 exiting the OpenOCD configuration stage,
3677 but systems with a JTAG router can
3678 enable or disable TAPs dynamically.
3679 @end deffn
3681 @c FIXME! "jtag cget" should be able to return all TAP
3682 @c attributes, like "$target_name cget" does for targets.
3684 @c Probably want "jtag eventlist", and a "tap-reset" event
3685 @c (on entry to RESET state).
3687 @section TAP Names
3688 @cindex dotted name
3690 When TAP objects are declared with @command{jtag newtap},
3691 a @dfn{} is created for the TAP, combining the
3692 name of a module (usually a chip) and a label for the TAP.
3693 For example: @code{xilinx.tap}, @code{str912.flash},
3694 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3695 Many other commands use that to manipulate or
3696 refer to the TAP. For example, CPU configuration uses the
3697 name, as does declaration of NAND or NOR flash banks.
3699 The components of a dotted name should follow ``C'' symbol
3700 name rules: start with an alphabetic character, then numbers
3701 and underscores are OK; while others (including dots!) are not.
3703 @quotation Tip
3704 In older code, JTAG TAPs were numbered from 0..N.
3705 This feature is still present.
3706 However its use is highly discouraged, and
3707 should not be relied on; it will be removed by mid-2010.
3708 Update all of your scripts to use TAP names rather than numbers,
3709 by paying attention to the runtime warnings they trigger.
3710 Using TAP numbers in target configuration scripts prevents
3711 reusing those scripts on boards with multiple targets.
3712 @end quotation
3714 @section TAP Declaration Commands
3716 @c shouldn't this be(come) a {Config Command}?
3717 @deffn Command {jtag newtap} chipname tapname configparams...
3718 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3719 and configured according to the various @var{configparams}.
3721 The @var{chipname} is a symbolic name for the chip.
3722 Conventionally target config files use @code{$_CHIPNAME},
3723 defaulting to the model name given by the chip vendor but
3724 overridable.
3726 @cindex TAP naming convention
3727 The @var{tapname} reflects the role of that TAP,
3728 and should follow this convention:
3730 @itemize @bullet
3731 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3732 @item @code{cpu} -- The main CPU of the chip, alternatively
3733 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3734 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3735 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3736 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3737 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3738 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3739 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3740 with a single TAP;
3741 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3742 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3743 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3744 a JTAG TAP; that TAP should be named @code{sdma}.
3745 @end itemize
3747 Every TAP requires at least the following @var{configparams}:
3749 @itemize @bullet
3750 @item @code{-irlen} @var{NUMBER}
3751 @*The length in bits of the
3752 instruction register, such as 4 or 5 bits.
3753 @end itemize
3755 A TAP may also provide optional @var{configparams}:
3757 @itemize @bullet
3758 @item @code{-disable} (or @code{-enable})
3759 @*Use the @code{-disable} parameter to flag a TAP which is not
3760 linked in to the scan chain after a reset using either TRST
3761 or the JTAG state machine's @sc{reset} state.
3762 You may use @code{-enable} to highlight the default state
3763 (the TAP is linked in).
3764 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3765 @item @code{-expected-id} @var{number}
3766 @*A non-zero @var{number} represents a 32-bit IDCODE
3767 which you expect to find when the scan chain is examined.
3768 These codes are not required by all JTAG devices.
3769 @emph{Repeat the option} as many times as required if more than one
3770 ID code could appear (for example, multiple versions).
3771 Specify @var{number} as zero to suppress warnings about IDCODE
3772 values that were found but not included in the list.
3774 Provide this value if at all possible, since it lets OpenOCD
3775 tell when the scan chain it sees isn't right. These values
3776 are provided in vendors' chip documentation, usually a technical
3777 reference manual. Sometimes you may need to probe the JTAG
3778 hardware to find these values.
3779 @xref{autoprobing,,Autoprobing}.
3780 @item @code{-ignore-version}
3781 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3782 option. When vendors put out multiple versions of a chip, or use the same
3783 JTAG-level ID for several largely-compatible chips, it may be more practical
3784 to ignore the version field than to update config files to handle all of
3785 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3786 @item @code{-ircapture} @var{NUMBER}
3787 @*The bit pattern loaded by the TAP into the JTAG shift register
3788 on entry to the @sc{ircapture} state, such as 0x01.
3789 JTAG requires the two LSBs of this value to be 01.
3790 By default, @code{-ircapture} and @code{-irmask} are set
3791 up to verify that two-bit value. You may provide
3792 additional bits, if you know them, or indicate that
3793 a TAP doesn't conform to the JTAG specification.
3794 @item @code{-irmask} @var{NUMBER}
3795 @*A mask used with @code{-ircapture}
3796 to verify that instruction scans work correctly.
3797 Such scans are not used by OpenOCD except to verify that
3798 there seems to be no problems with JTAG scan chain operations.
3799 @end itemize
3800 @end deffn
3802 @section Other TAP commands
3804 @deffn Command {jtag cget} @option{-event} name
3805 @deffnx Command {jtag configure} @option{-event} name string
3806 At this writing this TAP attribute
3807 mechanism is used only for event handling.
3808 (It is not a direct analogue of the @code{cget}/@code{configure}
3809 mechanism for debugger targets.)
3810 See the next section for information about the available events.
3812 The @code{configure} subcommand assigns an event handler,
3813 a TCL string which is evaluated when the event is triggered.
3814 The @code{cget} subcommand returns that handler.
3815 @end deffn
3817 @section TAP Events
3818 @cindex events
3819 @cindex TAP events
3821 OpenOCD includes two event mechanisms.
3822 The one presented here applies to all JTAG TAPs.
3823 The other applies to debugger targets,
3824 which are associated with certain TAPs.
3826 The TAP events currently defined are:
3828 @itemize @bullet
3829 @item @b{post-reset}
3830 @* The TAP has just completed a JTAG reset.
3831 The tap may still be in the JTAG @sc{reset} state.
3832 Handlers for these events might perform initialization sequences
3833 such as issuing TCK cycles, TMS sequences to ensure
3834 exit from the ARM SWD mode, and more.
3836 Because the scan chain has not yet been verified, handlers for these events
3837 @emph{should not issue commands which scan the JTAG IR or DR registers}
3838 of any particular target.
3839 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3840 @item @b{setup}
3841 @* The scan chain has been reset and verified.
3842 This handler may enable TAPs as needed.
3843 @item @b{tap-disable}
3844 @* The TAP needs to be disabled. This handler should
3845 implement @command{jtag tapdisable}
3846 by issuing the relevant JTAG commands.
3847 @item @b{tap-enable}
3848 @* The TAP needs to be enabled. This handler should
3849 implement @command{jtag tapenable}
3850 by issuing the relevant JTAG commands.
3851 @end itemize
3853 If you need some action after each JTAG reset, which isn't actually
3854 specific to any TAP (since you can't yet trust the scan chain's
3855 contents to be accurate), you might:
3857 @example
3858 jtag configure CHIP.jrc -event post-reset @{
3859 echo "JTAG Reset done"
3860 ... non-scan jtag operations to be done after reset
3861 @}
3862 @end example
3865 @anchor{enablinganddisablingtaps}
3866 @section Enabling and Disabling TAPs
3867 @cindex JTAG Route Controller
3868 @cindex jrc
3870 In some systems, a @dfn{JTAG Route Controller} (JRC)
3871 is used to enable and/or disable specific JTAG TAPs.
3872 Many ARM based chips from Texas Instruments include
3873 an ``ICEpick'' module, which is a JRC.
3874 Such chips include DaVinci and OMAP3 processors.
3876 A given TAP may not be visible until the JRC has been
3877 told to link it into the scan chain; and if the JRC
3878 has been told to unlink that TAP, it will no longer
3879 be visible.
3880 Such routers address problems that JTAG ``bypass mode''
3881 ignores, such as:
3883 @itemize
3884 @item The scan chain can only go as fast as its slowest TAP.
3885 @item Having many TAPs slows instruction scans, since all
3886 TAPs receive new instructions.
3887 @item TAPs in the scan chain must be powered up, which wastes
3888 power and prevents debugging some power management mechanisms.
3889 @end itemize
3891 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3892 as implied by the existence of JTAG routers.
3893 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3894 does include a kind of JTAG router functionality.
3896 @c (a) currently the event handlers don't seem to be able to
3897 @c fail in a way that could lead to no-change-of-state.
3899 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3900 shown below, and is implemented using TAP event handlers.
3901 So for example, when defining a TAP for a CPU connected to
3902 a JTAG router, your @file{target.cfg} file
3903 should define TAP event handlers using
3904 code that looks something like this:
3906 @example
3907 jtag configure CHIP.cpu -event tap-enable @{
3908 ... jtag operations using CHIP.jrc
3909 @}
3910 jtag configure CHIP.cpu -event tap-disable @{
3911 ... jtag operations using CHIP.jrc
3912 @}
3913 @end example
3915 Then you might want that CPU's TAP enabled almost all the time:
3917 @example
3918 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3919 @end example
3921 Note how that particular setup event handler declaration
3922 uses quotes to evaluate @code{$CHIP} when the event is configured.
3923 Using brackets @{ @} would cause it to be evaluated later,
3924 at runtime, when it might have a different value.
3926 @deffn Command {jtag tapdisable}
3927 If necessary, disables the tap
3928 by sending it a @option{tap-disable} event.
3929 Returns the string "1" if the tap
3930 specified by @var{} is enabled,
3931 and "0" if it is disabled.
3932 @end deffn
3934 @deffn Command {jtag tapenable}
3935 If necessary, enables the tap
3936 by sending it a @option{tap-enable} event.
3937 Returns the string "1" if the tap
3938 specified by @var{} is enabled,
3939 and "0" if it is disabled.
3940 @end deffn
3942 @deffn Command {jtag tapisenabled}
3943 Returns the string "1" if the tap
3944 specified by @var{} is enabled,
3945 and "0" if it is disabled.
3947 @quotation Note
3948 Humans will find the @command{scan_chain} command more helpful
3949 for querying the state of the JTAG taps.
3950 @end quotation
3951 @end deffn
3953 @anchor{autoprobing}
3954 @section Autoprobing
3955 @cindex autoprobe
3956 @cindex JTAG autoprobe
3958 TAP configuration is the first thing that needs to be done
3959 after interface and reset configuration. Sometimes it's
3960 hard finding out what TAPs exist, or how they are identified.
3961 Vendor documentation is not always easy to find and use.
3963 To help you get past such problems, OpenOCD has a limited
3964 @emph{autoprobing} ability to look at the scan chain, doing
3965 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3966 To use this mechanism, start the OpenOCD server with only data
3967 that configures your JTAG interface, and arranges to come up
3968 with a slow clock (many devices don't support fast JTAG clocks
3969 right when they come out of reset).
3971 For example, your @file{openocd.cfg} file might have:
3973 @example
3974 source [find interface/olimex-arm-usb-tiny-h.cfg]
3975 reset_config trst_and_srst
3976 jtag_rclk 8
3977 @end example
3979 When you start the server without any TAPs configured, it will
3980 attempt to autoconfigure the TAPs. There are two parts to this:
3982 @enumerate
3983 @item @emph{TAP discovery} ...
3984 After a JTAG reset (sometimes a system reset may be needed too),
3985 each TAP's data registers will hold the contents of either the
3986 IDCODE or BYPASS register.
3987 If JTAG communication is working, OpenOCD will see each TAP,
3988 and report what @option{-expected-id} to use with it.
3989 @item @emph{IR Length discovery} ...
3990 Unfortunately JTAG does not provide a reliable way to find out
3991 the value of the @option{-irlen} parameter to use with a TAP
3992 that is discovered.
3993 If OpenOCD can discover the length of a TAP's instruction
3994 register, it will report it.
3995 Otherwise you may need to consult vendor documentation, such
3996 as chip data sheets or BSDL files.
3997 @end enumerate
3999 In many cases your board will have a simple scan chain with just
4000 a single device. Here's what OpenOCD reported with one board
4001 that's a bit more complex:
4003 @example
4004 clock speed 8 kHz
4005 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4006 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4007 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4008 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4009 AUTO auto0.tap - use "... -irlen 4"
4010 AUTO auto1.tap - use "... -irlen 4"
4011 AUTO auto2.tap - use "... -irlen 6"
4012 no gdb ports allocated as no target has been specified
4013 @end example
4015 Given that information, you should be able to either find some existing
4016 config files to use, or create your own. If you create your own, you
4017 would configure from the bottom up: first a @file{target.cfg} file
4018 with these TAPs, any targets associated with them, and any on-chip
4019 resources; then a @file{board.cfg} with off-chip resources, clocking,
4020 and so forth.
4022 @node CPU Configuration
4023 @chapter CPU Configuration
4024 @cindex GDB target
4026 This chapter discusses how to set up GDB debug targets for CPUs.
4027 You can also access these targets without GDB
4028 (@pxref{Architecture and Core Commands},
4029 and @ref{targetstatehandling,,Target State handling}) and
4030 through various kinds of NAND and NOR flash commands.
4031 If you have multiple CPUs you can have multiple such targets.
4033 We'll start by looking at how to examine the targets you have,
4034 then look at how to add one more target and how to configure it.
4036 @section Target List
4037 @cindex target, current
4038 @cindex target, list
4040 All targets that have been set up are part of a list,
4041 where each member has a name.
4042 That name should normally be the same as the TAP name.
4043 You can display the list with the @command{targets}
4044 (plural!) command.
4045 This display often has only one CPU; here's what it might
4046 look like with more than one:
4047 @verbatim
4048 TargetName Type Endian TapName State
4049 -- ------------------ ---------- ------ ------------------ ------------
4050 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4051 1 MyTarget cortex_m little tap-disabled
4052 @end verbatim
4054 One member of that list is the @dfn{current target}, which
4055 is implicitly referenced by many commands.
4056 It's the one marked with a @code{*} near the target name.
4057 In particular, memory addresses often refer to the address
4058 space seen by that current target.
4059 Commands like @command{mdw} (memory display words)
4060 and @command{flash erase_address} (erase NOR flash blocks)
4061 are examples; and there are many more.
4063 Several commands let you examine the list of targets:
4065 @deffn Command {target count}
4066 @emph{Note: target numbers are deprecated; don't use them.
4067 They will be removed shortly after August 2010, including this command.
4068 Iterate target using @command{target names}, not by counting.}
4070 Returns the number of targets, @math{N}.
4071 The highest numbered target is @math{N - 1}.
4072 @example
4073 set c [target count]
4074 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
4075 # Assuming you have created this function
4076 print_target_details $x
4077 @}
4078 @end example
4079 @end deffn
4081 @deffn Command {target current}
4082 Returns the name of the current target.
4083 @end deffn
4085 @deffn Command {target names}
4086 Lists the names of all current targets in the list.
4087 @example
4088 foreach t [target names] @{
4089 puts [format "Target: %s\n" $t]
4090 @}
4091 @end example
4092 @end deffn
4094 @deffn Command {target number} number
4095 @emph{Note: target numbers are deprecated; don't use them.
4096 They will be removed shortly after August 2010, including this command.}
4098 The list of targets is numbered starting at zero.
4099 This command returns the name of the target at index @var{number}.
4100 @example
4101 set thename [target number $x]
4102 puts [format "Target %d is: %s\n" $x $thename]
4103 @end example
4104 @end deffn
4106 @c yep, "target list" would have been better.
4107 @c plus maybe "target setdefault".
4109 @deffn Command targets [name]
4110 @emph{Note: the name of this command is plural. Other target
4111 command names are singular.}
4113 With no parameter, this command displays a table of all known
4114 targets in a user friendly form.
4116 With a parameter, this command sets the current target to
4117 the given target with the given @var{name}; this is
4118 only relevant on boards which have more than one target.
4119 @end deffn
4121 @section Target CPU Types and Variants
4122 @cindex target type
4123 @cindex CPU type
4124 @cindex CPU variant
4126 Each target has a @dfn{CPU type}, as shown in the output of
4127 the @command{targets} command. You need to specify that type
4128 when calling @command{target create}.
4129 The CPU type indicates more than just the instruction set.
4130 It also indicates how that instruction set is implemented,
4131 what kind of debug support it integrates,
4132 whether it has an MMU (and if so, what kind),
4133 what core-specific commands may be available
4134 (@pxref{Architecture and Core Commands}),
4135 and more.
4137 For some CPU types, OpenOCD also defines @dfn{variants} which
4138 indicate differences that affect their handling.
4139 For example, a particular implementation bug might need to be
4140 worked around in some chip versions.
4142 It's easy to see what target types are supported,
4143 since there's a command to list them.
4144 However, there is currently no way to list what target variants
4145 are supported (other than by reading the OpenOCD source code).
4147 @anchor{targettypes}
4148 @deffn Command {target types}
4149 Lists all supported target types.
4150 At this writing, the supported CPU types and variants are:
4152 @itemize @bullet
4153 @item @code{arm11} -- this is a generation of ARMv6 cores
4154 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4155 @item @code{arm7tdmi} -- this is an ARMv4 core
4156 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4157 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4158 @item @code{arm966e} -- this is an ARMv5 core
4159 @item @code{arm9tdmi} -- this is an ARMv4 core
4160 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4161 (Support for this is preliminary and incomplete.)
4162 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4163 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4164 compact Thumb2 instruction set.
4165 @item @code{dragonite} -- resembles arm966e
4166 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4167 (Support for this is still incomplete.)
4168 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4169 @item @code{feroceon} -- resembles arm926
4170 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
4171 @item @code{xscale} -- this is actually an architecture,
4172 not a CPU type. It is based on the ARMv5 architecture.
4173 There are several variants defined: