doc: replace luminary with TI urls's
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * TFTP:: TFTP
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on:
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
94 @end menu
96 @node About
97 @unnumbered About
98 @cindex about
100 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
101 University of Applied Sciences Augsburg (@uref{}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
104 around the world.
106 @section What is OpenOCD?
107 @cindex TAP
108 @cindex JTAG
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
112 devices.
114 It does so with the assistance of a @dfn{debug adapter}, which is
115 a small hardware module which helps provide the right kind of
116 electrical signaling to the target being debugged. These are
117 required since the debug host (on which OpenOCD runs) won't
118 usually have native support for such signaling, or the connector
119 needed to hook up to the target.
121 Such debug adapters support one or more @dfn{transport} protocols,
122 each of which involves different electrical signaling (and uses
123 different messaging protocols on top of that signaling). There
124 are many types of debug adapter, and little uniformity in what
125 they are called. (There are also product naming differences.)
127 These adapters are sometimes packaged as discrete dongles, which
128 may generically be called @dfn{hardware interface dongles}.
129 Some development boards also integrate them directly, which may
130 let the development board can be directly connected to the debug
131 host over USB (and sometimes also to power it over USB).
133 For example, a @dfn{JTAG Adapter} supports JTAG
134 signaling, and is used to communicate
135 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
136 A @dfn{TAP} is a ``Test Access Port'', a module which processes
137 special instructions and data. TAPs are daisy-chained within and
138 between chips and boards. JTAG supports debugging and boundary
139 scan operations.
141 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
142 signaling to communicate with some newer ARM cores, as well as debug
143 adapters which support both JTAG and SWD transports. SWD only supports
144 debugging, whereas JTAG also supports boundary scan operations.
146 For some chips, there are also @dfn{Programming Adapters} supporting
147 special transports used only to write code to flash memory, without
148 support for on-chip debugging or boundary scan.
149 (At this writing, OpenOCD does not support such non-debug adapters.)
152 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
153 based, parallel port based, and other standalone boxes that run
154 OpenOCD internally. @xref{Debug Adapter Hardware}.
156 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
157 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
158 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
159 debugged via the GDB protocol.
161 @b{Flash Programing:} Flash writing is supported for external CFI
162 compatible NOR flashes (Intel and AMD/Spansion command set) and several
163 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
164 STM32x). Preliminary support for various NAND flash controllers
165 (LPC3180, Orion, S3C24xx, more) controller is included.
167 @section OpenOCD Web Site
169 The OpenOCD web site provides the latest public news from the community:
171 @uref{}
173 @section Latest User's Guide:
175 The user's guide you are now reading may not be the latest one
176 available. A version for more recent code may be available.
177 Its HTML form is published regularly at:
179 @uref{}
181 PDF form is likewise published at:
183 @uref{}
185 @section OpenOCD User's Forum
187 There is an OpenOCD forum (phpBB) hosted by SparkFun,
188 which might be helpful to you. Note that if you want
189 anything to come to the attention of developers, you
190 should post it to the OpenOCD Developer Mailing List
191 instead of this forum.
193 @uref{}
195 @section OpenOCD User's Mailing List
197 The OpenOCD User Mailing List provides the primary means of
198 communication between users:
200 @uref{}
202 @section OpenOCD IRC
204 Support can also be found on irc:
205 @uref{irc://}
207 @node Developers
208 @chapter OpenOCD Developer Resources
209 @cindex developers
211 If you are interested in improving the state of OpenOCD's debugging and
212 testing support, new contributions will be welcome. Motivated developers
213 can produce new target, flash or interface drivers, improve the
214 documentation, as well as more conventional bug fixes and enhancements.
216 The resources in this chapter are available for developers wishing to explore
217 or expand the OpenOCD source code.
219 @section OpenOCD GIT Repository
221 During the 0.3.x release cycle, OpenOCD switched from Subversion to
222 a GIT repository hosted at SourceForge. The repository URL is:
224 @uref{git://}
226 You may prefer to use a mirror and the HTTP protocol:
228 @uref{}
230 With standard GIT tools, use @command{git clone} to initialize
231 a local repository, and @command{git pull} to update it.
232 There are also gitweb pages letting you browse the repository
233 with a web browser, or download arbitrary snapshots without
234 needing a GIT client:
236 @uref{}
238 @uref{}
240 The @file{README} file contains the instructions for building the project
241 from the repository or a snapshot.
243 Developers that want to contribute patches to the OpenOCD system are
244 @b{strongly} encouraged to work against mainline.
245 Patches created against older versions may require additional
246 work from their submitter in order to be updated for newer releases.
248 @section Doxygen Developer Manual
250 During the 0.2.x release cycle, the OpenOCD project began
251 providing a Doxygen reference manual. This document contains more
252 technical information about the software internals, development
253 processes, and similar documentation:
255 @uref{}
257 This document is a work-in-progress, but contributions would be welcome
258 to fill in the gaps. All of the source files are provided in-tree,
259 listed in the Doxyfile configuration in the top of the source tree.
261 @section OpenOCD Developer Mailing List
263 The OpenOCD Developer Mailing List provides the primary means of
264 communication between developers:
266 @uref{}
268 Discuss and submit patches to this list.
269 The @file{HACKING} file contains basic information about how
270 to prepare patches.
272 @section OpenOCD Bug Database
274 During the 0.4.x release cycle the OpenOCD project team began
275 using Trac for its bug database:
277 @uref{}
280 @node Debug Adapter Hardware
281 @chapter Debug Adapter Hardware
282 @cindex dongles
283 @cindex FTDI
284 @cindex wiggler
285 @cindex zy1000
286 @cindex printer port
287 @cindex USB Adapter
288 @cindex RTCK
290 Defined: @b{dongle}: A small device that plugins into a computer and serves as
291 an adapter .... [snip]
293 In the OpenOCD case, this generally refers to @b{a small adapter} that
294 attaches to your computer via USB or the Parallel Printer Port. One
295 exception is the Zylin ZY1000, packaged as a small box you attach via
296 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
297 require any drivers to be installed on the developer PC. It also has
298 a built in web interface. It supports RTCK/RCLK or adaptive clocking
299 and has a built in relay to power cycle targets remotely.
302 @section Choosing a Dongle
304 There are several things you should keep in mind when choosing a dongle.
306 @enumerate
307 @item @b{Transport} Does it support the kind of communication that you need?
308 OpenOCD focusses mostly on JTAG. Your version may also support
309 other ways to communicate with target devices.
310 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
311 Does your dongle support it? You might need a level converter.
312 @item @b{Pinout} What pinout does your target board use?
313 Does your dongle support it? You may be able to use jumper
314 wires, or an "octopus" connector, to convert pinouts.
315 @item @b{Connection} Does your computer have the USB, printer, or
316 Ethernet port needed?
317 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
318 RTCK support? Also known as ``adaptive clocking''
319 @end enumerate
321 @section Stand alone Systems
323 @b{ZY1000} See: @url{} Technically, not a
324 dongle, but a standalone box. The ZY1000 has the advantage that it does
325 not require any drivers installed on the developer PC. It also has
326 a built in web interface. It supports RTCK/RCLK or adaptive clocking
327 and has a built in relay to power cycle targets remotely.
329 @section USB FT2232 Based
331 There are many USB JTAG dongles on the market, many of them are based
332 on a chip from ``Future Technology Devices International'' (FTDI)
333 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
334 See: @url{} for more information.
335 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
336 chips are starting to become available in JTAG adapters. (Adapters
337 using those high speed FT2232H chips may support adaptive clocking.)
339 The FT2232 chips are flexible enough to support some other
340 transport options, such as SWD or the SPI variants used to
341 program some chips. They have two communications channels,
342 and one can be used for a UART adapter at the same time the
343 other one is used to provide a debug adapter.
345 Also, some development boards integrate an FT2232 chip to serve as
346 a built-in low cost debug adapter and usb-to-serial solution.
348 @itemize @bullet
349 @item @b{usbjtag}
350 @* Link @url{}
351 @item @b{jtagkey}
352 @* See: @url{}
353 @item @b{jtagkey2}
354 @* See: @url{}
355 @item @b{oocdlink}
356 @* See: @url{} By Joern Kaipf
357 @item @b{signalyzer}
358 @* See: @url{}
359 @item @b{Stellaris Eval Boards}
360 @* See: @url{} - The Stellaris eval boards
361 bundle FT2232-based JTAG and SWD support, which can be used to debug
362 the Stellaris chips. Using separate JTAG adapters is optional.
363 These boards can also be used in a "pass through" mode as JTAG adapters
364 to other target boards, disabling the Stellaris chip.
365 @item @b{TI/Luminary ICDI}
366 @* See: @url{} - TI/Luminary In-Circuit Debug
367 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
368 Evaluation Kits. Like the non-detachable FT2232 support on the other
369 Stellaris eval boards, they can be used to debug other target boards.
370 @item @b{olimex-jtag}
371 @* See: @url{}
372 @item @b{Flyswatter/Flyswatter2}
373 @* See: @url{}
374 @item @b{turtelizer2}
375 @* See:
376 @uref{, Turtelizer 2}, or
377 @url{}
378 @item @b{comstick}
379 @* Link: @url{}
380 @item @b{stm32stick}
381 @* Link @url{}
382 @item @b{axm0432_jtag}
383 @* Axiom AXM-0432 Link @url{} - NOTE: This JTAG does not appear
384 to be available anymore as of April 2012.
385 @item @b{cortino}
386 @* Link @url{}
387 @item @b{dlp-usb1232h}
388 @* Link @url{}
389 @item @b{digilent-hs1}
390 @* Link @url{}
391 @end itemize
393 @section USB-JTAG / Altera USB-Blaster compatibles
395 These devices also show up as FTDI devices, but are not
396 protocol-compatible with the FT2232 devices. They are, however,
397 protocol-compatible among themselves. USB-JTAG devices typically consist
398 of a FT245 followed by a CPLD that understands a particular protocol,
399 or emulate this protocol using some other hardware.
401 They may appear under different USB VID/PID depending on the particular
402 product. The driver can be configured to search for any VID/PID pair
403 (see the section on driver commands).
405 @itemize
406 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
407 @* Link: @url{}
408 @item @b{Altera USB-Blaster}
409 @* Link: @url{}
410 @end itemize
412 @section USB JLINK based
413 There are several OEM versions of the Segger @b{JLINK} adapter. It is
414 an example of a micro controller based JTAG adapter, it uses an
415 AT91SAM764 internally.
417 @itemize @bullet
418 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
419 @* Link: @url{}
420 @item @b{SEGGER JLINK}
421 @* Link: @url{}
422 @item @b{IAR J-Link}
423 @* Link: @url{}
424 @end itemize
426 @section USB RLINK based
427 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
429 @itemize @bullet
430 @item @b{Raisonance RLink}
431 @* Link: @url{}
432 @item @b{STM32 Primer}
433 @* Link: @url{}
434 @item @b{STM32 Primer2}
435 @* Link: @url{}
436 @end itemize
438 @section USB ST-LINK based
439 ST Micro has an adapter called @b{ST-LINK}.
440 They only work with ST Micro chips, notably STM32 and STM8.
442 @itemize @bullet
443 @item @b{ST-LINK}
444 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
445 @* Link: @url{}
446 @item @b{ST-LINK/V2}
447 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
448 @* Link: @url{}
449 @end itemize
451 For info the original ST-LINK enumerates using the mass storage usb class, however
452 it's implementation is completely broken. The result is this causes issues under linux.
453 The simplest solution is to get linux to ignore the ST-LINK using one of the following methods:
454 @itemize @bullet
455 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
456 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
457 @end itemize
459 @section USB TI/Stellaris ICDI based
460 Texas Instruments has an adapter called @b{ICDI}.
461 It is not to be confused with the FTDI based adapters that were originally fitted to their
462 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
464 @section USB Other
465 @itemize @bullet
466 @item @b{USBprog}
467 @* Link: @url{} - which uses an Atmel MEGA32 and a UBN9604
469 @item @b{USB - Presto}
470 @* Link: @url{}
472 @item @b{Versaloon-Link}
473 @* Link: @url{}
475 @item @b{ARM-JTAG-EW}
476 @* Link: @url{}
478 @item @b{Buspirate}
479 @* Link: @url{}
481 @item @b{opendous}
482 @* Link: @url{}
484 @item @b{estick}
485 @* Link: @url{}
487 @item @b{Keil ULINK v1}
488 @* Link: @url{}
489 @end itemize
491 @section IBM PC Parallel Printer Port Based
493 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
494 and the Macraigor Wiggler. There are many clones and variations of
495 these on the market.
497 Note that parallel ports are becoming much less common, so if you
498 have the choice you should probably avoid these adapters in favor
499 of USB-based ones.
501 @itemize @bullet
503 @item @b{Wiggler} - There are many clones of this.
504 @* Link: @url{}
506 @item @b{DLC5} - From XILINX - There are many clones of this
507 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
508 produced, PDF schematics are easily found and it is easy to make.
510 @item @b{Amontec - JTAG Accelerator}
511 @* Link: @url{}
513 @item @b{GW16402}
514 @* Link: @url{}
516 @item @b{Wiggler2}
517 @* Link: @url{}
519 @item @b{Wiggler_ntrst_inverted}
520 @* Yet another variation - See the source code, src/jtag/parport.c
522 @item @b{old_amt_wiggler}
523 @* Unknown - probably not on the market today
525 @item @b{arm-jtag}
526 @* Link: Most likely @url{} [another wiggler clone]
528 @item @b{chameleon}
529 @* Link: @url{}
531 @item @b{Triton}
532 @* Unknown.
534 @item @b{Lattice}
535 @* ispDownload from Lattice Semiconductor
536 @url{}
538 @item @b{flashlink}
539 @* From ST Microsystems;
540 @* Link: @url{}
542 @end itemize
544 @section Other...
545 @itemize @bullet
547 @item @b{ep93xx}
548 @* An EP93xx based Linux machine using the GPIO pins directly.
550 @item @b{at91rm9200}
551 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
553 @end itemize
555 @node About Jim-Tcl
556 @chapter About Jim-Tcl
557 @cindex Jim-Tcl
558 @cindex tcl
560 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
561 This programming language provides a simple and extensible
562 command interpreter.
564 All commands presented in this Guide are extensions to Jim-Tcl.
565 You can use them as simple commands, without needing to learn
566 much of anything about Tcl.
567 Alternatively, can write Tcl programs with them.
569 You can learn more about Jim at its website, @url{}.
570 There is an active and responsive community, get on the mailing list
571 if you have any questions. Jim-Tcl maintainers also lurk on the
572 OpenOCD mailing list.
574 @itemize @bullet
575 @item @b{Jim vs. Tcl}
576 @* Jim-Tcl is a stripped down version of the well known Tcl language,
577 which can be found here: @url{}. Jim-Tcl has far
578 fewer features. Jim-Tcl is several dozens of .C files and .H files and
579 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
580 4.2 MB .zip file containing 1540 files.
582 @item @b{Missing Features}
583 @* Our practice has been: Add/clone the real Tcl feature if/when
584 needed. We welcome Jim-Tcl improvements, not bloat. Also there
585 are a large number of optional Jim-Tcl features that are not
586 enabled in OpenOCD.
588 @item @b{Scripts}
589 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
590 command interpreter today is a mixture of (newer)
591 Jim-Tcl commands, and (older) the orginal command interpreter.
593 @item @b{Commands}
594 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
595 can type a Tcl for() loop, set variables, etc.
596 Some of the commands documented in this guide are implemented
597 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
599 @item @b{Historical Note}
600 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
601 before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
602 as a git submodule, which greatly simplified upgrading Jim Tcl
603 to benefit from new features and bugfixes in Jim Tcl.
605 @item @b{Need a crash course in Tcl?}
606 @*@xref{Tcl Crash Course}.
607 @end itemize
609 @node Running
610 @chapter Running
611 @cindex command line options
612 @cindex logfile
613 @cindex directory search
615 Properly installing OpenOCD sets up your operating system to grant it access
616 to the debug adapters. On Linux, this usually involves installing a file
617 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
618 complex and confusing driver configuration for every peripheral. Such issues
619 are unique to each operating system, and are not detailed in this User's Guide.
621 Then later you will invoke the OpenOCD server, with various options to
622 tell it how each debug session should work.
623 The @option{--help} option shows:
624 @verbatim
625 bash$ openocd --help
627 --help | -h display this help
628 --version | -v display OpenOCD version
629 --file | -f use configuration file <name>
630 --search | -s dir to search for config files and scripts
631 --debug | -d set debug level <0-3>
632 --log_output | -l redirect log output to file <name>
633 --command | -c run <command>
634 @end verbatim
636 If you don't give any @option{-f} or @option{-c} options,
637 OpenOCD tries to read the configuration file @file{openocd.cfg}.
638 To specify one or more different
639 configuration files, use @option{-f} options. For example:
641 @example
642 openocd -f config1.cfg -f config2.cfg -f config3.cfg
643 @end example
645 Configuration files and scripts are searched for in
646 @enumerate
647 @item the current directory,
648 @item any search dir specified on the command line using the @option{-s} option,
649 @item any search dir specified using the @command{add_script_search_dir} command,
650 @item @file{$HOME/.openocd} (not on Windows),
651 @item the site wide script library @file{$pkgdatadir/site} and
652 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
653 @end enumerate
654 The first found file with a matching file name will be used.
656 @quotation Note
657 Don't try to use configuration script names or paths which
658 include the "#" character. That character begins Tcl comments.
659 @end quotation
661 @section Simple setup, no customization
663 In the best case, you can use two scripts from one of the script
664 libraries, hook up your JTAG adapter, and start the server ... and
665 your JTAG setup will just work "out of the box". Always try to
666 start by reusing those scripts, but assume you'll need more
667 customization even if this works. @xref{OpenOCD Project Setup}.
669 If you find a script for your JTAG adapter, and for your board or
670 target, you may be able to hook up your JTAG adapter then start
671 the server like:
673 @example
674 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
675 @end example
677 You might also need to configure which reset signals are present,
678 using @option{-c 'reset_config trst_and_srst'} or something similar.
679 If all goes well you'll see output something like
681 @example
682 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
683 For bug reports, read
685 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
686 (mfg: 0x23b, part: 0xba00, ver: 0x3)
687 @end example
689 Seeing that "tap/device found" message, and no warnings, means
690 the JTAG communication is working. That's a key milestone, but
691 you'll probably need more project-specific setup.
693 @section What OpenOCD does as it starts
695 OpenOCD starts by processing the configuration commands provided
696 on the command line or, if there were no @option{-c command} or
697 @option{-f file.cfg} options given, in @file{openocd.cfg}.
698 @xref{Configuration Stage}.
699 At the end of the configuration stage it verifies the JTAG scan
700 chain defined using those commands; your configuration should
701 ensure that this always succeeds.
702 Normally, OpenOCD then starts running as a daemon.
703 Alternatively, commands may be used to terminate the configuration
704 stage early, perform work (such as updating some flash memory),
705 and then shut down without acting as a daemon.
707 Once OpenOCD starts running as a daemon, it waits for connections from
708 clients (Telnet, GDB, Other) and processes the commands issued through
709 those channels.
711 If you are having problems, you can enable internal debug messages via
712 the @option{-d} option.
714 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
715 @option{-c} command line switch.
717 To enable debug output (when reporting problems or working on OpenOCD
718 itself), use the @option{-d} command line switch. This sets the
719 @option{debug_level} to "3", outputting the most information,
720 including debug messages. The default setting is "2", outputting only
721 informational messages, warnings and errors. You can also change this
722 setting from within a telnet or gdb session using @command{debug_level
723 <n>} (@pxref{debug_level}).
725 You can redirect all output from the daemon to a file using the
726 @option{-l <logfile>} switch.
728 Note! OpenOCD will launch the GDB & telnet server even if it can not
729 establish a connection with the target. In general, it is possible for
730 the JTAG controller to be unresponsive until the target is set up
731 correctly via e.g. GDB monitor commands in a GDB init script.
733 @node OpenOCD Project Setup
734 @chapter OpenOCD Project Setup
736 To use OpenOCD with your development projects, you need to do more than
737 just connecting the JTAG adapter hardware (dongle) to your development board
738 and then starting the OpenOCD server.
739 You also need to configure that server so that it knows
740 about that adapter and board, and helps your work.
741 You may also want to connect OpenOCD to GDB, possibly
742 using Eclipse or some other GUI.
744 @section Hooking up the JTAG Adapter
746 Today's most common case is a dongle with a JTAG cable on one side
747 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
748 and a USB cable on the other.
749 Instead of USB, some cables use Ethernet;
750 older ones may use a PC parallel port, or even a serial port.
752 @enumerate
753 @item @emph{Start with power to your target board turned off},
754 and nothing connected to your JTAG adapter.
755 If you're particularly paranoid, unplug power to the board.
756 It's important to have the ground signal properly set up,
757 unless you are using a JTAG adapter which provides
758 galvanic isolation between the target board and the
759 debugging host.
761 @item @emph{Be sure it's the right kind of JTAG connector.}
762 If your dongle has a 20-pin ARM connector, you need some kind
763 of adapter (or octopus, see below) to hook it up to
764 boards using 14-pin or 10-pin connectors ... or to 20-pin
765 connectors which don't use ARM's pinout.
767 In the same vein, make sure the voltage levels are compatible.
768 Not all JTAG adapters have the level shifters needed to work
769 with 1.2 Volt boards.
771 @item @emph{Be certain the cable is properly oriented} or you might
772 damage your board. In most cases there are only two possible
773 ways to connect the cable.
774 Connect the JTAG cable from your adapter to the board.
775 Be sure it's firmly connected.
777 In the best case, the connector is keyed to physically
778 prevent you from inserting it wrong.
779 This is most often done using a slot on the board's male connector
780 housing, which must match a key on the JTAG cable's female connector.
781 If there's no housing, then you must look carefully and
782 make sure pin 1 on the cable hooks up to pin 1 on the board.
783 Ribbon cables are frequently all grey except for a wire on one
784 edge, which is red. The red wire is pin 1.
786 Sometimes dongles provide cables where one end is an ``octopus'' of
787 color coded single-wire connectors, instead of a connector block.
788 These are great when converting from one JTAG pinout to another,
789 but are tedious to set up.
790 Use these with connector pinout diagrams to help you match up the
791 adapter signals to the right board pins.
793 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
794 A USB, parallel, or serial port connector will go to the host which
795 you are using to run OpenOCD.
796 For Ethernet, consult the documentation and your network administrator.
798 For USB based JTAG adapters you have an easy sanity check at this point:
799 does the host operating system see the JTAG adapter? If that host is an
800 MS-Windows host, you'll need to install a driver before OpenOCD works.
802 @item @emph{Connect the adapter's power supply, if needed.}
803 This step is primarily for non-USB adapters,
804 but sometimes USB adapters need extra power.
806 @item @emph{Power up the target board.}
807 Unless you just let the magic smoke escape,
808 you're now ready to set up the OpenOCD server
809 so you can use JTAG to work with that board.
811 @end enumerate
813 Talk with the OpenOCD server using
814 telnet (@code{telnet localhost 4444} on many systems) or GDB.
815 @xref{GDB and OpenOCD}.
817 @section Project Directory
819 There are many ways you can configure OpenOCD and start it up.
821 A simple way to organize them all involves keeping a
822 single directory for your work with a given board.
823 When you start OpenOCD from that directory,
824 it searches there first for configuration files, scripts,
825 files accessed through semihosting,
826 and for code you upload to the target board.
827 It is also the natural place to write files,
828 such as log files and data you download from the board.
830 @section Configuration Basics
832 There are two basic ways of configuring OpenOCD, and
833 a variety of ways you can mix them.
834 Think of the difference as just being how you start the server:
836 @itemize
837 @item Many @option{-f file} or @option{-c command} options on the command line
838 @item No options, but a @dfn{user config file}
839 in the current directory named @file{openocd.cfg}
840 @end itemize
842 Here is an example @file{openocd.cfg} file for a setup
843 using a Signalyzer FT2232-based JTAG adapter to talk to
844 a board with an Atmel AT91SAM7X256 microcontroller:
846 @example
847 source [find interface/signalyzer.cfg]
849 # GDB can also flash my flash!
850 gdb_memory_map enable
851 gdb_flash_program enable
853 source [find target/sam7x256.cfg]
854 @end example
856 Here is the command line equivalent of that configuration:
858 @example
859 openocd -f interface/signalyzer.cfg \
860 -c "gdb_memory_map enable" \
861 -c "gdb_flash_program enable" \
862 -f target/sam7x256.cfg
863 @end example
865 You could wrap such long command lines in shell scripts,
866 each supporting a different development task.
867 One might re-flash the board with a specific firmware version.
868 Another might set up a particular debugging or run-time environment.
870 @quotation Important
871 At this writing (October 2009) the command line method has
872 problems with how it treats variables.
873 For example, after @option{-c "set VAR value"}, or doing the
874 same in a script, the variable @var{VAR} will have no value
875 that can be tested in a later script.
876 @end quotation
878 Here we will focus on the simpler solution: one user config
879 file, including basic configuration plus any TCL procedures
880 to simplify your work.
882 @section User Config Files
883 @cindex config file, user
884 @cindex user config file
885 @cindex config file, overview
887 A user configuration file ties together all the parts of a project
888 in one place.
889 One of the following will match your situation best:
891 @itemize
892 @item Ideally almost everything comes from configuration files
893 provided by someone else.
894 For example, OpenOCD distributes a @file{scripts} directory
895 (probably in @file{/usr/share/openocd/scripts} on Linux).
896 Board and tool vendors can provide these too, as can individual
897 user sites; the @option{-s} command line option lets you say
898 where to find these files. (@xref{Running}.)
899 The AT91SAM7X256 example above works this way.
901 Three main types of non-user configuration file each have their
902 own subdirectory in the @file{scripts} directory:
904 @enumerate
905 @item @b{interface} -- one for each different debug adapter;
906 @item @b{board} -- one for each different board
907 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
908 @end enumerate
910 Best case: include just two files, and they handle everything else.
911 The first is an interface config file.
912 The second is board-specific, and it sets up the JTAG TAPs and
913 their GDB targets (by deferring to some @file{target.cfg} file),
914 declares all flash memory, and leaves you nothing to do except
915 meet your deadline:
917 @example
918 source [find interface/olimex-jtag-tiny.cfg]
919 source [find board/csb337.cfg]
920 @end example
922 Boards with a single microcontroller often won't need more
923 than the target config file, as in the AT91SAM7X256 example.
924 That's because there is no external memory (flash, DDR RAM), and
925 the board differences are encapsulated by application code.
927 @item Maybe you don't know yet what your board looks like to JTAG.
928 Once you know the @file{interface.cfg} file to use, you may
929 need help from OpenOCD to discover what's on the board.
930 Once you find the JTAG TAPs, you can just search for appropriate
931 target and board
932 configuration files ... or write your own, from the bottom up.
933 @xref{Autoprobing}.
935 @item You can often reuse some standard config files but
936 need to write a few new ones, probably a @file{board.cfg} file.
937 You will be using commands described later in this User's Guide,
938 and working with the guidelines in the next chapter.
940 For example, there may be configuration files for your JTAG adapter
941 and target chip, but you need a new board-specific config file
942 giving access to your particular flash chips.
943 Or you might need to write another target chip configuration file
944 for a new chip built around the Cortex M3 core.
946 @quotation Note
947 When you write new configuration files, please submit
948 them for inclusion in the next OpenOCD release.
949 For example, a @file{board/newboard.cfg} file will help the
950 next users of that board, and a @file{target/newcpu.cfg}
951 will help support users of any board using that chip.
952 @end quotation
954 @item
955 You may may need to write some C code.
956 It may be as simple as a supporting a new ft2232 or parport
957 based adapter; a bit more involved, like a NAND or NOR flash
958 controller driver; or a big piece of work like supporting
959 a new chip architecture.
960 @end itemize
962 Reuse the existing config files when you can.
963 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
964 You may find a board configuration that's a good example to follow.
966 When you write config files, separate the reusable parts
967 (things every user of that interface, chip, or board needs)
968 from ones specific to your environment and debugging approach.
969 @itemize
971 @item
972 For example, a @code{gdb-attach} event handler that invokes
973 the @command{reset init} command will interfere with debugging
974 early boot code, which performs some of the same actions
975 that the @code{reset-init} event handler does.
977 @item
978 Likewise, the @command{arm9 vector_catch} command (or
979 @cindex vector_catch
980 its siblings @command{xscale vector_catch}
981 and @command{cortex_m3 vector_catch}) can be a timesaver
982 during some debug sessions, but don't make everyone use that either.
983 Keep those kinds of debugging aids in your user config file,
984 along with messaging and tracing setup.
985 (@xref{Software Debug Messages and Tracing}.)
987 @item
988 You might need to override some defaults.
989 For example, you might need to move, shrink, or back up the target's
990 work area if your application needs much SRAM.
992 @item
993 TCP/IP port configuration is another example of something which
994 is environment-specific, and should only appear in
995 a user config file. @xref{TCP/IP Ports}.
996 @end itemize
998 @section Project-Specific Utilities
1000 A few project-specific utility
1001 routines may well speed up your work.
1002 Write them, and keep them in your project's user config file.
1004 For example, if you are making a boot loader work on a
1005 board, it's nice to be able to debug the ``after it's
1006 loaded to RAM'' parts separately from the finicky early
1007 code which sets up the DDR RAM controller and clocks.
1008 A script like this one, or a more GDB-aware sibling,
1009 may help:
1011 @example
1012 proc ramboot @{ @} @{
1013 # Reset, running the target's "reset-init" scripts
1014 # to initialize clocks and the DDR RAM controller.
1015 # Leave the CPU halted.
1016 reset init
1018 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1019 load_image u-boot.bin 0x20000000
1021 # Start running.
1022 resume 0x20000000
1023 @}
1024 @end example
1026 Then once that code is working you will need to make it
1027 boot from NOR flash; a different utility would help.
1028 Alternatively, some developers write to flash using GDB.
1029 (You might use a similar script if you're working with a flash
1030 based microcontroller application instead of a boot loader.)
1032 @example
1033 proc newboot @{ @} @{
1034 # Reset, leaving the CPU halted. The "reset-init" event
1035 # proc gives faster access to the CPU and to NOR flash;
1036 # "reset halt" would be slower.
1037 reset init
1039 # Write standard version of U-Boot into the first two
1040 # sectors of NOR flash ... the standard version should
1041 # do the same lowlevel init as "reset-init".
1042 flash protect 0 0 1 off
1043 flash erase_sector 0 0 1
1044 flash write_bank 0 u-boot.bin 0x0
1045 flash protect 0 0 1 on
1047 # Reboot from scratch using that new boot loader.
1048 reset run
1049 @}
1050 @end example
1052 You may need more complicated utility procedures when booting
1053 from NAND.
1054 That often involves an extra bootloader stage,
1055 running from on-chip SRAM to perform DDR RAM setup so it can load
1056 the main bootloader code (which won't fit into that SRAM).
1058 Other helper scripts might be used to write production system images,
1059 involving considerably more than just a three stage bootloader.
1061 @section Target Software Changes
1063 Sometimes you may want to make some small changes to the software
1064 you're developing, to help make JTAG debugging work better.
1065 For example, in C or assembly language code you might
1066 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1067 handling issues like:
1069 @itemize @bullet
1071 @item @b{Watchdog Timers}...
1072 Watchog timers are typically used to automatically reset systems if
1073 some application task doesn't periodically reset the timer. (The
1074 assumption is that the system has locked up if the task can't run.)
1075 When a JTAG debugger halts the system, that task won't be able to run
1076 and reset the timer ... potentially causing resets in the middle of
1077 your debug sessions.
1079 It's rarely a good idea to disable such watchdogs, since their usage
1080 needs to be debugged just like all other parts of your firmware.
1081 That might however be your only option.
1083 Look instead for chip-specific ways to stop the watchdog from counting
1084 while the system is in a debug halt state. It may be simplest to set
1085 that non-counting mode in your debugger startup scripts. You may however
1086 need a different approach when, for example, a motor could be physically
1087 damaged by firmware remaining inactive in a debug halt state. That might
1088 involve a type of firmware mode where that "non-counting" mode is disabled
1089 at the beginning then re-enabled at the end; a watchdog reset might fire
1090 and complicate the debug session, but hardware (or people) would be
1091 protected.@footnote{Note that many systems support a "monitor mode" debug
1092 that is a somewhat cleaner way to address such issues. You can think of
1093 it as only halting part of the system, maybe just one task,
1094 instead of the whole thing.
1095 At this writing, January 2010, OpenOCD based debugging does not support
1096 monitor mode debug, only "halt mode" debug.}
1098 @item @b{ARM Semihosting}...
1099 @cindex ARM semihosting
1100 When linked with a special runtime library provided with many
1101 toolchains@footnote{See chapter 8 "Semihosting" in
1102 @uref{,
1103 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1104 The CodeSourcery EABI toolchain also includes a semihosting library.},
1105 your target code can use I/O facilities on the debug host. That library
1106 provides a small set of system calls which are handled by OpenOCD.
1107 It can let the debugger provide your system console and a file system,
1108 helping with early debugging or providing a more capable environment
1109 for sometimes-complex tasks like installing system firmware onto
1110 NAND or SPI flash.
1112 @item @b{ARM Wait-For-Interrupt}...
1113 Many ARM chips synchronize the JTAG clock using the core clock.
1114 Low power states which stop that core clock thus prevent JTAG access.
1115 Idle loops in tasking environments often enter those low power states
1116 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1118 You may want to @emph{disable that instruction} in source code,
1119 or otherwise prevent using that state,
1120 to ensure you can get JTAG access at any time.@footnote{As a more
1121 polite alternative, some processors have special debug-oriented
1122 registers which can be used to change various features including
1123 how the low power states are clocked while debugging.
1124 The STM32 DBGMCU_CR register is an example; at the cost of extra
1125 power consumption, JTAG can be used during low power states.}
1126 For example, the OpenOCD @command{halt} command may not
1127 work for an idle processor otherwise.
1129 @item @b{Delay after reset}...
1130 Not all chips have good support for debugger access
1131 right after reset; many LPC2xxx chips have issues here.
1132 Similarly, applications that reconfigure pins used for
1133 JTAG access as they start will also block debugger access.
1135 To work with boards like this, @emph{enable a short delay loop}
1136 the first thing after reset, before "real" startup activities.
1137 For example, one second's delay is usually more than enough
1138 time for a JTAG debugger to attach, so that
1139 early code execution can be debugged
1140 or firmware can be replaced.
1142 @item @b{Debug Communications Channel (DCC)}...
1143 Some processors include mechanisms to send messages over JTAG.
1144 Many ARM cores support these, as do some cores from other vendors.
1145 (OpenOCD may be able to use this DCC internally, speeding up some
1146 operations like writing to memory.)
1148 Your application may want to deliver various debugging messages
1149 over JTAG, by @emph{linking with a small library of code}
1150 provided with OpenOCD and using the utilities there to send
1151 various kinds of message.
1152 @xref{Software Debug Messages and Tracing}.
1154 @end itemize
1156 @section Target Hardware Setup
1158 Chip vendors often provide software development boards which
1159 are highly configurable, so that they can support all options
1160 that product boards may require. @emph{Make sure that any
1161 jumpers or switches match the system configuration you are
1162 working with.}
1164 Common issues include:
1166 @itemize @bullet
1168 @item @b{JTAG setup} ...
1169 Boards may support more than one JTAG configuration.
1170 Examples include jumpers controlling pullups versus pulldowns
1171 on the nTRST and/or nSRST signals, and choice of connectors
1172 (e.g. which of two headers on the base board,
1173 or one from a daughtercard).
1174 For some Texas Instruments boards, you may need to jumper the
1175 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1177 @item @b{Boot Modes} ...
1178 Complex chips often support multiple boot modes, controlled
1179 by external jumpers. Make sure this is set up correctly.
1180 For example many i.MX boards from NXP need to be jumpered
1181 to "ATX mode" to start booting using the on-chip ROM, when
1182 using second stage bootloader code stored in a NAND flash chip.
1184 Such explicit configuration is common, and not limited to
1185 booting from NAND. You might also need to set jumpers to
1186 start booting using code loaded from an MMC/SD card; external
1187 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1188 flash; some external host; or various other sources.
1191 @item @b{Memory Addressing} ...
1192 Boards which support multiple boot modes may also have jumpers
1193 to configure memory addressing. One board, for example, jumpers
1194 external chipselect 0 (used for booting) to address either
1195 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1196 or NAND flash. When it's jumpered to address NAND flash, that
1197 board must also be told to start booting from on-chip ROM.
1199 Your @file{board.cfg} file may also need to be told this jumper
1200 configuration, so that it can know whether to declare NOR flash
1201 using @command{flash bank} or instead declare NAND flash with
1202 @command{nand device}; and likewise which probe to perform in
1203 its @code{reset-init} handler.
1205 A closely related issue is bus width. Jumpers might need to
1206 distinguish between 8 bit or 16 bit bus access for the flash
1207 used to start booting.
1209 @item @b{Peripheral Access} ...
1210 Development boards generally provide access to every peripheral
1211 on the chip, sometimes in multiple modes (such as by providing
1212 multiple audio codec chips).
1213 This interacts with software
1214 configuration of pin multiplexing, where for example a
1215 given pin may be routed either to the MMC/SD controller
1216 or the GPIO controller. It also often interacts with
1217 configuration jumpers. One jumper may be used to route
1218 signals to an MMC/SD card slot or an expansion bus (which
1219 might in turn affect booting); others might control which
1220 audio or video codecs are used.
1222 @end itemize
1224 Plus you should of course have @code{reset-init} event handlers
1225 which set up the hardware to match that jumper configuration.
1226 That includes in particular any oscillator or PLL used to clock
1227 the CPU, and any memory controllers needed to access external
1228 memory and peripherals. Without such handlers, you won't be
1229 able to access those resources without working target firmware
1230 which can do that setup ... this can be awkward when you're
1231 trying to debug that target firmware. Even if there's a ROM
1232 bootloader which handles a few issues, it rarely provides full
1233 access to all board-specific capabilities.
1236 @node Config File Guidelines
1237 @chapter Config File Guidelines
1239 This chapter is aimed at any user who needs to write a config file,
1240 including developers and integrators of OpenOCD and any user who
1241 needs to get a new board working smoothly.
1242 It provides guidelines for creating those files.
1244 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1245 with files including the ones listed here.
1246 Use them as-is where you can; or as models for new files.
1247 @itemize @bullet
1248 @item @file{interface} ...
1249 These are for debug adapters.
1250 Files that configure JTAG adapters go here.
1251 @example
1252 $ ls interface
1253 altera-usb-blaster.cfg hilscher_nxhx50_etm.cfg openrd.cfg
1254 arm-jtag-ew.cfg hilscher_nxhx50_re.cfg osbdm.cfg
1255 arm-usb-ocd.cfg hitex_str9-comstick.cfg parport.cfg
1256 at91rm9200.cfg icebear.cfg parport_dlc5.cfg
1257 axm0432.cfg jlink.cfg redbee-econotag.cfg
1258 busblaster.cfg jtagkey2.cfg redbee-usb.cfg
1259 buspirate.cfg jtagkey2p.cfg rlink.cfg
1260 calao-usb-a9260-c01.cfg jtagkey.cfg sheevaplug.cfg
1261 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg signalyzer.cfg
1262 calao-usb-a9260.cfg kt-link.cfg signalyzer-h2.cfg
1263 chameleon.cfg lisa-l.cfg signalyzer-h4.cfg
1264 cortino.cfg luminary.cfg signalyzer-lite.cfg
1265 digilent-hs1.cfg luminary-icdi.cfg stlink-v1.cfg
1266 dlp-usb1232h.cfg luminary-lm3s811.cfg stlink-v2.cfg
1267 dummy.cfg minimodule.cfg stm32-stick.cfg
1268 estick.cfg neodb.cfg turtelizer2.cfg
1269 flashlink.cfg ngxtech.cfg ulink.cfg
1270 flossjtag.cfg olimex-arm-usb-ocd.cfg usb-jtag.cfg
1271 flossjtag-noeeprom.cfg olimex-arm-usb-ocd-h.cfg usbprog.cfg
1272 flyswatter2.cfg olimex-arm-usb-tiny-h.cfg vpaclink.cfg
1273 flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
1274 hilscher_nxhx10_etm.cfg oocdlink.cfg xds100v2.cfg
1275 hilscher_nxhx500_etm.cfg opendous.cfg
1276 hilscher_nxhx500_re.cfg openocd-usb.cfg
1277 $
1278 @end example
1279 @item @file{board} ...
1280 think Circuit Board, PWA, PCB, they go by many names. Board files
1281 contain initialization items that are specific to a board.
1282 They reuse target configuration files, since the same
1283 microprocessor chips are used on many boards,
1284 but support for external parts varies widely. For
1285 example, the SDRAM initialization sequence for the board, or the type
1286 of external flash and what address it uses. Any initialization
1287 sequence to enable that external flash or SDRAM should be found in the
1288 board file. Boards may also contain multiple targets: two CPUs; or
1289 a CPU and an FPGA.
1290 @example
1291 $ ls board
1292 actux3.cfg logicpd_imx27.cfg
1293 am3517evm.cfg lubbock.cfg
1294 arm_evaluator7t.cfg mcb1700.cfg
1295 at91cap7a-stk-sdram.cfg microchip_explorer16.cfg
1296 at91eb40a.cfg mini2440.cfg
1297 at91rm9200-dk.cfg mini6410.cfg
1298 at91rm9200-ek.cfg olimex_LPC2378STK.cfg
1299 at91sam9261-ek.cfg olimex_lpc_h2148.cfg
1300 at91sam9263-ek.cfg olimex_sam7_ex256.cfg
1301 at91sam9g20-ek.cfg olimex_sam9_l9260.cfg
1302 atmel_at91sam7s-ek.cfg olimex_stm32_h103.cfg
1303 atmel_at91sam9260-ek.cfg olimex_stm32_h107.cfg
1304 atmel_at91sam9rl-ek.cfg olimex_stm32_p107.cfg
1305 atmel_sam3n_ek.cfg omap2420_h4.cfg
1306 atmel_sam3s_ek.cfg open-bldc.cfg
1307 atmel_sam3u_ek.cfg openrd.cfg
1308 atmel_sam3x_ek.cfg osk5912.cfg
1309 atmel_sam4s_ek.cfg phytec_lpc3250.cfg
1310 balloon3-cpu.cfg pic-p32mx.cfg
1311 colibri.cfg propox_mmnet1001.cfg
1312 crossbow_tech_imote2.cfg pxa255_sst.cfg
1313 csb337.cfg redbee.cfg
1314 csb732.cfg rsc-w910.cfg
1315 da850evm.cfg sheevaplug.cfg
1316 digi_connectcore_wi-9c.cfg smdk6410.cfg
1317 diolan_lpc4350-db1.cfg spear300evb.cfg
1318 dm355evm.cfg spear300evb_mod.cfg
1319 dm365evm.cfg spear310evb20.cfg
1320 dm6446evm.cfg spear310evb20_mod.cfg
1321 efikamx.cfg spear320cpu.cfg
1322 eir.cfg spear320cpu_mod.cfg
1323 ek-lm3s1968.cfg steval_pcc010.cfg
1324 ek-lm3s3748.cfg stm320518_eval_stlink.cfg
1325 ek-lm3s6965.cfg stm32100b_eval.cfg
1326 ek-lm3s811.cfg stm3210b_eval.cfg
1327 ek-lm3s811-revb.cfg stm3210c_eval.cfg
1328 ek-lm3s9b9x.cfg stm3210e_eval.cfg
1329 ek-lm4f232.cfg stm3220g_eval.cfg
1330 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1331 ethernut3.cfg stm3241g_eval.cfg
1332 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1333 hammer.cfg stm32f0discovery.cfg
1334 hilscher_nxdb500sys.cfg stm32f4discovery.cfg
1335 hilscher_nxeb500hmi.cfg stm32ldiscovery.cfg
1336 hilscher_nxhx10.cfg stm32vldiscovery.cfg
1337 hilscher_nxhx500.cfg str910-eval.cfg
1338 hilscher_nxhx50.cfg telo.cfg
1339 hilscher_nxsb100.cfg ti_beagleboard.cfg
1340 hitex_lpc2929.cfg ti_beagleboard_xm.cfg
1341 hitex_stm32-performancestick.cfg ti_beaglebone.cfg
1342 hitex_str9-comstick.cfg ti_blaze.cfg
1343 iar_lpc1768.cfg ti_pandaboard.cfg
1344 iar_str912_sk.cfg ti_pandaboard_es.cfg
1345 icnova_imx53_sodimm.cfg topas910.cfg
1346 icnova_sam9g45_sodimm.cfg topasa900.cfg
1347 imx27ads.cfg twr-k60n512.cfg
1348 imx27lnst.cfg tx25_stk5.cfg
1349 imx28evk.cfg tx27_stk5.cfg
1350 imx31pdk.cfg unknown_at91sam9260.cfg
1351 imx35pdk.cfg uptech_2410.cfg
1352 imx53loco.cfg verdex.cfg
1353 keil_mcb1700.cfg voipac.cfg
1354 keil_mcb2140.cfg voltcraft_dso-3062c.cfg
1355 kwikstik.cfg x300t.cfg
1356 linksys_nslu2.cfg zy1000.cfg
1357 lisa-l.cfg
1358 $
1359 @end example
1360 @item @file{target} ...
1361 think chip. The ``target'' directory represents the JTAG TAPs
1362 on a chip
1363 which OpenOCD should control, not a board. Two common types of targets
1364 are ARM chips and FPGA or CPLD chips.
1365 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1366 the target config file defines all of them.
1367 @example
1368 $ ls target
1369 $duc702x.cfg ixp42x.cfg
1370 am335x.cfg k40.cfg
1371 amdm37x.cfg k60.cfg
1372 ar71xx.cfg lpc1768.cfg
1373 at32ap7000.cfg lpc2103.cfg
1374 at91r40008.cfg lpc2124.cfg
1375 at91rm9200.cfg lpc2129.cfg
1376 at91sam3ax_4x.cfg lpc2148.cfg
1377 at91sam3ax_8x.cfg lpc2294.cfg
1378 at91sam3ax_xx.cfg lpc2378.cfg
1379 at91sam3nXX.cfg lpc2460.cfg
1380 at91sam3sXX.cfg lpc2478.cfg
1381 at91sam3u1c.cfg lpc2900.cfg
1382 at91sam3u1e.cfg lpc2xxx.cfg
1383 at91sam3u2c.cfg lpc3131.cfg
1384 at91sam3u2e.cfg lpc3250.cfg
1385 at91sam3u4c.cfg lpc4350.cfg
1386 at91sam3u4e.cfg mc13224v.cfg
1387 at91sam3uxx.cfg nuc910.cfg
1388 at91sam3XXX.cfg omap2420.cfg
1389 at91sam4sXX.cfg omap3530.cfg
1390 at91sam4XXX.cfg omap4430.cfg
1391 at91sam7se512.cfg omap4460.cfg
1392 at91sam7sx.cfg omap5912.cfg
1393 at91sam7x256.cfg omapl138.cfg
1394 at91sam7x512.cfg pic32mx.cfg
1395 at91sam9260.cfg pxa255.cfg
1396 at91sam9260_ext_RAM_ext_flash.cfg pxa270.cfg
1397 at91sam9261.cfg pxa3xx.cfg
1398 at91sam9263.cfg readme.txt
1399 at91sam9.cfg samsung_s3c2410.cfg
1400 at91sam9g10.cfg samsung_s3c2440.cfg
1401 at91sam9g20.cfg samsung_s3c2450.cfg
1402 at91sam9g45.cfg samsung_s3c4510.cfg
1403 at91sam9rl.cfg samsung_s3c6410.cfg
1404 atmega128.cfg sharp_lh79532.cfg
1405 avr32.cfg smp8634.cfg
1406 c100.cfg spear3xx.cfg
1407 c100config.tcl stellaris.cfg
1408 c100helper.tcl stm32.cfg
1409 c100regs.tcl stm32f0x_stlink.cfg
1410 cs351x.cfg stm32f1x.cfg
1411 davinci.cfg stm32f1x_stlink.cfg
1412 dragonite.cfg stm32f2x.cfg
1413 dsp56321.cfg stm32f2x_stlink.cfg
1414 dsp568013.cfg stm32f2xxx.cfg
1415 dsp568037.cfg stm32f4x.cfg
1416 epc9301.cfg stm32f4x_stlink.cfg
1417 faux.cfg stm32l.cfg
1418 feroceon.cfg stm32lx_stlink.cfg
1419 fm3.cfg stm32_stlink.cfg
1420 hilscher_netx10.cfg stm32xl.cfg
1421 hilscher_netx500.cfg str710.cfg
1422 hilscher_netx50.cfg str730.cfg
1423 icepick.cfg str750.cfg
1424 imx21.cfg str912.cfg
1425 imx25.cfg swj-dp.tcl
1426 imx27.cfg test_reset_syntax_error.cfg
1427 imx28.cfg test_syntax_error.cfg
1428 imx31.cfg ti_dm355.cfg
1429 imx35.cfg ti_dm365.cfg
1430 imx51.cfg ti_dm6446.cfg
1431 imx53.cfg tmpa900.cfg
1432 imx.cfg tmpa910.cfg
1433 is5114.cfg u8500.cfg
1434 @end example
1435 @item @emph{more} ... browse for other library files which may be useful.
1436 For example, there are various generic and CPU-specific utilities.
1437 @end itemize
1439 The @file{openocd.cfg} user config
1440 file may override features in any of the above files by
1441 setting variables before sourcing the target file, or by adding
1442 commands specific to their situation.
1444 @section Interface Config Files
1446 The user config file
1447 should be able to source one of these files with a command like this:
1449 @example
1450 source [find interface/FOOBAR.cfg]
1451 @end example
1453 A preconfigured interface file should exist for every debug adapter
1454 in use today with OpenOCD.
1455 That said, perhaps some of these config files
1456 have only been used by the developer who created it.
1458 A separate chapter gives information about how to set these up.
1459 @xref{Debug Adapter Configuration}.
1460 Read the OpenOCD source code (and Developer's Guide)
1461 if you have a new kind of hardware interface
1462 and need to provide a driver for it.
1464 @section Board Config Files
1465 @cindex config file, board
1466 @cindex board config file
1468 The user config file
1469 should be able to source one of these files with a command like this:
1471 @example
1472 source [find board/FOOBAR.cfg]
1473 @end example
1475 The point of a board config file is to package everything
1476 about a given board that user config files need to know.
1477 In summary the board files should contain (if present)
1479 @enumerate
1480 @item One or more @command{source [target/...cfg]} statements
1481 @item NOR flash configuration (@pxref{NOR Configuration})
1482 @item NAND flash configuration (@pxref{NAND Configuration})
1483 @item Target @code{reset} handlers for SDRAM and I/O configuration
1484 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1485 @item All things that are not ``inside a chip''
1486 @end enumerate
1488 Generic things inside target chips belong in target config files,
1489 not board config files. So for example a @code{reset-init} event
1490 handler should know board-specific oscillator and PLL parameters,
1491 which it passes to target-specific utility code.
1493 The most complex task of a board config file is creating such a
1494 @code{reset-init} event handler.
1495 Define those handlers last, after you verify the rest of the board
1496 configuration works.
1498 @subsection Communication Between Config files
1500 In addition to target-specific utility code, another way that
1501 board and target config files communicate is by following a
1502 convention on how to use certain variables.
1504 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1505 Thus the rule we follow in OpenOCD is this: Variables that begin with
1506 a leading underscore are temporary in nature, and can be modified and
1507 used at will within a target configuration file.
1509 Complex board config files can do the things like this,
1510 for a board with three chips:
1512 @example
1513 # Chip #1: PXA270 for network side, big endian
1514 set CHIPNAME network
1515 set ENDIAN big
1516 source [find target/pxa270.cfg]
1517 # on return: _TARGETNAME = network.cpu
1518 # other commands can refer to the "network.cpu" target.
1519 $_TARGETNAME configure .... events for this CPU..
1521 # Chip #2: PXA270 for video side, little endian
1522 set CHIPNAME video
1523 set ENDIAN little
1524 source [find target/pxa270.cfg]
1525 # on return: _TARGETNAME = video.cpu
1526 # other commands can refer to the "video.cpu" target.
1527 $_TARGETNAME configure .... events for this CPU..
1529 # Chip #3: Xilinx FPGA for glue logic
1530 set CHIPNAME xilinx
1531 unset ENDIAN
1532 source [find target/spartan3.cfg]
1533 @end example
1535 That example is oversimplified because it doesn't show any flash memory,
1536 or the @code{reset-init} event handlers to initialize external DRAM
1537 or (assuming it needs it) load a configuration into the FPGA.
1538 Such features are usually needed for low-level work with many boards,
1539 where ``low level'' implies that the board initialization software may
1540 not be working. (That's a common reason to need JTAG tools. Another
1541 is to enable working with microcontroller-based systems, which often
1542 have no debugging support except a JTAG connector.)
1544 Target config files may also export utility functions to board and user
1545 config files. Such functions should use name prefixes, to help avoid
1546 naming collisions.
1548 Board files could also accept input variables from user config files.
1549 For example, there might be a @code{J4_JUMPER} setting used to identify
1550 what kind of flash memory a development board is using, or how to set
1551 up other clocks and peripherals.
1553 @subsection Variable Naming Convention
1554 @cindex variable names
1556 Most boards have only one instance of a chip.
1557 However, it should be easy to create a board with more than
1558 one such chip (as shown above).
1559 Accordingly, we encourage these conventions for naming
1560 variables associated with different @file{target.cfg} files,
1561 to promote consistency and
1562 so that board files can override target defaults.
1564 Inputs to target config files include:
1566 @itemize @bullet
1567 @item @code{CHIPNAME} ...
1568 This gives a name to the overall chip, and is used as part of
1569 tap identifier dotted names.
1570 While the default is normally provided by the chip manufacturer,
1571 board files may need to distinguish between instances of a chip.
1572 @item @code{ENDIAN} ...
1573 By default @option{little} - although chips may hard-wire @option{big}.
1574 Chips that can't change endianness don't need to use this variable.
1575 @item @code{CPUTAPID} ...
1576 When OpenOCD examines the JTAG chain, it can be told verify the
1577 chips against the JTAG IDCODE register.
1578 The target file will hold one or more defaults, but sometimes the
1579 chip in a board will use a different ID (perhaps a newer revision).
1580 @end itemize
1582 Outputs from target config files include:
1584 @itemize @bullet
1585 @item @code{_TARGETNAME} ...
1586 By convention, this variable is created by the target configuration
1587 script. The board configuration file may make use of this variable to
1588 configure things like a ``reset init'' script, or other things
1589 specific to that board and that target.
1590 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1591 @code{_TARGETNAME1}, ... etc.
1592 @end itemize
1594 @subsection The reset-init Event Handler
1595 @cindex event, reset-init
1596 @cindex reset-init handler
1598 Board config files run in the OpenOCD configuration stage;
1599 they can't use TAPs or targets, since they haven't been
1600 fully set up yet.
1601 This means you can't write memory or access chip registers;
1602 you can't even verify that a flash chip is present.
1603 That's done later in event handlers, of which the target @code{reset-init}
1604 handler is one of the most important.
1606 Except on microcontrollers, the basic job of @code{reset-init} event
1607 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1608 Microcontrollers rarely use boot loaders; they run right out of their
1609 on-chip flash and SRAM memory. But they may want to use one of these
1610 handlers too, if just for developer convenience.
1612 @quotation Note
1613 Because this is so very board-specific, and chip-specific, no examples
1614 are included here.
1615 Instead, look at the board config files distributed with OpenOCD.
1616 If you have a boot loader, its source code will help; so will
1617 configuration files for other JTAG tools
1618 (@pxref{Translating Configuration Files}).
1619 @end quotation
1621 Some of this code could probably be shared between different boards.
1622 For example, setting up a DRAM controller often doesn't differ by
1623 much except the bus width (16 bits or 32?) and memory timings, so a
1624 reusable TCL procedure loaded by the @file{target.cfg} file might take
1625 those as parameters.
1626 Similarly with oscillator, PLL, and clock setup;
1627 and disabling the watchdog.
1628 Structure the code cleanly, and provide comments to help
1629 the next developer doing such work.
1630 (@emph{You might be that next person} trying to reuse init code!)
1632 The last thing normally done in a @code{reset-init} handler is probing
1633 whatever flash memory was configured. For most chips that needs to be
1634 done while the associated target is halted, either because JTAG memory
1635 access uses the CPU or to prevent conflicting CPU access.
1637 @subsection JTAG Clock Rate
1639 Before your @code{reset-init} handler has set up
1640 the PLLs and clocking, you may need to run with
1641 a low JTAG clock rate.
1642 @xref{JTAG Speed}.
1643 Then you'd increase that rate after your handler has
1644 made it possible to use the faster JTAG clock.
1645 When the initial low speed is board-specific, for example
1646 because it depends on a board-specific oscillator speed, then
1647 you should probably set it up in the board config file;
1648 if it's target-specific, it belongs in the target config file.
1650 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1651 @uref{} gives details.}
1652 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1653 Consult chip documentation to determine the peak JTAG clock rate,
1654 which might be less than that.
1656 @quotation Warning
1657 On most ARMs, JTAG clock detection is coupled to the core clock, so
1658 software using a @option{wait for interrupt} operation blocks JTAG access.
1659 Adaptive clocking provides a partial workaround, but a more complete
1660 solution just avoids using that instruction with JTAG debuggers.
1661 @end quotation
1663 If both the chip and the board support adaptive clocking,
1664 use the @command{jtag_rclk}
1665 command, in case your board is used with JTAG adapter which
1666 also supports it. Otherwise use @command{adapter_khz}.
1667 Set the slow rate at the beginning of the reset sequence,
1668 and the faster rate as soon as the clocks are at full speed.
1670 @anchor{The init_board procedure}
1671 @subsection The init_board procedure
1672 @cindex init_board procedure
1674 The concept of @code{init_board} procedure is very similar to @code{init_targets} (@xref{The init_targets procedure}.)
1675 - it's a replacement of ``linear'' configuration scripts. This procedure is meant to be executed when OpenOCD enters run
1676 stage (@xref{Entering the Run Stage},) after @code{init_targets}. The idea to have spearate @code{init_targets} and
1677 @code{init_board} procedures is to allow the first one to configure everything target specific (internal flash,
1678 internal RAM, etc.) and the second one to configure everything board specific (reset signals, chip frequency,
1679 reset-init event handler, external memory, etc.). Additionally ``linear'' board config file will most likely fail when
1680 target config file uses @code{init_targets} scheme (``linear'' script is executed before @code{init} and
1681 @code{init_targets} - after), so separating these two configuration stages is very convenient, as the easiest way to
1682 overcome this problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1683 need to override @code{init_targets} defined in target config files when they only need to to add some specifics.
1685 Just as @code{init_targets}, the @code{init_board} procedure can be overriden by ``next level'' script (which sources
1686 the original), allowing greater code reuse.
1688 @example
1689 ### board_file.cfg ###
1691 # source target file that does most of the config in init_targets
1692 source [find target/target.cfg]
1694 proc enable_fast_clock @{@} @{
1695 # enables fast on-board clock source
1696 # configures the chip to use it
1697 @}
1699 # initialize only board specifics - reset, clock, adapter frequency
1700 proc init_board @{@} @{
1701 reset_config trst_and_srst trst_pulls_srst
1703 $_TARGETNAME configure -event reset-init @{
1704 adapter_khz 1
1705 enable_fast_clock
1706 adapter_khz 10000
1707 @}
1708 @}
1709 @end example
1711 @section Target Config Files
1712 @cindex config file, target
1713 @cindex target config file
1715 Board config files communicate with target config files using
1716 naming conventions as described above, and may source one or
1717 more target config files like this:
1719 @example
1720 source [find target/FOOBAR.cfg]
1721 @end example
1723 The point of a target config file is to package everything
1724 about a given chip that board config files need to know.
1725 In summary the target files should contain
1727 @enumerate
1728 @item Set defaults
1729 @item Add TAPs to the scan chain
1730 @item Add CPU targets (includes GDB support)
1731 @item CPU/Chip/CPU-Core specific features
1732 @item On-Chip flash
1733 @end enumerate
1735 As a rule of thumb, a target file sets up only one chip.
1736 For a microcontroller, that will often include a single TAP,
1737 which is a CPU needing a GDB target, and its on-chip flash.
1739 More complex chips may include multiple TAPs, and the target
1740 config file may need to define them all before OpenOCD
1741 can talk to the chip.
1742 For example, some phone chips have JTAG scan chains that include
1743 an ARM core for operating system use, a DSP,
1744 another ARM core embedded in an image processing engine,
1745 and other processing engines.
1747 @subsection Default Value Boiler Plate Code
1749 All target configuration files should start with code like this,
1750 letting board config files express environment-specific
1751 differences in how things should be set up.
1753 @example
1754 # Boards may override chip names, perhaps based on role,
1755 # but the default should match what the vendor uses
1756 if @{ [info exists CHIPNAME] @} @{
1758 @} else @{
1759 set _CHIPNAME sam7x256
1760 @}
1762 # ONLY use ENDIAN with targets that can change it.
1763 if @{ [info exists ENDIAN] @} @{
1764 set _ENDIAN $ENDIAN
1765 @} else @{
1766 set _ENDIAN little
1767 @}
1769 # TAP identifiers may change as chips mature, for example with
1770 # new revision fields (the "3" here). Pick a good default; you
1771 # can pass several such identifiers to the "jtag newtap" command.
1772 if @{ [info exists CPUTAPID ] @} @{
1774 @} else @{
1775 set _CPUTAPID 0x3f0f0f0f
1776 @}
1777 @end example
1778 @c but 0x3f0f0f0f is for an str73x part ...
1780 @emph{Remember:} Board config files may include multiple target
1781 config files, or the same target file multiple times
1782 (changing at least @code{CHIPNAME}).
1784 Likewise, the target configuration file should define
1785 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1786 use it later on when defining debug targets:
1788 @example
1790 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1791 @end example
1793 @subsection Adding TAPs to the Scan Chain
1794 After the ``defaults'' are set up,
1795 add the TAPs on each chip to the JTAG scan chain.
1796 @xref{TAP Declaration}, and the naming convention
1797 for taps.
1799 In the simplest case the chip has only one TAP,
1800 probably for a CPU or FPGA.
1801 The config file for the Atmel AT91SAM7X256
1802 looks (in part) like this:
1804 @example
1805 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1806 @end example
1808 A board with two such at91sam7 chips would be able
1809 to source such a config file twice, with different
1810 values for @code{CHIPNAME}, so
1811 it adds a different TAP each time.
1813 If there are nonzero @option{-expected-id} values,
1814 OpenOCD attempts to verify the actual tap id against those values.
1815 It will issue error messages if there is mismatch, which
1816 can help to pinpoint problems in OpenOCD configurations.
1818 @example
1819 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1820 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1821 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1822 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1823 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1824 @end example
1826 There are more complex examples too, with chips that have
1827 multiple TAPs. Ones worth looking at include:
1829 @itemize
1830 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1831 plus a JRC to enable them
1832 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1833 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1834 is not currently used)
1835 @end itemize
1837 @subsection Add CPU targets
1839 After adding a TAP for a CPU, you should set it up so that
1840 GDB and other commands can use it.
1841 @xref{CPU Configuration}.
1842 For the at91sam7 example above, the command can look like this;
1843 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1844 to little endian, and this chip doesn't support changing that.
1846 @example
1848 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1849 @end example
1851 Work areas are small RAM areas associated with CPU targets.
1852 They are used by OpenOCD to speed up downloads,
1853 and to download small snippets of code to program flash chips.
1854 If the chip includes a form of ``on-chip-ram'' - and many do - define
1855 a work area if you can.
1856 Again using the at91sam7 as an example, this can look like:
1858 @example
1859 $_TARGETNAME configure -work-area-phys 0x00200000 \
1860 -work-area-size 0x4000 -work-area-backup 0
1861 @end example
1863 @anchor{Define CPU targets working in SMP}
1864 @subsection Define CPU targets working in SMP
1865 @cindex SMP
1866 After setting targets, you can define a list of targets working in SMP.
1868 @example
1869 set _TARGETNAME_1 $_CHIPNAME.cpu1
1870 set _TARGETNAME_2 $_CHIPNAME.cpu2
1871 target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap \
1872 -coreid 0 -dbgbase $_DAP_DBG1
1873 target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap \
1874 -coreid 1 -dbgbase $_DAP_DBG2
1875 #define 2 targets working in smp.
1876 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1877 @end example
1878 In the above example on cortex_a8, 2 cpus are working in SMP.
1879 In SMP only one GDB instance is created and :
1880 @itemize @bullet
1881 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1882 @item halt command triggers the halt of all targets in the list.
1883 @item resume command triggers the write context and the restart of all targets in the list.
1884 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1885 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1886 displayed by the GDB session @pxref{Using openocd SMP with GDB}.
1887 @end itemize
1889 The SMP behaviour can be disabled/enabled dynamically. On cortex_a8 following
1890 command have been implemented.
1891 @itemize @bullet
1892 @item cortex_a8 smp_on : enable SMP mode, behaviour is as described above.
1893 @item cortex_a8 smp_off : disable SMP mode, the current target is the one
1894 displayed in the GDB session, only this target is now controlled by GDB
1895 session. This behaviour is useful during system boot up.
1896 @item cortex_a8 smp_gdb : display/fix the core id displayed in GDB session see
1897 following example.
1898 @end itemize
1900 @example
1901 >cortex_a8 smp_gdb
1902 gdb coreid 0 -> -1
1903 #0 : coreid 0 is displayed to GDB ,
1904 #-> -1 : next resume triggers a real resume
1905 > cortex_a8 smp_gdb 1
1906 gdb coreid 0 -> 1
1907 #0 :coreid 0 is displayed to GDB ,
1908 #->1 : next resume displays coreid 1 to GDB
1909 > resume
1910 > cortex_a8 smp_gdb
1911 gdb coreid 1 -> 1
1912 #1 :coreid 1 is displayed to GDB ,
1913 #->1 : next resume displays coreid 1 to GDB
1914 > cortex_a8 smp_gdb -1
1915 gdb coreid 1 -> -1
1916 #1 :coreid 1 is displayed to GDB,
1917 #->-1 : next resume triggers a real resume
1918 @end example
1921 @subsection Chip Reset Setup
1923 As a rule, you should put the @command{reset_config} command
1924 into the board file. Most things you think you know about a
1925 chip can be tweaked by the board.
1927 Some chips have specific ways the TRST and SRST signals are
1928 managed. In the unusual case that these are @emph{chip specific}
1929 and can never be changed by board wiring, they could go here.
1930 For example, some chips can't support JTAG debugging without
1931 both signals.
1933 Provide a @code{reset-assert} event handler if you can.
1934 Such a handler uses JTAG operations to reset the target,
1935 letting this target config be used in systems which don't
1936 provide the optional SRST signal, or on systems where you
1937 don't want to reset all targets at once.
1938 Such a handler might write to chip registers to force a reset,
1939 use a JRC to do that (preferable -- the target may be wedged!),
1940 or force a watchdog timer to trigger.
1941 (For Cortex-M3 targets, this is not necessary. The target
1942 driver knows how to use trigger an NVIC reset when SRST is
1943 not available.)
1945 Some chips need special attention during reset handling if
1946 they're going to be used with JTAG.
1947 An example might be needing to send some commands right
1948 after the target's TAP has been reset, providing a
1949 @code{reset-deassert-post} event handler that writes a chip
1950 register to report that JTAG debugging is being done.
1951 Another would be reconfiguring the watchdog so that it stops
1952 counting while the core is halted in the debugger.
1954 JTAG clocking constraints often change during reset, and in
1955 some cases target config files (rather than board config files)
1956 are the right places to handle some of those issues.
1957 For example, immediately after reset most chips run using a
1958 slower clock than they will use later.
1959 That means that after reset (and potentially, as OpenOCD
1960 first starts up) they must use a slower JTAG clock rate
1961 than they will use later.
1962 @xref{JTAG Speed}.
1964 @quotation Important
1965 When you are debugging code that runs right after chip
1966 reset, getting these issues right is critical.
1967 In particular, if you see intermittent failures when
1968 OpenOCD verifies the scan chain after reset,
1969 look at how you are setting up JTAG clocking.
1970 @end quotation
1972 @anchor{The init_targets procedure}
1973 @subsection The init_targets procedure
1974 @cindex init_targets procedure
1976 Target config files can either be ``linear'' (script executed line-by-line when parsed in configuration stage,
1977 @xref{Configuration Stage},) or they can contain a special procedure called @code{init_targets}, which will be executed
1978 when entering run stage (after parsing all config files or after @code{init} command, @xref{Entering the Run Stage}.)
1979 Such procedure can be overriden by ``next level'' script (which sources the original). This concept faciliates code
1980 reuse when basic target config files provide generic configuration procedures and @code{init_targets} procedure, which
1981 can then be sourced and enchanced or changed in a ``more specific'' target config file. This is not possible with
1982 ``linear'' config scripts, because sourcing them executes every initialization commands they provide.
1984 @example
1985 ### generic_file.cfg ###
1987 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1988 # basic initialization procedure ...
1989 @}
1991 proc init_targets @{@} @{
1992 # initializes generic chip with 4kB of flash and 1kB of RAM
1993 setup_my_chip MY_GENERIC_CHIP 4096 1024
1994 @}
1996 ### specific_file.cfg ###
1998 source [find target/generic_file.cfg]
2000 proc init_targets @{@} @{
2001 # initializes specific chip with 128kB of flash and 64kB of RAM
2002 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
2003 @}
2004 @end example
2006 The easiest way to convert ``linear'' config files to @code{init_targets} version is to enclose every line of ``code''
2007 (i.e. not @code{source} commands, procedures, etc.) in this procedure.
2009 For an example of this scheme see LPC2000 target config files.
2011 The @code{init_boards} procedure is a similar concept concerning board config files (@xref{The init_board procedure}.)
2013 @subsection ARM Core Specific Hacks
2015 If the chip has a DCC, enable it. If the chip is an ARM9 with some
2016 special high speed download features - enable it.
2018 If present, the MMU, the MPU and the CACHE should be disabled.
2020 Some ARM cores are equipped with trace support, which permits
2021 examination of the instruction and data bus activity. Trace
2022 activity is controlled through an ``Embedded Trace Module'' (ETM)
2023 on one of the core's scan chains. The ETM emits voluminous data
2024 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
2025 If you are using an external trace port,
2026 configure it in your board config file.
2027 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2028 configure it in your target config file.
2030 @example
2031 etm config $_TARGETNAME 16 normal full etb
2032 etb config $_TARGETNAME $_CHIPNAME.etb
2033 @end example
2035 @subsection Internal Flash Configuration
2037 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2039 @b{Never ever} in the ``target configuration file'' define any type of
2040 flash that is external to the chip. (For example a BOOT flash on
2041 Chip Select 0.) Such flash information goes in a board file - not
2042 the TARGET (chip) file.
2044 Examples:
2045 @itemize @bullet
2046 @item at91sam7x256 - has 256K flash YES enable it.
2047 @item str912 - has flash internal YES enable it.
2048 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2049 @item pxa270 - again - CS0 flash - it goes in the board file.
2050 @end itemize
2052 @anchor{Translating Configuration Files}
2053 @section Translating Configuration Files
2054 @cindex translation
2055 If you have a configuration file for another hardware debugger
2056 or toolset (Abatron, BDI2000, BDI3000, CCS,
2057 Lauterbach, Segger, Macraigor, etc.), translating
2058 it into OpenOCD syntax is often quite straightforward. The most tricky
2059 part of creating a configuration script is oftentimes the reset init
2060 sequence where e.g. PLLs, DRAM and the like is set up.
2062 One trick that you can use when translating is to write small
2063 Tcl procedures to translate the syntax into OpenOCD syntax. This
2064 can avoid manual translation errors and make it easier to
2065 convert other scripts later on.
2067 Example of transforming quirky arguments to a simple search and
2068 replace job:
2070 @example
2071 # Lauterbach syntax(?)
2072 #
2073 # Data.Set c15:0x042f %long 0x40000015
2074 #
2075 # OpenOCD syntax when using procedure below.
2076 #
2077 # setc15 0x01 0x00050078
2079 proc setc15 @{regs value@} @{
2080 global TARGETNAME
2082 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2084 arm mcr 15 [expr ($regs>>12)&0x7] \
2085 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2086 [expr ($regs>>8)&0x7] $value
2087 @}
2088 @end example
2092 @node Daemon Configuration
2093 @chapter Daemon Configuration
2094 @cindex initialization
2095 The commands here are commonly found in the openocd.cfg file and are
2096 used to specify what TCP/IP ports are used, and how GDB should be
2097 supported.
2099 @anchor{Configuration Stage}
2100 @section Configuration Stage
2101 @cindex configuration stage
2102 @cindex config command
2104 When the OpenOCD server process starts up, it enters a
2105 @emph{configuration stage} which is the only time that
2106 certain commands, @emph{configuration commands}, may be issued.
2107 Normally, configuration commands are only available
2108 inside startup scripts.
2110 In this manual, the definition of a configuration command is
2111 presented as a @emph{Config Command}, not as a @emph{Command}
2112 which may be issued interactively.
2113 The runtime @command{help} command also highlights configuration
2114 commands, and those which may be issued at any time.
2116 Those configuration commands include declaration of TAPs,
2117 flash banks,
2118 the interface used for JTAG communication,
2119 and other basic setup.
2120 The server must leave the configuration stage before it
2121 may access or activate TAPs.
2122 After it leaves this stage, configuration commands may no
2123 longer be issued.
2125 @anchor{Entering the Run Stage}
2126 @section Entering the Run Stage
2128 The first thing OpenOCD does after leaving the configuration
2129 stage is to verify that it can talk to the scan chain
2130 (list of TAPs) which has been configured.
2131 It will warn if it doesn't find TAPs it expects to find,
2132 or finds TAPs that aren't supposed to be there.
2133 You should see no errors at this point.
2134 If you see errors, resolve them by correcting the
2135 commands you used to configure the server.
2136 Common errors include using an initial JTAG speed that's too
2137 fast, and not providing the right IDCODE values for the TAPs
2138 on the scan chain.
2140 Once OpenOCD has entered the run stage, a number of commands
2141 become available.
2142 A number of these relate to the debug targets you may have declared.
2143 For example, the @command{mww} command will not be available until
2144 a target has been successfuly instantiated.
2145 If you want to use those commands, you may need to force
2146 entry to the run stage.
2148 @deffn {Config Command} init
2149 This command terminates the configuration stage and
2150 enters the run stage. This helps when you need to have
2151 the startup scripts manage tasks such as resetting the target,
2152 programming flash, etc. To reset the CPU upon startup, add "init" and
2153 "reset" at the end of the config script or at the end of the OpenOCD
2154 command line using the @option{-c} command line switch.
2156 If this command does not appear in any startup/configuration file
2157 OpenOCD executes the command for you after processing all
2158 configuration files and/or command line options.
2160 @b{NOTE:} This command normally occurs at or near the end of your
2161 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2162 targets ready. For example: If your openocd.cfg file needs to
2163 read/write memory on your target, @command{init} must occur before
2164 the memory read/write commands. This includes @command{nand probe}.
2165 @end deffn
2167 @deffn {Overridable Procedure} jtag_init
2168 This is invoked at server startup to verify that it can talk
2169 to the scan chain (list of TAPs) which has been configured.
2171 The default implementation first tries @command{jtag arp_init},
2172 which uses only a lightweight JTAG reset before examining the
2173 scan chain.
2174 If that fails, it tries again, using a harder reset
2175 from the overridable procedure @command{init_reset}.
2177 Implementations must have verified the JTAG scan chain before
2178 they return.
2179 This is done by calling @command{jtag arp_init}
2180 (or @command{jtag arp_init-reset}).
2181 @end deffn
2183 @anchor{TCP/IP Ports}
2184 @section TCP/IP Ports
2185 @cindex TCP port
2186 @cindex server
2187 @cindex port
2188 @cindex security
2189 The OpenOCD server accepts remote commands in several syntaxes.
2190 Each syntax uses a different TCP/IP port, which you may specify
2191 only during configuration (before those ports are opened).
2193 For reasons including security, you may wish to prevent remote
2194 access using one or more of these ports.
2195 In such cases, just specify the relevant port number as zero.
2196 If you disable all access through TCP/IP, you will need to
2197 use the command line @option{-pipe} option.
2199 @deffn {Command} gdb_port [number]
2200 @cindex GDB server
2201 Normally gdb listens to a TCP/IP port, but GDB can also
2202 communicate via pipes(stdin/out or named pipes). The name
2203 "gdb_port" stuck because it covers probably more than 90% of
2204 the normal use cases.
2206 No arguments reports GDB port. "pipe" means listen to stdin
2207 output to stdout, an integer is base port number, "disable"
2208 disables the gdb server.
2210 When using "pipe", also use log_output to redirect the log
2211 output to a file so as not to flood the stdin/out pipes.
2213 The -p/--pipe option is deprecated and a warning is printed
2214 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2216 Any other string is interpreted as named pipe to listen to.
2217 Output pipe is the same name as input pipe, but with 'o' appended,
2218 e.g. /var/gdb, /var/gdbo.
2220 The GDB port for the first target will be the base port, the
2221 second target will listen on gdb_port + 1, and so on.
2222 When not specified during the configuration stage,
2223 the port @var{number} defaults to 3333.
2224 @end deffn
2226 @deffn {Command} tcl_port [number]
2227 Specify or query the port used for a simplified RPC
2228 connection that can be used by clients to issue TCL commands and get the
2229 output from the Tcl engine.
2230 Intended as a machine interface.
2231 When not specified during the configuration stage,
2232 the port @var{number} defaults to 6666.
2234 @end deffn
2236 @deffn {Command} telnet_port [number]
2237 Specify or query the
2238 port on which to listen for incoming telnet connections.
2239 This port is intended for interaction with one human through TCL commands.
2240 When not specified during the configuration stage,
2241 the port @var{number} defaults to 4444.
2242 When specified as zero, this port is not activated.
2243 @end deffn
2245 @anchor{GDB Configuration}
2246 @section GDB Configuration
2247 @cindex GDB
2248 @cindex GDB configuration
2249 You can reconfigure some GDB behaviors if needed.
2250 The ones listed here are static and global.
2251 @xref{Target Configuration}, about configuring individual targets.
2252 @xref{Target Events}, about configuring target-specific event handling.
2254 @anchor{gdb_breakpoint_override}
2255 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2256 Force breakpoint type for gdb @command{break} commands.
2257 This option supports GDB GUIs which don't
2258 distinguish hard versus soft breakpoints, if the default OpenOCD and
2259 GDB behaviour is not sufficient. GDB normally uses hardware
2260 breakpoints if the memory map has been set up for flash regions.
2261 @end deffn
2263 @anchor{gdb_flash_program}
2264 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2265 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2266 vFlash packet is received.
2267 The default behaviour is @option{enable}.
2268 @end deffn
2270 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2271 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2272 requested. GDB will then know when to set hardware breakpoints, and program flash
2273 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2274 for flash programming to work.
2275 Default behaviour is @option{enable}.
2276 @xref{gdb_flash_program}.
2277 @end deffn
2279 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2280 Specifies whether data aborts cause an error to be reported
2281 by GDB memory read packets.
2282 The default behaviour is @option{disable};
2283 use @option{enable} see these errors reported.
2284 @end deffn
2286 @anchor{Event Polling}
2287 @section Event Polling
2289 Hardware debuggers are parts of asynchronous systems,
2290 where significant events can happen at any time.
2291 The OpenOCD server needs to detect some of these events,
2292 so it can report them to through TCL command line
2293 or to GDB.
2295 Examples of such events include:
2297 @itemize
2298 @item One of the targets can stop running ... maybe it triggers
2299 a code breakpoint or data watchpoint, or halts itself.
2300 @item Messages may be sent over ``debug message'' channels ... many
2301 targets support such messages sent over JTAG,
2302 for receipt by the person debugging or tools.
2303 @item Loss of power ... some adapters can detect these events.
2304 @item Resets not issued through JTAG ... such reset sources
2305 can include button presses or other system hardware, sometimes
2306 including the target itself (perhaps through a watchdog).
2307 @item Debug instrumentation sometimes supports event triggering
2308 such as ``trace buffer full'' (so it can quickly be emptied)
2309 or other signals (to correlate with code behavior).
2310 @end itemize
2312 None of those events are signaled through standard JTAG signals.
2313 However, most conventions for JTAG connectors include voltage
2314 level and system reset (SRST) signal detection.
2315 Some connectors also include instrumentation signals, which
2316 can imply events when those signals are inputs.
2318 In general, OpenOCD needs to periodically check for those events,
2319 either by looking at the status of signals on the JTAG connector
2320 or by sending synchronous ``tell me your status'' JTAG requests
2321 to the various active targets.
2322 There is a command to manage and monitor that polling,
2323 which is normally done in the background.
2325 @deffn Command poll [@option{on}|@option{off}]
2326 Poll the current target for its current state.
2327 (Also, @pxref{target curstate}.)
2328 If that target is in debug mode, architecture
2329 specific information about the current state is printed.
2330 An optional parameter
2331 allows background polling to be enabled and disabled.
2333 You could use this from the TCL command shell, or
2334 from GDB using @command{monitor poll} command.
2335 Leave background polling enabled while you're using GDB.
2336 @example
2337 > poll
2338 background polling: on
2339 target state: halted
2340 target halted in ARM state due to debug-request, \
2341 current mode: Supervisor
2342 cpsr: 0x800000d3 pc: 0x11081bfc
2343 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2344 >
2345 @end example
2346 @end deffn
2348 @node Debug Adapter Configuration
2349 @chapter Debug Adapter Configuration
2350 @cindex config file, interface
2351 @cindex interface config file
2353 Correctly installing OpenOCD includes making your operating system give
2354 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2355 are used to select which one is used, and to configure how it is used.
2357 @quotation Note
2358 Because OpenOCD started out with a focus purely on JTAG, you may find
2359 places where it wrongly presumes JTAG is the only transport protocol
2360 in use. Be aware that recent versions of OpenOCD are removing that
2361 limitation. JTAG remains more functional than most other transports.
2362 Other transports do not support boundary scan operations, or may be
2363 specific to a given chip vendor. Some might be usable only for
2364 programming flash memory, instead of also for debugging.
2365 @end quotation
2367 Debug Adapters/Interfaces/Dongles are normally configured
2368 through commands in an interface configuration
2369 file which is sourced by your @file{openocd.cfg} file, or
2370 through a command line @option{-f interface/....cfg} option.
2372 @example
2373 source [find interface/olimex-jtag-tiny.cfg]
2374 @end example
2376 These commands tell
2377 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2378 A few cases are so simple that you only need to say what driver to use:
2380 @example
2381 # jlink interface
2382 interface jlink
2383 @end example
2385 Most adapters need a bit more configuration than that.
2388 @section Interface Configuration
2390 The interface command tells OpenOCD what type of debug adapter you are
2391 using. Depending on the type of adapter, you may need to use one or
2392 more additional commands to further identify or configure the adapter.
2394 @deffn {Config Command} {interface} name
2395 Use the interface driver @var{name} to connect to the
2396 target.
2397 @end deffn
2399 @deffn Command {interface_list}
2400 List the debug adapter drivers that have been built into
2401 the running copy of OpenOCD.
2402 @end deffn
2403 @deffn Command {interface transports} transport_name+
2404 Specifies the transports supported by this debug adapter.
2405 The adapter driver builds-in similar knowledge; use this only
2406 when external configuration (such as jumpering) changes what
2407 the hardware can support.
2408 @end deffn
2412 @deffn Command {adapter_name}
2413 Returns the name of the debug adapter driver being used.
2414 @end deffn
2416 @section Interface Drivers
2418 Each of the interface drivers listed here must be explicitly
2419 enabled when OpenOCD is configured, in order to be made
2420 available at run time.
2422 @deffn {Interface Driver} {amt_jtagaccel}
2423 Amontec Chameleon in its JTAG Accelerator configuration,
2424 connected to a PC's EPP mode parallel port.
2425 This defines some driver-specific commands:
2427 @deffn {Config Command} {parport_port} number
2428 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2429 the number of the @file{/dev/parport} device.
2430 @end deffn
2432 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2433 Displays status of RTCK option.
2434 Optionally sets that option first.
2435 @end deffn
2436 @end deffn
2438 @deffn {Interface Driver} {arm-jtag-ew}
2439 Olimex ARM-JTAG-EW USB adapter
2440 This has one driver-specific command:
2442 @deffn Command {armjtagew_info}
2443 Logs some status
2444 @end deffn
2445 @end deffn
2447 @deffn {Interface Driver} {at91rm9200}
2448 Supports bitbanged JTAG from the local system,
2449 presuming that system is an Atmel AT91rm9200
2450 and a specific set of GPIOs is used.
2451 @c command: at91rm9200_device NAME
2452 @c chooses among list of bit configs ... only one option
2453 @end deffn
2455 @deffn {Interface Driver} {dummy}
2456 A dummy software-only driver for debugging.
2457 @end deffn
2459 @deffn {Interface Driver} {ep93xx}
2460 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2461 @end deffn
2463 @deffn {Interface Driver} {ft2232}
2464 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2465 These interfaces have several commands, used to configure the driver
2466 before initializing the JTAG scan chain:
2468 @deffn {Config Command} {ft2232_device_desc} description
2469 Provides the USB device description (the @emph{iProduct string})
2470 of the FTDI FT2232 device. If not
2471 specified, the FTDI default value is used. This setting is only valid
2472 if compiled with FTD2XX support.
2473 @end deffn
2475 @deffn {Config Command} {ft2232_serial} serial-number
2476 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2477 in case the vendor provides unique IDs and more than one FT2232 device
2478 is connected to the host.
2479 If not specified, serial numbers are not considered.
2480 (Note that USB serial numbers can be arbitrary Unicode strings,
2481 and are not restricted to containing only decimal digits.)
2482 @end deffn
2484 @deffn {Config Command} {ft2232_layout} name
2485 Each vendor's FT2232 device can use different GPIO signals
2486 to control output-enables, reset signals, and LEDs.
2487 Currently valid layout @var{name} values include:
2488 @itemize @minus
2489 @item @b{axm0432_jtag} Axiom AXM-0432
2490 @item @b{comstick} Hitex STR9 comstick
2491 @item @b{cortino} Hitex Cortino JTAG interface
2492 @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
2493 either for the local Cortex-M3 (SRST only)
2494 or in a passthrough mode (neither SRST nor TRST)
2495 This layout can not support the SWO trace mechanism, and should be
2496 used only for older boards (before rev C).
2497 @item @b{luminary_icdi} This layout should be used with most TI/Luminary
2498 eval boards, including Rev C LM3S811 eval boards and the eponymous
2499 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2500 to debug some other target. It can support the SWO trace mechanism.
2501 @item @b{flyswatter} Tin Can Tools Flyswatter
2502 @item @b{icebear} ICEbear JTAG adapter from Section 5
2503 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2504 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2505 @item @b{m5960} American Microsystems M5960
2506 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2507 @item @b{oocdlink} OOCDLink
2508 @c oocdlink ~= jtagkey_prototype_v1
2509 @item @b{redbee-econotag} Integrated with a Redbee development board.
2510 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2511 @item @b{sheevaplug} Marvell Sheevaplug development kit
2512 @item @b{signalyzer} Xverve Signalyzer
2513 @item @b{stm32stick} Hitex STM32 Performance Stick
2514 @item @b{turtelizer2} egnite Software turtelizer2
2515 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2516 @end itemize
2517 @end deffn
2519 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2520 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2521 default values are used.
2522 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2523 @example
2524 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2525 @end example
2526 @end deffn
2528 @deffn {Config Command} {ft2232_latency} ms
2529 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2530 ft2232_read() fails to return the expected number of bytes. This can be caused by
2531 USB communication delays and has proved hard to reproduce and debug. Setting the
2532 FT2232 latency timer to a larger value increases delays for short USB packets but it
2533 also reduces the risk of timeouts before receiving the expected number of bytes.
2534 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2535 @end deffn
2537 For example, the interface config file for a
2538 Turtelizer JTAG Adapter looks something like this:
2540 @example
2541 interface ft2232
2542 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2543 ft2232_layout turtelizer2
2544 ft2232_vid_pid 0x0403 0xbdc8
2545 @end example
2546 @end deffn
2548 @deffn {Interface Driver} {remote_bitbang}
2549 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2550 with a remote process and sends ASCII encoded bitbang requests to that process
2551 instead of directly driving JTAG.
2553 The remote_bitbang driver is useful for debugging software running on
2554 processors which are being simulated.
2556 @deffn {Config Command} {remote_bitbang_port} number
2557 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2558 sockets instead of TCP.
2559 @end deffn
2561 @deffn {Config Command} {remote_bitbang_host} hostname
2562 Specifies the hostname of the remote process to connect to using TCP, or the
2563 name of the UNIX socket to use if remote_bitbang_port is 0.
2564 @end deffn
2566 For example, to connect remotely via TCP to the host foobar you might have
2567 something like:
2569 @example
2570 interface remote_bitbang
2571 remote_bitbang_port 3335
2572 remote_bitbang_host foobar
2573 @end example
2575 To connect to another process running locally via UNIX sockets with socket
2576 named mysocket:
2578 @example
2579 interface remote_bitbang
2580 remote_bitbang_port 0
2581 remote_bitbang_host mysocket
2582 @end example
2583 @end deffn
2585 @deffn {Interface Driver} {usb_blaster}
2586 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2587 for FTDI chips. These interfaces have several commands, used to
2588 configure the driver before initializing the JTAG scan chain:
2590 @deffn {Config Command} {usb_blaster_device_desc} description
2591 Provides the USB device description (the @emph{iProduct string})
2592 of the FTDI FT245 device. If not
2593 specified, the FTDI default value is used. This setting is only valid
2594 if compiled with FTD2XX support.
2595 @end deffn
2597 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2598 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2599 default values are used.
2600 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2601 Altera USB-Blaster (default):
2602 @example
2603 usb_blaster_vid_pid 0x09FB 0x6001
2604 @end example
2605 The following VID/PID is for Kolja Waschk's USB JTAG:
2606 @example
2607 usb_blaster_vid_pid 0x16C0 0x06AD
2608 @end example
2609 @end deffn
2611 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2612 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2613 female JTAG header). These pins can be used as SRST and/or TRST provided the
2614 appropriate connections are made on the target board.
2616 For example, to use pin 6 as SRST (as with an AVR board):
2617 @example
2618 $_TARGETNAME configure -event reset-assert \
2619 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2620 @end example
2621 @end deffn
2623 @end deffn
2625 @deffn {Interface Driver} {gw16012}
2626 Gateworks GW16012 JTAG programmer.
2627 This has one driver-specific command:
2629 @deffn {Config Command} {parport_port} [port_number]
2630 Display either the address of the I/O port
2631 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2632 If a parameter is provided, first switch to use that port.
2633 This is a write-once setting.
2634 @end deffn
2635 @end deffn
2637 @deffn {Interface Driver} {jlink}
2638 Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
2640 @quotation Compatibility Note
2641 Segger released many firmware versions for the many harware versions they
2642 produced. OpenOCD was extensively tested and intended to run on all of them,
2643 but some combinations were reported as incompatible. As a general
2644 recommendation, it is advisable to use the latest firmware version
2645 available for each hardware version. However the current V8 is a moving
2646 target, and Segger firmware versions released after the OpenOCD was
2647 released may not be compatible. In such cases it is recommended to
2648 revert to the last known functional version. For 0.5.0, this is from
2649 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2650 version is from "May 3 2012 18:36:22", packed with 4.46f.
2651 @end quotation
2653 @deffn {Command} {jlink caps}
2654 Display the device firmware capabilities.
2655 @end deffn
2656 @deffn {Command} {jlink info}
2657 Display various device information, like hardware version, firmware version, current bus status.
2658 @end deffn
2659 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2660 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2661 @end deffn
2662 @deffn {Command} {jlink config}
2663 Display the J-Link configuration.
2664 @end deffn
2665 @deffn {Command} {jlink config kickstart} [val]
2666 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2667 @end deffn
2668 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2669 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2670 @end deffn
2671 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2672 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2673 E the bit of the subnet mask and
2674 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2675 @end deffn
2676 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2677 Set the USB address; this will also change the product id. Without argument, show the USB address.
2678 @end deffn
2679 @deffn {Command} {jlink config reset}
2680 Reset the current configuration.
2681 @end deffn
2682 @deffn {Command} {jlink config save}
2683 Save the current configuration to the internal persistent storage.
2684 @end deffn
2685 @deffn {Config} {jlink pid} val
2686 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2687 @end deffn
2688 @end deffn
2690 @deffn {Interface Driver} {parport}
2691 Supports PC parallel port bit-banging cables:
2692 Wigglers, PLD download cable, and more.
2693 These interfaces have several commands, used to configure the driver
2694 before initializing the JTAG scan chain:
2696 @deffn {Config Command} {parport_cable} name
2697 Set the layout of the parallel port cable used to connect to the target.
2698 This is a write-once setting.
2699 Currently valid cable @var{name} values include:
2701 @itemize @minus
2702 @item @b{altium} Altium Universal JTAG cable.
2703 @item @b{arm-jtag} Same as original wiggler except SRST and
2704 TRST connections reversed and TRST is also inverted.
2705 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2706 in configuration mode. This is only used to
2707 program the Chameleon itself, not a connected target.
2708 @item @b{dlc5} The Xilinx Parallel cable III.
2709 @item @b{flashlink} The ST Parallel cable.
2710 @item @b{lattice} Lattice ispDOWNLOAD Cable
2711 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2712 some versions of
2713 Amontec's Chameleon Programmer. The new version available from
2714 the website uses the original Wiggler layout ('@var{wiggler}')
2715 @item @b{triton} The parallel port adapter found on the
2716 ``Karo Triton 1 Development Board''.
2717 This is also the layout used by the HollyGates design
2718 (see @uref{}).
2719 @item @b{wiggler} The original Wiggler layout, also supported by
2720 several clones, such as the Olimex ARM-JTAG
2721 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2722 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2723 @end itemize
2724 @end deffn
2726 @deffn {Config Command} {parport_port} [port_number]
2727 Display either the address of the I/O port
2728 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2729 If a parameter is provided, first switch to use that port.
2730 This is a write-once setting.
2732 When using PPDEV to access the parallel port, use the number of the parallel port:
2733 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2734 you may encounter a problem.
2735 @end deffn
2737 @deffn Command {parport_toggling_time} [nanoseconds]
2738 Displays how many nanoseconds the hardware needs to toggle TCK;
2739 the parport driver uses this value to obey the
2740 @command{adapter_khz} configuration.
2741 When the optional @var{nanoseconds} parameter is given,
2742 that setting is changed before displaying the current value.
2744 The default setting should work reasonably well on commodity PC hardware.
2745 However, you may want to calibrate for your specific hardware.
2746 @quotation Tip
2747 To measure the toggling time with a logic analyzer or a digital storage
2748 oscilloscope, follow the procedure below:
2749 @example
2750 > parport_toggling_time 1000
2751 > adapter_khz 500
2752 @end example
2753 This sets the maximum JTAG clock speed of the hardware, but
2754 the actual speed probably deviates from the requested 500 kHz.
2755 Now, measure the time between the two closest spaced TCK transitions.
2756 You can use @command{runtest 1000} or something similar to generate a
2757 large set of samples.
2758 Update the setting to match your measurement:
2759 @example
2760 > parport_toggling_time <measured nanoseconds>
2761 @end example
2762 Now the clock speed will be a better match for @command{adapter_khz rate}
2763 commands given in OpenOCD scripts and event handlers.
2765 You can do something similar with many digital multimeters, but note
2766 that you'll probably need to run the clock continuously for several
2767 seconds before it decides what clock rate to show. Adjust the
2768 toggling time up or down until the measured clock rate is a good
2769 match for the adapter_khz rate you specified; be conservative.
2770 @end quotation
2771 @end deffn
2773 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2774 This will configure the parallel driver to write a known
2775 cable-specific value to the parallel interface on exiting OpenOCD.
2776 @end deffn
2778 For example, the interface configuration file for a
2779 classic ``Wiggler'' cable on LPT2 might look something like this:
2781 @example
2782 interface parport
2783 parport_port 0x278
2784 parport_cable wiggler
2785 @end example
2786 @end deffn
2788 @deffn {Interface Driver} {presto}
2789 ASIX PRESTO USB JTAG programmer.
2790 @deffn {Config Command} {presto_serial} serial_string
2791 Configures the USB serial number of the Presto device to use.
2792 @end deffn
2793 @end deffn
2795 @deffn {Interface Driver} {rlink}
2796 Raisonance RLink USB adapter
2797 @end deffn
2799 @deffn {Interface Driver} {usbprog}
2800 usbprog is a freely programmable USB adapter.
2801 @end deffn
2803 @deffn {Interface Driver} {vsllink}
2804 vsllink is part of Versaloon which is a versatile USB programmer.
2806 @quotation Note
2807 This defines quite a few driver-specific commands,
2808 which are not currently documented here.
2809 @end quotation
2810 @end deffn
2812 @deffn {Interface Driver} {hla}
2813 This is a driver that supports multiple High Level Adapters.
2814 This type of adapter does not expose some of the lower level api's
2815 that OpenOCD would normally use to access the target.
2817 Currently supported adapters include the ST STLINK and TI ICDI.
2819 @deffn {Config Command} {hla_device_desc} description
2820 Currently Not Supported.
2821 @end deffn
2823 @deffn {Config Command} {hla_serial} serial
2824 Currently Not Supported.
2825 @end deffn
2827 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
2828 Specifies the adapter layout to use.
2829 @end deffn
2831 @deffn {Config Command} {hla_vid_pid} vid pid
2832 The vendor ID and product ID of the device.
2833 @end deffn
2835 @deffn {Config Command} {stlink_api} api_level
2836 Manually sets the stlink api used, valid options are 1 or 2. (@b{STLINK Only}).
2837 @end deffn
2838 @end deffn
2840 @deffn {Interface Driver} {opendous}
2841 opendous-jtag is a freely programmable USB adapter.
2842 @end deffn
2844 @deffn {Interface Driver} {ulink}
2845 This is the Keil ULINK v1 JTAG debugger.
2846 @end deffn
2848 @deffn {Interface Driver} {ZY1000}
2849 This is the Zylin ZY1000 JTAG debugger.
2850 @end deffn
2852 @quotation Note
2853 This defines some driver-specific commands,
2854 which are not currently documented here.
2855 @end quotation
2857 @deffn Command power [@option{on}|@option{off}]
2858 Turn power switch to target on/off.
2859 No arguments: print status.
2860 @end deffn
2862 @section Transport Configuration
2863 @cindex Transport
2864 As noted earlier, depending on the version of OpenOCD you use,
2865 and the debug adapter you are using,
2866 several transports may be available to
2867 communicate with debug targets (or perhaps to program flash memory).
2868 @deffn Command {transport list}
2869 displays the names of the transports supported by this
2870 version of OpenOCD.
2871 @end deffn
2873 @deffn Command {transport select} transport_name
2874 Select which of the supported transports to use in this OpenOCD session.
2875 The transport must be supported by the debug adapter hardware and by the
2876 version of OPenOCD you are using (including the adapter's driver).
2877 No arguments: returns name of session's selected transport.
2878 @end deffn
2880 @subsection JTAG Transport
2881 @cindex JTAG
2882 JTAG is the original transport supported by OpenOCD, and most
2883 of the OpenOCD commands support it.
2884 JTAG transports expose a chain of one or more Test Access Points (TAPs),
2885 each of which must be explicitly declared.
2886 JTAG supports both debugging and boundary scan testing.
2887 Flash programming support is built on top of debug support.
2888 @subsection SWD Transport
2889 @cindex SWD
2890 @cindex Serial Wire Debug
2891 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
2892 Debug Access Point (DAP, which must be explicitly declared.
2893 (SWD uses fewer signal wires than JTAG.)
2894 SWD is debug-oriented, and does not support boundary scan testing.
2895 Flash programming support is built on top of debug support.
2896 (Some processors support both JTAG and SWD.)
2897 @deffn Command {swd newdap} ...
2898 Declares a single DAP which uses SWD transport.
2899 Parameters are currently the same as "jtag newtap" but this is
2900 expected to change.
2901 @end deffn
2902 @deffn Command {swd wcr trn prescale}
2903 Updates TRN (turnaraound delay) and prescaling.fields of the
2904 Wire Control Register (WCR).
2905 No parameters: displays current settings.
2906 @end deffn
2908 @subsection SPI Transport
2909 @cindex SPI
2910 @cindex Serial Peripheral Interface
2911 The Serial Peripheral Interface (SPI) is a general purpose transport
2912 which uses four wire signaling. Some processors use it as part of a
2913 solution for flash programming.
2915 @anchor{JTAG Speed}
2916 @section JTAG Speed
2917 JTAG clock setup is part of system setup.
2918 It @emph{does not belong with interface setup} since any interface
2919 only knows a few of the constraints for the JTAG clock speed.
2920 Sometimes the JTAG speed is
2921 changed during the target initialization process: (1) slow at
2922 reset, (2) program the CPU clocks, (3) run fast.
2923 Both the "slow" and "fast" clock rates are functions of the
2924 oscillators used, the chip, the board design, and sometimes
2925 power management software that may be active.
2927 The speed used during reset, and the scan chain verification which
2928 follows reset, can be adjusted using a @code{reset-start}
2929 target event handler.
2930 It can then be reconfigured to a faster speed by a
2931 @code{reset-init} target event handler after it reprograms those
2932 CPU clocks, or manually (if something else, such as a boot loader,
2933 sets up those clocks).
2934 @xref{Target Events}.
2935 When the initial low JTAG speed is a chip characteristic, perhaps
2936 because of a required oscillator speed, provide such a handler
2937 in the target config file.
2938 When that speed is a function of a board-specific characteristic
2939 such as which speed oscillator is used, it belongs in the board
2940 config file instead.
2941 In both cases it's safest to also set the initial JTAG clock rate
2942 to that same slow speed, so that OpenOCD never starts up using a
2943 clock speed that's faster than the scan chain can support.
2945 @example
2946 jtag_rclk 3000
2947 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
2948 @end example
2950 If your system supports adaptive clocking (RTCK), configuring
2951 JTAG to use that is probably the most robust approach.
2952 However, it introduces delays to synchronize clocks; so it
2953 may not be the fastest solution.
2955 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
2956 instead of @command{adapter_khz}, but only for (ARM) cores and boards
2957 which support adaptive clocking.
2959 @deffn {Command} adapter_khz max_speed_kHz
2960 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
2961 JTAG interfaces usually support a limited number of
2962 speeds. The speed actually used won't be faster
2963 than the speed specified.
2965 Chip data sheets generally include a top JTAG clock rate.
2966 The actual rate is often a function of a CPU core clock,
2967 and is normally less than that peak rate.
2968 For example, most ARM cores accept at most one sixth of the CPU clock.
2970 Speed 0 (khz) selects RTCK method.
2971 @xref{FAQ RTCK}.
2972 If your system uses RTCK, you won't need to change the
2973 JTAG clocking after setup.
2974 Not all interfaces, boards, or targets support ``rtck''.
2975 If the interface device can not
2976 support it, an error is returned when you try to use RTCK.
2977 @end deffn
2979 @defun jtag_rclk fallback_speed_kHz
2980 @cindex adaptive clocking
2981 @cindex RTCK
2982 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
2983 If that fails (maybe the interface, board, or target doesn't
2984 support it), falls back to the specified frequency.
2985 @example
2986 # Fall back to 3mhz if RTCK is not supported
2987 jtag_rclk 3000
2988 @end example
2989 @end defun
2991 @node Reset Configuration
2992 @chapter Reset Configuration
2993 @cindex Reset Configuration
2995 Every system configuration may require a different reset
2996 configuration. This can also be quite confusing.
2997 Resets also interact with @var{reset-init} event handlers,
2998 which do things like setting up clocks and DRAM, and
2999 JTAG clock rates. (@xref{JTAG Speed}.)
3000 They can also interact with JTAG routers.
3001 Please see the various board files for examples.
3003 @quotation Note
3004 To maintainers and integrators:
3005 Reset configuration touches several things at once.
3006 Normally the board configuration file
3007 should define it and assume that the JTAG adapter supports
3008 everything that's wired up to the board's JTAG connector.
3010 However, the target configuration file could also make note
3011 of something the silicon vendor has done inside the chip,
3012 which will be true for most (or all) boards using that chip.
3013 And when the JTAG adapter doesn't support everything, the
3014 user configuration file will need to override parts of
3015 the reset configuration provided by other files.
3016 @end quotation
3018 @section Types of Reset
3020 There are many kinds of reset possible through JTAG, but
3021 they may not all work with a given board and adapter.
3022 That's part of why reset configuration can be error prone.
3024 @itemize @bullet
3025 @item
3026 @emph{System Reset} ... the @emph{SRST} hardware signal
3027 resets all chips connected to the JTAG adapter, such as processors,
3028 power management chips, and I/O controllers. Normally resets triggered
3029 with this signal behave exactly like pressing a RESET button.
3030 @item
3031 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3032 just the TAP controllers connected to the JTAG adapter.
3033 Such resets should not be visible to the rest of the system; resetting a
3034 device's TAP controller just puts that controller into a known state.
3035 @item
3036 @emph{Emulation Reset} ... many devices can be reset through JTAG
3037 commands. These resets are often distinguishable from system
3038 resets, either explicitly (a "reset reason" register says so)
3039 or implicitly (not all parts of the chip get reset).
3040 @item
3041 @emph{Other Resets} ... system-on-chip devices often support
3042 several other types of reset.
3043 You may need to arrange that a watchdog timer stops
3044 while debugging, preventing a watchdog reset.
3045 There may be individual module resets.
3046 @end itemize
3048 In the best case, OpenOCD can hold SRST, then reset
3049 the TAPs via TRST and send commands through JTAG to halt the
3050 CPU at the reset vector before the 1st instruction is executed.
3051 Then when it finally releases the SRST signal, the system is
3052 halted under debugger control before any code has executed.
3053 This is the behavior required to support the @command{reset halt}
3054 and @command{reset init} commands; after @command{reset init} a
3055 board-specific script might do things like setting up DRAM.
3056 (@xref{Reset Command}.)
3058 @anchor{SRST and TRST Issues}
3059 @section SRST and TRST Issues
3061 Because SRST and TRST are hardware signals, they can have a
3062 variety of system-specific constraints. Some of the most
3063 common issues are:
3065 @itemize @bullet
3067 @item @emph{Signal not available} ... Some boards don't wire
3068 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3069 support such signals even if they are wired up.
3070 Use the @command{reset_config} @var{signals} options to say
3071 when either of those signals is not connected.
3072 When SRST is not available, your code might not be able to rely
3073 on controllers having been fully reset during code startup.
3074 Missing TRST is not a problem, since JTAG-level resets can
3075 be triggered using with TMS signaling.
3077 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3078 adapter will connect SRST to TRST, instead of keeping them separate.
3079 Use the @command{reset_config} @var{combination} options to say
3080 when those signals aren't properly independent.
3082 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3083 delay circuit, reset supervisor, or on-chip features can extend
3084 the effect of a JTAG adapter's reset for some time after the adapter
3085 stops issuing the reset. For example, there may be chip or board
3086 requirements that all reset pulses last for at least a
3087 certain amount of time; and reset buttons commonly have
3088 hardware debouncing.
3089 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3090 commands to say when extra delays are needed.
3092 @item @emph{Drive type} ... Reset lines often have a pullup
3093 resistor, letting the JTAG interface treat them as open-drain
3094 signals. But that's not a requirement, so the adapter may need
3095 to use push/pull output drivers.
3096 Also, with weak pullups it may be advisable to drive
3097 signals to both levels (push/pull) to minimize rise times.
3098 Use the @command{reset_config} @var{trst_type} and
3099 @var{srst_type} parameters to say how to drive reset signals.
3101 @item @emph{Special initialization} ... Targets sometimes need
3102 special JTAG initialization sequences to handle chip-specific
3103 issues (not limited to errata).
3104 For example, certain JTAG commands might need to be issued while
3105 the system as a whole is in a reset state (SRST active)
3106 but the JTAG scan chain is usable (TRST inactive).
3107 Many systems treat combined assertion of SRST and TRST as a
3108 trigger for a harder reset than SRST alone.
3109 Such custom reset handling is discussed later in this chapter.
3110 @end itemize
3112 There can also be other issues.
3113 Some devices don't fully conform to the JTAG specifications.
3114 Trivial system-specific differences are common, such as
3115 SRST and TRST using slightly different names.
3116 There are also vendors who distribute key JTAG documentation for
3117 their chips only to developers who have signed a Non-Disclosure
3118 Agreement (NDA).
3120 Sometimes there are chip-specific extensions like a requirement to use
3121 the normally-optional TRST signal (precluding use of JTAG adapters which
3122 don't pass TRST through), or needing extra steps to complete a TAP reset.
3124 In short, SRST and especially TRST handling may be very finicky,
3125 needing to cope with both architecture and board specific constraints.
3127 @section Commands for Handling Resets
3129 @deffn {Command} adapter_nsrst_assert_width milliseconds
3130 Minimum amount of time (in milliseconds) OpenOCD should wait
3131 after asserting nSRST (active-low system reset) before
3132 allowing it to be deasserted.
3133 @end deffn
3135 @deffn {Command} adapter_nsrst_delay milliseconds
3136 How long (in milliseconds) OpenOCD should wait after deasserting
3137 nSRST (active-low system reset) before starting new JTAG operations.
3138 When a board has a reset button connected to SRST line it will
3139 probably have hardware debouncing, implying you should use this.
3140 @end deffn
3142 @deffn {Command} jtag_ntrst_assert_width milliseconds
3143 Minimum amount of time (in milliseconds) OpenOCD should wait
3144 after asserting nTRST (active-low JTAG TAP reset) before
3145 allowing it to be deasserted.
3146 @end deffn
3148 @deffn {Command} jtag_ntrst_delay milliseconds
3149 How long (in milliseconds) OpenOCD should wait after deasserting
3150 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3151 @end deffn
3153 @deffn {Command} reset_config mode_flag ...
3154 This command displays or modifies the reset configuration
3155 of your combination of JTAG board and target in target
3156 configuration scripts.
3158 Information earlier in this section describes the kind of problems
3159 the command is intended to address (@pxref{SRST and TRST Issues}).
3160 As a rule this command belongs only in board config files,
3161 describing issues like @emph{board doesn't connect TRST};
3162 or in user config files, addressing limitations derived
3163 from a particular combination of interface and board.
3164 (An unlikely example would be using a TRST-only adapter
3165 with a board that only wires up SRST.)
3167 The @var{mode_flag} options can be specified in any order, but only one
3168 of each type -- @var{signals}, @var{combination}, @var{gates},
3169 @var{trst_type}, @var{srst_type} and @var{connect_type}
3170 -- may be specified at a time.
3171 If you don't provide a new value for a given type, its previous
3172 value (perhaps the default) is unchanged.
3173 For example, this means that you don't need to say anything at all about
3174 TRST just to declare that if the JTAG adapter should want to drive SRST,
3175 it must explicitly be driven high (@option{srst_push_pull}).
3177 @itemize
3178 @item
3179 @var{signals} can specify which of the reset signals are connected.
3180 For example, If the JTAG interface provides SRST, but the board doesn't
3181 connect that signal properly, then OpenOCD can't use it.
3182 Possible values are @option{none} (the default), @option{trst_only},
3183 @option{srst_only} and @option{trst_and_srst}.
3185 @quotation Tip
3186 If your board provides SRST and/or TRST through the JTAG connector,
3187 you must declare that so those signals can be used.
3188 @end quotation
3190 @item
3191 The @var{combination} is an optional value specifying broken reset
3192 signal implementations.
3193 The default behaviour if no option given is @option{separate},
3194 indicating everything behaves normally.
3195 @option{srst_pulls_trst} states that the
3196 test logic is reset together with the reset of the system (e.g. NXP
3197 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3198 the system is reset together with the test logic (only hypothetical, I
3199 haven't seen hardware with such a bug, and can be worked around).
3200 @option{combined} implies both @option{srst_pulls_trst} and
3201 @option{trst_pulls_srst}.
3203 @item
3204 The @var{gates} tokens control flags that describe some cases where
3205 JTAG may be unvailable during reset.
3206 @option{srst_gates_jtag} (default)
3207 indicates that asserting SRST gates the
3208 JTAG clock. This means that no communication can happen on JTAG
3209 while SRST is asserted.
3210 Its converse is @option{srst_nogate}, indicating that JTAG commands
3211 can safely be issued while SRST is active.
3213 @item
3214 The @var{connect_type} tokens control flags that describe some cases where
3215 SRST is asserted while connecting to the target. @option{srst_nogate}
3216 is required to use this option.
3217 @option{connect_deassert_srst} (default)
3218 indicates that SRST will not be asserted while connecting to the target.
3219 Its converse is @option{connect_assert_srst}, indicating that SRST will
3220 be asserted before any target connection.
3221 Only some targets support this feature, STM32 and STR9 are examples.
3222 This feature is useful if you are unable to connect to your target due
3223 to incorrect options byte config or illegal program execution.
3224 @end itemize
3226 The optional @var{trst_type} and @var{srst_type} parameters allow the
3227 driver mode of each reset line to be specified. These values only affect
3228 JTAG interfaces with support for different driver modes, like the Amontec
3229 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3230 relevant signal (TRST or SRST) is not connected.
3232 @itemize
3233 @item
3234 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3235 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3236 Most boards connect this signal to a pulldown, so the JTAG TAPs
3237 never leave reset unless they are hooked up to a JTAG adapter.
3239 @item
3240 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3241 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3242 Most boards connect this signal to a pullup, and allow the
3243 signal to be pulled low by various events including system
3244 powerup and pressing a reset button.
3245 @end itemize
3246 @end deffn
3248 @section Custom Reset Handling
3249 @cindex events
3251 OpenOCD has several ways to help support the various reset
3252 mechanisms provided by chip and board vendors.
3253 The commands shown in the previous section give standard parameters.
3254 There are also @emph{event handlers} associated with TAPs or Targets.
3255 Those handlers are Tcl procedures you can provide, which are invoked
3256 at particular points in the reset sequence.
3258 @emph{When SRST is not an option} you must set
3259 up a @code{reset-assert} event handler for your target.
3260 For example, some JTAG adapters don't include the SRST signal;
3261 and some boards have multiple targets, and you won't always
3262 want to reset everything at once.
3264 After configuring those mechanisms, you might still
3265 find your board doesn't start up or reset correctly.
3266 For example, maybe it needs a slightly different sequence
3267 of SRST and/or TRST manipulations, because of quirks that
3268 the @command{reset_config} mechanism doesn't address;
3269 or asserting both might trigger a stronger reset, which
3270 needs special attention.
3272 Experiment with lower level operations, such as @command{jtag_reset}
3273 and the @command{jtag arp_*} operations shown here,
3274 to find a sequence of operations that works.
3275 @xref{JTAG Commands}.
3276 When you find a working sequence, it can be used to override
3277 @command{jtag_init}, which fires during OpenOCD startup
3278 (@pxref{Configuration Stage});
3279 or @command{init_reset}, which fires during reset processing.
3281 You might also want to provide some project-specific reset
3282 schemes. For example, on a multi-target board the standard
3283 @command{reset} command would reset all targets, but you
3284 may need the ability to reset only one target at time and
3285 thus want to avoid using the board-wide SRST signal.
3287 @deffn {Overridable Procedure} init_reset mode
3288 This is invoked near the beginning of the @command{reset} command,
3289 usually to provide as much of a cold (power-up) reset as practical.
3290 By default it is also invoked from @command{jtag_init} if
3291 the scan chain does not respond to pure JTAG operations.
3292 The @var{mode} parameter is the parameter given to the
3293 low level reset command (@option{halt},
3294 @option{init}, or @option{run}), @option{setup},
3295 or potentially some other value.
3297 The default implementation just invokes @command{jtag arp_init-reset}.
3298 Replacements will normally build on low level JTAG
3299 operations such as @command{jtag_reset}.
3300 Operations here must not address individual TAPs
3301 (or their associated targets)
3302 until the JTAG scan chain has first been verified to work.
3304 Implementations must have verified the JTAG scan chain before
3305 they return.
3306 This is done by calling @command{jtag arp_init}
3307 (or @command{jtag arp_init-reset}).
3308 @end deffn
3310 @deffn Command {jtag arp_init}
3311 This validates the scan chain using just the four
3312 standard JTAG signals (TMS, TCK, TDI, TDO).
3313 It starts by issuing a JTAG-only reset.
3314 Then it performs checks to verify that the scan chain configuration
3315 matches the TAPs it can observe.
3316 Those checks include checking IDCODE values for each active TAP,
3317 and verifying the length of their instruction registers using
3318 TAP @code{-ircapture} and @code{-irmask} values.
3319 If these tests all pass, TAP @code{setup} events are
3320 issued to all TAPs with handlers for that event.
3321 @end deffn
3323 @deffn Command {jtag arp_init-reset}
3324 This uses TRST and SRST to try resetting
3325 everything on the JTAG scan chain
3326 (and anything else connected to SRST).
3327 It then invokes the logic of @command{jtag arp_init}.
3328 @end deffn
3331 @node TAP Declaration
3332 @chapter TAP Declaration
3333 @cindex TAP declaration
3334 @cindex TAP configuration
3336 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3337 TAPs serve many roles, including:
3339 @itemize @bullet
3340 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
3341 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
3342 Others do it indirectly, making a CPU do it.
3343 @item @b{Program Download} Using the same CPU support GDB uses,
3344 you can initialize a DRAM controller, download code to DRAM, and then
3345 start running that code.
3346 @item @b{Boundary Scan} Most chips support boundary scan, which
3347 helps test for board assembly problems like solder bridges
3348 and missing connections
3349 @end itemize
3351 OpenOCD must know about the active TAPs on your board(s).
3352 Setting up the TAPs is the core task of your configuration files.
3353 Once those TAPs are set up, you can pass their names to code
3354 which sets up CPUs and exports them as GDB targets,
3355 probes flash memory, performs low-level JTAG operations, and more.
3357 @section Scan Chains
3358 @cindex scan chain
3360 TAPs are part of a hardware @dfn{scan chain},
3361 which is daisy chain of TAPs.
3362 They also need to be added to
3363 OpenOCD's software mirror of that hardware list,
3364 giving each member a name and associating other data with it.
3365 Simple scan chains, with a single TAP, are common in
3366 systems with a single microcontroller or microprocessor.
3367 More complex chips may have several TAPs internally.
3368 Very complex scan chains might have a dozen or more TAPs:
3369 several in one chip, more in the next, and connecting
3370 to other boards with their own chips and TAPs.
3372 You can display the list with the @command{scan_chain} command.
3373 (Don't confuse this with the list displayed by the @command{targets}
3374 command, presented in the next chapter.
3375 That only displays TAPs for CPUs which are configured as
3376 debugging targets.)
3377 Here's what the scan chain might look like for a chip more than one TAP:
3379 @verbatim
3380 TapName Enabled IdCode Expected IrLen IrCap IrMask
3381 -- ------------------ ------- ---------- ---------- ----- ----- ------
3382 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3383 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3384 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3385 @end verbatim
3387 OpenOCD can detect some of that information, but not all
3388 of it. @xref{Autoprobing}.
3389 Unfortunately those TAPs can't always be autoconfigured,
3390 because not all devices provide good support for that.
3391 JTAG doesn't require supporting IDCODE instructions, and
3392 chips with JTAG routers may not link TAPs into the chain
3393 until they are told to do so.
3395 The configuration mechanism currently supported by OpenOCD
3396 requires explicit configuration of all TAP devices using
3397 @command{jtag newtap} commands, as detailed later in this chapter.
3398 A command like this would declare one tap and name it @code{chip1.cpu}:
3400 @example
3401 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3402 @end example
3404 Each target configuration file lists the TAPs provided
3405 by a given chip.
3406 Board configuration files combine all the targets on a board,
3407 and so forth.
3408 Note that @emph{the order in which TAPs are declared is very important.}
3409 It must match the order in the JTAG scan chain, both inside
3410 a single chip and between them.
3411 @xref{FAQ TAP Order}.
3413 For example, the ST Microsystems STR912 chip has
3414 three separate TAPs@footnote{See the ST
3415 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3416 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3417 @url{}}.
3418 To configure those taps, @file{target/str912.cfg}
3419 includes commands something like this:
3421 @example
3422 jtag newtap str912 flash ... params ...
3423 jtag newtap str912 cpu ... params ...
3424 jtag newtap str912 bs ... params ...
3425 @end example
3427 Actual config files use a variable instead of literals like
3428 @option{str912}, to support more than one chip of each type.
3429 @xref{Config File Guidelines}.
3431 @deffn Command {jtag names}
3432 Returns the names of all current TAPs in the scan chain.
3433 Use @command{jtag cget} or @command{jtag tapisenabled}
3434 to examine attributes and state of each TAP.
3435 @example
3436 foreach t [jtag names] @{
3437 puts [format "TAP: %s\n" $t]
3438 @}
3439 @end example
3440 @end deffn
3442 @deffn Command {scan_chain}
3443 Displays the TAPs in the scan chain configuration,
3444 and their status.
3445 The set of TAPs listed by this command is fixed by
3446 exiting the OpenOCD configuration stage,
3447 but systems with a JTAG router can
3448 enable or disable TAPs dynamically.
3449 @end deffn
3451 @c FIXME! "jtag cget" should be able to return all TAP
3452 @c attributes, like "$target_name cget" does for targets.
3454 @c Probably want "jtag eventlist", and a "tap-reset" event
3455 @c (on entry to RESET state).
3457 @section TAP Names
3458 @cindex dotted name
3460 When TAP objects are declared with @command{jtag newtap},
3461 a @dfn{} is created for the TAP, combining the
3462 name of a module (usually a chip) and a label for the TAP.
3463 For example: @code{xilinx.tap}, @code{str912.flash},
3464 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3465 Many other commands use that to manipulate or
3466 refer to the TAP. For example, CPU configuration uses the
3467 name, as does declaration of NAND or NOR flash banks.
3469 The components of a dotted name should follow ``C'' symbol
3470 name rules: start with an alphabetic character, then numbers
3471 and underscores are OK; while others (including dots!) are not.
3473 @quotation Tip
3474 In older code, JTAG TAPs were numbered from 0..N.
3475 This feature is still present.
3476 However its use is highly discouraged, and
3477 should not be relied on; it will be removed by mid-2010.
3478 Update all of your scripts to use TAP names rather than numbers,
3479 by paying attention to the runtime warnings they trigger.
3480 Using TAP numbers in target configuration scripts prevents
3481 reusing those scripts on boards with multiple targets.
3482 @end quotation
3484 @section TAP Declaration Commands
3486 @c shouldn't this be(come) a {Config Command}?
3487 @anchor{jtag newtap}
3488 @deffn Command {jtag newtap} chipname tapname configparams...
3489 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3490 and configured according to the various @var{configparams}.
3492 The @var{chipname} is a symbolic name for the chip.
3493 Conventionally target config files use @code{$_CHIPNAME},
3494 defaulting to the model name given by the chip vendor but
3495 overridable.
3497 @cindex TAP naming convention
3498 The @var{tapname} reflects the role of that TAP,
3499 and should follow this convention:
3501 @itemize @bullet
3502 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3503 @item @code{cpu} -- The main CPU of the chip, alternatively
3504 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3505 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3506 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3507 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3508 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3509 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3510 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3511 with a single TAP;
3512 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3513 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3514 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3515 a JTAG TAP; that TAP should be named @code{sdma}.
3516 @end itemize
3518 Every TAP requires at least the following @var{configparams}:
3520 @itemize @bullet
3521 @item @code{-irlen} @var{NUMBER}
3522 @*The length in bits of the
3523 instruction register, such as 4 or 5 bits.
3524 @end itemize
3526 A TAP may also provide optional @var{configparams}:
3528 @itemize @bullet
3529 @item @code{-disable} (or @code{-enable})
3530 @*Use the @code{-disable} parameter to flag a TAP which is not
3531 linked in to the scan chain after a reset using either TRST
3532 or the JTAG state machine's @sc{reset} state.
3533 You may use @code{-enable} to highlight the default state
3534 (the TAP is linked in).
3535 @xref{Enabling and Disabling TAPs}.
3536 @item @code{-expected-id} @var{number}
3537 @*A non-zero @var{number} represents a 32-bit IDCODE
3538 which you expect to find when the scan chain is examined.
3539 These codes are not required by all JTAG devices.
3540 @emph{Repeat the option} as many times as required if more than one
3541 ID code could appear (for example, multiple versions).
3542 Specify @var{number} as zero to suppress warnings about IDCODE
3543 values that were found but not included in the list.
3545 Provide this value if at all possible, since it lets OpenOCD
3546 tell when the scan chain it sees isn't right. These values
3547 are provided in vendors' chip documentation, usually a technical
3548 reference manual. Sometimes you may need to probe the JTAG
3549 hardware to find these values.
3550 @xref{Autoprobing}.
3551 @item @code{-ignore-version}
3552 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3553 option. When vendors put out multiple versions of a chip, or use the same
3554 JTAG-level ID for several largely-compatible chips, it may be more practical
3555 to ignore the version field than to update config files to handle all of
3556 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3557 @item @code{-ircapture} @var{NUMBER}
3558 @*The bit pattern loaded by the TAP into the JTAG shift register
3559 on entry to the @sc{ircapture} state, such as 0x01.
3560 JTAG requires the two LSBs of this value to be 01.
3561 By default, @code{-ircapture} and @code{-irmask} are set
3562 up to verify that two-bit value. You may provide
3563 additional bits, if you know them, or indicate that
3564 a TAP doesn't conform to the JTAG specification.
3565 @item @code{-irmask} @var{NUMBER}
3566 @*A mask used with @code{-ircapture}
3567 to verify that instruction scans work correctly.
3568 Such scans are not used by OpenOCD except to verify that
3569 there seems to be no problems with JTAG scan chain operations.
3570 @end itemize
3571 @end deffn
3573 @section Other TAP commands
3575 @deffn Command {jtag cget} @option{-event} name
3576 @deffnx Command {jtag configure} @option{-event} name string
3577 At this writing this TAP attribute
3578 mechanism is used only for event handling.
3579 (It is not a direct analogue of the @code{cget}/@code{configure}
3580 mechanism for debugger targets.)
3581 See the next section for information about the available events.
3583 The @code{configure} subcommand assigns an event handler,
3584 a TCL string which is evaluated when the event is triggered.
3585 The @code{cget} subcommand returns that handler.
3586 @end deffn
3588 @anchor{TAP Events}
3589 @section TAP Events
3590 @cindex events
3591 @cindex TAP events
3593 OpenOCD includes two event mechanisms.
3594 The one presented here applies to all JTAG TAPs.
3595 The other applies to debugger targets,
3596 which are associated with certain TAPs.
3598 The TAP events currently defined are:
3600 @itemize @bullet
3601 @item @b{post-reset}
3602 @* The TAP has just completed a JTAG reset.
3603 The tap may still be in the JTAG @sc{reset} state.
3604 Handlers for these events might perform initialization sequences
3605 such as issuing TCK cycles, TMS sequences to ensure
3606 exit from the ARM SWD mode, and more.
3608 Because the scan chain has not yet been verified, handlers for these events
3609 @emph{should not issue commands which scan the JTAG IR or DR registers}
3610 of any particular target.
3611 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3612 @item @b{setup}
3613 @* The scan chain has been reset and verified.
3614 This handler may enable TAPs as needed.
3615 @item @b{tap-disable}
3616 @* The TAP needs to be disabled. This handler should
3617 implement @command{jtag tapdisable}
3618 by issuing the relevant JTAG commands.
3619 @item @b{tap-enable}
3620 @* The TAP needs to be enabled. This handler should
3621 implement @command{jtag tapenable}
3622 by issuing the relevant JTAG commands.
3623 @end itemize
3625 If you need some action after each JTAG reset, which isn't actually
3626 specific to any TAP (since you can't yet trust the scan chain's
3627 contents to be accurate), you might:
3629 @example
3630 jtag configure CHIP.jrc -event post-reset @{
3631 echo "JTAG Reset done"
3632 ... non-scan jtag operations to be done after reset
3633 @}
3634 @end example
3637 @anchor{Enabling and Disabling TAPs}
3638 @section Enabling and Disabling TAPs
3639 @cindex JTAG Route Controller
3640 @cindex jrc
3642 In some systems, a @dfn{JTAG Route Controller} (JRC)
3643 is used to enable and/or disable specific JTAG TAPs.
3644 Many ARM based chips from Texas Instruments include
3645 an ``ICEpick'' module, which is a JRC.
3646 Such chips include DaVinci and OMAP3 processors.
3648 A given TAP may not be visible until the JRC has been
3649 told to link it into the scan chain; and if the JRC
3650 has been told to unlink that TAP, it will no longer
3651 be visible.
3652 Such routers address problems that JTAG ``bypass mode''
3653 ignores, such as:
3655 @itemize
3656 @item The scan chain can only go as fast as its slowest TAP.
3657 @item Having many TAPs slows instruction scans, since all
3658 TAPs receive new instructions.
3659 @item TAPs in the scan chain must be powered up, which wastes
3660 power and prevents debugging some power management mechanisms.
3661 @end itemize
3663 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3664 as implied by the existence of JTAG routers.
3665 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3666 does include a kind of JTAG router functionality.
3668 @c (a) currently the event handlers don't seem to be able to
3669 @c fail in a way that could lead to no-change-of-state.
3671 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3672 shown below, and is implemented using TAP event handlers.
3673 So for example, when defining a TAP for a CPU connected to
3674 a JTAG router, your @file{target.cfg} file
3675 should define TAP event handlers using
3676 code that looks something like this:
3678 @example
3679 jtag configure CHIP.cpu -event tap-enable @{
3680 ... jtag operations using CHIP.jrc
3681 @}
3682 jtag configure CHIP.cpu -event tap-disable @{
3683 ... jtag operations using CHIP.jrc
3684 @}
3685 @end example
3687 Then you might want that CPU's TAP enabled almost all the time:
3689 @example
3690 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3691 @end example
3693 Note how that particular setup event handler declaration
3694 uses quotes to evaluate @code{$CHIP} when the event is configured.
3695 Using brackets @{ @} would cause it to be evaluated later,
3696 at runtime, when it might have a different value.
3698 @deffn Command {jtag tapdisable}
3699 If necessary, disables the tap
3700 by sending it a @option{tap-disable} event.
3701 Returns the string "1" if the tap
3702 specified by @var{} is enabled,
3703 and "0" if it is disabled.
3704 @end deffn
3706 @deffn Command {jtag tapenable}
3707 If necessary, enables the tap
3708 by sending it a @option{tap-enable} event.
3709 Returns the string "1" if the tap
3710 specified by @var{} is enabled,
3711 and "0" if it is disabled.
3712 @end deffn
3714 @deffn Command {jtag tapisenabled}
3715 Returns the string "1" if the tap
3716 specified by @var{} is enabled,
3717 and "0" if it is disabled.
3719 @quotation Note
3720 Humans will find the @command{scan_chain} command more helpful
3721 for querying the state of the JTAG taps.
3722 @end quotation
3723 @end deffn
3725 @anchor{Autoprobing}
3726 @section Autoprobing
3727 @cindex autoprobe
3728 @cindex JTAG autoprobe
3730 TAP configuration is the first thing that needs to be done
3731 after interface and reset configuration. Sometimes it's
3732 hard finding out what TAPs exist, or how they are identified.
3733 Vendor documentation is not always easy to find and use.
3735 To help you get past such problems, OpenOCD has a limited
3736 @emph{autoprobing} ability to look at the scan chain, doing
3737 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3738 To use this mechanism, start the OpenOCD server with only data
3739 that configures your JTAG interface, and arranges to come up
3740 with a slow clock (many devices don't support fast JTAG clocks
3741 right when they come out of reset).
3743 For example, your @file{openocd.cfg} file might have:
3745 @example
3746 source [find interface/olimex-arm-usb-tiny-h.cfg]
3747 reset_config trst_and_srst
3748 jtag_rclk 8
3749 @end example
3751 When you start the server without any TAPs configured, it will
3752 attempt to autoconfigure the TAPs. There are two parts to this:
3754 @enumerate
3755 @item @emph{TAP discovery} ...
3756 After a JTAG reset (sometimes a system reset may be needed too),
3757 each TAP's data registers will hold the contents of either the
3758 IDCODE or BYPASS register.
3759 If JTAG communication is working, OpenOCD will see each TAP,
3760 and report what @option{-expected-id} to use with it.
3761 @item @emph{IR Length discovery} ...
3762 Unfortunately JTAG does not provide a reliable way to find out
3763 the value of the @option{-irlen} parameter to use with a TAP
3764 that is discovered.
3765 If OpenOCD can discover the length of a TAP's instruction
3766 register, it will report it.
3767 Otherwise you may need to consult vendor documentation, such
3768 as chip data sheets or BSDL files.
3769 @end enumerate
3771 In many cases your board will have a simple scan chain with just
3772 a single device. Here's what OpenOCD reported with one board
3773 that's a bit more complex:
3775 @example
3776 clock speed 8 kHz
3777 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3778 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3779 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3780 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3781 AUTO auto0.tap - use "... -irlen 4"
3782 AUTO auto1.tap - use "... -irlen 4"
3783 AUTO auto2.tap - use "... -irlen 6"
3784 no gdb ports allocated as no target has been specified
3785 @end example
3787 Given that information, you should be able to either find some existing
3788 config files to use, or create your own. If you create your own, you
3789 would configure from the bottom up: first a @file{target.cfg} file
3790 with these TAPs, any targets associated with them, and any on-chip
3791 resources; then a @file{board.cfg} with off-chip resources, clocking,
3792 and so forth.
3794 @node CPU Configuration
3795 @chapter CPU Configuration
3796 @cindex GDB target
3798 This chapter discusses how to set up GDB debug targets for CPUs.
3799 You can also access these targets without GDB
3800 (@pxref{Architecture and Core Commands},
3801 and @ref{Target State handling}) and
3802 through various kinds of NAND and NOR flash commands.
3803 If you have multiple CPUs you can have multiple such targets.
3805 We'll start by looking at how to examine the targets you have,
3806 then look at how to add one more target and how to configure it.
3808 @section Target List
3809 @cindex target, current
3810 @cindex target, list
3812 All targets that have been set up are part of a list,
3813 where each member has a name.
3814 That name should normally be the same as the TAP name.
3815 You can display the list with the @command{targets}
3816 (plural!) command.
3817 This display often has only one CPU; here's what it might
3818 look like with more than one:
3819 @verbatim
3820 TargetName Type Endian TapName State
3821 -- ------------------ ---------- ------ ------------------ ------------
3822 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
3823 1 MyTarget cortex_m3 little tap-disabled
3824 @end verbatim
3826 One member of that list is the @dfn{current target}, which
3827 is implicitly referenced by many commands.
3828 It's the one marked with a @code{*} near the target name.
3829 In particular, memory addresses often refer to the address
3830 space seen by that current target.
3831 Commands like @command{mdw} (memory display words)
3832 and @command{flash erase_address} (erase NOR flash blocks)
3833 are examples; and there are many more.
3835 Several commands let you examine the list of targets:
3837 @deffn Command {target count}
3838 @emph{Note: target numbers are deprecated; don't use them.
3839 They will be removed shortly after August 2010, including this command.
3840 Iterate target using @command{target names}, not by counting.}
3842 Returns the number of targets, @math{N}.
3843 The highest numbered target is @math{N - 1}.
3844 @example
3845 set c [target count]
3846 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
3847 # Assuming you have created this function
3848 print_target_details $x
3849 @}
3850 @end example
3851 @end deffn
3853 @deffn Command {target current}
3854 Returns the name of the current target.
3855 @end deffn
3857 @deffn Command {target names}
3858 Lists the names of all current targets in the list.
3859 @example
3860 foreach t [target names] @{
3861 puts [format "Target: %s\n" $t]
3862 @}
3863 @end example
3864 @end deffn
3866 @deffn Command {target number} number
3867 @emph{Note: target numbers are deprecated; don't use them.
3868 They will be removed shortly after August 2010, including this command.}
3870 The list of targets is numbered starting at zero.
3871 This command returns the name of the target at index @var{number}.
3872 @example
3873 set thename [target number $x]
3874 puts [format "Target %d is: %s\n" $x $thename]
3875 @end example
3876 @end deffn
3878 @c yep, "target list" would have been better.
3879 @c plus maybe "target setdefault".
3881 @deffn Command targets [name]
3882 @emph{Note: the name of this command is plural. Other target
3883 command names are singular.}
3885 With no parameter, this command displays a table of all known
3886 targets in a user friendly form.
3888 With a parameter, this command sets the current target to
3889 the given target with the given @var{name}; this is
3890 only relevant on boards which have more than one target.
3891 @end deffn
3893 @section Target CPU Types and Variants
3894 @cindex target type
3895 @cindex CPU type
3896 @cindex CPU variant
3898 Each target has a @dfn{CPU type}, as shown in the output of
3899 the @command{targets} command. You need to specify that type
3900 when calling @command{target create}.
3901 The CPU type indicates more than just the instruction set.
3902 It also indicates how that instruction set is implemented,
3903 what kind of debug support it integrates,
3904 whether it has an MMU (and if so, what kind),
3905 what core-specific commands may be available
3906 (@pxref{Architecture and Core Commands}),
3907 and more.
3909 For some CPU types, OpenOCD also defines @dfn{variants} which
3910 indicate differences that affect their handling.
3911 For example, a particular implementation bug might need to be
3912 worked around in some chip versions.
3914 It's easy to see what target types are supported,
3915 since there's a command to list them.
3916 However, there is currently no way to list what target variants
3917 are supported (other than by reading the OpenOCD source code).
3919 @anchor{target types}
3920 @deffn Command {target types}
3921 Lists all supported target types.
3922 At this writing, the supported CPU types and variants are:
3924 @itemize @bullet
3925 @item @code{arm11} -- this is a generation of ARMv6 cores
3926 @item @code{arm720t} -- this is an ARMv4 core with an MMU
3927 @item @code{arm7tdmi} -- this is an ARMv4 core
3928 @item @code{arm920t} -- this is an ARMv4 core with an MMU
3929 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
3930 @item @code{arm966e} -- this is an ARMv5 core
3931 @item @code{arm9tdmi} -- this is an ARMv4 core
3932 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
3933 (Support for this is preliminary and incomplete.)
3934 @item @code{cortex_a8} -- this is an ARMv7 core with an MMU
3935 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
3936 compact Thumb2 instruction set.
3937 @item @code{dragonite} -- resembles arm966e
3938 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
3939 (Support for this is still incomplete.)
3940 @item @code{fa526} -- resembles arm920 (w/o Thumb)
3941 @item @code{feroceon} -- resembles arm926
3942 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
3943 @item @code{xscale} -- this is actually an architecture,
3944 not a CPU type. It is based on the ARMv5 architecture.
3945 There are several variants defined:
3946 @itemize @minus
3947 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
3948 @code{pxa27x} ... instruction register length is 7 bits
3949 @item @code{pxa250}, @code{pxa255},
3950 @code{pxa26x} ... instruction register length is 5 bits
3951 @item @code{pxa3xx} ... instruction register length is 11 bits
3952 @end itemize
3953 @end itemize
3954 @end deffn
3956 To avoid being confused by the variety of ARM based cores, remember
3957 this key point: @emph{ARM is a technology licencing company}.
3958 (See: @url{}.)
3959 The CPU name used by OpenOCD will reflect the CPU design that was
3960 licenced, not a vendor brand which incorporates that design.
3961 Name prefixes like arm7, arm9, arm11, and cortex
3962 reflect design generations;
3963 while names like ARMv4, ARMv5, ARMv6, and ARMv7
3964 reflect an architecture version implemented by a CPU design.
3966 @anchor{Target Configuration}
3967 @section Target Configuration
3969 Before creating a ``target'', you must have added its TAP to the scan chain.
3970 When you've added that TAP, you will have a @code{}
3971 which is used to set up the CPU support.
3972 The chip-specific configuration file will normally configure its CPU(s)
3973 right after it adds all of the chip's TAPs to the scan chain.
3975 Although you can set up a target in one step, it's often clearer if you
3976 use shorter commands and do it in two steps: create it, then configure
3977 optional parts.
3978 All operations on the target after it's created will use a new
3979 command, created as part of target creation.
3981 The two main things to configure after target creation are
3982 a work area, which usually has target-specific defaults even
3983 if the board setup code overrides them later;
3984 and event handlers (@pxref{Target Events}), which tend
3985 to be much more board-specific.
3986 The key steps you use might look something like this
3988 @example
3989 target create MyTarget cortex_m3 -chain-position mychip.cpu
3990 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
3991 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
3992 $MyTarget configure -event reset-init @{ myboard_reinit @}
3993 @end example
3995 You should specify a working area if you can; typically it uses some
3996 on-chip SRAM.
3997 Such a working area can speed up many things, including bulk
3998 writes to target memory;
3999 flash operations like checking to see if memory needs to be erased;
4000 GDB memory checksumming;
4001 and more.
4003 @quotation Warning
4004 On more complex chips, the work area can become
4005 inaccessible when application code
4006 (such as an operating system)
4007 enables or disables the MMU.
4008 For example, the particular MMU context used to acess the virtual
4009 address will probably matter ... and that context might not have
4010 easy access to other addresses needed.
4011 At this writing, OpenOCD doesn't have much MMU intelligence.
4012 @end quotation
4014 It's often very useful to define a @code{reset-init} event handler.
4015 For systems that are normally used with a boot loader,
4016 common tasks include updating clocks and initializing memory
4017 controllers.
4018 That may be needed to let you write the boot loader into flash,
4019 in order to ``de-brick'' your board; or to load programs into
4020 external DDR memory without having run the boot loader.
4022 @deffn Command {target create} target_name type configparams...
4023 This command creates a GDB debug target that refers to a specific JTAG tap.
4024 It enters that target into a list, and creates a new
4025 command (@command{@var{target_name}}) which is used for various
4026 purposes including additional configuration.
4028 @itemize @bullet
4029 @item @var{target_name} ... is the name of the debug target.
4030 By convention this should be the same as the @emph{}
4031 of the TAP associated with this target, which must be specified here
4032 using the @code{-chain-position @var{}} configparam.
4034 This name is also used to create the target object command,
4035 referred to here as @command{$target_name},
4036 and in other places the target needs to be identified.
4037 @item @var{type} ... specifies the target type. @xref{target types}.
4038 @item @var{configparams} ... all parameters accepted by
4039 @command{$target_name configure} are permitted.
4040 If the target is big-endian, set it here with @code{-endian big}.
4041 If the variant matters, set it here with @code{-variant}.
4043 You @emph{must} set the @code{-chain-position @var{}} here.
4044 @end itemize
4045 @end deffn
4047 @deffn Command {$target_name configure} configparams...
4048 The options accepted by this command may also be
4049 specified as parameters to @command{target create}.
4050 Their values can later be queried one at a time by
4051 using the @command{$target_name cget} command.
4053 @emph{Warning:} changing some of these after setup is dangerous.
4054 For example, moving a target from one TAP to another;
4055 and changing its endianness or variant.
4057 @itemize @bullet
4059 @item @code{-chain-position} @var{} -- names the TAP
4060 used to access this target.
4062 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4063 whether the CPU uses big or little endian conventions
4065 @item @code{-event} @var{event_name} @var{event_body} --
4066 @xref{Target Events}.
4067 Note that this updates a list of named event handlers.
4068 Calling this twice with two different event names assigns
4069 two different handlers, but calling it twice with the
4070 same event name assigns only one handler.
4072 @item @code{-variant} @var{name} -- specifies a variant of the target,
4073 which OpenOCD needs to know about.
4075 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4076 whether the work area gets backed up; by default,
4077 @emph{it is not backed up.}
4078 When possible, use a working_area that doesn't need to be backed up,
4079 since performing a backup slows down operations.
4080 For example, the beginning of an SRAM block is likely to
4081 be used by most build systems, but the end is often unused.
4083 @item @code{-work-area-size} @var{size} -- specify work are size,
4084 in bytes. The same size applies regardless of whether its physical
4085 or virtual address is being used.
4087 @item @code{-work-area-phys} @var{address} -- set the work area
4088 base @var{address} to be used when no MMU is active.
4090 @item @code{-work-area-virt} @var{address} -- set the work area
4091 base @var{address} to be used when an MMU is active.
4092 @emph{Do not specify a value for this except on targets with an MMU.}
4093 The value should normally correspond to a static mapping for the
4094 @code{-work-area-phys} address, set up by the current operating system.
4096 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4097 @var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}|
4098 @option{FreeRTOS}|@option{linux}|@option{ChibiOS}.
4100 @end itemize
4101 @end deffn
4103 @section Other $target_name Commands
4104 @cindex object command
4106 The Tcl/Tk language has the concept of object commands,
4107 and OpenOCD adopts that same model for targets.
4109 A good Tk example is a on screen button.
4110 Once a button is created a button
4111 has a name (a path in Tk terms) and that name is useable as a first
4112 class command. For example in Tk, one can create a button and later
4113 configure it like this:
4115 @example
4116 # Create
4117 button .foobar -background red -command @{ foo @}
4118 # Modify
4119 .foobar configure -foreground blue
4120 # Query
4121 set x [.foobar cget -background]
4122 # Report
4123 puts [format "The button is %s" $x]
4124 @end example
4126 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4127 button, and its object commands are invoked the same way.
4129 @example
4130 str912.cpu mww 0x1234 0x42
4131 omap3530.cpu mww 0x5555 123
4132 @end example
4134 The commands supported by OpenOCD target objects are:
4136 @deffn Command {$target_name arp_examine}
4137 @deffnx Command {$target_name arp_halt}
4138 @deffnx Command {$target_name arp_poll}
4139 @deffnx Command {$target_name arp_reset}
4140 @deffnx Command {$target_name arp_waitstate}
4141 Internal OpenOCD scripts (most notably @file{startup.tcl})
4142 use these to deal with specific reset cases.
4143 They are not otherwise documented here.
4144 @end deffn
4146 @deffn Command {$target_name array2mem} arrayname width address count
4147 @deffnx Command {$target_name mem2array} arrayname width address count
4148 These provide an efficient script-oriented interface to memory.
4149 The @code{array2mem} primitive writes bytes, halfwords, or words;
4150 while @code{mem2array} reads them.
4151 In both cases, the TCL side uses an array, and
4152 the target side uses raw memory.
4154 The efficiency comes from enabling the use of
4155 bulk JTAG data transfer operations.
4156 The script orientation comes from working with data
4157 values that are packaged for use by TCL scripts;
4158 @command{mdw} type primitives only print data they retrieve,
4159 and neither store nor return those values.
4161 @itemize
4162 @item @var{arrayname} ... is the name of an array variable
4163 @item @var{width} ... is 8/16/32 - indicating the memory access size
4164 @item @var{address} ... is the target memory address
4165 @item @var{count} ... is the number of elements to process
4166 @end itemize
4167 @end deffn
4169 @deffn Command {$target_name cget} queryparm
4170 Each configuration parameter accepted by
4171 @command{$target_name configure}
4172 can be individually queried, to return its current value.
4173 The @var{queryparm} is a parameter name
4174 accepted by that command, such as @code{-work-area-phys}.
4175 There are a few special cases:
4177 @itemize @bullet
4178 @item @code{-event} @var{event_name} -- returns the handler for the
4179 event named @var{event_name}.
4180 This is a special case because setting a handler requires