jtag: add connect_type reset_config mode flag
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * TFTP:: TFTP
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
94 @end menu
96 @node About
97 @unnumbered About
98 @cindex about
100 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
101 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
104 around the world.
106 @section What is OpenOCD?
107 @cindex TAP
108 @cindex JTAG
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
112 devices.
114 It does so with the assistance of a @dfn{debug adapter}, which is
115 a small hardware module which helps provide the right kind of
116 electrical signaling to the target being debugged. These are
117 required since the debug host (on which OpenOCD runs) won't
118 usually have native support for such signaling, or the connector
119 needed to hook up to the target.
121 Such debug adapters support one or more @dfn{transport} protocols,
122 each of which involves different electrical signaling (and uses
123 different messaging protocols on top of that signaling). There
124 are many types of debug adapter, and little uniformity in what
125 they are called. (There are also product naming differences.)
127 These adapters are sometimes packaged as discrete dongles, which
128 may generically be called @dfn{hardware interface dongles}.
129 Some development boards also integrate them directly, which may
130 let the development board can be directly connected to the debug
131 host over USB (and sometimes also to power it over USB).
133 For example, a @dfn{JTAG Adapter} supports JTAG
134 signaling, and is used to communicate
135 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
136 A @dfn{TAP} is a ``Test Access Port'', a module which processes
137 special instructions and data. TAPs are daisy-chained within and
138 between chips and boards. JTAG supports debugging and boundary
139 scan operations.
141 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
142 signaling to communicate with some newer ARM cores, as well as debug
143 adapters which support both JTAG and SWD transports. SWD only supports
144 debugging, whereas JTAG also supports boundary scan operations.
146 For some chips, there are also @dfn{Programming Adapters} supporting
147 special transports used only to write code to flash memory, without
148 support for on-chip debugging or boundary scan.
149 (At this writing, OpenOCD does not support such non-debug adapters.)
152 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
153 based, parallel port based, and other standalone boxes that run
154 OpenOCD internally. @xref{Debug Adapter Hardware}.
156 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
157 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
158 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
159 debugged via the GDB protocol.
161 @b{Flash Programing:} Flash writing is supported for external CFI
162 compatible NOR flashes (Intel and AMD/Spansion command set) and several
163 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
164 STM32x). Preliminary support for various NAND flash controllers
165 (LPC3180, Orion, S3C24xx, more) controller is included.
167 @section OpenOCD Web Site
169 The OpenOCD web site provides the latest public news from the community:
171 @uref{http://openocd.sourceforge.net/}
173 @section Latest User's Guide:
175 The user's guide you are now reading may not be the latest one
176 available. A version for more recent code may be available.
177 Its HTML form is published regularly at:
179 @uref{http://openocd.sourceforge.net/doc/html/index.html}
181 PDF form is likewise published at:
183 @uref{http://openocd.sourceforge.net/doc/pdf/openocd.pdf}
185 @section OpenOCD User's Forum
187 There is an OpenOCD forum (phpBB) hosted by SparkFun,
188 which might be helpful to you. Note that if you want
189 anything to come to the attention of developers, you
190 should post it to the OpenOCD Developer Mailing List
191 instead of this forum.
193 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
195 @section OpenOCD User's Mailing List
197 The OpenOCD User Mailing List provides the primary means of
198 communication between users:
200 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
202 @section OpenOCD IRC
204 Support can also be found on irc:
205 @uref{irc://irc.freenode.net/openocd}
207 @node Developers
208 @chapter OpenOCD Developer Resources
209 @cindex developers
211 If you are interested in improving the state of OpenOCD's debugging and
212 testing support, new contributions will be welcome. Motivated developers
213 can produce new target, flash or interface drivers, improve the
214 documentation, as well as more conventional bug fixes and enhancements.
216 The resources in this chapter are available for developers wishing to explore
217 or expand the OpenOCD source code.
219 @section OpenOCD GIT Repository
221 During the 0.3.x release cycle, OpenOCD switched from Subversion to
222 a GIT repository hosted at SourceForge. The repository URL is:
224 @uref{git://openocd.git.sourceforge.net/gitroot/openocd/openocd}
226 You may prefer to use a mirror and the HTTP protocol:
228 @uref{http://repo.or.cz/r/openocd.git}
230 With standard GIT tools, use @command{git clone} to initialize
231 a local repository, and @command{git pull} to update it.
232 There are also gitweb pages letting you browse the repository
233 with a web browser, or download arbitrary snapshots without
234 needing a GIT client:
236 @uref{http://openocd.git.sourceforge.net/git/gitweb.cgi?p=openocd/openocd}
238 @uref{http://repo.or.cz/w/openocd.git}
240 The @file{README} file contains the instructions for building the project
241 from the repository or a snapshot.
243 Developers that want to contribute patches to the OpenOCD system are
244 @b{strongly} encouraged to work against mainline.
245 Patches created against older versions may require additional
246 work from their submitter in order to be updated for newer releases.
248 @section Doxygen Developer Manual
250 During the 0.2.x release cycle, the OpenOCD project began
251 providing a Doxygen reference manual. This document contains more
252 technical information about the software internals, development
253 processes, and similar documentation:
255 @uref{http://openocd.sourceforge.net/doc/doxygen/html/index.html}
257 This document is a work-in-progress, but contributions would be welcome
258 to fill in the gaps. All of the source files are provided in-tree,
259 listed in the Doxyfile configuration in the top of the source tree.
261 @section OpenOCD Developer Mailing List
263 The OpenOCD Developer Mailing List provides the primary means of
264 communication between developers:
266 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
268 Discuss and submit patches to this list.
269 The @file{HACKING} file contains basic information about how
270 to prepare patches.
272 @section OpenOCD Bug Database
274 During the 0.4.x release cycle the OpenOCD project team began
275 using Trac for its bug database:
277 @uref{https://sourceforge.net/apps/trac/openocd}
280 @node Debug Adapter Hardware
281 @chapter Debug Adapter Hardware
282 @cindex dongles
283 @cindex FTDI
284 @cindex wiggler
285 @cindex zy1000
286 @cindex printer port
287 @cindex USB Adapter
288 @cindex RTCK
290 Defined: @b{dongle}: A small device that plugins into a computer and serves as
291 an adapter .... [snip]
293 In the OpenOCD case, this generally refers to @b{a small adapter} that
294 attaches to your computer via USB or the Parallel Printer Port. One
295 exception is the Zylin ZY1000, packaged as a small box you attach via
296 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
297 require any drivers to be installed on the developer PC. It also has
298 a built in web interface. It supports RTCK/RCLK or adaptive clocking
299 and has a built in relay to power cycle targets remotely.
302 @section Choosing a Dongle
304 There are several things you should keep in mind when choosing a dongle.
306 @enumerate
307 @item @b{Transport} Does it support the kind of communication that you need?
308 OpenOCD focusses mostly on JTAG. Your version may also support
309 other ways to communicate with target devices.
310 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
311 Does your dongle support it? You might need a level converter.
312 @item @b{Pinout} What pinout does your target board use?
313 Does your dongle support it? You may be able to use jumper
314 wires, or an "octopus" connector, to convert pinouts.
315 @item @b{Connection} Does your computer have the USB, printer, or
316 Ethernet port needed?
317 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
318 RTCK support? Also known as ``adaptive clocking''
319 @end enumerate
321 @section Stand alone Systems
323 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/33-zylin-zy1000-jtag-probe} Technically, not a
324 dongle, but a standalone box. The ZY1000 has the advantage that it does
325 not require any drivers installed on the developer PC. It also has
326 a built in web interface. It supports RTCK/RCLK or adaptive clocking
327 and has a built in relay to power cycle targets remotely.
329 @section USB FT2232 Based
331 There are many USB JTAG dongles on the market, many of them are based
332 on a chip from ``Future Technology Devices International'' (FTDI)
333 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
334 See: @url{http://www.ftdichip.com} for more information.
335 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
336 chips are starting to become available in JTAG adapters. (Adapters
337 using those high speed FT2232H chips may support adaptive clocking.)
339 The FT2232 chips are flexible enough to support some other
340 transport options, such as SWD or the SPI variants used to
341 program some chips. They have two communications channels,
342 and one can be used for a UART adapter at the same time the
343 other one is used to provide a debug adapter.
345 Also, some development boards integrate an FT2232 chip to serve as
346 a built-in low cost debug adapter and usb-to-serial solution.
348 @itemize @bullet
349 @item @b{usbjtag}
350 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
351 @item @b{jtagkey}
352 @* See: @url{http://www.amontec.com/jtagkey.shtml}
353 @item @b{jtagkey2}
354 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
355 @item @b{oocdlink}
356 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
357 @item @b{signalyzer}
358 @* See: @url{http://www.signalyzer.com}
359 @item @b{Stellaris Eval Boards}
360 @* See: @url{http://www.luminarymicro.com} - The Stellaris eval boards
361 bundle FT2232-based JTAG and SWD support, which can be used to debug
362 the Stellaris chips. Using separate JTAG adapters is optional.
363 These boards can also be used in a "pass through" mode as JTAG adapters
364 to other target boards, disabling the Stellaris chip.
365 @item @b{Luminary ICDI}
366 @* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug
367 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
368 Evaluation Kits. Like the non-detachable FT2232 support on the other
369 Stellaris eval boards, they can be used to debug other target boards.
370 @item @b{olimex-jtag}
371 @* See: @url{http://www.olimex.com}
372 @item @b{Flyswatter/Flyswatter2}
373 @* See: @url{http://www.tincantools.com}
374 @item @b{turtelizer2}
375 @* See:
376 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
377 @url{http://www.ethernut.de}
378 @item @b{comstick}
379 @* Link: @url{http://www.hitex.com/index.php?id=383}
380 @item @b{stm32stick}
381 @* Link @url{http://www.hitex.com/stm32-stick}
382 @item @b{axm0432_jtag}
383 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
384 to be available anymore as of April 2012.
385 @item @b{cortino}
386 @* Link @url{http://www.hitex.com/index.php?id=cortino}
387 @item @b{dlp-usb1232h}
388 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
389 @item @b{digilent-hs1}
390 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
391 @end itemize
393 @section USB-JTAG / Altera USB-Blaster compatibles
395 These devices also show up as FTDI devices, but are not
396 protocol-compatible with the FT2232 devices. They are, however,
397 protocol-compatible among themselves. USB-JTAG devices typically consist
398 of a FT245 followed by a CPLD that understands a particular protocol,
399 or emulate this protocol using some other hardware.
401 They may appear under different USB VID/PID depending on the particular
402 product. The driver can be configured to search for any VID/PID pair
403 (see the section on driver commands).
405 @itemize
406 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
407 @* Link: @url{http://ixo-jtag.sourceforge.net/}
408 @item @b{Altera USB-Blaster}
409 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
410 @end itemize
412 @section USB JLINK based
413 There are several OEM versions of the Segger @b{JLINK} adapter. It is
414 an example of a micro controller based JTAG adapter, it uses an
415 AT91SAM764 internally.
417 @itemize @bullet
418 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
419 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
420 @item @b{SEGGER JLINK}
421 @* Link: @url{http://www.segger.com/jlink.html}
422 @item @b{IAR J-Link}
423 @* Link: @url{http://www.iar.com/en/products/hardware-debug-probes/iar-j-link/}
424 @end itemize
426 @section USB RLINK based
427 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
429 @itemize @bullet
430 @item @b{Raisonance RLink}
431 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
432 @item @b{STM32 Primer}
433 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
434 @item @b{STM32 Primer2}
435 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
436 @end itemize
438 @section USB ST-LINK based
439 ST Micro has an adapter called @b{ST-LINK}.
440 They only work with ST Micro chips, notably STM32 and STM8.
442 @itemize @bullet
443 @item @b{ST-LINK}
444 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
445 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
446 @item @b{ST-LINK/V2}
447 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
448 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
449 @end itemize
451 For info the original ST-LINK enumerates using the mass storage usb class, however
452 it's implementation is completely broken. The result is this causes issues under linux.
453 The simplest solution is to get linux to ignore the ST-LINK using one of the following methods:
454 @itemize @bullet
455 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
456 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
457 @end itemize
459 @section USB Other
460 @itemize @bullet
461 @item @b{USBprog}
462 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
464 @item @b{USB - Presto}
465 @* Link: @url{http://tools.asix.net/prg_presto.htm}
467 @item @b{Versaloon-Link}
468 @* Link: @url{http://www.versaloon.com}
470 @item @b{ARM-JTAG-EW}
471 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
473 @item @b{Buspirate}
474 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
476 @item @b{opendous}
477 @* Link: @url{http://code.google.com/p/opendous-jtag/}
479 @item @b{estick}
480 @* Link: @url{http://code.google.com/p/estick-jtag/}
482 @item @b{Keil ULINK v1}
483 @* Link: @url{http://www.keil.com/ulink1/}
484 @end itemize
486 @section IBM PC Parallel Printer Port Based
488 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
489 and the Macraigor Wiggler. There are many clones and variations of
490 these on the market.
492 Note that parallel ports are becoming much less common, so if you
493 have the choice you should probably avoid these adapters in favor
494 of USB-based ones.
496 @itemize @bullet
498 @item @b{Wiggler} - There are many clones of this.
499 @* Link: @url{http://www.macraigor.com/wiggler.htm}
501 @item @b{DLC5} - From XILINX - There are many clones of this
502 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
503 produced, PDF schematics are easily found and it is easy to make.
505 @item @b{Amontec - JTAG Accelerator}
506 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
508 @item @b{GW16402}
509 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
511 @item @b{Wiggler2}
512 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
514 @item @b{Wiggler_ntrst_inverted}
515 @* Yet another variation - See the source code, src/jtag/parport.c
517 @item @b{old_amt_wiggler}
518 @* Unknown - probably not on the market today
520 @item @b{arm-jtag}
521 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
523 @item @b{chameleon}
524 @* Link: @url{http://www.amontec.com/chameleon.shtml}
526 @item @b{Triton}
527 @* Unknown.
529 @item @b{Lattice}
530 @* ispDownload from Lattice Semiconductor
531 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
533 @item @b{flashlink}
534 @* From ST Microsystems;
535 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
537 @end itemize
539 @section Other...
540 @itemize @bullet
542 @item @b{ep93xx}
543 @* An EP93xx based Linux machine using the GPIO pins directly.
545 @item @b{at91rm9200}
546 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
548 @end itemize
550 @node About Jim-Tcl
551 @chapter About Jim-Tcl
552 @cindex Jim-Tcl
553 @cindex tcl
555 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
556 This programming language provides a simple and extensible
557 command interpreter.
559 All commands presented in this Guide are extensions to Jim-Tcl.
560 You can use them as simple commands, without needing to learn
561 much of anything about Tcl.
562 Alternatively, can write Tcl programs with them.
564 You can learn more about Jim at its website, @url{http://jim.berlios.de}.
565 There is an active and responsive community, get on the mailing list
566 if you have any questions. Jim-Tcl maintainers also lurk on the
567 OpenOCD mailing list.
569 @itemize @bullet
570 @item @b{Jim vs. Tcl}
571 @* Jim-Tcl is a stripped down version of the well known Tcl language,
572 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
573 fewer features. Jim-Tcl is several dozens of .C files and .H files and
574 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
575 4.2 MB .zip file containing 1540 files.
577 @item @b{Missing Features}
578 @* Our practice has been: Add/clone the real Tcl feature if/when
579 needed. We welcome Jim-Tcl improvements, not bloat. Also there
580 are a large number of optional Jim-Tcl features that are not
581 enabled in OpenOCD.
583 @item @b{Scripts}
584 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
585 command interpreter today is a mixture of (newer)
586 Jim-Tcl commands, and (older) the orginal command interpreter.
588 @item @b{Commands}
589 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
590 can type a Tcl for() loop, set variables, etc.
591 Some of the commands documented in this guide are implemented
592 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
594 @item @b{Historical Note}
595 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
596 before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
597 as a git submodule, which greatly simplified upgrading Jim Tcl
598 to benefit from new features and bugfixes in Jim Tcl.
600 @item @b{Need a crash course in Tcl?}
601 @*@xref{Tcl Crash Course}.
602 @end itemize
604 @node Running
605 @chapter Running
606 @cindex command line options
607 @cindex logfile
608 @cindex directory search
610 Properly installing OpenOCD sets up your operating system to grant it access
611 to the debug adapters. On Linux, this usually involves installing a file
612 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
613 complex and confusing driver configuration for every peripheral. Such issues
614 are unique to each operating system, and are not detailed in this User's Guide.
616 Then later you will invoke the OpenOCD server, with various options to
617 tell it how each debug session should work.
618 The @option{--help} option shows:
619 @verbatim
620 bash$ openocd --help
622 --help | -h display this help
623 --version | -v display OpenOCD version
624 --file | -f use configuration file <name>
625 --search | -s dir to search for config files and scripts
626 --debug | -d set debug level <0-3>
627 --log_output | -l redirect log output to file <name>
628 --command | -c run <command>
629 @end verbatim
631 If you don't give any @option{-f} or @option{-c} options,
632 OpenOCD tries to read the configuration file @file{openocd.cfg}.
633 To specify one or more different
634 configuration files, use @option{-f} options. For example:
636 @example
637 openocd -f config1.cfg -f config2.cfg -f config3.cfg
638 @end example
640 Configuration files and scripts are searched for in
641 @enumerate
642 @item the current directory,
643 @item any search dir specified on the command line using the @option{-s} option,
644 @item any search dir specified using the @command{add_script_search_dir} command,
645 @item @file{$HOME/.openocd} (not on Windows),
646 @item the site wide script library @file{$pkgdatadir/site} and
647 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
648 @end enumerate
649 The first found file with a matching file name will be used.
651 @quotation Note
652 Don't try to use configuration script names or paths which
653 include the "#" character. That character begins Tcl comments.
654 @end quotation
656 @section Simple setup, no customization
658 In the best case, you can use two scripts from one of the script
659 libraries, hook up your JTAG adapter, and start the server ... and
660 your JTAG setup will just work "out of the box". Always try to
661 start by reusing those scripts, but assume you'll need more
662 customization even if this works. @xref{OpenOCD Project Setup}.
664 If you find a script for your JTAG adapter, and for your board or
665 target, you may be able to hook up your JTAG adapter then start
666 the server like:
668 @example
669 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
670 @end example
672 You might also need to configure which reset signals are present,
673 using @option{-c 'reset_config trst_and_srst'} or something similar.
674 If all goes well you'll see output something like
676 @example
677 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
678 For bug reports, read
679 http://openocd.sourceforge.net/doc/doxygen/bugs.html
680 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
681 (mfg: 0x23b, part: 0xba00, ver: 0x3)
682 @end example
684 Seeing that "tap/device found" message, and no warnings, means
685 the JTAG communication is working. That's a key milestone, but
686 you'll probably need more project-specific setup.
688 @section What OpenOCD does as it starts
690 OpenOCD starts by processing the configuration commands provided
691 on the command line or, if there were no @option{-c command} or
692 @option{-f file.cfg} options given, in @file{openocd.cfg}.
693 @xref{Configuration Stage}.
694 At the end of the configuration stage it verifies the JTAG scan
695 chain defined using those commands; your configuration should
696 ensure that this always succeeds.
697 Normally, OpenOCD then starts running as a daemon.
698 Alternatively, commands may be used to terminate the configuration
699 stage early, perform work (such as updating some flash memory),
700 and then shut down without acting as a daemon.
702 Once OpenOCD starts running as a daemon, it waits for connections from
703 clients (Telnet, GDB, Other) and processes the commands issued through
704 those channels.
706 If you are having problems, you can enable internal debug messages via
707 the @option{-d} option.
709 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
710 @option{-c} command line switch.
712 To enable debug output (when reporting problems or working on OpenOCD
713 itself), use the @option{-d} command line switch. This sets the
714 @option{debug_level} to "3", outputting the most information,
715 including debug messages. The default setting is "2", outputting only
716 informational messages, warnings and errors. You can also change this
717 setting from within a telnet or gdb session using @command{debug_level
718 <n>} (@pxref{debug_level}).
720 You can redirect all output from the daemon to a file using the
721 @option{-l <logfile>} switch.
723 Note! OpenOCD will launch the GDB & telnet server even if it can not
724 establish a connection with the target. In general, it is possible for
725 the JTAG controller to be unresponsive until the target is set up
726 correctly via e.g. GDB monitor commands in a GDB init script.
728 @node OpenOCD Project Setup
729 @chapter OpenOCD Project Setup
731 To use OpenOCD with your development projects, you need to do more than
732 just connecting the JTAG adapter hardware (dongle) to your development board
733 and then starting the OpenOCD server.
734 You also need to configure that server so that it knows
735 about that adapter and board, and helps your work.
736 You may also want to connect OpenOCD to GDB, possibly
737 using Eclipse or some other GUI.
739 @section Hooking up the JTAG Adapter
741 Today's most common case is a dongle with a JTAG cable on one side
742 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
743 and a USB cable on the other.
744 Instead of USB, some cables use Ethernet;
745 older ones may use a PC parallel port, or even a serial port.
747 @enumerate
748 @item @emph{Start with power to your target board turned off},
749 and nothing connected to your JTAG adapter.
750 If you're particularly paranoid, unplug power to the board.
751 It's important to have the ground signal properly set up,
752 unless you are using a JTAG adapter which provides
753 galvanic isolation between the target board and the
754 debugging host.
756 @item @emph{Be sure it's the right kind of JTAG connector.}
757 If your dongle has a 20-pin ARM connector, you need some kind
758 of adapter (or octopus, see below) to hook it up to
759 boards using 14-pin or 10-pin connectors ... or to 20-pin
760 connectors which don't use ARM's pinout.
762 In the same vein, make sure the voltage levels are compatible.
763 Not all JTAG adapters have the level shifters needed to work
764 with 1.2 Volt boards.
766 @item @emph{Be certain the cable is properly oriented} or you might
767 damage your board. In most cases there are only two possible
768 ways to connect the cable.
769 Connect the JTAG cable from your adapter to the board.
770 Be sure it's firmly connected.
772 In the best case, the connector is keyed to physically
773 prevent you from inserting it wrong.
774 This is most often done using a slot on the board's male connector
775 housing, which must match a key on the JTAG cable's female connector.
776 If there's no housing, then you must look carefully and
777 make sure pin 1 on the cable hooks up to pin 1 on the board.
778 Ribbon cables are frequently all grey except for a wire on one
779 edge, which is red. The red wire is pin 1.
781 Sometimes dongles provide cables where one end is an ``octopus'' of
782 color coded single-wire connectors, instead of a connector block.
783 These are great when converting from one JTAG pinout to another,
784 but are tedious to set up.
785 Use these with connector pinout diagrams to help you match up the
786 adapter signals to the right board pins.
788 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
789 A USB, parallel, or serial port connector will go to the host which
790 you are using to run OpenOCD.
791 For Ethernet, consult the documentation and your network administrator.
793 For USB based JTAG adapters you have an easy sanity check at this point:
794 does the host operating system see the JTAG adapter? If that host is an
795 MS-Windows host, you'll need to install a driver before OpenOCD works.
797 @item @emph{Connect the adapter's power supply, if needed.}
798 This step is primarily for non-USB adapters,
799 but sometimes USB adapters need extra power.
801 @item @emph{Power up the target board.}
802 Unless you just let the magic smoke escape,
803 you're now ready to set up the OpenOCD server
804 so you can use JTAG to work with that board.
806 @end enumerate
808 Talk with the OpenOCD server using
809 telnet (@code{telnet localhost 4444} on many systems) or GDB.
810 @xref{GDB and OpenOCD}.
812 @section Project Directory
814 There are many ways you can configure OpenOCD and start it up.
816 A simple way to organize them all involves keeping a
817 single directory for your work with a given board.
818 When you start OpenOCD from that directory,
819 it searches there first for configuration files, scripts,
820 files accessed through semihosting,
821 and for code you upload to the target board.
822 It is also the natural place to write files,
823 such as log files and data you download from the board.
825 @section Configuration Basics
827 There are two basic ways of configuring OpenOCD, and
828 a variety of ways you can mix them.
829 Think of the difference as just being how you start the server:
831 @itemize
832 @item Many @option{-f file} or @option{-c command} options on the command line
833 @item No options, but a @dfn{user config file}
834 in the current directory named @file{openocd.cfg}
835 @end itemize
837 Here is an example @file{openocd.cfg} file for a setup
838 using a Signalyzer FT2232-based JTAG adapter to talk to
839 a board with an Atmel AT91SAM7X256 microcontroller:
841 @example
842 source [find interface/signalyzer.cfg]
844 # GDB can also flash my flash!
845 gdb_memory_map enable
846 gdb_flash_program enable
848 source [find target/sam7x256.cfg]
849 @end example
851 Here is the command line equivalent of that configuration:
853 @example
854 openocd -f interface/signalyzer.cfg \
855 -c "gdb_memory_map enable" \
856 -c "gdb_flash_program enable" \
857 -f target/sam7x256.cfg
858 @end example
860 You could wrap such long command lines in shell scripts,
861 each supporting a different development task.
862 One might re-flash the board with a specific firmware version.
863 Another might set up a particular debugging or run-time environment.
865 @quotation Important
866 At this writing (October 2009) the command line method has
867 problems with how it treats variables.
868 For example, after @option{-c "set VAR value"}, or doing the
869 same in a script, the variable @var{VAR} will have no value
870 that can be tested in a later script.
871 @end quotation
873 Here we will focus on the simpler solution: one user config
874 file, including basic configuration plus any TCL procedures
875 to simplify your work.
877 @section User Config Files
878 @cindex config file, user
879 @cindex user config file
880 @cindex config file, overview
882 A user configuration file ties together all the parts of a project
883 in one place.
884 One of the following will match your situation best:
886 @itemize
887 @item Ideally almost everything comes from configuration files
888 provided by someone else.
889 For example, OpenOCD distributes a @file{scripts} directory
890 (probably in @file{/usr/share/openocd/scripts} on Linux).
891 Board and tool vendors can provide these too, as can individual
892 user sites; the @option{-s} command line option lets you say
893 where to find these files. (@xref{Running}.)
894 The AT91SAM7X256 example above works this way.
896 Three main types of non-user configuration file each have their
897 own subdirectory in the @file{scripts} directory:
899 @enumerate
900 @item @b{interface} -- one for each different debug adapter;
901 @item @b{board} -- one for each different board
902 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
903 @end enumerate
905 Best case: include just two files, and they handle everything else.
906 The first is an interface config file.
907 The second is board-specific, and it sets up the JTAG TAPs and
908 their GDB targets (by deferring to some @file{target.cfg} file),
909 declares all flash memory, and leaves you nothing to do except
910 meet your deadline:
912 @example
913 source [find interface/olimex-jtag-tiny.cfg]
914 source [find board/csb337.cfg]
915 @end example
917 Boards with a single microcontroller often won't need more
918 than the target config file, as in the AT91SAM7X256 example.
919 That's because there is no external memory (flash, DDR RAM), and
920 the board differences are encapsulated by application code.
922 @item Maybe you don't know yet what your board looks like to JTAG.
923 Once you know the @file{interface.cfg} file to use, you may
924 need help from OpenOCD to discover what's on the board.
925 Once you find the JTAG TAPs, you can just search for appropriate
926 target and board
927 configuration files ... or write your own, from the bottom up.
928 @xref{Autoprobing}.
930 @item You can often reuse some standard config files but
931 need to write a few new ones, probably a @file{board.cfg} file.
932 You will be using commands described later in this User's Guide,
933 and working with the guidelines in the next chapter.
935 For example, there may be configuration files for your JTAG adapter
936 and target chip, but you need a new board-specific config file
937 giving access to your particular flash chips.
938 Or you might need to write another target chip configuration file
939 for a new chip built around the Cortex M3 core.
941 @quotation Note
942 When you write new configuration files, please submit
943 them for inclusion in the next OpenOCD release.
944 For example, a @file{board/newboard.cfg} file will help the
945 next users of that board, and a @file{target/newcpu.cfg}
946 will help support users of any board using that chip.
947 @end quotation
949 @item
950 You may may need to write some C code.
951 It may be as simple as a supporting a new ft2232 or parport
952 based adapter; a bit more involved, like a NAND or NOR flash
953 controller driver; or a big piece of work like supporting
954 a new chip architecture.
955 @end itemize
957 Reuse the existing config files when you can.
958 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
959 You may find a board configuration that's a good example to follow.
961 When you write config files, separate the reusable parts
962 (things every user of that interface, chip, or board needs)
963 from ones specific to your environment and debugging approach.
964 @itemize
966 @item
967 For example, a @code{gdb-attach} event handler that invokes
968 the @command{reset init} command will interfere with debugging
969 early boot code, which performs some of the same actions
970 that the @code{reset-init} event handler does.
972 @item
973 Likewise, the @command{arm9 vector_catch} command (or
974 @cindex vector_catch
975 its siblings @command{xscale vector_catch}
976 and @command{cortex_m3 vector_catch}) can be a timesaver
977 during some debug sessions, but don't make everyone use that either.
978 Keep those kinds of debugging aids in your user config file,
979 along with messaging and tracing setup.
980 (@xref{Software Debug Messages and Tracing}.)
982 @item
983 You might need to override some defaults.
984 For example, you might need to move, shrink, or back up the target's
985 work area if your application needs much SRAM.
987 @item
988 TCP/IP port configuration is another example of something which
989 is environment-specific, and should only appear in
990 a user config file. @xref{TCP/IP Ports}.
991 @end itemize
993 @section Project-Specific Utilities
995 A few project-specific utility
996 routines may well speed up your work.
997 Write them, and keep them in your project's user config file.
999 For example, if you are making a boot loader work on a
1000 board, it's nice to be able to debug the ``after it's
1001 loaded to RAM'' parts separately from the finicky early
1002 code which sets up the DDR RAM controller and clocks.
1003 A script like this one, or a more GDB-aware sibling,
1004 may help:
1006 @example
1007 proc ramboot @{ @} @{
1008 # Reset, running the target's "reset-init" scripts
1009 # to initialize clocks and the DDR RAM controller.
1010 # Leave the CPU halted.
1011 reset init
1013 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1014 load_image u-boot.bin 0x20000000
1016 # Start running.
1017 resume 0x20000000
1018 @}
1019 @end example
1021 Then once that code is working you will need to make it
1022 boot from NOR flash; a different utility would help.
1023 Alternatively, some developers write to flash using GDB.
1024 (You might use a similar script if you're working with a flash
1025 based microcontroller application instead of a boot loader.)
1027 @example
1028 proc newboot @{ @} @{
1029 # Reset, leaving the CPU halted. The "reset-init" event
1030 # proc gives faster access to the CPU and to NOR flash;
1031 # "reset halt" would be slower.
1032 reset init
1034 # Write standard version of U-Boot into the first two
1035 # sectors of NOR flash ... the standard version should
1036 # do the same lowlevel init as "reset-init".
1037 flash protect 0 0 1 off
1038 flash erase_sector 0 0 1
1039 flash write_bank 0 u-boot.bin 0x0
1040 flash protect 0 0 1 on
1042 # Reboot from scratch using that new boot loader.
1043 reset run
1044 @}
1045 @end example
1047 You may need more complicated utility procedures when booting
1048 from NAND.
1049 That often involves an extra bootloader stage,
1050 running from on-chip SRAM to perform DDR RAM setup so it can load
1051 the main bootloader code (which won't fit into that SRAM).
1053 Other helper scripts might be used to write production system images,
1054 involving considerably more than just a three stage bootloader.
1056 @section Target Software Changes
1058 Sometimes you may want to make some small changes to the software
1059 you're developing, to help make JTAG debugging work better.
1060 For example, in C or assembly language code you might
1061 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1062 handling issues like:
1064 @itemize @bullet
1066 @item @b{Watchdog Timers}...
1067 Watchog timers are typically used to automatically reset systems if
1068 some application task doesn't periodically reset the timer. (The
1069 assumption is that the system has locked up if the task can't run.)
1070 When a JTAG debugger halts the system, that task won't be able to run
1071 and reset the timer ... potentially causing resets in the middle of
1072 your debug sessions.
1074 It's rarely a good idea to disable such watchdogs, since their usage
1075 needs to be debugged just like all other parts of your firmware.
1076 That might however be your only option.
1078 Look instead for chip-specific ways to stop the watchdog from counting
1079 while the system is in a debug halt state. It may be simplest to set
1080 that non-counting mode in your debugger startup scripts. You may however
1081 need a different approach when, for example, a motor could be physically
1082 damaged by firmware remaining inactive in a debug halt state. That might
1083 involve a type of firmware mode where that "non-counting" mode is disabled
1084 at the beginning then re-enabled at the end; a watchdog reset might fire
1085 and complicate the debug session, but hardware (or people) would be
1086 protected.@footnote{Note that many systems support a "monitor mode" debug
1087 that is a somewhat cleaner way to address such issues. You can think of
1088 it as only halting part of the system, maybe just one task,
1089 instead of the whole thing.
1090 At this writing, January 2010, OpenOCD based debugging does not support
1091 monitor mode debug, only "halt mode" debug.}
1093 @item @b{ARM Semihosting}...
1094 @cindex ARM semihosting
1095 When linked with a special runtime library provided with many
1096 toolchains@footnote{See chapter 8 "Semihosting" in
1097 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1098 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1099 The CodeSourcery EABI toolchain also includes a semihosting library.},
1100 your target code can use I/O facilities on the debug host. That library
1101 provides a small set of system calls which are handled by OpenOCD.
1102 It can let the debugger provide your system console and a file system,
1103 helping with early debugging or providing a more capable environment
1104 for sometimes-complex tasks like installing system firmware onto
1105 NAND or SPI flash.
1107 @item @b{ARM Wait-For-Interrupt}...
1108 Many ARM chips synchronize the JTAG clock using the core clock.
1109 Low power states which stop that core clock thus prevent JTAG access.
1110 Idle loops in tasking environments often enter those low power states
1111 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1113 You may want to @emph{disable that instruction} in source code,
1114 or otherwise prevent using that state,
1115 to ensure you can get JTAG access at any time.@footnote{As a more
1116 polite alternative, some processors have special debug-oriented
1117 registers which can be used to change various features including
1118 how the low power states are clocked while debugging.
1119 The STM32 DBGMCU_CR register is an example; at the cost of extra
1120 power consumption, JTAG can be used during low power states.}
1121 For example, the OpenOCD @command{halt} command may not
1122 work for an idle processor otherwise.
1124 @item @b{Delay after reset}...
1125 Not all chips have good support for debugger access
1126 right after reset; many LPC2xxx chips have issues here.
1127 Similarly, applications that reconfigure pins used for
1128 JTAG access as they start will also block debugger access.
1130 To work with boards like this, @emph{enable a short delay loop}
1131 the first thing after reset, before "real" startup activities.
1132 For example, one second's delay is usually more than enough
1133 time for a JTAG debugger to attach, so that
1134 early code execution can be debugged
1135 or firmware can be replaced.
1137 @item @b{Debug Communications Channel (DCC)}...
1138 Some processors include mechanisms to send messages over JTAG.
1139 Many ARM cores support these, as do some cores from other vendors.
1140 (OpenOCD may be able to use this DCC internally, speeding up some
1141 operations like writing to memory.)
1143 Your application may want to deliver various debugging messages
1144 over JTAG, by @emph{linking with a small library of code}
1145 provided with OpenOCD and using the utilities there to send
1146 various kinds of message.
1147 @xref{Software Debug Messages and Tracing}.
1149 @end itemize
1151 @section Target Hardware Setup
1153 Chip vendors often provide software development boards which
1154 are highly configurable, so that they can support all options
1155 that product boards may require. @emph{Make sure that any
1156 jumpers or switches match the system configuration you are
1157 working with.}
1159 Common issues include:
1161 @itemize @bullet
1163 @item @b{JTAG setup} ...
1164 Boards may support more than one JTAG configuration.
1165 Examples include jumpers controlling pullups versus pulldowns
1166 on the nTRST and/or nSRST signals, and choice of connectors
1167 (e.g. which of two headers on the base board,
1168 or one from a daughtercard).
1169 For some Texas Instruments boards, you may need to jumper the
1170 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1172 @item @b{Boot Modes} ...
1173 Complex chips often support multiple boot modes, controlled
1174 by external jumpers. Make sure this is set up correctly.
1175 For example many i.MX boards from NXP need to be jumpered
1176 to "ATX mode" to start booting using the on-chip ROM, when
1177 using second stage bootloader code stored in a NAND flash chip.
1179 Such explicit configuration is common, and not limited to
1180 booting from NAND. You might also need to set jumpers to
1181 start booting using code loaded from an MMC/SD card; external
1182 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1183 flash; some external host; or various other sources.
1186 @item @b{Memory Addressing} ...
1187 Boards which support multiple boot modes may also have jumpers
1188 to configure memory addressing. One board, for example, jumpers
1189 external chipselect 0 (used for booting) to address either
1190 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1191 or NAND flash. When it's jumpered to address NAND flash, that
1192 board must also be told to start booting from on-chip ROM.
1194 Your @file{board.cfg} file may also need to be told this jumper
1195 configuration, so that it can know whether to declare NOR flash
1196 using @command{flash bank} or instead declare NAND flash with
1197 @command{nand device}; and likewise which probe to perform in
1198 its @code{reset-init} handler.
1200 A closely related issue is bus width. Jumpers might need to
1201 distinguish between 8 bit or 16 bit bus access for the flash
1202 used to start booting.
1204 @item @b{Peripheral Access} ...
1205 Development boards generally provide access to every peripheral
1206 on the chip, sometimes in multiple modes (such as by providing
1207 multiple audio codec chips).
1208 This interacts with software
1209 configuration of pin multiplexing, where for example a
1210 given pin may be routed either to the MMC/SD controller
1211 or the GPIO controller. It also often interacts with
1212 configuration jumpers. One jumper may be used to route
1213 signals to an MMC/SD card slot or an expansion bus (which
1214 might in turn affect booting); others might control which
1215 audio or video codecs are used.
1217 @end itemize
1219 Plus you should of course have @code{reset-init} event handlers
1220 which set up the hardware to match that jumper configuration.
1221 That includes in particular any oscillator or PLL used to clock
1222 the CPU, and any memory controllers needed to access external
1223 memory and peripherals. Without such handlers, you won't be
1224 able to access those resources without working target firmware
1225 which can do that setup ... this can be awkward when you're
1226 trying to debug that target firmware. Even if there's a ROM
1227 bootloader which handles a few issues, it rarely provides full
1228 access to all board-specific capabilities.
1231 @node Config File Guidelines
1232 @chapter Config File Guidelines
1234 This chapter is aimed at any user who needs to write a config file,
1235 including developers and integrators of OpenOCD and any user who
1236 needs to get a new board working smoothly.
1237 It provides guidelines for creating those files.
1239 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1240 with files including the ones listed here.
1241 Use them as-is where you can; or as models for new files.
1242 @itemize @bullet
1243 @item @file{interface} ...
1244 These are for debug adapters.
1245 Files that configure JTAG adapters go here.
1246 @example
1247 $ ls interface
1248 altera-usb-blaster.cfg hilscher_nxhx50_etm.cfg openrd.cfg
1249 arm-jtag-ew.cfg hilscher_nxhx50_re.cfg osbdm.cfg
1250 arm-usb-ocd.cfg hitex_str9-comstick.cfg parport.cfg
1251 at91rm9200.cfg icebear.cfg parport_dlc5.cfg
1252 axm0432.cfg jlink.cfg redbee-econotag.cfg
1253 busblaster.cfg jtagkey2.cfg redbee-usb.cfg
1254 buspirate.cfg jtagkey2p.cfg rlink.cfg
1255 calao-usb-a9260-c01.cfg jtagkey.cfg sheevaplug.cfg
1256 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg signalyzer.cfg
1257 calao-usb-a9260.cfg kt-link.cfg signalyzer-h2.cfg
1258 chameleon.cfg lisa-l.cfg signalyzer-h4.cfg
1259 cortino.cfg luminary.cfg signalyzer-lite.cfg
1260 digilent-hs1.cfg luminary-icdi.cfg stlink-v1.cfg
1261 dlp-usb1232h.cfg luminary-lm3s811.cfg stlink-v2.cfg
1262 dummy.cfg minimodule.cfg stm32-stick.cfg
1263 estick.cfg neodb.cfg turtelizer2.cfg
1264 flashlink.cfg ngxtech.cfg ulink.cfg
1265 flossjtag.cfg olimex-arm-usb-ocd.cfg usb-jtag.cfg
1266 flossjtag-noeeprom.cfg olimex-arm-usb-ocd-h.cfg usbprog.cfg
1267 flyswatter2.cfg olimex-arm-usb-tiny-h.cfg vpaclink.cfg
1268 flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
1269 hilscher_nxhx10_etm.cfg oocdlink.cfg xds100v2.cfg
1270 hilscher_nxhx500_etm.cfg opendous.cfg
1271 hilscher_nxhx500_re.cfg openocd-usb.cfg
1272 $
1273 @end example
1274 @item @file{board} ...
1275 think Circuit Board, PWA, PCB, they go by many names. Board files
1276 contain initialization items that are specific to a board.
1277 They reuse target configuration files, since the same
1278 microprocessor chips are used on many boards,
1279 but support for external parts varies widely. For
1280 example, the SDRAM initialization sequence for the board, or the type
1281 of external flash and what address it uses. Any initialization
1282 sequence to enable that external flash or SDRAM should be found in the
1283 board file. Boards may also contain multiple targets: two CPUs; or
1284 a CPU and an FPGA.
1285 @example
1286 $ ls board
1287 actux3.cfg logicpd_imx27.cfg
1288 am3517evm.cfg lubbock.cfg
1289 arm_evaluator7t.cfg mcb1700.cfg
1290 at91cap7a-stk-sdram.cfg microchip_explorer16.cfg
1291 at91eb40a.cfg mini2440.cfg
1292 at91rm9200-dk.cfg mini6410.cfg
1293 at91rm9200-ek.cfg olimex_LPC2378STK.cfg
1294 at91sam9261-ek.cfg olimex_lpc_h2148.cfg
1295 at91sam9263-ek.cfg olimex_sam7_ex256.cfg
1296 at91sam9g20-ek.cfg olimex_sam9_l9260.cfg
1297 atmel_at91sam7s-ek.cfg olimex_stm32_h103.cfg
1298 atmel_at91sam9260-ek.cfg olimex_stm32_h107.cfg
1299 atmel_at91sam9rl-ek.cfg olimex_stm32_p107.cfg
1300 atmel_sam3n_ek.cfg omap2420_h4.cfg
1301 atmel_sam3s_ek.cfg open-bldc.cfg
1302 atmel_sam3u_ek.cfg openrd.cfg
1303 atmel_sam3x_ek.cfg osk5912.cfg
1304 atmel_sam4s_ek.cfg phytec_lpc3250.cfg
1305 balloon3-cpu.cfg pic-p32mx.cfg
1306 colibri.cfg propox_mmnet1001.cfg
1307 crossbow_tech_imote2.cfg pxa255_sst.cfg
1308 csb337.cfg redbee.cfg
1309 csb732.cfg rsc-w910.cfg
1310 da850evm.cfg sheevaplug.cfg
1311 digi_connectcore_wi-9c.cfg smdk6410.cfg
1312 diolan_lpc4350-db1.cfg spear300evb.cfg
1313 dm355evm.cfg spear300evb_mod.cfg
1314 dm365evm.cfg spear310evb20.cfg
1315 dm6446evm.cfg spear310evb20_mod.cfg
1316 efikamx.cfg spear320cpu.cfg
1317 eir.cfg spear320cpu_mod.cfg
1318 ek-lm3s1968.cfg steval_pcc010.cfg
1319 ek-lm3s3748.cfg stm320518_eval_stlink.cfg
1320 ek-lm3s6965.cfg stm32100b_eval.cfg
1321 ek-lm3s811.cfg stm3210b_eval.cfg
1322 ek-lm3s811-revb.cfg stm3210c_eval.cfg
1323 ek-lm3s9b9x.cfg stm3210e_eval.cfg
1324 ek-lm4f232.cfg stm3220g_eval.cfg
1325 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1326 ethernut3.cfg stm3241g_eval.cfg
1327 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1328 hammer.cfg stm32f0discovery.cfg
1329 hilscher_nxdb500sys.cfg stm32f4discovery.cfg
1330 hilscher_nxeb500hmi.cfg stm32ldiscovery.cfg
1331 hilscher_nxhx10.cfg stm32vldiscovery.cfg
1332 hilscher_nxhx500.cfg str910-eval.cfg
1333 hilscher_nxhx50.cfg telo.cfg
1334 hilscher_nxsb100.cfg ti_beagleboard.cfg
1335 hitex_lpc2929.cfg ti_beagleboard_xm.cfg
1336 hitex_stm32-performancestick.cfg ti_beaglebone.cfg
1337 hitex_str9-comstick.cfg ti_blaze.cfg
1338 iar_lpc1768.cfg ti_pandaboard.cfg
1339 iar_str912_sk.cfg ti_pandaboard_es.cfg
1340 icnova_imx53_sodimm.cfg topas910.cfg
1341 icnova_sam9g45_sodimm.cfg topasa900.cfg
1342 imx27ads.cfg twr-k60n512.cfg
1343 imx27lnst.cfg tx25_stk5.cfg
1344 imx28evk.cfg tx27_stk5.cfg
1345 imx31pdk.cfg unknown_at91sam9260.cfg
1346 imx35pdk.cfg uptech_2410.cfg
1347 imx53loco.cfg verdex.cfg
1348 keil_mcb1700.cfg voipac.cfg
1349 keil_mcb2140.cfg voltcraft_dso-3062c.cfg
1350 kwikstik.cfg x300t.cfg
1351 linksys_nslu2.cfg zy1000.cfg
1352 lisa-l.cfg
1353 $
1354 @end example
1355 @item @file{target} ...
1356 think chip. The ``target'' directory represents the JTAG TAPs
1357 on a chip
1358 which OpenOCD should control, not a board. Two common types of targets
1359 are ARM chips and FPGA or CPLD chips.
1360 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1361 the target config file defines all of them.
1362 @example
1363 $ ls target
1364 $duc702x.cfg ixp42x.cfg
1365 am335x.cfg k40.cfg
1366 amdm37x.cfg k60.cfg
1367 ar71xx.cfg lpc1768.cfg
1368 at32ap7000.cfg lpc2103.cfg
1369 at91r40008.cfg lpc2124.cfg
1370 at91rm9200.cfg lpc2129.cfg
1371 at91sam3ax_4x.cfg lpc2148.cfg
1372 at91sam3ax_8x.cfg lpc2294.cfg
1373 at91sam3ax_xx.cfg lpc2378.cfg
1374 at91sam3nXX.cfg lpc2460.cfg
1375 at91sam3sXX.cfg lpc2478.cfg
1376 at91sam3u1c.cfg lpc2900.cfg
1377 at91sam3u1e.cfg lpc2xxx.cfg
1378 at91sam3u2c.cfg lpc3131.cfg
1379 at91sam3u2e.cfg lpc3250.cfg
1380 at91sam3u4c.cfg lpc4350.cfg
1381 at91sam3u4e.cfg mc13224v.cfg
1382 at91sam3uxx.cfg nuc910.cfg
1383 at91sam3XXX.cfg omap2420.cfg
1384 at91sam4sXX.cfg omap3530.cfg
1385 at91sam4XXX.cfg omap4430.cfg
1386 at91sam7se512.cfg omap4460.cfg
1387 at91sam7sx.cfg omap5912.cfg
1388 at91sam7x256.cfg omapl138.cfg
1389 at91sam7x512.cfg pic32mx.cfg
1390 at91sam9260.cfg pxa255.cfg
1391 at91sam9260_ext_RAM_ext_flash.cfg pxa270.cfg
1392 at91sam9261.cfg pxa3xx.cfg
1393 at91sam9263.cfg readme.txt
1394 at91sam9.cfg samsung_s3c2410.cfg
1395 at91sam9g10.cfg samsung_s3c2440.cfg
1396 at91sam9g20.cfg samsung_s3c2450.cfg
1397 at91sam9g45.cfg samsung_s3c4510.cfg
1398 at91sam9rl.cfg samsung_s3c6410.cfg
1399 atmega128.cfg sharp_lh79532.cfg
1400 avr32.cfg smp8634.cfg
1401 c100.cfg spear3xx.cfg
1402 c100config.tcl stellaris.cfg
1403 c100helper.tcl stm32.cfg
1404 c100regs.tcl stm32f0x_stlink.cfg
1405 cs351x.cfg stm32f1x.cfg
1406 davinci.cfg stm32f1x_stlink.cfg
1407 dragonite.cfg stm32f2x.cfg
1408 dsp56321.cfg stm32f2x_stlink.cfg
1409 dsp568013.cfg stm32f2xxx.cfg
1410 dsp568037.cfg stm32f4x.cfg
1411 epc9301.cfg stm32f4x_stlink.cfg
1412 faux.cfg stm32l.cfg
1413 feroceon.cfg stm32lx_stlink.cfg
1414 fm3.cfg stm32_stlink.cfg
1415 hilscher_netx10.cfg stm32xl.cfg
1416 hilscher_netx500.cfg str710.cfg
1417 hilscher_netx50.cfg str730.cfg
1418 icepick.cfg str750.cfg
1419 imx21.cfg str912.cfg
1420 imx25.cfg swj-dp.tcl
1421 imx27.cfg test_reset_syntax_error.cfg
1422 imx28.cfg test_syntax_error.cfg
1423 imx31.cfg ti_dm355.cfg
1424 imx35.cfg ti_dm365.cfg
1425 imx51.cfg ti_dm6446.cfg
1426 imx53.cfg tmpa900.cfg
1427 imx.cfg tmpa910.cfg
1428 is5114.cfg u8500.cfg
1429 @end example
1430 @item @emph{more} ... browse for other library files which may be useful.
1431 For example, there are various generic and CPU-specific utilities.
1432 @end itemize
1434 The @file{openocd.cfg} user config
1435 file may override features in any of the above files by
1436 setting variables before sourcing the target file, or by adding
1437 commands specific to their situation.
1439 @section Interface Config Files
1441 The user config file
1442 should be able to source one of these files with a command like this:
1444 @example
1445 source [find interface/FOOBAR.cfg]
1446 @end example
1448 A preconfigured interface file should exist for every debug adapter
1449 in use today with OpenOCD.
1450 That said, perhaps some of these config files
1451 have only been used by the developer who created it.
1453 A separate chapter gives information about how to set these up.
1454 @xref{Debug Adapter Configuration}.
1455 Read the OpenOCD source code (and Developer's Guide)
1456 if you have a new kind of hardware interface
1457 and need to provide a driver for it.
1459 @section Board Config Files
1460 @cindex config file, board
1461 @cindex board config file
1463 The user config file
1464 should be able to source one of these files with a command like this:
1466 @example
1467 source [find board/FOOBAR.cfg]
1468 @end example
1470 The point of a board config file is to package everything
1471 about a given board that user config files need to know.
1472 In summary the board files should contain (if present)
1474 @enumerate
1475 @item One or more @command{source [target/...cfg]} statements
1476 @item NOR flash configuration (@pxref{NOR Configuration})
1477 @item NAND flash configuration (@pxref{NAND Configuration})
1478 @item Target @code{reset} handlers for SDRAM and I/O configuration
1479 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1480 @item All things that are not ``inside a chip''
1481 @end enumerate
1483 Generic things inside target chips belong in target config files,
1484 not board config files. So for example a @code{reset-init} event
1485 handler should know board-specific oscillator and PLL parameters,
1486 which it passes to target-specific utility code.
1488 The most complex task of a board config file is creating such a
1489 @code{reset-init} event handler.
1490 Define those handlers last, after you verify the rest of the board
1491 configuration works.
1493 @subsection Communication Between Config files
1495 In addition to target-specific utility code, another way that
1496 board and target config files communicate is by following a
1497 convention on how to use certain variables.
1499 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1500 Thus the rule we follow in OpenOCD is this: Variables that begin with
1501 a leading underscore are temporary in nature, and can be modified and
1502 used at will within a target configuration file.
1504 Complex board config files can do the things like this,
1505 for a board with three chips:
1507 @example
1508 # Chip #1: PXA270 for network side, big endian
1509 set CHIPNAME network
1510 set ENDIAN big
1511 source [find target/pxa270.cfg]
1512 # on return: _TARGETNAME = network.cpu
1513 # other commands can refer to the "network.cpu" target.
1514 $_TARGETNAME configure .... events for this CPU..
1516 # Chip #2: PXA270 for video side, little endian
1517 set CHIPNAME video
1518 set ENDIAN little
1519 source [find target/pxa270.cfg]
1520 # on return: _TARGETNAME = video.cpu
1521 # other commands can refer to the "video.cpu" target.
1522 $_TARGETNAME configure .... events for this CPU..
1524 # Chip #3: Xilinx FPGA for glue logic
1525 set CHIPNAME xilinx
1526 unset ENDIAN
1527 source [find target/spartan3.cfg]
1528 @end example
1530 That example is oversimplified because it doesn't show any flash memory,
1531 or the @code{reset-init} event handlers to initialize external DRAM
1532 or (assuming it needs it) load a configuration into the FPGA.
1533 Such features are usually needed for low-level work with many boards,
1534 where ``low level'' implies that the board initialization software may
1535 not be working. (That's a common reason to need JTAG tools. Another
1536 is to enable working with microcontroller-based systems, which often
1537 have no debugging support except a JTAG connector.)
1539 Target config files may also export utility functions to board and user
1540 config files. Such functions should use name prefixes, to help avoid
1541 naming collisions.
1543 Board files could also accept input variables from user config files.
1544 For example, there might be a @code{J4_JUMPER} setting used to identify
1545 what kind of flash memory a development board is using, or how to set
1546 up other clocks and peripherals.
1548 @subsection Variable Naming Convention
1549 @cindex variable names
1551 Most boards have only one instance of a chip.
1552 However, it should be easy to create a board with more than
1553 one such chip (as shown above).
1554 Accordingly, we encourage these conventions for naming
1555 variables associated with different @file{target.cfg} files,
1556 to promote consistency and
1557 so that board files can override target defaults.
1559 Inputs to target config files include:
1561 @itemize @bullet
1562 @item @code{CHIPNAME} ...
1563 This gives a name to the overall chip, and is used as part of
1564 tap identifier dotted names.
1565 While the default is normally provided by the chip manufacturer,
1566 board files may need to distinguish between instances of a chip.
1567 @item @code{ENDIAN} ...
1568 By default @option{little} - although chips may hard-wire @option{big}.
1569 Chips that can't change endianness don't need to use this variable.
1570 @item @code{CPUTAPID} ...
1571 When OpenOCD examines the JTAG chain, it can be told verify the
1572 chips against the JTAG IDCODE register.
1573 The target file will hold one or more defaults, but sometimes the
1574 chip in a board will use a different ID (perhaps a newer revision).
1575 @end itemize
1577 Outputs from target config files include:
1579 @itemize @bullet
1580 @item @code{_TARGETNAME} ...
1581 By convention, this variable is created by the target configuration
1582 script. The board configuration file may make use of this variable to
1583 configure things like a ``reset init'' script, or other things
1584 specific to that board and that target.
1585 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1586 @code{_TARGETNAME1}, ... etc.
1587 @end itemize
1589 @subsection The reset-init Event Handler
1590 @cindex event, reset-init
1591 @cindex reset-init handler
1593 Board config files run in the OpenOCD configuration stage;
1594 they can't use TAPs or targets, since they haven't been
1595 fully set up yet.
1596 This means you can't write memory or access chip registers;
1597 you can't even verify that a flash chip is present.
1598 That's done later in event handlers, of which the target @code{reset-init}
1599 handler is one of the most important.
1601 Except on microcontrollers, the basic job of @code{reset-init} event
1602 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1603 Microcontrollers rarely use boot loaders; they run right out of their
1604 on-chip flash and SRAM memory. But they may want to use one of these
1605 handlers too, if just for developer convenience.
1607 @quotation Note
1608 Because this is so very board-specific, and chip-specific, no examples
1609 are included here.
1610 Instead, look at the board config files distributed with OpenOCD.
1611 If you have a boot loader, its source code will help; so will
1612 configuration files for other JTAG tools
1613 (@pxref{Translating Configuration Files}).
1614 @end quotation
1616 Some of this code could probably be shared between different boards.
1617 For example, setting up a DRAM controller often doesn't differ by
1618 much except the bus width (16 bits or 32?) and memory timings, so a
1619 reusable TCL procedure loaded by the @file{target.cfg} file might take
1620 those as parameters.
1621 Similarly with oscillator, PLL, and clock setup;
1622 and disabling the watchdog.
1623 Structure the code cleanly, and provide comments to help
1624 the next developer doing such work.
1625 (@emph{You might be that next person} trying to reuse init code!)
1627 The last thing normally done in a @code{reset-init} handler is probing
1628 whatever flash memory was configured. For most chips that needs to be
1629 done while the associated target is halted, either because JTAG memory
1630 access uses the CPU or to prevent conflicting CPU access.
1632 @subsection JTAG Clock Rate
1634 Before your @code{reset-init} handler has set up
1635 the PLLs and clocking, you may need to run with
1636 a low JTAG clock rate.
1637 @xref{JTAG Speed}.
1638 Then you'd increase that rate after your handler has
1639 made it possible to use the faster JTAG clock.
1640 When the initial low speed is board-specific, for example
1641 because it depends on a board-specific oscillator speed, then
1642 you should probably set it up in the board config file;
1643 if it's target-specific, it belongs in the target config file.
1645 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1646 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1647 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1648 Consult chip documentation to determine the peak JTAG clock rate,
1649 which might be less than that.
1651 @quotation Warning
1652 On most ARMs, JTAG clock detection is coupled to the core clock, so
1653 software using a @option{wait for interrupt} operation blocks JTAG access.
1654 Adaptive clocking provides a partial workaround, but a more complete
1655 solution just avoids using that instruction with JTAG debuggers.
1656 @end quotation
1658 If both the chip and the board support adaptive clocking,
1659 use the @command{jtag_rclk}
1660 command, in case your board is used with JTAG adapter which
1661 also supports it. Otherwise use @command{adapter_khz}.
1662 Set the slow rate at the beginning of the reset sequence,
1663 and the faster rate as soon as the clocks are at full speed.
1665 @anchor{The init_board procedure}
1666 @subsection The init_board procedure
1667 @cindex init_board procedure
1669 The concept of @code{init_board} procedure is very similar to @code{init_targets} (@xref{The init_targets procedure}.)
1670 - it's a replacement of ``linear'' configuration scripts. This procedure is meant to be executed when OpenOCD enters run
1671 stage (@xref{Entering the Run Stage},) after @code{init_targets}. The idea to have spearate @code{init_targets} and
1672 @code{init_board} procedures is to allow the first one to configure everything target specific (internal flash,
1673 internal RAM, etc.) and the second one to configure everything board specific (reset signals, chip frequency,
1674 reset-init event handler, external memory, etc.). Additionally ``linear'' board config file will most likely fail when
1675 target config file uses @code{init_targets} scheme (``linear'' script is executed before @code{init} and
1676 @code{init_targets} - after), so separating these two configuration stages is very convenient, as the easiest way to
1677 overcome this problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1678 need to override @code{init_targets} defined in target config files when they only need to to add some specifics.
1680 Just as @code{init_targets}, the @code{init_board} procedure can be overriden by ``next level'' script (which sources
1681 the original), allowing greater code reuse.
1683 @example
1684 ### board_file.cfg ###
1686 # source target file that does most of the config in init_targets
1687 source [find target/target.cfg]
1689 proc enable_fast_clock @{@} @{
1690 # enables fast on-board clock source
1691 # configures the chip to use it
1692 @}
1694 # initialize only board specifics - reset, clock, adapter frequency
1695 proc init_board @{@} @{
1696 reset_config trst_and_srst trst_pulls_srst
1698 $_TARGETNAME configure -event reset-init @{
1699 adapter_khz 1
1700 enable_fast_clock
1701 adapter_khz 10000
1702 @}
1703 @}
1704 @end example
1706 @section Target Config Files
1707 @cindex config file, target
1708 @cindex target config file
1710 Board config files communicate with target config files using
1711 naming conventions as described above, and may source one or
1712 more target config files like this:
1714 @example
1715 source [find target/FOOBAR.cfg]
1716 @end example
1718 The point of a target config file is to package everything
1719 about a given chip that board config files need to know.
1720 In summary the target files should contain
1722 @enumerate
1723 @item Set defaults
1724 @item Add TAPs to the scan chain
1725 @item Add CPU targets (includes GDB support)
1726 @item CPU/Chip/CPU-Core specific features
1727 @item On-Chip flash
1728 @end enumerate
1730 As a rule of thumb, a target file sets up only one chip.
1731 For a microcontroller, that will often include a single TAP,
1732 which is a CPU needing a GDB target, and its on-chip flash.
1734 More complex chips may include multiple TAPs, and the target
1735 config file may need to define them all before OpenOCD
1736 can talk to the chip.
1737 For example, some phone chips have JTAG scan chains that include
1738 an ARM core for operating system use, a DSP,
1739 another ARM core embedded in an image processing engine,
1740 and other processing engines.
1742 @subsection Default Value Boiler Plate Code
1744 All target configuration files should start with code like this,
1745 letting board config files express environment-specific
1746 differences in how things should be set up.
1748 @example
1749 # Boards may override chip names, perhaps based on role,
1750 # but the default should match what the vendor uses
1751 if @{ [info exists CHIPNAME] @} @{
1753 @} else @{
1754 set _CHIPNAME sam7x256
1755 @}
1757 # ONLY use ENDIAN with targets that can change it.
1758 if @{ [info exists ENDIAN] @} @{
1759 set _ENDIAN $ENDIAN
1760 @} else @{
1761 set _ENDIAN little
1762 @}
1764 # TAP identifiers may change as chips mature, for example with
1765 # new revision fields (the "3" here). Pick a good default; you
1766 # can pass several such identifiers to the "jtag newtap" command.
1767 if @{ [info exists CPUTAPID ] @} @{
1769 @} else @{
1770 set _CPUTAPID 0x3f0f0f0f
1771 @}
1772 @end example
1773 @c but 0x3f0f0f0f is for an str73x part ...
1775 @emph{Remember:} Board config files may include multiple target
1776 config files, or the same target file multiple times
1777 (changing at least @code{CHIPNAME}).
1779 Likewise, the target configuration file should define
1780 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1781 use it later on when defining debug targets:
1783 @example
1785 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1786 @end example
1788 @subsection Adding TAPs to the Scan Chain
1789 After the ``defaults'' are set up,
1790 add the TAPs on each chip to the JTAG scan chain.
1791 @xref{TAP Declaration}, and the naming convention
1792 for taps.
1794 In the simplest case the chip has only one TAP,
1795 probably for a CPU or FPGA.
1796 The config file for the Atmel AT91SAM7X256
1797 looks (in part) like this:
1799 @example
1800 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1801 @end example
1803 A board with two such at91sam7 chips would be able
1804 to source such a config file twice, with different
1805 values for @code{CHIPNAME}, so
1806 it adds a different TAP each time.
1808 If there are nonzero @option{-expected-id} values,
1809 OpenOCD attempts to verify the actual tap id against those values.
1810 It will issue error messages if there is mismatch, which
1811 can help to pinpoint problems in OpenOCD configurations.
1813 @example
1814 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1815 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1816 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1817 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1818 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1819 @end example
1821 There are more complex examples too, with chips that have
1822 multiple TAPs. Ones worth looking at include:
1824 @itemize
1825 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1826 plus a JRC to enable them
1827 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1828 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1829 is not currently used)
1830 @end itemize
1832 @subsection Add CPU targets
1834 After adding a TAP for a CPU, you should set it up so that
1835 GDB and other commands can use it.
1836 @xref{CPU Configuration}.
1837 For the at91sam7 example above, the command can look like this;
1838 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1839 to little endian, and this chip doesn't support changing that.
1841 @example
1843 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1844 @end example
1846 Work areas are small RAM areas associated with CPU targets.
1847 They are used by OpenOCD to speed up downloads,
1848 and to download small snippets of code to program flash chips.
1849 If the chip includes a form of ``on-chip-ram'' - and many do - define
1850 a work area if you can.
1851 Again using the at91sam7 as an example, this can look like:
1853 @example
1854 $_TARGETNAME configure -work-area-phys 0x00200000 \
1855 -work-area-size 0x4000 -work-area-backup 0
1856 @end example
1858 @anchor{Define CPU targets working in SMP}
1859 @subsection Define CPU targets working in SMP
1860 @cindex SMP
1861 After setting targets, you can define a list of targets working in SMP.
1863 @example
1864 set _TARGETNAME_1 $_CHIPNAME.cpu1
1865 set _TARGETNAME_2 $_CHIPNAME.cpu2
1866 target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap \
1867 -coreid 0 -dbgbase $_DAP_DBG1
1868 target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap \
1869 -coreid 1 -dbgbase $_DAP_DBG2
1870 #define 2 targets working in smp.
1871 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1872 @end example
1873 In the above example on cortex_a8, 2 cpus are working in SMP.
1874 In SMP only one GDB instance is created and :
1875 @itemize @bullet
1876 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1877 @item halt command triggers the halt of all targets in the list.
1878 @item resume command triggers the write context and the restart of all targets in the list.
1879 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1880 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1881 displayed by the GDB session @pxref{Using openocd SMP with GDB}.
1882 @end itemize
1884 The SMP behaviour can be disabled/enabled dynamically. On cortex_a8 following
1885 command have been implemented.
1886 @itemize @bullet
1887 @item cortex_a8 smp_on : enable SMP mode, behaviour is as described above.
1888 @item cortex_a8 smp_off : disable SMP mode, the current target is the one
1889 displayed in the GDB session, only this target is now controlled by GDB
1890 session. This behaviour is useful during system boot up.
1891 @item cortex_a8 smp_gdb : display/fix the core id displayed in GDB session see
1892 following example.
1893 @end itemize
1895 @example
1896 >cortex_a8 smp_gdb
1897 gdb coreid 0 -> -1
1898 #0 : coreid 0 is displayed to GDB ,
1899 #-> -1 : next resume triggers a real resume
1900 > cortex_a8 smp_gdb 1
1901 gdb coreid 0 -> 1
1902 #0 :coreid 0 is displayed to GDB ,
1903 #->1 : next resume displays coreid 1 to GDB
1904 > resume
1905 > cortex_a8 smp_gdb
1906 gdb coreid 1 -> 1
1907 #1 :coreid 1 is displayed to GDB ,
1908 #->1 : next resume displays coreid 1 to GDB
1909 > cortex_a8 smp_gdb -1
1910 gdb coreid 1 -> -1
1911 #1 :coreid 1 is displayed to GDB,
1912 #->-1 : next resume triggers a real resume
1913 @end example
1916 @subsection Chip Reset Setup
1918 As a rule, you should put the @command{reset_config} command
1919 into the board file. Most things you think you know about a
1920 chip can be tweaked by the board.
1922 Some chips have specific ways the TRST and SRST signals are
1923 managed. In the unusual case that these are @emph{chip specific}
1924 and can never be changed by board wiring, they could go here.
1925 For example, some chips can't support JTAG debugging without
1926 both signals.
1928 Provide a @code{reset-assert} event handler if you can.
1929 Such a handler uses JTAG operations to reset the target,
1930 letting this target config be used in systems which don't
1931 provide the optional SRST signal, or on systems where you
1932 don't want to reset all targets at once.
1933 Such a handler might write to chip registers to force a reset,
1934 use a JRC to do that (preferable -- the target may be wedged!),
1935 or force a watchdog timer to trigger.
1936 (For Cortex-M3 targets, this is not necessary. The target
1937 driver knows how to use trigger an NVIC reset when SRST is
1938 not available.)
1940 Some chips need special attention during reset handling if
1941 they're going to be used with JTAG.
1942 An example might be needing to send some commands right
1943 after the target's TAP has been reset, providing a
1944 @code{reset-deassert-post} event handler that writes a chip
1945 register to report that JTAG debugging is being done.
1946 Another would be reconfiguring the watchdog so that it stops
1947 counting while the core is halted in the debugger.
1949 JTAG clocking constraints often change during reset, and in
1950 some cases target config files (rather than board config files)
1951 are the right places to handle some of those issues.
1952 For example, immediately after reset most chips run using a
1953 slower clock than they will use later.
1954 That means that after reset (and potentially, as OpenOCD
1955 first starts up) they must use a slower JTAG clock rate
1956 than they will use later.
1957 @xref{JTAG Speed}.
1959 @quotation Important
1960 When you are debugging code that runs right after chip
1961 reset, getting these issues right is critical.
1962 In particular, if you see intermittent failures when
1963 OpenOCD verifies the scan chain after reset,
1964 look at how you are setting up JTAG clocking.
1965 @end quotation
1967 @anchor{The init_targets procedure}
1968 @subsection The init_targets procedure
1969 @cindex init_targets procedure
1971 Target config files can either be ``linear'' (script executed line-by-line when parsed in configuration stage,
1972 @xref{Configuration Stage},) or they can contain a special procedure called @code{init_targets}, which will be executed
1973 when entering run stage (after parsing all config files or after @code{init} command, @xref{Entering the Run Stage}.)
1974 Such procedure can be overriden by ``next level'' script (which sources the original). This concept faciliates code
1975 reuse when basic target config files provide generic configuration procedures and @code{init_targets} procedure, which
1976 can then be sourced and enchanced or changed in a ``more specific'' target config file. This is not possible with
1977 ``linear'' config scripts, because sourcing them executes every initialization commands they provide.
1979 @example
1980 ### generic_file.cfg ###
1982 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1983 # basic initialization procedure ...
1984 @}
1986 proc init_targets @{@} @{
1987 # initializes generic chip with 4kB of flash and 1kB of RAM
1988 setup_my_chip MY_GENERIC_CHIP 4096 1024
1989 @}
1991 ### specific_file.cfg ###
1993 source [find target/generic_file.cfg]
1995 proc init_targets @{@} @{
1996 # initializes specific chip with 128kB of flash and 64kB of RAM
1997 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1998 @}
1999 @end example
2001 The easiest way to convert ``linear'' config files to @code{init_targets} version is to enclose every line of ``code''
2002 (i.e. not @code{source} commands, procedures, etc.) in this procedure.
2004 For an example of this scheme see LPC2000 target config files.
2006 The @code{init_boards} procedure is a similar concept concerning board config files (@xref{The init_board procedure}.)
2008 @subsection ARM Core Specific Hacks
2010 If the chip has a DCC, enable it. If the chip is an ARM9 with some
2011 special high speed download features - enable it.
2013 If present, the MMU, the MPU and the CACHE should be disabled.
2015 Some ARM cores are equipped with trace support, which permits
2016 examination of the instruction and data bus activity. Trace
2017 activity is controlled through an ``Embedded Trace Module'' (ETM)
2018 on one of the core's scan chains. The ETM emits voluminous data
2019 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
2020 If you are using an external trace port,
2021 configure it in your board config file.
2022 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2023 configure it in your target config file.
2025 @example
2026 etm config $_TARGETNAME 16 normal full etb
2027 etb config $_TARGETNAME $_CHIPNAME.etb
2028 @end example
2030 @subsection Internal Flash Configuration
2032 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2034 @b{Never ever} in the ``target configuration file'' define any type of
2035 flash that is external to the chip. (For example a BOOT flash on
2036 Chip Select 0.) Such flash information goes in a board file - not
2037 the TARGET (chip) file.
2039 Examples:
2040 @itemize @bullet
2041 @item at91sam7x256 - has 256K flash YES enable it.
2042 @item str912 - has flash internal YES enable it.
2043 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2044 @item pxa270 - again - CS0 flash - it goes in the board file.
2045 @end itemize
2047 @anchor{Translating Configuration Files}
2048 @section Translating Configuration Files
2049 @cindex translation
2050 If you have a configuration file for another hardware debugger
2051 or toolset (Abatron, BDI2000, BDI3000, CCS,
2052 Lauterbach, Segger, Macraigor, etc.), translating
2053 it into OpenOCD syntax is often quite straightforward. The most tricky
2054 part of creating a configuration script is oftentimes the reset init
2055 sequence where e.g. PLLs, DRAM and the like is set up.
2057 One trick that you can use when translating is to write small
2058 Tcl procedures to translate the syntax into OpenOCD syntax. This
2059 can avoid manual translation errors and make it easier to
2060 convert other scripts later on.
2062 Example of transforming quirky arguments to a simple search and
2063 replace job:
2065 @example
2066 # Lauterbach syntax(?)
2067 #
2068 # Data.Set c15:0x042f %long 0x40000015
2069 #
2070 # OpenOCD syntax when using procedure below.
2071 #
2072 # setc15 0x01 0x00050078
2074 proc setc15 @{regs value@} @{
2075 global TARGETNAME
2077 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2079 arm mcr 15 [expr ($regs>>12)&0x7] \
2080 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2081 [expr ($regs>>8)&0x7] $value
2082 @}
2083 @end example
2087 @node Daemon Configuration
2088 @chapter Daemon Configuration
2089 @cindex initialization
2090 The commands here are commonly found in the openocd.cfg file and are
2091 used to specify what TCP/IP ports are used, and how GDB should be
2092 supported.
2094 @anchor{Configuration Stage}
2095 @section Configuration Stage
2096 @cindex configuration stage
2097 @cindex config command
2099 When the OpenOCD server process starts up, it enters a
2100 @emph{configuration stage} which is the only time that
2101 certain commands, @emph{configuration commands}, may be issued.
2102 Normally, configuration commands are only available
2103 inside startup scripts.
2105 In this manual, the definition of a configuration command is
2106 presented as a @emph{Config Command}, not as a @emph{Command}
2107 which may be issued interactively.
2108 The runtime @command{help} command also highlights configuration
2109 commands, and those which may be issued at any time.
2111 Those configuration commands include declaration of TAPs,
2112 flash banks,
2113 the interface used for JTAG communication,
2114 and other basic setup.
2115 The server must leave the configuration stage before it
2116 may access or activate TAPs.
2117 After it leaves this stage, configuration commands may no
2118 longer be issued.
2120 @anchor{Entering the Run Stage}
2121 @section Entering the Run Stage
2123 The first thing OpenOCD does after leaving the configuration
2124 stage is to verify that it can talk to the scan chain
2125 (list of TAPs) which has been configured.
2126 It will warn if it doesn't find TAPs it expects to find,
2127 or finds TAPs that aren't supposed to be there.
2128 You should see no errors at this point.
2129 If you see errors, resolve them by correcting the
2130 commands you used to configure the server.
2131 Common errors include using an initial JTAG speed that's too
2132 fast, and not providing the right IDCODE values for the TAPs
2133 on the scan chain.
2135 Once OpenOCD has entered the run stage, a number of commands
2136 become available.
2137 A number of these relate to the debug targets you may have declared.
2138 For example, the @command{mww} command will not be available until
2139 a target has been successfuly instantiated.
2140 If you want to use those commands, you may need to force
2141 entry to the run stage.
2143 @deffn {Config Command} init
2144 This command terminates the configuration stage and
2145 enters the run stage. This helps when you need to have
2146 the startup scripts manage tasks such as resetting the target,
2147 programming flash, etc. To reset the CPU upon startup, add "init" and
2148 "reset" at the end of the config script or at the end of the OpenOCD
2149 command line using the @option{-c} command line switch.
2151 If this command does not appear in any startup/configuration file
2152 OpenOCD executes the command for you after processing all
2153 configuration files and/or command line options.
2155 @b{NOTE:} This command normally occurs at or near the end of your
2156 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2157 targets ready. For example: If your openocd.cfg file needs to
2158 read/write memory on your target, @command{init} must occur before
2159 the memory read/write commands. This includes @command{nand probe}.
2160 @end deffn
2162 @deffn {Overridable Procedure} jtag_init
2163 This is invoked at server startup to verify that it can talk
2164 to the scan chain (list of TAPs) which has been configured.
2166 The default implementation first tries @command{jtag arp_init},
2167 which uses only a lightweight JTAG reset before examining the
2168 scan chain.
2169 If that fails, it tries again, using a harder reset
2170 from the overridable procedure @command{init_reset}.
2172 Implementations must have verified the JTAG scan chain before
2173 they return.
2174 This is done by calling @command{jtag arp_init}
2175 (or @command{jtag arp_init-reset}).
2176 @end deffn
2178 @anchor{TCP/IP Ports}
2179 @section TCP/IP Ports
2180 @cindex TCP port
2181 @cindex server
2182 @cindex port
2183 @cindex security
2184 The OpenOCD server accepts remote commands in several syntaxes.
2185 Each syntax uses a different TCP/IP port, which you may specify
2186 only during configuration (before those ports are opened).
2188 For reasons including security, you may wish to prevent remote
2189 access using one or more of these ports.
2190 In such cases, just specify the relevant port number as zero.
2191 If you disable all access through TCP/IP, you will need to
2192 use the command line @option{-pipe} option.
2194 @deffn {Command} gdb_port [number]
2195 @cindex GDB server
2196 Normally gdb listens to a TCP/IP port, but GDB can also
2197 communicate via pipes(stdin/out or named pipes). The name
2198 "gdb_port" stuck because it covers probably more than 90% of
2199 the normal use cases.
2201 No arguments reports GDB port. "pipe" means listen to stdin
2202 output to stdout, an integer is base port number, "disable"
2203 disables the gdb server.
2205 When using "pipe", also use log_output to redirect the log
2206 output to a file so as not to flood the stdin/out pipes.
2208 The -p/--pipe option is deprecated and a warning is printed
2209 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2211 Any other string is interpreted as named pipe to listen to.
2212 Output pipe is the same name as input pipe, but with 'o' appended,
2213 e.g. /var/gdb, /var/gdbo.
2215 The GDB port for the first target will be the base port, the
2216 second target will listen on gdb_port + 1, and so on.
2217 When not specified during the configuration stage,
2218 the port @var{number} defaults to 3333.
2219 @end deffn
2221 @deffn {Command} tcl_port [number]
2222 Specify or query the port used for a simplified RPC
2223 connection that can be used by clients to issue TCL commands and get the
2224 output from the Tcl engine.
2225 Intended as a machine interface.
2226 When not specified during the configuration stage,
2227 the port @var{number} defaults to 6666.
2229 @end deffn
2231 @deffn {Command} telnet_port [number]
2232 Specify or query the
2233 port on which to listen for incoming telnet connections.
2234 This port is intended for interaction with one human through TCL commands.
2235 When not specified during the configuration stage,
2236 the port @var{number} defaults to 4444.
2237 When specified as zero, this port is not activated.
2238 @end deffn
2240 @anchor{GDB Configuration}
2241 @section GDB Configuration
2242 @cindex GDB
2243 @cindex GDB configuration
2244 You can reconfigure some GDB behaviors if needed.
2245 The ones listed here are static and global.
2246 @xref{Target Configuration}, about configuring individual targets.
2247 @xref{Target Events}, about configuring target-specific event handling.
2249 @anchor{gdb_breakpoint_override}
2250 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2251 Force breakpoint type for gdb @command{break} commands.
2252 This option supports GDB GUIs which don't
2253 distinguish hard versus soft breakpoints, if the default OpenOCD and
2254 GDB behaviour is not sufficient. GDB normally uses hardware
2255 breakpoints if the memory map has been set up for flash regions.
2256 @end deffn
2258 @anchor{gdb_flash_program}
2259 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2260 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2261 vFlash packet is received.
2262 The default behaviour is @option{enable}.
2263 @end deffn
2265 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2266 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2267 requested. GDB will then know when to set hardware breakpoints, and program flash
2268 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2269 for flash programming to work.
2270 Default behaviour is @option{enable}.
2271 @xref{gdb_flash_program}.
2272 @end deffn
2274 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2275 Specifies whether data aborts cause an error to be reported
2276 by GDB memory read packets.
2277 The default behaviour is @option{disable};
2278 use @option{enable} see these errors reported.
2279 @end deffn
2281 @anchor{Event Polling}
2282 @section Event Polling
2284 Hardware debuggers are parts of asynchronous systems,
2285 where significant events can happen at any time.
2286 The OpenOCD server needs to detect some of these events,
2287 so it can report them to through TCL command line
2288 or to GDB.
2290 Examples of such events include:
2292 @itemize
2293 @item One of the targets can stop running ... maybe it triggers
2294 a code breakpoint or data watchpoint, or halts itself.
2295 @item Messages may be sent over ``debug message'' channels ... many
2296 targets support such messages sent over JTAG,
2297 for receipt by the person debugging or tools.
2298 @item Loss of power ... some adapters can detect these events.
2299 @item Resets not issued through JTAG ... such reset sources
2300 can include button presses or other system hardware, sometimes
2301 including the target itself (perhaps through a watchdog).
2302 @item Debug instrumentation sometimes supports event triggering
2303 such as ``trace buffer full'' (so it can quickly be emptied)
2304 or other signals (to correlate with code behavior).
2305 @end itemize
2307 None of those events are signaled through standard JTAG signals.
2308 However, most conventions for JTAG connectors include voltage
2309 level and system reset (SRST) signal detection.
2310 Some connectors also include instrumentation signals, which
2311 can imply events when those signals are inputs.
2313 In general, OpenOCD needs to periodically check for those events,
2314 either by looking at the status of signals on the JTAG connector
2315 or by sending synchronous ``tell me your status'' JTAG requests
2316 to the various active targets.
2317 There is a command to manage and monitor that polling,
2318 which is normally done in the background.
2320 @deffn Command poll [@option{on}|@option{off}]
2321 Poll the current target for its current state.
2322 (Also, @pxref{target curstate}.)
2323 If that target is in debug mode, architecture
2324 specific information about the current state is printed.
2325 An optional parameter
2326 allows background polling to be enabled and disabled.
2328 You could use this from the TCL command shell, or
2329 from GDB using @command{monitor poll} command.
2330 Leave background polling enabled while you're using GDB.
2331 @example
2332 > poll
2333 background polling: on
2334 target state: halted
2335 target halted in ARM state due to debug-request, \
2336 current mode: Supervisor
2337 cpsr: 0x800000d3 pc: 0x11081bfc
2338 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2339 >
2340 @end example
2341 @end deffn
2343 @node Debug Adapter Configuration
2344 @chapter Debug Adapter Configuration
2345 @cindex config file, interface
2346 @cindex interface config file
2348 Correctly installing OpenOCD includes making your operating system give
2349 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2350 are used to select which one is used, and to configure how it is used.
2352 @quotation Note
2353 Because OpenOCD started out with a focus purely on JTAG, you may find
2354 places where it wrongly presumes JTAG is the only transport protocol
2355 in use. Be aware that recent versions of OpenOCD are removing that
2356 limitation. JTAG remains more functional than most other transports.
2357 Other transports do not support boundary scan operations, or may be
2358 specific to a given chip vendor. Some might be usable only for
2359 programming flash memory, instead of also for debugging.
2360 @end quotation
2362 Debug Adapters/Interfaces/Dongles are normally configured
2363 through commands in an interface configuration
2364 file which is sourced by your @file{openocd.cfg} file, or
2365 through a command line @option{-f interface/....cfg} option.
2367 @example
2368 source [find interface/olimex-jtag-tiny.cfg]
2369 @end example
2371 These commands tell
2372 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2373 A few cases are so simple that you only need to say what driver to use:
2375 @example
2376 # jlink interface
2377 interface jlink
2378 @end example
2380 Most adapters need a bit more configuration than that.
2383 @section Interface Configuration
2385 The interface command tells OpenOCD what type of debug adapter you are
2386 using. Depending on the type of adapter, you may need to use one or
2387 more additional commands to further identify or configure the adapter.
2389 @deffn {Config Command} {interface} name
2390 Use the interface driver @var{name} to connect to the
2391 target.
2392 @end deffn
2394 @deffn Command {interface_list}
2395 List the debug adapter drivers that have been built into
2396 the running copy of OpenOCD.
2397 @end deffn
2398 @deffn Command {interface transports} transport_name+
2399 Specifies the transports supported by this debug adapter.
2400 The adapter driver builds-in similar knowledge; use this only
2401 when external configuration (such as jumpering) changes what
2402 the hardware can support.
2403 @end deffn
2407 @deffn Command {adapter_name}
2408 Returns the name of the debug adapter driver being used.
2409 @end deffn
2411 @section Interface Drivers
2413 Each of the interface drivers listed here must be explicitly
2414 enabled when OpenOCD is configured, in order to be made
2415 available at run time.
2417 @deffn {Interface Driver} {amt_jtagaccel}
2418 Amontec Chameleon in its JTAG Accelerator configuration,
2419 connected to a PC's EPP mode parallel port.
2420 This defines some driver-specific commands:
2422 @deffn {Config Command} {parport_port} number
2423 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2424 the number of the @file{/dev/parport} device.
2425 @end deffn
2427 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2428 Displays status of RTCK option.
2429 Optionally sets that option first.
2430 @end deffn
2431 @end deffn
2433 @deffn {Interface Driver} {arm-jtag-ew}
2434 Olimex ARM-JTAG-EW USB adapter
2435 This has one driver-specific command:
2437 @deffn Command {armjtagew_info}
2438 Logs some status
2439 @end deffn
2440 @end deffn
2442 @deffn {Interface Driver} {at91rm9200}
2443 Supports bitbanged JTAG from the local system,
2444 presuming that system is an Atmel AT91rm9200
2445 and a specific set of GPIOs is used.
2446 @c command: at91rm9200_device NAME
2447 @c chooses among list of bit configs ... only one option
2448 @end deffn
2450 @deffn {Interface Driver} {dummy}
2451 A dummy software-only driver for debugging.
2452 @end deffn
2454 @deffn {Interface Driver} {ep93xx}
2455 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2456 @end deffn
2458 @deffn {Interface Driver} {ft2232}
2459 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2460 These interfaces have several commands, used to configure the driver
2461 before initializing the JTAG scan chain:
2463 @deffn {Config Command} {ft2232_device_desc} description
2464 Provides the USB device description (the @emph{iProduct string})
2465 of the FTDI FT2232 device. If not
2466 specified, the FTDI default value is used. This setting is only valid
2467 if compiled with FTD2XX support.
2468 @end deffn
2470 @deffn {Config Command} {ft2232_serial} serial-number
2471 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2472 in case the vendor provides unique IDs and more than one FT2232 device
2473 is connected to the host.
2474 If not specified, serial numbers are not considered.
2475 (Note that USB serial numbers can be arbitrary Unicode strings,
2476 and are not restricted to containing only decimal digits.)
2477 @end deffn
2479 @deffn {Config Command} {ft2232_layout} name
2480 Each vendor's FT2232 device can use different GPIO signals
2481 to control output-enables, reset signals, and LEDs.
2482 Currently valid layout @var{name} values include:
2483 @itemize @minus
2484 @item @b{axm0432_jtag} Axiom AXM-0432
2485 @item @b{comstick} Hitex STR9 comstick
2486 @item @b{cortino} Hitex Cortino JTAG interface
2487 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
2488 either for the local Cortex-M3 (SRST only)
2489 or in a passthrough mode (neither SRST nor TRST)
2490 This layout can not support the SWO trace mechanism, and should be
2491 used only for older boards (before rev C).
2492 @item @b{luminary_icdi} This layout should be used with most Luminary
2493 eval boards, including Rev C LM3S811 eval boards and the eponymous
2494 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2495 to debug some other target. It can support the SWO trace mechanism.
2496 @item @b{flyswatter} Tin Can Tools Flyswatter
2497 @item @b{icebear} ICEbear JTAG adapter from Section 5
2498 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2499 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2500 @item @b{m5960} American Microsystems M5960
2501 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2502 @item @b{oocdlink} OOCDLink
2503 @c oocdlink ~= jtagkey_prototype_v1
2504 @item @b{redbee-econotag} Integrated with a Redbee development board.
2505 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2506 @item @b{sheevaplug} Marvell Sheevaplug development kit
2507 @item @b{signalyzer} Xverve Signalyzer
2508 @item @b{stm32stick} Hitex STM32 Performance Stick
2509 @item @b{turtelizer2} egnite Software turtelizer2
2510 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2511 @end itemize
2512 @end deffn
2514 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2515 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2516 default values are used.
2517 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2518 @example
2519 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2520 @end example
2521 @end deffn
2523 @deffn {Config Command} {ft2232_latency} ms
2524 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2525 ft2232_read() fails to return the expected number of bytes. This can be caused by
2526 USB communication delays and has proved hard to reproduce and debug. Setting the
2527 FT2232 latency timer to a larger value increases delays for short USB packets but it
2528 also reduces the risk of timeouts before receiving the expected number of bytes.
2529 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2530 @end deffn
2532 For example, the interface config file for a
2533 Turtelizer JTAG Adapter looks something like this:
2535 @example
2536 interface ft2232
2537 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2538 ft2232_layout turtelizer2
2539 ft2232_vid_pid 0x0403 0xbdc8
2540 @end example
2541 @end deffn
2543 @deffn {Interface Driver} {remote_bitbang}
2544 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2545 with a remote process and sends ASCII encoded bitbang requests to that process
2546 instead of directly driving JTAG.
2548 The remote_bitbang driver is useful for debugging software running on
2549 processors which are being simulated.
2551 @deffn {Config Command} {remote_bitbang_port} number
2552 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2553 sockets instead of TCP.
2554 @end deffn
2556 @deffn {Config Command} {remote_bitbang_host} hostname
2557 Specifies the hostname of the remote process to connect to using TCP, or the
2558 name of the UNIX socket to use if remote_bitbang_port is 0.
2559 @end deffn
2561 For example, to connect remotely via TCP to the host foobar you might have
2562 something like:
2564 @example
2565 interface remote_bitbang
2566 remote_bitbang_port 3335
2567 remote_bitbang_host foobar
2568 @end example
2570 To connect to another process running locally via UNIX sockets with socket
2571 named mysocket:
2573 @example
2574 interface remote_bitbang
2575 remote_bitbang_port 0
2576 remote_bitbang_host mysocket
2577 @end example
2578 @end deffn
2580 @deffn {Interface Driver} {usb_blaster}
2581 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2582 for FTDI chips. These interfaces have several commands, used to
2583 configure the driver before initializing the JTAG scan chain:
2585 @deffn {Config Command} {usb_blaster_device_desc} description
2586 Provides the USB device description (the @emph{iProduct string})
2587 of the FTDI FT245 device. If not
2588 specified, the FTDI default value is used. This setting is only valid
2589 if compiled with FTD2XX support.
2590 @end deffn
2592 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2593 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2594 default values are used.
2595 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2596 Altera USB-Blaster (default):
2597 @example
2598 usb_blaster_vid_pid 0x09FB 0x6001
2599 @end example
2600 The following VID/PID is for Kolja Waschk's USB JTAG:
2601 @example
2602 usb_blaster_vid_pid 0x16C0 0x06AD
2603 @end example
2604 @end deffn
2606 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2607 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2608 female JTAG header). These pins can be used as SRST and/or TRST provided the
2609 appropriate connections are made on the target board.
2611 For example, to use pin 6 as SRST (as with an AVR board):
2612 @example
2613 $_TARGETNAME configure -event reset-assert \
2614 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2615 @end example
2616 @end deffn
2618 @end deffn
2620 @deffn {Interface Driver} {gw16012}
2621 Gateworks GW16012 JTAG programmer.
2622 This has one driver-specific command:
2624 @deffn {Config Command} {parport_port} [port_number]
2625 Display either the address of the I/O port
2626 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2627 If a parameter is provided, first switch to use that port.
2628 This is a write-once setting.
2629 @end deffn
2630 @end deffn
2632 @deffn {Interface Driver} {jlink}
2633 Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
2635 @quotation Compatibility Note
2636 Segger released many firmware versions for the many harware versions they
2637 produced. OpenOCD was extensively tested and intended to run on all of them,
2638 but some combinations were reported as incompatible. As a general
2639 recommendation, it is advisable to use the latest firmware version
2640 available for each hardware version. However the current V8 is a moving
2641 target, and Segger firmware versions released after the OpenOCD was
2642 released may not be compatible. In such cases it is recommended to
2643 revert to the last known functional version. For 0.5.0, this is from
2644 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2645 version is from "May 3 2012 18:36:22", packed with 4.46f.
2646 @end quotation
2648 @deffn {Command} {jlink caps}
2649 Display the device firmware capabilities.
2650 @end deffn
2651 @deffn {Command} {jlink info}
2652 Display various device information, like hardware version, firmware version, current bus status.
2653 @end deffn
2654 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2655 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2656 @end deffn
2657 @deffn {Command} {jlink config}
2658 Display the J-Link configuration.
2659 @end deffn
2660 @deffn {Command} {jlink config kickstart} [val]
2661 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2662 @end deffn
2663 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2664 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2665 @end deffn
2666 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2667 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2668 E the bit of the subnet mask and
2669 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2670 @end deffn
2671 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2672 Set the USB address; this will also change the product id. Without argument, show the USB address.
2673 @end deffn
2674 @deffn {Command} {jlink config reset}
2675 Reset the current configuration.
2676 @end deffn
2677 @deffn {Command} {jlink config save}
2678 Save the current configuration to the internal persistent storage.
2679 @end deffn
2680 @deffn {Config} {jlink pid} val
2681 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2682 @end deffn
2683 @end deffn
2685 @deffn {Interface Driver} {parport}
2686 Supports PC parallel port bit-banging cables:
2687 Wigglers, PLD download cable, and more.
2688 These interfaces have several commands, used to configure the driver
2689 before initializing the JTAG scan chain:
2691 @deffn {Config Command} {parport_cable} name
2692 Set the layout of the parallel port cable used to connect to the target.
2693 This is a write-once setting.
2694 Currently valid cable @var{name} values include:
2696 @itemize @minus
2697 @item @b{altium} Altium Universal JTAG cable.
2698 @item @b{arm-jtag} Same as original wiggler except SRST and
2699 TRST connections reversed and TRST is also inverted.
2700 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2701 in configuration mode. This is only used to
2702 program the Chameleon itself, not a connected target.
2703 @item @b{dlc5} The Xilinx Parallel cable III.
2704 @item @b{flashlink} The ST Parallel cable.
2705 @item @b{lattice} Lattice ispDOWNLOAD Cable
2706 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2707 some versions of
2708 Amontec's Chameleon Programmer. The new version available from
2709 the website uses the original Wiggler layout ('@var{wiggler}')
2710 @item @b{triton} The parallel port adapter found on the
2711 ``Karo Triton 1 Development Board''.
2712 This is also the layout used by the HollyGates design
2713 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2714 @item @b{wiggler} The original Wiggler layout, also supported by
2715 several clones, such as the Olimex ARM-JTAG
2716 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2717 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2718 @end itemize
2719 @end deffn
2721 @deffn {Config Command} {parport_port} [port_number]
2722 Display either the address of the I/O port
2723 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2724 If a parameter is provided, first switch to use that port.
2725 This is a write-once setting.
2727 When using PPDEV to access the parallel port, use the number of the parallel port:
2728 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2729 you may encounter a problem.
2730 @end deffn
2732 @deffn Command {parport_toggling_time} [nanoseconds]
2733 Displays how many nanoseconds the hardware needs to toggle TCK;
2734 the parport driver uses this value to obey the
2735 @command{adapter_khz} configuration.
2736 When the optional @var{nanoseconds} parameter is given,
2737 that setting is changed before displaying the current value.
2739 The default setting should work reasonably well on commodity PC hardware.
2740 However, you may want to calibrate for your specific hardware.
2741 @quotation Tip
2742 To measure the toggling time with a logic analyzer or a digital storage
2743 oscilloscope, follow the procedure below:
2744 @example
2745 > parport_toggling_time 1000
2746 > adapter_khz 500
2747 @end example
2748 This sets the maximum JTAG clock speed of the hardware, but
2749 the actual speed probably deviates from the requested 500 kHz.
2750 Now, measure the time between the two closest spaced TCK transitions.
2751 You can use @command{runtest 1000} or something similar to generate a
2752 large set of samples.
2753 Update the setting to match your measurement:
2754 @example
2755 > parport_toggling_time <measured nanoseconds>
2756 @end example
2757 Now the clock speed will be a better match for @command{adapter_khz rate}
2758 commands given in OpenOCD scripts and event handlers.
2760 You can do something similar with many digital multimeters, but note
2761 that you'll probably need to run the clock continuously for several
2762 seconds before it decides what clock rate to show. Adjust the
2763 toggling time up or down until the measured clock rate is a good
2764 match for the adapter_khz rate you specified; be conservative.
2765 @end quotation
2766 @end deffn
2768 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2769 This will configure the parallel driver to write a known
2770 cable-specific value to the parallel interface on exiting OpenOCD.
2771 @end deffn
2773 For example, the interface configuration file for a
2774 classic ``Wiggler'' cable on LPT2 might look something like this:
2776 @example
2777 interface parport
2778 parport_port 0x278
2779 parport_cable wiggler
2780 @end example
2781 @end deffn
2783 @deffn {Interface Driver} {presto}
2784 ASIX PRESTO USB JTAG programmer.
2785 @deffn {Config Command} {presto_serial} serial_string
2786 Configures the USB serial number of the Presto device to use.
2787 @end deffn
2788 @end deffn
2790 @deffn {Interface Driver} {rlink}
2791 Raisonance RLink USB adapter
2792 @end deffn
2794 @deffn {Interface Driver} {usbprog}
2795 usbprog is a freely programmable USB adapter.
2796 @end deffn
2798 @deffn {Interface Driver} {vsllink}
2799 vsllink is part of Versaloon which is a versatile USB programmer.
2801 @quotation Note
2802 This defines quite a few driver-specific commands,
2803 which are not currently documented here.
2804 @end quotation
2805 @end deffn
2807 @deffn {Interface Driver} {stlink}
2808 ST Micro ST-LINK adapter.
2810 @deffn {Config Command} {stlink_device_desc} description
2811 Currently Not Supported.
2812 @end deffn
2814 @deffn {Config Command} {stlink_serial} serial
2815 Currently Not Supported.
2816 @end deffn
2818 @deffn {Config Command} {stlink_layout} (@option{sg}|@option{usb})
2819 Specifies the stlink layout to use.
2820 @end deffn
2822 @deffn {Config Command} {stlink_vid_pid} vid pid
2823 The vendor ID and product ID of the STLINK device.
2824 @end deffn
2826 @deffn {Config Command} {stlink_api} api_level
2827 Manually sets the stlink api used, valid options are 1 or 2.
2828 @end deffn
2829 @end deffn
2831 @deffn {Interface Driver} {opendous}
2832 opendous-jtag is a freely programmable USB adapter.
2833 @end deffn
2835 @deffn {Interface Driver} {ulink}
2836 This is the Keil ULINK v1 JTAG debugger.
2837 @end deffn
2839 @deffn {Interface Driver} {ZY1000}
2840 This is the Zylin ZY1000 JTAG debugger.
2841 @end deffn
2843 @quotation Note
2844 This defines some driver-specific commands,
2845 which are not currently documented here.
2846 @end quotation
2848 @deffn Command power [@option{on}|@option{off}]
2849 Turn power switch to target on/off.
2850 No arguments: print status.
2851 @end deffn
2853 @section Transport Configuration
2854 @cindex Transport
2855 As noted earlier, depending on the version of OpenOCD you use,
2856 and the debug adapter you are using,
2857 several transports may be available to
2858 communicate with debug targets (or perhaps to program flash memory).
2859 @deffn Command {transport list}
2860 displays the names of the transports supported by this
2861 version of OpenOCD.
2862 @end deffn
2864 @deffn Command {transport select} transport_name
2865 Select which of the supported transports to use in this OpenOCD session.
2866 The transport must be supported by the debug adapter hardware and by the
2867 version of OPenOCD you are using (including the adapter's driver).
2868 No arguments: returns name of session's selected transport.
2869 @end deffn
2871 @subsection JTAG Transport
2872 @cindex JTAG
2873 JTAG is the original transport supported by OpenOCD, and most
2874 of the OpenOCD commands support it.
2875 JTAG transports expose a chain of one or more Test Access Points (TAPs),
2876 each of which must be explicitly declared.
2877 JTAG supports both debugging and boundary scan testing.
2878 Flash programming support is built on top of debug support.
2879 @subsection SWD Transport
2880 @cindex SWD
2881 @cindex Serial Wire Debug
2882 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
2883 Debug Access Point (DAP, which must be explicitly declared.
2884 (SWD uses fewer signal wires than JTAG.)
2885 SWD is debug-oriented, and does not support boundary scan testing.
2886 Flash programming support is built on top of debug support.
2887 (Some processors support both JTAG and SWD.)
2888 @deffn Command {swd newdap} ...
2889 Declares a single DAP which uses SWD transport.
2890 Parameters are currently the same as "jtag newtap" but this is
2891 expected to change.
2892 @end deffn
2893 @deffn Command {swd wcr trn prescale}
2894 Updates TRN (turnaraound delay) and prescaling.fields of the
2895 Wire Control Register (WCR).
2896 No parameters: displays current settings.
2897 @end deffn
2899 @subsection SPI Transport
2900 @cindex SPI
2901 @cindex Serial Peripheral Interface
2902 The Serial Peripheral Interface (SPI) is a general purpose transport
2903 which uses four wire signaling. Some processors use it as part of a
2904 solution for flash programming.
2906 @anchor{JTAG Speed}
2907 @section JTAG Speed
2908 JTAG clock setup is part of system setup.
2909 It @emph{does not belong with interface setup} since any interface
2910 only knows a few of the constraints for the JTAG clock speed.
2911 Sometimes the JTAG speed is
2912 changed during the target initialization process: (1) slow at
2913 reset, (2) program the CPU clocks, (3) run fast.
2914 Both the "slow" and "fast" clock rates are functions of the
2915 oscillators used, the chip, the board design, and sometimes
2916 power management software that may be active.
2918 The speed used during reset, and the scan chain verification which
2919 follows reset, can be adjusted using a @code{reset-start}
2920 target event handler.
2921 It can then be reconfigured to a faster speed by a
2922 @code{reset-init} target event handler after it reprograms those
2923 CPU clocks, or manually (if something else, such as a boot loader,
2924 sets up those clocks).
2925 @xref{Target Events}.
2926 When the initial low JTAG speed is a chip characteristic, perhaps
2927 because of a required oscillator speed, provide such a handler
2928 in the target config file.
2929 When that speed is a function of a board-specific characteristic
2930 such as which speed oscillator is used, it belongs in the board
2931 config file instead.
2932 In both cases it's safest to also set the initial JTAG clock rate
2933 to that same slow speed, so that OpenOCD never starts up using a
2934 clock speed that's faster than the scan chain can support.
2936 @example
2937 jtag_rclk 3000
2938 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
2939 @end example
2941 If your system supports adaptive clocking (RTCK), configuring
2942 JTAG to use that is probably the most robust approach.
2943 However, it introduces delays to synchronize clocks; so it
2944 may not be the fastest solution.
2946 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
2947 instead of @command{adapter_khz}, but only for (ARM) cores and boards
2948 which support adaptive clocking.
2950 @deffn {Command} adapter_khz max_speed_kHz
2951 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
2952 JTAG interfaces usually support a limited number of
2953 speeds. The speed actually used won't be faster
2954 than the speed specified.
2956 Chip data sheets generally include a top JTAG clock rate.
2957 The actual rate is often a function of a CPU core clock,
2958 and is normally less than that peak rate.
2959 For example, most ARM cores accept at most one sixth of the CPU clock.
2961 Speed 0 (khz) selects RTCK method.
2962 @xref{FAQ RTCK}.
2963 If your system uses RTCK, you won't need to change the
2964 JTAG clocking after setup.
2965 Not all interfaces, boards, or targets support ``rtck''.
2966 If the interface device can not
2967 support it, an error is returned when you try to use RTCK.
2968 @end deffn
2970 @defun jtag_rclk fallback_speed_kHz
2971 @cindex adaptive clocking
2972 @cindex RTCK
2973 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
2974 If that fails (maybe the interface, board, or target doesn't
2975 support it), falls back to the specified frequency.
2976 @example
2977 # Fall back to 3mhz if RTCK is not supported
2978 jtag_rclk 3000
2979 @end example
2980 @end defun
2982 @node Reset Configuration
2983 @chapter Reset Configuration
2984 @cindex Reset Configuration
2986 Every system configuration may require a different reset
2987 configuration. This can also be quite confusing.
2988 Resets also interact with @var{reset-init} event handlers,
2989 which do things like setting up clocks and DRAM, and
2990 JTAG clock rates. (@xref{JTAG Speed}.)
2991 They can also interact with JTAG routers.
2992 Please see the various board files for examples.
2994 @quotation Note
2995 To maintainers and integrators:
2996 Reset configuration touches several things at once.
2997 Normally the board configuration file
2998 should define it and assume that the JTAG adapter supports
2999 everything that's wired up to the board's JTAG connector.
3001 However, the target configuration file could also make note
3002 of something the silicon vendor has done inside the chip,
3003 which will be true for most (or all) boards using that chip.
3004 And when the JTAG adapter doesn't support everything, the
3005 user configuration file will need to override parts of
3006 the reset configuration provided by other files.
3007 @end quotation
3009 @section Types of Reset
3011 There are many kinds of reset possible through JTAG, but
3012 they may not all work with a given board and adapter.
3013 That's part of why reset configuration can be error prone.
3015 @itemize @bullet
3016 @item
3017 @emph{System Reset} ... the @emph{SRST} hardware signal
3018 resets all chips connected to the JTAG adapter, such as processors,
3019 power management chips, and I/O controllers. Normally resets triggered
3020 with this signal behave exactly like pressing a RESET button.
3021 @item
3022 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3023 just the TAP controllers connected to the JTAG adapter.
3024 Such resets should not be visible to the rest of the system; resetting a
3025 device's TAP controller just puts that controller into a known state.
3026 @item
3027 @emph{Emulation Reset} ... many devices can be reset through JTAG
3028 commands. These resets are often distinguishable from system
3029 resets, either explicitly (a "reset reason" register says so)
3030 or implicitly (not all parts of the chip get reset).
3031 @item
3032 @emph{Other Resets} ... system-on-chip devices often support
3033 several other types of reset.
3034 You may need to arrange that a watchdog timer stops
3035 while debugging, preventing a watchdog reset.
3036 There may be individual module resets.
3037 @end itemize
3039 In the best case, OpenOCD can hold SRST, then reset
3040 the TAPs via TRST and send commands through JTAG to halt the
3041 CPU at the reset vector before the 1st instruction is executed.
3042 Then when it finally releases the SRST signal, the system is
3043 halted under debugger control before any code has executed.
3044 This is the behavior required to support the @command{reset halt}
3045 and @command{reset init} commands; after @command{reset init} a
3046 board-specific script might do things like setting up DRAM.
3047 (@xref{Reset Command}.)
3049 @anchor{SRST and TRST Issues}
3050 @section SRST and TRST Issues
3052 Because SRST and TRST are hardware signals, they can have a
3053 variety of system-specific constraints. Some of the most
3054 common issues are:
3056 @itemize @bullet
3058 @item @emph{Signal not available} ... Some boards don't wire
3059 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3060 support such signals even if they are wired up.
3061 Use the @command{reset_config} @var{signals} options to say
3062 when either of those signals is not connected.
3063 When SRST is not available, your code might not be able to rely
3064 on controllers having been fully reset during code startup.
3065 Missing TRST is not a problem, since JTAG-level resets can
3066 be triggered using with TMS signaling.
3068 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3069 adapter will connect SRST to TRST, instead of keeping them separate.
3070 Use the @command{reset_config} @var{combination} options to say
3071 when those signals aren't properly independent.
3073 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3074 delay circuit, reset supervisor, or on-chip features can extend
3075 the effect of a JTAG adapter's reset for some time after the adapter
3076 stops issuing the reset. For example, there may be chip or board
3077 requirements that all reset pulses last for at least a
3078 certain amount of time; and reset buttons commonly have
3079 hardware debouncing.
3080 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3081 commands to say when extra delays are needed.
3083 @item @emph{Drive type} ... Reset lines often have a pullup
3084 resistor, letting the JTAG interface treat them as open-drain
3085 signals. But that's not a requirement, so the adapter may need
3086 to use push/pull output drivers.
3087 Also, with weak pullups it may be advisable to drive
3088 signals to both levels (push/pull) to minimize rise times.
3089 Use the @command{reset_config} @var{trst_type} and
3090 @var{srst_type} parameters to say how to drive reset signals.
3092 @item @emph{Special initialization} ... Targets sometimes need
3093 special JTAG initialization sequences to handle chip-specific
3094 issues (not limited to errata).
3095 For example, certain JTAG commands might need to be issued while
3096 the system as a whole is in a reset state (SRST active)
3097 but the JTAG scan chain is usable (TRST inactive).
3098 Many systems treat combined assertion of SRST and TRST as a
3099 trigger for a harder reset than SRST alone.
3100 Such custom reset handling is discussed later in this chapter.
3101 @end itemize
3103 There can also be other issues.
3104 Some devices don't fully conform to the JTAG specifications.
3105 Trivial system-specific differences are common, such as
3106 SRST and TRST using slightly different names.
3107 There are also vendors who distribute key JTAG documentation for
3108 their chips only to developers who have signed a Non-Disclosure
3109 Agreement (NDA).
3111 Sometimes there are chip-specific extensions like a requirement to use
3112 the normally-optional TRST signal (precluding use of JTAG adapters which
3113 don't pass TRST through), or needing extra steps to complete a TAP reset.
3115 In short, SRST and especially TRST handling may be very finicky,
3116 needing to cope with both architecture and board specific constraints.
3118 @section Commands for Handling Resets
3120 @deffn {Command} adapter_nsrst_assert_width milliseconds
3121 Minimum amount of time (in milliseconds) OpenOCD should wait
3122 after asserting nSRST (active-low system reset) before
3123 allowing it to be deasserted.
3124 @end deffn
3126 @deffn {Command} adapter_nsrst_delay milliseconds
3127 How long (in milliseconds) OpenOCD should wait after deasserting
3128 nSRST (active-low system reset) before starting new JTAG operations.
3129 When a board has a reset button connected to SRST line it will
3130 probably have hardware debouncing, implying you should use this.
3131 @end deffn
3133 @deffn {Command} jtag_ntrst_assert_width milliseconds
3134 Minimum amount of time (in milliseconds) OpenOCD should wait
3135 after asserting nTRST (active-low JTAG TAP reset) before
3136 allowing it to be deasserted.
3137 @end deffn
3139 @deffn {Command} jtag_ntrst_delay milliseconds
3140 How long (in milliseconds) OpenOCD should wait after deasserting
3141 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3142 @end deffn
3144 @deffn {Command} reset_config mode_flag ...
3145 This command displays or modifies the reset configuration
3146 of your combination of JTAG board and target in target
3147 configuration scripts.
3149 Information earlier in this section describes the kind of problems
3150 the command is intended to address (@pxref{SRST and TRST Issues}).
3151 As a rule this command belongs only in board config files,
3152 describing issues like @emph{board doesn't connect TRST};
3153 or in user config files, addressing limitations derived
3154 from a particular combination of interface and board.
3155 (An unlikely example would be using a TRST-only adapter
3156 with a board that only wires up SRST.)
3158 The @var{mode_flag} options can be specified in any order, but only one
3159 of each type -- @var{signals}, @var{combination}, @var{gates},
3160 @var{trst_type}, @var{srst_type} and @var{connect_type}
3161 -- may be specified at a time.
3162 If you don't provide a new value for a given type, its previous
3163 value (perhaps the default) is unchanged.
3164 For example, this means that you don't need to say anything at all about
3165 TRST just to declare that if the JTAG adapter should want to drive SRST,
3166 it must explicitly be driven high (@option{srst_push_pull}).
3168 @itemize
3169 @item
3170 @var{signals} can specify which of the reset signals are connected.
3171 For example, If the JTAG interface provides SRST, but the board doesn't
3172 connect that signal properly, then OpenOCD can't use it.
3173 Possible values are @option{none} (the default), @option{trst_only},
3174 @option{srst_only} and @option{trst_and_srst}.
3176 @quotation Tip
3177 If your board provides SRST and/or TRST through the JTAG connector,
3178 you must declare that so those signals can be used.
3179 @end quotation
3181 @item
3182 The @var{combination} is an optional value specifying broken reset
3183 signal implementations.
3184 The default behaviour if no option given is @option{separate},
3185 indicating everything behaves normally.
3186 @option{srst_pulls_trst} states that the
3187 test logic is reset together with the reset of the system (e.g. NXP
3188 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3189 the system is reset together with the test logic (only hypothetical, I
3190 haven't seen hardware with such a bug, and can be worked around).
3191 @option{combined} implies both @option{srst_pulls_trst} and
3192 @option{trst_pulls_srst}.
3194 @item
3195 The @var{gates} tokens control flags that describe some cases where
3196 JTAG may be unvailable during reset.
3197 @option{srst_gates_jtag} (default)
3198 indicates that asserting SRST gates the
3199 JTAG clock. This means that no communication can happen on JTAG
3200 while SRST is asserted.
3201 Its converse is @option{srst_nogate}, indicating that JTAG commands
3202 can safely be issued while SRST is active.
3204 @item
3205 The @var{connect_type} tokens control flags that describe some cases where
3206 SRST is asserted while connecting to the target. @option{srst_nogate}
3207 is required to use this option.
3208 @option{connect_deassert_srst} (default)
3209 indicates that SRST will not be asserted while connecting to the target.
3210 Its converse is @option{connect_assert_srst}, indicating that SRST will
3211 be asserted before any target connection.
3212 Only some targets support this feature, STM32 and STR9 are examples.
3213 This feature is useful if you are unable to connect to your target due
3214 to incorrect options byte config or illegal program execution.
3215 @end itemize
3217 The optional @var{trst_type} and @var{srst_type} parameters allow the
3218 driver mode of each reset line to be specified. These values only affect
3219 JTAG interfaces with support for different driver modes, like the Amontec
3220 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3221 relevant signal (TRST or SRST) is not connected.
3223 @itemize
3224 @item
3225 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3226 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3227 Most boards connect this signal to a pulldown, so the JTAG TAPs
3228 never leave reset unless they are hooked up to a JTAG adapter.
3230 @item
3231 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3232 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3233 Most boards connect this signal to a pullup, and allow the
3234 signal to be pulled low by various events including system
3235 powerup and pressing a reset button.
3236 @end itemize
3237 @end deffn
3239 @section Custom Reset Handling
3240 @cindex events
3242 OpenOCD has several ways to help support the various reset
3243 mechanisms provided by chip and board vendors.
3244 The commands shown in the previous section give standard parameters.
3245 There are also @emph{event handlers} associated with TAPs or Targets.
3246 Those handlers are Tcl procedures you can provide, which are invoked
3247 at particular points in the reset sequence.
3249 @emph{When SRST is not an option} you must set
3250 up a @code{reset-assert} event handler for your target.
3251 For example, some JTAG adapters don't include the SRST signal;
3252 and some boards have multiple targets, and you won't always
3253 want to reset everything at once.
3255 After configuring those mechanisms, you might still
3256 find your board doesn't start up or reset correctly.
3257 For example, maybe it needs a slightly different sequence
3258 of SRST and/or TRST manipulations, because of quirks that
3259 the @command{reset_config} mechanism doesn't address;
3260 or asserting both might trigger a stronger reset, which
3261 needs special attention.
3263 Experiment with lower level operations, such as @command{jtag_reset}
3264 and the @command{jtag arp_*} operations shown here,
3265 to find a sequence of operations that works.
3266 @xref{JTAG Commands}.
3267 When you find a working sequence, it can be used to override
3268 @command{jtag_init}, which fires during OpenOCD startup
3269 (@pxref{Configuration Stage});
3270 or @command{init_reset}, which fires during reset processing.
3272 You might also want to provide some project-specific reset
3273 schemes. For example, on a multi-target board the standard
3274 @command{reset} command would reset all targets, but you
3275 may need the ability to reset only one target at time and
3276 thus want to avoid using the board-wide SRST signal.
3278 @deffn {Overridable Procedure} init_reset mode
3279 This is invoked near the beginning of the @command{reset} command,
3280 usually to provide as much of a cold (power-up) reset as practical.
3281 By default it is also invoked from @command{jtag_init} if
3282 the scan chain does not respond to pure JTAG operations.
3283 The @var{mode} parameter is the parameter given to the
3284 low level reset command (@option{halt},
3285 @option{init}, or @option{run}), @option{setup},
3286 or potentially some other value.
3288 The default implementation just invokes @command{jtag arp_init-reset}.
3289 Replacements will normally build on low level JTAG
3290 operations such as @command{jtag_reset}.
3291 Operations here must not address individual TAPs
3292 (or their associated targets)
3293 until the JTAG scan chain has first been verified to work.
3295 Implementations must have verified the JTAG scan chain before
3296 they return.
3297 This is done by calling @command{jtag arp_init}
3298 (or @command{jtag arp_init-reset}).
3299 @end deffn
3301 @deffn Command {jtag arp_init}
3302 This validates the scan chain using just the four
3303 standard JTAG signals (TMS, TCK, TDI, TDO).
3304 It starts by issuing a JTAG-only reset.
3305 Then it performs checks to verify that the scan chain configuration
3306 matches the TAPs it can observe.
3307 Those checks include checking IDCODE values for each active TAP,
3308 and verifying the length of their instruction registers using
3309 TAP @code{-ircapture} and @code{-irmask} values.
3310 If these tests all pass, TAP @code{setup} events are
3311 issued to all TAPs with handlers for that event.
3312 @end deffn
3314 @deffn Command {jtag arp_init-reset}
3315 This uses TRST and SRST to try resetting
3316 everything on the JTAG scan chain
3317 (and anything else connected to SRST).
3318 It then invokes the logic of @command{jtag arp_init}.
3319 @end deffn
3322 @node TAP Declaration
3323 @chapter TAP Declaration
3324 @cindex TAP declaration
3325 @cindex TAP configuration
3327 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3328 TAPs serve many roles, including:
3330 @itemize @bullet
3331 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
3332 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
3333 Others do it indirectly, making a CPU do it.
3334 @item @b{Program Download} Using the same CPU support GDB uses,
3335 you can initialize a DRAM controller, download code to DRAM, and then
3336 start running that code.
3337 @item @b{Boundary Scan} Most chips support boundary scan, which
3338 helps test for board assembly problems like solder bridges
3339 and missing connections
3340 @end itemize
3342 OpenOCD must know about the active TAPs on your board(s).
3343 Setting up the TAPs is the core task of your configuration files.
3344 Once those TAPs are set up, you can pass their names to code
3345 which sets up CPUs and exports them as GDB targets,
3346 probes flash memory, performs low-level JTAG operations, and more.
3348 @section Scan Chains
3349 @cindex scan chain
3351 TAPs are part of a hardware @dfn{scan chain},
3352 which is daisy chain of TAPs.
3353 They also need to be added to
3354 OpenOCD's software mirror of that hardware list,
3355 giving each member a name and associating other data with it.
3356 Simple scan chains, with a single TAP, are common in
3357 systems with a single microcontroller or microprocessor.
3358 More complex chips may have several TAPs internally.
3359 Very complex scan chains might have a dozen or more TAPs:
3360 several in one chip, more in the next, and connecting
3361 to other boards with their own chips and TAPs.
3363 You can display the list with the @command{scan_chain} command.
3364 (Don't confuse this with the list displayed by the @command{targets}
3365 command, presented in the next chapter.
3366 That only displays TAPs for CPUs which are configured as
3367 debugging targets.)
3368 Here's what the scan chain might look like for a chip more than one TAP:
3370 @verbatim
3371 TapName Enabled IdCode Expected IrLen IrCap IrMask
3372 -- ------------------ ------- ---------- ---------- ----- ----- ------
3373 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3374 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3375 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3376 @end verbatim
3378 OpenOCD can detect some of that information, but not all
3379 of it. @xref{Autoprobing}.
3380 Unfortunately those TAPs can't always be autoconfigured,
3381 because not all devices provide good support for that.
3382 JTAG doesn't require supporting IDCODE instructions, and
3383 chips with JTAG routers may not link TAPs into the chain
3384 until they are told to do so.
3386 The configuration mechanism currently supported by OpenOCD
3387 requires explicit configuration of all TAP devices using
3388 @command{jtag newtap} commands, as detailed later in this chapter.
3389 A command like this would declare one tap and name it @code{chip1.cpu}:
3391 @example
3392 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3393 @end example
3395 Each target configuration file lists the TAPs provided
3396 by a given chip.
3397 Board configuration files combine all the targets on a board,
3398 and so forth.
3399 Note that @emph{the order in which TAPs are declared is very important.}
3400 It must match the order in the JTAG scan chain, both inside
3401 a single chip and between them.
3402 @xref{FAQ TAP Order}.
3404 For example, the ST Microsystems STR912 chip has
3405 three separate TAPs@footnote{See the ST
3406 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3407 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3408 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3409 To configure those taps, @file{target/str912.cfg}
3410 includes commands something like this:
3412 @example
3413 jtag newtap str912 flash ... params ...
3414 jtag newtap str912 cpu ... params ...
3415 jtag newtap str912 bs ... params ...
3416 @end example
3418 Actual config files use a variable instead of literals like
3419 @option{str912}, to support more than one chip of each type.
3420 @xref{Config File Guidelines}.
3422 @deffn Command {jtag names}
3423 Returns the names of all current TAPs in the scan chain.
3424 Use @command{jtag cget} or @command{jtag tapisenabled}
3425 to examine attributes and state of each TAP.
3426 @example
3427 foreach t [jtag names] @{
3428 puts [format "TAP: %s\n" $t]
3429 @}
3430 @end example
3431 @end deffn
3433 @deffn Command {scan_chain}
3434 Displays the TAPs in the scan chain configuration,
3435 and their status.
3436 The set of TAPs listed by this command is fixed by
3437 exiting the OpenOCD configuration stage,
3438 but systems with a JTAG router can
3439 enable or disable TAPs dynamically.
3440 @end deffn
3442 @c FIXME! "jtag cget" should be able to return all TAP
3443 @c attributes, like "$target_name cget" does for targets.
3445 @c Probably want "jtag eventlist", and a "tap-reset" event
3446 @c (on entry to RESET state).
3448 @section TAP Names
3449 @cindex dotted name
3451 When TAP objects are declared with @command{jtag newtap},
3452 a @dfn{dotted.name} is created for the TAP, combining the
3453 name of a module (usually a chip) and a label for the TAP.
3454 For example: @code{xilinx.tap}, @code{str912.flash},
3455 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3456 Many other commands use that dotted.name to manipulate or
3457 refer to the TAP. For example, CPU configuration uses the
3458 name, as does declaration of NAND or NOR flash banks.
3460 The components of a dotted name should follow ``C'' symbol
3461 name rules: start with an alphabetic character, then numbers
3462 and underscores are OK; while others (including dots!) are not.
3464 @quotation Tip
3465 In older code, JTAG TAPs were numbered from 0..N.
3466 This feature is still present.
3467 However its use is highly discouraged, and
3468 should not be relied on; it will be removed by mid-2010.
3469 Update all of your scripts to use TAP names rather than numbers,
3470 by paying attention to the runtime warnings they trigger.
3471 Using TAP numbers in target configuration scripts prevents
3472 reusing those scripts on boards with multiple targets.
3473 @end quotation
3475 @section TAP Declaration Commands
3477 @c shouldn't this be(come) a {Config Command}?
3478 @anchor{jtag newtap}
3479 @deffn Command {jtag newtap} chipname tapname configparams...
3480 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3481 and configured according to the various @var{configparams}.
3483 The @var{chipname} is a symbolic name for the chip.
3484 Conventionally target config files use @code{$_CHIPNAME},
3485 defaulting to the model name given by the chip vendor but
3486 overridable.
3488 @cindex TAP naming convention
3489 The @var{tapname} reflects the role of that TAP,
3490 and should follow this convention:
3492 @itemize @bullet
3493 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3494 @item @code{cpu} -- The main CPU of the chip, alternatively
3495 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3496 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3497 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3498 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3499 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3500 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3501 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3502 with a single TAP;
3503 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3504 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3505 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3506 a JTAG TAP; that TAP should be named @code{sdma}.
3507 @end itemize
3509 Every TAP requires at least the following @var{configparams}:
3511 @itemize @bullet
3512 @item @code{-irlen} @var{NUMBER}
3513 @*The length in bits of the
3514 instruction register, such as 4 or 5 bits.
3515 @end itemize
3517 A TAP may also provide optional @var{configparams}:
3519 @itemize @bullet
3520 @item @code{-disable} (or @code{-enable})
3521 @*Use the @code{-disable} parameter to flag a TAP which is not
3522 linked in to the scan chain after a reset using either TRST
3523 or the JTAG state machine's @sc{reset} state.
3524 You may use @code{-enable} to highlight the default state
3525 (the TAP is linked in).
3526 @xref{Enabling and Disabling TAPs}.
3527 @item @code{-expected-id} @var{number}
3528 @*A non-zero @var{number} represents a 32-bit IDCODE
3529 which you expect to find when the scan chain is examined.
3530 These codes are not required by all JTAG devices.
3531 @emph{Repeat the option} as many times as required if more than one
3532 ID code could appear (for example, multiple versions).
3533 Specify @var{number} as zero to suppress warnings about IDCODE
3534 values that were found but not included in the list.
3536 Provide this value if at all possible, since it lets OpenOCD
3537 tell when the scan chain it sees isn't right. These values
3538 are provided in vendors' chip documentation, usually a technical
3539 reference manual. Sometimes you may need to probe the JTAG
3540 hardware to find these values.
3541 @xref{Autoprobing}.
3542 @item @code{-ignore-version}
3543 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3544 option. When vendors put out multiple versions of a chip, or use the same
3545 JTAG-level ID for several largely-compatible chips, it may be more practical
3546 to ignore the version field than to update config files to handle all of
3547 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3548 @item @code{-ircapture} @var{NUMBER}
3549 @*The bit pattern loaded by the TAP into the JTAG shift register
3550 on entry to the @sc{ircapture} state, such as 0x01.
3551 JTAG requires the two LSBs of this value to be 01.
3552 By default, @code{-ircapture} and @code{-irmask} are set
3553 up to verify that two-bit value. You may provide
3554 additional bits, if you know them, or indicate that
3555 a TAP doesn't conform to the JTAG specification.
3556 @item @code{-irmask} @var{NUMBER}
3557 @*A mask used with @code{-ircapture}
3558 to verify that instruction scans work correctly.
3559 Such scans are not used by OpenOCD except to verify that
3560 there seems to be no problems with JTAG scan chain operations.
3561 @end itemize
3562 @end deffn
3564 @section Other TAP commands
3566 @deffn Command {jtag cget} dotted.name @option{-event} name
3567 @deffnx Command {jtag configure} dotted.name @option{-event} name string
3568 At this writing this TAP attribute
3569 mechanism is used only for event handling.
3570 (It is not a direct analogue of the @code{cget}/@code{configure}
3571 mechanism for debugger targets.)
3572 See the next section for information about the available events.
3574 The @code{configure} subcommand assigns an event handler,
3575 a TCL string which is evaluated when the event is triggered.
3576 The @code{cget} subcommand returns that handler.
3577 @end deffn
3579 @anchor{TAP Events}
3580 @section TAP Events
3581 @cindex events
3582 @cindex TAP events
3584 OpenOCD includes two event mechanisms.
3585 The one presented here applies to all JTAG TAPs.
3586 The other applies to debugger targets,
3587 which are associated with certain TAPs.
3589 The TAP events currently defined are:
3591 @itemize @bullet
3592 @item @b{post-reset}
3593 @* The TAP has just completed a JTAG reset.
3594 The tap may still be in the JTAG @sc{reset} state.
3595 Handlers for these events might perform initialization sequences
3596 such as issuing TCK cycles, TMS sequences to ensure
3597 exit from the ARM SWD mode, and more.
3599 Because the scan chain has not yet been verified, handlers for these events
3600 @emph{should not issue commands which scan the JTAG IR or DR registers}
3601 of any particular target.
3602 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3603 @item @b{setup}
3604 @* The scan chain has been reset and verified.
3605 This handler may enable TAPs as needed.
3606 @item @b{tap-disable}
3607 @* The TAP needs to be disabled. This handler should
3608 implement @command{jtag tapdisable}
3609 by issuing the relevant JTAG commands.
3610 @item @b{tap-enable}
3611 @* The TAP needs to be enabled. This handler should
3612 implement @command{jtag tapenable}
3613 by issuing the relevant JTAG commands.
3614 @end itemize
3616 If you need some action after each JTAG reset, which isn't actually
3617 specific to any TAP (since you can't yet trust the scan chain's
3618 contents to be accurate), you might:
3620 @example
3621 jtag configure CHIP.jrc -event post-reset @{
3622 echo "JTAG Reset done"
3623 ... non-scan jtag operations to be done after reset
3624 @}
3625 @end example
3628 @anchor{Enabling and Disabling TAPs}
3629 @section Enabling and Disabling TAPs
3630 @cindex JTAG Route Controller
3631 @cindex jrc
3633 In some systems, a @dfn{JTAG Route Controller} (JRC)
3634 is used to enable and/or disable specific JTAG TAPs.
3635 Many ARM based chips from Texas Instruments include
3636 an ``ICEpick'' module, which is a JRC.
3637 Such chips include DaVinci and OMAP3 processors.
3639 A given TAP may not be visible until the JRC has been
3640 told to link it into the scan chain; and if the JRC
3641 has been told to unlink that TAP, it will no longer
3642 be visible.
3643 Such routers address problems that JTAG ``bypass mode''
3644 ignores, such as:
3646 @itemize
3647 @item The scan chain can only go as fast as its slowest TAP.
3648 @item Having many TAPs slows instruction scans, since all
3649 TAPs receive new instructions.
3650 @item TAPs in the scan chain must be powered up, which wastes
3651 power and prevents debugging some power management mechanisms.
3652 @end itemize
3654 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3655 as implied by the existence of JTAG routers.
3656 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3657 does include a kind of JTAG router functionality.
3659 @c (a) currently the event handlers don't seem to be able to
3660 @c fail in a way that could lead to no-change-of-state.
3662 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3663 shown below, and is implemented using TAP event handlers.
3664 So for example, when defining a TAP for a CPU connected to
3665 a JTAG router, your @file{target.cfg} file
3666 should define TAP event handlers using
3667 code that looks something like this:
3669 @example
3670 jtag configure CHIP.cpu -event tap-enable @{
3671 ... jtag operations using CHIP.jrc
3672 @}
3673 jtag configure CHIP.cpu -event tap-disable @{
3674 ... jtag operations using CHIP.jrc
3675 @}
3676 @end example
3678 Then you might want that CPU's TAP enabled almost all the time:
3680 @example
3681 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3682 @end example
3684 Note how that particular setup event handler declaration
3685 uses quotes to evaluate @code{$CHIP} when the event is configured.
3686 Using brackets @{ @} would cause it to be evaluated later,
3687 at runtime, when it might have a different value.
3689 @deffn Command {jtag tapdisable} dotted.name
3690 If necessary, disables the tap
3691 by sending it a @option{tap-disable} event.
3692 Returns the string "1" if the tap
3693 specified by @var{dotted.name} is enabled,
3694 and "0" if it is disabled.
3695 @end deffn
3697 @deffn Command {jtag tapenable} dotted.name
3698 If necessary, enables the tap
3699 by sending it a @option{tap-enable} event.
3700 Returns the string "1" if the tap
3701 specified by @var{dotted.name} is enabled,
3702 and "0" if it is disabled.
3703 @end deffn
3705 @deffn Command {jtag tapisenabled} dotted.name
3706 Returns the string "1" if the tap
3707 specified by @var{dotted.name} is enabled,
3708 and "0" if it is disabled.
3710 @quotation Note
3711 Humans will find the @command{scan_chain} command more helpful
3712 for querying the state of the JTAG taps.
3713 @end quotation
3714 @end deffn
3716 @anchor{Autoprobing}
3717 @section Autoprobing
3718 @cindex autoprobe
3719 @cindex JTAG autoprobe
3721 TAP configuration is the first thing that needs to be done
3722 after interface and reset configuration. Sometimes it's
3723 hard finding out what TAPs exist, or how they are identified.
3724 Vendor documentation is not always easy to find and use.
3726 To help you get past such problems, OpenOCD has a limited
3727 @emph{autoprobing} ability to look at the scan chain, doing
3728 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3729 To use this mechanism, start the OpenOCD server with only data
3730 that configures your JTAG interface, and arranges to come up
3731 with a slow clock (many devices don't support fast JTAG clocks
3732 right when they come out of reset).
3734 For example, your @file{openocd.cfg} file might have:
3736 @example
3737 source [find interface/olimex-arm-usb-tiny-h.cfg]
3738 reset_config trst_and_srst
3739 jtag_rclk 8
3740 @end example
3742 When you start the server without any TAPs configured, it will
3743 attempt to autoconfigure the TAPs. There are two parts to this:
3745 @enumerate
3746 @item @emph{TAP discovery} ...
3747 After a JTAG reset (sometimes a system reset may be needed too),
3748 each TAP's data registers will hold the contents of either the
3749 IDCODE or BYPASS register.
3750 If JTAG communication is working, OpenOCD will see each TAP,
3751 and report what @option{-expected-id} to use with it.
3752 @item @emph{IR Length discovery} ...
3753 Unfortunately JTAG does not provide a reliable way to find out
3754 the value of the @option{-irlen} parameter to use with a TAP
3755 that is discovered.
3756 If OpenOCD can discover the length of a TAP's instruction
3757 register, it will report it.
3758 Otherwise you may need to consult vendor documentation, such
3759 as chip data sheets or BSDL files.
3760 @end enumerate
3762 In many cases your board will have a simple scan chain with just
3763 a single device. Here's what OpenOCD reported with one board
3764 that's a bit more complex:
3766 @example
3767 clock speed 8 kHz
3768 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3769 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3770 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3771 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3772 AUTO auto0.tap - use "... -irlen 4"
3773 AUTO auto1.tap - use "... -irlen 4"
3774 AUTO auto2.tap - use "... -irlen 6"
3775 no gdb ports allocated as no target has been specified
3776 @end example
3778 Given that information, you should be able to either find some existing
3779 config files to use, or create your own. If you create your own, you
3780 would configure from the bottom up: first a @file{target.cfg} file
3781 with these TAPs, any targets associated with them, and any on-chip
3782 resources; then a @file{board.cfg} with off-chip resources, clocking,
3783 and so forth.
3785 @node CPU Configuration
3786 @chapter CPU Configuration
3787 @cindex GDB target
3789 This chapter discusses how to set up GDB debug targets for CPUs.
3790 You can also access these targets without GDB
3791 (@pxref{Architecture and Core Commands},
3792 and @ref{Target State handling}) and
3793 through various kinds of NAND and NOR flash commands.
3794 If you have multiple CPUs you can have multiple such targets.
3796 We'll start by looking at how to examine the targets you have,
3797 then look at how to add one more target and how to configure it.
3799 @section Target List
3800 @cindex target, current
3801 @cindex target, list
3803 All targets that have been set up are part of a list,
3804 where each member has a name.
3805 That name should normally be the same as the TAP name.
3806 You can display the list with the @command{targets}
3807 (plural!) command.
3808 This display often has only one CPU; here's what it might
3809 look like with more than one:
3810 @verbatim
3811 TargetName Type Endian TapName State
3812 -- ------------------ ---------- ------ ------------------ ------------
3813 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
3814 1 MyTarget cortex_m3 little mychip.foo tap-disabled
3815 @end verbatim
3817 One member of that list is the @dfn{current target}, which
3818 is implicitly referenced by many commands.
3819 It's the one marked with a @code{*} near the target name.
3820 In particular, memory addresses often refer to the address
3821 space seen by that current target.
3822 Commands like @command{mdw} (memory display words)
3823 and @command{flash erase_address} (erase NOR flash blocks)
3824 are examples; and there are many more.
3826 Several commands let you examine the list of targets:
3828 @deffn Command {target count}
3829 @emph{Note: target numbers are deprecated; don't use them.
3830 They will be removed shortly after August 2010, including this command.
3831 Iterate target using @command{target names}, not by counting.}
3833 Returns the number of targets, @math{N}.
3834 The highest numbered target is @math{N - 1}.
3835 @example
3836 set c [target count]
3837 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
3838 # Assuming you have created this function
3839 print_target_details $x
3840 @}
3841 @end example
3842 @end deffn
3844 @deffn Command {target current}
3845 Returns the name of the current target.
3846 @end deffn
3848 @deffn Command {target names}
3849 Lists the names of all current targets in the list.
3850 @example
3851 foreach t [target names] @{
3852 puts [format "Target: %s\n" $t]
3853 @}
3854 @end example
3855 @end deffn
3857 @deffn Command {target number} number
3858 @emph{Note: target numbers are deprecated; don't use them.
3859 They will be removed shortly after August 2010, including this command.}
3861 The list of targets is numbered starting at zero.
3862 This command returns the name of the target at index @var{number}.
3863 @example
3864 set thename [target number $x]
3865 puts [format "Target %d is: %s\n" $x $thename]
3866 @end example
3867 @end deffn
3869 @c yep, "target list" would have been better.
3870 @c plus maybe "target setdefault".
3872 @deffn Command targets [name]
3873 @emph{Note: the name of this command is plural. Other target
3874 command names are singular.}
3876 With no parameter, this command displays a table of all known
3877 targets in a user friendly form.
3879 With a parameter, this command sets the current target to
3880 the given target with the given @var{name}; this is
3881 only relevant on boards which have more than one target.
3882 @end deffn
3884 @section Target CPU Types and Variants
3885 @cindex target type
3886 @cindex CPU type
3887 @cindex CPU variant
3889 Each target has a @dfn{CPU type}, as shown in the output of
3890 the @command{targets} command. You need to specify that type
3891 when calling @command{target create}.
3892 The CPU type indicates more than just the instruction set.
3893 It also indicates how that instruction set is implemented,
3894 what kind of debug support it integrates,
3895 whether it has an MMU (and if so, what kind),
3896 what core-specific commands may be available
3897 (@pxref{Architecture and Core Commands}),
3898 and more.
3900 For some CPU types, OpenOCD also defines @dfn{variants} which
3901 indicate differences that affect their handling.
3902 For example, a particular implementation bug might need to be
3903 worked around in some chip versions.
3905 It's easy to see what target types are supported,
3906 since there's a command to list them.
3907 However, there is currently no way to list what target variants
3908 are supported (other than by reading the OpenOCD source code).
3910 @anchor{target types}
3911 @deffn Command {target types}
3912 Lists all supported target types.
3913 At this writing, the supported CPU types and variants are:
3915 @itemize @bullet
3916 @item @code{arm11} -- this is a generation of ARMv6 cores
3917 @item @code{arm720t} -- this is an ARMv4 core with an MMU
3918 @item @code{arm7tdmi} -- this is an ARMv4 core
3919 @item @code{arm920t} -- this is an ARMv4 core with an MMU
3920 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
3921 @item @code{arm966e} -- this is an ARMv5 core
3922 @item @code{arm9tdmi} -- this is an ARMv4 core
3923 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
3924 (Support for this is preliminary and incomplete.)
3925 @item @code{cortex_a8} -- this is an ARMv7 core with an MMU
3926 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
3927 compact Thumb2 instruction set.
3928 @item @code{dragonite} -- resembles arm966e
3929 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
3930 (Support for this is still incomplete.)
3931 @item @code{fa526} -- resembles arm920 (w/o Thumb)
3932 @item @code{feroceon} -- resembles arm926
3933 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
3934 @item @code{xscale} -- this is actually an architecture,
3935 not a CPU type. It is based on the ARMv5 architecture.
3936 There are several variants defined:
3937 @itemize @minus
3938 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
3939 @code{pxa27x} ... instruction register length is 7 bits
3940 @item @code{pxa250}, @code{pxa255},
3941 @code{pxa26x} ... instruction register length is 5 bits
3942 @item @code{pxa3xx} ... instruction register length is 11 bits
3943 @end itemize
3944 @end itemize
3945 @end deffn
3947 To avoid being confused by the variety of ARM based cores, remember
3948 this key point: @emph{ARM is a technology licencing company}.
3949 (See: @url{http://www.arm.com}.)
3950 The CPU name used by OpenOCD will reflect the CPU design that was
3951 licenced, not a vendor brand which incorporates that design.
3952 Name prefixes like arm7, arm9, arm11, and cortex
3953 reflect design generations;
3954 while names like ARMv4, ARMv5, ARMv6, and ARMv7
3955 reflect an architecture version implemented by a CPU design.
3957 @anchor{Target Configuration}
3958 @section Target Configuration
3960 Before creating a ``target'', you must have added its TAP to the scan chain.
3961 When you've added that TAP, you will have a @code{dotted.name}
3962 which is used to set up the CPU support.
3963 The chip-specific configuration file will normally configure its CPU(s)
3964 right after it adds all of the chip's TAPs to the scan chain.
3966 Although you can set up a target in one step, it's often clearer if you
3967 use shorter commands and do it in two steps: create it, then configure
3968 optional parts.
3969 All operations on the target after it's created will use a new
3970 command, created as part of target creation.
3972 The two main things to configure after target creation are
3973 a work area, which usually has target-specific defaults even
3974 if the board setup code overrides them later;
3975 and event handlers (@pxref{Target Events}), which tend
3976 to be much more board-specific.
3977 The key steps you use might look something like this
3979 @example
3980 target create MyTarget cortex_m3 -chain-position mychip.cpu
3981 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
3982 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
3983 $MyTarget configure -event reset-init @{ myboard_reinit @}
3984 @end example
3986 You should specify a working area if you can; typically it uses some
3987 on-chip SRAM.
3988 Such a working area can speed up many things, including bulk
3989 writes to target memory;
3990 flash operations like checking to see if memory needs to be erased;
3991 GDB memory checksumming;
3992 and more.
3994 @quotation Warning
3995 On more complex chips, the work area can become
3996 inaccessible when application code
3997 (such as an operating system)
3998 enables or disables the MMU.
3999 For example, the particular MMU context used to acess the virtual
4000 address will probably matter ... and that context might not have
4001 easy access to other addresses needed.
4002 At this writing, OpenOCD doesn't have much MMU intelligence.
4003 @end quotation
4005 It's often very useful to define a @code{reset-init} event handler.
4006 For systems that are normally used with a boot loader,
4007 common tasks include updating clocks and initializing memory
4008 controllers.
4009 That may be needed to let you write the boot loader into flash,
4010 in order to ``de-brick'' your board; or to load programs into
4011 external DDR memory without having run the boot loader.
4013 @deffn Command {target create} target_name type configparams...
4014 This command creates a GDB debug target that refers to a specific JTAG tap.
4015 It enters that target into a list, and creates a new
4016 command (@command{@var{target_name}}) which is used for various
4017 purposes including additional configuration.
4019 @itemize @bullet
4020 @item @var{target_name} ... is the name of the debug target.
4021 By convention this should be the same as the @emph{dotted.name}
4022 of the TAP associated with this target, which must be specified here
4023 using the @code{-chain-position @var{dotted.name}} configparam.
4025 This name is also used to create the target object command,
4026 referred to here as @command{$target_name},
4027 and in other places the target needs to be identified.
4028 @item @var{type} ... specifies the target type. @xref{target types}.
4029 @item @var{configparams} ... all parameters accepted by
4030 @command{$target_name configure} are permitted.
4031 If the target is big-endian, set it here with @code{-endian big}.
4032 If the variant matters, set it here with @code{-variant}.
4034 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
4035 @end itemize
4036 @end deffn
4038 @deffn Command {$target_name configure} configparams...
4039 The options accepted by this command may also be
4040 specified as parameters to @command{target create}.
4041 Their values can later be queried one at a time by
4042 using the @command{$target_name cget} command.
4044 @emph{Warning:} changing some of these after setup is dangerous.
4045 For example, moving a target from one TAP to another;
4046 and changing its endianness or variant.
4048 @itemize @bullet
4050 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4051 used to access this target.
4053 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4054 whether the CPU uses big or little endian conventions
4056 @item @code{-event} @var{event_name} @var{event_body} --
4057 @xref{Target Events}.
4058 Note that this updates a list of named event handlers.
4059 Calling this twice with two different event names assigns
4060 two different handlers, but calling it twice with the
4061 same event name assigns only one handler.
4063 @item @code{-variant} @var{name} -- specifies a variant of the target,
4064 which OpenOCD needs to know about.
4066 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4067 whether the work area gets backed up; by default,
4068 @emph{it is not backed up.}
4069 When possible, use a working_area that doesn't need to be backed up,
4070 since performing a backup slows down operations.
4071 For example, the beginning of an SRAM block is likely to
4072 be used by most build systems, but the end is often unused.
4074 @item @code{-work-area-size} @var{size} -- specify work are size,
4075 in bytes. The same size applies regardless of whether its physical
4076 or virtual address is being used.
4078 @item @code{-work-area-phys} @var{address} -- set the work area
4079 base @var{address} to be used when no MMU is active.
4081 @item @code{-work-area-virt} @var{address} -- set the work area
4082 base @var{address} to be used when an MMU is active.
4083 @emph{Do not specify a value for this except on targets with an MMU.}
4084 The value should normally correspond to a static mapping for the
4085 @code{-work-area-phys} address, set up by the current operating system.
4087 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4088 @var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}|
4089 @option{FreeRTOS}|@option{linux}|@option{ChibiOS}.
4091 @end itemize
4092 @end deffn
4094 @section Other $target_name Commands
4095 @cindex object command
4097 The Tcl/Tk language has the concept of object commands,
4098 and OpenOCD adopts that same model for targets.
4100 A good Tk example is a on screen button.
4101 Once a button is created a button
4102 has a name (a path in Tk terms) and that name is useable as a first
4103 class command. For example in Tk, one can create a button and later
4104 configure it like this:
4106 @example
4107 # Create
4108 button .foobar -background red -command @{ foo @}
4109 # Modify
4110 .foobar configure -foreground blue
4111 # Query
4112 set x [.foobar cget -background]
4113 # Report
4114 puts [format "The button is %s" $x]
4115 @end example
4117 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4118 button, and its object commands are invoked the same way.
4120 @example
4121 str912.cpu mww 0x1234 0x42
4122 omap3530.cpu mww 0x5555 123
4123 @end example
4125 The commands supported by OpenOCD target objects are:
4127 @deffn Command {$target_name arp_examine}
4128 @deffnx Command {$target_name arp_halt}
4129 @deffnx Command {$target_name arp_poll}
4130 @deffnx Command {$target_name arp_reset}
4131 @deffnx Command {$target_name arp_waitstate}
4132 Internal OpenOCD scripts (most notably @file{startup.tcl})
4133 use these to deal with specific reset cases.
4134 They are not otherwise documented here.
4135 @end deffn
4137 @deffn Command {$target_name array2mem} arrayname width address count
4138 @deffnx Command {$target_name mem2array} arrayname width address count
4139 These provide an efficient script-oriented interface to memory.
4140 The @code{array2mem} primitive writes bytes, halfwords, or words;
4141 while @code{mem2array} reads them.
4142 In both cases, the TCL side uses an array, and
4143 the target side uses raw memory.
4145 The efficiency comes from enabling the use of
4146 bulk JTAG data transfer operations.
4147 The script orientation comes from working with data
4148 values that are packaged for use by TCL scripts;
4149 @command{mdw} type primitives only print data they retrieve,
4150 and neither store nor return those values.
4152 @itemize
4153 @item @var{arrayname} ... is the name of an array variable
4154 @item @var{width} ... is 8/16/32 - indicating the memory access size
4155 @item @var{address} ... is the target memory address
4156 @item @var{count} ... is the number of elements to process
4157 @end itemize
4158 @end deffn
4160 @deffn Command {$target_name cget} queryparm
4161 Each configuration parameter accepted by
4162 @command{$target_name configure}
4163 can be individually queried, to return its current value.
4164 The @var{queryparm} is a parameter name
4165 accepted by that command, such as @code{-work-area-phys}.
4166 There are a few special cases:
4168 @itemize @bullet
4169 @item @code{-event} @var{event_name} -- returns the handler for the
4170 event named @var{event_name}.
4171 This is a special case because setting a handler requires
4172 two parameters.
4173 @item @code{-type} -- returns the target type.
4174 This is a special case because this is set using
4175 @command{target create} and can't be changed
4176 using @command{$target_name configure}.
4177 @end itemize
4179 For example, if you wanted to summarize information about
4180 all the targets you might use something like this: