Change most in-tree references from SVN to GIT.
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
11
12 @include version.texi
13
14 @copying
15
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
20
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009 David Brownell
27 @end itemize
28
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
38
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
45
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
50
51 @summarycontents
52 @contents
53
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
57
58 @insertcopying
59 @end ifnottex
60
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developers
64 * JTAG Hardware Dongles:: JTAG Hardware Dongles
65 * About JIM-Tcl:: About JIM-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Interface - Dongle Configuration:: Interface - Dongle Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * TFTP:: TFTP
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * Upgrading:: Deprecated/Removed Commands
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
88
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
95 @end menu
96
97 @node About
98 @unnumbered About
99 @cindex about
100
101 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
102 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
105 around the world.
106
107 @section What is OpenOCD?
108 @cindex TAP
109 @cindex JTAG
110
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
113 devices.
114
115 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
116 with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
117 A @dfn{TAP} is a ``Test Access Port'', a module which processes
118 special instructions and data. TAPs are daisy-chained within and
119 between chips and boards.
120
121 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
122 based, parallel port based, and other standalone boxes that run
123 OpenOCD internally. @xref{JTAG Hardware Dongles}.
124
125 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
126 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
127 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
128 debugged via the GDB protocol.
129
130 @b{Flash Programing:} Flash writing is supported for external CFI
131 compatible NOR flashes (Intel and AMD/Spansion command set) and several
132 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
133 STM32x). Preliminary support for various NAND flash controllers
134 (LPC3180, Orion, S3C24xx, more) controller is included.
135
136 @section OpenOCD Web Site
137
138 The OpenOCD web site provides the latest public news from the community:
139
140 @uref{http://openocd.berlios.de/web/}
141
142 @section Latest User's Guide:
143
144 The user's guide you are now reading may not be the latest one
145 available. A version for more recent code may be available.
146 Its HTML form is published irregularly at:
147
148 @uref{http://openocd.berlios.de/doc/html/index.html}
149
150 PDF form is likewise published at:
151
152 @uref{http://openocd.berlios.de/doc/pdf/openocd.pdf}
153
154 @section OpenOCD User's Forum
155
156 There is an OpenOCD forum (phpBB) hosted by SparkFun:
157
158 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
159
160
161 @node Developers
162 @chapter OpenOCD Developer Resources
163 @cindex developers
164
165 If you are interested in improving the state of OpenOCD's debugging and
166 testing support, new contributions will be welcome. Motivated developers
167 can produce new target, flash or interface drivers, improve the
168 documentation, as well as more conventional bug fixes and enhancements.
169
170 The resources in this chapter are available for developers wishing to explore
171 or expand the OpenOCD source code.
172
173 @section OpenOCD GIT Repository
174
175 During the 0.3.x release cycle, OpenOCD switched from Subversion to
176 a GIT repository hosted at SourceForge. The repository URL is:
177
178 @uref{git://openocd.git.sourceforge.net/gitroot/openocd/openocd}
179
180 With standard GIT tools, use @command{git clone} to initialize
181 a local repository, and @command{git pull} to update it.
182 There are also gitweb pages letting you browse the repository
183 with a web browser, or download arbitrary snapshots without
184 needing a GIT client:
185
186 @uref{http://openocd.git.sourceforge.net/git/gitweb.cgi?p=openocd/openocd}
187
188 The @file{README} file contains the instructions for building the project
189 from the repository or a snapshot.
190
191 Developers that want to contribute patches to the OpenOCD system are
192 @b{strongly} encouraged to work against mainline.
193 Patches created against older versions may require additional
194 work from their submitter in order to be updated for newer releases.
195
196 @section Doxygen Developer Manual
197
198 During the 0.2.x release cycle, the OpenOCD project began
199 providing a Doxygen reference manual. This document contains more
200 technical information about the software internals, development
201 processes, and similar documentation:
202
203 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
204
205 This document is a work-in-progress, but contributions would be welcome
206 to fill in the gaps. All of the source files are provided in-tree,
207 listed in the Doxyfile configuration in the top of the source tree.
208
209 @section OpenOCD Developer Mailing List
210
211 The OpenOCD Developer Mailing List provides the primary means of
212 communication between developers:
213
214 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
215
216 Discuss and submit patches to this list.
217 The @file{PATCHES} file contains basic information about how
218 to prepare patches.
219
220
221 @node JTAG Hardware Dongles
222 @chapter JTAG Hardware Dongles
223 @cindex dongles
224 @cindex FTDI
225 @cindex wiggler
226 @cindex zy1000
227 @cindex printer port
228 @cindex USB Adapter
229 @cindex RTCK
230
231 Defined: @b{dongle}: A small device that plugins into a computer and serves as
232 an adapter .... [snip]
233
234 In the OpenOCD case, this generally refers to @b{a small adapater} one
235 attaches to your computer via USB or the Parallel Printer Port. The
236 execption being the Zylin ZY1000 which is a small box you attach via
237 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
238 require any drivers to be installed on the developer PC. It also has
239 a built in web interface. It supports RTCK/RCLK or adaptive clocking
240 and has a built in relay to power cycle targets remotely.
241
242
243 @section Choosing a Dongle
244
245 There are several things you should keep in mind when choosing a dongle.
246
247 @enumerate
248 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
249 Does your dongle support it? You might need a level converter.
250 @item @b{Pinout} What pinout does your target board use?
251 Does your dongle support it? You may be able to use jumper
252 wires, or an "octopus" connector, to convert pinouts.
253 @item @b{Connection} Does your computer have the USB, printer, or
254 Ethernet port needed?
255 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
256 @end enumerate
257
258 @section Stand alone Systems
259
260 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
261 dongle, but a standalone box. The ZY1000 has the advantage that it does
262 not require any drivers installed on the developer PC. It also has
263 a built in web interface. It supports RTCK/RCLK or adaptive clocking
264 and has a built in relay to power cycle targets remotely.
265
266 @section USB FT2232 Based
267
268 There are many USB JTAG dongles on the market, many of them are based
269 on a chip from ``Future Technology Devices International'' (FTDI)
270 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
271 See: @url{http://www.ftdichip.com} for more information.
272 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
273 chips are starting to become available in JTAG adapters.
274
275 @itemize @bullet
276 @item @b{usbjtag}
277 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
278 @item @b{jtagkey}
279 @* See: @url{http://www.amontec.com/jtagkey.shtml}
280 @item @b{jtagkey2}
281 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
282 @item @b{oocdlink}
283 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
284 @item @b{signalyzer}
285 @* See: @url{http://www.signalyzer.com}
286 @item @b{evb_lm3s811}
287 @* See: @url{http://www.luminarymicro.com} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
288 @item @b{luminary_icdi}
289 @* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug Interface (ICDI) Board, included in the Stellaris LM3S9B90 and LM3S9B92 Evaluation Kits.
290 @item @b{olimex-jtag}
291 @* See: @url{http://www.olimex.com}
292 @item @b{flyswatter}
293 @* See: @url{http://www.tincantools.com}
294 @item @b{turtelizer2}
295 @* See:
296 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
297 @url{http://www.ethernut.de}
298 @item @b{comstick}
299 @* Link: @url{http://www.hitex.com/index.php?id=383}
300 @item @b{stm32stick}
301 @* Link @url{http://www.hitex.com/stm32-stick}
302 @item @b{axm0432_jtag}
303 @* Axiom AXM-0432 Link @url{http://www.axman.com}
304 @item @b{cortino}
305 @* Link @url{http://www.hitex.com/index.php?id=cortino}
306 @end itemize
307
308 @section USB JLINK based
309 There are several OEM versions of the Segger @b{JLINK} adapter. It is
310 an example of a micro controller based JTAG adapter, it uses an
311 AT91SAM764 internally.
312
313 @itemize @bullet
314 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
315 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
316 @item @b{SEGGER JLINK}
317 @* Link: @url{http://www.segger.com/jlink.html}
318 @item @b{IAR J-Link}
319 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
320 @end itemize
321
322 @section USB RLINK based
323 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
324
325 @itemize @bullet
326 @item @b{Raisonance RLink}
327 @* Link: @url{http://www.raisonance.com/products/RLink.php}
328 @item @b{STM32 Primer}
329 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
330 @item @b{STM32 Primer2}
331 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
332 @end itemize
333
334 @section USB Other
335 @itemize @bullet
336 @item @b{USBprog}
337 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
338
339 @item @b{USB - Presto}
340 @* Link: @url{http://tools.asix.net/prg_presto.htm}
341
342 @item @b{Versaloon-Link}
343 @* Link: @url{http://www.simonqian.com/en/Versaloon}
344
345 @item @b{ARM-JTAG-EW}
346 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
347 @end itemize
348
349 @section IBM PC Parallel Printer Port Based
350
351 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
352 and the MacGraigor Wiggler. There are many clones and variations of
353 these on the market.
354
355 Note that parallel ports are becoming much less common, so if you
356 have the choice you should probably avoid these adapters in favor
357 of USB-based ones.
358
359 @itemize @bullet
360
361 @item @b{Wiggler} - There are many clones of this.
362 @* Link: @url{http://www.macraigor.com/wiggler.htm}
363
364 @item @b{DLC5} - From XILINX - There are many clones of this
365 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
366 produced, PDF schematics are easily found and it is easy to make.
367
368 @item @b{Amontec - JTAG Accelerator}
369 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
370
371 @item @b{GW16402}
372 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
373
374 @item @b{Wiggler2}
375 @*@uref{http://www.ccac.rwth-aachen.de/@/~michaels/@/index.php/hardware/@/armjtag,
376 Improved parallel-port wiggler-style JTAG adapter}
377
378 @item @b{Wiggler_ntrst_inverted}
379 @* Yet another variation - See the source code, src/jtag/parport.c
380
381 @item @b{old_amt_wiggler}
382 @* Unknown - probably not on the market today
383
384 @item @b{arm-jtag}
385 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
386
387 @item @b{chameleon}
388 @* Link: @url{http://www.amontec.com/chameleon.shtml}
389
390 @item @b{Triton}
391 @* Unknown.
392
393 @item @b{Lattice}
394 @* ispDownload from Lattice Semiconductor
395 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
396
397 @item @b{flashlink}
398 @* From ST Microsystems;
399 @uref{http://www.st.com/stonline/@/products/literature/um/7889.pdf,
400 FlashLINK JTAG programing cable for PSD and uPSD}
401
402 @end itemize
403
404 @section Other...
405 @itemize @bullet
406
407 @item @b{ep93xx}
408 @* An EP93xx based Linux machine using the GPIO pins directly.
409
410 @item @b{at91rm9200}
411 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
412
413 @end itemize
414
415 @node About JIM-Tcl
416 @chapter About JIM-Tcl
417 @cindex JIM Tcl
418 @cindex tcl
419
420 OpenOCD includes a small ``Tcl Interpreter'' known as JIM-Tcl.
421 This programming language provides a simple and extensible
422 command interpreter.
423
424 All commands presented in this Guide are extensions to JIM-Tcl.
425 You can use them as simple commands, without needing to learn
426 much of anything about Tcl.
427 Alternatively, can write Tcl programs with them.
428
429 You can learn more about JIM at its website, @url{http://jim.berlios.de}.
430
431 @itemize @bullet
432 @item @b{JIM vs. Tcl}
433 @* JIM-TCL is a stripped down version of the well known Tcl language,
434 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
435 fewer features. JIM-Tcl is a single .C file and a single .H file and
436 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
437 4.2 MB .zip file containing 1540 files.
438
439 @item @b{Missing Features}
440 @* Our practice has been: Add/clone the real Tcl feature if/when
441 needed. We welcome JIM Tcl improvements, not bloat.
442
443 @item @b{Scripts}
444 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
445 command interpreter today is a mixture of (newer)
446 JIM-Tcl commands, and (older) the orginal command interpreter.
447
448 @item @b{Commands}
449 @* At the OpenOCD telnet command line (or via the GDB mon command) one
450 can type a Tcl for() loop, set variables, etc.
451 Some of the commands documented in this guide are implemented
452 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
453
454 @item @b{Historical Note}
455 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
456
457 @item @b{Need a crash course in Tcl?}
458 @*@xref{Tcl Crash Course}.
459 @end itemize
460
461 @node Running
462 @chapter Running
463 @cindex command line options
464 @cindex logfile
465 @cindex directory search
466
467 The @option{--help} option shows:
468 @verbatim
469 bash$ openocd --help
470
471 --help | -h display this help
472 --version | -v display OpenOCD version
473 --file | -f use configuration file <name>
474 --search | -s dir to search for config files and scripts
475 --debug | -d set debug level <0-3>
476 --log_output | -l redirect log output to file <name>
477 --command | -c run <command>
478 --pipe | -p use pipes when talking to gdb
479 @end verbatim
480
481 By default OpenOCD reads the file configuration file @file{openocd.cfg}
482 in the current directory. To specify a different (or multiple)
483 configuration file, you can use the ``-f'' option. For example:
484
485 @example
486 openocd -f config1.cfg -f config2.cfg -f config3.cfg
487 @end example
488
489 OpenOCD starts by processing the configuration commands provided
490 on the command line or in @file{openocd.cfg}.
491 @xref{Configuration Stage}.
492 At the end of the configuration stage it verifies the JTAG scan
493 chain defined using those commands; your configuration should
494 ensure that this always succeeds.
495 Normally, OpenOCD then starts running as a daemon.
496 Alternatively, commands may be used to terminate the configuration
497 stage early, perform work (such as updating some flash memory),
498 and then shut down without acting as a daemon.
499
500 Once OpenOCD starts running as a daemon, it waits for connections from
501 clients (Telnet, GDB, Other) and processes the commands issued through
502 those channels.
503
504 If you are having problems, you can enable internal debug messages via
505 the ``-d'' option.
506
507 Also it is possible to interleave JIM-Tcl commands w/config scripts using the
508 @option{-c} command line switch.
509
510 To enable debug output (when reporting problems or working on OpenOCD
511 itself), use the @option{-d} command line switch. This sets the
512 @option{debug_level} to "3", outputting the most information,
513 including debug messages. The default setting is "2", outputting only
514 informational messages, warnings and errors. You can also change this
515 setting from within a telnet or gdb session using @command{debug_level
516 <n>} (@pxref{debug_level}).
517
518 You can redirect all output from the daemon to a file using the
519 @option{-l <logfile>} switch.
520
521 Search paths for config/script files can be added to OpenOCD by using
522 the @option{-s <search>} switch. The current directory and the OpenOCD
523 target library is in the search path by default.
524
525 For details on the @option{-p} option. @xref{Connecting to GDB}.
526
527 Note! OpenOCD will launch the GDB & telnet server even if it can not
528 establish a connection with the target. In general, it is possible for
529 the JTAG controller to be unresponsive until the target is set up
530 correctly via e.g. GDB monitor commands in a GDB init script.
531
532 @node OpenOCD Project Setup
533 @chapter OpenOCD Project Setup
534
535 To use OpenOCD with your development projects, you need to do more than
536 just connecting the JTAG adapter hardware (dongle) to your development board
537 and then starting the OpenOCD server.
538 You also need to configure that server so that it knows
539 about that adapter and board, and helps your work.
540
541 @section Hooking up the JTAG Adapter
542
543 Today's most common case is a dongle with a JTAG cable on one side
544 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
545 and a USB cable on the other.
546 Instead of USB, some cables use Ethernet;
547 older ones may use a PC parallel port, or even a serial port.
548
549 @enumerate
550 @item @emph{Start with power to your target board turned off},
551 and nothing connected to your JTAG adapter.
552 If you're particularly paranoid, unplug power to the board.
553 It's important to have the ground signal properly set up,
554 unless you are using a JTAG adapter which provides
555 galvanic isolation between the target board and the
556 debugging host.
557
558 @item @emph{Be sure it's the right kind of JTAG connector.}
559 If your dongle has a 20-pin ARM connector, you need some kind
560 of adapter (or octopus, see below) to hook it up to
561 boards using 14-pin or 10-pin connectors ... or to 20-pin
562 connectors which don't use ARM's pinout.
563
564 In the same vein, make sure the voltage levels are compatible.
565 Not all JTAG adapters have the level shifters needed to work
566 with 1.2 Volt boards.
567
568 @item @emph{Be certain the cable is properly oriented} or you might
569 damage your board. In most cases there are only two possible
570 ways to connect the cable.
571 Connect the JTAG cable from your adapter to the board.
572 Be sure it's firmly connected.
573
574 In the best case, the connector is keyed to physically
575 prevent you from inserting it wrong.
576 This is most often done using a slot on the board's male connector
577 housing, which must match a key on the JTAG cable's female connector.
578 If there's no housing, then you must look carefully and
579 make sure pin 1 on the cable hooks up to pin 1 on the board.
580 Ribbon cables are frequently all grey except for a wire on one
581 edge, which is red. The red wire is pin 1.
582
583 Sometimes dongles provide cables where one end is an ``octopus'' of
584 color coded single-wire connectors, instead of a connector block.
585 These are great when converting from one JTAG pinout to another,
586 but are tedious to set up.
587 Use these with connector pinout diagrams to help you match up the
588 adapter signals to the right board pins.
589
590 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
591 A USB, parallel, or serial port connector will go to the host which
592 you are using to run OpenOCD.
593 For Ethernet, consult the documentation and your network administrator.
594
595 For USB based JTAG adapters you have an easy sanity check at this point:
596 does the host operating system see the JTAG adapter?
597
598 @item @emph{Connect the adapter's power supply, if needed.}
599 This step is primarily for non-USB adapters,
600 but sometimes USB adapters need extra power.
601
602 @item @emph{Power up the target board.}
603 Unless you just let the magic smoke escape,
604 you're now ready to set up the OpenOCD server
605 so you can use JTAG to work with that board.
606
607 @end enumerate
608
609 Talk with the OpenOCD server using
610 telnet (@code{telnet localhost 4444} on many systems) or GDB.
611 @xref{GDB and OpenOCD}.
612
613 @section Project Directory
614
615 There are many ways you can configure OpenOCD and start it up.
616
617 A simple way to organize them all involves keeping a
618 single directory for your work with a given board.
619 When you start OpenOCD from that directory,
620 it searches there first for configuration files, scripts,
621 and for code you upload to the target board.
622 It is also the natural place to write files,
623 such as log files and data you download from the board.
624
625 @section Configuration Basics
626
627 There are two basic ways of configuring OpenOCD, and
628 a variety of ways you can mix them.
629 Think of the difference as just being how you start the server:
630
631 @itemize
632 @item Many @option{-f file} or @option{-c command} options on the command line
633 @item No options, but a @dfn{user config file}
634 in the current directory named @file{openocd.cfg}
635 @end itemize
636
637 Here is an example @file{openocd.cfg} file for a setup
638 using a Signalyzer FT2232-based JTAG adapter to talk to
639 a board with an Atmel AT91SAM7X256 microcontroller:
640
641 @example
642 source [find interface/signalyzer.cfg]
643
644 # GDB can also flash my flash!
645 gdb_memory_map enable
646 gdb_flash_program enable
647
648 source [find target/sam7x256.cfg]
649 @end example
650
651 Here is the command line equivalent of that configuration:
652
653 @example
654 openocd -f interface/signalyzer.cfg \
655 -c "gdb_memory_map enable" \
656 -c "gdb_flash_program enable" \
657 -f target/sam7x256.cfg
658 @end example
659
660 You could wrap such long command lines in shell scripts,
661 each supporting a different development task.
662 One might re-flash the board with a specific firmware version.
663 Another might set up a particular debugging or run-time environment.
664
665 @quotation Important
666 At this writing (October 2009) the command line method has
667 problems with how it treats variables.
668 For example, after @option{-c "set VAR value"}, or doing the
669 same in a script, the variable @var{VAR} will have no value
670 that can be tested in a later script.
671 @end quotation
672
673 Here we will focus on the simpler solution: one user config
674 file, including basic configuration plus any TCL procedures
675 to simplify your work.
676
677 @section User Config Files
678 @cindex config file, user
679 @cindex user config file
680 @cindex config file, overview
681
682 A user configuration file ties together all the parts of a project
683 in one place.
684 One of the following will match your situation best:
685
686 @itemize
687 @item Ideally almost everything comes from configuration files
688 provided by someone else.
689 For example, OpenOCD distributes a @file{scripts} directory
690 (probably in @file{/usr/share/openocd/scripts} on Linux).
691 Board and tool vendors can provide these too, as can individual
692 user sites; the @option{-s} command line option lets you say
693 where to find these files. (@xref{Running}.)
694 The AT91SAM7X256 example above works this way.
695
696 Three main types of non-user configuration file each have their
697 own subdirectory in the @file{scripts} directory:
698
699 @enumerate
700 @item @b{interface} -- one for each kind of JTAG adapter/dongle
701 @item @b{board} -- one for each different board
702 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
703 @end enumerate
704
705 Best case: include just two files, and they handle everything else.
706 The first is an interface config file.
707 The second is board-specific, and it sets up the JTAG TAPs and
708 their GDB targets (by deferring to some @file{target.cfg} file),
709 declares all flash memory, and leaves you nothing to do except
710 meet your deadline:
711
712 @example
713 source [find interface/olimex-jtag-tiny.cfg]
714 source [find board/csb337.cfg]
715 @end example
716
717 Boards with a single microcontroller often won't need more
718 than the target config file, as in the AT91SAM7X256 example.
719 That's because there is no external memory (flash, DDR RAM), and
720 the board differences are encapsulated by application code.
721
722 @item You can often reuse some standard config files but
723 need to write a few new ones, probably a @file{board.cfg} file.
724 You will be using commands described later in this User's Guide,
725 and working with the guidelines in the next chapter.
726
727 For example, there may be configuration files for your JTAG adapter
728 and target chip, but you need a new board-specific config file
729 giving access to your particular flash chips.
730 Or you might need to write another target chip configuration file
731 for a new chip built around the Cortex M3 core.
732
733 @quotation Note
734 When you write new configuration files, please submit
735 them for inclusion in the next OpenOCD release.
736 For example, a @file{board/newboard.cfg} file will help the
737 next users of that board, and a @file{target/newcpu.cfg}
738 will help support users of any board using that chip.
739 @end quotation
740
741 @item
742 You may may need to write some C code.
743 It may be as simple as a supporting a new ft2232 or parport
744 based dongle; a bit more involved, like a NAND or NOR flash
745 controller driver; or a big piece of work like supporting
746 a new chip architecture.
747 @end itemize
748
749 Reuse the existing config files when you can.
750 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
751 You may find a board configuration that's a good example to follow.
752
753 When you write config files, separate the reusable parts
754 (things every user of that interface, chip, or board needs)
755 from ones specific to your environment and debugging approach.
756 @itemize
757
758 @item
759 For example, a @code{gdb-attach} event handler that invokes
760 the @command{reset init} command will interfere with debugging
761 early boot code, which performs some of the same actions
762 that the @code{reset-init} event handler does.
763
764 @item
765 Likewise, the @command{arm9tdmi vector_catch} command (or
766 @cindex vector_catch
767 its siblings @command{xscale vector_catch}
768 and @command{cortex_m3 vector_catch}) can be a timesaver
769 during some debug sessions, but don't make everyone use that either.
770 Keep those kinds of debugging aids in your user config file,
771 along with messaging and tracing setup.
772 (@xref{Software Debug Messages and Tracing}.)
773
774 @item
775 You might need to override some defaults.
776 For example, you might need to move, shrink, or back up the target's
777 work area if your application needs much SRAM.
778
779 @item
780 TCP/IP port configuration is another example of something which
781 is environment-specific, and should only appear in
782 a user config file. @xref{TCP/IP Ports}.
783 @end itemize
784
785 @section Project-Specific Utilities
786
787 A few project-specific utility
788 routines may well speed up your work.
789 Write them, and keep them in your project's user config file.
790
791 For example, if you are making a boot loader work on a
792 board, it's nice to be able to debug the ``after it's
793 loaded to RAM'' parts separately from the finicky early
794 code which sets up the DDR RAM controller and clocks.
795 A script like this one, or a more GDB-aware sibling,
796 may help:
797
798 @example
799 proc ramboot @{ @} @{
800 # Reset, running the target's "reset-init" scripts
801 # to initialize clocks and the DDR RAM controller.
802 # Leave the CPU halted.
803 reset init
804
805 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
806 load_image u-boot.bin 0x20000000
807
808 # Start running.
809 resume 0x20000000
810 @}
811 @end example
812
813 Then once that code is working you will need to make it
814 boot from NOR flash; a different utility would help.
815 Alternatively, some developers write to flash using GDB.
816 (You might use a similar script if you're working with a flash
817 based microcontroller application instead of a boot loader.)
818
819 @example
820 proc newboot @{ @} @{
821 # Reset, leaving the CPU halted. The "reset-init" event
822 # proc gives faster access to the CPU and to NOR flash;
823 # "reset halt" would be slower.
824 reset init
825
826 # Write standard version of U-Boot into the first two
827 # sectors of NOR flash ... the standard version should
828 # do the same lowlevel init as "reset-init".
829 flash protect 0 0 1 off
830 flash erase_sector 0 0 1
831 flash write_bank 0 u-boot.bin 0x0
832 flash protect 0 0 1 on
833
834 # Reboot from scratch using that new boot loader.
835 reset run
836 @}
837 @end example
838
839 You may need more complicated utility procedures when booting
840 from NAND.
841 That often involves an extra bootloader stage,
842 running from on-chip SRAM to perform DDR RAM setup so it can load
843 the main bootloader code (which won't fit into that SRAM).
844
845 Other helper scripts might be used to write production system images,
846 involving considerably more than just a three stage bootloader.
847
848 @section Target Software Changes
849
850 Sometimes you may want to make some small changes to the software
851 you're developing, to help make JTAG debugging work better.
852 For example, in C or assembly language code you might
853 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
854 handling issues like:
855
856 @itemize @bullet
857
858 @item @b{ARM Wait-For-Interrupt}...
859 Many ARM chips synchronize the JTAG clock using the core clock.
860 Low power states which stop that core clock thus prevent JTAG access.
861 Idle loops in tasking environments often enter those low power states
862 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
863
864 You may want to @emph{disable that instruction} in source code,
865 or otherwise prevent using that state,
866 to ensure you can get JTAG access at any time.
867 For example, the OpenOCD @command{halt} command may not
868 work for an idle processor otherwise.
869
870 @item @b{Delay after reset}...
871 Not all chips have good support for debugger access
872 right after reset; many LPC2xxx chips have issues here.
873 Similarly, applications that reconfigure pins used for
874 JTAG access as they start will also block debugger access.
875
876 To work with boards like this, @emph{enable a short delay loop}
877 the first thing after reset, before "real" startup activities.
878 For example, one second's delay is usually more than enough
879 time for a JTAG debugger to attach, so that
880 early code execution can be debugged
881 or firmware can be replaced.
882
883 @item @b{Debug Communications Channel (DCC)}...
884 Some processors include mechanisms to send messages over JTAG.
885 Many ARM cores support these, as do some cores from other vendors.
886 (OpenOCD may be able to use this DCC internally, speeding up some
887 operations like writing to memory.)
888
889 Your application may want to deliver various debugging messages
890 over JTAG, by @emph{linking with a small library of code}
891 provided with OpenOCD and using the utilities there to send
892 various kinds of message.
893 @xref{Software Debug Messages and Tracing}.
894
895 @end itemize
896
897 @node Config File Guidelines
898 @chapter Config File Guidelines
899
900 This chapter is aimed at any user who needs to write a config file,
901 including developers and integrators of OpenOCD and any user who
902 needs to get a new board working smoothly.
903 It provides guidelines for creating those files.
904
905 You should find the following directories under @t{$(INSTALLDIR)/scripts},
906 with files including the ones listed here.
907 Use them as-is where you can; or as models for new files.
908
909 @itemize @bullet
910 @item @file{interface} ...
911 think JTAG Dongle. Files that configure JTAG adapters go here.
912 @example
913 $ ls interface
914 arm-jtag-ew.cfg hitex_str9-comstick.cfg oocdlink.cfg
915 arm-usb-ocd.cfg icebear.cfg openocd-usb.cfg
916 at91rm9200.cfg jlink.cfg parport.cfg
917 axm0432.cfg jtagkey2.cfg parport_dlc5.cfg
918 calao-usb-a9260-c01.cfg jtagkey.cfg rlink.cfg
919 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg sheevaplug.cfg
920 calao-usb-a9260.cfg luminary.cfg signalyzer.cfg
921 chameleon.cfg luminary-icdi.cfg stm32-stick.cfg
922 cortino.cfg luminary-lm3s811.cfg turtelizer2.cfg
923 dummy.cfg olimex-arm-usb-ocd.cfg usbprog.cfg
924 flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
925 $
926 @end example
927 @item @file{board} ...
928 think Circuit Board, PWA, PCB, they go by many names. Board files
929 contain initialization items that are specific to a board.
930 They reuse target configuration files, since the same
931 microprocessor chips are used on many boards,
932 but support for external parts varies widely. For
933 example, the SDRAM initialization sequence for the board, or the type
934 of external flash and what address it uses. Any initialization
935 sequence to enable that external flash or SDRAM should be found in the
936 board file. Boards may also contain multiple targets: two CPUs; or
937 a CPU and an FPGA.
938 @example
939 $ ls board
940 arm_evaluator7t.cfg keil_mcb1700.cfg
941 at91rm9200-dk.cfg keil_mcb2140.cfg
942 at91sam9g20-ek.cfg linksys_nslu2.cfg
943 atmel_at91sam7s-ek.cfg logicpd_imx27.cfg
944 atmel_at91sam9260-ek.cfg mini2440.cfg
945 atmel_sam3u_ek.cfg olimex_LPC2378STK.cfg
946 crossbow_tech_imote2.cfg olimex_lpc_h2148.cfg
947 csb337.cfg olimex_sam7_ex256.cfg
948 csb732.cfg olimex_sam9_l9260.cfg
949 digi_connectcore_wi-9c.cfg olimex_stm32_h103.cfg
950 dm355evm.cfg omap2420_h4.cfg
951 dm365evm.cfg osk5912.cfg
952 dm6446evm.cfg pic-p32mx.cfg
953 eir.cfg propox_mmnet1001.cfg
954 ek-lm3s1968.cfg pxa255_sst.cfg
955 ek-lm3s3748.cfg sheevaplug.cfg
956 ek-lm3s811.cfg stm3210e_eval.cfg
957 ek-lm3s9b9x.cfg stm32f10x_128k_eval.cfg
958 hammer.cfg str910-eval.cfg
959 hitex_lpc2929.cfg telo.cfg
960 hitex_stm32-performancestick.cfg ti_beagleboard.cfg
961 hitex_str9-comstick.cfg topas910.cfg
962 iar_str912_sk.cfg topasa900.cfg
963 imx27ads.cfg unknown_at91sam9260.cfg
964 imx27lnst.cfg x300t.cfg
965 imx31pdk.cfg zy1000.cfg
966 $
967 @end example
968 @item @file{target} ...
969 think chip. The ``target'' directory represents the JTAG TAPs
970 on a chip
971 which OpenOCD should control, not a board. Two common types of targets
972 are ARM chips and FPGA or CPLD chips.
973 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
974 the target config file defines all of them.
975 @example
976 $ ls target
977 aduc702x.cfg imx27.cfg pxa255.cfg
978 ar71xx.cfg imx31.cfg pxa270.cfg
979 at91eb40a.cfg imx35.cfg readme.txt
980 at91r40008.cfg is5114.cfg sam7se512.cfg
981 at91rm9200.cfg ixp42x.cfg sam7x256.cfg
982 at91sam3u1c.cfg lm3s1968.cfg samsung_s3c2410.cfg
983 at91sam3u1e.cfg lm3s3748.cfg samsung_s3c2440.cfg
984 at91sam3u2c.cfg lm3s6965.cfg samsung_s3c2450.cfg
985 at91sam3u2e.cfg lm3s811.cfg samsung_s3c4510.cfg
986 at91sam3u4c.cfg lm3s9b9x.cfg samsung_s3c6410.cfg
987 at91sam3u4e.cfg lpc1768.cfg sharp_lh79532.cfg
988 at91sam3uXX.cfg lpc2103.cfg smdk6410.cfg
989 at91sam7sx.cfg lpc2124.cfg smp8634.cfg
990 at91sam9260.cfg lpc2129.cfg stm32.cfg
991 c100.cfg lpc2148.cfg str710.cfg
992 c100config.tcl lpc2294.cfg str730.cfg
993 c100helper.tcl lpc2378.cfg str750.cfg
994 c100regs.tcl lpc2478.cfg str912.cfg
995 cs351x.cfg lpc2900.cfg telo.cfg
996 davinci.cfg mega128.cfg ti_dm355.cfg
997 dragonite.cfg netx500.cfg ti_dm365.cfg
998 epc9301.cfg omap2420.cfg ti_dm6446.cfg
999 feroceon.cfg omap3530.cfg tmpa900.cfg
1000 icepick.cfg omap5912.cfg tmpa910.cfg
1001 imx21.cfg pic32mx.cfg xba_revA3.cfg
1002 $
1003 @end example
1004 @item @emph{more} ... browse for other library files which may be useful.
1005 For example, there are various generic and CPU-specific utilities.
1006 @end itemize
1007
1008 The @file{openocd.cfg} user config
1009 file may override features in any of the above files by
1010 setting variables before sourcing the target file, or by adding
1011 commands specific to their situation.
1012
1013 @section Interface Config Files
1014
1015 The user config file
1016 should be able to source one of these files with a command like this:
1017
1018 @example
1019 source [find interface/FOOBAR.cfg]
1020 @end example
1021
1022 A preconfigured interface file should exist for every interface in use
1023 today, that said, perhaps some interfaces have only been used by the
1024 sole developer who created it.
1025
1026 A separate chapter gives information about how to set these up.
1027 @xref{Interface - Dongle Configuration}.
1028 Read the OpenOCD source code if you have a new kind of hardware interface
1029 and need to provide a driver for it.
1030
1031 @section Board Config Files
1032 @cindex config file, board
1033 @cindex board config file
1034
1035 The user config file
1036 should be able to source one of these files with a command like this:
1037
1038 @example
1039 source [find board/FOOBAR.cfg]
1040 @end example
1041
1042 The point of a board config file is to package everything
1043 about a given board that user config files need to know.
1044 In summary the board files should contain (if present)
1045
1046 @enumerate
1047 @item One or more @command{source [target/...cfg]} statements
1048 @item NOR flash configuration (@pxref{NOR Configuration})
1049 @item NAND flash configuration (@pxref{NAND Configuration})
1050 @item Target @code{reset} handlers for SDRAM and I/O configuration
1051 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1052 @item All things that are not ``inside a chip''
1053 @end enumerate
1054
1055 Generic things inside target chips belong in target config files,
1056 not board config files. So for example a @code{reset-init} event
1057 handler should know board-specific oscillator and PLL parameters,
1058 which it passes to target-specific utility code.
1059
1060 The most complex task of a board config file is creating such a
1061 @code{reset-init} event handler.
1062 Define those handlers last, after you verify the rest of the board
1063 configuration works.
1064
1065 @subsection Communication Between Config files
1066
1067 In addition to target-specific utility code, another way that
1068 board and target config files communicate is by following a
1069 convention on how to use certain variables.
1070
1071 The full Tcl/Tk language supports ``namespaces'', but JIM-Tcl does not.
1072 Thus the rule we follow in OpenOCD is this: Variables that begin with
1073 a leading underscore are temporary in nature, and can be modified and
1074 used at will within a target configuration file.
1075
1076 Complex board config files can do the things like this,
1077 for a board with three chips:
1078
1079 @example
1080 # Chip #1: PXA270 for network side, big endian
1081 set CHIPNAME network
1082 set ENDIAN big
1083 source [find target/pxa270.cfg]
1084 # on return: _TARGETNAME = network.cpu
1085 # other commands can refer to the "network.cpu" target.
1086 $_TARGETNAME configure .... events for this CPU..
1087
1088 # Chip #2: PXA270 for video side, little endian
1089 set CHIPNAME video
1090 set ENDIAN little
1091 source [find target/pxa270.cfg]
1092 # on return: _TARGETNAME = video.cpu
1093 # other commands can refer to the "video.cpu" target.
1094 $_TARGETNAME configure .... events for this CPU..
1095
1096 # Chip #3: Xilinx FPGA for glue logic
1097 set CHIPNAME xilinx
1098 unset ENDIAN
1099 source [find target/spartan3.cfg]
1100 @end example
1101
1102 That example is oversimplified because it doesn't show any flash memory,
1103 or the @code{reset-init} event handlers to initialize external DRAM
1104 or (assuming it needs it) load a configuration into the FPGA.
1105 Such features are usually needed for low-level work with many boards,
1106 where ``low level'' implies that the board initialization software may
1107 not be working. (That's a common reason to need JTAG tools. Another
1108 is to enable working with microcontroller-based systems, which often
1109 have no debugging support except a JTAG connector.)
1110
1111 Target config files may also export utility functions to board and user
1112 config files. Such functions should use name prefixes, to help avoid
1113 naming collisions.
1114
1115 Board files could also accept input variables from user config files.
1116 For example, there might be a @code{J4_JUMPER} setting used to identify
1117 what kind of flash memory a development board is using, or how to set
1118 up other clocks and peripherals.
1119
1120 @subsection Variable Naming Convention
1121 @cindex variable names
1122
1123 Most boards have only one instance of a chip.
1124 However, it should be easy to create a board with more than
1125 one such chip (as shown above).
1126 Accordingly, we encourage these conventions for naming
1127 variables associated with different @file{target.cfg} files,
1128 to promote consistency and
1129 so that board files can override target defaults.
1130
1131 Inputs to target config files include:
1132
1133 @itemize @bullet
1134 @item @code{CHIPNAME} ...
1135 This gives a name to the overall chip, and is used as part of
1136 tap identifier dotted names.
1137 While the default is normally provided by the chip manufacturer,
1138 board files may need to distinguish between instances of a chip.
1139 @item @code{ENDIAN} ...
1140 By default @option{little} - although chips may hard-wire @option{big}.
1141 Chips that can't change endianness don't need to use this variable.
1142 @item @code{CPUTAPID} ...
1143 When OpenOCD examines the JTAG chain, it can be told verify the
1144 chips against the JTAG IDCODE register.
1145 The target file will hold one or more defaults, but sometimes the
1146 chip in a board will use a different ID (perhaps a newer revision).
1147 @end itemize
1148
1149 Outputs from target config files include:
1150
1151 @itemize @bullet
1152 @item @code{_TARGETNAME} ...
1153 By convention, this variable is created by the target configuration
1154 script. The board configuration file may make use of this variable to
1155 configure things like a ``reset init'' script, or other things
1156 specific to that board and that target.
1157 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1158 @code{_TARGETNAME1}, ... etc.
1159 @end itemize
1160
1161 @subsection The reset-init Event Handler
1162 @cindex event, reset-init
1163 @cindex reset-init handler
1164
1165 Board config files run in the OpenOCD configuration stage;
1166 they can't use TAPs or targets, since they haven't been
1167 fully set up yet.
1168 This means you can't write memory or access chip registers;
1169 you can't even verify that a flash chip is present.
1170 That's done later in event handlers, of which the target @code{reset-init}
1171 handler is one of the most important.
1172
1173 Except on microcontrollers, the basic job of @code{reset-init} event
1174 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1175 Microcontrollers rarely use boot loaders; they run right out of their
1176 on-chip flash and SRAM memory. But they may want to use one of these
1177 handlers too, if just for developer convenience.
1178
1179 @quotation Note
1180 Because this is so very board-specific, and chip-specific, no examples
1181 are included here.
1182 Instead, look at the board config files distributed with OpenOCD.
1183 If you have a boot loader, its source code may also be useful.
1184 @end quotation
1185
1186 Some of this code could probably be shared between different boards.
1187 For example, setting up a DRAM controller often doesn't differ by
1188 much except the bus width (16 bits or 32?) and memory timings, so a
1189 reusable TCL procedure loaded by the @file{target.cfg} file might take
1190 those as parameters.
1191 Similarly with oscillator, PLL, and clock setup;
1192 and disabling the watchdog.
1193 Structure the code cleanly, and provide comments to help
1194 the next developer doing such work.
1195 (@emph{You might be that next person} trying to reuse init code!)
1196
1197 The last thing normally done in a @code{reset-init} handler is probing
1198 whatever flash memory was configured. For most chips that needs to be
1199 done while the associated target is halted, either because JTAG memory
1200 access uses the CPU or to prevent conflicting CPU access.
1201
1202 @subsection JTAG Clock Rate
1203
1204 Before your @code{reset-init} handler has set up
1205 the PLLs and clocking, you may need to run with
1206 a low JTAG clock rate.
1207 @xref{JTAG Speed}.
1208 Then you'd increase that rate after your handler has
1209 made it possible to use the faster JTAG clock.
1210 When the initial low speed is board-specific, for example
1211 because it depends on a board-specific oscillator speed, then
1212 you should probably set it up in the board config file;
1213 if it's target-specific, it belongs in the target config file.
1214
1215 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1216 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1217 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1218 Consult chip documentation to determine the peak JTAG clock rate,
1219 which might be less than that.
1220
1221 @quotation Warning
1222 On most ARMs, JTAG clock detection is coupled to the core clock, so
1223 software using a @option{wait for interrupt} operation blocks JTAG access.
1224 Adaptive clocking provides a partial workaround, but a more complete
1225 solution just avoids using that instruction with JTAG debuggers.
1226 @end quotation
1227
1228 If the board supports adaptive clocking, use the @command{jtag_rclk}
1229 command, in case your board is used with JTAG adapter which
1230 also supports it. Otherwise use @command{jtag_khz}.
1231 Set the slow rate at the beginning of the reset sequence,
1232 and the faster rate as soon as the clocks are at full speed.
1233
1234 @section Target Config Files
1235 @cindex config file, target
1236 @cindex target config file
1237
1238 Board config files communicate with target config files using
1239 naming conventions as described above, and may source one or
1240 more target config files like this:
1241
1242 @example
1243 source [find target/FOOBAR.cfg]
1244 @end example
1245
1246 The point of a target config file is to package everything
1247 about a given chip that board config files need to know.
1248 In summary the target files should contain
1249
1250 @enumerate
1251 @item Set defaults
1252 @item Add TAPs to the scan chain
1253 @item Add CPU targets (includes GDB support)
1254 @item CPU/Chip/CPU-Core specific features
1255 @item On-Chip flash
1256 @end enumerate
1257
1258 As a rule of thumb, a target file sets up only one chip.
1259 For a microcontroller, that will often include a single TAP,
1260 which is a CPU needing a GDB target, and its on-chip flash.
1261
1262 More complex chips may include multiple TAPs, and the target
1263 config file may need to define them all before OpenOCD
1264 can talk to the chip.
1265 For example, some phone chips have JTAG scan chains that include
1266 an ARM core for operating system use, a DSP,
1267 another ARM core embedded in an image processing engine,
1268 and other processing engines.
1269
1270 @subsection Default Value Boiler Plate Code
1271
1272 All target configuration files should start with code like this,
1273 letting board config files express environment-specific
1274 differences in how things should be set up.
1275
1276 @example
1277 # Boards may override chip names, perhaps based on role,
1278 # but the default should match what the vendor uses
1279 if @{ [info exists CHIPNAME] @} @{
1280 set _CHIPNAME $CHIPNAME
1281 @} else @{
1282 set _CHIPNAME sam7x256
1283 @}
1284
1285 # ONLY use ENDIAN with targets that can change it.
1286 if @{ [info exists ENDIAN] @} @{
1287 set _ENDIAN $ENDIAN
1288 @} else @{
1289 set _ENDIAN little
1290 @}
1291
1292 # TAP identifiers may change as chips mature, for example with
1293 # new revision fields (the "3" here). Pick a good default; you
1294 # can pass several such identifiers to the "jtag newtap" command.
1295 if @{ [info exists CPUTAPID ] @} @{
1296 set _CPUTAPID $CPUTAPID
1297 @} else @{
1298 set _CPUTAPID 0x3f0f0f0f
1299 @}
1300 @end example
1301 @c but 0x3f0f0f0f is for an str73x part ...
1302
1303 @emph{Remember:} Board config files may include multiple target
1304 config files, or the same target file multiple times
1305 (changing at least @code{CHIPNAME}).
1306
1307 Likewise, the target configuration file should define
1308 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1309 use it later on when defining debug targets:
1310
1311 @example
1312 set _TARGETNAME $_CHIPNAME.cpu
1313 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1314 @end example
1315
1316 @subsection Adding TAPs to the Scan Chain
1317 After the ``defaults'' are set up,
1318 add the TAPs on each chip to the JTAG scan chain.
1319 @xref{TAP Declaration}, and the naming convention
1320 for taps.
1321
1322 In the simplest case the chip has only one TAP,
1323 probably for a CPU or FPGA.
1324 The config file for the Atmel AT91SAM7X256
1325 looks (in part) like this:
1326
1327 @example
1328 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
1329 -expected-id $_CPUTAPID
1330 @end example
1331
1332 A board with two such at91sam7 chips would be able
1333 to source such a config file twice, with different
1334 values for @code{CHIPNAME}, so
1335 it adds a different TAP each time.
1336
1337 If there are nonzero @option{-expected-id} values,
1338 OpenOCD attempts to verify the actual tap id against those values.
1339 It will issue error messages if there is mismatch, which
1340 can help to pinpoint problems in OpenOCD configurations.
1341
1342 @example
1343 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1344 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1345 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1346 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1347 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1348 @end example
1349
1350 There are more complex examples too, with chips that have
1351 multiple TAPs. Ones worth looking at include:
1352
1353 @itemize
1354 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1355 plus a JRC to enable them
1356 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1357 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1358 is not currently used)
1359 @end itemize
1360
1361 @subsection Add CPU targets
1362
1363 After adding a TAP for a CPU, you should set it up so that
1364 GDB and other commands can use it.
1365 @xref{CPU Configuration}.
1366 For the at91sam7 example above, the command can look like this;
1367 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1368 to little endian, and this chip doesn't support changing that.
1369
1370 @example
1371 set _TARGETNAME $_CHIPNAME.cpu
1372 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1373 @end example
1374
1375 Work areas are small RAM areas associated with CPU targets.
1376 They are used by OpenOCD to speed up downloads,
1377 and to download small snippets of code to program flash chips.
1378 If the chip includes a form of ``on-chip-ram'' - and many do - define
1379 a work area if you can.
1380 Again using the at91sam7 as an example, this can look like:
1381
1382 @example
1383 $_TARGETNAME configure -work-area-phys 0x00200000 \
1384 -work-area-size 0x4000 -work-area-backup 0
1385 @end example
1386
1387 @subsection Chip Reset Setup
1388
1389 As a rule, you should put the @command{reset_config} command
1390 into the board file. Most things you think you know about a
1391 chip can be tweaked by the board.
1392
1393 Some chips have specific ways the TRST and SRST signals are
1394 managed. In the unusual case that these are @emph{chip specific}
1395 and can never be changed by board wiring, they could go here.
1396
1397 Some chips need special attention during reset handling if
1398 they're going to be used with JTAG.
1399 An example might be needing to send some commands right
1400 after the target's TAP has been reset, providing a
1401 @code{reset-deassert-post} event handler that writes a chip
1402 register to report that JTAG debugging is being done.
1403
1404 JTAG clocking constraints often change during reset, and in
1405 some cases target config files (rather than board config files)
1406 are the right places to handle some of those issues.
1407 For example, immediately after reset most chips run using a
1408 slower clock than they will use later.
1409 That means that after reset (and potentially, as OpenOCD
1410 first starts up) they must use a slower JTAG clock rate
1411 than they will use later.
1412 @xref{JTAG Speed}.
1413
1414 @quotation Important
1415 When you are debugging code that runs right after chip
1416 reset, getting these issues right is critical.
1417 In particular, if you see intermittent failures when
1418 OpenOCD verifies the scan chain after reset,
1419 look at how you are setting up JTAG clocking.
1420 @end quotation
1421
1422 @subsection ARM Core Specific Hacks
1423
1424 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1425 special high speed download features - enable it.
1426
1427 If present, the MMU, the MPU and the CACHE should be disabled.
1428
1429 Some ARM cores are equipped with trace support, which permits
1430 examination of the instruction and data bus activity. Trace
1431 activity is controlled through an ``Embedded Trace Module'' (ETM)
1432 on one of the core's scan chains. The ETM emits voluminous data
1433 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
1434 If you are using an external trace port,
1435 configure it in your board config file.
1436 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1437 configure it in your target config file.
1438
1439 @example
1440 etm config $_TARGETNAME 16 normal full etb
1441 etb config $_TARGETNAME $_CHIPNAME.etb
1442 @end example
1443
1444 @subsection Internal Flash Configuration
1445
1446 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1447
1448 @b{Never ever} in the ``target configuration file'' define any type of
1449 flash that is external to the chip. (For example a BOOT flash on
1450 Chip Select 0.) Such flash information goes in a board file - not
1451 the TARGET (chip) file.
1452
1453 Examples:
1454 @itemize @bullet
1455 @item at91sam7x256 - has 256K flash YES enable it.
1456 @item str912 - has flash internal YES enable it.
1457 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1458 @item pxa270 - again - CS0 flash - it goes in the board file.
1459 @end itemize
1460
1461 @node Daemon Configuration
1462 @chapter Daemon Configuration
1463 @cindex initialization
1464 The commands here are commonly found in the openocd.cfg file and are
1465 used to specify what TCP/IP ports are used, and how GDB should be
1466 supported.
1467
1468 @anchor{Configuration Stage}
1469 @section Configuration Stage
1470 @cindex configuration stage
1471 @cindex config command
1472
1473 When the OpenOCD server process starts up, it enters a
1474 @emph{configuration stage} which is the only time that
1475 certain commands, @emph{configuration commands}, may be issued.
1476 In this manual, the definition of a configuration command is
1477 presented as a @emph{Config Command}, not as a @emph{Command}
1478 which may be issued interactively.
1479
1480 Those configuration commands include declaration of TAPs,
1481 flash banks,
1482 the interface used for JTAG communication,
1483 and other basic setup.
1484 The server must leave the configuration stage before it
1485 may access or activate TAPs.
1486 After it leaves this stage, configuration commands may no
1487 longer be issued.
1488
1489 The first thing OpenOCD does after leaving the configuration
1490 stage is to verify that it can talk to the scan chain
1491 (list of TAPs) which has been configured.
1492 It will warn if it doesn't find TAPs it expects to find,
1493 or finds TAPs that aren't supposed to be there.
1494 You should see no errors at this point.
1495 If you see errors, resolve them by correcting the
1496 commands you used to configure the server.
1497 Common errors include using an initial JTAG speed that's too
1498 fast, and not providing the right IDCODE values for the TAPs
1499 on the scan chain.
1500
1501 @deffn {Config Command} init
1502 This command terminates the configuration stage and
1503 enters the normal command mode. This can be useful to add commands to
1504 the startup scripts and commands such as resetting the target,
1505 programming flash, etc. To reset the CPU upon startup, add "init" and
1506 "reset" at the end of the config script or at the end of the OpenOCD
1507 command line using the @option{-c} command line switch.
1508
1509 If this command does not appear in any startup/configuration file
1510 OpenOCD executes the command for you after processing all
1511 configuration files and/or command line options.
1512
1513 @b{NOTE:} This command normally occurs at or near the end of your
1514 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1515 targets ready. For example: If your openocd.cfg file needs to
1516 read/write memory on your target, @command{init} must occur before
1517 the memory read/write commands. This includes @command{nand probe}.
1518 @end deffn
1519
1520 @anchor{TCP/IP Ports}
1521 @section TCP/IP Ports
1522 @cindex TCP port
1523 @cindex server
1524 @cindex port
1525 @cindex security
1526 The OpenOCD server accepts remote commands in several syntaxes.
1527 Each syntax uses a different TCP/IP port, which you may specify
1528 only during configuration (before those ports are opened).
1529
1530 For reasons including security, you may wish to prevent remote
1531 access using one or more of these ports.
1532 In such cases, just specify the relevant port number as zero.
1533 If you disable all access through TCP/IP, you will need to
1534 use the command line @option{-pipe} option.
1535
1536 @deffn {Command} gdb_port (number)
1537 @cindex GDB server
1538 Specify or query the first port used for incoming GDB connections.
1539 The GDB port for the
1540 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1541 When not specified during the configuration stage,
1542 the port @var{number} defaults to 3333.
1543 When specified as zero, this port is not activated.
1544 @end deffn
1545
1546 @deffn {Command} tcl_port (number)
1547 Specify or query the port used for a simplified RPC
1548 connection that can be used by clients to issue TCL commands and get the
1549 output from the Tcl engine.
1550 Intended as a machine interface.
1551 When not specified during the configuration stage,
1552 the port @var{number} defaults to 6666.
1553 When specified as zero, this port is not activated.
1554 @end deffn
1555
1556 @deffn {Command} telnet_port (number)
1557 Specify or query the
1558 port on which to listen for incoming telnet connections.
1559 This port is intended for interaction with one human through TCL commands.
1560 When not specified during the configuration stage,
1561 the port @var{number} defaults to 4444.
1562 When specified as zero, this port is not activated.
1563 @end deffn
1564
1565 @anchor{GDB Configuration}
1566 @section GDB Configuration
1567 @cindex GDB
1568 @cindex GDB configuration
1569 You can reconfigure some GDB behaviors if needed.
1570 The ones listed here are static and global.
1571 @xref{Target Configuration}, about configuring individual targets.
1572 @xref{Target Events}, about configuring target-specific event handling.
1573
1574 @anchor{gdb_breakpoint_override}
1575 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
1576 Force breakpoint type for gdb @command{break} commands.
1577 This option supports GDB GUIs which don't
1578 distinguish hard versus soft breakpoints, if the default OpenOCD and
1579 GDB behaviour is not sufficient. GDB normally uses hardware
1580 breakpoints if the memory map has been set up for flash regions.
1581 @end deffn
1582
1583 @deffn {Config Command} gdb_detach (@option{resume}|@option{reset}|@option{halt}|@option{nothing})
1584 Configures what OpenOCD will do when GDB detaches from the daemon.
1585 Default behaviour is @option{resume}.
1586 @end deffn
1587
1588 @anchor{gdb_flash_program}
1589 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
1590 Set to @option{enable} to cause OpenOCD to program the flash memory when a
1591 vFlash packet is received.
1592 The default behaviour is @option{enable}.
1593 @end deffn
1594
1595 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
1596 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
1597 requested. GDB will then know when to set hardware breakpoints, and program flash
1598 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1599 for flash programming to work.
1600 Default behaviour is @option{enable}.
1601 @xref{gdb_flash_program}.
1602 @end deffn
1603
1604 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
1605 Specifies whether data aborts cause an error to be reported
1606 by GDB memory read packets.
1607 The default behaviour is @option{disable};
1608 use @option{enable} see these errors reported.
1609 @end deffn
1610
1611 @anchor{Event Polling}
1612 @section Event Polling
1613
1614 Hardware debuggers are parts of asynchronous systems,
1615 where significant events can happen at any time.
1616 The OpenOCD server needs to detect some of these events,
1617 so it can report them to through TCL command line
1618 or to GDB.
1619
1620 Examples of such events include:
1621
1622 @itemize
1623 @item One of the targets can stop running ... maybe it triggers
1624 a code breakpoint or data watchpoint, or halts itself.
1625 @item Messages may be sent over ``debug message'' channels ... many
1626 targets support such messages sent over JTAG,
1627 for receipt by the person debugging or tools.
1628 @item Loss of power ... some adapters can detect these events.
1629 @item Resets not issued through JTAG ... such reset sources
1630 can include button presses or other system hardware, sometimes
1631 including the target itself (perhaps through a watchdog).
1632 @item Debug instrumentation sometimes supports event triggering
1633 such as ``trace buffer full'' (so it can quickly be emptied)
1634 or other signals (to correlate with code behavior).
1635 @end itemize
1636
1637 None of those events are signaled through standard JTAG signals.
1638 However, most conventions for JTAG connectors include voltage
1639 level and system reset (SRST) signal detection.
1640 Some connectors also include instrumentation signals, which
1641 can imply events when those signals are inputs.
1642
1643 In general, OpenOCD needs to periodically check for those events,
1644 either by looking at the status of signals on the JTAG connector
1645 or by sending synchronous ``tell me your status'' JTAG requests
1646 to the various active targets.
1647 There is a command to manage and monitor that polling,
1648 which is normally done in the background.
1649
1650 @deffn Command poll [@option{on}|@option{off}]
1651 Poll the current target for its current state.
1652 (Also, @pxref{target curstate}.)
1653 If that target is in debug mode, architecture
1654 specific information about the current state is printed.
1655 An optional parameter
1656 allows background polling to be enabled and disabled.
1657
1658 You could use this from the TCL command shell, or
1659 from GDB using @command{monitor poll} command.
1660 @example
1661 > poll
1662 background polling: on
1663 target state: halted
1664 target halted in ARM state due to debug-request, \
1665 current mode: Supervisor
1666 cpsr: 0x800000d3 pc: 0x11081bfc
1667 MMU: disabled, D-Cache: disabled, I-Cache: enabled
1668 >
1669 @end example
1670 @end deffn
1671
1672 @node Interface - Dongle Configuration
1673 @chapter Interface - Dongle Configuration
1674 @cindex config file, interface
1675 @cindex interface config file
1676
1677 JTAG Adapters/Interfaces/Dongles are normally configured
1678 through commands in an interface configuration
1679 file which is sourced by your @file{openocd.cfg} file, or
1680 through a command line @option{-f interface/....cfg} option.
1681
1682 @example
1683 source [find interface/olimex-jtag-tiny.cfg]
1684 @end example
1685
1686 These commands tell
1687 OpenOCD what type of JTAG adapter you have, and how to talk to it.
1688 A few cases are so simple that you only need to say what driver to use:
1689
1690 @example
1691 # jlink interface
1692 interface jlink
1693 @end example
1694
1695 Most adapters need a bit more configuration than that.
1696
1697
1698 @section Interface Configuration
1699
1700 The interface command tells OpenOCD what type of JTAG dongle you are
1701 using. Depending on the type of dongle, you may need to have one or
1702 more additional commands.
1703
1704 @deffn {Config Command} {interface} name
1705 Use the interface driver @var{name} to connect to the
1706 target.
1707 @end deffn
1708
1709 @deffn Command {interface_list}
1710 List the interface drivers that have been built into
1711 the running copy of OpenOCD.
1712 @end deffn
1713
1714 @deffn Command {jtag interface}
1715 Returns the name of the interface driver being used.
1716 @end deffn
1717
1718 @section Interface Drivers
1719
1720 Each of the interface drivers listed here must be explicitly
1721 enabled when OpenOCD is configured, in order to be made
1722 available at run time.
1723
1724 @deffn {Interface Driver} {amt_jtagaccel}
1725 Amontec Chameleon in its JTAG Accelerator configuration,
1726 connected to a PC's EPP mode parallel port.
1727 This defines some driver-specific commands:
1728
1729 @deffn {Config Command} {parport_port} number
1730 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1731 the number of the @file{/dev/parport} device.
1732 @end deffn
1733
1734 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
1735 Displays status of RTCK option.
1736 Optionally sets that option first.
1737 @end deffn
1738 @end deffn
1739
1740 @deffn {Interface Driver} {arm-jtag-ew}
1741 Olimex ARM-JTAG-EW USB adapter
1742 This has one driver-specific command:
1743
1744 @deffn Command {armjtagew_info}
1745 Logs some status
1746 @end deffn
1747 @end deffn
1748
1749 @deffn {Interface Driver} {at91rm9200}
1750 Supports bitbanged JTAG from the local system,
1751 presuming that system is an Atmel AT91rm9200
1752 and a specific set of GPIOs is used.
1753 @c command: at91rm9200_device NAME
1754 @c chooses among list of bit configs ... only one option
1755 @end deffn
1756
1757 @deffn {Interface Driver} {dummy}
1758 A dummy software-only driver for debugging.
1759 @end deffn
1760
1761 @deffn {Interface Driver} {ep93xx}
1762 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1763 @end deffn
1764
1765 @deffn {Interface Driver} {ft2232}
1766 FTDI FT2232 (USB) based devices over one of the userspace libraries.
1767 These interfaces have several commands, used to configure the driver
1768 before initializing the JTAG scan chain:
1769
1770 @deffn {Config Command} {ft2232_device_desc} description
1771 Provides the USB device description (the @emph{iProduct string})
1772 of the FTDI FT2232 device. If not
1773 specified, the FTDI default value is used. This setting is only valid
1774 if compiled with FTD2XX support.
1775 @end deffn
1776
1777 @deffn {Config Command} {ft2232_serial} serial-number
1778 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
1779 in case the vendor provides unique IDs and more than one FT2232 device
1780 is connected to the host.
1781 If not specified, serial numbers are not considered.
1782 (Note that USB serial numbers can be arbitrary Unicode strings,
1783 and are not restricted to containing only decimal digits.)
1784 @end deffn
1785
1786 @deffn {Config Command} {ft2232_layout} name
1787 Each vendor's FT2232 device can use different GPIO signals
1788 to control output-enables, reset signals, and LEDs.
1789 Currently valid layout @var{name} values include:
1790 @itemize @minus
1791 @item @b{axm0432_jtag} Axiom AXM-0432
1792 @item @b{comstick} Hitex STR9 comstick
1793 @item @b{cortino} Hitex Cortino JTAG interface
1794 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
1795 either for the local Cortex-M3 (SRST only)
1796 or in a passthrough mode (neither SRST nor TRST)
1797 @item @b{luminary_icdi} Luminary In-Circuit Debug Interface (ICDI) Board
1798 @item @b{flyswatter} Tin Can Tools Flyswatter
1799 @item @b{icebear} ICEbear JTAG adapter from Section 5
1800 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
1801 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
1802 @item @b{m5960} American Microsystems M5960
1803 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
1804 @item @b{oocdlink} OOCDLink
1805 @c oocdlink ~= jtagkey_prototype_v1
1806 @item @b{sheevaplug} Marvell Sheevaplug development kit
1807 @item @b{signalyzer} Xverve Signalyzer
1808 @item @b{stm32stick} Hitex STM32 Performance Stick
1809 @item @b{turtelizer2} egnite Software turtelizer2
1810 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
1811 @end itemize
1812 @end deffn
1813
1814 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
1815 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1816 default values are used.
1817 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
1818 @example
1819 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1820 @end example
1821 @end deffn
1822
1823 @deffn {Config Command} {ft2232_latency} ms
1824 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1825 ft2232_read() fails to return the expected number of bytes. This can be caused by
1826 USB communication delays and has proved hard to reproduce and debug. Setting the
1827 FT2232 latency timer to a larger value increases delays for short USB packets but it
1828 also reduces the risk of timeouts before receiving the expected number of bytes.
1829 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1830 @end deffn
1831
1832 For example, the interface config file for a
1833 Turtelizer JTAG Adapter looks something like this:
1834
1835 @example
1836 interface ft2232
1837 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
1838 ft2232_layout turtelizer2
1839 ft2232_vid_pid 0x0403 0xbdc8
1840 @end example
1841 @end deffn
1842
1843 @deffn {Interface Driver} {gw16012}
1844 Gateworks GW16012 JTAG programmer.
1845 This has one driver-specific command:
1846
1847 @deffn {Config Command} {parport_port} number
1848 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1849 the number of the @file{/dev/parport} device.
1850 @end deffn
1851 @end deffn
1852
1853 @deffn {Interface Driver} {jlink}
1854 Segger jlink USB adapter
1855 @c command: jlink_info
1856 @c dumps status
1857 @c command: jlink_hw_jtag (2|3)
1858 @c sets version 2 or 3
1859 @end deffn
1860
1861 @deffn {Interface Driver} {parport}
1862 Supports PC parallel port bit-banging cables:
1863 Wigglers, PLD download cable, and more.
1864 These interfaces have several commands, used to configure the driver
1865 before initializing the JTAG scan chain:
1866
1867 @deffn {Config Command} {parport_cable} name
1868 The layout of the parallel port cable used to connect to the target.
1869 Currently valid cable @var{name} values include:
1870
1871 @itemize @minus
1872 @item @b{altium} Altium Universal JTAG cable.
1873 @item @b{arm-jtag} Same as original wiggler except SRST and
1874 TRST connections reversed and TRST is also inverted.
1875 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
1876 in configuration mode. This is only used to
1877 program the Chameleon itself, not a connected target.
1878 @item @b{dlc5} The Xilinx Parallel cable III.
1879 @item @b{flashlink} The ST Parallel cable.
1880 @item @b{lattice} Lattice ispDOWNLOAD Cable
1881 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
1882 some versions of
1883 Amontec's Chameleon Programmer. The new version available from
1884 the website uses the original Wiggler layout ('@var{wiggler}')
1885 @item @b{triton} The parallel port adapter found on the
1886 ``Karo Triton 1 Development Board''.
1887 This is also the layout used by the HollyGates design
1888 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1889 @item @b{wiggler} The original Wiggler layout, also supported by
1890 several clones, such as the Olimex ARM-JTAG
1891 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
1892 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
1893 @end itemize
1894 @end deffn
1895
1896 @deffn {Config Command} {parport_port} number
1897 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1898 the @file{/dev/parport} device
1899
1900 When using PPDEV to access the parallel port, use the number of the parallel port:
1901 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1902 you may encounter a problem.
1903 @end deffn
1904
1905 @deffn {Config Command} {parport_write_on_exit} (on|off)
1906 This will configure the parallel driver to write a known
1907 cable-specific value to the parallel interface on exiting OpenOCD
1908 @end deffn
1909
1910 For example, the interface configuration file for a
1911 classic ``Wiggler'' cable might look something like this:
1912
1913 @example
1914 interface parport
1915 parport_port 0xc8b8
1916 parport_cable wiggler
1917 @end example
1918 @end deffn
1919
1920 @deffn {Interface Driver} {presto}
1921 ASIX PRESTO USB JTAG programmer.
1922 @c command: presto_serial str
1923 @c sets serial number
1924 @end deffn
1925
1926 @deffn {Interface Driver} {rlink}
1927 Raisonance RLink USB adapter
1928 @end deffn
1929
1930 @deffn {Interface Driver} {usbprog}
1931 usbprog is a freely programmable USB adapter.
1932 @end deffn
1933
1934 @deffn {Interface Driver} {vsllink}
1935 vsllink is part of Versaloon which is a versatile USB programmer.
1936
1937 @quotation Note
1938 This defines quite a few driver-specific commands,
1939 which are not currently documented here.
1940 @end quotation
1941 @end deffn
1942
1943 @deffn {Interface Driver} {ZY1000}
1944 This is the Zylin ZY1000 JTAG debugger.
1945
1946 @quotation Note
1947 This defines some driver-specific commands,
1948 which are not currently documented here.
1949 @end quotation
1950
1951 @deffn Command power [@option{on}|@option{off}]
1952 Turn power switch to target on/off.
1953 No arguments: print status.
1954 @end deffn
1955
1956 @end deffn
1957
1958 @anchor{JTAG Speed}
1959 @section JTAG Speed
1960 JTAG clock setup is part of system setup.
1961 It @emph{does not belong with interface setup} since any interface
1962 only knows a few of the constraints for the JTAG clock speed.
1963 Sometimes the JTAG speed is
1964 changed during the target initialization process: (1) slow at
1965 reset, (2) program the CPU clocks, (3) run fast.
1966 Both the "slow" and "fast" clock rates are functions of the
1967 oscillators used, the chip, the board design, and sometimes
1968 power management software that may be active.
1969
1970 The speed used during reset, and the scan chain verification which
1971 follows reset, can be adjusted using a @code{reset-start}
1972 target event handler.
1973 It can then be reconfigured to a faster speed by a
1974 @code{reset-init} target event handler after it reprograms those
1975 CPU clocks, or manually (if something else, such as a boot loader,
1976 sets up those clocks).
1977 @xref{Target Events}.
1978 When the initial low JTAG speed is a chip characteristic, perhaps
1979 because of a required oscillator speed, provide such a handler
1980 in the target config file.
1981 When that speed is a function of a board-specific characteristic
1982 such as which speed oscillator is used, it belongs in the board
1983 config file instead.
1984 In both cases it's safest to also set the initial JTAG clock rate
1985 to that same slow speed, so that OpenOCD never starts up using a
1986 clock speed that's faster than the scan chain can support.
1987
1988 @example
1989 jtag_rclk 3000
1990 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
1991 @end example
1992
1993 If your system supports adaptive clocking (RTCK), configuring
1994 JTAG to use that is probably the most robust approach.
1995 However, it introduces delays to synchronize clocks; so it
1996 may not be the fastest solution.
1997
1998 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
1999 instead of @command{jtag_khz}.
2000
2001 @deffn {Command} jtag_khz max_speed_kHz
2002 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
2003 JTAG interfaces usually support a limited number of
2004 speeds. The speed actually used won't be faster
2005 than the speed specified.
2006
2007 Chip data sheets generally include a top JTAG clock rate.
2008 The actual rate is often a function of a CPU core clock,
2009 and is normally less than that peak rate.
2010 For example, most ARM cores accept at most one sixth of the CPU clock.
2011
2012 Speed 0 (khz) selects RTCK method.
2013 @xref{FAQ RTCK}.
2014 If your system uses RTCK, you won't need to change the
2015 JTAG clocking after setup.
2016 Not all interfaces, boards, or targets support ``rtck''.
2017 If the interface device can not
2018 support it, an error is returned when you try to use RTCK.
2019 @end deffn
2020
2021 @defun jtag_rclk fallback_speed_kHz
2022 @cindex adaptive clocking
2023 @cindex RTCK
2024 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
2025 If that fails (maybe the interface, board, or target doesn't
2026 support it), falls back to the specified frequency.
2027 @example
2028 # Fall back to 3mhz if RTCK is not supported
2029 jtag_rclk 3000
2030 @end example
2031 @end defun
2032
2033 @node Reset Configuration
2034 @chapter Reset Configuration
2035 @cindex Reset Configuration
2036
2037 Every system configuration may require a different reset
2038 configuration. This can also be quite confusing.
2039 Resets also interact with @var{reset-init} event handlers,
2040 which do things like setting up clocks and DRAM, and
2041 JTAG clock rates. (@xref{JTAG Speed}.)
2042 They can also interact with JTAG routers.
2043 Please see the various board files for examples.
2044
2045 @quotation Note
2046 To maintainers and integrators:
2047 Reset configuration touches several things at once.
2048 Normally the board configuration file
2049 should define it and assume that the JTAG adapter supports
2050 everything that's wired up to the board's JTAG connector.
2051
2052 However, the target configuration file could also make note
2053 of something the silicon vendor has done inside the chip,
2054 which will be true for most (or all) boards using that chip.
2055 And when the JTAG adapter doesn't support everything, the
2056 user configuration file will need to override parts of
2057 the reset configuration provided by other files.
2058 @end quotation
2059
2060 @section Types of Reset
2061
2062 There are many kinds of reset possible through JTAG, but
2063 they may not all work with a given board and adapter.
2064 That's part of why reset configuration can be error prone.
2065
2066 @itemize @bullet
2067 @item
2068 @emph{System Reset} ... the @emph{SRST} hardware signal
2069 resets all chips connected to the JTAG adapter, such as processors,
2070 power management chips, and I/O controllers. Normally resets triggered
2071 with this signal behave exactly like pressing a RESET button.
2072 @item
2073 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
2074 just the TAP controllers connected to the JTAG adapter.
2075 Such resets should not be visible to the rest of the system; resetting a
2076 device's the TAP controller just puts that controller into a known state.
2077 @item
2078 @emph{Emulation Reset} ... many devices can be reset through JTAG
2079 commands. These resets are often distinguishable from system
2080 resets, either explicitly (a "reset reason" register says so)
2081 or implicitly (not all parts of the chip get reset).
2082 @item
2083 @emph{Other Resets} ... system-on-chip devices often support
2084 several other types of reset.
2085 You may need to arrange that a watchdog timer stops
2086 while debugging, preventing a watchdog reset.
2087 There may be individual module resets.
2088 @end itemize
2089
2090 In the best case, OpenOCD can hold SRST, then reset
2091 the TAPs via TRST and send commands through JTAG to halt the
2092 CPU at the reset vector before the 1st instruction is executed.
2093 Then when it finally releases the SRST signal, the system is
2094 halted under debugger control before any code has executed.
2095 This is the behavior required to support the @command{reset halt}
2096 and @command{reset init} commands; after @command{reset init} a
2097 board-specific script might do things like setting up DRAM.
2098 (@xref{Reset Command}.)
2099
2100 @anchor{SRST and TRST Issues}
2101 @section SRST and TRST Issues
2102
2103 Because SRST and TRST are hardware signals, they can have a
2104 variety of system-specific constraints. Some of the most
2105 common issues are:
2106
2107 @itemize @bullet
2108
2109 @item @emph{Signal not available} ... Some boards don't wire
2110 SRST or TRST to the JTAG connector. Some JTAG adapters don't
2111 support such signals even if they are wired up.
2112 Use the @command{reset_config} @var{signals} options to say
2113 when either of those signals is not connected.
2114 When SRST is not available, your code might not be able to rely
2115 on controllers having been fully reset during code startup.
2116 Missing TRST is not a problem, since JTAG level resets can
2117 be triggered using with TMS signaling.
2118
2119 @item @emph{Signals shorted} ... Sometimes a chip, board, or
2120 adapter will connect SRST to TRST, instead of keeping them separate.
2121 Use the @command{reset_config} @var{combination} options to say
2122 when those signals aren't properly independent.
2123
2124 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
2125 delay circuit, reset supervisor, or on-chip features can extend
2126 the effect of a JTAG adapter's reset for some time after the adapter
2127 stops issuing the reset. For example, there may be chip or board
2128 requirements that all reset pulses last for at least a
2129 certain amount of time; and reset buttons commonly have
2130 hardware debouncing.
2131 Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
2132 commands to say when extra delays are needed.
2133
2134 @item @emph{Drive type} ... Reset lines often have a pullup
2135 resistor, letting the JTAG interface treat them as open-drain
2136 signals. But that's not a requirement, so the adapter may need
2137 to use push/pull output drivers.
2138 Also, with weak pullups it may be advisable to drive
2139 signals to both levels (push/pull) to minimize rise times.
2140 Use the @command{reset_config} @var{trst_type} and
2141 @var{srst_type} parameters to say how to drive reset signals.
2142
2143 @item @emph{Special initialization} ... Targets sometimes need
2144 special JTAG initialization sequences to handle chip-specific
2145 issues (not limited to errata).
2146 For example, certain JTAG commands might need to be issued while
2147 the system as a whole is in a reset state (SRST active)
2148 but the JTAG scan chain is usable (TRST inactive).
2149 (@xref{JTAG Commands}, where the @command{jtag_reset}
2150 command is presented.)
2151 @end itemize
2152
2153 There can also be other issues.
2154 Some devices don't fully conform to the JTAG specifications.
2155 Trivial system-specific differences are common, such as
2156 SRST and TRST using slightly different names.
2157 There are also vendors who distribute key JTAG documentation for
2158 their chips only to developers who have signed a Non-Disclosure
2159 Agreement (NDA).
2160
2161 Sometimes there are chip-specific extensions like a requirement to use
2162 the normally-optional TRST signal (precluding use of JTAG adapters which
2163 don't pass TRST through), or needing extra steps to complete a TAP reset.
2164
2165 In short, SRST and especially TRST handling may be very finicky,
2166 needing to cope with both architecture and board specific constraints.
2167
2168 @section Commands for Handling Resets
2169
2170 @deffn {Command} jtag_nsrst_delay milliseconds
2171 How long (in milliseconds) OpenOCD should wait after deasserting
2172 nSRST (active-low system reset) before starting new JTAG operations.
2173 When a board has a reset button connected to SRST line it will
2174 probably have hardware debouncing, implying you should use this.
2175 @end deffn
2176
2177 @deffn {Command} jtag_ntrst_delay milliseconds
2178 How long (in milliseconds) OpenOCD should wait after deasserting
2179 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
2180 @end deffn
2181
2182 @deffn {Command} reset_config mode_flag ...
2183 This command displays or modifies the reset configuration
2184 of your combination of JTAG board and target in target
2185 configuration scripts.
2186
2187 Information earlier in this section describes the kind of problems
2188 the command is intended to address (@pxref{SRST and TRST Issues}).
2189 As a rule this command belongs only in board config files,
2190 describing issues like @emph{board doesn't connect TRST};
2191 or in user config files, addressing limitations derived
2192 from a particular combination of interface and board.
2193 (An unlikely example would be using a TRST-only adapter
2194 with a board that only wires up SRST.)
2195
2196 The @var{mode_flag} options can be specified in any order, but only one
2197 of each type -- @var{signals}, @var{combination},
2198 @var{gates},
2199 @var{trst_type},
2200 and @var{srst_type} -- may be specified at a time.
2201 If you don't provide a new value for a given type, its previous
2202 value (perhaps the default) is unchanged.
2203 For example, this means that you don't need to say anything at all about
2204 TRST just to declare that if the JTAG adapter should want to drive SRST,
2205 it must explicitly be driven high (@option{srst_push_pull}).
2206
2207 @itemize
2208 @item
2209 @var{signals} can specify which of the reset signals are connected.
2210 For example, If the JTAG interface provides SRST, but the board doesn't
2211 connect that signal properly, then OpenOCD can't use it.
2212 Possible values are @option{none} (the default), @option{trst_only},
2213 @option{srst_only} and @option{trst_and_srst}.
2214
2215 @quotation Tip
2216 If your board provides SRST and/or TRST through the JTAG connector,
2217 you must declare that or else those signals will not be used.
2218 @end quotation
2219
2220 @item
2221 The @var{combination} is an optional value specifying broken reset
2222 signal implementations.
2223 The default behaviour if no option given is @option{separate},
2224 indicating everything behaves normally.
2225 @option{srst_pulls_trst} states that the
2226 test logic is reset together with the reset of the system (e.g. Philips
2227 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
2228 the system is reset together with the test logic (only hypothetical, I
2229 haven't seen hardware with such a bug, and can be worked around).
2230 @option{combined} implies both @option{srst_pulls_trst} and
2231 @option{trst_pulls_srst}.
2232
2233 @item
2234 The @var{gates} tokens control flags that describe some cases where
2235 JTAG may be unvailable during reset.
2236 @option{srst_gates_jtag} (default)
2237 indicates that asserting SRST gates the
2238 JTAG clock. This means that no communication can happen on JTAG
2239 while SRST is asserted.
2240 Its converse is @option{srst_nogate}, indicating that JTAG commands
2241 can safely be issued while SRST is active.
2242 @end itemize
2243
2244 The optional @var{trst_type} and @var{srst_type} parameters allow the
2245 driver mode of each reset line to be specified. These values only affect
2246 JTAG interfaces with support for different driver modes, like the Amontec
2247 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
2248 relevant signal (TRST or SRST) is not connected.
2249
2250 @itemize
2251 @item
2252 Possible @var{trst_type} driver modes for the test reset signal (TRST)
2253 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
2254 Most boards connect this signal to a pulldown, so the JTAG TAPs
2255 never leave reset unless they are hooked up to a JTAG adapter.
2256
2257 @item
2258 Possible @var{srst_type} driver modes for the system reset signal (SRST)
2259 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
2260 Most boards connect this signal to a pullup, and allow the
2261 signal to be pulled low by various events including system
2262 powerup and pressing a reset button.
2263 @end itemize
2264 @end deffn
2265
2266
2267 @node TAP Declaration
2268 @chapter TAP Declaration
2269 @cindex TAP declaration
2270 @cindex TAP configuration
2271
2272 @emph{Test Access Ports} (TAPs) are the core of JTAG.
2273 TAPs serve many roles, including:
2274
2275 @itemize @bullet
2276 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
2277 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
2278 Others do it indirectly, making a CPU do it.
2279 @item @b{Program Download} Using the same CPU support GDB uses,
2280 you can initialize a DRAM controller, download code to DRAM, and then
2281 start running that code.
2282 @item @b{Boundary Scan} Most chips support boundary scan, which
2283 helps test for board assembly problems like solder bridges
2284 and missing connections
2285 @end itemize
2286
2287 OpenOCD must know about the active TAPs on your board(s).
2288 Setting up the TAPs is the core task of your configuration files.
2289 Once those TAPs are set up, you can pass their names to code
2290 which sets up CPUs and exports them as GDB targets,
2291 probes flash memory, performs low-level JTAG operations, and more.
2292
2293 @section Scan Chains
2294 @cindex scan chain
2295
2296 TAPs are part of a hardware @dfn{scan chain},
2297 which is daisy chain of TAPs.
2298 They also need to be added to
2299 OpenOCD's software mirror of that hardware list,
2300 giving each member a name and associating other data with it.
2301 Simple scan chains, with a single TAP, are common in
2302 systems with a single microcontroller or microprocessor.
2303 More complex chips may have several TAPs internally.
2304 Very complex scan chains might have a dozen or more TAPs:
2305 several in one chip, more in the next, and connecting
2306 to other boards with their own chips and TAPs.
2307
2308 You can display the list with the @command{scan_chain} command.
2309 (Don't confuse this with the list displayed by the @command{targets}
2310 command, presented in the next chapter.
2311 That only displays TAPs for CPUs which are configured as
2312 debugging targets.)
2313 Here's what the scan chain might look like for a chip more than one TAP:
2314
2315 @verbatim
2316 TapName Enabled IdCode Expected IrLen IrCap IrMask Instr
2317 -- ------------------ ------- ---------- ---------- ----- ----- ------ -----
2318 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0 0 0x...
2319 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x1 0 0xc
2320 2 omap5912.unknown Y 0x00000000 0x00000000 8 0 0 0xff
2321 @end verbatim
2322
2323 Unfortunately those TAPs can't always be autoconfigured,
2324 because not all devices provide good support for that.
2325 JTAG doesn't require supporting IDCODE instructions, and
2326 chips with JTAG routers may not link TAPs into the chain
2327 until they are told to do so.
2328
2329 The configuration mechanism currently supported by OpenOCD
2330 requires explicit configuration of all TAP devices using
2331 @command{jtag newtap} commands, as detailed later in this chapter.
2332 A command like this would declare one tap and name it @code{chip1.cpu}:
2333
2334 @example
2335 jtag newtap chip1 cpu -irlen 7 -ircapture 0x01 -irmask 0x55
2336 @end example
2337
2338 Each target configuration file lists the TAPs provided
2339 by a given chip.
2340 Board configuration files combine all the targets on a board,
2341 and so forth.
2342 Note that @emph{the order in which TAPs are declared is very important.}
2343 It must match the order in the JTAG scan chain, both inside
2344 a single chip and between them.
2345 @xref{FAQ TAP Order}.
2346
2347 For example, the ST Microsystems STR912 chip has
2348 three separate TAPs@footnote{See the ST
2349 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
2350 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
2351 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
2352 To configure those taps, @file{target/str912.cfg}
2353 includes commands something like this:
2354
2355 @example
2356 jtag newtap str912 flash ... params ...
2357 jtag newtap str912 cpu ... params ...
2358 jtag newtap str912 bs ... params ...
2359 @end example
2360
2361 Actual config files use a variable instead of literals like
2362 @option{str912}, to support more than one chip of each type.
2363 @xref{Config File Guidelines}.
2364
2365 @deffn Command {jtag names}
2366 Returns the names of all current TAPs in the scan chain.
2367 Use @command{jtag cget} or @command{jtag tapisenabled}
2368 to examine attributes and state of each TAP.
2369 @example
2370 foreach t [jtag names] @{
2371 puts [format "TAP: %s\n" $t]
2372 @}
2373 @end example
2374 @end deffn
2375
2376 @deffn Command {scan_chain}
2377 Displays the TAPs in the scan chain configuration,
2378 and their status.
2379 The set of TAPs listed by this command is fixed by
2380 exiting the OpenOCD configuration stage,
2381 but systems with a JTAG router can
2382 enable or disable TAPs dynamically.
2383 In addition to the enable/disable status, the contents of
2384 each TAP's instruction register can also change.
2385 @end deffn
2386
2387 @c FIXME! "jtag cget" should be able to return all TAP
2388 @c attributes, like "$target_name cget" does for targets.
2389
2390 @c Probably want "jtag eventlist", and a "tap-reset" event
2391 @c (on entry to RESET state).
2392
2393 @section TAP Names
2394 @cindex dotted name
2395
2396 When TAP objects are declared with @command{jtag newtap},
2397 a @dfn{dotted.name} is created for the TAP, combining the
2398 name of a module (usually a chip) and a label for the TAP.
2399 For example: @code{xilinx.tap}, @code{str912.flash},
2400 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
2401 Many other commands use that dotted.name to manipulate or
2402 refer to the TAP. For example, CPU configuration uses the
2403 name, as does declaration of NAND or NOR flash banks.
2404
2405 The components of a dotted name should follow ``C'' symbol
2406 name rules: start with an alphabetic character, then numbers
2407 and underscores are OK; while others (including dots!) are not.
2408
2409 @quotation Tip
2410 In older code, JTAG TAPs were numbered from 0..N.
2411 This feature is still present.
2412 However its use is highly discouraged, and
2413 should not be relied on; it will be removed by mid-2010.
2414 Update all of your scripts to use TAP names rather than numbers,
2415 by paying attention to the runtime warnings they trigger.
2416 Using TAP numbers in target configuration scripts prevents
2417 reusing those scripts on boards with multiple targets.
2418 @end quotation
2419
2420 @section TAP Declaration Commands
2421
2422 @c shouldn't this be(come) a {Config Command}?
2423 @anchor{jtag newtap}
2424 @deffn Command {jtag newtap} chipname tapname configparams...
2425 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
2426 and configured according to the various @var{configparams}.
2427
2428 The @var{chipname} is a symbolic name for the chip.
2429 Conventionally target config files use @code{$_CHIPNAME},
2430 defaulting to the model name given by the chip vendor but
2431 overridable.
2432
2433 @cindex TAP naming convention
2434 The @var{tapname} reflects the role of that TAP,
2435 and should follow this convention:
2436
2437 @itemize @bullet
2438 @item @code{bs} -- For boundary scan if this is a seperate TAP;
2439 @item @code{cpu} -- The main CPU of the chip, alternatively
2440 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
2441 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
2442 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
2443 @item @code{flash} -- If the chip has a flash TAP, like the str912;
2444 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
2445 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
2446 @item @code{tap} -- Should be used only FPGA or CPLD like devices
2447 with a single TAP;
2448 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
2449 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
2450 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
2451 a JTAG TAP; that TAP should be named @code{sdma}.
2452 @end itemize
2453
2454 Every TAP requires at least the following @var{configparams}:
2455
2456 @itemize @bullet
2457 @item @code{-irlen} @var{NUMBER}
2458 @*The length in bits of the
2459 instruction register, such as 4 or 5 bits.
2460 @end itemize
2461
2462 A TAP may also provide optional @var{configparams}:
2463
2464 @itemize @bullet
2465 @item @code{-disable} (or @code{-enable})
2466 @*Use the @code{-disable} parameter to flag a TAP which is not
2467 linked in to the scan chain after a reset using either TRST
2468 or the JTAG state machine's @sc{reset} state.
2469 You may use @code{-enable} to highlight the default state
2470 (the TAP is linked in).
2471 @xref{Enabling and Disabling TAPs}.
2472 @item @code{-expected-id} @var{number}
2473 @*A non-zero @var{number} represents a 32-bit IDCODE
2474 which you expect to find when the scan chain is examined.
2475 These codes are not required by all JTAG devices.
2476 @emph{Repeat the option} as many times as required if more than one
2477 ID code could appear (for example, multiple versions).
2478 Specify @var{number} as zero to suppress warnings about IDCODE
2479 values that were found but not included in the list.
2480 @item @code{-ircapture} @var{NUMBER}
2481 @*The bit pattern loaded by the TAP into the JTAG shift register
2482 on entry to the @sc{ircapture} state, such as 0x01.
2483 JTAG requires the two LSBs of this value to be 01.
2484 By default, @code{-ircapture} and @code{-irmask} are set
2485 up to verify that two-bit value; but you may provide
2486 additional bits, if you know them.
2487 @item @code{-irmask} @var{NUMBER}
2488 @*A mask used with @code{-ircapture}
2489 to verify that instruction scans work correctly.
2490 Such scans are not used by OpenOCD except to verify that
2491 there seems to be no problems with JTAG scan chain operations.
2492 @end itemize
2493 @end deffn
2494
2495 @section Other TAP commands
2496
2497 @c @deffn Command {jtag arp_init-reset}
2498 @c ... more or less "toggle TRST ... and SRST too, what the heck"
2499
2500 @deffn Command {jtag cget} dotted.name @option{-event} name
2501 @deffnx Command {jtag configure} dotted.name @option{-event} name string
2502 At this writing this TAP attribute
2503 mechanism is used only for event handling.
2504 (It is not a direct analogue of the @code{cget}/@code{configure}
2505 mechanism for debugger targets.)
2506 See the next section for information about the available events.
2507
2508 The @code{configure} subcommand assigns an event handler,
2509 a TCL string which is evaluated when the event is triggered.
2510 The @code{cget} subcommand returns that handler.
2511 @end deffn
2512
2513 @anchor{TAP Events}
2514 @section TAP Events
2515 @cindex events
2516 @cindex TAP events
2517
2518 OpenOCD includes two event mechanisms.
2519 The one presented here applies to all JTAG TAPs.
2520 The other applies to debugger targets,
2521 which are associated with certain TAPs.
2522
2523 The TAP events currently defined are:
2524
2525 @itemize @bullet
2526 @item @b{post-reset}
2527 @* The TAP has just completed a JTAG reset.
2528 The tap may still be in the JTAG @sc{reset} state.
2529 Handlers for these events might perform initialization sequences
2530 such as issuing TCK cycles, TMS sequences to ensure
2531 exit from the ARM SWD mode, and more.
2532
2533 Because the scan chain has not yet been verified, handlers for these events
2534 @emph{should not issue commands which scan the JTAG IR or DR registers}
2535 of any particular target.
2536 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
2537 @item @b{setup}
2538 @* The scan chain has been reset and verified.
2539 This handler may enable TAPs as needed.
2540 @item @b{tap-disable}
2541 @* The TAP needs to be disabled. This handler should
2542 implement @command{jtag tapdisable}
2543 by issuing the relevant JTAG commands.
2544 @item @b{tap-enable}
2545 @* The TAP needs to be enabled. This handler should
2546 implement @command{jtag tapenable}
2547 by issuing the relevant JTAG commands.
2548 @end itemize
2549
2550 If you need some action after each JTAG reset, which isn't actually
2551 specific to any TAP (since you can't yet trust the scan chain's
2552 contents to be accurate), you might:
2553
2554 @example
2555 jtag configure CHIP.jrc -event post-reset @{
2556 echo "JTAG Reset done"
2557 ... non-scan jtag operations to be done after reset
2558 @}
2559 @end example
2560
2561
2562 @anchor{Enabling and Disabling TAPs}
2563 @section Enabling and Disabling TAPs
2564 @cindex JTAG Route Controller
2565 @cindex jrc
2566
2567 In some systems, a @dfn{JTAG Route Controller} (JRC)
2568 is used to enable and/or disable specific JTAG TAPs.
2569 Many ARM based chips from Texas Instruments include
2570 an ``ICEpick'' module, which is a JRC.
2571 Such chips include DaVinci and OMAP3 processors.
2572
2573 A given TAP may not be visible until the JRC has been
2574 told to link it into the scan chain; and if the JRC
2575 has been told to unlink that TAP, it will no longer
2576 be visible.
2577 Such routers address problems that JTAG ``bypass mode''
2578 ignores, such as:
2579
2580 @itemize
2581 @item The scan chain can only go as fast as its slowest TAP.
2582 @item Having many TAPs slows instruction scans, since all
2583 TAPs receive new instructions.
2584 @item TAPs in the scan chain must be powered up, which wastes
2585 power and prevents debugging some power management mechanisms.
2586 @end itemize
2587
2588 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
2589 as implied by the existence of JTAG routers.
2590 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
2591 does include a kind of JTAG router functionality.
2592
2593 @c (a) currently the event handlers don't seem to be able to
2594 @c fail in a way that could lead to no-change-of-state.
2595
2596 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
2597 shown below, and is implemented using TAP event handlers.
2598 So for example, when defining a TAP for a CPU connected to
2599 a JTAG router, your @file{target.cfg} file
2600 should define TAP event handlers using
2601 code that looks something like this:
2602
2603 @example
2604 jtag configure CHIP.cpu -event tap-enable @{
2605 ... jtag operations using CHIP.jrc
2606 @}
2607 jtag configure CHIP.cpu -event tap-disable @{
2608 ... jtag operations using CHIP.jrc
2609 @}
2610 @end example
2611
2612 Then you might want that CPU's TAP enabled almost all the time:
2613
2614 @example
2615 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
2616 @end example
2617
2618 Note how that particular setup event handler declaration
2619 uses quotes to evaluate @code{$CHIP} when the event is configured.
2620 Using brackets @{ @} would cause it to be evaluated later,
2621 at runtime, when it might have a different value.
2622
2623 @deffn Command {jtag tapdisable} dotted.name
2624 If necessary, disables the tap
2625 by sending it a @option{tap-disable} event.
2626 Returns the string "1" if the tap
2627 specified by @var{dotted.name} is enabled,
2628 and "0" if it is disabled.
2629 @end deffn
2630
2631 @deffn Command {jtag tapenable} dotted.name
2632 If necessary, enables the tap
2633 by sending it a @option{tap-enable} event.
2634 Returns the string "1" if the tap
2635 specified by @var{dotted.name} is enabled,
2636 and "0" if it is disabled.
2637 @end deffn
2638
2639 @deffn Command {jtag tapisenabled} dotted.name
2640 Returns the string "1" if the tap
2641 specified by @var{dotted.name} is enabled,
2642 and "0" if it is disabled.
2643
2644 @quotation Note
2645 Humans will find the @command{scan_chain} command more helpful
2646 for querying the state of the JTAG taps.
2647 @end quotation
2648 @end deffn
2649
2650 @node CPU Configuration
2651 @chapter CPU Configuration
2652 @cindex GDB target
2653
2654 This chapter discusses how to set up GDB debug targets for CPUs.
2655 You can also access these targets without GDB
2656 (@pxref{Architecture and Core Commands},
2657 and @ref{Target State handling}) and
2658 through various kinds of NAND and NOR flash commands.
2659 If you have multiple CPUs you can have multiple such targets.
2660
2661 We'll start by looking at how to examine the targets you have,
2662 then look at how to add one more target and how to configure it.
2663
2664 @section Target List
2665 @cindex target, current
2666 @cindex target, list
2667
2668 All targets that have been set up are part of a list,
2669 where each member has a name.
2670 That name should normally be the same as the TAP name.
2671 You can display the list with the @command{targets}
2672 (plural!) command.
2673 This display often has only one CPU; here's what it might
2674 look like with more than one:
2675 @verbatim
2676 TargetName Type Endian TapName State
2677 -- ------------------ ---------- ------ ------------------ ------------
2678 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
2679 1 MyTarget cortex_m3 little mychip.foo tap-disabled
2680 @end verbatim
2681
2682 One member of that list is the @dfn{current target}, which
2683 is implicitly referenced by many commands.
2684 It's the one marked with a @code{*} near the target name.
2685 In particular, memory addresses often refer to the address
2686 space seen by that current target.
2687 Commands like @command{mdw} (memory display words)
2688 and @command{flash erase_address} (erase NOR flash blocks)
2689 are examples; and there are many more.
2690
2691 Several commands let you examine the list of targets:
2692
2693 @deffn Command {target count}
2694 @emph{Note: target numbers are deprecated; don't use them.
2695 They will be removed shortly after August 2010, including this command.
2696 Iterate target using @command{target names}, not by counting.}
2697
2698 Returns the number of targets, @math{N}.
2699 The highest numbered target is @math{N - 1}.
2700 @example
2701 set c [target count]
2702 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
2703 # Assuming you have created this function
2704 print_target_details $x
2705 @}
2706 @end example
2707 @end deffn
2708
2709 @deffn Command {target current}
2710 Returns the name of the current target.
2711 @end deffn
2712
2713 @deffn Command {target names}
2714 Lists the names of all current targets in the list.
2715 @example
2716 foreach t [target names] @{
2717 puts [format "Target: %s\n" $t]
2718 @}
2719 @end example
2720 @end deffn
2721
2722 @deffn Command {target number} number
2723 @emph{Note: target numbers are deprecated; don't use them.
2724 They will be removed shortly after August 2010, including this command.}
2725
2726 The list of targets is numbered starting at zero.
2727 This command returns the name of the target at index @var{number}.
2728 @example
2729 set thename [target number $x]
2730 puts [format "Target %d is: %s\n" $x $thename]
2731 @end example
2732 @end deffn
2733
2734 @c yep, "target list" would have been better.
2735 @c plus maybe "target setdefault".
2736
2737 @deffn Command targets [name]
2738 @emph{Note: the name of this command is plural. Other target
2739 command names are singular.}
2740
2741 With no parameter, this command displays a table of all known
2742 targets in a user friendly form.
2743
2744 With a parameter, this command sets the current target to
2745 the given target with the given @var{name}; this is
2746 only relevant on boards which have more than one target.
2747 @end deffn
2748
2749 @section Target CPU Types and Variants
2750 @cindex target type
2751 @cindex CPU type
2752 @cindex CPU variant
2753
2754 Each target has a @dfn{CPU type}, as shown in the output of
2755 the @command{targets} command. You need to specify that type
2756 when calling @command{target create}.
2757 The CPU type indicates more than just the instruction set.
2758 It also indicates how that instruction set is implemented,
2759 what kind of debug support it integrates,
2760 whether it has an MMU (and if so, what kind),
2761 what core-specific commands may be available
2762 (@pxref{Architecture and Core Commands}),
2763 and more.
2764
2765 For some CPU types, OpenOCD also defines @dfn{variants} which
2766 indicate differences that affect their handling.
2767 For example, a particular implementation bug might need to be
2768 worked around in some chip versions.
2769
2770 It's easy to see what target types are supported,
2771 since there's a command to list them.
2772 However, there is currently no way to list what target variants
2773 are supported (other than by reading the OpenOCD source code).
2774
2775 @anchor{target types}
2776 @deffn Command {target types}
2777 Lists all supported target types.
2778 At this writing, the supported CPU types and variants are:
2779
2780 @itemize @bullet
2781 @item @code{arm11} -- this is a generation of ARMv6 cores
2782 @item @code{arm720t} -- this is an ARMv4 core
2783 @item @code{arm7tdmi} -- this is an ARMv4 core
2784 @item @code{arm920t} -- this is an ARMv5 core
2785 @item @code{arm926ejs} -- this is an ARMv5 core
2786 @item @code{arm966e} -- this is an ARMv5 core
2787 @item @code{arm9tdmi} -- this is an ARMv4 core
2788 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
2789 (Support for this is preliminary and incomplete.)
2790 @item @code{cortex_a8} -- this is an ARMv7 core
2791 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
2792 compact Thumb2 instruction set. It supports one variant:
2793 @itemize @minus
2794 @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
2795 This will cause OpenOCD to use a software reset rather than asserting
2796 SRST, to avoid a issue with clearing the debug registers.
2797 This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
2798 be detected and the normal reset behaviour used.
2799 @end itemize
2800 @item @code{fa526} -- resembles arm920 (w/o Thumb)
2801 @item @code{feroceon} -- resembles arm926
2802 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
2803 @itemize @minus
2804 @item @code{ejtag_srst} ... Use this when debugging targets that do not
2805 provide a functional SRST line on the EJTAG connector. This causes
2806 OpenOCD to instead use an EJTAG software reset command to reset the
2807 processor.
2808 You still need to enable @option{srst} on the @command{reset_config}
2809 command to enable OpenOCD hardware reset functionality.
2810 @end itemize
2811 @item @code{xscale} -- this is actually an architecture,
2812 not a CPU type. It is based on the ARMv5 architecture.
2813 There are several variants defined:
2814 @itemize @minus
2815 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
2816 @code{pxa27x} ... instruction register length is 7 bits
2817 @item @code{pxa250}, @code{pxa255},
2818 @code{pxa26x} ... instruction register length is 5 bits
2819 @end itemize
2820 @end itemize
2821 @end deffn
2822
2823 To avoid being confused by the variety of ARM based cores, remember
2824 this key point: @emph{ARM is a technology licencing company}.
2825 (See: @url{http://www.arm.com}.)
2826 The CPU name used by OpenOCD will reflect the CPU design that was
2827 licenced, not a vendor brand which incorporates that design.
2828 Name prefixes like arm7, arm9, arm11, and cortex
2829 reflect design generations;
2830 while names like ARMv4, ARMv5, ARMv6, and ARMv7
2831 reflect an architecture version implemented by a CPU design.
2832
2833 @anchor{Target Configuration}
2834 @section Target Configuration
2835
2836 Before creating a ``target'', you must have added its TAP to the scan chain.
2837 When you've added that TAP, you will have a @code{dotted.name}
2838 which is used to set up the CPU support.
2839 The chip-specific configuration file will normally configure its CPU(s)
2840 right after it adds all of the chip's TAPs to the scan chain.
2841
2842 Although you can set up a target in one step, it's often clearer if you
2843 use shorter commands and do it in two steps: create it, then configure
2844 optional parts.
2845 All operations on the target after it's created will use a new
2846 command, created as part of target creation.
2847
2848 The two main things to configure after target creation are
2849 a work area, which usually has target-specific defaults even
2850 if the board setup code overrides them later;
2851 and event handlers (@pxref{Target Events}), which tend
2852 to be much more board-specific.
2853 The key steps you use might look something like this
2854
2855 @example
2856 target create MyTarget cortex_m3 -chain-position mychip.cpu
2857 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
2858 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
2859 $MyTarget configure -event reset-init @{ myboard_reinit @}
2860 @end example
2861
2862 You should specify a working area if you can; typically it uses some
2863 on-chip SRAM.
2864 Such a working area can speed up many things, including bulk
2865 writes to target memory;
2866 flash operations like checking to see if memory needs to be erased;
2867 GDB memory checksumming;
2868 and more.
2869
2870 @quotation Warning
2871 On more complex chips, the work area can become
2872 inaccessible when application code
2873 (such as an operating system)
2874 enables or disables the MMU.
2875 For example, the particular MMU context used to acess the virtual
2876 address will probably matter ... and that context might not have
2877 easy access to other addresses needed.
2878 At this writing, OpenOCD doesn't have much MMU intelligence.
2879 @end quotation
2880
2881 It's often very useful to define a @code{reset-init} event handler.
2882 For systems that are normally used with a boot loader,
2883 common tasks include updating clocks and initializing memory
2884 controllers.
2885 That may be needed to let you write the boot loader into flash,
2886 in order to ``de-brick'' your board; or to load programs into
2887 external DDR memory without having run the boot loader.
2888
2889 @deffn Command {target create} target_name type configparams...
2890 This command creates a GDB debug target that refers to a specific JTAG tap.
2891 It enters that target into a list, and creates a new
2892 command (@command{@var{target_name}}) which is used for various
2893 purposes including additional configuration.
2894
2895 @itemize @bullet
2896 @item @var{target_name} ... is the name of the debug target.
2897 By convention this should be the same as the @emph{dotted.name}
2898 of the TAP associated with this target, which must be specified here
2899 using the @code{-chain-position @var{dotted.name}} configparam.
2900
2901 This name is also used to create the target object command,
2902 referred to here as @command{$target_name},
2903 and in other places the target needs to be identified.
2904 @item @var{type} ... specifies the target type. @xref{target types}.
2905 @item @var{configparams} ... all parameters accepted by
2906 @command{$target_name configure} are permitted.
2907 If the target is big-endian, set it here with @code{-endian big}.
2908 If the variant matters, set it here with @code{-variant}.
2909
2910 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
2911 @end itemize
2912 @end deffn
2913
2914 @deffn Command {$target_name configure} configparams...
2915 The options accepted by this command may also be
2916 specified as parameters to @command{target create}.
2917 Their values can later be queried one at a time by
2918 using the @command{$target_name cget} command.
2919
2920 @emph{Warning:} changing some of these after setup is dangerous.
2921 For example, moving a target from one TAP to another;
2922 and changing its endianness or variant.
2923
2924 @itemize @bullet
2925
2926 @item @code{-chain-position} @var{dotted.name} -- names the TAP
2927 used to access this target.
2928
2929 @item @code{-endian} (@option{big}|@option{little}) -- specifies
2930 whether the CPU uses big or little endian conventions
2931
2932 @item @code{-event} @var{event_name} @var{event_body} --
2933 @xref{Target Events}.
2934 Note that this updates a list of named event handlers.
2935 Calling this twice with two different event names assigns
2936 two different handlers, but calling it twice with the
2937 same event name assigns only one handler.
2938
2939 @item @code{-variant} @var{name} -- specifies a variant of the target,
2940 which OpenOCD needs to know about.
2941
2942 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
2943 whether the work area gets backed up; by default,
2944 @emph{it is not backed up.}
2945 When possible, use a working_area that doesn't need to be backed up,
2946 since performing a backup slows down operations.
2947 For example, the beginning of an SRAM block is likely to
2948 be used by most build systems, but the end is often unused.
2949
2950 @item @code{-work-area-size} @var{size} -- specify/set the work area
2951
2952 @item @code{-work-area-phys} @var{address} -- set the work area
2953 base @var{address} to be used when no MMU is active.
2954
2955 @item @code{-work-area-virt} @var{address} -- set the work area
2956 base @var{address} to be used when an MMU is active.
2957
2958 @end itemize
2959 @end deffn
2960
2961 @section Other $target_name Commands
2962 @cindex object command
2963
2964 The Tcl/Tk language has the concept of object commands,
2965 and OpenOCD adopts that same model for targets.
2966
2967 A good Tk example is a on screen button.
2968 Once a button is created a button
2969 has a name (a path in Tk terms) and that name is useable as a first
2970 class command. For example in Tk, one can create a button and later
2971 configure it like this:
2972
2973 @example
2974 # Create
2975 button .foobar -background red -command @{ foo @}
2976 # Modify
2977 .foobar configure -foreground blue
2978 # Query
2979 set x [.foobar cget -background]
2980 # Report
2981 puts [format "The button is %s" $x]
2982 @end example
2983
2984 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
2985 button, and its object commands are invoked the same way.
2986
2987 @example
2988 str912.cpu mww 0x1234 0x42
2989 omap3530.cpu mww 0x5555 123
2990 @end example
2991
2992 The commands supported by OpenOCD target objects are:
2993
2994 @deffn Command {$target_name arp_examine}
2995 @deffnx Command {$target_name arp_halt}
2996 @deffnx Command {$target_name arp_poll}
2997 @deffnx Command {$target_name arp_reset}
2998 @deffnx Command {$target_name arp_waitstate}
2999 Internal OpenOCD scripts (most notably @file{startup.tcl})
3000 use these to deal with specific reset cases.
3001 They are not otherwise documented here.
3002 @end deffn
3003
3004 @deffn Command {$target_name array2mem} arrayname width address count
3005 @deffnx Command {$target_name mem2array} arrayname width address count
3006 These provide an efficient script-oriented interface to memory.
3007 The @code{array2mem} primitive writes bytes, halfwords, or words;
3008 while @code{mem2array} reads them.
3009 In both cases, the TCL side uses an array, and
3010 the target side uses raw memory.
3011
3012 The efficiency comes from enabling the use of
3013 bulk JTAG data transfer operations.
3014 The script orientation comes from working with data
3015 values that are packaged for use by TCL scripts;
3016 @command{mdw} type primitives only print data they retrieve,
3017 and neither store nor return those values.
3018
3019 @itemize
3020 @item @var{arrayname} ... is the name of an array variable
3021 @item @var{width} ... is 8/16/32 - indicating the memory access size
3022 @item @var{address} ... is the target memory address
3023 @item @var{count} ... is the number of elements to process
3024 @end itemize
3025 @end deffn
3026
3027 @deffn Command {$target_name cget} queryparm
3028 Each configuration parameter accepted by
3029 @command{$target_name configure}
3030 can be individually queried, to return its current value.
3031 The @var{queryparm} is a parameter name
3032 accepted by that command, such as @code{-work-area-phys}.
3033 There are a few special cases:
3034
3035 @itemize @bullet
3036 @item @code{-event} @var{event_name} -- returns the handler for the
3037 event named @var{event_name}.
3038 This is a special case because setting a handler requires
3039 two parameters.
3040 @item @code{-type} -- returns the target type.
3041 This is a special case because this is set using
3042 @command{target create} and can't be changed
3043 using @command{$target_name configure}.
3044 @end itemize
3045
3046 For example, if you wanted to summarize information about
3047 all the targets you might use something like this:
3048
3049 @example
3050 foreach name [target names] @{
3051 set y [$name cget -endian]
3052 set z [$name cget -type]
3053 puts [format "Chip %d is %s, Endian: %s, type: %s" \
3054 $x $name $y $z]
3055 @}
3056 @end example
3057 @end deffn
3058
3059 @anchor{target curstate}
3060 @deffn Command {$target_name curstate}
3061 Displays the current target state:
3062 @code{debug-running},
3063 @code{halted},
3064 @code{reset},
3065 @code{running}, or @code{unknown}.
3066 (Also, @pxref{Event Polling}.)
3067 @end deffn
3068
3069 @deffn Command {$target_name eventlist}
3070 Displays a table listing all event handlers
3071 currently associated with this target.
3072 @xref{Target Events}.
3073 @end deffn
3074
3075 @deffn Command {$target_name invoke-event} event_name
3076 Invokes the handler for the event named @var{event_name}.
3077 (This is primarily intended for use by OpenOCD framework
3078 code, for example by the reset code in @file{startup.tcl}.)
3079 @end deffn
3080
3081 @deffn Command {$target_name mdw} addr [count]
3082 @deffnx Command {$target_name mdh} addr [count]
3083 @deffnx Command {$target_name mdb} addr [count]
3084 Display contents of address @var{addr}, as
3085 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
3086 or 8-bit bytes (@command{mdb}).
3087 If @var{count} is specified, displays that many units.
3088 (If you want to manipulate the data instead of displaying it,
3089 see the @code{mem2array} primitives.)
3090 @end deffn
3091
3092 @deffn Command {$target_name mww} addr word
3093 @deffnx Command {$target_name mwh} addr halfword
3094 @deffnx Command {$target_name mwb} addr byte
3095 Writes the specified @var{word} (32 bits),
3096 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3097 at the specified address @var{addr}.
3098 @end deffn
3099
3100 @anchor{Target Events}
3101 @section Target Events
3102 @cindex target events
3103 @cindex events
3104 At various times, certain things can happen, or you want them to happen.
3105 For example:
3106 @itemize @bullet
3107 @item What should happen when GDB connects? Should your target reset?
3108 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
3109 @item During reset, do you need to write to certain memory locations
3110 to set up system clocks or
3111 to reconfigure the SDRAM?
3112 @end itemize
3113
3114 All of the above items can be addressed by target event handlers.
3115 These are set up by @command{$target_name configure -event} or
3116 @command{target create ... -event}.
3117
3118 The programmer's model matches the @code{-command} option used in Tcl/Tk
3119 buttons and events. The two examples below act the same, but one creates
3120 and invokes a small procedure while the other inlines it.
3121
3122 @example
3123 proc my_attach_proc @{ @} @{
3124 echo "Reset..."
3125 reset halt
3126 @}
3127 mychip.cpu configure -event gdb-attach my_attach_proc
3128 mychip.cpu configure -event gdb-attach @{
3129 echo "Reset..."
3130 reset halt
3131 @}
3132 @end example
3133
3134 The following target events are defined:
3135
3136 @itemize @bullet
3137 @item @b{debug-halted}
3138 @* The target has halted for debug reasons (i.e.: breakpoint)
3139 @item @b{debug-resumed}
3140 @* The target has resumed (i.e.: gdb said run)
3141 @item @b{early-halted}
3142 @* Occurs early in the halt process
3143 @ignore
3144 @item @b{examine-end}
3145 @* Currently not used (goal: when JTAG examine completes)
3146 @item @b{examine-start}
3147 @* Currently not used (goal: when JTAG examine starts)
3148 @end ignore
3149 @item @b{gdb-attach}
3150 @* When GDB connects
3151 @item @b{gdb-detach}
3152 @* When GDB disconnects
3153 @item @b{gdb-end}
3154 @* When the target has halted and GDB is not doing anything (see early halt)
3155 @item @b{gdb-flash-erase-start}
3156 @* Before the GDB flash process tries to erase the flash
3157 @item @b{gdb-flash-erase-end}
3158 @* After the GDB flash process has finished erasing the flash
3159 @item @b{gdb-flash-write-start}
3160 @* Before GDB writes to the flash
3161 @item @b{gdb-flash-write-end}
3162 @* After GDB writes to the flash
3163 @item @b{gdb-start}
3164 @* Before the target steps, gdb is trying to start/resume the target
3165 @item @b{halted}
3166 @* The target has halted
3167 @ignore
3168 @item @b{old-gdb_program_config}
3169 @* DO NOT USE THIS: Used internally
3170 @item @b{old-pre_resume}
3171 @* DO NOT USE THIS: Used internally
3172 @end ignore
3173 @item @b{reset-assert-pre}
3174 @* Issued as part of @command{reset} processing
3175 after SRST and/or TRST were activated and deactivated,
3176 but before SRST alone is re-asserted on the tap.
3177 @item @b{reset-assert-post}
3178 @* Issued as part of @command{reset} processing
3179 when SRST is asserted on the tap.
3180 @item @b{reset-deassert-pre}
3181 @* Issued as part of @command{reset} processing
3182 when SRST is about to be released on the tap.
3183 @item @b{reset-deassert-post}
3184 @* Issued as part of @command{reset} processing
3185 when SRST has been released on the tap.
3186 @item @b{reset-end}
3187 @* Issued as the final step in @command{reset} processing.
3188 @ignore
3189 @item @b{reset-halt-post}
3190 @* Currently not used
3191 @item @b{reset-halt-pre}
3192 @* Currently not used
3193 @end ignore
3194 @item @b{reset-init}
3195 @* Used by @b{reset init} command for board-specific initialization.
3196 This event fires after @emph{reset-deassert-post}.
3197
3198 This is where you would configure PLLs and clocking, set up DRAM so
3199 you can download programs that don't fit in on-chip SRAM, set up pin
3200 multiplexing, and so on.
3201 (You may be able to switch to a fast JTAG clock rate here, after
3202 the target clocks are fully set up.)
3203 @item @b{reset-start}
3204 @* Issued as part of @command{reset} processing
3205 before either SRST or TRST are activated.
3206
3207 This is the most robust place to switch to a low JTAG clock rate, if
3208 SRST disables PLLs needed to use a fast clock.
3209 @ignore
3210 @item @b{reset-wait-pos}
3211 @* Currently not used
3212 @item @b{reset-wait-pre}
3213 @* Currently not used
3214 @end ignore
3215 @item @b{resume-start}
3216 @* Before any target is resumed
3217 @item @b{resume-end}
3218 @* After all targets have resumed
3219 @item @b{resume-ok}
3220 @* Success
3221 @item @b{resumed}
3222 @* Target has resumed
3223 @end itemize
3224
3225
3226 @node Flash Commands
3227 @chapter Flash Commands
3228
3229 OpenOCD has different commands for NOR and NAND flash;
3230 the ``flash'' command works with NOR flash, while
3231 the ``nand'' command works with NAND flash.
3232 This partially reflects different hardware technologies:
3233 NOR flash usually supports direct CPU instruction and data bus access,
3234 while data from a NAND flash must be copied to memory before it can be
3235 used. (SPI flash must also be copied to memory before use.)
3236 However, the documentation also uses ``flash'' as a generic term;
3237 for example, ``Put flash configuration in board-specific files''.
3238
3239 Flash Steps:
3240 @enumerate
3241 @item Configure via the command @command{flash bank}
3242 @* Do this in a board-specific configuration file,
3243 passing parameters as needed by the driver.
3244 @item Operate on the flash via @command{flash subcommand}
3245 @* Often commands to manipulate the flash are typed by a human, or run
3246 via a script in some automated way. Common tasks include writing a
3247 boot loader, operating system, or other data.
3248 @item GDB Flashing
3249 @* Flashing via GDB requires the flash be configured via ``flash
3250 bank'', and the GDB flash features be enabled.
3251 @xref{GDB Configuration}.
3252 @end enumerate
3253
3254 Many CPUs have the ablity to ``boot'' from the first flash bank.
3255 This means that misprogramming that bank can ``brick'' a system,
3256 so that it can't boot.
3257 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
3258 board by (re)installing working boot firmware.
3259
3260 @anchor{NOR Configuration}
3261 @section Flash Configuration Commands
3262 @cindex flash configuration
3263
3264 @deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
3265 Configures a flash bank which provides persistent storage
3266 for addresses from @math{base} to @math{base + size - 1}.
3267 These banks will often be visible to GDB through the target's memory map.
3268 In some cases, configuring a flash bank will activate extra commands;
3269 see the driver-specific documentation.
3270
3271 @itemize @bullet
3272 @item @var{driver} ... identifies the controller driver
3273 associated with the flash bank being declared.
3274 This is usually @code{cfi} for external flash, or else
3275 the name of a microcontroller with embedded flash memory.
3276 @xref{Flash Driver List}.
3277 @item @var{base} ... Base address of the flash chip.
3278 @item @var{size} ... Size of the chip, in bytes.
3279 For some drivers, this value is detected from the hardware.
3280 @item @var{chip_width} ... Width of the flash chip, in bytes;
3281 ignored for most microcontroller drivers.
3282 @item @var{bus_width} ... Width of the data bus used to access the
3283 chip, in bytes; ignored for most microcontroller drivers.
3284 @item @var{target} ... Names the target used to issue
3285 commands to the flash controller.
3286 @comment Actually, it's currently a controller-specific parameter...
3287 @item @var{driver_options} ... drivers may support, or require,
3288 additional parameters. See the driver-specific documentation
3289 for more information.
3290 @end itemize
3291 @quotation Note
3292 This command is not available after OpenOCD initialization has completed.
3293 Use it in board specific configuration files, not interactively.
3294 @end quotation
3295 @end deffn
3296
3297 @comment the REAL name for this command is "ocd_flash_banks"
3298 @comment less confusing would be: "flash list" (like "nand list")
3299 @deffn Command {flash banks}
3300 Prints a one-line summary of each device declared
3301 using @command{flash bank}, numbered from zero.
3302 Note that this is the @emph{plural} form;
3303 the @emph{singular} form is a very different command.
3304 @end deffn
3305
3306 @deffn Command {flash probe} num
3307 Identify the flash, or validate the parameters of the configured flash. Operation
3308 depends on the flash type.
3309 The @var{num} parameter is a value shown by @command{flash banks}.
3310 Most flash commands will implicitly @emph{autoprobe} the bank;
3311 flash drivers can distinguish between probing and autoprobing,
3312 but most don't bother.
3313 @end deffn
3314
3315 @section Erasing, Reading, Writing to Flash
3316 @cindex flash erasing
3317 @cindex flash reading
3318 @cindex flash writing
3319 @cindex flash programming
3320
3321 One feature distinguishing NOR flash from NAND or serial flash technologies
3322 is that for read access, it acts exactly like any other addressible memory.
3323 This means you can use normal memory read commands like @command{mdw} or
3324 @command{dump_image} with it, with no special @command{flash} subcommands.
3325 @xref{Memory access}, and @ref{Image access}.
3326
3327 Write access works differently. Flash memory normally needs to be erased
3328 before it's written. Erasing a sector turns all of its bits to ones, and
3329 writing can turn ones into zeroes. This is why there are special commands
3330 for interactive erasing and writing, and why GDB needs to know which parts
3331 of the address space hold NOR flash memory.
3332
3333 @quotation Note
3334 Most of these erase and write commands leverage the fact that NOR flash
3335 chips consume target address space. They implicitly refer to the current
3336 JTAG target, and map from an address in that target's address space
3337 back to a flash bank.
3338 @comment In May 2009, those mappings may fail if any bank associated
3339 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
3340 A few commands use abstract addressing based on bank and sector numbers,
3341 and don't depend on searching the current target and its address space.
3342 Avoid confusing the two command models.
3343 @end quotation
3344
3345 Some flash chips implement software protection against accidental writes,
3346 since such buggy writes could in some cases ``brick'' a system.
3347 For such systems, erasing and writing may require sector protection to be
3348 disabled first.
3349 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
3350 and AT91SAM7 on-chip flash.
3351 @xref{flash protect}.
3352
3353 @anchor{flash erase_sector}
3354 @deffn Command {flash erase_sector} num first last
3355 Erase sectors in bank @var{num}, starting at sector @var{first}
3356 up to and including @var{last}.
3357 Sector numbering starts at 0.
3358 Providing a @var{last} sector of @option{last}
3359 specifies "to the end of the flash bank".
3360 The @var{num} parameter is a value shown by @command{flash banks}.
3361 @end deffn
3362
3363 @deffn Command {flash erase_address} address length
3364 Erase sectors starting at @var{address} for @var{length} bytes.
3365 The flash bank to use is inferred from the @var{address}, and
3366 the specified length must stay within that bank.
3367 As a special case, when @var{length} is zero and @var{address} is
3368 the start of the bank, the whole flash is erased.
3369 @end deffn
3370
3371 @deffn Command {flash fillw} address word length
3372 @deffnx Command {flash fillh} address halfword length
3373 @deffnx Command {flash fillb} address byte length
3374 Fills flash memory with the specified @var{word} (32 bits),
3375 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3376 starting at @var{address} and continuing
3377 for @var{length} units (word/halfword/byte).
3378 No erasure is done before writing; when needed, that must be done
3379 before issuing this command.
3380 Writes are done in blocks of up to 1024 bytes, and each write is
3381 verified by reading back the data and comparing it to what was written.
3382 The flash bank to use is inferred from the @var{address} of
3383 each block, and the specified length must stay within that bank.
3384 @end deffn
3385 @comment no current checks for errors if fill blocks touch multiple banks!
3386
3387 @anchor{flash write_bank}
3388 @deffn Command {flash write_bank} num filename offset
3389 Write the binary @file{filename} to flash bank @var{num},
3390 starting at @var{offset} bytes from the beginning of the bank.
3391 The @var{num} parameter is a value shown by @command{flash banks}.
3392 @end deffn
3393
3394 @anchor{flash write_image}
3395 @deffn Command {flash write_image} [erase] filename [offset] [type]
3396 Write the image @file{filename} to the current target's flash bank(s).
3397 A relocation @var{offset} may be specified, in which case it is added
3398 to the base address for each section in the image.
3399 The file [@var{type}] can be specified
3400 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
3401 @option{elf} (ELF file), @option{s19} (Motorola s19).
3402 @option{mem}, or @option{builder}.
3403 The relevant flash sectors will be erased prior to programming
3404 if the @option{erase} parameter is given.
3405 The flash bank to use is inferred from the @var{address} of
3406 each image segment.
3407 @end deffn
3408
3409 @section Other Flash commands
3410 @cindex flash protection
3411
3412 @deffn Command {flash erase_check} num
3413 Check erase state of sectors in flash bank @var{num},
3414 and display that status.
3415 The @var{num} parameter is a value shown by @command{flash banks}.
3416 This is the only operation that
3417 updates the erase state information displayed by @option{flash info}. That means you have
3418 to issue a @command{flash erase_check} command after erasing or programming the device
3419 to get updated information.
3420 (Code execution may have invalidated any state records kept by OpenOCD.)
3421 @end deffn
3422
3423 @deffn Command {flash info} num
3424 Print info about flash bank @var{num}
3425 The @var{num} parameter is a value shown by @command{flash banks}.
3426 The information includes per-sector protect status.
3427 @end deffn
3428
3429 @anchor{flash protect}
3430 @deffn Command {flash protect} num first last (@option{on}|@option{off})
3431 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
3432 in flash bank @var{num}, starting at sector @var{first}
3433 and continuing up to and including @var{last}.
3434 Providing a @var{last} sector of @option{last}
3435 specifies "to the end of the flash bank".
3436 The @var{num} parameter is a value shown by @command{flash banks}.
3437 @end deffn
3438
3439 @deffn Command {flash protect_check} num
3440 Check protection state of sectors in flash bank @var{num}.
3441 The @var{num} parameter is a value shown by @command{flash banks}.
3442 @comment @option{flash erase_sector} using the same syntax.
3443 @end deffn
3444
3445 @anchor{Flash Driver List}
3446 @section Flash Drivers, Options, and Commands
3447 As noted above, the @command{flash bank} command requires a driver name,
3448 and allows driver-specific options and behaviors.
3449 Some drivers also activate driver-specific commands.
3450
3451 @subsection External Flash
3452
3453 @deffn {Flash Driver} cfi
3454 @cindex Common Flash Interface
3455 @cindex CFI
3456 The ``Common Flash Interface'' (CFI) is the main standard for
3457 external NOR flash chips, each of which connects to a
3458 specific external chip select on the CPU.
3459 Frequently the first such chip is used to boot the system.
3460 Your board's @code{reset-init} handler might need to
3461 configure additional chip selects using other commands (like: @command{mww} to
3462 configure a bus and its timings) , or
3463 perhaps configure a GPIO pin that controls the ``write protect'' pin
3464 on the flash chip.
3465 The CFI driver can use a target-specific working area to significantly
3466 speed up operation.
3467
3468 The CFI driver can accept the following optional parameters, in any order:
3469
3470 @itemize
3471 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
3472 like AM29LV010 and similar types.
3473 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
3474 @end itemize
3475
3476 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
3477 wide on a sixteen bit bus:
3478
3479 @example
3480 flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
3481 flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
3482 @end example
3483 @c "cfi part_id" disabled
3484 @end deffn
3485
3486 @subsection Internal Flash (Microcontrollers)
3487
3488 @deffn {Flash Driver} aduc702x
3489 The ADUC702x analog microcontrollers from Analog Devices
3490 include internal flash and use ARM7TDMI cores.
3491 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
3492 The setup command only requires the @var{target} argument
3493 since all devices in this family have the same memory layout.
3494
3495 @example
3496 flash bank aduc702x 0 0 0 0 $_TARGETNAME
3497 @end example
3498 @end deffn
3499
3500 @deffn {Flash Driver} at91sam3
3501 @cindex at91sam3
3502 All members of the AT91SAM3 microcontroller family from
3503 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
3504 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
3505 that the driver was orginaly developed and tested using the
3506 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
3507 the family was cribbed from the data sheet. @emph{Note to future
3508 readers/updaters: Please remove this worrysome comment after other
3509 chips are confirmed.}
3510
3511 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
3512 have one flash bank. In all cases the flash banks are at
3513 the following fixed locations:
3514
3515 @example
3516 # Flash bank 0 - all chips
3517 flash bank at91sam3 0x00080000 0 1 1 $_TARGETNAME
3518 # Flash bank 1 - only 256K chips
3519 flash bank at91sam3 0x00100000 0 1 1 $_TARGETNAME
3520 @end example
3521
3522 Internally, the AT91SAM3 flash memory is organized as follows.
3523 Unlike the AT91SAM7 chips, these are not used as parameters
3524 to the @command{flash bank} command:
3525
3526 @itemize
3527 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
3528 @item @emph{Bank Size:} 128K/64K Per flash bank
3529 @item @emph{Sectors:} 16 or 8 per bank
3530 @item @emph{SectorSize:} 8K Per Sector
3531 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
3532 @end itemize
3533
3534 The AT91SAM3 driver adds some additional commands:
3535
3536 @deffn Command {at91sam3 gpnvm}
3537 @deffnx Command {at91sam3 gpnvm clear} number
3538 @deffnx Command {at91sam3 gpnvm set} number
3539 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
3540 With no parameters, @command{show} or @command{show all},
3541 shows the status of all GPNVM bits.
3542 With @command{show} @var{number}, displays that bit.
3543
3544 With @command{set} @var{number} or @command{clear} @var{number},
3545 modifies that GPNVM bit.
3546 @end deffn
3547
3548 @deffn Command {at91sam3 info}
3549 This command attempts to display information about the AT91SAM3
3550 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
3551 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
3552 document id: doc6430A] and decodes the values. @emph{Second} it reads the
3553 various clock configuration registers and attempts to display how it
3554 believes the chip is configured. By default, the SLOWCLK is assumed to
3555 be 32768 Hz, see the command @command{at91sam3 slowclk}.
3556 @end deffn
3557
3558 @deffn Command {at91sam3 slowclk} [value]
3559 This command shows/sets the slow clock frequency used in the
3560 @command{at91sam3 info} command calculations above.
3561 @end deffn
3562 @end deffn
3563
3564 @deffn {Flash Driver} at91sam7
3565 All members of the AT91SAM7 microcontroller family from Atmel include
3566 internal flash and use ARM7TDMI cores. The driver automatically
3567 recognizes a number of these chips using the chip identification
3568 register, and autoconfigures itself.
3569
3570 @example
3571 flash bank at91sam7 0 0 0 0 $_TARGETNAME
3572 @end example
3573
3574 For chips which are not recognized by the controller driver, you must
3575 provide additional parameters in the following order:
3576
3577 @itemize
3578 @item @var{chip_model} ... label used with @command{flash info}
3579 @item @var{banks}
3580 @item @var{sectors_per_bank}
3581 @item @var{pages_per_sector}
3582 @item @var{pages_size}
3583 @item @var{num_nvm_bits}
3584 @item @var{freq_khz} ... required if an external clock is provided,
3585 optional (but recommended) when the oscillator frequency is known
3586 @end itemize
3587
3588 It is recommended that you provide zeroes for all of those values
3589 except the clock frequency, so that everything except that frequency
3590 will be autoconfigured.
3591 Knowing the frequency helps ensure correct timings for flash access.
3592
3593 The flash controller handles erases automatically on a page (128/256 byte)
3594 basis, so explicit erase commands are not necessary for flash programming.
3595 However, there is an ``EraseAll`` command that can erase an entire flash
3596 plane (of up to 256KB), and it will be used automatically when you issue
3597 @command{flash erase_sector} or @command{flash erase_address} commands.
3598
3599 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
3600 Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
3601 bit for the processor. Each processor has a number of such bits,
3602 used for controlling features such as brownout detection (so they
3603 are not truly general purpose).
3604 @quotation Note
3605 This assumes that the first flash bank (number 0) is associated with
3606 the appropriate at91sam7 target.
3607 @end quotation
3608 @end deffn
3609 @end deffn
3610
3611 @deffn {Flash Driver} avr
3612 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
3613 @emph{The current implementation is incomplete.}
3614 @comment - defines mass_erase ... pointless given flash_erase_address
3615 @end deffn
3616
3617 @deffn {Flash Driver} ecosflash
3618 @emph{No idea what this is...}
3619 The @var{ecosflash} driver defines one mandatory parameter,
3620 the name of a modules of target code which is downloaded
3621 and executed.
3622 @end deffn
3623
3624 @deffn {Flash Driver} lpc2000
3625 Most members of the LPC1700 and LPC2000 microcontroller families from NXP
3626 include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
3627
3628 @quotation Note
3629 There are LPC2000 devices which are not supported by the @var{lpc2000}
3630 driver:
3631 The LPC2888 is supported by the @var{lpc288x} driver.
3632 The LPC29xx family is supported by the @var{lpc2900} driver.
3633 @end quotation
3634
3635 The @var{lpc2000} driver defines two mandatory and one optional parameters,
3636 which must appear in the following order:
3637
3638 @itemize
3639 @item @var{variant} ... required, may be
3640 @var{lpc2000_v1} (older LPC21xx and LPC22xx)
3641 @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
3642 or @var{lpc1700} (LPC175x and LPC176x)
3643 @item @var{clock_kHz} ... the frequency, in kiloHertz,
3644 at which the core is running
3645 @item @var{calc_checksum} ... optional (but you probably want to provide this!),
3646 telling the driver to calculate a valid checksum for the exception vector table.
3647 @end itemize
3648
3649 LPC flashes don't require the chip and bus width to be specified.
3650
3651 @example
3652 flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
3653 lpc2000_v2 14765 calc_checksum
3654 @end example
3655
3656 @deffn {Command} {lpc2000 part_id} bank
3657 Displays the four byte part identifier associated with
3658 the specified flash @var{bank}.
3659 @end deffn
3660 @end deffn
3661
3662 @deffn {Flash Driver} lpc288x
3663 The LPC2888 microcontroller from NXP needs slightly different flash
3664 support from its lpc2000 siblings.
3665 The @var{lpc288x} driver defines one mandatory parameter,
3666 the programming clock rate in Hz.
3667 LPC flashes don't require the chip and bus width to be specified.
3668
3669 @example
3670 flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
3671 @end example
3672 @end deffn
3673
3674 @deffn {Flash Driver} lpc2900
3675 This driver supports the LPC29xx ARM968E based microcontroller family
3676 from NXP.
3677
3678 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
3679 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
3680 sector layout are auto-configured by the driver.
3681 The driver has one additional mandatory parameter: The CPU clock rate
3682 (in kHz) at the time the flash operations will take place. Most of the time this
3683 will not be the crystal frequency, but a higher PLL frequency. The
3684 @code{reset-init} event handler in the board script is usually the place where
3685 you start the PLL.
3686
3687 The driver rejects flashless devices (currently the LPC2930).
3688
3689 The EEPROM in LPC2900 devices is not mapped directly into the address space.
3690 It must be handled much more like NAND flash memory, and will therefore be
3691 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
3692
3693 Sector protection in terms of the LPC2900 is handled transparently. Every time a
3694 sector needs to be erased or programmed, it is automatically unprotected.
3695 What is shown as protection status in the @code{flash info} command, is
3696 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
3697 sector from ever being erased or programmed again. As this is an irreversible
3698 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
3699 and not by the standard @code{flash protect} command.
3700
3701 Example for a 125 MHz clock frequency:
3702 @example
3703 flash bank lpc2900 0 0 0 0 $_TARGETNAME 125000
3704 @end example
3705
3706 Some @code{lpc2900}-specific commands are defined. In the following command list,
3707 the @var{bank} parameter is the bank number as obtained by the
3708 @code{flash banks} command.
3709
3710 @deffn Command {lpc2900 signature} bank
3711 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
3712 content. This is a hardware feature of the flash block, hence the calculation is
3713 very fast. You may use this to verify the content of a programmed device against
3714 a known signature.
3715 Example:
3716 @example
3717 lpc2900 signature 0
3718 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
3719 @end example
3720 @end deffn
3721
3722 @deffn Command {lpc2900 read_custom} bank filename
3723 Reads the 912 bytes of customer information from the flash index sector, and
3724 saves it to a file in binary format.
3725 Example:
3726 @example
3727 lpc2900 read_custom 0 /path_to/customer_info.bin
3728 @end example
3729 @end deffn
3730
3731 The index sector of the flash is a @emph{write-only} sector. It cannot be
3732 erased! In order to guard against unintentional write access, all following
3733 commands need to be preceeded by a successful call to the @code{password}
3734 command:
3735
3736 @deffn Command {lpc2900 password} bank password
3737 You need to use this command right before each of the following commands:
3738 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
3739 @code{lpc2900 secure_jtag}.
3740
3741 The password string is fixed to "I_know_what_I_am_doing".
3742 Example:
3743 @example
3744 lpc2900 password 0 I_know_what_I_am_doing
3745 Potentially dangerous operation allowed in next command!
3746 @end example
3747 @end deffn
3748
3749 @deffn Command {lpc2900 write_custom} bank filename type
3750 Writes the content of the file into the customer info space of the flash index
3751 sector. The filetype can be specified with the @var{type} field. Possible values
3752 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
3753 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
3754 contain a single section, and the contained data length must be exactly
3755 912 bytes.
3756 @quotation Attention
3757 This cannot be reverted! Be careful!
3758 @end quotation
3759 Example:
3760 @example
3761 lpc2900 write_custom 0 /path_to/customer_info.bin bin
3762 @end example
3763 @end deffn
3764
3765 @deffn Command {lpc2900 secure_sector} bank first last
3766 Secures the sector range from @var{first} to @var{last} (including) against
3767 further program and erase operations. The sector security will be effective
3768 after the next power cycle.
3769 @quotation Attention
3770 This cannot be reverted! Be careful!
3771 @end quotation
3772 Secured sectors appear as @emph{protected} in the @code{flash info} command.
3773 Example:
3774 @example
3775 lpc2900 secure_sector 0 1 1
3776 flash info 0
3777 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
3778 # 0: 0x00000000 (0x2000 8kB) not protected
3779 # 1: 0x00002000 (0x2000 8kB) protected
3780 # 2: 0x00004000 (0x2000 8kB) not protected
3781 @end example
3782 @end deffn
3783
3784 @deffn Command {lpc2900 secure_jtag} bank
3785 Irreversibly disable the JTAG port. The new JTAG security setting will be
3786 effective after the next power cycle.
3787 @quotation Attention
3788 This cannot be reverted! Be careful!
3789 @end quotation
3790 Examples:
3791 @example
3792 lpc2900 secure_jtag 0
3793 @end example
3794 @end deffn
3795 @end deffn
3796
3797 @deffn {Flash Driver} ocl
3798 @emph{No idea what this is, other than using some arm7/arm9 core.}
3799
3800 @example
3801 flash bank ocl 0 0 0 0 $_TARGETNAME
3802 @end example
3803 @end deffn
3804
3805 @deffn {Flash Driver} pic32mx
3806 The PIC32MX microcontrollers are based on the MIPS 4K cores,
3807 and integrate flash memory.
3808 @emph{The current implementation is incomplete.}
3809
3810 @example
3811 flash bank pix32mx 0 0 0 0 $_TARGETNAME
3812 @end example
3813
3814 @comment numerous *disabled* commands are defined:
3815 @comment - chip_erase ... pointless given flash_erase_address
3816 @comment - lock, unlock ... pointless given protect on/off (yes?)
3817 @comment - pgm_word ... shouldn't bank be deduced from address??
3818 Some pic32mx-specific commands are defined:
3819 @deffn Command {pic32mx pgm_word} address value bank
3820 Programs the specified 32-bit @var{value} at the given @var{address}
3821 in the specified chip @var{bank}.
3822 @end deffn
3823 @end deffn
3824
3825 @deffn {Flash Driver} stellaris
3826 All members of the Stellaris LM3Sxxx microcontroller family from
3827 Texas Instruments
3828 include internal flash and use ARM Cortex M3 cores.
3829 The driver automatically recognizes a number of these chips using
3830 the chip identification register, and autoconfigures itself.
3831 @footnote{Currently there is a @command{stellaris mass_erase} command.
3832 That seems pointless since the same effect can be had using the
3833 standard @command{flash erase_address} command.}
3834
3835 @example
3836 flash bank stellaris 0 0 0 0 $_TARGETNAME
3837 @end example
3838 @end deffn
3839
3840 @deffn {Flash Driver} stm32x
3841 All members of the STM32 microcontroller family from ST Microelectronics
3842 include internal flash and use ARM Cortex M3 cores.
3843 The driver automatically recognizes a number of these chips using
3844 the chip identification register, and autoconfigures itself.
3845
3846 @example
3847 flash bank stm32x 0 0 0 0 $_TARGETNAME
3848 @end example
3849
3850 Some stm32x-specific commands
3851 @footnote{Currently there is a @command{stm32x mass_erase} command.
3852 That seems pointless since the same effect can be had using the
3853 standard @command{flash erase_address} command.}
3854 are defined:
3855
3856 @deffn Command {stm32x lock} num
3857 Locks the entire stm32 device.
3858 The @var{num} parameter is a value shown by @command{flash banks}.
3859 @end deffn
3860
3861 @deffn Command {stm32x unlock} num
3862 Unlocks the entire stm32 device.
3863 The @var{num} parameter is a value shown by @command{flash banks}.
3864 @end deffn
3865
3866 @deffn Command {stm32x options_read} num
3867 Read and display the stm32 option bytes written by
3868 the @command{stm32x options_write} command.
3869 The @var{num} parameter is a value shown by @command{flash banks}.
3870 @end deffn
3871
3872 @deffn Command {stm32x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
3873 Writes the stm32 option byte with the specified values.
3874 The @var{num} parameter is a value shown by @command{flash banks}.
3875 @end deffn
3876 @end deffn
3877
3878 @deffn {Flash Driver} str7x
3879 All members of the STR7 microcontroller family from ST Microelectronics
3880 include internal flash and use ARM7TDMI cores.
3881 The @var{str7x} driver defines one mandatory parameter, @var{variant},
3882 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
3883
3884 @example
3885 flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
3886 @end example
3887
3888 @deffn Command {str7x disable_jtag} bank
3889 Activate the Debug/Readout protection mechanism
3890 for the specified flash bank.
3891 @end deffn
3892 @end deffn
3893
3894 @deffn {Flash Driver} str9x
3895 Most members of the STR9 microcontroller family from ST Microelectronics
3896 include internal flash and use ARM966E cores.
3897 The str9 needs the flash controller to be configured using
3898 the @command{str9x flash_config} command prior to Flash programming.
3899
3900 @example
3901 flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
3902 str9x flash_config 0 4 2 0 0x80000
3903 @end example
3904
3905 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
3906 Configures the str9 flash controller.
3907 The @var{num} parameter is a value shown by @command{flash banks}.
3908
3909 @itemize @bullet
3910 @item @var{bbsr} - Boot Bank Size register
3911 @item @var{nbbsr} - Non Boot Bank Size register
3912 @item @var{bbadr} - Boot Bank Start Address register
3913 @item @var{nbbadr} - Boot Bank Start Address register
3914 @end itemize
3915 @end deffn
3916
3917 @end deffn
3918
3919 @deffn {Flash Driver} tms470
3920 Most members of the TMS470 microcontroller family from Texas Instruments
3921 include internal flash and use ARM7TDMI cores.
3922 This driver doesn't require the chip and bus width to be specified.
3923
3924 Some tms470-specific commands are defined:
3925
3926 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
3927 Saves programming keys in a register, to enable flash erase and write commands.
3928 @end deffn
3929
3930 @deffn Command {tms470 osc_mhz} clock_mhz
3931 Reports the clock speed, which is used to calculate timings.
3932 @end deffn
3933
3934 @deffn Command {tms470 plldis} (0|1)
3935 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
3936 the flash clock.
3937 @end deffn
3938 @end deffn
3939
3940 @subsection str9xpec driver
3941 @cindex str9xpec
3942
3943 Here is some background info to help
3944 you better understand how this driver works. OpenOCD has two flash drivers for
3945 the str9:
3946 @enumerate
3947 @item
3948 Standard driver @option{str9x} programmed via the str9 core. Normally used for
3949 flash programming as it is faster than the @option{str9xpec} driver.
3950 @item
3951 Direct programming @option{str9xpec} using the flash controller. This is an
3952 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
3953 core does not need to be running to program using this flash driver. Typical use
3954 for this driver is locking/unlocking the target and programming the option bytes.
3955 @end enumerate
3956
3957 Before we run any commands using the @option{str9xpec} driver we must first disable
3958 the str9 core. This example assumes the @option{str9xpec} driver has been
3959 configured for flash bank 0.
3960 @example
3961 # assert srst, we do not want core running
3962 # while accessing str9xpec flash driver
3963 jtag_reset 0 1
3964 # turn off target polling
3965 poll off
3966 # disable str9 core
3967 str9xpec enable_turbo 0
3968 # read option bytes
3969 str9xpec options_read 0
3970 # re-enable str9 core
3971 str9xpec disable_turbo 0
3972 poll on
3973 reset halt
3974 @end example
3975 The above example will read the str9 option bytes.
3976 When performing a unlock remember that you will not be able to halt the str9 - it
3977 has been locked. Halting the core is not required for the @option{str9xpec} driver
3978 as mentioned above, just issue the commands above manually or from a telnet prompt.
3979
3980 @deffn {Flash Driver} str9xpec
3981 Only use this driver for locking/unlocking the device or configuring the option bytes.
3982 Use the standard str9 driver for programming.
3983 Before using the flash commands the turbo mode must be enabled using the
3984 @command{str9xpec enable_turbo} command.
3985
3986 Several str9xpec-specific commands are defined:
3987
3988 @deffn Command {str9xpec disable_turbo} num
3989 Restore the str9 into JTAG chain.
3990 @end deffn
3991
3992 @deffn Command {str9xpec enable_turbo} num
3993 Enable turbo mode, will simply remove the str9 from the chain and talk
3994 directly to the embedded flash controller.
3995 @end deffn
3996
3997 @deffn Command {str9xpec lock} num
3998 Lock str9 device. The str9 will only respond to an unlock command that will
3999 erase the device.
4000 @end deffn
4001
4002 @deffn Command {str9xpec part_id} num
4003 Prints the part identifier for bank @var{num}.
4004 @end deffn
4005
4006 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
4007 Configure str9 boot bank.
4008 @end deffn
4009
4010 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
4011 Configure str9 lvd source.
4012 @end deffn
4013
4014 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
4015 Configure str9 lvd threshold.
4016 @end deffn
4017
4018 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
4019 Configure str9 lvd reset warning source.
4020 @end deffn
4021
4022 @deffn Command {str9xpec options_read} num
4023 Read str9 option bytes.
4024 @end deffn
4025
4026 @deffn Command {str9xpec options_write} num
4027 Write str9 option bytes.
4028 @end deffn
4029
4030 @deffn Command {str9xpec unlock} num
4031 unlock str9 device.
4032 @end deffn
4033
4034 @end deffn
4035
4036
4037 @section mFlash
4038
4039 @subsection mFlash Configuration
4040 @cindex mFlash Configuration
4041
4042 @deffn {Config Command} {mflash bank} soc base RST_pin target
4043 Configures a mflash for @var{soc} host bank at
4044 address @var{base}.
4045 The pin number format depends on the host GPIO naming convention.
4046 Currently, the mflash driver supports s3c2440 and pxa270.
4047
4048 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
4049
4050 @example
4051 mflash bank s3c2440 0x10000000 1b 0
4052 @end example
4053
4054 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
4055
4056 @example
4057 mflash bank pxa270 0x08000000 43 0
4058 @end example
4059 @end deffn
4060
4061 @subsection mFlash commands
4062 @cindex mFlash commands
4063
4064 @deffn Command {mflash config pll} frequency
4065 Configure mflash PLL.
4066 The @var{frequency} is the mflash input frequency, in Hz.
4067 Issuing this command will erase mflash's whole internal nand and write new pll.
4068 After this command, mflash needs power-on-reset for normal operation.
4069 If pll was newly configured, storage and boot(optional) info also need to be update.
4070 @end deffn
4071
4072 @deffn Command {mflash config boot}
4073 Configure bootable option.
4074 If bootable option is set, mflash offer the first 8 sectors
4075 (4kB) for boot.
4076 @end deffn
4077
4078 @deffn Command {mflash config storage}
4079 Configure storage information.
4080 For the normal storage operation, this information must be
4081 written.
4082 @end deffn
4083
4084 @deffn Command {mflash dump} num filename offset size
4085 Dump @var{size} bytes, starting at @var{offset} bytes from the
4086 beginning of the bank @var{num}, to the file named @var{filename}.
4087 @end deffn
4088
4089 @deffn Command {mflash probe}
4090 Probe mflash.
4091 @end deffn
4092
4093 @deffn Command {mflash write} num filename offset
4094 Write the binary file @var{filename} to mflash bank @var{num}, starting at
4095 @var{offset} bytes from the beginning of the bank.
4096 @end deffn
4097
4098 @node NAND Flash Commands
4099 @chapter NAND Flash Commands
4100 @cindex NAND
4101
4102 Compared to NOR or SPI flash, NAND devices are inexpensive
4103 and high density. Today's NAND chips, and multi-chip modules,
4104 commonly hold multiple GigaBytes of data.
4105
4106 NAND chips consist of a number of ``erase blocks'' of a given
4107 size (such as 128 KBytes), each of which is divided into a
4108 number of pages (of perhaps 512 or 2048 bytes each). Each
4109 page of a NAND flash has an ``out of band'' (OOB) area to hold
4110 Error Correcting Code (ECC) and other metadata, usually 16 bytes
4111 of OOB for every 512 bytes of page data.
4112
4113 One key characteristic of NAND flash is that its error rate
4114 is higher than that of NOR flash. In normal operation, that
4115 ECC is used to correct and detect errors. However, NAND
4116 blocks can also wear out and become unusable; those blocks
4117 are then marked "bad". NAND chips are even shipped from the
4118 manufacturer with a few bad blocks. The highest density chips
4119 use a technology (MLC) that wears out more quickly, so ECC
4120 support is increasingly important as a way to detect blocks
4121 that have begun to fail, and help to preserve data integrity
4122 with techniques such as wear leveling.
4123
4124 Software is used to manage the ECC. Some controllers don't
4125 support ECC directly; in those cases, software ECC is used.
4126 Other controllers speed up the ECC calculations with hardware.
4127 Single-bit error correction hardware is routine. Controllers
4128 geared for newer MLC chips may correct 4 or more errors for
4129 every 512 bytes of data.
4130
4131 You will need to make sure that any data you write using
4132 OpenOCD includes the apppropriate kind of ECC. For example,
4133 that may mean passing the @code{oob_softecc} flag when
4134 writing NAND data, or ensuring that the correct hardware
4135 ECC mode is used.
4136
4137 The basic steps for using NAND devices include:
4138 @enumerate
4139 @item Declare via the command @command{nand device}
4140 @* Do this in a board-specific configuration file,
4141 passing parameters as needed by the controller.
4142 @item Configure each device using @command{nand probe}.
4143 @* Do this only after the associated target is set up,
4144 such as in its reset-init script or in procures defined
4145 to access that device.
4146 @item Operate on the flash via @command{nand subcommand}
4147 @* Often commands to manipulate the flash are typed by a human, or run
4148 via a script in some automated way. Common task include writing a
4149 boot loader, operating system, or other data needed to initialize or
4150 de-brick a board.
4151 @end enumerate
4152
4153 @b{NOTE:} At the time this text was written, the largest NAND
4154 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
4155 This is because the variables used to hold offsets and lengths
4156 are only 32 bits wide.
4157 (Larger chips may work in some cases, unless an offset or length
4158 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
4159 Some larger devices will work, since they are actually multi-chip
4160 modules with two smaller chips and individual chipselect lines.
4161
4162 @anchor{NAND Configuration}
4163 @section NAND Configuration Commands
4164 @cindex NAND configuration
4165
4166 NAND chips must be declared in configuration scripts,
4167 plus some additional configuration that's done after
4168 OpenOCD has initialized.
4169
4170 @deffn {Config Command} {nand device} controller target [configparams...]
4171 Declares a NAND device, which can be read and written to
4172 after it has been configured through @command{nand probe}.
4173 In OpenOCD, devices are single chips; this is unlike some
4174 operating systems, which may manage multiple chips as if
4175 they were a single (larger) device.
4176 In some cases, configuring a device will activate extra
4177 commands; see the controller-specific documentation.
4178
4179 @b{NOTE:} This command is not available after OpenOCD
4180 initialization has completed. Use it in board specific
4181 configuration files, not interactively.
4182
4183 @itemize @bullet
4184 @item @var{controller} ... identifies the controller driver
4185 associated with the NAND device being declared.
4186 @xref{NAND Driver List}.
4187 @item @var{target} ... names the target used when issuing
4188 commands to the NAND controller.
4189 @comment Actually, it's currently a controller-specific parameter...
4190 @item @var{configparams} ... controllers may support, or require,
4191 additional parameters. See the controller-specific documentation
4192 for more information.
4193 @end itemize
4194 @end deffn
4195
4196 @deffn Command {nand list}
4197 Prints a summary of each device declared
4198 using @command{nand device}, numbered from zero.
4199 Note that un-probed devices show no details.
4200 @example
4201 > nand list
4202 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
4203 blocksize: 131072, blocks: 8192
4204 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
4205 blocksize: 131072, blocks: 8192
4206 >