doc: add missing ulink v1 to supported interfaces
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
11
12 @include version.texi
13
14 @copying
15
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
20
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
28
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
38
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
45
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
50
51 @summarycontents
52 @contents
53
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
57
58 @insertcopying
59 @end ifnottex
60
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * TFTP:: TFTP
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
87
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
94 @end menu
95
96 @node About
97 @unnumbered About
98 @cindex about
99
100 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
101 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
104 around the world.
105
106 @section What is OpenOCD?
107 @cindex TAP
108 @cindex JTAG
109
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
112 devices.
113
114 It does so with the assistance of a @dfn{debug adapter}, which is
115 a small hardware module which helps provide the right kind of
116 electrical signaling to the target being debugged. These are
117 required since the debug host (on which OpenOCD runs) won't
118 usually have native support for such signaling, or the connector
119 needed to hook up to the target.
120
121 Such debug adapters support one or more @dfn{transport} protocols,
122 each of which involves different electrical signaling (and uses
123 different messaging protocols on top of that signaling). There
124 are many types of debug adapter, and little uniformity in what
125 they are called. (There are also product naming differences.)
126
127 These adapters are sometimes packaged as discrete dongles, which
128 may generically be called @dfn{hardware interface dongles}.
129 Some development boards also integrate them directly, which may
130 let the development board can be directly connected to the debug
131 host over USB (and sometimes also to power it over USB).
132
133 For example, a @dfn{JTAG Adapter} supports JTAG
134 signaling, and is used to communicate
135 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
136 A @dfn{TAP} is a ``Test Access Port'', a module which processes
137 special instructions and data. TAPs are daisy-chained within and
138 between chips and boards. JTAG supports debugging and boundary
139 scan operations.
140
141 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
142 signaling to communicate with some newer ARM cores, as well as debug
143 adapters which support both JTAG and SWD transports. SWD only supports
144 debugging, whereas JTAG also supports boundary scan operations.
145
146 For some chips, there are also @dfn{Programming Adapters} supporting
147 special transports used only to write code to flash memory, without
148 support for on-chip debugging or boundary scan.
149 (At this writing, OpenOCD does not support such non-debug adapters.)
150
151
152 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
153 based, parallel port based, and other standalone boxes that run
154 OpenOCD internally. @xref{Debug Adapter Hardware}.
155
156 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
157 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
158 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
159 debugged via the GDB protocol.
160
161 @b{Flash Programing:} Flash writing is supported for external CFI
162 compatible NOR flashes (Intel and AMD/Spansion command set) and several
163 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
164 STM32x). Preliminary support for various NAND flash controllers
165 (LPC3180, Orion, S3C24xx, more) controller is included.
166
167 @section OpenOCD Web Site
168
169 The OpenOCD web site provides the latest public news from the community:
170
171 @uref{http://openocd.sourceforge.net/}
172
173 @section Latest User's Guide:
174
175 The user's guide you are now reading may not be the latest one
176 available. A version for more recent code may be available.
177 Its HTML form is published irregularly at:
178
179 @uref{http://openocd.sourceforge.net/doc/html/index.html}
180
181 PDF form is likewise published at:
182
183 @uref{http://openocd.sourceforge.net/doc/pdf/openocd.pdf}
184
185 @section OpenOCD User's Forum
186
187 There is an OpenOCD forum (phpBB) hosted by SparkFun,
188 which might be helpful to you. Note that if you want
189 anything to come to the attention of developers, you
190 should post it to the OpenOCD Developer Mailing List
191 instead of this forum.
192
193 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
194
195
196 @node Developers
197 @chapter OpenOCD Developer Resources
198 @cindex developers
199
200 If you are interested in improving the state of OpenOCD's debugging and
201 testing support, new contributions will be welcome. Motivated developers
202 can produce new target, flash or interface drivers, improve the
203 documentation, as well as more conventional bug fixes and enhancements.
204
205 The resources in this chapter are available for developers wishing to explore
206 or expand the OpenOCD source code.
207
208 @section OpenOCD GIT Repository
209
210 During the 0.3.x release cycle, OpenOCD switched from Subversion to
211 a GIT repository hosted at SourceForge. The repository URL is:
212
213 @uref{git://openocd.git.sourceforge.net/gitroot/openocd/openocd}
214
215 You may prefer to use a mirror and the HTTP protocol:
216
217 @uref{http://repo.or.cz/r/openocd.git}
218
219 With standard GIT tools, use @command{git clone} to initialize
220 a local repository, and @command{git pull} to update it.
221 There are also gitweb pages letting you browse the repository
222 with a web browser, or download arbitrary snapshots without
223 needing a GIT client:
224
225 @uref{http://openocd.git.sourceforge.net/git/gitweb.cgi?p=openocd/openocd}
226
227 @uref{http://repo.or.cz/w/openocd.git}
228
229 The @file{README} file contains the instructions for building the project
230 from the repository or a snapshot.
231
232 Developers that want to contribute patches to the OpenOCD system are
233 @b{strongly} encouraged to work against mainline.
234 Patches created against older versions may require additional
235 work from their submitter in order to be updated for newer releases.
236
237 @section Doxygen Developer Manual
238
239 During the 0.2.x release cycle, the OpenOCD project began
240 providing a Doxygen reference manual. This document contains more
241 technical information about the software internals, development
242 processes, and similar documentation:
243
244 @uref{http://openocd.sourceforge.net/doc/doxygen/html/index.html}
245
246 This document is a work-in-progress, but contributions would be welcome
247 to fill in the gaps. All of the source files are provided in-tree,
248 listed in the Doxyfile configuration in the top of the source tree.
249
250 @section OpenOCD Developer Mailing List
251
252 The OpenOCD Developer Mailing List provides the primary means of
253 communication between developers:
254
255 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
256
257 Discuss and submit patches to this list.
258 The @file{HACKING} file contains basic information about how
259 to prepare patches.
260
261 @section OpenOCD Bug Database
262
263 During the 0.4.x release cycle the OpenOCD project team began
264 using Trac for its bug database:
265
266 @uref{https://sourceforge.net/apps/trac/openocd}
267
268
269 @node Debug Adapter Hardware
270 @chapter Debug Adapter Hardware
271 @cindex dongles
272 @cindex FTDI
273 @cindex wiggler
274 @cindex zy1000
275 @cindex printer port
276 @cindex USB Adapter
277 @cindex RTCK
278
279 Defined: @b{dongle}: A small device that plugins into a computer and serves as
280 an adapter .... [snip]
281
282 In the OpenOCD case, this generally refers to @b{a small adapter} that
283 attaches to your computer via USB or the Parallel Printer Port. One
284 exception is the Zylin ZY1000, packaged as a small box you attach via
285 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
286 require any drivers to be installed on the developer PC. It also has
287 a built in web interface. It supports RTCK/RCLK or adaptive clocking
288 and has a built in relay to power cycle targets remotely.
289
290
291 @section Choosing a Dongle
292
293 There are several things you should keep in mind when choosing a dongle.
294
295 @enumerate
296 @item @b{Transport} Does it support the kind of communication that you need?
297 OpenOCD focusses mostly on JTAG. Your version may also support
298 other ways to communicate with target devices.
299 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
300 Does your dongle support it? You might need a level converter.
301 @item @b{Pinout} What pinout does your target board use?
302 Does your dongle support it? You may be able to use jumper
303 wires, or an "octopus" connector, to convert pinouts.
304 @item @b{Connection} Does your computer have the USB, printer, or
305 Ethernet port needed?
306 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
307 RTCK support? Also known as ``adaptive clocking''
308 @end enumerate
309
310 @section Stand alone Systems
311
312 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/33-zylin-zy1000-jtag-probe} Technically, not a
313 dongle, but a standalone box. The ZY1000 has the advantage that it does
314 not require any drivers installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built in relay to power cycle targets remotely.
317
318 @section USB FT2232 Based
319
320 There are many USB JTAG dongles on the market, many of them are based
321 on a chip from ``Future Technology Devices International'' (FTDI)
322 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
323 See: @url{http://www.ftdichip.com} for more information.
324 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
325 chips are starting to become available in JTAG adapters. (Adapters
326 using those high speed FT2232H chips may support adaptive clocking.)
327
328 The FT2232 chips are flexible enough to support some other
329 transport options, such as SWD or the SPI variants used to
330 program some chips. They have two communications channels,
331 and one can be used for a UART adapter at the same time the
332 other one is used to provide a debug adapter.
333
334 Also, some development boards integrate an FT2232 chip to serve as
335 a built-in low cost debug adapter and usb-to-serial solution.
336
337 @itemize @bullet
338 @item @b{usbjtag}
339 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
340 @item @b{jtagkey}
341 @* See: @url{http://www.amontec.com/jtagkey.shtml}
342 @item @b{jtagkey2}
343 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
344 @item @b{oocdlink}
345 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
346 @item @b{signalyzer}
347 @* See: @url{http://www.signalyzer.com}
348 @item @b{Stellaris Eval Boards}
349 @* See: @url{http://www.luminarymicro.com} - The Stellaris eval boards
350 bundle FT2232-based JTAG and SWD support, which can be used to debug
351 the Stellaris chips. Using separate JTAG adapters is optional.
352 These boards can also be used in a "pass through" mode as JTAG adapters
353 to other target boards, disabling the Stellaris chip.
354 @item @b{Luminary ICDI}
355 @* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug
356 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
357 Evaluation Kits. Like the non-detachable FT2232 support on the other
358 Stellaris eval boards, they can be used to debug other target boards.
359 @item @b{olimex-jtag}
360 @* See: @url{http://www.olimex.com}
361 @item @b{Flyswatter/Flyswatter2}
362 @* See: @url{http://www.tincantools.com}
363 @item @b{turtelizer2}
364 @* See:
365 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
366 @url{http://www.ethernut.de}
367 @item @b{comstick}
368 @* Link: @url{http://www.hitex.com/index.php?id=383}
369 @item @b{stm32stick}
370 @* Link @url{http://www.hitex.com/stm32-stick}
371 @item @b{axm0432_jtag}
372 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
373 to be available anymore as of April 2012.
374 @item @b{cortino}
375 @* Link @url{http://www.hitex.com/index.php?id=cortino}
376 @item @b{dlp-usb1232h}
377 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
378 @item @b{digilent-hs1}
379 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
380 @end itemize
381
382 @section USB-JTAG / Altera USB-Blaster compatibles
383
384 These devices also show up as FTDI devices, but are not
385 protocol-compatible with the FT2232 devices. They are, however,
386 protocol-compatible among themselves. USB-JTAG devices typically consist
387 of a FT245 followed by a CPLD that understands a particular protocol,
388 or emulate this protocol using some other hardware.
389
390 They may appear under different USB VID/PID depending on the particular
391 product. The driver can be configured to search for any VID/PID pair
392 (see the section on driver commands).
393
394 @itemize
395 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
396 @* Link: @url{http://ixo-jtag.sourceforge.net/}
397 @item @b{Altera USB-Blaster}
398 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
399 @end itemize
400
401 @section USB JLINK based
402 There are several OEM versions of the Segger @b{JLINK} adapter. It is
403 an example of a micro controller based JTAG adapter, it uses an
404 AT91SAM764 internally.
405
406 @itemize @bullet
407 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
408 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
409 @item @b{SEGGER JLINK}
410 @* Link: @url{http://www.segger.com/jlink.html}
411 @item @b{IAR J-Link}
412 @* Link: @url{http://www.iar.com/en/products/hardware-debug-probes/iar-j-link/}
413 @end itemize
414
415 @section USB RLINK based
416 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
417
418 @itemize @bullet
419 @item @b{Raisonance RLink}
420 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
421 @item @b{STM32 Primer}
422 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
423 @item @b{STM32 Primer2}
424 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
425 @end itemize
426
427 @section USB ST-LINK based
428 ST Micro has an adapter called @b{ST-LINK}.
429 They only work with ST Micro chips, notably STM32 and STM8.
430
431 @itemize @bullet
432 @item @b{ST-LINK}
433 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
434 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
435 @item @b{ST-LINK/V2}
436 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
437 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
438 @end itemize
439
440 For info the original ST-LINK enumerates using the mass storage usb class, however
441 it's implementation is completely broken. The result is this causes issues under linux.
442 The simplest solution is to get linux to ignore the ST-LINK using one of the following methods:
443 @itemize @bullet
444 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
445 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
446 @end itemize
447
448 @section USB Other
449 @itemize @bullet
450 @item @b{USBprog}
451 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
452
453 @item @b{USB - Presto}
454 @* Link: @url{http://tools.asix.net/prg_presto.htm}
455
456 @item @b{Versaloon-Link}
457 @* Link: @url{http://www.versaloon.com}
458
459 @item @b{ARM-JTAG-EW}
460 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
461
462 @item @b{Buspirate}
463 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
464
465 @item @b{opendous}
466 @* Link: @url{http://code.google.com/p/opendous-jtag/}
467
468 @item @b{estick}
469 @* Link: @url{http://code.google.com/p/estick-jtag/}
470
471 @item @b{Keil ULINK v1}
472 @* Link: @url{http://www.keil.com/ulink1/}
473 @end itemize
474
475 @section IBM PC Parallel Printer Port Based
476
477 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
478 and the Macraigor Wiggler. There are many clones and variations of
479 these on the market.
480
481 Note that parallel ports are becoming much less common, so if you
482 have the choice you should probably avoid these adapters in favor
483 of USB-based ones.
484
485 @itemize @bullet
486
487 @item @b{Wiggler} - There are many clones of this.
488 @* Link: @url{http://www.macraigor.com/wiggler.htm}
489
490 @item @b{DLC5} - From XILINX - There are many clones of this
491 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
492 produced, PDF schematics are easily found and it is easy to make.
493
494 @item @b{Amontec - JTAG Accelerator}
495 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
496
497 @item @b{GW16402}
498 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
499
500 @item @b{Wiggler2}
501 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
502
503 @item @b{Wiggler_ntrst_inverted}
504 @* Yet another variation - See the source code, src/jtag/parport.c
505
506 @item @b{old_amt_wiggler}
507 @* Unknown - probably not on the market today
508
509 @item @b{arm-jtag}
510 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
511
512 @item @b{chameleon}
513 @* Link: @url{http://www.amontec.com/chameleon.shtml}
514
515 @item @b{Triton}
516 @* Unknown.
517
518 @item @b{Lattice}
519 @* ispDownload from Lattice Semiconductor
520 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
521
522 @item @b{flashlink}
523 @* From ST Microsystems;
524 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
525
526 @end itemize
527
528 @section Other...
529 @itemize @bullet
530
531 @item @b{ep93xx}
532 @* An EP93xx based Linux machine using the GPIO pins directly.
533
534 @item @b{at91rm9200}
535 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
536
537 @end itemize
538
539 @node About Jim-Tcl
540 @chapter About Jim-Tcl
541 @cindex Jim-Tcl
542 @cindex tcl
543
544 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
545 This programming language provides a simple and extensible
546 command interpreter.
547
548 All commands presented in this Guide are extensions to Jim-Tcl.
549 You can use them as simple commands, without needing to learn
550 much of anything about Tcl.
551 Alternatively, can write Tcl programs with them.
552
553 You can learn more about Jim at its website, @url{http://jim.berlios.de}.
554 There is an active and responsive community, get on the mailing list
555 if you have any questions. Jim-Tcl maintainers also lurk on the
556 OpenOCD mailing list.
557
558 @itemize @bullet
559 @item @b{Jim vs. Tcl}
560 @* Jim-Tcl is a stripped down version of the well known Tcl language,
561 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
562 fewer features. Jim-Tcl is several dozens of .C files and .H files and
563 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
564 4.2 MB .zip file containing 1540 files.
565
566 @item @b{Missing Features}
567 @* Our practice has been: Add/clone the real Tcl feature if/when
568 needed. We welcome Jim-Tcl improvements, not bloat. Also there
569 are a large number of optional Jim-Tcl features that are not
570 enabled in OpenOCD.
571
572 @item @b{Scripts}
573 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
574 command interpreter today is a mixture of (newer)
575 Jim-Tcl commands, and (older) the orginal command interpreter.
576
577 @item @b{Commands}
578 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
579 can type a Tcl for() loop, set variables, etc.
580 Some of the commands documented in this guide are implemented
581 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
582
583 @item @b{Historical Note}
584 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
585 before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
586 as a git submodule, which greatly simplified upgrading Jim Tcl
587 to benefit from new features and bugfixes in Jim Tcl.
588
589 @item @b{Need a crash course in Tcl?}
590 @*@xref{Tcl Crash Course}.
591 @end itemize
592
593 @node Running
594 @chapter Running
595 @cindex command line options
596 @cindex logfile
597 @cindex directory search
598
599 Properly installing OpenOCD sets up your operating system to grant it access
600 to the debug adapters. On Linux, this usually involves installing a file
601 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
602 complex and confusing driver configuration for every peripheral. Such issues
603 are unique to each operating system, and are not detailed in this User's Guide.
604
605 Then later you will invoke the OpenOCD server, with various options to
606 tell it how each debug session should work.
607 The @option{--help} option shows:
608 @verbatim
609 bash$ openocd --help
610
611 --help | -h display this help
612 --version | -v display OpenOCD version
613 --file | -f use configuration file <name>
614 --search | -s dir to search for config files and scripts
615 --debug | -d set debug level <0-3>
616 --log_output | -l redirect log output to file <name>
617 --command | -c run <command>
618 @end verbatim
619
620 If you don't give any @option{-f} or @option{-c} options,
621 OpenOCD tries to read the configuration file @file{openocd.cfg}.
622 To specify one or more different
623 configuration files, use @option{-f} options. For example:
624
625 @example
626 openocd -f config1.cfg -f config2.cfg -f config3.cfg
627 @end example
628
629 Configuration files and scripts are searched for in
630 @enumerate
631 @item the current directory,
632 @item any search dir specified on the command line using the @option{-s} option,
633 @item any search dir specified using the @command{add_script_search_dir} command,
634 @item @file{$HOME/.openocd} (not on Windows),
635 @item the site wide script library @file{$pkgdatadir/site} and
636 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
637 @end enumerate
638 The first found file with a matching file name will be used.
639
640 @quotation Note
641 Don't try to use configuration script names or paths which
642 include the "#" character. That character begins Tcl comments.
643 @end quotation
644
645 @section Simple setup, no customization
646
647 In the best case, you can use two scripts from one of the script
648 libraries, hook up your JTAG adapter, and start the server ... and
649 your JTAG setup will just work "out of the box". Always try to
650 start by reusing those scripts, but assume you'll need more
651 customization even if this works. @xref{OpenOCD Project Setup}.
652
653 If you find a script for your JTAG adapter, and for your board or
654 target, you may be able to hook up your JTAG adapter then start
655 the server like:
656
657 @example
658 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
659 @end example
660
661 You might also need to configure which reset signals are present,
662 using @option{-c 'reset_config trst_and_srst'} or something similar.
663 If all goes well you'll see output something like
664
665 @example
666 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
667 For bug reports, read
668 http://openocd.sourceforge.net/doc/doxygen/bugs.html
669 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
670 (mfg: 0x23b, part: 0xba00, ver: 0x3)
671 @end example
672
673 Seeing that "tap/device found" message, and no warnings, means
674 the JTAG communication is working. That's a key milestone, but
675 you'll probably need more project-specific setup.
676
677 @section What OpenOCD does as it starts
678
679 OpenOCD starts by processing the configuration commands provided
680 on the command line or, if there were no @option{-c command} or
681 @option{-f file.cfg} options given, in @file{openocd.cfg}.
682 @xref{Configuration Stage}.
683 At the end of the configuration stage it verifies the JTAG scan
684 chain defined using those commands; your configuration should
685 ensure that this always succeeds.
686 Normally, OpenOCD then starts running as a daemon.
687 Alternatively, commands may be used to terminate the configuration
688 stage early, perform work (such as updating some flash memory),
689 and then shut down without acting as a daemon.
690
691 Once OpenOCD starts running as a daemon, it waits for connections from
692 clients (Telnet, GDB, Other) and processes the commands issued through
693 those channels.
694
695 If you are having problems, you can enable internal debug messages via
696 the @option{-d} option.
697
698 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
699 @option{-c} command line switch.
700
701 To enable debug output (when reporting problems or working on OpenOCD
702 itself), use the @option{-d} command line switch. This sets the
703 @option{debug_level} to "3", outputting the most information,
704 including debug messages. The default setting is "2", outputting only
705 informational messages, warnings and errors. You can also change this
706 setting from within a telnet or gdb session using @command{debug_level
707 <n>} (@pxref{debug_level}).
708
709 You can redirect all output from the daemon to a file using the
710 @option{-l <logfile>} switch.
711
712 Note! OpenOCD will launch the GDB & telnet server even if it can not
713 establish a connection with the target. In general, it is possible for
714 the JTAG controller to be unresponsive until the target is set up
715 correctly via e.g. GDB monitor commands in a GDB init script.
716
717 @node OpenOCD Project Setup
718 @chapter OpenOCD Project Setup
719
720 To use OpenOCD with your development projects, you need to do more than
721 just connecting the JTAG adapter hardware (dongle) to your development board
722 and then starting the OpenOCD server.
723 You also need to configure that server so that it knows
724 about that adapter and board, and helps your work.
725 You may also want to connect OpenOCD to GDB, possibly
726 using Eclipse or some other GUI.
727
728 @section Hooking up the JTAG Adapter
729
730 Today's most common case is a dongle with a JTAG cable on one side
731 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
732 and a USB cable on the other.
733 Instead of USB, some cables use Ethernet;
734 older ones may use a PC parallel port, or even a serial port.
735
736 @enumerate
737 @item @emph{Start with power to your target board turned off},
738 and nothing connected to your JTAG adapter.
739 If you're particularly paranoid, unplug power to the board.
740 It's important to have the ground signal properly set up,
741 unless you are using a JTAG adapter which provides
742 galvanic isolation between the target board and the
743 debugging host.
744
745 @item @emph{Be sure it's the right kind of JTAG connector.}
746 If your dongle has a 20-pin ARM connector, you need some kind
747 of adapter (or octopus, see below) to hook it up to
748 boards using 14-pin or 10-pin connectors ... or to 20-pin
749 connectors which don't use ARM's pinout.
750
751 In the same vein, make sure the voltage levels are compatible.
752 Not all JTAG adapters have the level shifters needed to work
753 with 1.2 Volt boards.
754
755 @item @emph{Be certain the cable is properly oriented} or you might
756 damage your board. In most cases there are only two possible
757 ways to connect the cable.
758 Connect the JTAG cable from your adapter to the board.
759 Be sure it's firmly connected.
760
761 In the best case, the connector is keyed to physically
762 prevent you from inserting it wrong.
763 This is most often done using a slot on the board's male connector
764 housing, which must match a key on the JTAG cable's female connector.
765 If there's no housing, then you must look carefully and
766 make sure pin 1 on the cable hooks up to pin 1 on the board.
767 Ribbon cables are frequently all grey except for a wire on one
768 edge, which is red. The red wire is pin 1.
769
770 Sometimes dongles provide cables where one end is an ``octopus'' of
771 color coded single-wire connectors, instead of a connector block.
772 These are great when converting from one JTAG pinout to another,
773 but are tedious to set up.
774 Use these with connector pinout diagrams to help you match up the
775 adapter signals to the right board pins.
776
777 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
778 A USB, parallel, or serial port connector will go to the host which
779 you are using to run OpenOCD.
780 For Ethernet, consult the documentation and your network administrator.
781
782 For USB based JTAG adapters you have an easy sanity check at this point:
783 does the host operating system see the JTAG adapter? If that host is an
784 MS-Windows host, you'll need to install a driver before OpenOCD works.
785
786 @item @emph{Connect the adapter's power supply, if needed.}
787 This step is primarily for non-USB adapters,
788 but sometimes USB adapters need extra power.
789
790 @item @emph{Power up the target board.}
791 Unless you just let the magic smoke escape,
792 you're now ready to set up the OpenOCD server
793 so you can use JTAG to work with that board.
794
795 @end enumerate
796
797 Talk with the OpenOCD server using
798 telnet (@code{telnet localhost 4444} on many systems) or GDB.
799 @xref{GDB and OpenOCD}.
800
801 @section Project Directory
802
803 There are many ways you can configure OpenOCD and start it up.
804
805 A simple way to organize them all involves keeping a
806 single directory for your work with a given board.
807 When you start OpenOCD from that directory,
808 it searches there first for configuration files, scripts,
809 files accessed through semihosting,
810 and for code you upload to the target board.
811 It is also the natural place to write files,
812 such as log files and data you download from the board.
813
814 @section Configuration Basics
815
816 There are two basic ways of configuring OpenOCD, and
817 a variety of ways you can mix them.
818 Think of the difference as just being how you start the server:
819
820 @itemize
821 @item Many @option{-f file} or @option{-c command} options on the command line
822 @item No options, but a @dfn{user config file}
823 in the current directory named @file{openocd.cfg}
824 @end itemize
825
826 Here is an example @file{openocd.cfg} file for a setup
827 using a Signalyzer FT2232-based JTAG adapter to talk to
828 a board with an Atmel AT91SAM7X256 microcontroller:
829
830 @example
831 source [find interface/signalyzer.cfg]
832
833 # GDB can also flash my flash!
834 gdb_memory_map enable
835 gdb_flash_program enable
836
837 source [find target/sam7x256.cfg]
838 @end example
839
840 Here is the command line equivalent of that configuration:
841
842 @example
843 openocd -f interface/signalyzer.cfg \
844 -c "gdb_memory_map enable" \
845 -c "gdb_flash_program enable" \
846 -f target/sam7x256.cfg
847 @end example
848
849 You could wrap such long command lines in shell scripts,
850 each supporting a different development task.
851 One might re-flash the board with a specific firmware version.
852 Another might set up a particular debugging or run-time environment.
853
854 @quotation Important
855 At this writing (October 2009) the command line method has
856 problems with how it treats variables.
857 For example, after @option{-c "set VAR value"}, or doing the
858 same in a script, the variable @var{VAR} will have no value
859 that can be tested in a later script.
860 @end quotation
861
862 Here we will focus on the simpler solution: one user config
863 file, including basic configuration plus any TCL procedures
864 to simplify your work.
865
866 @section User Config Files
867 @cindex config file, user
868 @cindex user config file
869 @cindex config file, overview
870
871 A user configuration file ties together all the parts of a project
872 in one place.
873 One of the following will match your situation best:
874
875 @itemize
876 @item Ideally almost everything comes from configuration files
877 provided by someone else.
878 For example, OpenOCD distributes a @file{scripts} directory
879 (probably in @file{/usr/share/openocd/scripts} on Linux).
880 Board and tool vendors can provide these too, as can individual
881 user sites; the @option{-s} command line option lets you say
882 where to find these files. (@xref{Running}.)
883 The AT91SAM7X256 example above works this way.
884
885 Three main types of non-user configuration file each have their
886 own subdirectory in the @file{scripts} directory:
887
888 @enumerate
889 @item @b{interface} -- one for each different debug adapter;
890 @item @b{board} -- one for each different board
891 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
892 @end enumerate
893
894 Best case: include just two files, and they handle everything else.
895 The first is an interface config file.
896 The second is board-specific, and it sets up the JTAG TAPs and
897 their GDB targets (by deferring to some @file{target.cfg} file),
898 declares all flash memory, and leaves you nothing to do except
899 meet your deadline:
900
901 @example
902 source [find interface/olimex-jtag-tiny.cfg]
903 source [find board/csb337.cfg]
904 @end example
905
906 Boards with a single microcontroller often won't need more
907 than the target config file, as in the AT91SAM7X256 example.
908 That's because there is no external memory (flash, DDR RAM), and
909 the board differences are encapsulated by application code.
910
911 @item Maybe you don't know yet what your board looks like to JTAG.
912 Once you know the @file{interface.cfg} file to use, you may
913 need help from OpenOCD to discover what's on the board.
914 Once you find the JTAG TAPs, you can just search for appropriate
915 target and board
916 configuration files ... or write your own, from the bottom up.
917 @xref{Autoprobing}.
918
919 @item You can often reuse some standard config files but
920 need to write a few new ones, probably a @file{board.cfg} file.
921 You will be using commands described later in this User's Guide,
922 and working with the guidelines in the next chapter.
923
924 For example, there may be configuration files for your JTAG adapter
925 and target chip, but you need a new board-specific config file
926 giving access to your particular flash chips.
927 Or you might need to write another target chip configuration file
928 for a new chip built around the Cortex M3 core.
929
930 @quotation Note
931 When you write new configuration files, please submit
932 them for inclusion in the next OpenOCD release.
933 For example, a @file{board/newboard.cfg} file will help the
934 next users of that board, and a @file{target/newcpu.cfg}
935 will help support users of any board using that chip.
936 @end quotation
937
938 @item
939 You may may need to write some C code.
940 It may be as simple as a supporting a new ft2232 or parport
941 based adapter; a bit more involved, like a NAND or NOR flash
942 controller driver; or a big piece of work like supporting
943 a new chip architecture.
944 @end itemize
945
946 Reuse the existing config files when you can.
947 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
948 You may find a board configuration that's a good example to follow.
949
950 When you write config files, separate the reusable parts
951 (things every user of that interface, chip, or board needs)
952 from ones specific to your environment and debugging approach.
953 @itemize
954
955 @item
956 For example, a @code{gdb-attach} event handler that invokes
957 the @command{reset init} command will interfere with debugging
958 early boot code, which performs some of the same actions
959 that the @code{reset-init} event handler does.
960
961 @item
962 Likewise, the @command{arm9 vector_catch} command (or
963 @cindex vector_catch
964 its siblings @command{xscale vector_catch}
965 and @command{cortex_m3 vector_catch}) can be a timesaver
966 during some debug sessions, but don't make everyone use that either.
967 Keep those kinds of debugging aids in your user config file,
968 along with messaging and tracing setup.
969 (@xref{Software Debug Messages and Tracing}.)
970
971 @item
972 You might need to override some defaults.
973 For example, you might need to move, shrink, or back up the target's
974 work area if your application needs much SRAM.
975
976 @item
977 TCP/IP port configuration is another example of something which
978 is environment-specific, and should only appear in
979 a user config file. @xref{TCP/IP Ports}.
980 @end itemize
981
982 @section Project-Specific Utilities
983
984 A few project-specific utility
985 routines may well speed up your work.
986 Write them, and keep them in your project's user config file.
987
988 For example, if you are making a boot loader work on a
989 board, it's nice to be able to debug the ``after it's
990 loaded to RAM'' parts separately from the finicky early
991 code which sets up the DDR RAM controller and clocks.
992 A script like this one, or a more GDB-aware sibling,
993 may help:
994
995 @example
996 proc ramboot @{ @} @{
997 # Reset, running the target's "reset-init" scripts
998 # to initialize clocks and the DDR RAM controller.
999 # Leave the CPU halted.
1000 reset init
1001
1002 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1003 load_image u-boot.bin 0x20000000
1004
1005 # Start running.
1006 resume 0x20000000
1007 @}
1008 @end example
1009
1010 Then once that code is working you will need to make it
1011 boot from NOR flash; a different utility would help.
1012 Alternatively, some developers write to flash using GDB.
1013 (You might use a similar script if you're working with a flash
1014 based microcontroller application instead of a boot loader.)
1015
1016 @example
1017 proc newboot @{ @} @{
1018 # Reset, leaving the CPU halted. The "reset-init" event
1019 # proc gives faster access to the CPU and to NOR flash;
1020 # "reset halt" would be slower.
1021 reset init
1022
1023 # Write standard version of U-Boot into the first two
1024 # sectors of NOR flash ... the standard version should
1025 # do the same lowlevel init as "reset-init".
1026 flash protect 0 0 1 off
1027 flash erase_sector 0 0 1
1028 flash write_bank 0 u-boot.bin 0x0
1029 flash protect 0 0 1 on
1030
1031 # Reboot from scratch using that new boot loader.
1032 reset run
1033 @}
1034 @end example
1035
1036 You may need more complicated utility procedures when booting
1037 from NAND.
1038 That often involves an extra bootloader stage,
1039 running from on-chip SRAM to perform DDR RAM setup so it can load
1040 the main bootloader code (which won't fit into that SRAM).
1041
1042 Other helper scripts might be used to write production system images,
1043 involving considerably more than just a three stage bootloader.
1044
1045 @section Target Software Changes
1046
1047 Sometimes you may want to make some small changes to the software
1048 you're developing, to help make JTAG debugging work better.
1049 For example, in C or assembly language code you might
1050 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1051 handling issues like:
1052
1053 @itemize @bullet
1054
1055 @item @b{Watchdog Timers}...
1056 Watchog timers are typically used to automatically reset systems if
1057 some application task doesn't periodically reset the timer. (The
1058 assumption is that the system has locked up if the task can't run.)
1059 When a JTAG debugger halts the system, that task won't be able to run
1060 and reset the timer ... potentially causing resets in the middle of
1061 your debug sessions.
1062
1063 It's rarely a good idea to disable such watchdogs, since their usage
1064 needs to be debugged just like all other parts of your firmware.
1065 That might however be your only option.
1066
1067 Look instead for chip-specific ways to stop the watchdog from counting
1068 while the system is in a debug halt state. It may be simplest to set
1069 that non-counting mode in your debugger startup scripts. You may however
1070 need a different approach when, for example, a motor could be physically
1071 damaged by firmware remaining inactive in a debug halt state. That might
1072 involve a type of firmware mode where that "non-counting" mode is disabled
1073 at the beginning then re-enabled at the end; a watchdog reset might fire
1074 and complicate the debug session, but hardware (or people) would be
1075 protected.@footnote{Note that many systems support a "monitor mode" debug
1076 that is a somewhat cleaner way to address such issues. You can think of
1077 it as only halting part of the system, maybe just one task,
1078 instead of the whole thing.
1079 At this writing, January 2010, OpenOCD based debugging does not support
1080 monitor mode debug, only "halt mode" debug.}
1081
1082 @item @b{ARM Semihosting}...
1083 @cindex ARM semihosting
1084 When linked with a special runtime library provided with many
1085 toolchains@footnote{See chapter 8 "Semihosting" in
1086 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1087 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1088 The CodeSourcery EABI toolchain also includes a semihosting library.},
1089 your target code can use I/O facilities on the debug host. That library
1090 provides a small set of system calls which are handled by OpenOCD.
1091 It can let the debugger provide your system console and a file system,
1092 helping with early debugging or providing a more capable environment
1093 for sometimes-complex tasks like installing system firmware onto
1094 NAND or SPI flash.
1095
1096 @item @b{ARM Wait-For-Interrupt}...
1097 Many ARM chips synchronize the JTAG clock using the core clock.
1098 Low power states which stop that core clock thus prevent JTAG access.
1099 Idle loops in tasking environments often enter those low power states
1100 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1101
1102 You may want to @emph{disable that instruction} in source code,
1103 or otherwise prevent using that state,
1104 to ensure you can get JTAG access at any time.@footnote{As a more
1105 polite alternative, some processors have special debug-oriented
1106 registers which can be used to change various features including
1107 how the low power states are clocked while debugging.
1108 The STM32 DBGMCU_CR register is an example; at the cost of extra
1109 power consumption, JTAG can be used during low power states.}
1110 For example, the OpenOCD @command{halt} command may not
1111 work for an idle processor otherwise.
1112
1113 @item @b{Delay after reset}...
1114 Not all chips have good support for debugger access
1115 right after reset; many LPC2xxx chips have issues here.
1116 Similarly, applications that reconfigure pins used for
1117 JTAG access as they start will also block debugger access.
1118
1119 To work with boards like this, @emph{enable a short delay loop}
1120 the first thing after reset, before "real" startup activities.
1121 For example, one second's delay is usually more than enough
1122 time for a JTAG debugger to attach, so that
1123 early code execution can be debugged
1124 or firmware can be replaced.
1125
1126 @item @b{Debug Communications Channel (DCC)}...
1127 Some processors include mechanisms to send messages over JTAG.
1128 Many ARM cores support these, as do some cores from other vendors.
1129 (OpenOCD may be able to use this DCC internally, speeding up some
1130 operations like writing to memory.)
1131
1132 Your application may want to deliver various debugging messages
1133 over JTAG, by @emph{linking with a small library of code}
1134 provided with OpenOCD and using the utilities there to send
1135 various kinds of message.
1136 @xref{Software Debug Messages and Tracing}.
1137
1138 @end itemize
1139
1140 @section Target Hardware Setup
1141
1142 Chip vendors often provide software development boards which
1143 are highly configurable, so that they can support all options
1144 that product boards may require. @emph{Make sure that any
1145 jumpers or switches match the system configuration you are
1146 working with.}
1147
1148 Common issues include:
1149
1150 @itemize @bullet
1151
1152 @item @b{JTAG setup} ...
1153 Boards may support more than one JTAG configuration.
1154 Examples include jumpers controlling pullups versus pulldowns
1155 on the nTRST and/or nSRST signals, and choice of connectors
1156 (e.g. which of two headers on the base board,
1157 or one from a daughtercard).
1158 For some Texas Instruments boards, you may need to jumper the
1159 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1160
1161 @item @b{Boot Modes} ...
1162 Complex chips often support multiple boot modes, controlled
1163 by external jumpers. Make sure this is set up correctly.
1164 For example many i.MX boards from NXP need to be jumpered
1165 to "ATX mode" to start booting using the on-chip ROM, when
1166 using second stage bootloader code stored in a NAND flash chip.
1167
1168 Such explicit configuration is common, and not limited to
1169 booting from NAND. You might also need to set jumpers to
1170 start booting using code loaded from an MMC/SD card; external
1171 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1172 flash; some external host; or various other sources.
1173
1174
1175 @item @b{Memory Addressing} ...
1176 Boards which support multiple boot modes may also have jumpers
1177 to configure memory addressing. One board, for example, jumpers
1178 external chipselect 0 (used for booting) to address either
1179 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1180 or NAND flash. When it's jumpered to address NAND flash, that
1181 board must also be told to start booting from on-chip ROM.
1182
1183 Your @file{board.cfg} file may also need to be told this jumper
1184 configuration, so that it can know whether to declare NOR flash
1185 using @command{flash bank} or instead declare NAND flash with
1186 @command{nand device}; and likewise which probe to perform in
1187 its @code{reset-init} handler.
1188
1189 A closely related issue is bus width. Jumpers might need to
1190 distinguish between 8 bit or 16 bit bus access for the flash
1191 used to start booting.
1192
1193 @item @b{Peripheral Access} ...
1194 Development boards generally provide access to every peripheral
1195 on the chip, sometimes in multiple modes (such as by providing
1196 multiple audio codec chips).
1197 This interacts with software
1198 configuration of pin multiplexing, where for example a
1199 given pin may be routed either to the MMC/SD controller
1200 or the GPIO controller. It also often interacts with
1201 configuration jumpers. One jumper may be used to route
1202 signals to an MMC/SD card slot or an expansion bus (which
1203 might in turn affect booting); others might control which
1204 audio or video codecs are used.
1205
1206 @end itemize
1207
1208 Plus you should of course have @code{reset-init} event handlers
1209 which set up the hardware to match that jumper configuration.
1210 That includes in particular any oscillator or PLL used to clock
1211 the CPU, and any memory controllers needed to access external
1212 memory and peripherals. Without such handlers, you won't be
1213 able to access those resources without working target firmware
1214 which can do that setup ... this can be awkward when you're
1215 trying to debug that target firmware. Even if there's a ROM
1216 bootloader which handles a few issues, it rarely provides full
1217 access to all board-specific capabilities.
1218
1219
1220 @node Config File Guidelines
1221 @chapter Config File Guidelines
1222
1223 This chapter is aimed at any user who needs to write a config file,
1224 including developers and integrators of OpenOCD and any user who
1225 needs to get a new board working smoothly.
1226 It provides guidelines for creating those files.
1227
1228 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1229 with files including the ones listed here.
1230 Use them as-is where you can; or as models for new files.
1231 @itemize @bullet
1232 @item @file{interface} ...
1233 These are for debug adapters.
1234 Files that configure JTAG adapters go here.
1235 @example
1236 $ ls interface
1237 altera-usb-blaster.cfg hilscher_nxhx50_etm.cfg openrd.cfg
1238 arm-jtag-ew.cfg hilscher_nxhx50_re.cfg osbdm.cfg
1239 arm-usb-ocd.cfg hitex_str9-comstick.cfg parport.cfg
1240 at91rm9200.cfg icebear.cfg parport_dlc5.cfg
1241 axm0432.cfg jlink.cfg redbee-econotag.cfg
1242 busblaster.cfg jtagkey2.cfg redbee-usb.cfg
1243 buspirate.cfg jtagkey2p.cfg rlink.cfg
1244 calao-usb-a9260-c01.cfg jtagkey.cfg sheevaplug.cfg
1245 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg signalyzer.cfg
1246 calao-usb-a9260.cfg kt-link.cfg signalyzer-h2.cfg
1247 chameleon.cfg lisa-l.cfg signalyzer-h4.cfg
1248 cortino.cfg luminary.cfg signalyzer-lite.cfg
1249 digilent-hs1.cfg luminary-icdi.cfg stlink-v1.cfg
1250 dlp-usb1232h.cfg luminary-lm3s811.cfg stlink-v2.cfg
1251 dummy.cfg minimodule.cfg stm32-stick.cfg
1252 estick.cfg neodb.cfg turtelizer2.cfg
1253 flashlink.cfg ngxtech.cfg ulink.cfg
1254 flossjtag.cfg olimex-arm-usb-ocd.cfg usb-jtag.cfg
1255 flossjtag-noeeprom.cfg olimex-arm-usb-ocd-h.cfg usbprog.cfg
1256 flyswatter2.cfg olimex-arm-usb-tiny-h.cfg vpaclink.cfg
1257 flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
1258 hilscher_nxhx10_etm.cfg oocdlink.cfg xds100v2.cfg
1259 hilscher_nxhx500_etm.cfg opendous.cfg
1260 hilscher_nxhx500_re.cfg openocd-usb.cfg
1261 $
1262 @end example
1263 @item @file{board} ...
1264 think Circuit Board, PWA, PCB, they go by many names. Board files
1265 contain initialization items that are specific to a board.
1266 They reuse target configuration files, since the same
1267 microprocessor chips are used on many boards,
1268 but support for external parts varies widely. For
1269 example, the SDRAM initialization sequence for the board, or the type
1270 of external flash and what address it uses. Any initialization
1271 sequence to enable that external flash or SDRAM should be found in the
1272 board file. Boards may also contain multiple targets: two CPUs; or
1273 a CPU and an FPGA.
1274 @example
1275 $ ls board
1276 actux3.cfg logicpd_imx27.cfg
1277 am3517evm.cfg lubbock.cfg
1278 arm_evaluator7t.cfg mcb1700.cfg
1279 at91cap7a-stk-sdram.cfg microchip_explorer16.cfg
1280 at91eb40a.cfg mini2440.cfg
1281 at91rm9200-dk.cfg mini6410.cfg
1282 at91rm9200-ek.cfg olimex_LPC2378STK.cfg
1283 at91sam9261-ek.cfg olimex_lpc_h2148.cfg
1284 at91sam9263-ek.cfg olimex_sam7_ex256.cfg
1285 at91sam9g20-ek.cfg olimex_sam9_l9260.cfg
1286 atmel_at91sam7s-ek.cfg olimex_stm32_h103.cfg
1287 atmel_at91sam9260-ek.cfg olimex_stm32_h107.cfg
1288 atmel_at91sam9rl-ek.cfg olimex_stm32_p107.cfg
1289 atmel_sam3n_ek.cfg omap2420_h4.cfg
1290 atmel_sam3s_ek.cfg open-bldc.cfg
1291 atmel_sam3u_ek.cfg openrd.cfg
1292 atmel_sam3x_ek.cfg osk5912.cfg
1293 atmel_sam4s_ek.cfg phytec_lpc3250.cfg
1294 balloon3-cpu.cfg pic-p32mx.cfg
1295 colibri.cfg propox_mmnet1001.cfg
1296 crossbow_tech_imote2.cfg pxa255_sst.cfg
1297 csb337.cfg redbee.cfg
1298 csb732.cfg rsc-w910.cfg
1299 da850evm.cfg sheevaplug.cfg
1300 digi_connectcore_wi-9c.cfg smdk6410.cfg
1301 diolan_lpc4350-db1.cfg spear300evb.cfg
1302 dm355evm.cfg spear300evb_mod.cfg
1303 dm365evm.cfg spear310evb20.cfg
1304 dm6446evm.cfg spear310evb20_mod.cfg
1305 efikamx.cfg spear320cpu.cfg
1306 eir.cfg spear320cpu_mod.cfg
1307 ek-lm3s1968.cfg steval_pcc010.cfg
1308 ek-lm3s3748.cfg stm320518_eval_stlink.cfg
1309 ek-lm3s6965.cfg stm32100b_eval.cfg
1310 ek-lm3s811.cfg stm3210b_eval.cfg
1311 ek-lm3s811-revb.cfg stm3210c_eval.cfg
1312 ek-lm3s9b9x.cfg stm3210e_eval.cfg
1313 ek-lm4f232.cfg stm3220g_eval.cfg
1314 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1315 ethernut3.cfg stm3241g_eval.cfg
1316 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1317 hammer.cfg stm32f0discovery.cfg
1318 hilscher_nxdb500sys.cfg stm32f4discovery.cfg
1319 hilscher_nxeb500hmi.cfg stm32ldiscovery.cfg
1320 hilscher_nxhx10.cfg stm32vldiscovery.cfg
1321 hilscher_nxhx500.cfg str910-eval.cfg
1322 hilscher_nxhx50.cfg telo.cfg
1323 hilscher_nxsb100.cfg ti_beagleboard.cfg
1324 hitex_lpc2929.cfg ti_beagleboard_xm.cfg
1325 hitex_stm32-performancestick.cfg ti_beaglebone.cfg
1326 hitex_str9-comstick.cfg ti_blaze.cfg
1327 iar_lpc1768.cfg ti_pandaboard.cfg
1328 iar_str912_sk.cfg ti_pandaboard_es.cfg
1329 icnova_imx53_sodimm.cfg topas910.cfg
1330 icnova_sam9g45_sodimm.cfg topasa900.cfg
1331 imx27ads.cfg twr-k60n512.cfg
1332 imx27lnst.cfg tx25_stk5.cfg
1333 imx28evk.cfg tx27_stk5.cfg
1334 imx31pdk.cfg unknown_at91sam9260.cfg
1335 imx35pdk.cfg uptech_2410.cfg
1336 imx53loco.cfg verdex.cfg
1337 keil_mcb1700.cfg voipac.cfg
1338 keil_mcb2140.cfg voltcraft_dso-3062c.cfg
1339 kwikstik.cfg x300t.cfg
1340 linksys_nslu2.cfg zy1000.cfg
1341 lisa-l.cfg
1342 $
1343 @end example
1344 @item @file{target} ...
1345 think chip. The ``target'' directory represents the JTAG TAPs
1346 on a chip
1347 which OpenOCD should control, not a board. Two common types of targets
1348 are ARM chips and FPGA or CPLD chips.
1349 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1350 the target config file defines all of them.
1351 @example
1352 $ ls target
1353 $duc702x.cfg ixp42x.cfg
1354 am335x.cfg k40.cfg
1355 amdm37x.cfg k60.cfg
1356 ar71xx.cfg lpc1768.cfg
1357 at32ap7000.cfg lpc2103.cfg
1358 at91r40008.cfg lpc2124.cfg
1359 at91rm9200.cfg lpc2129.cfg
1360 at91sam3ax_4x.cfg lpc2148.cfg
1361 at91sam3ax_8x.cfg lpc2294.cfg
1362 at91sam3ax_xx.cfg lpc2378.cfg
1363 at91sam3nXX.cfg lpc2460.cfg
1364 at91sam3sXX.cfg lpc2478.cfg
1365 at91sam3u1c.cfg lpc2900.cfg
1366 at91sam3u1e.cfg lpc2xxx.cfg
1367 at91sam3u2c.cfg lpc3131.cfg
1368 at91sam3u2e.cfg lpc3250.cfg
1369 at91sam3u4c.cfg lpc4350.cfg
1370 at91sam3u4e.cfg mc13224v.cfg
1371 at91sam3uxx.cfg nuc910.cfg
1372 at91sam3XXX.cfg omap2420.cfg
1373 at91sam4sXX.cfg omap3530.cfg
1374 at91sam4XXX.cfg omap4430.cfg
1375 at91sam7se512.cfg omap4460.cfg
1376 at91sam7sx.cfg omap5912.cfg
1377 at91sam7x256.cfg omapl138.cfg
1378 at91sam7x512.cfg pic32mx.cfg
1379 at91sam9260.cfg pxa255.cfg
1380 at91sam9260_ext_RAM_ext_flash.cfg pxa270.cfg
1381 at91sam9261.cfg pxa3xx.cfg
1382 at91sam9263.cfg readme.txt
1383 at91sam9.cfg samsung_s3c2410.cfg
1384 at91sam9g10.cfg samsung_s3c2440.cfg
1385 at91sam9g20.cfg samsung_s3c2450.cfg
1386 at91sam9g45.cfg samsung_s3c4510.cfg
1387 at91sam9rl.cfg samsung_s3c6410.cfg
1388 atmega128.cfg sharp_lh79532.cfg
1389 avr32.cfg smp8634.cfg
1390 c100.cfg spear3xx.cfg
1391 c100config.tcl stellaris.cfg
1392 c100helper.tcl stm32.cfg
1393 c100regs.tcl stm32f0x_stlink.cfg
1394 cs351x.cfg stm32f1x.cfg
1395 davinci.cfg stm32f1x_stlink.cfg
1396 dragonite.cfg stm32f2x.cfg
1397 dsp56321.cfg stm32f2x_stlink.cfg
1398 dsp568013.cfg stm32f2xxx.cfg
1399 dsp568037.cfg stm32f4x.cfg
1400 epc9301.cfg stm32f4x_stlink.cfg
1401 faux.cfg stm32l.cfg
1402 feroceon.cfg stm32lx_stlink.cfg
1403 fm3.cfg stm32_stlink.cfg
1404 hilscher_netx10.cfg stm32xl.cfg
1405 hilscher_netx500.cfg str710.cfg
1406 hilscher_netx50.cfg str730.cfg
1407 icepick.cfg str750.cfg
1408 imx21.cfg str912.cfg
1409 imx25.cfg swj-dp.tcl
1410 imx27.cfg test_reset_syntax_error.cfg
1411 imx28.cfg test_syntax_error.cfg
1412 imx31.cfg ti_dm355.cfg
1413 imx35.cfg ti_dm365.cfg
1414 imx51.cfg ti_dm6446.cfg
1415 imx53.cfg tmpa900.cfg
1416 imx.cfg tmpa910.cfg
1417 is5114.cfg u8500.cfg
1418 @end example
1419 @item @emph{more} ... browse for other library files which may be useful.
1420 For example, there are various generic and CPU-specific utilities.
1421 @end itemize
1422
1423 The @file{openocd.cfg} user config
1424 file may override features in any of the above files by
1425 setting variables before sourcing the target file, or by adding
1426 commands specific to their situation.
1427
1428 @section Interface Config Files
1429
1430 The user config file
1431 should be able to source one of these files with a command like this:
1432
1433 @example
1434 source [find interface/FOOBAR.cfg]
1435 @end example
1436
1437 A preconfigured interface file should exist for every debug adapter
1438 in use today with OpenOCD.
1439 That said, perhaps some of these config files
1440 have only been used by the developer who created it.
1441
1442 A separate chapter gives information about how to set these up.
1443 @xref{Debug Adapter Configuration}.
1444 Read the OpenOCD source code (and Developer's Guide)
1445 if you have a new kind of hardware interface
1446 and need to provide a driver for it.
1447
1448 @section Board Config Files
1449 @cindex config file, board
1450 @cindex board config file
1451
1452 The user config file
1453 should be able to source one of these files with a command like this:
1454
1455 @example
1456 source [find board/FOOBAR.cfg]
1457 @end example
1458
1459 The point of a board config file is to package everything
1460 about a given board that user config files need to know.
1461 In summary the board files should contain (if present)
1462
1463 @enumerate
1464 @item One or more @command{source [target/...cfg]} statements
1465 @item NOR flash configuration (@pxref{NOR Configuration})
1466 @item NAND flash configuration (@pxref{NAND Configuration})
1467 @item Target @code{reset} handlers for SDRAM and I/O configuration
1468 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1469 @item All things that are not ``inside a chip''
1470 @end enumerate
1471
1472 Generic things inside target chips belong in target config files,
1473 not board config files. So for example a @code{reset-init} event
1474 handler should know board-specific oscillator and PLL parameters,
1475 which it passes to target-specific utility code.
1476
1477 The most complex task of a board config file is creating such a
1478 @code{reset-init} event handler.
1479 Define those handlers last, after you verify the rest of the board
1480 configuration works.
1481
1482 @subsection Communication Between Config files
1483
1484 In addition to target-specific utility code, another way that
1485 board and target config files communicate is by following a
1486 convention on how to use certain variables.
1487
1488 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1489 Thus the rule we follow in OpenOCD is this: Variables that begin with
1490 a leading underscore are temporary in nature, and can be modified and
1491 used at will within a target configuration file.
1492
1493 Complex board config files can do the things like this,
1494 for a board with three chips:
1495
1496 @example
1497 # Chip #1: PXA270 for network side, big endian
1498 set CHIPNAME network
1499 set ENDIAN big
1500 source [find target/pxa270.cfg]
1501 # on return: _TARGETNAME = network.cpu
1502 # other commands can refer to the "network.cpu" target.
1503 $_TARGETNAME configure .... events for this CPU..
1504
1505 # Chip #2: PXA270 for video side, little endian
1506 set CHIPNAME video
1507 set ENDIAN little
1508 source [find target/pxa270.cfg]
1509 # on return: _TARGETNAME = video.cpu
1510 # other commands can refer to the "video.cpu" target.
1511 $_TARGETNAME configure .... events for this CPU..
1512
1513 # Chip #3: Xilinx FPGA for glue logic
1514 set CHIPNAME xilinx
1515 unset ENDIAN
1516 source [find target/spartan3.cfg]
1517 @end example
1518
1519 That example is oversimplified because it doesn't show any flash memory,
1520 or the @code{reset-init} event handlers to initialize external DRAM
1521 or (assuming it needs it) load a configuration into the FPGA.
1522 Such features are usually needed for low-level work with many boards,
1523 where ``low level'' implies that the board initialization software may
1524 not be working. (That's a common reason to need JTAG tools. Another
1525 is to enable working with microcontroller-based systems, which often
1526 have no debugging support except a JTAG connector.)
1527
1528 Target config files may also export utility functions to board and user
1529 config files. Such functions should use name prefixes, to help avoid
1530 naming collisions.
1531
1532 Board files could also accept input variables from user config files.
1533 For example, there might be a @code{J4_JUMPER} setting used to identify
1534 what kind of flash memory a development board is using, or how to set
1535 up other clocks and peripherals.
1536
1537 @subsection Variable Naming Convention
1538 @cindex variable names
1539
1540 Most boards have only one instance of a chip.
1541 However, it should be easy to create a board with more than
1542 one such chip (as shown above).
1543 Accordingly, we encourage these conventions for naming
1544 variables associated with different @file{target.cfg} files,
1545 to promote consistency and
1546 so that board files can override target defaults.
1547
1548 Inputs to target config files include:
1549
1550 @itemize @bullet
1551 @item @code{CHIPNAME} ...
1552 This gives a name to the overall chip, and is used as part of
1553 tap identifier dotted names.
1554 While the default is normally provided by the chip manufacturer,
1555 board files may need to distinguish between instances of a chip.
1556 @item @code{ENDIAN} ...
1557 By default @option{little} - although chips may hard-wire @option{big}.
1558 Chips that can't change endianness don't need to use this variable.
1559 @item @code{CPUTAPID} ...
1560 When OpenOCD examines the JTAG chain, it can be told verify the
1561 chips against the JTAG IDCODE register.
1562 The target file will hold one or more defaults, but sometimes the
1563 chip in a board will use a different ID (perhaps a newer revision).
1564 @end itemize
1565
1566 Outputs from target config files include:
1567
1568 @itemize @bullet
1569 @item @code{_TARGETNAME} ...
1570 By convention, this variable is created by the target configuration
1571 script. The board configuration file may make use of this variable to
1572 configure things like a ``reset init'' script, or other things
1573 specific to that board and that target.
1574 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1575 @code{_TARGETNAME1}, ... etc.
1576 @end itemize
1577
1578 @subsection The reset-init Event Handler
1579 @cindex event, reset-init
1580 @cindex reset-init handler
1581
1582 Board config files run in the OpenOCD configuration stage;
1583 they can't use TAPs or targets, since they haven't been
1584 fully set up yet.
1585 This means you can't write memory or access chip registers;
1586 you can't even verify that a flash chip is present.
1587 That's done later in event handlers, of which the target @code{reset-init}
1588 handler is one of the most important.
1589
1590 Except on microcontrollers, the basic job of @code{reset-init} event
1591 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1592 Microcontrollers rarely use boot loaders; they run right out of their
1593 on-chip flash and SRAM memory. But they may want to use one of these
1594 handlers too, if just for developer convenience.
1595
1596 @quotation Note
1597 Because this is so very board-specific, and chip-specific, no examples
1598 are included here.
1599 Instead, look at the board config files distributed with OpenOCD.
1600 If you have a boot loader, its source code will help; so will
1601 configuration files for other JTAG tools
1602 (@pxref{Translating Configuration Files}).
1603 @end quotation
1604
1605 Some of this code could probably be shared between different boards.
1606 For example, setting up a DRAM controller often doesn't differ by
1607 much except the bus width (16 bits or 32?) and memory timings, so a
1608 reusable TCL procedure loaded by the @file{target.cfg} file might take
1609 those as parameters.
1610 Similarly with oscillator, PLL, and clock setup;
1611 and disabling the watchdog.
1612 Structure the code cleanly, and provide comments to help
1613 the next developer doing such work.
1614 (@emph{You might be that next person} trying to reuse init code!)
1615
1616 The last thing normally done in a @code{reset-init} handler is probing
1617 whatever flash memory was configured. For most chips that needs to be
1618 done while the associated target is halted, either because JTAG memory
1619 access uses the CPU or to prevent conflicting CPU access.
1620
1621 @subsection JTAG Clock Rate
1622
1623 Before your @code{reset-init} handler has set up
1624 the PLLs and clocking, you may need to run with
1625 a low JTAG clock rate.
1626 @xref{JTAG Speed}.
1627 Then you'd increase that rate after your handler has
1628 made it possible to use the faster JTAG clock.
1629 When the initial low speed is board-specific, for example
1630 because it depends on a board-specific oscillator speed, then
1631 you should probably set it up in the board config file;
1632 if it's target-specific, it belongs in the target config file.
1633
1634 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1635 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1636 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1637 Consult chip documentation to determine the peak JTAG clock rate,
1638 which might be less than that.
1639
1640 @quotation Warning
1641 On most ARMs, JTAG clock detection is coupled to the core clock, so
1642 software using a @option{wait for interrupt} operation blocks JTAG access.
1643 Adaptive clocking provides a partial workaround, but a more complete
1644 solution just avoids using that instruction with JTAG debuggers.
1645 @end quotation
1646
1647 If both the chip and the board support adaptive clocking,
1648 use the @command{jtag_rclk}
1649 command, in case your board is used with JTAG adapter which
1650 also supports it. Otherwise use @command{adapter_khz}.
1651 Set the slow rate at the beginning of the reset sequence,
1652 and the faster rate as soon as the clocks are at full speed.
1653
1654 @anchor{The init_board procedure}
1655 @subsection The init_board procedure
1656 @cindex init_board procedure
1657
1658 The concept of @code{init_board} procedure is very similar to @code{init_targets} (@xref{The init_targets procedure}.)
1659 - it's a replacement of ``linear'' configuration scripts. This procedure is meant to be executed when OpenOCD enters run
1660 stage (@xref{Entering the Run Stage},) after @code{init_targets}. The idea to have spearate @code{init_targets} and
1661 @code{init_board} procedures is to allow the first one to configure everything target specific (internal flash,
1662 internal RAM, etc.) and the second one to configure everything board specific (reset signals, chip frequency,
1663 reset-init event handler, external memory, etc.). Additionally ``linear'' board config file will most likely fail when
1664 target config file uses @code{init_targets} scheme (``linear'' script is executed before @code{init} and
1665 @code{init_targets} - after), so separating these two configuration stages is very convenient, as the easiest way to
1666 overcome this problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1667 need to override @code{init_targets} defined in target config files when they only need to to add some specifics.
1668
1669 Just as @code{init_targets}, the @code{init_board} procedure can be overriden by ``next level'' script (which sources
1670 the original), allowing greater code reuse.
1671
1672 @example
1673 ### board_file.cfg ###
1674
1675 # source target file that does most of the config in init_targets
1676 source [find target/target.cfg]
1677
1678 proc enable_fast_clock @{@} @{
1679 # enables fast on-board clock source
1680 # configures the chip to use it
1681 @}
1682
1683 # initialize only board specifics - reset, clock, adapter frequency
1684 proc init_board @{@} @{
1685 reset_config trst_and_srst trst_pulls_srst
1686
1687 $_TARGETNAME configure -event reset-init @{
1688 adapter_khz 1
1689 enable_fast_clock
1690 adapter_khz 10000
1691 @}
1692 @}
1693 @end example
1694
1695 @section Target Config Files
1696 @cindex config file, target
1697 @cindex target config file
1698
1699 Board config files communicate with target config files using
1700 naming conventions as described above, and may source one or
1701 more target config files like this:
1702
1703 @example
1704 source [find target/FOOBAR.cfg]
1705 @end example
1706
1707 The point of a target config file is to package everything
1708 about a given chip that board config files need to know.
1709 In summary the target files should contain
1710
1711 @enumerate
1712 @item Set defaults
1713 @item Add TAPs to the scan chain
1714 @item Add CPU targets (includes GDB support)
1715 @item CPU/Chip/CPU-Core specific features
1716 @item On-Chip flash
1717 @end enumerate
1718
1719 As a rule of thumb, a target file sets up only one chip.
1720 For a microcontroller, that will often include a single TAP,
1721 which is a CPU needing a GDB target, and its on-chip flash.
1722
1723 More complex chips may include multiple TAPs, and the target
1724 config file may need to define them all before OpenOCD
1725 can talk to the chip.
1726 For example, some phone chips have JTAG scan chains that include
1727 an ARM core for operating system use, a DSP,
1728 another ARM core embedded in an image processing engine,
1729 and other processing engines.
1730
1731 @subsection Default Value Boiler Plate Code
1732
1733 All target configuration files should start with code like this,
1734 letting board config files express environment-specific
1735 differences in how things should be set up.
1736
1737 @example
1738 # Boards may override chip names, perhaps based on role,
1739 # but the default should match what the vendor uses
1740 if @{ [info exists CHIPNAME] @} @{
1741 set _CHIPNAME $CHIPNAME
1742 @} else @{
1743 set _CHIPNAME sam7x256
1744 @}
1745
1746 # ONLY use ENDIAN with targets that can change it.
1747 if @{ [info exists ENDIAN] @} @{
1748 set _ENDIAN $ENDIAN
1749 @} else @{
1750 set _ENDIAN little
1751 @}
1752
1753 # TAP identifiers may change as chips mature, for example with
1754 # new revision fields (the "3" here). Pick a good default; you
1755 # can pass several such identifiers to the "jtag newtap" command.
1756 if @{ [info exists CPUTAPID ] @} @{
1757 set _CPUTAPID $CPUTAPID
1758 @} else @{
1759 set _CPUTAPID 0x3f0f0f0f
1760 @}
1761 @end example
1762 @c but 0x3f0f0f0f is for an str73x part ...
1763
1764 @emph{Remember:} Board config files may include multiple target
1765 config files, or the same target file multiple times
1766 (changing at least @code{CHIPNAME}).
1767
1768 Likewise, the target configuration file should define
1769 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1770 use it later on when defining debug targets:
1771
1772 @example
1773 set _TARGETNAME $_CHIPNAME.cpu
1774 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1775 @end example
1776
1777 @subsection Adding TAPs to the Scan Chain
1778 After the ``defaults'' are set up,
1779 add the TAPs on each chip to the JTAG scan chain.
1780 @xref{TAP Declaration}, and the naming convention
1781 for taps.
1782
1783 In the simplest case the chip has only one TAP,
1784 probably for a CPU or FPGA.
1785 The config file for the Atmel AT91SAM7X256
1786 looks (in part) like this:
1787
1788 @example
1789 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1790 @end example
1791
1792 A board with two such at91sam7 chips would be able
1793 to source such a config file twice, with different
1794 values for @code{CHIPNAME}, so
1795 it adds a different TAP each time.
1796
1797 If there are nonzero @option{-expected-id} values,
1798 OpenOCD attempts to verify the actual tap id against those values.
1799 It will issue error messages if there is mismatch, which
1800 can help to pinpoint problems in OpenOCD configurations.
1801
1802 @example
1803 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1804 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1805 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1806 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1807 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1808 @end example
1809
1810 There are more complex examples too, with chips that have
1811 multiple TAPs. Ones worth looking at include:
1812
1813 @itemize
1814 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1815 plus a JRC to enable them
1816 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1817 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1818 is not currently used)
1819 @end itemize
1820
1821 @subsection Add CPU targets
1822
1823 After adding a TAP for a CPU, you should set it up so that
1824 GDB and other commands can use it.
1825 @xref{CPU Configuration}.
1826 For the at91sam7 example above, the command can look like this;
1827 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1828 to little endian, and this chip doesn't support changing that.
1829
1830 @example
1831 set _TARGETNAME $_CHIPNAME.cpu
1832 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1833 @end example
1834
1835 Work areas are small RAM areas associated with CPU targets.
1836 They are used by OpenOCD to speed up downloads,
1837 and to download small snippets of code to program flash chips.
1838 If the chip includes a form of ``on-chip-ram'' - and many do - define
1839 a work area if you can.
1840 Again using the at91sam7 as an example, this can look like:
1841
1842 @example
1843 $_TARGETNAME configure -work-area-phys 0x00200000 \
1844 -work-area-size 0x4000 -work-area-backup 0
1845 @end example
1846
1847 @anchor{Define CPU targets working in SMP}
1848 @subsection Define CPU targets working in SMP
1849 @cindex SMP
1850 After setting targets, you can define a list of targets working in SMP.
1851
1852 @example
1853 set _TARGETNAME_1 $_CHIPNAME.cpu1
1854 set _TARGETNAME_2 $_CHIPNAME.cpu2
1855 target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap \
1856 -coreid 0 -dbgbase $_DAP_DBG1
1857 target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap \
1858 -coreid 1 -dbgbase $_DAP_DBG2
1859 #define 2 targets working in smp.
1860 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1861 @end example
1862 In the above example on cortex_a8, 2 cpus are working in SMP.
1863 In SMP only one GDB instance is created and :
1864 @itemize @bullet
1865 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1866 @item halt command triggers the halt of all targets in the list.
1867 @item resume command triggers the write context and the restart of all targets in the list.
1868 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1869 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1870 displayed by the GDB session @pxref{Using openocd SMP with GDB}.
1871 @end itemize
1872
1873 The SMP behaviour can be disabled/enabled dynamically. On cortex_a8 following
1874 command have been implemented.
1875 @itemize @bullet
1876 @item cortex_a8 smp_on : enable SMP mode, behaviour is as described above.
1877 @item cortex_a8 smp_off : disable SMP mode, the current target is the one
1878 displayed in the GDB session, only this target is now controlled by GDB
1879 session. This behaviour is useful during system boot up.
1880 @item cortex_a8 smp_gdb : display/fix the core id displayed in GDB session see
1881 following example.
1882 @end itemize
1883
1884 @example
1885 >cortex_a8 smp_gdb
1886 gdb coreid 0 -> -1
1887 #0 : coreid 0 is displayed to GDB ,
1888 #-> -1 : next resume triggers a real resume
1889 > cortex_a8 smp_gdb 1
1890 gdb coreid 0 -> 1
1891 #0 :coreid 0 is displayed to GDB ,
1892 #->1 : next resume displays coreid 1 to GDB
1893 > resume
1894 > cortex_a8 smp_gdb
1895 gdb coreid 1 -> 1
1896 #1 :coreid 1 is displayed to GDB ,
1897 #->1 : next resume displays coreid 1 to GDB
1898 > cortex_a8 smp_gdb -1
1899 gdb coreid 1 -> -1
1900 #1 :coreid 1 is displayed to GDB,
1901 #->-1 : next resume triggers a real resume
1902 @end example
1903
1904
1905 @subsection Chip Reset Setup
1906
1907 As a rule, you should put the @command{reset_config} command
1908 into the board file. Most things you think you know about a
1909 chip can be tweaked by the board.
1910
1911 Some chips have specific ways the TRST and SRST signals are
1912 managed. In the unusual case that these are @emph{chip specific}
1913 and can never be changed by board wiring, they could go here.
1914 For example, some chips can't support JTAG debugging without
1915 both signals.
1916
1917 Provide a @code{reset-assert} event handler if you can.
1918 Such a handler uses JTAG operations to reset the target,
1919 letting this target config be used in systems which don't
1920 provide the optional SRST signal, or on systems where you
1921 don't want to reset all targets at once.
1922 Such a handler might write to chip registers to force a reset,
1923 use a JRC to do that (preferable -- the target may be wedged!),
1924 or force a watchdog timer to trigger.
1925 (For Cortex-M3 targets, this is not necessary. The target
1926 driver knows how to use trigger an NVIC reset when SRST is
1927 not available.)
1928
1929 Some chips need special attention during reset handling if
1930 they're going to be used with JTAG.
1931 An example might be needing to send some commands right
1932 after the target's TAP has been reset, providing a
1933 @code{reset-deassert-post} event handler that writes a chip
1934 register to report that JTAG debugging is being done.
1935 Another would be reconfiguring the watchdog so that it stops
1936 counting while the core is halted in the debugger.
1937
1938 JTAG clocking constraints often change during reset, and in
1939 some cases target config files (rather than board config files)
1940 are the right places to handle some of those issues.
1941 For example, immediately after reset most chips run using a
1942 slower clock than they will use later.
1943 That means that after reset (and potentially, as OpenOCD
1944 first starts up) they must use a slower JTAG clock rate
1945 than they will use later.
1946 @xref{JTAG Speed}.
1947
1948 @quotation Important
1949 When you are debugging code that runs right after chip
1950 reset, getting these issues right is critical.
1951 In particular, if you see intermittent failures when
1952 OpenOCD verifies the scan chain after reset,
1953 look at how you are setting up JTAG clocking.
1954 @end quotation
1955
1956 @anchor{The init_targets procedure}
1957 @subsection The init_targets procedure
1958 @cindex init_targets procedure
1959
1960 Target config files can either be ``linear'' (script executed line-by-line when parsed in configuration stage,
1961 @xref{Configuration Stage},) or they can contain a special procedure called @code{init_targets}, which will be executed
1962 when entering run stage (after parsing all config files or after @code{init} command, @xref{Entering the Run Stage}.)
1963 Such procedure can be overriden by ``next level'' script (which sources the original). This concept faciliates code
1964 reuse when basic target config files provide generic configuration procedures and @code{init_targets} procedure, which
1965 can then be sourced and enchanced or changed in a ``more specific'' target config file. This is not possible with
1966 ``linear'' config scripts, because sourcing them executes every initialization commands they provide.
1967
1968 @example
1969 ### generic_file.cfg ###
1970
1971 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1972 # basic initialization procedure ...
1973 @}
1974
1975 proc init_targets @{@} @{
1976 # initializes generic chip with 4kB of flash and 1kB of RAM
1977 setup_my_chip MY_GENERIC_CHIP 4096 1024
1978 @}
1979
1980 ### specific_file.cfg ###
1981
1982 source [find target/generic_file.cfg]
1983
1984 proc init_targets @{@} @{
1985 # initializes specific chip with 128kB of flash and 64kB of RAM
1986 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1987 @}
1988 @end example
1989
1990 The easiest way to convert ``linear'' config files to @code{init_targets} version is to enclose every line of ``code''
1991 (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1992
1993 For an example of this scheme see LPC2000 target config files.
1994
1995 The @code{init_boards} procedure is a similar concept concerning board config files (@xref{The init_board procedure}.)
1996
1997 @subsection ARM Core Specific Hacks
1998
1999 If the chip has a DCC, enable it. If the chip is an ARM9 with some
2000 special high speed download features - enable it.
2001
2002 If present, the MMU, the MPU and the CACHE should be disabled.
2003
2004 Some ARM cores are equipped with trace support, which permits
2005 examination of the instruction and data bus activity. Trace
2006 activity is controlled through an ``Embedded Trace Module'' (ETM)
2007 on one of the core's scan chains. The ETM emits voluminous data
2008 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
2009 If you are using an external trace port,
2010 configure it in your board config file.
2011 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2012 configure it in your target config file.
2013
2014 @example
2015 etm config $_TARGETNAME 16 normal full etb
2016 etb config $_TARGETNAME $_CHIPNAME.etb
2017 @end example
2018
2019 @subsection Internal Flash Configuration
2020
2021 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2022
2023 @b{Never ever} in the ``target configuration file'' define any type of
2024 flash that is external to the chip. (For example a BOOT flash on
2025 Chip Select 0.) Such flash information goes in a board file - not
2026 the TARGET (chip) file.
2027
2028 Examples:
2029 @itemize @bullet
2030 @item at91sam7x256 - has 256K flash YES enable it.
2031 @item str912 - has flash internal YES enable it.
2032 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2033 @item pxa270 - again - CS0 flash - it goes in the board file.
2034 @end itemize
2035
2036 @anchor{Translating Configuration Files}
2037 @section Translating Configuration Files
2038 @cindex translation
2039 If you have a configuration file for another hardware debugger
2040 or toolset (Abatron, BDI2000, BDI3000, CCS,
2041 Lauterbach, Segger, Macraigor, etc.), translating
2042 it into OpenOCD syntax is often quite straightforward. The most tricky
2043 part of creating a configuration script is oftentimes the reset init
2044 sequence where e.g. PLLs, DRAM and the like is set up.
2045
2046 One trick that you can use when translating is to write small
2047 Tcl procedures to translate the syntax into OpenOCD syntax. This
2048 can avoid manual translation errors and make it easier to
2049 convert other scripts later on.
2050
2051 Example of transforming quirky arguments to a simple search and
2052 replace job:
2053
2054 @example
2055 # Lauterbach syntax(?)
2056 #
2057 # Data.Set c15:0x042f %long 0x40000015
2058 #
2059 # OpenOCD syntax when using procedure below.
2060 #
2061 # setc15 0x01 0x00050078
2062
2063 proc setc15 @{regs value@} @{
2064 global TARGETNAME
2065
2066 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2067
2068 arm mcr 15 [expr ($regs>>12)&0x7] \
2069 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2070 [expr ($regs>>8)&0x7] $value
2071 @}
2072 @end example
2073
2074
2075
2076 @node Daemon Configuration
2077 @chapter Daemon Configuration
2078 @cindex initialization
2079 The commands here are commonly found in the openocd.cfg file and are
2080 used to specify what TCP/IP ports are used, and how GDB should be
2081 supported.
2082
2083 @anchor{Configuration Stage}
2084 @section Configuration Stage
2085 @cindex configuration stage
2086 @cindex config command
2087
2088 When the OpenOCD server process starts up, it enters a
2089 @emph{configuration stage} which is the only time that
2090 certain commands, @emph{configuration commands}, may be issued.
2091 Normally, configuration commands are only available
2092 inside startup scripts.
2093
2094 In this manual, the definition of a configuration command is
2095 presented as a @emph{Config Command}, not as a @emph{Command}
2096 which may be issued interactively.
2097 The runtime @command{help} command also highlights configuration
2098 commands, and those which may be issued at any time.
2099
2100 Those configuration commands include declaration of TAPs,
2101 flash banks,
2102 the interface used for JTAG communication,
2103 and other basic setup.
2104 The server must leave the configuration stage before it
2105 may access or activate TAPs.
2106 After it leaves this stage, configuration commands may no
2107 longer be issued.
2108
2109 @anchor{Entering the Run Stage}
2110 @section Entering the Run Stage
2111
2112 The first thing OpenOCD does after leaving the configuration
2113 stage is to verify that it can talk to the scan chain
2114 (list of TAPs) which has been configured.
2115 It will warn if it doesn't find TAPs it expects to find,
2116 or finds TAPs that aren't supposed to be there.
2117 You should see no errors at this point.
2118 If you see errors, resolve them by correcting the
2119 commands you used to configure the server.
2120 Common errors include using an initial JTAG speed that's too
2121 fast, and not providing the right IDCODE values for the TAPs
2122 on the scan chain.
2123
2124 Once OpenOCD has entered the run stage, a number of commands
2125 become available.
2126 A number of these relate to the debug targets you may have declared.
2127 For example, the @command{mww} command will not be available until
2128 a target has been successfuly instantiated.
2129 If you want to use those commands, you may need to force
2130 entry to the run stage.
2131
2132 @deffn {Config Command} init
2133 This command terminates the configuration stage and
2134 enters the run stage. This helps when you need to have
2135 the startup scripts manage tasks such as resetting the target,
2136 programming flash, etc. To reset the CPU upon startup, add "init" and
2137 "reset" at the end of the config script or at the end of the OpenOCD
2138 command line using the @option{-c} command line switch.
2139
2140 If this command does not appear in any startup/configuration file
2141 OpenOCD executes the command for you after processing all
2142 configuration files and/or command line options.
2143
2144 @b{NOTE:} This command normally occurs at or near the end of your
2145 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2146 targets ready. For example: If your openocd.cfg file needs to
2147 read/write memory on your target, @command{init} must occur before
2148 the memory read/write commands. This includes @command{nand probe}.
2149 @end deffn
2150
2151 @deffn {Overridable Procedure} jtag_init
2152 This is invoked at server startup to verify that it can talk
2153 to the scan chain (list of TAPs) which has been configured.
2154
2155 The default implementation first tries @command{jtag arp_init},
2156 which uses only a lightweight JTAG reset before examining the
2157 scan chain.
2158 If that fails, it tries again, using a harder reset
2159 from the overridable procedure @command{init_reset}.
2160
2161 Implementations must have verified the JTAG scan chain before
2162 they return.
2163 This is done by calling @command{jtag arp_init}
2164 (or @command{jtag arp_init-reset}).
2165 @end deffn
2166
2167 @anchor{TCP/IP Ports}
2168 @section TCP/IP Ports
2169 @cindex TCP port
2170 @cindex server
2171 @cindex port
2172 @cindex security
2173 The OpenOCD server accepts remote commands in several syntaxes.
2174 Each syntax uses a different TCP/IP port, which you may specify
2175 only during configuration (before those ports are opened).
2176
2177 For reasons including security, you may wish to prevent remote
2178 access using one or more of these ports.
2179 In such cases, just specify the relevant port number as zero.
2180 If you disable all access through TCP/IP, you will need to
2181 use the command line @option{-pipe} option.
2182
2183 @deffn {Command} gdb_port [number]
2184 @cindex GDB server
2185 Normally gdb listens to a TCP/IP port, but GDB can also
2186 communicate via pipes(stdin/out or named pipes). The name
2187 "gdb_port" stuck because it covers probably more than 90% of
2188 the normal use cases.
2189
2190 No arguments reports GDB port. "pipe" means listen to stdin
2191 output to stdout, an integer is base port number, "disable"
2192 disables the gdb server.
2193
2194 When using "pipe", also use log_output to redirect the log
2195 output to a file so as not to flood the stdin/out pipes.
2196
2197 The -p/--pipe option is deprecated and a warning is printed
2198 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2199
2200 Any other string is interpreted as named pipe to listen to.
2201 Output pipe is the same name as input pipe, but with 'o' appended,
2202 e.g. /var/gdb, /var/gdbo.
2203
2204 The GDB port for the first target will be the base port, the
2205 second target will listen on gdb_port + 1, and so on.
2206 When not specified during the configuration stage,
2207 the port @var{number} defaults to 3333.
2208 @end deffn
2209
2210 @deffn {Command} tcl_port [number]
2211 Specify or query the port used for a simplified RPC
2212 connection that can be used by clients to issue TCL commands and get the
2213 output from the Tcl engine.
2214 Intended as a machine interface.
2215 When not specified during the configuration stage,
2216 the port @var{number} defaults to 6666.
2217
2218 @end deffn
2219
2220 @deffn {Command} telnet_port [number]
2221 Specify or query the
2222 port on which to listen for incoming telnet connections.
2223 This port is intended for interaction with one human through TCL commands.
2224 When not specified during the configuration stage,
2225 the port @var{number} defaults to 4444.
2226 When specified as zero, this port is not activated.
2227 @end deffn
2228
2229 @anchor{GDB Configuration}
2230 @section GDB Configuration
2231 @cindex GDB
2232 @cindex GDB configuration
2233 You can reconfigure some GDB behaviors if needed.
2234 The ones listed here are static and global.
2235 @xref{Target Configuration}, about configuring individual targets.
2236 @xref{Target Events}, about configuring target-specific event handling.
2237
2238 @anchor{gdb_breakpoint_override}
2239 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2240 Force breakpoint type for gdb @command{break} commands.
2241 This option supports GDB GUIs which don't
2242 distinguish hard versus soft breakpoints, if the default OpenOCD and
2243 GDB behaviour is not sufficient. GDB normally uses hardware
2244 breakpoints if the memory map has been set up for flash regions.
2245 @end deffn
2246
2247 @anchor{gdb_flash_program}
2248 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2249 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2250 vFlash packet is received.
2251 The default behaviour is @option{enable}.
2252 @end deffn
2253
2254 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2255 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2256 requested. GDB will then know when to set hardware breakpoints, and program flash
2257 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2258 for flash programming to work.
2259 Default behaviour is @option{enable}.
2260 @xref{gdb_flash_program}.
2261 @end deffn
2262
2263 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2264 Specifies whether data aborts cause an error to be reported
2265 by GDB memory read packets.
2266 The default behaviour is @option{disable};
2267 use @option{enable} see these errors reported.
2268 @end deffn
2269
2270 @anchor{Event Polling}
2271 @section Event Polling
2272
2273 Hardware debuggers are parts of asynchronous systems,
2274 where significant events can happen at any time.
2275 The OpenOCD server needs to detect some of these events,
2276 so it can report them to through TCL command line
2277 or to GDB.
2278
2279 Examples of such events include:
2280
2281 @itemize
2282 @item One of the targets can stop running ... maybe it triggers
2283 a code breakpoint or data watchpoint, or halts itself.
2284 @item Messages may be sent over ``debug message'' channels ... many
2285 targets support such messages sent over JTAG,
2286 for receipt by the person debugging or tools.
2287 @item Loss of power ... some adapters can detect these events.
2288 @item Resets not issued through JTAG ... such reset sources
2289 can include button presses or other system hardware, sometimes
2290 including the target itself (perhaps through a watchdog).
2291 @item Debug instrumentation sometimes supports event triggering
2292 such as ``trace buffer full'' (so it can quickly be emptied)
2293 or other signals (to correlate with code behavior).
2294 @end itemize
2295
2296 None of those events are signaled through standard JTAG signals.
2297 However, most conventions for JTAG connectors include voltage
2298 level and system reset (SRST) signal detection.
2299 Some connectors also include instrumentation signals, which
2300 can imply events when those signals are inputs.
2301
2302 In general, OpenOCD needs to periodically check for those events,
2303 either by looking at the status of signals on the JTAG connector
2304 or by sending synchronous ``tell me your status'' JTAG requests
2305 to the various active targets.
2306 There is a command to manage and monitor that polling,
2307 which is normally done in the background.
2308
2309 @deffn Command poll [@option{on}|@option{off}]
2310 Poll the current target for its current state.
2311 (Also, @pxref{target curstate}.)
2312 If that target is in debug mode, architecture
2313 specific information about the current state is printed.
2314 An optional parameter
2315 allows background polling to be enabled and disabled.
2316
2317 You could use this from the TCL command shell, or
2318 from GDB using @command{monitor poll} command.
2319 Leave background polling enabled while you're using GDB.
2320 @example
2321 > poll
2322 background polling: on
2323 target state: halted
2324 target halted in ARM state due to debug-request, \
2325 current mode: Supervisor
2326 cpsr: 0x800000d3 pc: 0x11081bfc
2327 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2328 >
2329 @end example
2330 @end deffn
2331
2332 @node Debug Adapter Configuration
2333 @chapter Debug Adapter Configuration
2334 @cindex config file, interface
2335 @cindex interface config file
2336
2337 Correctly installing OpenOCD includes making your operating system give
2338 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2339 are used to select which one is used, and to configure how it is used.
2340
2341 @quotation Note
2342 Because OpenOCD started out with a focus purely on JTAG, you may find
2343 places where it wrongly presumes JTAG is the only transport protocol
2344 in use. Be aware that recent versions of OpenOCD are removing that
2345 limitation. JTAG remains more functional than most other transports.
2346 Other transports do not support boundary scan operations, or may be
2347 specific to a given chip vendor. Some might be usable only for
2348 programming flash memory, instead of also for debugging.
2349 @end quotation
2350
2351 Debug Adapters/Interfaces/Dongles are normally configured
2352 through commands in an interface configuration
2353 file which is sourced by your @file{openocd.cfg} file, or
2354 through a command line @option{-f interface/....cfg} option.
2355
2356 @example
2357 source [find interface/olimex-jtag-tiny.cfg]
2358 @end example
2359
2360 These commands tell
2361 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2362 A few cases are so simple that you only need to say what driver to use:
2363
2364 @example
2365 # jlink interface
2366 interface jlink
2367 @end example
2368
2369 Most adapters need a bit more configuration than that.
2370
2371
2372 @section Interface Configuration
2373
2374 The interface command tells OpenOCD what type of debug adapter you are
2375 using. Depending on the type of adapter, you may need to use one or
2376 more additional commands to further identify or configure the adapter.
2377
2378 @deffn {Config Command} {interface} name
2379 Use the interface driver @var{name} to connect to the
2380 target.
2381 @end deffn
2382
2383 @deffn Command {interface_list}
2384 List the debug adapter drivers that have been built into
2385 the running copy of OpenOCD.
2386 @end deffn
2387 @deffn Command {interface transports} transport_name+
2388 Specifies the transports supported by this debug adapter.
2389 The adapter driver builds-in similar knowledge; use this only
2390 when external configuration (such as jumpering) changes what
2391 the hardware can support.
2392 @end deffn
2393
2394
2395
2396 @deffn Command {adapter_name}
2397 Returns the name of the debug adapter driver being used.
2398 @end deffn
2399
2400 @section Interface Drivers
2401
2402 Each of the interface drivers listed here must be explicitly
2403 enabled when OpenOCD is configured, in order to be made
2404 available at run time.
2405
2406 @deffn {Interface Driver} {amt_jtagaccel}
2407 Amontec Chameleon in its JTAG Accelerator configuration,
2408 connected to a PC's EPP mode parallel port.
2409 This defines some driver-specific commands:
2410
2411 @deffn {Config Command} {parport_port} number
2412 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2413 the number of the @file{/dev/parport} device.
2414 @end deffn
2415
2416 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2417 Displays status of RTCK option.
2418 Optionally sets that option first.
2419 @end deffn
2420 @end deffn
2421
2422 @deffn {Interface Driver} {arm-jtag-ew}
2423 Olimex ARM-JTAG-EW USB adapter
2424 This has one driver-specific command:
2425
2426 @deffn Command {armjtagew_info}
2427 Logs some status
2428 @end deffn
2429 @end deffn
2430
2431 @deffn {Interface Driver} {at91rm9200}
2432 Supports bitbanged JTAG from the local system,
2433 presuming that system is an Atmel AT91rm9200
2434 and a specific set of GPIOs is used.
2435 @c command: at91rm9200_device NAME
2436 @c chooses among list of bit configs ... only one option
2437 @end deffn
2438
2439 @deffn {Interface Driver} {dummy}
2440 A dummy software-only driver for debugging.
2441 @end deffn
2442
2443 @deffn {Interface Driver} {ep93xx}
2444 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2445 @end deffn
2446
2447 @deffn {Interface Driver} {ft2232}
2448 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2449 These interfaces have several commands, used to configure the driver
2450 before initializing the JTAG scan chain:
2451
2452 @deffn {Config Command} {ft2232_device_desc} description
2453 Provides the USB device description (the @emph{iProduct string})
2454 of the FTDI FT2232 device. If not
2455 specified, the FTDI default value is used. This setting is only valid
2456 if compiled with FTD2XX support.
2457 @end deffn
2458
2459 @deffn {Config Command} {ft2232_serial} serial-number
2460 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2461 in case the vendor provides unique IDs and more than one FT2232 device
2462 is connected to the host.
2463 If not specified, serial numbers are not considered.
2464 (Note that USB serial numbers can be arbitrary Unicode strings,
2465 and are not restricted to containing only decimal digits.)
2466 @end deffn
2467
2468 @deffn {Config Command} {ft2232_layout} name
2469 Each vendor's FT2232 device can use different GPIO signals
2470 to control output-enables, reset signals, and LEDs.
2471 Currently valid layout @var{name} values include:
2472 @itemize @minus
2473 @item @b{axm0432_jtag} Axiom AXM-0432
2474 @item @b{comstick} Hitex STR9 comstick
2475 @item @b{cortino} Hitex Cortino JTAG interface
2476 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
2477 either for the local Cortex-M3 (SRST only)
2478 or in a passthrough mode (neither SRST nor TRST)
2479 This layout can not support the SWO trace mechanism, and should be
2480 used only for older boards (before rev C).
2481 @item @b{luminary_icdi} This layout should be used with most Luminary
2482 eval boards, including Rev C LM3S811 eval boards and the eponymous
2483 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2484 to debug some other target. It can support the SWO trace mechanism.
2485 @item @b{flyswatter} Tin Can Tools Flyswatter
2486 @item @b{icebear} ICEbear JTAG adapter from Section 5
2487 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2488 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2489 @item @b{m5960} American Microsystems M5960
2490 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2491 @item @b{oocdlink} OOCDLink
2492 @c oocdlink ~= jtagkey_prototype_v1
2493 @item @b{redbee-econotag} Integrated with a Redbee development board.
2494 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2495 @item @b{sheevaplug} Marvell Sheevaplug development kit
2496 @item @b{signalyzer} Xverve Signalyzer
2497 @item @b{stm32stick} Hitex STM32 Performance Stick
2498 @item @b{turtelizer2} egnite Software turtelizer2
2499 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2500 @end itemize
2501 @end deffn
2502
2503 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2504 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2505 default values are used.
2506 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2507 @example
2508 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2509 @end example
2510 @end deffn
2511
2512 @deffn {Config Command} {ft2232_latency} ms
2513 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2514 ft2232_read() fails to return the expected number of bytes. This can be caused by
2515 USB communication delays and has proved hard to reproduce and debug. Setting the
2516 FT2232 latency timer to a larger value increases delays for short USB packets but it
2517 also reduces the risk of timeouts before receiving the expected number of bytes.
2518 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2519 @end deffn
2520
2521 For example, the interface config file for a
2522 Turtelizer JTAG Adapter looks something like this:
2523
2524 @example
2525 interface ft2232
2526 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2527 ft2232_layout turtelizer2
2528 ft2232_vid_pid 0x0403 0xbdc8
2529 @end example
2530 @end deffn
2531
2532 @deffn {Interface Driver} {remote_bitbang}
2533 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2534 with a remote process and sends ASCII encoded bitbang requests to that process
2535 instead of directly driving JTAG.
2536
2537 The remote_bitbang driver is useful for debugging software running on
2538 processors which are being simulated.
2539
2540 @deffn {Config Command} {remote_bitbang_port} number
2541 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2542 sockets instead of TCP.
2543 @end deffn
2544
2545 @deffn {Config Command} {remote_bitbang_host} hostname
2546 Specifies the hostname of the remote process to connect to using TCP, or the
2547 name of the UNIX socket to use if remote_bitbang_port is 0.
2548 @end deffn
2549
2550 For example, to connect remotely via TCP to the host foobar you might have
2551 something like:
2552
2553 @example
2554 interface remote_bitbang
2555 remote_bitbang_port 3335
2556 remote_bitbang_host foobar
2557 @end example
2558
2559 To connect to another process running locally via UNIX sockets with socket
2560 named mysocket:
2561
2562 @example
2563 interface remote_bitbang
2564 remote_bitbang_port 0
2565 remote_bitbang_host mysocket
2566 @end example
2567 @end deffn
2568
2569 @deffn {Interface Driver} {usb_blaster}
2570 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2571 for FTDI chips. These interfaces have several commands, used to
2572 configure the driver before initializing the JTAG scan chain:
2573
2574 @deffn {Config Command} {usb_blaster_device_desc} description
2575 Provides the USB device description (the @emph{iProduct string})
2576 of the FTDI FT245 device. If not
2577 specified, the FTDI default value is used. This setting is only valid
2578 if compiled with FTD2XX support.
2579 @end deffn
2580
2581 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2582 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2583 default values are used.
2584 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2585 Altera USB-Blaster (default):
2586 @example
2587 usb_blaster_vid_pid 0x09FB 0x6001
2588 @end example
2589 The following VID/PID is for Kolja Waschk's USB JTAG:
2590 @example
2591 usb_blaster_vid_pid 0x16C0 0x06AD
2592 @end example
2593 @end deffn
2594
2595 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2596 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2597 female JTAG header). These pins can be used as SRST and/or TRST provided the
2598 appropriate connections are made on the target board.
2599
2600 For example, to use pin 6 as SRST (as with an AVR board):
2601 @example
2602 $_TARGETNAME configure -event reset-assert \
2603 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2604 @end example
2605 @end deffn
2606
2607 @end deffn
2608
2609 @deffn {Interface Driver} {gw16012}
2610 Gateworks GW16012 JTAG programmer.
2611 This has one driver-specific command:
2612
2613 @deffn {Config Command} {parport_port} [port_number]
2614 Display either the address of the I/O port
2615 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2616 If a parameter is provided, first switch to use that port.
2617 This is a write-once setting.
2618 @end deffn
2619 @end deffn
2620
2621 @deffn {Interface Driver} {jlink}
2622 Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
2623
2624 @quotation Compatibility Note
2625 Segger released many firmware versions for the many harware versions they
2626 produced. OpenOCD was extensively tested and intended to run on all of them,
2627 but some combinations were reported as incompatible. As a general
2628 recommendation, it is advisable to use the latest firmware version
2629 available for each hardware version. However the current V8 is a moving
2630 target, and Segger firmware versions released after the OpenOCD was
2631 released may not be compatible. In such cases it is recommended to
2632 revert to the last known functional version. For 0.5.0, this is from
2633 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2634 version is from "May 3 2012 18:36:22", packed with 4.46f.
2635 @end quotation
2636
2637 @deffn {Command} {jlink caps}
2638 Display the device firmware capabilities.
2639 @end deffn
2640 @deffn {Command} {jlink info}
2641 Display various device information, like hardware version, firmware version, current bus status.
2642 @end deffn
2643 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2644 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2645 @end deffn
2646 @deffn {Command} {jlink config}
2647 Display the J-Link configuration.
2648 @end deffn
2649 @deffn {Command} {jlink config kickstart} [val]
2650 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2651 @end deffn
2652 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2653 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2654 @end deffn
2655 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2656 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2657 E the bit of the subnet mask and
2658 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2659 @end deffn
2660 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2661 Set the USB address; this will also change the product id. Without argument, show the USB address.
2662 @end deffn
2663 @deffn {Command} {jlink config reset}
2664 Reset the current configuration.
2665 @end deffn
2666 @deffn {Command} {jlink config save}
2667 Save the current configuration to the internal persistent storage.
2668 @end deffn
2669 @deffn {Config} {jlink pid} val
2670 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2671 @end deffn
2672 @end deffn
2673
2674 @deffn {Interface Driver} {parport}
2675 Supports PC parallel port bit-banging cables:
2676 Wigglers, PLD download cable, and more.
2677 These interfaces have several commands, used to configure the driver
2678 before initializing the JTAG scan chain:
2679
2680 @deffn {Config Command} {parport_cable} name
2681 Set the layout of the parallel port cable used to connect to the target.
2682 This is a write-once setting.
2683 Currently valid cable @var{name} values include:
2684
2685 @itemize @minus
2686 @item @b{altium} Altium Universal JTAG cable.
2687 @item @b{arm-jtag} Same as original wiggler except SRST and
2688 TRST connections reversed and TRST is also inverted.
2689 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2690 in configuration mode. This is only used to
2691 program the Chameleon itself, not a connected target.
2692 @item @b{dlc5} The Xilinx Parallel cable III.
2693 @item @b{flashlink} The ST Parallel cable.
2694 @item @b{lattice} Lattice ispDOWNLOAD Cable
2695 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2696 some versions of
2697 Amontec's Chameleon Programmer. The new version available from
2698 the website uses the original Wiggler layout ('@var{wiggler}')
2699 @item @b{triton} The parallel port adapter found on the
2700 ``Karo Triton 1 Development Board''.
2701 This is also the layout used by the HollyGates design
2702 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2703 @item @b{wiggler} The original Wiggler layout, also supported by
2704 several clones, such as the Olimex ARM-JTAG
2705 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2706 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2707 @end itemize
2708 @end deffn
2709
2710 @deffn {Config Command} {parport_port} [port_number]
2711 Display either the address of the I/O port
2712 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2713 If a parameter is provided, first switch to use that port.
2714 This is a write-once setting.
2715
2716 When using PPDEV to access the parallel port, use the number of the parallel port:
2717 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2718 you may encounter a problem.
2719 @end deffn
2720
2721 @deffn Command {parport_toggling_time} [nanoseconds]
2722 Displays how many nanoseconds the hardware needs to toggle TCK;
2723 the parport driver uses this value to obey the
2724 @command{adapter_khz} configuration.
2725 When the optional @var{nanoseconds} parameter is given,
2726 that setting is changed before displaying the current value.
2727
2728 The default setting should work reasonably well on commodity PC hardware.
2729 However, you may want to calibrate for your specific hardware.
2730 @quotation Tip
2731 To measure the toggling time with a logic analyzer or a digital storage
2732 oscilloscope, follow the procedure below:
2733 @example
2734 > parport_toggling_time 1000
2735 > adapter_khz 500
2736 @end example
2737 This sets the maximum JTAG clock speed of the hardware, but
2738 the actual speed probably deviates from the requested 500 kHz.
2739 Now, measure the time between the two closest spaced TCK transitions.
2740 You can use @command{runtest 1000} or something similar to generate a
2741 large set of samples.
2742 Update the setting to match your measurement:
2743 @example
2744 > parport_toggling_time <measured nanoseconds>
2745 @end example
2746 Now the clock speed will be a better match for @command{adapter_khz rate}
2747 commands given in OpenOCD scripts and event handlers.
2748
2749 You can do something similar with many digital multimeters, but note
2750 that you'll probably need to run the clock continuously for several
2751 seconds before it decides what clock rate to show. Adjust the
2752 toggling time up or down until the measured clock rate is a good
2753 match for the adapter_khz rate you specified; be conservative.
2754 @end quotation
2755 @end deffn
2756
2757 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2758 This will configure the parallel driver to write a known
2759 cable-specific value to the parallel interface on exiting OpenOCD.
2760 @end deffn
2761
2762 For example, the interface configuration file for a
2763 classic ``Wiggler'' cable on LPT2 might look something like this:
2764
2765 @example
2766 interface parport
2767 parport_port 0x278
2768 parport_cable wiggler
2769 @end example
2770 @end deffn
2771
2772 @deffn {Interface Driver} {presto}
2773 ASIX PRESTO USB JTAG programmer.
2774 @deffn {Config Command} {presto_serial} serial_string
2775 Configures the USB serial number of the Presto device to use.
2776 @end deffn
2777 @end deffn
2778
2779 @deffn {Interface Driver} {rlink}
2780 Raisonance RLink USB adapter
2781 @end deffn
2782
2783 @deffn {Interface Driver} {usbprog}
2784 usbprog is a freely programmable USB adapter.
2785 @end deffn
2786
2787 @deffn {Interface Driver} {vsllink}
2788 vsllink is part of Versaloon which is a versatile USB programmer.
2789
2790 @quotation Note
2791 This defines quite a few driver-specific commands,
2792 which are not currently documented here.
2793 @end quotation
2794 @end deffn
2795
2796 @deffn {Interface Driver} {stlink}
2797 ST Micro ST-LINK adapter.
2798
2799 @deffn {Config Command} {stlink_device_desc} description
2800 Currently Not Supported.
2801 @end deffn
2802
2803 @deffn {Config Command} {stlink_serial} serial
2804 Currently Not Supported.
2805 @end deffn
2806
2807 @deffn {Config Command} {stlink_layout} (@option{sg}|@option{usb})
2808 Specifies the stlink layout to use.
2809 @end deffn
2810
2811 @deffn {Config Command} {stlink_vid_pid} vid pid
2812 The vendor ID and product ID of the STLINK device.
2813 @end deffn
2814
2815 @deffn {Config Command} {stlink_api} api_level
2816 Manually sets the stlink api used, valid options are 1 or 2.
2817 @end deffn
2818 @end deffn
2819
2820 @deffn {Interface Driver} {opendous}
2821 opendous-jtag is a freely programmable USB adapter.
2822 @end deffn
2823
2824 @deffn {Interface Driver} {ulink}
2825 This is the Keil ULINK v1 JTAG debugger.
2826 @end deffn
2827
2828 @deffn {Interface Driver} {ZY1000}
2829 This is the Zylin ZY1000 JTAG debugger.
2830 @end deffn
2831
2832 @quotation Note
2833 This defines some driver-specific commands,
2834 which are not currently documented here.
2835 @end quotation
2836
2837 @deffn Command power [@option{on}|@option{off}]
2838 Turn power switch to target on/off.
2839 No arguments: print status.
2840 @end deffn
2841
2842 @section Transport Configuration
2843 @cindex Transport
2844 As noted earlier, depending on the version of OpenOCD you use,
2845 and the debug adapter you are using,
2846 several transports may be available to
2847 communicate with debug targets (or perhaps to program flash memory).
2848 @deffn Command {transport list}
2849 displays the names of the transports supported by this
2850 version of OpenOCD.
2851 @end deffn
2852
2853 @deffn Command {transport select} transport_name
2854 Select which of the supported transports to use in this OpenOCD session.
2855 The transport must be supported by the debug adapter hardware and by the
2856 version of OPenOCD you are using (including the adapter's driver).
2857 No arguments: returns name of session's selected transport.
2858 @end deffn
2859
2860 @subsection JTAG Transport
2861 @cindex JTAG
2862 JTAG is the original transport supported by OpenOCD, and most
2863 of the OpenOCD commands support it.
2864 JTAG transports expose a chain of one or more Test Access Points (TAPs),
2865 each of which must be explicitly declared.
2866 JTAG supports both debugging and boundary scan testing.
2867 Flash programming support is built on top of debug support.
2868 @subsection SWD Transport
2869 @cindex SWD
2870 @cindex Serial Wire Debug
2871 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
2872 Debug Access Point (DAP, which must be explicitly declared.
2873 (SWD uses fewer signal wires than JTAG.)
2874 SWD is debug-oriented, and does not support boundary scan testing.
2875 Flash programming support is built on top of debug support.
2876 (Some processors support both JTAG and SWD.)
2877 @deffn Command {swd newdap} ...
2878 Declares a single DAP which uses SWD transport.
2879 Parameters are currently the same as "jtag newtap" but this is
2880 expected to change.
2881 @end deffn
2882 @deffn Command {swd wcr trn prescale}
2883 Updates TRN (turnaraound delay) and prescaling.fields of the
2884 Wire Control Register (WCR).
2885 No parameters: displays current settings.
2886 @end deffn
2887
2888 @subsection SPI Transport
2889 @cindex SPI
2890 @cindex Serial Peripheral Interface
2891 The Serial Peripheral Interface (SPI) is a general purpose transport
2892 which uses four wire signaling. Some processors use it as part of a
2893 solution for flash programming.
2894
2895 @anchor{JTAG Speed}
2896 @section JTAG Speed
2897 JTAG clock setup is part of system setup.
2898 It @emph{does not belong with interface setup} since any interface
2899 only knows a few of the constraints for the JTAG clock speed.
2900 Sometimes the JTAG speed is
2901 changed during the target initialization process: (1) slow at
2902 reset, (2) program the CPU clocks, (3) run fast.
2903 Both the "slow" and "fast" clock rates are functions of the
2904 oscillators used, the chip, the board design, and sometimes
2905 power management software that may be active.
2906
2907 The speed used during reset, and the scan chain verification which
2908 follows reset, can be adjusted using a @code{reset-start}
2909 target event handler.
2910 It can then be reconfigured to a faster speed by a
2911 @code{reset-init} target event handler after it reprograms those
2912 CPU clocks, or manually (if something else, such as a boot loader,
2913 sets up those clocks).
2914 @xref{Target Events}.
2915 When the initial low JTAG speed is a chip characteristic, perhaps
2916 because of a required oscillator speed, provide such a handler
2917 in the target config file.
2918 When that speed is a function of a board-specific characteristic
2919 such as which speed oscillator is used, it belongs in the board
2920 config file instead.
2921 In both cases it's safest to also set the initial JTAG clock rate
2922 to that same slow speed, so that OpenOCD never starts up using a
2923 clock speed that's faster than the scan chain can support.
2924
2925 @example
2926 jtag_rclk 3000
2927 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
2928 @end example
2929
2930 If your system supports adaptive clocking (RTCK), configuring
2931 JTAG to use that is probably the most robust approach.
2932 However, it introduces delays to synchronize clocks; so it
2933 may not be the fastest solution.
2934
2935 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
2936 instead of @command{adapter_khz}, but only for (ARM) cores and boards
2937 which support adaptive clocking.
2938
2939 @deffn {Command} adapter_khz max_speed_kHz
2940 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
2941 JTAG interfaces usually support a limited number of
2942 speeds. The speed actually used won't be faster
2943 than the speed specified.
2944
2945 Chip data sheets generally include a top JTAG clock rate.
2946 The actual rate is often a function of a CPU core clock,
2947 and is normally less than that peak rate.
2948 For example, most ARM cores accept at most one sixth of the CPU clock.
2949
2950 Speed 0 (khz) selects RTCK method.
2951 @xref{FAQ RTCK}.
2952 If your system uses RTCK, you won't need to change the
2953 JTAG clocking after setup.
2954 Not all interfaces, boards, or targets support ``rtck''.
2955 If the interface device can not
2956 support it, an error is returned when you try to use RTCK.
2957 @end deffn
2958
2959 @defun jtag_rclk fallback_speed_kHz
2960 @cindex adaptive clocking
2961 @cindex RTCK
2962 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
2963 If that fails (maybe the interface, board, or target doesn't
2964 support it), falls back to the specified frequency.
2965 @example
2966 # Fall back to 3mhz if RTCK is not supported
2967 jtag_rclk 3000
2968 @end example
2969 @end defun
2970
2971 @node Reset Configuration
2972 @chapter Reset Configuration
2973 @cindex Reset Configuration
2974
2975 Every system configuration may require a different reset
2976 configuration. This can also be quite confusing.
2977 Resets also interact with @var{reset-init} event handlers,
2978 which do things like setting up clocks and DRAM, and
2979 JTAG clock rates. (@xref{JTAG Speed}.)
2980 They can also interact with JTAG routers.
2981 Please see the various board files for examples.
2982
2983 @quotation Note
2984 To maintainers and integrators:
2985 Reset configuration touches several things at once.
2986 Normally the board configuration file
2987 should define it and assume that the JTAG adapter supports
2988 everything that's wired up to the board's JTAG connector.
2989
2990 However, the target configuration file could also make note
2991 of something the silicon vendor has done inside the chip,
2992 which will be true for most (or all) boards using that chip.
2993 And when the JTAG adapter doesn't support everything, the
2994 user configuration file will need to override parts of
2995 the reset configuration provided by other files.
2996 @end quotation
2997
2998 @section Types of Reset
2999
3000 There are many kinds of reset possible through JTAG, but
3001 they may not all work with a given board and adapter.
3002 That's part of why reset configuration can be error prone.
3003
3004 @itemize @bullet
3005 @item
3006 @emph{System Reset} ... the @emph{SRST} hardware signal
3007 resets all chips connected to the JTAG adapter, such as processors,
3008 power management chips, and I/O controllers. Normally resets triggered
3009 with this signal behave exactly like pressing a RESET button.
3010 @item
3011 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3012 just the TAP controllers connected to the JTAG adapter.
3013 Such resets should not be visible to the rest of the system; resetting a
3014 device's TAP controller just puts that controller into a known state.
3015 @item
3016 @emph{Emulation Reset} ... many devices can be reset through JTAG
3017 commands. These resets are often distinguishable from system
3018 resets, either explicitly (a "reset reason" register says so)
3019 or implicitly (not all parts of the chip get reset).
3020 @item
3021 @emph{Other Resets} ... system-on-chip devices often support
3022 several other types of reset.
3023 You may need to arrange that a watchdog timer stops
3024 while debugging, preventing a watchdog reset.
3025 There may be individual module resets.
3026 @end itemize
3027
3028 In the best case, OpenOCD can hold SRST, then reset
3029 the TAPs via TRST and send commands through JTAG to halt the
3030 CPU at the reset vector before the 1st instruction is executed.
3031 Then when it finally releases the SRST signal, the system is
3032 halted under debugger control before any code has executed.
3033 This is the behavior required to support the @command{reset halt}
3034 and @command{reset init} commands; after @command{reset init} a
3035 board-specific script might do things like setting up DRAM.
3036 (@xref{Reset Command}.)
3037
3038 @anchor{SRST and TRST Issues}
3039 @section SRST and TRST Issues
3040
3041 Because SRST and TRST are hardware signals, they can have a
3042 variety of system-specific constraints. Some of the most
3043 common issues are:
3044
3045 @itemize @bullet
3046
3047 @item @emph{Signal not available} ... Some boards don't wire
3048 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3049 support such signals even if they are wired up.
3050 Use the @command{reset_config} @var{signals} options to say
3051 when either of those signals is not connected.
3052 When SRST is not available, your code might not be able to rely
3053 on controllers having been fully reset during code startup.
3054 Missing TRST is not a problem, since JTAG-level resets can
3055 be triggered using with TMS signaling.
3056
3057 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3058 adapter will connect SRST to TRST, instead of keeping them separate.
3059 Use the @command{reset_config} @var{combination} options to say
3060 when those signals aren't properly independent.
3061
3062 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3063 delay circuit, reset supervisor, or on-chip features can extend
3064 the effect of a JTAG adapter's reset for some time after the adapter
3065 stops issuing the reset. For example, there may be chip or board
3066 requirements that all reset pulses last for at least a
3067 certain amount of time; and reset buttons commonly have
3068 hardware debouncing.
3069 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3070 commands to say when extra delays are needed.
3071
3072 @item @emph{Drive type} ... Reset lines often have a pullup
3073 resistor, letting the JTAG interface treat them as open-drain
3074 signals. But that's not a requirement, so the adapter may need
3075 to use push/pull output drivers.
3076 Also, with weak pullups it may be advisable to drive
3077 signals to both levels (push/pull) to minimize rise times.
3078 Use the @command{reset_config} @var{trst_type} and
3079 @var{srst_type} parameters to say how to drive reset signals.
3080
3081 @item @emph{Special initialization} ... Targets sometimes need
3082 special JTAG initialization sequences to handle chip-specific
3083 issues (not limited to errata).
3084 For example, certain JTAG commands might need to be issued while
3085 the system as a whole is in a reset state (SRST active)
3086 but the JTAG scan chain is usable (TRST inactive).
3087 Many systems treat combined assertion of SRST and TRST as a
3088 trigger for a harder reset than SRST alone.
3089 Such custom reset handling is discussed later in this chapter.
3090 @end itemize
3091
3092 There can also be other issues.
3093 Some devices don't fully conform to the JTAG specifications.
3094 Trivial system-specific differences are common, such as
3095 SRST and TRST using slightly different names.
3096 There are also vendors who distribute key JTAG documentation for
3097 their chips only to developers who have signed a Non-Disclosure
3098 Agreement (NDA).
3099
3100 Sometimes there are chip-specific extensions like a requirement to use
3101 the normally-optional TRST signal (precluding use of JTAG adapters which
3102 don't pass TRST through), or needing extra steps to complete a TAP reset.
3103
3104 In short, SRST and especially TRST handling may be very finicky,
3105 needing to cope with both architecture and board specific constraints.
3106
3107 @section Commands for Handling Resets
3108
3109 @deffn {Command} adapter_nsrst_assert_width milliseconds
3110 Minimum amount of time (in milliseconds) OpenOCD should wait
3111 after asserting nSRST (active-low system reset) before
3112 allowing it to be deasserted.
3113 @end deffn
3114
3115 @deffn {Command} adapter_nsrst_delay milliseconds
3116 How long (in milliseconds) OpenOCD should wait after deasserting
3117 nSRST (active-low system reset) before starting new JTAG operations.
3118 When a board has a reset button connected to SRST line it will
3119 probably have hardware debouncing, implying you should use this.
3120 @end deffn
3121
3122 @deffn {Command} jtag_ntrst_assert_width milliseconds
3123 Minimum amount of time (in milliseconds) OpenOCD should wait
3124 after asserting nTRST (active-low JTAG TAP reset) before
3125 allowing it to be deasserted.
3126 @end deffn
3127
3128 @deffn {Command} jtag_ntrst_delay milliseconds
3129 How long (in milliseconds) OpenOCD should wait after deasserting
3130 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3131 @end deffn
3132
3133 @deffn {Command} reset_config mode_flag ...
3134 This command displays or modifies the reset configuration
3135 of your combination of JTAG board and target in target
3136 configuration scripts.
3137
3138 Information earlier in this section describes the kind of problems
3139 the command is intended to address (@pxref{SRST and TRST Issues}).
3140 As a rule this command belongs only in board config files,
3141 describing issues like @emph{board doesn't connect TRST};
3142 or in user config files, addressing limitations derived
3143 from a particular combination of interface and board.
3144 (An unlikely example would be using a TRST-only adapter
3145 with a board that only wires up SRST.)
3146
3147 The @var{mode_flag} options can be specified in any order, but only one
3148 of each type -- @var{signals}, @var{combination},
3149 @var{gates},
3150 @var{trst_type},
3151 and @var{srst_type} -- may be specified at a time.
3152 If you don't provide a new value for a given type, its previous
3153 value (perhaps the default) is unchanged.
3154 For example, this means that you don't need to say anything at all about
3155 TRST just to declare that if the JTAG adapter should want to drive SRST,
3156 it must explicitly be driven high (@option{srst_push_pull}).
3157
3158 @itemize
3159 @item
3160 @var{signals} can specify which of the reset signals are connected.
3161 For example, If the JTAG interface provides SRST, but the board doesn't
3162 connect that signal properly, then OpenOCD can't use it.
3163 Possible values are @option{none} (the default), @option{trst_only},
3164 @option{srst_only} and @option{trst_and_srst}.
3165
3166 @quotation Tip
3167 If your board provides SRST and/or TRST through the JTAG connector,
3168 you must declare that so those signals can be used.
3169 @end quotation
3170
3171 @item
3172 The @var{combination} is an optional value specifying broken reset
3173 signal implementations.
3174 The default behaviour if no option given is @option{separate},
3175 indicating everything behaves normally.
3176 @option{srst_pulls_trst} states that the
3177 test logic is reset together with the reset of the system (e.g. NXP
3178 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3179 the system is reset together with the test logic (only hypothetical, I
3180 haven't seen hardware with such a bug, and can be worked around).
3181 @option{combined} implies both @option{srst_pulls_trst} and
3182 @option{trst_pulls_srst}.
3183
3184 @item
3185 The @var{gates} tokens control flags that describe some cases where
3186 JTAG may be unvailable during reset.
3187 @option{srst_gates_jtag} (default)
3188 indicates that asserting SRST gates the
3189 JTAG clock. This means that no communication can happen on JTAG
3190 while SRST is asserted.
3191 Its converse is @option{srst_nogate}, indicating that JTAG commands
3192 can safely be issued while SRST is active.
3193 @end itemize
3194
3195 The optional @var{trst_type} and @var{srst_type} parameters allow the
3196 driver mode of each reset line to be specified. These values only affect
3197 JTAG interfaces with support for different driver modes, like the Amontec
3198 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3199 relevant signal (TRST or SRST) is not connected.
3200
3201 @itemize
3202 @item
3203 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3204 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3205 Most boards connect this signal to a pulldown, so the JTAG TAPs
3206 never leave reset unless they are hooked up to a JTAG adapter.
3207
3208 @item
3209 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3210 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3211 Most boards connect this signal to a pullup, and allow the
3212 signal to be pulled low by various events including system
3213 powerup and pressing a reset button.
3214 @end itemize
3215 @end deffn
3216
3217 @section Custom Reset Handling
3218 @cindex events
3219
3220 OpenOCD has several ways to help support the various reset
3221 mechanisms provided by chip and board vendors.
3222 The commands shown in the previous section give standard parameters.
3223 There are also @emph{event handlers} associated with TAPs or Targets.
3224 Those handlers are Tcl procedures you can provide, which are invoked
3225 at particular points in the reset sequence.
3226
3227 @emph{When SRST is not an option} you must set
3228 up a @code{reset-assert} event handler for your target.
3229 For example, some JTAG adapters don't include the SRST signal;
3230 and some boards have multiple targets, and you won't always
3231 want to reset everything at once.
3232
3233 After configuring those mechanisms, you might still
3234 find your board doesn't start up or reset correctly.
3235 For example, maybe it needs a slightly different sequence
3236 of SRST and/or TRST manipulations, because of quirks that
3237 the @command{reset_config} mechanism doesn't address;
3238 or asserting both might trigger a stronger reset, which
3239 needs special attention.
3240
3241 Experiment with lower level operations, such as @command{jtag_reset}
3242 and the @command{jtag arp_*} operations shown here,
3243 to find a sequence of operations that works.
3244 @xref{JTAG Commands}.
3245 When you find a working sequence, it can be used to override
3246 @command{jtag_init}, which fires during OpenOCD startup
3247 (@pxref{Configuration Stage});
3248 or @command{init_reset}, which fires during reset processing.
3249
3250 You might also want to provide some project-specific reset
3251 schemes. For example, on a multi-target board the standard
3252 @command{reset} command would reset all targets, but you
3253 may need the ability to reset only one target at time and
3254 thus want to avoid using the board-wide SRST signal.
3255
3256 @deffn {Overridable Procedure} init_reset mode
3257 This is invoked near the beginning of the @command{reset} command,
3258 usually to provide as much of a cold (power-up) reset as practical.
3259 By default it is also invoked from @command{jtag_init} if
3260 the scan chain does not respond to pure JTAG operations.
3261 The @var{mode} parameter is the parameter given to the
3262 low level reset command (@option{halt},
3263 @option{init}, or @option{run}), @option{setup},
3264 or potentially some other value.
3265
3266 The default implementation just invokes @command{jtag arp_init-reset}.
3267 Replacements will normally build on low level JTAG
3268 operations such as @command{jtag_reset}.
3269 Operations here must not address individual TAPs
3270 (or their associated targets)
3271 until the JTAG scan chain has first been verified to work.
3272
3273 Implementations must have verified the JTAG scan chain before
3274 they return.
3275 This is done by calling @command{jtag arp_init}
3276 (or @command{jtag arp_init-reset}).
3277 @end deffn
3278
3279 @deffn Command {jtag arp_init}
3280 This validates the scan chain using just the four
3281 standard JTAG signals (TMS, TCK, TDI, TDO).
3282 It starts by issuing a JTAG-only reset.
3283 Then it performs checks to verify that the scan chain configuration
3284 matches the TAPs it can observe.
3285 Those checks include checking IDCODE values for each active TAP,
3286 and verifying the length of their instruction registers using
3287 TAP @code{-ircapture} and @code{-irmask} values.
3288 If these tests all pass, TAP @code{setup} events are
3289 issued to all TAPs with handlers for that event.
3290 @end deffn
3291
3292 @deffn Command {jtag arp_init-reset}
3293 This uses TRST and SRST to try resetting
3294 everything on the JTAG scan chain
3295 (and anything else connected to SRST).
3296 It then invokes the logic of @command{jtag arp_init}.
3297 @end deffn
3298
3299
3300 @node TAP Declaration
3301 @chapter TAP Declaration
3302 @cindex TAP declaration
3303 @cindex TAP configuration
3304
3305 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3306 TAPs serve many roles, including:
3307
3308 @itemize @bullet
3309 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
3310 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
3311 Others do it indirectly, making a CPU do it.
3312 @item @b{Program Download} Using the same CPU support GDB uses,
3313 you can initialize a DRAM controller, download code to DRAM, and then
3314 start running that code.
3315 @item @b{Boundary Scan} Most chips support boundary scan, which
3316 helps test for board assembly problems like solder bridges
3317 and missing connections
3318 @end itemize
3319
3320 OpenOCD must know about the active TAPs on your board(s).
3321 Setting up the TAPs is the core task of your configuration files.
3322 Once those TAPs are set up, you can pass their names to code
3323 which sets up CPUs and exports them as GDB targets,
3324 probes flash memory, performs low-level JTAG operations, and more.
3325
3326 @section Scan Chains
3327 @cindex scan chain
3328
3329 TAPs are part of a hardware @dfn{scan chain},
3330 which is daisy chain of TAPs.
3331 They also need to be added to
3332 OpenOCD's software mirror of that hardware list,
3333 giving each member a name and associating other data with it.
3334 Simple scan chains, with a single TAP, are common in
3335 systems with a single microcontroller or microprocessor.
3336 More complex chips may have several TAPs internally.
3337 Very complex scan chains might have a dozen or more TAPs:
3338 several in one chip, more in the next, and connecting
3339 to other boards with their own chips and TAPs.
3340
3341 You can display the list with the @command{scan_chain} command.
3342 (Don't confuse this with the list displayed by the @command{targets}
3343 command, presented in the next chapter.
3344 That only displays TAPs for CPUs which are configured as
3345 debugging targets.)
3346 Here's what the scan chain might look like for a chip more than one TAP:
3347
3348 @verbatim
3349 TapName Enabled IdCode Expected IrLen IrCap IrMask
3350 -- ------------------ ------- ---------- ---------- ----- ----- ------
3351 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3352 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3353 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3354 @end verbatim
3355
3356 OpenOCD can detect some of that information, but not all
3357 of it. @xref{Autoprobing}.
3358 Unfortunately those TAPs can't always be autoconfigured,
3359 because not all devices provide good support for that.
3360 JTAG doesn't require supporting IDCODE instructions, and
3361 chips with JTAG routers may not link TAPs into the chain
3362 until they are told to do so.
3363
3364 The configuration mechanism currently supported by OpenOCD
3365 requires explicit configuration of all TAP devices using
3366 @command{jtag newtap} commands, as detailed later in this chapter.
3367 A command like this would declare one tap and name it @code{chip1.cpu}:
3368
3369 @example
3370 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3371 @end example
3372
3373 Each target configuration file lists the TAPs provided
3374 by a given chip.
3375 Board configuration files combine all the targets on a board,
3376 and so forth.
3377 Note that @emph{the order in which TAPs are declared is very important.}
3378 It must match the order in the JTAG scan chain, both inside
3379 a single chip and between them.
3380 @xref{FAQ TAP Order}.
3381
3382 For example, the ST Microsystems STR912 chip has
3383 three separate TAPs@footnote{See the ST
3384 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3385 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3386 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3387 To configure those taps, @file{target/str912.cfg}
3388 includes commands something like this:
3389
3390 @example
3391 jtag newtap str912 flash ... params ...
3392 jtag newtap str912 cpu ... params ...
3393 jtag newtap str912 bs ... params ...
3394 @end example
3395
3396 Actual config files use a variable instead of literals like
3397 @option{str912}, to support more than one chip of each type.
3398 @xref{Config File Guidelines}.
3399
3400 @deffn Command {jtag names}
3401 Returns the names of all current TAPs in the scan chain.
3402 Use @command{jtag cget} or @command{jtag tapisenabled}
3403 to examine attributes and state of each TAP.
3404 @example
3405 foreach t [jtag names] @{
3406 puts [format "TAP: %s\n" $t]
3407 @}
3408 @end example
3409 @end deffn
3410
3411 @deffn Command {scan_chain}
3412 Displays the TAPs in the scan chain configuration,
3413 and their status.
3414 The set of TAPs listed by this command is fixed by
3415 exiting the OpenOCD configuration stage,
3416 but systems with a JTAG router can
3417 enable or disable TAPs dynamically.
3418 @end deffn
3419
3420 @c FIXME! "jtag cget" should be able to return all TAP
3421 @c attributes, like "$target_name cget" does for targets.
3422
3423 @c Probably want "jtag eventlist", and a "tap-reset" event
3424 @c (on entry to RESET state).
3425
3426 @section TAP Names
3427 @cindex dotted name
3428
3429 When TAP objects are declared with @command{jtag newtap},
3430 a @dfn{dotted.name} is created for the TAP, combining the
3431 name of a module (usually a chip) and a label for the TAP.
3432 For example: @code{xilinx.tap}, @code{str912.flash},
3433 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3434 Many other commands use that dotted.name to manipulate or
3435 refer to the TAP. For example, CPU configuration uses the
3436 name, as does declaration of NAND or NOR flash banks.
3437
3438 The components of a dotted name should follow ``C'' symbol
3439 name rules: start with an alphabetic character, then numbers
3440 and underscores are OK; while others (including dots!) are not.
3441
3442 @quotation Tip
3443 In older code, JTAG TAPs were numbered from 0..N.
3444 This feature is still present.
3445 However its use is highly discouraged, and
3446 should not be relied on; it will be removed by mid-2010.
3447 Update all of your scripts to use TAP names rather than numbers,
3448 by paying attention to the runtime warnings they trigger.
3449 Using TAP numbers in target configuration scripts prevents
3450 reusing those scripts on boards with multiple targets.
3451 @end quotation
3452
3453 @section TAP Declaration Commands
3454
3455 @c shouldn't this be(come) a {Config Command}?
3456 @anchor{jtag newtap}
3457 @deffn Command {jtag newtap} chipname tapname configparams...
3458 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3459 and configured according to the various @var{configparams}.
3460
3461 The @var{chipname} is a symbolic name for the chip.
3462 Conventionally target config files use @code{$_CHIPNAME},
3463 defaulting to the model name given by the chip vendor but
3464 overridable.
3465
3466 @cindex TAP naming convention
3467 The @var{tapname} reflects the role of that TAP,
3468 and should follow this convention:
3469
3470 @itemize @bullet
3471 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3472 @item @code{cpu} -- The main CPU of the chip, alternatively
3473 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3474 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3475 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3476 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3477 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3478 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3479 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3480 with a single TAP;
3481 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3482 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3483 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3484 a JTAG TAP; that TAP should be named @code{sdma}.
3485 @end itemize
3486
3487 Every TAP requires at least the following @var{configparams}:
3488
3489 @itemize @bullet
3490 @item @code{-irlen} @var{NUMBER}
3491 @*The length in bits of the
3492 instruction register, such as 4 or 5 bits.
3493 @end itemize
3494
3495 A TAP may also provide optional @var{configparams}:
3496
3497 @itemize @bullet
3498 @item @code{-disable} (or @code{-enable})
3499 @*Use the @code{-disable} parameter to flag a TAP which is not
3500 linked in to the scan chain after a reset using either TRST
3501 or the JTAG state machine's @sc{reset} state.
3502 You may use @code{-enable} to highlight the default state
3503 (the TAP is linked in).
3504 @xref{Enabling and Disabling TAPs}.
3505 @item @code{-expected-id} @var{number}
3506 @*A non-zero @var{number} represents a 32-bit IDCODE
3507 which you expect to find when the scan chain is examined.
3508 These codes are not required by all JTAG devices.
3509 @emph{Repeat the option} as many times as required if more than one
3510 ID code could appear (for example, multiple versions).
3511 Specify @var{number} as zero to suppress warnings about IDCODE
3512 values that were found but not included in the list.
3513
3514 Provide this value if at all possible, since it lets OpenOCD
3515 tell when the scan chain it sees isn't right. These values
3516 are provided in vendors' chip documentation, usually a technical
3517 reference manual. Sometimes you may need to probe the JTAG
3518 hardware to find these values.
3519 @xref{Autoprobing}.
3520 @item @code{-ignore-version}
3521 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3522 option. When vendors put out multiple versions of a chip, or use the same
3523 JTAG-level ID for several largely-compatible chips, it may be more practical
3524 to ignore the version field than to update config files to handle all of
3525 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3526 @item @code{-ircapture} @var{NUMBER}
3527 @*The bit pattern loaded by the TAP into the JTAG shift register
3528 on entry to the @sc{ircapture} state, such as 0x01.
3529 JTAG requires the two LSBs of this value to be 01.
3530 By default, @code{-ircapture} and @code{-irmask} are set
3531 up to verify that two-bit value. You may provide
3532 additional bits, if you know them, or indicate that
3533 a TAP doesn't conform to the JTAG specification.
3534 @item @code{-irmask} @var{NUMBER}
3535 @*A mask used with @code{-ircapture}
3536 to verify that instruction scans work correctly.
3537 Such scans are not used by OpenOCD except to verify that
3538 there seems to be no problems with JTAG scan chain operations.
3539 @end itemize
3540 @end deffn
3541
3542 @section Other TAP commands
3543
3544 @deffn Command {jtag cget} dotted.name @option{-event} name
3545 @deffnx Command {jtag configure} dotted.name @option{-event} name string
3546 At this writing this TAP attribute
3547 mechanism is used only for event handling.
3548 (It is not a direct analogue of the @code{cget}/@code{configure}
3549 mechanism for debugger targets.)
3550 See the next section for information about the available events.
3551
3552 The @code{configure} subcommand assigns an event handler,
3553 a TCL string which is evaluated when the event is triggered.
3554 The @code{cget} subcommand returns that handler.
3555 @end deffn
3556
3557 @anchor{TAP Events}
3558 @section TAP Events
3559 @cindex events
3560 @cindex TAP events
3561
3562 OpenOCD includes two event mechanisms.
3563 The one presented here applies to all JTAG TAPs.
3564 The other applies to debugger targets,
3565 which are associated with certain TAPs.
3566
3567 The TAP events currently defined are:
3568
3569 @itemize @bullet
3570 @item @b{post-reset}
3571 @* The TAP has just completed a JTAG reset.
3572 The tap may still be in the JTAG @sc{reset} state.
3573 Handlers for these events might perform initialization sequences
3574 such as issuing TCK cycles, TMS sequences to ensure
3575 exit from the ARM SWD mode, and more.
3576
3577 Because the scan chain has not yet been verified, handlers for these events
3578 @emph{should not issue commands which scan the JTAG IR or DR registers}
3579 of any particular target.
3580 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3581 @item @b{setup}
3582 @* The scan chain has been reset and verified.
3583 This handler may enable TAPs as needed.
3584 @item @b{tap-disable}
3585 @* The TAP needs to be disabled. This handler should
3586 implement @command{jtag tapdisable}
3587 by issuing the relevant JTAG commands.
3588 @item @b{tap-enable}
3589 @* The TAP needs to be enabled. This handler should
3590 implement @command{jtag tapenable}
3591 by issuing the relevant JTAG commands.
3592 @end itemize
3593
3594 If you need some action after each JTAG reset, which isn't actually
3595 specific to any TAP (since you can't yet trust the scan chain's
3596 contents to be accurate), you might:
3597
3598 @example
3599 jtag configure CHIP.jrc -event post-reset @{
3600 echo "JTAG Reset done"
3601 ... non-scan jtag operations to be done after reset
3602 @}
3603 @end example
3604
3605
3606 @anchor{Enabling and Disabling TAPs}
3607 @section Enabling and Disabling TAPs
3608 @cindex JTAG Route Controller
3609 @cindex jrc
3610
3611 In some systems, a @dfn{JTAG Route Controller} (JRC)
3612 is used to enable and/or disable specific JTAG TAPs.
3613 Many ARM based chips from Texas Instruments include
3614 an ``ICEpick'' module, which is a JRC.
3615 Such chips include DaVinci and OMAP3 processors.
3616
3617 A given TAP may not be visible until the JRC has been
3618 told to link it into the scan chain; and if the JRC
3619 has been told to unlink that TAP, it will no longer
3620 be visible.
3621 Such routers address problems that JTAG ``bypass mode''
3622 ignores, such as:
3623
3624 @itemize
3625 @item The scan chain can only go as fast as its slowest TAP.
3626 @item Having many TAPs slows instruction scans, since all
3627 TAPs receive new instructions.
3628 @item TAPs in the scan chain must be powered up, which wastes
3629 power and prevents debugging some power management mechanisms.
3630 @end itemize
3631
3632 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3633 as implied by the existence of JTAG routers.
3634 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3635 does include a kind of JTAG router functionality.
3636
3637 @c (a) currently the event handlers don't seem to be able to
3638 @c fail in a way that could lead to no-change-of-state.
3639
3640 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3641 shown below, and is implemented using TAP event handlers.
3642 So for example, when defining a TAP for a CPU connected to
3643 a JTAG router, your @file{target.cfg} file
3644 should define TAP event handlers using
3645 code that looks something like this:
3646
3647 @example
3648 jtag configure CHIP.cpu -event tap-enable @{
3649 ... jtag operations using CHIP.jrc
3650 @}
3651 jtag configure CHIP.cpu -event tap-disable @{
3652 ... jtag operations using CHIP.jrc
3653 @}
3654 @end example
3655
3656 Then you might want that CPU's TAP enabled almost all the time:
3657
3658 @example
3659 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3660 @end example
3661
3662 Note how that particular setup event handler declaration
3663 uses quotes to evaluate @code{$CHIP} when the event is configured.
3664 Using brackets @{ @} would cause it to be evaluated later,
3665 at runtime, when it might have a different value.
3666
3667 @deffn Command {jtag tapdisable} dotted.name
3668 If necessary, disables the tap
3669 by sending it a @option{tap-disable} event.
3670 Returns the string "1" if the tap
3671 specified by @var{dotted.name} is enabled,
3672 and "0" if it is disabled.
3673 @end deffn
3674
3675 @deffn Command {jtag tapenable} dotted.name
3676 If necessary, enables the tap
3677 by sending it a @option{tap-enable} event.
3678 Returns the string "1" if the tap
3679 specified by @var{dotted.name} is enabled,
3680 and "0" if it is disabled.
3681 @end deffn
3682
3683 @deffn Command {jtag tapisenabled} dotted.name
3684 Returns the string "1" if the tap
3685 specified by @var{dotted.name} is enabled,
3686 and "0" if it is disabled.
3687
3688 @quotation Note
3689 Humans will find the @command{scan_chain} command more helpful
3690 for querying the state of the JTAG taps.
3691 @end quotation
3692 @end deffn
3693
3694 @anchor{Autoprobing}
3695 @section Autoprobing
3696 @cindex autoprobe
3697 @cindex JTAG autoprobe
3698
3699 TAP configuration is the first thing that needs to be done
3700 after interface and reset configuration. Sometimes it's
3701 hard finding out what TAPs exist, or how they are identified.
3702 Vendor documentation is not always easy to find and use.
3703
3704 To help you get past such problems, OpenOCD has a limited
3705 @emph{autoprobing} ability to look at the scan chain, doing
3706 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3707 To use this mechanism, start the OpenOCD server with only data
3708 that configures your JTAG interface, and arranges to come up
3709 with a slow clock (many devices don't support fast JTAG clocks
3710 right when they come out of reset).
3711
3712 For example, your @file{openocd.cfg} file might have:
3713
3714 @example
3715 source [find interface/olimex-arm-usb-tiny-h.cfg]
3716 reset_config trst_and_srst
3717 jtag_rclk 8
3718 @end example
3719
3720 When you start the server without any TAPs configured, it will
3721 attempt to autoconfigure the TAPs. There are two parts to this:
3722
3723 @enumerate
3724 @item @emph{TAP discovery} ...
3725 After a JTAG reset (sometimes a system reset may be needed too),
3726 each TAP's data registers will hold the contents of either the
3727 IDCODE or BYPASS register.
3728 If JTAG communication is working, OpenOCD will see each TAP,
3729 and report what @option{-expected-id} to use with it.
3730 @item @emph{IR Length discovery} ...
3731 Unfortunately JTAG does not provide a reliable way to find out
3732 the value of the @option{-irlen} parameter to use with a TAP
3733 that is discovered.
3734 If OpenOCD can discover the length of a TAP's instruction
3735 register, it will report it.
3736 Otherwise you may need to consult vendor documentation, such
3737 as chip data sheets or BSDL files.
3738 @end enumerate
3739
3740 In many cases your board will have a simple scan chain with just
3741 a single device. Here's what OpenOCD reported with one board
3742 that's a bit more complex:
3743
3744 @example
3745 clock speed 8 kHz
3746 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3747 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3748 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3749 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3750 AUTO auto0.tap - use "... -irlen 4"
3751 AUTO auto1.tap - use "... -irlen 4"
3752 AUTO auto2.tap - use "... -irlen 6"
3753 no gdb ports allocated as no target has been specified
3754 @end example
3755
3756 Given that information, you should be able to either find some existing
3757 config files to use, or create your own. If you create your own, you
3758 would configure from the bottom up: first a @file{target.cfg} file
3759 with these TAPs, any targets associated with them, and any on-chip
3760 resources; then a @file{board.cfg} with off-chip resources, clocking,
3761 and so forth.
3762
3763 @node CPU Configuration
3764 @chapter CPU Configuration
3765 @cindex GDB target
3766
3767 This chapter discusses how to set up GDB debug targets for CPUs.
3768 You can also access these targets without GDB
3769 (@pxref{Architecture and Core Commands},
3770 and @ref{Target State handling}) and
3771 through various kinds of NAND and NOR flash commands.
3772 If you have multiple CPUs you can have multiple such targets.
3773
3774 We'll start by looking at how to examine the targets you have,
3775 then look at how to add one more target and how to configure it.
3776
3777 @section Target List
3778 @cindex target, current
3779 @cindex target, list
3780
3781 All targets that have been set up are part of a list,
3782 where each member has a name.
3783 That name should normally be the same as the TAP name.
3784 You can display the list with the @command{targets}
3785 (plural!) command.
3786 This display often has only one CPU; here's what it might
3787 look like with more than one:
3788 @verbatim
3789 TargetName Type Endian TapName State
3790 -- ------------------ ---------- ------ ------------------ ------------
3791 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
3792 1 MyTarget cortex_m3 little mychip.foo tap-disabled
3793 @end verbatim
3794
3795 One member of that list is the @dfn{current target}, which
3796 is implicitly referenced by many commands.
3797 It's the one marked with a @code{*} near the target name.
3798 In particular, memory addresses often refer to the address
3799 space seen by that current target.
3800 Commands like @command{mdw} (memory display words)
3801 and @command{flash erase_address} (erase NOR flash blocks)
3802 are examples; and there are many more.
3803
3804 Several commands let you examine the list of targets:
3805
3806 @deffn Command {target count}
3807 @emph{Note: target numbers are deprecated; don't use them.
3808 They will be removed shortly after August 2010, including this command.
3809 Iterate target using @command{target names}, not by counting.}
3810
3811 Returns the number of targets, @math{N}.
3812 The highest numbered target is @math{N - 1}.
3813 @example
3814 set c [target count]
3815 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
3816 # Assuming you have created this function
3817 print_target_details $x
3818 @}
3819 @end example
3820 @end deffn
3821
3822 @deffn Command {target current}
3823 Returns the name of the current target.
3824 @end deffn
3825
3826 @deffn Command {target names}
3827 Lists the names of all current targets in the list.
3828 @example
3829 foreach t [target names] @{
3830 puts [format "Target: %s\n" $t]
3831 @}
3832 @end example
3833 @end deffn
3834
3835 @deffn Command {target number} number
3836 @emph{Note: target numbers are deprecated; don't use them.
3837 They will be removed shortly after August 2010, including this command.}
3838
3839 The list of targets is numbered starting at zero.
3840 This command returns the name of the target at index @var{number}.
3841 @example
3842 set thename [target number $x]
3843 puts [format "Target %d is: %s\n" $x $thename]
3844 @end example
3845 @end deffn
3846
3847 @c yep, "target list" would have been better.
3848 @c plus maybe "target setdefault".
3849
3850 @deffn Command targets [name]
3851 @emph{Note: the name of this command is plural. Other target
3852 command names are singular.}
3853
3854 With no parameter, this command displays a table of all known
3855 targets in a user friendly form.
3856
3857 With a parameter, this command sets the current target to
3858 the given target with the given @var{name}; this is
3859 only relevant on boards which have more than one target.
3860 @end deffn
3861
3862 @section Target CPU Types and Variants
3863 @cindex target type
3864 @cindex CPU type
3865 @cindex CPU variant
3866
3867 Each target has a @dfn{CPU type}, as shown in the output of
3868 the @command{targets} command. You need to specify that type
3869 when calling @command{target create}.
3870 The CPU type indicates more than just the instruction set.
3871 It also indicates how that instruction set is implemented,
3872 what kind of debug support it integrates,
3873 whether it has an MMU (and if so, what kind),
3874 what core-specific commands may be available
3875 (@pxref{Architecture and Core Commands}),
3876 and more.
3877
3878 For some CPU types, OpenOCD also defines @dfn{variants} which
3879 indicate differences that affect their handling.
3880 For example, a particular implementation bug might need to be
3881 worked around in some chip versions.
3882
3883 It's easy to see what target types are supported,
3884 since there's a command to list them.
3885 However, there is currently no way to list what target variants
3886 are supported (other than by reading the OpenOCD source code).
3887
3888 @anchor{target types}
3889 @deffn Command {target types}
3890 Lists all supported target types.
3891 At this writing, the supported CPU types and variants are:
3892
3893 @itemize @bullet
3894 @item @code{arm11} -- this is a generation of ARMv6 cores
3895 @item @code{arm720t} -- this is an ARMv4 core with an MMU
3896 @item @code{arm7tdmi} -- this is an ARMv4 core
3897 @item @code{arm920t} -- this is an ARMv4 core with an MMU
3898 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
3899 @item @code{arm966e} -- this is an ARMv5 core
3900 @item @code{arm9tdmi} -- this is an ARMv4 core
3901 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
3902 (Support for this is preliminary and incomplete.)
3903 @item @code{cortex_a8} -- this is an ARMv7 core with an MMU
3904 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
3905 compact Thumb2 instruction set.
3906 @item @code{dragonite} -- resembles arm966e
3907 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
3908 (Support for this is still incomplete.)
3909 @item @code{fa526} -- resembles arm920 (w/o Thumb)
3910 @item @code{feroceon} -- resembles arm926
3911 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
3912 @item @code{xscale} -- this is actually an architecture,
3913 not a CPU type. It is based on the ARMv5 architecture.
3914 There are several variants defined:
3915 @itemize @minus
3916 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
3917 @code{pxa27x} ... instruction register length is 7 bits
3918 @item @code{pxa250}, @code{pxa255},
3919 @code{pxa26x} ... instruction register length is 5 bits
3920 @item @code{pxa3xx} ... instruction register length is 11 bits
3921 @end itemize
3922 @end itemize
3923 @end deffn
3924
3925 To avoid being confused by the variety of ARM based cores, remember
3926 this key point: @emph{ARM is a technology licencing company}.
3927 (See: @url{http://www.arm.com}.)
3928 The CPU name used by OpenOCD will reflect the CPU design that was
3929 licenced, not a vendor brand which incorporates that design.
3930 Name prefixes like arm7, arm9, arm11, and cortex
3931 reflect design generations;
3932 while names like ARMv4, ARMv5, ARMv6, and ARMv7
3933 reflect an architecture version implemented by a CPU design.
3934
3935 @anchor{Target Configuration}
3936 @section Target Configuration
3937
3938 Before creating a ``target'', you must have added its TAP to the scan chain.
3939 When you've added that TAP, you will have a @code{dotted.name}
3940 which is used to set up the CPU support.
3941 The chip-specific configuration file will normally configure its CPU(s)
3942 right after it adds all of the chip's TAPs to the scan chain.
3943
3944 Although you can set up a target in one step, it's often clearer if you
3945 use shorter commands and do it in two steps: create it, then configure
3946 optional parts.
3947 All operations on the target after it's created will use a new
3948 command, created as part of target creation.
3949
3950 The two main things to configure after target creation are
3951 a work area, which usually has target-specific defaults even
3952 if the board setup code overrides them later;
3953 and event handlers (@pxref{Target Events}), which tend
3954 to be much more board-specific.
3955 The key steps you use might look something like this
3956
3957 @example
3958 target create MyTarget cortex_m3 -chain-position mychip.cpu
3959 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
3960 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
3961 $MyTarget configure -event reset-init @{ myboard_reinit @}
3962 @end example
3963
3964 You should specify a working area if you can; typically it uses some
3965 on-chip SRAM.
3966 Such a working area can speed up many things, including bulk
3967 writes to target memory;
3968 flash operations like checking to see if memory needs to be erased;
3969 GDB memory checksumming;
3970 and more.
3971
3972 @quotation Warning
3973 On more complex chips, the work area can become
3974 inaccessible when application code
3975 (such as an operating system)
3976 enables or disables the MMU.
3977 For example, the particular MMU context used to acess the virtual
3978 address will probably matter ... and that context might not have
3979 easy access to other addresses needed.
3980 At this writing, OpenOCD doesn't have much MMU intelligence.
3981 @end quotation
3982
3983 It's often very useful to define a @code{reset-init} event handler.
3984 For systems that are normally used with a boot loader,
3985 common tasks include updating clocks and initializing memory
3986 controllers.
3987 That may be needed to let you write the boot loader into flash,
3988 in order to ``de-brick'' your board; or to load programs into
3989 external DDR memory without having run the boot loader.
3990
3991 @deffn Command {target create} target_name type configparams...
3992 This command creates a GDB debug target that refers to a specific JTAG tap.
3993 It enters that target into a list, and creates a new
3994 command (@command{@var{target_name}}) which is used for various
3995 purposes including additional configuration.
3996
3997 @itemize @bullet
3998 @item @var{target_name} ... is the name of the debug target.
3999 By convention this should be the same as the @emph{dotted.name}
4000 of the TAP associated with this target, which must be specified here
4001 using the @code{-chain-position @var{dotted.name}} configparam.
4002
4003 This name is also used to create the target object command,
4004 referred to here as @command{$target_name},
4005 and in other places the target needs to be identified.
4006 @item @var{type} ... specifies the target type. @xref{target types}.
4007 @item @var{configparams} ... all parameters accepted by
4008 @command{$target_name configure} are permitted.
4009 If the target is big-endian, set it here with @code{-endian big}.
4010 If the variant matters, set it here with @code{-variant}.
4011
4012 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
4013 @end itemize
4014 @end deffn
4015
4016 @deffn Command {$target_name configure} configparams...
4017 The options accepted by this command may also be
4018 specified as parameters to @command{target create}.
4019 Their values can later be queried one at a time by
4020 using the @command{$target_name cget} command.
4021
4022 @emph{Warning:} changing some of these after setup is dangerous.
4023 For example, moving a target from one TAP to another;
4024 and changing its endianness or variant.
4025
4026 @itemize @bullet
4027
4028 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4029 used to access this target.
4030
4031 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4032 whether the CPU uses big or little endian conventions
4033
4034 @item @code{-event} @var{event_name} @var{event_body} --
4035 @xref{Target Events}.
4036 Note that this updates a list of named event handlers.
4037 Calling this twice with two different event names assigns
4038 two different handlers, but calling it twice with the
4039 same event name assigns only one handler.
4040
4041 @item @code{-variant} @var{name} -- specifies a variant of the target,
4042 which OpenOCD needs to know about.
4043
4044 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4045 whether the work area gets backed up; by default,
4046 @emph{it is not backed up.}
4047 When possible, use a working_area that doesn't need to be backed up,
4048 since performing a backup slows down operations.
4049 For example, the beginning of an SRAM block is likely to
4050 be used by most build systems, but the end is often unused.
4051
4052 @item @code{-work-area-size} @var{size} -- specify work are size,
4053 in bytes. The same size applies regardless of whether its physical
4054 or virtual address is being used.
4055
4056 @item @code{-work-area-phys} @var{address} -- set the work area
4057 base @var{address} to be used when no MMU is active.
4058
4059 @item @code{-work-area-virt} @var{address} -- set the work area
4060 base @var{address} to be used when an MMU is active.
4061 @emph{Do not specify a value for this except on targets with an MMU.}
4062 The value should normally correspond to a static mapping for the
4063 @code{-work-area-phys} address, set up by the current operating system.
4064
4065 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4066 @var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}|
4067 @option{FreeRTOS}|@option{linux}.
4068
4069 @end itemize
4070 @end deffn
4071
4072 @section Other $target_name Commands
4073 @cindex object command
4074
4075 The Tcl/Tk language has the concept of object commands,
4076 and OpenOCD adopts that same model for targets.
4077
4078 A good Tk example is a on screen button.
4079 Once a button is created a button
4080 has a name (a path in Tk terms) and that name is useable as a first
4081 class command. For example in Tk, one can create a button and later
4082 configure it like this:
4083
4084 @example
4085 # Create
4086 button .foobar -background red -command @{ foo @}
4087 # Modify
4088 .foobar configure -foreground blue
4089 # Query
4090 set x [.foobar cget -background]
4091 # Report
4092 puts [format "The button is %s" $x]
4093 @end example
4094
4095 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4096 button, and its object commands are invoked the same way.
4097
4098 @example
4099 str912.cpu mww 0x1234 0x42
4100 omap3530.cpu mww 0x5555 123
4101 @end example
4102
4103 The commands supported by OpenOCD target objects are:
4104
4105 @deffn Command {$target_name arp_examine}
4106 @deffnx Command {$target_name arp_halt}
4107 @deffnx Command {$target_name arp_poll}
4108 @deffnx Command {$target_name arp_reset}
4109 @deffnx Command {$target_name arp_waitstate}
4110 Internal OpenOCD scripts (most notably @file{startup.tcl})
4111 use these to deal with specific reset cases.
4112 They are not otherwise documented here.
4113 @end deffn
4114
4115 @deffn Command {$target_name array2mem} arrayname width address count
4116 @deffnx Command {$target_name mem2array} arrayname width address count
4117 These provide an efficient script-oriented interface to memory.
4118 The @code{array2mem} primitive writes bytes, halfwords, or words;
4119 while @code{mem2array} reads them.
4120 In both cases, the TCL side uses an array, and
4121 the target side uses raw memory.
4122
4123 The efficiency comes from enabling the use of
4124 bulk JTAG data transfer operations.
4125 The script orientation comes from working with data
4126 values that are packaged for use by TCL scripts;
4127 @command{mdw} type primitives only print data they retrieve,
4128 and neither store nor return those values.
4129
4130 @itemize
4131 @item @var{arrayname} ... is the name of an array variable
4132 @item @var{width} ... is 8/16/32 - indicating the memory access size
4133 @item @var{address} ... is the target memory address
4134 @item @var{count} ... is the number of elements to process
4135 @end itemize
4136 @end deffn
4137
4138 @deffn Command {$target_name cget} queryparm
4139 Each configuration parameter accepted by
4140 @command{$target_name configure}
4141 can be individually queried, to return its current value.
4142 The @var{queryparm} is a parameter name
4143 accepted by that command, such as @code{-work-area-phys}.
4144 There are a few special cases:
4145
4146 @itemize @bullet
4147 @item @code{-event} @var{event_name} -- returns the handler for the
4148 event named @var{event_name}.
4149 This is a special case because setting a handler requires
4150 two parameters.
4151 @item @code{-type} -- returns the target type.
4152 This is a special case because this is set using
4153 @command{target create} and can't be changed
4154 using @command{$target_name configure}.
4155 @end itemize
4156
4157 For example, if you wanted to summarize information about
4158 all the targets you might use something like this:
4159
4160 @example
4161 foreach name [target names] @{
4162 set y [$name cget -endian]
4163 set z [$name cget -type]
4164 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4165 $x $name $y $z]
4166 @}
4167 @end example
4168 @end deffn
4169
4170 @anchor{target curstate}
4171 @deffn Command {$target_name curstate}
4172 Displays the current target state:
4173 @code{debug-running},
4174 @code{halted},
4175 @code{reset},
4176 @code{running}, or @code{unknown}.
4177 (Also, @pxref{Event Polling}.)
4178 @end deffn
4179
4180 @deffn Command {$target_name eventlist}
4181 Displays a table listing all event handlers
4182 currently associated with this target.
4183 @xref{Target Events}.
4184 @end deffn
4185
4186 @deffn Command {$target_name invoke-event} event_name
4187 Invokes the handler for the event named @var{event_name}.
4188 (This is primarily intended for use by OpenOCD framework
4189 code, for example by the reset code in @file{startup.tcl}.)
4190 @end deffn
4191
4192 @deffn Command {$target_name mdw} addr [count]
4193 @deffnx Command {$target_name mdh} addr [count]
4194 @deffnx Command {$target_name mdb} addr [count]
4195 Display contents of address @var{addr}, as
4196 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4197 or 8-bit bytes (@command{mdb}).
4198 If @var{count} is specified, displays that many units.
4199 (If you want to manipulate the data instead of displaying it,
4200 see the @code{mem2array} primitives.)
4201 @end deffn
4202
4203 @deffn Command {$target_name mww} addr word
4204 @deffnx Command {$target_name mwh} addr halfword
4205 @deffnx Command {$target_name mwb} addr byte
4206 Writes the specified @var{word} (32 bits),
4207 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4208 at the specified address @var{addr}.
4209 @end deffn
4210
4211 @anchor{Target Events}
4212 @section Target Events
4213 @cindex target events
4214 @cindex events
4215 At various times, certain things can happen, or you want them to happen.
4216 For example:
4217 @itemize @bullet
4218 @item What should happen when GDB connects? Should your target reset?
4219 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4220 @item Is using SRST appropriate (and possible) on your system?
4221 Or instead of that, do you need to issue JTAG commands to trigger reset?
4222 SRST usually resets everything on the scan chain, which can be inappropriate.
4223 @item During reset, do you need to write to certain memory locations
4224 to set up system clocks or
4225 to reconfigure the SDRAM?
4226 How about configuring the watchdog timer, or other peripherals,
4227 to stop running while you hold the core stopped for debugging?
4228 @end itemize
4229
4230 All of the above items can be addressed by target event handlers.
4231 These are set up by @command{$target_name configure -event} or
4232 @command{target create ... -event}.
4233
4234 The programmer's model matches the @code{-command} option used in Tcl/Tk
4235 buttons and events. The two examples below act the same, but one creates
4236 and invokes a small procedure while the other inlines it.
4237
4238 @example
4239 proc my_attach_proc @{ @} @{
4240 echo "Reset..."
4241 reset halt
4242 @}
4243 mychip.cpu configure -event gdb-attach my_attach_proc
4244 mychip.cpu configure -event gdb-attach @{
4245 echo "Reset..."
4246 # To make flash probe and gdb load to flash work we need a reset init.
4247 reset init
4248 @}
4249 @end example
4250
4251 The following target events are defined:
4252
4253 @itemize @bullet
4254 @item @b{debug-halted}
4255 @* The target has halted for debug reasons (i.e.: breakpoint)
4256 @item @b{debug-resumed}
4257 @* The target has resumed (i.e.: gdb said run)
4258 @item @b{early-halted}
4259 @* Occurs early in the halt process
4260 @item @b{examine-start}
4261 @* Before target examine is called.
4262 @item @b{examine-end}
4263 @* After target examine is called with no errors.
4264 @item @b{gdb-attach}
4265 @* When GDB connects. This is before any communication with the target, so this
4266 can be used to set up the target so it is possible to probe flash. Probing flash
4267 is necessary during gdb connect if gdb load is to write the image to flash. Another
4268 use of the flash memory map is for GDB to automatically hardware/software breakpoints
4269 depending on whether the breakpoint is in RAM or read only memory.
4270 @item @b{gdb-detach}
4271 @* When GDB disconnects
4272 @item @b{gdb-end}
4273 @* When the target has halted and GDB is not doing anything (see early halt)
4274 @item @b{gdb-flash-erase-start}
4275 @* Before the GDB flash process tries to erase the flash
4276 @item @b{gdb-flash-erase-end}
4277 @* After the GDB flash process has finished erasing the flash
4278 @item @b{gdb-flash-write-start}
4279 @* Before GDB writes to the flash
4280 @item @b{gdb-flash-write-end}
4281 @* After GDB writes to the flash
4282 @item @b{gdb-start}
4283 @* Before the target steps, gdb is trying to start/resume the target
4284 @item @b{halted}
4285 @* The target has halted
4286 @item @b{reset-assert-pre}
4287 @* Issued as part of @command{reset} processing
4288 after @command{reset_init} was triggered
4289 but before either SRST alone is re-asserted on the scan chain,
4290 or @code{reset-assert} is triggered.
4291 @item @b{reset-assert}
4292 @* Issued as part of @command{reset} processing
4293 after @command{reset-assert-pre} was triggered.
4294 When such a handler is present, cores which support this event will use
4295 it instead of asserting SRST.
4296 This support is essential for debugging with JTAG interfaces which
4297 don't include an SRST line (JTAG doesn't require SRST), and for
4298 selective reset on scan chains that have multiple targets.
4299 @item @b{reset-assert-post}
4300 @* Issued as part of @command{reset} processing
4301 after @code{reset-assert} has been triggered.
4302 or the target asserted SRST on the entire scan chain.
4303 @item @b{reset-deassert-pre}
4304 @* Issued as part of @command{reset} processing
4305 after @code{reset-assert-post} has been triggered.
4306 @item @b{reset-deassert-post}
4307 @* Issued as part of @command{reset} processing
4308 after @code{reset-deassert-pre} has been triggered
4309 and (if the target is using it) after SRST has been
4310 released on the scan chain.
4311 @item @b{reset-end}
4312 @* Issued as the final step in @command{reset} processing.
4313 @ignore
4314 @item @b{reset-halt-post}
4315 @* Currently not used
4316 @item @b{reset-halt-pre}
4317 @* Currently not used
4318 @end ignore
4319 @item @b{reset-init}
4320 @* Used by @b{reset init} command for board-specific initialization.
4321 This event fires after @emph{reset-deassert-post}.
4322
4323 This is where you would configure PLLs and clocking, set up DRAM so
4324 you can download programs that don't fit in on-chip SRAM, set up pin
4325 multiplexing, and so on.
4326 (You may be able to switch to a fast JTAG clock rate here, after
4327 the target clocks are fully set up.)
4328 @item @b{reset-start}
4329 @* Issued as part of @command{reset} processing
4330 before @command{reset_init} is called.
4331
4332 This is the most robust place to use @command{jtag_rclk}
4333 or @command{adapter_khz} to switch to a low JTAG clock rate,
4334 when reset disables PLLs needed to use a fast clock.
4335 @ignore
4336 @item @b{reset-wait-pos}
4337 @* Currently not used
4338 @item @b{reset-wait-pre}
4339 @* Currently not used
4340 @end ignore
4341 @item @b{resume-start}
4342 @* Before any target is resumed
4343 @item @b{resume-end}
4344 @* After all targets have resumed
4345 @item @b{resumed}
4346 @* Target has resumed
4347 @end itemize
4348
4349 @node Flash Commands
4350 @chapter Flash Commands
4351
4352 OpenOCD has different commands for NOR and NAND flash;
4353 the ``flash'' command works with NOR flash, while
4354 the ``nand'' command works with NAND flash.
4355 This partially reflects different hardware technologies:
4356 NOR flash usually supports direct CPU instruction and data bus access,
4357 while data from a NAND flash must be copied to memory before it can be
4358 used. (SPI flash must also be copied to memory before use.)
4359 However, the documentation also uses ``flash'' as a generic term;
4360 for example, ``Put flash configuration in board-specific files''.
4361
4362 Flash Steps:
4363 @enumerate
4364 @item Configure via the command @command{flash bank}
4365 @* Do this in a board-specific configuration file,
4366 passing parameters as needed by the driver.
4367 @item Operate on the flash via @command{flash subcommand}
4368 @* Often commands to manipulate the flash are typed by a human, or run
4369 via a script in some automated way. Common tasks include writing a
4370 boot loader, operating system, or other data.
4371 @item GDB Flashing
4372 @* Flashing via GDB requires the flash be configured via ``flash
4373 bank'', and the GDB flash features be enabled.
4374 @xref{GDB Configuration}.
4375 @end enumerate
4376
4377 Many CPUs have the ablity to ``boot'' from the first flash bank.
4378 This means that misprogramming that bank can ``brick'' a system,
4379 so that it can't boot.
4380 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4381 board by (re)installing working boot firmware.
4382
4383 @anchor{NOR Configuration}
4384 @section Flash Configuration Commands
4385 @cindex flash configuration
4386
4387 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4388 Configures a flash bank which provides persistent storage
4389 for addresses from @math{base} to @math{base + size - 1}.
4390 These banks will often be visible to GDB through the target's memory map.
4391 In some cases, configuring a flash bank will activate extra commands;
4392 see the driver-specific documentation.
4393
4394 @itemize @bullet
4395 @item @var{name} ... may be used to reference the flash bank
4396 in other flash commands. A number is also available.
4397 @item @var{driver} ... identifies the controller driver
4398 associated with the flash bank being declared.
4399 This is usually @code{cfi} for external flash, or else
4400 the name of a microcontroller with embedded flash memory.
4401 @xref{Flash Driver List}.
4402 @item @var{base} ... Base address of the flash chip.
4403 @item @var{size} ... Size of the chip, in bytes.
4404 For some drivers, this value is detected from the hardware.
4405 @item @var{chip_width} ... Width of the flash chip, in bytes;
4406 ignored for most microcontroller drivers.
4407 @item @var{bus_width} ... Width of the data bus used to access the
4408 chip, in bytes; ignored for most microcontroller drivers.
4409 @item @var{target} ... Names the target used to issue
4410 commands to the flash controller.
4411 @comment Actually, it's currently a controller-specific parameter...
4412 @item @var{driver_options} ... drivers may support, or require,
4413 additional parameters. See the driver-specific documentation
4414 for more information.
4415 @end itemize
4416 @quotation Note
4417 This command is not available after OpenOCD initialization has completed.
4418 Use it in board specific configuration files, not interactively.
4419 @end quotation
4420 @end deffn
4421
4422 @comment the REAL name for this command is "ocd_flash_banks"
4423 @comment less confusing would be: "flash list" (like "nand list")
4424 @deffn Command {flash banks}
4425 Prints a one-line summary of each device that was
4426 declared using @command{flash bank}, numbered from zero.
4427 Note that this is the @emph{plural} form;
4428 the @emph{singular} form is a very different command.
4429 @end deffn
4430
4431 @deffn Command {flash list}
4432 Retrieves a list of associative arrays for each device that was
4433 declared using @command{flash bank}, numbered from zero.
4434 This returned list can be manipulated easily from within scripts.
4435 @end deffn
4436
4437 @deffn Command {flash probe} num
4438 Identify the flash, or validate the parameters of the configured flash. Operation
4439 depends on the flash type.
4440 The @var{num} parameter is a value shown by @command{flash banks}.
4441 Most flash commands will implicitly @emph{autoprobe} the bank;
4442 flash drivers can distinguish between probing and autoprobing,
4443 but most don't bother.
4444 @end deffn
4445
4446 @section Erasing, Reading, Writing to Flash
4447 @cindex flash erasing
4448 @cindex flash reading
4449 @cindex flash writing
4450 @cindex flash programming
4451
4452 One feature distinguishing NOR flash from NAND or serial flash technologies
4453 is that for read access, it acts exactly like any other addressible memory.
4454 This means you can use normal memory read commands like @command{mdw} or
4455 @command{dump_image} with it, with no special @command{flash} subcommands.
4456 @xref{Memory access}, and @ref{Image access}.
4457
4458 Write access works differently. Flash memory normally needs to be erased
4459 before it's written. Erasing a sector turns all of its bits to ones, and
4460 writing can turn ones into zeroes. This is why there are special commands
4461 for interactive erasing and writing, and why GDB needs to know which parts
4462 of the address space hold NOR flash memory.
4463
4464 @quotation Note
4465 Most of these erase and write commands leverage the fact that NOR flash
4466 chips consume target address space. They implicitly refer to the current
4467 JTAG target, and map from an address in that target's address space
4468 back to a flash bank.
4469 @comment In May 2009, those mappings may fail if any bank associated
4470 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
4471 A few commands use abstract addressing based on bank and sector numbers,
4472 and don't depend on searching the current target and its address space.
4473 Avoid confusing the two command models.
4474 @end quotation
4475
4476 Some flash chips implement software protection against accidental writes,
4477 since such buggy writes could in some cases ``brick'' a system.
4478 For such systems, erasing and writing may require sector protection to be
4479 disabled first.
4480 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4481 and AT91SAM7 on-chip flash.
4482 @xref{flash protect}.
4483
4484 @anchor{flash erase_sector}
4485 @deffn Command {flash erase_sector} num first last
4486 Erase sectors in bank @var{num}, starting at sector @var{first}
4487 up to and including @var{last}.
4488 Sector numbering starts at 0.
4489 Providing a @var{last} sector of @option{last}
4490 specifies "to the end of the flash bank".
4491 The @var{num} parameter is a value shown by @command{flash banks}.
4492 @end deffn
4493
4494 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4495 Erase sectors starting at @var{address} for @var{length} bytes.
4496 Unless @option{pad} is specified, @math{address} must begin a
4497 flash sector, and @math{address + length - 1} must end a sector.
4498 Specifying @option{pad} erases extra data at the beginning and/or
4499 end of the specified region, as needed to erase only full sectors.
4500 The flash bank to use is inferred from the @var{address}, and
4501 the specified length must stay within that bank.
4502 As a special case, when @var{length} is zero and @var{address} is
4503 the start of the bank, the whole flash is erased.
4504 If @option{unlock} is specified, then the flash is unprotected
4505 before erase starts.
4506 @end deffn
4507
4508 @deffn Command {flash fillw} address word length
4509 @deffnx Command {flash fillh} address halfword length
4510 @deffnx Command {flash fillb} address byte length
4511 Fills flash memory with the specified @var{word} (32 bits),
4512 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4513 starting at @var{address} and continuing
4514 for @var{length} units (word/halfword/byte).
4515 No erasure is done before writing; when needed, that must be done
4516 before issuing this command.
4517 Writes are done in blocks of up to 1024 bytes, and each write is
4518 verified by reading back the data and comparing it to what was written.
4519 The flash bank to use is inferred from the @var{address} of
4520 each block, and the specified length must stay within that bank.
4521 @end deffn
4522 @comment no current checks for errors if fill blocks touch multiple banks!
4523
4524 @anchor{flash write_bank}
4525 @deffn Command {flash write_bank} num filename offset
4526 Write the binary @file{filename} to flash bank @var{num},
4527 starting at @var{offset} bytes from the beginning of the bank.
4528 The @var{num} parameter is a value shown by @command{flash banks}.
4529 @end deffn
4530
4531 @anchor{flash write_image}
4532 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4533 Write the image @file{filename} to the current target's flash bank(s).
4534 A relocation @var{offset} may be specified, in which case it is added
4535 to the base address for each section in the image.
4536 The file [@var{type}] can be specified
4537 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4538 @option{elf} (ELF file), @option{s19} (Motorola s19).
4539 @option{mem}, or @option{builder}.
4540 The relevant flash sectors will be erased prior to programming
4541 if the @option{erase} parameter is given. If @option{unlock} is
4542 provided, then the flash banks are unlocked before erase and
4543 program. The flash bank to use is inferred from the address of
4544 each image section.
4545
4546 @quotation Warning
4547 Be careful using the @option{erase} flag when the flash is holding
4548 data you want to preserve.
4549 Portions of the flash outside those described in the image's
4550 sections might be erased with no notice.
4551 @itemize
4552 @item
4553 When a section of the image being written does not fill out all the
4554 sectors it uses, the unwritten parts of those sectors are necessarily
4555 also erased, because sectors can't be partially erased.
4556 @item
4557 Data stored in sector "holes" between image sections are also affected.
4558 For example, "@command{flash write_image erase ...}" of an image with
4559 one byte at the beginning of a flash bank and one byte at the end
4560 erases the entire bank -- not just the two sectors being written.
4561 @end itemize
4562 Also, when flash protection is important, you must re-apply it after
4563 it has been removed by the @option{unlock} flag.
4564 @end quotation
4565
4566 @end deffn
4567
4568 @section Other Flash commands
4569 @cindex flash protection
4570
4571 @deffn Command {flash erase_check} num
4572 Check erase state of sectors in flash bank @var{num},
4573 and display that status.
4574 The @var{num} parameter is a value shown by @command{flash banks}.
4575 @end deffn
4576
4577 @deffn Command {flash info} num
4578 Print info about flash bank @var{num}
4579 The @var{num} parameter is a value shown by @command{flash banks}.
4580 This command will first query the hardware, it does not print cached
4581 and possibly stale information.
4582 @end deffn
4583
4584 @anchor{flash protect}
4585 @deffn Command {flash protect} num first last (@option{on}|@option{off})
4586 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
4587 in flash bank @var{num}, starting at sector @var{first}
4588 and continuing up to and including @var{last}.
4589 Providing a @var{last} sector of @option{last}
4590 specifies "to the end of the flash bank".
4591 The @var{num} parameter is a value shown by @command{flash banks}.
4592 @end deffn
4593
4594 @anchor{Flash Driver List}
4595 @section Flash Driver List
4596 As noted above, the @command{flash bank} command requires a driver name,
4597 and allows driver-specific options and behaviors.
4598 Some drivers also activate driver-specific commands.
4599
4600 @subsection External Flash
4601
4602 @deffn {Flash Driver} cfi
4603 @cindex Common Flash Interface
4604 @cindex CFI
4605 The ``Common Flash Interface'' (CFI) is the main standard for
4606 external NOR flash chips, each of which connects to a
4607 specific external chip select on the CPU.
4608 Frequently the first such chip is used to boot the system.
4609 Your board's @code{reset-init} handler might need to
4610 configure additional chip selects using other commands (like: @command{mww} to
4611 configure a bus and its timings), or
4612 perhaps configure a GPIO pin that controls the ``write protect'' pin
4613 on the flash chip.
4614 The CFI driver can use a target-specific working area to significantly
4615 speed up operation.
4616
4617 The CFI driver can accept the following optional parameters, in any order:
4618
4619 @itemize
4620 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
4621 like AM29LV010 and similar types.
4622 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
4623 @end itemize
4624
4625 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
4626 wide on a sixteen bit bus:
4627
4628 @example
4629 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
4630 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
4631 @end example
4632
4633 To configure one bank of 32 MBytes
4634 built from two sixteen bit (two byte) wide parts wired in parallel
4635 to create a thirty-two bit (four byte) bus with doubled throughput:
4636
4637 @example
4638 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
4639 @end example
4640
4641 @c "cfi part_id" disabled
4642 @end deffn
4643
4644 @deffn {Flash Driver} stmsmi
4645 @cindex STMicroelectronics Serial Memory Interface
4646 @cindex SMI
4647 @cindex stmsmi
4648 Some devices form STMicroelectronics (e.g. STR75x MCU family,
4649 SPEAr MPU family) include a proprietary
4650 ``Serial Memory Interface'' (SMI) controller able to drive external
4651 SPI flash devices.
4652 Depending on specific device and board configuration, up to 4 external
4653 flash devices can be connected.
4654
4655 SMI makes the flash content directly accessible in the CPU address
4656 space; each external device is mapped in a memory bank.
4657 CPU can directly read data, execute code and boot from SMI banks.
4658 Normal OpenOCD commands like @command{mdw} can be used to display
4659 the flash content.
4660
4661 The setup command only requires the @var{base} parameter in order
4662 to identify the memory bank.
4663 All other parameters are ignored. Additional information, like
4664 flash size, are detected automatically.
4665
4666 @example
4667 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
4668 @end example
4669
4670 @end deffn
4671
4672 @subsection Internal Flash (Microcontrollers)
4673
4674 @deffn {Flash Driver} aduc702x
4675 The ADUC702x analog microcontrollers from Analog Devices
4676 include internal flash and use ARM7TDMI cores.
4677 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
4678 The setup command only requires the @var{target} argument
4679 since all devices in this family have the same memory layout.
4680
4681 @example
4682 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
4683 @end example
4684 @end deffn
4685
4686 @anchor{at91sam3}
4687 @deffn {Flash Driver} at91sam3
4688 @cindex at91sam3
4689 All members of the AT91SAM3 microcontroller family from
4690 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
4691 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
4692 that the driver was orginaly developed and tested using the
4693 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
4694 the family was cribbed from the data sheet. @emph{Note to future
4695 readers/updaters: Please remove this worrysome comment after other
4696 chips are confirmed.}
4697
4698 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
4699 have one flash bank. In all cases the flash banks are at
4700 the following fixed locations:
4701
4702 @example
4703 # Flash bank 0 - all chips
4704 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
4705 # Flash bank 1 - only 256K chips
4706 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
4707 @end example
4708
4709 Internally, the AT91SAM3 flash memory is organized as follows.
4710 Unlike the AT91SAM7 chips, these are not used as parameters
4711 to the @command{flash bank} command:
4712
4713 @itemize
4714 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
4715 @item @emph{Bank Size:} 128K/64K Per flash bank
4716 @item @emph{Sectors:} 16 or 8 per bank
4717 @item @emph{SectorSize:} 8K Per Sector
4718 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
4719 @end itemize
4720
4721 The AT91SAM3 driver adds some additional commands:
4722
4723 @deffn Command {at91sam3 gpnvm}
4724 @deffnx Command {at91sam3 gpnvm clear} number
4725 @deffnx Command {at91sam3 gpnvm set} number
4726 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
4727 With no parameters, @command{show} or @command{show all},
4728 shows the status of all GPNVM bits.
4729 With @command{show} @var{number}, displays that bit.
4730
4731 With @command{set} @var{number} or @command{clear} @var{number},
4732 modifies that GPNVM bit.
4733 @end deffn
4734
4735 @deffn Command {at91sam3 info}
4736 This command attempts to display information about the AT91SAM3
4737 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
4738 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
4739 document id: doc6430A] and decodes the values. @emph{Second} it reads the
4740 various clock configuration registers and attempts to display how it
4741 believes the chip is configured. By default, the SLOWCLK is assumed to
4742 be 32768 Hz, see the command @command{at91sam3 slowclk}.
4743 @end deffn
4744
4745 @deffn Command {at91sam3 slowclk} [value]
4746 This command shows/sets the slow clock frequency used in the
4747 @command{at91sam3 info} command calculations above.
4748 @end deffn
4749 @end deffn
4750
4751 @deffn {Flash Driver} at91sam4
4752 @cindex at91sam4
4753 All members of the AT91SAM4 microcontroller family from
4754 Atmel include internal flash and use ARM's Cortex-M4 core.
4755 This driver uses the same cmd names/syntax as @xref{at91sam3}.
4756 @end deffn
4757
4758 @deffn {Flash Driver} at91sam7
4759 All members of the AT91SAM7 microcontroller family from Atmel include
4760 internal flash and use ARM7TDMI cores. The driver automatically
4761 recognizes a number of these chips using the chip identification
4762 register, and autoconfigures itself.
4763
4764 @example
4765 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
4766 @end example
4767
4768 For chips which are not recognized by the controller driver, you must
4769 provide additional parameters in the following order:
4770
4771 @itemize
4772 @item @var{chip_model} ... label used with @command{flash info}
4773 @item @var{banks}
4774 @item @var{sectors_per_bank}
4775 @item @var{pages_per_sector}
4776 @item @var{pages_size}
4777 @item @var{num_nvm_bits}
4778 @item @var{freq_khz} ... required if an external clock is provided,
4779 optional (but recommended) when the oscillator frequency is known
4780 @end itemize
4781
4782 It is recommended that you provide zeroes for all of those values
4783 except the clock frequency, so that everything except that frequency
4784 will be autoconfigured.
4785 Knowing the frequency helps ensure correct timings for flash access.
4786
4787 The flash controller handles erases automatically on a page (128/256 byte)
4788 basis, so explicit erase commands are not necessary for flash programming.
4789 However, there is an ``EraseAll`` command that can erase an entire flash
4790 plane (of up to 256KB), and it will be used automatically when you issue
4791 @command{flash erase_sector} or @command{flash erase_address} commands.
4792
4793 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
4794 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
4795 bit for the processor. Each processor has a number of such bits,
4796 used for controlling features such as brownout detection (so they
4797 are not truly general purpose).
4798 @quotation Note
4799 This assumes that the first flash bank (number 0) is associated with
4800 the appropriate at91sam7 target.
4801 @end quotation
4802 @end deffn
4803 @end deffn
4804
4805 @deffn {Flash Driver} avr
4806 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
4807 @emph{The current implementation is incomplete.}
4808 @comment - defines mass_erase ... pointless given flash_erase_address
4809 @end deffn
4810
4811 @deffn {Flash Driver} lpc2000
4812 Most members of the LPC1700 and LPC2000 microcontroller families from NXP
4813 include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
4814
4815 @quotation Note
4816 There are LPC2000 devices which are not supported by the @var{lpc2000}
4817 driver:
4818 The LPC2888 is supported by the @var{lpc288x} driver.
4819 The LPC29xx family is supported by the @var{lpc2900} driver.
4820 @end quotation
4821
4822 The @var{lpc2000} driver defines two mandatory and one optional parameters,
4823 which must appear in the following order:
4824
4825 @itemize
4826 @item @var{variant} ... required, may be
4827 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
4828 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
4829 or @option{lpc1700} (LPC175x and LPC176x)
4830 @item @var{clock_kHz} ... the frequency, in kiloHertz,
4831 at which the core is running
4832 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
4833 telling the driver to calculate a valid checksum for the exception vector table.
4834 @quotation Note
4835 If you don't provide @option{calc_checksum} when you're writing the vector
4836 table, the boot ROM will almost certainly ignore your flash image.
4837 However, if you do provide it,
4838 with most tool chains @command{verify_image} will fail.
4839 @end quotation
4840 @end itemize
4841
4842 LPC flashes don't require the chip and bus width to be specified.
4843
4844 @example
4845 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
4846 lpc2000_v2 14765 calc_checksum
4847 @end example
4848
4849 @deffn {Command} {lpc2000 part_id} bank
4850 Displays the four byte part identifier associated with
4851 the specified flash @var{bank}.
4852 @end deffn
4853 @end deffn
4854
4855 @deffn {Flash Driver} lpc288x
4856 The LPC2888 microcontroller from NXP needs slightly different flash
4857 support from its lpc2000 siblings.
4858 The @var{lpc288x} driver defines one mandatory parameter,
4859 the programming clock rate in Hz.
4860 LPC flashes don't require the chip and bus width to be specified.
4861
4862 @example
4863 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
4864 @end example
4865 @end deffn
4866
4867 @deffn {Flash Driver} lpc2900
4868 This driver supports the LPC29xx ARM968E based microcontroller family
4869 from NXP.
4870
4871 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
4872 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
4873 sector layout are auto-configured by the driver.
4874 The driver has one additional mandatory parameter: The CPU clock rate
4875 (in kHz) at the time the flash operations will take place. Most of the time this
4876 will not be the crystal frequency, but a higher PLL frequency. The
4877 @code{reset-init} event handler in the board script is usually the place where
4878 you start the PLL.
4879
4880 The driver rejects flashless devices (currently the LPC2930).
4881
4882 The EEPROM in LPC2900 devices is not mapped directly into the address space.
4883 It must be handled much more like NAND flash memory, and will therefore be
4884 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
4885
4886 Sector protection in terms of the LPC2900 is handled transparently. Every time a
4887 sector needs to be erased or programmed, it is automatically unprotected.
4888 What is shown as protection status in the @code{flash info} command, is
4889 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
4890 sector from ever being erased or programmed again. As this is an irreversible
4891 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
4892 and not by the standard @code{flash protect} command.
4893
4894 Example for a 125 MHz clock frequency:
4895 @example
4896 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
4897 @end example
4898
4899 Some @code{lpc2900}-specific commands are defined. In the following command list,
4900 the @var{bank} parameter is the bank number as obtained by the
4901 @code{flash banks} command.
4902
4903 @deffn Command {lpc2900 signature} bank
4904 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
4905 content. This is a hardware feature of the flash block, hence the calculation is
4906 very fast. You may use this to verify the content of a programmed device against
4907 a known signature.
4908 Example:
4909 @example
4910 lpc2900 signature 0
4911 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
4912 @end example
4913 @end deffn
4914
4915 @deffn Command {lpc2900 read_custom} bank filename
4916 Reads the 912 bytes of customer information from the flash index sector, and
4917 saves it to a file in binary format.
4918 Example:
4919 @example
4920 lpc2900 read_custom 0 /path_to/customer_info.bin
4921 @end example
4922 @end deffn
4923
4924 The index sector of the flash is a @emph{write-only} sector. It cannot be
4925 erased! In order to guard against unintentional write access, all following
4926 commands need to be preceeded by a successful call to the @code{password}
4927 command:
4928
4929 @deffn Command {lpc2900 password} bank password
4930 You need to use this command right before each of the following commands:
4931 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
4932 @code{lpc2900 secure_jtag}.
4933
4934 The password string is fixed to "I_know_what_I_am_doing".
4935 Example:
4936 @example
4937 lpc2900 password 0 I_know_what_I_am_doing
4938 Potentially dangerous operation allowed in next command!
4939 @end example
4940 @end deffn
4941
4942 @deffn Command {lpc2900 write_custom} bank filename type
4943 Writes the content of the file into the customer info space of the flash index
4944 sector. The filetype can be specified with the @var{type} field. Possible values
4945 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
4946 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
4947 contain a single section, and the contained data length must be exactly
4948 912 bytes.
4949 @quotation Attention
4950 This cannot be reverted! Be careful!
4951 @end quotation
4952 Example:
4953 @example
4954 lpc2900 write_custom 0 /path_to/customer_info.bin bin
4955 @end example
4956 @end deffn
4957
4958 @deffn Command {lpc2900 secure_sector} bank first last
4959 Secures the sector range from @var{first} to @var{last} (including) against
4960 further program and erase operations. The sector security will be effective
4961 after the next power cycle.
4962 @quotation Attention
4963 This cannot be reverted! Be careful!
4964 @end quotation
4965 Secured sectors appear as @emph{protected} in the @code{flash info} command.
4966 Example:
4967 @example
4968 lpc2900 secure_sector 0 1 1
4969 flash info 0
4970 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
4971 # 0: 0x00000000 (0x2000 8kB) not protected
4972 # 1: 0x00002000 (0x2000 8kB) protected
4973 # 2: 0x00004000 (0x2000 8kB) not protected
4974 @end example
4975 @end deffn
4976
4977 @deffn Command {lpc2900 secure_jtag} bank
4978 Irreversibly disable the JTAG port. The new JTAG security setting will be
4979 effective after the next power cycle.
4980 @quotation Attention
4981 This cannot be reverted! Be careful!
4982 @end quotation
4983 Examples:
4984 @example
4985 lpc2900 secure_jtag 0
4986 @end example
4987 @end deffn
4988 @end deffn
4989
4990 @deffn {Flash Driver} ocl
4991 @emph{No idea what this is, other than using some arm7/arm9 core.}
4992
4993 @example
4994 flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
4995 @end example
4996 @end deffn
4997
4998 @deffn {Flash Driver} pic32mx
4999 The PIC32MX microcontrollers are based on the MIPS 4K cores,
5000 and integrate flash memory.
5001
5002 @example
5003 flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
5004 flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
5005 @end example
5006
5007 @comment numerous *disabled* commands are defined:
5008 @comment - chip_erase ... pointless given flash_erase_address
5009 @comment - lock, unlock ... pointless given protect on/off (yes?)
5010 @comment - pgm_word ... shouldn't bank be deduced from address??
5011 Some pic32mx-specific commands are defined:
5012 @deffn Command {pic32mx pgm_word} address value bank
5013 Programs the specified 32-bit @var{value} at the given @var{address}
5014 in the specified chip @var{bank}.
5015 @end deffn
5016 @deffn Command {pic32mx unlock} bank
5017 Unlock and erase specified chip @var{bank}.
5018 This will remove any Code Protection.
5019 @end deffn
5020 @end deffn
5021
5022 @deffn {Flash Driver} stellaris
5023 All members of the Stellaris LM3Sxxx microcontroller family from
5024 Texas Instruments
5025 include internal flash and use ARM Cortex M3 cores.
5026 The driver automatically recognizes a number of these chips using
5027 the chip identification register, and autoconfigures itself.
5028 @footnote{Currently there is a @command{stellaris mass_erase} command.
5029 That seems pointless since the same effect can be had using the
5030 standard @command{flash erase_address} command.}
5031
5032 @example
5033 flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
5034 @end example
5035 @end deffn
5036
5037 @deffn Command {stellaris recover bank_id}
5038 Performs the @emph{Recovering a "Locked" Device} procedure to
5039 restore the flash specified by @var{bank_id} and its associated
5040 nonvolatile registers to their factory default values (erased).
5041 This is the only way to remove flash protection or re-enable
5042 debugging if that capability has been disabled.
5043
5044 Note that the final "power cycle the chip" step in this procedure
5045 must be performed by hand, since OpenOCD can't do it.
5046 @quotation Warning
5047 if more than one Stellaris chip is connected, the procedure is