docs: remove mixed case typo
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
11
12 @include version.texi
13
14 @copying
15
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
20
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
28
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
38
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
45
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
50
51 @summarycontents
52 @contents
53
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
57
58 @insertcopying
59 @end ifnottex
60
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * NAND Flash Commands:: NAND Flash Commands
77 * PLD/FPGA Commands:: PLD/FPGA Commands
78 * General Commands:: General Commands
79 * Architecture and Core Commands:: Architecture and Core Commands
80 * JTAG Commands:: JTAG Commands
81 * Boundary Scan Commands:: Boundary Scan Commands
82 * TFTP:: TFTP
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
88
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
95 @end menu
96
97 @node About
98 @unnumbered About
99 @cindex about
100
101 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
102 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
105 around the world.
106
107 @section What is OpenOCD?
108 @cindex TAP
109 @cindex JTAG
110
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
113 devices.
114
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
121
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
127
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board can be directly connected to the debug
132 host over USB (and sometimes also to power it over USB).
133
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
140 scan operations.
141
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD only supports
145 debugging, whereas JTAG also supports boundary scan operations.
146
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
151
152
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
154 based, parallel port based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
156
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
159 Cortex-M3 (Stellaris LM3, ST STM32 and Energy Micro EFM32) based cores to be
160 debugged via the GDB protocol.
161
162 @b{Flash Programing:} Flash writing is supported for external CFI
163 compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) controller is included.
167
168 @section OpenOCD Web Site
169
170 The OpenOCD web site provides the latest public news from the community:
171
172 @uref{http://openocd.sourceforge.net/}
173
174 @section Latest User's Guide:
175
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
179
180 @uref{http://openocd.sourceforge.net/doc/html/index.html}
181
182 PDF form is likewise published at:
183
184 @uref{http://openocd.sourceforge.net/doc/pdf/openocd.pdf}
185
186 @section OpenOCD User's Forum
187
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
193
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
195
196 @section OpenOCD User's Mailing List
197
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
200
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
202
203 @section OpenOCD IRC
204
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
207
208 @node Developers
209 @chapter OpenOCD Developer Resources
210 @cindex developers
211
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
216
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
219
220 @section OpenOCD GIT Repository
221
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a GIT repository hosted at SourceForge. The repository URL is:
224
225 @uref{git://git.code.sf.net/p/openocd/code}
226
227 or via http
228
229 @uref{http://git.code.sf.net/p/openocd/code}
230
231 You may prefer to use a mirror and the HTTP protocol:
232
233 @uref{http://repo.or.cz/r/openocd.git}
234
235 With standard GIT tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a GIT client:
240
241 @uref{http://repo.or.cz/w/openocd.git}
242
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
245
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
250
251 @section Doxygen Developer Manual
252
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
257
258 @uref{http://openocd.sourceforge.net/doc/doxygen/html/index.html}
259
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration in the top of the source tree.
263
264 @section OpenOCD Developer Mailing List
265
266 The OpenOCD Developer Mailing List provides the primary means of
267 communication between developers:
268
269 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
270
271 Discuss and submit patches to this list.
272 The @file{HACKING} file contains basic information about how
273 to prepare patches.
274
275 @section OpenOCD Bug Database
276
277 During the 0.4.x release cycle the OpenOCD project team began
278 using Trac for its bug database:
279
280 @uref{https://sourceforge.net/apps/trac/openocd}
281
282
283 @node Debug Adapter Hardware
284 @chapter Debug Adapter Hardware
285 @cindex dongles
286 @cindex FTDI
287 @cindex wiggler
288 @cindex zy1000
289 @cindex printer port
290 @cindex USB Adapter
291 @cindex RTCK
292
293 Defined: @b{dongle}: A small device that plugins into a computer and serves as
294 an adapter .... [snip]
295
296 In the OpenOCD case, this generally refers to @b{a small adapter} that
297 attaches to your computer via USB or the Parallel Printer Port. One
298 exception is the Zylin ZY1000, packaged as a small box you attach via
299 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
300 require any drivers to be installed on the developer PC. It also has
301 a built in web interface. It supports RTCK/RCLK or adaptive clocking
302 and has a built in relay to power cycle targets remotely.
303
304
305 @section Choosing a Dongle
306
307 There are several things you should keep in mind when choosing a dongle.
308
309 @enumerate
310 @item @b{Transport} Does it support the kind of communication that you need?
311 OpenOCD focusses mostly on JTAG. Your version may also support
312 other ways to communicate with target devices.
313 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
314 Does your dongle support it? You might need a level converter.
315 @item @b{Pinout} What pinout does your target board use?
316 Does your dongle support it? You may be able to use jumper
317 wires, or an "octopus" connector, to convert pinouts.
318 @item @b{Connection} Does your computer have the USB, printer, or
319 Ethernet port needed?
320 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
321 RTCK support? Also known as ``adaptive clocking''
322 @end enumerate
323
324 @section Stand-alone JTAG Probe
325
326 The ZY1000 from Ultimate Solutions is technically not a dongle but a
327 stand-alone JTAG probe that unlikemost dongles doesn’t require any drivers
328 running on the developers host computer.
329 Once installed on a network using DHCP or a static IP assignment, users can
330 access the ZY1000 probe locally or remotely from any host with access to the
331 IP address assigned to the probe.
332 The ZY1000 provides an intuitive web interface with direct access to the
333 OpenOCD debugger.
334 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
335 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
336 the target.
337 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
338 to power cycle the target remotely.
339
340 For more information, visit:
341
342 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/33-zylin-zy1000-jtag-probe}
343
344 @section USB FT2232 Based
345
346 There are many USB JTAG dongles on the market, many of them are based
347 on a chip from ``Future Technology Devices International'' (FTDI)
348 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
349 See: @url{http://www.ftdichip.com} for more information.
350 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
351 chips are starting to become available in JTAG adapters. Around 2012 a new
352 variant appeared - FT232H - this is a single-channel version of FT2232H.
353 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
354 clocking.)
355
356 The FT2232 chips are flexible enough to support some other
357 transport options, such as SWD or the SPI variants used to
358 program some chips. They have two communications channels,
359 and one can be used for a UART adapter at the same time the
360 other one is used to provide a debug adapter.
361
362 Also, some development boards integrate an FT2232 chip to serve as
363 a built-in low cost debug adapter and usb-to-serial solution.
364
365 @itemize @bullet
366 @item @b{usbjtag}
367 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
368 @item @b{jtagkey}
369 @* See: @url{http://www.amontec.com/jtagkey.shtml}
370 @item @b{jtagkey2}
371 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
372 @item @b{oocdlink}
373 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
374 @item @b{signalyzer}
375 @* See: @url{http://www.signalyzer.com}
376 @item @b{Stellaris Eval Boards}
377 @* See: @url{http://www.ti.com} - The Stellaris eval boards
378 bundle FT2232-based JTAG and SWD support, which can be used to debug
379 the Stellaris chips. Using separate JTAG adapters is optional.
380 These boards can also be used in a "pass through" mode as JTAG adapters
381 to other target boards, disabling the Stellaris chip.
382 @item @b{TI/Luminary ICDI}
383 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
384 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
385 Evaluation Kits. Like the non-detachable FT2232 support on the other
386 Stellaris eval boards, they can be used to debug other target boards.
387 @item @b{olimex-jtag}
388 @* See: @url{http://www.olimex.com}
389 @item @b{Flyswatter/Flyswatter2}
390 @* See: @url{http://www.tincantools.com}
391 @item @b{turtelizer2}
392 @* See:
393 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
394 @url{http://www.ethernut.de}
395 @item @b{comstick}
396 @* Link: @url{http://www.hitex.com/index.php?id=383}
397 @item @b{stm32stick}
398 @* Link @url{http://www.hitex.com/stm32-stick}
399 @item @b{axm0432_jtag}
400 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
401 to be available anymore as of April 2012.
402 @item @b{cortino}
403 @* Link @url{http://www.hitex.com/index.php?id=cortino}
404 @item @b{dlp-usb1232h}
405 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
406 @item @b{digilent-hs1}
407 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
408 @item @b{opendous}
409 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
410 (OpenHardware).
411 @item @b{JTAG-lock-pick Tiny 2}
412 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
413 @end itemize
414
415 @section USB-JTAG / Altera USB-Blaster compatibles
416
417 These devices also show up as FTDI devices, but are not
418 protocol-compatible with the FT2232 devices. They are, however,
419 protocol-compatible among themselves. USB-JTAG devices typically consist
420 of a FT245 followed by a CPLD that understands a particular protocol,
421 or emulate this protocol using some other hardware.
422
423 They may appear under different USB VID/PID depending on the particular
424 product. The driver can be configured to search for any VID/PID pair
425 (see the section on driver commands).
426
427 @itemize
428 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
429 @* Link: @url{http://ixo-jtag.sourceforge.net/}
430 @item @b{Altera USB-Blaster}
431 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
432 @end itemize
433
434 @section USB JLINK based
435 There are several OEM versions of the Segger @b{JLINK} adapter. It is
436 an example of a micro controller based JTAG adapter, it uses an
437 AT91SAM764 internally.
438
439 @itemize @bullet
440 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
441 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
442 @item @b{SEGGER JLINK}
443 @* Link: @url{http://www.segger.com/jlink.html}
444 @item @b{IAR J-Link}
445 @* Link: @url{http://www.iar.com/en/products/hardware-debug-probes/iar-j-link/}
446 @end itemize
447
448 @section USB RLINK based
449 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
450 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
451 SWD and not JTAG, thus not supported.
452
453 @itemize @bullet
454 @item @b{Raisonance RLink}
455 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
456 @item @b{STM32 Primer}
457 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
458 @item @b{STM32 Primer2}
459 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
460 @end itemize
461
462 @section USB ST-LINK based
463 ST Micro has an adapter called @b{ST-LINK}.
464 They only work with ST Micro chips, notably STM32 and STM8.
465
466 @itemize @bullet
467 @item @b{ST-LINK}
468 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
469 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
470 @item @b{ST-LINK/V2}
471 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
472 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
473 @end itemize
474
475 For info the original ST-LINK enumerates using the mass storage usb class, however
476 it's implementation is completely broken. The result is this causes issues under linux.
477 The simplest solution is to get linux to ignore the ST-LINK using one of the following methods:
478 @itemize @bullet
479 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
480 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
481 @end itemize
482
483 @section USB TI/Stellaris ICDI based
484 Texas Instruments has an adapter called @b{ICDI}.
485 It is not to be confused with the FTDI based adapters that were originally fitted to their
486 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
487
488 @section USB Other
489 @itemize @bullet
490 @item @b{USBprog}
491 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
492
493 @item @b{USB - Presto}
494 @* Link: @url{http://tools.asix.net/prg_presto.htm}
495
496 @item @b{Versaloon-Link}
497 @* Link: @url{http://www.versaloon.com}
498
499 @item @b{ARM-JTAG-EW}
500 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
501
502 @item @b{Buspirate}
503 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
504
505 @item @b{opendous}
506 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
507
508 @item @b{estick}
509 @* Link: @url{http://code.google.com/p/estick-jtag/}
510
511 @item @b{Keil ULINK v1}
512 @* Link: @url{http://www.keil.com/ulink1/}
513 @end itemize
514
515 @section IBM PC Parallel Printer Port Based
516
517 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
518 and the Macraigor Wiggler. There are many clones and variations of
519 these on the market.
520
521 Note that parallel ports are becoming much less common, so if you
522 have the choice you should probably avoid these adapters in favor
523 of USB-based ones.
524
525 @itemize @bullet
526
527 @item @b{Wiggler} - There are many clones of this.
528 @* Link: @url{http://www.macraigor.com/wiggler.htm}
529
530 @item @b{DLC5} - From XILINX - There are many clones of this
531 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
532 produced, PDF schematics are easily found and it is easy to make.
533
534 @item @b{Amontec - JTAG Accelerator}
535 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
536
537 @item @b{GW16402}
538 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
539
540 @item @b{Wiggler2}
541 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
542
543 @item @b{Wiggler_ntrst_inverted}
544 @* Yet another variation - See the source code, src/jtag/parport.c
545
546 @item @b{old_amt_wiggler}
547 @* Unknown - probably not on the market today
548
549 @item @b{arm-jtag}
550 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
551
552 @item @b{chameleon}
553 @* Link: @url{http://www.amontec.com/chameleon.shtml}
554
555 @item @b{Triton}
556 @* Unknown.
557
558 @item @b{Lattice}
559 @* ispDownload from Lattice Semiconductor
560 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
561
562 @item @b{flashlink}
563 @* From ST Microsystems;
564 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
565
566 @end itemize
567
568 @section Other...
569 @itemize @bullet
570
571 @item @b{ep93xx}
572 @* An EP93xx based Linux machine using the GPIO pins directly.
573
574 @item @b{at91rm9200}
575 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
576
577 @item @b{bcm2835gpio}
578 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
579
580 @end itemize
581
582 @node About Jim-Tcl
583 @chapter About Jim-Tcl
584 @cindex Jim-Tcl
585 @cindex tcl
586
587 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
588 This programming language provides a simple and extensible
589 command interpreter.
590
591 All commands presented in this Guide are extensions to Jim-Tcl.
592 You can use them as simple commands, without needing to learn
593 much of anything about Tcl.
594 Alternatively, can write Tcl programs with them.
595
596 You can learn more about Jim at its website, @url{http://jim.berlios.de}.
597 There is an active and responsive community, get on the mailing list
598 if you have any questions. Jim-Tcl maintainers also lurk on the
599 OpenOCD mailing list.
600
601 @itemize @bullet
602 @item @b{Jim vs. Tcl}
603 @* Jim-Tcl is a stripped down version of the well known Tcl language,
604 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
605 fewer features. Jim-Tcl is several dozens of .C files and .H files and
606 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
607 4.2 MB .zip file containing 1540 files.
608
609 @item @b{Missing Features}
610 @* Our practice has been: Add/clone the real Tcl feature if/when
611 needed. We welcome Jim-Tcl improvements, not bloat. Also there
612 are a large number of optional Jim-Tcl features that are not
613 enabled in OpenOCD.
614
615 @item @b{Scripts}
616 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
617 command interpreter today is a mixture of (newer)
618 Jim-Tcl commands, and (older) the orginal command interpreter.
619
620 @item @b{Commands}
621 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
622 can type a Tcl for() loop, set variables, etc.
623 Some of the commands documented in this guide are implemented
624 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
625
626 @item @b{Historical Note}
627 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
628 before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
629 as a git submodule, which greatly simplified upgrading Jim Tcl
630 to benefit from new features and bugfixes in Jim Tcl.
631
632 @item @b{Need a crash course in Tcl?}
633 @*@xref{Tcl Crash Course}.
634 @end itemize
635
636 @node Running
637 @chapter Running
638 @cindex command line options
639 @cindex logfile
640 @cindex directory search
641
642 Properly installing OpenOCD sets up your operating system to grant it access
643 to the debug adapters. On Linux, this usually involves installing a file
644 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
645 complex and confusing driver configuration for every peripheral. Such issues
646 are unique to each operating system, and are not detailed in this User's Guide.
647
648 Then later you will invoke the OpenOCD server, with various options to
649 tell it how each debug session should work.
650 The @option{--help} option shows:
651 @verbatim
652 bash$ openocd --help
653
654 --help | -h display this help
655 --version | -v display OpenOCD version
656 --file | -f use configuration file <name>
657 --search | -s dir to search for config files and scripts
658 --debug | -d set debug level <0-3>
659 --log_output | -l redirect log output to file <name>
660 --command | -c run <command>
661 @end verbatim
662
663 If you don't give any @option{-f} or @option{-c} options,
664 OpenOCD tries to read the configuration file @file{openocd.cfg}.
665 To specify one or more different
666 configuration files, use @option{-f} options. For example:
667
668 @example
669 openocd -f config1.cfg -f config2.cfg -f config3.cfg
670 @end example
671
672 Configuration files and scripts are searched for in
673 @enumerate
674 @item the current directory,
675 @item any search dir specified on the command line using the @option{-s} option,
676 @item any search dir specified using the @command{add_script_search_dir} command,
677 @item @file{$HOME/.openocd} (not on Windows),
678 @item the site wide script library @file{$pkgdatadir/site} and
679 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
680 @end enumerate
681 The first found file with a matching file name will be used.
682
683 @quotation Note
684 Don't try to use configuration script names or paths which
685 include the "#" character. That character begins Tcl comments.
686 @end quotation
687
688 @section Simple setup, no customization
689
690 In the best case, you can use two scripts from one of the script
691 libraries, hook up your JTAG adapter, and start the server ... and
692 your JTAG setup will just work "out of the box". Always try to
693 start by reusing those scripts, but assume you'll need more
694 customization even if this works. @xref{OpenOCD Project Setup}.
695
696 If you find a script for your JTAG adapter, and for your board or
697 target, you may be able to hook up your JTAG adapter then start
698 the server like:
699
700 @example
701 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
702 @end example
703
704 You might also need to configure which reset signals are present,
705 using @option{-c 'reset_config trst_and_srst'} or something similar.
706 If all goes well you'll see output something like
707
708 @example
709 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
710 For bug reports, read
711 http://openocd.sourceforge.net/doc/doxygen/bugs.html
712 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
713 (mfg: 0x23b, part: 0xba00, ver: 0x3)
714 @end example
715
716 Seeing that "tap/device found" message, and no warnings, means
717 the JTAG communication is working. That's a key milestone, but
718 you'll probably need more project-specific setup.
719
720 @section What OpenOCD does as it starts
721
722 OpenOCD starts by processing the configuration commands provided
723 on the command line or, if there were no @option{-c command} or
724 @option{-f file.cfg} options given, in @file{openocd.cfg}.
725 @xref{configurationstage,,Configuration Stage}.
726 At the end of the configuration stage it verifies the JTAG scan
727 chain defined using those commands; your configuration should
728 ensure that this always succeeds.
729 Normally, OpenOCD then starts running as a daemon.
730 Alternatively, commands may be used to terminate the configuration
731 stage early, perform work (such as updating some flash memory),
732 and then shut down without acting as a daemon.
733
734 Once OpenOCD starts running as a daemon, it waits for connections from
735 clients (Telnet, GDB, Other) and processes the commands issued through
736 those channels.
737
738 If you are having problems, you can enable internal debug messages via
739 the @option{-d} option.
740
741 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
742 @option{-c} command line switch.
743
744 To enable debug output (when reporting problems or working on OpenOCD
745 itself), use the @option{-d} command line switch. This sets the
746 @option{debug_level} to "3", outputting the most information,
747 including debug messages. The default setting is "2", outputting only
748 informational messages, warnings and errors. You can also change this
749 setting from within a telnet or gdb session using @command{debug_level<n>}
750 (@pxref{debuglevel,,debug_level}).
751
752 You can redirect all output from the daemon to a file using the
753 @option{-l <logfile>} switch.
754
755 Note! OpenOCD will launch the GDB & telnet server even if it can not
756 establish a connection with the target. In general, it is possible for
757 the JTAG controller to be unresponsive until the target is set up
758 correctly via e.g. GDB monitor commands in a GDB init script.
759
760 @node OpenOCD Project Setup
761 @chapter OpenOCD Project Setup
762
763 To use OpenOCD with your development projects, you need to do more than
764 just connecting the JTAG adapter hardware (dongle) to your development board
765 and then starting the OpenOCD server.
766 You also need to configure that server so that it knows
767 about that adapter and board, and helps your work.
768 You may also want to connect OpenOCD to GDB, possibly
769 using Eclipse or some other GUI.
770
771 @section Hooking up the JTAG Adapter
772
773 Today's most common case is a dongle with a JTAG cable on one side
774 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
775 and a USB cable on the other.
776 Instead of USB, some cables use Ethernet;
777 older ones may use a PC parallel port, or even a serial port.
778
779 @enumerate
780 @item @emph{Start with power to your target board turned off},
781 and nothing connected to your JTAG adapter.
782 If you're particularly paranoid, unplug power to the board.
783 It's important to have the ground signal properly set up,
784 unless you are using a JTAG adapter which provides
785 galvanic isolation between the target board and the
786 debugging host.
787
788 @item @emph{Be sure it's the right kind of JTAG connector.}
789 If your dongle has a 20-pin ARM connector, you need some kind
790 of adapter (or octopus, see below) to hook it up to
791 boards using 14-pin or 10-pin connectors ... or to 20-pin
792 connectors which don't use ARM's pinout.
793
794 In the same vein, make sure the voltage levels are compatible.
795 Not all JTAG adapters have the level shifters needed to work
796 with 1.2 Volt boards.
797
798 @item @emph{Be certain the cable is properly oriented} or you might
799 damage your board. In most cases there are only two possible
800 ways to connect the cable.
801 Connect the JTAG cable from your adapter to the board.
802 Be sure it's firmly connected.
803
804 In the best case, the connector is keyed to physically
805 prevent you from inserting it wrong.
806 This is most often done using a slot on the board's male connector
807 housing, which must match a key on the JTAG cable's female connector.
808 If there's no housing, then you must look carefully and
809 make sure pin 1 on the cable hooks up to pin 1 on the board.
810 Ribbon cables are frequently all grey except for a wire on one
811 edge, which is red. The red wire is pin 1.
812
813 Sometimes dongles provide cables where one end is an ``octopus'' of
814 color coded single-wire connectors, instead of a connector block.
815 These are great when converting from one JTAG pinout to another,
816 but are tedious to set up.
817 Use these with connector pinout diagrams to help you match up the
818 adapter signals to the right board pins.
819
820 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
821 A USB, parallel, or serial port connector will go to the host which
822 you are using to run OpenOCD.
823 For Ethernet, consult the documentation and your network administrator.
824
825 For USB based JTAG adapters you have an easy sanity check at this point:
826 does the host operating system see the JTAG adapter? If that host is an
827 MS-Windows host, you'll need to install a driver before OpenOCD works.
828
829 @item @emph{Connect the adapter's power supply, if needed.}
830 This step is primarily for non-USB adapters,
831 but sometimes USB adapters need extra power.
832
833 @item @emph{Power up the target board.}
834 Unless you just let the magic smoke escape,
835 you're now ready to set up the OpenOCD server
836 so you can use JTAG to work with that board.
837
838 @end enumerate
839
840 Talk with the OpenOCD server using
841 telnet (@code{telnet localhost 4444} on many systems) or GDB.
842 @xref{GDB and OpenOCD}.
843
844 @section Project Directory
845
846 There are many ways you can configure OpenOCD and start it up.
847
848 A simple way to organize them all involves keeping a
849 single directory for your work with a given board.
850 When you start OpenOCD from that directory,
851 it searches there first for configuration files, scripts,
852 files accessed through semihosting,
853 and for code you upload to the target board.
854 It is also the natural place to write files,
855 such as log files and data you download from the board.
856
857 @section Configuration Basics
858
859 There are two basic ways of configuring OpenOCD, and
860 a variety of ways you can mix them.
861 Think of the difference as just being how you start the server:
862
863 @itemize
864 @item Many @option{-f file} or @option{-c command} options on the command line
865 @item No options, but a @dfn{user config file}
866 in the current directory named @file{openocd.cfg}
867 @end itemize
868
869 Here is an example @file{openocd.cfg} file for a setup
870 using a Signalyzer FT2232-based JTAG adapter to talk to
871 a board with an Atmel AT91SAM7X256 microcontroller:
872
873 @example
874 source [find interface/signalyzer.cfg]
875
876 # GDB can also flash my flash!
877 gdb_memory_map enable
878 gdb_flash_program enable
879
880 source [find target/sam7x256.cfg]
881 @end example
882
883 Here is the command line equivalent of that configuration:
884
885 @example
886 openocd -f interface/signalyzer.cfg \
887 -c "gdb_memory_map enable" \
888 -c "gdb_flash_program enable" \
889 -f target/sam7x256.cfg
890 @end example
891
892 You could wrap such long command lines in shell scripts,
893 each supporting a different development task.
894 One might re-flash the board with a specific firmware version.
895 Another might set up a particular debugging or run-time environment.
896
897 @quotation Important
898 At this writing (October 2009) the command line method has
899 problems with how it treats variables.
900 For example, after @option{-c "set VAR value"}, or doing the
901 same in a script, the variable @var{VAR} will have no value
902 that can be tested in a later script.
903 @end quotation
904
905 Here we will focus on the simpler solution: one user config
906 file, including basic configuration plus any TCL procedures
907 to simplify your work.
908
909 @section User Config Files
910 @cindex config file, user
911 @cindex user config file
912 @cindex config file, overview
913
914 A user configuration file ties together all the parts of a project
915 in one place.
916 One of the following will match your situation best:
917
918 @itemize
919 @item Ideally almost everything comes from configuration files
920 provided by someone else.
921 For example, OpenOCD distributes a @file{scripts} directory
922 (probably in @file{/usr/share/openocd/scripts} on Linux).
923 Board and tool vendors can provide these too, as can individual
924 user sites; the @option{-s} command line option lets you say
925 where to find these files. (@xref{Running}.)
926 The AT91SAM7X256 example above works this way.
927
928 Three main types of non-user configuration file each have their
929 own subdirectory in the @file{scripts} directory:
930
931 @enumerate
932 @item @b{interface} -- one for each different debug adapter;
933 @item @b{board} -- one for each different board
934 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
935 @end enumerate
936
937 Best case: include just two files, and they handle everything else.
938 The first is an interface config file.
939 The second is board-specific, and it sets up the JTAG TAPs and
940 their GDB targets (by deferring to some @file{target.cfg} file),
941 declares all flash memory, and leaves you nothing to do except
942 meet your deadline:
943
944 @example
945 source [find interface/olimex-jtag-tiny.cfg]
946 source [find board/csb337.cfg]
947 @end example
948
949 Boards with a single microcontroller often won't need more
950 than the target config file, as in the AT91SAM7X256 example.
951 That's because there is no external memory (flash, DDR RAM), and
952 the board differences are encapsulated by application code.
953
954 @item Maybe you don't know yet what your board looks like to JTAG.
955 Once you know the @file{interface.cfg} file to use, you may
956 need help from OpenOCD to discover what's on the board.
957 Once you find the JTAG TAPs, you can just search for appropriate
958 target and board
959 configuration files ... or write your own, from the bottom up.
960 @xref{autoprobing,,Autoprobing}.
961
962 @item You can often reuse some standard config files but
963 need to write a few new ones, probably a @file{board.cfg} file.
964 You will be using commands described later in this User's Guide,
965 and working with the guidelines in the next chapter.
966
967 For example, there may be configuration files for your JTAG adapter
968 and target chip, but you need a new board-specific config file
969 giving access to your particular flash chips.
970 Or you might need to write another target chip configuration file
971 for a new chip built around the Cortex M3 core.
972
973 @quotation Note
974 When you write new configuration files, please submit
975 them for inclusion in the next OpenOCD release.
976 For example, a @file{board/newboard.cfg} file will help the
977 next users of that board, and a @file{target/newcpu.cfg}
978 will help support users of any board using that chip.
979 @end quotation
980
981 @item
982 You may may need to write some C code.
983 It may be as simple as a supporting a new ft2232 or parport
984 based adapter; a bit more involved, like a NAND or NOR flash
985 controller driver; or a big piece of work like supporting
986 a new chip architecture.
987 @end itemize
988
989 Reuse the existing config files when you can.
990 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
991 You may find a board configuration that's a good example to follow.
992
993 When you write config files, separate the reusable parts
994 (things every user of that interface, chip, or board needs)
995 from ones specific to your environment and debugging approach.
996 @itemize
997
998 @item
999 For example, a @code{gdb-attach} event handler that invokes
1000 the @command{reset init} command will interfere with debugging
1001 early boot code, which performs some of the same actions
1002 that the @code{reset-init} event handler does.
1003
1004 @item
1005 Likewise, the @command{arm9 vector_catch} command (or
1006 @cindex vector_catch
1007 its siblings @command{xscale vector_catch}
1008 and @command{cortex_m vector_catch}) can be a timesaver
1009 during some debug sessions, but don't make everyone use that either.
1010 Keep those kinds of debugging aids in your user config file,
1011 along with messaging and tracing setup.
1012 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1013
1014 @item
1015 You might need to override some defaults.
1016 For example, you might need to move, shrink, or back up the target's
1017 work area if your application needs much SRAM.
1018
1019 @item
1020 TCP/IP port configuration is another example of something which
1021 is environment-specific, and should only appear in
1022 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1023 @end itemize
1024
1025 @section Project-Specific Utilities
1026
1027 A few project-specific utility
1028 routines may well speed up your work.
1029 Write them, and keep them in your project's user config file.
1030
1031 For example, if you are making a boot loader work on a
1032 board, it's nice to be able to debug the ``after it's
1033 loaded to RAM'' parts separately from the finicky early
1034 code which sets up the DDR RAM controller and clocks.
1035 A script like this one, or a more GDB-aware sibling,
1036 may help:
1037
1038 @example
1039 proc ramboot @{ @} @{
1040 # Reset, running the target's "reset-init" scripts
1041 # to initialize clocks and the DDR RAM controller.
1042 # Leave the CPU halted.
1043 reset init
1044
1045 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1046 load_image u-boot.bin 0x20000000
1047
1048 # Start running.
1049 resume 0x20000000
1050 @}
1051 @end example
1052
1053 Then once that code is working you will need to make it
1054 boot from NOR flash; a different utility would help.
1055 Alternatively, some developers write to flash using GDB.
1056 (You might use a similar script if you're working with a flash
1057 based microcontroller application instead of a boot loader.)
1058
1059 @example
1060 proc newboot @{ @} @{
1061 # Reset, leaving the CPU halted. The "reset-init" event
1062 # proc gives faster access to the CPU and to NOR flash;
1063 # "reset halt" would be slower.
1064 reset init
1065
1066 # Write standard version of U-Boot into the first two
1067 # sectors of NOR flash ... the standard version should
1068 # do the same lowlevel init as "reset-init".
1069 flash protect 0 0 1 off
1070 flash erase_sector 0 0 1
1071 flash write_bank 0 u-boot.bin 0x0
1072 flash protect 0 0 1 on
1073
1074 # Reboot from scratch using that new boot loader.
1075 reset run
1076 @}
1077 @end example
1078
1079 You may need more complicated utility procedures when booting
1080 from NAND.
1081 That often involves an extra bootloader stage,
1082 running from on-chip SRAM to perform DDR RAM setup so it can load
1083 the main bootloader code (which won't fit into that SRAM).
1084
1085 Other helper scripts might be used to write production system images,
1086 involving considerably more than just a three stage bootloader.
1087
1088 @section Target Software Changes
1089
1090 Sometimes you may want to make some small changes to the software
1091 you're developing, to help make JTAG debugging work better.
1092 For example, in C or assembly language code you might
1093 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1094 handling issues like:
1095
1096 @itemize @bullet
1097
1098 @item @b{Watchdog Timers}...
1099 Watchog timers are typically used to automatically reset systems if
1100 some application task doesn't periodically reset the timer. (The
1101 assumption is that the system has locked up if the task can't run.)
1102 When a JTAG debugger halts the system, that task won't be able to run
1103 and reset the timer ... potentially causing resets in the middle of
1104 your debug sessions.
1105
1106 It's rarely a good idea to disable such watchdogs, since their usage
1107 needs to be debugged just like all other parts of your firmware.
1108 That might however be your only option.
1109
1110 Look instead for chip-specific ways to stop the watchdog from counting
1111 while the system is in a debug halt state. It may be simplest to set
1112 that non-counting mode in your debugger startup scripts. You may however
1113 need a different approach when, for example, a motor could be physically
1114 damaged by firmware remaining inactive in a debug halt state. That might
1115 involve a type of firmware mode where that "non-counting" mode is disabled
1116 at the beginning then re-enabled at the end; a watchdog reset might fire
1117 and complicate the debug session, but hardware (or people) would be
1118 protected.@footnote{Note that many systems support a "monitor mode" debug
1119 that is a somewhat cleaner way to address such issues. You can think of
1120 it as only halting part of the system, maybe just one task,
1121 instead of the whole thing.
1122 At this writing, January 2010, OpenOCD based debugging does not support
1123 monitor mode debug, only "halt mode" debug.}
1124
1125 @item @b{ARM Semihosting}...
1126 @cindex ARM semihosting
1127 When linked with a special runtime library provided with many
1128 toolchains@footnote{See chapter 8 "Semihosting" in
1129 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1130 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1131 The CodeSourcery EABI toolchain also includes a semihosting library.},
1132 your target code can use I/O facilities on the debug host. That library
1133 provides a small set of system calls which are handled by OpenOCD.
1134 It can let the debugger provide your system console and a file system,
1135 helping with early debugging or providing a more capable environment
1136 for sometimes-complex tasks like installing system firmware onto
1137 NAND or SPI flash.
1138
1139 @item @b{ARM Wait-For-Interrupt}...
1140 Many ARM chips synchronize the JTAG clock using the core clock.
1141 Low power states which stop that core clock thus prevent JTAG access.
1142 Idle loops in tasking environments often enter those low power states
1143 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1144
1145 You may want to @emph{disable that instruction} in source code,
1146 or otherwise prevent using that state,
1147 to ensure you can get JTAG access at any time.@footnote{As a more
1148 polite alternative, some processors have special debug-oriented
1149 registers which can be used to change various features including
1150 how the low power states are clocked while debugging.
1151 The STM32 DBGMCU_CR register is an example; at the cost of extra
1152 power consumption, JTAG can be used during low power states.}
1153 For example, the OpenOCD @command{halt} command may not
1154 work for an idle processor otherwise.
1155
1156 @item @b{Delay after reset}...
1157 Not all chips have good support for debugger access
1158 right after reset; many LPC2xxx chips have issues here.
1159 Similarly, applications that reconfigure pins used for
1160 JTAG access as they start will also block debugger access.
1161
1162 To work with boards like this, @emph{enable a short delay loop}
1163 the first thing after reset, before "real" startup activities.
1164 For example, one second's delay is usually more than enough
1165 time for a JTAG debugger to attach, so that
1166 early code execution can be debugged
1167 or firmware can be replaced.
1168
1169 @item @b{Debug Communications Channel (DCC)}...
1170 Some processors include mechanisms to send messages over JTAG.
1171 Many ARM cores support these, as do some cores from other vendors.
1172 (OpenOCD may be able to use this DCC internally, speeding up some
1173 operations like writing to memory.)
1174
1175 Your application may want to deliver various debugging messages
1176 over JTAG, by @emph{linking with a small library of code}
1177 provided with OpenOCD and using the utilities there to send
1178 various kinds of message.
1179 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1180
1181 @end itemize
1182
1183 @section Target Hardware Setup
1184
1185 Chip vendors often provide software development boards which
1186 are highly configurable, so that they can support all options
1187 that product boards may require. @emph{Make sure that any
1188 jumpers or switches match the system configuration you are
1189 working with.}
1190
1191 Common issues include:
1192
1193 @itemize @bullet
1194
1195 @item @b{JTAG setup} ...
1196 Boards may support more than one JTAG configuration.
1197 Examples include jumpers controlling pullups versus pulldowns
1198 on the nTRST and/or nSRST signals, and choice of connectors
1199 (e.g. which of two headers on the base board,
1200 or one from a daughtercard).
1201 For some Texas Instruments boards, you may need to jumper the
1202 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1203
1204 @item @b{Boot Modes} ...
1205 Complex chips often support multiple boot modes, controlled
1206 by external jumpers. Make sure this is set up correctly.
1207 For example many i.MX boards from NXP need to be jumpered
1208 to "ATX mode" to start booting using the on-chip ROM, when
1209 using second stage bootloader code stored in a NAND flash chip.
1210
1211 Such explicit configuration is common, and not limited to
1212 booting from NAND. You might also need to set jumpers to
1213 start booting using code loaded from an MMC/SD card; external
1214 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1215 flash; some external host; or various other sources.
1216
1217
1218 @item @b{Memory Addressing} ...
1219 Boards which support multiple boot modes may also have jumpers
1220 to configure memory addressing. One board, for example, jumpers
1221 external chipselect 0 (used for booting) to address either
1222 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1223 or NAND flash. When it's jumpered to address NAND flash, that
1224 board must also be told to start booting from on-chip ROM.
1225
1226 Your @file{board.cfg} file may also need to be told this jumper
1227 configuration, so that it can know whether to declare NOR flash
1228 using @command{flash bank} or instead declare NAND flash with
1229 @command{nand device}; and likewise which probe to perform in
1230 its @code{reset-init} handler.
1231
1232 A closely related issue is bus width. Jumpers might need to
1233 distinguish between 8 bit or 16 bit bus access for the flash
1234 used to start booting.
1235
1236 @item @b{Peripheral Access} ...
1237 Development boards generally provide access to every peripheral
1238 on the chip, sometimes in multiple modes (such as by providing
1239 multiple audio codec chips).
1240 This interacts with software
1241 configuration of pin multiplexing, where for example a
1242 given pin may be routed either to the MMC/SD controller
1243 or the GPIO controller. It also often interacts with
1244 configuration jumpers. One jumper may be used to route
1245 signals to an MMC/SD card slot or an expansion bus (which
1246 might in turn affect booting); others might control which
1247 audio or video codecs are used.
1248
1249 @end itemize
1250
1251 Plus you should of course have @code{reset-init} event handlers
1252 which set up the hardware to match that jumper configuration.
1253 That includes in particular any oscillator or PLL used to clock
1254 the CPU, and any memory controllers needed to access external
1255 memory and peripherals. Without such handlers, you won't be
1256 able to access those resources without working target firmware
1257 which can do that setup ... this can be awkward when you're
1258 trying to debug that target firmware. Even if there's a ROM
1259 bootloader which handles a few issues, it rarely provides full
1260 access to all board-specific capabilities.
1261
1262
1263 @node Config File Guidelines
1264 @chapter Config File Guidelines
1265
1266 This chapter is aimed at any user who needs to write a config file,
1267 including developers and integrators of OpenOCD and any user who
1268 needs to get a new board working smoothly.
1269 It provides guidelines for creating those files.
1270
1271 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1272 with files including the ones listed here.
1273 Use them as-is where you can; or as models for new files.
1274 @itemize @bullet
1275 @item @file{interface} ...
1276 These are for debug adapters.
1277 Files that configure JTAG adapters go here.
1278 @example
1279 $ ls interface -R
1280 interface/:
1281 altera-usb-blaster.cfg hilscher_nxhx50_re.cfg openocd-usb-hs.cfg
1282 arm-jtag-ew.cfg hitex_str9-comstick.cfg openrd.cfg
1283 at91rm9200.cfg icebear.cfg osbdm.cfg
1284 axm0432.cfg jlink.cfg parport.cfg
1285 busblaster.cfg jtagkey2.cfg parport_dlc5.cfg
1286 buspirate.cfg jtagkey2p.cfg redbee-econotag.cfg
1287 calao-usb-a9260-c01.cfg jtagkey.cfg redbee-usb.cfg
1288 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg rlink.cfg
1289 calao-usb-a9260.cfg jtag-lock-pick_tiny_2.cfg sheevaplug.cfg
1290 chameleon.cfg kt-link.cfg signalyzer.cfg
1291 cortino.cfg lisa-l.cfg signalyzer-h2.cfg
1292 digilent-hs1.cfg luminary.cfg signalyzer-h4.cfg
1293 dlp-usb1232h.cfg luminary-icdi.cfg signalyzer-lite.cfg
1294 dummy.cfg luminary-lm3s811.cfg stlink-v1.cfg
1295 estick.cfg minimodule.cfg stlink-v2.cfg
1296 flashlink.cfg neodb.cfg stm32-stick.cfg
1297 flossjtag.cfg ngxtech.cfg sysfsgpio-raspberrypi.cfg
1298 flossjtag-noeeprom.cfg olimex-arm-usb-ocd.cfg ti-icdi.cfg
1299 flyswatter2.cfg olimex-arm-usb-ocd-h.cfg turtelizer2.cfg
1300 flyswatter.cfg olimex-arm-usb-tiny-h.cfg ulink.cfg
1301 ftdi olimex-jtag-tiny.cfg usb-jtag.cfg
1302 hilscher_nxhx10_etm.cfg oocdlink.cfg usbprog.cfg
1303 hilscher_nxhx500_etm.cfg opendous.cfg vpaclink.cfg
1304 hilscher_nxhx500_re.cfg opendous_ftdi.cfg vsllink.cfg
1305 hilscher_nxhx50_etm.cfg openocd-usb.cfg xds100v2.cfg
1306
1307 interface/ftdi:
1308 axm0432.cfg icebear.cfg oocdlink.cfg
1309 calao-usb-a9260-c01.cfg jtagkey2.cfg opendous_ftdi.cfg
1310 calao-usb-a9260-c02.cfg jtagkey2p.cfg openocd-usb.cfg
1311 cortino.cfg jtagkey.cfg openocd-usb-hs.cfg
1312 dlp-usb1232h.cfg jtag-lock-pick_tiny_2.cfg openrd.cfg
1313 dp_busblaster.cfg kt-link.cfg redbee-econotag.cfg
1314 flossjtag.cfg lisa-l.cfg redbee-usb.cfg
1315 flossjtag-noeeprom.cfg luminary.cfg sheevaplug.cfg
1316 flyswatter2.cfg luminary-icdi.cfg signalyzer.cfg
1317 flyswatter.cfg luminary-lm3s811.cfg signalyzer-lite.cfg
1318 hilscher_nxhx10_etm.cfg minimodule.cfg stm32-stick.cfg
1319 hilscher_nxhx500_etm.cfg neodb.cfg turtelizer2-revB.cfg
1320 hilscher_nxhx500_re.cfg ngxtech.cfg turtelizer2-revC.cfg
1321 hilscher_nxhx50_etm.cfg olimex-arm-usb-ocd.cfg vpaclink.cfg
1322 hilscher_nxhx50_re.cfg olimex-arm-usb-ocd-h.cfg xds100v2.cfg
1323 hitex_lpc1768stick.cfg olimex-arm-usb-tiny-h.cfg
1324 hitex_str9-comstick.cfg olimex-jtag-tiny.cfg
1325 $
1326 @end example
1327 @item @file{board} ...
1328 think Circuit Board, PWA, PCB, they go by many names. Board files
1329 contain initialization items that are specific to a board.
1330 They reuse target configuration files, since the same
1331 microprocessor chips are used on many boards,
1332 but support for external parts varies widely. For
1333 example, the SDRAM initialization sequence for the board, or the type
1334 of external flash and what address it uses. Any initialization
1335 sequence to enable that external flash or SDRAM should be found in the
1336 board file. Boards may also contain multiple targets: two CPUs; or
1337 a CPU and an FPGA.
1338 @example
1339 $ ls board
1340 actux3.cfg lpc1850_spifi_generic.cfg
1341 am3517evm.cfg lpc4350_spifi_generic.cfg
1342 arm_evaluator7t.cfg lubbock.cfg
1343 at91cap7a-stk-sdram.cfg mcb1700.cfg
1344 at91eb40a.cfg microchip_explorer16.cfg
1345 at91rm9200-dk.cfg mini2440.cfg
1346 at91rm9200-ek.cfg mini6410.cfg
1347 at91sam9261-ek.cfg netgear-dg834v3.cfg
1348 at91sam9263-ek.cfg olimex_LPC2378STK.cfg
1349 at91sam9g20-ek.cfg olimex_lpc_h2148.cfg
1350 atmel_at91sam7s-ek.cfg olimex_sam7_ex256.cfg
1351 atmel_at91sam9260-ek.cfg olimex_sam9_l9260.cfg
1352 atmel_at91sam9rl-ek.cfg olimex_stm32_h103.cfg
1353 atmel_sam3n_ek.cfg olimex_stm32_h107.cfg
1354 atmel_sam3s_ek.cfg olimex_stm32_p107.cfg
1355 atmel_sam3u_ek.cfg omap2420_h4.cfg
1356 atmel_sam3x_ek.cfg open-bldc.cfg
1357 atmel_sam4s_ek.cfg openrd.cfg
1358 balloon3-cpu.cfg osk5912.cfg
1359 colibri.cfg phone_se_j100i.cfg
1360 crossbow_tech_imote2.cfg phytec_lpc3250.cfg
1361 csb337.cfg pic-p32mx.cfg
1362 csb732.cfg propox_mmnet1001.cfg
1363 da850evm.cfg pxa255_sst.cfg
1364 digi_connectcore_wi-9c.cfg redbee.cfg
1365 diolan_lpc4350-db1.cfg rsc-w910.cfg
1366 dm355evm.cfg sheevaplug.cfg
1367 dm365evm.cfg smdk6410.cfg
1368 dm6446evm.cfg spear300evb.cfg
1369 efikamx.cfg spear300evb_mod.cfg
1370 eir.cfg spear310evb20.cfg
1371 ek-lm3s1968.cfg spear310evb20_mod.cfg
1372 ek-lm3s3748.cfg spear320cpu.cfg
1373 ek-lm3s6965.cfg spear320cpu_mod.cfg
1374 ek-lm3s811.cfg steval_pcc010.cfg
1375 ek-lm3s811-revb.cfg stm320518_eval_stlink.cfg
1376 ek-lm3s8962.cfg stm32100b_eval.cfg
1377 ek-lm3s9b9x.cfg stm3210b_eval.cfg
1378 ek-lm3s9d92.cfg stm3210c_eval.cfg
1379 ek-lm4f120xl.cfg stm3210e_eval.cfg
1380 ek-lm4f232.cfg stm3220g_eval.cfg
1381 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1382 ethernut3.cfg stm3241g_eval.cfg
1383 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1384 hammer.cfg stm32f0discovery.cfg
1385 hilscher_nxdb500sys.cfg stm32f3discovery.cfg
1386 hilscher_nxeb500hmi.cfg stm32f4discovery.cfg
1387 hilscher_nxhx10.cfg stm32ldiscovery.cfg
1388 hilscher_nxhx500.cfg stm32vldiscovery.cfg
1389 hilscher_nxhx50.cfg str910-eval.cfg
1390 hilscher_nxsb100.cfg telo.cfg
1391 hitex_lpc1768stick.cfg ti_am335xevm.cfg
1392 hitex_lpc2929.cfg ti_beagleboard.cfg
1393 hitex_stm32-performancestick.cfg ti_beagleboard_xm.cfg
1394 hitex_str9-comstick.cfg ti_beaglebone.cfg
1395 iar_lpc1768.cfg ti_blaze.cfg
1396 iar_str912_sk.cfg ti_pandaboard.cfg
1397 icnova_imx53_sodimm.cfg ti_pandaboard_es.cfg
1398 icnova_sam9g45_sodimm.cfg topas910.cfg
1399 imx27ads.cfg topasa900.cfg
1400 imx27lnst.cfg twr-k60f120m.cfg
1401 imx28evk.cfg twr-k60n512.cfg
1402 imx31pdk.cfg tx25_stk5.cfg
1403 imx35pdk.cfg tx27_stk5.cfg
1404 imx53loco.cfg unknown_at91sam9260.cfg
1405 keil_mcb1700.cfg uptech_2410.cfg
1406 keil_mcb2140.cfg verdex.cfg
1407 kwikstik.cfg voipac.cfg
1408 linksys_nslu2.cfg voltcraft_dso-3062c.cfg
1409 lisa-l.cfg x300t.cfg
1410 logicpd_imx27.cfg zy1000.cfg
1411 $
1412 @end example
1413 @item @file{target} ...
1414 think chip. The ``target'' directory represents the JTAG TAPs
1415 on a chip
1416 which OpenOCD should control, not a board. Two common types of targets
1417 are ARM chips and FPGA or CPLD chips.
1418 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1419 the target config file defines all of them.
1420 @example
1421 $ ls target
1422 aduc702x.cfg lpc1763.cfg
1423 am335x.cfg lpc1764.cfg
1424 amdm37x.cfg lpc1765.cfg
1425 ar71xx.cfg lpc1766.cfg
1426 at32ap7000.cfg lpc1767.cfg
1427 at91r40008.cfg lpc1768.cfg
1428 at91rm9200.cfg lpc1769.cfg
1429 at91sam3ax_4x.cfg lpc1788.cfg
1430 at91sam3ax_8x.cfg lpc17xx.cfg
1431 at91sam3ax_xx.cfg lpc1850.cfg
1432 at91sam3nXX.cfg lpc2103.cfg
1433 at91sam3sXX.cfg lpc2124.cfg
1434 at91sam3u1c.cfg lpc2129.cfg
1435 at91sam3u1e.cfg lpc2148.cfg
1436 at91sam3u2c.cfg lpc2294.cfg
1437 at91sam3u2e.cfg lpc2378.cfg
1438 at91sam3u4c.cfg lpc2460.cfg
1439 at91sam3u4e.cfg lpc2478.cfg
1440 at91sam3uxx.cfg lpc2900.cfg
1441 at91sam3XXX.cfg lpc2xxx.cfg
1442 at91sam4sd32x.cfg lpc3131.cfg
1443 at91sam4sXX.cfg lpc3250.cfg
1444 at91sam4XXX.cfg lpc4350.cfg
1445 at91sam7se512.cfg lpc4350.cfg.orig
1446 at91sam7sx.cfg mc13224v.cfg
1447 at91sam7x256.cfg nuc910.cfg
1448 at91sam7x512.cfg omap2420.cfg
1449 at91sam9260.cfg omap3530.cfg
1450 at91sam9260_ext_RAM_ext_flash.cfg omap4430.cfg
1451 at91sam9261.cfg omap4460.cfg
1452 at91sam9263.cfg omap5912.cfg
1453 at91sam9.cfg omapl138.cfg
1454 at91sam9g10.cfg pic32mx.cfg
1455 at91sam9g20.cfg pxa255.cfg
1456 at91sam9g45.cfg pxa270.cfg
1457 at91sam9rl.cfg pxa3xx.cfg
1458 atmega128.cfg readme.txt
1459 avr32.cfg samsung_s3c2410.cfg
1460 c100.cfg samsung_s3c2440.cfg
1461 c100config.tcl samsung_s3c2450.cfg
1462 c100helper.tcl samsung_s3c4510.cfg
1463 c100regs.tcl samsung_s3c6410.cfg
1464 cs351x.cfg sharp_lh79532.cfg
1465 davinci.cfg smp8634.cfg
1466 dragonite.cfg spear3xx.cfg
1467 dsp56321.cfg stellaris.cfg
1468 dsp568013.cfg stellaris_icdi.cfg
1469 dsp568037.cfg stm32f0x_stlink.cfg
1470 efm32_stlink.cfg stm32f1x.cfg
1471 epc9301.cfg stm32f1x_stlink.cfg
1472 faux.cfg stm32f2x.cfg
1473 feroceon.cfg stm32f2x_stlink.cfg
1474 fm3.cfg stm32f3x.cfg
1475 hilscher_netx10.cfg stm32f3x_stlink.cfg
1476 hilscher_netx500.cfg stm32f4x.cfg
1477 hilscher_netx50.cfg stm32f4x_stlink.cfg
1478 icepick.cfg stm32l.cfg
1479 imx21.cfg stm32lx_dual_bank.cfg
1480 imx25.cfg stm32lx_stlink.cfg
1481 imx27.cfg stm32_stlink.cfg
1482 imx28.cfg stm32w108_stlink.cfg
1483 imx31.cfg stm32xl.cfg
1484 imx35.cfg str710.cfg
1485 imx51.cfg str730.cfg
1486 imx53.cfg str750.cfg
1487 imx6.cfg str912.cfg
1488 imx.cfg swj-dp.tcl
1489 is5114.cfg test_reset_syntax_error.cfg
1490 ixp42x.cfg test_syntax_error.cfg
1491 k40.cfg ti-ar7.cfg
1492 k60.cfg ti_calypso.cfg
1493 lpc1751.cfg ti_dm355.cfg
1494 lpc1752.cfg ti_dm365.cfg
1495 lpc1754.cfg ti_dm6446.cfg
1496 lpc1756.cfg tmpa900.cfg
1497 lpc1758.cfg tmpa910.cfg
1498 lpc1759.cfg u8500.cfg
1499 @end example
1500 @item @emph{more} ... browse for other library files which may be useful.
1501 For example, there are various generic and CPU-specific utilities.
1502 @end itemize
1503
1504 The @file{openocd.cfg} user config
1505 file may override features in any of the above files by
1506 setting variables before sourcing the target file, or by adding
1507 commands specific to their situation.
1508
1509 @section Interface Config Files
1510
1511 The user config file
1512 should be able to source one of these files with a command like this:
1513
1514 @example
1515 source [find interface/FOOBAR.cfg]
1516 @end example
1517
1518 A preconfigured interface file should exist for every debug adapter
1519 in use today with OpenOCD.
1520 That said, perhaps some of these config files
1521 have only been used by the developer who created it.
1522
1523 A separate chapter gives information about how to set these up.
1524 @xref{Debug Adapter Configuration}.
1525 Read the OpenOCD source code (and Developer's Guide)
1526 if you have a new kind of hardware interface
1527 and need to provide a driver for it.
1528
1529 @section Board Config Files
1530 @cindex config file, board
1531 @cindex board config file
1532
1533 The user config file
1534 should be able to source one of these files with a command like this:
1535
1536 @example
1537 source [find board/FOOBAR.cfg]
1538 @end example
1539
1540 The point of a board config file is to package everything
1541 about a given board that user config files need to know.
1542 In summary the board files should contain (if present)
1543
1544 @enumerate
1545 @item One or more @command{source [target/...cfg]} statements
1546 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1547 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1548 @item Target @code{reset} handlers for SDRAM and I/O configuration
1549 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1550 @item All things that are not ``inside a chip''
1551 @end enumerate
1552
1553 Generic things inside target chips belong in target config files,
1554 not board config files. So for example a @code{reset-init} event
1555 handler should know board-specific oscillator and PLL parameters,
1556 which it passes to target-specific utility code.
1557
1558 The most complex task of a board config file is creating such a
1559 @code{reset-init} event handler.
1560 Define those handlers last, after you verify the rest of the board
1561 configuration works.
1562
1563 @subsection Communication Between Config files
1564
1565 In addition to target-specific utility code, another way that
1566 board and target config files communicate is by following a
1567 convention on how to use certain variables.
1568
1569 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1570 Thus the rule we follow in OpenOCD is this: Variables that begin with
1571 a leading underscore are temporary in nature, and can be modified and
1572 used at will within a target configuration file.
1573
1574 Complex board config files can do the things like this,
1575 for a board with three chips:
1576
1577 @example
1578 # Chip #1: PXA270 for network side, big endian
1579 set CHIPNAME network
1580 set ENDIAN big
1581 source [find target/pxa270.cfg]
1582 # on return: _TARGETNAME = network.cpu
1583 # other commands can refer to the "network.cpu" target.
1584 $_TARGETNAME configure .... events for this CPU..
1585
1586 # Chip #2: PXA270 for video side, little endian
1587 set CHIPNAME video
1588 set ENDIAN little
1589 source [find target/pxa270.cfg]
1590 # on return: _TARGETNAME = video.cpu
1591 # other commands can refer to the "video.cpu" target.
1592 $_TARGETNAME configure .... events for this CPU..
1593
1594 # Chip #3: Xilinx FPGA for glue logic
1595 set CHIPNAME xilinx
1596 unset ENDIAN
1597 source [find target/spartan3.cfg]
1598 @end example
1599
1600 That example is oversimplified because it doesn't show any flash memory,
1601 or the @code{reset-init} event handlers to initialize external DRAM
1602 or (assuming it needs it) load a configuration into the FPGA.
1603 Such features are usually needed for low-level work with many boards,
1604 where ``low level'' implies that the board initialization software may
1605 not be working. (That's a common reason to need JTAG tools. Another
1606 is to enable working with microcontroller-based systems, which often
1607 have no debugging support except a JTAG connector.)
1608
1609 Target config files may also export utility functions to board and user
1610 config files. Such functions should use name prefixes, to help avoid
1611 naming collisions.
1612
1613 Board files could also accept input variables from user config files.
1614 For example, there might be a @code{J4_JUMPER} setting used to identify
1615 what kind of flash memory a development board is using, or how to set
1616 up other clocks and peripherals.
1617
1618 @subsection Variable Naming Convention
1619 @cindex variable names
1620
1621 Most boards have only one instance of a chip.
1622 However, it should be easy to create a board with more than
1623 one such chip (as shown above).
1624 Accordingly, we encourage these conventions for naming
1625 variables associated with different @file{target.cfg} files,
1626 to promote consistency and
1627 so that board files can override target defaults.
1628
1629 Inputs to target config files include:
1630
1631 @itemize @bullet
1632 @item @code{CHIPNAME} ...
1633 This gives a name to the overall chip, and is used as part of
1634 tap identifier dotted names.
1635 While the default is normally provided by the chip manufacturer,
1636 board files may need to distinguish between instances of a chip.
1637 @item @code{ENDIAN} ...
1638 By default @option{little} - although chips may hard-wire @option{big}.
1639 Chips that can't change endianness don't need to use this variable.
1640 @item @code{CPUTAPID} ...
1641 When OpenOCD examines the JTAG chain, it can be told verify the
1642 chips against the JTAG IDCODE register.
1643 The target file will hold one or more defaults, but sometimes the
1644 chip in a board will use a different ID (perhaps a newer revision).
1645 @end itemize
1646
1647 Outputs from target config files include:
1648
1649 @itemize @bullet
1650 @item @code{_TARGETNAME} ...
1651 By convention, this variable is created by the target configuration
1652 script. The board configuration file may make use of this variable to
1653 configure things like a ``reset init'' script, or other things
1654 specific to that board and that target.
1655 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1656 @code{_TARGETNAME1}, ... etc.
1657 @end itemize
1658
1659 @subsection The reset-init Event Handler
1660 @cindex event, reset-init
1661 @cindex reset-init handler
1662
1663 Board config files run in the OpenOCD configuration stage;
1664 they can't use TAPs or targets, since they haven't been
1665 fully set up yet.
1666 This means you can't write memory or access chip registers;
1667 you can't even verify that a flash chip is present.
1668 That's done later in event handlers, of which the target @code{reset-init}
1669 handler is one of the most important.
1670
1671 Except on microcontrollers, the basic job of @code{reset-init} event
1672 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1673 Microcontrollers rarely use boot loaders; they run right out of their
1674 on-chip flash and SRAM memory. But they may want to use one of these
1675 handlers too, if just for developer convenience.
1676
1677 @quotation Note
1678 Because this is so very board-specific, and chip-specific, no examples
1679 are included here.
1680 Instead, look at the board config files distributed with OpenOCD.
1681 If you have a boot loader, its source code will help; so will
1682 configuration files for other JTAG tools
1683 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1684 @end quotation
1685
1686 Some of this code could probably be shared between different boards.
1687 For example, setting up a DRAM controller often doesn't differ by
1688 much except the bus width (16 bits or 32?) and memory timings, so a
1689 reusable TCL procedure loaded by the @file{target.cfg} file might take
1690 those as parameters.
1691 Similarly with oscillator, PLL, and clock setup;
1692 and disabling the watchdog.
1693 Structure the code cleanly, and provide comments to help
1694 the next developer doing such work.
1695 (@emph{You might be that next person} trying to reuse init code!)
1696
1697 The last thing normally done in a @code{reset-init} handler is probing
1698 whatever flash memory was configured. For most chips that needs to be
1699 done while the associated target is halted, either because JTAG memory
1700 access uses the CPU or to prevent conflicting CPU access.
1701
1702 @subsection JTAG Clock Rate
1703
1704 Before your @code{reset-init} handler has set up
1705 the PLLs and clocking, you may need to run with
1706 a low JTAG clock rate.
1707 @xref{jtagspeed,,JTAG Speed}.
1708 Then you'd increase that rate after your handler has
1709 made it possible to use the faster JTAG clock.
1710 When the initial low speed is board-specific, for example
1711 because it depends on a board-specific oscillator speed, then
1712 you should probably set it up in the board config file;
1713 if it's target-specific, it belongs in the target config file.
1714
1715 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1716 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1717 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1718 Consult chip documentation to determine the peak JTAG clock rate,
1719 which might be less than that.
1720
1721 @quotation Warning
1722 On most ARMs, JTAG clock detection is coupled to the core clock, so
1723 software using a @option{wait for interrupt} operation blocks JTAG access.
1724 Adaptive clocking provides a partial workaround, but a more complete
1725 solution just avoids using that instruction with JTAG debuggers.
1726 @end quotation
1727
1728 If both the chip and the board support adaptive clocking,
1729 use the @command{jtag_rclk}
1730 command, in case your board is used with JTAG adapter which
1731 also supports it. Otherwise use @command{adapter_khz}.
1732 Set the slow rate at the beginning of the reset sequence,
1733 and the faster rate as soon as the clocks are at full speed.
1734
1735 @anchor{theinitboardprocedure}
1736 @subsection The init_board procedure
1737 @cindex init_board procedure
1738
1739 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1740 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1741 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1742 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1743 spearate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1744 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1745 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1746 Additionally ``linear'' board config file will most likely fail when target config file uses
1747 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1748 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1749 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1750 need to override @code{init_targets} defined in target config files when they only need to to add some specifics.
1751
1752 Just as @code{init_targets}, the @code{init_board} procedure can be overriden by ``next level'' script (which sources
1753 the original), allowing greater code reuse.
1754
1755 @example
1756 ### board_file.cfg ###
1757
1758 # source target file that does most of the config in init_targets
1759 source [find target/target.cfg]
1760
1761 proc enable_fast_clock @{@} @{
1762 # enables fast on-board clock source
1763 # configures the chip to use it
1764 @}
1765
1766 # initialize only board specifics - reset, clock, adapter frequency
1767 proc init_board @{@} @{
1768 reset_config trst_and_srst trst_pulls_srst
1769
1770 $_TARGETNAME configure -event reset-init @{
1771 adapter_khz 1
1772 enable_fast_clock
1773 adapter_khz 10000
1774 @}
1775 @}
1776 @end example
1777
1778 @section Target Config Files
1779 @cindex config file, target
1780 @cindex target config file
1781
1782 Board config files communicate with target config files using
1783 naming conventions as described above, and may source one or
1784 more target config files like this:
1785
1786 @example
1787 source [find target/FOOBAR.cfg]
1788 @end example
1789
1790 The point of a target config file is to package everything
1791 about a given chip that board config files need to know.
1792 In summary the target files should contain
1793
1794 @enumerate
1795 @item Set defaults
1796 @item Add TAPs to the scan chain
1797 @item Add CPU targets (includes GDB support)
1798 @item CPU/Chip/CPU-Core specific features
1799 @item On-Chip flash
1800 @end enumerate
1801
1802 As a rule of thumb, a target file sets up only one chip.
1803 For a microcontroller, that will often include a single TAP,
1804 which is a CPU needing a GDB target, and its on-chip flash.
1805
1806 More complex chips may include multiple TAPs, and the target
1807 config file may need to define them all before OpenOCD
1808 can talk to the chip.
1809 For example, some phone chips have JTAG scan chains that include
1810 an ARM core for operating system use, a DSP,
1811 another ARM core embedded in an image processing engine,
1812 and other processing engines.
1813
1814 @subsection Default Value Boiler Plate Code
1815
1816 All target configuration files should start with code like this,
1817 letting board config files express environment-specific
1818 differences in how things should be set up.
1819
1820 @example
1821 # Boards may override chip names, perhaps based on role,
1822 # but the default should match what the vendor uses
1823 if @{ [info exists CHIPNAME] @} @{
1824 set _CHIPNAME $CHIPNAME
1825 @} else @{
1826 set _CHIPNAME sam7x256
1827 @}
1828
1829 # ONLY use ENDIAN with targets that can change it.
1830 if @{ [info exists ENDIAN] @} @{
1831 set _ENDIAN $ENDIAN
1832 @} else @{
1833 set _ENDIAN little
1834 @}
1835
1836 # TAP identifiers may change as chips mature, for example with
1837 # new revision fields (the "3" here). Pick a good default; you
1838 # can pass several such identifiers to the "jtag newtap" command.
1839 if @{ [info exists CPUTAPID ] @} @{
1840 set _CPUTAPID $CPUTAPID
1841 @} else @{
1842 set _CPUTAPID 0x3f0f0f0f
1843 @}
1844 @end example
1845 @c but 0x3f0f0f0f is for an str73x part ...
1846
1847 @emph{Remember:} Board config files may include multiple target
1848 config files, or the same target file multiple times
1849 (changing at least @code{CHIPNAME}).
1850
1851 Likewise, the target configuration file should define
1852 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1853 use it later on when defining debug targets:
1854
1855 @example
1856 set _TARGETNAME $_CHIPNAME.cpu
1857 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1858 @end example
1859
1860 @subsection Adding TAPs to the Scan Chain
1861 After the ``defaults'' are set up,
1862 add the TAPs on each chip to the JTAG scan chain.
1863 @xref{TAP Declaration}, and the naming convention
1864 for taps.
1865
1866 In the simplest case the chip has only one TAP,
1867 probably for a CPU or FPGA.
1868 The config file for the Atmel AT91SAM7X256
1869 looks (in part) like this:
1870
1871 @example
1872 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1873 @end example
1874
1875 A board with two such at91sam7 chips would be able
1876 to source such a config file twice, with different
1877 values for @code{CHIPNAME}, so
1878 it adds a different TAP each time.
1879
1880 If there are nonzero @option{-expected-id} values,
1881 OpenOCD attempts to verify the actual tap id against those values.
1882 It will issue error messages if there is mismatch, which
1883 can help to pinpoint problems in OpenOCD configurations.
1884
1885 @example
1886 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1887 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1888 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1889 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1890 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1891 @end example
1892
1893 There are more complex examples too, with chips that have
1894 multiple TAPs. Ones worth looking at include:
1895
1896 @itemize
1897 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1898 plus a JRC to enable them
1899 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1900 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1901 is not currently used)
1902 @end itemize
1903
1904 @subsection Add CPU targets
1905
1906 After adding a TAP for a CPU, you should set it up so that
1907 GDB and other commands can use it.
1908 @xref{CPU Configuration}.
1909 For the at91sam7 example above, the command can look like this;
1910 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1911 to little endian, and this chip doesn't support changing that.
1912
1913 @example
1914 set _TARGETNAME $_CHIPNAME.cpu
1915 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1916 @end example
1917
1918 Work areas are small RAM areas associated with CPU targets.
1919 They are used by OpenOCD to speed up downloads,
1920 and to download small snippets of code to program flash chips.
1921 If the chip includes a form of ``on-chip-ram'' - and many do - define
1922 a work area if you can.
1923 Again using the at91sam7 as an example, this can look like:
1924
1925 @example
1926 $_TARGETNAME configure -work-area-phys 0x00200000 \
1927 -work-area-size 0x4000 -work-area-backup 0
1928 @end example
1929
1930 @anchor{definecputargetsworkinginsmp}
1931 @subsection Define CPU targets working in SMP
1932 @cindex SMP
1933 After setting targets, you can define a list of targets working in SMP.
1934
1935 @example
1936 set _TARGETNAME_1 $_CHIPNAME.cpu1
1937 set _TARGETNAME_2 $_CHIPNAME.cpu2
1938 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1939 -coreid 0 -dbgbase $_DAP_DBG1
1940 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1941 -coreid 1 -dbgbase $_DAP_DBG2
1942 #define 2 targets working in smp.
1943 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1944 @end example
1945 In the above example on cortex_a, 2 cpus are working in SMP.
1946 In SMP only one GDB instance is created and :
1947 @itemize @bullet
1948 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1949 @item halt command triggers the halt of all targets in the list.
1950 @item resume command triggers the write context and the restart of all targets in the list.
1951 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1952 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1953 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1954 @end itemize
1955
1956 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1957 command have been implemented.
1958 @itemize @bullet
1959 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1960 @item cortex_a smp_off : disable SMP mode, the current target is the one
1961 displayed in the GDB session, only this target is now controlled by GDB
1962 session. This behaviour is useful during system boot up.
1963 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1964 following example.
1965 @end itemize
1966
1967 @example
1968 >cortex_a smp_gdb
1969 gdb coreid 0 -> -1
1970 #0 : coreid 0 is displayed to GDB ,
1971 #-> -1 : next resume triggers a real resume
1972 > cortex_a smp_gdb 1
1973 gdb coreid 0 -> 1
1974 #0 :coreid 0 is displayed to GDB ,
1975 #->1 : next resume displays coreid 1 to GDB
1976 > resume
1977 > cortex_a smp_gdb
1978 gdb coreid 1 -> 1
1979 #1 :coreid 1 is displayed to GDB ,
1980 #->1 : next resume displays coreid 1 to GDB
1981 > cortex_a smp_gdb -1
1982 gdb coreid 1 -> -1
1983 #1 :coreid 1 is displayed to GDB,
1984 #->-1 : next resume triggers a real resume
1985 @end example
1986
1987
1988 @subsection Chip Reset Setup
1989
1990 As a rule, you should put the @command{reset_config} command
1991 into the board file. Most things you think you know about a
1992 chip can be tweaked by the board.
1993
1994 Some chips have specific ways the TRST and SRST signals are
1995 managed. In the unusual case that these are @emph{chip specific}
1996 and can never be changed by board wiring, they could go here.
1997 For example, some chips can't support JTAG debugging without
1998 both signals.
1999
2000 Provide a @code{reset-assert} event handler if you can.
2001 Such a handler uses JTAG operations to reset the target,
2002 letting this target config be used in systems which don't
2003 provide the optional SRST signal, or on systems where you
2004 don't want to reset all targets at once.
2005 Such a handler might write to chip registers to force a reset,
2006 use a JRC to do that (preferable -- the target may be wedged!),
2007 or force a watchdog timer to trigger.
2008 (For Cortex-M targets, this is not necessary. The target
2009 driver knows how to use trigger an NVIC reset when SRST is
2010 not available.)
2011
2012 Some chips need special attention during reset handling if
2013 they're going to be used with JTAG.
2014 An example might be needing to send some commands right
2015 after the target's TAP has been reset, providing a
2016 @code{reset-deassert-post} event handler that writes a chip
2017 register to report that JTAG debugging is being done.
2018 Another would be reconfiguring the watchdog so that it stops
2019 counting while the core is halted in the debugger.
2020
2021 JTAG clocking constraints often change during reset, and in
2022 some cases target config files (rather than board config files)
2023 are the right places to handle some of those issues.
2024 For example, immediately after reset most chips run using a
2025 slower clock than they will use later.
2026 That means that after reset (and potentially, as OpenOCD
2027 first starts up) they must use a slower JTAG clock rate
2028 than they will use later.
2029 @xref{jtagspeed,,JTAG Speed}.
2030
2031 @quotation Important
2032 When you are debugging code that runs right after chip
2033 reset, getting these issues right is critical.
2034 In particular, if you see intermittent failures when
2035 OpenOCD verifies the scan chain after reset,
2036 look at how you are setting up JTAG clocking.
2037 @end quotation
2038
2039 @anchor{theinittargetsprocedure}
2040 @subsection The init_targets procedure
2041 @cindex init_targets procedure
2042
2043 Target config files can either be ``linear'' (script executed line-by-line when parsed in
2044 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
2045 procedure called @code{init_targets}, which will be executed when entering run stage
2046 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
2047 Such procedure can be overriden by ``next level'' script (which sources the original).
2048 This concept faciliates code reuse when basic target config files provide generic configuration
2049 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
2050 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
2051 because sourcing them executes every initialization commands they provide.
2052
2053 @example
2054 ### generic_file.cfg ###
2055
2056 proc setup_my_chip @{chip_name flash_size ram_size@} @{
2057 # basic initialization procedure ...
2058 @}
2059
2060 proc init_targets @{@} @{
2061 # initializes generic chip with 4kB of flash and 1kB of RAM
2062 setup_my_chip MY_GENERIC_CHIP 4096 1024
2063 @}
2064
2065 ### specific_file.cfg ###
2066
2067 source [find target/generic_file.cfg]
2068
2069 proc init_targets @{@} @{
2070 # initializes specific chip with 128kB of flash and 64kB of RAM
2071 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
2072 @}
2073 @end example
2074
2075 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
2076 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
2077
2078 For an example of this scheme see LPC2000 target config files.
2079
2080 The @code{init_boards} procedure is a similar concept concerning board config files
2081 (@xref{theinitboardprocedure,,The init_board procedure}.)
2082
2083 @subsection ARM Core Specific Hacks
2084
2085 If the chip has a DCC, enable it. If the chip is an ARM9 with some
2086 special high speed download features - enable it.
2087
2088 If present, the MMU, the MPU and the CACHE should be disabled.
2089
2090 Some ARM cores are equipped with trace support, which permits
2091 examination of the instruction and data bus activity. Trace
2092 activity is controlled through an ``Embedded Trace Module'' (ETM)
2093 on one of the core's scan chains. The ETM emits voluminous data
2094 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
2095 If you are using an external trace port,
2096 configure it in your board config file.
2097 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2098 configure it in your target config file.
2099
2100 @example
2101 etm config $_TARGETNAME 16 normal full etb
2102 etb config $_TARGETNAME $_CHIPNAME.etb
2103 @end example
2104
2105 @subsection Internal Flash Configuration
2106
2107 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2108
2109 @b{Never ever} in the ``target configuration file'' define any type of
2110 flash that is external to the chip. (For example a BOOT flash on
2111 Chip Select 0.) Such flash information goes in a board file - not
2112 the TARGET (chip) file.
2113
2114 Examples:
2115 @itemize @bullet
2116 @item at91sam7x256 - has 256K flash YES enable it.
2117 @item str912 - has flash internal YES enable it.
2118 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2119 @item pxa270 - again - CS0 flash - it goes in the board file.
2120 @end itemize
2121
2122 @anchor{translatingconfigurationfiles}
2123 @section Translating Configuration Files
2124 @cindex translation
2125 If you have a configuration file for another hardware debugger
2126 or toolset (Abatron, BDI2000, BDI3000, CCS,
2127 Lauterbach, Segger, Macraigor, etc.), translating
2128 it into OpenOCD syntax is often quite straightforward. The most tricky
2129 part of creating a configuration script is oftentimes the reset init
2130 sequence where e.g. PLLs, DRAM and the like is set up.
2131
2132 One trick that you can use when translating is to write small
2133 Tcl procedures to translate the syntax into OpenOCD syntax. This
2134 can avoid manual translation errors and make it easier to
2135 convert other scripts later on.
2136
2137 Example of transforming quirky arguments to a simple search and
2138 replace job:
2139
2140 @example
2141 # Lauterbach syntax(?)
2142 #
2143 # Data.Set c15:0x042f %long 0x40000015
2144 #
2145 # OpenOCD syntax when using procedure below.
2146 #
2147 # setc15 0x01 0x00050078
2148
2149 proc setc15 @{regs value@} @{
2150 global TARGETNAME
2151
2152 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2153
2154 arm mcr 15 [expr ($regs>>12)&0x7] \
2155 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2156 [expr ($regs>>8)&0x7] $value
2157 @}
2158 @end example
2159
2160
2161
2162 @node Daemon Configuration
2163 @chapter Daemon Configuration
2164 @cindex initialization
2165 The commands here are commonly found in the openocd.cfg file and are
2166 used to specify what TCP/IP ports are used, and how GDB should be
2167 supported.
2168
2169 @anchor{configurationstage}
2170 @section Configuration Stage
2171 @cindex configuration stage
2172 @cindex config command
2173
2174 When the OpenOCD server process starts up, it enters a
2175 @emph{configuration stage} which is the only time that
2176 certain commands, @emph{configuration commands}, may be issued.
2177 Normally, configuration commands are only available
2178 inside startup scripts.
2179
2180 In this manual, the definition of a configuration command is
2181 presented as a @emph{Config Command}, not as a @emph{Command}
2182 which may be issued interactively.
2183 The runtime @command{help} command also highlights configuration
2184 commands, and those which may be issued at any time.
2185
2186 Those configuration commands include declaration of TAPs,
2187 flash banks,
2188 the interface used for JTAG communication,
2189 and other basic setup.
2190 The server must leave the configuration stage before it
2191 may access or activate TAPs.
2192 After it leaves this stage, configuration commands may no
2193 longer be issued.
2194
2195 @anchor{enteringtherunstage}
2196 @section Entering the Run Stage
2197
2198 The first thing OpenOCD does after leaving the configuration
2199 stage is to verify that it can talk to the scan chain
2200 (list of TAPs) which has been configured.
2201 It will warn if it doesn't find TAPs it expects to find,
2202 or finds TAPs that aren't supposed to be there.
2203 You should see no errors at this point.
2204 If you see errors, resolve them by correcting the
2205 commands you used to configure the server.
2206 Common errors include using an initial JTAG speed that's too
2207 fast, and not providing the right IDCODE values for the TAPs
2208 on the scan chain.
2209
2210 Once OpenOCD has entered the run stage, a number of commands
2211 become available.
2212 A number of these relate to the debug targets you may have declared.
2213 For example, the @command{mww} command will not be available until
2214 a target has been successfuly instantiated.
2215 If you want to use those commands, you may need to force
2216 entry to the run stage.
2217
2218 @deffn {Config Command} init
2219 This command terminates the configuration stage and
2220 enters the run stage. This helps when you need to have
2221 the startup scripts manage tasks such as resetting the target,
2222 programming flash, etc. To reset the CPU upon startup, add "init" and
2223 "reset" at the end of the config script or at the end of the OpenOCD
2224 command line using the @option{-c} command line switch.
2225
2226 If this command does not appear in any startup/configuration file
2227 OpenOCD executes the command for you after processing all
2228 configuration files and/or command line options.
2229
2230 @b{NOTE:} This command normally occurs at or near the end of your
2231 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2232 targets ready. For example: If your openocd.cfg file needs to
2233 read/write memory on your target, @command{init} must occur before
2234 the memory read/write commands. This includes @command{nand probe}.
2235 @end deffn
2236
2237 @deffn {Overridable Procedure} jtag_init
2238 This is invoked at server startup to verify that it can talk
2239 to the scan chain (list of TAPs) which has been configured.
2240
2241 The default implementation first tries @command{jtag arp_init},
2242 which uses only a lightweight JTAG reset before examining the
2243 scan chain.
2244 If that fails, it tries again, using a harder reset
2245 from the overridable procedure @command{init_reset}.
2246
2247 Implementations must have verified the JTAG scan chain before
2248 they return.
2249 This is done by calling @command{jtag arp_init}
2250 (or @command{jtag arp_init-reset}).
2251 @end deffn
2252
2253 @anchor{tcpipports}
2254 @section TCP/IP Ports
2255 @cindex TCP port
2256 @cindex server
2257 @cindex port
2258 @cindex security
2259 The OpenOCD server accepts remote commands in several syntaxes.
2260 Each syntax uses a different TCP/IP port, which you may specify
2261 only during configuration (before those ports are opened).
2262
2263 For reasons including security, you may wish to prevent remote
2264 access using one or more of these ports.
2265 In such cases, just specify the relevant port number as zero.
2266 If you disable all access through TCP/IP, you will need to
2267 use the command line @option{-pipe} option.
2268
2269 @deffn {Command} gdb_port [number]
2270 @cindex GDB server
2271 Normally gdb listens to a TCP/IP port, but GDB can also
2272 communicate via pipes(stdin/out or named pipes). The name
2273 "gdb_port" stuck because it covers probably more than 90% of
2274 the normal use cases.
2275
2276 No arguments reports GDB port. "pipe" means listen to stdin
2277 output to stdout, an integer is base port number, "disable"
2278 disables the gdb server.
2279
2280 When using "pipe", also use log_output to redirect the log
2281 output to a file so as not to flood the stdin/out pipes.
2282
2283 The -p/--pipe option is deprecated and a warning is printed
2284 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2285
2286 Any other string is interpreted as named pipe to listen to.
2287 Output pipe is the same name as input pipe, but with 'o' appended,
2288 e.g. /var/gdb, /var/gdbo.
2289
2290 The GDB port for the first target will be the base port, the
2291 second target will listen on gdb_port + 1, and so on.
2292 When not specified during the configuration stage,
2293 the port @var{number} defaults to 3333.
2294 @end deffn
2295
2296 @deffn {Command} tcl_port [number]
2297 Specify or query the port used for a simplified RPC
2298 connection that can be used by clients to issue TCL commands and get the
2299 output from the Tcl engine.
2300 Intended as a machine interface.
2301 When not specified during the configuration stage,
2302 the port @var{number} defaults to 6666.
2303
2304 @end deffn
2305
2306 @deffn {Command} telnet_port [number]
2307 Specify or query the
2308 port on which to listen for incoming telnet connections.
2309 This port is intended for interaction with one human through TCL commands.
2310 When not specified during the configuration stage,
2311 the port @var{number} defaults to 4444.
2312 When specified as zero, this port is not activated.
2313 @end deffn
2314
2315 @anchor{gdbconfiguration}
2316 @section GDB Configuration
2317 @cindex GDB
2318 @cindex GDB configuration
2319 You can reconfigure some GDB behaviors if needed.
2320 The ones listed here are static and global.
2321 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2322 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2323
2324 @anchor{gdbbreakpointoverride}
2325 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2326 Force breakpoint type for gdb @command{break} commands.
2327 This option supports GDB GUIs which don't
2328 distinguish hard versus soft breakpoints, if the default OpenOCD and
2329 GDB behaviour is not sufficient. GDB normally uses hardware
2330 breakpoints if the memory map has been set up for flash regions.
2331 @end deffn
2332
2333 @anchor{gdbflashprogram}
2334 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2335 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2336 vFlash packet is received.
2337 The default behaviour is @option{enable}.
2338 @end deffn
2339
2340 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2341 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2342 requested. GDB will then know when to set hardware breakpoints, and program flash
2343 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2344 for flash programming to work.
2345 Default behaviour is @option{enable}.
2346 @xref{gdbflashprogram,,gdb_flash_program}.
2347 @end deffn
2348
2349 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2350 Specifies whether data aborts cause an error to be reported
2351 by GDB memory read packets.
2352 The default behaviour is @option{disable};
2353 use @option{enable} see these errors reported.
2354 @end deffn
2355
2356 @anchor{eventpolling}
2357 @section Event Polling
2358
2359 Hardware debuggers are parts of asynchronous systems,
2360 where significant events can happen at any time.
2361 The OpenOCD server needs to detect some of these events,
2362 so it can report them to through TCL command line
2363 or to GDB.
2364
2365 Examples of such events include:
2366
2367 @itemize
2368 @item One of the targets can stop running ... maybe it triggers
2369 a code breakpoint or data watchpoint, or halts itself.
2370 @item Messages may be sent over ``debug message'' channels ... many
2371 targets support such messages sent over JTAG,
2372 for receipt by the person debugging or tools.
2373 @item Loss of power ... some adapters can detect these events.
2374 @item Resets not issued through JTAG ... such reset sources
2375 can include button presses or other system hardware, sometimes
2376 including the target itself (perhaps through a watchdog).
2377 @item Debug instrumentation sometimes supports event triggering
2378 such as ``trace buffer full'' (so it can quickly be emptied)
2379 or other signals (to correlate with code behavior).
2380 @end itemize
2381
2382 None of those events are signaled through standard JTAG signals.
2383 However, most conventions for JTAG connectors include voltage
2384 level and system reset (SRST) signal detection.
2385 Some connectors also include instrumentation signals, which
2386 can imply events when those signals are inputs.
2387
2388 In general, OpenOCD needs to periodically check for those events,
2389 either by looking at the status of signals on the JTAG connector
2390 or by sending synchronous ``tell me your status'' JTAG requests
2391 to the various active targets.
2392 There is a command to manage and monitor that polling,
2393 which is normally done in the background.
2394
2395 @deffn Command poll [@option{on}|@option{off}]
2396 Poll the current target for its current state.
2397 (Also, @pxref{targetcurstate,,target curstate}.)
2398 If that target is in debug mode, architecture
2399 specific information about the current state is printed.
2400 An optional parameter
2401 allows background polling to be enabled and disabled.
2402
2403 You could use this from the TCL command shell, or
2404 from GDB using @command{monitor poll} command.
2405 Leave background polling enabled while you're using GDB.
2406 @example
2407 > poll
2408 background polling: on
2409 target state: halted
2410 target halted in ARM state due to debug-request, \
2411 current mode: Supervisor
2412 cpsr: 0x800000d3 pc: 0x11081bfc
2413 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2414 >
2415 @end example
2416 @end deffn
2417
2418 @node Debug Adapter Configuration
2419 @chapter Debug Adapter Configuration
2420 @cindex config file, interface
2421 @cindex interface config file
2422
2423 Correctly installing OpenOCD includes making your operating system give
2424 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2425 are used to select which one is used, and to configure how it is used.
2426
2427 @quotation Note
2428 Because OpenOCD started out with a focus purely on JTAG, you may find
2429 places where it wrongly presumes JTAG is the only transport protocol
2430 in use. Be aware that recent versions of OpenOCD are removing that
2431 limitation. JTAG remains more functional than most other transports.
2432 Other transports do not support boundary scan operations, or may be
2433 specific to a given chip vendor. Some might be usable only for
2434 programming flash memory, instead of also for debugging.
2435 @end quotation
2436
2437 Debug Adapters/Interfaces/Dongles are normally configured
2438 through commands in an interface configuration
2439 file which is sourced by your @file{openocd.cfg} file, or
2440 through a command line @option{-f interface/....cfg} option.
2441
2442 @example
2443 source [find interface/olimex-jtag-tiny.cfg]
2444 @end example
2445
2446 These commands tell
2447 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2448 A few cases are so simple that you only need to say what driver to use:
2449
2450 @example
2451 # jlink interface
2452 interface jlink
2453 @end example
2454
2455 Most adapters need a bit more configuration than that.
2456
2457
2458 @section Interface Configuration
2459
2460 The interface command tells OpenOCD what type of debug adapter you are
2461 using. Depending on the type of adapter, you may need to use one or
2462 more additional commands to further identify or configure the adapter.
2463
2464 @deffn {Config Command} {interface} name
2465 Use the interface driver @var{name} to connect to the
2466 target.
2467 @end deffn
2468
2469 @deffn Command {interface_list}
2470 List the debug adapter drivers that have been built into
2471 the running copy of OpenOCD.
2472 @end deffn
2473 @deffn Command {interface transports} transport_name+
2474 Specifies the transports supported by this debug adapter.
2475 The adapter driver builds-in similar knowledge; use this only
2476 when external configuration (such as jumpering) changes what
2477 the hardware can support.
2478 @end deffn
2479
2480
2481
2482 @deffn Command {adapter_name}
2483 Returns the name of the debug adapter driver being used.
2484 @end deffn
2485
2486 @section Interface Drivers
2487
2488 Each of the interface drivers listed here must be explicitly
2489 enabled when OpenOCD is configured, in order to be made
2490 available at run time.
2491
2492 @deffn {Interface Driver} {amt_jtagaccel}
2493 Amontec Chameleon in its JTAG Accelerator configuration,
2494 connected to a PC's EPP mode parallel port.
2495 This defines some driver-specific commands:
2496
2497 @deffn {Config Command} {parport_port} number
2498 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2499 the number of the @file{/dev/parport} device.
2500 @end deffn
2501
2502 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2503 Displays status of RTCK option.
2504 Optionally sets that option first.
2505 @end deffn
2506 @end deffn
2507
2508 @deffn {Interface Driver} {arm-jtag-ew}
2509 Olimex ARM-JTAG-EW USB adapter
2510 This has one driver-specific command:
2511
2512 @deffn Command {armjtagew_info}
2513 Logs some status
2514 @end deffn
2515 @end deffn
2516
2517 @deffn {Interface Driver} {at91rm9200}
2518 Supports bitbanged JTAG from the local system,
2519 presuming that system is an Atmel AT91rm9200
2520 and a specific set of GPIOs is used.
2521 @c command: at91rm9200_device NAME
2522 @c chooses among list of bit configs ... only one option
2523 @end deffn
2524
2525 @deffn {Interface Driver} {dummy}
2526 A dummy software-only driver for debugging.
2527 @end deffn
2528
2529 @deffn {Interface Driver} {ep93xx}
2530 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2531 @end deffn
2532
2533 @deffn {Interface Driver} {ft2232}
2534 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2535
2536 Note that this driver has several flaws and the @command{ftdi} driver is
2537 recommended as its replacement.
2538
2539 These interfaces have several commands, used to configure the driver
2540 before initializing the JTAG scan chain:
2541
2542 @deffn {Config Command} {ft2232_device_desc} description
2543 Provides the USB device description (the @emph{iProduct string})
2544 of the FTDI FT2232 device. If not
2545 specified, the FTDI default value is used. This setting is only valid
2546 if compiled with FTD2XX support.
2547 @end deffn
2548
2549 @deffn {Config Command} {ft2232_serial} serial-number
2550 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2551 in case the vendor provides unique IDs and more than one FT2232 device
2552 is connected to the host.
2553 If not specified, serial numbers are not considered.
2554 (Note that USB serial numbers can be arbitrary Unicode strings,
2555 and are not restricted to containing only decimal digits.)
2556 @end deffn
2557
2558 @deffn {Config Command} {ft2232_layout} name
2559 Each vendor's FT2232 device can use different GPIO signals
2560 to control output-enables, reset signals, and LEDs.
2561 Currently valid layout @var{name} values include:
2562 @itemize @minus
2563 @item @b{axm0432_jtag} Axiom AXM-0432
2564 @item @b{comstick} Hitex STR9 comstick
2565 @item @b{cortino} Hitex Cortino JTAG interface
2566 @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
2567 either for the local Cortex-M3 (SRST only)
2568 or in a passthrough mode (neither SRST nor TRST)
2569 This layout can not support the SWO trace mechanism, and should be
2570 used only for older boards (before rev C).
2571 @item @b{luminary_icdi} This layout should be used with most TI/Luminary
2572 eval boards, including Rev C LM3S811 eval boards and the eponymous
2573 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2574 to debug some other target. It can support the SWO trace mechanism.
2575 @item @b{flyswatter} Tin Can Tools Flyswatter
2576 @item @b{icebear} ICEbear JTAG adapter from Section 5
2577 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2578 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2579 @item @b{m5960} American Microsystems M5960
2580 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2581 @item @b{oocdlink} OOCDLink
2582 @c oocdlink ~= jtagkey_prototype_v1
2583 @item @b{redbee-econotag} Integrated with a Redbee development board.
2584 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2585 @item @b{sheevaplug} Marvell Sheevaplug development kit
2586 @item @b{signalyzer} Xverve Signalyzer
2587 @item @b{stm32stick} Hitex STM32 Performance Stick
2588 @item @b{turtelizer2} egnite Software turtelizer2
2589 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2590 @end itemize
2591 @end deffn
2592
2593 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2594 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2595 default values are used.
2596 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2597 @example
2598 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2599 @end example
2600 @end deffn
2601
2602 @deffn {Config Command} {ft2232_latency} ms
2603 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2604 ft2232_read() fails to return the expected number of bytes. This can be caused by
2605 USB communication delays and has proved hard to reproduce and debug. Setting the
2606 FT2232 latency timer to a larger value increases delays for short USB packets but it
2607 also reduces the risk of timeouts before receiving the expected number of bytes.
2608 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2609 @end deffn
2610
2611 @deffn {Config Command} {ft2232_channel} channel
2612 Used to select the channel of the ft2232 chip to use (between 1 and 4).
2613 The default value is 1.
2614 @end deffn
2615
2616 For example, the interface config file for a
2617 Turtelizer JTAG Adapter looks something like this:
2618
2619 @example
2620 interface ft2232
2621 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2622 ft2232_layout turtelizer2
2623 ft2232_vid_pid 0x0403 0xbdc8
2624 @end example
2625 @end deffn
2626
2627 @deffn {Interface Driver} {ftdi}
2628 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2629 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2630 It is a complete rewrite to address a large number of problems with the ft2232
2631 interface driver.
2632
2633 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2634 bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
2635 consistently faster than the ft2232 driver, sometimes several times faster.
2636
2637 A major improvement of this driver is that support for new FTDI based adapters
2638 can be added competely through configuration files, without the need to patch
2639 and rebuild OpenOCD.
2640
2641 The driver uses a signal abstraction to enable Tcl configuration files to
2642 define outputs for one or several FTDI GPIO. These outputs can then be
2643 controlled using the @command{ftdi_set_signal} command. Special signal names
2644 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2645 will be used for their customary purpose.
2646
2647 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2648 be controlled differently. In order to support tristateable signals such as
2649 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2650 signal. The following output buffer configurations are supported:
2651
2652 @itemize @minus
2653 @item Push-pull with one FTDI output as (non-)inverted data line
2654 @item Open drain with one FTDI output as (non-)inverted output-enable
2655 @item Tristate with one FTDI output as (non-)inverted data line and another
2656 FTDI output as (non-)inverted output-enable
2657 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2658 switching data and direction as necessary
2659 @end itemize
2660
2661 These interfaces have several commands, used to configure the driver
2662 before initializing the JTAG scan chain:
2663
2664 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2665 The vendor ID and product ID of the adapter. If not specified, the FTDI
2666 default values are used.
2667 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2668 @example
2669 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2670 @end example
2671 @end deffn
2672
2673 @deffn {Config Command} {ftdi_device_desc} description
2674 Provides the USB device description (the @emph{iProduct string})
2675 of the adapter. If not specified, the device description is ignored
2676 during device selection.
2677 @end deffn
2678
2679 @deffn {Config Command} {ftdi_serial} serial-number
2680 Specifies the @var{serial-number} of the adapter to use,
2681 in case the vendor provides unique IDs and more than one adapter
2682 is connected to the host.
2683 If not specified, serial numbers are not considered.
2684 (Note that USB serial numbers can be arbitrary Unicode strings,
2685 and are not restricted to containing only decimal digits.)
2686 @end deffn
2687
2688 @deffn {Config Command} {ftdi_channel} channel
2689 Selects the channel of the FTDI device to use for MPSSE operations. Most
2690 adapters use the default, channel 0, but there are exceptions.
2691 @end deffn
2692
2693 @deffn {Config Command} {ftdi_layout_init} data direction
2694 Specifies the initial values of the FTDI GPIO data and direction registers.
2695 Each value is a 16-bit number corresponding to the concatenation of the high
2696 and low FTDI GPIO registers. The values should be selected based on the
2697 schematics of the adapter, such that all signals are set to safe levels with
2698 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2699 and initially asserted reset signals.
2700 @end deffn
2701
2702 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask]
2703 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2704 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2705 register bitmasks to tell the driver the connection and type of the output
2706 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2707 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2708 used with inverting data inputs and @option{-data} with non-inverting inputs.
2709 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2710 not-output-enable) input to the output buffer is connected.
2711
2712 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2713 simple open-collector transistor driver would be specified with @option{-oe}
2714 only. In that case the signal can only be set to drive low or to Hi-Z and the
2715 driver will complain if the signal is set to drive high. Which means that if
2716 it's a reset signal, @command{reset_config} must be specified as
2717 @option{srst_open_drain}, not @option{srst_push_pull}.
2718
2719 A special case is provided when @option{-data} and @option{-oe} is set to the
2720 same bitmask. Then the FTDI pin is considered being connected straight to the
2721 target without any buffer. The FTDI pin is then switched between output and
2722 input as necessary to provide the full set of low, high and Hi-Z
2723 characteristics. In all other cases, the pins specified in a signal definition
2724 are always driven by the FTDI.
2725 @end deffn
2726
2727 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2728 Set a previously defined signal to the specified level.
2729 @itemize @minus
2730 @item @option{0}, drive low
2731 @item @option{1}, drive high
2732 @item @option{z}, set to high-impedance
2733 @end itemize
2734 @end deffn
2735
2736 For example adapter definitions, see the configuration files shipped in the
2737 @file{interface/ftdi} directory.
2738 @end deffn
2739
2740 @deffn {Interface Driver} {remote_bitbang}
2741 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2742 with a remote process and sends ASCII encoded bitbang requests to that process
2743 instead of directly driving JTAG.
2744
2745 The remote_bitbang driver is useful for debugging software running on
2746 processors which are being simulated.
2747
2748 @deffn {Config Command} {remote_bitbang_port} number
2749 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2750 sockets instead of TCP.
2751 @end deffn
2752
2753 @deffn {Config Command} {remote_bitbang_host} hostname
2754 Specifies the hostname of the remote process to connect to using TCP, or the
2755 name of the UNIX socket to use if remote_bitbang_port is 0.
2756 @end deffn
2757
2758 For example, to connect remotely via TCP to the host foobar you might have
2759 something like:
2760
2761 @example
2762 interface remote_bitbang
2763 remote_bitbang_port 3335
2764 remote_bitbang_host foobar
2765 @end example
2766
2767 To connect to another process running locally via UNIX sockets with socket
2768 named mysocket:
2769
2770 @example
2771 interface remote_bitbang
2772 remote_bitbang_port 0
2773 remote_bitbang_host mysocket
2774 @end example
2775 @end deffn
2776
2777 @deffn {Interface Driver} {usb_blaster}
2778 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2779 for FTDI chips. These interfaces have several commands, used to
2780 configure the driver before initializing the JTAG scan chain:
2781
2782 @deffn {Config Command} {usb_blaster_device_desc} description
2783 Provides the USB device description (the @emph{iProduct string})
2784 of the FTDI FT245 device. If not
2785 specified, the FTDI default value is used. This setting is only valid
2786 if compiled with FTD2XX support.
2787 @end deffn
2788
2789 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2790 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2791 default values are used.
2792 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2793 Altera USB-Blaster (default):
2794 @example
2795 usb_blaster_vid_pid 0x09FB 0x6001
2796 @end example
2797 The following VID/PID is for Kolja Waschk's USB JTAG:
2798 @example
2799 usb_blaster_vid_pid 0x16C0 0x06AD
2800 @end example
2801 @end deffn
2802
2803 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2804 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2805 female JTAG header). These pins can be used as SRST and/or TRST provided the
2806 appropriate connections are made on the target board.
2807
2808 For example, to use pin 6 as SRST (as with an AVR board):
2809 @example
2810 $_TARGETNAME configure -event reset-assert \
2811 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2812 @end example
2813 @end deffn
2814
2815 @end deffn
2816
2817 @deffn {Interface Driver} {gw16012}
2818 Gateworks GW16012 JTAG programmer.
2819 This has one driver-specific command:
2820
2821 @deffn {Config Command} {parport_port} [port_number]
2822 Display either the address of the I/O port
2823 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2824 If a parameter is provided, first switch to use that port.
2825 This is a write-once setting.
2826 @end deffn
2827 @end deffn
2828
2829 @deffn {Interface Driver} {jlink}
2830 Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
2831
2832 @quotation Compatibility Note
2833 Segger released many firmware versions for the many harware versions they
2834 produced. OpenOCD was extensively tested and intended to run on all of them,
2835 but some combinations were reported as incompatible. As a general
2836 recommendation, it is advisable to use the latest firmware version
2837 available for each hardware version. However the current V8 is a moving
2838 target, and Segger firmware versions released after the OpenOCD was
2839 released may not be compatible. In such cases it is recommended to
2840 revert to the last known functional version. For 0.5.0, this is from
2841 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2842 version is from "May 3 2012 18:36:22", packed with 4.46f.
2843 @end quotation
2844
2845 @deffn {Command} {jlink caps}
2846 Display the device firmware capabilities.
2847 @end deffn
2848 @deffn {Command} {jlink info}
2849 Display various device information, like hardware version, firmware version, current bus status.
2850 @end deffn
2851 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2852 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2853 @end deffn
2854 @deffn {Command} {jlink config}
2855 Display the J-Link configuration.
2856 @end deffn
2857 @deffn {Command} {jlink config kickstart} [val]
2858 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2859 @end deffn
2860 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2861 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2862 @end deffn
2863 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2864 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2865 E the bit of the subnet mask and
2866 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2867 @end deffn
2868 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2869 Set the USB address; this will also change the product id. Without argument, show the USB address.
2870 @end deffn
2871 @deffn {Command} {jlink config reset}
2872 Reset the current configuration.
2873 @end deffn
2874 @deffn {Command} {jlink config save}
2875 Save the current configuration to the internal persistent storage.
2876 @end deffn
2877 @deffn {Config} {jlink pid} val
2878 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2879 @end deffn
2880 @end deffn
2881
2882 @deffn {Interface Driver} {parport}
2883 Supports PC parallel port bit-banging cables:
2884 Wigglers, PLD download cable, and more.
2885 These interfaces have several commands, used to configure the driver
2886 before initializing the JTAG scan chain:
2887
2888 @deffn {Config Command} {parport_cable} name
2889 Set the layout of the parallel port cable used to connect to the target.
2890 This is a write-once setting.
2891 Currently valid cable @var{name} values include:
2892
2893 @itemize @minus
2894 @item @b{altium} Altium Universal JTAG cable.
2895 @item @b{arm-jtag} Same as original wiggler except SRST and
2896 TRST connections reversed and TRST is also inverted.
2897 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2898 in configuration mode. This is only used to
2899 program the Chameleon itself, not a connected target.
2900 @item @b{dlc5} The Xilinx Parallel cable III.
2901 @item @b{flashlink} The ST Parallel cable.
2902 @item @b{lattice} Lattice ispDOWNLOAD Cable
2903 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2904 some versions of
2905 Amontec's Chameleon Programmer. The new version available from
2906 the website uses the original Wiggler layout ('@var{wiggler}')
2907 @item @b{triton} The parallel port adapter found on the
2908 ``Karo Triton 1 Development Board''.
2909 This is also the layout used by the HollyGates design
2910 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2911 @item @b{wiggler} The original Wiggler layout, also supported by
2912 several clones, such as the Olimex ARM-JTAG
2913 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2914 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2915 @end itemize
2916 @end deffn
2917
2918 @deffn {Config Command} {parport_port} [port_number]
2919 Display either the address of the I/O port
2920 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2921 If a parameter is provided, first switch to use that port.
2922 This is a write-once setting.
2923
2924 When using PPDEV to access the parallel port, use the number of the parallel port:
2925 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2926 you may encounter a problem.
2927 @end deffn
2928
2929 @deffn Command {parport_toggling_time} [nanoseconds]
2930 Displays how many nanoseconds the hardware needs to toggle TCK;
2931 the parport driver uses this value to obey the
2932 @command{adapter_khz} configuration.
2933 When the optional @var{nanoseconds} parameter is given,
2934 that setting is changed before displaying the current value.
2935
2936 The default setting should work reasonably well on commodity PC hardware.
2937 However, you may want to calibrate for your specific hardware.
2938 @quotation Tip
2939 To measure the toggling time with a logic analyzer or a digital storage
2940 oscilloscope, follow the procedure below:
2941 @example
2942 > parport_toggling_time 1000
2943 > adapter_khz 500
2944 @end example
2945 This sets the maximum JTAG clock speed of the hardware, but
2946 the actual speed probably deviates from the requested 500 kHz.
2947 Now, measure the time between the two closest spaced TCK transitions.
2948 You can use @command{runtest 1000} or something similar to generate a
2949 large set of samples.
2950 Update the setting to match your measurement:
2951 @example
2952 > parport_toggling_time <measured nanoseconds>
2953 @end example
2954 Now the clock speed will be a better match for @command{adapter_khz rate}
2955 commands given in OpenOCD scripts and event handlers.
2956
2957 You can do something similar with many digital multimeters, but note
2958 that you'll probably need to run the clock continuously for several
2959 seconds before it decides what clock rate to show. Adjust the
2960 toggling time up or down until the measured clock rate is a good
2961 match for the adapter_khz rate you specified; be conservative.
2962 @end quotation
2963 @end deffn
2964
2965 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2966 This will configure the parallel driver to write a known
2967 cable-specific value to the parallel interface on exiting OpenOCD.
2968 @end deffn
2969
2970 For example, the interface configuration file for a
2971 classic ``Wiggler'' cable on LPT2 might look something like this:
2972
2973 @example
2974 interface parport
2975 parport_port 0x278
2976 parport_cable wiggler
2977 @end example
2978 @end deffn
2979
2980 @deffn {Interface Driver} {presto}
2981 ASIX PRESTO USB JTAG programmer.
2982 @deffn {Config Command} {presto_serial} serial_string
2983 Configures the USB serial number of the Presto device to use.
2984 @end deffn
2985 @end deffn
2986
2987 @deffn {Interface Driver} {rlink}
2988 Raisonance RLink USB adapter
2989 @end deffn
2990
2991 @deffn {Interface Driver} {usbprog}
2992 usbprog is a freely programmable USB adapter.
2993 @end deffn
2994
2995 @deffn {Interface Driver} {vsllink}
2996 vsllink is part of Versaloon which is a versatile USB programmer.
2997
2998 @quotation Note
2999 This defines quite a few driver-specific commands,
3000 which are not currently documented here.
3001 @end quotation
3002 @end deffn
3003
3004 @deffn {Interface Driver} {hla}
3005 This is a driver that supports multiple High Level Adapters.
3006 This type of adapter does not expose some of the lower level api's
3007 that OpenOCD would normally use to access the target.
3008
3009 Currently supported adapters include the ST STLINK and TI ICDI.
3010
3011 @deffn {Config Command} {hla_device_desc} description
3012 Currently Not Supported.
3013 @end deffn
3014
3015 @deffn {Config Command} {hla_serial} serial
3016 Currently Not Supported.
3017 @end deffn
3018
3019 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
3020 Specifies the adapter layout to use.
3021 @end deffn
3022
3023 @deffn {Config Command} {hla_vid_pid} vid pid
3024 The vendor ID and product ID of the device.
3025 @end deffn
3026
3027 @deffn {Config Command} {stlink_api} api_level
3028 Manually sets the stlink api used, valid options are 1 or 2. (@b{STLINK Only}).
3029 @end deffn
3030
3031 @deffn {Config Command} {trace} output_file_path source_clock_hz
3032 Enable SWO tracing (if supported), trace data is appended to the specified
3033 output file and the file is created if it does not exist. The source clock
3034 rate for the trace port must be specified, this is typically the CPU clock
3035 rate.
3036 @end deffn
3037 @end deffn
3038
3039 @deffn {Interface Driver} {opendous}
3040 opendous-jtag is a freely programmable USB adapter.
3041 @end deffn
3042
3043 @deffn {Interface Driver} {ulink}
3044 This is the Keil ULINK v1 JTAG debugger.
3045 @end deffn
3046
3047 @deffn {Interface Driver} {ZY1000}
3048 This is the Zylin ZY1000 JTAG debugger.
3049 @end deffn
3050
3051 @quotation Note
3052 This defines some driver-specific commands,
3053 which are not currently documented here.
3054 @end quotation
3055
3056 @deffn Command power [@option{on}|@option{off}]
3057 Turn power switch to target on/off.
3058 No arguments: print status.
3059 @end deffn
3060
3061 @deffn {Interface Driver} {bcm2835gpio}
3062 This SoC is present in Raspberry Pi which is a cheap single-board computer
3063 exposing some GPIOs on its expansion header.
3064
3065 The driver accesses memory-mapped GPIO peripheral registers directly
3066 for maximum performance, but the only possible race condition is for
3067 the pins' modes/muxing (which is highly unlikely), so it should be
3068 able to coexist nicely with both sysfs bitbanging and various
3069 peripherals' kernel drivers. The driver restores the previous
3070 configuration on exit.
3071
3072 See @file{interface/raspberrypi-native.cfg} for a sample config and
3073 pinout.
3074
3075 @end deffn
3076
3077 @section Transport Configuration
3078 @cindex Transport
3079 As noted earlier, depending on the version of OpenOCD you use,
3080 and the debug adapter you are using,
3081 several transports may be available to
3082 communicate with debug targets (or perhaps to program flash memory).
3083 @deffn Command {transport list}
3084 displays the names of the transports supported by this
3085 version of OpenOCD.
3086 @end deffn
3087
3088 @deffn Command {transport select} transport_name
3089 Select which of the supported transports to use in this OpenOCD session.
3090 The transport must be supported by the debug adapter hardware and by the
3091 version of OpenOCD you are using (including the adapter's driver).
3092 No arguments: returns name of session's selected transport.
3093 @end deffn
3094
3095 @subsection JTAG Transport
3096 @cindex JTAG
3097 JTAG is the original transport supported by OpenOCD, and most
3098 of the OpenOCD commands support it.
3099 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3100 each of which must be explicitly declared.
3101 JTAG supports both debugging and boundary scan testing.
3102 Flash programming support is built on top of debug support.
3103 @subsection SWD Transport
3104 @cindex SWD
3105 @cindex Serial Wire Debug
3106 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3107 Debug Access Point (DAP, which must be explicitly declared.
3108 (SWD uses fewer signal wires than JTAG.)
3109 SWD is debug-oriented, and does not support boundary scan testing.
3110 Flash programming support is built on top of debug support.
3111 (Some processors support both JTAG and SWD.)
3112 @deffn Command {swd newdap} ...
3113 Declares a single DAP which uses SWD transport.
3114 Parameters are currently the same as "jtag newtap" but this is
3115 expected to change.
3116 @end deffn
3117 @deffn Command {swd wcr trn prescale}
3118 Updates TRN (turnaraound delay) and prescaling.fields of the
3119 Wire Control Register (WCR).
3120 No parameters: displays current settings.
3121 @end deffn
3122
3123 @subsection SPI Transport
3124 @cindex SPI
3125 @cindex Serial Peripheral Interface
3126 The Serial Peripheral Interface (SPI) is a general purpose transport
3127 which uses four wire signaling. Some processors use it as part of a
3128 solution for flash programming.
3129
3130 @anchor{jtagspeed}
3131 @section JTAG Speed
3132 JTAG clock setup is part of system setup.
3133 It @emph{does not belong with interface setup} since any interface
3134 only knows a few of the constraints for the JTAG clock speed.
3135 Sometimes the JTAG speed is
3136 changed during the target initialization process: (1) slow at
3137 reset, (2) program the CPU clocks, (3) run fast.
3138 Both the "slow" and "fast" clock rates are functions of the
3139 oscillators used, the chip, the board design, and sometimes
3140 power management software that may be active.
3141
3142 The speed used during reset, and the scan chain verification which
3143 follows reset, can be adjusted using a @code{reset-start}
3144 target event handler.
3145 It can then be reconfigured to a faster speed by a
3146 @code{reset-init} target event handler after it reprograms those
3147 CPU clocks, or manually (if something else, such as a boot loader,
3148 sets up those clocks).
3149 @xref{targetevents,,Target Events}.
3150 When the initial low JTAG speed is a chip characteristic, perhaps
3151 because of a required oscillator speed, provide such a handler
3152 in the target config file.
3153 When that speed is a function of a board-specific characteristic
3154 such as which speed oscillator is used, it belongs in the board
3155 config file instead.
3156 In both cases it's safest to also set the initial JTAG clock rate
3157 to that same slow speed, so that OpenOCD never starts up using a
3158 clock speed that's faster than the scan chain can support.
3159
3160 @example
3161 jtag_rclk 3000
3162 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3163 @end example
3164
3165 If your system supports adaptive clocking (RTCK), configuring
3166 JTAG to use that is probably the most robust approach.
3167 However, it introduces delays to synchronize clocks; so it
3168 may not be the fastest solution.
3169
3170 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3171 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3172 which support adaptive clocking.
3173
3174 @deffn {Command} adapter_khz max_speed_kHz
3175 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3176 JTAG interfaces usually support a limited number of
3177 speeds. The speed actually used won't be faster
3178 than the speed specified.
3179
3180 Chip data sheets generally include a top JTAG clock rate.
3181 The actual rate is often a function of a CPU core clock,
3182 and is normally less than that peak rate.
3183 For example, most ARM cores accept at most one sixth of the CPU clock.
3184
3185 Speed 0 (khz) selects RTCK method.
3186 @xref{faqrtck,,FAQ RTCK}.
3187 If your system uses RTCK, you won't need to change the
3188 JTAG clocking after setup.
3189 Not all interfaces, boards, or targets support ``rtck''.
3190 If the interface device can not
3191 support it, an error is returned when you try to use RTCK.
3192 @end deffn
3193
3194 @defun jtag_rclk fallback_speed_kHz
3195 @cindex adaptive clocking
3196 @cindex RTCK
3197 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3198 If that fails (maybe the interface, board, or target doesn't
3199 support it), falls back to the specified frequency.
3200 @example
3201 # Fall back to 3mhz if RTCK is not supported
3202 jtag_rclk 3000
3203 @end example
3204 @end defun
3205
3206 @node Reset Configuration
3207 @chapter Reset Configuration
3208 @cindex Reset Configuration
3209
3210 Every system configuration may require a different reset
3211 configuration. This can also be quite confusing.
3212 Resets also interact with @var{reset-init} event handlers,
3213 which do things like setting up clocks and DRAM, and
3214 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3215 They can also interact with JTAG routers.
3216 Please see the various board files for examples.
3217
3218 @quotation Note
3219 To maintainers and integrators:
3220 Reset configuration touches several things at once.
3221 Normally the board configuration file
3222 should define it and assume that the JTAG adapter supports
3223 everything that's wired up to the board's JTAG connector.
3224
3225 However, the target configuration file could also make note
3226 of something the silicon vendor has done inside the chip,
3227 which will be true for most (or all) boards using that chip.
3228 And when the JTAG adapter doesn't support everything, the
3229 user configuration file will need to override parts of
3230 the reset configuration provided by other files.
3231 @end quotation
3232
3233 @section Types of Reset
3234
3235 There are many kinds of reset possible through JTAG, but
3236 they may not all work with a given board and adapter.
3237 That's part of why reset configuration can be error prone.
3238
3239 @itemize @bullet
3240 @item
3241 @emph{System Reset} ... the @emph{SRST} hardware signal
3242 resets all chips connected to the JTAG adapter, such as processors,
3243 power management chips, and I/O controllers. Normally resets triggered
3244 with this signal behave exactly like pressing a RESET button.
3245 @item
3246 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3247 just the TAP controllers connected to the JTAG adapter.
3248 Such resets should not be visible to the rest of the system; resetting a
3249 device's TAP controller just puts that controller into a known state.
3250 @item
3251 @emph{Emulation Reset} ... many devices can be reset through JTAG
3252 commands. These resets are often distinguishable from system
3253 resets, either explicitly (a "reset reason" register says so)
3254 or implicitly (not all parts of the chip get reset).
3255 @item
3256 @emph{Other Resets} ... system-on-chip devices often support
3257 several other types of reset.
3258 You may need to arrange that a watchdog timer stops
3259 while debugging, preventing a watchdog reset.
3260 There may be individual module resets.
3261 @end itemize
3262
3263 In the best case, OpenOCD can hold SRST, then reset
3264 the TAPs via TRST and send commands through JTAG to halt the
3265 CPU at the reset vector before the 1st instruction is executed.
3266 Then when it finally releases the SRST signal, the system is
3267 halted under debugger control before any code has executed.
3268 This is the behavior required to support the @command{reset halt}
3269 and @command{reset init} commands; after @command{reset init} a
3270 board-specific script might do things like setting up DRAM.
3271 (@xref{resetcommand,,Reset Command}.)
3272
3273 @anchor{srstandtrstissues}
3274 @section SRST and TRST Issues
3275
3276 Because SRST and TRST are hardware signals, they can have a
3277 variety of system-specific constraints. Some of the most
3278 common issues are:
3279
3280 @itemize @bullet
3281
3282 @item @emph{Signal not available} ... Some boards don't wire
3283 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3284 support such signals even if they are wired up.
3285 Use the @command{reset_config} @var{signals} options to say
3286 when either of those signals is not connected.
3287 When SRST is not available, your code might not be able to rely
3288 on controllers having been fully reset during code startup.
3289 Missing TRST is not a problem, since JTAG-level resets can
3290 be triggered using with TMS signaling.
3291
3292 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3293 adapter will connect SRST to TRST, instead of keeping them separate.
3294 Use the @command{reset_config} @var{combination} options to say
3295 when those signals aren't properly independent.
3296
3297 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3298 delay circuit, reset supervisor, or on-chip features can extend
3299 the effect of a JTAG adapter's reset for some time after the adapter
3300 stops issuing the reset. For example, there may be chip or board
3301 requirements that all reset pulses last for at least a
3302 certain amount of time; and reset buttons commonly have
3303 hardware debouncing.
3304 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3305 commands to say when extra delays are needed.
3306
3307 @item @emph{Drive type} ... Reset lines often have a pullup
3308 resistor, letting the JTAG interface treat them as open-drain
3309 signals. But that's not a requirement, so the adapter may need
3310 to use push/pull output drivers.
3311 Also, with weak pullups it may be advisable to drive
3312 signals to both levels (push/pull) to minimize rise times.
3313 Use the @command{reset_config} @var{trst_type} and
3314 @var{srst_type} parameters to say how to drive reset signals.
3315
3316 @item @emph{Special initialization} ... Targets sometimes need
3317 special JTAG initialization sequences to handle chip-specific
3318 issues (not limited to errata).
3319 For example, certain JTAG commands might need to be issued while
3320 the system as a whole is in a reset state (SRST active)
3321 but the JTAG scan chain is usable (TRST inactive).
3322 Many systems treat combined assertion of SRST and TRST as a
3323 trigger for a harder reset than SRST alone.
3324 Such custom reset handling is discussed later in this chapter.
3325 @end itemize
3326
3327 There can also be other issues.
3328 Some devices don't fully conform to the JTAG specifications.
3329 Trivial system-specific differences are common, such as
3330 SRST and TRST using slightly different names.
3331 There are also vendors who distribute key JTAG documentation for
3332 their chips only to developers who have signed a Non-Disclosure
3333 Agreement (NDA).
3334
3335 Sometimes there are chip-specific extensions like a requirement to use
3336 the normally-optional TRST signal (precluding use of JTAG adapters which
3337 don't pass TRST through), or needing extra steps to complete a TAP reset.
3338
3339 In short, SRST and especially TRST handling may be very finicky,
3340 needing to cope with both architecture and board specific constraints.
3341
3342 @section Commands for Handling Resets
3343
3344 @deffn {Command} adapter_nsrst_assert_width milliseconds
3345 Minimum amount of time (in milliseconds) OpenOCD should wait
3346 after asserting nSRST (active-low system reset) before
3347 allowing it to be deasserted.
3348 @end deffn
3349
3350 @deffn {Command} adapter_nsrst_delay milliseconds
3351 How long (in milliseconds) OpenOCD should wait after deasserting
3352 nSRST (active-low system reset) before starting new JTAG operations.
3353 When a board has a reset button connected to SRST line it will
3354 probably have hardware debouncing, implying you should use this.
3355 @end deffn
3356
3357 @deffn {Command} jtag_ntrst_assert_width milliseconds
3358 Minimum amount of time (in milliseconds) OpenOCD should wait
3359 after asserting nTRST (active-low JTAG TAP reset) before
3360 allowing it to be deasserted.
3361 @end deffn
3362
3363 @deffn {Command} jtag_ntrst_delay milliseconds
3364 How long (in milliseconds) OpenOCD should wait after deasserting
3365 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3366 @end deffn
3367
3368 @deffn {Command} reset_config mode_flag ...
3369 This command displays or modifies the reset configuration
3370 of your combination of JTAG board and target in target
3371 configuration scripts.
3372
3373 Information earlier in this section describes the kind of problems
3374 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3375 As a rule this command belongs only in board config files,
3376 describing issues like @emph{board doesn't connect TRST};
3377 or in user config files, addressing limitations derived
3378 from a particular combination of interface and board.
3379 (An unlikely example would be using a TRST-only adapter
3380 with a board that only wires up SRST.)
3381
3382 The @var{mode_flag} options can be specified in any order, but only one
3383 of each type -- @var{signals}, @var{combination}, @var{gates},
3384 @var{trst_type}, @var{srst_type} and @var{connect_type}
3385 -- may be specified at a time.
3386 If you don't provide a new value for a given type, its previous
3387 value (perhaps the default) is unchanged.
3388 For example, this means that you don't need to say anything at all about
3389 TRST just to declare that if the JTAG adapter should want to drive SRST,
3390 it must explicitly be driven high (@option{srst_push_pull}).
3391
3392 @itemize
3393 @item
3394 @var{signals} can specify which of the reset signals are connected.
3395 For example, If the JTAG interface provides SRST, but the board doesn't
3396 connect that signal properly, then OpenOCD can't use it.
3397 Possible values are @option{none} (the default), @option{trst_only},
3398 @option{srst_only} and @option{trst_and_srst}.
3399
3400 @quotation Tip
3401 If your board provides SRST and/or TRST through the JTAG connector,
3402 you must declare that so those signals can be used.
3403 @end quotation
3404
3405 @item
3406 The @var{combination} is an optional value specifying broken reset
3407 signal implementations.
3408 The default behaviour if no option given is @option{separate},
3409 indicating everything behaves normally.
3410 @option{srst_pulls_trst} states that the
3411 test logic is reset together with the reset of the system (e.g. NXP
3412 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3413 the system is reset together with the test logic (only hypothetical, I
3414 haven't seen hardware with such a bug, and can be worked around).
3415 @option{combined} implies both @option{srst_pulls_trst} and
3416 @option{trst_pulls_srst}.
3417
3418 @item
3419 The @var{gates} tokens control flags that describe some cases where
3420 JTAG may be unvailable during reset.
3421 @option{srst_gates_jtag} (default)
3422 indicates that asserting SRST gates the
3423 JTAG clock. This means that no communication can happen on JTAG
3424 while SRST is asserted.
3425 Its converse is @option{srst_nogate}, indicating that JTAG commands
3426 can safely be issued while SRST is active.
3427
3428 @item
3429 The @var{connect_type} tokens control flags that describe some cases where
3430 SRST is asserted while connecting to the target. @option{srst_nogate}
3431 is required to use this option.
3432 @option{connect_deassert_srst} (default)
3433 indicates that SRST will not be asserted while connecting to the target.
3434 Its converse is @option{connect_assert_srst}, indicating that SRST will
3435 be asserted before any target connection.
3436 Only some targets support this feature, STM32 and STR9 are examples.
3437 This feature is useful if you are unable to connect to your target due
3438 to incorrect options byte config or illegal program execution.
3439 @end itemize
3440
3441 The optional @var{trst_type} and @var{srst_type} parameters allow the
3442 driver mode of each reset line to be specified. These values only affect
3443 JTAG interfaces with support for different driver modes, like the Amontec
3444 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3445 relevant signal (TRST or SRST) is not connected.
3446
3447 @itemize
3448 @item
3449 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3450 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3451 Most boards connect this signal to a pulldown, so the JTAG TAPs
3452 never leave reset unless they are hooked up to a JTAG adapter.
3453
3454 @item
3455 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3456 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3457 Most boards connect this signal to a pullup, and allow the
3458 signal to be pulled low by various events including system
3459 powerup and pressing a reset button.
3460 @end itemize
3461 @end deffn
3462
3463 @section Custom Reset Handling
3464 @cindex events
3465
3466 OpenOCD has several ways to help support the various reset
3467 mechanisms provided by chip and board vendors.
3468 The commands shown in the previous section give standard parameters.
3469 There are also @emph{event handlers} associated with TAPs or Targets.
3470 Those handlers are Tcl procedures you can provide, which are invoked
3471 at particular points in the reset sequence.
3472
3473 @emph{When SRST is not an option} you must set
3474 up a @code{reset-assert} event handler for your target.
3475 For example, some JTAG adapters don't include the SRST signal;
3476 and some boards have multiple targets, and you won't always
3477 want to reset everything at once.
3478
3479 After configuring those mechanisms, you might still
3480 find your board doesn't start up or reset correctly.
3481 For example, maybe it needs a slightly different sequence
3482 of SRST and/or TRST manipulations, because of quirks that
3483 the @command{reset_config} mechanism doesn't address;
3484 or asserting both might trigger a stronger reset, which
3485 needs special attention.
3486
3487 Experiment with lower level operations, such as @command{jtag_reset}
3488 and the @command{jtag arp_*} operations shown here,
3489 to find a sequence of operations that works.
3490 @xref{JTAG Commands}.
3491 When you find a working sequence, it can be used to override
3492 @command{jtag_init}, which fires during OpenOCD startup
3493 (@pxref{configurationstage,,Configuration Stage});
3494 or @command{init_reset}, which fires during reset processing.
3495
3496 You might also want to provide some project-specific reset
3497 schemes. For example, on a multi-target board the standard
3498 @command{reset} command would reset all targets, but you
3499 may need the ability to reset only one target at time and
3500 thus want to avoid using the board-wide SRST signal.
3501
3502 @deffn {Overridable Procedure} init_reset mode
3503 This is invoked near the beginning of the @command{reset} command,
3504 usually to provide as much of a cold (power-up) reset as practical.
3505 By default it is also invoked from @command{jtag_init} if
3506 the scan chain does not respond to pure JTAG operations.
3507 The @var{mode} parameter is the parameter given to the
3508 low level reset command (@option{halt},
3509 @option{init}, or @option{run}), @option{setup},
3510 or potentially some other value.
3511
3512 The default implementation just invokes @command{jtag arp_init-reset}.
3513 Replacements will normally build on low level JTAG
3514 operations such as @command{jtag_reset}.
3515 Operations here must not address individual TAPs
3516 (or their associated targets)
3517 until the JTAG scan chain has first been verified to work.
3518
3519 Implementations must have verified the JTAG scan chain before
3520 they return.
3521 This is done by calling @command{jtag arp_init}
3522 (or @command{jtag arp_init-reset}).
3523 @end deffn
3524
3525 @deffn Command {jtag arp_init}
3526 This validates the scan chain using just the four
3527 standard JTAG signals (TMS, TCK, TDI, TDO).
3528 It starts by issuing a JTAG-only reset.
3529 Then it performs checks to verify that the scan chain configuration
3530 matches the TAPs it can observe.
3531 Those checks include checking IDCODE values for each active TAP,
3532 and verifying the length of their instruction registers using
3533 TAP @code{-ircapture} and @code{-irmask} values.
3534 If these tests all pass, TAP @code{setup} events are
3535 issued to all TAPs with handlers for that event.
3536 @end deffn
3537
3538 @deffn Command {jtag arp_init-reset}
3539 This uses TRST and SRST to try resetting
3540 everything on the JTAG scan chain
3541 (and anything else connected to SRST).
3542 It then invokes the logic of @command{jtag arp_init}.
3543 @end deffn
3544
3545
3546 @node TAP Declaration
3547 @chapter TAP Declaration
3548 @cindex TAP declaration
3549 @cindex TAP configuration
3550
3551 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3552 TAPs serve many roles, including:
3553
3554 @itemize @bullet
3555 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
3556 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
3557 Others do it indirectly, making a CPU do it.
3558 @item @b{Program Download} Using the same CPU support GDB uses,
3559 you can initialize a DRAM controller, download code to DRAM, and then
3560 start running that code.
3561 @item @b{Boundary Scan} Most chips support boundary scan, which
3562 helps test for board assembly problems like solder bridges
3563 and missing connections
3564 @end itemize
3565
3566 OpenOCD must know about the active TAPs on your board(s).
3567 Setting up the TAPs is the core task of your configuration files.
3568 Once those TAPs are set up, you can pass their names to code
3569 which sets up CPUs and exports them as GDB targets,
3570 probes flash memory, performs low-level JTAG operations, and more.
3571
3572 @section Scan Chains
3573 @cindex scan chain
3574
3575 TAPs are part of a hardware @dfn{scan chain},
3576 which is daisy chain of TAPs.
3577 They also need to be added to
3578 OpenOCD's software mirror of that hardware list,
3579 giving each member a name and associating other data with it.
3580 Simple scan chains, with a single TAP, are common in
3581 systems with a single microcontroller or microprocessor.
3582 More complex chips may have several TAPs internally.
3583 Very complex scan chains might have a dozen or more TAPs:
3584 several in one chip, more in the next, and connecting
3585 to other boards with their own chips and TAPs.
3586
3587 You can display the list with the @command{scan_chain} command.
3588 (Don't confuse this with the list displayed by the @command{targets}
3589 command, presented in the next chapter.
3590 That only displays TAPs for CPUs which are configured as
3591 debugging targets.)
3592 Here's what the scan chain might look like for a chip more than one TAP:
3593
3594 @verbatim
3595 TapName Enabled IdCode Expected IrLen IrCap IrMask
3596 -- ------------------ ------- ---------- ---------- ----- ----- ------
3597 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3598 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3599 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3600 @end verbatim
3601
3602 OpenOCD can detect some of that information, but not all
3603 of it. @xref{autoprobing,,Autoprobing}.
3604 Unfortunately those TAPs can't always be autoconfigured,
3605 because not all devices provide good support for that.
3606 JTAG doesn't require supporting IDCODE instructions, and
3607 chips with JTAG routers may not link TAPs into the chain
3608 until they are told to do so.
3609
3610 The configuration mechanism currently supported by OpenOCD
3611 requires explicit configuration of all TAP devices using
3612 @command{jtag newtap} commands, as detailed later in this chapter.
3613 A command like this would declare one tap and name it @code{chip1.cpu}:
3614
3615 @example
3616 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3617 @end example
3618
3619 Each target configuration file lists the TAPs provided
3620 by a given chip.
3621 Board configuration files combine all the targets on a board,
3622 and so forth.
3623 Note that @emph{the order in which TAPs are declared is very important.}
3624 It must match the order in the JTAG scan chain, both inside
3625 a single chip and between them.
3626 @xref{faqtaporder,,FAQ TAP Order}.
3627
3628 For example, the ST Microsystems STR912 chip has
3629 three separate TAPs@footnote{See the ST
3630 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3631 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3632 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3633 To configure those taps, @file{target/str912.cfg}
3634 includes commands something like this:
3635
3636 @example
3637 jtag newtap str912 flash ... params ...
3638 jtag newtap str912 cpu ... params ...
3639 jtag newtap str912 bs ... params ...
3640 @end example
3641
3642 Actual config files use a variable instead of literals like
3643 @option{str912}, to support more than one chip of each type.
3644 @xref{Config File Guidelines}.
3645
3646 @deffn Command {jtag names}
3647 Returns the names of all current TAPs in the scan chain.
3648 Use @command{jtag cget} or @command{jtag tapisenabled}
3649 to examine attributes and state of each TAP.
3650 @example
3651 foreach t [jtag names] @{
3652 puts [format "TAP: %s\n" $t]
3653 @}
3654 @end example
3655 @end deffn
3656
3657 @deffn Command {scan_chain}
3658 Displays the TAPs in the scan chain configuration,
3659 and their status.
3660 The set of TAPs listed by this command is fixed by
3661 exiting the OpenOCD configuration stage,
3662 but systems with a JTAG router can
3663 enable or disable TAPs dynamically.
3664 @end deffn
3665
3666 @c FIXME! "jtag cget" should be able to return all TAP
3667 @c attributes, like "$target_name cget" does for targets.
3668
3669 @c Probably want "jtag eventlist", and a "tap-reset" event
3670 @c (on entry to RESET state).
3671
3672 @section TAP Names
3673 @cindex dotted name
3674
3675 When TAP objects are declared with @command{jtag newtap},
3676 a @dfn{dotted.name} is created for the TAP, combining the
3677 name of a module (usually a chip) and a label for the TAP.
3678 For example: @code{xilinx.tap}, @code{str912.flash},
3679 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3680 Many other commands use that dotted.name to manipulate or
3681 refer to the TAP. For example, CPU configuration uses the
3682 name, as does declaration of NAND or NOR flash banks.
3683
3684 The components of a dotted name should follow ``C'' symbol
3685 name rules: start with an alphabetic character, then numbers
3686 and underscores are OK; while others (including dots!) are not.
3687
3688 @quotation Tip
3689 In older code, JTAG TAPs were numbered from 0..N.
3690 This feature is still present.
3691 However its use is highly discouraged, and
3692 should not be relied on; it will be removed by mid-2010.
3693 Update all of your scripts to use TAP names rather than numbers,
3694 by paying attention to the runtime warnings they trigger.
3695 Using TAP numbers in target configuration scripts prevents
3696 reusing those scripts on boards with multiple targets.
3697 @end quotation
3698
3699 @section TAP Declaration Commands
3700
3701 @c shouldn't this be(come) a {Config Command}?
3702 @deffn Command {jtag newtap} chipname tapname configparams...
3703 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3704 and configured according to the various @var{configparams}.
3705
3706 The @var{chipname} is a symbolic name for the chip.
3707 Conventionally target config files use @code{$_CHIPNAME},
3708 defaulting to the model name given by the chip vendor but
3709 overridable.
3710
3711 @cindex TAP naming convention
3712 The @var{tapname} reflects the role of that TAP,
3713 and should follow this convention:
3714
3715 @itemize @bullet
3716 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3717 @item @code{cpu} -- The main CPU of the chip, alternatively
3718 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3719 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3720 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3721 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3722 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3723 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3724 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3725 with a single TAP;
3726 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3727 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3728 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3729 a JTAG TAP; that TAP should be named @code{sdma}.
3730 @end itemize
3731
3732 Every TAP requires at least the following @var{configparams}:
3733
3734 @itemize @bullet
3735 @item @code{-irlen} @var{NUMBER}
3736 @*The length in bits of the
3737 instruction register, such as 4 or 5 bits.
3738 @end itemize
3739
3740 A TAP may also provide optional @var{configparams}:
3741
3742 @itemize @bullet
3743 @item @code{-disable} (or @code{-enable})
3744 @*Use the @code{-disable} parameter to flag a TAP which is not
3745 linked in to the scan chain after a reset using either TRST
3746 or the JTAG state machine's @sc{reset} state.
3747 You may use @code{-enable} to highlight the default state
3748 (the TAP is linked in).
3749 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3750 @item @code{-expected-id} @var{number}
3751 @*A non-zero @var{number} represents a 32-bit IDCODE
3752 which you expect to find when the scan chain is examined.
3753 These codes are not required by all JTAG devices.
3754 @emph{Repeat the option} as many times as required if more than one
3755 ID code could appear (for example, multiple versions).
3756 Specify @var{number} as zero to suppress warnings about IDCODE
3757 values that were found but not included in the list.
3758
3759 Provide this value if at all possible, since it lets OpenOCD
3760 tell when the scan chain it sees isn't right. These values
3761 are provided in vendors' chip documentation, usually a technical
3762 reference manual. Sometimes you may need to probe the JTAG
3763 hardware to find these values.
3764 @xref{autoprobing,,Autoprobing}.
3765 @item @code{-ignore-version}
3766 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3767 option. When vendors put out multiple versions of a chip, or use the same
3768 JTAG-level ID for several largely-compatible chips, it may be more practical
3769 to ignore the version field than to update config files to handle all of
3770 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3771 @item @code{-ircapture} @var{NUMBER}
3772 @*The bit pattern loaded by the TAP into the JTAG shift register
3773 on entry to the @sc{ircapture} state, such as 0x01.
3774 JTAG requires the two LSBs of this value to be 01.
3775 By default, @code{-ircapture} and @code{-irmask} are set
3776 up to verify that two-bit value. You may provide
3777 additional bits, if you know them, or indicate that
3778 a TAP doesn't conform to the JTAG specification.
3779 @item @code{-irmask} @var{NUMBER}
3780 @*A mask used with @code{-ircapture}
3781 to verify that instruction scans work correctly.
3782 Such scans are not used by OpenOCD except to verify that
3783 there seems to be no problems with JTAG scan chain operations.
3784 @end itemize
3785 @end deffn
3786
3787 @section Other TAP commands
3788
3789 @deffn Command {jtag cget} dotted.name @option{-event} name
3790 @deffnx Command {jtag configure} dotted.name @option{-event} name string
3791 At this writing this TAP attribute
3792 mechanism is used only for event handling.
3793 (It is not a direct analogue of the @code{cget}/@code{configure}
3794 mechanism for debugger targets.)
3795 See the next section for information about the available events.
3796
3797 The @code{configure} subcommand assigns an event handler,
3798 a TCL string which is evaluated when the event is triggered.
3799 The @code{cget} subcommand returns that handler.
3800 @end deffn
3801
3802 @section TAP Events
3803 @cindex events
3804 @cindex TAP events
3805
3806 OpenOCD includes two event mechanisms.
3807 The one presented here applies to all JTAG TAPs.
3808 The other applies to debugger targets,
3809 which are associated with certain TAPs.
3810
3811 The TAP events currently defined are:
3812
3813 @itemize @bullet
3814 @item @b{post-reset}
3815 @* The TAP has just completed a JTAG reset.
3816 The tap may still be in the JTAG @sc{reset} state.
3817 Handlers for these events might perform initialization sequences
3818 such as issuing TCK cycles, TMS sequences to ensure
3819 exit from the ARM SWD mode, and more.
3820
3821 Because the scan chain has not yet been verified, handlers for these events
3822 @emph{should not issue commands which scan the JTAG IR or DR registers}
3823 of any particular target.
3824 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3825 @item @b{setup}
3826 @* The scan chain has been reset and verified.
3827 This handler may enable TAPs as needed.
3828 @item @b{tap-disable}
3829 @* The TAP needs to be disabled. This handler should
3830 implement @command{jtag tapdisable}
3831 by issuing the relevant JTAG commands.
3832 @item @b{tap-enable}
3833 @* The TAP needs to be enabled. This handler should
3834 implement @command{jtag tapenable}
3835 by issuing the relevant JTAG commands.
3836 @end itemize
3837
3838 If you need some action after each JTAG reset, which isn't actually
3839 specific to any TAP (since you can't yet trust the scan chain's
3840 contents to be accurate), you might:
3841
3842 @example
3843 jtag configure CHIP.jrc -event post-reset @{
3844 echo "JTAG Reset done"
3845 ... non-scan jtag operations to be done after reset
3846 @}
3847 @end example
3848
3849
3850 @anchor{enablinganddisablingtaps}
3851 @section Enabling and Disabling TAPs
3852 @cindex JTAG Route Controller
3853 @cindex jrc
3854
3855 In some systems, a @dfn{JTAG Route Controller} (JRC)
3856 is used to enable and/or disable specific JTAG TAPs.
3857 Many ARM based chips from Texas Instruments include
3858 an ``ICEpick'' module, which is a JRC.
3859 Such chips include DaVinci and OMAP3 processors.
3860
3861 A given TAP may not be visible until the JRC has been
3862 told to link it into the scan chain; and if the JRC
3863 has been told to unlink that TAP, it will no longer
3864 be visible.
3865 Such routers address problems that JTAG ``bypass mode''
3866 ignores, such as:
3867
3868 @itemize
3869 @item The scan chain can only go as fast as its slowest TAP.
3870 @item Having many TAPs slows instruction scans, since all
3871 TAPs receive new instructions.
3872 @item TAPs in the scan chain must be powered up, which wastes
3873 power and prevents debugging some power management mechanisms.
3874 @end itemize
3875
3876 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3877 as implied by the existence of JTAG routers.
3878 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3879 does include a kind of JTAG router functionality.
3880
3881 @c (a) currently the event handlers don't seem to be able to
3882 @c fail in a way that could lead to no-change-of-state.
3883
3884 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3885 shown below, and is implemented using TAP event handlers.
3886 So for example, when defining a TAP for a CPU connected to
3887 a JTAG router, your @file{target.cfg} file
3888 should define TAP event handlers using
3889 code that looks something like this:
3890
3891 @example
3892 jtag configure CHIP.cpu -event tap-enable @{
3893 ... jtag operations using CHIP.jrc
3894 @}
3895 jtag configure CHIP.cpu -event tap-disable @{
3896 ... jtag operations using CHIP.jrc
3897 @}
3898 @end example
3899
3900 Then you might want that CPU's TAP enabled almost all the time:
3901
3902 @example
3903 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3904 @end example
3905
3906 Note how that particular setup event handler declaration
3907 uses quotes to evaluate @code{$CHIP} when the event is configured.
3908 Using brackets @{ @} would cause it to be evaluated later,
3909 at runtime, when it might have a different value.
3910
3911 @deffn Command {jtag tapdisable} dotted.name
3912 If necessary, disables the tap
3913 by sending it a @option{tap-disable} event.
3914 Returns the string "1" if the tap
3915 specified by @var{dotted.name} is enabled,
3916 and "0" if it is disabled.
3917 @end deffn
3918
3919 @deffn Command {jtag tapenable} dotted.name
3920 If necessary, enables the tap
3921 by sending it a @option{tap-enable} event.
3922 Returns the string "1" if the tap
3923 specified by @var{dotted.name} is enabled,
3924 and "0" if it is disabled.
3925 @end deffn
3926
3927 @deffn Command {jtag tapisenabled} dotted.name
3928 Returns the string "1" if the tap
3929 specified by @var{dotted.name} is enabled,
3930 and "0" if it is disabled.
3931
3932 @quotation Note
3933 Humans will find the @command{scan_chain} command more helpful
3934 for querying the state of the JTAG taps.
3935 @end quotation
3936 @end deffn
3937
3938 @anchor{autoprobing}
3939 @section Autoprobing
3940 @cindex autoprobe
3941 @cindex JTAG autoprobe
3942
3943 TAP configuration is the first thing that needs to be done
3944 after interface and reset configuration. Sometimes it's
3945 hard finding out what TAPs exist, or how they are identified.
3946 Vendor documentation is not always easy to find and use.
3947
3948 To help you get past such problems, OpenOCD has a limited
3949 @emph{autoprobing} ability to look at the scan chain, doing
3950 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3951 To use this mechanism, start the OpenOCD server with only data
3952 that configures your JTAG interface, and arranges to come up
3953 with a slow clock (many devices don't support fast JTAG clocks
3954 right when they come out of reset).
3955
3956 For example, your @file{openocd.cfg} file might have:
3957
3958 @example
3959 source [find interface/olimex-arm-usb-tiny-h.cfg]
3960 reset_config trst_and_srst
3961 jtag_rclk 8
3962 @end example
3963
3964 When you start the server without any TAPs configured, it will
3965 attempt to autoconfigure the TAPs. There are two parts to this:
3966
3967 @enumerate
3968 @item @emph{TAP discovery} ...
3969 After a JTAG reset (sometimes a system reset may be needed too),
3970 each TAP's data registers will hold the contents of either the
3971 IDCODE or BYPASS register.
3972 If JTAG communication is working, OpenOCD will see each TAP,
3973 and report what @option{-expected-id} to use with it.
3974 @item @emph{IR Length discovery} ...
3975 Unfortunately JTAG does not provide a reliable way to find out
3976 the value of the @option{-irlen} parameter to use with a TAP
3977 that is discovered.
3978 If OpenOCD can discover the length of a TAP's instruction
3979 register, it will report it.
3980 Otherwise you may need to consult vendor documentation, such
3981 as chip data sheets or BSDL files.
3982 @end enumerate
3983
3984 In many cases your board will have a simple scan chain with just
3985 a single device. Here's what OpenOCD reported with one board
3986 that's a bit more complex:
3987
3988 @example
3989 clock speed 8 kHz
3990 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3991 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3992 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3993 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3994 AUTO auto0.tap - use "... -irlen 4"
3995 AUTO auto1.tap - use "... -irlen 4"
3996 AUTO auto2.tap - use "... -irlen 6"
3997 no gdb ports allocated as no target has been specified
3998 @end example
3999
4000 Given that information, you should be able to either find some existing
4001 config files to use, or create your own. If you create your own, you
4002 would configure from the bottom up: first a @file{target.cfg} file
4003 with these TAPs, any targets associated with them, and any on-chip
4004 resources; then a @file{board.cfg} with off-chip resources, clocking,
4005 and so forth.
4006
4007 @node CPU Configuration
4008 @chapter CPU Configuration
4009 @cindex GDB target
4010
4011 This chapter discusses how to set up GDB debug targets for CPUs.
4012 You can also access these targets without GDB
4013 (@pxref{Architecture and Core Commands},
4014 and @ref{targetstatehandling,,Target State handling}) and
4015 through various kinds of NAND and NOR flash commands.
4016 If you have multiple CPUs you can have multiple such targets.
4017
4018 We'll start by looking at how to examine the targets you have,
4019 then look at how to add one more target and how to configure it.
4020
4021 @section Target List
4022 @cindex target, current
4023 @cindex target, list
4024
4025 All targets that have been set up are part of a list,
4026 where each member has a name.
4027 That name should normally be the same as the TAP name.
4028 You can display the list with the @command{targets}
4029 (plural!) command.
4030 This display often has only one CPU; here's what it might
4031 look like with more than one:
4032 @verbatim
4033 TargetName Type Endian TapName State
4034 -- ------------------ ---------- ------ ------------------ ------------
4035 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4036 1 MyTarget cortex_m little mychip.foo tap-disabled
4037 @end verbatim
4038
4039 One member of that list is the @dfn{current target}, which
4040 is implicitly referenced by many commands.
4041 It's the one marked with a @code{*} near the target name.
4042 In particular, memory addresses often refer to the address
4043 space seen by that current target.
4044 Commands like @command{mdw} (memory display words)
4045 and @command{flash erase_address} (erase NOR flash blocks)
4046 are examples; and there are many more.
4047
4048 Several commands let you examine the list of targets:
4049
4050 @deffn Command {target count}
4051 @emph{Note: target numbers are deprecated; don't use them.
4052 They will be removed shortly after August 2010, including this command.
4053 Iterate target using @command{target names}, not by counting.}
4054
4055 Returns the number of targets, @math{N}.
4056 The highest numbered target is @math{N - 1}.
4057 @example
4058 set c [target count]
4059 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
4060 # Assuming you have created this function
4061 print_target_details $x
4062 @}
4063 @end example
4064 @end deffn
4065
4066 @deffn Command {target current}
4067 Returns the name of the current target.
4068 @end deffn
4069
4070 @deffn Command {target names}
4071 Lists the names of all current targets in the list.
4072 @example
4073 foreach t [target names] @{
4074 puts [format "Target: %s\n" $t]
4075 @}
4076 @end example
4077 @end deffn
4078
4079 @deffn Command {target number} number
4080 @emph{Note: target numbers are deprecated; don't use them.
4081 They will be removed shortly after August 2010, including this command.}
4082
4083 The list of targets is numbered starting at zero.
4084 This command returns the name of the target at index @var{number}.
4085 @example
4086 set thename [target number $x]
4087 puts [format "Target %d is: %s\n" $x $thename]
4088 @end example
4089 @end deffn
4090
4091 @c yep, "target list" would have been better.
4092 @c plus maybe "target setdefault".
4093
4094 @deffn Command targets [name]
4095 @emph{Note: the name of this command is plural. Other target
4096 command names are singular.}
4097
4098 With no parameter, this command displays a table of all known
4099 targets in a user friendly form.
4100
4101 With a parameter, this command sets the current target to
4102 the given target with the given @var{name}; this is
4103 only relevant on boards which have more than one target.
4104 @end deffn
4105
4106 @section Target CPU Types and Variants
4107 @cindex target type
4108 @cindex CPU type
4109 @cindex CPU variant
4110
4111 Each target has a @dfn{CPU type}, as shown in the output of
4112 the @command{targets} command. You need to specify that type
4113 when calling @command{target create}.
4114 The CPU type indicates more than just the instruction set.
4115 It also indicates how that instruction set is implemented,
4116 what kind of debug support it integrates,
4117 whether it has an MMU (and if so, what kind),
4118 what core-specific commands may be available
4119 (@pxref{Architecture and Core Commands}),
4120 and more.
4121
4122 For some CPU types, OpenOCD also defines @dfn{variants} which
4123 indicate differences that affect their handling.
4124 For example, a particular implementation bug might need to be
4125 worked around in some chip versions.
4126
4127 It's easy to see what target types are supported,
4128 since there's a command to list them.
4129 However, there is currently no way to list what target variants
4130 are supported (other than by reading the OpenOCD source code).
4131
4132 @anchor{targettypes}
4133 @deffn Command {target types}
4134 Lists all supported target types.
4135 At this writing, the supported CPU types and variants are:
4136
4137 @itemize @bullet
4138 @item @code{arm11} -- this is a generation of ARMv6 cores
4139 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4140 @item @code{arm7tdmi} -- this is an ARMv4 core
4141 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4142 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4143 @item @code{arm966e} -- this is an ARMv5 core
4144 @item @code{arm9tdmi} -- this is an ARMv4 core
4145 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4146 (Support for this is preliminary and incomplete.)
4147 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4148 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4149 compact Thumb2 instruction set.
4150 @item @code{dragonite} -- resembles arm966e
4151 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4152 (Support for this is still incomplete.)
4153 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4154 @item @code{feroceon} -- resembles arm926
4155 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
4156 @item @code{xscale} -- this is actually an architecture,
4157 not a CPU type. It is based on the ARMv5 architecture.
4158 There are several variants defined:
4159 @itemize @minus
4160 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
4161 @code{pxa27x} ... instruction register length is 7 bits
4162 @item @code{pxa250}, @code{pxa255},
4163 @code{pxa26x} ... instruction register length is 5 bits
4164 @item @code{pxa3xx} ... instruction register length is 11 bits
4165 @end itemize
4166 @end itemize
4167 @end deffn
4168
4169 To avoid being confused by the variety of ARM based cores, remember
4170 this key point: @emph{ARM is a technology licencing company}.
4171 (See: @url{http://www.arm.com}.)
4172 The CPU name used by OpenOCD will reflect the CPU design that was
4173 licenced, not a vendor brand which incorporates that design.
4174 Name prefixes like arm7, arm9, arm11, and cortex
4175 reflect design generations;
4176 while names like ARMv4, ARMv5, ARMv6, and ARMv7
4177 reflect an architecture version implemented by a CPU design.
4178
4179 @anchor{targetconfiguration}
4180 @section Target Configuration
4181
4182 Before creating a ``target'', you must have added its TAP to the scan chain.
4183 When you've added that TAP, you will have a @code{dotted.name}
4184 which is used to set up the CPU support.
4185 The chip-specific configuration file will normally configure its CPU(s)
4186 right after it adds all of the chip's TAPs to the scan chain.
4187
4188 Although you can set up a target in one step, it's often clearer if you
4189 use shorter commands and do it in two steps: create it, then configure
4190 optional parts.
4191 All operations on the target after it's created will use a new
4192 command, created as part of target creation.
4193
4194 The two main things to configure after target creation are
4195 a work area, which usually has target-specific defaults even
4196 if the board setup code overrides them later;
4197 and event handlers (@pxref{targetevents,,Target Events}), which tend
4198 to be much more board-specific.
4199 The key steps you use might look something like this
4200
4201 @example
4202 target create MyTarget cortex_m -chain-position mychip.cpu
4203 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4204 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4205 $MyTarget configure -event reset-init @{ myboard_reinit @}
4206 @end example
4207
4208 You should specify a working area if you can; typically it uses some
4209 on-chip SRAM.
4210 Such a working area can speed up many things, including bulk
4211 writes to target memory;
4212 flash operations like checking to see if memory needs to be erased;
4213 GDB memory checksumming;
4214 and more.
4215
4216 @quotation Warning
4217 On more complex chips, the work area can become
4218 inaccessible when application code
4219 (such as an operating system)
4220 enables or disables the MMU.
4221 For example, the particular MMU context used to acess the virtual
4222 address will probably matter ... and that context might not have
4223 easy access to other addresses needed.
4224 At this writing, OpenOCD doesn't have much MMU intelligence.
4225 @end quotation
4226
4227 It's often very useful to define a @code{reset-init} event handler.
4228 For systems that are normally used with a boot loader,
4229 common tasks include updating clocks and initializing memory
4230 controllers.
4231 That may be needed to let you write the boot loader into flash,
4232 in order to ``de-brick'' your board; or to load programs into
4233 external DDR memory without having run the boot loader.
4234
4235 @deffn Command {target create} target_name type configparams...
4236 This command creates a GDB debug target that refers to a specific JTAG tap.
4237 It enters that target into a list, and creates a new
4238 command (@command{@var{target_name}}) which is used for various
4239 purposes including additional configuration.
4240
4241 @itemize @bullet
4242 @item @var{target_name} ... is the name of the debug target.
4243 By convention this should be the same as the @emph{dotted.name}
4244 of the TAP associated with this target, which must be specified here
4245 using the @code{-chain-position @var{dotted.name}} configparam.
4246
4247 This name is also used to create the target object command,
4248 referred to here as @command{$target_name},
4249 and in other places the target needs to be identified.
4250 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4251 @item @var{configparams} ... all parameters accepted by
4252 @command{$target_name configure} are permitted.
4253 If the target is big-endian, set it here with @code{-endian big}.
4254 If the variant matters, set it here with @code{-variant}.
4255
4256 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
4257 @end itemize
4258 @end deffn
4259
4260 @deffn Command {$target_name configure} configparams...
4261 The options accepted by this command may also be
4262 specified as parameters to @command{target create}.
4263 Their values can later be queried one at a time by
4264 using the @command{$target_name cget} command.
4265
4266 @emph{Warning:} changing some of these after setup is dangerous.
4267 For example, moving a target from one TAP to another;
4268 and changing its endianness or variant.
4269
4270 @itemize @bullet
4271
4272 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4273 used to access this target.
4274
4275 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4276 whether the CPU uses big or little endian conventions
4277
4278 @item @code{-event} @var{event_name} @var{event_body} --
4279 @xref{targetevents,,Target Events}.
4280 Note that this updates a list of named event handlers.
4281 Calling this twice with two different event names assigns
4282 two different handlers, but calling it twice with the
4283 same event name assigns only one handler.
4284
4285 @item @code{-variant} @var{name} -- specifies a variant of the target,
4286 which OpenOCD needs to know about.
4287
4288 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4289 whether the work area gets backed up; by default,
4290 @emph{it is not backed up.}
4291 When possible, use a working_area that doesn't need to be backed up,
4292 since performing a backup slows down operations.
4293 For example, the beginning of an SRAM block is likely to
4294 be used by most build systems, but the end is often unused.
4295
4296 @item @code{-work-area-size} @var{size} -- specify work are size,
4297 in bytes. The same size applies regardless of whether its physical
4298 or virtual address is being used.
4299
4300 @item @code{-work-area-phys} @var{address} -- set the work area
4301 base @var{address} to be used when no MMU is active.
4302
4303 @item @code{-work-area-virt} @var{address} -- set the work area
4304 base @var{address} to be used when an MMU is active.
4305 @emph{Do not specify a value for this except on targets with an MMU.}
4306 The value should normally correspond to a static mapping for the
4307 @code{-work-area-phys} address, set up by the current operating system.
4308
4309 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4310 @var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}|
4311 @option{FreeRTOS}|@option{linux}|@option{ChibiOS}|@option{embKernel}.
4312
4313 @end itemize
4314 @end deffn
4315
4316 @section Other $target_name Commands
4317 @cindex object command
4318
4319 The Tcl/Tk language has the concept of object commands,
4320 and OpenOCD adopts that same model for targets.
4321
4322 A good Tk example is a on screen button.
4323 Once a button is created a button
4324 has a name (a path in Tk terms) and that name is useable as a first
4325 class command. For example in Tk, one can create a button and later
4326 configure it like this:
4327
4328 @example
4329 # Create
4330 button .foobar -background red -command @{ foo @}
4331 # Modify
4332 .foobar configure -foreground blue
4333 # Query
4334 set x [.foobar cget -background]
4335 # Report
4336 puts [format "The button is %s" $x]
4337 @end example
4338
4339 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4340 button, and its object commands are invoked the same way.
4341
4342 @example
4343 str912.cpu mww 0x1234 0x42
4344 omap3530.cpu mww 0x5555 123
4345 @end example
4346
4347 The commands supported by OpenOCD target objects are:
4348
4349 @deffn Command {$target_name arp_examine}
4350 @deffnx Command {$target_name arp_halt}
4351 @deffnx Command {$target_name arp_poll}
4352 @deffnx Command {$target_name arp_reset}
4353 @deffnx Command {$target_name arp_waitstate}
4354 Internal OpenOCD scripts (most notably @file{startup.tcl})
4355 use these to deal with specific reset cases.
4356 They are not otherwise documented here.
4357 @end deffn
4358
4359 @deffn Command {$target_name array2mem} arrayname width address count
4360 @deffnx Command {$target_name mem2array} arrayname width address count
4361 These provide an efficient script-oriented interface to memory.
4362 The @code{array2mem} primitive writes bytes, halfwords, or words;
4363 while @code{mem2array} reads them.
4364 In both cases, the TCL side uses an array, and
4365 the target side uses raw memory.
4366
4367 The efficiency comes from enabling the use of
4368 bulk JTAG data transfer operations.
4369 The script orientation comes from working with data
4370 values that are packaged for use by TCL scripts;
4371 @command{mdw} type primitives only print data they retrieve,
4372 and neither store nor return those values.
4373
4374 @itemize
4375 @item @var{arrayname} ... is the name of an array variable
4376 @item @var{width} ... is 8/16/32 - indicating the memory access size
4377 @item @var{address} ... is the target memory address
4378 @item @var{count} ... is the number of elements to process
4379 @end itemize
4380 @end deffn
4381
4382 @deffn Command {$target_name cget} queryparm
4383 Each configuration parameter accepted by
4384 @command{$target_name configure}
4385 can be individually queried, to return its current value.
4386 The @var{queryparm} is a parameter name
4387 accepted by that command, such as @code{-work-area-phys}.
4388 There are a few special cases:
4389
4390 @itemize @bullet
4391 @item @code{-event} @var{event_name} -- returns the handler for the
4392 event named @var{event_name}.
4393 This is a special case because setting a handler requires
4394 two parameters.
4395 @item @code{-type} -- returns the target type.
4396 This is a special case because this is set using
4397 @command{target create} and can't be changed
4398 using @command{$target_name configure}.
4399 @end itemize
4400
4401 For example, if you wanted to summarize information about
4402 all the targets you might use something like this:
4403
4404 @example
4405 foreach name [target names] @{
4406 set y [$name cget -endian]
4407 set z [$name cget -type]
4408 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4409 $x $name $y $z]
4410 @}
4411 @end example
4412 @end deffn
4413
4414 @anchor{targetcurstate}
4415 @deffn Command {$target_name curstate}
4416 Displays the current target state:
4417 @code{debug-running},
4418 @code{halted},
4419 @code{reset},
4420 @code{running}, or @code{unknown}.
4421 (Also, @pxref{eventpolling,,Event Polling}.)
4422 @end deffn
4423
4424 @deffn Command {$target_name eventlist}
4425 Displays a table listing all event handlers
4426 currently associated with this target.
4427 @xref{targetevents,,Target Events}.
4428 @end deffn
4429
4430 @deffn Command {$target_name invoke-event} event_name
4431 Invokes the handler for the event named @var{event_name}.
4432 (This is primarily intended for use by OpenOCD framework
4433 code, for example by the reset code in @file{startup.tcl}.)
4434 @end deffn
4435
4436 @deffn Command {$target_name mdw} addr [count]
4437 @deffnx Command {$target_name mdh} addr [count]
4438 @deffnx Command {$target_name mdb} addr [count]
4439 Display contents of address @var{addr}, as
4440 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4441 or 8-bit bytes (@command{mdb}).
4442 If @var{count} is specified, displays that many units.
4443 (If you want to manipulate the data instead of displaying it,
4444 see the @code{mem2array} primitives.)
4445 @end deffn
4446
4447 @deffn Command {$target_name mww} addr word
4448 @deffnx Command {$target_name mwh} addr halfword
4449 @deffnx Command {$target_name mwb} addr byte
4450 Writes the specified @var{word} (32 bits),
4451 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4452 at the specified address @var{addr}.
4453 @end deffn
4454
4455 @anchor{targetevents}
4456 @section Target Events
4457 @cindex target events
4458 @cindex events
4459 At various times, certain things can happen, or you want them to happen.
4460 For example:
4461 @itemize @bullet
4462 @item What should happen when GDB connects? Should your target reset?
4463 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4464 @item Is using SRST appropriate (and possible) on your system?
4465 Or instead of that, do you need to issue JTAG commands to trigger reset?
4466 SRST usually resets everything on the scan chain, which can be inappropriate.
4467 @item During reset, do you need to write to certain memory locations
4468 to set up system clocks or
4469 to reconfigure the SDRAM?
4470 How about configuring the watchdog timer, or other peripherals,
4471 to stop running while you hold the core stopped for debugging?
4472 @end itemize
4473
4474 All of the above items can be addressed by target event handlers.
4475 These are set up by @command{$target_name configure -event} or
4476 @command{target create ... -event}.
4477
4478 The programmer's model matches the @code{-command} option used in Tcl/Tk
4479 buttons and events. The two examples below act the same, but one creates
4480 and invokes a small procedure while the other inlines it.
4481
4482 @example
4483 proc my_attach_proc @{ @} @{
4484 echo "Reset..."
4485 reset halt
4486 @}
4487 mychip.cpu configure -event gdb-attach my_attach_proc
4488 mychip.cpu configure -event gdb-attach @{
4489 echo "Reset..."
4490 # To make flash probe and gdb load to flash work we need a reset init.
4491 reset init
4492 @}
4493 @end example
4494
4495 The following target events are defined:
4496
4497 @itemize @bullet
4498 @item @b{debug-halted}
4499 @* The target has halted for debug reasons (i.e.: breakpoint)
4500 @item @b{debug-resumed}
4501 @* The target has resumed (i.e.: gdb said run)
4502 @item @b{early-halted}
4503 @* Occurs early in the halt process
4504 @item @b{examine-start}
4505 @* Before target examine is called.
4506 @item @b{examine-end}
4507 @* After target examine is called with no errors.
4508 @item @b{gdb-attach}
4509 @* When GDB connects. This is before any communication with the target, so this
4510 can be used to set up the target so it is possible to probe flash. Probing flash
4511 is necessary during gdb connect if gdb load is to write the image to flash. Another
4512 use of the flash memory map is for GDB to automatically hardware/software breakpoints
4513 depending on whether the breakpoint is in RAM or read only memory.
4514 @item @b{gdb-detach}
4515 @* When GDB disconnects
4516 @item @b{gdb-end}
4517 @* When the target has halted and GDB is not doing anything (see early halt)
4518 @item @b{gdb-flash-erase-start}
4519 @* Before the GDB flash process tries to erase the flash
4520 @item @b{gdb-flash-erase-end}
4521 @* After the GDB flash process has finished erasing the flash
4522 @item @b{gdb-flash-write-start}
4523 @* Before GDB writes to the flash
4524 @item @b{gdb-flash-write-end}
4525 @* After GDB writes to the flash
4526 @item @b{gdb-start}
4527 @* Before the target steps, gdb is trying to start/resume the target
4528 @item @b{halted}
4529 @* The target has halted
4530 @item @b{reset-assert-pre}
4531 @* Issued as part of @command{reset} processing
4532 after @command{reset_init} was triggered
4533 but before either SRST alone is re-asserted on the scan chain,
4534 or @code{reset-assert} is triggered.
4535 @item @b{reset-assert}
4536 @* Issued as part of @command{reset} processing
4537 after @command{reset-assert-pre} was triggered.
4538 When such a handler is present, cores which support this event will use
4539 it instead of asserting SRST.
4540 This support is essential for debugging with JTAG interfaces which
4541 don't include an SRST line (JTAG doesn't require SRST), and for
4542 selective reset on scan chains that have multiple targets.
4543 @item @b{reset-assert-post}
4544 @* Issued as part of @command{reset} processing
4545 after @code{reset-assert} has been triggered.
4546 or the target asserted SRST on the entire scan chain.
4547 @item @b{reset-deassert-pre}
4548 @* Issued as part of @command{reset} processing
4549 after @code{reset-assert-post} has been triggered.
4550 @item @b{reset-deassert-post}
4551 @* Issued as part of @command{reset} processing
4552 after @code{reset-deassert-pre} has been triggered
4553 and (if the target is using it) after SRST has been
4554 released on the scan chain.
4555 @item @b{reset-end}
4556 @* Issued as the final step in @command{reset} processing.
4557 @ignore
4558 @item @b{reset-halt-post}
4559 @* Currently not used
4560 @item @b{reset-halt-pre}
4561 @* Currently not used
4562 @end ignore
4563 @item @b{reset-init}
4564 @* Used by @b{reset init} command for board-specific initialization.
4565 This event fires after @emph{reset-deassert-post}.
4566
4567 This is where you would configure PLLs and clocking, set up DRAM so
4568 you can download programs that don't fit in on-chip SRAM, set up pin
4569 multiplexing, and so on.
4570 (You may be able to switch to a fast JTAG clock rate here, after
4571 the target clocks are fully set up.)
4572 @item @b{reset-start}
4573 @* Issued as part of @command{reset} processing
4574 before @command{reset_init} is called.
4575
4576 This is the most robust place to use @command{jtag_rclk}
4577 or @command{adapter_khz} to switch to a low JTAG clock rate,
4578 when reset disables PLLs needed to use a fast clock.
4579 @ignore
4580 @item @b{reset-wait-pos}
4581 @* Currently not used
4582 @item @b{reset-wait-pre}
4583 @* Currently not used
4584 @end ignore
4585 @item @b{resume-start}
4586 @* Before any target is resumed
4587 @item @b{resume-end}
4588 @* After all targets have resumed
4589 @item @b{resumed}
4590 @* Target has resumed
4591 @end itemize
4592
4593 @node Flash Commands
4594 @chapter Flash Commands
4595
4596 OpenOCD has different commands for NOR and NAND flash;
4597 the ``flash'' command works with NOR flash, while
4598 the ``nand'' command works with NAND flash.
4599 This partially reflects different hardware technologies:
4600 NOR flash usually supports direct CPU instruction and data bus access,
4601 while data from a NAND flash must be copied to memory before it can be
4602 used. (SPI flash must also be copied to memory before use.)
4603 However, the documentation also uses ``flash'' as a generic term;
4604 for example, ``Put flash configuration in board-specific files''.
4605
4606 Flash Steps:
4607 @enumerate
4608 @item Configure via the command @command{flash bank}
4609 @* Do this in a board-specific configuration file,
4610 passing parameters as needed by the driver.
4611 @item Operate on the flash via @command{flash subcommand}
4612 @* Often commands to manipulate the flash are typed by a human, or run
4613 via a script in some automated way. Common tasks include writing a
4614 boot loader, operating system, or other data.
4615 @item GDB Flashing
4616 @* Flashing via GDB requires the flash be configured via ``flash
4617 bank'', and the GDB flash features be enabled.
4618 @xref{gdbconfiguration,,GDB Configuration}.
4619 @end enumerate
4620
4621 Many CPUs have the ablity to ``boot'' from the first flash bank.
4622 This means that misprogramming that bank can ``brick'' a system,
4623 so that it can't boot.
4624 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4625 board by (re)installing working boot firmware.
4626
4627 @anchor{norconfiguration}
4628 @section Flash Configuration Commands
4629 @cindex flash configuration
4630
4631 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4632 Configures a flash bank which provides persistent storage
4633 for addresses from @math{base} to @math{base + size - 1}.
4634 These banks will often be visible to GDB through the target's memory map.
4635 In some cases, configuring a flash bank will activate extra commands;
4636 see the driver-specific documentation.
4637
4638 @itemize @bullet
4639 @item @var{name} ... may be used to reference the flash bank
4640 in other flash commands. A number is also available.
4641 @item @var{driver} ... identifies the controller driver
4642 associated with the flash bank being declared.
4643 This is usually @code{cfi} for external flash, or else
4644 the name of a microcontroller with embedded flash memory.
4645 @xref{flashdriverlist,,Flash Driver List}.
4646 @item @var{base} ... Base address of the flash chip.
4647 @item @var{size} ... Size of the chip, in bytes.
4648 For some drivers, this value is detected from the hardware.
4649 @item @var{chip_width} ... Width of the flash chip, in bytes;
4650 ignored for most microcontroller drivers.
4651 @item @var{bus_width} ... Width of the data bus used to access the
4652 chip, in bytes; ignored for most microcontroller drivers.
4653 @item @var{target} ... Names the target used to issue
4654 commands to the flash controller.
4655 @comment Actually, it's currently a controller-specific parameter...
4656 @item @var{driver_options} ... drivers may support, or require,
4657 additional parameters. See the driver-specific documentation
4658 for more information.
4659 @end itemize
4660 @quotation Note
4661 This command is not available after OpenOCD initialization has completed.
4662 Use it in board specific configuration files, not interactively.
4663 @end quotation
4664 @end deffn
4665
4666 @comment the REAL name for this command is "ocd_flash_banks"
4667 @comment less confusing would be: "flash list" (like "nand list")
4668 @deffn Command {flash banks}
4669 Prints a one-line summary of each device that was
4670 declared using @command{flash bank}, numbered from zero.
4671 Note that this is the @emph{plural} form;
4672 the @emph{singular} form is a very different command.
4673 @end deffn
4674
4675 @deffn Command {flash list}
4676 Retrieves a list of associative arrays for each device that was
4677 declared using @command{flash bank}, numbered from zero.
4678 This returned list can be manipulated easily from within scripts.
4679 @end deffn
4680
4681 @deffn Command {flash probe} num
4682 Identify the flash, or validate the parameters of the configured flash. Operation
4683 depends on the flash type.
4684 The @var{num} parameter is a value shown by @command{flash banks}.
4685 Most flash commands will implicitly @emph{autoprobe} the bank;
4686 flash drivers can distinguish between probing and autoprobing,
4687 but most don't bother.
4688 @end deffn
4689
4690 @section Erasing, Reading, Writing to Flash
4691 @cindex flash erasing
4692 @cindex flash reading
4693 @cindex flash writing
4694 @cindex flash programming
4695 @anchor{flashprogrammingcommands}
4696
4697 One feature distinguishing NOR flash from NAND or serial flash technologies
4698 is that for read access, it acts exactly like any other addressible memory.
4699 This means you can use normal memory read commands like @command{mdw} or
4700 @command{dump_image} with it, with no special @command{flash} subcommands.
4701 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
4702
4703 Write access works differently. Flash memory normally needs to be erased
4704 before it's written. Erasing a sector turns all of its bits to ones, and
4705 writing can turn ones into zeroes. This is why there are special commands
4706 for interactive erasing and writing, and why GDB needs to know which parts
4707 of the address space hold NOR flash memory.
4708
4709 @quotation Note
4710 Most of these erase and write commands leverage the fact that NOR flash
4711 chips consume target address space. They implicitly refer to the current
4712 JTAG target, and map from an address in that target's address space
4713 back to a flash bank.
4714 @comment In May 2009, those mappings may fail if any bank associated
4715 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
4716 A few commands use abstract addressing based on bank and sector numbers,
4717 and don't depend on searching the current target and its address space.
4718 Avoid confusing the two command models.
4719 @end quotation
4720
4721 Some flash chips implement software protection against accidental writes,
4722 since such buggy writes could in some cases ``brick'' a system.
4723 For such systems, erasing and writing may require sector protection to be
4724 disabled first.
4725 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4726 and AT91SAM7 on-chip flash.
4727 @xref{flashprotect,,flash protect}.
4728
4729 @deffn Command {flash erase_sector} num first last
4730 Erase sectors in bank @var{num}, starting at sector @var{first}
4731 up to and including @var{last}.
4732 Sector numbering starts at 0.
4733 Providing a @var{last} sector of @option{last}
4734 specifies "to the end of the flash bank".
4735 The @var{num} parameter is a value shown by @command{flash banks}.
4736 @end deffn
4737
4738 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4739 Erase sectors starting at @var{address} for @var{length} bytes.
4740 Unless @option{pad} is specified, @math{address} must begin a
4741 flash sector, and @math{address + length - 1} must end a sector.
4742 Specifying @option{pad} erases extra data at the beginning and/or
4743 end of the specified region, as needed to erase only full sectors.
4744 The flash bank to use is inferred from the @var{address}, and
4745 the specified length must stay within that bank.
4746 As a special case, when @var{length} is zero and @var{address} is
4747 the start of the bank, the whole flash is erased.
4748 If @option{unlock} is specified, then the flash is unprotected
4749 before erase starts.
4750 @end deffn
4751
4752 @deffn Command {flash fillw} address word length
4753 @deffnx Command {flash fillh} address halfword length
4754 @deffnx Command {flash fillb} address byte length
4755 Fills flash memory with the specified @var{word} (32 bits),
4756 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4757 starting at @var{address} and continuing
4758 for @var{length} units (word/halfword/byte).
4759 No erasure is done before writing; when needed, that must be done
4760 before issuing this command.
4761 Writes are done in blocks of up to 1024 bytes, and each write is
4762 verified by reading back the data and comparing it to what was written.
4763 The flash bank to use is inferred from the @var{address} of
4764 each block, and the specified length must stay within that bank.
4765 @end deffn
4766 @comment no current checks for errors if fill blocks touch multiple banks!
4767
4768 @deffn Command {flash write_bank} num filename offset
4769 Write the binary @file{filename} to flash bank @var{num},
4770 starting at @var{offset} bytes from the beginning of the bank.
4771 The @var{num} parameter is a value shown by @command{flash banks}.
4772 @end deffn
4773
4774 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4775 Write the image @file{filename} to the current target's flash bank(s).
4776 A relocation @var{offset} may be specified, in which case it is added
4777 to the base address for each section in the image.
4778 The file [@var{type}] can be specified
4779 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4780 @option{elf} (ELF file), @option{s19} (Motorola s19).
4781 @option{mem}, or @option{builder}.
4782 The relevant flash sectors will be erased prior to programming
4783 if the @option{erase} parameter is given. If @option{unlock} is
4784 provided, then the flash banks are unlocked before erase and
4785 program. The flash bank to use is inferred from the address of
4786 each image section.
4787
4788 @quotation Warning
4789 Be careful using the @option{erase} flag when the flash is holding
4790 data you want to preserve.
4791 Portions of the flash outside those described in the image's
4792 sections might be erased with no notice.
4793 @itemize
4794 @item
4795 When a section of the image being written does not fill out all the
4796 sectors it uses, the unwritten parts of those sectors are necessarily
4797 also erased, because sectors can't be partially erased.
4798 @item
4799 Data stored in sector "holes" between image sections are also affected.
4800 For example, "@command{flash write_image erase ...}" of an image with
4801 one byte at the beginning of a flash bank and one byte at the end
4802 erases the entire bank -- not just the two sectors being written.
4803 @end itemize
4804 Also, when flash protection is important, you must re-apply it after
4805 it has been removed by the @option{unlock} flag.
4806 @end quotation
4807
4808 @end deffn
4809
4810 @section Other Flash commands
4811 @cindex flash protection
4812
4813 @deffn Command {flash erase_check} num
4814 Check erase state of sectors in flash bank @var{num},
4815 and display that status.
4816 The @var{num} parameter is a value shown by @command{flash banks}.
4817 @end deffn
4818
4819 @deffn Command {flash info} num
4820 Print info about flash bank @var{num}
4821 The @var{num} parameter is a value shown by @command{flash banks}.
4822 This command will first query the hardware, it does not print cached
4823 and possibly stale information.
4824 @end deffn
4825
4826 @anchor{flashprotect}
4827 @deffn Command {flash protect} num first last (@option{on}|@option{off})
4828 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
4829 in flash bank @var{num}, starting at sector @var{first}
4830 and continuing up to and including @var{last}.
4831 Providing a @var{last} sector of @option{last}
4832 specifies "to the end of the flash bank".
4833 The @var{num} parameter is a value shown by @command{flash banks}.
4834 @end deffn
4835
4836 @anchor{program}
4837 @deffn Command {program} filename [verify] [reset] [offset]
4838 This is a helper script that simplifies using OpenOCD as a standalone
4839 programmer. The only required parameter is @option{filename}, the others are optional.
4840 @xref{Flash Programming}.
4841 @end deffn
4842
4843 @anchor{flashdriverlist}
4844 @section Flash Driver List
4845 As noted above, the @command{flash bank} command requires a driver name,
4846 and allows driver-specific options and behaviors.
4847 Some drivers also activate driver-specific commands.
4848
4849 @subsection External Flash
4850
4851 @deffn {Flash Driver} cfi
4852 @cindex Common Flash Interface
4853 @cindex CFI
4854 The ``Common Flash Interface'' (CFI) is the main standard for
4855 external NOR flash chips, each of which connects to a
4856 specific external chip select on the CPU.
4857 Frequently the first such chip is used to boot the system.
4858 Your board's @code{reset-init} handler might need to
4859 configure additional chip selects using other commands (like: @command{mww} to
4860 configure a bus and its timings), or
4861 perhaps configure a GPIO pin that controls the ``write protect'' pin
4862 on the flash chip.
4863 The CFI driver can use a target-specific working area to significantly
4864 speed up operation.
4865
4866 The CFI driver can accept the following optional parameters, in any order:
4867
4868 @itemize
4869 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
4870 like AM29LV010 and similar types.
4871 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
4872 @end itemize
4873
4874 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
4875 wide on a sixteen bit bus:
4876
4877 @example
4878 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
4879 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
4880 @end example
4881
4882 To configure one bank of 32 MBytes
4883 built from two sixteen bit (two byte) wide parts wired in parallel
4884 to create a thirty-two bit (four byte) bus with doubled throughput:
4885
4886 @example
4887 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
4888 @end example
4889
4890 @c "cfi part_id" disabled
4891 @end deffn
4892
4893 @deffn {Flash Driver} lpcspifi
4894 @cindex NXP SPI Flash Interface
4895 @cindex SPIFI
4896 @cindex lpcspifi
4897 NXP's LPC43xx and LPC18xx families include a proprietary SPI
4898 Flash Interface (SPIFI) peripheral that can drive and provide
4899 memory mapped access to external SPI flash devices.
4900
4901 The lpcspifi driver initializes this interface and provides
4902 program and erase functionality for these serial flash devices.
4903 Use of this driver @b{requires} a working area of at least 1kB
4904 to be configured on the target device; more than this will
4905 significantly reduce flash programming times.
4906
4907 The setup command only requires the @var{base} parameter. All
4908 other parameters are ignored, and the flash size and layout
4909 are configured by the driver.
4910
4911 @example
4912 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
4913 @end example
4914
4915 @end deffn
4916
4917 @deffn {Flash Driver} stmsmi
4918 @cindex STMicroelectronics Serial Memory Interface
4919 @cindex SMI
4920 @cindex stmsmi
4921 Some devices form STMicroelectronics (e.g. STR75x MCU family,
4922 SPEAr MPU family) include a proprietary
4923 ``Serial Memory Interface'' (SMI) controller able to drive external
4924 SPI flash devices.
4925 Depending on specific device and board configuration, up to 4 external
4926 flash devices can be connected.
4927
4928 SMI makes the flash content directly accessible in the CPU address
4929 space; each external device is mapped in a memory bank.
4930 CPU can directly read data, execute code and boot from SMI banks.
4931 Normal OpenOCD commands like @command{mdw} can be used to display
4932 the flash content.
4933
4934 The setup command only requires the @var{base} parameter in order
4935 to identify the memory bank.
4936 All other parameters are ignored. Additional information, like
4937 flash size, are detected automatically.
4938
4939 @example
4940 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
4941 @end example
4942
4943 @end deffn
4944
4945 @subsection Internal Flash (Microcontrollers)
4946
4947 @deffn {Flash Driver} aduc702x
4948 The ADUC702x analog microcontrollers from Analog Devices
4949 include internal flash and use ARM7TDMI cores.
4950 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
4951 The setup command only requires the @var{target} argument
4952 since all devices in this family have the same memory layout.
4953
4954 @example
4955 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
4956 @end example
4957 @end deffn
4958
4959 @anchor{at91sam3}
4960 @deffn {Flash Driver} at91sam3
4961 @cindex at91sam3
4962 All members of the AT91SAM3 microcontroller family from
4963 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
4964 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
4965 that the driver was orginaly developed and tested using the
4966 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
4967 the family was cribbed from the data sheet. @emph{Note to future
4968 readers/updaters: Please remove this worrysome comment after other
4969 chips are confirmed.}
4970
4971 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
4972 have one flash bank. In all cases the flash banks are at
4973 the following fixed locations:
4974
4975 @example
4976 # Flash bank 0 - all chips
4977 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
4978 # Flash bank 1 - only 256K chips
4979 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
4980 @end example
4981
4982 Internally, the AT91SAM3 flash memory is organized as follows.
4983 Unlike the AT91SAM7 chips, these are not used as parameters
4984 to the @command{flash bank} command:
4985
4986 @itemize
4987 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
4988 @item @emph{Bank Size:} 128K/64K Per flash bank
4989 @item @emph{Sectors:} 16 or 8 per bank
4990 @item @emph{SectorSize:} 8K Per Sector
4991 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
4992 @end itemize
4993
4994 The AT91SAM3 driver adds some additional commands:
4995
4996 @deffn Command {at91sam3 gpnvm}
4997 @deffnx Command {at91sam3 gpnvm clear} number
4998 @deffnx Command {at91sam3 gpnvm set} number
4999 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
5000 With no parameters, @command{show} or @command{show all},
5001 shows the status of all GPNVM bits.
5002 With @command{show} @var{number}, displays that bit.
5003
5004 With @command{set} @var{number} or @command{clear} @var{number},
5005 modifies that GPNVM bit.
5006 @end deffn
5007
5008 @deffn Command {at91sam3 info}
5009 This command attempts to display information about the AT91SAM3
5010 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
5011 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
5012 document id: doc6430A] and decodes the values. @emph{Second} it reads the
5013 various clock configuration registers and attempts to display how it
5014 believes the chip is configured. By default, the SLOWCLK is assumed to
5015 be 32768 Hz, see the command @command{at91sam3 slowclk}.
5016 @end deffn
5017
5018 @deffn Command {at91sam3 slowclk} [value]
5019 This command shows/sets the slow clock frequency used in the
5020 @command{at91sam3 info} command calculations above.
5021 @end deffn
5022 @end deffn
5023
5024 @deffn {Flash Driver} at91sam4
5025 @cindex at91sam4
5026 All members of the AT91SAM4 microcontroller family from
5027 Atmel include internal flash and use ARM's Cortex-M4 core.
5028 This driver uses the same cmd names/syntax as @xref{at91sam3}.
5029 @end deffn
5030
5031 @deffn {Flash Driver} at91sam7
5032 All members of the AT91SAM7 microcontroller family from Atmel include
5033 internal flash and use ARM7TDMI cores. The driver automatically
5034 recognizes a number of these chips using the chip identification
5035 register, and autoconfigures itself.
5036