1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developers
64 * JTAG Hardware Dongles:: JTAG Hardware Dongles
65 * About JIM-Tcl:: About JIM-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Interface - Dongle Configuration:: Interface - Dongle Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * Upgrading:: Deprecated/Removed Commands
85 * Target Library:: Target Library
86 * FAQ:: Frequently Asked Questions
87 * Tcl Crash Course:: Tcl Crash Course
88 * License:: GNU Free Documentation License
90 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
91 @comment case issue with ``Index.html'' and ``index.html''
92 @comment Occurs when creating ``--html --no-split'' output
93 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
94 * OpenOCD Concept Index:: Concept Index
95 * Command and Driver Index:: Command and Driver Index
102 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
103 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
104 Since that time, the project has grown into an active open-source project,
105 supported by a diverse community of software and hardware developers from
108 @section What is OpenOCD?
112 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
113 in-system programming and boundary-scan testing for embedded target
116 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
117 with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
118 A @dfn{TAP} is a ``Test Access Port'', a module which processes
119 special instructions and data. TAPs are daisy-chained within and
120 between chips and boards.
122 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
123 based, parallel port based, and other standalone boxes that run
124 OpenOCD internally. @xref{JTAG Hardware Dongles}.
126 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
127 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
128 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
129 debugged via the GDB protocol.
131 @b{Flash Programing:} Flash writing is supported for external CFI
132 compatible NOR flashes (Intel and AMD/Spansion command set) and several
133 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
134 STM32x). Preliminary support for various NAND flash controllers
135 (LPC3180, Orion, S3C24xx, more) controller is included.
137 @section OpenOCD Web Site
139 The OpenOCD web site provides the latest public news from the community:
141 @uref{http://openocd.berlios.de/web/}
143 @section Latest User's Guide:
145 The user's guide you are now reading may not be the latest one
146 available. A version for more recent code may be available.
147 Its HTML form is published irregularly at:
149 @uref{http://openocd.berlios.de/doc/html/index.html}
151 PDF form is likewise published at:
153 @uref{http://openocd.berlios.de/doc/pdf/openocd.pdf}
155 @section OpenOCD User's Forum
157 There is an OpenOCD forum (phpBB) hosted by SparkFun:
159 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
163 @chapter OpenOCD Developer Resources
166 If you are interested in improving the state of OpenOCD's debugging and
167 testing support, new contributions will be welcome. Motivated developers
168 can produce new target, flash or interface drivers, improve the
169 documentation, as well as more conventional bug fixes and enhancements.
171 The resources in this chapter are available for developers wishing to explore
172 or expand the OpenOCD source code.
174 @section OpenOCD Subversion Repository
176 You can download the current SVN version with an SVN client of your
177 choice from the following repositories:
179 @uref{svn://svn.berlios.de/openocd/trunk}
183 @uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
185 Using the SVN command line client, you can use the following command to
186 fetch the latest version (make sure there is no (non-svn) directory
187 called "openocd" in the current directory):
189 svn checkout svn://svn.berlios.de/openocd/trunk openocd
191 If you prefer GIT based tools, the @command{git-svn} package works too:
193 git svn clone -s svn://svn.berlios.de/openocd
195 The ``README'' file contains the instructions for building the project
198 Developers that want to contribute patches to the OpenOCD system are
199 @b{strongly} encouraged to base their work off of the most recent trunk
200 revision. Patches created against older versions may require additional
201 work from their submitter in order to be updated for newer releases.
203 @section Doxygen Developer Manual
205 During the development of the 0.2.0 release, the OpenOCD project began
206 providing a Doxygen reference manual. This document contains more
207 technical information about the software internals, development
208 processes, and similar documentation:
210 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
212 This document is a work-in-progress, but contributions would be welcome
213 to fill in the gaps. All of the source files are provided in-tree,
214 listed in the Doxyfile configuration in the top of the repository trunk.
216 @section OpenOCD Developer Mailing List
218 The OpenOCD Developer Mailing List provides the primary means of
219 communication between developers:
221 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
223 All drivers developers are enouraged to also subscribe to the list of
224 SVN commits to keep pace with the ongoing changes:
226 @uref{https://lists.berlios.de/mailman/listinfo/openocd-svn}
229 @node JTAG Hardware Dongles
230 @chapter JTAG Hardware Dongles
239 Defined: @b{dongle}: A small device that plugins into a computer and serves as
240 an adapter .... [snip]
242 In the OpenOCD case, this generally refers to @b{a small adapater} one
243 attaches to your computer via USB or the Parallel Printer Port. The
244 execption being the Zylin ZY1000 which is a small box you attach via
245 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
246 require any drivers to be installed on the developer PC. It also has
247 a built in web interface. It supports RTCK/RCLK or adaptive clocking
248 and has a built in relay to power cycle targets remotely.
251 @section Choosing a Dongle
253 There are several things you should keep in mind when choosing a dongle.
256 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
257 Does your dongle support it? You might need a level converter.
258 @item @b{Pinout} What pinout does your target board use?
259 Does your dongle support it? You may be able to use jumper
260 wires, or an "octopus" connector, to convert pinouts.
261 @item @b{Connection} Does your computer have the USB, printer, or
262 Ethernet port needed?
263 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
266 @section Stand alone Systems
268 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
269 dongle, but a standalone box. The ZY1000 has the advantage that it does
270 not require any drivers installed on the developer PC. It also has
271 a built in web interface. It supports RTCK/RCLK or adaptive clocking
272 and has a built in relay to power cycle targets remotely.
274 @section USB FT2232 Based
276 There are many USB JTAG dongles on the market, many of them are based
277 on a chip from ``Future Technology Devices International'' (FTDI)
278 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
279 See: @url{http://www.ftdichip.com} for more information.
280 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
281 chips are starting to become available in JTAG adapters.
285 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
287 @* See: @url{http://www.amontec.com/jtagkey.shtml}
289 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
291 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
293 @* See: @url{http://www.signalyzer.com}
294 @item @b{evb_lm3s811}
295 @* See: @url{http://www.luminarymicro.com} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
296 @item @b{luminary_icdi}
297 @* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug Interface (ICDI) Board, included in the Stellaris LM3S9B90 and LM3S9B92 Evaluation Kits.
298 @item @b{olimex-jtag}
299 @* See: @url{http://www.olimex.com}
301 @* See: @url{http://www.tincantools.com}
302 @item @b{turtelizer2}
304 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
305 @url{http://www.ethernut.de}
307 @* Link: @url{http://www.hitex.com/index.php?id=383}
309 @* Link @url{http://www.hitex.com/stm32-stick}
310 @item @b{axm0432_jtag}
311 @* Axiom AXM-0432 Link @url{http://www.axman.com}
313 @* Link @url{http://www.hitex.com/index.php?id=cortino}
316 @section USB JLINK based
317 There are several OEM versions of the Segger @b{JLINK} adapter. It is
318 an example of a micro controller based JTAG adapter, it uses an
319 AT91SAM764 internally.
322 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
323 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
324 @item @b{SEGGER JLINK}
325 @* Link: @url{http://www.segger.com/jlink.html}
327 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
330 @section USB RLINK based
331 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
334 @item @b{Raisonance RLink}
335 @* Link: @url{http://www.raisonance.com/products/RLink.php}
336 @item @b{STM32 Primer}
337 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
338 @item @b{STM32 Primer2}
339 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
345 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
347 @item @b{USB - Presto}
348 @* Link: @url{http://tools.asix.net/prg_presto.htm}
350 @item @b{Versaloon-Link}
351 @* Link: @url{http://www.simonqian.com/en/Versaloon}
353 @item @b{ARM-JTAG-EW}
354 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
357 @section IBM PC Parallel Printer Port Based
359 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
360 and the MacGraigor Wiggler. There are many clones and variations of
363 Note that parallel ports are becoming much less common, so if you
364 have the choice you should probably avoid these adapters in favor
369 @item @b{Wiggler} - There are many clones of this.
370 @* Link: @url{http://www.macraigor.com/wiggler.htm}
372 @item @b{DLC5} - From XILINX - There are many clones of this
373 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
374 produced, PDF schematics are easily found and it is easy to make.
376 @item @b{Amontec - JTAG Accelerator}
377 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
380 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
383 @*@uref{http://www.ccac.rwth-aachen.de/@/~michaels/@/index.php/hardware/@/armjtag,
384 Improved parallel-port wiggler-style JTAG adapter}
386 @item @b{Wiggler_ntrst_inverted}
387 @* Yet another variation - See the source code, src/jtag/parport.c
389 @item @b{old_amt_wiggler}
390 @* Unknown - probably not on the market today
393 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
396 @* Link: @url{http://www.amontec.com/chameleon.shtml}
402 @* ispDownload from Lattice Semiconductor
403 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
406 @* From ST Microsystems;
407 @uref{http://www.st.com/stonline/@/products/literature/um/7889.pdf,
408 FlashLINK JTAG programing cable for PSD and uPSD}
416 @* An EP93xx based Linux machine using the GPIO pins directly.
419 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
424 @chapter About JIM-Tcl
428 OpenOCD includes a small ``Tcl Interpreter'' known as JIM-Tcl.
429 This programming language provides a simple and extensible
432 All commands presented in this Guide are extensions to JIM-Tcl.
433 You can use them as simple commands, without needing to learn
434 much of anything about Tcl.
435 Alternatively, can write Tcl programs with them.
437 You can learn more about JIM at its website, @url{http://jim.berlios.de}.
440 @item @b{JIM vs. Tcl}
441 @* JIM-TCL is a stripped down version of the well known Tcl language,
442 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
443 fewer features. JIM-Tcl is a single .C file and a single .H file and
444 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
445 4.2 MB .zip file containing 1540 files.
447 @item @b{Missing Features}
448 @* Our practice has been: Add/clone the real Tcl feature if/when
449 needed. We welcome JIM Tcl improvements, not bloat.
452 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
453 command interpreter today is a mixture of (newer)
454 JIM-Tcl commands, and (older) the orginal command interpreter.
457 @* At the OpenOCD telnet command line (or via the GDB mon command) one
458 can type a Tcl for() loop, set variables, etc.
459 Some of the commands documented in this guide are implemented
460 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
462 @item @b{Historical Note}
463 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
465 @item @b{Need a crash course in Tcl?}
466 @*@xref{Tcl Crash Course}.
471 @cindex command line options
473 @cindex directory search
475 The @option{--help} option shows:
479 --help | -h display this help
480 --version | -v display OpenOCD version
481 --file | -f use configuration file <name>
482 --search | -s dir to search for config files and scripts
483 --debug | -d set debug level <0-3>
484 --log_output | -l redirect log output to file <name>
485 --command | -c run <command>
486 --pipe | -p use pipes when talking to gdb
489 By default OpenOCD reads the file configuration file @file{openocd.cfg}
490 in the current directory. To specify a different (or multiple)
491 configuration file, you can use the ``-f'' option. For example:
494 openocd -f config1.cfg -f config2.cfg -f config3.cfg
497 OpenOCD starts by processing the configuration commands provided
498 on the command line or in @file{openocd.cfg}.
499 @xref{Configuration Stage}.
500 At the end of the configuration stage it verifies the JTAG scan
501 chain defined using those commands; your configuration should
502 ensure that this always succeeds.
503 Normally, OpenOCD then starts running as a daemon.
504 Alternatively, commands may be used to terminate the configuration
505 stage early, perform work (such as updating some flash memory),
506 and then shut down without acting as a daemon.
508 Once OpenOCD starts running as a daemon, it waits for connections from
509 clients (Telnet, GDB, Other) and processes the commands issued through
512 If you are having problems, you can enable internal debug messages via
515 Also it is possible to interleave JIM-Tcl commands w/config scripts using the
516 @option{-c} command line switch.
518 To enable debug output (when reporting problems or working on OpenOCD
519 itself), use the @option{-d} command line switch. This sets the
520 @option{debug_level} to "3", outputting the most information,
521 including debug messages. The default setting is "2", outputting only
522 informational messages, warnings and errors. You can also change this
523 setting from within a telnet or gdb session using @command{debug_level
524 <n>} (@pxref{debug_level}).
526 You can redirect all output from the daemon to a file using the
527 @option{-l <logfile>} switch.
529 Search paths for config/script files can be added to OpenOCD by using
530 the @option{-s <search>} switch. The current directory and the OpenOCD
531 target library is in the search path by default.
533 For details on the @option{-p} option. @xref{Connecting to GDB}.
535 Note! OpenOCD will launch the GDB & telnet server even if it can not
536 establish a connection with the target. In general, it is possible for
537 the JTAG controller to be unresponsive until the target is set up
538 correctly via e.g. GDB monitor commands in a GDB init script.
540 @node OpenOCD Project Setup
541 @chapter OpenOCD Project Setup
543 To use OpenOCD with your development projects, you need to do more than
544 just connecting the JTAG adapter hardware (dongle) to your development board
545 and then starting the OpenOCD server.
546 You also need to configure that server so that it knows
547 about that adapter and board, and helps your work.
549 @section Hooking up the JTAG Adapter
551 Today's most common case is a dongle with a JTAG cable on one side
552 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
553 and a USB cable on the other.
554 Instead of USB, some cables use Ethernet;
555 older ones may use a PC parallel port, or even a serial port.
558 @item @emph{Start with power to your target board turned off},
559 and nothing connected to your JTAG adapter.
560 If you're particularly paranoid, unplug power to the board.
561 It's important to have the ground signal properly set up,
562 unless you are using a JTAG adapter which provides
563 galvanic isolation between the target board and the
566 @item @emph{Be sure it's the right kind of JTAG connector.}
567 If your dongle has a 20-pin ARM connector, you need some kind
568 of adapter (or octopus, see below) to hook it up to
569 boards using 14-pin or 10-pin connectors ... or to 20-pin
570 connectors which don't use ARM's pinout.
572 In the same vein, make sure the voltage levels are compatible.
573 Not all JTAG adapters have the level shifters needed to work
574 with 1.2 Volt boards.
576 @item @emph{Be certain the cable is properly oriented} or you might
577 damage your board. In most cases there are only two possible
578 ways to connect the cable.
579 Connect the JTAG cable from your adapter to the board.
580 Be sure it's firmly connected.
582 In the best case, the connector is keyed to physically
583 prevent you from inserting it wrong.
584 This is most often done using a slot on the board's male connector
585 housing, which must match a key on the JTAG cable's female connector.
586 If there's no housing, then you must look carefully and
587 make sure pin 1 on the cable hooks up to pin 1 on the board.
588 Ribbon cables are frequently all grey except for a wire on one
589 edge, which is red. The red wire is pin 1.
591 Sometimes dongles provide cables where one end is an ``octopus'' of
592 color coded single-wire connectors, instead of a connector block.
593 These are great when converting from one JTAG pinout to another,
594 but are tedious to set up.
595 Use these with connector pinout diagrams to help you match up the
596 adapter signals to the right board pins.
598 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
599 A USB, parallel, or serial port connector will go to the host which
600 you are using to run OpenOCD.
601 For Ethernet, consult the documentation and your network administrator.
603 For USB based JTAG adapters you have an easy sanity check at this point:
604 does the host operating system see the JTAG adapter?
606 @item @emph{Connect the adapter's power supply, if needed.}
607 This step is primarily for non-USB adapters,
608 but sometimes USB adapters need extra power.
610 @item @emph{Power up the target board.}
611 Unless you just let the magic smoke escape,
612 you're now ready to set up the OpenOCD server
613 so you can use JTAG to work with that board.
617 Talk with the OpenOCD server using
618 telnet (@code{telnet localhost 4444} on many systems) or GDB.
619 @xref{GDB and OpenOCD}.
621 @section Project Directory
623 There are many ways you can configure OpenOCD and start it up.
625 A simple way to organize them all involves keeping a
626 single directory for your work with a given board.
627 When you start OpenOCD from that directory,
628 it searches there first for configuration files, scripts,
629 and for code you upload to the target board.
630 It is also the natural place to write files,
631 such as log files and data you download from the board.
633 @section Configuration Basics
635 There are two basic ways of configuring OpenOCD, and
636 a variety of ways you can mix them.
637 Think of the difference as just being how you start the server:
640 @item Many @option{-f file} or @option{-c command} options on the command line
641 @item No options, but a @dfn{user config file}
642 in the current directory named @file{openocd.cfg}
645 Here is an example @file{openocd.cfg} file for a setup
646 using a Signalyzer FT2232-based JTAG adapter to talk to
647 a board with an Atmel AT91SAM7X256 microcontroller:
650 source [find interface/signalyzer.cfg]
652 # GDB can also flash my flash!
653 gdb_memory_map enable
654 gdb_flash_program enable
656 source [find target/sam7x256.cfg]
659 Here is the command line equivalent of that configuration:
662 openocd -f interface/signalyzer.cfg \
663 -c "gdb_memory_map enable" \
664 -c "gdb_flash_program enable" \
665 -f target/sam7x256.cfg
668 You could wrap such long command lines in shell scripts,
669 each supporting a different development task.
670 One might re-flash the board with a specific firmware version.
671 Another might set up a particular debugging or run-time environment.
673 Here we will focus on the simpler solution: one user config
674 file, including basic configuration plus any TCL procedures
675 to simplify your work.
677 @section User Config Files
678 @cindex config file, user
679 @cindex user config file
680 @cindex config file, overview
682 A user configuration file ties together all the parts of a project
684 One of the following will match your situation best:
687 @item Ideally almost everything comes from configuration files
688 provided by someone else.
689 For example, OpenOCD distributes a @file{scripts} directory
690 (probably in @file{/usr/share/openocd/scripts} on Linux).
691 Board and tool vendors can provide these too, as can individual
692 user sites; the @option{-s} command line option lets you say
693 where to find these files. (@xref{Running}.)
694 The AT91SAM7X256 example above works this way.
696 Three main types of non-user configuration file each have their
697 own subdirectory in the @file{scripts} directory:
700 @item @b{interface} -- one for each kind of JTAG adapter/dongle
701 @item @b{board} -- one for each different board
702 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
705 Best case: include just two files, and they handle everything else.
706 The first is an interface config file.
707 The second is board-specific, and it sets up the JTAG TAPs and
708 their GDB targets (by deferring to some @file{target.cfg} file),
709 declares all flash memory, and leaves you nothing to do except
713 source [find interface/olimex-jtag-tiny.cfg]
714 source [find board/csb337.cfg]
717 Boards with a single microcontroller often won't need more
718 than the target config file, as in the AT91SAM7X256 example.
719 That's because there is no external memory (flash, DDR RAM), and
720 the board differences are encapsulated by application code.
722 @item You can often reuse some standard config files but
723 need to write a few new ones, probably a @file{board.cfg} file.
724 You will be using commands described later in this User's Guide,
725 and working with the guidelines in the next chapter.
727 For example, there may be configuration files for your JTAG adapter
728 and target chip, but you need a new board-specific config file
729 giving access to your particular flash chips.
730 Or you might need to write another target chip configuration file
731 for a new chip built around the Cortex M3 core.
734 When you write new configuration files, please submit
735 them for inclusion in the next OpenOCD release.
736 For example, a @file{board/newboard.cfg} file will help the
737 next users of that board, and a @file{target/newcpu.cfg}
738 will help support users of any board using that chip.
742 You may may need to write some C code.
743 It may be as simple as a supporting a new ft2232 or parport
744 based dongle; a bit more involved, like a NAND or NOR flash
745 controller driver; or a big piece of work like supporting
746 a new chip architecture.
749 Reuse the existing config files when you can.
750 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
751 You may find a board configuration that's a good example to follow.
753 When you write config files, separate the reusable parts
754 (things every user of that interface, chip, or board needs)
755 from ones specific to your environment and debugging approach.
759 For example, a @code{gdb-attach} event handler that invokes
760 the @command{reset init} command will interfere with debugging
761 early boot code, which performs some of the same actions
762 that the @code{reset-init} event handler does.
765 Likewise, the @command{arm9tdmi vector_catch} command (or
767 its siblings @command{xscale vector_catch}
768 and @command{cortex_m3 vector_catch}) can be a timesaver
769 during some debug sessions, but don't make everyone use that either.
770 Keep those kinds of debugging aids in your user config file,
771 along with messaging and tracing setup.
772 (@xref{Software Debug Messages and Tracing}.)
775 You might need to override some defaults.
776 For example, you might need to move, shrink, or back up the target's
777 work area if your application needs much SRAM.
780 TCP/IP port configuration is another example of something which
781 is environment-specific, and should only appear in
782 a user config file. @xref{TCP/IP Ports}.
785 @section Project-Specific Utilities
787 A few project-specific utility
788 routines may well speed up your work.
789 Write them, and keep them in your project's user config file.
791 For example, if you are making a boot loader work on a
792 board, it's nice to be able to debug the ``after it's
793 loaded to RAM'' parts separately from the finicky early
794 code which sets up the DDR RAM controller and clocks.
795 A script like this one, or a more GDB-aware sibling,
799 proc ramboot @{ @} @{
800 # Reset, running the target's "reset-init" scripts
801 # to initialize clocks and the DDR RAM controller.
802 # Leave the CPU halted.
805 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
806 load_image u-boot.bin 0x20000000
813 Then once that code is working you will need to make it
814 boot from NOR flash; a different utility would help.
815 Alternatively, some developers write to flash using GDB.
816 (You might use a similar script if you're working with a flash
817 based microcontroller application instead of a boot loader.)
820 proc newboot @{ @} @{
821 # Reset, leaving the CPU halted. The "reset-init" event
822 # proc gives faster access to the CPU and to NOR flash;
823 # "reset halt" would be slower.
826 # Write standard version of U-Boot into the first two
827 # sectors of NOR flash ... the standard version should
828 # do the same lowlevel init as "reset-init".
829 flash protect 0 0 1 off
830 flash erase_sector 0 0 1
831 flash write_bank 0 u-boot.bin 0x0
832 flash protect 0 0 1 on
834 # Reboot from scratch using that new boot loader.
839 You may need more complicated utility procedures when booting
841 That often involves an extra bootloader stage,
842 running from on-chip SRAM to perform DDR RAM setup so it can load
843 the main bootloader code (which won't fit into that SRAM).
845 Other helper scripts might be used to write production system images,
846 involving considerably more than just a three stage bootloader.
849 @node Config File Guidelines
850 @chapter Config File Guidelines
852 This chapter is aimed at any user who needs to write a config file,
853 including developers and integrators of OpenOCD and any user who
854 needs to get a new board working smoothly.
855 It provides guidelines for creating those files.
857 You should find the following directories under @t{$(INSTALLDIR)/scripts}:
860 @item @file{interface} ...
861 think JTAG Dongle. Files that configure JTAG adapters go here.
862 @item @file{board} ...
863 think Circuit Board, PWA, PCB, they go by many names. Board files
864 contain initialization items that are specific to a board. For
865 example, the SDRAM initialization sequence for the board, or the type
866 of external flash and what address it uses. Any initialization
867 sequence to enable that external flash or SDRAM should be found in the
868 board file. Boards may also contain multiple targets: two CPUs; or
869 a CPU and an FPGA or CPLD.
870 @item @file{target} ...
871 think chip. The ``target'' directory represents the JTAG TAPs
873 which OpenOCD should control, not a board. Two common types of targets
874 are ARM chips and FPGA or CPLD chips.
875 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
876 the target config file defines all of them.
879 The @file{openocd.cfg} user config
880 file may override features in any of the above files by
881 setting variables before sourcing the target file, or by adding
882 commands specific to their situation.
884 @section Interface Config Files
887 should be able to source one of these files with a command like this:
890 source [find interface/FOOBAR.cfg]
893 A preconfigured interface file should exist for every interface in use
894 today, that said, perhaps some interfaces have only been used by the
895 sole developer who created it.
897 A separate chapter gives information about how to set these up.
898 @xref{Interface - Dongle Configuration}.
899 Read the OpenOCD source code if you have a new kind of hardware interface
900 and need to provide a driver for it.
902 @section Board Config Files
903 @cindex config file, board
904 @cindex board config file
907 should be able to source one of these files with a command like this:
910 source [find board/FOOBAR.cfg]
913 The point of a board config file is to package everything
914 about a given board that user config files need to know.
915 In summary the board files should contain (if present)
918 @item One or more @command{source [target/...cfg]} statements
919 @item NOR flash configuration (@pxref{NOR Configuration})
920 @item NAND flash configuration (@pxref{NAND Configuration})
921 @item Target @code{reset} handlers for SDRAM and I/O configuration
922 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
923 @item All things that are not ``inside a chip''
926 Generic things inside target chips belong in target config files,
927 not board config files. So for example a @code{reset-init} event
928 handler should know board-specific oscillator and PLL parameters,
929 which it passes to target-specific utility code.
931 The most complex task of a board config file is creating such a
932 @code{reset-init} event handler.
933 Define those handlers last, after you verify the rest of the board
936 @subsection Communication Between Config files
938 In addition to target-specific utility code, another way that
939 board and target config files communicate is by following a
940 convention on how to use certain variables.
942 The full Tcl/Tk language supports ``namespaces'', but JIM-Tcl does not.
943 Thus the rule we follow in OpenOCD is this: Variables that begin with
944 a leading underscore are temporary in nature, and can be modified and
945 used at will within a target configuration file.
947 Complex board config files can do the things like this,
948 for a board with three chips:
951 # Chip #1: PXA270 for network side, big endian
954 source [find target/pxa270.cfg]
955 # on return: _TARGETNAME = network.cpu
956 # other commands can refer to the "network.cpu" target.
957 $_TARGETNAME configure .... events for this CPU..
959 # Chip #2: PXA270 for video side, little endian
962 source [find target/pxa270.cfg]
963 # on return: _TARGETNAME = video.cpu
964 # other commands can refer to the "video.cpu" target.
965 $_TARGETNAME configure .... events for this CPU..
967 # Chip #3: Xilinx FPGA for glue logic
970 source [find target/spartan3.cfg]
973 That example is oversimplified because it doesn't show any flash memory,
974 or the @code{reset-init} event handlers to initialize external DRAM
975 or (assuming it needs it) load a configuration into the FPGA.
976 Such features are usually needed for low-level work with many boards,
977 where ``low level'' implies that the board initialization software may
978 not be working. (That's a common reason to need JTAG tools. Another
979 is to enable working with microcontroller-based systems, which often
980 have no debugging support except a JTAG connector.)
982 Target config files may also export utility functions to board and user
983 config files. Such functions should use name prefixes, to help avoid
986 Board files could also accept input variables from user config files.
987 For example, there might be a @code{J4_JUMPER} setting used to identify
988 what kind of flash memory a development board is using, or how to set
989 up other clocks and peripherals.
991 @subsection Variable Naming Convention
992 @cindex variable names
994 Most boards have only one instance of a chip.
995 However, it should be easy to create a board with more than
996 one such chip (as shown above).
997 Accordingly, we encourage these conventions for naming
998 variables associated with different @file{target.cfg} files,
999 to promote consistency and
1000 so that board files can override target defaults.
1002 Inputs to target config files include:
1005 @item @code{CHIPNAME} ...
1006 This gives a name to the overall chip, and is used as part of
1007 tap identifier dotted names.
1008 While the default is normally provided by the chip manufacturer,
1009 board files may need to distinguish between instances of a chip.
1010 @item @code{ENDIAN} ...
1011 By default @option{little} - although chips may hard-wire @option{big}.
1012 Chips that can't change endianness don't need to use this variable.
1013 @item @code{CPUTAPID} ...
1014 When OpenOCD examines the JTAG chain, it can be told verify the
1015 chips against the JTAG IDCODE register.
1016 The target file will hold one or more defaults, but sometimes the
1017 chip in a board will use a different ID (perhaps a newer revision).
1020 Outputs from target config files include:
1023 @item @code{_TARGETNAME} ...
1024 By convention, this variable is created by the target configuration
1025 script. The board configuration file may make use of this variable to
1026 configure things like a ``reset init'' script, or other things
1027 specific to that board and that target.
1028 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1029 @code{_TARGETNAME1}, ... etc.
1032 @subsection The reset-init Event Handler
1033 @cindex event, reset-init
1034 @cindex reset-init handler
1036 Board config files run in the OpenOCD configuration stage;
1037 they can't use TAPs or targets, since they haven't been
1039 This means you can't write memory or access chip registers;
1040 you can't even verify that a flash chip is present.
1041 That's done later in event handlers, of which the target @code{reset-init}
1042 handler is one of the most important.
1044 Except on microcontrollers, the basic job of @code{reset-init} event
1045 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1046 Microcontrollers rarely use boot loaders; they run right out of their
1047 on-chip flash and SRAM memory. But they may want to use one of these
1048 handlers too, if just for developer convenience.
1051 Because this is so very board-specific, and chip-specific, no examples
1053 Instead, look at the board config files distributed with OpenOCD.
1054 If you have a boot loader, its source code may also be useful.
1057 Some of this code could probably be shared between different boards.
1058 For example, setting up a DRAM controller often doesn't differ by
1059 much except the bus width (16 bits or 32?) and memory timings, so a
1060 reusable TCL procedure loaded by the @file{target.cfg} file might take
1061 those as parameters.
1062 Similarly with oscillator, PLL, and clock setup;
1063 and disabling the watchdog.
1064 Structure the code cleanly, and provide comments to help
1065 the next developer doing such work.
1066 (@emph{You might be that next person} trying to reuse init code!)
1068 The last thing normally done in a @code{reset-init} handler is probing
1069 whatever flash memory was configured. For most chips that needs to be
1070 done while the associated target is halted, either because JTAG memory
1071 access uses the CPU or to prevent conflicting CPU access.
1073 @subsection JTAG Clock Rate
1075 Before your @code{reset-init} handler has set up
1076 the PLLs and clocking, you may need to run with
1077 a low JTAG clock rate.
1079 Then you'd increase that rate after your handler has
1080 made it possible to use the faster JTAG clock.
1081 When the initial low speed is board-specific, for example
1082 because it depends on a board-specific oscillator speed, then
1083 you should probably set it up in the board config file;
1084 if it's target-specific, it belongs in the target config file.
1086 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1087 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1088 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1089 Consult chip documentation to determine the peak JTAG clock rate,
1090 which might be less than that.
1093 On most ARMs, JTAG clock detection is coupled to the core clock, so
1094 software using a @option{wait for interrupt} operation blocks JTAG access.
1095 Adaptive clocking provides a partial workaround, but a more complete
1096 solution just avoids using that instruction with JTAG debuggers.
1099 If the board supports adaptive clocking, use the @command{jtag_rclk}
1100 command, in case your board is used with JTAG adapter which
1101 also supports it. Otherwise use @command{jtag_khz}.
1102 Set the slow rate at the beginning of the reset sequence,
1103 and the faster rate as soon as the clocks are at full speed.
1105 @section Target Config Files
1106 @cindex config file, target
1107 @cindex target config file
1109 Board config files communicate with target config files using
1110 naming conventions as described above, and may source one or
1111 more target config files like this:
1114 source [find target/FOOBAR.cfg]
1117 The point of a target config file is to package everything
1118 about a given chip that board config files need to know.
1119 In summary the target files should contain
1123 @item Add TAPs to the scan chain
1124 @item Add CPU targets (includes GDB support)
1125 @item CPU/Chip/CPU-Core specific features
1129 As a rule of thumb, a target file sets up only one chip.
1130 For a microcontroller, that will often include a single TAP,
1131 which is a CPU needing a GDB target, and its on-chip flash.
1133 More complex chips may include multiple TAPs, and the target
1134 config file may need to define them all before OpenOCD
1135 can talk to the chip.
1136 For example, some phone chips have JTAG scan chains that include
1137 an ARM core for operating system use, a DSP,
1138 another ARM core embedded in an image processing engine,
1139 and other processing engines.
1141 @subsection Default Value Boiler Plate Code
1143 All target configuration files should start with code like this,
1144 letting board config files express environment-specific
1145 differences in how things should be set up.
1148 # Boards may override chip names, perhaps based on role,
1149 # but the default should match what the vendor uses
1150 if @{ [info exists CHIPNAME] @} @{
1151 set _CHIPNAME $CHIPNAME
1153 set _CHIPNAME sam7x256
1156 # ONLY use ENDIAN with targets that can change it.
1157 if @{ [info exists ENDIAN] @} @{
1163 # TAP identifiers may change as chips mature, for example with
1164 # new revision fields (the "3" here). Pick a good default; you
1165 # can pass several such identifiers to the "jtag newtap" command.
1166 if @{ [info exists CPUTAPID ] @} @{
1167 set _CPUTAPID $CPUTAPID
1169 set _CPUTAPID 0x3f0f0f0f
1172 @c but 0x3f0f0f0f is for an str73x part ...
1174 @emph{Remember:} Board config files may include multiple target
1175 config files, or the same target file multiple times
1176 (changing at least @code{CHIPNAME}).
1178 Likewise, the target configuration file should define
1179 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1180 use it later on when defining debug targets:
1183 set _TARGETNAME $_CHIPNAME.cpu
1184 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1187 @subsection Adding TAPs to the Scan Chain
1188 After the ``defaults'' are set up,
1189 add the TAPs on each chip to the JTAG scan chain.
1190 @xref{TAP Declaration}, and the naming convention
1193 In the simplest case the chip has only one TAP,
1194 probably for a CPU or FPGA.
1195 The config file for the Atmel AT91SAM7X256
1196 looks (in part) like this:
1199 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
1200 -expected-id $_CPUTAPID
1203 A board with two such at91sam7 chips would be able
1204 to source such a config file twice, with different
1205 values for @code{CHIPNAME}, so
1206 it adds a different TAP each time.
1208 If there are one or more nonzero @option{-expected-id} values,
1209 OpenOCD attempts to verify the actual tap id against those values.
1210 It will issue error messages if there is mismatch, which
1211 can help to pinpoint problems in OpenOCD configurations.
1214 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1215 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1216 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1217 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1218 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1221 There are more complex examples too, with chips that have
1222 multiple TAPs. Ones worth looking at include:
1225 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1226 plus a JRC to enable them
1227 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1228 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1229 is not currently used)
1232 @subsection Add CPU targets
1234 After adding a TAP for a CPU, you should set it up so that
1235 GDB and other commands can use it.
1236 @xref{CPU Configuration}.
1237 For the at91sam7 example above, the command can look like this;
1238 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1239 to little endian, and this chip doesn't support changing that.
1242 set _TARGETNAME $_CHIPNAME.cpu
1243 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1246 Work areas are small RAM areas associated with CPU targets.
1247 They are used by OpenOCD to speed up downloads,
1248 and to download small snippets of code to program flash chips.
1249 If the chip includes a form of ``on-chip-ram'' - and many do - define
1250 a work area if you can.
1251 Again using the at91sam7 as an example, this can look like:
1254 $_TARGETNAME configure -work-area-phys 0x00200000 \
1255 -work-area-size 0x4000 -work-area-backup 0
1258 @subsection Chip Reset Setup
1260 As a rule, you should put the @command{reset_config} command
1261 into the board file. Most things you think you know about a
1262 chip can be tweaked by the board.
1264 Some chips have specific ways the TRST and SRST signals are
1265 managed. In the unusual case that these are @emph{chip specific}
1266 and can never be changed by board wiring, they could go here.
1268 Some chips need special attention during reset handling if
1269 they're going to be used with JTAG.
1270 An example might be needing to send some commands right
1271 after the target's TAP has been reset, providing a
1272 @code{reset-deassert-post} event handler that writes a chip
1273 register to report that JTAG debugging is being done.
1275 JTAG clocking constraints often change during reset, and in
1276 some cases target config files (rather than board config files)
1277 are the right places to handle some of those issues.
1278 For example, immediately after reset most chips run using a
1279 slower clock than they will use later.
1280 That means that after reset (and potentially, as OpenOCD
1281 first starts up) they must use a slower JTAG clock rate
1282 than they will use later.
1285 @quotation Important
1286 When you are debugging code that runs right after chip
1287 reset, getting these issues right is critical.
1288 In particular, if you see intermittent failures when
1289 OpenOCD verifies the scan chain after reset,
1290 look at how you are setting up JTAG clocking.
1293 @subsection ARM Core Specific Hacks
1295 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1296 special high speed download features - enable it.
1298 If present, the MMU, the MPU and the CACHE should be disabled.
1300 Some ARM cores are equipped with trace support, which permits
1301 examination of the instruction and data bus activity. Trace
1302 activity is controlled through an ``Embedded Trace Module'' (ETM)
1303 on one of the core's scan chains. The ETM emits voluminous data
1304 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
1305 If you are using an external trace port,
1306 configure it in your board config file.
1307 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1308 configure it in your target config file.
1311 etm config $_TARGETNAME 16 normal full etb
1312 etb config $_TARGETNAME $_CHIPNAME.etb
1315 @subsection Internal Flash Configuration
1317 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1319 @b{Never ever} in the ``target configuration file'' define any type of
1320 flash that is external to the chip. (For example a BOOT flash on
1321 Chip Select 0.) Such flash information goes in a board file - not
1322 the TARGET (chip) file.
1326 @item at91sam7x256 - has 256K flash YES enable it.
1327 @item str912 - has flash internal YES enable it.
1328 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1329 @item pxa270 - again - CS0 flash - it goes in the board file.
1332 @node Daemon Configuration
1333 @chapter Daemon Configuration
1334 @cindex initialization
1335 The commands here are commonly found in the openocd.cfg file and are
1336 used to specify what TCP/IP ports are used, and how GDB should be
1339 @anchor{Configuration Stage}
1340 @section Configuration Stage
1341 @cindex configuration stage
1342 @cindex config command
1344 When the OpenOCD server process starts up, it enters a
1345 @emph{configuration stage} which is the only time that
1346 certain commands, @emph{configuration commands}, may be issued.
1347 In this manual, the definition of a configuration command is
1348 presented as a @emph{Config Command}, not as a @emph{Command}
1349 which may be issued interactively.
1351 Those configuration commands include declaration of TAPs,
1353 the interface used for JTAG communication,
1354 and other basic setup.
1355 The server must leave the configuration stage before it
1356 may access or activate TAPs.
1357 After it leaves this stage, configuration commands may no
1360 The first thing OpenOCD does after leaving the configuration
1361 stage is to verify that it can talk to the scan chain
1362 (list of TAPs) which has been configured.
1363 It will warn if it doesn't find TAPs it expects to find,
1364 or finds TAPs that aren't supposed to be there.
1365 You should see no errors at this point.
1366 If you see errors, resolve them by correcting the
1367 commands you used to configure the server.
1368 Common errors include using an initial JTAG speed that's too
1369 fast, and not providing the right IDCODE values for the TAPs
1372 @deffn {Config Command} init
1373 This command terminates the configuration stage and
1374 enters the normal command mode. This can be useful to add commands to
1375 the startup scripts and commands such as resetting the target,
1376 programming flash, etc. To reset the CPU upon startup, add "init" and
1377 "reset" at the end of the config script or at the end of the OpenOCD
1378 command line using the @option{-c} command line switch.
1380 If this command does not appear in any startup/configuration file
1381 OpenOCD executes the command for you after processing all
1382 configuration files and/or command line options.
1384 @b{NOTE:} This command normally occurs at or near the end of your
1385 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1386 targets ready. For example: If your openocd.cfg file needs to
1387 read/write memory on your target, @command{init} must occur before
1388 the memory read/write commands. This includes @command{nand probe}.
1391 @anchor{TCP/IP Ports}
1392 @section TCP/IP Ports
1397 The OpenOCD server accepts remote commands in several syntaxes.
1398 Each syntax uses a different TCP/IP port, which you may specify
1399 only during configuration (before those ports are opened).
1401 For reasons including security, you may wish to prevent remote
1402 access using one or more of these ports.
1403 In such cases, just specify the relevant port number as zero.
1404 If you disable all access through TCP/IP, you will need to
1405 use the command line @option{-pipe} option.
1407 @deffn {Command} gdb_port (number)
1409 Specify or query the first port used for incoming GDB connections.
1410 The GDB port for the
1411 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1412 When not specified during the configuration stage,
1413 the port @var{number} defaults to 3333.
1414 When specified as zero, this port is not activated.
1417 @deffn {Command} tcl_port (number)
1418 Specify or query the port used for a simplified RPC
1419 connection that can be used by clients to issue TCL commands and get the
1420 output from the Tcl engine.
1421 Intended as a machine interface.
1422 When not specified during the configuration stage,
1423 the port @var{number} defaults to 6666.
1424 When specified as zero, this port is not activated.
1427 @deffn {Command} telnet_port (number)
1428 Specify or query the
1429 port on which to listen for incoming telnet connections.
1430 This port is intended for interaction with one human through TCL commands.
1431 When not specified during the configuration stage,
1432 the port @var{number} defaults to 4444.
1433 When specified as zero, this port is not activated.
1436 @anchor{GDB Configuration}
1437 @section GDB Configuration
1439 @cindex GDB configuration
1440 You can reconfigure some GDB behaviors if needed.
1441 The ones listed here are static and global.
1442 @xref{Target Configuration}, about configuring individual targets.
1443 @xref{Target Events}, about configuring target-specific event handling.
1445 @anchor{gdb_breakpoint_override}
1446 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
1447 Force breakpoint type for gdb @command{break} commands.
1448 This option supports GDB GUIs which don't
1449 distinguish hard versus soft breakpoints, if the default OpenOCD and
1450 GDB behaviour is not sufficient. GDB normally uses hardware
1451 breakpoints if the memory map has been set up for flash regions.
1454 @deffn {Config Command} gdb_detach (@option{resume}|@option{reset}|@option{halt}|@option{nothing})
1455 Configures what OpenOCD will do when GDB detaches from the daemon.
1456 Default behaviour is @option{resume}.
1459 @anchor{gdb_flash_program}
1460 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
1461 Set to @option{enable} to cause OpenOCD to program the flash memory when a
1462 vFlash packet is received.
1463 The default behaviour is @option{enable}.
1466 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
1467 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
1468 requested. GDB will then know when to set hardware breakpoints, and program flash
1469 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1470 for flash programming to work.
1471 Default behaviour is @option{enable}.
1472 @xref{gdb_flash_program}.
1475 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
1476 Specifies whether data aborts cause an error to be reported
1477 by GDB memory read packets.
1478 The default behaviour is @option{disable};
1479 use @option{enable} see these errors reported.
1482 @anchor{Event Polling}
1483 @section Event Polling
1485 Hardware debuggers are parts of asynchronous systems,
1486 where significant events can happen at any time.
1487 The OpenOCD server needs to detect some of these events,
1488 so it can report them to through TCL command line
1491 Examples of such events include:
1494 @item One of the targets can stop running ... maybe it triggers
1495 a code breakpoint or data watchpoint, or halts itself.
1496 @item Messages may be sent over ``debug message'' channels ... many
1497 targets support such messages sent over JTAG,
1498 for receipt by the person debugging or tools.
1499 @item Loss of power ... some adapters can detect these events.
1500 @item Resets not issued through JTAG ... such reset sources
1501 can include button presses or other system hardware, sometimes
1502 including the target itself (perhaps through a watchdog).
1503 @item Debug instrumentation sometimes supports event triggering
1504 such as ``trace buffer full'' (so it can quickly be emptied)
1505 or other signals (to correlate with code behavior).
1508 None of those events are signaled through standard JTAG signals.
1509 However, most conventions for JTAG connectors include voltage
1510 level and system reset (SRST) signal detection.
1511 Some connectors also include instrumentation signals, which
1512 can imply events when those signals are inputs.
1514 In general, OpenOCD needs to periodically check for those events,
1515 either by looking at the status of signals on the JTAG connector
1516 or by sending synchronous ``tell me your status'' JTAG requests
1517 to the various active targets.
1518 There is a command to manage and monitor that polling,
1519 which is normally done in the background.
1521 @deffn Command poll [@option{on}|@option{off}]
1522 Poll the current target for its current state.
1523 (Also, @pxref{target curstate}.)
1524 If that target is in debug mode, architecture
1525 specific information about the current state is printed.
1526 An optional parameter
1527 allows background polling to be enabled and disabled.
1529 You could use this from the TCL command shell, or
1530 from GDB using @command{monitor poll} command.
1533 background polling: on
1534 target state: halted
1535 target halted in ARM state due to debug-request, \
1536 current mode: Supervisor
1537 cpsr: 0x800000d3 pc: 0x11081bfc
1538 MMU: disabled, D-Cache: disabled, I-Cache: enabled
1543 @node Interface - Dongle Configuration
1544 @chapter Interface - Dongle Configuration
1545 @cindex config file, interface
1546 @cindex interface config file
1548 JTAG Adapters/Interfaces/Dongles are normally configured
1549 through commands in an interface configuration
1550 file which is sourced by your @file{openocd.cfg} file, or
1551 through a command line @option{-f interface/....cfg} option.
1554 source [find interface/olimex-jtag-tiny.cfg]
1558 OpenOCD what type of JTAG adapter you have, and how to talk to it.
1559 A few cases are so simple that you only need to say what driver to use:
1566 Most adapters need a bit more configuration than that.
1569 @section Interface Configuration
1571 The interface command tells OpenOCD what type of JTAG dongle you are
1572 using. Depending on the type of dongle, you may need to have one or
1573 more additional commands.
1575 @deffn {Config Command} {interface} name
1576 Use the interface driver @var{name} to connect to the
1580 @deffn Command {interface_list}
1581 List the interface drivers that have been built into
1582 the running copy of OpenOCD.
1585 @deffn Command {jtag interface}
1586 Returns the name of the interface driver being used.
1589 @section Interface Drivers
1591 Each of the interface drivers listed here must be explicitly
1592 enabled when OpenOCD is configured, in order to be made
1593 available at run time.
1595 @deffn {Interface Driver} {amt_jtagaccel}
1596 Amontec Chameleon in its JTAG Accelerator configuration,
1597 connected to a PC's EPP mode parallel port.
1598 This defines some driver-specific commands:
1600 @deffn {Config Command} {parport_port} number
1601 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1602 the number of the @file{/dev/parport} device.
1605 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
1606 Displays status of RTCK option.
1607 Optionally sets that option first.
1611 @deffn {Interface Driver} {arm-jtag-ew}
1612 Olimex ARM-JTAG-EW USB adapter
1613 This has one driver-specific command:
1615 @deffn Command {armjtagew_info}
1620 @deffn {Interface Driver} {at91rm9200}
1621 Supports bitbanged JTAG from the local system,
1622 presuming that system is an Atmel AT91rm9200
1623 and a specific set of GPIOs is used.
1624 @c command: at91rm9200_device NAME
1625 @c chooses among list of bit configs ... only one option
1628 @deffn {Interface Driver} {dummy}
1629 A dummy software-only driver for debugging.
1632 @deffn {Interface Driver} {ep93xx}
1633 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1636 @deffn {Interface Driver} {ft2232}
1637 FTDI FT2232 (USB) based devices over one of the userspace libraries.
1638 These interfaces have several commands, used to configure the driver
1639 before initializing the JTAG scan chain:
1641 @deffn {Config Command} {ft2232_device_desc} description
1642 Provides the USB device description (the @emph{iProduct string})
1643 of the FTDI FT2232 device. If not
1644 specified, the FTDI default value is used. This setting is only valid
1645 if compiled with FTD2XX support.
1648 @deffn {Config Command} {ft2232_serial} serial-number
1649 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
1650 in case the vendor provides unique IDs and more than one FT2232 device
1651 is connected to the host.
1652 If not specified, serial numbers are not considered.
1653 (Note that USB serial numbers can be arbitrary Unicode strings,
1654 and are not restricted to containing only decimal digits.)
1657 @deffn {Config Command} {ft2232_layout} name
1658 Each vendor's FT2232 device can use different GPIO signals
1659 to control output-enables, reset signals, and LEDs.
1660 Currently valid layout @var{name} values include:
1662 @item @b{axm0432_jtag} Axiom AXM-0432
1663 @item @b{comstick} Hitex STR9 comstick
1664 @item @b{cortino} Hitex Cortino JTAG interface
1665 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
1666 either for the local Cortex-M3 (SRST only)
1667 or in a passthrough mode (neither SRST nor TRST)
1668 @item @b{luminary_icdi} Luminary In-Circuit Debug Interface (ICDI) Board
1669 @item @b{flyswatter} Tin Can Tools Flyswatter
1670 @item @b{icebear} ICEbear JTAG adapter from Section 5
1671 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
1672 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
1673 @item @b{m5960} American Microsystems M5960
1674 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
1675 @item @b{oocdlink} OOCDLink
1676 @c oocdlink ~= jtagkey_prototype_v1
1677 @item @b{sheevaplug} Marvell Sheevaplug development kit
1678 @item @b{signalyzer} Xverve Signalyzer
1679 @item @b{stm32stick} Hitex STM32 Performance Stick
1680 @item @b{turtelizer2} egnite Software turtelizer2
1681 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
1685 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
1686 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1687 default values are used.
1688 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
1690 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1694 @deffn {Config Command} {ft2232_latency} ms
1695 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1696 ft2232_read() fails to return the expected number of bytes. This can be caused by
1697 USB communication delays and has proved hard to reproduce and debug. Setting the
1698 FT2232 latency timer to a larger value increases delays for short USB packets but it
1699 also reduces the risk of timeouts before receiving the expected number of bytes.
1700 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1703 For example, the interface config file for a
1704 Turtelizer JTAG Adapter looks something like this:
1708 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
1709 ft2232_layout turtelizer2
1710 ft2232_vid_pid 0x0403 0xbdc8
1714 @deffn {Interface Driver} {gw16012}
1715 Gateworks GW16012 JTAG programmer.
1716 This has one driver-specific command:
1718 @deffn {Config Command} {parport_port} number
1719 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1720 the number of the @file{/dev/parport} device.
1724 @deffn {Interface Driver} {jlink}
1725 Segger jlink USB adapter
1726 @c command: jlink_info
1728 @c command: jlink_hw_jtag (2|3)
1729 @c sets version 2 or 3
1732 @deffn {Interface Driver} {parport}
1733 Supports PC parallel port bit-banging cables:
1734 Wigglers, PLD download cable, and more.
1735 These interfaces have several commands, used to configure the driver
1736 before initializing the JTAG scan chain:
1738 @deffn {Config Command} {parport_cable} name
1739 The layout of the parallel port cable used to connect to the target.
1740 Currently valid cable @var{name} values include:
1743 @item @b{altium} Altium Universal JTAG cable.
1744 @item @b{arm-jtag} Same as original wiggler except SRST and
1745 TRST connections reversed and TRST is also inverted.
1746 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
1747 in configuration mode. This is only used to
1748 program the Chameleon itself, not a connected target.
1749 @item @b{dlc5} The Xilinx Parallel cable III.
1750 @item @b{flashlink} The ST Parallel cable.
1751 @item @b{lattice} Lattice ispDOWNLOAD Cable
1752 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
1754 Amontec's Chameleon Programmer. The new version available from
1755 the website uses the original Wiggler layout ('@var{wiggler}')
1756 @item @b{triton} The parallel port adapter found on the
1757 ``Karo Triton 1 Development Board''.
1758 This is also the layout used by the HollyGates design
1759 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1760 @item @b{wiggler} The original Wiggler layout, also supported by
1761 several clones, such as the Olimex ARM-JTAG
1762 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
1763 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
1767 @deffn {Config Command} {parport_port} number
1768 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1769 the @file{/dev/parport} device
1771 When using PPDEV to access the parallel port, use the number of the parallel port:
1772 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1773 you may encounter a problem.
1776 @deffn {Config Command} {parport_write_on_exit} (on|off)
1777 This will configure the parallel driver to write a known
1778 cable-specific value to the parallel interface on exiting OpenOCD
1781 For example, the interface configuration file for a
1782 classic ``Wiggler'' cable might look something like this:
1787 parport_cable wiggler
1791 @deffn {Interface Driver} {presto}
1792 ASIX PRESTO USB JTAG programmer.
1793 @c command: presto_serial str
1794 @c sets serial number
1797 @deffn {Interface Driver} {rlink}
1798 Raisonance RLink USB adapter
1801 @deffn {Interface Driver} {usbprog}
1802 usbprog is a freely programmable USB adapter.
1805 @deffn {Interface Driver} {vsllink}
1806 vsllink is part of Versaloon which is a versatile USB programmer.
1809 This defines quite a few driver-specific commands,
1810 which are not currently documented here.
1814 @deffn {Interface Driver} {ZY1000}
1815 This is the Zylin ZY1000 JTAG debugger.
1818 This defines some driver-specific commands,
1819 which are not currently documented here.
1822 @deffn Command power [@option{on}|@option{off}]
1823 Turn power switch to target on/off.
1824 No arguments: print status.
1831 JTAG clock setup is part of system setup.
1832 It @emph{does not belong with interface setup} since any interface
1833 only knows a few of the constraints for the JTAG clock speed.
1834 Sometimes the JTAG speed is
1835 changed during the target initialization process: (1) slow at
1836 reset, (2) program the CPU clocks, (3) run fast.
1837 Both the "slow" and "fast" clock rates are functions of the
1838 oscillators used, the chip, the board design, and sometimes
1839 power management software that may be active.
1841 The speed used during reset, and the scan chain verification which
1842 follows reset, can be adjusted using a @code{reset-start}
1843 target event handler.
1844 It can then be reconfigured to a faster speed by a
1845 @code{reset-init} target event handler after it reprograms those
1846 CPU clocks, or manually (if something else, such as a boot loader,
1847 sets up those clocks).
1848 @xref{Target Events}.
1849 When the initial low JTAG speed is a chip characteristic, perhaps
1850 because of a required oscillator speed, provide such a handler
1851 in the target config file.
1852 When that speed is a function of a board-specific characteristic
1853 such as which speed oscillator is used, it belongs in the board
1854 config file instead.
1855 In both cases it's safest to also set the initial JTAG clock rate
1856 to that same slow speed, so that OpenOCD never starts up using a
1857 clock speed that's faster than the scan chain can support.
1861 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
1864 If your system supports adaptive clocking (RTCK), configuring
1865 JTAG to use that is probably the most robust approach.
1866 However, it introduces delays to synchronize clocks; so it
1867 may not be the fastest solution.
1869 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
1870 instead of @command{jtag_khz}.
1872 @deffn {Command} jtag_khz max_speed_kHz
1873 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
1874 JTAG interfaces usually support a limited number of
1875 speeds. The speed actually used won't be faster
1876 than the speed specified.
1878 Chip data sheets generally include a top JTAG clock rate.
1879 The actual rate is often a function of a CPU core clock,
1880 and is normally less than that peak rate.
1881 For example, most ARM cores accept at most one sixth of the CPU clock.
1883 Speed 0 (khz) selects RTCK method.
1885 If your system uses RTCK, you won't need to change the
1886 JTAG clocking after setup.
1887 Not all interfaces, boards, or targets support ``rtck''.
1888 If the interface device can not
1889 support it, an error is returned when you try to use RTCK.
1892 @defun jtag_rclk fallback_speed_kHz
1893 @cindex adaptive clocking
1895 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
1896 If that fails (maybe the interface, board, or target doesn't
1897 support it), falls back to the specified frequency.
1899 # Fall back to 3mhz if RTCK is not supported
1904 @node Reset Configuration
1905 @chapter Reset Configuration
1906 @cindex Reset Configuration
1908 Every system configuration may require a different reset
1909 configuration. This can also be quite confusing.
1910 Resets also interact with @var{reset-init} event handlers,
1911 which do things like setting up clocks and DRAM, and
1912 JTAG clock rates. (@xref{JTAG Speed}.)
1913 They can also interact with JTAG routers.
1914 Please see the various board files for examples.
1917 To maintainers and integrators:
1918 Reset configuration touches several things at once.
1919 Normally the board configuration file
1920 should define it and assume that the JTAG adapter supports
1921 everything that's wired up to the board's JTAG connector.
1923 However, the target configuration file could also make note
1924 of something the silicon vendor has done inside the chip,
1925 which will be true for most (or all) boards using that chip.
1926 And when the JTAG adapter doesn't support everything, the
1927 user configuration file will need to override parts of
1928 the reset configuration provided by other files.
1931 @section Types of Reset
1933 There are many kinds of reset possible through JTAG, but
1934 they may not all work with a given board and adapter.
1935 That's part of why reset configuration can be error prone.
1939 @emph{System Reset} ... the @emph{SRST} hardware signal
1940 resets all chips connected to the JTAG adapter, such as processors,
1941 power management chips, and I/O controllers. Normally resets triggered
1942 with this signal behave exactly like pressing a RESET button.
1944 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
1945 just the TAP controllers connected to the JTAG adapter.
1946 Such resets should not be visible to the rest of the system; resetting a
1947 device's the TAP controller just puts that controller into a known state.
1949 @emph{Emulation Reset} ... many devices can be reset through JTAG
1950 commands. These resets are often distinguishable from system
1951 resets, either explicitly (a "reset reason" register says so)
1952 or implicitly (not all parts of the chip get reset).
1954 @emph{Other Resets} ... system-on-chip devices often support
1955 several other types of reset.
1956 You may need to arrange that a watchdog timer stops
1957 while debugging, preventing a watchdog reset.
1958 There may be individual module resets.
1961 In the best case, OpenOCD can hold SRST, then reset
1962 the TAPs via TRST and send commands through JTAG to halt the
1963 CPU at the reset vector before the 1st instruction is executed.
1964 Then when it finally releases the SRST signal, the system is
1965 halted under debugger control before any code has executed.
1966 This is the behavior required to support the @command{reset halt}
1967 and @command{reset init} commands; after @command{reset init} a
1968 board-specific script might do things like setting up DRAM.
1969 (@xref{Reset Command}.)
1971 @anchor{SRST and TRST Issues}
1972 @section SRST and TRST Issues
1974 Because SRST and TRST are hardware signals, they can have a
1975 variety of system-specific constraints. Some of the most
1980 @item @emph{Signal not available} ... Some boards don't wire
1981 SRST or TRST to the JTAG connector. Some JTAG adapters don't
1982 support such signals even if they are wired up.
1983 Use the @command{reset_config} @var{signals} options to say
1984 when either of those signals is not connected.
1985 When SRST is not available, your code might not be able to rely
1986 on controllers having been fully reset during code startup.
1987 Missing TRST is not a problem, since JTAG level resets can
1988 be triggered using with TMS signaling.
1990 @item @emph{Signals shorted} ... Sometimes a chip, board, or
1991 adapter will connect SRST to TRST, instead of keeping them separate.
1992 Use the @command{reset_config} @var{combination} options to say
1993 when those signals aren't properly independent.
1995 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
1996 delay circuit, reset supervisor, or on-chip features can extend
1997 the effect of a JTAG adapter's reset for some time after the adapter
1998 stops issuing the reset. For example, there may be chip or board
1999 requirements that all reset pulses last for at least a
2000 certain amount of time; and reset buttons commonly have
2001 hardware debouncing.
2002 Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
2003 commands to say when extra delays are needed.
2005 @item @emph{Drive type} ... Reset lines often have a pullup
2006 resistor, letting the JTAG interface treat them as open-drain
2007 signals. But that's not a requirement, so the adapter may need
2008 to use push/pull output drivers.
2009 Also, with weak pullups it may be advisable to drive
2010 signals to both levels (push/pull) to minimize rise times.
2011 Use the @command{reset_config} @var{trst_type} and
2012 @var{srst_type} parameters to say how to drive reset signals.
2014 @item @emph{Special initialization} ... Targets sometimes need
2015 special JTAG initialization sequences to handle chip-specific
2016 issues (not limited to errata).
2017 For example, certain JTAG commands might need to be issued while
2018 the system as a whole is in a reset state (SRST active)
2019 but the JTAG scan chain is usable (TRST inactive).
2020 (@xref{JTAG Commands}, where the @command{jtag_reset}
2021 command is presented.)
2024 There can also be other issues.
2025 Some devices don't fully conform to the JTAG specifications.
2026 Trivial system-specific differences are common, such as
2027 SRST and TRST using slightly different names.
2028 There are also vendors who distribute key JTAG documentation for
2029 their chips only to developers who have signed a Non-Disclosure
2032 Sometimes there are chip-specific extensions like a requirement to use
2033 the normally-optional TRST signal (precluding use of JTAG adapters which
2034 don't pass TRST through), or needing extra steps to complete a TAP reset.
2036 In short, SRST and especially TRST handling may be very finicky,
2037 needing to cope with both architecture and board specific constraints.
2039 @section Commands for Handling Resets
2041 @deffn {Command} jtag_nsrst_delay milliseconds
2042 How long (in milliseconds) OpenOCD should wait after deasserting
2043 nSRST (active-low system reset) before starting new JTAG operations.
2044 When a board has a reset button connected to SRST line it will
2045 probably have hardware debouncing, implying you should use this.
2048 @deffn {Command} jtag_ntrst_delay milliseconds
2049 How long (in milliseconds) OpenOCD should wait after deasserting
2050 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
2053 @deffn {Command} reset_config mode_flag ...
2054 This command tells OpenOCD the reset configuration
2055 of your combination of JTAG board and target in target
2056 configuration scripts.
2058 Information earlier in this section describes the kind of problems
2059 the command is intended to address (@pxref{SRST and TRST Issues}).
2060 As a rule this command belongs only in board config files,
2061 describing issues like @emph{board doesn't connect TRST};
2062 or in user config files, addressing limitations derived
2063 from a particular combination of interface and board.
2064 (An unlikely example would be using a TRST-only adapter
2065 with a board that only wires up SRST.)
2067 The @var{mode_flag} options can be specified in any order, but only one
2068 of each type -- @var{signals}, @var{combination}, @var{trst_type},
2069 and @var{srst_type} -- may be specified at a time.
2070 If you don't provide a new value for a given type, its previous
2071 value (perhaps the default) is unchanged.
2072 For example, this means that you don't need to say anything at all about
2073 TRST just to declare that if the JTAG adapter should want to drive SRST,
2074 it must explicitly be driven high (@option{srst_push_pull}).
2076 @var{signals} can specify which of the reset signals are connected.
2077 For example, If the JTAG interface provides SRST, but the board doesn't
2078 connect that signal properly, then OpenOCD can't use it.
2079 Possible values are @option{none} (the default), @option{trst_only},
2080 @option{srst_only} and @option{trst_and_srst}.
2083 If your board provides SRST or TRST through the JTAG connector,
2084 you must declare that or else those signals will not be used.
2087 The @var{combination} is an optional value specifying broken reset
2088 signal implementations.
2089 The default behaviour if no option given is @option{separate},
2090 indicating everything behaves normally.
2091 @option{srst_pulls_trst} states that the
2092 test logic is reset together with the reset of the system (e.g. Philips
2093 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
2094 the system is reset together with the test logic (only hypothetical, I
2095 haven't seen hardware with such a bug, and can be worked around).
2096 @option{combined} implies both @option{srst_pulls_trst} and
2097 @option{trst_pulls_srst}.
2099 @option{srst_gates_jtag} indicates that asserting SRST gates the
2100 JTAG clock. This means that no communication can happen on JTAG
2101 while SRST is asserted.
2103 The optional @var{trst_type} and @var{srst_type} parameters allow the
2104 driver mode of each reset line to be specified. These values only affect
2105 JTAG interfaces with support for different driver modes, like the Amontec
2106 JTAGkey and JTAGAccelerator. Also, they are necessarily ignored if the
2107 relevant signal (TRST or SRST) is not connected.
2109 Possible @var{trst_type} driver modes for the test reset signal (TRST)
2110 are @option{trst_push_pull} (default) and @option{trst_open_drain}.
2111 Most boards connect this signal to a pulldown, so the JTAG TAPs
2112 never leave reset unless they are hooked up to a JTAG adapter.
2114 Possible @var{srst_type} driver modes for the system reset signal (SRST)
2115 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
2116 Most boards connect this signal to a pullup, and allow the
2117 signal to be pulled low by various events including system
2118 powerup and pressing a reset button.
2122 @node TAP Declaration
2123 @chapter TAP Declaration
2124 @cindex TAP declaration
2125 @cindex TAP configuration
2127 @emph{Test Access Ports} (TAPs) are the core of JTAG.
2128 TAPs serve many roles, including:
2131 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
2132 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
2133 Others do it indirectly, making a CPU do it.
2134 @item @b{Program Download} Using the same CPU support GDB uses,
2135 you can initialize a DRAM controller, download code to DRAM, and then
2136 start running that code.
2137 @item @b{Boundary Scan} Most chips support boundary scan, which
2138 helps test for board assembly problems like solder bridges
2139 and missing connections
2142 OpenOCD must know about the active TAPs on your board(s).
2143 Setting up the TAPs is the core task of your configuration files.
2144 Once those TAPs are set up, you can pass their names to code
2145 which sets up CPUs and exports them as GDB targets,
2146 probes flash memory, performs low-level JTAG operations, and more.
2148 @section Scan Chains
2151 TAPs are part of a hardware @dfn{scan chain},
2152 which is daisy chain of TAPs.
2153 They also need to be added to
2154 OpenOCD's software mirror of that hardware list,
2155 giving each member a name and associating other data with it.
2156 Simple scan chains, with a single TAP, are common in
2157 systems with a single microcontroller or microprocessor.
2158 More complex chips may have several TAPs internally.
2159 Very complex scan chains might have a dozen or more TAPs:
2160 several in one chip, more in the next, and connecting
2161 to other boards with their own chips and TAPs.
2163 You can display the list with the @command{scan_chain} command.
2164 (Don't confuse this with the list displayed by the @command{targets}
2165 command, presented in the next chapter.
2166 That only displays TAPs for CPUs which are configured as
2168 Here's what the scan chain might look like for a chip more than one TAP:
2171 TapName Enabled IdCode Expected IrLen IrCap IrMask Instr
2172 -- ------------------ ------- ---------- ---------- ----- ----- ------ -----
2173 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0 0 0x...
2174 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x1 0 0xc
2175 2 omap5912.unknown Y 0x00000000 0x00000000 8 0 0 0xff
2178 Unfortunately those TAPs can't always be autoconfigured,
2179 because not all devices provide good support for that.
2180 JTAG doesn't require supporting IDCODE instructions, and
2181 chips with JTAG routers may not link TAPs into the chain
2182 until they are told to do so.
2184 The configuration mechanism currently supported by OpenOCD
2185 requires explicit configuration of all TAP devices using
2186 @command{jtag newtap} commands, as detailed later in this chapter.
2187 A command like this would declare one tap and name it @code{chip1.cpu}:
2190 jtag newtap chip1 cpu -irlen 7 -ircapture 0x01 -irmask 0x55
2193 Each target configuration file lists the TAPs provided
2195 Board configuration files combine all the targets on a board,
2197 Note that @emph{the order in which TAPs are declared is very important.}
2198 It must match the order in the JTAG scan chain, both inside
2199 a single chip and between them.
2200 @xref{FAQ TAP Order}.
2202 For example, the ST Microsystems STR912 chip has
2203 three separate TAPs@footnote{See the ST
2204 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
2205 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
2206 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
2207 To configure those taps, @file{target/str912.cfg}
2208 includes commands something like this:
2211 jtag newtap str912 flash ... params ...
2212 jtag newtap str912 cpu ... params ...
2213 jtag newtap str912 bs ... params ...
2216 Actual config files use a variable instead of literals like
2217 @option{str912}, to support more than one chip of each type.
2218 @xref{Config File Guidelines}.
2220 @deffn Command {jtag names}
2221 Returns the names of all current TAPs in the scan chain.
2222 Use @command{jtag cget} or @command{jtag tapisenabled}
2223 to examine attributes and state of each TAP.
2225 foreach t [jtag names] @{
2226 puts [format "TAP: %s\n" $t]
2231 @deffn Command {scan_chain}
2232 Displays the TAPs in the scan chain configuration,
2234 The set of TAPs listed by this command is fixed by
2235 exiting the OpenOCD configuration stage,
2236 but systems with a JTAG router can
2237 enable or disable TAPs dynamically.
2238 In addition to the enable/disable status, the contents of
2239 each TAP's instruction register can also change.
2242 @c FIXME! "jtag cget" should be able to return all TAP
2243 @c attributes, like "$target_name cget" does for targets.
2245 @c Probably want "jtag eventlist", and a "tap-reset" event
2246 @c (on entry to RESET state).
2251 When TAP objects are declared with @command{jtag newtap},
2252 a @dfn{dotted.name} is created for the TAP, combining the
2253 name of a module (usually a chip) and a label for the TAP.
2254 For example: @code{xilinx.tap}, @code{str912.flash},
2255 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
2256 Many other commands use that dotted.name to manipulate or
2257 refer to the TAP. For example, CPU configuration uses the
2258 name, as does declaration of NAND or NOR flash banks.
2260 The components of a dotted name should follow ``C'' symbol
2261 name rules: start with an alphabetic character, then numbers
2262 and underscores are OK; while others (including dots!) are not.
2265 In older code, JTAG TAPs were numbered from 0..N.
2266 This feature is still present.
2267 However its use is highly discouraged, and
2268 should not be relied on; it will be removed by mid-2010.
2269 Update all of your scripts to use TAP names rather than numbers,
2270 by paying attention to the runtime warnings they trigger.
2271 Using TAP numbers in target configuration scripts prevents
2272 reusing those scripts on boards with multiple targets.
2275 @section TAP Declaration Commands
2277 @c shouldn't this be(come) a {Config Command}?
2278 @anchor{jtag newtap}
2279 @deffn Command {jtag newtap} chipname tapname configparams...
2280 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
2281 and configured according to the various @var{configparams}.
2283 The @var{chipname} is a symbolic name for the chip.
2284 Conventionally target config files use @code{$_CHIPNAME},
2285 defaulting to the model name given by the chip vendor but
2288 @cindex TAP naming convention
2289 The @var{tapname} reflects the role of that TAP,
2290 and should follow this convention:
2293 @item @code{bs} -- For boundary scan if this is a seperate TAP;
2294 @item @code{cpu} -- The main CPU of the chip, alternatively
2295 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
2296 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
2297 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
2298 @item @code{flash} -- If the chip has a flash TAP, like the str912;
2299 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
2300 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
2301 @item @code{tap} -- Should be used only FPGA or CPLD like devices
2303 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
2304 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
2305 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
2306 a JTAG TAP; that TAP should be named @code{sdma}.
2309 Every TAP requires at least the following @var{configparams}:
2312 @item @code{-irlen} @var{NUMBER}
2313 @*The length in bits of the
2314 instruction register, such as 4 or 5 bits.
2317 A TAP may also provide optional @var{configparams}:
2320 @item @code{-disable} (or @code{-enable})
2321 @*Use the @code{-disable} parameter to flag a TAP which is not
2322 linked in to the scan chain after a reset using either TRST
2323 or the JTAG state machine's @sc{reset} state.
2324 You may use @code{-enable} to highlight the default state
2325 (the TAP is linked in).
2326 @xref{Enabling and Disabling TAPs}.
2327 @item @code{-expected-id} @var{number}
2328 @*A non-zero value represents the expected 32-bit IDCODE
2329 found when the JTAG chain is examined.
2330 These codes are not required by all JTAG devices.
2331 @emph{Repeat the option} as many times as required if more than one
2332 ID code could appear (for example, multiple versions).
2333 @item @code{-ircapture} @var{NUMBER}
2334 @*The bit pattern loaded by the TAP into the JTAG shift register
2335 on entry to the @sc{ircapture} state, such as 0x01.
2336 JTAG requires the two LSBs of this value to be 01.
2337 By default, @code{-ircapture} and @code{-irmask} are set
2338 up to verify that two-bit value; but you may provide
2339 additional bits, if you know them.
2340 @item @code{-irmask} @var{NUMBER}
2341 @*A mask used with @code{-ircapture}
2342 to verify that instruction scans work correctly.
2343 Such scans are not used by OpenOCD except to verify that
2344 there seems to be no problems with JTAG scan chain operations.
2348 @section Other TAP commands
2350 @c @deffn Command {jtag arp_init-reset}
2351 @c ... more or less "toggle TRST ... and SRST too, what the heck"
2353 @deffn Command {jtag cget} dotted.name @option{-event} name
2354 @deffnx Command {jtag configure} dotted.name @option{-event} name string
2355 At this writing this TAP attribute
2356 mechanism is used only for event handling.
2357 (It is not a direct analogue of the @code{cget}/@code{configure}
2358 mechanism for debugger targets.)
2359 See the next section for information about the available events.
2361 The @code{configure} subcommand assigns an event handler,
2362 a TCL string which is evaluated when the event is triggered.
2363 The @code{cget} subcommand returns that handler.
2371 OpenOCD includes two event mechanisms.
2372 The one presented here applies to all JTAG TAPs.
2373 The other applies to debugger targets,
2374 which are associated with certain TAPs.
2376 The TAP events currently defined are:
2379 @item @b{post-reset}
2380 @* The TAP has just completed a JTAG reset.
2381 For the first such handler called, the tap is still
2382 in the JTAG @sc{reset} state.
2383 Because the scan chain has not yet been verified, handlers for these events
2384 @emph{should not issue commands which scan the JTAG IR or DR registers}
2385 of any particular target.
2386 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
2387 @item @b{tap-disable}
2388 @* The TAP needs to be disabled. This handler should
2389 implement @command{jtag tapdisable}
2390 by issuing the relevant JTAG commands.
2391 @item @b{tap-enable}
2392 @* The TAP needs to be enabled. This handler should
2393 implement @command{jtag tapenable}
2394 by issuing the relevant JTAG commands.
2397 If you need some action after each JTAG reset, which isn't actually
2398 specific to any TAP (since you can't yet trust the scan chain's
2399 contents to be accurate), you might:
2402 jtag configure CHIP.jrc -event post-reset @{
2404 ... non-scan jtag operations to be done after reset
2409 @anchor{Enabling and Disabling TAPs}
2410 @section Enabling and Disabling TAPs
2411 @cindex JTAG Route Controller
2414 In some systems, a @dfn{JTAG Route Controller} (JRC)
2415 is used to enable and/or disable specific JTAG TAPs.
2416 Many ARM based chips from Texas Instruments include
2417 an ``ICEpick'' module, which is a JRC.
2418 Such chips include DaVinci and OMAP3 processors.
2420 A given TAP may not be visible until the JRC has been
2421 told to link it into the scan chain; and if the JRC
2422 has been told to unlink that TAP, it will no longer
2424 Such routers address problems that JTAG ``bypass mode''
2428 @item The scan chain can only go as fast as its slowest TAP.
2429 @item Having many TAPs slows instruction scans, since all
2430 TAPs receive new instructions.
2431 @item TAPs in the scan chain must be powered up, which wastes
2432 power and prevents debugging some power management mechanisms.
2435 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
2436 as implied by the existence of JTAG routers.
2437 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
2438 does include a kind of JTAG router functionality.
2440 @c (a) currently the event handlers don't seem to be able to
2441 @c fail in a way that could lead to no-change-of-state.
2443 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
2444 shown below, and is implemented using TAP event handlers.
2445 So for example, when defining a TAP for a CPU connected to
2446 a JTAG router, you should define TAP event handlers using
2447 code that looks something like this:
2450 jtag configure CHIP.cpu -event tap-enable @{
2451 echo "Enabling CPU TAP"
2452 ... jtag operations using CHIP.jrc
2454 jtag configure CHIP.cpu -event tap-disable @{
2455 echo "Disabling CPU TAP"
2456 ... jtag operations using CHIP.jrc
2460 @deffn Command {jtag tapdisable} dotted.name
2461 If necessary, disables the tap
2462 by sending it a @option{tap-disable} event.
2463 Returns the string "1" if the tap
2464 specified by @var{dotted.name} is enabled,
2465 and "0" if it is disbabled.
2468 @deffn Command {jtag tapenable} dotted.name
2469 If necessary, enables the tap
2470 by sending it a @option{tap-enable} event.
2471 Returns the string "1" if the tap
2472 specified by @var{dotted.name} is enabled,
2473 and "0" if it is disbabled.
2476 @deffn Command {jtag tapisenabled} dotted.name
2477 Returns the string "1" if the tap
2478 specified by @var{dotted.name} is enabled,
2479 and "0" if it is disbabled.
2482 Humans will find the @command{scan_chain} command more helpful
2483 for querying the state of the JTAG taps.
2487 @node CPU Configuration
2488 @chapter CPU Configuration
2491 This chapter discusses how to set up GDB debug targets for CPUs.
2492 You can also access these targets without GDB
2493 (@pxref{Architecture and Core Commands},
2494 and @ref{Target State handling}) and
2495 through various kinds of NAND and NOR flash commands.
2496 If you have multiple CPUs you can have multiple such targets.
2498 We'll start by looking at how to examine the targets you have,
2499 then look at how to add one more target and how to configure it.
2501 @section Target List
2502 @cindex target, current
2503 @cindex target, list
2505 All targets that have been set up are part of a list,
2506 where each member has a name.
2507 That name should normally be the same as the TAP name.
2508 You can display the list with the @command{targets}
2510 This display often has only one CPU; here's what it might
2511 look like with more than one:
2513 TargetName Type Endian TapName State
2514 -- ------------------ ---------- ------ ------------------ ------------
2515 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
2516 1 MyTarget cortex_m3 little mychip.foo tap-disabled
2519 One member of that list is the @dfn{current target}, which
2520 is implicitly referenced by many commands.
2521 It's the one marked with a @code{*} near the target name.
2522 In particular, memory addresses often refer to the address
2523 space seen by that current target.
2524 Commands like @command{mdw} (memory display words)
2525 and @command{flash erase_address} (erase NOR flash blocks)
2526 are examples; and there are many more.
2528 Several commands let you examine the list of targets:
2530 @deffn Command {target count}
2531 @emph{Note: target numbers are deprecated; don't use them.
2532 They will be removed shortly after August 2010, including this command.
2533 Iterate target using @command{target names}, not by counting.}
2535 Returns the number of targets, @math{N}.
2536 The highest numbered target is @math{N - 1}.
2538 set c [target count]
2539 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
2540 # Assuming you have created this function
2541 print_target_details $x
2546 @deffn Command {target current}
2547 Returns the name of the current target.
2550 @deffn Command {target names}
2551 Lists the names of all current targets in the list.
2553 foreach t [target names] @{
2554 puts [format "Target: %s\n" $t]
2559 @deffn Command {target number} number
2560 @emph{Note: target numbers are deprecated; don't use them.
2561 They will be removed shortly after August 2010, including this command.}
2563 The list of targets is numbered starting at zero.
2564 This command returns the name of the target at index @var{number}.
2566 set thename [target number $x]
2567 puts [format "Target %d is: %s\n" $x $thename]
2571 @c yep, "target list" would have been better.
2572 @c plus maybe "target setdefault".
2574 @deffn Command targets [name]
2575 @emph{Note: the name of this command is plural. Other target
2576 command names are singular.}
2578 With no parameter, this command displays a table of all known
2579 targets in a user friendly form.
2581 With a parameter, this command sets the current target to
2582 the given target with the given @var{name}; this is
2583 only relevant on boards which have more than one target.
2586 @section Target CPU Types and Variants
2591 Each target has a @dfn{CPU type}, as shown in the output of
2592 the @command{targets} command. You need to specify that type
2593 when calling @command{target create}.
2594 The CPU type indicates more than just the instruction set.
2595 It also indicates how that instruction set is implemented,
2596 what kind of debug support it integrates,
2597 whether it has an MMU (and if so, what kind),
2598 what core-specific commands may be available
2599 (@pxref{Architecture and Core Commands}),
2602 For some CPU types, OpenOCD also defines @dfn{variants} which
2603 indicate differences that affect their handling.
2604 For example, a particular implementation bug might need to be
2605 worked around in some chip versions.
2607 It's easy to see what target types are supported,
2608 since there's a command to list them.
2609 However, there is currently no way to list what target variants
2610 are supported (other than by reading the OpenOCD source code).
2612 @anchor{target types}
2613 @deffn Command {target types}
2614 Lists all supported target types.
2615 At this writing, the supported CPU types and variants are:
2618 @item @code{arm11} -- this is a generation of ARMv6 cores
2619 @item @code{arm720t} -- this is an ARMv4 core
2620 @item @code{arm7tdmi} -- this is an ARMv4 core
2621 @item @code{arm920t} -- this is an ARMv5 core
2622 @item @code{arm926ejs} -- this is an ARMv5 core
2623 @item @code{arm966e} -- this is an ARMv5 core
2624 @item @code{arm9tdmi} -- this is an ARMv4 core
2625 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
2626 (Support for this is preliminary and incomplete.)
2627 @item @code{cortex_a8} -- this is an ARMv7 core
2628 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
2629 compact Thumb2 instruction set. It supports one variant:
2631 @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
2632 This will cause OpenOCD to use a software reset rather than asserting
2633 SRST, to avoid a issue with clearing the debug registers.
2634 This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
2635 be detected and the normal reset behaviour used.
2637 @item @code{fa526} -- resembles arm920 (w/o Thumb)
2638 @item @code{feroceon} -- resembles arm926
2639 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
2641 @item @code{ejtag_srst} ... Use this when debugging targets that do not
2642 provide a functional SRST line on the EJTAG connector. This causes
2643 OpenOCD to instead use an EJTAG software reset command to reset the
2645 You still need to enable @option{srst} on the @command{reset_config}
2646 command to enable OpenOCD hardware reset functionality.
2648 @item @code{xscale} -- this is actually an architecture,
2649 not a CPU type. It is based on the ARMv5 architecture.
2650 There are several variants defined:
2652 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
2653 @code{pxa27x} ... instruction register length is 7 bits
2654 @item @code{pxa250}, @code{pxa255},
2655 @code{pxa26x} ... instruction register length is 5 bits
2660 To avoid being confused by the variety of ARM based cores, remember
2661 this key point: @emph{ARM is a technology licencing company}.
2662 (See: @url{http://www.arm.com}.)
2663 The CPU name used by OpenOCD will reflect the CPU design that was
2664 licenced, not a vendor brand which incorporates that design.
2665 Name prefixes like arm7, arm9, arm11, and cortex
2666 reflect design generations;
2667 while names like ARMv4, ARMv5, ARMv6, and ARMv7
2668 reflect an architecture version implemented by a CPU design.
2670 @anchor{Target Configuration}
2671 @section Target Configuration
2673 Before creating a ``target'', you must have added its TAP to the scan chain.
2674 When you've added that TAP, you will have a @code{dotted.name}
2675 which is used to set up the CPU support.
2676 The chip-specific configuration file will normally configure its CPU(s)
2677 right after it adds all of the chip's TAPs to the scan chain.
2679 Although you can set up a target in one step, it's often clearer if you
2680 use shorter commands and do it in two steps: create it, then configure
2682 All operations on the target after it's created will use a new
2683 command, created as part of target creation.
2685 The two main things to configure after target creation are
2686 a work area, which usually has target-specific defaults even
2687 if the board setup code overrides them later;
2688 and event handlers (@pxref{Target Events}), which tend
2689 to be much more board-specific.
2690 The key steps you use might look something like this
2693 target create MyTarget cortex_m3 -chain-position mychip.cpu
2694 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
2695 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
2696 $MyTarget configure -event reset-init @{ myboard_reinit @}
2699 You should specify a working area if you can; typically it uses some
2701 Such a working area can speed up many things, including bulk
2702 writes to target memory;
2703 flash operations like checking to see if memory needs to be erased;
2704 GDB memory checksumming;
2708 On more complex chips, the work area can become
2709 inaccessible when application code
2710 (such as an operating system)
2711 enables or disables the MMU.
2712 For example, the particular MMU context used to acess the virtual
2713 address will probably matter ... and that context might not have
2714 easy access to other addresses needed.
2715 At this writing, OpenOCD doesn't have much MMU intelligence.
2718 It's often very useful to define a @code{reset-init} event handler.
2719 For systems that are normally used with a boot loader,
2720 common tasks include updating clocks and initializing memory
2722 That may be needed to let you write the boot loader into flash,
2723 in order to ``de-brick'' your board; or to load programs into
2724 external DDR memory without having run the boot loader.
2726 @deffn Command {target create} target_name type configparams...
2727 This command creates a GDB debug target that refers to a specific JTAG tap.
2728 It enters that target into a list, and creates a new
2729 command (@command{@var{target_name}}) which is used for various
2730 purposes including additional configuration.
2733 @item @var{target_name} ... is the name of the debug target.
2734 By convention this should be the same as the @emph{dotted.name}
2735 of the TAP associated with this target, which must be specified here
2736 using the @code{-chain-position @var{dotted.name}} configparam.
2738 This name is also used to create the target object command,
2739 referred to here as @command{$target_name},
2740 and in other places the target needs to be identified.
2741 @item @var{type} ... specifies the target type. @xref{target types}.
2742 @item @var{configparams} ... all parameters accepted by
2743 @command{$target_name configure} are permitted.
2744 If the target is big-endian, set it here with @code{-endian big}.
2745 If the variant matters, set it here with @code{-variant}.
2747 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
2751 @deffn Command {$target_name configure} configparams...
2752 The options accepted by this command may also be
2753 specified as parameters to @command{target create}.
2754 Their values can later be queried one at a time by
2755 using the @command{$target_name cget} command.
2757 @emph{Warning:} changing some of these after setup is dangerous.
2758 For example, moving a target from one TAP to another;
2759 and changing its endianness or variant.
2763 @item @code{-chain-position} @var{dotted.name} -- names the TAP
2764 used to access this target.
2766 @item @code{-endian} (@option{big}|@option{little}) -- specifies
2767 whether the CPU uses big or little endian conventions
2769 @item @code{-event} @var{event_name} @var{event_body} --
2770 @xref{Target Events}.
2771 Note that this updates a list of named event handlers.
2772 Calling this twice with two different event names assigns
2773 two different handlers, but calling it twice with the
2774 same event name assigns only one handler.
2776 @item @code{-variant} @var{name} -- specifies a variant of the target,
2777 which OpenOCD needs to know about.
2779 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
2780 whether the work area gets backed up; by default,
2781 @emph{it is not backed up.}
2782 When possible, use a working_area that doesn't need to be backed up,
2783 since performing a backup slows down operations.
2784 For example, the beginning of an SRAM block is likely to
2785 be used by most build systems, but the end is often unused.
2787 @item @code{-work-area-size} @var{size} -- specify/set the work area
2789 @item @code{-work-area-phys} @var{address} -- set the work area
2790 base @var{address} to be used when no MMU is active.
2792 @item @code{-work-area-virt} @var{address} -- set the work area
2793 base @var{address} to be used when an MMU is active.
2798 @section Other $target_name Commands
2799 @cindex object command
2801 The Tcl/Tk language has the concept of object commands,
2802 and OpenOCD adopts that same model for targets.
2804 A good Tk example is a on screen button.
2805 Once a button is created a button
2806 has a name (a path in Tk terms) and that name is useable as a first
2807 class command. For example in Tk, one can create a button and later
2808 configure it like this:
2812 button .foobar -background red -command @{ foo @}
2814 .foobar configure -foreground blue
2816 set x [.foobar cget -background]
2818 puts [format "The button is %s" $x]
2821 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
2822 button, and its object commands are invoked the same way.
2825 str912.cpu mww 0x1234 0x42
2826 omap3530.cpu mww 0x5555 123
2829 The commands supported by OpenOCD target objects are:
2831 @deffn Command {$target_name arp_examine}
2832 @deffnx Command {$target_name arp_halt}
2833 @deffnx Command {$target_name arp_poll}
2834 @deffnx Command {$target_name arp_reset}
2835 @deffnx Command {$target_name arp_waitstate}
2836 Internal OpenOCD scripts (most notably @file{startup.tcl})
2837 use these to deal with specific reset cases.
2838 They are not otherwise documented here.
2841 @deffn Command {$target_name array2mem} arrayname width address count
2842 @deffnx Command {$target_name mem2array} arrayname width address count
2843 These provide an efficient script-oriented interface to memory.
2844 The @code{array2mem} primitive writes bytes, halfwords, or words;
2845 while @code{mem2array} reads them.
2846 In both cases, the TCL side uses an array, and
2847 the target side uses raw memory.
2849 The efficiency comes from enabling the use of
2850 bulk JTAG data transfer operations.
2851 The script orientation comes from working with data
2852 values that are packaged for use by TCL scripts;
2853 @command{mdw} type primitives only print data they retrieve,
2854 and neither store nor return those values.
2857 @item @var{arrayname} ... is the name of an array variable
2858 @item @var{width} ... is 8/16/32 - indicating the memory access size
2859 @item @var{address} ... is the target memory address
2860 @item @var{count} ... is the number of elements to process
2864 @deffn Command {$target_name cget} queryparm
2865 Each configuration parameter accepted by
2866 @command{$target_name configure}
2867 can be individually queried, to return its current value.
2868 The @var{queryparm} is a parameter name
2869 accepted by that command, such as @code{-work-area-phys}.
2870 There are a few special cases:
2873 @item @code{-event} @var{event_name} -- returns the handler for the
2874 event named @var{event_name}.
2875 This is a special case because setting a handler requires
2877 @item @code{-type} -- returns the target type.
2878 This is a special case because this is set using
2879 @command{target create} and can't be changed
2880 using @command{$target_name configure}.
2883 For example, if you wanted to summarize information about
2884 all the targets you might use something like this:
2887 foreach name [target names] @{
2888 set y [$name cget -endian]
2889 set z [$name cget -type]
2890 puts [format "Chip %d is %s, Endian: %s, type: %s" \
2896 @anchor{target curstate}
2897 @deffn Command {$target_name curstate}
2898 Displays the current target state:
2899 @code{debug-running},
2902 @code{running}, or @code{unknown}.
2903 (Also, @pxref{Event Polling}.)
2906 @deffn Command {$target_name eventlist}
2907 Displays a table listing all event handlers
2908 currently associated with this target.
2909 @xref{Target Events}.
2912 @deffn Command {$target_name invoke-event} event_name
2913 Invokes the handler for the event named @var{event_name}.
2914 (This is primarily intended for use by OpenOCD framework
2915 code, for example by the reset code in @file{startup.tcl}.)
2918 @deffn Command {$target_name mdw} addr [count]
2919 @deffnx Command {$target_name mdh} addr [count]
2920 @deffnx Command {$target_name mdb} addr [count]
2921 Display contents of address @var{addr}, as
2922 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
2923 or 8-bit bytes (@command{mdb}).
2924 If @var{count} is specified, displays that many units.
2925 (If you want to manipulate the data instead of displaying it,
2926 see the @code{mem2array} primitives.)
2929 @deffn Command {$target_name mww} addr word
2930 @deffnx Command {$target_name mwh} addr halfword
2931 @deffnx Command {$target_name mwb} addr byte
2932 Writes the specified @var{word} (32 bits),
2933 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
2934 at the specified address @var{addr}.
2937 @anchor{Target Events}
2938 @section Target Events
2939 @cindex target events
2941 At various times, certain things can happen, or you want them to happen.
2944 @item What should happen when GDB connects? Should your target reset?
2945 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
2946 @item During reset, do you need to write to certain memory locations
2947 to set up system clocks or
2948 to reconfigure the SDRAM?
2951 All of the above items can be addressed by target event handlers.
2952 These are set up by @command{$target_name configure -event} or
2953 @command{target create ... -event}.
2955 The programmer's model matches the @code{-command} option used in Tcl/Tk
2956 buttons and events. The two examples below act the same, but one creates
2957 and invokes a small procedure while the other inlines it.
2960 proc my_attach_proc @{ @} @{
2964 mychip.cpu configure -event gdb-attach my_attach_proc
2965 mychip.cpu configure -event gdb-attach @{
2971 The following target events are defined:
2974 @item @b{debug-halted}
2975 @* The target has halted for debug reasons (i.e.: breakpoint)
2976 @item @b{debug-resumed}
2977 @* The target has resumed (i.e.: gdb said run)
2978 @item @b{early-halted}
2979 @* Occurs early in the halt process
2981 @item @b{examine-end}
2982 @* Currently not used (goal: when JTAG examine completes)
2983 @item @b{examine-start}
2984 @* Currently not used (goal: when JTAG examine starts)
2986 @item @b{gdb-attach}
2987 @* When GDB connects
2988 @item @b{gdb-detach}
2989 @* When GDB disconnects
2991 @* When the target has halted and GDB is not doing anything (see early halt)
2992 @item @b{gdb-flash-erase-start}
2993 @* Before the GDB flash process tries to erase the flash
2994 @item @b{gdb-flash-erase-end}
2995 @* After the GDB flash process has finished erasing the flash
2996 @item @b{gdb-flash-write-start}
2997 @* Before GDB writes to the flash
2998 @item @b{gdb-flash-write-end}
2999 @* After GDB writes to the flash
3001 @* Before the target steps, gdb is trying to start/resume the target
3003 @* The target has halted
3005 @item @b{old-gdb_program_config}
3006 @* DO NOT USE THIS: Used internally
3007 @item @b{old-pre_resume}
3008 @* DO NOT USE THIS: Used internally
3010 @item @b{reset-assert-pre}
3011 @* Issued as part of @command{reset} processing
3012 after SRST and/or TRST were activated and deactivated,
3013 but before SRST alone is re-asserted on the tap.
3014 @item @b{reset-assert-post}
3015 @* Issued as part of @command{reset} processing
3016 when SRST is asserted on the tap.
3017 @item @b{reset-deassert-pre}
3018 @* Issued as part of @command{reset} processing
3019 when SRST is about to be released on the tap.
3020 @item @b{reset-deassert-post}
3021 @* Issued as part of @command{reset} processing
3022 when SRST has been released on the tap.
3024 @* Issued as the final step in @command{reset} processing.
3026 @item @b{reset-halt-post}
3027 @* Currently not used
3028 @item @b{reset-halt-pre}
3029 @* Currently not used
3031 @item @b{reset-init}
3032 @* Used by @b{reset init} command for board-specific initialization.
3033 This event fires after @emph{reset-deassert-post}.
3035 This is where you would configure PLLs and clocking, set up DRAM so
3036 you can download programs that don't fit in on-chip SRAM, set up pin
3037 multiplexing, and so on.
3038 (You may be able to switch to a fast JTAG clock rate here, after
3039 the target clocks are fully set up.)
3040 @item @b{reset-start}
3041 @* Issued as part of @command{reset} processing
3042 before either SRST or TRST are activated.
3044 This is the most robust place to switch to a low JTAG clock rate, if
3045 SRST disables PLLs needed to use a fast clock.
3047 @item @b{reset-wait-pos}
3048 @* Currently not used
3049 @item @b{reset-wait-pre}
3050 @* Currently not used
3052 @item @b{resume-start}
3053 @* Before any target is resumed
3054 @item @b{resume-end}
3055 @* After all targets have resumed
3059 @* Target has resumed
3063 @node Flash Commands
3064 @chapter Flash Commands
3066 OpenOCD has different commands for NOR and NAND flash;
3067 the ``flash'' command works with NOR flash, while
3068 the ``nand'' command works with NAND flash.
3069 This partially reflects different hardware technologies:
3070 NOR flash usually supports direct CPU instruction and data bus access,
3071 while data from a NAND flash must be copied to memory before it can be
3072 used. (SPI flash must also be copied to memory before use.)
3073 However, the documentation also uses ``flash'' as a generic term;
3074 for example, ``Put flash configuration in board-specific files''.
3078 @item Configure via the command @command{flash bank}
3079 @* Do this in a board-specific configuration file,
3080 passing parameters as needed by the driver.
3081 @item Operate on the flash via @command{flash subcommand}
3082 @* Often commands to manipulate the flash are typed by a human, or run
3083 via a script in some automated way. Common tasks include writing a
3084 boot loader, operating system, or other data.
3086 @* Flashing via GDB requires the flash be configured via ``flash
3087 bank'', and the GDB flash features be enabled.
3088 @xref{GDB Configuration}.
3091 Many CPUs have the ablity to ``boot'' from the first flash bank.
3092 This means that misprogramming that bank can ``brick'' a system,
3093 so that it can't boot.
3094 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
3095 board by (re)installing working boot firmware.
3097 @anchor{NOR Configuration}
3098 @section Flash Configuration Commands
3099 @cindex flash configuration
3101 @deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
3102 Configures a flash bank which provides persistent storage
3103 for addresses from @math{base} to @math{base + size - 1}.
3104 These banks will often be visible to GDB through the target's memory map.
3105 In some cases, configuring a flash bank will activate extra commands;
3106 see the driver-specific documentation.
3109 @item @var{driver} ... identifies the controller driver
3110 associated with the flash bank being declared.
3111 This is usually @code{cfi} for external flash, or else
3112 the name of a microcontroller with embedded flash memory.
3113 @xref{Flash Driver List}.
3114 @item @var{base} ... Base address of the flash chip.
3115 @item @var{size} ... Size of the chip, in bytes.
3116 For some drivers, this value is detected from the hardware.
3117 @item @var{chip_width} ... Width of the flash chip, in bytes;
3118 ignored for most microcontroller drivers.
3119 @item @var{bus_width} ... Width of the data bus used to access the
3120 chip, in bytes; ignored for most microcontroller drivers.
3121 @item @var{target} ... Names the target used to issue
3122 commands to the flash controller.
3123 @comment Actually, it's currently a controller-specific parameter...
3124 @item @var{driver_options} ... drivers may support, or require,
3125 additional parameters. See the driver-specific documentation
3126 for more information.
3129 This command is not available after OpenOCD initialization has completed.
3130 Use it in board specific configuration files, not interactively.
3134 @comment the REAL name for this command is "ocd_flash_banks"
3135 @comment less confusing would be: "flash list" (like "nand list")
3136 @deffn Command {flash banks}
3137 Prints a one-line summary of each device declared
3138 using @command{flash bank}, numbered from zero.
3139 Note that this is the @emph{plural} form;
3140 the @emph{singular} form is a very different command.
3143 @deffn Command {flash probe} num
3144 Identify the flash, or validate the parameters of the configured flash. Operation
3145 depends on the flash type.
3146 The @var{num} parameter is a value shown by @command{flash banks}.
3147 Most flash commands will implicitly @emph{autoprobe} the bank;
3148 flash drivers can distinguish between probing and autoprobing,
3149 but most don't bother.
3152 @section Erasing, Reading, Writing to Flash
3153 @cindex flash erasing
3154 @cindex flash reading
3155 @cindex flash writing
3156 @cindex flash programming
3158 One feature distinguishing NOR flash from NAND or serial flash technologies
3159 is that for read access, it acts exactly like any other addressible memory.
3160 This means you can use normal memory read commands like @command{mdw} or
3161 @command{dump_image} with it, with no special @command{flash} subcommands.
3162 @xref{Memory access}, and @ref{Image access}.
3164 Write access works differently. Flash memory normally needs to be erased
3165 before it's written. Erasing a sector turns all of its bits to ones, and
3166 writing can turn ones into zeroes. This is why there are special commands
3167 for interactive erasing and writing, and why GDB needs to know which parts
3168 of the address space hold NOR flash memory.
3171 Most of these erase and write commands leverage the fact that NOR flash
3172 chips consume target address space. They implicitly refer to the current
3173 JTAG target, and map from an address in that target's address space
3174 back to a flash bank.
3175 @comment In May 2009, those mappings may fail if any bank associated
3176 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
3177 A few commands use abstract addressing based on bank and sector numbers,
3178 and don't depend on searching the current target and its address space.
3179 Avoid confusing the two command models.
3182 Some flash chips implement software protection against accidental writes,
3183 since such buggy writes could in some cases ``brick'' a system.
3184 For such systems, erasing and writing may require sector protection to be
3186 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
3187 and AT91SAM7 on-chip flash.
3188 @xref{flash protect}.
3190 @anchor{flash erase_sector}
3191 @deffn Command {flash erase_sector} num first last
3192 Erase sectors in bank @var{num}, starting at sector @var{first}
3193 up to and including @var{last}.
3194 Sector numbering starts at 0.
3195 Providing a @var{last} sector of @option{last}
3196 specifies "to the end of the flash bank".
3197 The @var{num} parameter is a value shown by @command{flash banks}.
3200 @deffn Command {flash erase_address} address length
3201 Erase sectors starting at @var{address} for @var{length} bytes.
3202 The flash bank to use is inferred from the @var{address}, and
3203 the specified length must stay within that bank.
3204 As a special case, when @var{length} is zero and @var{address} is
3205 the start of the bank, the whole flash is erased.
3208 @deffn Command {flash fillw} address word length
3209 @deffnx Command {flash fillh} address halfword length
3210 @deffnx Command {flash fillb} address byte length
3211 Fills flash memory with the specified @var{word} (32 bits),
3212 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3213 starting at @var{address} and continuing
3214 for @var{length} units (word/halfword/byte).
3215 No erasure is done before writing; when needed, that must be done
3216 before issuing this command.
3217 Writes are done in blocks of up to 1024 bytes, and each write is
3218 verified by reading back the data and comparing it to what was written.
3219 The flash bank to use is inferred from the @var{address} of
3220 each block, and the specified length must stay within that bank.
3222 @comment no current checks for errors if fill blocks touch multiple banks!
3224 @anchor{flash write_bank}
3225 @deffn Command {flash write_bank} num filename offset
3226 Write the binary @file{filename} to flash bank @var{num},
3227 starting at @var{offset} bytes from the beginning of the bank.
3228 The @var{num} parameter is a value shown by @command{flash banks}.
3231 @anchor{flash write_image}
3232 @deffn Command {flash write_image} [erase] filename [offset] [type]
3233 Write the image @file{filename} to the current target's flash bank(s).
3234 A relocation @var{offset} may be specified, in which case it is added
3235 to the base address for each section in the image.
3236 The file [@var{type}] can be specified
3237 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
3238 @option{elf} (ELF file), @option{s19} (Motorola s19).
3239 @option{mem}, or @option{builder}.
3240 The relevant flash sectors will be erased prior to programming
3241 if the @option{erase} parameter is given.
3242 The flash bank to use is inferred from the @var{address} of
3246 @section Other Flash commands
3247 @cindex flash protection
3249 @deffn Command {flash erase_check} num
3250 Check erase state of sectors in flash bank @var{num},
3251 and display that status.
3252 The @var{num} parameter is a value shown by @command{flash banks}.
3253 This is the only operation that
3254 updates the erase state information displayed by @option{flash info}. That means you have
3255 to issue a @command{flash erase_check} command after erasing or programming the device
3256 to get updated information.
3257 (Code execution may have invalidated any state records kept by OpenOCD.)
3260 @deffn Command {flash info} num
3261 Print info about flash bank @var{num}
3262 The @var{num} parameter is a value shown by @command{flash banks}.
3263 The information includes per-sector protect status.
3266 @anchor{flash protect}
3267 @deffn Command {flash protect} num first last (@option{on}|@option{off})
3268 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
3269 in flash bank @var{num}, starting at sector @var{first}
3270 and continuing up to and including @var{last}.
3271 Providing a @var{last} sector of @option{last}
3272 specifies "to the end of the flash bank".
3273 The @var{num} parameter is a value shown by @command{flash banks}.
3276 @deffn Command {flash protect_check} num
3277 Check protection state of sectors in flash bank @var{num}.
3278 The @var{num} parameter is a value shown by @command{flash banks}.
3279 @comment @option{flash erase_sector} using the same syntax.
3282 @anchor{Flash Driver List}
3283 @section Flash Drivers, Options, and Commands
3284 As noted above, the @command{flash bank} command requires a driver name,
3285 and allows driver-specific options and behaviors.
3286 Some drivers also activate driver-specific commands.
3288 @subsection External Flash
3290 @deffn {Flash Driver} cfi
3291 @cindex Common Flash Interface
3293 The ``Common Flash Interface'' (CFI) is the main standard for
3294 external NOR flash chips, each of which connects to a
3295 specific external chip select on the CPU.
3296 Frequently the first such chip is used to boot the system.
3297 Your board's @code{reset-init} handler might need to
3298 configure additional chip selects using other commands (like: @command{mww} to
3299 configure a bus and its timings) , or
3300 perhaps configure a GPIO pin that controls the ``write protect'' pin
3302 The CFI driver can use a target-specific working area to significantly
3305 The CFI driver can accept the following optional parameters, in any order:
3308 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
3309 like AM29LV010 and similar types.
3310 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
3313 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
3314 wide on a sixteen bit bus:
3317 flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
3318 flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
3320 @c "cfi part_id" disabled
3323 @subsection Internal Flash (Microcontrollers)
3325 @deffn {Flash Driver} aduc702x
3326 The ADUC702x analog microcontrollers from Analog Devices
3327 include internal flash and use ARM7TDMI cores.
3328 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
3329 The setup command only requires the @var{target} argument
3330 since all devices in this family have the same memory layout.
3333 flash bank aduc702x 0 0 0 0 $_TARGETNAME
3337 @deffn {Flash Driver} at91sam3
3339 All members of the AT91SAM3 microcontroller family from
3340 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
3341 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
3342 that the driver was orginaly developed and tested using the
3343 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
3344 the family was cribbed from the data sheet. @emph{Note to future
3345 readers/updaters: Please remove this worrysome comment after other
3346 chips are confirmed.}
3348 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
3349 have one flash bank. In all cases the flash banks are at
3350 the following fixed locations:
3353 # Flash bank 0 - all chips
3354 flash bank at91sam3 0x00080000 0 1 1 $_TARGETNAME
3355 # Flash bank 1 - only 256K chips
3356 flash bank at91sam3 0x00100000 0 1 1 $_TARGETNAME
3359 Internally, the AT91SAM3 flash memory is organized as follows.
3360 Unlike the AT91SAM7 chips, these are not used as parameters
3361 to the @command{flash bank} command:
3364 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
3365 @item @emph{Bank Size:} 128K/64K Per flash bank
3366 @item @emph{Sectors:} 16 or 8 per bank
3367 @item @emph{SectorSize:} 8K Per Sector
3368 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
3371 The AT91SAM3 driver adds some additional commands:
3373 @deffn Command {at91sam3 gpnvm}
3374 @deffnx Command {at91sam3 gpnvm clear} number
3375 @deffnx Command {at91sam3 gpnvm set} number
3376 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
3377 With no parameters, @command{show} or @command{show all},
3378 shows the status of all GPNVM bits.
3379 With @command{show} @var{number}, displays that bit.
3381 With @command{set} @var{number} or @command{clear} @var{number},
3382 modifies that GPNVM bit.
3385 @deffn Command {at91sam3 info}
3386 This command attempts to display information about the AT91SAM3
3387 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
3388 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
3389 document id: doc6430A] and decodes the values. @emph{Second} it reads the
3390 various clock configuration registers and attempts to display how it
3391 believes the chip is configured. By default, the SLOWCLK is assumed to
3392 be 32768 Hz, see the command @command{at91sam3 slowclk}.
3395 @deffn Command {at91sam3 slowclk} [value]
3396 This command shows/sets the slow clock frequency used in the
3397 @command{at91sam3 info} command calculations above.
3401 @deffn {Flash Driver} at91sam7
3402 All members of the AT91SAM7 microcontroller family from Atmel include
3403 internal flash and use ARM7TDMI cores. The driver automatically
3404 recognizes a number of these chips using the chip identification
3405 register, and autoconfigures itself.
3408 flash bank at91sam7 0 0 0 0 $_TARGETNAME
3411 For chips which are not recognized by the controller driver, you must
3412 provide additional parameters in the following order:
3415 @item @var{chip_model} ... label used with @command{flash info}
3417 @item @var{sectors_per_bank}
3418 @item @var{pages_per_sector}
3419 @item @var{pages_size}
3420 @item @var{num_nvm_bits}
3421 @item @var{freq_khz} ... required if an external clock is provided,
3422 optional (but recommended) when the oscillator frequency is known
3425 It is recommended that you provide zeroes for all of those values
3426 except the clock frequency, so that everything except that frequency
3427 will be autoconfigured.
3428 Knowing the frequency helps ensure correct timings for flash access.
3430 The flash controller handles erases automatically on a page (128/256 byte)
3431 basis, so explicit erase commands are not necessary for flash programming.
3432 However, there is an ``EraseAll`` command that can erase an entire flash
3433 plane (of up to 256KB), and it will be used automatically when you issue
3434 @command{flash erase_sector} or @command{flash erase_address} commands.
3436 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
3437 Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
3438 bit for the processor. Each processor has a number of such bits,
3439 used for controlling features such as brownout detection (so they
3440 are not truly general purpose).
3442 This assumes that the first flash bank (number 0) is associated with
3443 the appropriate at91sam7 target.
3448 @deffn {Flash Driver} avr
3449 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
3450 @emph{The current implementation is incomplete.}
3451 @comment - defines mass_erase ... pointless given flash_erase_address
3454 @deffn {Flash Driver} ecosflash
3455 @emph{No idea what this is...}
3456 The @var{ecosflash} driver defines one mandatory parameter,
3457 the name of a modules of target code which is downloaded
3461 @deffn {Flash Driver} lpc2000
3462 Most members of the LPC1700 and LPC2000 microcontroller families from NXP
3463 include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
3466 There are LPC2000 devices which are not supported by the @var{lpc2000}
3468 The LPC2888 is supported by the @var{lpc288x} driver.
3469 The LPC29xx family is supported by the @var{lpc2900} driver.
3472 The @var{lpc2000} driver defines two mandatory and one optional parameters,
3473 which must appear in the following order:
3476 @item @var{variant} ... required, may be
3477 @var{lpc2000_v1} (older LPC21xx and LPC22xx)
3478 @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
3479 or @var{lpc1700} (LPC175x and LPC176x)
3480 @item @var{clock_kHz} ... the frequency, in kiloHertz,
3481 at which the core is running
3482 @item @var{calc_checksum} ... optional (but you probably want to provide this!),
3483 telling the driver to calculate a valid checksum for the exception vector table.
3486 LPC flashes don't require the chip and bus width to be specified.
3489 flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
3490 lpc2000_v2 14765 calc_checksum
3493 @deffn {Command} {lpc2000 part_id} bank
3494 Displays the four byte part identifier associated with
3495 the specified flash @var{bank}.
3499 @deffn {Flash Driver} lpc288x
3500 The LPC2888 microcontroller from NXP needs slightly different flash
3501 support from its lpc2000 siblings.
3502 The @var{lpc288x} driver defines one mandatory parameter,
3503 the programming clock rate in Hz.
3504 LPC flashes don't require the chip and bus width to be specified.
3507 flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
3511 @deffn {Flash Driver} lpc2900
3512 This driver supports the LPC29xx ARM968E based microcontroller family
3515 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
3516 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
3517 sector layout are auto-configured by the driver.
3518 The driver has one additional mandatory parameter: The CPU clock rate
3519 (in kHz) at the time the flash operations will take place. Most of the time this
3520 will not be the crystal frequency, but a higher PLL frequency. The
3521 @code{reset-init} event handler in the board script is usually the place where
3524 The driver rejects flashless devices (currently the LPC2930).
3526 The EEPROM in LPC2900 devices is not mapped directly into the address space.
3527 It must be handled much more like NAND flash memory, and will therefore be
3528 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
3530 Sector protection in terms of the LPC2900 is handled transparently. Every time a
3531 sector needs to be erased or programmed, it is automatically unprotected.
3532 What is shown as protection status in the @code{flash info} command, is
3533 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
3534 sector from ever being erased or programmed again. As this is an irreversible
3535 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
3536 and not by the standard @code{flash protect} command.
3538 Example for a 125 MHz clock frequency:
3540 flash bank lpc2900 0 0 0 0 $_TARGETNAME 125000
3543 Some @code{lpc2900}-specific commands are defined. In the following command list,
3544 the @var{bank} parameter is the bank number as obtained by the
3545 @code{flash banks} command.
3547 @deffn Command {lpc2900 signature} bank
3548 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
3549 content. This is a hardware feature of the flash block, hence the calculation is
3550 very fast. You may use this to verify the content of a programmed device against
3555 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
3559 @deffn Command {lpc2900 read_custom} bank filename
3560 Reads the 912 bytes of customer information from the flash index sector, and
3561 saves it to a file in binary format.
3564 lpc2900 read_custom 0 /path_to/customer_info.bin
3568 The index sector of the flash is a @emph{write-only} sector. It cannot be
3569 erased! In order to guard against unintentional write access, all following
3570 commands need to be preceeded by a successful call to the @code{password}
3573 @deffn Command {lpc2900 password} bank password
3574 You need to use this command right before each of the following commands:
3575 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
3576 @code{lpc2900 secure_jtag}.
3578 The password string is fixed to "I_know_what_I_am_doing".
3581 lpc2900 password 0 I_know_what_I_am_doing
3582 Potentially dangerous operation allowed in next command!
3586 @deffn Command {lpc2900 write_custom} bank filename type
3587 Writes the content of the file into the customer info space of the flash index
3588 sector. The filetype can be specified with the @var{type} field. Possible values
3589 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
3590 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
3591 contain a single section, and the contained data length must be exactly
3593 @quotation Attention
3594 This cannot be reverted! Be careful!
3598 lpc2900 write_custom 0 /path_to/customer_info.bin bin
3602 @deffn Command {lpc2900 secure_sector} bank first last
3603 Secures the sector range from @var{first} to @var{last} (including) against
3604 further program and erase operations. The sector security will be effective
3605 after the next power cycle.
3606 @quotation Attention
3607 This cannot be reverted! Be careful!
3609 Secured sectors appear as @emph{protected} in the @code{flash info} command.
3612 lpc2900 secure_sector 0 1 1
3614 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
3615 # 0: 0x00000000 (0x2000 8kB) not protected
3616 # 1: 0x00002000 (0x2000 8kB) protected
3617 # 2: 0x00004000 (0x2000 8kB) not protected
3621 @deffn Command {lpc2900 secure_jtag} bank
3622 Irreversibly disable the JTAG port. The new JTAG security setting will be
3623 effective after the next power cycle.
3624 @quotation Attention
3625 This cannot be reverted! Be careful!
3629 lpc2900 secure_jtag 0
3634 @deffn {Flash Driver} ocl
3635 @emph{No idea what this is, other than using some arm7/arm9 core.}
3638 flash bank ocl 0 0 0 0 $_TARGETNAME
3642 @deffn {Flash Driver} pic32mx
3643 The PIC32MX microcontrollers are based on the MIPS 4K cores,
3644 and integrate flash memory.
3645 @emph{The current implementation is incomplete.}
3648 flash bank pix32mx 0 0 0 0 $_TARGETNAME
3651 @comment numerous *disabled* commands are defined:
3652 @comment - chip_erase ... pointless given flash_erase_address
3653 @comment - lock, unlock ... pointless given protect on/off (yes?)
3654 @comment - pgm_word ... shouldn't bank be deduced from address??
3655 Some pic32mx-specific commands are defined:
3656 @deffn Command {pic32mx pgm_word} address value bank
3657 Programs the specified 32-bit @var{value} at the given @var{address}
3658 in the specified chip @var{bank}.
3662 @deffn {Flash Driver} stellaris
3663 All members of the Stellaris LM3Sxxx microcontroller family from
3665 include internal flash and use ARM Cortex M3 cores.
3666 The driver automatically recognizes a number of these chips using
3667 the chip identification register, and autoconfigures itself.
3668 @footnote{Currently there is a @command{stellaris mass_erase} command.
3669 That seems pointless since the same effect can be had using the
3670 standard @command{flash erase_address} command.}
3673 flash bank stellaris 0 0 0 0 $_TARGETNAME
3677 @deffn {Flash Driver} stm32x
3678 All members of the STM32 microcontroller family from ST Microelectronics
3679 include internal flash and use ARM Cortex M3 cores.
3680 The driver automatically recognizes a number of these chips using
3681 the chip identification register, and autoconfigures itself.
3684 flash bank stm32x 0 0 0 0 $_TARGETNAME
3687 Some stm32x-specific commands
3688 @footnote{Currently there is a @command{stm32x mass_erase} command.
3689 That seems pointless since the same effect can be had using the
3690 standard @command{flash erase_address} command.}
3693 @deffn Command {stm32x lock} num
3694 Locks the entire stm32 device.
3695 The @var{num} parameter is a value shown by @command{flash banks}.
3698 @deffn Command {stm32x unlock} num
3699 Unlocks the entire stm32 device.
3700 The @var{num} parameter is a value shown by @command{flash banks}.
3703 @deffn Command {stm32x options_read} num
3704 Read and display the stm32 option bytes written by
3705 the @command{stm32x options_write} command.
3706 The @var{num} parameter is a value shown by @command{flash banks}.
3709 @deffn Command {stm32x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
3710 Writes the stm32 option byte with the specified values.
3711 The @var{num} parameter is a value shown by @command{flash banks}.
3715 @deffn {Flash Driver} str7x
3716 All members of the STR7 microcontroller family from ST Microelectronics
3717 include internal flash and use ARM7TDMI cores.
3718 The @var{str7x} driver defines one mandatory parameter, @var{variant},
3719 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
3722 flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
3725 @deffn Command {str7x disable_jtag} bank
3726 Activate the Debug/Readout protection mechanism
3727 for the specified flash bank.
3731 @deffn {Flash Driver} str9x
3732 Most members of the STR9 microcontroller family from ST Microelectronics
3733 include internal flash and use ARM966E cores.
3734 The str9 needs the flash controller to be configured using
3735 the @command{str9x flash_config} command prior to Flash programming.
3738 flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
3739 str9x flash_config 0 4 2 0 0x80000
3742 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
3743 Configures the str9 flash controller.
3744 The @var{num} parameter is a value shown by @command{flash banks}.
3747 @item @var{bbsr} - Boot Bank Size register
3748 @item @var{nbbsr} - Non Boot Bank Size register
3749 @item @var{bbadr} - Boot Bank Start Address register
3750 @item @var{nbbadr} - Boot Bank Start Address register
3756 @deffn {Flash Driver} tms470
3757 Most members of the TMS470 microcontroller family from Texas Instruments
3758 include internal flash and use ARM7TDMI cores.
3759 This driver doesn't require the chip and bus width to be specified.
3761 Some tms470-specific commands are defined:
3763 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
3764 Saves programming keys in a register, to enable flash erase and write commands.
3767 @deffn Command {tms470 osc_mhz} clock_mhz
3768 Reports the clock speed, which is used to calculate timings.
3771 @deffn Command {tms470 plldis} (0|1)
3772 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
3777 @subsection str9xpec driver
3780 Here is some background info to help
3781 you better understand how this driver works. OpenOCD has two flash drivers for
3785 Standard driver @option{str9x} programmed via the str9 core. Normally used for
3786 flash programming as it is faster than the @option{str9xpec} driver.
3788 Direct programming @option{str9xpec} using the flash controller. This is an
3789 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
3790 core does not need to be running to program using this flash driver. Typical use
3791 for this driver is locking/unlocking the target and programming the option bytes.
3794 Before we run any commands using the @option{str9xpec} driver we must first disable
3795 the str9 core. This example assumes the @option{str9xpec} driver has been
3796 configured for flash bank 0.
3798 # assert srst, we do not want core running
3799 # while accessing str9xpec flash driver
3801 # turn off target polling
3804 str9xpec enable_turbo 0
3806 str9xpec options_read 0
3807 # re-enable str9 core
3808 str9xpec disable_turbo 0
3812 The above example will read the str9 option bytes.
3813 When performing a unlock remember that you will not be able to halt the str9 - it
3814 has been locked. Halting the core is not required for the @option{str9xpec} driver
3815 as mentioned above, just issue the commands above manually or from a telnet prompt.
3817 @deffn {Flash Driver} str9xpec
3818 Only use this driver for locking/unlocking the device or configuring the option bytes.
3819 Use the standard str9 driver for programming.
3820 Before using the flash commands the turbo mode must be enabled using the
3821 @command{str9xpec enable_turbo} command.
3823 Several str9xpec-specific commands are defined:
3825 @deffn Command {str9xpec disable_turbo} num
3826 Restore the str9 into JTAG chain.
3829 @deffn Command {str9xpec enable_turbo} num
3830 Enable turbo mode, will simply remove the str9 from the chain and talk
3831 directly to the embedded flash controller.
3834 @deffn Command {str9xpec lock} num
3835 Lock str9 device. The str9 will only respond to an unlock command that will
3839 @deffn Command {str9xpec part_id} num
3840 Prints the part identifier for bank @var{num}.
3843 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
3844 Configure str9 boot bank.
3847 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
3848 Configure str9 lvd source.
3851 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
3852 Configure str9 lvd threshold.
3855 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
3856 Configure str9 lvd reset warning source.
3859 @deffn Command {str9xpec options_read} num
3860 Read str9 option bytes.
3863 @deffn Command {str9xpec options_write} num
3864 Write str9 option bytes.
3867 @deffn Command {str9xpec unlock} num
3876 @subsection mFlash Configuration
3877 @cindex mFlash Configuration
3879 @deffn {Config Command} {mflash bank} soc base RST_pin target
3880 Configures a mflash for @var{soc} host bank at
3882 The pin number format depends on the host GPIO naming convention.
3883 Currently, the mflash driver supports s3c2440 and pxa270.
3885 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
3888 mflash bank s3c2440 0x10000000 1b 0
3891 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
3894 mflash bank pxa270 0x08000000 43 0
3898 @subsection mFlash commands
3899 @cindex mFlash commands
3901 @deffn Command {mflash config pll} frequency
3902 Configure mflash PLL.
3903 The @var{frequency} is the mflash input frequency, in Hz.
3904 Issuing this command will erase mflash's whole internal nand and write new pll.
3905 After this command, mflash needs power-on-reset for normal operation.
3906 If pll was newly configured, storage and boot(optional) info also need to be update.
3909 @deffn Command {mflash config boot}
3910 Configure bootable option.
3911 If bootable option is set, mflash offer the first 8 sectors
3915 @deffn Command {mflash config storage}
3916 Configure storage information.
3917 For the normal storage operation, this information must be
3921 @deffn Command {mflash dump} num filename offset size
3922 Dump @var{size} bytes, starting at @var{offset} bytes from the
3923 beginning of the bank @var{num}, to the file named @var{filename}.
3926 @deffn Command {mflash probe}
3930 @deffn Command {mflash write} num filename offset
3931 Write the binary file @var{filename} to mflash bank @var{num}, starting at
3932 @var{offset} bytes from the beginning of the bank.
3935 @node NAND Flash Commands
3936 @chapter NAND Flash Commands
3939 Compared to NOR or SPI flash, NAND devices are inexpensive
3940 and high density. Today's NAND chips, and multi-chip modules,
3941 commonly hold multiple GigaBytes of data.
3943 NAND chips consist of a number of ``erase blocks'' of a given
3944 size (such as 128 KBytes), each of which is divided into a
3945 number of pages (of perhaps 512 or 2048 bytes each). Each
3946 page of a NAND flash has an ``out of band'' (OOB) area to hold
3947 Error Correcting Code (ECC) and other metadata, usually 16 bytes
3948 of OOB for every 512 bytes of page data.
3950 One key characteristic of NAND flash is that its error rate
3951 is higher than that of NOR flash. In normal operation, that
3952 ECC is used to correct and detect errors. However, NAND
3953 blocks can also wear out and become unusable; those blocks
3954 are then marked "bad". NAND chips are even shipped from the
3955 manufacturer with a few bad blocks. The highest density chips
3956 use a technology (MLC) that wears out more quickly, so ECC
3957 support is increasingly important as a way to detect blocks
3958 that have begun to fail, and help to preserve data integrity
3959 with techniques such as wear leveling.
3961 Software is used to manage the ECC. Some controllers don't
3962 support ECC directly; in those cases, software ECC is used.
3963 Other controllers speed up the ECC calculations with hardware.
3964 Single-bit error correction hardware is routine. Controllers
3965 geared for newer MLC chips may correct 4 or more errors for
3966 every 512 bytes of data.
3968 You will need to make sure that any data you write using
3969 OpenOCD includes the apppropriate kind of ECC. For example,
3970 that may mean passing the @code{oob_softecc} flag when
3971 writing NAND data, or ensuring that the correct hardware
3974 The basic steps for using NAND devices include:
3976 @item Declare via the command @command{nand device}
3977 @* Do this in a board-specific configuration file,
3978 passing parameters as needed by the controller.
3979 @item Configure each device using @command{nand probe}.
3980 @* Do this only after the associated target is set up,
3981 such as in its reset-init script or in procures defined
3982 to access that device.
3983 @item Operate on the flash via @command{nand subcommand}
3984 @* Often commands to manipulate the flash are typed by a human, or run
3985 via a script in some automated way. Common task include writing a
3986 boot loader, operating system, or other data needed to initialize or
3990 @b{NOTE:} At the time this text was written, the largest NAND
3991 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
3992 This is because the variables used to hold offsets and lengths
3993 are only 32 bits wide.
3994 (Larger chips may work in some cases, unless an offset or length
3995 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
3996 Some larger devices will work, since they are actually multi-chip
3997 modules with two smaller chips and individual chipselect lines.
3999 @anchor{NAND Configuration}
4000 @section NAND Configuration Commands
4001 @cindex NAND configuration
4003 NAND chips must be declared in configuration scripts,
4004 plus some additional configuration that's done after
4005 OpenOCD has initialized.
4007 @deffn {Config Command} {nand device} controller target [configparams...]
4008 Declares a NAND device, which can be read and written to
4009 after it has been configured through @command{nand probe}.
4010 In OpenOCD, devices are single chips; this is unlike some
4011 operating systems, which may manage multiple chips as if
4012 they were a single (larger) device.
4013 In some cases, configuring a device will activate extra
4014 commands; see the controller-specific documentation.
4016 @b{NOTE:} This command is not available after OpenOCD
4017 initialization has completed. Use it in board specific
4018 configuration files, not interactively.
4021 @item @var{controller} ... identifies the controller driver
4022 associated with the NAND device being declared.
4023 @xref{NAND Driver List}.
4024 @item @var{target} ... names the target used when issuing
4025 commands to the NAND controller.
4026 @comment Actually, it's currently a controller-specific parameter...
4027 @item @var{configparams} ... controllers may support, or require,
4028 additional parameters. See the controller-specific documentation
4029 for more information.
4033 @deffn Command {nand list}
4034 Prints a summary of each device declared
4035 using @command{nand device}, numbered from zero.
4036 Note that un-probed devices show no details.
4039 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
4040 blocksize: 131072, blocks: 8192
4041 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
4042 blocksize: 131072, blocks: 8192
4047 @deffn Command {nand probe} num
4048 Probes the specified device to determine key characteristics
4049 like its page and block sizes, and how many blocks it has.
4050 The @var{num} parameter is the value shown by @command{nand list}.
4051 You must (successfully) probe a device before you can use
4052 it with most other NAND commands.
4055 @section Erasing, Reading, Writing to NAND Flash
4057 @deffn Command {nand dump} num filename offset length [oob_option]
4058 @cindex NAND reading
4059 Reads binary data from the NAND device and writes it to the file,
4060 starting at the specified offset.
4061 The @var{num} parameter is the value shown by @command{nand list}.
4063 Use a complete path name for @var{filename}, so you don't depend
4064 on the directory used to start the OpenOCD server.
4066 The @var{offset} and @var{length} must be exact multiples of the
4067 device's page size. They describe a data region; the OOB data
4068 associated with each such page may also be accessed.
4070 @b{NOTE:} At the time this text was written, no error correction
4071 was done on the data that's read, unless raw access was disabled
4072 and the underlying NAND controller driver had a @code{read_page}
4073 method which handled that error correction.
4075 By default, only page data is saved to the specified file.
4076 Use an @var{oob_option} parameter to save OOB data:
4078 @item no oob_* parameter
4079 @*Output file holds only page data; OOB is discarded.
4080 @item @code{oob_raw}
4081 @*Output file interleaves page data and OOB data;
4082 the file will be longer than "length" by the size of the
4083 spare areas associated with each data page.
4084 Note that this kind of "raw" access is different from
4085 what's implied by @command{nand raw_access}, which just
4086 controls whether a hardware-aware access method is used.
4087 @item @code{oob_only}
4088 @*Output file has only raw OOB data, and will
4089 be smaller than "length" since it will contain only the
4090 spare areas associated with each data page.
4094 @deffn Command {nand erase} num [offset length]
4095 @cindex NAND erasing
4096 @cindex NAND programming
4097 Erases blocks on the specified NAND device, starting at the
4098 specified @var{offset} and continuing for @var{length} bytes.
4099 Both of those values must be exact multiples of the device's
4100 block size, and the region they specify must fit entirely in the chip.
4101 If those parameters are not specified,
4102 the whole NAND chip will be erased.
4103 The @var{num} parameter is the value shown by @command{nand list}.
4105 @b{NOTE:} This command will try to erase bad blocks, when told
4106 to do so, which will probably invalidate the manufacturer's bad
4108 For the remainder of the current server session, @command{nand info}
4109 will still report that the block ``is'' bad.
4112 @deffn Command {nand write} num filename offset [option...]
4113 @cindex NAND writing
4114 @cindex NAND programming
4115 Writes binary data from the file into the specified NAND device,
4116 starting at the specified offset. Those pages should already
4117 have been erased; you can't change zero bits to one bits.
4118 The @var{num} parameter is the value shown by @command{nand list}.
4120 Use a complete path name for @var{filename}, so you don't depend
4121 on the directory used to start the OpenOCD server.
4123 The @var{offset} must be an exact multiple of the device's page size.
4124 All data in the file will be written, assuming it doesn't run
4125 past the end of the device.
4126 Only full pages are written, and any extra space in the last
4127 page will be filled with 0xff bytes. (That includes OOB data,
4128 if that's being written.)
4130 @b{NOTE:} At the time this text was written, bad blocks are
4131 ignored. That is, this routine will not skip bad blocks,
4132 but will instead try to write them. This can cause problems.
4134 Provide at most one @var{option} parameter. With some
4135 NAND drivers, the meanings of these parameters may change
4136 if @command{nand raw_access} was used to disable hardware ECC.
4138 @item no oob_* parameter
4139 @*File has only page data, which is written.
4140 If raw acccess is in use, the OOB area will not be written.
4141 Otherwise, if the underlying NAND controller driver has
4142 a @code{write_page} routine, that routine may write the OOB
4143 with hardware-computed ECC data.
4144 @item @code{oob_only}
4145 @*File has only raw OOB data, which is written to the OOB area.
4146 Each page's data area stays untouched. @i{This can be a dangerous
4147 option}, since it can invalidate the ECC data.
4148 You may need to force raw access to use this mode.
4149 @item @code{oob_raw}
4150 @*File interleaves data and OOB data, both of which are written
4151 If raw access is enabled, the data is written first, then the
4153 Otherwise, if the underlying NAND controller driver has
4154 a @code{write_page} routine, that routine may modify the OOB
4155 before it's written, to include hardware-computed ECC data.
4156 @item @code{oob_softecc}
4157 @*File has only page data, which is written.
4158 The OOB area is filled with 0xff, except for a standard 1-bit
4159 software ECC code stored in conventional locations.
4160 You might need to force raw access to use this mode, to prevent
4161 the underlying driver from applying hardware ECC.
4162 @item @code{oob_softecc_kw}
4163 @*File has only page data, which is written.
4164 The OOB area is filled with 0xff, except for a 4-bit software ECC
4165 specific to the boot ROM in Marvell Kirkwood SoCs.
4166 You might need to force raw access to use this mode, to prevent
4167 the underlying driver from applying hardware ECC.
4171 @section Other NAND commands
4172 @cindex NAND other commands
4174 @deffn Command {nand check_bad_blocks} [offset length]
4175 Checks for manufacturer bad block markers on the specified NAND
4176 device. If no parameters are provided, checks the whole
4177 device; otherwise, starts at the specified @var{offset} and
4178 continues for @var{length} bytes.
4179 Both of those values must be exact multiples of the device's
4180 block size, and the region they specify must fit entirely in the chip.
4181 The @var{num} parameter is the value shown by @command{nand list}.
4183 @b{NOTE:} Before using this command you should force raw access
4184 with @command{nand raw_access enable} to ensure that the underlying
4185 driver will not try to apply hardware ECC.
4188 @deffn Command {nand info} num
4189 The @var{num} parameter is the value shown by @command{nand list}.
4190 This prints the one-line summary from "nand list", plus for
4191 devices which have been probed this also prints any known
4192 status for each block.
4195 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
4196 Sets or clears an flag affecting how page I/O is done.
4197 The @var{num} parameter is the value shown by @command{nand list}.
4199 This flag is cleared (disabled) by default, but changing that
4200 value won't affect all NAND devices. The key factor is whether
4201 the underlying driver provides @code{read_page} or @code{write_page}
4202 methods. If it doesn't provide those methods, the setting of
4203 this flag is irrelevant; all access is effectively ``raw''.
4205 When those methods exist, they are normally used when reading
4206 data (@command{nand dump} or reading bad block markers) or
4207 writing it (@command{nand write}). However, enabling
4208 raw access (setting the flag) prevents use of those methods,
4209 bypassing hardware ECC logic.
4210 @i{This can be a dangerous option}, since writing blocks
4211 with the wrong ECC data can cause them to be marked as bad.
4214 @anchor{NAND Driver List}
4215 @section NAND Drivers, Options, and Commands
4216 As noted above, the @command{nand device} command allows
4217 driver-specific options and behaviors.
4218 Some controllers also activate controller-specific commands.
4220 @deffn {NAND Driver} davinci
4221 This driver handles the NAND controllers found on DaVinci family
4222 chips from Texas Instruments.
4223 It takes three extra parameters:
4224 address of the NAND chip;
4225 hardware ECC mode to use (@option{hwecc1},
4226 @option{hwecc4}, @option{hwecc4_infix});
4227 address of the AEMIF controller on this processor.
4229 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
4231 All DaVinci processors support the single-bit ECC hardware,
4232 and newer ones also support the four-bit ECC hardware.
4233 The @code{write_page} and @code{read_page} methods are used
4234 to implement those ECC modes, unless they are disabled using
4235 the @command{nand raw_access} command.
4238 @deffn {NAND Driver} lpc3180
4239 These controllers require an extra @command{nand device}
4240 parameter: the clock rate used by the controller.
4241 @deffn Command {lpc3180 select} num [mlc|slc]
4242 Configures use of the MLC or SLC controller mode.
4243 MLC implies use of hardware ECC.
4244 The @var{num} parameter is the value shown by @command{nand list}.
4247 At this writing, this driver includes @code{write_page}
4248 and @code{read_page} methods. Using @command{nand raw_access}
4249 to disable those methods will prevent use of hardware ECC
4250 in the MLC controller mode, but won't change SLC behavior.
4252 @comment current lpc3180 code won't issue 5-byte address cycles
4254 @deffn {NAND Driver} orion
4255 These controllers require an extra @command{nand device}
4256 parameter: the address of the controller.
4258 nand device orion 0xd8000000
4260 These controllers don't define any specialized commands.
4261 At this writing, their drivers don't include @code{write_page}
4262 or @code{read_page} methods, so @command{nand raw_access} won't
4263 change any behavior.
4266 @deffn {NAND Driver} s3c2410
4267 @deffnx {NAND Driver} s3c2412
4268 @deffnx {NAND Driver} s3c2440
4269 @deffnx {NAND Driver} s3c2443
4270 These S3C24xx family controllers don't have any special
4271 @command{nand device} options, and don't define any
4272 specialized commands.
4273 At this writing, their drivers don't include @code{write_page}
4274 or @code{read_page} methods, so @command{nand raw_access} won't
4275 change any behavior.
4278 @node PLD/FPGA Commands
4279 @chapter PLD/FPGA Commands
4283 Programmable Logic Devices (PLDs) and the more flexible
4284 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
4285 OpenOCD can support programming them.
4286 Although PLDs are generally restrictive (cells are less functional, and
4287 there are no special purpose cells for memory or computational tasks),
4288 they share the same OpenOCD infrastructure.
4289 Accordingly, both are called PLDs here.
4291 @section PLD/FPGA Configuration and Commands
4293 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
4294 OpenOCD maintains a list of PLDs available for use in various commands.
4295 Also, each such PLD requires a driver.
4297 They are referenced by the number shown by the @command{pld devices} command,
4298 and new PLDs are defined by @command{pld device driver_name}.
4300 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
4301 Defines a new PLD device, supported by driver @var{driver_name},
4302 using the TAP named @var{tap_name}.
4303 The driver may make use of any @var{driver_options} to configure its
4307 @deffn {Command} {pld devices}
4308 Lists the PLDs and their numbers.
4311 @deffn {Command} {pld load} num filename
4312 Loads the file @file{filename} into the PLD identified by @var{num}.
4313 The file format must be inferred by the driver.
4316 @section PLD/FPGA Drivers, Options, and Commands
4318 Drivers may support PLD-specific options to the @command{pld device}
4319 definition command, and may also define commands usable only with
4320 that particular type of PLD.
4322 @deffn {FPGA Driver} virtex2
4323 Virtex-II is a family of FPGAs sold by Xilinx.
4324 It supports the IEEE 1532 standard for In-System Configuration (ISC).
4325 No driver-specific PLD definition options are used,
4326 and one driver-specific command is defined.
4328 @deffn {Command} {virtex2 read_stat} num
4329 Reads and displays the Virtex-II status register (STAT)
4334 @node General Commands
4335 @chapter General Commands
4338 The commands documented in this chapter here are common commands that
4339 you, as a human, may want to type and see the output of. Configuration type
4340 commands are documented elsewhere.
4344 @item @b{Source Of Commands}
4345 @* OpenOCD commands can occur in a configuration script (discussed
4346 elsewhere) or typed manually by a human or supplied programatically,
4347 or via one of several TCP/IP Ports.
4349 @item @b{From the human}
4350 @* A human should interact with the telnet interface (default port: 4444)
4351 or via GDB (default port 3333).
4353 To issue commands from within a GDB session, use the @option{monitor}
4354 command, e.g. use @option{monitor poll} to issue the @option{poll}
4355 command. All output is relayed through the GDB session.
4357 @item @b{Machine Interface}
4358 The Tcl interface's intent is to be a machine interface. The default Tcl
4363 @section Daemon Commands
4365 @deffn {Command} exit
4366 Exits the current telnet session.
4369 @c note EXTREMELY ANNOYING word wrap at column 75
4370 @c even when lines are e.g. 100+ columns ...
4371 @c coded in startup.tcl
4372 @deffn {Command} help [string]
4373 With no parameters, prints help text for all commands.
4374 Otherwise, prints each helptext containing @var{string}.
4375 Not every command provides helptext.
4378 @deffn Command sleep msec [@option{busy}]
4379 Wait for at least @var{msec} milliseconds before resuming.
4380 If @option{busy} is passed, busy-wait instead of sleeping.
4381 (This option is strongly discouraged.)
4382 Useful in connection with script files
4383 (@command{script} command and @command{target_name} configuration).
4386 @deffn Command shutdown
4387 Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
4390 @anchor{debug_level}
4391 @deffn Command debug_level [n]
4392 @cindex message level
4393 Display debug level.
4394 If @var{n} (from 0..3) is provided, then set it to that level.
4395 This affects the kind of messages sent to the server log.
4396 Level 0 is error messages only;
4397 level 1 adds warnings;
4398 level 2 adds informational messages;
4399 and level 3 adds debugging messages.
4400 The default is level 2, but that can be overridden on
4401 the command line along with the location of that log
4402 file (which is normally the server's standard output).
4406 @deffn Command fast (@option{enable}|@option{disable})
4408 Set default behaviour of OpenOCD to be "fast and dangerous".
4410 At this writing, this only affects the defaults for two ARM7/ARM9 parameters:
4411 fast memory access, and DCC downloads. Those parameters may still be
4412 individually overridden.
4414 The target specific "dangerous" optimisation tweaking options may come and go
4415 as more robust and user friendly ways are found to ensure maximum throughput
4416 and robustness with a minimum of configuration.
4418 Typically the "fast enable" is specified first on the command line:
4421 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
4425 @deffn Command echo message
4426 Logs a message at "user" priority.
4427 Output @var{message} to stdout.
4429 echo "Downloading kernel -- please wait"
4433 @deffn Command log_output [filename]
4434 Redirect logging to @var{filename};
4435 the initial log output channel is stderr.
4438 @anchor{Target State handling}
4439 @section Target State handling
4442 @cindex target initialization
4444 In this section ``target'' refers to a CPU configured as
4445 shown earlier (@pxref{CPU Configuration}).
4446 These commands, like many, implicitly refer to
4447 a current target which is used to perform the
4448 various operations. The current target may be changed
4449 by using @command{targets} command with the name of the
4450 target which should become current.
4452 @deffn Command reg [(number|name) [value]]
4453 Access a single register by @var{number} or by its @var{name}.
4455 @emph{With no arguments}:
4456 list all available registers for the current target,
4457 showing number, name, size, value, and cache status.
4459 @emph{With number/name}: display that register's value.
4461 @emph{With both number/name and value}: set register's value.
4463 Cores may have surprisingly many registers in their
4464 Debug and trace infrastructure:
4468 (0) r0 (/32): 0x0000D3C2 (dirty: 1, valid: 1)
4469 (1) r1 (/32): 0xFD61F31C (dirty: 0, valid: 1)
4470 (2) r2 (/32): 0x00022551 (dirty: 0, valid: 1)
4472 (164) ETM_CONTEXTID_COMPARATOR_MASK (/32): \
4473 0x00000000 (dirty: 0, valid: 0)
4478 @deffn Command halt [ms]
4479 @deffnx Command wait_halt [ms]
4480 The @command{halt} command first sends a halt request to the target,
4481 which @command{wait_halt} doesn't.
4482 Otherwise these behave the same: wait up to @var{ms} milliseconds,
4483 or 5 seconds if there is no parameter, for the target to halt
4484 (and enter debug mode).
4485 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
4488 On ARM cores, software using the @emph{wait for interrupt} operation
4489 often blocks the JTAG access needed by a @command{halt} command.
4490 This is because that operation also puts the core into a low
4491 power mode by gating the core clock;
4492 but the core clock is needed to detect JTAG clock transitions.
4494 One partial workaround uses adaptive clocking: when the core is
4495 interrupted the operation completes, then JTAG clocks are accepted
4496 at least until the interrupt handler completes.
4497 However, this workaround is often unusable since the processor, board,
4498 and JTAG adapter must all support adaptive JTAG clocking.
4499 Also, it can't work until an interrupt is issued.
4501 A more complete workaround is to not use that operation while you
4502 work with a JTAG debugger.
4503 Tasking environments generaly have idle loops where the body is the
4504 @emph{wait for interrupt} operation.
4505 (On older cores, it is a coprocessor action;
4506 newer cores have a @option{wfi} instruction.)
4507 Such loops can just remove that operation, at the cost of higher
4508 power consumption (because the CPU is needlessly clocked).
4513 @deffn Command resume [address]
4514 Resume the target at its current code position,
4515 or the optional @var{address} if it is provided.
4516 OpenOCD will wait 5 seconds for the target to resume.
4519 @deffn Command step [address]
4520 Single-step the target at its current code position,
4521 or the optional @var{address} if it is provided.
4524 @anchor{Reset Command}
4525 @deffn Command reset
4526 @deffnx Command {reset run}
4527 @deffnx Command {reset halt}
4528 @deffnx Command {reset init}
4529 Perform as hard a reset as possible, using SRST if possible.
4530 @emph{All defined targets will be reset, and target
4531 events will fire during the reset sequence.}
4533 The optional parameter specifies what should
4534 happen after the reset.
4535 If there is no parameter, a @command{reset run} is executed.
4536 The other options will not work on all systems.
4537 @xref{Reset Configuration}.
4540 @item @b{run} Let the target run
4541 @item @b{halt} Immediately halt the target
4542 @item @b{init} Immediately halt the target, and execute the reset-init script
4546 @deffn Command soft_reset_halt
4547 Requesting target halt and executing a soft reset. This is often used
4548 when a target cannot be reset and halted. The target, after reset is
4549 released begins to execute code. OpenOCD attempts to stop the CPU and
4550 then sets the program counter back to the reset vector. Unfortunately
4551 the code that was executed may have left the hardware in an unknown
4555 @section I/O Utilities
4557 These commands are available when
4558 OpenOCD is built with @option{--enable-ioutil}.
4559 They are mainly useful on embedded targets,
4561 Hosts with operating systems have complementary tools.
4563 @emph{Note:} there are several more such commands.
4565 @deffn Command append_file filename [string]*
4566 Appends the @var{string} parameters to
4567 the text file @file{filename}.
4568 Each string except the last one is followed by one space.
4569 The last string is followed by a newline.
4572 @deffn Command cat filename
4573 Reads and displays the text file @file{filename}.
4576 @deffn Command cp src_filename dest_filename
4577 Copies contents from the file @file{src_filename}
4578 into @file{dest_filename}.
4582 @emph{No description provided.}
4586 @emph{No description provided.}
4590 @emph{No description provided.}
4593 @deffn Command meminfo
4594 Display available RAM memory on OpenOCD host.
4595 Used in OpenOCD regression testing scripts.
4599 @emph{No description provided.}
4603 @emph{No description provided.}
4606 @deffn Command rm filename
4607 @c "rm" has both normal and Jim-level versions??
4608 Unlinks the file @file{filename}.
4611 @deffn Command trunc filename
4612 Removes all data in the file @file{filename}.
4615 @anchor{Memory access}
4616 @section Memory access commands
4617 @cindex memory access
4619 These commands allow accesses of a specific size to the memory
4620 system. Often these are used to configure the current target in some
4621 special way. For example - one may need to write certain values to the
4622 SDRAM controller to enable SDRAM.
4625 @item Use the @command{targets} (plural) command
4626 to change the current target.
4627 @item In system level scripts these commands are deprecated.
4628 Please use their TARGET object siblings to avoid making assumptions
4629 about what TAP is the current target, or about MMU configuration.
4632 @deffn Command mdw addr [count]
4633 @deffnx Command mdh addr [count]
4634 @deffnx Command mdb addr [count]
4635 Display contents of address @var{addr}, as
4636 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4637 or 8-bit bytes (@command{mdb}).
4638 If @var{count} is specified, displays that many units.
4639 (If you want to manipulate the data instead of displaying it,
4640 see the @code{mem2array} primitives.)
4643 @deffn Command mww addr word
4644 @deffnx Command mwh addr halfword
4645 @deffnx Command mwb addr byte
4646 Writes the specified @var{word} (32 bits),
4647 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4648 at the specified address @var{addr}.
4652 @anchor{Image access}
4653 @section Image loading commands
4654 @cindex image loading
4655 @cindex image dumping
4658 @deffn Command {dump_image} filename address size
4659 Dump @var{size} bytes of target memory starting at @var{address} to the
4660 binary file named @var{filename}.
4663 @deffn Command {fast_load}
4664 Loads an image stored in memory by @command{fast_load_image} to the
4665 current target. Must be preceeded by fast_load_image.
4668 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4669 Normally you should be using @command{load_image} or GDB load. However, for
4670 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
4671 host), storing the image in memory and uploading the image to the target
4672 can be a way to upload e.g. multiple debug sessions when the binary does not change.
4673 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
4674 memory, i.e. does not affect target. This approach is also useful when profiling
4675 target programming performance as I/O and target programming can easily be profiled
4680 @deffn Command {load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4681 Load image from file @var{filename} to target memory at @var{address}.
4682 The file format may optionally be specified
4683 (@option{bin}, @option{ihex}, or @option{elf})
4686 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
4687 Displays image section sizes and addresses
4688 as if @var{filename} were loaded into target memory
4689 starting at @var{address} (defaults to zero).
4690 The file format may optionally be specified
4691 (@option{bin}, @option{ihex}, or @option{elf})
4694 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4695 Verify @var{filename} against target memory starting at @var{address}.
4696 The file format may optionally be specified
4697 (@option{bin}, @option{ihex}, or @option{elf})
4698 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
4702 @section Breakpoint and Watchpoint commands
4706 CPUs often make debug modules accessible through JTAG, with
4707 hardware support for a handful of code breakpoints and data
4709 In addition, CPUs almost always support software breakpoints.
4711 @deffn Command {bp} [address len [@option{hw}]]
4712 With no parameters, lists all active breakpoints.
4713 Else sets a breakpoint on code execution starting
4714 at @var{address} for @var{length} bytes.
4715 This is a software breakpoint, unless @option{hw} is specified
4716 in which case it will be a hardware breakpoint.
4718 (@xref{arm9tdmi vector_catch}, or @pxref{xscale vector_catch},
4719 for similar mechanisms that do not consume hardware breakpoints.)
4722 @deffn Command {rbp} address
4723 Remove the breakpoint at @var{address}.
4726 @deffn Command {rwp} address
4727 Remove data watchpoint on @var{address}
4730 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
4731 With no parameters, lists all active watchpoints.
4732 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
4733 The watch point is an "access" watchpoint unless
4734 the @option{r} or @option{w} parameter is provided,
4735 defining it as respectively a read or write watchpoint.
4736 If a @var{value} is provided, that value is used when determining if
4737 the watchpoint should trigger. The value may be first be masked
4738 using @var{mask} to mark ``don't care'' fields.
4741 @section Misc Commands
4744 @deffn Command {profile} seconds filename
4745 Profiling samples the CPU's program counter as quickly as possible,
4746 which is useful for non-intrusive stochastic profiling.
4747 Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
4750 @deffn Command {version}
4751 Displays a string identifying the version of this OpenOCD server.
4754 @deffn Command {virt2phys} virtual_address
4755 Requests the current target to map the specified @var{virtual_address}
4756 to its corresponding physical address, and displays the result.
4759 @node Architecture and Core Commands
4760 @chapter Architecture and Core Commands
4761 @cindex Architecture Specific Commands
4762 @cindex Core Specific Commands
4764 Most CPUs have specialized JTAG operations to support debugging.
4765 OpenOCD packages most such operations in its standard command framework.
4766 Some of those operations don't fit well in that framework, so they are
4767 exposed here as architecture or implementation (core) specific commands.
4769 @anchor{ARM Hardware Tracing}
4770 @section ARM Hardware Tracing
4775 CPUs based on ARM cores may include standard tracing interfaces,
4776 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
4777 address and data bus trace records to a ``Trace Port''.
4781 Development-oriented boards will sometimes provide a high speed
4782 trace connector for collecting that data, when the particular CPU
4783 supports such an interface.
4784 (The standard connector is a 38-pin Mictor, with both JTAG
4785 and trace port support.)
4786 Those trace connectors are supported by higher end JTAG adapters
4787 and some logic analyzer modules; frequently those modules can
4788 buffer several megabytes of trace data.
4789 Configuring an ETM coupled to such an external trace port belongs
4790 in the board-specific configuration file.
4792 If the CPU doesn't provide an external interface, it probably
4793 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
4794 dedicated SRAM. 4KBytes is one common ETB size.
4795 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
4796 (target) configuration file, since it works the same on all boards.
4799 ETM support in OpenOCD doesn't seem to be widely used yet.
4802 ETM support may be buggy, and at least some @command{etm config}
4803 parameters should be detected by asking the ETM for them.
4804 It seems like a GDB hookup should be possible,
4805 as well as triggering trace on specific events
4806 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
4807 There should be GUI tools to manipulate saved trace data and help
4808 analyse it in conjunction with the source code.
4809 It's unclear how much of a common interface is shared
4810 with the current XScale trace support, or should be
4811 shared with eventual Nexus-style trace module support.
4812 At this writing (September 2009) only ARM7 and ARM9 support
4813 for ETM modules is available. The code should be able to
4814 work with some newer cores; but not all of them support
4815 this original style of JTAG access.
4818 @subsection ETM Configuration
4819 ETM setup is coupled with the trace port driver configuration.
4821 @deffn {Config Command} {etm config} target width mode clocking driver
4822 Declares the ETM associated with @var{target}, and associates it
4823 with a given trace port @var{driver}. @xref{Trace Port Drivers}.
4825 Several of the parameters must reflect the trace port configuration.
4826 The @var{width} must be either 4, 8, or 16.
4827 The @var{mode} must be @option{normal}, @option{multiplexted},
4828 or @option{demultiplexted}.
4829 The @var{clocking} must be @option{half} or @option{full}.
4832 You can see the ETM registers using the @command{reg} command.
4833 Not all possible registers are present in every ETM.
4834 Most of the registers are write-only, and are used to configure
4835 what CPU activities are traced.
4839 @deffn Command {etm info}
4840 Displays information about the current target's ETM.
4843 @deffn Command {etm status}
4844 Displays status of the current target's ETM:
4845 is the ETM idle, or is it collecting data?
4846 Did trace data overflow?
4850 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
4851 Displays what data that ETM will collect.
4852 If arguments are provided, first configures that data.
4853 When the configuration changes, tracing is stopped
4854 and any buffered trace data is invalidated.
4857 @item @var{type} ... one of
4858 @option{none} (save nothing),
4859 @option{data} (save data),
4860 @option{address} (save addresses),
4861 @option{all} (save data and addresses)
4862 @item @var{context_id_bits} ... 0, 8, 16, or 32
4863 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
4864 @item @var{branch_output} ... @option{enable} or @option{disable}
4868 @deffn Command {etm trigger_percent} percent
4869 @emph{Buggy and effectively a NOP ... @var{percent} from 2..100}
4872 @subsection ETM Trace Operation
4874 After setting up the ETM, you can use it to collect data.
4875 That data can be exported to files for later analysis.
4876 It can also be parsed with OpenOCD, for basic sanity checking.
4878 To configure what is being traced, you will need to write
4879 various trace registers using @command{reg ETM_*} commands.
4880 For the definitions of these registers, read ARM publication
4881 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
4882 Be aware that most of the relevant registers are write-only,
4883 and that ETM resources are limited. There are only a handful
4884 of address comparators, data comparators, counters, and so on.
4886 Examples of scenarios you might arrange to trace include:
4889 @item Code flow within a function, @emph{excluding} subroutines
4890 it calls. Use address range comparators to enable tracing
4891 for instruction access within that function's body.
4892 @item Code flow within a function, @emph{including} subroutines
4893 it calls. Use the sequencer and address comparators to activate
4894 tracing on an ``entered function'' state, then deactivate it by
4895 exiting that state when the function's exit code is invoked.
4896 @item Code flow starting at the fifth invocation of a function,
4897 combining one of the above models with a counter.
4898 @item CPU data accesses to the registers for a particular device,
4899 using address range comparators and the ViewData logic.
4900 @item Such data accesses only during IRQ handling, combining the above
4901 model with sequencer triggers which on entry and exit to the IRQ handler.
4902 @item @emph{... more}
4905 At this writing, September 2009, there are no Tcl utility
4906 procedures to help set up any common tracing scenarios.
4908 @deffn Command {etm analyze}
4909 Reads trace data into memory, if it wasn't already present.
4910 Decodes and prints the data that was collected.
4913 @deffn Command {etm dump} filename
4914 Stores the captured trace data in @file{filename}.
4917 @deffn Command {etm image} filename [base_address] [type]
4918 Opens an image file.
4921 @deffn Command {etm load} filename
4922 Loads captured trace data from @file{filename}.
4925 @deffn Command {etm start}
4926 Starts trace data collection.
4929 @deffn Command {etm stop}
4930 Stops trace data collection.
4933 @anchor{Trace Port Drivers}
4934 @subsection Trace Port Drivers
4936 To use an ETM trace port it must be associated with a driver.
4938 @deffn {Trace Port Driver} dummy
4939 Use the @option{dummy} driver if you are configuring an ETM that's
4940 not connected to anything (on-chip ETB or off-chip trace connector).
4941 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
4942 any trace data collection.}
4943 @deffn {Config Command} {etm_dummy config} target
4944 Associates the ETM for @var{target} with a dummy driver.
4948 @deffn {Trace Port Driver} etb
4949 Use the @option{etb} driver if you are configuring an ETM
4950 to use on-chip ETB memory.
4951 @deffn {Config Command} {etb config} target etb_tap
4952 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
4953 You can see the ETB registers using the @command{reg} command.
4957 @deffn {Trace Port Driver} oocd_trace
4958 This driver isn't available unless OpenOCD was explicitly configured
4959 with the @option{--enable-oocd_trace} option. You probably don't want
4960 to configure it unless you've built the appropriate prototype hardware;
4961 it's @emph{proof-of-concept} software.
4963 Use the @option{oocd_trace} driver if you are configuring an ETM that's
4964 connected to an off-chip trace connector.
4966 @deffn {Config Command} {oocd_trace config} target tty
4967 Associates the ETM for @var{target} with a trace driver which
4968 collects data through the serial port @var{tty}.
4971 @deffn Command {oocd_trace resync}
4972 Re-synchronizes with the capture clock.
4975 @deffn Command {oocd_trace status}
4976 Reports whether the capture clock is locked or not.
4981 @section ARMv4 and ARMv5 Architecture
4985 These commands are specific to ARM architecture v4 and v5,
4986 including all ARM7 or ARM9 systems and Intel XScale.
4987 They are available in addition to other core-specific
4988 commands that may be available.
4990 @deffn Command {armv4_5 core_state} [@option{arm}|@option{thumb}]
4991 Displays the core_state, optionally changing it to process
4992 either @option{arm} or @option{thumb} instructions.
4993 The target may later be resumed in the currently set core_state.
4994 (Processors may also support the Jazelle state, but
4995 that is not currently supported in OpenOCD.)
4998 @deffn Command {armv4_5 disassemble} address [count [@option{thumb}]]
5000 Disassembles @var{count} instructions starting at @var{address}.
5001 If @var{count} is not specified, a single instruction is disassembled.
5002 If @option{thumb} is specified, or the low bit of the address is set,
5003 Thumb (16-bit) instructions are used;
5004 else ARM (32-bit) instructions are used.
5005 (Processors may also support the Jazelle state, but
5006 those instructions are not currently understood by OpenOCD.)
5009 @deffn Command {armv4_5 reg}
5010 Display a table of all banked core registers, fetching the current value from every
5011 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
5015 @subsection ARM7 and ARM9 specific commands
5019 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
5020 ARM9TDMI, ARM920T or ARM926EJ-S.
5021 They are available in addition to the ARMv4/5 commands,
5022 and any other core-specific commands that may be available.
5024 @deffn Command {arm7_9 dbgrq} (@option{enable}|@option{disable})
5025 Control use of the EmbeddedIce DBGRQ signal to force entry into debug mode,
5026 instead of breakpoints. This should be
5027 safe for all but ARM7TDMI--S cores (like Philips LPC).
5028 This feature is enabled by default on most ARM9 cores,
5029 including ARM9TDMI, ARM920T, and ARM926EJ-S.
5032 @deffn Command {arm7_9 dcc_downloads} (@option{enable}|@option{disable})
5034 Control the use of the debug communications channel (DCC) to write larger (>128 byte)
5035 amounts of memory. DCC downloads offer a huge speed increase, but might be
5036 unsafe, especially with targets running at very low speeds. This command was introduced
5037 with OpenOCD rev. 60, and requires a few bytes of working area.
5040 @anchor{arm7_9 fast_memory_access}
5041 @deffn Command {arm7_9 fast_memory_access} (@option{enable}|@option{disable})
5042 Enable or disable memory writes and reads that don't check completion of
5043 the operation. This provides a huge speed increase, especially with USB JTAG
5044 cables (FT2232), but might be unsafe if used with targets running at very low
5045 speeds, like the 32kHz startup clock of an AT91RM9200.
5048 @deffn {Debug Command} {arm7_9 write_core_reg} num mode word
5049 @emph{This is intended for use while debugging OpenOCD; you probably
5052 Writes a 32-bit @var{word} to register @var{num} (from 0 to 16)
5053 as used in the specified @var{mode}
5054 (where e.g. mode 16 is "user" and mode 19 is "supervisor";
5055 the M4..M0 bits of the PSR).
5056 Registers 0..15 are the normal CPU registers such as r0(0), r1(1) ... pc(15).
5057 Register 16 is the mode-specific SPSR,
5058 unless the specified mode is 0xffffffff (32-bit all-ones)
5059 in which case register 16 is the CPSR.
5060 The write goes directly to the CPU, bypassing the register cache.
5063 @deffn {Debug Command} {arm7_9 write_xpsr} word (@option{0}|@option{1})
5064 @emph{This is intended for use while debugging OpenOCD; you probably
5067 If the second parameter is zero, writes @var{word} to the
5068 Current Program Status register (CPSR).
5069 Else writes @var{word} to the current mode's Saved PSR (SPSR).
5070 In both cases, this bypasses the register cache.
5073 @deffn {Debug Command} {arm7_9 write_xpsr_im8} byte rotate (@option{0}|@option{1})
5074 @emph{This is intended for use while debugging OpenOCD; you probably
5077 Writes eight bits to the CPSR or SPSR,
5078 first rotating them by @math{2*rotate} bits,
5079 and bypassing the register cache.
5080 This has lower JTAG overhead than writing the entire CPSR or SPSR
5081 with @command{arm7_9 write_xpsr}.
5084 @subsection ARM720T specific commands
5087 These commands are available to ARM720T based CPUs,
5088 which are implementations of the ARMv4T architecture
5089 based on the ARM7TDMI-S integer core.
5090 They are available in addition to the ARMv4/5 and ARM7/ARM9 commands.
5092 @deffn Command {arm720t cp15} regnum [value]
5093 Display cp15 register @var{regnum};
5094 else if a @var{value} is provided, that value is written to that register.
5097 @deffn Command {arm720t mdw_phys} addr [count]
5098 @deffnx Command {arm720t mdh_phys} addr [count]
5099 @deffnx Command {arm720t mdb_phys} addr [count]
5100 Display contents of physical address @var{addr}, as
5101 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
5102 or 8-bit bytes (@command{mdb_phys}).
5103 If @var{count} is specified, displays that many units.
5106 @deffn Command {arm720t mww_phys} addr word
5107 @deffnx Command {arm720t mwh_phys} addr halfword
5108 @deffnx Command {arm720t mwb_phys} addr byte
5109 Writes the specified @var{word} (32 bits),
5110 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5111 at the specified physical address @var{addr}.
5114 @deffn Command {arm720t virt2phys} va
5115 Translate a virtual address @var{va} to a physical address
5116 and display the result.
5119 @subsection ARM9 specific commands
5122 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
5124 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
5126 For historical reasons, one command shared by these cores starts
5127 with the @command{arm9tdmi} prefix.
5128 This is true even for ARM9E based processors, which implement the
5129 ARMv5TE architecture instead of ARMv4T.
5131 @c 9-june-2009: tried this on arm920t, it didn't work.
5132 @c no-params always lists nothing caught, and that's how it acts.
5134 @anchor{arm9tdmi vector_catch}
5135 @deffn Command {arm9tdmi vector_catch} [@option{all}|@option{none}|list]
5136 @cindex vector_catch
5137 Vector Catch hardware provides a sort of dedicated breakpoint
5138 for hardware events such as reset, interrupt, and abort.
5139 You can use this to conserve normal breakpoint resources,
5140 so long as you're not concerned with code that branches directly
5141 to those hardware vectors.
5143 This always finishes by listing the current configuration.
5144 If parameters are provided, it first reconfigures the
5145 vector catch hardware to intercept
5146 @option{all} of the hardware vectors,
5147 @option{none} of them,
5148 or a list with one or more of the following:
5149 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
5150 @option{irq} @option{fiq}.
5153 @subsection ARM920T specific commands
5156 These commands are available to ARM920T based CPUs,
5157 which are implementations of the ARMv4T architecture
5158 built using the ARM9TDMI integer core.
5159 They are available in addition to the ARMv4/5, ARM7/ARM9,
5160 and ARM9TDMI commands.
5162 @deffn Command {arm920t cache_info}
5163 Print information about the caches found. This allows to see whether your target
5164 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
5167 @deffn Command {arm920t cp15} regnum [value]
5168 Display cp15 register @var{regnum};
5169 else if a @var{value} is provided, that value is written to that register.
5172 @deffn Command {arm920t cp15i} opcode [value [address]]
5173 Interpreted access using cp15 @var{opcode}.
5174 If no @var{value} is provided, the result is displayed.
5175 Else if that value is written using the specified @var{address},
5176 or using zero if no other address is not provided.
5179 @deffn Command {arm920t mdw_phys} addr [count]
5180 @deffnx Command {arm920t mdh_phys} addr [count]
5181 @deffnx Command {arm920t mdb_phys} addr [count]
5182 Display contents of physical address @var{addr}, as
5183 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
5184 or 8-bit bytes (@command{mdb_phys}).
5185 If @var{count} is specified, displays that many units.
5188 @deffn Command {arm920t mww_phys} addr word
5189 @deffnx Command {arm920t mwh_phys} addr halfword
5190 @deffnx Command {arm920t mwb_phys} addr byte
5191 Writes the specified @var{word} (32 bits),
5192 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5193 at the specified physical address @var{addr}.
5196 @deffn Command {arm920t read_cache} filename
5197 Dump the content of ICache and DCache to a file named @file{filename}.
5200 @deffn Command {arm920t read_mmu} filename
5201 Dump the content of the ITLB and DTLB to a file named @file{filename}.
5204 @deffn Command {arm920t virt2phys} va
5205 Translate a virtual address @var{va} to a physical address
5206 and display the result.
5209 @subsection ARM926ej-s specific commands
5212 These commands are available to ARM926ej-s based CPUs,
5213 which are implementations of the ARMv5TEJ architecture
5214 based on the ARM9EJ-S integer core.
5215 They are available in addition to the ARMv4/5, ARM7/ARM9,
5216 and ARM9TDMI commands.
5218 The Feroceon cores also support these commands, although
5219 they are not built from ARM926ej-s designs.
5221 @deffn Command {arm926ejs cache_info}
5222 Print information about the caches found.
5225 @deffn Command {arm926ejs cp15} opcode1 opcode2 CRn CRm regnum [value]
5226 Accesses cp15 register @var{regnum} using
5227 @var{opcode1}, @var{opcode2}, @var{CRn}, and @var{CRm}.
5228 If a @var{value} is provided, that value is written to that register.
5229 Else that register is read and displayed.
5232 @deffn Command {arm926ejs mdw_phys} addr [count]
5233 @deffnx Command {arm926ejs mdh_phys} addr [count]
5234 @deffnx Command {arm926ejs mdb_phys} addr [count]
5235 Display contents of physical address @var{addr}, as
5236 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
5237 or 8-bit bytes (@command{mdb_phys}).
5238 If @var{count} is specified, displays that many units.
5241 @deffn Command {arm926ejs mww_phys} addr word
5242 @deffnx Command {arm926ejs mwh_phys} addr halfword
5243 @deffnx Command {arm926ejs mwb_phys} addr byte
5244 Writes the specified @var{word} (32 bits),
5245 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5246 at the specified physical address @var{addr}.
5249 @deffn Command {arm926ejs virt2phys} va
5250 Translate a virtual address @var{va} to a physical address
5251 and display the result.
5254 @subsection ARM966E specific commands
5257 These commands are available to ARM966 based CPUs,
5258 which are implementations of the ARMv5TE architecture.
5259 They are available in addition to the ARMv4/5, ARM7/ARM9,
5260 and ARM9TDMI commands.
5262 @deffn Command {arm966e cp15} regnum [value]
5263 Display cp15 register @var{regnum};
5264 else if a @var{value} is provided, that value is written to that register.
5267 @subsection XScale specific commands
5270 Some notes about the debug implementation on the XScale CPUs:
5272 The XScale CPU provides a special debug-only mini-instruction cache
5273 (mini-IC) in which exception vectors and target-resident debug handler
5274 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
5275 must point vector 0 (the reset vector) to the entry of the debug
5276 handler. However, this means that the complete first cacheline in the
5277 mini-IC is marked valid, which makes the CPU fetch all exception
5278 handlers from the mini-IC, ignoring the code in RAM.
5280 OpenOCD currently does not sync the mini-IC entries with the RAM
5281 contents (which would fail anyway while the target is running), so
5282 the user must provide appropriate values using the @code{xscale
5283 vector_table} command.
5285 It is recommended to place a pc-relative indirect branch in the vector
5286 table, and put the branch destination somewhere in memory. Doing so
5287 makes sure the code in the vector table stays constant regardless of
5288 code layout in memory:
5291 ldr pc,[pc,#0x100-8]
5292 ldr pc,[pc,#0x100-8]
5293 ldr pc,[pc,#0x100-8]
5294 ldr pc,[pc,#0x100-8]
5295 ldr pc,[pc,#0x100-8]
5296 ldr pc,[pc,#0x100-8]
5297 ldr pc,[pc,#0x100-8]
5298 ldr pc,[pc,#0x100-8]
5300 .long real_reset_vector
5301 .long real_ui_handler
5302 .long real_swi_handler
5304 .long real_data_abort
5305 .long 0 /* unused */
5306 .long real_irq_handler
5307 .long real_fiq_handler
5310 The debug handler must be placed somewhere in the address space using
5311 the @code{xscale debug_handler} command. The allowed locations for the
5312 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
5313 0xfffff800). The default value is 0xfe000800.
5316 These commands are available to XScale based CPUs,
5317 which are implementations of the ARMv5TE architecture.
5319 @deffn Command {xscale analyze_trace}
5320 Displays the contents of the trace buffer.
5323 @deffn Command {xscale cache_clean_address} address
5324 Changes the address used when cleaning the data cache.
5327 @deffn Command {xscale cache_info}
5328 Displays information about the CPU caches.
5331 @deffn Command {xscale cp15} regnum [value]
5332 Display cp15 register @var{regnum};
5333 else if a @var{value} is provided, that value is written to that register.
5336 @deffn Command {xscale debug_handler} target address
5337 Changes the address used for the specified target's debug handler.
5340 @deffn Command {xscale dcache} (@option{enable}|@option{disable})
5341 Enables or disable the CPU's data cache.
5344 @deffn Command {xscale dump_trace} filename
5345 Dumps the raw contents of the trace buffer to @file{filename}.
5348 @deffn Command {xscale icache} (@option{enable}|@option{disable})
5349 Enables or disable the CPU's instruction cache.
5352 @deffn Command {xscale mmu} (@option{enable}|@option{disable})
5353 Enables or disable the CPU's memory management unit.
5356 @deffn Command {xscale trace_buffer} (@option{enable}|@option{disable}) [@option{fill} [n] | @option{wrap}]
5357 Enables or disables the trace buffer,
5358 and controls how it is emptied.
5361 @deffn Command {xscale trace_image} filename [offset [type]]
5362 Opens a trace image from @file{filename}, optionally rebasing
5363 its segment addresses by @var{offset}.
5364 The image @var{type} may be one of
5365 @option{bin} (binary), @option{ihex} (Intel hex),
5366 @option{elf} (ELF file), @option{s19} (Motorola s19),
5367 @option{mem}, or @option{builder}.
5370 @anchor{xscale vector_catch}
5371 @deffn Command {xscale vector_catch} [mask]
5372 @cindex vector_catch
5373 Display a bitmask showing the hardware vectors to catch.
5374 If the optional parameter is provided, first set the bitmask to that value.
5376 The mask bits correspond with bit 16..23 in the DCSR:
5379 0x02 Trap Undefined Instructions
5380 0x04 Trap Software Interrupt
5381 0x08 Trap Prefetch Abort
5382 0x10 Trap Data Abort
5389 @anchor{xscale vector_table}
5390 @deffn Command {xscale vector_table} [<low|high> <index> <value>]
5391 @cindex vector_table
5393 Set an entry in the mini-IC vector table. There are two tables: one for
5394 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
5395 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
5396 points to the debug handler entry and can not be overwritten.
5397 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
5399 Without arguments, the current settings are displayed.
5403 @section ARMv6 Architecture
5406 @subsection ARM11 specific commands
5409 @deffn Command {arm11 mcr} pX opc1 CRn CRm opc2 value
5410 Write @var{value} to a coprocessor @var{pX} register
5411 passing parameters @var{CRn},
5412 @var{CRm}, opcodes @var{opc1} and @var{opc2},
5413 and the MCR instruction.
5414 (The difference beween this and the MCR2 instruction is
5415 one bit in the encoding, effecively a fifth parameter.)
5418 @deffn Command {arm11 memwrite burst} [value]
5419 Displays the value of the memwrite burst-enable flag,
5420 which is enabled by default.
5421 If @var{value} is defined, first assigns that.
5424 @deffn Command {arm11 memwrite error_fatal} [value]
5425 Displays the value of the memwrite error_fatal flag,
5426 which is enabled by default.
5427 If @var{value} is defined, first assigns that.
5430 @deffn Command {arm11 mrc} pX opc1 CRn CRm opc2
5431 Read a coprocessor @var{pX} register passing parameters @var{CRn},
5432 @var{CRm}, opcodes @var{opc1} and @var{opc2},
5433 and the MRC instruction.
5434 (The difference beween this and the MRC2 instruction is
5435 one bit in the encoding, effecively a fifth parameter.)
5436 Displays the result.
5439 @deffn Command {arm11 no_increment} [value]
5440 Displays the value of the flag controlling whether
5441 some read or write operations increment the pointer
5442 (the default behavior) or not (acting like a FIFO).
5443 If @var{value} is defined, first assigns that.
5446 @deffn Command {arm11 step_irq_enable} [value]
5447 Displays the value of the flag controlling whether
5448 IRQs are enabled during single stepping;
5449 they is disabled by default.
5450 If @var{value} is defined, first assigns that.
5453 @section ARMv7 Architecture
5456 @subsection ARMv7 Debug Access Port (DAP) specific commands
5457 @cindex Debug Access Port
5459 These commands are specific to ARM architecture v7 Debug Access Port (DAP),
5460 included on cortex-m3 and cortex-a8 systems.
5461 They are available in addition to other core-specific commands that may be available.
5463 @deffn Command {dap info} [num]
5464 Displays dap info for ap @var{num}, defaulting to the currently selected AP.
5467 @deffn Command {dap apsel} [num]
5468 Select AP @var{num}, defaulting to 0.
5471 @deffn Command {dap apid} [num]
5472 Displays id register from AP @var{num},
5473 defaulting to the currently selected AP.
5476 @deffn Command {dap baseaddr} [num]
5477 Displays debug base address from AP @var{num},
5478 defaulting to the currently selected AP.
5481 @deffn Command {dap memaccess} [value]
5482 Displays the number of extra tck for mem-ap memory bus access [0-255].
5483 If @var{value} is defined, first assigns that.
5486 @subsection ARMv7-A specific commands
5489 @deffn Command {armv7a disassemble} address [count [@option{thumb}]]
5491 Disassembles @var{count} instructions starting at @var{address}.
5492 If @var{count} is not specified, a single instruction is disassembled.
5493 If @option{thumb} is specified, or the low bit of the address is set,
5494 Thumb2 (mixed 16/32-bit) instructions are used;
5495 else ARM (32-bit) instructions are used.
5496 With a handful of exceptions, ThumbEE instructions are the same as Thumb2;
5497 ThumbEE disassembly currently has no explicit support.
5498 (Processors may also support the Jazelle state, but
5499 those instructions are not currently understood by OpenOCD.)
5503 @subsection Cortex-M3 specific commands
5506 @deffn Command {cortex_m3 disassemble} address [count]
5508 Disassembles @var{count} Thumb2 instructions starting at @var{address}.
5509 If @var{count} is not specified, a single instruction is disassembled.
5512 @deffn Command {cortex_m3 maskisr} (@option{on}|@option{off})
5513 Control masking (disabling) interrupts during target step/resume.
5516 @deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list]
5517 @cindex vector_catch
5518 Vector Catch hardware provides dedicated breakpoints
5519 for certain hardware events.
5521 Parameters request interception of
5522 @option{all} of these hardware event vectors,
5523 @option{none} of them,
5524 or one or more of the following:
5525 @option{hard_err} for a HardFault exception;
5526 @option{mm_err} for a MemManage exception;
5527 @option{bus_err} for a BusFault exception;
5530 @option{chk_err}, or
5531 @option{nocp_err} for various UsageFault exceptions; or
5533 If NVIC setup code does not enable them,
5534 MemManage, BusFault, and UsageFault exceptions
5535 are mapped to HardFault.
5536 UsageFault checks for
5537 divide-by-zero and unaligned access
5538 must also be explicitly enabled.
5540 This finishes by listing the current vector catch configuration.
5543 @anchor{Software Debug Messages and Tracing}
5544 @section Software Debug Messages and Tracing
5545 @cindex Linux-ARM DCC support
5549 OpenOCD can process certain requests from target software. Currently
5550 @command{target_request debugmsgs}
5551 is supported only for @option{arm7_9} and @option{cortex_m3} cores.
5552 These messages are received as part of target polling, so
5553 you need to have @command{poll on} active to receive them.
5554 They are intrusive in that they will affect program execution
5555 times. If that is a problem, @pxref{ARM Hardware Tracing}.
5557 See @file{libdcc} in the contrib dir for more details.
5558 In addition to sending strings, characters, and
5559 arrays of various size integers from the target,
5560 @file{libdcc} also exports a software trace point mechanism.
5561 The target being debugged may
5562 issue trace messages which include a 24-bit @dfn{trace point} number.
5563 Trace point support includes two distinct mechanisms,
5564 each supported by a command:
5567 @item @emph{History} ... A circular buffer of trace points
5568 can be set up, and then displayed at any time.
5569 This tracks where code has been, which can be invaluable in
5570 finding out how some fault was triggered.
5572 The buffer may overflow, since it collects records continuously.
5573 It may be useful to use some of the 24 bits to represent a
5574 particular event, and other bits to hold data.
5576 @item @emph{Counting} ... An array of counters can be set up,
5577 and then displayed at any time.
5578 This can help establish code coverage and identify hot spots.
5580 The array of counters is directly indexed by the trace point
5581 number, so trace points with higher numbers are not counted.
5584 Linux-ARM kernels have a ``Kernel low-level debugging
5585 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
5586 depends on CONFIG_DEBUG_LL) which uses this mechanism to
5587 deliver messages before a serial console can be activated.
5588 This is not the same format used by @file{libdcc}.
5589 Other software, such as the U-Boot boot loader, sometimes
5590 does the same thing.
5592 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
5593 Displays current handling of target DCC message requests.
5594 These messages may be sent to the debugger while the target is running.
5595 The optional @option{enable} and @option{charmsg} parameters
5596 both enable the messages, while @option{disable} disables them.
5598 With @option{charmsg} the DCC words each contain one character,
5599 as used by Linux with CONFIG_DEBUG_ICEDCC;
5600 otherwise the libdcc format is used.
5603 @deffn Command {trace history} (@option{clear}|count)
5604 With no parameter, displays all the trace points that have triggered
5605 in the order they triggered.
5606 With the parameter @option{clear}, erases all current trace history records.
5607 With a @var{count} parameter, allocates space for that many
5611 @deffn Command {trace point} (@option{clear}|identifier)
5612 With no parameter, displays all trace point identifiers and how many times
5613 they have been triggered.
5614 With the parameter @option{clear}, erases all current trace point counters.
5615 With a numeric @var{identifier} parameter, creates a new a trace point counter
5616 and associates it with that identifier.
5618 @emph{Important:} The identifier and the trace point number
5619 are not related except by this command.
5620 These trace point numbers always start at zero (from server startup,
5621 or after @command{trace point clear}) and count up from there.
5626 @chapter JTAG Commands
5627 @cindex JTAG Commands
5628 Most general purpose JTAG commands have been presented earlier.
5629 (@xref{JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
5630 Lower level JTAG commands, as presented here,
5631 may be needed to work with targets which require special
5632 attention during operations such as reset or initialization.
5634 To use these commands you will need to understand some
5635 of the basics of JTAG, including:
5638 @item A JTAG scan chain consists of a sequence of individual TAP
5639 devices such as a CPUs.
5640 @item Control operations involve moving each TAP through the same
5641 standard state machine (in parallel)
5642 using their shared TMS and clock signals.
5643 @item Data transfer involves shifting data through the chain of
5644 instruction or data registers of each TAP, writing new register values
5645 while the reading previous ones.
5646 @item Data register sizes are a function of the instruction active in
5647 a given TAP, while instruction register sizes are fixed for each TAP.
5648 All TAPs support a BYPASS instruction with a single bit data register.
5649 @item The way OpenOCD differentiates between TAP devices is by
5650 shifting different instructions into (and out of) their instruction
5654 @section Low Level JTAG Commands
5656 These commands are used by developers who need to access
5657 JTAG instruction or data registers, possibly controlling
5658 the order of TAP state transitions.
5659 If you're not debugging OpenOCD internals, or bringing up a
5660 new JTAG adapter or a new type of TAP device (like a CPU or
5661 JTAG router), you probably won't need to use these commands.
5663 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
5664 Loads the data register of @var{tap} with a series of bit fields
5665 that specify the entire register.
5666 Each field is @var{numbits} bits long with
5667 a numeric @var{value} (hexadecimal encouraged).
5668 The return value holds the original value of each
5671 For example, a 38 bit number might be specified as one
5672 field of 32 bits then one of 6 bits.
5673 @emph{For portability, never pass fields which are more
5674 than 32 bits long. Many OpenOCD implementations do not
5675 support 64-bit (or larger) integer values.}
5677 All TAPs other than @var{tap} must be in BYPASS mode.
5678 The single bit in their data registers does not matter.
5680 When @var{tap_state} is specified, the JTAG state machine is left
5682 For example @sc{drpause} might be specified, so that more
5683 instructions can be issued before re-entering the @sc{run/idle} state.
5684 If the end state is not specified, the @sc{run/idle} state is entered.
5687 OpenOCD does not record information about data register lengths,
5688 so @emph{it is important that you get the bit field lengths right}.
5689 Remember that different JTAG instructions refer to different
5690 data registers, which may have different lengths.
5691 Moreover, those lengths may not be fixed;
5692 the SCAN_N instruction can change the length of
5693 the register accessed by the INTEST instruction
5694 (by connecting a different scan chain).
5698 @deffn Command {flush_count}
5699 Returns the number of times the JTAG queue has been flushed.
5700 This may be used for performance tuning.
5702 For example, flushing a queue over USB involves a
5703 minimum latency, often several milliseconds, which does
5704 not change with the amount of data which is written.
5705 You may be able to identify performance problems by finding
5706 tasks which waste bandwidth by flushing small transfers too often,
5707 instead of batching them into larger operations.
5710 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
5711 For each @var{tap} listed, loads the instruction register
5712 with its associated numeric @var{instruction}.
5713 (The number of bits in that instruction may be displayed
5714 using the @command{scan_chain} command.)
5715 For other TAPs, a BYPASS instruction is loaded.
5717 When @var{tap_state} is specified, the JTAG state machine is left
5719 For example @sc{irpause} might be specified, so the data register
5720 can be loaded before re-entering the @sc{run/idle} state.
5721 If the end state is not specified, the @sc{run/idle} state is entered.
5724 OpenOCD currently supports only a single field for instruction
5725 register values, unlike data register values.
5726 For TAPs where the instruction register length is more than 32 bits,
5727 portable scripts currently must issue only BYPASS instructions.
5731 @deffn Command {jtag_reset} trst srst
5732 Set values of reset signals.
5733 The @var{trst} and @var{srst} parameter values may be
5734 @option{0}, indicating that reset is inactive (pulled or driven high),
5735 or @option{1}, indicating it is active (pulled or driven low).
5736 The @command{reset_config} command should already have been used
5737 to configure how the board and JTAG adapter treat these two
5738 signals, and to say if either signal is even present.
5739 @xref{Reset Configuration}.
5742 @deffn Command {runtest} @var{num_cycles}
5743 Move to the @sc{run/idle} state, and execute at least
5744 @var{num_cycles} of the JTAG clock (TCK).
5745 Instructions often need some time
5746 to execute before they take effect.
5749 @c tms_sequence (short|long)
5750 @c ... temporary, debug-only, probably gone before 0.2 ships
5752 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
5753 Verify values captured during @sc{ircapture} and returned
5754 during IR scans. Default is enabled, but this can be
5755 overridden by @command{verify_jtag}.
5758 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
5759 Enables verification of DR and IR scans, to help detect
5760 programming errors. For IR scans, @command{verify_ircapture}
5761 must also be enabled.
5765 @section TAP state names
5766 @cindex TAP state names
5768 The @var{tap_state} names used by OpenOCD in the @command{drscan},
5769 and @command{irscan} commands are:
5772 @item @b{RESET} ... should act as if TRST were active
5773 @item @b{RUN/IDLE} ... don't assume this always means IDLE
5776 @item @b{DRSHIFT} ... TDI/TDO shifting through the data register
5778 @item @b{DRPAUSE} ... data register ready for update or more shifting
5783 @item @b{IRSHIFT} ... TDI/TDO shifting through the instruction register
5785 @item @b{IRPAUSE} ... instruction register ready for update or more shifting
5790 Note that only six of those states are fully ``stable'' in the
5791 face of TMS fixed (low except for @sc{reset})
5792 and a free-running JTAG clock. For all the
5793 others, the next TCK transition changes to a new state.
5796 @item From @sc{drshift} and @sc{irshift}, clock transitions will
5797 produce side effects by changing register contents. The values
5798 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
5799 may not be as expected.
5800 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
5801 choices after @command{drscan} or @command{irscan} commands,
5802 since they are free of JTAG side effects.
5803 However, @sc{run/idle} may have side effects that appear at other
5804 levels, such as advancing the ARM9E-S instruction pipeline.
5805 Consult the documentation for the TAP(s) you are working with.
5808 @node Boundary Scan Commands
5809 @chapter Boundary Scan Commands
5811 One of the original purposes of JTAG was to support
5812 boundary scan based hardware testing.
5813 Although its primary focus is to support On-Chip Debugging,
5814 OpenOCD also includes some boundary scan commands.
5816 @section SVF: Serial Vector Format
5817 @cindex Serial Vector Format
5820 The Serial Vector Format, better known as @dfn{SVF}, is a
5821 way to represent JTAG test patterns in text files.
5822 OpenOCD supports running such test files.
5824 @deffn Command {svf} filename [@option{quiet}]
5825 This issues a JTAG reset (Test-Logic-Reset) and then
5826 runs the SVF script from @file{filename}.
5827 Unless the @option{quiet} option is specified,
5828 each command is logged before it is executed.
5831 @section XSVF: Xilinx Serial Vector Format
5832 @cindex Xilinx Serial Vector Format
5835 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
5836 binary representation of SVF which is optimized for use with
5838 OpenOCD supports running such test files.
5840 @quotation Important
5841 Not all XSVF commands are supported.
5844 @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
5845 This issues a JTAG reset (Test-Logic-Reset) and then
5846 runs the XSVF script from @file{filename}.
5847 When a @var{tapname} is specified, the commands are directed at
5849 When @option{virt2} is specified, the @sc{xruntest} command counts
5850 are interpreted as TCK cycles instead of microseconds.
5851 Unless the @option{quiet} option is specified,
5852 messages are logged for comments and some retries.
5858 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
5859 be used to access files on PCs (either the developer's PC or some other PC).
5861 The way this works on the ZY1000 is to prefix a filename by
5862 "/tftp/ip/" and append the TFTP path on the TFTP
5863 server (tftpd). For example,
5866 load_image /tftp/10.0.0.96/c:\temp\abc.elf
5869 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
5870 if the file was hosted on the embedded host.
5872 In order to achieve decent performance, you must choose a TFTP server
5873 that supports a packet size bigger than the default packet size (512 bytes). There
5874 are numerous TFTP servers out there (free and commercial) and you will have to do
5875 a bit of googling to find something that fits your requirements.
5877 @node GDB and OpenOCD
5878 @chapter GDB and OpenOCD
5880 OpenOCD complies with the remote gdbserver protocol, and as such can be used
5881 to debug remote targets.
5883 @anchor{Connecting to GDB}
5884 @section Connecting to GDB
5885 @cindex Connecting to GDB
5886 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
5887 instance GDB 6.3 has a known bug that produces bogus memory access
5888 errors, which has since been fixed: look up 1836 in
5889 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
5891 OpenOCD can communicate with GDB in two ways:
5895 A socket (TCP/IP) connection is typically started as follows:
5897 target remote localhost:3333
5899 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
5901 A pipe connection is typically started as follows:
5903 target remote | openocd --pipe
5905 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
5906 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
5910 To list the available OpenOCD commands type @command{monitor help} on the
5913 OpenOCD supports the gdb @option{qSupported} packet, this enables information
5914 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
5915 packet size and the device's memory map.
5917 Previous versions of OpenOCD required the following GDB options to increase
5918 the packet size and speed up GDB communication:
5920 set remote memory-write-packet-size 1024
5921 set remote memory-write-packet-size fixed
5922 set remote memory-read-packet-size 1024
5923 set remote memory-read-packet-size fixed
5925 This is now handled in the @option{qSupported} PacketSize and should not be required.
5927 @section Programming using GDB
5928 @cindex Programming using GDB
5930 By default the target memory map is sent to GDB. This can be disabled by
5931 the following OpenOCD configuration option:
5933 gdb_memory_map disable
5935 For this to function correctly a valid flash configuration must also be set
5936 in OpenOCD. For faster performance you should also configure a valid
5939 Informing GDB of the memory map of the target will enable GDB to protect any
5940 flash areas of the target and use hardware breakpoints by default. This means
5941 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
5942 using a memory map. @xref{gdb_breakpoint_override}.
5944 To view the configured memory map in GDB, use the GDB command @option{info mem}
5945 All other unassigned addresses within GDB are treated as RAM.
5947 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
5948 This can be changed to the old behaviour by using the following GDB command
5950 set mem inaccessible-by-default off
5953 If @command{gdb_flash_program enable} is also used, GDB will be able to
5954 program any flash memory using the vFlash interface.
5956 GDB will look at the target memory map when a load command is given, if any
5957 areas to be programmed lie within the target flash area the vFlash packets
5960 If the target needs configuring before GDB programming, an event
5961 script can be executed:
5963 $_TARGETNAME configure -event EVENTNAME BODY
5966 To verify any flash programming the GDB command @option{compare-sections}
5969 @node Tcl Scripting API
5970 @chapter Tcl Scripting API
5971 @cindex Tcl Scripting API
5975 The commands are stateless. E.g. the telnet command line has a concept
5976 of currently active target, the Tcl API proc's take this sort of state
5977 information as an argument to each proc.
5979 There are three main types of return values: single value, name value
5980 pair list and lists.
5982 Name value pair. The proc 'foo' below returns a name/value pair
5988 > set foo(you) Oyvind
5989 > set foo(mouse) Micky
5990 > set foo(duck) Donald
5998 me Duane you Oyvind mouse Micky duck Donald
6000 Thus, to get the names of the associative array is easy:
6002 foreach { name value } [set foo] {
6003 puts "Name: $name, Value: $value"
6007 Lists returned must be relatively small. Otherwise a range
6008 should be passed in to the proc in question.
6010 @section Internal low-level Commands
6012 By low-level, the intent is a human would not directly use these commands.
6014 Low-level commands are (should be) prefixed with "ocd_", e.g.
6015 @command{ocd_flash_banks}
6016 is the low level API upon which @command{flash banks} is implemented.
6019 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
6021 Read memory and return as a Tcl array for script processing
6022 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
6024 Convert a Tcl array to memory locations and write the values
6025 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
6027 Return information about the flash banks
6030 OpenOCD commands can consist of two words, e.g. "flash banks". The
6031 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
6032 called "flash_banks".
6034 @section OpenOCD specific Global Variables
6038 Real Tcl has ::tcl_platform(), and platform::identify, and many other
6039 variables. JimTCL, as implemented in OpenOCD creates $HostOS which
6040 holds one of the following values:
6043 @item @b{winxx} Built using Microsoft Visual Studio
6044 @item @b{linux} Linux is the underlying operating sytem
6045 @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
6046 @item @b{cygwin} Running under Cygwin
6047 @item @b{mingw32} Running under MingW32
6048 @item @b{other} Unknown, none of the above.
6051 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
6054 We should add support for a variable like Tcl variable
6055 @code{tcl_platform(platform)}, it should be called
6056 @code{jim_platform} (because it
6057 is jim, not real tcl).
6061 @chapter Deprecated/Removed Commands
6062 @cindex Deprecated/Removed Commands
6063 Certain OpenOCD commands have been deprecated or
6064 removed during the various revisions.
6066 Upgrade your scripts as soon as possible.
6067 These descriptions for old commands may be removed
6068 a year after the command itself was removed.
6069 This means that in January 2010 this chapter may
6070 become much shorter.
6073 @item @b{arm7_9 fast_writes}
6074 @cindex arm7_9 fast_writes
6075 @*Use @command{arm7_9 fast_memory_access} instead.
6076 @xref{arm7_9 fast_memory_access}.
6079 @*An buggy old command that would not really work since background polling would wipe out the global endstate
6080 @item @b{arm7_9 force_hw_bkpts}
6081 @*Use @command{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
6082 for flash if the GDB memory map has been set up(default when flash is declared in
6083 target configuration). @xref{gdb_breakpoint_override}.
6084 @item @b{arm7_9 sw_bkpts}
6085 @*On by default. @xref{gdb_breakpoint_override}.
6086 @item @b{daemon_startup}
6087 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
6088 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
6089 and @option{target cortex_m3 little reset_halt 0}.
6090 @item @b{dump_binary}
6091 @*use @option{dump_image} command with same args. @xref{dump_image}.
6092 @item @b{flash erase}
6093 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
6094 @item @b{flash write}
6095 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
6096 @item @b{flash write_binary}
6097 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
6098 @item @b{flash auto_erase}
6099 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
6101 @item @b{jtag_device}
6102 @*use the @command{jtag newtap} command, converting from positional syntax
6103 to named prefixes, and naming the TAP.
6105 Note that if you try to use the old command, a message will tell you the
6106 right new command to use; and that the fourth parameter in the old syntax
6107 was never actually used.
6109 OLD: jtag_device 8 0x01 0xe3 0xfe
6110 NEW: jtag newtap CHIPNAME TAPNAME \
6111 -irlen 8 -ircapture 0x01 -irmask 0xe3
6114 @item @b{jtag_speed} value
6115 @*@xref{JTAG Speed}.
6116 Usually, a value of zero means maximum
6117 speed. The actual effect of this option depends on the JTAG interface used.
6119 @item wiggler: maximum speed / @var{number}
6120 @item ft2232: 6MHz / (@var{number}+1)
6121 @item amt jtagaccel: 8 / 2**@var{number}
6122 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
6123 @item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
6124 @comment end speed list.
6127 @item @b{load_binary}
6128 @*use @option{load_image} command with same args. @xref{load_image}.
6129 @item @b{run_and_halt_time}
6130 @*This command has been removed for simpler reset behaviour, it can be simulated with the
6137 @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
6138 @*use the create subcommand of @option{target}.
6139 @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
6140 @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
6141 @item @b{working_area}
6142 @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
6150 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
6152 @cindex adaptive clocking
6155 In digital circuit design it is often refered to as ``clock
6156 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
6157 operating at some speed, your target is operating at another. The two
6158 clocks are not synchronised, they are ``asynchronous''
6160 In order for the two to work together they must be synchronised. Otherwise
6161 the two systems will get out of sync with each other and nothing will
6162 work. There are 2 basic options:
6165 Use a special circuit.
6167 One clock must be some multiple slower than the other.
6170 @b{Does this really matter?} For some chips and some situations, this
6171 is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
6172 Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
6173 program/enable the oscillators and eventually the main clock. It is in
6174 those critical times you must slow the JTAG clock to sometimes 1 to
6177 Imagine debugging a 500MHz ARM926 hand held battery powered device
6178 that ``deep sleeps'' at 32kHz between every keystroke. It can be
6181 @b{Solution #1 - A special circuit}
6183 In order to make use of this, your JTAG dongle must support the RTCK
6184 feature. Not all dongles support this - keep reading!
6186 The RTCK signal often found in some ARM chips is used to help with
6187 this problem. ARM has a good description of the problem described at
6188 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
6189 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
6190 work? / how does adaptive clocking work?''.
6192 The nice thing about adaptive clocking is that ``battery powered hand
6193 held device example'' - the adaptiveness works perfectly all the
6194 time. One can set a break point or halt the system in the deep power
6195 down code, slow step out until the system speeds up.
6197 Note that adaptive clocking may also need to work at the board level,
6198 when a board-level scan chain has multiple chips.
6199 Parallel clock voting schemes are good way to implement this,
6200 both within and between chips, and can easily be implemented
6202 It's not difficult to have logic fan a module's input TCK signal out
6203 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
6204 back with the right polarity before changing the output RTCK signal.
6205 Texas Instruments makes some clock voting logic available
6206 for free (with no support) in VHDL form; see
6207 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
6209 @b{Solution #2 - Always works - but may be slower}
6211 Often this is a perfectly acceptable solution.
6213 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
6214 the target clock speed. But what that ``magic division'' is varies
6215 depending on the chips on your board.
6216 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
6217 ARM11 cores use an 8:1 division.
6218 @b{Xilinx rule of thumb} is 1/12 the clock speed.
6220 Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
6222 You can still debug the 'low power' situations - you just need to
6223 manually adjust the clock speed at every step. While painful and
6224 tedious, it is not always practical.
6226 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
6227 have a special debug mode in your application that does a ``high power
6228 sleep''. If you are careful - 98% of your problems can be debugged
6231 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
6232 operation in your idle loops even if you don't otherwise change the CPU
6234 That operation gates the CPU clock, and thus the JTAG clock; which
6235 prevents JTAG access. One consequence is not being able to @command{halt}
6236 cores which are executing that @emph{wait for interrupt} operation.
6238 To set the JTAG frequency use the command:
6246 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
6248 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
6249 around Windows filenames.
6262 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
6264 Make sure you have Cygwin installed, or at least a version of OpenOCD that
6265 claims to come with all the necessary DLLs. When using Cygwin, try launching
6266 OpenOCD from the Cygwin shell.
6268 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
6269 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
6270 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
6272 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
6273 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
6274 software breakpoints consume one of the two available hardware breakpoints.
6276 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
6278 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
6279 clock at the time you're programming the flash. If you've specified the crystal's
6280 frequency, make sure the PLL is disabled. If you've specified the full core speed
6281 (e.g. 60MHz), make sure the PLL is enabled.
6283 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
6284 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
6285 out while waiting for end of scan, rtck was disabled".
6287 Make sure your PC's parallel port operates in EPP mode. You might have to try several
6288 settings in your PC BIOS (ECP, EPP, and different versions of those).
6290 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
6291 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
6292 memory read caused data abort".
6294 The errors are non-fatal, and are the result of GDB trying to trace stack frames
6295 beyond the last valid frame. It might be possible to prevent this by setting up
6296 a proper "initial" stack frame, if you happen to know what exactly has to
6297 be done, feel free to add this here.
6299 @b{Simple:} In your startup code - push 8 registers of zeros onto the
6300 stack before calling main(). What GDB is doing is ``climbing'' the run
6301 time stack by reading various values on the stack using the standard
6302 call frame for the target. GDB keeps going - until one of 2 things
6303 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
6304 stackframes have been processed. By pushing zeros on the stack, GDB
6307 @b{Debugging Interrupt Service Routines} - In your ISR before you call
6308 your C code, do the same - artifically push some zeros onto the stack,
6309 remember to pop them off when the ISR is done.
6311 @b{Also note:} If you have a multi-threaded operating system, they
6312 often do not @b{in the intrest of saving memory} waste these few
6316 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
6317 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
6319 This warning doesn't indicate any serious problem, as long as you don't want to
6320 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
6321 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
6322 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
6323 independently. With this setup, it's not possible to halt the core right out of
6324 reset, everything else should work fine.
6326 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
6327 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
6328 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
6329 quit with an error message. Is there a stability issue with OpenOCD?
6331 No, this is not a stability issue concerning OpenOCD. Most users have solved
6332 this issue by simply using a self-powered USB hub, which they connect their
6333 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
6334 supply stable enough for the Amontec JTAGkey to be operated.
6336 @b{Laptops running on battery have this problem too...}
6338 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
6339 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
6340 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
6341 What does that mean and what might be the reason for this?
6343 First of all, the reason might be the USB power supply. Try using a self-powered
6344 hub instead of a direct connection to your computer. Secondly, the error code 4
6345 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
6346 chip ran into some sort of error - this points us to a USB problem.
6348 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
6349 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
6350 What does that mean and what might be the reason for this?
6352 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
6353 has closed the connection to OpenOCD. This might be a GDB issue.
6355 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
6356 are described, there is a parameter for specifying the clock frequency
6357 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
6358 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
6359 specified in kilohertz. However, I do have a quartz crystal of a
6360 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
6361 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
6364 No. The clock frequency specified here must be given as an integral number.
6365 However, this clock frequency is used by the In-Application-Programming (IAP)
6366 routines of the LPC2000 family only, which seems to be very tolerant concerning
6367 the given clock frequency, so a slight difference between the specified clock
6368 frequency and the actual clock frequency will not cause any trouble.
6370 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
6372 Well, yes and no. Commands can be given in arbitrary order, yet the
6373 devices listed for the JTAG scan chain must be given in the right
6374 order (jtag newdevice), with the device closest to the TDO-Pin being
6375 listed first. In general, whenever objects of the same type exist
6376 which require an index number, then these objects must be given in the
6377 right order (jtag newtap, targets and flash banks - a target
6378 references a jtag newtap and a flash bank references a target).
6380 You can use the ``scan_chain'' command to verify and display the tap order.
6382 Also, some commands can't execute until after @command{init} has been
6383 processed. Such commands include @command{nand probe} and everything
6384 else that needs to write to controller registers, perhaps for setting
6385 up DRAM and loading it with code.
6387 @anchor{FAQ TAP Order}
6388 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
6391 Yes; whenever you have more than one, you must declare them in
6392 the same order used by the hardware.
6394 Many newer devices have multiple JTAG TAPs. For example: ST
6395 Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
6396 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
6397 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
6398 connected to the boundary scan TAP, which then connects to the
6399 Cortex-M3 TAP, which then connects to the TDO pin.
6401 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
6402 (2) The boundary scan TAP. If your board includes an additional JTAG
6403 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
6404 place it before or after the STM32 chip in the chain. For example:
6407 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
6408 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
6409 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
6410 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
6411 @item Xilinx TDO Pin -> OpenOCD TDO (input)
6414 The ``jtag device'' commands would thus be in the order shown below. Note:
6417 @item jtag newtap Xilinx tap -irlen ...
6418 @item jtag newtap stm32 cpu -irlen ...
6419 @item jtag newtap stm32 bs -irlen ...
6420 @item # Create the debug target and say where it is
6421 @item target create stm32.cpu -chain-position stm32.cpu ...
6425 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
6426 log file, I can see these error messages: Error: arm7_9_common.c:561
6427 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
6433 @node Tcl Crash Course
6434 @chapter Tcl Crash Course
6437 Not everyone knows Tcl - this is not intended to be a replacement for
6438 learning Tcl, the intent of this chapter is to give you some idea of
6439 how the Tcl scripts work.
6441 This chapter is written with two audiences in mind. (1) OpenOCD users
6442 who need to understand a bit more of how JIM-Tcl works so they can do
6443 something useful, and (2) those that want to add a new command to
6446 @section Tcl Rule #1
6447 There is a famous joke, it goes like this:
6449 @item Rule #1: The wife is always correct
6450 @item Rule #2: If you think otherwise, See Rule #1
6453 The Tcl equal is this:
6456 @item Rule #1: Everything is a string
6457 @item Rule #2: If you think otherwise, See Rule #1
6460 As in the famous joke, the consequences of Rule #1 are profound. Once
6461 you understand Rule #1, you will understand Tcl.
6463 @section Tcl Rule #1b
6464 There is a second pair of rules.
6466 @item Rule #1: Control flow does not exist. Only commands
6467 @* For example: the classic FOR loop or IF statement is not a control
6468 flow item, they are commands, there is no such thing as control flow
6470 @item Rule #2: If you think otherwise, See Rule #1
6471 @* Actually what happens is this: There are commands that by
6472 convention, act like control flow key words in other languages. One of
6473 those commands is the word ``for'', another command is ``if''.
6476 @section Per Rule #1 - All Results are strings
6477 Every Tcl command results in a string. The word ``result'' is used
6478 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
6479 Everything is a string}
6481 @section Tcl Quoting Operators
6482 In life of a Tcl script, there are two important periods of time, the
6483 difference is subtle.
6486 @item Evaluation Time
6489 The two key items here are how ``quoted things'' work in Tcl. Tcl has
6490 three primary quoting constructs, the [square-brackets] the
6491 @{curly-braces@} and ``double-quotes''
6493 By now you should know $VARIABLES always start with a $DOLLAR
6494 sign. BTW: To set a variable, you actually use the command ``set'', as
6495 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
6496 = 1'' statement, but without the equal sign.
6499 @item @b{[square-brackets]}
6500 @* @b{[square-brackets]} are command substitutions. It operates much
6501 like Unix Shell `back-ticks`. The result of a [square-bracket]
6502 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
6503 string}. These two statements are roughly identical:
6507 echo "The Date is: $X"
6510 puts "The Date is: $X"
6512 @item @b{``double-quoted-things''}
6513 @* @b{``double-quoted-things''} are just simply quoted
6514 text. $VARIABLES and [square-brackets] are expanded in place - the
6515 result however is exactly 1 string. @i{Remember Rule #1 - Everything
6519 puts "It is now \"[date]\", $x is in 1 hour"
6521 @item @b{@{Curly-Braces@}}
6522 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
6523 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
6524 'single-quote' operators in BASH shell scripts, with the added
6525 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
6526 nested 3 times@}@}@} NOTE: [date] is a bad example;
6527 at this writing, Jim/OpenOCD does not have a date command.
6530 @section Consequences of Rule 1/2/3/4
6532 The consequences of Rule 1 are profound.
6534 @subsection Tokenisation & Execution.
6536 Of course, whitespace, blank lines and #comment lines are handled in
6539 As a script is parsed, each (multi) line in the script file is
6540 tokenised and according to the quoting rules. After tokenisation, that
6541 line is immedatly executed.
6543 Multi line statements end with one or more ``still-open''
6544 @{curly-braces@} which - eventually - closes a few lines later.
6546 @subsection Command Execution
6548 Remember earlier: There are no ``control flow''
6549 statements in Tcl. Instead there are COMMANDS that simply act like
6550 control flow operators.
6552 Commands are executed like this:
6555 @item Parse the next line into (argc) and (argv[]).
6556 @item Look up (argv[0]) in a table and call its function.
6557 @item Repeat until End Of File.
6560 It sort of works like this:
6563 ReadAndParse( &argc, &argv );
6565 cmdPtr = LookupCommand( argv[0] );
6567 (*cmdPtr->Execute)( argc, argv );
6571 When the command ``proc'' is parsed (which creates a procedure
6572 function) it gets 3 parameters on the command line. @b{1} the name of
6573 the proc (function), @b{2} the list of parameters, and @b{3} the body
6574 of the function. Not the choice of words: LIST and BODY. The PROC
6575 command stores these items in a table somewhere so it can be found by
6578 @subsection The FOR command
6580 The most interesting command to look at is the FOR command. In Tcl,
6581 the FOR command is normally implemented in C. Remember, FOR is a
6582 command just like any other command.
6584 When the ascii text containing the FOR command is parsed, the parser
6585 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
6589 @item The ascii text 'for'
6590 @item The start text
6591 @item The test expression
6596 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
6597 Remember @i{Rule #1 - Everything is a string.} The key point is this:
6598 Often many of those parameters are in @{curly-braces@} - thus the
6599 variables inside are not expanded or replaced until later.
6601 Remember that every Tcl command looks like the classic ``main( argc,
6602 argv )'' function in C. In JimTCL - they actually look like this:
6606 MyCommand( Jim_Interp *interp,
6608 Jim_Obj * const *argvs );
6611 Real Tcl is nearly identical. Although the newer versions have
6612 introduced a byte-code parser and intepreter, but at the core, it
6613 still operates in the same basic way.
6615 @subsection FOR command implementation
6617 To understand Tcl it is perhaps most helpful to see the FOR
6618 command. Remember, it is a COMMAND not a control flow structure.
6620 In Tcl there are two underlying C helper functions.
6622 Remember Rule #1 - You are a string.
6624 The @b{first} helper parses and executes commands found in an ascii
6625 string. Commands can be seperated by semicolons, or newlines. While
6626 parsing, variables are expanded via the quoting rules.
6628 The @b{second} helper evaluates an ascii string as a numerical
6629 expression and returns a value.
6631 Here is an example of how the @b{FOR} command could be
6632 implemented. The pseudo code below does not show error handling.
6634 void Execute_AsciiString( void *interp, const char *string );
6636 int Evaluate_AsciiExpression( void *interp, const char *string );
6639 MyForCommand( void *interp,
6644 SetResult( interp, "WRONG number of parameters");
6648 // argv[0] = the ascii string just like C
6650 // Execute the start statement.
6651 Execute_AsciiString( interp, argv[1] );
6655 i = Evaluate_AsciiExpression(interp, argv[2]);
6660 Execute_AsciiString( interp, argv[3] );
6662 // Execute the LOOP part
6663 Execute_AsciiString( interp, argv[4] );
6667 SetResult( interp, "" );
6672 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
6673 in the same basic way.
6675 @section OpenOCD Tcl Usage
6677 @subsection source and find commands
6678 @b{Where:} In many configuration files
6679 @* Example: @b{ source [find FILENAME] }
6680 @*Remember the parsing rules
6682 @item The FIND command is in square brackets.
6683 @* The FIND command is executed with the parameter FILENAME. It should
6684 find the full path to the named file. The RESULT is a string, which is
6685 substituted on the orginal command line.
6686 @item The command source is executed with the resulting filename.
6687 @* SOURCE reads a file and executes as a script.
6689 @subsection format command
6690 @b{Where:} Generally occurs in numerous places.
6691 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
6697 puts [format "The answer: %d" [expr $x * $y]]
6700 @item The SET command creates 2 variables, X and Y.
6701 @item The double [nested] EXPR command performs math
6702 @* The EXPR command produces numerical result as a string.
6704 @item The format command is executed, producing a single string
6705 @* Refer to Rule #1.
6706 @item The PUTS command outputs the text.
6708 @subsection Body or Inlined Text
6709 @b{Where:} Various TARGET scripts.
6712 proc someproc @{@} @{
6713 ... multiple lines of stuff ...
6715 $_TARGETNAME configure -event FOO someproc
6716 #2 Good - no variables
6717 $_TARGETNAME confgure -event foo "this ; that;"
6718 #3 Good Curly Braces
6719 $_TARGETNAME configure -event FOO @{
6722 #4 DANGER DANGER DANGER
6723 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
6726 @item The $_TARGETNAME is an OpenOCD variable convention.
6727 @*@b{$_TARGETNAME} represents the last target created, the value changes
6728 each time a new target is created. Remember the parsing rules. When
6729 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
6730 the name of the target which happens to be a TARGET (object)
6732 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
6733 @*There are 4 examples:
6735 @item The TCLBODY is a simple string that happens to be a proc name
6736 @item The TCLBODY is several simple commands seperated by semicolons
6737 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
6738 @item The TCLBODY is a string with variables that get expanded.
6741 In the end, when the target event FOO occurs the TCLBODY is
6742 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
6743 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
6745 Remember the parsing rules. In case #3, @{curly-braces@} mean the
6746 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
6747 and the text is evaluated. In case #4, they are replaced before the
6748 ``Target Object Command'' is executed. This occurs at the same time
6749 $_TARGETNAME is replaced. In case #4 the date will never
6750 change. @{BTW: [date] is a bad example; at this writing,
6751 Jim/OpenOCD does not have a date command@}
6753 @subsection Global Variables
6754 @b{Where:} You might discover this when writing your own procs @* In
6755 simple terms: Inside a PROC, if you need to access a global variable
6756 you must say so. See also ``upvar''. Example:
6758 proc myproc @{ @} @{
6759 set y 0 #Local variable Y
6760 global x #Global variable X
6761 puts [format "X=%d, Y=%d" $x $y]
6764 @section Other Tcl Hacks
6765 @b{Dynamic variable creation}
6767 # Dynamically create a bunch of variables.
6768 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
6770 set vn [format "BIT%d" $x]
6774 set $vn [expr (1 << $x)]
6777 @b{Dynamic proc/command creation}
6779 # One "X" function - 5 uart functions.
6780 foreach who @{A B C D E@}
6781 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
6785 @node Target Library
6786 @chapter Target Library
6787 @cindex Target Library
6789 OpenOCD comes with a target configuration script library. These scripts can be
6790 used as-is or serve as a starting point.
6792 The target library is published together with the OpenOCD executable and
6793 the path to the target library is in the OpenOCD script search path.
6794 Similarly there are example scripts for configuring the JTAG interface.
6796 The command line below uses the example parport configuration script
6797 that ship with OpenOCD, then configures the str710.cfg target and
6798 finally issues the init and reset commands. The communication speed
6799 is set to 10kHz for reset and 8MHz for post reset.
6802 openocd -f interface/parport.cfg -f target/str710.cfg \
6803 -c "init" -c "reset"
6806 To list the target scripts available:
6809 $ ls /usr/local/lib/openocd/target
6811 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
6812 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
6813 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
6814 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
6819 @node OpenOCD Concept Index
6820 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
6821 @comment case issue with ``Index.html'' and ``index.html''
6822 @comment Occurs when creating ``--html --no-split'' output
6823 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
6824 @unnumbered OpenOCD Concept Index
6828 @node Command and Driver Index
6829 @unnumbered Command and Driver Index