doc: document the OCL (on chip flash loader) driver
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
11
12 @include version.texi
13
14 @copying
15
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
20
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
28
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
38
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
45
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
50
51 @summarycontents
52 @contents
53
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
57
58 @insertcopying
59 @end ifnottex
60
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * NAND Flash Commands:: NAND Flash Commands
77 * PLD/FPGA Commands:: PLD/FPGA Commands
78 * General Commands:: General Commands
79 * Architecture and Core Commands:: Architecture and Core Commands
80 * JTAG Commands:: JTAG Commands
81 * Boundary Scan Commands:: Boundary Scan Commands
82 * Utility Commands:: Utility Commands
83 * TFTP:: TFTP
84 * GDB and OpenOCD:: Using GDB and OpenOCD
85 * Tcl Scripting API:: Tcl Scripting API
86 * FAQ:: Frequently Asked Questions
87 * Tcl Crash Course:: Tcl Crash Course
88 * License:: GNU Free Documentation License
89
90 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
91 @comment case issue with ``Index.html'' and ``index.html''
92 @comment Occurs when creating ``--html --no-split'' output
93 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
94 * OpenOCD Concept Index:: Concept Index
95 * Command and Driver Index:: Command and Driver Index
96 @end menu
97
98 @node About
99 @unnumbered About
100 @cindex about
101
102 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
103 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
104 Since that time, the project has grown into an active open-source project,
105 supported by a diverse community of software and hardware developers from
106 around the world.
107
108 @section What is OpenOCD?
109 @cindex TAP
110 @cindex JTAG
111
112 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
113 in-system programming and boundary-scan testing for embedded target
114 devices.
115
116 It does so with the assistance of a @dfn{debug adapter}, which is
117 a small hardware module which helps provide the right kind of
118 electrical signaling to the target being debugged. These are
119 required since the debug host (on which OpenOCD runs) won't
120 usually have native support for such signaling, or the connector
121 needed to hook up to the target.
122
123 Such debug adapters support one or more @dfn{transport} protocols,
124 each of which involves different electrical signaling (and uses
125 different messaging protocols on top of that signaling). There
126 are many types of debug adapter, and little uniformity in what
127 they are called. (There are also product naming differences.)
128
129 These adapters are sometimes packaged as discrete dongles, which
130 may generically be called @dfn{hardware interface dongles}.
131 Some development boards also integrate them directly, which may
132 let the development board connect directly to the debug
133 host over USB (and sometimes also to power it over USB).
134
135 For example, a @dfn{JTAG Adapter} supports JTAG
136 signaling, and is used to communicate
137 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
138 A @dfn{TAP} is a ``Test Access Port'', a module which processes
139 special instructions and data. TAPs are daisy-chained within and
140 between chips and boards. JTAG supports debugging and boundary
141 scan operations.
142
143 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
144 signaling to communicate with some newer ARM cores, as well as debug
145 adapters which support both JTAG and SWD transports. SWD supports only
146 debugging, whereas JTAG also supports boundary scan operations.
147
148 For some chips, there are also @dfn{Programming Adapters} supporting
149 special transports used only to write code to flash memory, without
150 support for on-chip debugging or boundary scan.
151 (At this writing, OpenOCD does not support such non-debug adapters.)
152
153
154 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
155 USB-based, parallel port-based, and other standalone boxes that run
156 OpenOCD internally. @xref{Debug Adapter Hardware}.
157
158 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
159 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
160 (Stellaris LM3, ST STM32 and Energy Micro EFM32) and Intel Quark (x10xx)
161 based cores to be debugged via the GDB protocol.
162
163 @b{Flash Programming:} Flash writing is supported for external
164 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
165 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
166 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
167 controllers (LPC3180, Orion, S3C24xx, more) is included.
168
169 @section OpenOCD Web Site
170
171 The OpenOCD web site provides the latest public news from the community:
172
173 @uref{http://openocd.sourceforge.net/}
174
175 @section Latest User's Guide:
176
177 The user's guide you are now reading may not be the latest one
178 available. A version for more recent code may be available.
179 Its HTML form is published regularly at:
180
181 @uref{http://openocd.sourceforge.net/doc/html/index.html}
182
183 PDF form is likewise published at:
184
185 @uref{http://openocd.sourceforge.net/doc/pdf/openocd.pdf}
186
187 @section OpenOCD User's Forum
188
189 There is an OpenOCD forum (phpBB) hosted by SparkFun,
190 which might be helpful to you. Note that if you want
191 anything to come to the attention of developers, you
192 should post it to the OpenOCD Developer Mailing List
193 instead of this forum.
194
195 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196
197 @section OpenOCD User's Mailing List
198
199 The OpenOCD User Mailing List provides the primary means of
200 communication between users:
201
202 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
203
204 @section OpenOCD IRC
205
206 Support can also be found on irc:
207 @uref{irc://irc.freenode.net/openocd}
208
209 @node Developers
210 @chapter OpenOCD Developer Resources
211 @cindex developers
212
213 If you are interested in improving the state of OpenOCD's debugging and
214 testing support, new contributions will be welcome. Motivated developers
215 can produce new target, flash or interface drivers, improve the
216 documentation, as well as more conventional bug fixes and enhancements.
217
218 The resources in this chapter are available for developers wishing to explore
219 or expand the OpenOCD source code.
220
221 @section OpenOCD Git Repository
222
223 During the 0.3.x release cycle, OpenOCD switched from Subversion to
224 a Git repository hosted at SourceForge. The repository URL is:
225
226 @uref{git://git.code.sf.net/p/openocd/code}
227
228 or via http
229
230 @uref{http://git.code.sf.net/p/openocd/code}
231
232 You may prefer to use a mirror and the HTTP protocol:
233
234 @uref{http://repo.or.cz/r/openocd.git}
235
236 With standard Git tools, use @command{git clone} to initialize
237 a local repository, and @command{git pull} to update it.
238 There are also gitweb pages letting you browse the repository
239 with a web browser, or download arbitrary snapshots without
240 needing a Git client:
241
242 @uref{http://repo.or.cz/w/openocd.git}
243
244 The @file{README} file contains the instructions for building the project
245 from the repository or a snapshot.
246
247 Developers that want to contribute patches to the OpenOCD system are
248 @b{strongly} encouraged to work against mainline.
249 Patches created against older versions may require additional
250 work from their submitter in order to be updated for newer releases.
251
252 @section Doxygen Developer Manual
253
254 During the 0.2.x release cycle, the OpenOCD project began
255 providing a Doxygen reference manual. This document contains more
256 technical information about the software internals, development
257 processes, and similar documentation:
258
259 @uref{http://openocd.sourceforge.net/doc/doxygen/html/index.html}
260
261 This document is a work-in-progress, but contributions would be welcome
262 to fill in the gaps. All of the source files are provided in-tree,
263 listed in the Doxyfile configuration at the top of the source tree.
264
265 @section Gerrit Review System
266
267 All changes in the OpenOCD Git repository go through the web-based Gerrit
268 Code Review System:
269
270 @uref{http://openocd.zylin.com/}
271
272 After a one-time registration and repository setup, anyone can push commits
273 from their local Git repository directly into Gerrit.
274 All users and developers are encouraged to review, test, discuss and vote
275 for changes in Gerrit. The feedback provides the basis for a maintainer to
276 eventually submit the change to the main Git repository.
277
278 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
279 Developer Manual, contains basic information about how to connect a
280 repository to Gerrit, prepare and push patches. Patch authors are expected to
281 maintain their changes while they're in Gerrit, respond to feedback and if
282 necessary rework and push improved versions of the change.
283
284 @section OpenOCD Developer Mailing List
285
286 The OpenOCD Developer Mailing List provides the primary means of
287 communication between developers:
288
289 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
290
291 @section OpenOCD Bug Tracker
292
293 The OpenOCD Bug Tracker is hosted on SourceForge:
294
295 @uref{https://sourceforge.net/p/openocd/tickets/}
296
297
298 @node Debug Adapter Hardware
299 @chapter Debug Adapter Hardware
300 @cindex dongles
301 @cindex FTDI
302 @cindex wiggler
303 @cindex zy1000
304 @cindex printer port
305 @cindex USB Adapter
306 @cindex RTCK
307
308 Defined: @b{dongle}: A small device that plugs into a computer and serves as
309 an adapter .... [snip]
310
311 In the OpenOCD case, this generally refers to @b{a small adapter} that
312 attaches to your computer via USB or the parallel port. One
313 exception is the Ultimate Solutions ZY1000, packaged as a small box you
314 attach via an ethernet cable. The ZY1000 has the advantage that it does not
315 require any drivers to be installed on the developer PC. It also has
316 a built in web interface. It supports RTCK/RCLK or adaptive clocking
317 and has a built-in relay to power cycle targets remotely.
318
319
320 @section Choosing a Dongle
321
322 There are several things you should keep in mind when choosing a dongle.
323
324 @enumerate
325 @item @b{Transport} Does it support the kind of communication that you need?
326 OpenOCD focusses mostly on JTAG. Your version may also support
327 other ways to communicate with target devices.
328 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
329 Does your dongle support it? You might need a level converter.
330 @item @b{Pinout} What pinout does your target board use?
331 Does your dongle support it? You may be able to use jumper
332 wires, or an "octopus" connector, to convert pinouts.
333 @item @b{Connection} Does your computer have the USB, parallel, or
334 Ethernet port needed?
335 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
336 RTCK support (also known as ``adaptive clocking'')?
337 @end enumerate
338
339 @section Stand-alone JTAG Probe
340
341 The ZY1000 from Ultimate Solutions is technically not a dongle but a
342 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
343 running on the developer's host computer.
344 Once installed on a network using DHCP or a static IP assignment, users can
345 access the ZY1000 probe locally or remotely from any host with access to the
346 IP address assigned to the probe.
347 The ZY1000 provides an intuitive web interface with direct access to the
348 OpenOCD debugger.
349 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
350 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
351 the target.
352 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
353 to power cycle the target remotely.
354
355 For more information, visit:
356
357 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/210-zylin-zy1000-main}
358
359 @section USB FT2232 Based
360
361 There are many USB JTAG dongles on the market, many of them based
362 on a chip from ``Future Technology Devices International'' (FTDI)
363 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
364 See: @url{http://www.ftdichip.com} for more information.
365 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
366 chips started to become available in JTAG adapters. Around 2012, a new
367 variant appeared - FT232H - this is a single-channel version of FT2232H.
368 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
369 clocking.)
370
371 The FT2232 chips are flexible enough to support some other
372 transport options, such as SWD or the SPI variants used to
373 program some chips. They have two communications channels,
374 and one can be used for a UART adapter at the same time the
375 other one is used to provide a debug adapter.
376
377 Also, some development boards integrate an FT2232 chip to serve as
378 a built-in low-cost debug adapter and USB-to-serial solution.
379
380 @itemize @bullet
381 @item @b{usbjtag}
382 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
383 @item @b{jtagkey}
384 @* See: @url{http://www.amontec.com/jtagkey.shtml}
385 @item @b{jtagkey2}
386 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
387 @item @b{oocdlink}
388 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
389 @item @b{signalyzer}
390 @* See: @url{http://www.signalyzer.com}
391 @item @b{Stellaris Eval Boards}
392 @* See: @url{http://www.ti.com} - The Stellaris eval boards
393 bundle FT2232-based JTAG and SWD support, which can be used to debug
394 the Stellaris chips. Using separate JTAG adapters is optional.
395 These boards can also be used in a "pass through" mode as JTAG adapters
396 to other target boards, disabling the Stellaris chip.
397 @item @b{TI/Luminary ICDI}
398 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
399 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
400 Evaluation Kits. Like the non-detachable FT2232 support on the other
401 Stellaris eval boards, they can be used to debug other target boards.
402 @item @b{olimex-jtag}
403 @* See: @url{http://www.olimex.com}
404 @item @b{Flyswatter/Flyswatter2}
405 @* See: @url{http://www.tincantools.com}
406 @item @b{turtelizer2}
407 @* See:
408 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
409 @url{http://www.ethernut.de}
410 @item @b{comstick}
411 @* Link: @url{http://www.hitex.com/index.php?id=383}
412 @item @b{stm32stick}
413 @* Link @url{http://www.hitex.com/stm32-stick}
414 @item @b{axm0432_jtag}
415 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
416 to be available anymore as of April 2012.
417 @item @b{cortino}
418 @* Link @url{http://www.hitex.com/index.php?id=cortino}
419 @item @b{dlp-usb1232h}
420 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
421 @item @b{digilent-hs1}
422 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
423 @item @b{opendous}
424 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
425 (OpenHardware).
426 @item @b{JTAG-lock-pick Tiny 2}
427 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
428
429 @item @b{GW16042}
430 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
431 FT2232H-based
432
433 @end itemize
434 @section USB-JTAG / Altera USB-Blaster compatibles
435
436 These devices also show up as FTDI devices, but are not
437 protocol-compatible with the FT2232 devices. They are, however,
438 protocol-compatible among themselves. USB-JTAG devices typically consist
439 of a FT245 followed by a CPLD that understands a particular protocol,
440 or emulates this protocol using some other hardware.
441
442 They may appear under different USB VID/PID depending on the particular
443 product. The driver can be configured to search for any VID/PID pair
444 (see the section on driver commands).
445
446 @itemize
447 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
448 @* Link: @url{http://ixo-jtag.sourceforge.net/}
449 @item @b{Altera USB-Blaster}
450 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
451 @end itemize
452
453 @section USB JLINK based
454 There are several OEM versions of the Segger @b{JLINK} adapter. It is
455 an example of a micro controller based JTAG adapter, it uses an
456 AT91SAM764 internally.
457
458 @itemize @bullet
459 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
460 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
461 @item @b{SEGGER JLINK}
462 @* Link: @url{http://www.segger.com/jlink.html}
463 @item @b{IAR J-Link}
464 @* Link: @url{http://www.iar.com/en/products/hardware-debug-probes/iar-j-link/}
465 @end itemize
466
467 @section USB RLINK based
468 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
469 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
470 SWD and not JTAG, thus not supported.
471
472 @itemize @bullet
473 @item @b{Raisonance RLink}
474 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
475 @item @b{STM32 Primer}
476 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
477 @item @b{STM32 Primer2}
478 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
479 @end itemize
480
481 @section USB ST-LINK based
482 ST Micro has an adapter called @b{ST-LINK}.
483 They only work with ST Micro chips, notably STM32 and STM8.
484
485 @itemize @bullet
486 @item @b{ST-LINK}
487 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
488 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
489 @item @b{ST-LINK/V2}
490 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
491 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
492 @end itemize
493
494 For info the original ST-LINK enumerates using the mass storage usb class; however,
495 its implementation is completely broken. The result is this causes issues under Linux.
496 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
497 @itemize @bullet
498 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
499 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
500 @end itemize
501
502 @section USB TI/Stellaris ICDI based
503 Texas Instruments has an adapter called @b{ICDI}.
504 It is not to be confused with the FTDI based adapters that were originally fitted to their
505 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
506
507 @section USB CMSIS-DAP based
508 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
509 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
510
511 @section USB Other
512 @itemize @bullet
513 @item @b{USBprog}
514 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
515
516 @item @b{USB - Presto}
517 @* Link: @url{http://tools.asix.net/prg_presto.htm}
518
519 @item @b{Versaloon-Link}
520 @* Link: @url{http://www.versaloon.com}
521
522 @item @b{ARM-JTAG-EW}
523 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
524
525 @item @b{Buspirate}
526 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
527
528 @item @b{opendous}
529 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
530
531 @item @b{estick}
532 @* Link: @url{http://code.google.com/p/estick-jtag/}
533
534 @item @b{Keil ULINK v1}
535 @* Link: @url{http://www.keil.com/ulink1/}
536 @end itemize
537
538 @section IBM PC Parallel Printer Port Based
539
540 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
541 and the Macraigor Wiggler. There are many clones and variations of
542 these on the market.
543
544 Note that parallel ports are becoming much less common, so if you
545 have the choice you should probably avoid these adapters in favor
546 of USB-based ones.
547
548 @itemize @bullet
549
550 @item @b{Wiggler} - There are many clones of this.
551 @* Link: @url{http://www.macraigor.com/wiggler.htm}
552
553 @item @b{DLC5} - From XILINX - There are many clones of this
554 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
555 produced, PDF schematics are easily found and it is easy to make.
556
557 @item @b{Amontec - JTAG Accelerator}
558 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
559
560 @item @b{Wiggler2}
561 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
562
563 @item @b{Wiggler_ntrst_inverted}
564 @* Yet another variation - See the source code, src/jtag/parport.c
565
566 @item @b{old_amt_wiggler}
567 @* Unknown - probably not on the market today
568
569 @item @b{arm-jtag}
570 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
571
572 @item @b{chameleon}
573 @* Link: @url{http://www.amontec.com/chameleon.shtml}
574
575 @item @b{Triton}
576 @* Unknown.
577
578 @item @b{Lattice}
579 @* ispDownload from Lattice Semiconductor
580 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
581
582 @item @b{flashlink}
583 @* From ST Microsystems;
584 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
585
586 @end itemize
587
588 @section Other...
589 @itemize @bullet
590
591 @item @b{ep93xx}
592 @* An EP93xx based Linux machine using the GPIO pins directly.
593
594 @item @b{at91rm9200}
595 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
596
597 @item @b{bcm2835gpio}
598 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
599
600 @item @b{jtag_vpi}
601 @* A JTAG driver acting as a client for the JTAG VPI server interface.
602 @* Link: @url{http://github.com/fjullien/jtag_vpi}
603
604 @end itemize
605
606 @node About Jim-Tcl
607 @chapter About Jim-Tcl
608 @cindex Jim-Tcl
609 @cindex tcl
610
611 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
612 This programming language provides a simple and extensible
613 command interpreter.
614
615 All commands presented in this Guide are extensions to Jim-Tcl.
616 You can use them as simple commands, without needing to learn
617 much of anything about Tcl.
618 Alternatively, you can write Tcl programs with them.
619
620 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
621 There is an active and responsive community, get on the mailing list
622 if you have any questions. Jim-Tcl maintainers also lurk on the
623 OpenOCD mailing list.
624
625 @itemize @bullet
626 @item @b{Jim vs. Tcl}
627 @* Jim-Tcl is a stripped down version of the well known Tcl language,
628 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
629 fewer features. Jim-Tcl is several dozens of .C files and .H files and
630 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
631 4.2 MB .zip file containing 1540 files.
632
633 @item @b{Missing Features}
634 @* Our practice has been: Add/clone the real Tcl feature if/when
635 needed. We welcome Jim-Tcl improvements, not bloat. Also there
636 are a large number of optional Jim-Tcl features that are not
637 enabled in OpenOCD.
638
639 @item @b{Scripts}
640 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
641 command interpreter today is a mixture of (newer)
642 Jim-Tcl commands, and the (older) original command interpreter.
643
644 @item @b{Commands}
645 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
646 can type a Tcl for() loop, set variables, etc.
647 Some of the commands documented in this guide are implemented
648 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
649
650 @item @b{Historical Note}
651 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
652 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
653 as a Git submodule, which greatly simplified upgrading Jim-Tcl
654 to benefit from new features and bugfixes in Jim-Tcl.
655
656 @item @b{Need a crash course in Tcl?}
657 @*@xref{Tcl Crash Course}.
658 @end itemize
659
660 @node Running
661 @chapter Running
662 @cindex command line options
663 @cindex logfile
664 @cindex directory search
665
666 Properly installing OpenOCD sets up your operating system to grant it access
667 to the debug adapters. On Linux, this usually involves installing a file
668 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
669 that works for many common adapters is shipped with OpenOCD in the
670 @file{contrib} directory. MS-Windows needs
671 complex and confusing driver configuration for every peripheral. Such issues
672 are unique to each operating system, and are not detailed in this User's Guide.
673
674 Then later you will invoke the OpenOCD server, with various options to
675 tell it how each debug session should work.
676 The @option{--help} option shows:
677 @verbatim
678 bash$ openocd --help
679
680 --help | -h display this help
681 --version | -v display OpenOCD version
682 --file | -f use configuration file <name>
683 --search | -s dir to search for config files and scripts
684 --debug | -d set debug level <0-3>
685 --log_output | -l redirect log output to file <name>
686 --command | -c run <command>
687 @end verbatim
688
689 If you don't give any @option{-f} or @option{-c} options,
690 OpenOCD tries to read the configuration file @file{openocd.cfg}.
691 To specify one or more different
692 configuration files, use @option{-f} options. For example:
693
694 @example
695 openocd -f config1.cfg -f config2.cfg -f config3.cfg
696 @end example
697
698 Configuration files and scripts are searched for in
699 @enumerate
700 @item the current directory,
701 @item any search dir specified on the command line using the @option{-s} option,
702 @item any search dir specified using the @command{add_script_search_dir} command,
703 @item @file{$HOME/.openocd} (not on Windows),
704 @item the site wide script library @file{$pkgdatadir/site} and
705 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
706 @end enumerate
707 The first found file with a matching file name will be used.
708
709 @quotation Note
710 Don't try to use configuration script names or paths which
711 include the "#" character. That character begins Tcl comments.
712 @end quotation
713
714 @section Simple setup, no customization
715
716 In the best case, you can use two scripts from one of the script
717 libraries, hook up your JTAG adapter, and start the server ... and
718 your JTAG setup will just work "out of the box". Always try to
719 start by reusing those scripts, but assume you'll need more
720 customization even if this works. @xref{OpenOCD Project Setup}.
721
722 If you find a script for your JTAG adapter, and for your board or
723 target, you may be able to hook up your JTAG adapter then start
724 the server with some variation of one of the following:
725
726 @example
727 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
728 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
729 @end example
730
731 You might also need to configure which reset signals are present,
732 using @option{-c 'reset_config trst_and_srst'} or something similar.
733 If all goes well you'll see output something like
734
735 @example
736 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
737 For bug reports, read
738 http://openocd.sourceforge.net/doc/doxygen/bugs.html
739 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
740 (mfg: 0x23b, part: 0xba00, ver: 0x3)
741 @end example
742
743 Seeing that "tap/device found" message, and no warnings, means
744 the JTAG communication is working. That's a key milestone, but
745 you'll probably need more project-specific setup.
746
747 @section What OpenOCD does as it starts
748
749 OpenOCD starts by processing the configuration commands provided
750 on the command line or, if there were no @option{-c command} or
751 @option{-f file.cfg} options given, in @file{openocd.cfg}.
752 @xref{configurationstage,,Configuration Stage}.
753 At the end of the configuration stage it verifies the JTAG scan
754 chain defined using those commands; your configuration should
755 ensure that this always succeeds.
756 Normally, OpenOCD then starts running as a daemon.
757 Alternatively, commands may be used to terminate the configuration
758 stage early, perform work (such as updating some flash memory),
759 and then shut down without acting as a daemon.
760
761 Once OpenOCD starts running as a daemon, it waits for connections from
762 clients (Telnet, GDB, Other) and processes the commands issued through
763 those channels.
764
765 If you are having problems, you can enable internal debug messages via
766 the @option{-d} option.
767
768 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
769 @option{-c} command line switch.
770
771 To enable debug output (when reporting problems or working on OpenOCD
772 itself), use the @option{-d} command line switch. This sets the
773 @option{debug_level} to "3", outputting the most information,
774 including debug messages. The default setting is "2", outputting only
775 informational messages, warnings and errors. You can also change this
776 setting from within a telnet or gdb session using @command{debug_level<n>}
777 (@pxref{debuglevel,,debug_level}).
778
779 You can redirect all output from the daemon to a file using the
780 @option{-l <logfile>} switch.
781
782 Note! OpenOCD will launch the GDB & telnet server even if it can not
783 establish a connection with the target. In general, it is possible for
784 the JTAG controller to be unresponsive until the target is set up
785 correctly via e.g. GDB monitor commands in a GDB init script.
786
787 @node OpenOCD Project Setup
788 @chapter OpenOCD Project Setup
789
790 To use OpenOCD with your development projects, you need to do more than
791 just connect the JTAG adapter hardware (dongle) to your development board
792 and start the OpenOCD server.
793 You also need to configure your OpenOCD server so that it knows
794 about your adapter and board, and helps your work.
795 You may also want to connect OpenOCD to GDB, possibly
796 using Eclipse or some other GUI.
797
798 @section Hooking up the JTAG Adapter
799
800 Today's most common case is a dongle with a JTAG cable on one side
801 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
802 and a USB cable on the other.
803 Instead of USB, some cables use Ethernet;
804 older ones may use a PC parallel port, or even a serial port.
805
806 @enumerate
807 @item @emph{Start with power to your target board turned off},
808 and nothing connected to your JTAG adapter.
809 If you're particularly paranoid, unplug power to the board.
810 It's important to have the ground signal properly set up,
811 unless you are using a JTAG adapter which provides
812 galvanic isolation between the target board and the
813 debugging host.
814
815 @item @emph{Be sure it's the right kind of JTAG connector.}
816 If your dongle has a 20-pin ARM connector, you need some kind
817 of adapter (or octopus, see below) to hook it up to
818 boards using 14-pin or 10-pin connectors ... or to 20-pin
819 connectors which don't use ARM's pinout.
820
821 In the same vein, make sure the voltage levels are compatible.
822 Not all JTAG adapters have the level shifters needed to work
823 with 1.2 Volt boards.
824
825 @item @emph{Be certain the cable is properly oriented} or you might
826 damage your board. In most cases there are only two possible
827 ways to connect the cable.
828 Connect the JTAG cable from your adapter to the board.
829 Be sure it's firmly connected.
830
831 In the best case, the connector is keyed to physically
832 prevent you from inserting it wrong.
833 This is most often done using a slot on the board's male connector
834 housing, which must match a key on the JTAG cable's female connector.
835 If there's no housing, then you must look carefully and
836 make sure pin 1 on the cable hooks up to pin 1 on the board.
837 Ribbon cables are frequently all grey except for a wire on one
838 edge, which is red. The red wire is pin 1.
839
840 Sometimes dongles provide cables where one end is an ``octopus'' of
841 color coded single-wire connectors, instead of a connector block.
842 These are great when converting from one JTAG pinout to another,
843 but are tedious to set up.
844 Use these with connector pinout diagrams to help you match up the
845 adapter signals to the right board pins.
846
847 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
848 A USB, parallel, or serial port connector will go to the host which
849 you are using to run OpenOCD.
850 For Ethernet, consult the documentation and your network administrator.
851
852 For USB-based JTAG adapters you have an easy sanity check at this point:
853 does the host operating system see the JTAG adapter? If you're running
854 Linux, try the @command{lsusb} command. If that host is an
855 MS-Windows host, you'll need to install a driver before OpenOCD works.
856
857 @item @emph{Connect the adapter's power supply, if needed.}
858 This step is primarily for non-USB adapters,
859 but sometimes USB adapters need extra power.
860
861 @item @emph{Power up the target board.}
862 Unless you just let the magic smoke escape,
863 you're now ready to set up the OpenOCD server
864 so you can use JTAG to work with that board.
865
866 @end enumerate
867
868 Talk with the OpenOCD server using
869 telnet (@code{telnet localhost 4444} on many systems) or GDB.
870 @xref{GDB and OpenOCD}.
871
872 @section Project Directory
873
874 There are many ways you can configure OpenOCD and start it up.
875
876 A simple way to organize them all involves keeping a
877 single directory for your work with a given board.
878 When you start OpenOCD from that directory,
879 it searches there first for configuration files, scripts,
880 files accessed through semihosting,
881 and for code you upload to the target board.
882 It is also the natural place to write files,
883 such as log files and data you download from the board.
884
885 @section Configuration Basics
886
887 There are two basic ways of configuring OpenOCD, and
888 a variety of ways you can mix them.
889 Think of the difference as just being how you start the server:
890
891 @itemize
892 @item Many @option{-f file} or @option{-c command} options on the command line
893 @item No options, but a @dfn{user config file}
894 in the current directory named @file{openocd.cfg}
895 @end itemize
896
897 Here is an example @file{openocd.cfg} file for a setup
898 using a Signalyzer FT2232-based JTAG adapter to talk to
899 a board with an Atmel AT91SAM7X256 microcontroller:
900
901 @example
902 source [find interface/signalyzer.cfg]
903
904 # GDB can also flash my flash!
905 gdb_memory_map enable
906 gdb_flash_program enable
907
908 source [find target/sam7x256.cfg]
909 @end example
910
911 Here is the command line equivalent of that configuration:
912
913 @example
914 openocd -f interface/signalyzer.cfg \
915 -c "gdb_memory_map enable" \
916 -c "gdb_flash_program enable" \
917 -f target/sam7x256.cfg
918 @end example
919
920 You could wrap such long command lines in shell scripts,
921 each supporting a different development task.
922 One might re-flash the board with a specific firmware version.
923 Another might set up a particular debugging or run-time environment.
924
925 @quotation Important
926 At this writing (October 2009) the command line method has
927 problems with how it treats variables.
928 For example, after @option{-c "set VAR value"}, or doing the
929 same in a script, the variable @var{VAR} will have no value
930 that can be tested in a later script.
931 @end quotation
932
933 Here we will focus on the simpler solution: one user config
934 file, including basic configuration plus any TCL procedures
935 to simplify your work.
936
937 @section User Config Files
938 @cindex config file, user
939 @cindex user config file
940 @cindex config file, overview
941
942 A user configuration file ties together all the parts of a project
943 in one place.
944 One of the following will match your situation best:
945
946 @itemize
947 @item Ideally almost everything comes from configuration files
948 provided by someone else.
949 For example, OpenOCD distributes a @file{scripts} directory
950 (probably in @file{/usr/share/openocd/scripts} on Linux).
951 Board and tool vendors can provide these too, as can individual
952 user sites; the @option{-s} command line option lets you say
953 where to find these files. (@xref{Running}.)
954 The AT91SAM7X256 example above works this way.
955
956 Three main types of non-user configuration file each have their
957 own subdirectory in the @file{scripts} directory:
958
959 @enumerate
960 @item @b{interface} -- one for each different debug adapter;
961 @item @b{board} -- one for each different board
962 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
963 @end enumerate
964
965 Best case: include just two files, and they handle everything else.
966 The first is an interface config file.
967 The second is board-specific, and it sets up the JTAG TAPs and
968 their GDB targets (by deferring to some @file{target.cfg} file),
969 declares all flash memory, and leaves you nothing to do except
970 meet your deadline:
971
972 @example
973 source [find interface/olimex-jtag-tiny.cfg]
974 source [find board/csb337.cfg]
975 @end example
976
977 Boards with a single microcontroller often won't need more
978 than the target config file, as in the AT91SAM7X256 example.
979 That's because there is no external memory (flash, DDR RAM), and
980 the board differences are encapsulated by application code.
981
982 @item Maybe you don't know yet what your board looks like to JTAG.
983 Once you know the @file{interface.cfg} file to use, you may
984 need help from OpenOCD to discover what's on the board.
985 Once you find the JTAG TAPs, you can just search for appropriate
986 target and board
987 configuration files ... or write your own, from the bottom up.
988 @xref{autoprobing,,Autoprobing}.
989
990 @item You can often reuse some standard config files but
991 need to write a few new ones, probably a @file{board.cfg} file.
992 You will be using commands described later in this User's Guide,
993 and working with the guidelines in the next chapter.
994
995 For example, there may be configuration files for your JTAG adapter
996 and target chip, but you need a new board-specific config file
997 giving access to your particular flash chips.
998 Or you might need to write another target chip configuration file
999 for a new chip built around the Cortex M3 core.
1000
1001 @quotation Note
1002 When you write new configuration files, please submit
1003 them for inclusion in the next OpenOCD release.
1004 For example, a @file{board/newboard.cfg} file will help the
1005 next users of that board, and a @file{target/newcpu.cfg}
1006 will help support users of any board using that chip.
1007 @end quotation
1008
1009 @item
1010 You may may need to write some C code.
1011 It may be as simple as supporting a new FT2232 or parport
1012 based adapter; a bit more involved, like a NAND or NOR flash
1013 controller driver; or a big piece of work like supporting
1014 a new chip architecture.
1015 @end itemize
1016
1017 Reuse the existing config files when you can.
1018 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1019 You may find a board configuration that's a good example to follow.
1020
1021 When you write config files, separate the reusable parts
1022 (things every user of that interface, chip, or board needs)
1023 from ones specific to your environment and debugging approach.
1024 @itemize
1025
1026 @item
1027 For example, a @code{gdb-attach} event handler that invokes
1028 the @command{reset init} command will interfere with debugging
1029 early boot code, which performs some of the same actions
1030 that the @code{reset-init} event handler does.
1031
1032 @item
1033 Likewise, the @command{arm9 vector_catch} command (or
1034 @cindex vector_catch
1035 its siblings @command{xscale vector_catch}
1036 and @command{cortex_m vector_catch}) can be a timesaver
1037 during some debug sessions, but don't make everyone use that either.
1038 Keep those kinds of debugging aids in your user config file,
1039 along with messaging and tracing setup.
1040 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1041
1042 @item
1043 You might need to override some defaults.
1044 For example, you might need to move, shrink, or back up the target's
1045 work area if your application needs much SRAM.
1046
1047 @item
1048 TCP/IP port configuration is another example of something which
1049 is environment-specific, and should only appear in
1050 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1051 @end itemize
1052
1053 @section Project-Specific Utilities
1054
1055 A few project-specific utility
1056 routines may well speed up your work.
1057 Write them, and keep them in your project's user config file.
1058
1059 For example, if you are making a boot loader work on a
1060 board, it's nice to be able to debug the ``after it's
1061 loaded to RAM'' parts separately from the finicky early
1062 code which sets up the DDR RAM controller and clocks.
1063 A script like this one, or a more GDB-aware sibling,
1064 may help:
1065
1066 @example
1067 proc ramboot @{ @} @{
1068 # Reset, running the target's "reset-init" scripts
1069 # to initialize clocks and the DDR RAM controller.
1070 # Leave the CPU halted.
1071 reset init
1072
1073 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1074 load_image u-boot.bin 0x20000000
1075
1076 # Start running.
1077 resume 0x20000000
1078 @}
1079 @end example
1080
1081 Then once that code is working you will need to make it
1082 boot from NOR flash; a different utility would help.
1083 Alternatively, some developers write to flash using GDB.
1084 (You might use a similar script if you're working with a flash
1085 based microcontroller application instead of a boot loader.)
1086
1087 @example
1088 proc newboot @{ @} @{
1089 # Reset, leaving the CPU halted. The "reset-init" event
1090 # proc gives faster access to the CPU and to NOR flash;
1091 # "reset halt" would be slower.
1092 reset init
1093
1094 # Write standard version of U-Boot into the first two
1095 # sectors of NOR flash ... the standard version should
1096 # do the same lowlevel init as "reset-init".
1097 flash protect 0 0 1 off
1098 flash erase_sector 0 0 1
1099 flash write_bank 0 u-boot.bin 0x0
1100 flash protect 0 0 1 on
1101
1102 # Reboot from scratch using that new boot loader.
1103 reset run
1104 @}
1105 @end example
1106
1107 You may need more complicated utility procedures when booting
1108 from NAND.
1109 That often involves an extra bootloader stage,
1110 running from on-chip SRAM to perform DDR RAM setup so it can load
1111 the main bootloader code (which won't fit into that SRAM).
1112
1113 Other helper scripts might be used to write production system images,
1114 involving considerably more than just a three stage bootloader.
1115
1116 @section Target Software Changes
1117
1118 Sometimes you may want to make some small changes to the software
1119 you're developing, to help make JTAG debugging work better.
1120 For example, in C or assembly language code you might
1121 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1122 handling issues like:
1123
1124 @itemize @bullet
1125
1126 @item @b{Watchdog Timers}...
1127 Watchog timers are typically used to automatically reset systems if
1128 some application task doesn't periodically reset the timer. (The
1129 assumption is that the system has locked up if the task can't run.)
1130 When a JTAG debugger halts the system, that task won't be able to run
1131 and reset the timer ... potentially causing resets in the middle of
1132 your debug sessions.
1133
1134 It's rarely a good idea to disable such watchdogs, since their usage
1135 needs to be debugged just like all other parts of your firmware.
1136 That might however be your only option.
1137
1138 Look instead for chip-specific ways to stop the watchdog from counting
1139 while the system is in a debug halt state. It may be simplest to set
1140 that non-counting mode in your debugger startup scripts. You may however
1141 need a different approach when, for example, a motor could be physically
1142 damaged by firmware remaining inactive in a debug halt state. That might
1143 involve a type of firmware mode where that "non-counting" mode is disabled
1144 at the beginning then re-enabled at the end; a watchdog reset might fire
1145 and complicate the debug session, but hardware (or people) would be
1146 protected.@footnote{Note that many systems support a "monitor mode" debug
1147 that is a somewhat cleaner way to address such issues. You can think of
1148 it as only halting part of the system, maybe just one task,
1149 instead of the whole thing.
1150 At this writing, January 2010, OpenOCD based debugging does not support
1151 monitor mode debug, only "halt mode" debug.}
1152
1153 @item @b{ARM Semihosting}...
1154 @cindex ARM semihosting
1155 When linked with a special runtime library provided with many
1156 toolchains@footnote{See chapter 8 "Semihosting" in
1157 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1158 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1159 The CodeSourcery EABI toolchain also includes a semihosting library.},
1160 your target code can use I/O facilities on the debug host. That library
1161 provides a small set of system calls which are handled by OpenOCD.
1162 It can let the debugger provide your system console and a file system,
1163 helping with early debugging or providing a more capable environment
1164 for sometimes-complex tasks like installing system firmware onto
1165 NAND or SPI flash.
1166
1167 @item @b{ARM Wait-For-Interrupt}...
1168 Many ARM chips synchronize the JTAG clock using the core clock.
1169 Low power states which stop that core clock thus prevent JTAG access.
1170 Idle loops in tasking environments often enter those low power states
1171 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1172
1173 You may want to @emph{disable that instruction} in source code,
1174 or otherwise prevent using that state,
1175 to ensure you can get JTAG access at any time.@footnote{As a more
1176 polite alternative, some processors have special debug-oriented
1177 registers which can be used to change various features including
1178 how the low power states are clocked while debugging.
1179 The STM32 DBGMCU_CR register is an example; at the cost of extra
1180 power consumption, JTAG can be used during low power states.}
1181 For example, the OpenOCD @command{halt} command may not
1182 work for an idle processor otherwise.
1183
1184 @item @b{Delay after reset}...
1185 Not all chips have good support for debugger access
1186 right after reset; many LPC2xxx chips have issues here.
1187 Similarly, applications that reconfigure pins used for
1188 JTAG access as they start will also block debugger access.
1189
1190 To work with boards like this, @emph{enable a short delay loop}
1191 the first thing after reset, before "real" startup activities.
1192 For example, one second's delay is usually more than enough
1193 time for a JTAG debugger to attach, so that
1194 early code execution can be debugged
1195 or firmware can be replaced.
1196
1197 @item @b{Debug Communications Channel (DCC)}...
1198 Some processors include mechanisms to send messages over JTAG.
1199 Many ARM cores support these, as do some cores from other vendors.
1200 (OpenOCD may be able to use this DCC internally, speeding up some
1201 operations like writing to memory.)
1202
1203 Your application may want to deliver various debugging messages
1204 over JTAG, by @emph{linking with a small library of code}
1205 provided with OpenOCD and using the utilities there to send
1206 various kinds of message.
1207 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1208
1209 @end itemize
1210
1211 @section Target Hardware Setup
1212
1213 Chip vendors often provide software development boards which
1214 are highly configurable, so that they can support all options
1215 that product boards may require. @emph{Make sure that any
1216 jumpers or switches match the system configuration you are
1217 working with.}
1218
1219 Common issues include:
1220
1221 @itemize @bullet
1222
1223 @item @b{JTAG setup} ...
1224 Boards may support more than one JTAG configuration.
1225 Examples include jumpers controlling pullups versus pulldowns
1226 on the nTRST and/or nSRST signals, and choice of connectors
1227 (e.g. which of two headers on the base board,
1228 or one from a daughtercard).
1229 For some Texas Instruments boards, you may need to jumper the
1230 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1231
1232 @item @b{Boot Modes} ...
1233 Complex chips often support multiple boot modes, controlled
1234 by external jumpers. Make sure this is set up correctly.
1235 For example many i.MX boards from NXP need to be jumpered
1236 to "ATX mode" to start booting using the on-chip ROM, when
1237 using second stage bootloader code stored in a NAND flash chip.
1238
1239 Such explicit configuration is common, and not limited to
1240 booting from NAND. You might also need to set jumpers to
1241 start booting using code loaded from an MMC/SD card; external
1242 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1243 flash; some external host; or various other sources.
1244
1245
1246 @item @b{Memory Addressing} ...
1247 Boards which support multiple boot modes may also have jumpers
1248 to configure memory addressing. One board, for example, jumpers
1249 external chipselect 0 (used for booting) to address either
1250 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1251 or NAND flash. When it's jumpered to address NAND flash, that
1252 board must also be told to start booting from on-chip ROM.
1253
1254 Your @file{board.cfg} file may also need to be told this jumper
1255 configuration, so that it can know whether to declare NOR flash
1256 using @command{flash bank} or instead declare NAND flash with
1257 @command{nand device}; and likewise which probe to perform in
1258 its @code{reset-init} handler.
1259
1260 A closely related issue is bus width. Jumpers might need to
1261 distinguish between 8 bit or 16 bit bus access for the flash
1262 used to start booting.
1263
1264 @item @b{Peripheral Access} ...
1265 Development boards generally provide access to every peripheral
1266 on the chip, sometimes in multiple modes (such as by providing
1267 multiple audio codec chips).
1268 This interacts with software
1269 configuration of pin multiplexing, where for example a
1270 given pin may be routed either to the MMC/SD controller
1271 or the GPIO controller. It also often interacts with
1272 configuration jumpers. One jumper may be used to route
1273 signals to an MMC/SD card slot or an expansion bus (which
1274 might in turn affect booting); others might control which
1275 audio or video codecs are used.
1276
1277 @end itemize
1278
1279 Plus you should of course have @code{reset-init} event handlers
1280 which set up the hardware to match that jumper configuration.
1281 That includes in particular any oscillator or PLL used to clock
1282 the CPU, and any memory controllers needed to access external
1283 memory and peripherals. Without such handlers, you won't be
1284 able to access those resources without working target firmware
1285 which can do that setup ... this can be awkward when you're
1286 trying to debug that target firmware. Even if there's a ROM
1287 bootloader which handles a few issues, it rarely provides full
1288 access to all board-specific capabilities.
1289
1290
1291 @node Config File Guidelines
1292 @chapter Config File Guidelines
1293
1294 This chapter is aimed at any user who needs to write a config file,
1295 including developers and integrators of OpenOCD and any user who
1296 needs to get a new board working smoothly.
1297 It provides guidelines for creating those files.
1298
1299 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1300 with files including the ones listed here.
1301 Use them as-is where you can; or as models for new files.
1302 @itemize @bullet
1303 @item @file{interface} ...
1304 These are for debug adapters.
1305 Files that configure JTAG adapters go here.
1306 @example
1307 $ ls interface -R
1308 interface/:
1309 altera-usb-blaster.cfg hilscher_nxhx50_re.cfg openocd-usb-hs.cfg
1310 arm-jtag-ew.cfg hitex_str9-comstick.cfg openrd.cfg
1311 at91rm9200.cfg icebear.cfg osbdm.cfg
1312 axm0432.cfg jlink.cfg parport.cfg
1313 busblaster.cfg jtagkey2.cfg parport_dlc5.cfg
1314 buspirate.cfg jtagkey2p.cfg redbee-econotag.cfg
1315 calao-usb-a9260-c01.cfg jtagkey.cfg redbee-usb.cfg
1316 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg rlink.cfg
1317 calao-usb-a9260.cfg jtag-lock-pick_tiny_2.cfg sheevaplug.cfg
1318 chameleon.cfg kt-link.cfg signalyzer.cfg
1319 cortino.cfg lisa-l.cfg signalyzer-h2.cfg
1320 digilent-hs1.cfg luminary.cfg signalyzer-h4.cfg
1321 dlp-usb1232h.cfg luminary-icdi.cfg signalyzer-lite.cfg
1322 dummy.cfg luminary-lm3s811.cfg stlink-v1.cfg
1323 estick.cfg minimodule.cfg stlink-v2.cfg
1324 flashlink.cfg neodb.cfg stm32-stick.cfg
1325 flossjtag.cfg ngxtech.cfg sysfsgpio-raspberrypi.cfg
1326 flossjtag-noeeprom.cfg olimex-arm-usb-ocd.cfg ti-icdi.cfg
1327 flyswatter2.cfg olimex-arm-usb-ocd-h.cfg turtelizer2.cfg
1328 flyswatter.cfg olimex-arm-usb-tiny-h.cfg ulink.cfg
1329 ftdi olimex-jtag-tiny.cfg usb-jtag.cfg
1330 hilscher_nxhx10_etm.cfg oocdlink.cfg usbprog.cfg
1331 hilscher_nxhx500_etm.cfg opendous.cfg vpaclink.cfg
1332 hilscher_nxhx500_re.cfg opendous_ftdi.cfg vsllink.cfg
1333 hilscher_nxhx50_etm.cfg openocd-usb.cfg xds100v2.cfg
1334
1335 interface/ftdi:
1336 axm0432.cfg hitex_str9-comstick.cfg olimex-jtag-tiny.cfg
1337 calao-usb-a9260-c01.cfg icebear.cfg oocdlink.cfg
1338 calao-usb-a9260-c02.cfg jtagkey2.cfg opendous_ftdi.cfg
1339 cortino.cfg jtagkey2p.cfg openocd-usb.cfg
1340 dlp-usb1232h.cfg jtagkey.cfg openocd-usb-hs.cfg
1341 dp_busblaster.cfg jtag-lock-pick_tiny_2.cfg openrd.cfg
1342 flossjtag.cfg kt-link.cfg redbee-econotag.cfg
1343 flossjtag-noeeprom.cfg lisa-l.cfg redbee-usb.cfg
1344 flyswatter2.cfg luminary.cfg sheevaplug.cfg
1345 flyswatter.cfg luminary-icdi.cfg signalyzer.cfg
1346 gw16042.cfg luminary-lm3s811.cfg signalyzer-lite.cfg
1347 hilscher_nxhx10_etm.cfg minimodule.cfg stm32-stick.cfg
1348 hilscher_nxhx500_etm.cfg neodb.cfg turtelizer2-revB.cfg
1349 hilscher_nxhx500_re.cfg ngxtech.cfg turtelizer2-revC.cfg
1350 hilscher_nxhx50_etm.cfg olimex-arm-usb-ocd.cfg vpaclink.cfg
1351 hilscher_nxhx50_re.cfg olimex-arm-usb-ocd-h.cfg xds100v2.cfg
1352 hitex_lpc1768stick.cfg olimex-arm-usb-tiny-h.cfg
1353 $
1354 @end example
1355 @item @file{board} ...
1356 think Circuit Board, PWA, PCB, they go by many names. Board files
1357 contain initialization items that are specific to a board.
1358 They reuse target configuration files, since the same
1359 microprocessor chips are used on many boards,
1360 but support for external parts varies widely. For
1361 example, the SDRAM initialization sequence for the board, or the type
1362 of external flash and what address it uses. Any initialization
1363 sequence to enable that external flash or SDRAM should be found in the
1364 board file. Boards may also contain multiple targets: two CPUs; or
1365 a CPU and an FPGA.
1366 @example
1367 $ ls board
1368 actux3.cfg lpc1850_spifi_generic.cfg
1369 am3517evm.cfg lpc4350_spifi_generic.cfg
1370 arm_evaluator7t.cfg lubbock.cfg
1371 at91cap7a-stk-sdram.cfg mcb1700.cfg
1372 at91eb40a.cfg microchip_explorer16.cfg
1373 at91rm9200-dk.cfg mini2440.cfg
1374 at91rm9200-ek.cfg mini6410.cfg
1375 at91sam9261-ek.cfg netgear-dg834v3.cfg
1376 at91sam9263-ek.cfg olimex_LPC2378STK.cfg
1377 at91sam9g20-ek.cfg olimex_lpc_h2148.cfg
1378 atmel_at91sam7s-ek.cfg olimex_sam7_ex256.cfg
1379 atmel_at91sam9260-ek.cfg olimex_sam9_l9260.cfg
1380 atmel_at91sam9rl-ek.cfg olimex_stm32_h103.cfg
1381 atmel_sam3n_ek.cfg olimex_stm32_h107.cfg
1382 atmel_sam3s_ek.cfg olimex_stm32_p107.cfg
1383 atmel_sam3u_ek.cfg omap2420_h4.cfg
1384 atmel_sam3x_ek.cfg open-bldc.cfg
1385 atmel_sam4s_ek.cfg openrd.cfg
1386 balloon3-cpu.cfg osk5912.cfg
1387 colibri.cfg phone_se_j100i.cfg
1388 crossbow_tech_imote2.cfg phytec_lpc3250.cfg
1389 csb337.cfg pic-p32mx.cfg
1390 csb732.cfg propox_mmnet1001.cfg
1391 da850evm.cfg pxa255_sst.cfg
1392 digi_connectcore_wi-9c.cfg redbee.cfg
1393 diolan_lpc4350-db1.cfg rsc-w910.cfg
1394 dm355evm.cfg sheevaplug.cfg
1395 dm365evm.cfg smdk6410.cfg
1396 dm6446evm.cfg spear300evb.cfg
1397 efikamx.cfg spear300evb_mod.cfg
1398 eir.cfg spear310evb20.cfg
1399 ek-lm3s1968.cfg spear310evb20_mod.cfg
1400 ek-lm3s3748.cfg spear320cpu.cfg
1401 ek-lm3s6965.cfg spear320cpu_mod.cfg
1402 ek-lm3s811.cfg steval_pcc010.cfg
1403 ek-lm3s811-revb.cfg stm320518_eval_stlink.cfg
1404 ek-lm3s8962.cfg stm32100b_eval.cfg
1405 ek-lm3s9b9x.cfg stm3210b_eval.cfg
1406 ek-lm3s9d92.cfg stm3210c_eval.cfg
1407 ek-lm4f120xl.cfg stm3210e_eval.cfg
1408 ek-lm4f232.cfg stm3220g_eval.cfg
1409 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1410 ethernut3.cfg stm3241g_eval.cfg
1411 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1412 hammer.cfg stm32f0discovery.cfg
1413 hilscher_nxdb500sys.cfg stm32f3discovery.cfg
1414 hilscher_nxeb500hmi.cfg stm32f4discovery.cfg
1415 hilscher_nxhx10.cfg stm32ldiscovery.cfg
1416 hilscher_nxhx500.cfg stm32vldiscovery.cfg
1417 hilscher_nxhx50.cfg str910-eval.cfg
1418 hilscher_nxsb100.cfg telo.cfg
1419 hitex_lpc1768stick.cfg ti_am335xevm.cfg
1420 hitex_lpc2929.cfg ti_beagleboard.cfg
1421 hitex_stm32-performancestick.cfg ti_beagleboard_xm.cfg
1422 hitex_str9-comstick.cfg ti_beaglebone.cfg
1423 iar_lpc1768.cfg ti_blaze.cfg
1424 iar_str912_sk.cfg ti_pandaboard.cfg
1425 icnova_imx53_sodimm.cfg ti_pandaboard_es.cfg
1426 icnova_sam9g45_sodimm.cfg topas910.cfg
1427 imx27ads.cfg topasa900.cfg
1428 imx27lnst.cfg twr-k60f120m.cfg
1429 imx28evk.cfg twr-k60n512.cfg
1430 imx31pdk.cfg tx25_stk5.cfg
1431 imx35pdk.cfg tx27_stk5.cfg
1432 imx53loco.cfg unknown_at91sam9260.cfg
1433 keil_mcb1700.cfg uptech_2410.cfg
1434 keil_mcb2140.cfg verdex.cfg
1435 kwikstik.cfg voipac.cfg
1436 linksys_nslu2.cfg voltcraft_dso-3062c.cfg
1437 lisa-l.cfg x300t.cfg
1438 logicpd_imx27.cfg zy1000.cfg
1439 $
1440 @end example
1441 @item @file{target} ...
1442 think chip. The ``target'' directory represents the JTAG TAPs
1443 on a chip
1444 which OpenOCD should control, not a board. Two common types of targets
1445 are ARM chips and FPGA or CPLD chips.
1446 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1447 the target config file defines all of them.
1448 @example
1449 $ ls target
1450 aduc702x.cfg lpc1763.cfg
1451 am335x.cfg lpc1764.cfg
1452 amdm37x.cfg lpc1765.cfg
1453 ar71xx.cfg lpc1766.cfg
1454 at32ap7000.cfg lpc1767.cfg
1455 at91r40008.cfg lpc1768.cfg
1456 at91rm9200.cfg lpc1769.cfg
1457 at91sam3ax_4x.cfg lpc1788.cfg
1458 at91sam3ax_8x.cfg lpc17xx.cfg
1459 at91sam3ax_xx.cfg lpc1850.cfg
1460 at91sam3nXX.cfg lpc2103.cfg
1461 at91sam3sXX.cfg lpc2124.cfg
1462 at91sam3u1c.cfg lpc2129.cfg
1463 at91sam3u1e.cfg lpc2148.cfg
1464 at91sam3u2c.cfg lpc2294.cfg
1465 at91sam3u2e.cfg lpc2378.cfg
1466 at91sam3u4c.cfg lpc2460.cfg
1467 at91sam3u4e.cfg lpc2478.cfg
1468 at91sam3uxx.cfg lpc2900.cfg
1469 at91sam3XXX.cfg lpc2xxx.cfg
1470 at91sam4sd32x.cfg lpc3131.cfg
1471 at91sam4sXX.cfg lpc3250.cfg
1472 at91sam4XXX.cfg lpc4350.cfg
1473 at91sam7se512.cfg lpc4350.cfg.orig
1474 at91sam7sx.cfg mc13224v.cfg
1475 at91sam7x256.cfg nuc910.cfg
1476 at91sam7x512.cfg omap2420.cfg
1477 at91sam9260.cfg omap3530.cfg
1478 at91sam9260_ext_RAM_ext_flash.cfg omap4430.cfg
1479 at91sam9261.cfg omap4460.cfg
1480 at91sam9263.cfg omap5912.cfg
1481 at91sam9.cfg omapl138.cfg
1482 at91sam9g10.cfg pic32mx.cfg
1483 at91sam9g20.cfg pxa255.cfg
1484 at91sam9g45.cfg pxa270.cfg
1485 at91sam9rl.cfg pxa3xx.cfg
1486 atmega128.cfg readme.txt
1487 avr32.cfg samsung_s3c2410.cfg
1488 c100.cfg samsung_s3c2440.cfg
1489 c100config.tcl samsung_s3c2450.cfg
1490 c100helper.tcl samsung_s3c4510.cfg
1491 c100regs.tcl samsung_s3c6410.cfg
1492 cs351x.cfg sharp_lh79532.cfg
1493 davinci.cfg smp8634.cfg
1494 dragonite.cfg spear3xx.cfg
1495 dsp56321.cfg stellaris.cfg
1496 dsp568013.cfg stellaris_icdi.cfg
1497 dsp568037.cfg stm32f0x_stlink.cfg
1498 efm32_stlink.cfg stm32f1x.cfg
1499 epc9301.cfg stm32f1x_stlink.cfg
1500 faux.cfg stm32f2x.cfg
1501 feroceon.cfg stm32f2x_stlink.cfg
1502 fm3.cfg stm32f3x.cfg
1503 hilscher_netx10.cfg stm32f3x_stlink.cfg
1504 hilscher_netx500.cfg stm32f4x.cfg
1505 hilscher_netx50.cfg stm32f4x_stlink.cfg
1506 icepick.cfg stm32l.cfg
1507 imx21.cfg stm32lx_dual_bank.cfg
1508 imx25.cfg stm32lx_stlink.cfg
1509 imx27.cfg stm32_stlink.cfg
1510 imx28.cfg stm32w108_stlink.cfg
1511 imx31.cfg stm32xl.cfg
1512 imx35.cfg str710.cfg
1513 imx51.cfg str730.cfg
1514 imx53.cfg str750.cfg
1515 imx6.cfg str912.cfg
1516 imx.cfg swj-dp.tcl
1517 is5114.cfg test_reset_syntax_error.cfg
1518 ixp42x.cfg test_syntax_error.cfg
1519 k40.cfg ti-ar7.cfg
1520 k60.cfg ti_calypso.cfg
1521 lpc1751.cfg ti_dm355.cfg
1522 lpc1752.cfg ti_dm365.cfg
1523 lpc1754.cfg ti_dm6446.cfg
1524 lpc1756.cfg tmpa900.cfg
1525 lpc1758.cfg tmpa910.cfg
1526 lpc1759.cfg u8500.cfg
1527 @end example
1528 @item @emph{more} ... browse for other library files which may be useful.
1529 For example, there are various generic and CPU-specific utilities.
1530 @end itemize
1531
1532 The @file{openocd.cfg} user config
1533 file may override features in any of the above files by
1534 setting variables before sourcing the target file, or by adding
1535 commands specific to their situation.
1536
1537 @section Interface Config Files
1538
1539 The user config file
1540 should be able to source one of these files with a command like this:
1541
1542 @example
1543 source [find interface/FOOBAR.cfg]
1544 @end example
1545
1546 A preconfigured interface file should exist for every debug adapter
1547 in use today with OpenOCD.
1548 That said, perhaps some of these config files
1549 have only been used by the developer who created it.
1550
1551 A separate chapter gives information about how to set these up.
1552 @xref{Debug Adapter Configuration}.
1553 Read the OpenOCD source code (and Developer's Guide)
1554 if you have a new kind of hardware interface
1555 and need to provide a driver for it.
1556
1557 @section Board Config Files
1558 @cindex config file, board
1559 @cindex board config file
1560
1561 The user config file
1562 should be able to source one of these files with a command like this:
1563
1564 @example
1565 source [find board/FOOBAR.cfg]
1566 @end example
1567
1568 The point of a board config file is to package everything
1569 about a given board that user config files need to know.
1570 In summary the board files should contain (if present)
1571
1572 @enumerate
1573 @item One or more @command{source [find target/...cfg]} statements
1574 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1575 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1576 @item Target @code{reset} handlers for SDRAM and I/O configuration
1577 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1578 @item All things that are not ``inside a chip''
1579 @end enumerate
1580
1581 Generic things inside target chips belong in target config files,
1582 not board config files. So for example a @code{reset-init} event
1583 handler should know board-specific oscillator and PLL parameters,
1584 which it passes to target-specific utility code.
1585
1586 The most complex task of a board config file is creating such a
1587 @code{reset-init} event handler.
1588 Define those handlers last, after you verify the rest of the board
1589 configuration works.
1590
1591 @subsection Communication Between Config files
1592
1593 In addition to target-specific utility code, another way that
1594 board and target config files communicate is by following a
1595 convention on how to use certain variables.
1596
1597 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1598 Thus the rule we follow in OpenOCD is this: Variables that begin with
1599 a leading underscore are temporary in nature, and can be modified and
1600 used at will within a target configuration file.
1601
1602 Complex board config files can do the things like this,
1603 for a board with three chips:
1604
1605 @example
1606 # Chip #1: PXA270 for network side, big endian
1607 set CHIPNAME network
1608 set ENDIAN big
1609 source [find target/pxa270.cfg]
1610 # on return: _TARGETNAME = network.cpu
1611 # other commands can refer to the "network.cpu" target.
1612 $_TARGETNAME configure .... events for this CPU..
1613
1614 # Chip #2: PXA270 for video side, little endian
1615 set CHIPNAME video
1616 set ENDIAN little
1617 source [find target/pxa270.cfg]
1618 # on return: _TARGETNAME = video.cpu
1619 # other commands can refer to the "video.cpu" target.
1620 $_TARGETNAME configure .... events for this CPU..
1621
1622 # Chip #3: Xilinx FPGA for glue logic
1623 set CHIPNAME xilinx
1624 unset ENDIAN
1625 source [find target/spartan3.cfg]
1626 @end example
1627
1628 That example is oversimplified because it doesn't show any flash memory,
1629 or the @code{reset-init} event handlers to initialize external DRAM
1630 or (assuming it needs it) load a configuration into the FPGA.
1631 Such features are usually needed for low-level work with many boards,
1632 where ``low level'' implies that the board initialization software may
1633 not be working. (That's a common reason to need JTAG tools. Another
1634 is to enable working with microcontroller-based systems, which often
1635 have no debugging support except a JTAG connector.)
1636
1637 Target config files may also export utility functions to board and user
1638 config files. Such functions should use name prefixes, to help avoid
1639 naming collisions.
1640
1641 Board files could also accept input variables from user config files.
1642 For example, there might be a @code{J4_JUMPER} setting used to identify
1643 what kind of flash memory a development board is using, or how to set
1644 up other clocks and peripherals.
1645
1646 @subsection Variable Naming Convention
1647 @cindex variable names
1648
1649 Most boards have only one instance of a chip.
1650 However, it should be easy to create a board with more than
1651 one such chip (as shown above).
1652 Accordingly, we encourage these conventions for naming
1653 variables associated with different @file{target.cfg} files,
1654 to promote consistency and
1655 so that board files can override target defaults.
1656
1657 Inputs to target config files include:
1658
1659 @itemize @bullet
1660 @item @code{CHIPNAME} ...
1661 This gives a name to the overall chip, and is used as part of
1662 tap identifier dotted names.
1663 While the default is normally provided by the chip manufacturer,
1664 board files may need to distinguish between instances of a chip.
1665 @item @code{ENDIAN} ...
1666 By default @option{little} - although chips may hard-wire @option{big}.
1667 Chips that can't change endianness don't need to use this variable.
1668 @item @code{CPUTAPID} ...
1669 When OpenOCD examines the JTAG chain, it can be told verify the
1670 chips against the JTAG IDCODE register.
1671 The target file will hold one or more defaults, but sometimes the
1672 chip in a board will use a different ID (perhaps a newer revision).
1673 @end itemize
1674
1675 Outputs from target config files include:
1676
1677 @itemize @bullet
1678 @item @code{_TARGETNAME} ...
1679 By convention, this variable is created by the target configuration
1680 script. The board configuration file may make use of this variable to
1681 configure things like a ``reset init'' script, or other things
1682 specific to that board and that target.
1683 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1684 @code{_TARGETNAME1}, ... etc.
1685 @end itemize
1686
1687 @subsection The reset-init Event Handler
1688 @cindex event, reset-init
1689 @cindex reset-init handler
1690
1691 Board config files run in the OpenOCD configuration stage;
1692 they can't use TAPs or targets, since they haven't been
1693 fully set up yet.
1694 This means you can't write memory or access chip registers;
1695 you can't even verify that a flash chip is present.
1696 That's done later in event handlers, of which the target @code{reset-init}
1697 handler is one of the most important.
1698
1699 Except on microcontrollers, the basic job of @code{reset-init} event
1700 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1701 Microcontrollers rarely use boot loaders; they run right out of their
1702 on-chip flash and SRAM memory. But they may want to use one of these
1703 handlers too, if just for developer convenience.
1704
1705 @quotation Note
1706 Because this is so very board-specific, and chip-specific, no examples
1707 are included here.
1708 Instead, look at the board config files distributed with OpenOCD.
1709 If you have a boot loader, its source code will help; so will
1710 configuration files for other JTAG tools
1711 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1712 @end quotation
1713
1714 Some of this code could probably be shared between different boards.
1715 For example, setting up a DRAM controller often doesn't differ by
1716 much except the bus width (16 bits or 32?) and memory timings, so a
1717 reusable TCL procedure loaded by the @file{target.cfg} file might take
1718 those as parameters.
1719 Similarly with oscillator, PLL, and clock setup;
1720 and disabling the watchdog.
1721 Structure the code cleanly, and provide comments to help
1722 the next developer doing such work.
1723 (@emph{You might be that next person} trying to reuse init code!)
1724
1725 The last thing normally done in a @code{reset-init} handler is probing
1726 whatever flash memory was configured. For most chips that needs to be
1727 done while the associated target is halted, either because JTAG memory
1728 access uses the CPU or to prevent conflicting CPU access.
1729
1730 @subsection JTAG Clock Rate
1731
1732 Before your @code{reset-init} handler has set up
1733 the PLLs and clocking, you may need to run with
1734 a low JTAG clock rate.
1735 @xref{jtagspeed,,JTAG Speed}.
1736 Then you'd increase that rate after your handler has
1737 made it possible to use the faster JTAG clock.
1738 When the initial low speed is board-specific, for example
1739 because it depends on a board-specific oscillator speed, then
1740 you should probably set it up in the board config file;
1741 if it's target-specific, it belongs in the target config file.
1742
1743 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1744 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1745 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1746 Consult chip documentation to determine the peak JTAG clock rate,
1747 which might be less than that.
1748
1749 @quotation Warning
1750 On most ARMs, JTAG clock detection is coupled to the core clock, so
1751 software using a @option{wait for interrupt} operation blocks JTAG access.
1752 Adaptive clocking provides a partial workaround, but a more complete
1753 solution just avoids using that instruction with JTAG debuggers.
1754 @end quotation
1755
1756 If both the chip and the board support adaptive clocking,
1757 use the @command{jtag_rclk}
1758 command, in case your board is used with JTAG adapter which
1759 also supports it. Otherwise use @command{adapter_khz}.
1760 Set the slow rate at the beginning of the reset sequence,
1761 and the faster rate as soon as the clocks are at full speed.
1762
1763 @anchor{theinitboardprocedure}
1764 @subsection The init_board procedure
1765 @cindex init_board procedure
1766
1767 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1768 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1769 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1770 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1771 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1772 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1773 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1774 Additionally ``linear'' board config file will most likely fail when target config file uses
1775 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1776 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1777 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1778 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1779
1780 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1781 the original), allowing greater code reuse.
1782
1783 @example
1784 ### board_file.cfg ###
1785
1786 # source target file that does most of the config in init_targets
1787 source [find target/target.cfg]
1788
1789 proc enable_fast_clock @{@} @{
1790 # enables fast on-board clock source
1791 # configures the chip to use it
1792 @}
1793
1794 # initialize only board specifics - reset, clock, adapter frequency
1795 proc init_board @{@} @{
1796 reset_config trst_and_srst trst_pulls_srst
1797
1798 $_TARGETNAME configure -event reset-init @{
1799 adapter_khz 1
1800 enable_fast_clock
1801 adapter_khz 10000
1802 @}
1803 @}
1804 @end example
1805
1806 @section Target Config Files
1807 @cindex config file, target
1808 @cindex target config file
1809
1810 Board config files communicate with target config files using
1811 naming conventions as described above, and may source one or
1812 more target config files like this:
1813
1814 @example
1815 source [find target/FOOBAR.cfg]
1816 @end example
1817
1818 The point of a target config file is to package everything
1819 about a given chip that board config files need to know.
1820 In summary the target files should contain
1821
1822 @enumerate
1823 @item Set defaults
1824 @item Add TAPs to the scan chain
1825 @item Add CPU targets (includes GDB support)
1826 @item CPU/Chip/CPU-Core specific features
1827 @item On-Chip flash
1828 @end enumerate
1829
1830 As a rule of thumb, a target file sets up only one chip.
1831 For a microcontroller, that will often include a single TAP,
1832 which is a CPU needing a GDB target, and its on-chip flash.
1833
1834 More complex chips may include multiple TAPs, and the target
1835 config file may need to define them all before OpenOCD
1836 can talk to the chip.
1837 For example, some phone chips have JTAG scan chains that include
1838 an ARM core for operating system use, a DSP,
1839 another ARM core embedded in an image processing engine,
1840 and other processing engines.
1841
1842 @subsection Default Value Boiler Plate Code
1843
1844 All target configuration files should start with code like this,
1845 letting board config files express environment-specific
1846 differences in how things should be set up.
1847
1848 @example
1849 # Boards may override chip names, perhaps based on role,
1850 # but the default should match what the vendor uses
1851 if @{ [info exists CHIPNAME] @} @{
1852 set _CHIPNAME $CHIPNAME
1853 @} else @{
1854 set _CHIPNAME sam7x256
1855 @}
1856
1857 # ONLY use ENDIAN with targets that can change it.
1858 if @{ [info exists ENDIAN] @} @{
1859 set _ENDIAN $ENDIAN
1860 @} else @{
1861 set _ENDIAN little
1862 @}
1863
1864 # TAP identifiers may change as chips mature, for example with
1865 # new revision fields (the "3" here). Pick a good default; you
1866 # can pass several such identifiers to the "jtag newtap" command.
1867 if @{ [info exists CPUTAPID ] @} @{
1868 set _CPUTAPID $CPUTAPID
1869 @} else @{
1870 set _CPUTAPID 0x3f0f0f0f
1871 @}
1872 @end example
1873 @c but 0x3f0f0f0f is for an str73x part ...
1874
1875 @emph{Remember:} Board config files may include multiple target
1876 config files, or the same target file multiple times
1877 (changing at least @code{CHIPNAME}).
1878
1879 Likewise, the target configuration file should define
1880 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1881 use it later on when defining debug targets:
1882
1883 @example
1884 set _TARGETNAME $_CHIPNAME.cpu
1885 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1886 @end example
1887
1888 @subsection Adding TAPs to the Scan Chain
1889 After the ``defaults'' are set up,
1890 add the TAPs on each chip to the JTAG scan chain.
1891 @xref{TAP Declaration}, and the naming convention
1892 for taps.
1893
1894 In the simplest case the chip has only one TAP,
1895 probably for a CPU or FPGA.
1896 The config file for the Atmel AT91SAM7X256
1897 looks (in part) like this:
1898
1899 @example
1900 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1901 @end example
1902
1903 A board with two such at91sam7 chips would be able
1904 to source such a config file twice, with different
1905 values for @code{CHIPNAME}, so
1906 it adds a different TAP each time.
1907
1908 If there are nonzero @option{-expected-id} values,
1909 OpenOCD attempts to verify the actual tap id against those values.
1910 It will issue error messages if there is mismatch, which
1911 can help to pinpoint problems in OpenOCD configurations.
1912
1913 @example
1914 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1915 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1916 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1917 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1918 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1919 @end example
1920
1921 There are more complex examples too, with chips that have
1922 multiple TAPs. Ones worth looking at include:
1923
1924 @itemize
1925 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1926 plus a JRC to enable them
1927 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1928 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1929 is not currently used)
1930 @end itemize
1931
1932 @subsection Add CPU targets
1933
1934 After adding a TAP for a CPU, you should set it up so that
1935 GDB and other commands can use it.
1936 @xref{CPU Configuration}.
1937 For the at91sam7 example above, the command can look like this;
1938 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1939 to little endian, and this chip doesn't support changing that.
1940
1941 @example
1942 set _TARGETNAME $_CHIPNAME.cpu
1943 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1944 @end example
1945
1946 Work areas are small RAM areas associated with CPU targets.
1947 They are used by OpenOCD to speed up downloads,
1948 and to download small snippets of code to program flash chips.
1949 If the chip includes a form of ``on-chip-ram'' - and many do - define
1950 a work area if you can.
1951 Again using the at91sam7 as an example, this can look like:
1952
1953 @example
1954 $_TARGETNAME configure -work-area-phys 0x00200000 \
1955 -work-area-size 0x4000 -work-area-backup 0
1956 @end example
1957
1958 @anchor{definecputargetsworkinginsmp}
1959 @subsection Define CPU targets working in SMP
1960 @cindex SMP
1961 After setting targets, you can define a list of targets working in SMP.
1962
1963 @example
1964 set _TARGETNAME_1 $_CHIPNAME.cpu1
1965 set _TARGETNAME_2 $_CHIPNAME.cpu2
1966 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1967 -coreid 0 -dbgbase $_DAP_DBG1
1968 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1969 -coreid 1 -dbgbase $_DAP_DBG2
1970 #define 2 targets working in smp.
1971 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1972 @end example
1973 In the above example on cortex_a, 2 cpus are working in SMP.
1974 In SMP only one GDB instance is created and :
1975 @itemize @bullet
1976 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1977 @item halt command triggers the halt of all targets in the list.
1978 @item resume command triggers the write context and the restart of all targets in the list.
1979 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1980 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1981 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1982 @end itemize
1983
1984 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1985 command have been implemented.
1986 @itemize @bullet
1987 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1988 @item cortex_a smp_off : disable SMP mode, the current target is the one
1989 displayed in the GDB session, only this target is now controlled by GDB
1990 session. This behaviour is useful during system boot up.
1991 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1992 following example.
1993 @end itemize
1994
1995 @example
1996 >cortex_a smp_gdb
1997 gdb coreid 0 -> -1
1998 #0 : coreid 0 is displayed to GDB ,
1999 #-> -1 : next resume triggers a real resume
2000 > cortex_a smp_gdb 1
2001 gdb coreid 0 -> 1
2002 #0 :coreid 0 is displayed to GDB ,
2003 #->1 : next resume displays coreid 1 to GDB
2004 > resume
2005 > cortex_a smp_gdb
2006 gdb coreid 1 -> 1
2007 #1 :coreid 1 is displayed to GDB ,
2008 #->1 : next resume displays coreid 1 to GDB
2009 > cortex_a smp_gdb -1
2010 gdb coreid 1 -> -1
2011 #1 :coreid 1 is displayed to GDB,
2012 #->-1 : next resume triggers a real resume
2013 @end example
2014
2015
2016 @subsection Chip Reset Setup
2017
2018 As a rule, you should put the @command{reset_config} command
2019 into the board file. Most things you think you know about a
2020 chip can be tweaked by the board.
2021
2022 Some chips have specific ways the TRST and SRST signals are
2023 managed. In the unusual case that these are @emph{chip specific}
2024 and can never be changed by board wiring, they could go here.
2025 For example, some chips can't support JTAG debugging without
2026 both signals.
2027
2028 Provide a @code{reset-assert} event handler if you can.
2029 Such a handler uses JTAG operations to reset the target,
2030 letting this target config be used in systems which don't
2031 provide the optional SRST signal, or on systems where you
2032 don't want to reset all targets at once.
2033 Such a handler might write to chip registers to force a reset,
2034 use a JRC to do that (preferable -- the target may be wedged!),
2035 or force a watchdog timer to trigger.
2036 (For Cortex-M targets, this is not necessary. The target
2037 driver knows how to use trigger an NVIC reset when SRST is
2038 not available.)
2039
2040 Some chips need special attention during reset handling if
2041 they're going to be used with JTAG.
2042 An example might be needing to send some commands right
2043 after the target's TAP has been reset, providing a
2044 @code{reset-deassert-post} event handler that writes a chip
2045 register to report that JTAG debugging is being done.
2046 Another would be reconfiguring the watchdog so that it stops
2047 counting while the core is halted in the debugger.
2048
2049 JTAG clocking constraints often change during reset, and in
2050 some cases target config files (rather than board config files)
2051 are the right places to handle some of those issues.
2052 For example, immediately after reset most chips run using a
2053 slower clock than they will use later.
2054 That means that after reset (and potentially, as OpenOCD
2055 first starts up) they must use a slower JTAG clock rate
2056 than they will use later.
2057 @xref{jtagspeed,,JTAG Speed}.
2058
2059 @quotation Important
2060 When you are debugging code that runs right after chip
2061 reset, getting these issues right is critical.
2062 In particular, if you see intermittent failures when
2063 OpenOCD verifies the scan chain after reset,
2064 look at how you are setting up JTAG clocking.
2065 @end quotation
2066
2067 @anchor{theinittargetsprocedure}
2068 @subsection The init_targets procedure
2069 @cindex init_targets procedure
2070
2071 Target config files can either be ``linear'' (script executed line-by-line when parsed in
2072 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
2073 procedure called @code{init_targets}, which will be executed when entering run stage
2074 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
2075 Such procedure can be overriden by ``next level'' script (which sources the original).
2076 This concept faciliates code reuse when basic target config files provide generic configuration
2077 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
2078 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
2079 because sourcing them executes every initialization commands they provide.
2080
2081 @example
2082 ### generic_file.cfg ###
2083
2084 proc setup_my_chip @{chip_name flash_size ram_size@} @{
2085 # basic initialization procedure ...
2086 @}
2087
2088 proc init_targets @{@} @{
2089 # initializes generic chip with 4kB of flash and 1kB of RAM
2090 setup_my_chip MY_GENERIC_CHIP 4096 1024
2091 @}
2092
2093 ### specific_file.cfg ###
2094
2095 source [find target/generic_file.cfg]
2096
2097 proc init_targets @{@} @{
2098 # initializes specific chip with 128kB of flash and 64kB of RAM
2099 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
2100 @}
2101 @end example
2102
2103 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
2104 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
2105
2106 For an example of this scheme see LPC2000 target config files.
2107
2108 The @code{init_boards} procedure is a similar concept concerning board config files
2109 (@xref{theinitboardprocedure,,The init_board procedure}.)
2110
2111 @anchor{theinittargeteventsprocedure}
2112 @subsection The init_target_events procedure
2113 @cindex init_target_events procedure
2114
2115 A special procedure called @code{init_target_events} is run just after
2116 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
2117 procedure}.) and before @code{init_board}
2118 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
2119 to set up default target events for the targets that do not have those
2120 events already assigned.
2121
2122 @subsection ARM Core Specific Hacks
2123
2124 If the chip has a DCC, enable it. If the chip is an ARM9 with some
2125 special high speed download features - enable it.
2126
2127 If present, the MMU, the MPU and the CACHE should be disabled.
2128
2129 Some ARM cores are equipped with trace support, which permits
2130 examination of the instruction and data bus activity. Trace
2131 activity is controlled through an ``Embedded Trace Module'' (ETM)
2132 on one of the core's scan chains. The ETM emits voluminous data
2133 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
2134 If you are using an external trace port,
2135 configure it in your board config file.
2136 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2137 configure it in your target config file.
2138
2139 @example
2140 etm config $_TARGETNAME 16 normal full etb
2141 etb config $_TARGETNAME $_CHIPNAME.etb
2142 @end example
2143
2144 @subsection Internal Flash Configuration
2145
2146 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2147
2148 @b{Never ever} in the ``target configuration file'' define any type of
2149 flash that is external to the chip. (For example a BOOT flash on
2150 Chip Select 0.) Such flash information goes in a board file - not
2151 the TARGET (chip) file.
2152
2153 Examples:
2154 @itemize @bullet
2155 @item at91sam7x256 - has 256K flash YES enable it.
2156 @item str912 - has flash internal YES enable it.
2157 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2158 @item pxa270 - again - CS0 flash - it goes in the board file.
2159 @end itemize
2160
2161 @anchor{translatingconfigurationfiles}
2162 @section Translating Configuration Files
2163 @cindex translation
2164 If you have a configuration file for another hardware debugger
2165 or toolset (Abatron, BDI2000, BDI3000, CCS,
2166 Lauterbach, Segger, Macraigor, etc.), translating
2167 it into OpenOCD syntax is often quite straightforward. The most tricky
2168 part of creating a configuration script is oftentimes the reset init
2169 sequence where e.g. PLLs, DRAM and the like is set up.
2170
2171 One trick that you can use when translating is to write small
2172 Tcl procedures to translate the syntax into OpenOCD syntax. This
2173 can avoid manual translation errors and make it easier to
2174 convert other scripts later on.
2175
2176 Example of transforming quirky arguments to a simple search and
2177 replace job:
2178
2179 @example
2180 # Lauterbach syntax(?)
2181 #
2182 # Data.Set c15:0x042f %long 0x40000015
2183 #
2184 # OpenOCD syntax when using procedure below.
2185 #
2186 # setc15 0x01 0x00050078
2187
2188 proc setc15 @{regs value@} @{
2189 global TARGETNAME
2190
2191 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2192
2193 arm mcr 15 [expr ($regs>>12)&0x7] \
2194 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2195 [expr ($regs>>8)&0x7] $value
2196 @}
2197 @end example
2198
2199
2200
2201 @node Daemon Configuration
2202 @chapter Daemon Configuration
2203 @cindex initialization
2204 The commands here are commonly found in the openocd.cfg file and are
2205 used to specify what TCP/IP ports are used, and how GDB should be
2206 supported.
2207
2208 @anchor{configurationstage}
2209 @section Configuration Stage
2210 @cindex configuration stage
2211 @cindex config command
2212
2213 When the OpenOCD server process starts up, it enters a
2214 @emph{configuration stage} which is the only time that
2215 certain commands, @emph{configuration commands}, may be issued.
2216 Normally, configuration commands are only available
2217 inside startup scripts.
2218
2219 In this manual, the definition of a configuration command is
2220 presented as a @emph{Config Command}, not as a @emph{Command}
2221 which may be issued interactively.
2222 The runtime @command{help} command also highlights configuration
2223 commands, and those which may be issued at any time.
2224
2225 Those configuration commands include declaration of TAPs,
2226 flash banks,
2227 the interface used for JTAG communication,
2228 and other basic setup.
2229 The server must leave the configuration stage before it
2230 may access or activate TAPs.
2231 After it leaves this stage, configuration commands may no
2232 longer be issued.
2233
2234 @anchor{enteringtherunstage}
2235 @section Entering the Run Stage
2236
2237 The first thing OpenOCD does after leaving the configuration
2238 stage is to verify that it can talk to the scan chain
2239 (list of TAPs) which has been configured.
2240 It will warn if it doesn't find TAPs it expects to find,
2241 or finds TAPs that aren't supposed to be there.
2242 You should see no errors at this point.
2243 If you see errors, resolve them by correcting the
2244 commands you used to configure the server.
2245 Common errors include using an initial JTAG speed that's too
2246 fast, and not providing the right IDCODE values for the TAPs
2247 on the scan chain.
2248
2249 Once OpenOCD has entered the run stage, a number of commands
2250 become available.
2251 A number of these relate to the debug targets you may have declared.
2252 For example, the @command{mww} command will not be available until
2253 a target has been successfuly instantiated.
2254 If you want to use those commands, you may need to force
2255 entry to the run stage.
2256
2257 @deffn {Config Command} init
2258 This command terminates the configuration stage and
2259 enters the run stage. This helps when you need to have
2260 the startup scripts manage tasks such as resetting the target,
2261 programming flash, etc. To reset the CPU upon startup, add "init" and
2262 "reset" at the end of the config script or at the end of the OpenOCD
2263 command line using the @option{-c} command line switch.
2264
2265 If this command does not appear in any startup/configuration file
2266 OpenOCD executes the command for you after processing all
2267 configuration files and/or command line options.
2268
2269 @b{NOTE:} This command normally occurs at or near the end of your
2270 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2271 targets ready. For example: If your openocd.cfg file needs to
2272 read/write memory on your target, @command{init} must occur before
2273 the memory read/write commands. This includes @command{nand probe}.
2274 @end deffn
2275
2276 @deffn {Overridable Procedure} jtag_init
2277 This is invoked at server startup to verify that it can talk
2278 to the scan chain (list of TAPs) which has been configured.
2279
2280 The default implementation first tries @command{jtag arp_init},
2281 which uses only a lightweight JTAG reset before examining the
2282 scan chain.
2283 If that fails, it tries again, using a harder reset
2284 from the overridable procedure @command{init_reset}.
2285
2286 Implementations must have verified the JTAG scan chain before
2287 they return.
2288 This is done by calling @command{jtag arp_init}
2289 (or @command{jtag arp_init-reset}).
2290 @end deffn
2291
2292 @anchor{tcpipports}
2293 @section TCP/IP Ports
2294 @cindex TCP port
2295 @cindex server
2296 @cindex port
2297 @cindex security
2298 The OpenOCD server accepts remote commands in several syntaxes.
2299 Each syntax uses a different TCP/IP port, which you may specify
2300 only during configuration (before those ports are opened).
2301
2302 For reasons including security, you may wish to prevent remote
2303 access using one or more of these ports.
2304 In such cases, just specify the relevant port number as zero.
2305 If you disable all access through TCP/IP, you will need to
2306 use the command line @option{-pipe} option.
2307
2308 @deffn {Command} gdb_port [number]
2309 @cindex GDB server
2310 Normally gdb listens to a TCP/IP port, but GDB can also
2311 communicate via pipes(stdin/out or named pipes). The name
2312 "gdb_port" stuck because it covers probably more than 90% of
2313 the normal use cases.
2314
2315 No arguments reports GDB port. "pipe" means listen to stdin
2316 output to stdout, an integer is base port number, "disable"
2317 disables the gdb server.
2318
2319 When using "pipe", also use log_output to redirect the log
2320 output to a file so as not to flood the stdin/out pipes.
2321
2322 The -p/--pipe option is deprecated and a warning is printed
2323 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2324
2325 Any other string is interpreted as named pipe to listen to.
2326 Output pipe is the same name as input pipe, but with 'o' appended,
2327 e.g. /var/gdb, /var/gdbo.
2328
2329 The GDB port for the first target will be the base port, the
2330 second target will listen on gdb_port + 1, and so on.
2331 When not specified during the configuration stage,
2332 the port @var{number} defaults to 3333.
2333 @end deffn
2334
2335 @deffn {Command} tcl_port [number]
2336 Specify or query the port used for a simplified RPC
2337 connection that can be used by clients to issue TCL commands and get the
2338 output from the Tcl engine.
2339 Intended as a machine interface.
2340 When not specified during the configuration stage,
2341 the port @var{number} defaults to 6666.
2342
2343 @end deffn
2344
2345 @deffn {Command} telnet_port [number]
2346 Specify or query the
2347 port on which to listen for incoming telnet connections.
2348 This port is intended for interaction with one human through TCL commands.
2349 When not specified during the configuration stage,
2350 the port @var{number} defaults to 4444.
2351 When specified as zero, this port is not activated.
2352 @end deffn
2353
2354 @anchor{gdbconfiguration}
2355 @section GDB Configuration
2356 @cindex GDB
2357 @cindex GDB configuration
2358 You can reconfigure some GDB behaviors if needed.
2359 The ones listed here are static and global.
2360 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2361 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2362
2363 @anchor{gdbbreakpointoverride}
2364 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2365 Force breakpoint type for gdb @command{break} commands.
2366 This option supports GDB GUIs which don't
2367 distinguish hard versus soft breakpoints, if the default OpenOCD and
2368 GDB behaviour is not sufficient. GDB normally uses hardware
2369 breakpoints if the memory map has been set up for flash regions.
2370 @end deffn
2371
2372 @anchor{gdbflashprogram}
2373 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2374 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2375 vFlash packet is received.
2376 The default behaviour is @option{enable}.
2377 @end deffn
2378
2379 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2380 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2381 requested. GDB will then know when to set hardware breakpoints, and program flash
2382 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2383 for flash programming to work.
2384 Default behaviour is @option{enable}.
2385 @xref{gdbflashprogram,,gdb_flash_program}.
2386 @end deffn
2387
2388 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2389 Specifies whether data aborts cause an error to be reported
2390 by GDB memory read packets.
2391 The default behaviour is @option{disable};
2392 use @option{enable} see these errors reported.
2393 @end deffn
2394
2395 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2396 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2397 The default behaviour is @option{disable}.
2398 @end deffn
2399
2400 @deffn {Command} gdb_save_tdesc
2401 Saves the target descripton file to the local file system.
2402
2403 The file name is @i{target_name}.xml.
2404 @end deffn
2405
2406 @anchor{eventpolling}
2407 @section Event Polling
2408
2409 Hardware debuggers are parts of asynchronous systems,
2410 where significant events can happen at any time.
2411 The OpenOCD server needs to detect some of these events,
2412 so it can report them to through TCL command line
2413 or to GDB.
2414
2415 Examples of such events include:
2416
2417 @itemize
2418 @item One of the targets can stop running ... maybe it triggers
2419 a code breakpoint or data watchpoint, or halts itself.
2420 @item Messages may be sent over ``debug message'' channels ... many
2421 targets support such messages sent over JTAG,
2422 for receipt by the person debugging or tools.
2423 @item Loss of power ... some adapters can detect these events.
2424 @item Resets not issued through JTAG ... such reset sources
2425 can include button presses or other system hardware, sometimes
2426 including the target itself (perhaps through a watchdog).
2427 @item Debug instrumentation sometimes supports event triggering
2428 such as ``trace buffer full'' (so it can quickly be emptied)
2429 or other signals (to correlate with code behavior).
2430 @end itemize
2431
2432 None of those events are signaled through standard JTAG signals.
2433 However, most conventions for JTAG connectors include voltage
2434 level and system reset (SRST) signal detection.
2435 Some connectors also include instrumentation signals, which
2436 can imply events when those signals are inputs.
2437
2438 In general, OpenOCD needs to periodically check for those events,
2439 either by looking at the status of signals on the JTAG connector
2440 or by sending synchronous ``tell me your status'' JTAG requests
2441 to the various active targets.
2442 There is a command to manage and monitor that polling,
2443 which is normally done in the background.
2444
2445 @deffn Command poll [@option{on}|@option{off}]
2446 Poll the current target for its current state.
2447 (Also, @pxref{targetcurstate,,target curstate}.)
2448 If that target is in debug mode, architecture
2449 specific information about the current state is printed.
2450 An optional parameter
2451 allows background polling to be enabled and disabled.
2452
2453 You could use this from the TCL command shell, or
2454 from GDB using @command{monitor poll} command.
2455 Leave background polling enabled while you're using GDB.
2456 @example
2457 > poll
2458 background polling: on
2459 target state: halted
2460 target halted in ARM state due to debug-request, \
2461 current mode: Supervisor
2462 cpsr: 0x800000d3 pc: 0x11081bfc
2463 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2464 >
2465 @end example
2466 @end deffn
2467
2468 @node Debug Adapter Configuration
2469 @chapter Debug Adapter Configuration
2470 @cindex config file, interface
2471 @cindex interface config file
2472
2473 Correctly installing OpenOCD includes making your operating system give
2474 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2475 are used to select which one is used, and to configure how it is used.
2476
2477 @quotation Note
2478 Because OpenOCD started out with a focus purely on JTAG, you may find
2479 places where it wrongly presumes JTAG is the only transport protocol
2480 in use. Be aware that recent versions of OpenOCD are removing that
2481 limitation. JTAG remains more functional than most other transports.
2482 Other transports do not support boundary scan operations, or may be
2483 specific to a given chip vendor. Some might be usable only for
2484 programming flash memory, instead of also for debugging.
2485 @end quotation
2486
2487 Debug Adapters/Interfaces/Dongles are normally configured
2488 through commands in an interface configuration
2489 file which is sourced by your @file{openocd.cfg} file, or
2490 through a command line @option{-f interface/....cfg} option.
2491
2492 @example
2493 source [find interface/olimex-jtag-tiny.cfg]
2494 @end example
2495
2496 These commands tell
2497 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2498 A few cases are so simple that you only need to say what driver to use:
2499
2500 @example
2501 # jlink interface
2502 interface jlink
2503 @end example
2504
2505 Most adapters need a bit more configuration than that.
2506
2507
2508 @section Interface Configuration
2509
2510 The interface command tells OpenOCD what type of debug adapter you are
2511 using. Depending on the type of adapter, you may need to use one or
2512 more additional commands to further identify or configure the adapter.
2513
2514 @deffn {Config Command} {interface} name
2515 Use the interface driver @var{name} to connect to the
2516 target.
2517 @end deffn
2518
2519 @deffn Command {interface_list}
2520 List the debug adapter drivers that have been built into
2521 the running copy of OpenOCD.
2522 @end deffn
2523 @deffn Command {interface transports} transport_name+
2524 Specifies the transports supported by this debug adapter.
2525 The adapter driver builds-in similar knowledge; use this only
2526 when external configuration (such as jumpering) changes what
2527 the hardware can support.
2528 @end deffn
2529
2530
2531
2532 @deffn Command {adapter_name}
2533 Returns the name of the debug adapter driver being used.
2534 @end deffn
2535
2536 @section Interface Drivers
2537
2538 Each of the interface drivers listed here must be explicitly
2539 enabled when OpenOCD is configured, in order to be made
2540 available at run time.
2541
2542 @deffn {Interface Driver} {amt_jtagaccel}
2543 Amontec Chameleon in its JTAG Accelerator configuration,
2544 connected to a PC's EPP mode parallel port.
2545 This defines some driver-specific commands:
2546
2547 @deffn {Config Command} {parport_port} number
2548 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2549 the number of the @file{/dev/parport} device.
2550 @end deffn
2551
2552 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2553 Displays status of RTCK option.
2554 Optionally sets that option first.
2555 @end deffn
2556 @end deffn
2557
2558 @deffn {Interface Driver} {arm-jtag-ew}
2559 Olimex ARM-JTAG-EW USB adapter
2560 This has one driver-specific command:
2561
2562 @deffn Command {armjtagew_info}
2563 Logs some status
2564 @end deffn
2565 @end deffn
2566
2567 @deffn {Interface Driver} {at91rm9200}
2568 Supports bitbanged JTAG from the local system,
2569 presuming that system is an Atmel AT91rm9200
2570 and a specific set of GPIOs is used.
2571 @c command: at91rm9200_device NAME
2572 @c chooses among list of bit configs ... only one option
2573 @end deffn
2574
2575 @deffn {Interface Driver} {cmsis-dap}
2576 ARM CMSIS-DAP compliant based adapter.
2577
2578 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2579 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2580 the driver will attempt to auto detect the CMSIS-DAP device.
2581 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2582 @example
2583 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2584 @end example
2585 @end deffn
2586
2587 @deffn {Config Command} {cmsis_dap_serial} [serial]
2588 Specifies the @var{serial} of the CMSIS-DAP device to use.
2589 If not specified, serial numbers are not considered.
2590 @end deffn
2591
2592 @deffn {Command} {cmsis-dap info}
2593 Display various device information, like hardware version, firmware version, current bus status.
2594 @end deffn
2595 @end deffn
2596
2597 @deffn {Interface Driver} {dummy}
2598 A dummy software-only driver for debugging.
2599 @end deffn
2600
2601 @deffn {Interface Driver} {ep93xx}
2602 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2603 @end deffn
2604
2605 @deffn {Interface Driver} {ft2232}
2606 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2607
2608 Note that this driver has several flaws and the @command{ftdi} driver is
2609 recommended as its replacement.
2610
2611 These interfaces have several commands, used to configure the driver
2612 before initializing the JTAG scan chain:
2613
2614 @deffn {Config Command} {ft2232_device_desc} description
2615 Provides the USB device description (the @emph{iProduct string})
2616 of the FTDI FT2232 device. If not
2617 specified, the FTDI default value is used. This setting is only valid
2618 if compiled with FTD2XX support.
2619 @end deffn
2620
2621 @deffn {Config Command} {ft2232_serial} serial-number
2622 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2623 in case the vendor provides unique IDs and more than one FT2232 device
2624 is connected to the host.
2625 If not specified, serial numbers are not considered.
2626 (Note that USB serial numbers can be arbitrary Unicode strings,
2627 and are not restricted to containing only decimal digits.)
2628 @end deffn
2629
2630 @deffn {Config Command} {ft2232_layout} name
2631 Each vendor's FT2232 device can use different GPIO signals
2632 to control output-enables, reset signals, and LEDs.
2633 Currently valid layout @var{name} values include:
2634 @itemize @minus
2635 @item @b{axm0432_jtag} Axiom AXM-0432
2636 @item @b{comstick} Hitex STR9 comstick
2637 @item @b{cortino} Hitex Cortino JTAG interface
2638 @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
2639 either for the local Cortex-M3 (SRST only)
2640 or in a passthrough mode (neither SRST nor TRST)
2641 This layout can not support the SWO trace mechanism, and should be
2642 used only for older boards (before rev C).
2643 @item @b{luminary_icdi} This layout should be used with most TI/Luminary
2644 eval boards, including Rev C LM3S811 eval boards and the eponymous
2645 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2646 to debug some other target. It can support the SWO trace mechanism.
2647 @item @b{flyswatter} Tin Can Tools Flyswatter
2648 @item @b{icebear} ICEbear JTAG adapter from Section 5
2649 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2650 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2651 @item @b{m5960} American Microsystems M5960
2652 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2653 @item @b{oocdlink} OOCDLink
2654 @c oocdlink ~= jtagkey_prototype_v1
2655 @item @b{redbee-econotag} Integrated with a Redbee development board.
2656 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2657 @item @b{sheevaplug} Marvell Sheevaplug development kit
2658 @item @b{signalyzer} Xverve Signalyzer
2659 @item @b{stm32stick} Hitex STM32 Performance Stick
2660 @item @b{turtelizer2} egnite Software turtelizer2
2661 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2662 @end itemize
2663 @end deffn
2664
2665 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2666 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2667 default values are used.
2668 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2669 @example
2670 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2671 @end example
2672 @end deffn
2673
2674 @deffn {Config Command} {ft2232_latency} ms
2675 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2676 ft2232_read() fails to return the expected number of bytes. This can be caused by
2677 USB communication delays and has proved hard to reproduce and debug. Setting the
2678 FT2232 latency timer to a larger value increases delays for short USB packets but it
2679 also reduces the risk of timeouts before receiving the expected number of bytes.
2680 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2681 @end deffn
2682
2683 @deffn {Config Command} {ft2232_channel} channel
2684 Used to select the channel of the ft2232 chip to use (between 1 and 4).
2685 The default value is 1.
2686 @end deffn
2687
2688 For example, the interface config file for a
2689 Turtelizer JTAG Adapter looks something like this:
2690
2691 @example
2692 interface ft2232
2693 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2694 ft2232_layout turtelizer2
2695 ft2232_vid_pid 0x0403 0xbdc8
2696 @end example
2697 @end deffn
2698
2699 @deffn {Interface Driver} {ftdi}
2700 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2701 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2702 It is a complete rewrite to address a large number of problems with the ft2232
2703 interface driver.
2704
2705 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2706 bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
2707 consistently faster than the ft2232 driver, sometimes several times faster.
2708
2709 A major improvement of this driver is that support for new FTDI based adapters
2710 can be added competely through configuration files, without the need to patch
2711 and rebuild OpenOCD.
2712
2713 The driver uses a signal abstraction to enable Tcl configuration files to
2714 define outputs for one or several FTDI GPIO. These outputs can then be
2715 controlled using the @command{ftdi_set_signal} command. Special signal names
2716 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2717 will be used for their customary purpose.
2718
2719 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2720 be controlled differently. In order to support tristateable signals such as
2721 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2722 signal. The following output buffer configurations are supported:
2723
2724 @itemize @minus
2725 @item Push-pull with one FTDI output as (non-)inverted data line
2726 @item Open drain with one FTDI output as (non-)inverted output-enable
2727 @item Tristate with one FTDI output as (non-)inverted data line and another
2728 FTDI output as (non-)inverted output-enable
2729 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2730 switching data and direction as necessary
2731 @end itemize
2732
2733 These interfaces have several commands, used to configure the driver
2734 before initializing the JTAG scan chain:
2735
2736 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2737 The vendor ID and product ID of the adapter. If not specified, the FTDI
2738 default values are used.
2739 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2740 @example
2741 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2742 @end example
2743 @end deffn
2744
2745 @deffn {Config Command} {ftdi_device_desc} description
2746 Provides the USB device description (the @emph{iProduct string})
2747 of the adapter. If not specified, the device description is ignored
2748 during device selection.
2749 @end deffn
2750
2751 @deffn {Config Command} {ftdi_serial} serial-number
2752 Specifies the @var{serial-number} of the adapter to use,
2753 in case the vendor provides unique IDs and more than one adapter
2754 is connected to the host.
2755 If not specified, serial numbers are not considered.
2756 (Note that USB serial numbers can be arbitrary Unicode strings,
2757 and are not restricted to containing only decimal digits.)
2758 @end deffn
2759
2760 @deffn {Config Command} {ftdi_channel} channel
2761 Selects the channel of the FTDI device to use for MPSSE operations. Most
2762 adapters use the default, channel 0, but there are exceptions.
2763 @end deffn
2764
2765 @deffn {Config Command} {ftdi_layout_init} data direction
2766 Specifies the initial values of the FTDI GPIO data and direction registers.
2767 Each value is a 16-bit number corresponding to the concatenation of the high
2768 and low FTDI GPIO registers. The values should be selected based on the
2769 schematics of the adapter, such that all signals are set to safe levels with
2770 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2771 and initially asserted reset signals.
2772 @end deffn
2773
2774 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2775 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2776 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2777 register bitmasks to tell the driver the connection and type of the output
2778 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2779 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2780 used with inverting data inputs and @option{-data} with non-inverting inputs.
2781 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2782 not-output-enable) input to the output buffer is connected.
2783
2784 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2785 simple open-collector transistor driver would be specified with @option{-oe}
2786 only. In that case the signal can only be set to drive low or to Hi-Z and the
2787 driver will complain if the signal is set to drive high. Which means that if
2788 it's a reset signal, @command{reset_config} must be specified as
2789 @option{srst_open_drain}, not @option{srst_push_pull}.
2790
2791 A special case is provided when @option{-data} and @option{-oe} is set to the
2792 same bitmask. Then the FTDI pin is considered being connected straight to the
2793 target without any buffer. The FTDI pin is then switched between output and
2794 input as necessary to provide the full set of low, high and Hi-Z
2795 characteristics. In all other cases, the pins specified in a signal definition
2796 are always driven by the FTDI.
2797
2798 If @option{-alias} or @option{-nalias} is used, the signal is created
2799 identical (or with data inverted) to an already specified signal
2800 @var{name}.
2801 @end deffn
2802
2803 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2804 Set a previously defined signal to the specified level.
2805 @itemize @minus
2806 @item @option{0}, drive low
2807 @item @option{1}, drive high
2808 @item @option{z}, set to high-impedance
2809 @end itemize
2810 @end deffn
2811
2812 For example adapter definitions, see the configuration files shipped in the
2813 @file{interface/ftdi} directory.
2814 @end deffn
2815
2816 @deffn {Interface Driver} {remote_bitbang}
2817 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2818 with a remote process and sends ASCII encoded bitbang requests to that process
2819 instead of directly driving JTAG.
2820
2821 The remote_bitbang driver is useful for debugging software running on
2822 processors which are being simulated.
2823
2824 @deffn {Config Command} {remote_bitbang_port} number
2825 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2826 sockets instead of TCP.
2827 @end deffn
2828
2829 @deffn {Config Command} {remote_bitbang_host} hostname
2830 Specifies the hostname of the remote process to connect to using TCP, or the
2831 name of the UNIX socket to use if remote_bitbang_port is 0.
2832 @end deffn
2833
2834 For example, to connect remotely via TCP to the host foobar you might have
2835 something like:
2836
2837 @example
2838 interface remote_bitbang
2839 remote_bitbang_port 3335
2840 remote_bitbang_host foobar
2841 @end example
2842
2843 To connect to another process running locally via UNIX sockets with socket
2844 named mysocket:
2845
2846 @example
2847 interface remote_bitbang
2848 remote_bitbang_port 0
2849 remote_bitbang_host mysocket
2850 @end example
2851 @end deffn
2852
2853 @deffn {Interface Driver} {usb_blaster}
2854 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2855 for FTDI chips. These interfaces have several commands, used to
2856 configure the driver before initializing the JTAG scan chain:
2857
2858 @deffn {Config Command} {usb_blaster_device_desc} description
2859 Provides the USB device description (the @emph{iProduct string})
2860 of the FTDI FT245 device. If not
2861 specified, the FTDI default value is used. This setting is only valid
2862 if compiled with FTD2XX support.
2863 @end deffn
2864
2865 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2866 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2867 default values are used.
2868 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2869 Altera USB-Blaster (default):
2870 @example
2871 usb_blaster_vid_pid 0x09FB 0x6001
2872 @end example
2873 The following VID/PID is for Kolja Waschk's USB JTAG:
2874 @example
2875 usb_blaster_vid_pid 0x16C0 0x06AD
2876 @end example
2877 @end deffn
2878
2879 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2880 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2881 female JTAG header). These pins can be used as SRST and/or TRST provided the
2882 appropriate connections are made on the target board.
2883
2884 For example, to use pin 6 as SRST (as with an AVR board):
2885 @example
2886 $_TARGETNAME configure -event reset-assert \
2887 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2888 @end example
2889 @end deffn
2890
2891 @end deffn
2892
2893 @deffn {Interface Driver} {gw16012}
2894 Gateworks GW16012 JTAG programmer.
2895 This has one driver-specific command:
2896
2897 @deffn {Config Command} {parport_port} [port_number]
2898 Display either the address of the I/O port
2899 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2900 If a parameter is provided, first switch to use that port.
2901 This is a write-once setting.
2902 @end deffn
2903 @end deffn
2904
2905 @deffn {Interface Driver} {jlink}
2906 Segger J-Link family of USB adapters. It currently supports JTAG and SWD transports.
2907
2908 @quotation Compatibility Note
2909 Segger released many firmware versions for the many harware versions they
2910 produced. OpenOCD was extensively tested and intended to run on all of them,
2911 but some combinations were reported as incompatible. As a general
2912 recommendation, it is advisable to use the latest firmware version
2913 available for each hardware version. However the current V8 is a moving
2914 target, and Segger firmware versions released after the OpenOCD was
2915 released may not be compatible. In such cases it is recommended to
2916 revert to the last known functional version. For 0.5.0, this is from
2917 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2918 version is from "May 3 2012 18:36:22", packed with 4.46f.
2919 @end quotation
2920
2921 @deffn {Command} {jlink caps}
2922 Display the device firmware capabilities.
2923 @end deffn
2924 @deffn {Command} {jlink info}
2925 Display various device information, like hardware version, firmware version, current bus status.
2926 @end deffn
2927 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2928 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2929 @end deffn
2930 @deffn {Command} {jlink config}
2931 Display the J-Link configuration.
2932 @end deffn
2933 @deffn {Command} {jlink config kickstart} [val]
2934 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2935 @end deffn
2936 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2937 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2938 @end deffn
2939 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2940 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2941 E the bit of the subnet mask and
2942 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2943 @end deffn
2944 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2945 Set the USB address; this will also change the product id. Without argument, show the USB address.
2946 @end deffn
2947 @deffn {Command} {jlink config reset}
2948 Reset the current configuration.
2949 @end deffn
2950 @deffn {Command} {jlink config save}
2951 Save the current configuration to the internal persistent storage.
2952 @end deffn
2953 @deffn {Config} {jlink pid} val
2954 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2955 @end deffn
2956 @end deffn
2957
2958 @deffn {Interface Driver} {parport}
2959 Supports PC parallel port bit-banging cables:
2960 Wigglers, PLD download cable, and more.
2961 These interfaces have several commands, used to configure the driver
2962 before initializing the JTAG scan chain:
2963
2964 @deffn {Config Command} {parport_cable} name
2965 Set the layout of the parallel port cable used to connect to the target.
2966 This is a write-once setting.
2967 Currently valid cable @var{name} values include:
2968
2969 @itemize @minus
2970 @item @b{altium} Altium Universal JTAG cable.
2971 @item @b{arm-jtag} Same as original wiggler except SRST and
2972 TRST connections reversed and TRST is also inverted.
2973 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2974 in configuration mode. This is only used to
2975 program the Chameleon itself, not a connected target.
2976 @item @b{dlc5} The Xilinx Parallel cable III.
2977 @item @b{flashlink} The ST Parallel cable.
2978 @item @b{lattice} Lattice ispDOWNLOAD Cable
2979 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2980 some versions of
2981 Amontec's Chameleon Programmer. The new version available from
2982 the website uses the original Wiggler layout ('@var{wiggler}')
2983 @item @b{triton} The parallel port adapter found on the
2984 ``Karo Triton 1 Development Board''.
2985 This is also the layout used by the HollyGates design
2986 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2987 @item @b{wiggler} The original Wiggler layout, also supported by
2988 several clones, such as the Olimex ARM-JTAG
2989 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2990 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2991 @end itemize
2992 @end deffn
2993
2994 @deffn {Config Command} {parport_port} [port_number]
2995 Display either the address of the I/O port
2996 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2997 If a parameter is provided, first switch to use that port.
2998 This is a write-once setting.
2999
3000 When using PPDEV to access the parallel port, use the number of the parallel port:
3001 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
3002 you may encounter a problem.
3003 @end deffn
3004
3005 @deffn Command {parport_toggling_time} [nanoseconds]
3006 Displays how many nanoseconds the hardware needs to toggle TCK;
3007 the parport driver uses this value to obey the
3008 @command{adapter_khz} configuration.
3009 When the optional @var{nanoseconds} parameter is given,
3010 that setting is changed before displaying the current value.
3011
3012 The default setting should work reasonably well on commodity PC hardware.
3013 However, you may want to calibrate for your specific hardware.
3014 @quotation Tip
3015 To measure the toggling time with a logic analyzer or a digital storage
3016 oscilloscope, follow the procedure below:
3017 @example
3018 > parport_toggling_time 1000
3019 > adapter_khz 500
3020 @end example
3021 This sets the maximum JTAG clock speed of the hardware, but
3022 the actual speed probably deviates from the requested 500 kHz.
3023 Now, measure the time between the two closest spaced TCK transitions.
3024 You can use @command{runtest 1000} or something similar to generate a
3025 large set of samples.
3026 Update the setting to match your measurement:
3027 @example
3028 > parport_toggling_time <measured nanoseconds>
3029 @end example
3030 Now the clock speed will be a better match for @command{adapter_khz rate}
3031 commands given in OpenOCD scripts and event handlers.
3032
3033 You can do something similar with many digital multimeters, but note
3034 that you'll probably need to run the clock continuously for several
3035 seconds before it decides what clock rate to show. Adjust the
3036 toggling time up or down until the measured clock rate is a good
3037 match for the adapter_khz rate you specified; be conservative.
3038 @end quotation
3039 @end deffn
3040
3041 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
3042 This will configure the parallel driver to write a known
3043 cable-specific value to the parallel interface on exiting OpenOCD.
3044 @end deffn
3045
3046 For example, the interface configuration file for a
3047 classic ``Wiggler'' cable on LPT2 might look something like this:
3048
3049 @example
3050 interface parport
3051 parport_port 0x278
3052 parport_cable wiggler
3053 @end example
3054 @end deffn
3055
3056 @deffn {Interface Driver} {presto}
3057 ASIX PRESTO USB JTAG programmer.
3058 @deffn {Config Command} {presto_serial} serial_string
3059 Configures the USB serial number of the Presto device to use.
3060 @end deffn
3061 @end deffn
3062
3063 @deffn {Interface Driver} {rlink}
3064 Raisonance RLink USB adapter
3065 @end deffn
3066
3067 @deffn {Interface Driver} {usbprog}
3068 usbprog is a freely programmable USB adapter.
3069 @end deffn
3070
3071 @deffn {Interface Driver} {vsllink}
3072 vsllink is part of Versaloon which is a versatile USB programmer.
3073
3074 @quotation Note
3075 This defines quite a few driver-specific commands,
3076 which are not currently documented here.
3077 @end quotation
3078 @end deffn
3079
3080 @deffn {Interface Driver} {hla}
3081 This is a driver that supports multiple High Level Adapters.
3082 This type of adapter does not expose some of the lower level api's
3083 that OpenOCD would normally use to access the target.
3084
3085 Currently supported adapters include the ST STLINK and TI ICDI.
3086 STLINK firmware version >= V2.J21.S4 recommended due to issues with earlier
3087 versions of firmware where serial number is reset after first use. Suggest
3088 using ST firmware update utility to upgrade STLINK firmware even if current
3089 version reported is V2.J21.S4.
3090
3091 @deffn {Config Command} {hla_device_desc} description
3092 Currently Not Supported.
3093 @end deffn
3094
3095 @deffn {Config Command} {hla_serial} serial
3096 Specifies the serial number of the adapter.
3097 @end deffn
3098
3099 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
3100 Specifies the adapter layout to use.
3101 @end deffn
3102
3103 @deffn {Config Command} {hla_vid_pid} vid pid
3104 The vendor ID and product ID of the device.
3105 @end deffn
3106
3107 @deffn {Command} {hla_command} command
3108 Execute a custom adapter-specific command. The @var{command} string is
3109 passed as is to the underlying adapter layout handler.
3110 @end deffn
3111
3112 @deffn {Config Command} {trace} source_clock_hz [output_file_path]
3113 Enable SWO tracing (if supported). The source clock rate for the
3114 trace port must be specified, this is typically the CPU clock rate. If
3115 the optional output file is specified then raw trace data is appended
3116 to the file, and the file is created if it does not exist.
3117 @end deffn
3118 @end deffn
3119
3120 @deffn {Interface Driver} {opendous}
3121 opendous-jtag is a freely programmable USB adapter.
3122 @end deffn
3123
3124 @deffn {Interface Driver} {ulink}
3125 This is the Keil ULINK v1 JTAG debugger.
3126 @end deffn
3127
3128 @deffn {Interface Driver} {ZY1000}
3129 This is the Zylin ZY1000 JTAG debugger.
3130 @end deffn
3131
3132 @quotation Note
3133 This defines some driver-specific commands,
3134 which are not currently documented here.
3135 @end quotation
3136
3137 @deffn Command power [@option{on}|@option{off}]
3138 Turn power switch to target on/off.
3139 No arguments: print status.
3140 @end deffn
3141
3142 @deffn {Interface Driver} {bcm2835gpio}
3143 This SoC is present in Raspberry Pi which is a cheap single-board computer
3144 exposing some GPIOs on its expansion header.
3145
3146 The driver accesses memory-mapped GPIO peripheral registers directly
3147 for maximum performance, but the only possible race condition is for
3148 the pins' modes/muxing (which is highly unlikely), so it should be
3149 able to coexist nicely with both sysfs bitbanging and various
3150 peripherals' kernel drivers. The driver restores the previous
3151 configuration on exit.
3152
3153 See @file{interface/raspberrypi-native.cfg} for a sample config and
3154 pinout.
3155
3156 @end deffn
3157
3158 @section Transport Configuration
3159 @cindex Transport
3160 As noted earlier, depending on the version of OpenOCD you use,
3161 and the debug adapter you are using,
3162 several transports may be available to
3163 communicate with debug targets (or perhaps to program flash memory).
3164 @deffn Command {transport list}
3165 displays the names of the transports supported by this
3166 version of OpenOCD.
3167 @end deffn
3168
3169 @deffn Command {transport select} transport_name
3170 Select which of the supported transports to use in this OpenOCD session.
3171 The transport must be supported by the debug adapter hardware and by the
3172 version of OpenOCD you are using (including the adapter's driver).
3173 No arguments: returns name of session's selected transport.
3174 @end deffn
3175
3176 @subsection JTAG Transport
3177 @cindex JTAG
3178 JTAG is the original transport supported by OpenOCD, and most
3179 of the OpenOCD commands support it.
3180 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3181 each of which must be explicitly declared.
3182 JTAG supports both debugging and boundary scan testing.
3183 Flash programming support is built on top of debug support.
3184 @subsection SWD Transport
3185 @cindex SWD
3186 @cindex Serial Wire Debug
3187 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3188 Debug Access Point (DAP, which must be explicitly declared.
3189 (SWD uses fewer signal wires than JTAG.)
3190 SWD is debug-oriented, and does not support boundary scan testing.
3191 Flash programming support is built on top of debug support.
3192 (Some processors support both JTAG and SWD.)
3193 @deffn Command {swd newdap} ...
3194 Declares a single DAP which uses SWD transport.
3195 Parameters are currently the same as "jtag newtap" but this is
3196 expected to change.
3197 @end deffn
3198 @deffn Command {swd wcr trn prescale}
3199 Updates TRN (turnaraound delay) and prescaling.fields of the
3200 Wire Control Register (WCR).
3201 No parameters: displays current settings.
3202 @end deffn
3203
3204 @subsection CMSIS-DAP Transport
3205 @cindex CMSIS-DAP
3206 CMSIS-DAP is an ARM-specific transport that is used to connect to
3207 compilant debuggers.
3208
3209 @subsection SPI Transport
3210 @cindex SPI
3211 @cindex Serial Peripheral Interface
3212 The Serial Peripheral Interface (SPI) is a general purpose transport
3213 which uses four wire signaling. Some processors use it as part of a
3214 solution for flash programming.
3215
3216 @anchor{jtagspeed}
3217 @section JTAG Speed
3218 JTAG clock setup is part of system setup.
3219 It @emph{does not belong with interface setup} since any interface
3220 only knows a few of the constraints for the JTAG clock speed.
3221 Sometimes the JTAG speed is
3222 changed during the target initialization process: (1) slow at
3223 reset, (2) program the CPU clocks, (3) run fast.
3224 Both the "slow" and "fast" clock rates are functions of the
3225 oscillators used, the chip, the board design, and sometimes
3226 power management software that may be active.
3227
3228 The speed used during reset, and the scan chain verification which
3229 follows reset, can be adjusted using a @code{reset-start}
3230 target event handler.
3231 It can then be reconfigured to a faster speed by a
3232 @code{reset-init} target event handler after it reprograms those
3233 CPU clocks, or manually (if something else, such as a boot loader,
3234 sets up those clocks).
3235 @xref{targetevents,,Target Events}.
3236 When the initial low JTAG speed is a chip characteristic, perhaps
3237 because of a required oscillator speed, provide such a handler
3238 in the target config file.
3239 When that speed is a function of a board-specific characteristic
3240 such as which speed oscillator is used, it belongs in the board
3241 config file instead.
3242 In both cases it's safest to also set the initial JTAG clock rate
3243 to that same slow speed, so that OpenOCD never starts up using a
3244 clock speed that's faster than the scan chain can support.
3245
3246 @example
3247 jtag_rclk 3000
3248 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3249 @end example
3250
3251 If your system supports adaptive clocking (RTCK), configuring
3252 JTAG to use that is probably the most robust approach.
3253 However, it introduces delays to synchronize clocks; so it
3254 may not be the fastest solution.
3255
3256 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3257 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3258 which support adaptive clocking.
3259
3260 @deffn {Command} adapter_khz max_speed_kHz
3261 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3262 JTAG interfaces usually support a limited number of
3263 speeds. The speed actually used won't be faster
3264 than the speed specified.
3265
3266 Chip data sheets generally include a top JTAG clock rate.
3267 The actual rate is often a function of a CPU core clock,
3268 and is normally less than that peak rate.
3269 For example, most ARM cores accept at most one sixth of the CPU clock.
3270
3271 Speed 0 (khz) selects RTCK method.
3272 @xref{faqrtck,,FAQ RTCK}.
3273 If your system uses RTCK, you won't need to change the
3274 JTAG clocking after setup.
3275 Not all interfaces, boards, or targets support ``rtck''.
3276 If the interface device can not
3277 support it, an error is returned when you try to use RTCK.
3278 @end deffn
3279
3280 @defun jtag_rclk fallback_speed_kHz
3281 @cindex adaptive clocking
3282 @cindex RTCK
3283 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3284 If that fails (maybe the interface, board, or target doesn't
3285 support it), falls back to the specified frequency.
3286 @example
3287 # Fall back to 3mhz if RTCK is not supported
3288 jtag_rclk 3000
3289 @end example
3290 @end defun
3291
3292 @node Reset Configuration
3293 @chapter Reset Configuration
3294 @cindex Reset Configuration
3295
3296 Every system configuration may require a different reset
3297 configuration. This can also be quite confusing.
3298 Resets also interact with @var{reset-init} event handlers,
3299 which do things like setting up clocks and DRAM, and
3300 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3301 They can also interact with JTAG routers.
3302 Please see the various board files for examples.
3303
3304 @quotation Note
3305 To maintainers and integrators:
3306 Reset configuration touches several things at once.
3307 Normally the board configuration file
3308 should define it and assume that the JTAG adapter supports
3309 everything that's wired up to the board's JTAG connector.
3310
3311 However, the target configuration file could also make note
3312 of something the silicon vendor has done inside the chip,
3313 which will be true for most (or all) boards using that chip.
3314 And when the JTAG adapter doesn't support everything, the
3315 user configuration file will need to override parts of
3316 the reset configuration provided by other files.
3317 @end quotation
3318
3319 @section Types of Reset
3320
3321 There are many kinds of reset possible through JTAG, but
3322 they may not all work with a given board and adapter.
3323 That's part of why reset configuration can be error prone.
3324
3325 @itemize @bullet
3326 @item
3327 @emph{System Reset} ... the @emph{SRST} hardware signal
3328 resets all chips connected to the JTAG adapter, such as processors,
3329 power management chips, and I/O controllers. Normally resets triggered
3330 with this signal behave exactly like pressing a RESET button.
3331 @item
3332 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3333 just the TAP controllers connected to the JTAG adapter.
3334 Such resets should not be visible to the rest of the system; resetting a
3335 device's TAP controller just puts that controller into a known state.
3336 @item
3337 @emph{Emulation Reset} ... many devices can be reset through JTAG
3338 commands. These resets are often distinguishable from system
3339 resets, either explicitly (a "reset reason" register says so)
3340 or implicitly (not all parts of the chip get reset).
3341 @item
3342 @emph{Other Resets} ... system-on-chip devices often support
3343 several other types of reset.
3344 You may need to arrange that a watchdog timer stops
3345 while debugging, preventing a watchdog reset.
3346 There may be individual module resets.
3347 @end itemize
3348
3349 In the best case, OpenOCD can hold SRST, then reset
3350 the TAPs via TRST and send commands through JTAG to halt the
3351 CPU at the reset vector before the 1st instruction is executed.
3352 Then when it finally releases the SRST signal, the system is
3353 halted under debugger control before any code has executed.
3354 This is the behavior required to support the @command{reset halt}
3355 and @command{reset init} commands; after @command{reset init} a
3356 board-specific script might do things like setting up DRAM.
3357 (@xref{resetcommand,,Reset Command}.)
3358
3359 @anchor{srstandtrstissues}
3360 @section SRST and TRST Issues
3361
3362 Because SRST and TRST are hardware signals, they can have a
3363 variety of system-specific constraints. Some of the most
3364 common issues are:
3365
3366 @itemize @bullet
3367
3368 @item @emph{Signal not available} ... Some boards don't wire
3369 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3370 support such signals even if they are wired up.
3371 Use the @command{reset_config} @var{signals} options to say
3372 when either of those signals is not connected.
3373 When SRST is not available, your code might not be able to rely
3374 on controllers having been fully reset during code startup.
3375 Missing TRST is not a problem, since JTAG-level resets can
3376 be triggered using with TMS signaling.
3377
3378 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3379 adapter will connect SRST to TRST, instead of keeping them separate.
3380 Use the @command{reset_config} @var{combination} options to say
3381 when those signals aren't properly independent.
3382
3383 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3384 delay circuit, reset supervisor, or on-chip features can extend
3385 the effect of a JTAG adapter's reset for some time after the adapter
3386 stops issuing the reset. For example, there may be chip or board
3387 requirements that all reset pulses last for at least a
3388 certain amount of time; and reset buttons commonly have
3389 hardware debouncing.
3390 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3391 commands to say when extra delays are needed.
3392
3393 @item @emph{Drive type} ... Reset lines often have a pullup
3394 resistor, letting the JTAG interface treat them as open-drain
3395 signals. But that's not a requirement, so the adapter may need
3396 to use push/pull output drivers.
3397 Also, with weak pullups it may be advisable to drive
3398 signals to both levels (push/pull) to minimize rise times.
3399 Use the @command{reset_config} @var{trst_type} and
3400 @var{srst_type} parameters to say how to drive reset signals.
3401
3402 @item @emph{Special initialization} ... Targets sometimes need
3403 special JTAG initialization sequences to handle chip-specific
3404 issues (not limited to errata).
3405 For example, certain JTAG commands might need to be issued while
3406 the system as a whole is in a reset state (SRST active)
3407 but the JTAG scan chain is usable (TRST inactive).
3408 Many systems treat combined assertion of SRST and TRST as a
3409 trigger for a harder reset than SRST alone.
3410 Such custom reset handling is discussed later in this chapter.
3411 @end itemize
3412
3413 There can also be other issues.
3414 Some devices don't fully conform to the JTAG specifications.
3415 Trivial system-specific differences are common, such as
3416 SRST and TRST using slightly different names.
3417 There are also vendors who distribute key JTAG documentation for
3418 their chips only to developers who have signed a Non-Disclosure
3419 Agreement (NDA).
3420
3421 Sometimes there are chip-specific extensions like a requirement to use
3422 the normally-optional TRST signal (precluding use of JTAG adapters which
3423 don't pass TRST through), or needing extra steps to complete a TAP reset.
3424
3425 In short, SRST and especially TRST handling may be very finicky,
3426 needing to cope with both architecture and board specific constraints.
3427
3428 @section Commands for Handling Resets
3429
3430 @deffn {Command} adapter_nsrst_assert_width milliseconds
3431 Minimum amount of time (in milliseconds) OpenOCD should wait
3432 after asserting nSRST (active-low system reset) before
3433 allowing it to be deasserted.
3434 @end deffn
3435
3436 @deffn {Command} adapter_nsrst_delay milliseconds
3437 How long (in milliseconds) OpenOCD should wait after deasserting
3438 nSRST (active-low system reset) before starting new JTAG operations.
3439 When a board has a reset button connected to SRST line it will
3440 probably have hardware debouncing, implying you should use this.
3441 @end deffn
3442
3443 @deffn {Command} jtag_ntrst_assert_width milliseconds
3444 Minimum amount of time (in milliseconds) OpenOCD should wait
3445 after asserting nTRST (active-low JTAG TAP reset) before
3446 allowing it to be deasserted.
3447 @end deffn
3448
3449 @deffn {Command} jtag_ntrst_delay milliseconds
3450 How long (in milliseconds) OpenOCD should wait after deasserting
3451 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3452 @end deffn
3453
3454 @deffn {Command} reset_config mode_flag ...
3455 This command displays or modifies the reset configuration
3456 of your combination of JTAG board and target in target
3457 configuration scripts.
3458
3459 Information earlier in this section describes the kind of problems
3460 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3461 As a rule this command belongs only in board config files,
3462 describing issues like @emph{board doesn't connect TRST};
3463 or in user config files, addressing limitations derived
3464 from a particular combination of interface and board.
3465 (An unlikely example would be using a TRST-only adapter
3466 with a board that only wires up SRST.)
3467
3468 The @var{mode_flag} options can be specified in any order, but only one
3469 of each type -- @var{signals}, @var{combination}, @var{gates},
3470 @var{trst_type}, @var{srst_type} and @var{connect_type}
3471 -- may be specified at a time.
3472 If you don't provide a new value for a given type, its previous
3473 value (perhaps the default) is unchanged.
3474 For example, this means that you don't need to say anything at all about
3475 TRST just to declare that if the JTAG adapter should want to drive SRST,
3476 it must explicitly be driven high (@option{srst_push_pull}).
3477
3478 @itemize
3479 @item
3480 @var{signals} can specify which of the reset signals are connected.
3481 For example, If the JTAG interface provides SRST, but the board doesn't
3482 connect that signal properly, then OpenOCD can't use it.
3483 Possible values are @option{none} (the default), @option{trst_only},
3484 @option{srst_only} and @option{trst_and_srst}.
3485
3486 @quotation Tip
3487 If your board provides SRST and/or TRST through the JTAG connector,
3488 you must declare that so those signals can be used.
3489 @end quotation
3490
3491 @item
3492 The @var{combination} is an optional value specifying broken reset
3493 signal implementations.
3494 The default behaviour if no option given is @option{separate},
3495 indicating everything behaves normally.
3496 @option{srst_pulls_trst} states that the
3497 test logic is reset together with the reset of the system (e.g. NXP
3498 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3499 the system is reset together with the test logic (only hypothetical, I
3500 haven't seen hardware with such a bug, and can be worked around).
3501 @option{combined} implies both @option{srst_pulls_trst} and
3502 @option{trst_pulls_srst}.
3503
3504 @item
3505 The @var{gates} tokens control flags that describe some cases where
3506 JTAG may be unvailable during reset.
3507 @option{srst_gates_jtag} (default)
3508 indicates that asserting SRST gates the
3509 JTAG clock. This means that no communication can happen on JTAG
3510 while SRST is asserted.
3511 Its converse is @option{srst_nogate}, indicating that JTAG commands
3512 can safely be issued while SRST is active.
3513
3514 @item
3515 The @var{connect_type} tokens control flags that describe some cases where
3516 SRST is asserted while connecting to the target. @option{srst_nogate}
3517 is required to use this option.
3518 @option{connect_deassert_srst} (default)
3519 indicates that SRST will not be asserted while connecting to the target.
3520 Its converse is @option{connect_assert_srst}, indicating that SRST will
3521 be asserted before any target connection.
3522 Only some targets support this feature, STM32 and STR9 are examples.
3523 This feature is useful if you are unable to connect to your target due
3524 to incorrect options byte config or illegal program execution.
3525 @end itemize
3526
3527 The optional @var{trst_type} and @var{srst_type} parameters allow the
3528 driver mode of each reset line to be specified. These values only affect
3529 JTAG interfaces with support for different driver modes, like the Amontec
3530 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3531 relevant signal (TRST or SRST) is not connected.
3532
3533 @itemize
3534 @item
3535 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3536 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3537 Most boards connect this signal to a pulldown, so the JTAG TAPs
3538 never leave reset unless they are hooked up to a JTAG adapter.
3539
3540 @item
3541 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3542 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3543 Most boards connect this signal to a pullup, and allow the
3544 signal to be pulled low by various events including system
3545 powerup and pressing a reset button.
3546 @end itemize
3547 @end deffn
3548
3549 @section Custom Reset Handling
3550 @cindex events
3551
3552 OpenOCD has several ways to help support the various reset
3553 mechanisms provided by chip and board vendors.
3554 The commands shown in the previous section give standard parameters.
3555 There are also @emph{event handlers} associated with TAPs or Targets.
3556 Those handlers are Tcl procedures you can provide, which are invoked
3557 at particular points in the reset sequence.
3558
3559 @emph{When SRST is not an option} you must set
3560 up a @code{reset-assert} event handler for your target.
3561 For example, some JTAG adapters don't include the SRST signal;
3562 and some boards have multiple targets, and you won't always
3563 want to reset everything at once.
3564
3565 After configuring those mechanisms, you might still
3566 find your board doesn't start up or reset correctly.
3567 For example, maybe it needs a slightly different sequence
3568 of SRST and/or TRST manipulations, because of quirks that
3569 the @command{reset_config} mechanism doesn't address;
3570 or asserting both might trigger a stronger reset, which
3571 needs special attention.
3572
3573 Experiment with lower level operations, such as @command{jtag_reset}
3574 and the @command{jtag arp_*} operations shown here,
3575 to find a sequence of operations that works.
3576 @xref{JTAG Commands}.
3577 When you find a working sequence, it can be used to override
3578 @command{jtag_init}, which fires during OpenOCD startup
3579 (@pxref{configurationstage,,Configuration Stage});
3580 or @command{init_reset}, which fires during reset processing.
3581
3582 You might also want to provide some project-specific reset
3583 schemes. For example, on a multi-target board the standard
3584 @command{reset} command would reset all targets, but you
3585 may need the ability to reset only one target at time and
3586 thus want to avoid using the board-wide SRST signal.
3587
3588 @deffn {Overridable Procedure} init_reset mode
3589 This is invoked near the beginning of the @command{reset} command,
3590 usually to provide as much of a cold (power-up) reset as practical.
3591 By default it is also invoked from @command{jtag_init} if
3592 the scan chain does not respond to pure JTAG operations.
3593 The @var{mode} parameter is the parameter given to the
3594 low level reset command (@option{halt},
3595 @option{init}, or @option{run}), @option{setup},
3596 or potentially some other value.
3597
3598 The default implementation just invokes @command{jtag arp_init-reset}.
3599 Replacements will normally build on low level JTAG
3600 operations such as @command{jtag_reset}.
3601 Operations here must not address individual TAPs
3602 (or their associated targets)
3603 until the JTAG scan chain has first been verified to work.
3604
3605 Implementations must have verified the JTAG scan chain before
3606 they return.
3607 This is done by calling @command{jtag arp_init}
3608 (or @command{jtag arp_init-reset}).
3609 @end deffn
3610
3611 @deffn Command {jtag arp_init}
3612 This validates the scan chain using just the four
3613 standard JTAG signals (TMS, TCK, TDI, TDO).
3614 It starts by issuing a JTAG-only reset.
3615 Then it performs checks to verify that the scan chain configuration
3616 matches the TAPs it can observe.
3617 Those checks include checking IDCODE values for each active TAP,
3618 and verifying the length of their instruction registers using
3619 TAP @code{-ircapture} and @code{-irmask} values.
3620 If these tests all pass, TAP @code{setup} events are
3621 issued to all TAPs with handlers for that event.
3622 @end deffn
3623
3624 @deffn Command {jtag arp_init-reset}
3625 This uses TRST and SRST to try resetting
3626 everything on the JTAG scan chain
3627 (and anything else connected to SRST).
3628 It then invokes the logic of @command{jtag arp_init}.
3629 @end deffn
3630
3631
3632 @node TAP Declaration
3633 @chapter TAP Declaration
3634 @cindex TAP declaration
3635 @cindex TAP configuration
3636
3637 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3638 TAPs serve many roles, including:
3639
3640 @itemize @bullet
3641 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3642 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3643 Others do it indirectly, making a CPU do it.
3644 @item @b{Program Download} Using the same CPU support GDB uses,
3645 you can initialize a DRAM controller, download code to DRAM, and then
3646 start running that code.
3647 @item @b{Boundary Scan} Most chips support boundary scan, which
3648 helps test for board assembly problems like solder bridges
3649 and missing connections.
3650 @end itemize
3651
3652 OpenOCD must know about the active TAPs on your board(s).
3653 Setting up the TAPs is the core task of your configuration files.
3654 Once those TAPs are set up, you can pass their names to code
3655 which sets up CPUs and exports them as GDB targets,
3656 probes flash memory, performs low-level JTAG operations, and more.
3657
3658 @section Scan Chains
3659 @cindex scan chain
3660
3661 TAPs are part of a hardware @dfn{scan chain},
3662 which is a daisy chain of TAPs.
3663 They also need to be added to
3664 OpenOCD's software mirror of that hardware list,
3665 giving each member a name and associating other data with it.
3666 Simple scan chains, with a single TAP, are common in
3667 systems with a single microcontroller or microprocessor.
3668 More complex chips may have several TAPs internally.
3669 Very complex scan chains might have a dozen or more TAPs:
3670 several in one chip, more in the next, and connecting
3671 to other boards with their own chips and TAPs.
3672
3673 You can display the list with the @command{scan_chain} command.
3674 (Don't confuse this with the list displayed by the @command{targets}
3675 command, presented in the next chapter.
3676 That only displays TAPs for CPUs which are configured as
3677 debugging targets.)
3678 Here's what the scan chain might look like for a chip more than one TAP:
3679
3680 @verbatim
3681 TapName Enabled IdCode Expected IrLen IrCap IrMask
3682 -- ------------------ ------- ---------- ---------- ----- ----- ------
3683 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3684 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3685 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3686 @end verbatim
3687
3688 OpenOCD can detect some of that information, but not all
3689 of it. @xref{autoprobing,,Autoprobing}.
3690 Unfortunately, those TAPs can't always be autoconfigured,
3691 because not all devices provide good support for that.
3692 JTAG doesn't require supporting IDCODE instructions, and
3693 chips with JTAG routers may not link TAPs into the chain
3694 until they are told to do so.
3695
3696 The configuration mechanism currently supported by OpenOCD
3697 requires explicit configuration of all TAP devices using
3698 @command{jtag newtap} commands, as detailed later in this chapter.
3699 A command like this would declare one tap and name it @code{chip1.cpu}:
3700
3701 @example
3702 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3703 @end example
3704
3705 Each target configuration file lists the TAPs provided
3706 by a given chip.
3707 Board configuration files combine all the targets on a board,
3708 and so forth.
3709 Note that @emph{the order in which TAPs are declared is very important.}
3710 That declaration order must match the order in the JTAG scan chain,
3711 both inside a single chip and between them.
3712 @xref{faqtaporder,,FAQ TAP Order}.
3713
3714 For example, the ST Microsystems STR912 chip has
3715 three separate TAPs@footnote{See the ST
3716 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3717 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3718 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3719 To configure those taps, @file{target/str912.cfg}
3720 includes commands something like this:
3721
3722 @example
3723 jtag newtap str912 flash ... params ...
3724 jtag newtap str912 cpu ... params ...
3725 jtag newtap str912 bs ... params ...
3726 @end example
3727
3728 Actual config files typically use a variable such as @code{$_CHIPNAME}
3729 instead of literals like @option{str912}, to support more than one chip
3730 of each type. @xref{Config File Guidelines}.
3731
3732 @deffn Command {jtag names}
3733 Returns the names of all current TAPs in the scan chain.
3734 Use @command{jtag cget} or @command{jtag tapisenabled}
3735 to examine attributes and state of each TAP.
3736 @example
3737 foreach t [jtag names] @{
3738 puts [format "TAP: %s\n" $t]
3739 @}
3740 @end example
3741 @end deffn
3742
3743 @deffn Command {scan_chain}
3744 Displays the TAPs in the scan chain configuration,
3745 and their status.
3746 The set of TAPs listed by this command is fixed by
3747 exiting the OpenOCD configuration stage,
3748 but systems with a JTAG router can
3749 enable or disable TAPs dynamically.
3750 @end deffn
3751
3752 @c FIXME! "jtag cget" should be able to return all TAP
3753 @c attributes, like "$target_name cget" does for targets.
3754
3755 @c Probably want "jtag eventlist", and a "tap-reset" event
3756 @c (on entry to RESET state).
3757
3758 @section TAP Names
3759 @cindex dotted name
3760
3761 When TAP objects are declared with @command{jtag newtap},
3762 a @dfn{dotted.name} is created for the TAP, combining the
3763 name of a module (usually a chip) and a label for the TAP.
3764 For example: @code{xilinx.tap}, @code{str912.flash},
3765 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3766 Many other commands use that dotted.name to manipulate or
3767 refer to the TAP. For example, CPU configuration uses the
3768 name, as does declaration of NAND or NOR flash banks.
3769
3770 The components of a dotted name should follow ``C'' symbol
3771 name rules: start with an alphabetic character, then numbers
3772 and underscores are OK; while others (including dots!) are not.
3773
3774 @section TAP Declaration Commands
3775
3776 @c shouldn't this be(come) a {Config Command}?
3777 @deffn Command {jtag newtap} chipname tapname configparams...
3778 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3779 and configured according to the various @var{configparams}.
3780
3781 The @var{chipname} is a symbolic name for the chip.
3782 Conventionally target config files use @code{$_CHIPNAME},
3783 defaulting to the model name given by the chip vendor but
3784 overridable.
3785
3786 @cindex TAP naming convention
3787 The @var{tapname} reflects the role of that TAP,
3788 and should follow this convention:
3789
3790 @itemize @bullet
3791 @item @code{bs} -- For boundary scan if this is a separate TAP;
3792 @item @code{cpu} -- The main CPU of the chip, alternatively
3793 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3794 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3795 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3796 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3797 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3798 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3799 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3800 with a single TAP;
3801 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3802 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3803 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3804 a JTAG TAP; that TAP should be named @code{sdma}.
3805 @end itemize
3806
3807 Every TAP requires at least the following @var{configparams}:
3808
3809 @itemize @bullet
3810 @item @code{-irlen} @var{NUMBER}
3811 @*The length in bits of the
3812 instruction register, such as 4 or 5 bits.
3813 @end itemize
3814
3815 A TAP may also provide optional @var{configparams}:
3816
3817 @itemize @bullet
3818 @item @code{-disable} (or @code{-enable})
3819 @*Use the @code{-disable} parameter to flag a TAP which is not
3820 linked into the scan chain after a reset using either TRST
3821 or the JTAG state machine's @sc{reset} state.
3822 You may use @code{-enable} to highlight the default state
3823 (the TAP is linked in).
3824 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3825 @item @code{-expected-id} @var{NUMBER}
3826 @*A non-zero @var{number} represents a 32-bit IDCODE
3827 which you expect to find when the scan chain is examined.
3828 These codes are not required by all JTAG devices.
3829 @emph{Repeat the option} as many times as required if more than one
3830 ID code could appear (for example, multiple versions).
3831 Specify @var{number} as zero to suppress warnings about IDCODE
3832 values that were found but not included in the list.
3833
3834 Provide this value if at all possible, since it lets OpenOCD
3835 tell when the scan chain it sees isn't right. These values
3836 are provided in vendors' chip documentation, usually a technical
3837 reference manual. Sometimes you may need to probe the JTAG
3838 hardware to find these values.
3839 @xref{autoprobing,,Autoprobing}.
3840 @item @code{-ignore-version}
3841 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3842 option. When vendors put out multiple versions of a chip, or use the same
3843 JTAG-level ID for several largely-compatible chips, it may be more practical
3844 to ignore the version field than to update config files to handle all of
3845 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3846 @item @code{-ircapture} @var{NUMBER}
3847 @*The bit pattern loaded by the TAP into the JTAG shift register
3848 on entry to the @sc{ircapture} state, such as 0x01.
3849 JTAG requires the two LSBs of this value to be 01.
3850 By default, @code{-ircapture} and @code{-irmask} are set
3851 up to verify that two-bit value. You may provide
3852 additional bits if you know them, or indicate that
3853 a TAP doesn't conform to the JTAG specification.
3854 @item @code{-irmask} @var{NUMBER}
3855 @*A mask used with @code{-ircapture}
3856 to verify that instruction scans work correctly.
3857 Such scans are not used by OpenOCD except to verify that
3858 there seems to be no problems with JTAG scan chain operations.
3859 @end itemize
3860 @end deffn
3861
3862 @section Other TAP commands
3863
3864 @deffn Command {jtag cget} dotted.name @option{-event} event_name
3865 @deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
3866 At this writing this TAP attribute
3867 mechanism is used only for event handling.
3868 (It is not a direct analogue of the @code{cget}/@code{configure}
3869 mechanism for debugger targets.)
3870 See the next section for information about the available events.
3871
3872 The @code{configure} subcommand assigns an event handler,
3873 a TCL string which is evaluated when the event is triggered.
3874 The @code{cget} subcommand returns that handler.
3875 @end deffn
3876
3877 @section TAP Events
3878 @cindex events
3879 @cindex TAP events
3880
3881 OpenOCD includes two event mechanisms.
3882 The one presented here applies to all JTAG TAPs.
3883 The other applies to debugger targets,
3884 which are associated with certain TAPs.
3885
3886 The TAP events currently defined are:
3887
3888 @itemize @bullet
3889 @item @b{post-reset}
3890 @* The TAP has just completed a JTAG reset.
3891 The tap may still be in the JTAG @sc{reset} state.
3892 Handlers for these events might perform initialization sequences
3893 such as issuing TCK cycles, TMS sequences to ensure
3894 exit from the ARM SWD mode, and more.
3895
3896 Because the scan chain has not yet been verified, handlers for these events
3897 @emph{should not issue commands which scan the JTAG IR or DR registers}
3898 of any particular target.
3899 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3900 @item @b{setup}
3901 @* The scan chain has been reset and verified.
3902 This handler may enable TAPs as needed.
3903 @item @b{tap-disable}
3904 @* The TAP needs to be disabled. This handler should
3905 implement @command{jtag tapdisable}
3906 by issuing the relevant JTAG commands.
3907 @item @b{tap-enable}
3908 @* The TAP needs to be enabled. This handler should
3909 implement @command{jtag tapenable}
3910 by issuing the relevant JTAG commands.
3911 @end itemize
3912
3913 If you need some action after each JTAG reset which isn't actually
3914 specific to any TAP (since you can't yet trust the scan chain's
3915 contents to be accurate), you might:
3916
3917 @example
3918 jtag configure CHIP.jrc -event post-reset @{
3919 echo "JTAG Reset done"
3920 ... non-scan jtag operations to be done after reset
3921 @}
3922 @end example
3923
3924
3925 @anchor{enablinganddisablingtaps}
3926 @section Enabling and Disabling TAPs
3927 @cindex JTAG Route Controller
3928 @cindex jrc
3929
3930 In some systems, a @dfn{JTAG Route Controller} (JRC)
3931 is used to enable and/or disable specific JTAG TAPs.
3932 Many ARM-based chips from Texas Instruments include
3933 an ``ICEPick'' module, which is a JRC.
3934 Such chips include DaVinci and OMAP3 processors.
3935
3936 A given TAP may not be visible until the JRC has been
3937 told to link it into the scan chain; and if the JRC
3938 has been told to unlink that TAP, it will no longer
3939 be visible.
3940 Such routers address problems that JTAG ``bypass mode''
3941 ignores, such as:
3942
3943 @itemize
3944 @item The scan chain can only go as fast as its slowest TAP.
3945 @item Having many TAPs slows instruction scans, since all
3946 TAPs receive new instructions.
3947 @item TAPs in the scan chain must be powered up, which wastes
3948 power and prevents debugging some power management mechanisms.
3949 @end itemize
3950
3951 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3952 as implied by the existence of JTAG routers.
3953 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3954 does include a kind of JTAG router functionality.
3955
3956 @c (a) currently the event handlers don't seem to be able to
3957 @c fail in a way that could lead to no-change-of-state.
3958
3959 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3960 shown below, and is implemented using TAP event handlers.
3961 So for example, when defining a TAP for a CPU connected to
3962 a JTAG router, your @file{target.cfg} file
3963 should define TAP event handlers using
3964 code that looks something like this:
3965
3966 @example
3967 jtag configure CHIP.cpu -event tap-enable @{
3968 ... jtag operations using CHIP.jrc
3969 @}
3970 jtag configure CHIP.cpu -event tap-disable @{
3971 ... jtag operations using CHIP.jrc
3972 @}
3973 @end example
3974
3975 Then you might want that CPU's TAP enabled almost all the time:
3976
3977 @example
3978 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3979 @end example
3980
3981 Note how that particular setup event handler declaration
3982 uses quotes to evaluate @code{$CHIP} when the event is configured.
3983 Using brackets @{ @} would cause it to be evaluated later,
3984 at runtime, when it might have a different value.
3985
3986 @deffn Command {jtag tapdisable} dotted.name
3987 If necessary, disables the tap
3988 by sending it a @option{tap-disable} event.
3989 Returns the string "1" if the tap
3990 specified by @var{dotted.name} is enabled,
3991 and "0" if it is disabled.
3992 @end deffn
3993
3994 @deffn Command {jtag tapenable} dotted.name
3995 If necessary, enables the tap
3996 by sending it a @option{tap-enable} event.
3997 Returns the string "1" if the tap
3998 specified by @var{dotted.name} is enabled,
3999 and "0" if it is disabled.
4000 @end deffn
4001
4002 @deffn Command {jtag tapisenabled} dotted.name
4003 Returns the string "1" if the tap
4004 specified by @var{dotted.name} is enabled,
4005 and "0" if it is disabled.
4006
4007 @quotation Note
4008 Humans will find the @command{scan_chain} command more helpful
4009 for querying the state of the JTAG taps.
4010 @end quotation
4011 @end deffn
4012
4013 @anchor{autoprobing}
4014 @section Autoprobing
4015 @cindex autoprobe
4016 @cindex JTAG autoprobe
4017
4018 TAP configuration is the first thing that needs to be done
4019 after interface and reset configuration. Sometimes it's
4020 hard finding out what TAPs exist, or how they are identified.
4021 Vendor documentation is not always easy to find and use.
4022
4023 To help you get past such problems, OpenOCD has a limited
4024 @emph{autoprobing} ability to look at the scan chain, doing
4025 a @dfn{blind interrogation} and then reporting the TAPs it finds.
4026 To use this mechanism, start the OpenOCD server with only data
4027 that configures your JTAG interface, and arranges to come up
4028 with a slow clock (many devices don't support fast JTAG clocks
4029 right when they come out of reset).
4030
4031 For example, your @file{openocd.cfg} file might have:
4032
4033 @example
4034 source [find interface/olimex-arm-usb-tiny-h.cfg]
4035 reset_config trst_and_srst
4036 jtag_rclk 8
4037 @end example
4038
4039 When you start the server without any TAPs configured, it will
4040 attempt to autoconfigure the TAPs. There are two parts to this:
4041
4042 @enumerate
4043 @item @emph{TAP discovery} ...
4044 After a JTAG reset (sometimes a system reset may be needed too),
4045 each TAP's data registers will hold the contents of either the
4046 IDCODE or BYPASS register.
4047 If JTAG communication is working, OpenOCD will see each TAP,
4048 and report what @option{-expected-id} to use with it.
4049 @item @emph{IR Length discovery} ...
4050 Unfortunately JTAG does not provide a reliable way to find out
4051 the value of the @option{-irlen} parameter to use with a TAP
4052 that is discovered.
4053 If OpenOCD can discover the length of a TAP's instruction
4054 register, it will report it.
4055 Otherwise you may need to consult vendor documentation, such
4056 as chip data sheets or BSDL files.
4057 @end enumerate
4058
4059 In many cases your board will have a simple scan chain with just
4060 a single device. Here's what OpenOCD reported with one board
4061 that's a bit more complex:
4062
4063 @example
4064 clock speed 8 kHz
4065 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4066 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4067 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4068 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4069 AUTO auto0.tap - use "... -irlen 4"
4070 AUTO auto1.tap - use "... -irlen 4"
4071 AUTO auto2.tap - use "... -irlen 6"
4072 no gdb ports allocated as no target has been specified
4073 @end example
4074
4075 Given that information, you should be able to either find some existing
4076 config files to use, or create your own. If you create your own, you
4077 would configure from the bottom up: first a @file{target.cfg} file
4078 with these TAPs, any targets associated with them, and any on-chip
4079 resources; then a @file{board.cfg} with off-chip resources, clocking,
4080 and so forth.
4081
4082 @node CPU Configuration
4083 @chapter CPU Configuration
4084 @cindex GDB target
4085
4086 This chapter discusses how to set up GDB debug targets for CPUs.
4087 You can also access these targets without GDB
4088 (@pxref{Architecture and Core Commands},
4089 and @ref{targetstatehandling,,Target State handling}) and
4090 through various kinds of NAND and NOR flash commands.
4091 If you have multiple CPUs you can have multiple such targets.
4092
4093 We'll start by looking at how to examine the targets you have,
4094 then look at how to add one more target and how to configure it.
4095
4096 @section Target List
4097 @cindex target, current
4098 @cindex target, list
4099
4100 All targets that have been set up are part of a list,
4101 where each member has a name.
4102 That name should normally be the same as the TAP name.
4103 You can display the list with the @command{targets}
4104 (plural!) command.
4105 This display often has only one CPU; here's what it might
4106 look like with more than one:
4107 @verbatim
4108 TargetName Type Endian TapName State
4109 -- ------------------ ---------- ------ ------------------ ------------
4110 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4111 1 MyTarget cortex_m little mychip.foo tap-disabled
4112 @end verbatim
4113
4114 One member of that list is the @dfn{current target}, which
4115 is implicitly referenced by many commands.
4116 It's the one marked with a @code{*} near the target name.
4117 In particular, memory addresses often refer to the address
4118 space seen by that current target.
4119 Commands like @command{mdw} (memory display words)
4120 and @command{flash erase_address} (erase NOR flash blocks)
4121 are examples; and there are many more.
4122
4123 Several commands let you examine the list of targets:
4124
4125 @deffn Command {target count}
4126 @emph{Note: target numbers are deprecated; don't use them.
4127 They will be removed shortly after August 2010, including this command.
4128 Iterate target using @command{target names}, not by counting.}
4129
4130 Returns the number of targets, @math{N}.
4131 The highest numbered target is @math{N - 1}.
4132 @example
4133 set c [target count]
4134 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
4135 # Assuming you have created this function
4136 print_target_details $x
4137 @}
4138 @end example
4139 @end deffn
4140
4141 @deffn Command {target current}
4142 Returns the name of the current target.
4143 @end deffn
4144
4145 @deffn Command {target names}
4146 Lists the names of all current targets in the list.
4147 @example
4148 foreach t [target names] @{
4149 puts [format "Target: %s\n" $t]
4150 @}
4151 @end example
4152 @end deffn
4153
4154 @deffn Command {target number} number
4155 @emph{Note: target numbers are deprecated; don't use them.
4156 They will be removed shortly after August 2010, including this command.}
4157
4158 The list of targets is numbered starting at zero.
4159 This command returns the name of the target at index @var{number}.
4160 @example
4161 set thename [target number $x]
4162 puts [format "Target %d is: %s\n" $x $thename]
4163 @end example
4164 @end deffn
4165
4166 @c yep, "target list" would have been better.
4167 @c plus maybe "target setdefault".
4168
4169 @deffn Command targets [name]
4170 @emph{Note: the name of this command is plural. Other target
4171 command names are singular.}
4172
4173 With no parameter, this command displays a table of all known
4174 targets in a user friendly form.
4175
4176 With a parameter, this command sets the current target to
4177 the given target with the given @var{name}; this is
4178 only relevant on boards which have more than one target.
4179 @end deffn
4180
4181 @section Target CPU Types
4182 @cindex target type
4183 @cindex CPU type
4184
4185 Each target has a @dfn{CPU type}, as shown in the output of
4186 the @command{targets} command. You need to specify that type
4187 when calling @command{target create}.
4188 The CPU type indicates more than just the instruction set.
4189 It also indicates how that instruction set is implemented,
4190 what kind of debug support it integrates,
4191 whether it has an MMU (and if so, what kind),
4192 what core-specific commands may be available
4193 (@pxref{Architecture and Core Commands}),
4194 and more.
4195
4196 It's easy to see what target types are supported,
4197 since there's a command to list them.
4198
4199 @anchor{targettypes}
4200 @deffn Command {target types}
4201 Lists all supported target types.
4202 At this writing, the supported CPU types are:
4203
4204 @itemize @bullet
4205 @item @code{arm11} -- this is a generation of ARMv6 cores
4206 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4207 @item @code{arm7tdmi} -- this is an ARMv4 core
4208 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4209 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4210 @item @code{arm966e} -- this is an ARMv5 core
4211 @item @code{arm9tdmi} -- this is an ARMv4 core
4212 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4213 (Support for this is preliminary and incomplete.)
4214 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4215 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4216 compact Thumb2 instruction set.
4217 @item @code{dragonite} -- resembles arm966e
4218 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4219 (Support for this is still incomplete.)
4220 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4221 @item @code{feroceon} -- resembles arm926
4222 @item @code{mips_m4k} -- a MIPS core
4223 @item @code{xscale} -- this is actually an architecture,
4224 not a CPU type. It is based on the ARMv5 architecture.
4225 @item @code{openrisc} -- this is an OpenRISC 1000 core.
4226 The current implementation supports three JTAG TAP cores:
4227 @itemize @minus
4228 @item @code{OpenCores TAP} (See: @emph{http://opencores.org/project,jtag})
4229 @item @code{Altera Virtual JTAG TAP} (See: @emph{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4230 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @emph{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4231 @end itemize
4232 And two debug interfaces cores:
4233 @itemize @minus
4234 @item @code{Advanced debug interface} (See: @emph{http://opencores.org/project,adv_debug_sys})
4235 @item @code{SoC Debug Interface} (See: @emph{http://opencores.org/project,dbg_interface})
4236 @end itemize
4237 @end itemize
4238 @end deffn
4239
4240 To avoid being confused by the variety of ARM based cores, remember
4241 this key point: @emph{ARM is a technology licencing company}.
4242 (See: @url{http://www.arm.com}.)
4243 The CPU name used by OpenOCD will reflect the CPU design that was
4244 licenced, not a vendor brand which incorporates that design.
4245 Name prefixes like arm7, arm9, arm11, and cortex
4246 reflect design generations;
4247 while names like ARMv4, ARMv5, ARMv6, and ARMv7
4248 reflect an architecture version implemented by a CPU design.
4249
4250 @anchor{targetconfiguration}
4251 @section Target Configuration
4252
4253 Before creating a ``target'', you must have added its TAP to the scan chain.
4254 When you've added that TAP, you will have a @code{dotted.name}
4255 which is used to set up the CPU support.
4256 The chip-specific configuration file will normally configure its CPU(s)
4257 right after it adds all of the chip's TAPs to the scan chain.
4258
4259 Although you can set up a target in one step, it's often clearer if you
4260 use shorter commands and do it in two steps: create it, then configure
4261 optional parts.
4262 All operations on the target after it's created will use a new
4263 command, created as part of target creation.
4264
4265 The two main things to configure after target creation are
4266 a work area, which usually has target-specific defaults even
4267 if the board setup code overrides them later;
4268 and event handlers (@pxref{targetevents,,Target Events}), which tend
4269 to be much more board-specific.
4270 The key steps you use might look something like this
4271
4272 @example
4273 target create MyTarget cortex_m -chain-position mychip.cpu
4274 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4275 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4276 $MyTarget configure -event reset-init @{ myboard_reinit @}
4277 @end example
4278
4279 You should specify a working area if you can; typically it uses some
4280 on-chip SRAM.
4281 Such a working area can speed up many things, including bulk
4282 writes to target memory;
4283 flash operations like checking to see if memory needs to be erased;
4284 GDB memory checksumming;
4285 and more.
4286
4287 @quotation Warning
4288 On more complex chips, the work area can become
4289 inaccessible when application code
4290 (such as an operating system)
4291 enables or disables the MMU.
4292 For example, the particular MMU context used to acess the virtual
4293 address will probably matter ... and that context might not have
4294 easy access to other addresses needed.
4295 At this writing, OpenOCD doesn't have much MMU intelligence.
4296 @end quotation
4297
4298 It's often very useful to define a @code{reset-init} event handler.
4299 For systems that are normally used with a boot loader,
4300 common tasks include updating clocks and initializing memory
4301 controllers.
4302 That may be needed to let you write the boot loader into flash,
4303 in order to ``de-brick'' your board; or to load programs into
4304 external DDR memory without having run the boot loader.
4305
4306 @deffn Command {target create} target_name type configparams...
4307 This command creates a GDB debug target that refers to a specific JTAG tap.
4308 It enters that target into a list, and creates a new
4309 command (@command{@var{target_name}}) which is used for various
4310 purposes including additional configuration.
4311
4312 @itemize @bullet
4313 @item @var{target_name} ... is the name of the debug target.
4314 By convention this should be the same as the @emph{dotted.name}
4315 of the TAP associated with this target, which must be specified here
4316 using the @code{-chain-position @var{dotted.name}} configparam.
4317
4318 This name is also used to create the target object command,
4319 referred to here as @command{$target_name},
4320 and in other places the target needs to be identified.
4321 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4322 @item @var{configparams} ... all parameters accepted by
4323 @command{$target_name configure} are permitted.
4324 If the target is big-endian, set it here with @code{-endian big}.
4325
4326 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
4327 @end itemize
4328 @end deffn
4329
4330 @deffn Command {$target_name configure} configparams...
4331 The options accepted by this command may also be
4332 specified as parameters to @command{target create}.
4333 Their values can later be queried one at a time by
4334 using the @command{$target_name cget} command.
4335
4336 @emph{Warning:} changing some of these after setup is dangerous.
4337 For example, moving a target from one TAP to another;
4338 and changing its endianness.
4339
4340 @itemize @bullet
4341
4342 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4343 used to access this target.
4344
4345 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4346 whether the CPU uses big or little endian conventions
4347
4348 @item @code{-event} @var{event_name} @var{event_body} --
4349 @xref{targetevents,,Target Events}.
4350 Note that this updates a list of named event handlers.
4351 Calling this twice with two different event names assigns
4352 two different handlers, but calling it twice with the
4353 same event name assigns only one handler.
4354
4355 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4356 whether the work area gets backed up; by default,
4357 @emph{it is not backed up.}
4358 When possible, use a working_area that doesn't need to be backed up,
4359 since performing a backup slows down operations.
4360 For example, the beginning of an SRAM block is likely to
4361 be used by most build systems, but the end is often unused.
4362
4363 @item @code{-work-area-size} @var{size} -- specify work are size,
4364 in bytes. The same size applies regardless of whether its physical
4365 or virtual address is being used.
4366
4367 @item @code{-work-area-phys} @var{address} -- set the work area
4368 base @var{address} to be used when no MMU is active.
4369
4370 @item @code{-work-area-virt} @var{address} -- set the work area
4371 base @var{address} to be used when an MMU is active.
4372 @emph{Do not specify a value for this except on targets with an MMU.}
4373 The value should normally correspond to a static mapping for the
4374 @code{-work-area-phys} address, set up by the current operating system.
4375
4376 @anchor{rtostype}
4377 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4378 @var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}|
4379 @option{FreeRTOS}|@option{linux}|@option{ChibiOS}|@option{embKernel}
4380 @xref{gdbrtossupport,,RTOS Support}.
4381
4382 @end itemize
4383 @end deffn
4384
4385 @section Other $target_name Commands
4386 @cindex object command
4387
4388 The Tcl/Tk language has the concept of object commands,
4389 and OpenOCD adopts that same model for targets.
4390
4391 A good Tk example is a on screen button.
4392 Once a button is created a button
4393 has a name (a path in Tk terms) and that name is useable as a first
4394 class command. For example in Tk, one can create a button and later
4395 configure it like this:
4396
4397 @example
4398 # Create
4399 button .foobar -background red -command @{ foo @}
4400 # Modify
4401 .foobar configure -foreground blue
4402 # Query
4403 set x [.foobar cget -background]
4404 # Report
4405 puts [format "The button is %s" $x]
4406 @end example
4407
4408 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4409 button, and its object commands are invoked the same way.
4410
4411 @example
4412 str912.cpu mww 0x1234 0x42
4413 omap3530.cpu mww 0x5555 123
4414 @end example
4415
4416 The commands supported by OpenOCD target objects are:
4417
4418 @deffn Command {$target_name arp_examine}
4419 @deffnx Command {$target_name arp_halt}
4420 @deffnx Command {$target_name arp_poll}
4421 @deffnx Command {$target_name arp_reset}
4422 @deffnx Command {$target_name arp_waitstate}
4423 Internal OpenOCD scripts (most notably @file{startup.tcl})
4424 use these to deal with specific reset cases.
4425 They are not otherwise documented here.
4426 @end deffn
4427
4428 @deffn Command {$target_name array2mem} arrayname width address count
4429 @deffnx Command {$target_name mem2array} arrayname width address count
4430 These provide an efficient script-oriented interface to memory.
4431 The @code{array2mem} primitive writes bytes, halfwords, or words;
4432 while @code{mem2array} reads them.
4433 In both cases, the TCL side uses an array, and
4434 the target side uses raw memory.
4435
4436 The efficiency comes from enabling the use of
4437 bulk JTAG data transfer operations.
4438 The script orientation comes from working with data
4439 values that are packaged for use by TCL scripts;
4440 @command{mdw} type primitives only print data they retrieve,
4441 and neither store nor return those values.
4442
4443 @itemize
4444 @item @var{arrayname} ... is the name of an array variable
4445 @item @var{width} ... is 8/16/32 - indicating the memory access size
4446 @item @var{address} ... is the target memory address
4447 @item @var{count} ... is the number of elements to process
4448 @end itemize
4449 @end deffn
4450
4451 @deffn Command {$target_name cget} queryparm
4452 Each configuration parameter accepted by
4453 @command{$target_name configure}
4454 can be individually queried, to return its current value.
4455 The @var{queryparm} is a parameter name
4456 accepted by that command, such as @code{-work-area-phys}.
4457 There are a few special cases:
4458
4459 @itemize @bullet
4460 @item @code{-event} @var{event_name} -- returns the handler for the
4461 event named @var{event_name}.
4462 This is a special case because setting a handler requires
4463 two parameters.
4464 @item @code{-type} -- returns the target type.
4465 This is a special case because this is set using
4466 @command{target create} and can't be changed
4467 using @command{$target_name configure}.
4468 @end itemize
4469
4470 For example, if you wanted to summarize information about
4471 all the targets you might use something like this:
4472
4473 @example
4474 foreach name [target names] @{
4475 set y [$name cget -endian]
4476 set z [$name cget -type]
4477 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4478 $x $name $y $z]
4479 @}
4480 @end example
4481 @end deffn
4482
4483 @anchor{targetcurstate}
4484 @deffn Command {$target_name curstate}
4485 Displays the current target state:
4486 @code{debug-running},
4487 @code{halted},
4488 @code{reset},
4489 @code{running}, or @code{unknown}.
4490 (Also, @pxref{eventpolling,,Event Polling}.)
4491 @end deffn
4492
4493 @deffn Command {$target_name eventlist}
4494 Displays a table listing all event handlers
4495 currently associated with this target.
4496 @xref{targetevents,,Target Events}.
4497 @end deffn
4498
4499 @deffn Command {$target_name invoke-event} event_name
4500 Invokes the handler for the event named @var{event_name}.
4501 (This is primarily intended for use by OpenOCD framework
4502 code, for example by the reset code in @file{startup.tcl}.)
4503 @end deffn
4504
4505 @deffn Command {$target_name mdw} addr [count]
4506 @deffnx Command {$target_name mdh} addr [count]
4507 @deffnx Command {$target_name mdb} addr [count]
4508 Display contents of address @var{addr}, as
4509 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4510 or 8-bit bytes (@command{mdb}).
4511 If @var{count} is specified, displays that many units.
4512 (If you want to manipulate the data instead of displaying it,
4513 see the @code{mem2array} primitives.)
4514 @end deffn
4515
4516 @deffn Command {$target_name mww} addr word
4517 @deffnx Command {$target_name mwh} addr halfword
4518 @deffnx Command {$target_name mwb} addr byte
4519 Writes the specified @var{word} (32 bits),
4520 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4521 at the specified address @var{addr}.
4522 @end deffn
4523
4524 @anchor{targetevents}
4525 @section Target Events
4526 @cindex target events
4527 @cindex events
4528 At various times, certain things can happen, or you want them to happen.
4529 For example:
4530 @itemize @bullet
4531 @item What should happen when GDB connects? Should your target reset?
4532 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4533 @item Is using SRST appropriate (and possible) on your system?
4534 Or instead of that, do you need to issue JTAG commands to trigger reset?
4535 SRST usually resets everything on the scan chain, which can be inappropriate.
4536 @item During reset, do you need to write to certain memory locations
4537 to set up system clocks or
4538 to reconfigure the SDRAM?
4539 How about configuring the watchdog timer, or other peripherals,
4540 to stop running while you hold the core stopped for debugging?
4541 @end itemize
4542
4543 All of the above items can be addressed by target event handlers.
4544 These are set up by @command{$target_name configure -event} or
4545 @command{target create ... -event}.
4546
4547 The programmer's model matches the @code{-command} option used in Tcl/Tk
4548 buttons and events. The two examples below act the same, but one creates
4549 and invokes a small procedure while the other inlines it.
4550
4551 @example
4552 proc my_attach_proc @{ @} @{
4553 echo "Reset..."
4554 reset halt
4555 @}
4556 mychip.cpu configure -event gdb-attach my_attach_proc
4557 mychip.cpu configure -event gdb-attach @{
4558 echo "Reset..."
4559 # To make flash probe and gdb load to flash work we need a reset init.
4560 reset init
4561 @}
4562 @end example
4563
4564 The following target events are defined:
4565
4566 @itemize @bullet
4567 @item @b{debug-halted}
4568 @* The target has halted for debug reasons (i.e.: breakpoint)
4569 @item @b{debug-resumed}
4570 @* The target has resumed (i.e.: gdb said run)
4571 @item @b{early-halted}
4572 @* Occurs early in the halt process
4573 @item @b{examine-start}
4574 @* Before target examine is called.
4575 @item @b{examine-end}
4576 @* After target examine is called with no errors.
4577 @item @b{gdb-attach}
4578 @* When GDB connects. This is before any communication with the target, so this
4579 can be used to set up the target so it is possible to probe flash. Probing flash
4580 is necessary during gdb connect if gdb load is to write the image to flash. Another
4581 use of the flash memory map is for GDB to automatically hardware/software breakpoints
4582 depending on whether the breakpoint is in RAM or read only memory.
4583 @item @b{gdb-detach}
4584 @* When GDB disconnects
4585 @item @b{gdb-end}
4586 @* When the target has halted and GDB is not doing anything (see early halt)
4587 @item @b{gdb-flash-erase-start}
4588 @* Before the GDB flash process tries to erase the flash (default is
4589 @code{reset init})
4590 @item @b{gdb-flash-erase-end}
4591 @* After the GDB flash process has finished erasing the flash
4592 @item @b{gdb-flash-write-start}
4593 @* Before GDB writes to the flash
4594 @item @b{gdb-flash-write-end}
4595 @* After GDB writes to the flash (default is @code{reset halt})
4596 @item @b{gdb-start}
4597 @* Before the target steps, gdb is trying to start/resume the target
4598 @item @b{halted}
4599 @* The target has halted
4600 @item @b{reset-assert-pre}
4601 @* Issued as part of @command{reset} processing
4602 after @command{reset_init} was triggered
4603 but before either SRST alone is re-asserted on the scan chain,
4604 or @code{reset-assert} is triggered.
4605 @item @b{reset-assert}
4606 @* Issued as part of @command{reset} processing
4607 after @command{reset-assert-pre} was triggered.
4608 When such a handler is present, cores which support this event will use
4609 it instead of asserting SRST.
4610 This support is essential for debugging with JTAG interfaces which
4611 don't include an SRST line (JTAG doesn't require SRST), and for
4612 selective reset on scan chains that have multiple targets.
4613 @item @b{reset-assert-post}
4614 @* Issued as part of @command{reset} processing
4615 after @code{reset-assert} has been triggered.
4616 or the target asserted SRST on the entire scan chain.
4617 @item @b{reset-deassert-pre}
4618 @* Issued as part of @command{reset} processing
4619 after @code{reset-assert-post} has been triggered.
4620 @item @b{reset-deassert-post}
4621 @* Issued as part of @command{reset} processing
4622 after @code{reset-deassert-pre} has been triggered
4623 and (if the target is using it) after SRST has been
4624 released on the scan chain.
4625 @item @b{reset-end}
4626 @* Issued as the final step in @command{reset} processing.
4627 @ignore
4628 @item @b{reset-halt-post}
4629 @* Currently not used
4630 @item @b{reset-halt-pre}
4631 @* Currently not used
4632 @end ignore
4633 @item @b{reset-init}
4634 @* Used by @b{reset init} command for board-specific initialization.
4635 This event fires after @emph{reset-deassert-post}.
4636
4637 This is where you would configure PLLs and clocking, set up DRAM so
4638 you can download programs that don't fit in on-chip SRAM, set up pin
4639 multiplexing, and so on.
4640 (You may be able to switch to a fast JTAG clock rate here, after
4641 the target clocks are fully set up.)
4642 @item @b{reset-start}
4643 @* Issued as part of @command{reset} processing
4644 before @command{reset_init} is called.
4645
4646 This is the most robust place to use @command{jtag_rclk}
4647 or @command{adapter_khz} to switch to a low JTAG clock rate,
4648 when reset disables PLLs needed to use a fast clock.
4649 @ignore
4650 @item @b{reset-wait-pos}
4651 @* Currently not used
4652 @item @b{reset-wait-pre}
4653 @* Currently not used
4654 @end ignore
4655 @item @b{resume-start}
4656 @* Before any target is resumed
4657 @item @b{resume-end}
4658 @* After all targets have resumed
4659 @item @b{resumed}
4660 @* Target has resumed
4661 @end itemize
4662
4663 @node Flash Commands
4664 @chapter Flash Commands
4665
4666 OpenOCD has different commands for NOR and NAND flash;
4667 the ``flash'' command works with NOR flash, while
4668 the ``nand'' command works with NAND flash.
4669 This partially reflects different hardware technologies:
4670 NOR flash usually supports direct CPU instruction and data bus access,
4671 while data from a NAND flash must be copied to memory before it can be
4672 used. (SPI flash must also be copied to memory before use.)
4673 However, the documentation also uses ``flash'' as a generic term;
4674 for example, ``Put flash configuration in board-specific files''.
4675
4676 Flash Steps:
4677 @enumerate
4678 @item Configure via the command @command{flash bank}
4679 @* Do this in a board-specific configuration file,
4680 passing parameters as needed by the driver.
4681 @item Operate on the flash via @command{flash subcommand}
4682 @* Often commands to manipulate the flash are typed by a human, or run
4683 via a script in some automated way. Common tasks include writing a
4684 boot loader, operating system, or other data.
4685 @item GDB Flashing
4686 @* Flashing via GDB requires the flash be configured via ``flash
4687 bank'', and the GDB flash features be enabled.
4688 @xref{gdbconfiguration,,GDB Configuration}.
4689 @end enumerate
4690
4691 Many CPUs have the ablity to ``boot'' from the first flash bank.
4692 This means that misprogramming that bank can ``brick'' a system,
4693 so that it can't boot.
4694 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4695 board by (re)installing working boot firmware.
4696
4697 @anchor{norconfiguration}
4698 @section Flash Configuration Commands
4699 @cindex flash configuration
4700
4701 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4702 Configures a flash bank which provides persistent storage
4703 for addresses from @math{base} to @math{base + size - 1}.
4704 These banks will often be visible to GDB through the target's memory map.
4705 In some cases, configuring a flash bank will activate extra commands;
4706 see the driver-specific documentation.
4707
4708 @itemize @bullet
4709 @item @var{name} ... may be used to reference the flash bank
4710 in other flash commands. A number is also available.
4711 @item @var{driver} ... identifies the controller driver
4712 associated with the flash bank being declared.
4713 This is usually @code{cfi} for external flash, or else
4714 the name of a microcontroller with embedded flash memory.
4715 @xref{flashdriverlist,,Flash Driver List}.
4716 @item @var{base} ... Base address of the flash chip.
4717 @item @var{size} ... Size of the chip, in bytes.
4718 For some drivers, this value is detected from the hardware.
4719 @item @var{chip_width} ... Width of the flash chip, in bytes;
4720 ignored for most microcontroller drivers.
4721 @item @var{bus_width} ... Width of the data bus used to access the
4722 chip, in bytes; ignored for most microcontroller drivers.
4723 @item @var{target} ... Names the target used to issue
4724 commands to the flash controller.
4725 @comment Actually, it's currently a controller-specific parameter...
4726 @item @var{driver_options} ... drivers may support, or require,
4727 additional parameters. See the driver-specific documentation
4728 for more information.
4729 @end itemize
4730 @quotation Note
4731 This command is not available after OpenOCD initialization has completed.
4732 Use it in board specific configuration files, not interactively.
4733 @end quotation
4734 @end deffn
4735
4736 @comment the REAL name for this command is "ocd_flash_banks"
4737 @comment less confusing would be: "flash list" (like "nand list")
4738 @deffn Command {flash banks}
4739 Prints a one-line summary of each device that was
4740 declared using @command{flash bank}, numbered from zero.
4741 Note that this is the @emph{plural} form;
4742 the @emph{singular} form is a very different command.
4743 @end deffn
4744
4745 @deffn Command {flash list}
4746 Retrieves a list of associative arrays for each device that was
4747 declared using @command{flash bank}, numbered from zero.
4748 This returned list can be manipulated easily from within scripts.
4749 @end deffn
4750
4751 @deffn Command {flash probe} num
4752 Identify the flash, or validate the parameters of the configured flash. Operation
4753 depends on the flash type.
4754 The @var{num} parameter is a value shown by @command{flash banks}.
4755 Most flash commands will implicitly @emph{autoprobe} the bank;
4756 flash drivers can distinguish between probing and autoprobing,
4757 but most don't bother.
4758 @end deffn
4759
4760 @section Erasing, Reading, Writing to Flash
4761 @cindex flash erasing
4762 @cindex flash reading
4763 @cindex flash writing
4764 @cindex flash programming
4765 @anchor{flashprogrammingcommands}
4766
4767 One feature distinguishing NOR flash from NAND or serial flash technologies
4768 is that for read access, it acts exactly like any other addressible memory.
4769 This means you can use normal memory read commands like @command{mdw} or
4770 @command{dump_image} with it, with no special @command{flash} subcommands.
4771 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
4772
4773 Write access works differently. Flash memory normally needs to be erased
4774 before it's written. Erasing a sector turns all of its bits to ones, and
4775 writing can turn ones into zeroes. This is why there are special commands
4776 for interactive erasing and writing, and why GDB needs to know which parts
4777 of the address space hold NOR flash memory.
4778
4779 @quotation Note
4780 Most of these erase and write commands leverage the fact that NOR flash
4781 chips consume target address space. They implicitly refer to the current
4782 JTAG target, and map from an address in that target's address space
4783 back to a flash bank.
4784 @comment In May 2009, those mappings may fail if any bank associated
4785 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
4786 A few commands use abstract addressing based on bank and sector numbers,
4787 and don't depend on searching the current target and its address space.
4788 Avoid confusing the two command models.
4789 @end quotation
4790
4791 Some flash chips implement software protection against accidental writes,
4792 since such buggy writes could in some cases ``brick'' a system.
4793 For such systems, erasing and writing may require sector protection to be
4794 disabled first.
4795 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4796 and AT91SAM7 on-chip flash.
4797 @xref{flashprotect,,flash protect}.
4798
4799 @deffn Command {flash erase_sector} num first last
4800 Erase sectors in bank @var{num}, starting at sector @var{first}
4801 up to and including @var{last}.
4802 Sector numbering starts at 0.
4803 Providing a @var{last} sector of @option{last}
4804 specifies "to the end of the flash bank".
4805 The @var{num} parameter is a value shown by @command{flash banks}.
4806 @end deffn
4807
4808 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4809 Erase sectors starting at @var{address} for @var{length} bytes.
4810 Unless @option{pad} is specified, @math{address} must begin a
4811 flash sector, and @math{address + length - 1} must end a sector.
4812 Specifying @option{pad} erases extra data at the beginning and/or
4813 end of the specified region, as needed to erase only full sectors.
4814 The flash bank to use is inferred from the @var{address}, and
4815 the specified length must stay within that bank.
4816 As a special case, when @var{length} is zero and @var{address} is
4817 the start of the bank, the whole flash is erased.
4818 If @option{unlock} is specified, then the flash is unprotected
4819 before erase starts.
4820 @end deffn
4821
4822 @deffn Command {flash fillw} address word length
4823 @deffnx Command {flash fillh} address halfword length
4824 @deffnx Command {flash fillb} address byte length
4825 Fills flash memory with the specified @var{word} (32 bits),
4826 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4827 starting at @var{address} and continuing
4828 for @var{length} units (word/halfword/byte).
4829 No erasure is done before writing; when needed, that must be done
4830 before issuing this command.
4831 Writes are done in blocks of up to 1024 bytes, and each write is
4832 verified by reading back the data and comparing it to what was written.
4833 The flash bank to use is inferred from the @var{address} of
4834 each block, and the specified length must stay within that bank.
4835 @end deffn
4836 @comment no current checks for errors if fill blocks touch multiple banks!
4837
4838 @deffn Command {flash write_bank} num filename offset
4839 Write the binary @file{filename} to flash bank @var{num},
4840 starting at @var{offset} bytes from the beginning of the bank.
4841 The @var{num} parameter is a value shown by @command{flash banks}.
4842 @end deffn
4843
4844 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4845 Write the image @file{filename} to the current target's flash bank(s).
4846 Only loadable sections from the image are written.
4847 A relocation @var{offset} may be specified, in which case it is added
4848 to the base address for each section in the image.
4849 The file [@var{type}] can be specified
4850 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4851 @option{elf} (ELF file), @option{s19} (Motorola s19).
4852 @option{mem}, or @option{builder}.
4853 The relevant flash sectors will be erased prior to programming
4854 if the @option{erase} parameter is given. If @option{unlock} is
4855 provided, then the flash banks are unlocked before erase and
4856 program. The flash bank to use is inferred from the address of
4857 each image section.
4858
4859 @quotation Warning
4860 Be careful using the @option{erase} flag when the flash is holding
4861 data you want to preserve.
4862 Portions of the flash outside those described in the image's
4863 sections might be erased with no notice.
4864 @itemize
4865 @item
4866 When a section of the image being written does not fill out all the
4867 sectors it uses, the unwritten parts of those sectors are necessarily
4868 also erased, because sectors can't be partially erased.
4869 @item
4870 Data stored in sector "holes" between image sections are also affected.
4871 For example, "@command{flash write_image erase ...}" of an image with
4872 one byte at the beginning of a flash bank and one byte at the end
4873 erases the entire bank -- not just the two sectors being written.
4874 @end itemize
4875 Also, when flash protection is important, you must re-apply it after
4876 it has been removed by the @option{unlock} flag.
4877 @end quotation
4878
4879 @end deffn
4880
4881 @section Other Flash commands
4882 @cindex flash protection
4883
4884 @deffn Command {flash erase_check} num
4885 Check erase state of sectors in flash bank @var{num},
4886 and display that status.
4887 The @var{num} parameter is a value shown by @command{flash banks}.
4888 @end deffn
4889
4890 @deffn Command {flash info} num
4891 Print info about flash bank @var{num}
4892 The @var{num} parameter is a value shown by @command{flash banks}.
4893 This command will first query the hardware, it does not print cached
4894 and possibly stale information.
4895 @end deffn
4896
4897 @anchor{flashprotect}
4898 @deffn Command {flash protect} num first last (@option{on}|@option{off})
4899 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
4900 in flash bank @var{num}, starting at sector @var{first}
4901 and continuing up to and including @var{last}.
4902 Providing a @var{last} sector of @option{last}
4903 specifies "to the end of the flash bank".
4904 The @var{num} parameter is a value shown by @command{flash banks}.
4905 @end deffn
4906
4907 @deffn Command {flash padded_value} num value
4908 Sets the default value used for padding any image sections, This should
4909 normally match the flash bank erased value. If not specified by this
4910 comamnd or the flash driver then it defaults to 0xff.
4911 @end deffn
4912
4913 @anchor{program}
4914 @deffn Command {program} filename [verify] [reset] [offset]
4915 This is a helper script that simplifies using OpenOCD as a standalone
4916 programmer. The only required parameter is @option{filename}, the others are optional.
4917 @xref{Flash Programming}.
4918 @end deffn
4919
4920 @anchor{flashdriverlist}
4921 @section Flash Driver List
4922 As noted above, the @command{flash bank} command requires a driver name,
4923 and allows driver-specific options and behaviors.
4924 Some drivers also activate driver-specific commands.
4925
4926 @subsection External Flash
4927
4928 @deffn {Flash Driver} cfi
4929 @cindex Common Flash Interface
4930 @cindex CFI
4931 The ``Common Flash Interface'' (CFI) is the main standard for
4932 external NOR flash chips, each of which connects to a
4933 specific external chip select on the CPU.
4934 Frequently the first such chip is used to boot the system.
4935 Your board's @code{reset-init} handler might need to
4936 configure additional chip selects using other commands (like: @command{mww} to
4937 configure a bus and its timings), or
4938 perhaps configure a GPIO pin that controls the ``write protect'' pin
4939 on the flash chip.
4940 The CFI driver can use a target-specific working area to significantly
4941 speed up operation.
4942
4943 The CFI driver can accept the following optional parameters, in any order:
4944
4945 @itemize
4946 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
4947 like AM29LV010 and similar types.
4948 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
4949 @end itemize
4950
4951 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
4952 wide on a sixteen bit bus:
4953
4954 @example
4955 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
4956 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
4957 @end example
4958
4959 To configure one bank of 32 MBytes
4960 built from two sixteen bit (two byte) wide parts wired in parallel
4961 to create a thirty-two bit (four byte) bus with doubled throughput:
4962
4963 @example
4964 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
4965 @end example
4966
4967 @c "cfi part_id" disabled
4968 @end deffn
4969
4970 @deffn {Flash Driver} lpcspifi
4971 @cindex NXP SPI Flash Interface
4972 @cindex SPIFI
4973 @cindex lpcspifi
4974 NXP's LPC43xx and LPC18xx families include a proprietary SPI
4975 Flash Interface (SPIFI) peripheral that can drive and provide
4976 memory mapped access to external SPI flash devices.
4977
4978 The lpcspifi driver initializes this interface and provides
4979 program and erase functionality for these serial flash devices.
4980 Use of this driver @b{requires} a working area of at least 1kB
4981 to be configured on the target device; more than this will
4982 significantly reduce flash programming times.
4983
4984 The setup command only requires the @var{base} parameter. All
4985 other parameters are ignored, and the flash size and layout
4986 are configured by the driver.
4987
4988 @example
4989 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
4990 @end example
4991
4992 @end deffn
4993
4994 @deffn {Flash Driver} stmsmi
4995 @cindex STMicroelectronics Serial Memory Interface
4996 @cindex SMI
4997 @cindex stmsmi
4998 Some devices form STMicroelectronics (e.g. STR75x MCU family,
4999 SPEAr MPU family) include a proprietary
5000 ``Serial Memory Interface'' (SMI) controller able to drive external
5001 SPI flash devices.
5002 Depending on specific device and board configuration, up to 4 external
5003 flash devices can be connected.
5004
5005 SMI makes the flash content directly accessible in the CPU address
5006 space; each external device is mapped in a memory bank.
5007 CPU can directly read data, execute code and boot from SMI banks.
5008 Normal OpenOCD commands like @command{mdw} can be used to display
5009 the flash content.
5010
5011 The setup command only requires the @var{base} parameter in order
5012 to identify the memory bank.
5013 All other parameters are ignored. Additional information, like
5014 flash size, are detected automatically.
5015
5016 @example
5017 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
5018 @end example
5019
5020 @end deffn
5021
5022 @subsection Internal Flash (Microcontrollers)
5023
5024 @deffn {Flash Driver} aduc702x
5025 The ADUC702x analog microcontrollers from Analog Devices
5026 include internal flash and use ARM7TDMI cores.
5027 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
5028 The setup command only requires the @var{target} argument
5029 since all devices in this family have the same memory layout.
5030
5031 @example
5032 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME