1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A
34 copy of the license is included in the section entitled ``GNU Free
35 Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
100 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
101 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
106 @section What is OpenOCD?
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
114 It does so with the assistance of a @dfn{debug adapter}, which is
115 a small hardware module which helps provide the right kind of
116 electrical signaling to the target being debugged. These are
117 required since the debug host (on which OpenOCD runs) won't
118 usually have native support for such signaling, or the connector
119 needed to hook up to the target.
121 Such debug adapters support one or more @dfn{transport} protocols,
122 each of which involves different electrical signaling (and uses
123 different messaging protocols on top of that signaling). There
124 are many types of debug adapter, and little uniformity in what
125 they are called. (There are also product naming differences.)
127 These adapters are sometimes packaged as discrete dongles, which
128 may generically be called @dfn{hardware interface dongles}.
129 Some development boards also integrate them directly, which may
130 let the development board connect directly to the debug
131 host over USB (and sometimes also to power it over USB).
133 For example, a @dfn{JTAG Adapter} supports JTAG
134 signaling, and is used to communicate
135 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
136 A @dfn{TAP} is a ``Test Access Port'', a module which processes
137 special instructions and data. TAPs are daisy-chained within and
138 between chips and boards. JTAG supports debugging and boundary
141 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
142 signaling to communicate with some newer ARM cores, as well as debug
143 adapters which support both JTAG and SWD transports. SWD supports only
144 debugging, whereas JTAG also supports boundary scan operations.
146 For some chips, there are also @dfn{Programming Adapters} supporting
147 special transports used only to write code to flash memory, without
148 support for on-chip debugging or boundary scan.
149 (At this writing, OpenOCD does not support such non-debug adapters.)
152 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
153 USB-based, parallel port-based, and other standalone boxes that run
154 OpenOCD internally. @xref{Debug Adapter Hardware}.
156 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
157 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
158 (Stellaris LM3, STMicroelectronics STM32 and Energy Micro EFM32) and
159 Intel Quark (x10xx) based cores to be debugged via the GDB protocol.
161 @b{Flash Programming:} Flash writing is supported for external
162 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
163 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
164 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
165 controllers (LPC3180, Orion, S3C24xx, more) is included.
167 @section OpenOCD Web Site
169 The OpenOCD web site provides the latest public news from the community:
171 @uref{http://openocd.org/}
173 @section Latest User's Guide:
175 The user's guide you are now reading may not be the latest one
176 available. A version for more recent code may be available.
177 Its HTML form is published regularly at:
179 @uref{http://openocd.org/doc/html/index.html}
181 PDF form is likewise published at:
183 @uref{http://openocd.org/doc/pdf/openocd.pdf}
185 @section OpenOCD User's Forum
187 There is an OpenOCD forum (phpBB) hosted by SparkFun,
188 which might be helpful to you. Note that if you want
189 anything to come to the attention of developers, you
190 should post it to the OpenOCD Developer Mailing List
191 instead of this forum.
193 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
195 @section OpenOCD User's Mailing List
197 The OpenOCD User Mailing List provides the primary means of
198 communication between users:
200 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
204 Support can also be found on irc:
205 @uref{irc://irc.libera.chat/openocd}
208 @chapter OpenOCD Developer Resources
211 If you are interested in improving the state of OpenOCD's debugging and
212 testing support, new contributions will be welcome. Motivated developers
213 can produce new target, flash or interface drivers, improve the
214 documentation, as well as more conventional bug fixes and enhancements.
216 The resources in this chapter are available for developers wishing to explore
217 or expand the OpenOCD source code.
219 @section OpenOCD Git Repository
221 During the 0.3.x release cycle, OpenOCD switched from Subversion to
222 a Git repository hosted at SourceForge. The repository URL is:
224 @uref{git://git.code.sf.net/p/openocd/code}
228 @uref{http://git.code.sf.net/p/openocd/code}
230 You may prefer to use a mirror and the HTTP protocol:
232 @uref{http://repo.or.cz/r/openocd.git}
234 With standard Git tools, use @command{git clone} to initialize
235 a local repository, and @command{git pull} to update it.
236 There are also gitweb pages letting you browse the repository
237 with a web browser, or download arbitrary snapshots without
238 needing a Git client:
240 @uref{http://repo.or.cz/w/openocd.git}
242 The @file{README} file contains the instructions for building the project
243 from the repository or a snapshot.
245 Developers that want to contribute patches to the OpenOCD system are
246 @b{strongly} encouraged to work against mainline.
247 Patches created against older versions may require additional
248 work from their submitter in order to be updated for newer releases.
250 @section Doxygen Developer Manual
252 During the 0.2.x release cycle, the OpenOCD project began
253 providing a Doxygen reference manual. This document contains more
254 technical information about the software internals, development
255 processes, and similar documentation:
257 @uref{http://openocd.org/doc/doxygen/html/index.html}
259 This document is a work-in-progress, but contributions would be welcome
260 to fill in the gaps. All of the source files are provided in-tree,
261 listed in the Doxyfile configuration at the top of the source tree.
263 @section Gerrit Review System
265 All changes in the OpenOCD Git repository go through the web-based Gerrit
268 @uref{https://review.openocd.org/}
270 After a one-time registration and repository setup, anyone can push commits
271 from their local Git repository directly into Gerrit.
272 All users and developers are encouraged to review, test, discuss and vote
273 for changes in Gerrit. The feedback provides the basis for a maintainer to
274 eventually submit the change to the main Git repository.
276 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
277 Developer Manual, contains basic information about how to connect a
278 repository to Gerrit, prepare and push patches. Patch authors are expected to
279 maintain their changes while they're in Gerrit, respond to feedback and if
280 necessary rework and push improved versions of the change.
282 @section OpenOCD Developer Mailing List
284 The OpenOCD Developer Mailing List provides the primary means of
285 communication between developers:
287 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
289 @section OpenOCD Bug Tracker
291 The OpenOCD Bug Tracker is hosted on SourceForge:
293 @uref{http://bugs.openocd.org/}
296 @node Debug Adapter Hardware
297 @chapter Debug Adapter Hardware
305 Defined: @b{dongle}: A small device that plugs into a computer and serves as
306 an adapter .... [snip]
308 In the OpenOCD case, this generally refers to @b{a small adapter} that
309 attaches to your computer via USB or the parallel port.
312 @section Choosing a Dongle
314 There are several things you should keep in mind when choosing a dongle.
317 @item @b{Transport} Does it support the kind of communication that you need?
318 OpenOCD focuses mostly on JTAG. Your version may also support
319 other ways to communicate with target devices.
320 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
321 Does your dongle support it? You might need a level converter.
322 @item @b{Pinout} What pinout does your target board use?
323 Does your dongle support it? You may be able to use jumper
324 wires, or an "octopus" connector, to convert pinouts.
325 @item @b{Connection} Does your computer have the USB, parallel, or
326 Ethernet port needed?
327 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
328 RTCK support (also known as ``adaptive clocking'')?
331 @section USB FT2232 Based
333 There are many USB JTAG dongles on the market, many of them based
334 on a chip from ``Future Technology Devices International'' (FTDI)
335 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
336 See: @url{http://www.ftdichip.com} for more information.
337 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
338 chips started to become available in JTAG adapters. Around 2012, a new
339 variant appeared - FT232H - this is a single-channel version of FT2232H.
340 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
343 The FT2232 chips are flexible enough to support some other
344 transport options, such as SWD or the SPI variants used to
345 program some chips. They have two communications channels,
346 and one can be used for a UART adapter at the same time the
347 other one is used to provide a debug adapter.
349 Also, some development boards integrate an FT2232 chip to serve as
350 a built-in low-cost debug adapter and USB-to-serial solution.
354 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
356 @* See: @url{http://www.amontec.com/jtagkey.shtml}
358 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
360 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
362 @* See: @url{http://www.signalyzer.com}
363 @item @b{Stellaris Eval Boards}
364 @* See: @url{http://www.ti.com} - The Stellaris eval boards
365 bundle FT2232-based JTAG and SWD support, which can be used to debug
366 the Stellaris chips. Using separate JTAG adapters is optional.
367 These boards can also be used in a "pass through" mode as JTAG adapters
368 to other target boards, disabling the Stellaris chip.
369 @item @b{TI/Luminary ICDI}
370 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
371 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
372 Evaluation Kits. Like the non-detachable FT2232 support on the other
373 Stellaris eval boards, they can be used to debug other target boards.
374 @item @b{olimex-jtag}
375 @* See: @url{http://www.olimex.com}
376 @item @b{Flyswatter/Flyswatter2}
377 @* See: @url{http://www.tincantools.com}
378 @item @b{turtelizer2}
380 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
381 @url{http://www.ethernut.de}
383 @* Link: @url{http://www.hitex.com/index.php?id=383}
385 @* Link @url{http://www.hitex.com/stm32-stick}
386 @item @b{axm0432_jtag}
387 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
388 to be available anymore as of April 2012.
390 @* Link @url{http://www.hitex.com/index.php?id=cortino}
391 @item @b{dlp-usb1232h}
392 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
393 @item @b{digilent-hs1}
394 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
396 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
398 @item @b{JTAG-lock-pick Tiny 2}
399 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
402 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
406 @section USB-JTAG / Altera USB-Blaster compatibles
408 These devices also show up as FTDI devices, but are not
409 protocol-compatible with the FT2232 devices. They are, however,
410 protocol-compatible among themselves. USB-JTAG devices typically consist
411 of a FT245 followed by a CPLD that understands a particular protocol,
412 or emulates this protocol using some other hardware.
414 They may appear under different USB VID/PID depending on the particular
415 product. The driver can be configured to search for any VID/PID pair
416 (see the section on driver commands).
419 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
420 @* Link: @url{http://ixo-jtag.sourceforge.net/}
421 @item @b{Altera USB-Blaster}
422 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
425 @section USB J-Link based
426 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
427 an example of a microcontroller based JTAG adapter, it uses an
428 AT91SAM764 internally.
431 @item @b{SEGGER J-Link}
432 @* Link: @url{http://www.segger.com/jlink.html}
433 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
434 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
438 @section USB RLINK based
439 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
440 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
441 SWD and not JTAG, thus not supported.
444 @item @b{Raisonance RLink}
445 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
446 @item @b{STM32 Primer}
447 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
448 @item @b{STM32 Primer2}
449 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
452 @section USB ST-LINK based
453 STMicroelectronics has an adapter called @b{ST-LINK}.
454 They only work with STMicroelectronics chips, notably STM32 and STM8.
458 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
459 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
461 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
462 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
464 @* This is available standalone and as part of some kits.
465 @* Link: @url{http://www.st.com/stlink-v3}
468 For info the original ST-LINK enumerates using the mass storage usb class; however,
469 its implementation is completely broken. The result is this causes issues under Linux.
470 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
472 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
473 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
476 @section USB TI/Stellaris ICDI based
477 Texas Instruments has an adapter called @b{ICDI}.
478 It is not to be confused with the FTDI based adapters that were originally fitted to their
479 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
481 @section USB Nuvoton Nu-Link
482 Nuvoton has an adapter called @b{Nu-Link}.
483 It is available either as stand-alone dongle and embedded on development boards.
484 It supports SWD, serial port bridge and mass storage for firmware update.
485 Both Nu-Link v1 and v2 are supported.
487 @section USB CMSIS-DAP based
488 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
489 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
494 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
496 @item @b{USB - Presto}
497 @* Link: @url{http://tools.asix.net/prg_presto.htm}
499 @item @b{Versaloon-Link}
500 @* Link: @url{http://www.versaloon.com}
502 @item @b{ARM-JTAG-EW}
503 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
506 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
509 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
512 @* Link: @url{http://code.google.com/p/estick-jtag/}
514 @item @b{Keil ULINK v1}
515 @* Link: @url{http://www.keil.com/ulink1/}
517 @item @b{TI XDS110 Debug Probe}
518 @* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds110.html}
519 @* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds_software_package_download.html#xds110-support-utilities}
522 @section IBM PC Parallel Printer Port Based
524 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
525 and the Macraigor Wiggler. There are many clones and variations of
528 Note that parallel ports are becoming much less common, so if you
529 have the choice you should probably avoid these adapters in favor
534 @item @b{Wiggler} - There are many clones of this.
535 @* Link: @url{http://www.macraigor.com/wiggler.htm}
537 @item @b{DLC5} - From XILINX - There are many clones of this
538 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
539 produced, PDF schematics are easily found and it is easy to make.
541 @item @b{Amontec - JTAG Accelerator}
542 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
545 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
547 @item @b{Wiggler_ntrst_inverted}
548 @* Yet another variation - See the source code, src/jtag/parport.c
550 @item @b{old_amt_wiggler}
551 @* Unknown - probably not on the market today
554 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
557 @* Link: @url{http://www.amontec.com/chameleon.shtml}
563 @* ispDownload from Lattice Semiconductor
564 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
567 @* From STMicroelectronics;
568 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
576 @* An EP93xx based Linux machine using the GPIO pins directly.
579 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
581 @item @b{bcm2835gpio}
582 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
585 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
588 @* A JTAG driver acting as a client for the JTAG VPI server interface.
589 @* Link: @url{http://github.com/fjullien/jtag_vpi}
592 @* A driver for Cadence virtual Debug Interface to emulated or simulated targets.
593 It implements a client connecting to the vdebug server, which in turn communicates
594 with the emulated or simulated RTL model through a transactor. The current version
595 supports only JTAG as a transport, but other virtual transports, like DAP are planned.
598 @* A JTAG driver acting as a client for the SystemVerilog Direct Programming
599 Interface (DPI) for JTAG devices. DPI allows OpenOCD to connect to the JTAG
600 interface of a hardware model written in SystemVerilog, for example, on an
601 emulation model of target hardware.
603 @item @b{xlnx_pcie_xvc}
604 @* A JTAG driver exposing Xilinx Virtual Cable over PCI Express to OpenOCD as JTAG/SWD interface.
607 @* A bitbang JTAG driver using Linux GPIO through library libgpiod.
610 @* A bitbang JTAG driver using Linux legacy sysfs GPIO.
611 This is deprecated from Linux v5.3; prefer using @b{linuxgpiod}.
616 @chapter About Jim-Tcl
620 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
621 This programming language provides a simple and extensible
624 All commands presented in this Guide are extensions to Jim-Tcl.
625 You can use them as simple commands, without needing to learn
626 much of anything about Tcl.
627 Alternatively, you can write Tcl programs with them.
629 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
630 There is an active and responsive community, get on the mailing list
631 if you have any questions. Jim-Tcl maintainers also lurk on the
632 OpenOCD mailing list.
635 @item @b{Jim vs. Tcl}
636 @* Jim-Tcl is a stripped down version of the well known Tcl language,
637 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
638 fewer features. Jim-Tcl is several dozens of .C files and .H files and
639 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
640 4.2 MB .zip file containing 1540 files.
642 @item @b{Missing Features}
643 @* Our practice has been: Add/clone the real Tcl feature if/when
644 needed. We welcome Jim-Tcl improvements, not bloat. Also there
645 are a large number of optional Jim-Tcl features that are not
649 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
650 command interpreter today is a mixture of (newer)
651 Jim-Tcl commands, and the (older) original command interpreter.
654 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
655 can type a Tcl for() loop, set variables, etc.
656 Some of the commands documented in this guide are implemented
657 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
659 @item @b{Historical Note}
660 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
661 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
662 as a Git submodule, which greatly simplified upgrading Jim-Tcl
663 to benefit from new features and bugfixes in Jim-Tcl.
665 @item @b{Need a crash course in Tcl?}
666 @*@xref{Tcl Crash Course}.
671 @cindex command line options
673 @cindex directory search
675 Properly installing OpenOCD sets up your operating system to grant it access
676 to the debug adapters. On Linux, this usually involves installing a file
677 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
678 that works for many common adapters is shipped with OpenOCD in the
679 @file{contrib} directory. MS-Windows needs
680 complex and confusing driver configuration for every peripheral. Such issues
681 are unique to each operating system, and are not detailed in this User's Guide.
683 Then later you will invoke the OpenOCD server, with various options to
684 tell it how each debug session should work.
685 The @option{--help} option shows:
689 --help | -h display this help
690 --version | -v display OpenOCD version
691 --file | -f use configuration file <name>
692 --search | -s dir to search for config files and scripts
693 --debug | -d set debug level to 3
694 | -d<n> set debug level to <level>
695 --log_output | -l redirect log output to file <name>
696 --command | -c run <command>
699 If you don't give any @option{-f} or @option{-c} options,
700 OpenOCD tries to read the configuration file @file{openocd.cfg}.
701 To specify one or more different
702 configuration files, use @option{-f} options. For example:
705 openocd -f config1.cfg -f config2.cfg -f config3.cfg
708 Configuration files and scripts are searched for in
710 @item the current directory,
711 @item any search dir specified on the command line using the @option{-s} option,
712 @item any search dir specified using the @command{add_script_search_dir} command,
713 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
714 @item @file{%APPDATA%/OpenOCD} (only on Windows),
715 @item @file{$HOME/Library/Preferences/org.openocd} (only on Darwin),
716 @item @file{$XDG_CONFIG_HOME/openocd} (@env{$XDG_CONFIG_HOME} defaults to @file{$HOME/.config}),
717 @item @file{$HOME/.openocd},
718 @item the site wide script library @file{$pkgdatadir/site} and
719 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
721 The first found file with a matching file name will be used.
724 Don't try to use configuration script names or paths which
725 include the "#" character. That character begins Tcl comments.
728 @section Simple setup, no customization
730 In the best case, you can use two scripts from one of the script
731 libraries, hook up your JTAG adapter, and start the server ... and
732 your JTAG setup will just work "out of the box". Always try to
733 start by reusing those scripts, but assume you'll need more
734 customization even if this works. @xref{OpenOCD Project Setup}.
736 If you find a script for your JTAG adapter, and for your board or
737 target, you may be able to hook up your JTAG adapter then start
738 the server with some variation of one of the following:
741 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
742 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
745 You might also need to configure which reset signals are present,
746 using @option{-c 'reset_config trst_and_srst'} or something similar.
747 If all goes well you'll see output something like
750 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
751 For bug reports, read
752 http://openocd.org/doc/doxygen/bugs.html
753 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
754 (mfg: 0x23b, part: 0xba00, ver: 0x3)
757 Seeing that "tap/device found" message, and no warnings, means
758 the JTAG communication is working. That's a key milestone, but
759 you'll probably need more project-specific setup.
761 @section What OpenOCD does as it starts
763 OpenOCD starts by processing the configuration commands provided
764 on the command line or, if there were no @option{-c command} or
765 @option{-f file.cfg} options given, in @file{openocd.cfg}.
766 @xref{configurationstage,,Configuration Stage}.
767 At the end of the configuration stage it verifies the JTAG scan
768 chain defined using those commands; your configuration should
769 ensure that this always succeeds.
770 Normally, OpenOCD then starts running as a server.
771 Alternatively, commands may be used to terminate the configuration
772 stage early, perform work (such as updating some flash memory),
773 and then shut down without acting as a server.
775 Once OpenOCD starts running as a server, it waits for connections from
776 clients (Telnet, GDB, RPC) and processes the commands issued through
779 If you are having problems, you can enable internal debug messages via
780 the @option{-d} option.
782 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
783 @option{-c} command line switch.
785 To enable debug output (when reporting problems or working on OpenOCD
786 itself), use the @option{-d} command line switch. This sets the
787 @option{debug_level} to "3", outputting the most information,
788 including debug messages. The default setting is "2", outputting only
789 informational messages, warnings and errors. You can also change this
790 setting from within a telnet or gdb session using @command{debug_level<n>}
791 (@pxref{debuglevel,,debug_level}).
793 You can redirect all output from the server to a file using the
794 @option{-l <logfile>} switch.
796 Note! OpenOCD will launch the GDB & telnet server even if it can not
797 establish a connection with the target. In general, it is possible for
798 the JTAG controller to be unresponsive until the target is set up
799 correctly via e.g. GDB monitor commands in a GDB init script.
801 @node OpenOCD Project Setup
802 @chapter OpenOCD Project Setup
804 To use OpenOCD with your development projects, you need to do more than
805 just connect the JTAG adapter hardware (dongle) to your development board
806 and start the OpenOCD server.
807 You also need to configure your OpenOCD server so that it knows
808 about your adapter and board, and helps your work.
809 You may also want to connect OpenOCD to GDB, possibly
810 using Eclipse or some other GUI.
812 @section Hooking up the JTAG Adapter
814 Today's most common case is a dongle with a JTAG cable on one side
815 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
816 and a USB cable on the other.
817 Instead of USB, some dongles use Ethernet;
818 older ones may use a PC parallel port, or even a serial port.
821 @item @emph{Start with power to your target board turned off},
822 and nothing connected to your JTAG adapter.
823 If you're particularly paranoid, unplug power to the board.
824 It's important to have the ground signal properly set up,
825 unless you are using a JTAG adapter which provides
826 galvanic isolation between the target board and the
829 @item @emph{Be sure it's the right kind of JTAG connector.}
830 If your dongle has a 20-pin ARM connector, you need some kind
831 of adapter (or octopus, see below) to hook it up to
832 boards using 14-pin or 10-pin connectors ... or to 20-pin
833 connectors which don't use ARM's pinout.
835 In the same vein, make sure the voltage levels are compatible.
836 Not all JTAG adapters have the level shifters needed to work
837 with 1.2 Volt boards.
839 @item @emph{Be certain the cable is properly oriented} or you might
840 damage your board. In most cases there are only two possible
841 ways to connect the cable.
842 Connect the JTAG cable from your adapter to the board.
843 Be sure it's firmly connected.
845 In the best case, the connector is keyed to physically
846 prevent you from inserting it wrong.
847 This is most often done using a slot on the board's male connector
848 housing, which must match a key on the JTAG cable's female connector.
849 If there's no housing, then you must look carefully and
850 make sure pin 1 on the cable hooks up to pin 1 on the board.
851 Ribbon cables are frequently all grey except for a wire on one
852 edge, which is red. The red wire is pin 1.
854 Sometimes dongles provide cables where one end is an ``octopus'' of
855 color coded single-wire connectors, instead of a connector block.
856 These are great when converting from one JTAG pinout to another,
857 but are tedious to set up.
858 Use these with connector pinout diagrams to help you match up the
859 adapter signals to the right board pins.
861 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
862 A USB, parallel, or serial port connector will go to the host which
863 you are using to run OpenOCD.
864 For Ethernet, consult the documentation and your network administrator.
866 For USB-based JTAG adapters you have an easy sanity check at this point:
867 does the host operating system see the JTAG adapter? If you're running
868 Linux, try the @command{lsusb} command. If that host is an
869 MS-Windows host, you'll need to install a driver before OpenOCD works.
871 @item @emph{Connect the adapter's power supply, if needed.}
872 This step is primarily for non-USB adapters,
873 but sometimes USB adapters need extra power.
875 @item @emph{Power up the target board.}
876 Unless you just let the magic smoke escape,
877 you're now ready to set up the OpenOCD server
878 so you can use JTAG to work with that board.
882 Talk with the OpenOCD server using
883 telnet (@code{telnet localhost 4444} on many systems) or GDB.
884 @xref{GDB and OpenOCD}.
886 @section Project Directory
888 There are many ways you can configure OpenOCD and start it up.
890 A simple way to organize them all involves keeping a
891 single directory for your work with a given board.
892 When you start OpenOCD from that directory,
893 it searches there first for configuration files, scripts,
894 files accessed through semihosting,
895 and for code you upload to the target board.
896 It is also the natural place to write files,
897 such as log files and data you download from the board.
899 @section Configuration Basics
901 There are two basic ways of configuring OpenOCD, and
902 a variety of ways you can mix them.
903 Think of the difference as just being how you start the server:
906 @item Many @option{-f file} or @option{-c command} options on the command line
907 @item No options, but a @dfn{user config file}
908 in the current directory named @file{openocd.cfg}
911 Here is an example @file{openocd.cfg} file for a setup
912 using a Signalyzer FT2232-based JTAG adapter to talk to
913 a board with an Atmel AT91SAM7X256 microcontroller:
916 source [find interface/ftdi/signalyzer.cfg]
918 # GDB can also flash my flash!
919 gdb_memory_map enable
920 gdb_flash_program enable
922 source [find target/sam7x256.cfg]
925 Here is the command line equivalent of that configuration:
928 openocd -f interface/ftdi/signalyzer.cfg \
929 -c "gdb_memory_map enable" \
930 -c "gdb_flash_program enable" \
931 -f target/sam7x256.cfg
934 You could wrap such long command lines in shell scripts,
935 each supporting a different development task.
936 One might re-flash the board with a specific firmware version.
937 Another might set up a particular debugging or run-time environment.
940 At this writing (October 2009) the command line method has
941 problems with how it treats variables.
942 For example, after @option{-c "set VAR value"}, or doing the
943 same in a script, the variable @var{VAR} will have no value
944 that can be tested in a later script.
947 Here we will focus on the simpler solution: one user config
948 file, including basic configuration plus any TCL procedures
949 to simplify your work.
951 @section User Config Files
952 @cindex config file, user
953 @cindex user config file
954 @cindex config file, overview
956 A user configuration file ties together all the parts of a project
958 One of the following will match your situation best:
961 @item Ideally almost everything comes from configuration files
962 provided by someone else.
963 For example, OpenOCD distributes a @file{scripts} directory
964 (probably in @file{/usr/share/openocd/scripts} on Linux).
965 Board and tool vendors can provide these too, as can individual
966 user sites; the @option{-s} command line option lets you say
967 where to find these files. (@xref{Running}.)
968 The AT91SAM7X256 example above works this way.
970 Three main types of non-user configuration file each have their
971 own subdirectory in the @file{scripts} directory:
974 @item @b{interface} -- one for each different debug adapter;
975 @item @b{board} -- one for each different board
976 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
979 Best case: include just two files, and they handle everything else.
980 The first is an interface config file.
981 The second is board-specific, and it sets up the JTAG TAPs and
982 their GDB targets (by deferring to some @file{target.cfg} file),
983 declares all flash memory, and leaves you nothing to do except
987 source [find interface/olimex-jtag-tiny.cfg]
988 source [find board/csb337.cfg]
991 Boards with a single microcontroller often won't need more
992 than the target config file, as in the AT91SAM7X256 example.
993 That's because there is no external memory (flash, DDR RAM), and
994 the board differences are encapsulated by application code.
996 @item Maybe you don't know yet what your board looks like to JTAG.
997 Once you know the @file{interface.cfg} file to use, you may
998 need help from OpenOCD to discover what's on the board.
999 Once you find the JTAG TAPs, you can just search for appropriate
1001 configuration files ... or write your own, from the bottom up.
1002 @xref{autoprobing,,Autoprobing}.
1004 @item You can often reuse some standard config files but
1005 need to write a few new ones, probably a @file{board.cfg} file.
1006 You will be using commands described later in this User's Guide,
1007 and working with the guidelines in the next chapter.
1009 For example, there may be configuration files for your JTAG adapter
1010 and target chip, but you need a new board-specific config file
1011 giving access to your particular flash chips.
1012 Or you might need to write another target chip configuration file
1013 for a new chip built around the Cortex-M3 core.
1016 When you write new configuration files, please submit
1017 them for inclusion in the next OpenOCD release.
1018 For example, a @file{board/newboard.cfg} file will help the
1019 next users of that board, and a @file{target/newcpu.cfg}
1020 will help support users of any board using that chip.
1024 You may need to write some C code.
1025 It may be as simple as supporting a new FT2232 or parport
1026 based adapter; a bit more involved, like a NAND or NOR flash
1027 controller driver; or a big piece of work like supporting
1028 a new chip architecture.
1031 Reuse the existing config files when you can.
1032 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1033 You may find a board configuration that's a good example to follow.
1035 When you write config files, separate the reusable parts
1036 (things every user of that interface, chip, or board needs)
1037 from ones specific to your environment and debugging approach.
1041 For example, a @code{gdb-attach} event handler that invokes
1042 the @command{reset init} command will interfere with debugging
1043 early boot code, which performs some of the same actions
1044 that the @code{reset-init} event handler does.
1047 Likewise, the @command{arm9 vector_catch} command (or
1048 @cindex vector_catch
1049 its siblings @command{xscale vector_catch}
1050 and @command{cortex_m vector_catch}) can be a time-saver
1051 during some debug sessions, but don't make everyone use that either.
1052 Keep those kinds of debugging aids in your user config file,
1053 along with messaging and tracing setup.
1054 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1057 You might need to override some defaults.
1058 For example, you might need to move, shrink, or back up the target's
1059 work area if your application needs much SRAM.
1062 TCP/IP port configuration is another example of something which
1063 is environment-specific, and should only appear in
1064 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1067 @section Project-Specific Utilities
1069 A few project-specific utility
1070 routines may well speed up your work.
1071 Write them, and keep them in your project's user config file.
1073 For example, if you are making a boot loader work on a
1074 board, it's nice to be able to debug the ``after it's
1075 loaded to RAM'' parts separately from the finicky early
1076 code which sets up the DDR RAM controller and clocks.
1077 A script like this one, or a more GDB-aware sibling,
1081 proc ramboot @{ @} @{
1082 # Reset, running the target's "reset-init" scripts
1083 # to initialize clocks and the DDR RAM controller.
1084 # Leave the CPU halted.
1087 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1088 load_image u-boot.bin 0x20000000
1095 Then once that code is working you will need to make it
1096 boot from NOR flash; a different utility would help.
1097 Alternatively, some developers write to flash using GDB.
1098 (You might use a similar script if you're working with a flash
1099 based microcontroller application instead of a boot loader.)
1102 proc newboot @{ @} @{
1103 # Reset, leaving the CPU halted. The "reset-init" event
1104 # proc gives faster access to the CPU and to NOR flash;
1105 # "reset halt" would be slower.
1108 # Write standard version of U-Boot into the first two
1109 # sectors of NOR flash ... the standard version should
1110 # do the same lowlevel init as "reset-init".
1111 flash protect 0 0 1 off
1112 flash erase_sector 0 0 1
1113 flash write_bank 0 u-boot.bin 0x0
1114 flash protect 0 0 1 on
1116 # Reboot from scratch using that new boot loader.
1121 You may need more complicated utility procedures when booting
1123 That often involves an extra bootloader stage,
1124 running from on-chip SRAM to perform DDR RAM setup so it can load
1125 the main bootloader code (which won't fit into that SRAM).
1127 Other helper scripts might be used to write production system images,
1128 involving considerably more than just a three stage bootloader.
1130 @section Target Software Changes
1132 Sometimes you may want to make some small changes to the software
1133 you're developing, to help make JTAG debugging work better.
1134 For example, in C or assembly language code you might
1135 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1136 handling issues like:
1140 @item @b{Watchdog Timers}...
1141 Watchdog timers are typically used to automatically reset systems if
1142 some application task doesn't periodically reset the timer. (The
1143 assumption is that the system has locked up if the task can't run.)
1144 When a JTAG debugger halts the system, that task won't be able to run
1145 and reset the timer ... potentially causing resets in the middle of
1146 your debug sessions.
1148 It's rarely a good idea to disable such watchdogs, since their usage
1149 needs to be debugged just like all other parts of your firmware.
1150 That might however be your only option.
1152 Look instead for chip-specific ways to stop the watchdog from counting
1153 while the system is in a debug halt state. It may be simplest to set
1154 that non-counting mode in your debugger startup scripts. You may however
1155 need a different approach when, for example, a motor could be physically
1156 damaged by firmware remaining inactive in a debug halt state. That might
1157 involve a type of firmware mode where that "non-counting" mode is disabled
1158 at the beginning then re-enabled at the end; a watchdog reset might fire
1159 and complicate the debug session, but hardware (or people) would be
1160 protected.@footnote{Note that many systems support a "monitor mode" debug
1161 that is a somewhat cleaner way to address such issues. You can think of
1162 it as only halting part of the system, maybe just one task,
1163 instead of the whole thing.
1164 At this writing, January 2010, OpenOCD based debugging does not support
1165 monitor mode debug, only "halt mode" debug.}
1167 @item @b{ARM Semihosting}...
1168 @cindex ARM semihosting
1169 When linked with a special runtime library provided with many
1170 toolchains@footnote{See chapter 8 "Semihosting" in
1171 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1172 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1173 The CodeSourcery EABI toolchain also includes a semihosting library.},
1174 your target code can use I/O facilities on the debug host. That library
1175 provides a small set of system calls which are handled by OpenOCD.
1176 It can let the debugger provide your system console and a file system,
1177 helping with early debugging or providing a more capable environment
1178 for sometimes-complex tasks like installing system firmware onto
1181 @item @b{ARM Wait-For-Interrupt}...
1182 Many ARM chips synchronize the JTAG clock using the core clock.
1183 Low power states which stop that core clock thus prevent JTAG access.
1184 Idle loops in tasking environments often enter those low power states
1185 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1187 You may want to @emph{disable that instruction} in source code,
1188 or otherwise prevent using that state,
1189 to ensure you can get JTAG access at any time.@footnote{As a more
1190 polite alternative, some processors have special debug-oriented
1191 registers which can be used to change various features including
1192 how the low power states are clocked while debugging.
1193 The STM32 DBGMCU_CR register is an example; at the cost of extra
1194 power consumption, JTAG can be used during low power states.}
1195 For example, the OpenOCD @command{halt} command may not
1196 work for an idle processor otherwise.
1198 @item @b{Delay after reset}...
1199 Not all chips have good support for debugger access
1200 right after reset; many LPC2xxx chips have issues here.
1201 Similarly, applications that reconfigure pins used for
1202 JTAG access as they start will also block debugger access.
1204 To work with boards like this, @emph{enable a short delay loop}
1205 the first thing after reset, before "real" startup activities.
1206 For example, one second's delay is usually more than enough
1207 time for a JTAG debugger to attach, so that
1208 early code execution can be debugged
1209 or firmware can be replaced.
1211 @item @b{Debug Communications Channel (DCC)}...
1212 Some processors include mechanisms to send messages over JTAG.
1213 Many ARM cores support these, as do some cores from other vendors.
1214 (OpenOCD may be able to use this DCC internally, speeding up some
1215 operations like writing to memory.)
1217 Your application may want to deliver various debugging messages
1218 over JTAG, by @emph{linking with a small library of code}
1219 provided with OpenOCD and using the utilities there to send
1220 various kinds of message.
1221 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1225 @section Target Hardware Setup
1227 Chip vendors often provide software development boards which
1228 are highly configurable, so that they can support all options
1229 that product boards may require. @emph{Make sure that any
1230 jumpers or switches match the system configuration you are
1233 Common issues include:
1237 @item @b{JTAG setup} ...
1238 Boards may support more than one JTAG configuration.
1239 Examples include jumpers controlling pullups versus pulldowns
1240 on the nTRST and/or nSRST signals, and choice of connectors
1241 (e.g. which of two headers on the base board,
1242 or one from a daughtercard).
1243 For some Texas Instruments boards, you may need to jumper the
1244 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1246 @item @b{Boot Modes} ...
1247 Complex chips often support multiple boot modes, controlled
1248 by external jumpers. Make sure this is set up correctly.
1249 For example many i.MX boards from NXP need to be jumpered
1250 to "ATX mode" to start booting using the on-chip ROM, when
1251 using second stage bootloader code stored in a NAND flash chip.
1253 Such explicit configuration is common, and not limited to
1254 booting from NAND. You might also need to set jumpers to
1255 start booting using code loaded from an MMC/SD card; external
1256 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1257 flash; some external host; or various other sources.
1260 @item @b{Memory Addressing} ...
1261 Boards which support multiple boot modes may also have jumpers
1262 to configure memory addressing. One board, for example, jumpers
1263 external chipselect 0 (used for booting) to address either
1264 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1265 or NAND flash. When it's jumpered to address NAND flash, that
1266 board must also be told to start booting from on-chip ROM.
1268 Your @file{board.cfg} file may also need to be told this jumper
1269 configuration, so that it can know whether to declare NOR flash
1270 using @command{flash bank} or instead declare NAND flash with
1271 @command{nand device}; and likewise which probe to perform in
1272 its @code{reset-init} handler.
1274 A closely related issue is bus width. Jumpers might need to
1275 distinguish between 8 bit or 16 bit bus access for the flash
1276 used to start booting.
1278 @item @b{Peripheral Access} ...
1279 Development boards generally provide access to every peripheral
1280 on the chip, sometimes in multiple modes (such as by providing
1281 multiple audio codec chips).
1282 This interacts with software
1283 configuration of pin multiplexing, where for example a
1284 given pin may be routed either to the MMC/SD controller
1285 or the GPIO controller. It also often interacts with
1286 configuration jumpers. One jumper may be used to route
1287 signals to an MMC/SD card slot or an expansion bus (which
1288 might in turn affect booting); others might control which
1289 audio or video codecs are used.
1293 Plus you should of course have @code{reset-init} event handlers
1294 which set up the hardware to match that jumper configuration.
1295 That includes in particular any oscillator or PLL used to clock
1296 the CPU, and any memory controllers needed to access external
1297 memory and peripherals. Without such handlers, you won't be
1298 able to access those resources without working target firmware
1299 which can do that setup ... this can be awkward when you're
1300 trying to debug that target firmware. Even if there's a ROM
1301 bootloader which handles a few issues, it rarely provides full
1302 access to all board-specific capabilities.
1305 @node Config File Guidelines
1306 @chapter Config File Guidelines
1308 This chapter is aimed at any user who needs to write a config file,
1309 including developers and integrators of OpenOCD and any user who
1310 needs to get a new board working smoothly.
1311 It provides guidelines for creating those files.
1313 You should find the following directories under
1314 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1315 them as-is where you can; or as models for new files.
1317 @item @file{interface} ...
1318 These are for debug adapters. Files that specify configuration to use
1319 specific JTAG, SWD and other adapters go here.
1320 @item @file{board} ...
1321 Think Circuit Board, PWA, PCB, they go by many names. Board files
1322 contain initialization items that are specific to a board.
1324 They reuse target configuration files, since the same
1325 microprocessor chips are used on many boards,
1326 but support for external parts varies widely. For
1327 example, the SDRAM initialization sequence for the board, or the type
1328 of external flash and what address it uses. Any initialization
1329 sequence to enable that external flash or SDRAM should be found in the
1330 board file. Boards may also contain multiple targets: two CPUs; or
1332 @item @file{target} ...
1333 Think chip. The ``target'' directory represents the JTAG TAPs
1335 which OpenOCD should control, not a board. Two common types of targets
1336 are ARM chips and FPGA or CPLD chips.
1337 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1338 the target config file defines all of them.
1339 @item @emph{more} ... browse for other library files which may be useful.
1340 For example, there are various generic and CPU-specific utilities.
1343 The @file{openocd.cfg} user config
1344 file may override features in any of the above files by
1345 setting variables before sourcing the target file, or by adding
1346 commands specific to their situation.
1348 @section Interface Config Files
1350 The user config file
1351 should be able to source one of these files with a command like this:
1354 source [find interface/FOOBAR.cfg]
1357 A preconfigured interface file should exist for every debug adapter
1358 in use today with OpenOCD.
1359 That said, perhaps some of these config files
1360 have only been used by the developer who created it.
1362 A separate chapter gives information about how to set these up.
1363 @xref{Debug Adapter Configuration}.
1364 Read the OpenOCD source code (and Developer's Guide)
1365 if you have a new kind of hardware interface
1366 and need to provide a driver for it.
1368 @deffn {Command} {find} 'filename'
1369 Prints full path to @var{filename} according to OpenOCD search rules.
1372 @deffn {Command} {ocd_find} 'filename'
1373 Prints full path to @var{filename} according to OpenOCD search rules. This
1374 is a low level function used by the @command{find}. Usually you want
1375 to use @command{find}, instead.
1378 @section Board Config Files
1379 @cindex config file, board
1380 @cindex board config file
1382 The user config file
1383 should be able to source one of these files with a command like this:
1386 source [find board/FOOBAR.cfg]
1389 The point of a board config file is to package everything
1390 about a given board that user config files need to know.
1391 In summary the board files should contain (if present)
1394 @item One or more @command{source [find target/...cfg]} statements
1395 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1396 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1397 @item Target @code{reset} handlers for SDRAM and I/O configuration
1398 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1399 @item All things that are not ``inside a chip''
1402 Generic things inside target chips belong in target config files,
1403 not board config files. So for example a @code{reset-init} event
1404 handler should know board-specific oscillator and PLL parameters,
1405 which it passes to target-specific utility code.
1407 The most complex task of a board config file is creating such a
1408 @code{reset-init} event handler.
1409 Define those handlers last, after you verify the rest of the board
1410 configuration works.
1412 @subsection Communication Between Config files
1414 In addition to target-specific utility code, another way that
1415 board and target config files communicate is by following a
1416 convention on how to use certain variables.
1418 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1419 Thus the rule we follow in OpenOCD is this: Variables that begin with
1420 a leading underscore are temporary in nature, and can be modified and
1421 used at will within a target configuration file.
1423 Complex board config files can do the things like this,
1424 for a board with three chips:
1427 # Chip #1: PXA270 for network side, big endian
1428 set CHIPNAME network
1430 source [find target/pxa270.cfg]
1431 # on return: _TARGETNAME = network.cpu
1432 # other commands can refer to the "network.cpu" target.
1433 $_TARGETNAME configure .... events for this CPU..
1435 # Chip #2: PXA270 for video side, little endian
1438 source [find target/pxa270.cfg]
1439 # on return: _TARGETNAME = video.cpu
1440 # other commands can refer to the "video.cpu" target.
1441 $_TARGETNAME configure .... events for this CPU..
1443 # Chip #3: Xilinx FPGA for glue logic
1446 source [find target/spartan3.cfg]
1449 That example is oversimplified because it doesn't show any flash memory,
1450 or the @code{reset-init} event handlers to initialize external DRAM
1451 or (assuming it needs it) load a configuration into the FPGA.
1452 Such features are usually needed for low-level work with many boards,
1453 where ``low level'' implies that the board initialization software may
1454 not be working. (That's a common reason to need JTAG tools. Another
1455 is to enable working with microcontroller-based systems, which often
1456 have no debugging support except a JTAG connector.)
1458 Target config files may also export utility functions to board and user
1459 config files. Such functions should use name prefixes, to help avoid
1462 Board files could also accept input variables from user config files.
1463 For example, there might be a @code{J4_JUMPER} setting used to identify
1464 what kind of flash memory a development board is using, or how to set
1465 up other clocks and peripherals.
1467 @subsection Variable Naming Convention
1468 @cindex variable names
1470 Most boards have only one instance of a chip.
1471 However, it should be easy to create a board with more than
1472 one such chip (as shown above).
1473 Accordingly, we encourage these conventions for naming
1474 variables associated with different @file{target.cfg} files,
1475 to promote consistency and
1476 so that board files can override target defaults.
1478 Inputs to target config files include:
1481 @item @code{CHIPNAME} ...
1482 This gives a name to the overall chip, and is used as part of
1483 tap identifier dotted names.
1484 While the default is normally provided by the chip manufacturer,
1485 board files may need to distinguish between instances of a chip.
1486 @item @code{ENDIAN} ...
1487 By default @option{little} - although chips may hard-wire @option{big}.
1488 Chips that can't change endianness don't need to use this variable.
1489 @item @code{CPUTAPID} ...
1490 When OpenOCD examines the JTAG chain, it can be told verify the
1491 chips against the JTAG IDCODE register.
1492 The target file will hold one or more defaults, but sometimes the
1493 chip in a board will use a different ID (perhaps a newer revision).
1496 Outputs from target config files include:
1499 @item @code{_TARGETNAME} ...
1500 By convention, this variable is created by the target configuration
1501 script. The board configuration file may make use of this variable to
1502 configure things like a ``reset init'' script, or other things
1503 specific to that board and that target.
1504 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1505 @code{_TARGETNAME1}, ... etc.
1508 @subsection The reset-init Event Handler
1509 @cindex event, reset-init
1510 @cindex reset-init handler
1512 Board config files run in the OpenOCD configuration stage;
1513 they can't use TAPs or targets, since they haven't been
1515 This means you can't write memory or access chip registers;
1516 you can't even verify that a flash chip is present.
1517 That's done later in event handlers, of which the target @code{reset-init}
1518 handler is one of the most important.
1520 Except on microcontrollers, the basic job of @code{reset-init} event
1521 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1522 Microcontrollers rarely use boot loaders; they run right out of their
1523 on-chip flash and SRAM memory. But they may want to use one of these
1524 handlers too, if just for developer convenience.
1527 Because this is so very board-specific, and chip-specific, no examples
1529 Instead, look at the board config files distributed with OpenOCD.
1530 If you have a boot loader, its source code will help; so will
1531 configuration files for other JTAG tools
1532 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1535 Some of this code could probably be shared between different boards.
1536 For example, setting up a DRAM controller often doesn't differ by
1537 much except the bus width (16 bits or 32?) and memory timings, so a
1538 reusable TCL procedure loaded by the @file{target.cfg} file might take
1539 those as parameters.
1540 Similarly with oscillator, PLL, and clock setup;
1541 and disabling the watchdog.
1542 Structure the code cleanly, and provide comments to help
1543 the next developer doing such work.
1544 (@emph{You might be that next person} trying to reuse init code!)
1546 The last thing normally done in a @code{reset-init} handler is probing
1547 whatever flash memory was configured. For most chips that needs to be
1548 done while the associated target is halted, either because JTAG memory
1549 access uses the CPU or to prevent conflicting CPU access.
1551 @subsection JTAG Clock Rate
1553 Before your @code{reset-init} handler has set up
1554 the PLLs and clocking, you may need to run with
1555 a low JTAG clock rate.
1556 @xref{jtagspeed,,JTAG Speed}.
1557 Then you'd increase that rate after your handler has
1558 made it possible to use the faster JTAG clock.
1559 When the initial low speed is board-specific, for example
1560 because it depends on a board-specific oscillator speed, then
1561 you should probably set it up in the board config file;
1562 if it's target-specific, it belongs in the target config file.
1564 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1565 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1566 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1567 Consult chip documentation to determine the peak JTAG clock rate,
1568 which might be less than that.
1571 On most ARMs, JTAG clock detection is coupled to the core clock, so
1572 software using a @option{wait for interrupt} operation blocks JTAG access.
1573 Adaptive clocking provides a partial workaround, but a more complete
1574 solution just avoids using that instruction with JTAG debuggers.
1577 If both the chip and the board support adaptive clocking,
1578 use the @command{jtag_rclk}
1579 command, in case your board is used with JTAG adapter which
1580 also supports it. Otherwise use @command{adapter speed}.
1581 Set the slow rate at the beginning of the reset sequence,
1582 and the faster rate as soon as the clocks are at full speed.
1584 @anchor{theinitboardprocedure}
1585 @subsection The init_board procedure
1586 @cindex init_board procedure
1588 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1589 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1590 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1591 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1592 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1593 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1594 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1595 Additionally ``linear'' board config file will most likely fail when target config file uses
1596 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1597 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1598 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1599 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1601 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1602 the original), allowing greater code reuse.
1605 ### board_file.cfg ###
1607 # source target file that does most of the config in init_targets
1608 source [find target/target.cfg]
1610 proc enable_fast_clock @{@} @{
1611 # enables fast on-board clock source
1612 # configures the chip to use it
1615 # initialize only board specifics - reset, clock, adapter frequency
1616 proc init_board @{@} @{
1617 reset_config trst_and_srst trst_pulls_srst
1619 $_TARGETNAME configure -event reset-start @{
1623 $_TARGETNAME configure -event reset-init @{
1630 @section Target Config Files
1631 @cindex config file, target
1632 @cindex target config file
1634 Board config files communicate with target config files using
1635 naming conventions as described above, and may source one or
1636 more target config files like this:
1639 source [find target/FOOBAR.cfg]
1642 The point of a target config file is to package everything
1643 about a given chip that board config files need to know.
1644 In summary the target files should contain
1648 @item Add TAPs to the scan chain
1649 @item Add CPU targets (includes GDB support)
1650 @item CPU/Chip/CPU-Core specific features
1654 As a rule of thumb, a target file sets up only one chip.
1655 For a microcontroller, that will often include a single TAP,
1656 which is a CPU needing a GDB target, and its on-chip flash.
1658 More complex chips may include multiple TAPs, and the target
1659 config file may need to define them all before OpenOCD
1660 can talk to the chip.
1661 For example, some phone chips have JTAG scan chains that include
1662 an ARM core for operating system use, a DSP,
1663 another ARM core embedded in an image processing engine,
1664 and other processing engines.
1666 @subsection Default Value Boiler Plate Code
1668 All target configuration files should start with code like this,
1669 letting board config files express environment-specific
1670 differences in how things should be set up.
1673 # Boards may override chip names, perhaps based on role,
1674 # but the default should match what the vendor uses
1675 if @{ [info exists CHIPNAME] @} @{
1676 set _CHIPNAME $CHIPNAME
1678 set _CHIPNAME sam7x256
1681 # ONLY use ENDIAN with targets that can change it.
1682 if @{ [info exists ENDIAN] @} @{
1688 # TAP identifiers may change as chips mature, for example with
1689 # new revision fields (the "3" here). Pick a good default; you
1690 # can pass several such identifiers to the "jtag newtap" command.
1691 if @{ [info exists CPUTAPID ] @} @{
1692 set _CPUTAPID $CPUTAPID
1694 set _CPUTAPID 0x3f0f0f0f
1697 @c but 0x3f0f0f0f is for an str73x part ...
1699 @emph{Remember:} Board config files may include multiple target
1700 config files, or the same target file multiple times
1701 (changing at least @code{CHIPNAME}).
1703 Likewise, the target configuration file should define
1704 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1705 use it later on when defining debug targets:
1708 set _TARGETNAME $_CHIPNAME.cpu
1709 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1712 @subsection Adding TAPs to the Scan Chain
1713 After the ``defaults'' are set up,
1714 add the TAPs on each chip to the JTAG scan chain.
1715 @xref{TAP Declaration}, and the naming convention
1718 In the simplest case the chip has only one TAP,
1719 probably for a CPU or FPGA.
1720 The config file for the Atmel AT91SAM7X256
1721 looks (in part) like this:
1724 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1727 A board with two such at91sam7 chips would be able
1728 to source such a config file twice, with different
1729 values for @code{CHIPNAME}, so
1730 it adds a different TAP each time.
1732 If there are nonzero @option{-expected-id} values,
1733 OpenOCD attempts to verify the actual tap id against those values.
1734 It will issue error messages if there is mismatch, which
1735 can help to pinpoint problems in OpenOCD configurations.
1738 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1739 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1740 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1741 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1742 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1745 There are more complex examples too, with chips that have
1746 multiple TAPs. Ones worth looking at include:
1749 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1750 plus a JRC to enable them
1751 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1752 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1753 is not currently used)
1756 @subsection Add CPU targets
1758 After adding a TAP for a CPU, you should set it up so that
1759 GDB and other commands can use it.
1760 @xref{CPU Configuration}.
1761 For the at91sam7 example above, the command can look like this;
1762 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1763 to little endian, and this chip doesn't support changing that.
1766 set _TARGETNAME $_CHIPNAME.cpu
1767 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1770 Work areas are small RAM areas associated with CPU targets.
1771 They are used by OpenOCD to speed up downloads,
1772 and to download small snippets of code to program flash chips.
1773 If the chip includes a form of ``on-chip-ram'' - and many do - define
1774 a work area if you can.
1775 Again using the at91sam7 as an example, this can look like:
1778 $_TARGETNAME configure -work-area-phys 0x00200000 \
1779 -work-area-size 0x4000 -work-area-backup 0
1782 @anchor{definecputargetsworkinginsmp}
1783 @subsection Define CPU targets working in SMP
1785 After setting targets, you can define a list of targets working in SMP.
1788 set _TARGETNAME_1 $_CHIPNAME.cpu1
1789 set _TARGETNAME_2 $_CHIPNAME.cpu2
1790 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1791 -coreid 0 -dbgbase $_DAP_DBG1
1792 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1793 -coreid 1 -dbgbase $_DAP_DBG2
1794 #define 2 targets working in smp.
1795 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1797 In the above example on cortex_a, 2 cpus are working in SMP.
1798 In SMP only one GDB instance is created and :
1800 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1801 @item halt command triggers the halt of all targets in the list.
1802 @item resume command triggers the write context and the restart of all targets in the list.
1803 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1804 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1805 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1808 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1809 command have been implemented.
1811 @item cortex_a smp on : enable SMP mode, behaviour is as described above.
1812 @item cortex_a smp off : disable SMP mode, the current target is the one
1813 displayed in the GDB session, only this target is now controlled by GDB
1814 session. This behaviour is useful during system boot up.
1815 @item cortex_a smp : display current SMP mode.
1816 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1823 #0 : coreid 0 is displayed to GDB ,
1824 #-> -1 : next resume triggers a real resume
1825 > cortex_a smp_gdb 1
1827 #0 :coreid 0 is displayed to GDB ,
1828 #->1 : next resume displays coreid 1 to GDB
1832 #1 :coreid 1 is displayed to GDB ,
1833 #->1 : next resume displays coreid 1 to GDB
1834 > cortex_a smp_gdb -1
1836 #1 :coreid 1 is displayed to GDB,
1837 #->-1 : next resume triggers a real resume
1841 @subsection Chip Reset Setup
1843 As a rule, you should put the @command{reset_config} command
1844 into the board file. Most things you think you know about a
1845 chip can be tweaked by the board.
1847 Some chips have specific ways the TRST and SRST signals are
1848 managed. In the unusual case that these are @emph{chip specific}
1849 and can never be changed by board wiring, they could go here.
1850 For example, some chips can't support JTAG debugging without
1853 Provide a @code{reset-assert} event handler if you can.
1854 Such a handler uses JTAG operations to reset the target,
1855 letting this target config be used in systems which don't
1856 provide the optional SRST signal, or on systems where you
1857 don't want to reset all targets at once.
1858 Such a handler might write to chip registers to force a reset,
1859 use a JRC to do that (preferable -- the target may be wedged!),
1860 or force a watchdog timer to trigger.
1861 (For Cortex-M targets, this is not necessary. The target
1862 driver knows how to use trigger an NVIC reset when SRST is
1865 Some chips need special attention during reset handling if
1866 they're going to be used with JTAG.
1867 An example might be needing to send some commands right
1868 after the target's TAP has been reset, providing a
1869 @code{reset-deassert-post} event handler that writes a chip
1870 register to report that JTAG debugging is being done.
1871 Another would be reconfiguring the watchdog so that it stops
1872 counting while the core is halted in the debugger.
1874 JTAG clocking constraints often change during reset, and in
1875 some cases target config files (rather than board config files)
1876 are the right places to handle some of those issues.
1877 For example, immediately after reset most chips run using a
1878 slower clock than they will use later.
1879 That means that after reset (and potentially, as OpenOCD
1880 first starts up) they must use a slower JTAG clock rate
1881 than they will use later.
1882 @xref{jtagspeed,,JTAG Speed}.
1884 @quotation Important
1885 When you are debugging code that runs right after chip
1886 reset, getting these issues right is critical.
1887 In particular, if you see intermittent failures when
1888 OpenOCD verifies the scan chain after reset,
1889 look at how you are setting up JTAG clocking.
1892 @anchor{theinittargetsprocedure}
1893 @subsection The init_targets procedure
1894 @cindex init_targets procedure
1896 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1897 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1898 procedure called @code{init_targets}, which will be executed when entering run stage
1899 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1900 Such procedure can be overridden by ``next level'' script (which sources the original).
1901 This concept facilitates code reuse when basic target config files provide generic configuration
1902 procedures and @code{init_targets} procedure, which can then be sourced and enhanced or changed in
1903 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1904 because sourcing them executes every initialization commands they provide.
1907 ### generic_file.cfg ###
1909 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1910 # basic initialization procedure ...
1913 proc init_targets @{@} @{
1914 # initializes generic chip with 4kB of flash and 1kB of RAM
1915 setup_my_chip MY_GENERIC_CHIP 4096 1024
1918 ### specific_file.cfg ###
1920 source [find target/generic_file.cfg]
1922 proc init_targets @{@} @{
1923 # initializes specific chip with 128kB of flash and 64kB of RAM
1924 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1928 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1929 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1931 For an example of this scheme see LPC2000 target config files.
1933 The @code{init_boards} procedure is a similar concept concerning board config files
1934 (@xref{theinitboardprocedure,,The init_board procedure}.)
1936 @anchor{theinittargeteventsprocedure}
1937 @subsection The init_target_events procedure
1938 @cindex init_target_events procedure
1940 A special procedure called @code{init_target_events} is run just after
1941 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1942 procedure}.) and before @code{init_board}
1943 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1944 to set up default target events for the targets that do not have those
1945 events already assigned.
1947 @subsection ARM Core Specific Hacks
1949 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1950 special high speed download features - enable it.
1952 If present, the MMU, the MPU and the CACHE should be disabled.
1954 Some ARM cores are equipped with trace support, which permits
1955 examination of the instruction and data bus activity. Trace
1956 activity is controlled through an ``Embedded Trace Module'' (ETM)
1957 on one of the core's scan chains. The ETM emits voluminous data
1958 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1959 If you are using an external trace port,
1960 configure it in your board config file.
1961 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1962 configure it in your target config file.
1965 etm config $_TARGETNAME 16 normal full etb
1966 etb config $_TARGETNAME $_CHIPNAME.etb
1969 @subsection Internal Flash Configuration
1971 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1973 @b{Never ever} in the ``target configuration file'' define any type of
1974 flash that is external to the chip. (For example a BOOT flash on
1975 Chip Select 0.) Such flash information goes in a board file - not
1976 the TARGET (chip) file.
1980 @item at91sam7x256 - has 256K flash YES enable it.
1981 @item str912 - has flash internal YES enable it.
1982 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1983 @item pxa270 - again - CS0 flash - it goes in the board file.
1986 @anchor{translatingconfigurationfiles}
1987 @section Translating Configuration Files
1989 If you have a configuration file for another hardware debugger
1990 or toolset (Abatron, BDI2000, BDI3000, CCS,
1991 Lauterbach, SEGGER, Macraigor, etc.), translating
1992 it into OpenOCD syntax is often quite straightforward. The most tricky
1993 part of creating a configuration script is oftentimes the reset init
1994 sequence where e.g. PLLs, DRAM and the like is set up.
1996 One trick that you can use when translating is to write small
1997 Tcl procedures to translate the syntax into OpenOCD syntax. This
1998 can avoid manual translation errors and make it easier to
1999 convert other scripts later on.
2001 Example of transforming quirky arguments to a simple search and
2005 # Lauterbach syntax(?)
2007 # Data.Set c15:0x042f %long 0x40000015
2009 # OpenOCD syntax when using procedure below.
2011 # setc15 0x01 0x00050078
2013 proc setc15 @{regs value@} @{
2016 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2018 arm mcr 15 [expr @{($regs >> 12) & 0x7@}] \
2019 [expr @{($regs >> 0) & 0xf@}] [expr @{($regs >> 4) & 0xf@}] \
2020 [expr @{($regs >> 8) & 0x7@}] $value
2026 @node Server Configuration
2027 @chapter Server Configuration
2028 @cindex initialization
2029 The commands here are commonly found in the openocd.cfg file and are
2030 used to specify what TCP/IP ports are used, and how GDB should be
2033 @anchor{configurationstage}
2034 @section Configuration Stage
2035 @cindex configuration stage
2036 @cindex config command
2038 When the OpenOCD server process starts up, it enters a
2039 @emph{configuration stage} which is the only time that
2040 certain commands, @emph{configuration commands}, may be issued.
2041 Normally, configuration commands are only available
2042 inside startup scripts.
2044 In this manual, the definition of a configuration command is
2045 presented as a @emph{Config Command}, not as a @emph{Command}
2046 which may be issued interactively.
2047 The runtime @command{help} command also highlights configuration
2048 commands, and those which may be issued at any time.
2050 Those configuration commands include declaration of TAPs,
2052 the interface used for JTAG communication,
2053 and other basic setup.
2054 The server must leave the configuration stage before it
2055 may access or activate TAPs.
2056 After it leaves this stage, configuration commands may no
2059 @deffn {Command} {command mode} [command_name]
2060 Returns the command modes allowed by a command: 'any', 'config', or
2061 'exec'. If no command is specified, returns the current command
2062 mode. Returns 'unknown' if an unknown command is given. Command can be
2063 multiple tokens. (command valid any time)
2065 In this document, the modes are described as stages, 'config' and
2066 'exec' mode correspond configuration stage and run stage. 'any' means
2067 the command can be executed in either
2068 stages. @xref{configurationstage,,Configuration Stage}, and
2069 @xref{enteringtherunstage,,Entering the Run Stage}.
2072 @anchor{enteringtherunstage}
2073 @section Entering the Run Stage
2075 The first thing OpenOCD does after leaving the configuration
2076 stage is to verify that it can talk to the scan chain
2077 (list of TAPs) which has been configured.
2078 It will warn if it doesn't find TAPs it expects to find,
2079 or finds TAPs that aren't supposed to be there.
2080 You should see no errors at this point.
2081 If you see errors, resolve them by correcting the
2082 commands you used to configure the server.
2083 Common errors include using an initial JTAG speed that's too
2084 fast, and not providing the right IDCODE values for the TAPs
2087 Once OpenOCD has entered the run stage, a number of commands
2089 A number of these relate to the debug targets you may have declared.
2090 For example, the @command{mww} command will not be available until
2091 a target has been successfully instantiated.
2092 If you want to use those commands, you may need to force
2093 entry to the run stage.
2095 @deffn {Config Command} {init}
2096 This command terminates the configuration stage and
2097 enters the run stage. This helps when you need to have
2098 the startup scripts manage tasks such as resetting the target,
2099 programming flash, etc. To reset the CPU upon startup, add "init" and
2100 "reset" at the end of the config script or at the end of the OpenOCD
2101 command line using the @option{-c} command line switch.
2103 If this command does not appear in any startup/configuration file
2104 OpenOCD executes the command for you after processing all
2105 configuration files and/or command line options.
2107 @b{NOTE:} This command normally occurs near the end of your
2108 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2109 targets ready. For example: If your openocd.cfg file needs to
2110 read/write memory on your target, @command{init} must occur before
2111 the memory read/write commands. This includes @command{nand probe}.
2113 @command{init} calls the following internal OpenOCD commands to initialize
2114 corresponding subsystems:
2115 @deffn {Config Command} {target init}
2116 @deffnx {Command} {transport init}
2117 @deffnx {Command} {dap init}
2118 @deffnx {Config Command} {flash init}
2119 @deffnx {Config Command} {nand init}
2120 @deffnx {Config Command} {pld init}
2121 @deffnx {Command} {tpiu init}
2124 At last, @command{init} executes all the commands that are specified in
2125 the TCL list @var{post_init_commands}. The commands are executed in the
2126 same order they occupy in the list. If one of the commands fails, then
2127 the error is propagated and OpenOCD fails too.
2129 lappend post_init_commands @{echo "OpenOCD successfully initialized."@}
2130 lappend post_init_commands @{echo "Have fun with OpenOCD !"@}
2134 @deffn {Config Command} {noinit}
2135 Prevent OpenOCD from implicit @command{init} call at the end of startup.
2136 Allows issuing configuration commands over telnet or Tcl connection.
2137 When you are done with configuration use @command{init} to enter
2141 @deffn {Overridable Procedure} {jtag_init}
2142 This is invoked at server startup to verify that it can talk
2143 to the scan chain (list of TAPs) which has been configured.
2145 The default implementation first tries @command{jtag arp_init},
2146 which uses only a lightweight JTAG reset before examining the
2148 If that fails, it tries again, using a harder reset
2149 from the overridable procedure @command{init_reset}.
2151 Implementations must have verified the JTAG scan chain before
2153 This is done by calling @command{jtag arp_init}
2154 (or @command{jtag arp_init-reset}).
2158 @section TCP/IP Ports
2163 The OpenOCD server accepts remote commands in several syntaxes.
2164 Each syntax uses a different TCP/IP port, which you may specify
2165 only during configuration (before those ports are opened).
2167 For reasons including security, you may wish to prevent remote
2168 access using one or more of these ports.
2169 In such cases, just specify the relevant port number as "disabled".
2170 If you disable all access through TCP/IP, you will need to
2171 use the command line @option{-pipe} option.
2174 @deffn {Config Command} {gdb_port} [number]
2176 Normally gdb listens to a TCP/IP port, but GDB can also
2177 communicate via pipes(stdin/out or named pipes). The name
2178 "gdb_port" stuck because it covers probably more than 90% of
2179 the normal use cases.
2181 No arguments reports GDB port. "pipe" means listen to stdin
2182 output to stdout, an integer is base port number, "disabled"
2183 disables the gdb server.
2185 When using "pipe", also use log_output to redirect the log
2186 output to a file so as not to flood the stdin/out pipes.
2188 Any other string is interpreted as named pipe to listen to.
2189 Output pipe is the same name as input pipe, but with 'o' appended,
2190 e.g. /var/gdb, /var/gdbo.
2192 The GDB port for the first target will be the base port, the
2193 second target will listen on gdb_port + 1, and so on.
2194 When not specified during the configuration stage,
2195 the port @var{number} defaults to 3333.
2196 When @var{number} is not a numeric value, incrementing it to compute
2197 the next port number does not work. In this case, specify the proper
2198 @var{number} for each target by using the option @code{-gdb-port} of the
2199 commands @command{target create} or @command{$target_name configure}.
2200 @xref{gdbportoverride,,option -gdb-port}.
2202 Note: when using "gdb_port pipe", increasing the default remote timeout in
2203 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2204 cause initialization to fail with "Unknown remote qXfer reply: OK".
2207 @deffn {Config Command} {tcl_port} [number]
2208 Specify or query the port used for a simplified RPC
2209 connection that can be used by clients to issue TCL commands and get the
2210 output from the Tcl engine.
2211 Intended as a machine interface.
2212 When not specified during the configuration stage,
2213 the port @var{number} defaults to 6666.
2214 When specified as "disabled", this service is not activated.
2217 @deffn {Config Command} {telnet_port} [number]
2218 Specify or query the
2219 port on which to listen for incoming telnet connections.
2220 This port is intended for interaction with one human through TCL commands.
2221 When not specified during the configuration stage,
2222 the port @var{number} defaults to 4444.
2223 When specified as "disabled", this service is not activated.
2226 @anchor{gdbconfiguration}
2227 @section GDB Configuration
2229 @cindex GDB configuration
2230 You can reconfigure some GDB behaviors if needed.
2231 The ones listed here are static and global.
2232 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2233 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2235 @anchor{gdbbreakpointoverride}
2236 @deffn {Command} {gdb_breakpoint_override} [@option{hard}|@option{soft}|@option{disable}]
2237 Force breakpoint type for gdb @command{break} commands.
2238 This option supports GDB GUIs which don't
2239 distinguish hard versus soft breakpoints, if the default OpenOCD and
2240 GDB behaviour is not sufficient. GDB normally uses hardware
2241 breakpoints if the memory map has been set up for flash regions.
2244 @anchor{gdbflashprogram}
2245 @deffn {Config Command} {gdb_flash_program} (@option{enable}|@option{disable})
2246 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2247 vFlash packet is received.
2248 The default behaviour is @option{enable}.
2251 @deffn {Config Command} {gdb_memory_map} (@option{enable}|@option{disable})
2252 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2253 requested. GDB will then know when to set hardware breakpoints, and program flash
2254 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2255 for flash programming to work.
2256 Default behaviour is @option{enable}.
2257 @xref{gdbflashprogram,,gdb_flash_program}.
2260 @deffn {Config Command} {gdb_report_data_abort} (@option{enable}|@option{disable})
2261 Specifies whether data aborts cause an error to be reported
2262 by GDB memory read packets.
2263 The default behaviour is @option{disable};
2264 use @option{enable} see these errors reported.
2267 @deffn {Config Command} {gdb_report_register_access_error} (@option{enable}|@option{disable})
2268 Specifies whether register accesses requested by GDB register read/write
2269 packets report errors or not.
2270 The default behaviour is @option{disable};
2271 use @option{enable} see these errors reported.
2274 @deffn {Config Command} {gdb_target_description} (@option{enable}|@option{disable})
2275 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2276 The default behaviour is @option{enable}.
2279 @deffn {Command} {gdb_save_tdesc}
2280 Saves the target description file to the local file system.
2282 The file name is @i{target_name}.xml.
2285 @anchor{eventpolling}
2286 @section Event Polling
2288 Hardware debuggers are parts of asynchronous systems,
2289 where significant events can happen at any time.
2290 The OpenOCD server needs to detect some of these events,
2291 so it can report them to through TCL command line
2294 Examples of such events include:
2297 @item One of the targets can stop running ... maybe it triggers
2298 a code breakpoint or data watchpoint, or halts itself.
2299 @item Messages may be sent over ``debug message'' channels ... many
2300 targets support such messages sent over JTAG,
2301 for receipt by the person debugging or tools.
2302 @item Loss of power ... some adapters can detect these events.
2303 @item Resets not issued through JTAG ... such reset sources
2304 can include button presses or other system hardware, sometimes
2305 including the target itself (perhaps through a watchdog).
2306 @item Debug instrumentation sometimes supports event triggering
2307 such as ``trace buffer full'' (so it can quickly be emptied)
2308 or other signals (to correlate with code behavior).
2311 None of those events are signaled through standard JTAG signals.
2312 However, most conventions for JTAG connectors include voltage
2313 level and system reset (SRST) signal detection.
2314 Some connectors also include instrumentation signals, which
2315 can imply events when those signals are inputs.
2317 In general, OpenOCD needs to periodically check for those events,
2318 either by looking at the status of signals on the JTAG connector
2319 or by sending synchronous ``tell me your status'' JTAG requests
2320 to the various active targets.
2321 There is a command to manage and monitor that polling,
2322 which is normally done in the background.
2324 @deffn {Command} {poll} [@option{on}|@option{off}]
2325 Poll the current target for its current state.
2326 (Also, @pxref{targetcurstate,,target curstate}.)
2327 If that target is in debug mode, architecture
2328 specific information about the current state is printed.
2329 An optional parameter
2330 allows background polling to be enabled and disabled.
2332 You could use this from the TCL command shell, or
2333 from GDB using @command{monitor poll} command.
2334 Leave background polling enabled while you're using GDB.
2337 background polling: on
2338 target state: halted
2339 target halted in ARM state due to debug-request, \
2340 current mode: Supervisor
2341 cpsr: 0x800000d3 pc: 0x11081bfc
2342 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2347 @node Debug Adapter Configuration
2348 @chapter Debug Adapter Configuration
2349 @cindex config file, interface
2350 @cindex interface config file
2352 Correctly installing OpenOCD includes making your operating system give
2353 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2354 are used to select which one is used, and to configure how it is used.
2357 Because OpenOCD started out with a focus purely on JTAG, you may find
2358 places where it wrongly presumes JTAG is the only transport protocol
2359 in use. Be aware that recent versions of OpenOCD are removing that
2360 limitation. JTAG remains more functional than most other transports.
2361 Other transports do not support boundary scan operations, or may be
2362 specific to a given chip vendor. Some might be usable only for
2363 programming flash memory, instead of also for debugging.
2366 Debug Adapters/Interfaces/Dongles are normally configured
2367 through commands in an interface configuration
2368 file which is sourced by your @file{openocd.cfg} file, or
2369 through a command line @option{-f interface/....cfg} option.
2372 source [find interface/olimex-jtag-tiny.cfg]
2376 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2377 A few cases are so simple that you only need to say what driver to use:
2381 adapter driver jlink
2384 Most adapters need a bit more configuration than that.
2387 @section Adapter Configuration
2389 The @command{adapter driver} command tells OpenOCD what type of debug adapter you are
2390 using. Depending on the type of adapter, you may need to use one or
2391 more additional commands to further identify or configure the adapter.
2393 @deffn {Config Command} {adapter driver} name
2394 Use the adapter driver @var{name} to connect to the
2398 @deffn {Command} {adapter list}
2399 List the debug adapter drivers that have been built into
2400 the running copy of OpenOCD.
2402 @deffn {Config Command} {adapter transports} transport_name+
2403 Specifies the transports supported by this debug adapter.
2404 The adapter driver builds-in similar knowledge; use this only
2405 when external configuration (such as jumpering) changes what
2406 the hardware can support.
2411 @deffn {Command} {adapter name}
2412 Returns the name of the debug adapter driver being used.
2415 @anchor{adapter_usb_location}
2416 @deffn {Config Command} {adapter usb location} [<bus>-<port>[.<port>]...]
2417 Displays or specifies the physical USB port of the adapter to use. The path
2418 roots at @var{bus} and walks down the physical ports, with each
2419 @var{port} option specifying a deeper level in the bus topology, the last
2420 @var{port} denoting where the target adapter is actually plugged.
2421 The USB bus topology can be queried with the command @emph{lsusb -t} or @emph{dmesg}.
2423 This command is only available if your libusb1 is at least version 1.0.16.
2426 @deffn {Config Command} {adapter serial} serial_string
2427 Specifies the @var{serial_string} of the adapter to use.
2428 If this command is not specified, serial strings are not checked.
2429 Only the following adapter drivers use the serial string from this command:
2430 aice (aice_usb), arm-jtag-ew, cmsis_dap, ft232r, ftdi, hla (stlink, ti-icdi), jlink, kitprog, opendus,
2431 openjtag, osbdm, presto, rlink, st-link, usb_blaster (ublast2), usbprog, vsllink, xds110.
2434 @section Interface Drivers
2436 Each of the interface drivers listed here must be explicitly
2437 enabled when OpenOCD is configured, in order to be made
2438 available at run time.
2440 @deffn {Interface Driver} {amt_jtagaccel}
2441 Amontec Chameleon in its JTAG Accelerator configuration,
2442 connected to a PC's EPP mode parallel port.
2443 This defines some driver-specific commands:
2445 @deffn {Config Command} {parport port} number
2446 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2447 the number of the @file{/dev/parport} device.
2450 @deffn {Config Command} {rtck} [@option{enable}|@option{disable}]
2451 Displays status of RTCK option.
2452 Optionally sets that option first.
2456 @deffn {Interface Driver} {arm-jtag-ew}
2457 Olimex ARM-JTAG-EW USB adapter
2458 This has one driver-specific command:
2460 @deffn {Command} {armjtagew_info}
2465 @deffn {Interface Driver} {at91rm9200}
2466 Supports bitbanged JTAG from the local system,
2467 presuming that system is an Atmel AT91rm9200
2468 and a specific set of GPIOs is used.
2469 @c command: at91rm9200_device NAME
2470 @c chooses among list of bit configs ... only one option
2473 @deffn {Interface Driver} {cmsis-dap}
2474 ARM CMSIS-DAP compliant based adapter v1 (USB HID based)
2477 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2478 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2479 the driver will attempt to auto detect the CMSIS-DAP device.
2480 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2482 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2486 @deffn {Config Command} {cmsis_dap_backend} [@option{auto}|@option{usb_bulk}|@option{hid}]
2487 Specifies how to communicate with the adapter:
2490 @item @option{hid} Use HID generic reports - CMSIS-DAP v1
2491 @item @option{usb_bulk} Use USB bulk - CMSIS-DAP v2
2492 @item @option{auto} First try USB bulk CMSIS-DAP v2, if not found try HID CMSIS-DAP v1.
2493 This is the default if @command{cmsis_dap_backend} is not specified.
2497 @deffn {Config Command} {cmsis_dap_usb interface} [number]
2498 Specifies the @var{number} of the USB interface to use in v2 mode (USB bulk).
2499 In most cases need not to be specified and interfaces are searched by
2500 interface string or for user class interface.
2503 @deffn {Command} {cmsis-dap info}
2504 Display various device information, like hardware version, firmware version, current bus status.
2507 @deffn {Command} {cmsis-dap cmd} number number ...
2508 Execute an arbitrary CMSIS-DAP command. Use for adapter testing or for handling
2509 of an adapter vendor specific command from a Tcl script.
2511 Take given numbers as bytes, assemble a CMSIS-DAP protocol command packet
2512 from them and send it to the adapter. The first 4 bytes of the adapter response
2514 See @url{https://arm-software.github.io/CMSIS_5/DAP/html/group__DAP__Commands__gr.html}
2518 @deffn {Interface Driver} {dummy}
2519 A dummy software-only driver for debugging.
2522 @deffn {Interface Driver} {ep93xx}
2523 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2526 @deffn {Interface Driver} {ftdi}
2527 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2528 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2530 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2531 bypassing intermediate libraries like libftdi.
2533 Support for new FTDI based adapters can be added completely through
2534 configuration files, without the need to patch and rebuild OpenOCD.
2536 The driver uses a signal abstraction to enable Tcl configuration files to
2537 define outputs for one or several FTDI GPIO. These outputs can then be
2538 controlled using the @command{ftdi set_signal} command. Special signal names
2539 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2540 will be used for their customary purpose. Inputs can be read using the
2541 @command{ftdi get_signal} command.
2543 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2544 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2545 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2546 required by the protocol, to tell the adapter to drive the data output onto
2547 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2549 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2550 be controlled differently. In order to support tristateable signals such as
2551 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2552 signal. The following output buffer configurations are supported:
2555 @item Push-pull with one FTDI output as (non-)inverted data line
2556 @item Open drain with one FTDI output as (non-)inverted output-enable
2557 @item Tristate with one FTDI output as (non-)inverted data line and another
2558 FTDI output as (non-)inverted output-enable
2559 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2560 switching data and direction as necessary
2563 These interfaces have several commands, used to configure the driver
2564 before initializing the JTAG scan chain:
2566 @deffn {Config Command} {ftdi vid_pid} [vid pid]+
2567 The vendor ID and product ID of the adapter. Up to eight
2568 [@var{vid}, @var{pid}] pairs may be given, e.g.
2570 ftdi vid_pid 0x0403 0xcff8 0x15ba 0x0003
2574 @deffn {Config Command} {ftdi device_desc} description
2575 Provides the USB device description (the @emph{iProduct string})
2576 of the adapter. If not specified, the device description is ignored
2577 during device selection.
2580 @deffn {Config Command} {ftdi channel} channel
2581 Selects the channel of the FTDI device to use for MPSSE operations. Most
2582 adapters use the default, channel 0, but there are exceptions.
2585 @deffn {Config Command} {ftdi layout_init} data direction
2586 Specifies the initial values of the FTDI GPIO data and direction registers.
2587 Each value is a 16-bit number corresponding to the concatenation of the high
2588 and low FTDI GPIO registers. The values should be selected based on the
2589 schematics of the adapter, such that all signals are set to safe levels with
2590 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2591 and initially asserted reset signals.
2594 @deffn {Command} {ftdi layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2595 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2596 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2597 register bitmasks to tell the driver the connection and type of the output
2598 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2599 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2600 used with inverting data inputs and @option{-data} with non-inverting inputs.
2601 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2602 not-output-enable) input to the output buffer is connected. The options
2603 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2604 with the method @command{ftdi get_signal}.
2606 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2607 simple open-collector transistor driver would be specified with @option{-oe}
2608 only. In that case the signal can only be set to drive low or to Hi-Z and the
2609 driver will complain if the signal is set to drive high. Which means that if
2610 it's a reset signal, @command{reset_config} must be specified as
2611 @option{srst_open_drain}, not @option{srst_push_pull}.
2613 A special case is provided when @option{-data} and @option{-oe} is set to the
2614 same bitmask. Then the FTDI pin is considered being connected straight to the
2615 target without any buffer. The FTDI pin is then switched between output and
2616 input as necessary to provide the full set of low, high and Hi-Z
2617 characteristics. In all other cases, the pins specified in a signal definition
2618 are always driven by the FTDI.
2620 If @option{-alias} or @option{-nalias} is used, the signal is created
2621 identical (or with data inverted) to an already specified signal
2625 @deffn {Command} {ftdi set_signal} name @option{0}|@option{1}|@option{z}
2626 Set a previously defined signal to the specified level.
2628 @item @option{0}, drive low
2629 @item @option{1}, drive high
2630 @item @option{z}, set to high-impedance
2634 @deffn {Command} {ftdi get_signal} name
2635 Get the value of a previously defined signal.
2638 @deffn {Command} {ftdi tdo_sample_edge} @option{rising}|@option{falling}
2639 Configure TCK edge at which the adapter samples the value of the TDO signal
2641 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2642 peculiar at high JTAG clock speeds. However, FTDI chips offer a possibility to sample
2643 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2644 stability at higher JTAG clocks.
2646 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2647 @item @option{falling}, sample TDO on falling edge of TCK
2651 For example adapter definitions, see the configuration files shipped in the
2652 @file{interface/ftdi} directory.
2656 @deffn {Interface Driver} {ft232r}
2657 This driver is implementing synchronous bitbang mode of an FTDI FT232R,
2658 FT230X, FT231X and similar USB UART bridge ICs by reusing RS232 signals as GPIO.
2659 It currently doesn't support using CBUS pins as GPIO.
2661 List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
2668 @item DCD(10) - SRST
2671 User can change default pinout by supplying configuration
2672 commands with GPIO numbers or RS232 signal names.
2673 GPIO numbers correspond to bit numbers in FTDI GPIO register.
2674 They differ from physical pin numbers.
2675 For details see actual FTDI chip datasheets.
2676 Every JTAG line must be configured to unique GPIO number
2677 different than any other JTAG line, even those lines
2678 that are sometimes not used like TRST or SRST.
2692 These interfaces have several commands, used to configure the driver
2693 before initializing the JTAG scan chain:
2695 @deffn {Config Command} {ft232r vid_pid} @var{vid} @var{pid}
2696 The vendor ID and product ID of the adapter. If not specified, default
2697 0x0403:0x6001 is used.
2700 @deffn {Config Command} {ft232r jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
2701 Set four JTAG GPIO numbers at once.
2702 If not specified, default 0 3 1 2 or TXD CTS RXD RTS is used.
2705 @deffn {Config Command} {ft232r tck_num} @var{tck}
2706 Set TCK GPIO number. If not specified, default 0 or TXD is used.
2709 @deffn {Config Command} {ft232r tms_num} @var{tms}
2710 Set TMS GPIO number. If not specified, default 3 or CTS is used.
2713 @deffn {Config Command} {ft232r tdi_num} @var{tdi}
2714 Set TDI GPIO number. If not specified, default 1 or RXD is used.
2717 @deffn {Config Command} {ft232r tdo_num} @var{tdo}
2718 Set TDO GPIO number. If not specified, default 2 or RTS is used.
2721 @deffn {Config Command} {ft232r trst_num} @var{trst}
2722 Set TRST GPIO number. If not specified, default 4 or DTR is used.
2725 @deffn {Config Command} {ft232r srst_num} @var{srst}
2726 Set SRST GPIO number. If not specified, default 6 or DCD is used.
2729 @deffn {Config Command} {ft232r restore_serial} @var{word}
2730 Restore serial port after JTAG. This USB bitmode control word
2731 (16-bit) will be sent before quit. Lower byte should
2732 set GPIO direction register to a "sane" state:
2733 0x15 for TXD RTS DTR as outputs (1), others as inputs (0). Higher
2734 byte is usually 0 to disable bitbang mode.
2735 When kernel driver reattaches, serial port should continue to work.
2736 Value 0xFFFF disables sending control word and serial port,
2737 then kernel driver will not reattach.
2738 If not specified, default 0xFFFF is used.
2743 @deffn {Interface Driver} {remote_bitbang}
2744 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2745 with a remote process and sends ASCII encoded bitbang requests to that process
2746 instead of directly driving JTAG.
2748 The remote_bitbang driver is useful for debugging software running on
2749 processors which are being simulated.
2751 @deffn {Config Command} {remote_bitbang port} number
2752 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2753 sockets instead of TCP.
2756 @deffn {Config Command} {remote_bitbang host} hostname
2757 Specifies the hostname of the remote process to connect to using TCP, or the
2758 name of the UNIX socket to use if remote_bitbang port is 0.
2761 For example, to connect remotely via TCP to the host foobar you might have
2765 adapter driver remote_bitbang
2766 remote_bitbang port 3335
2767 remote_bitbang host foobar
2770 To connect to another process running locally via UNIX sockets with socket
2774 adapter driver remote_bitbang
2775 remote_bitbang port 0
2776 remote_bitbang host mysocket
2780 @deffn {Interface Driver} {usb_blaster}
2781 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2782 for FTDI chips. These interfaces have several commands, used to
2783 configure the driver before initializing the JTAG scan chain:
2785 @deffn {Config Command} {usb_blaster vid_pid} vid pid
2786 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2787 default values are used.
2788 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2789 Altera USB-Blaster (default):
2791 usb_blaster vid_pid 0x09FB 0x6001
2793 The following VID/PID is for Kolja Waschk's USB JTAG:
2795 usb_blaster vid_pid 0x16C0 0x06AD
2799 @deffn {Command} {usb_blaster pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2800 Sets the state or function of the unused GPIO pins on USB-Blasters
2801 (pins 6 and 8 on the female JTAG header). These pins can be used as
2802 SRST and/or TRST provided the appropriate connections are made on the
2805 For example, to use pin 6 as SRST:
2807 usb_blaster pin pin6 s
2808 reset_config srst_only
2812 @deffn {Config Command} {usb_blaster lowlevel_driver} (@option{ftdi}|@option{ublast2})
2813 Chooses the low level access method for the adapter. If not specified,
2814 @option{ftdi} is selected unless it wasn't enabled during the
2815 configure stage. USB-Blaster II needs @option{ublast2}.
2818 @deffn {Config Command} {usb_blaster firmware} @var{path}
2819 This command specifies @var{path} to access USB-Blaster II firmware
2820 image. To be used with USB-Blaster II only.
2825 @deffn {Interface Driver} {gw16012}
2826 Gateworks GW16012 JTAG programmer.
2827 This has one driver-specific command:
2829 @deffn {Config Command} {parport port} [port_number]
2830 Display either the address of the I/O port
2831 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2832 If a parameter is provided, first switch to use that port.
2833 This is a write-once setting.
2837 @deffn {Interface Driver} {jlink}
2838 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2841 @quotation Compatibility Note
2842 SEGGER released many firmware versions for the many hardware versions they
2843 produced. OpenOCD was extensively tested and intended to run on all of them,
2844 but some combinations were reported as incompatible. As a general
2845 recommendation, it is advisable to use the latest firmware version
2846 available for each hardware version. However the current V8 is a moving
2847 target, and SEGGER firmware versions released after the OpenOCD was
2848 released may not be compatible. In such cases it is recommended to
2849 revert to the last known functional version. For 0.5.0, this is from
2850 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2851 version is from "May 3 2012 18:36:22", packed with 4.46f.
2854 @deffn {Command} {jlink hwstatus}
2855 Display various hardware related information, for example target voltage and pin
2858 @deffn {Command} {jlink freemem}
2859 Display free device internal memory.
2861 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2862 Set the JTAG command version to be used. Without argument, show the actual JTAG
2865 @deffn {Command} {jlink config}
2866 Display the device configuration.
2868 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2869 Set the target power state on JTAG-pin 19. Without argument, show the target
2872 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2873 Set the MAC address of the device. Without argument, show the MAC address.
2875 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2876 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2877 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2880 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2881 Set the USB address of the device. This will also change the USB Product ID
2882 (PID) of the device. Without argument, show the USB address.
2884 @deffn {Command} {jlink config reset}
2885 Reset the current configuration.
2887 @deffn {Command} {jlink config write}
2888 Write the current configuration to the internal persistent storage.
2890 @deffn {Command} {jlink emucom write} <channel> <data>
2891 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2894 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2895 the EMUCOM channel 0x10:
2897 > jlink emucom write 0x10 aa0b23
2900 @deffn {Command} {jlink emucom read} <channel> <length>
2901 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2904 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2906 > jlink emucom read 0x0 4
2910 @deffn {Config Command} {jlink usb} <@option{0} to @option{3}>
2911 Set the USB address of the interface, in case more than one adapter is connected
2912 to the host. If not specified, USB addresses are not considered. Device
2913 selection via USB address is not always unambiguous. It is recommended to use
2914 the serial number instead, if possible.
2916 As a configuration command, it can be used only before 'init'.
2920 @deffn {Interface Driver} {kitprog}
2921 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2922 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2923 families, but it is possible to use it with some other devices. If you are using
2924 this adapter with a PSoC or a PRoC, you may need to add
2925 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2926 configuration script.
2928 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2929 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2930 be used with this driver, and must either be used with the cmsis-dap driver or
2931 switched back to KitProg mode. See the Cypress KitProg User Guide for
2932 instructions on how to switch KitProg modes.
2936 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2938 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2939 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2940 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2941 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2942 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2943 SWD sequence must be sent after every target reset in order to re-establish
2944 communications with the target.
2945 @item Due in part to the limitation above, KitProg devices with firmware below
2946 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
2947 communicate with PSoC 5LP devices. This is because, assuming debug is not
2948 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
2949 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
2950 could only be sent with an acquisition sequence.
2953 @deffn {Config Command} {kitprog_init_acquire_psoc}
2954 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
2955 Please be aware that the acquisition sequence hard-resets the target.
2958 @deffn {Command} {kitprog acquire_psoc}
2959 Run a PSoC acquisition sequence immediately. Typically, this should not be used
2960 outside of the target-specific configuration scripts since it hard-resets the
2961 target as a side-effect.
2962 This is necessary for "reset halt" on some PSoC 4 series devices.
2965 @deffn {Command} {kitprog info}
2966 Display various adapter information, such as the hardware version, firmware
2967 version, and target voltage.
2971 @deffn {Interface Driver} {parport}
2972 Supports PC parallel port bit-banging cables:
2973 Wigglers, PLD download cable, and more.
2974 These interfaces have several commands, used to configure the driver
2975 before initializing the JTAG scan chain:
2977 @deffn {Config Command} {parport cable} name
2978 Set the layout of the parallel port cable used to connect to the target.
2979 This is a write-once setting.
2980 Currently valid cable @var{name} values include:
2983 @item @b{altium} Altium Universal JTAG cable.
2984 @item @b{arm-jtag} Same as original wiggler except SRST and
2985 TRST connections reversed and TRST is also inverted.
2986 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2987 in configuration mode. This is only used to
2988 program the Chameleon itself, not a connected target.
2989 @item @b{dlc5} The Xilinx Parallel cable III.
2990 @item @b{flashlink} The ST Parallel cable.
2991 @item @b{lattice} Lattice ispDOWNLOAD Cable
2992 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2994 Amontec's Chameleon Programmer. The new version available from
2995 the website uses the original Wiggler layout ('@var{wiggler}')
2996 @item @b{triton} The parallel port adapter found on the
2997 ``Karo Triton 1 Development Board''.
2998 This is also the layout used by the HollyGates design
2999 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
3000 @item @b{wiggler} The original Wiggler layout, also supported by
3001 several clones, such as the Olimex ARM-JTAG
3002 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
3003 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
3007 @deffn {Config Command} {parport port} [port_number]
3008 Display either the address of the I/O port
3009 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
3010 If a parameter is provided, first switch to use that port.
3011 This is a write-once setting.
3013 When using PPDEV to access the parallel port, use the number of the parallel port:
3014 @option{parport port 0} (the default). If @option{parport port 0x378} is specified
3015 you may encounter a problem.
3018 @deffn {Config Command} {parport toggling_time} [nanoseconds]
3019 Displays how many nanoseconds the hardware needs to toggle TCK;
3020 the parport driver uses this value to obey the
3021 @command{adapter speed} configuration.
3022 When the optional @var{nanoseconds} parameter is given,
3023 that setting is changed before displaying the current value.
3025 The default setting should work reasonably well on commodity PC hardware.
3026 However, you may want to calibrate for your specific hardware.
3028 To measure the toggling time with a logic analyzer or a digital storage
3029 oscilloscope, follow the procedure below:
3031 > parport toggling_time 1000
3034 This sets the maximum JTAG clock speed of the hardware, but
3035 the actual speed probably deviates from the requested 500 kHz.
3036 Now, measure the time between the two closest spaced TCK transitions.
3037 You can use @command{runtest 1000} or something similar to generate a
3038 large set of samples.
3039 Update the setting to match your measurement:
3041 > parport toggling_time <measured nanoseconds>
3043 Now the clock speed will be a better match for @command{adapter speed}
3044 command given in OpenOCD scripts and event handlers.
3046 You can do something similar with many digital multimeters, but note
3047 that you'll probably need to run the clock continuously for several
3048 seconds before it decides what clock rate to show. Adjust the
3049 toggling time up or down until the measured clock rate is a good
3050 match with the rate you specified in the @command{adapter speed} command;
3055 @deffn {Config Command} {parport write_on_exit} (@option{on}|@option{off})
3056 This will configure the parallel driver to write a known
3057 cable-specific value to the parallel interface on exiting OpenOCD.
3060 For example, the interface configuration file for a
3061 classic ``Wiggler'' cable on LPT2 might look something like this:
3064 adapter driver parport
3066 parport cable wiggler
3070 @deffn {Interface Driver} {presto}
3071 ASIX PRESTO USB JTAG programmer.
3074 @deffn {Interface Driver} {rlink}
3075 Raisonance RLink USB adapter
3078 @deffn {Interface Driver} {usbprog}
3079 usbprog is a freely programmable USB adapter.
3082 @deffn {Interface Driver} {vsllink}
3083 vsllink is part of Versaloon which is a versatile USB programmer.
3086 This defines quite a few driver-specific commands,
3087 which are not currently documented here.
3091 @anchor{hla_interface}
3092 @deffn {Interface Driver} {hla}
3093 This is a driver that supports multiple High Level Adapters.
3094 This type of adapter does not expose some of the lower level api's
3095 that OpenOCD would normally use to access the target.
3097 Currently supported adapters include the STMicroelectronics ST-LINK, TI ICDI
3098 and Nuvoton Nu-Link.
3099 ST-LINK firmware version >= V2.J21.S4 recommended due to issues with earlier
3100 versions of firmware where serial number is reset after first use. Suggest
3101 using ST firmware update utility to upgrade ST-LINK firmware even if current
3102 version reported is V2.J21.S4.
3104 @deffn {Config Command} {hla_device_desc} description
3105 Currently Not Supported.
3108 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi}|@option{nulink})
3109 Specifies the adapter layout to use.
3112 @deffn {Config Command} {hla_vid_pid} [vid pid]+
3113 Pairs of vendor IDs and product IDs of the device.
3116 @deffn {Config Command} {hla_stlink_backend} (usb | tcp [port])
3117 @emph{ST-Link only:} Choose between 'exclusive' USB communication (the default backend) or
3118 'shared' mode using ST-Link TCP server (the default port is 7184).
3120 @emph{Note:} ST-Link TCP server is a binary application provided by ST
3121 available from @url{https://www.st.com/en/development-tools/st-link-server.html,
3122 ST-LINK server software module}.
3125 @deffn {Command} {hla_command} command
3126 Execute a custom adapter-specific command. The @var{command} string is
3127 passed as is to the underlying adapter layout handler.
3131 @anchor{st_link_dap_interface}
3132 @deffn {Interface Driver} {st-link}
3133 This is a driver that supports STMicroelectronics adapters ST-LINK/V2
3134 (from firmware V2J24) and STLINK-V3, thanks to a new API that provides
3135 directly access the arm ADIv5 DAP.
3137 The new API provide access to multiple AP on the same DAP, but the
3138 maximum number of the AP port is limited by the specific firmware version
3139 (e.g. firmware V2J29 has 3 as maximum AP number, while V2J32 has 8).
3140 An error is returned for any AP number above the maximum allowed value.
3142 @emph{Note:} Either these same adapters and their older versions are
3143 also supported by @ref{hla_interface, the hla interface driver}.
3145 @deffn {Config Command} {st-link backend} (usb | tcp [port])
3146 Choose between 'exclusive' USB communication (the default backend) or
3147 'shared' mode using ST-Link TCP server (the default port is 7184).
3149 @emph{Note:} ST-Link TCP server is a binary application provided by ST
3150 available from @url{https://www.st.com/en/development-tools/st-link-server.html,
3151 ST-LINK server software module}.
3153 @emph{Note:} ST-Link TCP server does not support the SWIM transport.
3156 @deffn {Config Command} {st-link vid_pid} [vid pid]+
3157 Pairs of vendor IDs and product IDs of the device.
3160 @deffn {Command} {st-link cmd} rx_n (tx_byte)+
3161 Sends an arbitrary command composed by the sequence of bytes @var{tx_byte}
3162 and receives @var{rx_n} bytes.
3164 For example, the command to read the target's supply voltage is one byte 0xf7 followed
3165 by 15 bytes zero. It returns 8 bytes, where the first 4 bytes represent the ADC sampling
3166 of the reference voltage 1.2V and the last 4 bytes represent the ADC sampling of half
3167 the target's supply voltage.
3169 > st-link cmd 8 0xf7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3170 0xf1 0x05 0x00 0x00 0x0b 0x08 0x00 0x00
3172 The result can be converted to Volts (ignoring the most significant bytes, always zero)
3174 > set a [st-link cmd 8 0xf7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
3175 > set n [expr @{[lindex $a 4] + 256 * [lindex $a 5]@}]
3176 > set d [expr @{[lindex $a 0] + 256 * [lindex $a 1]@}]
3177 > echo [expr @{2 * 1.2 * $n / $d@}]
3183 @deffn {Interface Driver} {opendous}
3184 opendous-jtag is a freely programmable USB adapter.
3187 @deffn {Interface Driver} {ulink}
3188 This is the Keil ULINK v1 JTAG debugger.
3191 @deffn {Interface Driver} {xds110}
3192 The XDS110 is included as the embedded debug probe on many Texas Instruments
3193 LaunchPad evaluation boards. The XDS110 is also available as a stand-alone USB
3194 debug probe with the added capability to supply power to the target board. The
3195 following commands are supported by the XDS110 driver:
3197 @deffn {Config Command} {xds110 supply} voltage_in_millivolts
3198 Available only on the XDS110 stand-alone probe. Sets the voltage level of the
3199 XDS110 power supply. A value of 0 leaves the supply off. Otherwise, the supply
3200 can be set to any value in the range 1800 to 3600 millivolts.
3203 @deffn {Command} {xds110 info}
3204 Displays information about the connected XDS110 debug probe (e.g. firmware
3209 @deffn {Interface Driver} {xlnx_pcie_xvc}
3210 This driver supports the Xilinx Virtual Cable (XVC) over PCI Express.
3211 It is commonly found in Xilinx based PCI Express designs. It allows debugging
3212 fabric based JTAG/SWD devices such as Cortex-M1/M3 microcontrollers. Access to this is
3213 exposed via extended capability registers in the PCI Express configuration space.
3215 For more information see Xilinx PG245 (Section on From_PCIE_to_JTAG mode).
3217 @deffn {Config Command} {xlnx_pcie_xvc config} device
3218 Specifies the PCI Express device via parameter @var{device} to use.
3220 The correct value for @var{device} can be obtained by looking at the output
3221 of lscpi -D (first column) for the corresponding device.
3223 The string will be of the format "DDDD:BB:SS.F" such as "0000:65:00.1".
3228 @deffn {Interface Driver} {bcm2835gpio}
3229 This SoC is present in Raspberry Pi which is a cheap single-board computer
3230 exposing some GPIOs on its expansion header.
3232 The driver accesses memory-mapped GPIO peripheral registers directly
3233 for maximum performance, but the only possible race condition is for
3234 the pins' modes/muxing (which is highly unlikely), so it should be
3235 able to coexist nicely with both sysfs bitbanging and various
3236 peripherals' kernel drivers. The driver restores the previous
3237 configuration on exit.
3239 GPIO numbers >= 32 can't be used for performance reasons.
3241 See @file{interface/raspberrypi-native.cfg} for a sample config and
3244 @deffn {Config Command} {bcm2835gpio jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
3245 Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order).
3246 Must be specified to enable JTAG transport. These pins can also be specified
3250 @deffn {Config Command} {bcm2835gpio tck_num} @var{tck}
3251 Set TCK GPIO number. Must be specified to enable JTAG transport. Can also be
3252 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3255 @deffn {Config Command} {bcm2835gpio tms_num} @var{tms}
3256 Set TMS GPIO number. Must be specified to enable JTAG transport. Can also be
3257 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3260 @deffn {Config Command} {bcm2835gpio tdo_num} @var{tdo}
3261 Set TDO GPIO number. Must be specified to enable JTAG transport. Can also be
3262 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3265 @deffn {Config Command} {bcm2835gpio tdi_num} @var{tdi}
3266 Set TDI GPIO number. Must be specified to enable JTAG transport. Can also be
3267 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3270 @deffn {Config Command} {bcm2835gpio swd_nums} @var{swclk} @var{swdio}
3271 Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be
3272 specified to enable SWD transport. These pins can also be specified individually.
3275 @deffn {Config Command} {bcm2835gpio swclk_num} @var{swclk}
3276 Set SWCLK GPIO number. Must be specified to enable SWD transport. Can also be
3277 specified using the configuration command @command{bcm2835gpio swd_nums}.
3280 @deffn {Config Command} {bcm2835gpio swdio_num} @var{swdio}
3281 Set SWDIO GPIO number. Must be specified to enable SWD transport. Can also be
3282 specified using the configuration command @command{bcm2835gpio swd_nums}.
3285 @deffn {Config Command} {bcm2835gpio swdio_dir_num} @var{swdio} @var{dir}
3286 Set SWDIO direction control pin GPIO number. If specified, this pin can be used
3287 to control the direction of an external buffer on the SWDIO pin (set=output
3288 mode, clear=input mode). If not specified, this feature is disabled.
3291 @deffn {Config Command} {bcm2835gpio srst_num} @var{srst}
3292 Set SRST GPIO number. Must be specified to enable SRST.
3295 @deffn {Config Command} {bcm2835gpio trst_num} @var{trst}
3296 Set TRST GPIO number. Must be specified to enable TRST.
3299 @deffn {Config Command} {bcm2835gpio speed_coeffs} @var{speed_coeff} @var{speed_offset}
3300 Set SPEED_COEFF and SPEED_OFFSET for delay calculations. If unspecified,
3301 speed_coeff defaults to 113714, and speed_offset defaults to 28.
3304 @deffn {Config Command} {bcm2835gpio peripheral_base} @var{base}
3305 Set the peripheral base register address to access GPIOs. For the RPi1, use
3306 0x20000000. For RPi2 and RPi3, use 0x3F000000. For RPi4, use 0xFE000000. A full
3307 list can be found in the
3308 @uref{https://www.raspberrypi.org/documentation/hardware/raspberrypi/peripheral_addresses.md, official guide}.
3313 @deffn {Interface Driver} {imx_gpio}
3314 i.MX SoC is present in many community boards. Wandboard is an example
3315 of the one which is most popular.
3317 This driver is mostly the same as bcm2835gpio.
3319 See @file{interface/imx-native.cfg} for a sample config and
3325 @deffn {Interface Driver} {linuxgpiod}
3326 Linux provides userspace access to GPIO through libgpiod since Linux kernel version v4.6.
3327 The driver emulates either JTAG and SWD transport through bitbanging.
3329 See @file{interface/dln-2-gpiod.cfg} for a sample config.
3333 @deffn {Interface Driver} {sysfsgpio}
3334 Linux legacy userspace access to GPIO through sysfs is deprecated from Linux kernel version v5.3.
3335 Prefer using @b{linuxgpiod}, instead.
3337 See @file{interface/sysfsgpio-raspberrypi.cfg} for a sample config.
3341 @deffn {Interface Driver} {openjtag}
3342 OpenJTAG compatible USB adapter.
3343 This defines some driver-specific commands:
3345 @deffn {Config Command} {openjtag variant} variant
3346 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
3347 Currently valid @var{variant} values include:
3350 @item @b{standard} Standard variant (default).
3351 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3352 (see @uref{http://www.cypress.com/?rID=82870}).
3356 @deffn {Config Command} {openjtag device_desc} string
3357 The USB device description string of the adapter.
3358 This value is only used with the standard variant.
3363 @deffn {Interface Driver} {vdebug}
3364 Cadence Virtual Debug Interface driver.
3366 @deffn {Config Command} {vdebug server} host:port
3367 Specifies the host and TCP port number where the vdebug server runs.
3370 @deffn {Config Command} {vdebug batching} value
3371 Specifies the batching method for the vdebug request. Possible values are
3373 1 or wr to batch write transactions together (default)
3374 2 or rw to batch both read and write transactions
3377 @deffn {Config Command} {vdebug polling} min max
3378 Takes two values, representing the polling interval in ms. Lower values mean faster
3379 debugger responsiveness, but lower emulation performance. The minimum should be
3380 around 10, maximum should not exceed 1000, which is the default gdb and keepalive
3384 @deffn {Config Command} {vdebug bfm_path} path clk_period
3385 Specifies the hierarchical path and input clk period of the vdebug BFM in the design.
3386 The hierarchical path uses Verilog notation top.inst.inst
3387 The clock period must include the unit, for instance 40ns.
3390 @deffn {Config Command} {vdebug mem_path} path base size
3391 Specifies the hierarchical path to the design memory instance for backdoor access.
3392 Up to 4 memories can be specified. The hierarchical path uses Verilog notation.
3393 The base specifies start address in the design address space, size its size in bytes.
3394 Both values can use hexadecimal notation with prefix 0x.
3398 @deffn {Interface Driver} {jtag_dpi}
3399 SystemVerilog Direct Programming Interface (DPI) compatible driver for
3400 JTAG devices in emulation. The driver acts as a client for the SystemVerilog
3401 DPI server interface.
3403 @deffn {Config Command} {jtag_dpi set_port} port
3404 Specifies the TCP/IP port number of the SystemVerilog DPI server interface.
3407 @deffn {Config Command} {jtag_dpi set_address} address
3408 Specifies the TCP/IP address of the SystemVerilog DPI server interface.
3413 @deffn {Interface Driver} {buspirate}
3415 This driver is for the Bus Pirate (see @url{http://dangerousprototypes.com/docs/Bus_Pirate}) and compatible devices.
3416 It uses a simple data protocol over a serial port connection.
3418 Most hardware development boards have a UART, a real serial port, or a virtual USB serial device, so this driver
3419 allows you to start building your own JTAG adapter without the complexity of a custom USB connection.
3421 @deffn {Config Command} {buspirate port} serial_port
3422 Specify the serial port's filename. For example:
3424 buspirate port /dev/ttyUSB0
3428 @deffn {Config Command} {buspirate speed} (normal|fast)
3429 Set the communication speed to 115k (normal) or 1M (fast). For example:
3431 buspirate speed normal
3435 @deffn {Config Command} {buspirate mode} (normal|open-drain)
3436 Set the Bus Pirate output mode.
3438 @item In normal mode (push/pull), do not enable the pull-ups, and do not connect I/O header pin VPU to JTAG VREF.
3439 @item In open drain mode, you will then need to enable the pull-ups.
3443 buspirate mode normal
3447 @deffn {Config Command} {buspirate pullup} (0|1)
3448 Whether to connect (1) or not (0) the I/O header pin VPU (JTAG VREF)
3449 to the pull-up/pull-down resistors on MOSI (JTAG TDI), CLK (JTAG TCK), MISO (JTAG TDO) and CS (JTAG TMS).
3456 @deffn {Config Command} {buspirate vreg} (0|1)
3457 Whether to enable (1) or disable (0) the built-in voltage regulator,
3458 which can be used to supply power to a test circuit through
3459 I/O header pins +3V3 and +5V. For example:
3465 @deffn {Command} {buspirate led} (0|1)
3466 Turns the Bus Pirate's LED on (1) or off (0). For example:
3475 @section Transport Configuration
3477 As noted earlier, depending on the version of OpenOCD you use,
3478 and the debug adapter you are using,
3479 several transports may be available to
3480 communicate with debug targets (or perhaps to program flash memory).
3481 @deffn {Command} {transport list}
3482 displays the names of the transports supported by this
3486 @deffn {Command} {transport select} @option{transport_name}
3487 Select which of the supported transports to use in this OpenOCD session.
3489 When invoked with @option{transport_name}, attempts to select the named
3490 transport. The transport must be supported by the debug adapter
3491 hardware and by the version of OpenOCD you are using (including the
3494 If no transport has been selected and no @option{transport_name} is
3495 provided, @command{transport select} auto-selects the first transport
3496 supported by the debug adapter.
3498 @command{transport select} always returns the name of the session's selected
3502 @subsection JTAG Transport
3504 JTAG is the original transport supported by OpenOCD, and most
3505 of the OpenOCD commands support it.
3506 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3507 each of which must be explicitly declared.
3508 JTAG supports both debugging and boundary scan testing.
3509 Flash programming support is built on top of debug support.
3511 JTAG transport is selected with the command @command{transport select
3512 jtag}. Unless your adapter uses either @ref{hla_interface,the hla interface
3513 driver} (in which case the command is @command{transport select hla_jtag})
3514 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3515 the command is @command{transport select dapdirect_jtag}).
3517 @subsection SWD Transport
3519 @cindex Serial Wire Debug
3520 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3521 Debug Access Point (DAP, which must be explicitly declared.
3522 (SWD uses fewer signal wires than JTAG.)
3523 SWD is debug-oriented, and does not support boundary scan testing.
3524 Flash programming support is built on top of debug support.
3525 (Some processors support both JTAG and SWD.)
3527 SWD transport is selected with the command @command{transport select
3528 swd}. Unless your adapter uses either @ref{hla_interface,the hla interface
3529 driver} (in which case the command is @command{transport select hla_swd})
3530 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3531 the command is @command{transport select dapdirect_swd}).
3533 @deffn {Config Command} {swd newdap} ...
3534 Declares a single DAP which uses SWD transport.
3535 Parameters are currently the same as "jtag newtap" but this is
3539 @cindex SWD multi-drop
3540 The newer SWD devices (SW-DP v2 or SWJ-DP v2) support the multi-drop extension
3541 of SWD protocol: two or more devices can be connected to one SWD adapter.
3542 SWD transport works in multi-drop mode if @ref{dap_create,DAP} is configured
3543 with both @code{-dp-id} and @code{-instance-id} parameters regardless how many
3546 Not all adapters and adapter drivers support SWD multi-drop. Only the following
3547 adapter drivers are SWD multi-drop capable:
3548 cmsis_dap (use an adapter with CMSIS-DAP version 2.0), ftdi, all bitbang based.
3550 @subsection SPI Transport
3552 @cindex Serial Peripheral Interface
3553 The Serial Peripheral Interface (SPI) is a general purpose transport
3554 which uses four wire signaling. Some processors use it as part of a
3555 solution for flash programming.
3557 @anchor{swimtransport}
3558 @subsection SWIM Transport
3560 @cindex Single Wire Interface Module
3561 The Single Wire Interface Module (SWIM) is a low-pin-count debug protocol used
3562 by the STMicroelectronics MCU family STM8 and documented in the
3563 @uref{https://www.st.com/resource/en/user_manual/cd00173911.pdf, User Manual UM470}.
3565 SWIM does not support boundary scan testing nor multiple cores.
3567 The SWIM transport is selected with the command @command{transport select swim}.
3569 The concept of TAPs does not fit in the protocol since SWIM does not implement
3570 a scan chain. Nevertheless, the current SW model of OpenOCD requires defining a
3571 virtual SWIM TAP through the command @command{swim newtap basename tap_type}.
3572 The TAP definition must precede the target definition command
3573 @command{target create target_name stm8 -chain-position basename.tap_type}.
3577 JTAG clock setup is part of system setup.
3578 It @emph{does not belong with interface setup} since any interface
3579 only knows a few of the constraints for the JTAG clock speed.
3580 Sometimes the JTAG speed is
3581 changed during the target initialization process: (1) slow at
3582 reset, (2) program the CPU clocks, (3) run fast.
3583 Both the "slow" and "fast" clock rates are functions of the
3584 oscillators used, the chip, the board design, and sometimes
3585 power management software that may be active.
3587 The speed used during reset, and the scan chain verification which
3588 follows reset, can be adjusted using a @code{reset-start}
3589 target event handler.
3590 It can then be reconfigured to a faster speed by a
3591 @code{reset-init} target event handler after it reprograms those
3592 CPU clocks, or manually (if something else, such as a boot loader,
3593 sets up those clocks).
3594 @xref{targetevents,,Target Events}.
3595 When the initial low JTAG speed is a chip characteristic, perhaps
3596 because of a required oscillator speed, provide such a handler
3597 in the target config file.
3598 When that speed is a function of a board-specific characteristic
3599 such as which speed oscillator is used, it belongs in the board
3600 config file instead.
3601 In both cases it's safest to also set the initial JTAG clock rate
3602 to that same slow speed, so that OpenOCD never starts up using a
3603 clock speed that's faster than the scan chain can support.
3607 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3610 If your system supports adaptive clocking (RTCK), configuring
3611 JTAG to use that is probably the most robust approach.
3612 However, it introduces delays to synchronize clocks; so it
3613 may not be the fastest solution.
3615 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3616 instead of @command{adapter speed}, but only for (ARM) cores and boards
3617 which support adaptive clocking.
3619 @deffn {Command} {adapter speed} max_speed_kHz
3620 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3621 JTAG interfaces usually support a limited number of
3622 speeds. The speed actually used won't be faster
3623 than the speed specified.
3625 Chip data sheets generally include a top JTAG clock rate.
3626 The actual rate is often a function of a CPU core clock,
3627 and is normally less than that peak rate.
3628 For example, most ARM cores accept at most one sixth of the CPU clock.
3630 Speed 0 (khz) selects RTCK method.
3631 @xref{faqrtck,,FAQ RTCK}.
3632 If your system uses RTCK, you won't need to change the
3633 JTAG clocking after setup.
3634 Not all interfaces, boards, or targets support ``rtck''.
3635 If the interface device can not
3636 support it, an error is returned when you try to use RTCK.
3639 @defun jtag_rclk fallback_speed_kHz
3640 @cindex adaptive clocking
3642 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3643 If that fails (maybe the interface, board, or target doesn't
3644 support it), falls back to the specified frequency.
3646 # Fall back to 3mhz if RTCK is not supported
3651 @node Reset Configuration
3652 @chapter Reset Configuration
3653 @cindex Reset Configuration
3655 Every system configuration may require a different reset
3656 configuration. This can also be quite confusing.
3657 Resets also interact with @var{reset-init} event handlers,
3658 which do things like setting up clocks and DRAM, and
3659 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3660 They can also interact with JTAG routers.
3661 Please see the various board files for examples.
3664 To maintainers and integrators:
3665 Reset configuration touches several things at once.
3666 Normally the board configuration file
3667 should define it and assume that the JTAG adapter supports
3668 everything that's wired up to the board's JTAG connector.
3670 However, the target configuration file could also make note
3671 of something the silicon vendor has done inside the chip,
3672 which will be true for most (or all) boards using that chip.
3673 And when the JTAG adapter doesn't support everything, the
3674 user configuration file will need to override parts of
3675 the reset configuration provided by other files.
3678 @section Types of Reset
3680 There are many kinds of reset possible through JTAG, but
3681 they may not all work with a given board and adapter.
3682 That's part of why reset configuration can be error prone.
3686 @emph{System Reset} ... the @emph{SRST} hardware signal
3687 resets all chips connected to the JTAG adapter, such as processors,
3688 power management chips, and I/O controllers. Normally resets triggered
3689 with this signal behave exactly like pressing a RESET button.
3691 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3692 just the TAP controllers connected to the JTAG adapter.
3693 Such resets should not be visible to the rest of the system; resetting a
3694 device's TAP controller just puts that controller into a known state.
3696 @emph{Emulation Reset} ... many devices can be reset through JTAG
3697 commands. These resets are often distinguishable from system
3698 resets, either explicitly (a "reset reason" register says so)
3699 or implicitly (not all parts of the chip get reset).
3701 @emph{Other Resets} ... system-on-chip devices often support
3702 several other types of reset.
3703 You may need to arrange that a watchdog timer stops
3704 while debugging, preventing a watchdog reset.
3705 There may be individual module resets.
3708 In the best case, OpenOCD can hold SRST, then reset
3709 the TAPs via TRST and send commands through JTAG to halt the
3710 CPU at the reset vector before the 1st instruction is executed.
3711 Then when it finally releases the SRST signal, the system is
3712 halted under debugger control before any code has executed.
3713 This is the behavior required to support the @command{reset halt}
3714 and @command{reset init} commands; after @command{reset init} a
3715 board-specific script might do things like setting up DRAM.
3716 (@xref{resetcommand,,Reset Command}.)
3718 @anchor{srstandtrstissues}
3719 @section SRST and TRST Issues
3721 Because SRST and TRST are hardware signals, they can have a
3722 variety of system-specific constraints. Some of the most
3727 @item @emph{Signal not available} ... Some boards don't wire
3728 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3729 support such signals even if they are wired up.
3730 Use the @command{reset_config} @var{signals} options to say
3731 when either of those signals is not connected.
3732 When SRST is not available, your code might not be able to rely
3733 on controllers having been fully reset during code startup.
3734 Missing TRST is not a problem, since JTAG-level resets can
3735 be triggered using with TMS signaling.
3737 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3738 adapter will connect SRST to TRST, instead of keeping them separate.
3739 Use the @command{reset_config} @var{combination} options to say
3740 when those signals aren't properly independent.
3742 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3743 delay circuit, reset supervisor, or on-chip features can extend
3744 the effect of a JTAG adapter's reset for some time after the adapter
3745 stops issuing the reset. For example, there may be chip or board
3746 requirements that all reset pulses last for at least a
3747 certain amount of time; and reset buttons commonly have
3748 hardware debouncing.
3749 Use the @command{adapter srst delay} and @command{jtag_ntrst_delay}
3750 commands to say when extra delays are needed.
3752 @item @emph{Drive type} ... Reset lines often have a pullup
3753 resistor, letting the JTAG interface treat them as open-drain
3754 signals. But that's not a requirement, so the adapter may need
3755 to use push/pull output drivers.
3756 Also, with weak pullups it may be advisable to drive
3757 signals to both levels (push/pull) to minimize rise times.
3758 Use the @command{reset_config} @var{trst_type} and
3759 @var{srst_type} parameters to say how to drive reset signals.
3761 @item @emph{Special initialization} ... Targets sometimes need
3762 special JTAG initialization sequences to handle chip-specific
3763 issues (not limited to errata).
3764 For example, certain JTAG commands might need to be issued while
3765 the system as a whole is in a reset state (SRST active)
3766 but the JTAG scan chain is usable (TRST inactive).
3767 Many systems treat combined assertion of SRST and TRST as a
3768 trigger for a harder reset than SRST alone.
3769 Such custom reset handling is discussed later in this chapter.
3772 There can also be other issues.
3773 Some devices don't fully conform to the JTAG specifications.
3774 Trivial system-specific differences are common, such as
3775 SRST and TRST using slightly different names.
3776 There are also vendors who distribute key JTAG documentation for
3777 their chips only to developers who have signed a Non-Disclosure
3780 Sometimes there are chip-specific extensions like a requirement to use
3781 the normally-optional TRST signal (precluding use of JTAG adapters which
3782 don't pass TRST through), or needing extra steps to complete a TAP reset.
3784 In short, SRST and especially TRST handling may be very finicky,
3785 needing to cope with both architecture and board specific constraints.
3787 @section Commands for Handling Resets
3789 @deffn {Command} {adapter srst pulse_width} milliseconds
3790 Minimum amount of time (in milliseconds) OpenOCD should wait
3791 after asserting nSRST (active-low system reset) before
3792 allowing it to be deasserted.
3795 @deffn {Command} {adapter srst delay} milliseconds
3796 How long (in milliseconds) OpenOCD should wait after deasserting
3797 nSRST (active-low system reset) before starting new JTAG operations.
3798 When a board has a reset button connected to SRST line it will
3799 probably have hardware debouncing, implying you should use this.
3802 @deffn {Command} {jtag_ntrst_assert_width} milliseconds
3803 Minimum amount of time (in milliseconds) OpenOCD should wait
3804 after asserting nTRST (active-low JTAG TAP reset) before
3805 allowing it to be deasserted.
3808 @deffn {Command} {jtag_ntrst_delay} milliseconds
3809 How long (in milliseconds) OpenOCD should wait after deasserting
3810 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3813 @anchor{reset_config}
3814 @deffn {Command} {reset_config} mode_flag ...
3815 This command displays or modifies the reset configuration
3816 of your combination of JTAG board and target in target
3817 configuration scripts.
3819 Information earlier in this section describes the kind of problems
3820 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3821 As a rule this command belongs only in board config files,
3822 describing issues like @emph{board doesn't connect TRST};
3823 or in user config files, addressing limitations derived
3824 from a particular combination of interface and board.
3825 (An unlikely example would be using a TRST-only adapter
3826 with a board that only wires up SRST.)
3828 The @var{mode_flag} options can be specified in any order, but only one
3829 of each type -- @var{signals}, @var{combination}, @var{gates},
3830 @var{trst_type}, @var{srst_type} and @var{connect_type}
3831 -- may be specified at a time.
3832 If you don't provide a new value for a given type, its previous
3833 value (perhaps the default) is unchanged.
3834 For example, this means that you don't need to say anything at all about
3835 TRST just to declare that if the JTAG adapter should want to drive SRST,
3836 it must explicitly be driven high (@option{srst_push_pull}).
3840 @var{signals} can specify which of the reset signals are connected.
3841 For example, If the JTAG interface provides SRST, but the board doesn't
3842 connect that signal properly, then OpenOCD can't use it.
3843 Possible values are @option{none} (the default), @option{trst_only},
3844 @option{srst_only} and @option{trst_and_srst}.
3847 If your board provides SRST and/or TRST through the JTAG connector,
3848 you must declare that so those signals can be used.
3852 The @var{combination} is an optional value specifying broken reset
3853 signal implementations.
3854 The default behaviour if no option given is @option{separate},
3855 indicating everything behaves normally.
3856 @option{srst_pulls_trst} states that the
3857 test logic is reset together with the reset of the system (e.g. NXP
3858 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3859 the system is reset together with the test logic (only hypothetical, I
3860 haven't seen hardware with such a bug, and can be worked around).
3861 @option{combined} implies both @option{srst_pulls_trst} and
3862 @option{trst_pulls_srst}.
3865 The @var{gates} tokens control flags that describe some cases where
3866 JTAG may be unavailable during reset.
3867 @option{srst_gates_jtag} (default)
3868 indicates that asserting SRST gates the
3869 JTAG clock. This means that no communication can happen on JTAG
3870 while SRST is asserted.
3871 Its converse is @option{srst_nogate}, indicating that JTAG commands
3872 can safely be issued while SRST is active.
3875 The @var{connect_type} tokens control flags that describe some cases where
3876 SRST is asserted while connecting to the target. @option{srst_nogate}
3877 is required to use this option.
3878 @option{connect_deassert_srst} (default)
3879 indicates that SRST will not be asserted while connecting to the target.
3880 Its converse is @option{connect_assert_srst}, indicating that SRST will
3881 be asserted before any target connection.
3882 Only some targets support this feature, STM32 and STR9 are examples.
3883 This feature is useful if you are unable to connect to your target due
3884 to incorrect options byte config or illegal program execution.
3887 The optional @var{trst_type} and @var{srst_type} parameters allow the
3888 driver mode of each reset line to be specified. These values only affect
3889 JTAG interfaces with support for different driver modes, like the Amontec
3890 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3891 relevant signal (TRST or SRST) is not connected.
3895 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3896 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3897 Most boards connect this signal to a pulldown, so the JTAG TAPs
3898 never leave reset unless they are hooked up to a JTAG adapter.
3901 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3902 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3903 Most boards connect this signal to a pullup, and allow the
3904 signal to be pulled low by various events including system
3905 power-up and pressing a reset button.
3909 @section Custom Reset Handling
3912 OpenOCD has several ways to help support the various reset
3913 mechanisms provided by chip and board vendors.
3914 The commands shown in the previous section give standard parameters.
3915 There are also @emph{event handlers} associated with TAPs or Targets.
3916 Those handlers are Tcl procedures you can provide, which are invoked
3917 at particular points in the reset sequence.
3919 @emph{When SRST is not an option} you must set
3920 up a @code{reset-assert} event handler for your target.
3921 For example, some JTAG adapters don't include the SRST signal;
3922 and some boards have multiple targets, and you won't always
3923 want to reset everything at once.
3925 After configuring those mechanisms, you might still
3926 find your board doesn't start up or reset correctly.
3927 For example, maybe it needs a slightly different sequence
3928 of SRST and/or TRST manipulations, because of quirks that
3929 the @command{reset_config} mechanism doesn't address;
3930 or asserting both might trigger a stronger reset, which
3931 needs special attention.
3933 Experiment with lower level operations, such as
3934 @command{adapter assert}, @command{adapter deassert}
3935 and the @command{jtag arp_*} operations shown here,
3936 to find a sequence of operations that works.
3937 @xref{JTAG Commands}.
3938 When you find a working sequence, it can be used to override
3939 @command{jtag_init}, which fires during OpenOCD startup
3940 (@pxref{configurationstage,,Configuration Stage});
3941 or @command{init_reset}, which fires during reset processing.
3943 You might also want to provide some project-specific reset
3944 schemes. For example, on a multi-target board the standard
3945 @command{reset} command would reset all targets, but you
3946 may need the ability to reset only one target at time and
3947 thus want to avoid using the board-wide SRST signal.
3949 @deffn {Overridable Procedure} {init_reset} mode
3950 This is invoked near the beginning of the @command{reset} command,
3951 usually to provide as much of a cold (power-up) reset as practical.
3952 By default it is also invoked from @command{jtag_init} if
3953 the scan chain does not respond to pure JTAG operations.
3954 The @var{mode} parameter is the parameter given to the
3955 low level reset command (@option{halt},
3956 @option{init}, or @option{run}), @option{setup},
3957 or potentially some other value.
3959 The default implementation just invokes @command{jtag arp_init-reset}.
3960 Replacements will normally build on low level JTAG
3961 operations such as @command{adapter assert} and @command{adapter deassert}.
3962 Operations here must not address individual TAPs
3963 (or their associated targets)
3964 until the JTAG scan chain has first been verified to work.
3966 Implementations must have verified the JTAG scan chain before
3968 This is done by calling @command{jtag arp_init}
3969 (or @command{jtag arp_init-reset}).
3972 @deffn {Command} {jtag arp_init}
3973 This validates the scan chain using just the four
3974 standard JTAG signals (TMS, TCK, TDI, TDO).
3975 It starts by issuing a JTAG-only reset.
3976 Then it performs checks to verify that the scan chain configuration
3977 matches the TAPs it can observe.
3978 Those checks include checking IDCODE values for each active TAP,
3979 and verifying the length of their instruction registers using
3980 TAP @code{-ircapture} and @code{-irmask} values.
3981 If these tests all pass, TAP @code{setup} events are
3982 issued to all TAPs with handlers for that event.
3985 @deffn {Command} {jtag arp_init-reset}
3986 This uses TRST and SRST to try resetting
3987 everything on the JTAG scan chain
3988 (and anything else connected to SRST).
3989 It then invokes the logic of @command{jtag arp_init}.
3993 @node TAP Declaration
3994 @chapter TAP Declaration
3995 @cindex TAP declaration
3996 @cindex TAP configuration
3998 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3999 TAPs serve many roles, including:
4002 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
4003 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
4004 Others do it indirectly, making a CPU do it.
4005 @item @b{Program Download} Using the same CPU support GDB uses,
4006 you can initialize a DRAM controller, download code to DRAM, and then
4007 start running that code.
4008 @item @b{Boundary Scan} Most chips support boundary scan, which
4009 helps test for board assembly problems like solder bridges
4010 and missing connections.
4013 OpenOCD must know about the active TAPs on your board(s).
4014 Setting up the TAPs is the core task of your configuration files.
4015 Once those TAPs are set up, you can pass their names to code
4016 which sets up CPUs and exports them as GDB targets,
4017 probes flash memory, performs low-level JTAG operations, and more.
4019 @section Scan Chains
4022 TAPs are part of a hardware @dfn{scan chain},
4023 which is a daisy chain of TAPs.
4024 They also need to be added to
4025 OpenOCD's software mirror of that hardware list,
4026 giving each member a name and associating other data with it.
4027 Simple scan chains, with a single TAP, are common in
4028 systems with a single microcontroller or microprocessor.
4029 More complex chips may have several TAPs internally.
4030 Very complex scan chains might have a dozen or more TAPs:
4031 several in one chip, more in the next, and connecting
4032 to other boards with their own chips and TAPs.
4034 You can display the list with the @command{scan_chain} command.
4035 (Don't confuse this with the list displayed by the @command{targets}
4036 command, presented in the next chapter.
4037 That only displays TAPs for CPUs which are configured as
4039 Here's what the scan chain might look like for a chip more than one TAP:
4042 TapName Enabled IdCode Expected IrLen IrCap IrMask
4043 -- ------------------ ------- ---------- ---------- ----- ----- ------
4044 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
4045 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
4046 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
4049 OpenOCD can detect some of that information, but not all
4050 of it. @xref{autoprobing,,Autoprobing}.
4051 Unfortunately, those TAPs can't always be autoconfigured,
4052 because not all devices provide good support for that.
4053 JTAG doesn't require supporting IDCODE instructions, and
4054 chips with JTAG routers may not link TAPs into the chain
4055 until they are told to do so.
4057 The configuration mechanism currently supported by OpenOCD
4058 requires explicit configuration of all TAP devices using
4059 @command{jtag newtap} commands, as detailed later in this chapter.
4060 A command like this would declare one tap and name it @code{chip1.cpu}:
4063 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
4066 Each target configuration file lists the TAPs provided
4068 Board configuration files combine all the targets on a board,
4070 Note that @emph{the order in which TAPs are declared is very important.}
4071 That declaration order must match the order in the JTAG scan chain,
4072 both inside a single chip and between them.
4073 @xref{faqtaporder,,FAQ TAP Order}.
4075 For example, the STMicroelectronics STR912 chip has
4076 three separate TAPs@footnote{See the ST
4077 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
4078 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
4079 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
4080 To configure those taps, @file{target/str912.cfg}
4081 includes commands something like this:
4084 jtag newtap str912 flash ... params ...
4085 jtag newtap str912 cpu ... params ...
4086 jtag newtap str912 bs ... params ...
4089 Actual config files typically use a variable such as @code{$_CHIPNAME}
4090 instead of literals like @option{str912}, to support more than one chip
4091 of each type. @xref{Config File Guidelines}.
4093 @deffn {Command} {jtag names}
4094 Returns the names of all current TAPs in the scan chain.
4095 Use @command{jtag cget} or @command{jtag tapisenabled}
4096 to examine attributes and state of each TAP.
4098 foreach t [jtag names] @{
4099 puts [format "TAP: %s\n" $t]
4104 @deffn {Command} {scan_chain}
4105 Displays the TAPs in the scan chain configuration,
4107 The set of TAPs listed by this command is fixed by
4108 exiting the OpenOCD configuration stage,
4109 but systems with a JTAG router can
4110 enable or disable TAPs dynamically.
4113 @c FIXME! "jtag cget" should be able to return all TAP
4114 @c attributes, like "$target_name cget" does for targets.
4116 @c Probably want "jtag eventlist", and a "tap-reset" event
4117 @c (on entry to RESET state).
4122 When TAP objects are declared with @command{jtag newtap},
4123 a @dfn{dotted.name} is created for the TAP, combining the
4124 name of a module (usually a chip) and a label for the TAP.
4125 For example: @code{xilinx.tap}, @code{str912.flash},
4126 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
4127 Many other commands use that dotted.name to manipulate or
4128 refer to the TAP. For example, CPU configuration uses the
4129 name, as does declaration of NAND or NOR flash banks.
4131 The components of a dotted name should follow ``C'' symbol
4132 name rules: start with an alphabetic character, then numbers
4133 and underscores are OK; while others (including dots!) are not.
4135 @section TAP Declaration Commands
4137 @deffn {Config Command} {jtag newtap} chipname tapname configparams...
4138 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
4139 and configured according to the various @var{configparams}.
4141 The @var{chipname} is a symbolic name for the chip.
4142 Conventionally target config files use @code{$_CHIPNAME},
4143 defaulting to the model name given by the chip vendor but
4146 @cindex TAP naming convention
4147 The @var{tapname} reflects the role of that TAP,
4148 and should follow this convention:
4151 @item @code{bs} -- For boundary scan if this is a separate TAP;
4152 @item @code{cpu} -- The main CPU of the chip, alternatively
4153 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
4154 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
4155 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
4156 @item @code{flash} -- If the chip has a flash TAP, like the str912;
4157 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
4158 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
4159 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
4161 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
4162 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
4163 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
4164 a JTAG TAP; that TAP should be named @code{sdma}.
4167 Every TAP requires at least the following @var{configparams}:
4170 @item @code{-irlen} @var{NUMBER}
4171 @*The length in bits of the
4172 instruction register, such as 4 or 5 bits.
4175 A TAP may also provide optional @var{configparams}:
4178 @item @code{-disable} (or @code{-enable})
4179 @*Use the @code{-disable} parameter to flag a TAP which is not
4180 linked into the scan chain after a reset using either TRST
4181 or the JTAG state machine's @sc{reset} state.
4182 You may use @code{-enable} to highlight the default state
4183 (the TAP is linked in).
4184 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
4185 @item @code{-expected-id} @var{NUMBER}
4186 @*A non-zero @var{number} represents a 32-bit IDCODE
4187 which you expect to find when the scan chain is examined.
4188 These codes are not required by all JTAG devices.
4189 @emph{Repeat the option} as many times as required if more than one
4190 ID code could appear (for example, multiple versions).
4191 Specify @var{number} as zero to suppress warnings about IDCODE
4192 values that were found but not included in the list.
4194 Provide this value if at all possible, since it lets OpenOCD
4195 tell when the scan chain it sees isn't right. These values
4196 are provided in vendors' chip documentation, usually a technical
4197 reference manual. Sometimes you may need to probe the JTAG
4198 hardware to find these values.
4199 @xref{autoprobing,,Autoprobing}.
4200 @item @code{-ignore-version}
4201 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
4202 option. When vendors put out multiple versions of a chip, or use the same
4203 JTAG-level ID for several largely-compatible chips, it may be more practical
4204 to ignore the version field than to update config files to handle all of
4205 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
4206 @item @code{-ignore-bypass}
4207 @*Specify this to ignore the 'bypass' bit of the idcode. Some vendor put
4208 an invalid idcode regarding this bit. Specify this to ignore this bit and
4209 to not consider this tap in bypass mode.
4210 @item @code{-ircapture} @var{NUMBER}
4211 @*The bit pattern loaded by the TAP into the JTAG shift register
4212 on entry to the @sc{ircapture} state, such as 0x01.
4213 JTAG requires the two LSBs of this value to be 01.
4214 By default, @code{-ircapture} and @code{-irmask} are set
4215 up to verify that two-bit value. You may provide
4216 additional bits if you know them, or indicate that
4217 a TAP doesn't conform to the JTAG specification.
4218 @item @code{-irmask} @var{NUMBER}
4219 @*A mask used with @code{-ircapture}
4220 to verify that instruction scans work correctly.
4221 Such scans are not used by OpenOCD except to verify that
4222 there seems to be no problems with JTAG scan chain operations.
4223 @item @code{-ignore-syspwrupack}
4224 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4225 register during initial examination and when checking the sticky error bit.
4226 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4227 devices do not set the ack bit until sometime later.
4231 @section Other TAP commands
4233 @deffn {Command} {jtag cget} dotted.name @option{-idcode}
4234 Get the value of the IDCODE found in hardware.
4237 @deffn {Command} {jtag cget} dotted.name @option{-event} event_name
4238 @deffnx {Command} {jtag configure} dotted.name @option{-event} event_name handler
4239 At this writing this TAP attribute
4240 mechanism is limited and used mostly for event handling.
4241 (It is not a direct analogue of the @code{cget}/@code{configure}
4242 mechanism for debugger targets.)
4243 See the next section for information about the available events.
4245 The @code{configure} subcommand assigns an event handler,
4246 a TCL string which is evaluated when the event is triggered.
4247 The @code{cget} subcommand returns that handler.
4254 OpenOCD includes two event mechanisms.
4255 The one presented here applies to all JTAG TAPs.
4256 The other applies to debugger targets,
4257 which are associated with certain TAPs.
4259 The TAP events currently defined are:
4262 @item @b{post-reset}
4263 @* The TAP has just completed a JTAG reset.
4264 The tap may still be in the JTAG @sc{reset} state.
4265 Handlers for these events might perform initialization sequences
4266 such as issuing TCK cycles, TMS sequences to ensure
4267 exit from the ARM SWD mode, and more.
4269 Because the scan chain has not yet been verified, handlers for these events
4270 @emph{should not issue commands which scan the JTAG IR or DR registers}
4271 of any particular target.
4272 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
4274 @* The scan chain has been reset and verified.
4275 This handler may enable TAPs as needed.
4276 @item @b{tap-disable}
4277 @* The TAP needs to be disabled. This handler should
4278 implement @command{jtag tapdisable}
4279 by issuing the relevant JTAG commands.
4280 @item @b{tap-enable}
4281 @* The TAP needs to be enabled. This handler should
4282 implement @command{jtag tapenable}
4283 by issuing the relevant JTAG commands.
4286 If you need some action after each JTAG reset which isn't actually
4287 specific to any TAP (since you can't yet trust the scan chain's
4288 contents to be accurate), you might:
4291 jtag configure CHIP.jrc -event post-reset @{
4292 echo "JTAG Reset done"
4293 ... non-scan jtag operations to be done after reset
4298 @anchor{enablinganddisablingtaps}
4299 @section Enabling and Disabling TAPs
4300 @cindex JTAG Route Controller
4303 In some systems, a @dfn{JTAG Route Controller} (JRC)
4304 is used to enable and/or disable specific JTAG TAPs.
4305 Many ARM-based chips from Texas Instruments include
4306 an ``ICEPick'' module, which is a JRC.
4307 Such chips include DaVinci and OMAP3 processors.
4309 A given TAP may not be visible until the JRC has been
4310 told to link it into the scan chain; and if the JRC
4311 has been told to unlink that TAP, it will no longer
4313 Such routers address problems that JTAG ``bypass mode''
4317 @item The scan chain can only go as fast as its slowest TAP.
4318 @item Having many TAPs slows instruction scans, since all
4319 TAPs receive new instructions.
4320 @item TAPs in the scan chain must be powered up, which wastes
4321 power and prevents debugging some power management mechanisms.
4324 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
4325 as implied by the existence of JTAG routers.
4326 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
4327 does include a kind of JTAG router functionality.
4329 @c (a) currently the event handlers don't seem to be able to
4330 @c fail in a way that could lead to no-change-of-state.
4332 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
4333 shown below, and is implemented using TAP event handlers.
4334 So for example, when defining a TAP for a CPU connected to
4335 a JTAG router, your @file{target.cfg} file
4336 should define TAP event handlers using
4337 code that looks something like this:
4340 jtag configure CHIP.cpu -event tap-enable @{
4341 ... jtag operations using CHIP.jrc
4343 jtag configure CHIP.cpu -event tap-disable @{
4344 ... jtag operations using CHIP.jrc
4348 Then you might want that CPU's TAP enabled almost all the time:
4351 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
4354 Note how that particular setup event handler declaration
4355 uses quotes to evaluate @code{$CHIP} when the event is configured.
4356 Using brackets @{ @} would cause it to be evaluated later,
4357 at runtime, when it might have a different value.
4359 @deffn {Command} {jtag tapdisable} dotted.name
4360 If necessary, disables the tap
4361 by sending it a @option{tap-disable} event.
4362 Returns the string "1" if the tap
4363 specified by @var{dotted.name} is enabled,
4364 and "0" if it is disabled.
4367 @deffn {Command} {jtag tapenable} dotted.name
4368 If necessary, enables the tap
4369 by sending it a @option{tap-enable} event.
4370 Returns the string "1" if the tap
4371 specified by @var{dotted.name} is enabled,
4372 and "0" if it is disabled.
4375 @deffn {Command} {jtag tapisenabled} dotted.name
4376 Returns the string "1" if the tap
4377 specified by @var{dotted.name} is enabled,
4378 and "0" if it is disabled.
4381 Humans will find the @command{scan_chain} command more helpful
4382 for querying the state of the JTAG taps.
4386 @anchor{autoprobing}
4387 @section Autoprobing
4389 @cindex JTAG autoprobe
4391 TAP configuration is the first thing that needs to be done
4392 after interface and reset configuration. Sometimes it's
4393 hard finding out what TAPs exist, or how they are identified.
4394 Vendor documentation is not always easy to find and use.
4396 To help you get past such problems, OpenOCD has a limited
4397 @emph{autoprobing} ability to look at the scan chain, doing
4398 a @dfn{blind interrogation} and then reporting the TAPs it finds.
4399 To use this mechanism, start the OpenOCD server with only data
4400 that configures your JTAG interface, and arranges to come up
4401 with a slow clock (many devices don't support fast JTAG clocks
4402 right when they come out of reset).
4404 For example, your @file{openocd.cfg} file might have:
4407 source [find interface/olimex-arm-usb-tiny-h.cfg]
4408 reset_config trst_and_srst
4412 When you start the server without any TAPs configured, it will
4413 attempt to autoconfigure the TAPs. There are two parts to this:
4416 @item @emph{TAP discovery} ...
4417 After a JTAG reset (sometimes a system reset may be needed too),
4418 each TAP's data registers will hold the contents of either the
4419 IDCODE or BYPASS register.
4420 If JTAG communication is working, OpenOCD will see each TAP,
4421 and report what @option{-expected-id} to use with it.
4422 @item @emph{IR Length discovery} ...
4423 Unfortunately JTAG does not provide a reliable way to find out
4424 the value of the @option{-irlen} parameter to use with a TAP
4426 If OpenOCD can discover the length of a TAP's instruction
4427 register, it will report it.
4428 Otherwise you may need to consult vendor documentation, such
4429 as chip data sheets or BSDL files.
4432 In many cases your board will have a simple scan chain with just
4433 a single device. Here's what OpenOCD reported with one board
4434 that's a bit more complex:
4438 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4439 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4440 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4441 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4442 AUTO auto0.tap - use "... -irlen 4"
4443 AUTO auto1.tap - use "... -irlen 4"
4444 AUTO auto2.tap - use "... -irlen 6"
4445 no gdb ports allocated as no target has been specified
4448 Given that information, you should be able to either find some existing
4449 config files to use, or create your own. If you create your own, you
4450 would configure from the bottom up: first a @file{target.cfg} file
4451 with these TAPs, any targets associated with them, and any on-chip
4452 resources; then a @file{board.cfg} with off-chip resources, clocking,
4455 @anchor{dapdeclaration}
4456 @section DAP declaration (ARMv6-M, ARMv7 and ARMv8 targets)
4457 @cindex DAP declaration
4459 Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is
4460 no longer implicitly created together with the target. It must be
4461 explicitly declared using the @command{dap create} command. For all ARMv6-M, ARMv7
4462 and ARMv8 targets, the option "@option{-dap} @var{dap_name}" has to be used
4463 instead of "@option{-chain-position} @var{dotted.name}" when the target is created.
4465 The @command{dap} command group supports the following sub-commands:
4468 @deffn {Command} {dap create} dap_name @option{-chain-position} dotted.name configparams...
4469 Declare a DAP instance named @var{dap_name} linked to the JTAG tap
4470 @var{dotted.name}. This also creates a new command (@command{dap_name})
4471 which is used for various purposes including additional configuration.
4472 There can only be one DAP for each JTAG tap in the system.
4474 A DAP may also provide optional @var{configparams}:
4477 @item @code{-ignore-syspwrupack}
4478 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4479 register during initial examination and when checking the sticky error bit.
4480 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4481 devices do not set the ack bit until sometime later.
4483 @item @code{-dp-id} @var{number}
4484 @*Debug port identification number for SWD DPv2 multidrop.
4485 The @var{number} is written to bits 0..27 of DP TARGETSEL during DP selection.
4486 To find the id number of a single connected device read DP TARGETID:
4487 @code{device.dap dpreg 0x24}
4488 Use bits 0..27 of TARGETID.
4490 @item @code{-instance-id} @var{number}
4491 @*Instance identification number for SWD DPv2 multidrop.
4492 The @var{number} is written to bits 28..31 of DP TARGETSEL during DP selection.
4493 To find the instance number of a single connected device read DP DLPIDR:
4494 @code{device.dap dpreg 0x34}
4495 The instance number is in bits 28..31 of DLPIDR value.
4499 @deffn {Command} {dap names}
4500 This command returns a list of all registered DAP objects. It it useful mainly
4504 @deffn {Command} {dap info} [num]
4505 Displays the ROM table for MEM-AP @var{num},
4506 defaulting to the currently selected AP of the currently selected target.
4509 @deffn {Command} {dap init}
4510 Initialize all registered DAPs. This command is used internally
4511 during initialization. It can be issued at any time after the
4512 initialization, too.
4515 The following commands exist as subcommands of DAP instances:
4517 @deffn {Command} {$dap_name info} [num]
4518 Displays the ROM table for MEM-AP @var{num},
4519 defaulting to the currently selected AP.
4522 @deffn {Command} {$dap_name apid} [num]
4523 Displays ID register from AP @var{num}, defaulting to the currently selected AP.
4526 @anchor{DAP subcommand apreg}
4527 @deffn {Command} {$dap_name apreg} ap_num reg [value]
4528 Displays content of a register @var{reg} from AP @var{ap_num}
4529 or set a new value @var{value}.
4530 @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
4533 @deffn {Command} {$dap_name apsel} [num]
4534 Select AP @var{num}, defaulting to 0.
4537 @deffn {Command} {$dap_name dpreg} reg [value]
4538 Displays the content of DP register at address @var{reg}, or set it to a new
4541 In case of SWD, @var{reg} is a value in packed format
4542 @math{dpbanksel << 4 | addr} and assumes values 0, 4, 8 ... 0xfc.
4543 In case of JTAG it only assumes values 0, 4, 8 and 0xc.
4545 @emph{Note:} Consider using @command{poll off} to avoid any disturbing
4546 background activity by OpenOCD while you are operating at such low-level.
4549 @deffn {Command} {$dap_name baseaddr} [num]
4550 Displays debug base address from MEM-AP @var{num},
4551 defaulting to the currently selected AP.
4554 @deffn {Command} {$dap_name memaccess} [value]
4555 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
4556 memory bus access [0-255], giving additional time to respond to reads.
4557 If @var{value} is defined, first assigns that.
4560 @deffn {Command} {$dap_name apcsw} [value [mask]]
4561 Displays or changes CSW bit pattern for MEM-AP transfers.
4563 At the begin of each memory access the CSW pattern is extended (bitwise or-ed)
4564 by @dfn{Size} and @dfn{AddrInc} bit-fields according to transfer requirements
4565 and the result is written to the real CSW register. All bits except dynamically
4566 updated fields @dfn{Size} and @dfn{AddrInc} can be changed by changing
4567 the CSW pattern. Refer to ARM ADI v5 manual chapter 7.6.4 and appendix A
4570 Use @var{value} only syntax if you want to set the new CSW pattern as a whole.
4571 The example sets HPROT1 bit (required by Cortex-M) and clears the rest of
4574 kx.dap apcsw 0x2000000
4577 If @var{mask} is also used, the CSW pattern is changed only on bit positions
4578 where the mask bit is 1. The following example sets HPROT3 (cacheable)
4579 and leaves the rest of the pattern intact. It configures memory access through
4580 DCache on Cortex-M7.
4582 set CSW_HPROT3_CACHEABLE [expr @{1 << 27@}]
4583 samv.dap apcsw $CSW_HPROT3_CACHEABLE $CSW_HPROT3_CACHEABLE
4586 Another example clears SPROT bit and leaves the rest of pattern intact:
4588 set CSW_SPROT [expr @{1 << 30@}]
4589 samv.dap apcsw 0 $CSW_SPROT
4592 @emph{Note:} If you want to check the real value of CSW, not CSW pattern, use
4593 @code{xxx.dap apreg 0}. @xref{DAP subcommand apreg,,}.
4595 @emph{Warning:} Some of the CSW bits are vital for working memory transfer.
4596 If you set a wrong CSW pattern and MEM-AP stopped working, use the following
4597 example with a proper dap name:
4599 xxx.dap apcsw default
4603 @deffn {Config Command} {$dap_name ti_be_32_quirks} [@option{enable}]
4604 Set/get quirks mode for TI TMS450/TMS570 processors
4609 @node CPU Configuration
4610 @chapter CPU Configuration
4613 This chapter discusses how to set up GDB debug targets for CPUs.
4614 You can also access these targets without GDB
4615 (@pxref{Architecture and Core Commands},
4616 and @ref{targetstatehandling,,Target State handling}) and
4617 through various kinds of NAND and NOR flash commands.
4618 If you have multiple CPUs you can have multiple such targets.
4620 We'll start by looking at how to examine the targets you have,
4621 then look at how to add one more target and how to configure it.
4623 @section Target List
4624 @cindex target, current
4625 @cindex target, list
4627 All targets that have been set up are part of a list,
4628 where each member has a name.
4629 That name should normally be the same as the TAP name.
4630 You can display the list with the @command{targets}
4632 This display often has only one CPU; here's what it might
4633 look like with more than one:
4635 TargetName Type Endian TapName State
4636 -- ------------------ ---------- ------ ------------------ ------------
4637 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4638 1 MyTarget cortex_m little mychip.foo tap-disabled
4641 One member of that list is the @dfn{current target}, which
4642 is implicitly referenced by many commands.
4643 It's the one marked with a @code{*} near the target name.
4644 In particular, memory addresses often refer to the address
4645 space seen by that current target.
4646 Commands like @command{mdw} (memory display words)
4647 and @command{flash erase_address} (erase NOR flash blocks)
4648 are examples; and there are many more.
4650 Several commands let you examine the list of targets:
4652 @deffn {Command} {target current}
4653 Returns the name of the current target.
4656 @deffn {Command} {target names}
4657 Lists the names of all current targets in the list.
4659 foreach t [target names] @{
4660 puts [format "Target: %s\n" $t]
4665 @c yep, "target list" would have been better.
4666 @c plus maybe "target setdefault".
4668 @deffn {Command} {targets} [name]
4669 @emph{Note: the name of this command is plural. Other target
4670 command names are singular.}
4672 With no parameter, this command displays a table of all known
4673 targets in a user friendly form.
4675 With a parameter, this command sets the current target to
4676 the given target with the given @var{name}; this is
4677 only relevant on boards which have more than one target.
4680 @section Target CPU Types
4684 Each target has a @dfn{CPU type}, as shown in the output of
4685 the @command{targets} command. You need to specify that type
4686 when calling @command{target create}.
4687 The CPU type indicates more than just the instruction set.
4688 It also indicates how that instruction set is implemented,
4689 what kind of debug support it integrates,
4690 whether it has an MMU (and if so, what kind),
4691 what core-specific commands may be available
4692 (@pxref{Architecture and Core Commands}),
4695 It's easy to see what target types are supported,
4696 since there's a command to list them.
4698 @anchor{targettypes}
4699 @deffn {Command} {target types}
4700 Lists all supported target types.
4701 At this writing, the supported CPU types are:
4704 @item @code{aarch64} -- this is an ARMv8-A core with an MMU.
4705 @item @code{arm11} -- this is a generation of ARMv6 cores.
4706 @item @code{arm720t} -- this is an ARMv4 core with an MMU.
4707 @item @code{arm7tdmi} -- this is an ARMv4 core.
4708 @item @code{arm920t} -- this is an ARMv4 core with an MMU.
4709 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU.
4710 @item @code{arm946e} -- this is an ARMv5 core with an MMU.
4711 @item @code{arm966e} -- this is an ARMv5 core.
4712 @item @code{arm9tdmi} -- this is an ARMv4 core.
4713 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4714 (Support for this is preliminary and incomplete.)
4715 @item @code{avr32_ap7k} -- this an AVR32 core.
4716 @item @code{cortex_a} -- this is an ARMv7-A core with an MMU.
4717 @item @code{cortex_m} -- this is an ARMv7-M core, supporting only the
4718 compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores
4719 @item @code{cortex_r4} -- this is an ARMv7-R core.
4720 @item @code{dragonite} -- resembles arm966e.
4721 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4722 (Support for this is still incomplete.)
4723 @item @code{dsp5680xx} -- implements Freescale's 5680x DSP.
4724 @item @code{esirisc} -- this is an EnSilica eSi-RISC core.
4725 The current implementation supports eSi-32xx cores.
4726 @item @code{fa526} -- resembles arm920 (w/o Thumb).
4727 @item @code{feroceon} -- resembles arm926.
4728 @item @code{hla_target} -- a Cortex-M alternative to work with HL adapters like ST-Link.
4729 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4730 allowing access to physical memory addresses independently of CPU cores.
4731 @item @code{mem_ap} -- this is an ARM debug infrastructure Access Port without
4732 a CPU, through which bus read and write cycles can be generated; it may be
4733 useful for working with non-CPU hardware behind an AP or during development of
4734 support for new CPUs.
4735 It's possible to connect a GDB client to this target (the GDB port has to be
4736 specified, @xref{gdbportoverride,,option -gdb-port}.), and a fake ARM core will
4737 be emulated to comply to GDB remote protocol.
4738 @item @code{mips_m4k} -- a MIPS core.
4739 @item @code{mips_mips64} -- a MIPS64 core.
4740 @item @code{nds32_v2} -- this is an Andes NDS32 v2 core (deprecated; would be removed in v0.13.0).
4741 @item @code{nds32_v3} -- this is an Andes NDS32 v3 core (deprecated; would be removed in v0.13.0).
4742 @item @code{nds32_v3m} -- this is an Andes NDS32 v3m core (deprecated; would be removed in v0.13.0).
4743 @item @code{or1k} -- this is an OpenRISC 1000 core.
4744 The current implementation supports three JTAG TAP cores:
4746 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project@comma{}jtag})
4747 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4748 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4750 And two debug interfaces cores:
4752 @item @code{Advanced debug interface}
4753 @*(See: @url{http://opencores.org/project@comma{}adv_debug_sys})
4754 @item @code{SoC Debug Interface}
4755 @*(See: @url{http://opencores.org/project@comma{}dbg_interface})
4757 @item @code{quark_d20xx} -- an Intel Quark D20xx core.
4758 @item @code{quark_x10xx} -- an Intel Quark X10xx core.
4759 @item @code{riscv} -- a RISC-V core.
4760 @item @code{stm8} -- implements an STM8 core.
4761 @item @code{testee} -- a dummy target for cases without a real CPU, e.g. CPLD.
4762 @item @code{xscale} -- this is actually an architecture,
4763 not a CPU type. It is based on the ARMv5 architecture.
4767 To avoid being confused by the variety of ARM based cores, remember
4768 this key point: @emph{ARM is a technology licencing company}.
4769 (See: @url{http://www.arm.com}.)
4770 The CPU name used by OpenOCD will reflect the CPU design that was
4771 licensed, not a vendor brand which incorporates that design.
4772 Name prefixes like arm7, arm9, arm11, and cortex
4773 reflect design generations;
4774 while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
4775 reflect an architecture version implemented by a CPU design.
4777 @anchor{targetconfiguration}
4778 @section Target Configuration
4780 Before creating a ``target'', you must have added its TAP to the scan chain.
4781 When you've added that TAP, you will have a @code{dotted.name}
4782 which is used to set up the CPU support.
4783 The chip-specific configuration file will normally configure its CPU(s)
4784 right after it adds all of the chip's TAPs to the scan chain.
4786 Although you can set up a target in one step, it's often clearer if you
4787 use shorter commands and do it in two steps: create it, then configure
4789 All operations on the target after it's created will use a new
4790 command, created as part of target creation.
4792 The two main things to configure after target creation are
4793 a work area, which usually has target-specific defaults even
4794 if the board setup code overrides them later;
4795 and event handlers (@pxref{targetevents,,Target Events}), which tend
4796 to be much more board-specific.
4797 The key steps you use might look something like this
4800 dap create mychip.dap -chain-position mychip.cpu
4801 target create MyTarget cortex_m -dap mychip.dap
4802 MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4803 MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4804 MyTarget configure -event reset-init @{ myboard_reinit @}
4807 You should specify a working area if you can; typically it uses some
4809 Such a working area can speed up many things, including bulk
4810 writes to target memory;
4811 flash operations like checking to see if memory needs to be erased;
4812 GDB memory checksumming;
4816 On more complex chips, the work area can become
4817 inaccessible when application code
4818 (such as an operating system)
4819 enables or disables the MMU.
4820 For example, the particular MMU context used to access the virtual
4821 address will probably matter ... and that context might not have
4822 easy access to other addresses needed.
4823 At this writing, OpenOCD doesn't have much MMU intelligence.
4826 It's often very useful to define a @code{reset-init} event handler.
4827 For systems that are normally used with a boot loader,
4828 common tasks include updating clocks and initializing memory
4830 That may be needed to let you write the boot loader into flash,
4831 in order to ``de-brick'' your board; or to load programs into
4832 external DDR memory without having run the boot loader.
4834 @deffn {Config Command} {target create} target_name type configparams...
4835 This command creates a GDB debug target that refers to a specific JTAG tap.
4836 It enters that target into a list, and creates a new
4837 command (@command{@var{target_name}}) which is used for various
4838 purposes including additional configuration.
4841 @item @var{target_name} ... is the name of the debug target.
4842 By convention this should be the same as the @emph{dotted.name}
4843 of the TAP associated with this target, which must be specified here
4844 using the @code{-chain-position @var{dotted.name}} configparam.
4846 This name is also used to create the target object command,
4847 referred to here as @command{$target_name},
4848 and in other places the target needs to be identified.
4849 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4850 @item @var{configparams} ... all parameters accepted by
4851 @command{$target_name configure} are permitted.
4852 If the target is big-endian, set it here with @code{-endian big}.
4854 You @emph{must} set the @code{-chain-position @var{dotted.name}} or
4855 @code{-dap @var{dap_name}} here.
4859 @deffn {Command} {$target_name configure} configparams...
4860 The options accepted by this command may also be
4861 specified as parameters to @command{target create}.
4862 Their values can later be queried one at a time by
4863 using the @command{$target_name cget} command.
4865 @emph{Warning:} changing some of these after setup is dangerous.
4866 For example, moving a target from one TAP to another;
4867 and changing its endianness.
4871 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4872 used to access this target.
4874 @item @code{-dap} @var{dap_name} -- names the DAP used to access
4875 this target. @xref{dapdeclaration,,DAP declaration}, on how to
4876 create and manage DAP instances.
4878 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4879 whether the CPU uses big or little endian conventions
4881 @item @code{-event} @var{event_name} @var{event_body} --
4882 @xref{targetevents,,Target Events}.
4883 Note that this updates a list of named event handlers.
4884 Calling this twice with two different event names assigns
4885 two different handlers, but calling it twice with the
4886 same event name assigns only one handler.
4888 Current target is temporarily overridden to the event issuing target
4889 before handler code starts and switched back after handler is done.
4891 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4892 whether the work area gets backed up; by default,
4893 @emph{it is not backed up.}
4894 When possible, use a working_area that doesn't need to be backed up,
4895 since performing a backup slows down operations.
4896 For example, the beginning of an SRAM block is likely to
4897 be used by most build systems, but the end is often unused.
4899 @item @code{-work-area-size} @var{size} -- specify work are size,
4900 in bytes. The same size applies regardless of whether its physical
4901 or virtual address is being used.
4903 @item @code{-work-area-phys} @var{address} -- set the work area
4904 base @var{address} to be used when no MMU is active.
4906 @item @code{-work-area-virt} @var{address} -- set the work area
4907 base @var{address} to be used when an MMU is active.
4908 @emph{Do not specify a value for this except on targets with an MMU.}
4909 The value should normally correspond to a static mapping for the
4910 @code{-work-area-phys} address, set up by the current operating system.
4913 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4914 @var{rtos_type} can be one of @option{auto}, @option{eCos},
4915 @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
4916 @option{embKernel}, @option{mqx}, @option{uCOS-III}, @option{nuttx},
4917 @option{RIOT}, @option{Zephyr}
4918 @xref{gdbrtossupport,,RTOS Support}.
4920 @item @code{-defer-examine} -- skip target examination at initial JTAG chain
4921 scan and after a reset. A manual call to arp_examine is required to
4922 access the target for debugging.
4924 @item @code{-ap-num} @var{ap_number} -- set DAP access port for target,
4925 @var{ap_number} is the numeric index of the DAP AP the target is connected to.
4926 Use this option with systems where multiple, independent cores are connected
4927 to separate access ports of the same DAP.
4929 @item @code{-cti} @var{cti_name} -- set Cross-Trigger Interface (CTI) connected
4930 to the target. Currently, only the @code{aarch64} target makes use of this option,
4931 where it is a mandatory configuration for the target run control.
4932 @xref{armcrosstrigger,,ARM Cross-Trigger Interface},
4933 for instruction on how to declare and control a CTI instance.
4935 @anchor{gdbportoverride}
4936 @item @code{-gdb-port} @var{number} -- see command @command{gdb_port} for the
4937 possible values of the parameter @var{number}, which are not only numeric values.
4938 Use this option to override, for this target only, the global parameter set with
4939 command @command{gdb_port}.
4940 @xref{gdb_port,,command gdb_port}.
4942 @item @code{-gdb-max-connections} @var{number} -- EXPERIMENTAL: set the maximum
4943 number of GDB connections that are allowed for the target. Default is 1.
4944 A negative value for @var{number} means unlimited connections.
4945 See @xref{gdbmeminspect,,Using GDB as a non-intrusive memory inspector}.
4949 @section Other $target_name Commands
4950 @cindex object command
4952 The Tcl/Tk language has the concept of object commands,
4953 and OpenOCD adopts that same model for targets.
4955 A good Tk example is a on screen button.
4956 Once a button is created a button
4957 has a name (a path in Tk terms) and that name is useable as a first
4958 class command. For example in Tk, one can create a button and later
4959 configure it like this:
4963 button .foobar -background red -command @{ foo @}
4965 .foobar configure -foreground blue
4967 set x [.foobar cget -background]
4969 puts [format "The button is %s" $x]
4972 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4973 button, and its object commands are invoked the same way.
4976 str912.cpu mww 0x1234 0x42
4977 omap3530.cpu mww 0x5555 123
4980 The commands supported by OpenOCD target objects are:
4982 @deffn {Command} {$target_name arp_examine} @option{allow-defer}
4983 @deffnx {Command} {$target_name arp_halt}
4984 @deffnx {Command} {$target_name arp_poll}
4985 @deffnx {Command} {$target_name arp_reset}
4986 @deffnx {Command} {$target_name arp_waitstate}
4987 Internal OpenOCD scripts (most notably @file{startup.tcl})
4988 use these to deal with specific reset cases.
4989 They are not otherwise documented here.
4992 @deffn {Command} {$target_name set_reg} dict
4993 Set register values of the target.
4996 @item @var{dict} ... Tcl dictionary with pairs of register names and values.
4999 For example, the following command sets the value 0 to the program counter (pc)
5000 register and 0x1000 to the stack pointer (sp) register:
5003 set_reg @{pc 0 sp 0x1000@}
5007 @deffn {Command} {$target_name get_reg} [-force] list
5008 Get register values from the target and return them as Tcl dictionary with pairs
5009 of register names and values.
5010 If option "-force" is set, the register values are read directly from the
5011 target, bypassing any caching.
5014 @item @var{list} ... List of register names
5017 For example, the following command retrieves the values from the program
5018 counter (pc) and stack pointer (sp) register:
5025 @deffn {Command} {$target_name write_memory} address width data ['phys']
5026 This function provides an efficient way to write to the target memory from a Tcl
5030 @item @var{address} ... target memory address
5031 @item @var{width} ... memory access bit size, can be 8, 16, 32 or 64
5032 @item @var{data} ... Tcl list with the elements to write
5033 @item ['phys'] ... treat the memory address as physical instead of virtual address
5036 For example, the following command writes two 32 bit words into the target
5037 memory at address 0x20000000:
5040 write_memory 0x20000000 32 @{0xdeadbeef 0x00230500@}
5044 @deffn {Command} {$target_name read_memory} address width count ['phys']
5045 This function provides an efficient way to read the target memory from a Tcl
5047 A Tcl list containing the requested memory elements is returned by this function.
5050 @item @var{address} ... target memory address
5051 @item @var{width} ... memory access bit size, can be 8, 16, 32 or 64
5052 @item @var{count} ... number of elements to read
5053 @item ['phys'] ... treat the memory address as physical instead of virtual address
5056 For example, the following command reads two 32 bit words from the target
5057 memory at address 0x20000000:
5060 read_memory 0x20000000 32 2
5064 @deffn {Command} {$target_name cget} queryparm
5065 Each configuration parameter accepted by
5066 @command{$target_name configure}
5067 can be individually queried, to return its current value.
5068 The @var{queryparm} is a parameter name
5069 accepted by that command, such as @code{-work-area-phys}.
5070 There are a few special cases:
5073 @item @code{-event} @var{event_name} -- returns the handler for the
5074 event named @var{event_name}.
5075 This is a special case because setting a handler requires
5077 @item @code{-type} -- returns the target type.
5078 This is a special case because this is set using
5079 @command{target create} and can't be changed
5080 using @command{$target_name configure}.
5083 For example, if you wanted to summarize information about
5084 all the targets you might use something like this:
5087 foreach name [target names] @{
5088 set y [$name cget -endian]
5089 set z [$name cget -type]
5090 puts [format "Chip %d is %s, Endian: %s, type: %s" \
5096 @anchor{targetcurstate}
5097 @deffn {Command} {$target_name curstate}
5098 Displays the current target state:
5099 @code{debug-running},
5102 @code{running}, or @code{unknown}.
5103 (Also, @pxref{eventpolling,,Event Polling}.)
5106 @deffn {Command} {$target_name eventlist}
5107 Displays a table listing all event handlers
5108 currently associated with this target.
5109 @xref{targetevents,,Target Events}.
5112 @deffn {Command} {$target_name invoke-event} event_name
5113 Invokes the handler for the event named @var{event_name}.
5114 (This is primarily intended for use by OpenOCD framework
5115 code, for example by the reset code in @file{startup.tcl}.)
5118 @deffn {Command} {$target_name mdd} [phys] addr [count]
5119 @deffnx {Command} {$target_name mdw} [phys] addr [count]
5120 @deffnx {Command} {$target_name mdh} [phys] addr [count]
5121 @deffnx {Command} {$target_name mdb} [phys] addr [count]
5122 Display contents of address @var{addr}, as
5123 64-bit doublewords (@command{mdd}),
5124 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
5125 or 8-bit bytes (@command{mdb}).
5126 When the current target has an MMU which is present and active,
5127 @var{addr} is interpreted as a virtual address.
5128 Otherwise, or if the optional @var{phys} flag is specified,
5129 @var{addr} is interpreted as a physical address.
5130 If @var{count} is specified, displays that many units.
5131 (If you want to process the data instead of displaying it,
5132 see the @code{read_memory} primitives.)
5135 @deffn {Command} {$target_name mwd} [phys] addr doubleword [count]
5136 @deffnx {Command} {$target_name mww} [phys] addr word [count]
5137 @deffnx {Command} {$target_name mwh} [phys] addr halfword [count]
5138 @deffnx {Command} {$target_name mwb} [phys] addr byte [count]
5139 Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
5140 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
5141 at the specified address @var{addr}.
5142 When the current target has an MMU which is present and active,
5143 @var{addr} is interpreted as a virtual address.
5144 Otherwise, or if the optional @var{phys} flag is specified,
5145 @var{addr} is interpreted as a physical address.
5146 If @var{count} is specified, fills that many units of consecutive address.
5149 @anchor{targetevents}
5150 @section Target Events
5151 @cindex target events
5153 At various times, certain things can happen, or you want them to happen.
5156 @item What should happen when GDB connects? Should your target reset?
5157 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
5158 @item Is using SRST appropriate (and possible) on your system?
5159 Or instead of that, do you need to issue JTAG commands to trigger reset?
5160 SRST usually resets everything on the scan chain, which can be inappropriate.
5161 @item During reset, do you need to write to certain memory locations
5162 to set up system clocks or
5163 to reconfigure the SDRAM?
5164 How about configuring the watchdog timer, or other peripherals,
5165 to stop running while you hold the core stopped for debugging?
5168 All of the above items can be addressed by target event handlers.
5169 These are set up by @command{$target_name configure -event} or
5170 @command{target create ... -event}.
5172 The programmer's model matches the @code{-command} option used in Tcl/Tk
5173 buttons and events. The two examples below act the same, but one creates
5174 and invokes a small procedure while the other inlines it.
5177 proc my_init_proc @{ @} @{
5178 echo "Disabling watchdog..."
5179 mww 0xfffffd44 0x00008000
5181 mychip.cpu configure -event reset-init my_init_proc
5182 mychip.cpu configure -event reset-init @{
5183 echo "Disabling watchdog..."
5184 mww 0xfffffd44 0x00008000
5188 The following target events are defined:
5191 @item @b{debug-halted}
5192 @* The target has halted for debug reasons (i.e.: breakpoint)
5193 @item @b{debug-resumed}
5194 @* The target has resumed (i.e.: GDB said run)
5195 @item @b{early-halted}
5196 @* Occurs early in the halt process
5197 @item @b{examine-start}
5198 @* Before target examine is called.
5199 @item @b{examine-end}
5200 @* After target examine is called with no errors.
5201 @item @b{examine-fail}
5202 @* After target examine fails.
5203 @item @b{gdb-attach}
5204 @* When GDB connects. Issued before any GDB communication with the target
5205 starts. GDB expects the target is halted during attachment.
5206 @xref{gdbmeminspect,,GDB as a non-intrusive memory inspector}, how to
5207 connect GDB to running target.
5208 The event can be also used to set up the target so it is possible to probe flash.
5209 Probing flash is necessary during GDB connect if you want to use
5210 @pxref{programmingusinggdb,,programming using GDB}.
5211 Another use of the flash memory map is for GDB to automatically choose
5212 hardware or software breakpoints depending on whether the breakpoint
5213 is in RAM or read only memory.
5214 Default is @code{halt}
5215 @item @b{gdb-detach}
5216 @* When GDB disconnects
5218 @* When the target has halted and GDB is not doing anything (see early halt)
5219 @item @b{gdb-flash-erase-start}
5220 @* Before the GDB flash process tries to erase the flash (default is
5222 @item @b{gdb-flash-erase-end}
5223 @* After the GDB flash process has finished erasing the flash
5224 @item @b{gdb-flash-write-start}
5225 @* Before GDB writes to the flash
5226 @item @b{gdb-flash-write-end}
5227 @* After GDB writes to the flash (default is @code{reset halt})
5229 @* Before the target steps, GDB is trying to start/resume the target
5231 @* The target has halted
5232 @item @b{reset-assert-pre}
5233 @* Issued as part of @command{reset} processing
5234 after @command{reset-start} was triggered
5235 but before either SRST alone is asserted on the scan chain,
5236 or @code{reset-assert} is triggered.
5237 @item @b{reset-assert}
5238 @* Issued as part of @command{reset} processing
5239 after @command{reset-assert-pre} was triggered.
5240 When such a handler is present, cores which support this event will use
5241 it instead of asserting SRST.
5242 This support is essential for debugging with JTAG interfaces which
5243 don't include an SRST line (JTAG doesn't require SRST), and for
5244 selective reset on scan chains that have multiple targets.
5245 @item @b{reset-assert-post}
5246 @* Issued as part of @command{reset} processing
5247 after @code{reset-assert} has been triggered.
5248 or the target asserted SRST on the entire scan chain.
5249 @item @b{reset-deassert-pre}
5250 @* Issued as part of @command{reset} processing
5251 after @code{reset-assert-post} has been triggered.
5252 @item @b{reset-deassert-post}
5253 @* Issued as part of @command{reset} processing
5254 after @code{reset-deassert-pre} has been triggered
5255 and (if the target is using it) after SRST has been
5256 released on the scan chain.
5258 @* Issued as the final step in @command{reset} processing.
5259 @item @b{reset-init}
5260 @* Used by @b{reset init} command for board-specific initialization.
5261 This event fires after @emph{reset-deassert-post}.
5263 This is where you would configure PLLs and clocking, set up DRAM so
5264 you can download programs that don't fit in on-chip SRAM, set up pin
5265 multiplexing, and so on.
5266 (You may be able to switch to a fast JTAG clock rate here, after
5267 the target clocks are fully set up.)
5268 @item @b{reset-start}
5269 @* Issued as the first step in @command{reset} processing
5270 before @command{reset-assert-pre} is called.
5272 This is the most robust place to use @command{jtag_rclk}
5273 or @command{adapter speed} to switch to a low JTAG clock rate,
5274 when reset disables PLLs needed to use a fast clock.
5275 @item @b{resume-start}
5276 @* Before any target is resumed
5277 @item @b{resume-end}
5278 @* After all targets have resumed
5280 @* Target has resumed
5281 @item @b{step-start}
5282 @* Before a target is single-stepped
5284 @* After single-step has completed
5285 @item @b{trace-config}
5286 @* After target hardware trace configuration was changed
5287 @item @b{semihosting-user-cmd-0x100}
5288 @* The target made a semihosting call with user-defined operation number 0x100
5289 @item @b{semihosting-user-cmd-0x101}
5290 @* The target made a semihosting call with user-defined operation number 0x101
5291 @item @b{semihosting-user-cmd-0x102}
5292 @* The target made a semihosting call with user-defined operation number 0x102
5293 @item @b{semihosting-user-cmd-0x103}
5294 @* The target made a semihosting call with user-defined operation number 0x103
5295 @item @b{semihosting-user-cmd-0x104}
5296 @* The target made a semihosting call with user-defined operation number 0x104
5297 @item @b{semihosting-user-cmd-0x105}
5298 @* The target made a semihosting call with user-defined operation number 0x105
5299 @item @b{semihosting-user-cmd-0x106}
5300 @* The target made a semihosting call with user-defined operation number 0x106
5301 @item @b{semihosting-user-cmd-0x107}
5302 @* The target made a semihosting call with user-defined operation number 0x107
5306 OpenOCD events are not supposed to be preempt by another event, but this
5307 is not enforced in current code. Only the target event @b{resumed} is
5308 executed with polling disabled; this avoids polling to trigger the event
5309 @b{halted}, reversing the logical order of execution of their handlers.
5310 Future versions of OpenOCD will prevent the event preemption and will
5311 disable the schedule of polling during the event execution. Do not rely
5312 on polling in any event handler; this means, don't expect the status of
5313 a core to change during the execution of the handler. The event handler
5314 will have to enable polling or use @command{$target_name arp_poll} to
5315 check if the core has changed status.
5318 @node Flash Commands
5319 @chapter Flash Commands
5321 OpenOCD has different commands for NOR and NAND flash;
5322 the ``flash'' command works with NOR flash, while
5323 the ``nand'' command works with NAND flash.
5324 This partially reflects different hardware technologies:
5325 NOR flash usually supports direct CPU instruction and data bus access,
5326 while data from a NAND flash must be copied to memory before it can be
5327 used. (SPI flash must also be copied to memory before use.)
5328 However, the documentation also uses ``flash'' as a generic term;
5329 for example, ``Put flash configuration in board-specific files''.
5333 @item Configure via the command @command{flash bank}
5334 @* Do this in a board-specific configuration file,
5335 passing parameters as needed by the driver.
5336 @item Operate on the flash via @command{flash subcommand}
5337 @* Often commands to manipulate the flash are typed by a human, or run
5338 via a script in some automated way. Common tasks include writing a
5339 boot loader, operating system, or other data.
5341 @* Flashing via GDB requires the flash be configured via ``flash
5342 bank'', and the GDB flash features be enabled.
5343 @xref{gdbconfiguration,,GDB Configuration}.
5346 Many CPUs have the ability to ``boot'' from the first flash bank.
5347 This means that misprogramming that bank can ``brick'' a system,
5348 so that it can't boot.
5349 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
5350 board by (re)installing working boot firmware.
5352 @anchor{norconfiguration}
5353 @section Flash Configuration Commands
5354 @cindex flash configuration
5356 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
5357 Configures a flash bank which provides persistent storage
5358 for addresses from @math{base} to @math{base + size - 1}.
5359 These banks will often be visible to GDB through the target's memory map.
5360 In some cases, configuring a flash bank will activate extra commands;
5361 see the driver-specific documentation.
5364 @item @var{name} ... may be used to reference the flash bank
5365 in other flash commands. A number is also available.
5366 @item @var{driver} ... identifies the controller driver
5367 associated with the flash bank being declared.
5368 This is usually @code{cfi} for external flash, or else
5369 the name of a microcontroller with embedded flash memory.
5370 @xref{flashdriverlist,,Flash Driver List}.
5371 @item @var{base} ... Base address of the flash chip.
5372 @item @var{size} ... Size of the chip, in bytes.
5373 For some drivers, this value is detected from the hardware.
5374 @item @var{chip_width} ... Width of the flash chip, in bytes;
5375 ignored for most microcontroller drivers.
5376 @item @var{bus_width} ... Width of the data bus used to access the
5377 chip, in bytes; ignored for most microcontroller drivers.
5378 @item @var{target} ... Names the target used to issue
5379 commands to the flash controller.
5380 @comment Actually, it's currently a controller-specific parameter...
5381 @item @var{driver_options} ... drivers may support, or require,
5382 additional parameters. See the driver-specific documentation
5383 for more information.
5386 This command is not available after OpenOCD initialization has completed.
5387 Use it in board specific configuration files, not interactively.
5391 @comment less confusing would be: "flash list" (like "nand list")
5392 @deffn {Command} {flash banks}
5393 Prints a one-line summary of each device that was
5394 declared using @command{flash bank}, numbered from zero.
5395 Note that this is the @emph{plural} form;
5396 the @emph{singular} form is a very different command.
5399 @deffn {Command} {flash list}
5400 Retrieves a list of associative arrays for each device that was
5401 declared using @command{flash bank}, numbered from zero.
5402 This returned list can be manipulated easily from within scripts.
5405 @deffn {Command} {flash probe} num
5406 Identify the flash, or validate the parameters of the configured flash. Operation
5407 depends on the flash type.
5408 The @var{num} parameter is a value shown by @command{flash banks}.
5409 Most flash commands will implicitly @emph{autoprobe} the bank;
5410 flash drivers can distinguish between probing and autoprobing,
5411 but most don't bother.
5414 @section Preparing a Target before Flash Programming
5416 The target device should be in well defined state before the flash programming
5419 @emph{Always issue} @command{reset init} before @ref{flashprogrammingcommands,,Flash Programming Commands}.
5420 Do not issue another @command{reset} or @command{reset halt} or @command{resume}
5421 until the programming session is finished.
5423 If you use @ref{programmingusinggdb,,Programming using GDB},
5424 the target is prepared automatically in the event gdb-flash-erase-start
5426 The jimtcl script @command{program} calls @command{reset init} explicitly.
5428 @section Erasing, Reading, Writing to Flash
5429 @cindex flash erasing
5430 @cindex flash reading
5431 @cindex flash writing
5432 @cindex flash programming
5433 @anchor{flashprogrammingcommands}
5435 One feature distinguishing NOR flash from NAND or serial flash technologies
5436 is that for read access, it acts exactly like any other addressable memory.
5437 This means you can use normal memory read commands like @command{mdw} or
5438 @command{dump_image} with it, with no special @command{flash} subcommands.
5439 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
5441 Write access works differently. Flash memory normally needs to be erased
5442 before it's written. Erasing a sector turns all of its bits to ones, and
5443 writing can turn ones into zeroes. This is why there are special commands
5444 for interactive erasing and writing, and why GDB needs to know which parts
5445 of the address space hold NOR flash memory.
5448 Most of these erase and write commands leverage the fact that NOR flash
5449 chips consume target address space. They implicitly refer to the current
5450 JTAG target, and map from an address in that target's address space
5451 back to a flash bank.
5452 @comment In May 2009, those mappings may fail if any bank associated
5453 @comment with that target doesn't successfully autoprobe ... bug worth fixing?
5454 A few commands use abstract addressing based on bank and sector numbers,
5455 and don't depend on searching the current target and its address space.
5456 Avoid confusing the two command models.
5459 Some flash chips implement software protection against accidental writes,
5460 since such buggy writes could in some cases ``brick'' a system.
5461 For such systems, erasing and writing may require sector protection to be
5463 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
5464 and AT91SAM7 on-chip flash.
5465 @xref{flashprotect,,flash protect}.
5467 @deffn {Command} {flash erase_sector} num first last
5468 Erase sectors in bank @var{num}, starting at sector @var{first}
5469 up to and including @var{last}.
5470 Sector numbering starts at 0.
5471 Providing a @var{last} sector of @option{last}
5472 specifies "to the end of the flash bank".
5473 The @var{num} parameter is a value shown by @command{flash banks}.
5476 @deffn {Command} {flash erase_address} [@option{pad}] [@option{unlock}] address length
5477 Erase sectors starting at @var{address} for @var{length} bytes.
5478 Unless @option{pad} is specified, @math{address} must begin a
5479 flash sector, and @math{address + length - 1} must end a sector.
5480 Specifying @option{pad} erases extra data at the beginning and/or
5481 end of the specified region, as needed to erase only full sectors.
5482 The flash bank to use is inferred from the @var{address}, and
5483 the specified length must stay within that bank.
5484 As a special case, when @var{length} is zero and @var{address} is
5485 the start of the bank, the whole flash is erased.
5486 If @option{unlock} is specified, then the flash is unprotected
5487 before erase starts.
5490 @deffn {Command} {flash filld} address double-word length
5491 @deffnx {Command} {flash fillw} address word length
5492 @deffnx {Command} {flash fillh} address halfword length
5493 @deffnx {Command} {flash fillb} address byte length
5494 Fills flash memory with the specified @var{double-word} (64 bits), @var{word} (32 bits),
5495 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5496 starting at @var{address} and continuing
5497 for @var{length} units (word/halfword/byte).
5498 No erasure is done before writing; when needed, that must be done
5499 before issuing this command.
5500 Writes are done in blocks of up to 1024 bytes, and each write is
5501 verified by reading back the data and comparing it to what was written.
5502 The flash bank to use is inferred from the @var{address} of
5503 each block, and the specified length must stay within that bank.
5505 @comment no current checks for errors if fill blocks touch multiple banks!
5507 @deffn {Command} {flash mdw} addr [count]
5508 @deffnx {Command} {flash mdh} addr [count]
5509 @deffnx {Command} {flash mdb} addr [count]
5510 Display contents of address @var{addr}, as
5511 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
5512 or 8-bit bytes (@command{mdb}).
5513 If @var{count} is specified, displays that many units.
5514 Reads from flash using the flash driver, therefore it enables reading
5515 from a bank not mapped in target address space.
5516 The flash bank to use is inferred from the @var{address} of
5517 each block, and the specified length must stay within that bank.
5520 @deffn {Command} {flash write_bank} num filename [offset]
5521 Write the binary @file{filename} to flash bank @var{num},
5522 starting at @var{offset} bytes from the beginning of the bank. If @var{offset}
5523 is omitted, start at the beginning of the flash bank.
5524 The @var{num} parameter is a value shown by @command{flash banks}.
5527 @deffn {Command} {flash read_bank} num filename [offset [length]]
5528 Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
5529 and write the contents to the binary @file{filename}. If @var{offset} is
5530 omitted, start at the beginning of the flash bank. If @var{length} is omitted,
5531 read the remaining bytes from the flash bank.
5532 The @var{num} parameter is a value shown by @command{flash banks}.
5535 @deffn {Command} {flash verify_bank} num filename [offset]
5536 Compare the contents of the binary file @var{filename} with the contents of the
5537 flash bank @var{num} starting at @var{offset}. If @var{offset} is omitted,
5538 start at the beginning of the flash bank. Fail if the contents do not match.
5539 The @var{num} parameter is a value shown by @command{flash banks}.
5542 @deffn {Command} {flash write_image} [erase] [unlock] filename [offset] [type]
5543 Write the image @file{filename} to the current target's flash bank(s).
5544 Only loadable sections from the image are written.
5545 A relocation @var{offset} may be specified, in which case it is added
5546 to the base address for each section in the image.
5547 The file [@var{type}] can be specified
5548 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
5549 @option{elf} (ELF file), @option{s19} (Motorola s19).
5550 @option{mem}, or @option{builder}.
5551 The relevant flash sectors will be erased prior to programming
5552 if the @option{erase} parameter is given. If @option{unlock} is
5553 provided, then the flash banks are unlocked before erase and
5554 program. The flash bank to use is inferred from the address of
5558 Be careful using the @option{erase} flag when the flash is holding
5559 data you want to preserve.
5560 Portions of the flash outside those described in the image's
5561 sections might be erased with no notice.
5564 When a section of the image being written does not fill out all the
5565 sectors it uses, the unwritten parts of those sectors are necessarily
5566 also erased, because sectors can't be partially erased.
5568 Data stored in sector "holes" between image sections are also affected.
5569 For example, "@command{flash write_image erase ...}" of an image with
5570 one byte at the beginning of a flash bank and one byte at the end
5571 erases the entire bank -- not just the two sectors being written.
5573 Also, when flash protection is important, you must re-apply it after
5574 it has been removed by the @option{unlock} flag.
5579 @deffn {Command} {flash verify_image} filename [offset] [type]
5580 Verify the image @file{filename} to the current target's flash bank(s).
5581 Parameters follow the description of 'flash write_image'.
5582 In contrast to the 'verify_image' command, for banks with specific
5583 verify method, that one is used instead of the usual target's read
5584 memory methods. This is necessary for flash banks not readable by
5585 ordinary memory reads.
5586 This command gives only an overall good/bad result for each bank, not
5587 addresses of individual failed bytes as it's intended only as quick
5588 check for successful programming.
5591 @section Other Flash commands
5592 @cindex flash protection
5594 @deffn {Command} {flash erase_check} num
5595 Check erase state of sectors in flash bank @var{num},
5596 and display that status.
5597 The @var{num} parameter is a value shown by @command{flash banks}.
5600 @deffn {Command} {flash info} num [sectors]
5601 Print info about flash bank @var{num}, a list of protection blocks
5602 and their status. Use @option{sectors} to show a list of sectors instead.
5604 The @var{num} parameter is a value shown by @command{flash banks}.
5605 This command will first query the hardware, it does not print cached
5606 and possibly stale information.
5609 @anchor{flashprotect}
5610 @deffn {Command} {flash protect} num first last (@option{on}|@option{off})
5611 Enable (@option{on}) or disable (@option{off}) protection of flash blocks
5612 in flash bank @var{num}, starting at protection block @var{first}
5613 and continuing up to and including @var{last}.
5614 Providing a @var{last} block of @option{last}
5615 specifies "to the end of the flash bank".
5616 The @var{num} parameter is a value shown by @command{flash banks}.
5617 The protection block is usually identical to a flash sector.
5618 Some devices may utilize a protection block distinct from flash sector.
5619 See @command{flash info} for a list of protection blocks.
5622 @deffn {Command} {flash padded_value} num value
5623 Sets the default value used for padding any image sections, This should
5624 normally match the flash bank erased value. If not specified by this
5625 command or the flash driver then it defaults to 0xff.
5629 @deffn {Command} {program} filename [preverify] [verify] [reset] [exit] [offset]
5630 This is a helper script that simplifies using OpenOCD as a standalone
5631 programmer. The only required parameter is @option{filename}, the others are optional.
5632 @xref{Flash Programming}.
5635 @anchor{flashdriverlist}
5636 @section Flash Driver List
5637 As noted above, the @command{flash bank} command requires a driver name,
5638 and allows driver-specific options and behaviors.
5639 Some drivers also activate driver-specific commands.
5641 @deffn {Flash Driver} {virtual}
5642 This is a special driver that maps a previously defined bank to another
5643 address. All bank settings will be copied from the master physical bank.
5645 The @var{virtual} driver defines one mandatory parameters,
5648 @item @var{master_bank} The bank that this virtual address refers to.
5651 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
5652 the flash bank defined at address 0x1fc00000. Any command executed on
5653 the virtual banks is actually performed on the physical banks.
5655 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
5656 flash bank vbank0 virtual 0xbfc00000 0 0 0 \
5657 $_TARGETNAME $_FLASHNAME
5658 flash bank vbank1 virtual 0x9fc00000 0 0 0 \
5659 $_TARGETNAME $_FLASHNAME
5663 @subsection External Flash
5665 @deffn {Flash Driver} {cfi}
5666 @cindex Common Flash Interface
5668 The ``Common Flash Interface'' (CFI) is the main standard for
5669 external NOR flash chips, each of which connects to a
5670 specific external chip select on the CPU.
5671 Frequently the first such chip is used to boot the system.
5672 Your board's @code{reset-init} handler might need to
5673 configure additional chip selects using other commands (like: @command{mww} to
5674 configure a bus and its timings), or
5675 perhaps configure a GPIO pin that controls the ``write protect'' pin
5677 The CFI driver can use a target-specific working area to significantly
5680 The CFI driver can accept the following optional parameters, in any order:
5683 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
5684 like AM29LV010 and similar types.
5685 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
5686 @item @var{bus_swap} ... when data bytes in a 16-bit flash needs to be swapped.
5687 @item @var{data_swap} ... when data bytes in a 16-bit flash needs to be
5688 swapped when writing data values (i.e. not CFI commands).
5691 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
5692 wide on a sixteen bit bus:
5695 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
5696 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
5699 To configure one bank of 32 MBytes
5700 built from two sixteen bit (two byte) wide parts wired in parallel
5701 to create a thirty-two bit (four byte) bus with doubled throughput:
5704 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
5707 @c "cfi part_id" disabled
5710 @deffn {Flash Driver} {jtagspi}
5711 @cindex Generic JTAG2SPI driver
5715 Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
5716 SPI flash connected to them. To access this flash from the host, the device
5717 is first programmed with a special proxy bitstream that
5718 exposes the SPI flash on the device's JTAG interface. The flash can then be
5719 accessed through JTAG.
5721 Since signaling between JTAG and SPI is compatible, all that is required for
5722 a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
5723 the flash chip select when the JTAG state machine is in SHIFT-DR. Such
5724 a bitstream for several Xilinx FPGAs can be found in
5725 @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires
5726 @uref{https://github.com/m-labs/migen, migen} and a Xilinx toolchain to build.
5728 This flash bank driver requires a target on a JTAG tap and will access that
5729 tap directly. Since no support from the target is needed, the target can be a
5730 "testee" dummy. Since the target does not expose the flash memory
5731 mapping, target commands that would otherwise be expected to access the flash
5732 will not work. These include all @command{*_image} and
5733 @command{$target_name m*} commands as well as @command{program}. Equivalent
5734 functionality is available through the @command{flash write_bank},
5735 @command{flash read_bank}, and @command{flash verify_bank} commands.
5737 According to device size, 1- to 4-byte addresses are sent. However, some
5738 flash chips additionally have to be switched to 4-byte addresses by an extra
5742 @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
5743 For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
5744 @var{USER1} instruction.
5748 target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
5749 set _XILINX_USER1 0x02
5750 flash bank $_FLASHNAME spi 0x0 0 0 0 \
5751 $_TARGETNAME $_XILINX_USER1
5754 @deffn Command {jtagspi set} bank_id name total_size page_size read_cmd unused pprg_cmd mass_erase_cmd sector_size sector_erase_cmd
5755 Sets flash parameters: @var{name} human readable string, @var{total_size}
5756 size in bytes, @var{page_size} is write page size. @var{read_cmd} and @var{pprg_cmd}
5757 are commands for read and page program, respectively. @var{mass_erase_cmd},
5758 @var{sector_size} and @var{sector_erase_cmd} are optional.
5760 jtagspi set 0 w25q128 0x1000000 0x100 0x03 0 0x02 0xC7 0x10000 0xD8
5764 @deffn Command {jtagspi cmd} bank_id resp_num cmd_byte ...
5765 Sends command @var{cmd_byte} and at most 20 following bytes and reads
5766 @var{resp_num} bytes afterwards. E.g. for 'Enter 4-byte address mode'
5768 jtagspi cmd 0 0 0xB7
5772 @deffn Command {jtagspi always_4byte} bank_id [ on | off ]
5773 Some devices use 4-byte addresses for all commands except the legacy 0x03 read
5774 regardless of device size. This command controls the corresponding hack.
5778 @deffn {Flash Driver} {xcf}
5779 @cindex Xilinx Platform flash driver
5781 Xilinx FPGAs can be configured from specialized flash ICs named Platform Flash.
5782 It is (almost) regular NOR flash with erase sectors, program pages, etc. The
5783 only difference is special registers controlling its FPGA specific behavior.
5784 They must be properly configured for successful FPGA loading using
5785 additional @var{xcf} driver command:
5787 @deffn {Command} {xcf ccb} <bank_id>
5788 command accepts additional parameters:
5790 @item @var{external|internal} ... selects clock source.
5791 @item @var{serial|parallel} ... selects serial or parallel data bus mode.
5792 @item @var{slave|master} ... selects slave of master mode for flash device.
5793 @item @var{40|20} ... selects clock frequency in MHz for internal clock
5797 xcf ccb 0 external parallel slave 40
5799 All of them must be specified even if clock frequency is pointless
5800 in slave mode. If only bank id specified than command prints current
5801 CCB register value. Note: there is no need to write this register
5802 every time you erase/program data sectors because it stores in
5806 @deffn {Command} {xcf configure} <bank_id>
5807 Initiates FPGA loading procedure. Useful if your board has no "configure"
5814 Additional driver notes:
5816 @item Only single revision supported.
5817 @item Driver automatically detects need of bit reverse, but
5818 only "bin" (raw binary, do not confuse it with "bit") and "mcs"
5819 (Intel hex) file types supported.
5820 @item For additional info check xapp972.pdf and ug380.pdf.
5824 @deffn {Flash Driver} {lpcspifi}
5825 @cindex NXP SPI Flash Interface
5828 NXP's LPC43xx and LPC18xx families include a proprietary SPI
5829 Flash Interface (SPIFI) peripheral that can drive and provide
5830 memory mapped access to external SPI flash devices.
5832 The lpcspifi driver initializes this interface and provides
5833 program and erase functionality for these serial flash devices.
5834 Use of this driver @b{requires} a working area of at least 1kB
5835 to be configured on the target device; more than this will
5836 significantly reduce flash programming times.
5838 The setup command only requires the @var{base} parameter. All
5839 other parameters are ignored, and the flash size and layout
5840 are configured by the driver.
5843 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
5848 @deffn {Flash Driver} {stmsmi}
5849 @cindex STMicroelectronics Serial Memory Interface
5852 Some devices from STMicroelectronics (e.g. STR75x MCU family,
5853 SPEAr MPU family) include a proprietary
5854 ``Serial Memory Interface'' (SMI) controller able to drive external
5856 Depending on specific device and board configuration, up to 4 external
5857 flash devices can be connected.
5859 SMI makes the flash content directly accessible in the CPU address
5860 space; each external device is mapped in a memory bank.
5861 CPU can directly read data, execute code and boot from SMI banks.
5862 Normal OpenOCD commands like @command{mdw} can be used to display
5865 The setup command only requires the @var{base} parameter in order
5866 to identify the memory bank.
5867 All other parameters are ignored. Additional information, like
5868 flash size, are detected automatically.
5871 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
5876 @deffn {Flash Driver} {stmqspi}
5877 @cindex STMicroelectronics QuadSPI/OctoSPI Interface
5881 Some devices from STMicroelectronics include a proprietary ``QuadSPI Interface''
5882 (e.g. STM32F4, STM32F7, STM32L4) or ``OctoSPI Interface'' (e.g. STM32L4+)
5883 controller able to drive one or even two (dual mode) external SPI flash devices.
5884 The OctoSPI is a superset of QuadSPI, its presence is detected automatically.
5885 Currently only the regular command mode is supported, whereas the HyperFlash
5888 QuadSPI/OctoSPI makes the flash contents directly accessible in the CPU address
5889 space; in case of dual mode both devices must be of the same type and are
5890 mapped in the same memory bank (even and odd addresses interleaved).
5891 CPU can directly read data, execute code (but not boot) from QuadSPI bank.
5893 The 'flash bank' command only requires the @var{base} parameter and the extra
5894 parameter @var{io_base} in order to identify the memory bank. Both are fixed
5895 by hardware, see datasheet or RM. All other parameters are ignored.
5897 The controller must be initialized after each reset and properly configured
5898 for memory-mapped read operation for the particular flash chip(s), for the full
5899 list of available register settings cf. the controller's RM. This setup is quite
5900 board specific (that's why booting from this memory is not possible). The
5901 flash driver infers all parameters from current controller register values when
5902 'flash probe @var{bank_id}' is executed.
5904 Normal OpenOCD commands like @command{mdw} can be used to display the flash content,
5905 but only after proper controller initialization as described above. However,
5906 due to a silicon bug in some devices, attempting to access the very last word
5909 It is possible to use two (even different) flash chips alternatingly, if individual
5910 bank chip selects are available. For some package variants, this is not the case
5911 due to limited pin count. To switch from one to another, adjust FSEL bit accordingly
5912 and re-issue 'flash probe bank_id'. Note that the bank base address will @emph{not}
5913 change, so the address spaces of both devices will overlap. In dual flash mode
5914 both chips must be identical regarding size and most other properties.
5916 Block or sector protection internal to the flash chip is not handled by this
5917 driver at all, but can be dealt with manually by the 'cmd' command, see below.
5918 The sector protection via 'flash protect' command etc. is completely internal to
5919 openocd, intended only to prevent accidental erase or overwrite and it does not
5920 persist across openocd invocations.
5922 OpenOCD contains a hardcoded list of flash devices with their properties,
5923 these are auto-detected. If a device is not included in this list, SFDP discovery
5924 is attempted. If this fails or gives inappropriate results, manual setting is
5925 required (see 'set' command).
5928 flash bank $_FLASHNAME stmqspi 0x90000000 0 0 0 \
5929 $_TARGETNAME 0xA0001000
5930 flash bank $_FLASHNAME stmqspi 0x70000000 0 0 0 \
5931 $_TARGETNAME 0xA0001400
5934 There are three specific commands
5935 @deffn {Command} {stmqspi mass_erase} bank_id
5936 Clears sector protections and performs a mass erase. Works only if there is no
5937 chip specific write protection engaged.
5940 @deffn {Command} {stmqspi set} bank_id name total_size page_size read_cmd fread_cmd pprg_cmd mass_erase_cmd sector_size sector_erase_cmd
5941 Set flash parameters: @var{name} human readable string, @var{total_size} size
5942 in bytes, @var{page_size} is write page size. @var{read_cmd}, @var{fread_cmd} and @var{pprg_cmd}
5943 are commands for reading and page programming. @var{fread_cmd} is used in DPI and QPI modes,
5944 @var{read_cmd} in normal SPI (single line) mode. @var{mass_erase_cmd}, @var{sector_size}
5945 and @var{sector_erase_cmd} are optional.
5947 This command is required if chip id is not hardcoded yet and e.g. for EEPROMs or FRAMs
5948 which don't support an id command.
5950 In dual mode parameters of both chips are set identically. The parameters refer to
5951 a single chip, so the whole bank gets twice the specified capacity etc.
5954 @deffn {Command} {stmqspi cmd} bank_id resp_num cmd_byte ...
5955 If @var{resp_num} is zero, sends command @var{cmd_byte} and following data
5956 bytes. In dual mode command byte is sent to @emph{both} chips but data bytes are
5957 sent @emph{alternatingly} to chip 1 and 2, first to flash 1, second to flash 2, etc.,
5958 i.e. the total number of bytes (including cmd_byte) must be odd.
5960 If @var{resp_num} is not zero, cmd and at most four following data bytes are
5961 sent, in dual mode @emph{simultaneously} to both chips. Then @var{resp_num} bytes
5962 are read interleaved from both chips starting with chip 1. In this case
5963 @var{resp_num} must be even.
5965 Note the hardware dictated subtle difference of those two cases in dual-flash mode.
5967 To check basic communication settings, issue
5969 stmqspi cmd bank_id 0 0x04; stmqspi cmd bank_id 1 0x05
5970 stmqspi cmd bank_id 0 0x06; stmqspi cmd bank_id 1 0x05
5972 for single flash mode or
5974 stmqspi cmd bank_id 0 0x04; stmqspi cmd bank_id 2 0x05
5975 stmqspi cmd bank_id 0 0x06; stmqspi cmd bank_id 2 0x05
5977 for dual flash mode. This should return the status register contents.
5979 In 8-line mode, @var{cmd_byte} is sent twice - first time as given, second time
5980 complemented. Additionally, in 8-line mode only, some commands (e.g. Read Status)
5981 need a dummy address, e.g.
5983 stmqspi cmd bank_id 1 0x05 0x00 0x00 0x00 0x00
5985 should return the status register contents.
5991 @deffn {Flash Driver} {mrvlqspi}
5992 This driver supports QSPI flash controller of Marvell's Wireless
5993 Microcontroller platform.
5995 The flash size is autodetected based on the table of known JEDEC IDs
5996 hardcoded in the OpenOCD sources.
5999 flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
6004 @deffn {Flash Driver} {ath79}
6005 @cindex Atheros ath79 SPI driver
6007 Members of ATH79 SoC family from Atheros include a SPI interface with 3
6009 On reset a SPI flash connected to the first chip select (CS0) is made
6010 directly read-accessible in the CPU address space (up to 16MBytes)
6011 and is usually used to store the bootloader and operating system.
6012 Normal OpenOCD commands like @command{mdw} can be used to display
6013 the flash content while it is in memory-mapped mode (only the first
6014 4MBytes are accessible without additional configuration on reset).
6016 The setup command only requires the @var{base} parameter in order
6017 to identify the memory bank. The actual value for the base address
6018 is not otherwise used by the driver. However the mapping is passed
6019 to gdb. Thus for the memory mapped flash (chipselect CS0) the base
6020 address should be the actual memory mapped base address. For unmapped
6021 chipselects (CS1 and CS2) care should be taken to use a base address
6022 that does not overlap with real memory regions.
6023 Additional information, like flash size, are detected automatically.
6024 An optional additional parameter sets the chipselect for the bank,
6025 with the default CS0.
6026 CS1 and CS2 require additional GPIO setup before they can be used
6027 since the alternate function must be enabled on the GPIO pin
6028 CS1/CS2 is routed to on the given SoC.
6031 flash bank $_FLASHNAME ath79 0xbf000000 0 0 0 $_TARGETNAME
6033 # When using multiple chipselects the base should be different
6034 # for each, otherwise the write_image command is not able to
6035 # distinguish the banks.
6036 flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
6037 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
6038 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
6043 @deffn {Flash Driver} {fespi}
6044 @cindex Freedom E SPI
6047 SiFive's Freedom E SPI controller, used in HiFive and other boards.
6050 flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
6054 @subsection Internal Flash (Microcontrollers)
6056 @deffn {Flash Driver} {aduc702x}
6057 The ADUC702x analog microcontrollers from Analog Devices
6058 include internal flash and use ARM7TDMI cores.
6059 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
6060 The setup command only requires the @var{target} argument
6061 since all devices in this family have the same memory layout.
6064 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
6068 @deffn {Flash Driver} {ambiqmicro}
6071 All members of the Apollo microcontroller family from
6072 Ambiq Micro include internal flash and use ARM's Cortex-M4 core.
6073 The host connects over USB to an FTDI interface that communicates
6074 with the target using SWD.
6076 The @var{ambiqmicro} driver reads the Chip Information Register detect
6077 the device class of the MCU.
6078 The Flash and SRAM sizes directly follow device class, and are used
6079 to set up the flash banks.
6080 If this fails, the driver will use default values set to the minimum
6081 sizes of an Apollo chip.
6083 All Apollo chips have two flash banks of the same size.
6084 In all cases the first flash bank starts at location 0,
6085 and the second bank starts after the first.
6089 flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
6090 # Flash bank 1 - same size as bank0, starts after bank 0.
6091 flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \
6095 Flash is programmed using custom entry points into the bootloader.
6096 This is the only way to program the flash as no flash control registers
6097 are available to the user.
6099 The @var{ambiqmicro} driver adds some additional commands:
6101 @deffn {Command} {ambiqmicro mass_erase} <bank>
6104 @deffn {Command} {ambiqmicro page_erase} <bank> <first> <last>
6107 @deffn {Command} {ambiqmicro program_otp} <bank> <offset> <count>
6108 Program OTP is a one time operation to create write protected flash.
6109 The user writes sectors to SRAM starting at 0x10000010.
6110 Program OTP will write these sectors from SRAM to flash, and write protect
6116 @deffn {Flash Driver} {at91samd}
6118 All members of the ATSAM D2x, D1x, D0x, ATSAMR, ATSAML and ATSAMC microcontroller
6119 families from Atmel include internal flash and use ARM's Cortex-M0+ core.
6121 Do not use for ATSAM D51 and E5x: use @xref{atsame5}.
6123 The devices have one flash bank:
6126 flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME
6129 @deffn {Command} {at91samd chip-erase}
6130 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
6131 used to erase a chip back to its factory state and does not require the
6132 processor to be halted.
6135 @deffn {Command} {at91samd set-security}
6136 Secures the Flash via the Set Security Bit (SSB) command. This prevents access
6137 to the Flash and can only be undone by using the chip-erase command which
6138 erases the Flash contents and turns off the security bit. Warning: at this
6139 time, openocd will not be able to communicate with a secured chip and it is
6140 therefore not possible to chip-erase it without using another tool.
6143 at91samd set-security enable
6147 @deffn {Command} {at91samd eeprom}
6148 Shows or sets the EEPROM emulation size configuration, stored in the User Row
6149 of the Flash. When setting, the EEPROM size must be specified in bytes and it
6150 must be one of the permitted sizes according to the datasheet. Settings are
6151 written immediately but only take effect on MCU reset. EEPROM emulation
6152 requires additional firmware support and the minimum EEPROM size may not be
6153 the same as the minimum that the hardware supports. Set the EEPROM size to 0
6154 in order to disable this feature.
6158 at91samd eeprom 1024
6162 @deffn {Command} {at91samd bootloader}
6163 Shows or sets the bootloader size configuration, stored in the User Row of the
6164 Flash. This is called the BOOTPROT region. When setting, the bootloader size
6165 must be specified in bytes and it must be one of the permitted sizes according
6166 to the datasheet. Settings are written immediately but only take effect on
6167 MCU reset. Setting the bootloader size to 0 disables bootloader protection.
6171 at91samd bootloader 16384
6175 @deffn {Command} {at91samd dsu_reset_deassert}
6176 This command releases internal reset held by DSU
6177 and prepares reset vector catch in case of reset halt.
6178 Command is used internally in event reset-deassert-post.
6181 @deffn {Command} {at91samd nvmuserrow}
6182 Writes or reads the entire 64 bit wide NVM user row register which is located at
6183 0x804000. This register includes various fuses lock-bits and factory calibration
6184 data. Reading the register is done by invoking this command without any
6185 arguments. Writing is possible by giving 1 or 2 hex values. The first argument
6186 is the register value to be written and the second one is an optional changemask.
6187 Every bit which value in changemask is 0 will stay unchanged. The lock- and
6188 reserved-bits are masked out and cannot be changed.
6192 >at91samd nvmuserrow
6193 NVMUSERROW: 0xFFFFFC5DD8E0C788
6194 # Write 0xFFFFFC5DD8E0C788 to user row
6195 >at91samd nvmuserrow 0xFFFFFC5DD8E0C788
6196 # Write 0x12300 to user row but leave other bits and low
6198 >at91samd nvmuserrow 0x12345 0xFFF00
6205 @deffn {Flash Driver} {at91sam3}
6207 All members of the AT91SAM3 microcontroller family from
6208 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
6209 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
6210 that the driver was orginaly developed and tested using the
6211 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
6212 the family was cribbed from the data sheet. @emph{Note to future
6213 readers/updaters: Please remove this worrisome comment after other
6214 chips are confirmed.}
6216 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
6217 have one flash bank. In all cases the flash banks are at
6218 the following fixed locations:
6221 # Flash bank 0 - all chips
6222 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
6223 # Flash bank 1 - only 256K chips
6224 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
6227 Internally, the AT91SAM3 flash memory is organized as follows.
6228 Unlike the AT91SAM7 chips, these are not used as parameters
6229 to the @command{flash bank} command:
6232 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
6233 @item @emph{Bank Size:} 128K/64K Per flash bank
6234 @item @emph{Sectors:} 16 or 8 per bank
6235 @item @emph{SectorSize:} 8K Per Sector
6236 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
6239 The AT91SAM3 driver adds some additional commands:
6241 @deffn {Command} {at91sam3 gpnvm}
6242 @deffnx {Command} {at91sam3 gpnvm clear} number
6243 @deffnx {Command} {at91sam3 gpnvm set} number
6244 @deffnx {Command} {at91sam3 gpnvm show} [@option{all}|number]
6245 With no parameters, @command{show} or @command{show all},
6246 shows the status of all GPNVM bits.
6247 With @command{show} @var{number}, displays that bit.
6249 With @command{set} @var{number} or @command{clear} @var{number},
6250 modifies that GPNVM bit.
6253 @deffn {Command} {at91sam3 info}
6254 This command attempts to display information about the AT91SAM3
6255 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
6256 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
6257 document id: doc6430A] and decodes the values. @emph{Second} it reads the
6258 various clock configuration registers and attempts to display how it
6259 believes the chip is configured. By default, the SLOWCLK is assumed to
6260 be 32768 Hz, see the command @command{at91sam3 slowclk}.
6263 @deffn {Command} {at91sam3 slowclk} [value]
6264 This command shows/sets the slow clock frequency used in the
6265 @command{at91sam3 info} command calculations above.
6269 @deffn {Flash Driver} {at91sam4}
6271 All members of the AT91SAM4 microcontroller family from
6272 Atmel include internal flash and use ARM's Cortex-M4 core.
6273 This driver uses the same command names/syntax as @xref{at91sam3}.
6276 @deffn {Flash Driver} {at91sam4l}
6278 All members of the AT91SAM4L microcontroller family from
6279 Atmel include internal flash and use ARM's Cortex-M4 core.
6280 This driver uses the same command names/syntax as @xref{at91sam3}.
6282 The AT91SAM4L driver adds some additional commands:
6283 @deffn {Command} {at91sam4l smap_reset_deassert}
6284 This command releases internal reset held by SMAP
6285 and prepares reset vector catch in case of reset halt.
6286 Command is used internally in event reset-deassert-post.
6291 @deffn {Flash Driver} {atsame5}
6293 All members of the SAM E54, E53, E51 and D51 microcontroller
6294 families from Microchip (former Atmel) include internal flash
6295 and use ARM's Cortex-M4 core.
6297 The devices have two ECC flash banks with a swapping feature.
6298 This driver handles both banks together as it were one.
6299 Bank swapping is not supported yet.
6302 flash bank $_FLASHNAME atsame5 0x00000000 0 1 1 $_TARGETNAME
6305 @deffn {Command} {atsame5 bootloader}
6306 Shows or sets the bootloader size configuration, stored in the User Page of the
6307 Flash. This is called the BOOTPROT region. When setting, the bootloader size
6308 must be specified in bytes. The nearest bigger protection size is used.
6309 Settings are written immediately but only take effect on MCU reset.
6310 Setting the bootloader size to 0 disables bootloader protection.
6314 atsame5 bootloader 16384
6318 @deffn {Command} {atsame5 chip-erase}
6319 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
6320 used to erase a chip back to its factory state and does not require the
6321 processor to be halted.
6324 @deffn {Command} {atsame5 dsu_reset_deassert}
6325 This command releases internal reset held by DSU
6326 and prepares reset vector catch in case of reset halt.
6327 Command is used internally in event reset-deassert-post.
6330 @deffn {Command} {atsame5 userpage}
6331 Writes or reads the first 64 bits of NVM User Page which is located at
6332 0x804000. This field includes various fuses.
6333 Reading is done by invoking this command without any arguments.
6334 Writing is possible by giving 1 or 2 hex values. The first argument
6335 is the value to be written and the second one is an optional bit mask
6336 (a zero bit in the mask means the bit stays unchanged).
6337 The reserved fields are always masked out and cannot be changed.
6342 USER PAGE: 0xAEECFF80FE9A9239
6344 >atsame5 userpage 0xAEECFF80FE9A9239
6345 # Write 2 to SEESBLK and 4 to SEEPSZ fields but leave other
6346 # bits unchanged (setup SmartEEPROM of virtual size 8192
6348 >atsame5 userpage 0x4200000000 0x7f00000000
6354 @deffn {Flash Driver} {atsamv}
6356 All members of the ATSAMV7x, ATSAMS70, and ATSAME70 families from
6357 Atmel include internal flash and use ARM's Cortex-M7 core.
6358 This driver uses the same command names/syntax as @xref{at91sam3}.
6361 flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME
6364 @deffn {Command} {atsamv gpnvm} [@option{show} [@option{all}|number]]
6365 @deffnx {Command} {atsamv gpnvm} (@option{clr}|@option{set}) number
6366 With no parameters, @option{show} or @option{show all},
6367 shows the status of all GPNVM bits.
6368 With @option{show} @var{number}, displays that bit.
6370 With @option{set} @var{number} or @option{clear} @var{number},
6371 modifies that GPNVM bit.
6376 @deffn {Flash Driver} {at91sam7}
6377 All members of the AT91SAM7 microcontroller family from Atmel include
6378 internal flash and use ARM7TDMI cores. The driver automatically
6379 recognizes a number of these chips using the chip identification
6380 register, and autoconfigures itself.
6383 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
6386 For chips which are not recognized by the controller driver, you must
6387 provide additional parameters in the following order:
6390 @item @var{chip_model} ... label used with @command{flash info}
6392 @item @var{sectors_per_bank}
6393 @item @var{pages_per_sector}
6394 @item @var{pages_size}
6395 @item @var{num_nvm_bits}
6396 @item @var{freq_khz} ... required if an external clock is provided,
6397 optional (but recommended) when the oscillator frequency is known
6400 It is recommended that you provide zeroes for all of those values
6401 except the clock frequency, so that everything except that frequency
6402 will be autoconfigured.
6403 Knowing the frequency helps ensure correct timings for flash access.
6405 The flash controller handles erases automatically on a page (128/256 byte)
6406 basis, so explicit erase commands are not necessary for flash programming.
6407 However, there is an ``EraseAll`` command that can erase an entire flash
6408 plane (of up to 256KB), and it will be used automatically when you issue
6409 @command{flash erase_sector} or @command{flash erase_address} commands.
6411 @deffn {Command} {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
6412 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
6413 bit for the processor. Each processor has a number of such bits,
6414 used for controlling features such as brownout detection (so they
6415 are not truly general purpose).
6417 This assumes that the first flash bank (number 0) is associated with
6418 the appropriate at91sam7 target.
6423 @deffn {Flash Driver} {avr}
6424 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
6425 @emph{The current implementation is incomplete.}
6426 @comment - defines mass_erase ... pointless given flash_erase_address
6429 @deffn {Flash Driver} {bluenrg-x}
6430 STMicroelectronics BlueNRG-1, BlueNRG-2 and BlueNRG-LP/LPS Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0/M0+ core and internal flash memory.
6431 The driver automatically recognizes these chips using
6432 the chip identification registers, and autoconfigures itself.
6435 flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME
6438 Note that when users ask to erase all the sectors of the flash, a mass erase command is used which is faster than erasing
6439 each single sector one by one.
6442 flash erase_sector 0 0 last # It will perform a mass erase
6445 Triggering a mass erase is also useful when users want to disable readout protection.
6448 @deffn {Flash Driver} {cc26xx}
6449 All versions of the SimpleLink CC13xx and CC26xx microcontrollers from Texas
6450 Instruments include internal flash. The cc26xx flash driver supports both the
6451 CC13xx and CC26xx family of devices. The driver automatically recognizes the
6452 specific version's flash parameters and autoconfigures itself. The flash bank
6453 starts at address 0.
6456 flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
6460 @deffn {Flash Driver} {cc3220sf}
6461 The CC3220SF version of the SimpleLink CC32xx microcontrollers from Texas
6462 Instruments includes 1MB of internal flash. The cc3220sf flash driver only
6463 supports the internal flash. The serial flash on SimpleLink boards is
6464 programmed via the bootloader over a UART connection. Security features of
6465 the CC3220SF may erase the internal flash during power on reset. Refer to
6466 documentation at @url{www.ti.com/cc3220sf} for details on security features
6467 and programming the serial flash.
6470 flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
6474 @deffn {Flash Driver} {efm32}
6475 All members of the EFM32/EFR32 microcontroller family from Energy Micro (now Silicon Labs)
6476 include internal flash and use Arm Cortex-M3 or Cortex-M4 cores. The driver automatically
6477 recognizes a number of these chips using the chip identification register, and
6478 autoconfigures itself.
6480 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
6482 It supports writing to the user data page, as well as the portion of the lockbits page
6483 past 512 bytes on chips with larger page sizes. The latter is used by the SiLabs
6484 bootloader/AppLoader system for encryption keys. Setting protection on these pages is
6485 currently not supported.
6487 flash bank userdata.flash efm32 0x0FE00000 0 0 0 $_TARGETNAME
6488 flash bank lockbits.flash efm32 0x0FE04000 0 0 0 $_TARGETNAME
6491 A special feature of efm32 controllers is that it is possible to completely disable the
6492 debug interface by writing the correct values to the 'Debug Lock Word'. OpenOCD supports
6493 this via the following command:
6497 The @var{num} parameter is a value shown by @command{flash banks}.
6498 Note that in order for this command to take effect, the target needs to be reset.
6499 @emph{The current implementation is incomplete. Unprotecting flash pages is not
6503 @deffn {Flash Driver} {esirisc}
6504 Members of the eSi-RISC family may optionally include internal flash programmed
6505 via the eSi-TSMC Flash interface. Additional parameters are required to
6506 configure the driver: @option{cfg_address} is the base address of the
6507 configuration register interface, @option{clock_hz} is the expected clock
6508 frequency, and @option{wait_states} is the number of configured read wait states.
6511 flash bank $_FLASHNAME esirisc base_address size_bytes 0 0 \
6512 $_TARGETNAME cfg_address clock_hz wait_states
6515 @deffn {Command} {esirisc flash mass_erase} bank_id
6516 Erase all pages in data memory for the bank identified by @option{bank_id}.
6519 @deffn {Command} {esirisc flash ref_erase} bank_id
6520 Erase the reference cell for the bank identified by @option{bank_id}. @emph{This
6521 is an uncommon operation.}
6525 @deffn {Flash Driver} {fm3}
6526 All members of the FM3 microcontroller family from Fujitsu
6527 include internal flash and use ARM Cortex-M3 cores.
6528 The @var{fm3} driver uses the @var{target} parameter to select the
6529 correct bank config, it can currently be one of the following:
6530 @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
6531 @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
6534 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
6538 @deffn {Flash Driver} {fm4}
6539 All members of the FM4 microcontroller family from Spansion (formerly Fujitsu)
6540 include internal flash and use ARM Cortex-M4 cores.
6541 The @var{fm4} driver uses a @var{family} parameter to select the
6542 correct bank config, it can currently be one of the following:
6543 @code{MB9BFx64}, @code{MB9BFx65}, @code{MB9BFx66}, @code{MB9BFx67}, @code{MB9BFx68},
6544 @code{S6E2Cx8}, @code{S6E2Cx9}, @code{S6E2CxA} or @code{S6E2Dx},
6545 with @code{x} treated as wildcard and otherwise case (and any trailing
6546 characters) ignored.
6549 flash bank $@{_FLASHNAME@}0 fm4 0x00000000 0 0 0 \
6550 $_TARGETNAME S6E2CCAJ0A
6551 flash bank $@{_FLASHNAME@}1 fm4 0x00100000 0 0 0 \
6552 $_TARGETNAME S6E2CCAJ0A
6554 @emph{The current implementation is incomplete. Protection is not supported,
6555 nor is Chip Erase (only Sector Erase is implemented).}
6558 @deffn {Flash Driver} {kinetis}
6560 Kx, KLx, KVx and KE1x members of the Kinetis microcontroller family
6561 from NXP (former Freescale) include
6562 internal flash and use ARM Cortex-M0+ or M4 cores. The driver automatically
6563 recognizes flash size and a number of flash banks (1-4) using the chip
6564 identification register, and autoconfigures itself.
6565 Use kinetis_ke driver for KE0x and KEAx devices.
6567 The @var{kinetis} driver defines option:
6569 @item -sim-base @var{addr} ... base of System Integration Module where chip identification resides. Driver tries two known locations if option is omitted.
6573 flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
6576 @deffn {Config Command} {kinetis create_banks}
6577 Configuration command enables automatic creation of additional flash banks
6578 based on real flash layout of device. Banks are created during device probe.
6579 Use 'flash probe 0' to force probe.
6582 @deffn {Command} {kinetis fcf_source} [protection|write]
6583 Select what source is used when writing to a Flash Configuration Field.
6584 @option{protection} mode builds FCF content from protection bits previously
6585 set by 'flash protect' command.
6586 This mode is default. MCU is protected from unwanted locking by immediate
6587 writing FCF after erase of relevant sector.
6588 @option{write} mode enables direct write to FCF.
6589 Protection cannot be set by 'flash protect' command. FCF is written along
6590 with the rest of a flash image.
6591 @emph{BEWARE: Incorrect flash configuration may permanently lock the device!}
6594 @deffn {Command} {kinetis fopt} [num]
6595 Set value to write to FOPT byte of Flash Configuration Field.
6596 Used in kinetis 'fcf_source protection' mode only.
6599 @deffn {Command} {kinetis mdm check_security}
6600 Checks status of device security lock. Used internally in examine-end
6601 and examine-fail event.
6604 @deffn {Command} {kinetis mdm halt}
6605 Issues a halt via the MDM-AP. This command can be used to break a watchdog reset
6606 loop when connecting to an unsecured target.
6609 @deffn {Command} {kinetis mdm mass_erase}
6610 Issues a complete flash erase via the MDM-AP. This can be used to erase a chip
6611 back to its factory state, removing security. It does not require the processor
6612 to be halted, however the target will remain in a halted state after this
6616 @deffn {Command} {kinetis nvm_partition}
6617 For FlexNVM devices only (KxxDX and KxxFX).
6618 Command shows or sets data flash or EEPROM backup size in kilobytes,
6619 sets two EEPROM blocks sizes in bytes and enables/disables loading
6620 of EEPROM contents to FlexRAM during reset.
6622 For details see device reference manual, Flash Memory Module,
6623 Program Partition command.
6625 Setting is possible only once after mass_erase.
6626 Reset the device after partition setting.
6628 Show partition size:
6630 kinetis nvm_partition info
6633 Set 32 KB data flash, rest of FlexNVM is EEPROM backup. EEPROM has two blocks
6634 of 512 and 1536 bytes and its contents is loaded to FlexRAM during reset:
6636 kinetis nvm_partition dataflash 32 512 1536 on
6639 Set 16 KB EEPROM backup, rest of FlexNVM is a data flash. EEPROM has two blocks
6640 of 1024 bytes and its contents is not loaded to FlexRAM during reset:
6642 kinetis nvm_partition eebkp 16 1024 1024 off
6646 @deffn {Command} {kinetis mdm reset}
6647 Issues a reset via the MDM-AP. This causes the MCU to output a low pulse on the
6648 RESET pin, which can be used to reset other hardware on board.
6651 @deffn {Command} {kinetis disable_wdog}
6652 For Kx devices only (KLx has different COP watchdog, it is not supported).
6653 Command disables watchdog timer.
6657 @deffn {Flash Driver} {kinetis_ke}
6659 KE0x and KEAx members of the Kinetis microcontroller family from NXP include
6660 internal flash and use ARM Cortex-M0+. The driver automatically recognizes
6661 the KE0x sub-family using the chip identification register, and
6662 autoconfigures itself.
6663 Use kinetis (not kinetis_ke) driver for KE1x devices.
6666 flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
6669 @deffn {Command} {kinetis_ke mdm check_security}
6670 Checks status of device security lock. Used internally in examine-end event.
6673 @deffn {Command} {kinetis_ke mdm mass_erase}
6674 Issues a complete Flash erase via the MDM-AP.
6675 This can be used to erase a chip back to its factory state.
6676 Command removes security lock from a device (use of SRST highly recommended).
6677 It does not require the processor to be halted.
6680 @deffn {Command} {kinetis_ke disable_wdog}
6681 Command disables watchdog timer.
6685 @deffn {Flash Driver} {lpc2000}
6686 This is the driver to support internal flash of all members of the
6687 LPC11(x)00 and LPC1300 microcontroller families and most members of
6688 the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000, LPC54100,
6689 LPC8Nxx and NHS31xx microcontroller families from NXP.
6692 There are LPC2000 devices which are not supported by the @var{lpc2000}
6694 The LPC2888 is supported by the @var{lpc288x} driver.
6695 The LPC29xx family is supported by the @var{lpc2900} driver.
6698 The @var{lpc2000} driver defines two mandatory and two optional parameters,
6699 which must appear in the following order:
6702 @item @var{variant} ... required, may be
6703 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
6704 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
6705 @option{lpc1700} (LPC175x and LPC176x and LPC177x/8x)
6706 @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
6708 @option{lpc800} (LPC8xx)
6709 @option{lpc1100} (LPC11(x)xx and LPC13xx)
6710 @option{lpc1500} (LPC15xx)
6711 @option{lpc54100} (LPC541xx)
6712 @option{lpc4000} (LPC40xx)
6713 or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
6714 LPC8xx, LPC13xx, LPC17xx, LPC40xx, LPC8Nxx and NHS31xx
6715 @item @var{clock_kHz} ... the frequency, in kiloHertz,
6716 at which the core is running
6717 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
6718 telling the driver to calculate a valid checksum for the exception vector table.
6720 If you don't provide @option{calc_checksum} when you're writing the vector
6721 table, the boot ROM will almost certainly ignore your flash image.
6722 However, if you do provide it,
6723 with most tool chains @command{verify_image} will fail.
6725 @item @option{iap_entry} ... optional telling the driver to use a different
6726 ROM IAP entry point.
6729 LPC flashes don't require the chip and bus width to be specified.
6732 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
6733 lpc2000_v2 14765 calc_checksum
6736 @deffn {Command} {lpc2000 part_id} bank
6737 Displays the four byte part identifier associated with
6738 the specified flash @var{bank}.
6742 @deffn {Flash Driver} {lpc288x}
6743 The LPC2888 microcontroller from NXP needs slightly different flash
6744 support from its lpc2000 siblings.
6745 The @var{lpc288x} driver defines one mandatory parameter,
6746 the programming clock rate in Hz.
6747 LPC flashes don't require the chip and bus width to be specified.
6750 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
6754 @deffn {Flash Driver} {lpc2900}
6755 This driver supports the LPC29xx ARM968E based microcontroller family
6758 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
6759 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
6760 sector layout are auto-configured by the driver.
6761 The driver has one additional mandatory parameter: The CPU clock rate
6762 (in kHz) at the time the flash operations will take place. Most of the time this
6763 will not be the crystal frequency, but a higher PLL frequency. The
6764 @code{reset-init} event handler in the board script is usually the place where
6767 The driver rejects flashless devices (currently the LPC2930).
6769 The EEPROM in LPC2900 devices is not mapped directly into the address space.
6770 It must be handled much more like NAND flash memory, and will therefore be
6771 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
6773 Sector protection in terms of the LPC2900 is handled transparently. Every time a
6774 sector needs to be erased or programmed, it is automatically unprotected.
6775 What is shown as protection status in the @code{flash info} command, is
6776 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
6777 sector from ever being erased or programmed again. As this is an irreversible
6778 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
6779 and not by the standard @code{flash protect} command.
6781 Example for a 125 MHz clock frequency:
6783 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
6786 Some @code{lpc2900}-specific commands are defined. In the following command list,
6787 the @var{bank} parameter is the bank number as obtained by the
6788 @code{flash banks} command.
6790 @deffn {Command} {lpc2900 signature} bank
6791 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
6792 content. This is a hardware feature of the flash block, hence the calculation is
6793 very fast. You may use this to verify the content of a programmed device against
6798 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
6802 @deffn {Command} {lpc2900 read_custom} bank filename
6803 Reads the 912 bytes of customer information from the flash index sector, and
6804 saves it to a file in binary format.
6807 lpc2900 read_custom 0 /path_to/customer_info.bin
6811 The index sector of the flash is a @emph{write-only} sector. It cannot be
6812 erased! In order to guard against unintentional write access, all following
6813 commands need to be preceded by a successful call to the @code{password}
6816 @deffn {Command} {lpc2900 password} bank password
6817 You need to use this command right before each of the following commands:
6818 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
6819 @code{lpc2900 secure_jtag}.
6821 The password string is fixed to "I_know_what_I_am_doing".
6824 lpc2900 password 0 I_know_what_I_am_doing
6825 Potentially dangerous operation allowed in next command!
6829 @deffn {Command} {lpc2900 write_custom} bank filename type
6830 Writes the content of the file into the customer info space of the flash index
6831 sector. The filetype can be specified with the @var{type} field. Possible values
6832 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
6833 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
6834 contain a single section, and the contained data length must be exactly
6836 @quotation Attention
6837 This cannot be reverted! Be careful!
6841 lpc2900 write_custom 0 /path_to/customer_info.bin bin
6845 @deffn {Command} {lpc2900 secure_sector} bank first last
6846 Secures the sector range from @var{first} to @var{last} (including) against
6847 further program and erase operations. The sector security will be effective
6848 after the next power cycle.
6849 @quotation Attention
6850 This cannot be reverted! Be careful!
6852 Secured sectors appear as @emph{protected} in the @code{flash info} command.
6855 lpc2900 secure_sector 0 1 1
6857 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
6858 # 0: 0x00000000 (0x2000 8kB) not protected
6859 # 1: 0x00002000 (0x2000 8kB) protected
6860 # 2: 0x00004000 (0x2000 8kB) not protected
6864 @deffn {Command} {lpc2900 secure_jtag} bank
6865 Irreversibly disable the JTAG port. The new JTAG security setting will be
6866 effective after the next power cycle.
6867 @quotation Attention
6868 This cannot be reverted! Be careful!
6872 lpc2900 secure_jtag 0
6877 @deffn {Flash Driver} {mdr}
6878 This drivers handles the integrated NOR flash on Milandr Cortex-M
6879 based controllers. A known limitation is that the Info memory can't be
6880 read or verified as it's not memory mapped.
6883 flash bank <name> mdr <base> <size> \
6884 0 0 <target#> @var{type} @var{page_count} @var{sec_count}
6888 @item @var{type} - 0 for main memory, 1 for info memory
6889 @item @var{page_count} - total number of pages
6890 @item @var{sec_count} - number of sector per page count
6895 if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
6896 flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \
6897 0 0 $_TARGETNAME 1 1 4
6899 flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
6900 0 0 $_TARGETNAME 0 32 4
6905 @deffn {Flash Driver} {msp432}
6906 All versions of the SimpleLink MSP432 microcontrollers from Texas
6907 Instruments include internal flash. The msp432 flash driver automatically
6908 recognizes the specific version's flash parameters and autoconfigures itself.
6909 Main program flash starts at address 0. The information flash region on
6910 MSP432P4 versions starts at address 0x200000.
6913 flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
6916 @deffn {Command} {msp432 mass_erase} bank_id [main|all]
6917 Performs a complete erase of flash. By default, @command{mass_erase} will erase
6918 only the main program flash.
6920 On MSP432P4 versions, using @command{mass_erase all} will erase both the
6921 main program and information flash regions. To also erase the BSL in information
6922 flash, the user must first use the @command{bsl} command.
6925 @deffn {Command} {msp432 bsl} bank_id [unlock|lock]
6926 On MSP432P4 versions, @command{bsl} unlocks and locks the bootstrap loader (BSL)
6927 region in information flash so that flash commands can erase or write the BSL.
6928 Leave the BSL locked to prevent accidentally corrupting the bootstrap loader.
6930 To erase and program the BSL:
6933 flash erase_address 0x202000 0x2000
6934 flash write_image bsl.bin 0x202000
6940 @deffn {Flash Driver} {niietcm4}
6941 This drivers handles the integrated NOR flash on NIIET Cortex-M4
6942 based controllers. Flash size and sector layout are auto-configured by the driver.
6943 Main flash memory is called "Bootflash" and has main region and info region.
6944 Info region is NOT memory mapped by default,
6945 but it can replace first part of main region if needed.
6946 Full erase, single and block writes are supported for both main and info regions.
6947 There is additional not memory mapped flash called "Userflash", which
6948 also have division into regions: main and info.
6949 Purpose of userflash - to store system and user settings.
6950 Driver has special commands to perform operations with this memory.
6953 flash bank $_FLASHNAME niietcm4 0 0 0 0 $_TARGETNAME
6956 Some niietcm4-specific commands are defined:
6958 @deffn {Command} {niietcm4 uflash_read_byte} bank ('main'|'info') address
6959 Read byte from main or info userflash region.
6962 @deffn {Command} {niietcm4 uflash_write_byte} bank ('main'|'info') address value
6963 Write byte to main or info userflash region.
6966 @deffn {Command} {niietcm4 uflash_full_erase} bank
6967 Erase all userflash including info region.
6970 @deffn {Command} {niietcm4 uflash_erase} bank ('main'|'info') first_sector last_sector
6971 Erase sectors of main or info userflash region, starting at sector first up to and including last.
6974 @deffn {Command} {niietcm4 uflash_protect_check} bank ('main'|'info')
6975 Check sectors protect.
6978 @deffn {Command} {niietcm4 uflash_protect} bank ('main'|'info') first_sector last_sector ('on'|'off')
6979 Protect sectors of main or info userflash region, starting at sector first up to and including last.
6982 @deffn {Command} {niietcm4 bflash_info_remap} bank ('on'|'off')
6983 Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).
6986 @deffn {Command} {niietcm4 extmem_cfg} bank ('gpioa'|'gpiob'|'gpioc'|'gpiod'|'gpioe'|'gpiof'|'gpiog'|'gpioh') pin_num ('func1'|'func3')
6987 Configure external memory interface for boot.
6990 @deffn {Command} {niietcm4 service_mode_erase} bank
6991 Perform emergency erase of all flash (bootflash and userflash).
6994 @deffn {Command} {niietcm4 driver_info} bank
6995 Show information about flash driver.
7000 @deffn {Flash Driver} {npcx}
7001 All versions of the NPCX microcontroller families from Nuvoton include internal
7002 flash. The NPCX flash driver supports the NPCX family of devices. The driver
7003 automatically recognizes the specific version's flash parameters and
7004 autoconfigures itself. The flash bank starts at address 0x64000000.
7007 flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME
7011 @deffn {Flash Driver} {nrf5}
7012 All members of the nRF51 microcontroller families from Nordic Semiconductor
7013 include internal flash and use ARM Cortex-M0 core. nRF52 family powered
7014 by ARM Cortex-M4 or M4F core is supported too. nRF52832 is fully supported
7015 including BPROT flash protection scheme. nRF52833 and nRF52840 devices are
7016 supported with the exception of security extensions (flash access control list
7020 flash bank $_FLASHNAME nrf5 0 0x00000000 0 0 $_TARGETNAME
7023 Some nrf5-specific commands are defined:
7025 @deffn {Command} {nrf5 mass_erase}
7026 Erases the contents of the code memory and user information
7027 configuration registers as well. It must be noted that this command
7028 works only for chips that do not have factory pre-programmed region 0
7032 @deffn {Command} {nrf5 info}
7033 Decodes and shows information from FICR and UICR registers.
7038 @deffn {Flash Driver} {ocl}
7039 This driver is an implementation of the ``on chip flash loader''
7040 protocol proposed by Pavel Chromy.
7042 It is a minimalistic command-response protocol intended to be used
7043 over a DCC when communicating with an internal or external flash
7044 loader running from RAM. An example implementation for AT91SAM7x is
7045 available in @file{contrib/loaders/flash/at91sam7x/}.
7048 flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
7052 @deffn {Flash Driver} {pic32mx}
7053 The PIC32MX microcontrollers are based on the MIPS 4K cores,
7054 and integrate flash memory.
7057 flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
7058 flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
7061 @comment numerous *disabled* commands are defined:
7062 @comment - chip_erase ... pointless given flash_erase_address
7063 @comment - lock, unlock ... pointless given protect on/off (yes?)
7064 @comment - pgm_word ... shouldn't bank be deduced from address??
7065 Some pic32mx-specific commands are defined:
7066 @deffn {Command} {pic32mx pgm_word} address value bank
7067 Programs the specified 32-bit @var{value} at the given @var{address}
7068 in the specified chip @var{bank}.
7070 @deffn {Command} {pic32mx unlock} bank
7071 Unlock and erase specified chip @var{bank}.
7072 This will remove any Code Protection.
7076 @deffn {Flash Driver} {psoc4}
7077 All members of the PSoC 41xx/42xx microcontroller family from Cypress
7078 include internal flash and use ARM Cortex-M0 cores.
7079 The driver automatically recognizes a number of these chips using
7080 the chip identification register, and autoconfigures itself.
7082 Note: Erased internal flash reads as 00.
7083 System ROM of PSoC 4 does not implement erase of a flash sector.
7086 flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
7089 psoc4-specific commands
7090 @deffn {Command} {psoc4 flash_autoerase} num (on|off)
7091 Enables or disables autoerase mode for a flash bank.
7093 If flash_autoerase is off, use mass_erase before flash programming.
7094 Flash erase command fails if region to erase is not whole flash memory.
7096 If flash_autoerase is on, a sector is both erased and programmed in one
7097 system ROM call. Flash erase command is ignored.
7098 This mode is suitable for gdb load.
7100 The @var{num} parameter is a value shown by @command{flash banks}.
7103 @deffn {Command} {psoc4 mass_erase} num
7104 Erases the contents of the flash memory, protection and security lock.
7106 The @var{num} parameter is a value shown by @command{flash banks}.
7110 @deffn {Flash Driver} {psoc5lp}
7111 All members of the PSoC 5LP microcontroller family from Cypress
7112 include internal program flash and use ARM Cortex-M3 cores.
7113 The driver probes for a number of these chips and autoconfigures itself,
7114 apart from the base address.
7117 flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
7120 @b{Note:} PSoC 5LP chips can be configured to have ECC enabled or disabled.
7121 @quotation Attention
7122 If flash operations are performed in ECC-disabled mode, they will also affect
7123 the ECC flash region. Erasing a 16k flash sector in the 0x00000000 area will
7124 then also erase the corresponding 2k data bytes in the 0x48000000 area.
7125 Writing to the ECC data bytes in ECC-disabled mode is not implemented.
7128 Commands defined in the @var{psoc5lp} driver:
7130 @deffn {Command} {psoc5lp mass_erase}
7131 Erases all flash data and ECC/configuration bytes, all flash protection rows,
7132 and all row latches in all flash arrays on the device.
7136 @deffn {Flash Driver} {psoc5lp_eeprom}
7137 All members of the PSoC 5LP microcontroller family from Cypress
7138 include internal EEPROM and use ARM Cortex-M3 cores.
7139 The driver probes for a number of these chips and autoconfigures itself,
7140 apart from the base address.
7143 flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 \
7148 @deffn {Flash Driver} {psoc5lp_nvl}
7149 All members of the PSoC 5LP microcontroller family from Cypress
7150 include internal Nonvolatile Latches and use ARM Cortex-M3 cores.
7151 The driver probes for a number of these chips and autoconfigures itself.
7154 flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME
7157 PSoC 5LP chips have multiple NV Latches:
7160 @item Device Configuration NV Latch - 4 bytes
7161 @item Write Once (WO) NV Latch - 4 bytes
7164 @b{Note:} This driver only implements the Device Configuration NVL.
7166 The @var{psoc5lp} driver reads the ECC mode from Device Configuration NVL.
7167 @quotation Attention
7168 Switching ECC mode via write to Device Configuration NVL will require a reset
7169 after successful write.
7173 @deffn {Flash Driver} {psoc6}
7174 Supports PSoC6 (CY8C6xxx) family of Cypress microcontrollers.
7175 PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
7176 the same Flash/RAM/MMIO address space.
7178 Flash in PSoC6 is split into three regions:
7180 @item Main Flash - this is the main storage for user application.
7181 Total size varies among devices, sector size: 256 kBytes, row size:
7182 512 bytes. Supports erase operation on individual rows.
7183 @item Work Flash - intended to be used as storage for user data
7184 (e.g. EEPROM emulation). Total size: 32 KBytes, sector size: 32 KBytes,
7185 row size: 512 bytes.
7186 @item Supervisory Flash - special region which contains device-specific
7187 service data. This region does not support erase operation. Only few rows can
7188 be programmed by the user, most of the rows are read only. Programming
7189 operation will erase row automatically.
7192 All three flash regions are supported by the driver. Flash geometry is detected
7193 automatically by parsing data in SPCIF_GEOMETRY register.
7195 PSoC6 is equipped with NOR Flash so erased Flash reads as 0x00.
7198 flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 \
7200 flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 \
7202 flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 \
7204 flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 \
7206 flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 \
7208 flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 \
7211 flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 \
7213 flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 \
7215 flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 \
7217 flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 \
7219 flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 \
7221 flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 \
7225 psoc6-specific commands
7226 @deffn {Command} {psoc6 reset_halt}
7227 Command can be used to simulate broken Vector Catch from gdbinit or tcl scripts.
7228 When invoked for CM0+ target, it will set break point at application entry point
7229 and issue SYSRESETREQ. This will reset both cores and all peripherals. CM0+ will
7230 reset CM4 during boot anyway so this is safe. On CM4 target, VECTRESET is used
7231 instead of SYSRESETREQ to avoid unwanted reset of CM0+;
7234 @deffn {Command} {psoc6 mass_erase} num
7235 Erases the contents given flash bank. The @var{num} parameter is a value shown
7236 by @command{flash banks}.
7237 Note: only Main and Work flash regions support Erase operation.
7241 @deffn {Flash Driver} {rp2040}
7242 Supports RP2040 "Raspberry Pi Pico" microcontroller.
7243 RP2040 is a dual-core device with two CM0+ cores. Both cores share the same
7244 Flash/RAM/MMIO address space. Non-volatile storage is achieved with an
7245 external QSPI flash; a Boot ROM provides helper functions.
7248 flash bank $_FLASHNAME rp2040_flash $_FLASHBASE $_FLASHSIZE 1 32 $_TARGETNAME
7252 @deffn {Flash Driver} {sim3x}
7253 All members of the SiM3 microcontroller family from Silicon Laboratories
7254 include internal flash and use ARM Cortex-M3 cores. It supports both JTAG
7256 The @var{sim3x} driver tries to probe the device to auto detect the MCU.
7257 If this fails, it will use the @var{size} parameter as the size of flash bank.
7260 flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
7263 There are 2 commands defined in the @var{sim3x} driver:
7265 @deffn {Command} {sim3x mass_erase}
7266 Erases the complete flash. This is used to unlock the flash.
7267 And this command is only possible when using the SWD interface.
7270 @deffn {Command} {sim3x lock}
7271 Lock the flash. To unlock use the @command{sim3x mass_erase} command.
7275 @deffn {Flash Driver} {stellaris}
7276 All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
7277 families from Texas Instruments include internal flash. The driver
7278 automatically recognizes a number of these chips using the chip
7279 identification register, and autoconfigures itself.
7282 flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
7285 @deffn {Command} {stellaris recover}
7286 Performs the @emph{Recovering a "Locked" Device} procedure to restore
7287 the flash and its associated nonvolatile registers to their factory
7288 default values (erased). This is the only way to remove flash
7289 protection or re-enable debugging if that capability has been
7292 Note that the final "power cycle the chip" step in this procedure
7293 must be performed by hand, since OpenOCD can't do it.
7295 if more than one Stellaris chip is connected, the procedure is
7296 applied to all of them.
7301 @deffn {Flash Driver} {stm32f1x}
7302 All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
7303 from STMicroelectronics and all members of the GD32F1x0, GD32F3x0 and GD32E23x microcontroller
7304 families from GigaDevice include internal flash and use ARM Cortex-M0/M3/M4/M23 cores.
7305 The driver also works with GD32VF103 powered by RISC-V core.
7306 The driver automatically recognizes a number of these chips using
7307 the chip identification register, and autoconfigures itself.
7310 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
7313 Note that some devices have been found that have a flash size register that contains
7314 an invalid value, to workaround this issue you can override the probed value used by
7318 flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
7321 If you have a target with dual flash banks then define the second bank
7322 as per the following example.
7324 flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
7327 Some stm32f1x-specific commands are defined:
7329 @deffn {Command} {stm32f1x lock} num
7330 Locks the entire stm32 device against reading.
7331 The @var{num} parameter is a value shown by @command{flash banks}.
7334 @deffn {Command} {stm32f1x unlock} num
7335 Unlocks the entire stm32 device for reading. This command will cause
7336 a mass erase of the entire stm32 device if previously locked.
7337 The @var{num} parameter is a value shown by @command{flash banks}.
7340 @deffn {Command} {stm32f1x mass_erase} num
7341 Mass erases the entire stm32 device.
7342 The @var{num} parameter is a value shown by @command{flash banks}.
7345 @deffn {Command} {stm32f1x options_read} num
7346 Reads and displays active stm32 option bytes loaded during POR
7347 or upon executing the @command{stm32f1x options_load} command.
7348 The @var{num} parameter is a value shown by @command{flash banks}.
7351 @deffn {Command} {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP}) (@option{USEROPT} user_data)
7352 Writes the stm32 option byte with the specified values.
7353 The @var{num} parameter is a value shown by @command{flash banks}.
7354 The @var{user_data} parameter is content of higher 16 bits of the option byte register (Data0 and Data1 as one 16bit number).
7357 @deffn {Command} {stm32f1x options_load} num
7358 Generates a special kind of reset to re-load the stm32 option bytes written
7359 by the @command{stm32f1x options_write} or @command{flash protect} commands
7360 without having to power cycle the target. Not applicable to stm32f1x devices.
7361 The @var{num} parameter is a value shown by @command{flash banks}.
7365 @deffn {Flash Driver} {stm32f2x}
7366 All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from STMicroelectronics
7367 include internal flash and use ARM Cortex-M3/M4/M7 cores.
7368 The driver automatically recognizes a number of these chips using
7369 the chip identification register, and autoconfigures itself.
7372 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
7375 If you use OTP (One-Time Programmable) memory define it as a second bank
7376 as per the following example.
7378 flash bank $_FLASHNAME stm32f2x 0x1FFF7800 0 0 0 $_TARGETNAME
7381 @deffn {Command} {stm32f2x otp} num (@option{enable}|@option{disable}|@option{show})
7382 Enables or disables OTP write commands for bank @var{num}.
7383 The @var{num} parameter is a value shown by @command{flash banks}.
7386 Note that some devices have been found that have a flash size register that contains
7387 an invalid value, to workaround this issue you can override the probed value used by
7391 flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
7394 Some stm32f2x-specific commands are defined:
7396 @deffn {Command} {stm32f2x lock} num
7397 Locks the entire stm32 device.
7398 The @var{num} parameter is a value shown by @command{flash banks}.
7401 @deffn {Command} {stm32f2x unlock} num
7402 Unlocks the entire stm32 device.
7403 The @var{num} parameter is a value shown by @command{flash banks}.
7406 @deffn {Command} {stm32f2x mass_erase} num
7407 Mass erases the entire stm32f2x device.
7408 The @var{num} parameter is a value shown by @command{flash banks}.
7411 @deffn {Command} {stm32f2x options_read} num
7412 Reads and displays user options and (where implemented) boot_addr0, boot_addr1, optcr2.
7413 The @var{num} parameter is a value shown by @command{flash banks}.
7416 @deffn {Command} {stm32f2x options_write} num user_options boot_addr0 boot_addr1
7417 Writes user options and (where implemented) boot_addr0 and boot_addr1 in raw format.
7418 Warning: The meaning of the various bits depends on the device, always check datasheet!
7419 The @var{num} parameter is a value shown by @command{flash banks}, @var{user_options} a
7420 12 bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR, @var{boot_addr0} and
7421 @var{boot_addr1} two halfwords (of FLASH_OPTCR1).
7424 @deffn {Command} {stm32f2x optcr2_write} num optcr2
7425 Writes FLASH_OPTCR2 options. Warning: Clearing PCROPi bits requires a full mass erase!
7426 The @var{num} parameter is a value shown by @command{flash banks}, @var{optcr2} a 32-bit word.
7430 @deffn {Flash Driver} {stm32h7x}
7431 All members of the STM32H7 microcontroller families from STMicroelectronics
7432 include internal flash and use ARM Cortex-M7 core.
7433 The driver automatically recognizes a number of these chips using
7434 the chip identification register, and autoconfigures itself.
7437 flash bank $_FLASHNAME stm32h7x 0 0 0 0 $_TARGETNAME
7440 Note that some devices have been found that have a flash size register that contains
7441 an invalid value, to workaround this issue you can override the probed value used by
7445 flash bank $_FLASHNAME stm32h7x 0 0x20000 0 0 $_TARGETNAME
7448 Some stm32h7x-specific commands are defined:
7450 @deffn {Command} {stm32h7x lock} num
7451 Locks the entire stm32 device.
7452 The @var{num} parameter is a value shown by @command{flash banks}.
7455 @deffn {Command} {stm32h7x unlock} num
7456 Unlocks the entire stm32 device.
7457 The @var{num} parameter is a value shown by @command{flash banks}.
7460 @deffn {Command} {stm32h7x mass_erase} num
7461 Mass erases the entire stm32h7x device.
7462 The @var{num} parameter is a value shown by @command{flash banks}.
7465 @deffn {Command} {stm32h7x option_read} num reg_offset
7466 Reads an option byte register from the stm32h7x device.
7467 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7468 is the register offset of the option byte to read from the used bank registers' base.
7469 For example: in STM32H74x/H75x the bank 1 registers' base is 0x52002000 and 0x52002100 for bank 2.
7474 stm32h7x option_read 0 0x1c
7476 stm32h7x option_read 0 0x38
7478 stm32h7x option_read 1 0x38
7482 @deffn {Command} {stm32h7x option_write} num reg_offset value [reg_mask]
7483 Writes an option byte register of the stm32h7x device.
7484 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7485 is the register offset of the option byte to write from the used bank register base,
7486 and @var{reg_mask} is the mask to apply when writing the register (only bits with a '1'
7491 # swap bank 1 and bank 2 in dual bank devices
7492 # by setting SWAP_BANK_OPT bit in OPTSR_PRG
7493 stm32h7x option_write 0 0x20 0x8000000 0x8000000
7498 @deffn {Flash Driver} {stm32lx}
7499 All members of the STM32L0 and STM32L1 microcontroller families from STMicroelectronics
7500 include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
7501 The driver automatically recognizes a number of these chips using
7502 the chip identification register, and autoconfigures itself.
7505 flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
7508 Note that some devices have been found that have a flash size register that contains
7509 an invalid value, to workaround this issue you can override the probed value used by
7510 the flash driver. If you use 0 as the bank base address, it tells the
7511 driver to autodetect the bank location assuming you're configuring the
7515 flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
7518 Some stm32lx-specific commands are defined:
7520 @deffn {Command} {stm32lx lock} num
7521 Locks the entire stm32 device.
7522 The @var{num} parameter is a value shown by @command{flash banks}.
7525 @deffn {Command} {stm32lx unlock} num
7526 Unlocks the entire stm32 device.
7527 The @var{num} parameter is a value shown by @command{flash banks}.
7530 @deffn {Command} {stm32lx mass_erase} num
7531 Mass erases the entire stm32lx device (all flash banks and EEPROM
7532 data). This is the only way to unlock a protected flash (unless RDP
7533 Level is 2 which can't be unlocked at all).
7534 The @var{num} parameter is a value shown by @command{flash banks}.
7538 @deffn {Flash Driver} {stm32l4x}
7539 All members of the STM32 G0, G4, L4, L4+, L5, U5, WB and WL
7540 microcontroller families from STMicroelectronics include internal flash
7541 and use ARM Cortex-M0+, M4 and M33 cores.
7542 The driver automatically recognizes a number of these chips using
7543 the chip identification register, and autoconfigures itself.
7546 flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
7549 If you use OTP (One-Time Programmable) memory define it as a second bank
7550 as per the following example.
7552 flash bank $_FLASHNAME stm32l4x 0x1FFF7000 0 0 0 $_TARGETNAME
7555 @deffn {Command} {stm32l4x otp} num (@option{enable}|@option{disable}|@option{show})
7556 Enables or disables OTP write commands for bank @var{num}.
7557 The @var{num} parameter is a value shown by @command{flash banks}.
7560 Note that some devices have been found that have a flash size register that contains
7561 an invalid value, to workaround this issue you can override the probed value used by
7562 the flash driver. However, specifying a wrong value might lead to a completely
7563 wrong flash layout, so this feature must be used carefully.
7566 flash bank $_FLASHNAME stm32l4x 0x08000000 0x40000 0 0 $_TARGETNAME
7569 Some stm32l4x-specific commands are defined:
7571 @deffn {Command} {stm32l4x lock} num
7572 Locks the entire stm32 device.
7573 The @var{num} parameter is a value shown by @command{flash banks}.
7575 @emph{Note:} To apply the protection change immediately, use @command{stm32l4x option_load}.
7578 @deffn {Command} {stm32l4x unlock} num
7579 Unlocks the entire stm32 device.
7580 The @var{num} parameter is a value shown by @command{flash banks}.
7582 @emph{Note:} To apply the protection change immediately, use @command{stm32l4x option_load}.
7585 @deffn {Command} {stm32l4x mass_erase} num
7586 Mass erases the entire stm32l4x device.
7587 The @var{num} parameter is a value shown by @command{flash banks}.
7590 @deffn {Command} {stm32l4x option_read} num reg_offset
7591 Reads an option byte register from the stm32l4x device.
7592 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7593 is the register offset of the Option byte to read.
7595 For example to read the FLASH_OPTR register:
7597 stm32l4x option_read 0 0x20
7598 # Option Register (for STM32L4x): <0x40022020> = 0xffeff8aa
7599 # Option Register (for STM32WBx): <0x58004020> = ...
7600 # The correct flash base address will be used automatically
7603 The above example will read out the FLASH_OPTR register which contains the RDP
7604 option byte, Watchdog configuration, BOR level etc.
7607 @deffn {Command} {stm32l4x option_write} num reg_offset reg_mask
7608 Write an option byte register of the stm32l4x device.
7609 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7610 is the register offset of the Option byte to write, and @var{reg_mask} is the mask
7611 to apply when writing the register (only bits with a '1' will be touched).
7613 @emph{Note:} To apply the option bytes change immediately, use @command{stm32l4x option_load}.
7615 For example to write the WRP1AR option bytes:
7617 stm32l4x option_write 0 0x28 0x00FF0000 0x00FF00FF
7620 The above example will write the WRP1AR option register configuring the Write protection
7621 Area A for bank 1. The above example set WRP1AR_END=255, WRP1AR_START=0.
7622 This will effectively write protect all sectors in flash bank 1.
7625 @deffn {Command} {stm32l4x wrp_info} num [device_bank]
7626 List the protected areas using WRP.
7627 The @var{num} parameter is a value shown by @command{flash banks}.
7628 @var{device_bank} parameter is optional, possible values 'bank1' or 'bank2',
7629 if not specified, the command will display the whole flash protected areas.
7631 @b{Note:} @var{device_bank} is different from banks created using @code{flash bank}.
7632 Devices supported in this flash driver, can have main flash memory organized
7633 in single or dual-banks mode.
7634 Thus the usage of @var{device_bank} is meaningful only in dual-bank mode, to get
7635 write protected areas in a specific @var{device_bank}
7639 @deffn {Command} {stm32l4x option_load} num
7640 Forces a re-load of the option byte registers. Will cause a system reset of the device.
7641 The @var{num} parameter is a value shown by @command{flash banks}.
7644 @deffn Command {stm32l4x trustzone} num [@option{enable} | @option{disable}]
7645 Enables or disables Global TrustZone Security, using the TZEN option bit.
7646 If neither @option{enabled} nor @option{disable} are specified, the command will display
7647 the TrustZone status.
7648 @emph{Note:} This command works only with devices with TrustZone, eg. STM32L5.
7649 @emph{Note:} This command will perform an OBL_Launch after modifying the TZEN.
7653 @deffn {Flash Driver} {str7x}
7654 All members of the STR7 microcontroller family from STMicroelectronics
7655 include internal flash and use ARM7TDMI cores.
7656 The @var{str7x} driver defines one mandatory parameter, @var{variant},
7657 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
7660 flash bank $_FLASHNAME str7x \
7661 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
7664 @deffn {Command} {str7x disable_jtag} bank
7665 Activate the Debug/Readout protection mechanism
7666 for the specified flash bank.
7670 @deffn {Flash Driver} {str9x}
7671 Most members of the STR9 microcontroller family from STMicroelectronics
7672 include internal flash and use ARM966E cores.
7673 The str9 needs the flash controller to be configured using
7674 the @command{str9x flash_config} command prior to Flash programming.
7677 flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
7678 str9x flash_config 0 4 2 0 0x80000
7681 @deffn {Command} {str9x flash_config} num bbsr nbbsr bbadr nbbadr
7682 Configures the str9 flash controller.
7683 The @var{num} parameter is a value shown by @command{flash banks}.
7686 @item @var{bbsr} - Boot Bank Size register
7687 @item @var{nbbsr} - Non Boot Bank Size register
7688 @item @var{bbadr} - Boot Bank Start Address register
7689 @item @var{nbbadr} - Boot Bank Start Address register
7695 @deffn {Flash Driver} {str9xpec}
7698 Only use this driver for locking/unlocking the device or configuring the option bytes.
7699 Use the standard str9 driver for programming.
7700 Before using the flash commands the turbo mode must be enabled using the
7701 @command{str9xpec enable_turbo} command.
7703 Here is some background info to help
7704 you better understand how this driver works. OpenOCD has two flash drivers for
7708 Standard driver @option{str9x} programmed via the str9 core. Normally used for
7709 flash programming as it is faster than the @option{str9xpec} driver.
7711 Direct programming @option{str9xpec} using the flash controller. This is an
7712 ISC compliant (IEEE 1532) tap connected in series with the str9 core. The str9
7713 core does not need to be running to program using this flash driver. Typical use
7714 for this driver is locking/unlocking the target and programming the option bytes.
7717 Before we run any commands using the @option{str9xpec} driver we must first disable
7718 the str9 core. This example assumes the @option{str9xpec} driver has been
7719 configured for flash bank 0.
7721 # assert srst, we do not want core running
7722 # while accessing str9xpec flash driver
7724 # turn off target polling
7727 str9xpec enable_turbo 0
7729 str9xpec options_read 0
7730 # re-enable str9 core
7731 str9xpec disable_turbo 0
7735 The above example will read the str9 option bytes.
7736 When performing a unlock remember that you will not be able to halt the str9 - it
7737 has been locked. Halting the core is not required for the @option{str9xpec} driver
7738 as mentioned above, just issue the commands above manually or from a telnet prompt.
7740 Several str9xpec-specific commands are defined:
7742 @deffn {Command} {str9xpec disable_turbo} num
7743 Restore the str9 into JTAG chain.
7746 @deffn {Command} {str9xpec enable_turbo} num
7747 Enable turbo mode, will simply remove the str9 from the chain and talk
7748 directly to the embedded flash controller.
7751 @deffn {Command} {str9xpec lock} num
7752 Lock str9 device. The str9 will only respond to an unlock command that will
7756 @deffn {Command} {str9xpec part_id} num
7757 Prints the part identifier for bank @var{num}.
7760 @deffn {Command} {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
7761 Configure str9 boot bank.
7764 @deffn {Command} {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
7765 Configure str9 lvd source.
7768 @deffn {Command} {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
7769 Configure str9 lvd threshold.
7772 @deffn {Command} {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
7773 Configure str9 lvd reset warning source.
7776 @deffn {Command} {str9xpec options_read} num
7777 Read str9 option bytes.
7780 @deffn {Command} {str9xpec options_write} num
7781 Write str9 option bytes.
7784 @deffn {Command} {str9xpec unlock} num
7790 @deffn {Flash Driver} {swm050}
7792 All members of the swm050 microcontroller family from Foshan Synwit Tech.
7795 flash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME
7798 One swm050-specific command is defined:
7800 @deffn {Command} {swm050 mass_erase} bank_id
7801 Erases the entire flash bank.
7807 @deffn {Flash Driver} {tms470}
7808 Most members of the TMS470 microcontroller family from Texas Instruments
7809 include internal flash and use ARM7TDMI cores.
7810 This driver doesn't require the chip and bus width to be specified.
7812 Some tms470-specific commands are defined:
7814 @deffn {Command} {tms470 flash_keyset} key0 key1 key2 key3
7815 Saves programming keys in a register, to enable flash erase and write commands.
7818 @deffn {Command} {tms470 osc_megahertz} clock_mhz
7819 Reports the clock speed, which is used to calculate timings.
7822 @deffn {Command} {tms470 plldis} (0|1)
7823 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
7828 @deffn {Flash Driver} {w600}
7829 W60x series Wi-Fi SoC from WinnerMicro
7830 are designed with ARM Cortex-M3 and have 1M Byte QFLASH inside.
7831 The @var{w600} driver uses the @var{target} parameter to select the
7832 correct bank config.
7835 flash bank $_FLASHNAME w600 0x08000000 0 0 0 $_TARGETNAMEs
7839 @deffn {Flash Driver} {xmc1xxx}
7840 All members of the XMC1xxx microcontroller family from Infineon.
7841 This driver does not require the chip and bus width to be specified.
7844 @deffn {Flash Driver} {xmc4xxx}
7845 All members of the XMC4xxx microcontroller family from Infineon.
7846 This driver does not require the chip and bus width to be specified.
7848 Some xmc4xxx-specific commands are defined:
7850 @deffn {Command} {xmc4xxx flash_password} bank_id passwd1 passwd2
7851 Saves flash protection passwords which are used to lock the user flash
7854 @deffn {Command} {xmc4xxx flash_unprotect} bank_id user_level[0-1]
7855 Removes Flash write protection from the selected user bank
7860 @section NAND Flash Commands
7863 Compared to NOR or SPI flash, NAND devices are inexpensive
7864 and high density. Today's NAND chips, and multi-chip modules,
7865 commonly hold multiple GigaBytes of data.
7867 NAND chips consist of a number of ``erase blocks'' of a given
7868 size (such as 128 KBytes), each of which is divided into a
7869 number of pages (of perhaps 512 or 2048 bytes each). Each
7870 page of a NAND flash has an ``out of band'' (OOB) area to hold
7871 Error Correcting Code (ECC) and other metadata, usually 16 bytes
7872 of OOB for every 512 bytes of page data.
7874 One key characteristic of NAND flash is that its error rate
7875 is higher than that of NOR flash. In normal operation, that
7876 ECC is used to correct and detect errors. However, NAND
7877 blocks can also wear out and become unusable; those blocks
7878 are then marked "bad". NAND chips are even shipped from the
7879 manufacturer with a few bad blocks. The highest density chips
7880 use a technology (MLC) that wears out more quickly, so ECC
7881 support is increasingly important as a way to detect blocks
7882 that have begun to fail, and help to preserve data integrity
7883 with techniques such as wear leveling.
7885 Software is used to manage the ECC. Some controllers don't
7886 support ECC directly; in those cases, software ECC is used.
7887 Other controllers speed up the ECC calculations with hardware.
7888 Single-bit error correction hardware is routine. Controllers
7889 geared for newer MLC chips may correct 4 or more errors for
7890 every 512 bytes of data.
7892 You will need to make sure that any data you write using
7893 OpenOCD includes the appropriate kind of ECC. For example,
7894 that may mean passing the @code{oob_softecc} flag when
7895 writing NAND data, or ensuring that the correct hardware
7898 The basic steps for using NAND devices include:
7900 @item Declare via the command @command{nand device}
7901 @* Do this in a board-specific configuration file,
7902 passing parameters as needed by the controller.
7903 @item Configure each device using @command{nand probe}.
7904 @* Do this only after the associated target is set up,
7905 such as in its reset-init script or in procures defined
7906 to access that device.
7907 @item Operate on the flash via @command{nand subcommand}
7908 @* Often commands to manipulate the flash are typed by a human, or run
7909 via a script in some automated way. Common task include writing a
7910 boot loader, operating system, or other data needed to initialize or
7914 @b{NOTE:} At the time this text was written, the largest NAND
7915 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
7916 This is because the variables used to hold offsets and lengths
7917 are only 32 bits wide.
7918 (Larger chips may work in some cases, unless an offset or length
7919 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
7920 Some larger devices will work, since they are actually multi-chip
7921 modules with two smaller chips and individual chipselect lines.
7923 @anchor{nandconfiguration}
7924 @subsection NAND Configuration Commands
7925 @cindex NAND configuration
7927 NAND chips must be declared in configuration scripts,
7928 plus some additional configuration that's done after
7929 OpenOCD has initialized.
7931 @deffn {Config Command} {nand device} name driver target [configparams...]
7932 Declares a NAND device, which can be read and written to
7933 after it has been configured through @command{nand probe}.
7934 In OpenOCD, devices are single chips; this is unlike some
7935 operating systems, which may manage multiple chips as if
7936 they were a single (larger) device.
7937 In some cases, configuring a device will activate extra
7938 commands; see the controller-specific documentation.
7940 @b{NOTE:} This command is not available after OpenOCD
7941 initialization has completed. Use it in board specific
7942 configuration files, not interactively.
7945 @item @var{name} ... may be used to reference the NAND bank
7946 in most other NAND commands. A number is also available.
7947 @item @var{driver} ... identifies the NAND controller driver
7948 associated with the NAND device being declared.
7949 @xref{nanddriverlist,,NAND Driver List}.
7950 @item @var{target} ... names the target used when issuing
7951 commands to the NAND controller.
7952 @comment Actually, it's currently a controller-specific parameter...
7953 @item @var{configparams} ... controllers may support, or require,
7954 additional parameters. See the controller-specific documentation
7955 for more information.
7959 @deffn {Command} {nand list}
7960 Prints a summary of each device declared
7961 using @command{nand device}, numbered from zero.
7962 Note that un-probed devices show no details.
7965 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
7966 blocksize: 131072, blocks: 8192
7967 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
7968 blocksize: 131072, blocks: 8192
7973 @deffn {Command} {nand probe} num
7974 Probes the specified device to determine key characteristics
7975 like its page and block sizes, and how many blocks it has.
7976 The @var{num} parameter is the value shown by @command{nand list}.
7977 You must (successfully) probe a device before you can use
7978 it with most other NAND commands.
7981 @subsection Erasing, Reading, Writing to NAND Flash
7983 @deffn {Command} {nand dump} num filename offset length [oob_option]
7984 @cindex NAND reading
7985 Reads binary data from the NAND device and writes it to the file,
7986 starting at the specified offset.
7987 The @var{num} parameter is the value shown by @command{nand list}.
7989 Use a complete path name for @var{filename}, so you don't depend
7990 on the directory used to start the OpenOCD server.
7992 The @var{offset} and @var{length} must be exact multiples of the
7993 device's page size. They describe a data region; the OOB data
7994 associated with each such page may also be accessed.
7996 @b{NOTE:} At the time this text was written, no error correction
7997 was done on the data that's read, unless raw access was disabled
7998 and the underlying NAND controller driver had a @code{read_page}
7999 method which handled that error correction.
8001 By default, only page data is saved to the specified file.
8002 Use an @var{oob_option} parameter to save OOB data:
8004 @item no oob_* parameter
8005 @*Output file holds only page data; OOB is discarded.
8006 @item @code{oob_raw}
8007 @*Output file interleaves page data and OOB data;
8008 the file will be longer than "length" by the size of the
8009 spare areas associated with each data page.
8010 Note that this kind of "raw" access is different from
8011 what's implied by @command{nand raw_access}, which just
8012 controls whether a hardware-aware access method is used.
8013 @item @code{oob_only}
8014 @*Output file has only raw OOB data, and will
8015 be smaller than "length" since it will contain only the
8016 spare areas associated with each data page.
8020 @deffn {Command} {nand erase} num [offset length]
8021 @cindex NAND erasing
8022 @cindex NAND programming
8023 Erases blocks on the specified NAND device, starting at the
8024 specified @var{offset} and continuing for @var{length} bytes.
8025 Both of those values must be exact multiples of the device's
8026 block size, and the region they specify must fit entirely in the chip.
8027 If those parameters are not specified,
8028 the whole NAND chip will be erased.
8029 The @var{num} parameter is the value shown by @command{nand list}.
8031 @b{NOTE:} This command will try to erase bad blocks, when told
8032 to do so, which will probably invalidate the manufacturer's bad
8034 For the remainder of the current server session, @command{nand info}
8035 will still report that the block ``is'' bad.
8038 @deffn {Command} {nand write} num filename offset [option...]
8039 @cindex NAND writing
8040 @cindex NAND programming
8041 Writes binary data from the file into the specified NAND device,
8042 starting at the specified offset. Those pages should already
8043 have been erased; you can't change zero bits to one bits.
8044 The @var{num} parameter is the value shown by @command{nand list}.
8046 Use a complete path name for @var{filename}, so you don't depend
8047 on the directory used to start the OpenOCD server.
8049 The @var{offset} must be an exact multiple of the device's page size.
8050 All data in the file will be written, assuming it doesn't run
8051 past the end of the device.
8052 Only full pages are written, and any extra space in the last
8053 page will be filled with 0xff bytes. (That includes OOB data,
8054 if that's being written.)
8056 @b{NOTE:} At the time this text was written, bad blocks are
8057 ignored. That is, this routine will not skip bad blocks,
8058 but will instead try to write them. This can cause problems.
8060 Provide at most one @var{option} parameter. With some
8061 NAND drivers, the meanings of these parameters may change
8062 if @command{nand raw_access} was used to disable hardware ECC.
8064 @item no oob_* parameter
8065 @*File has only page data, which is written.
8066 If raw access is in use, the OOB area will not be written.
8067 Otherwise, if the underlying NAND controller driver has
8068 a @code{write_page} routine, that routine may write the OOB
8069 with hardware-computed ECC data.
8070 @item @code{oob_only}
8071 @*File has only raw OOB data, which is written to the OOB area.
8072 Each page's data area stays untouched. @i{This can be a dangerous
8073 option}, since it can invalidate the ECC data.
8074 You may need to force raw access to use this mode.
8075 @item @code{oob_raw}
8076 @*File interleaves data and OOB data, both of which are written
8077 If raw access is enabled, the data is written first, then the
8079 Otherwise, if the underlying NAND controller driver has
8080 a @code{write_page} routine, that routine may modify the OOB
8081 before it's written, to include hardware-computed ECC data.
8082 @item @code{oob_softecc}
8083 @*File has only page data, which is written.
8084 The OOB area is filled with 0xff, except for a standard 1-bit
8085 software ECC code stored in conventional locations.
8086 You might need to force raw access to use this mode, to prevent
8087 the underlying driver from applying hardware ECC.
8088 @item @code{oob_softecc_kw}
8089 @*File has only page data, which is written.
8090 The OOB area is filled with 0xff, except for a 4-bit software ECC
8091 specific to the boot ROM in Marvell Kirkwood SoCs.
8092 You might need to force raw access to use this mode, to prevent
8093 the underlying driver from applying hardware ECC.
8097 @deffn {Command} {nand verify} num filename offset [option...]
8098 @cindex NAND verification
8099 @cindex NAND programming
8100 Verify the binary data in the file has been programmed to the
8101 specified NAND device, starting at the specified offset.
8102 The @var{num} parameter is the value shown by @command{nand list}.
8104 Use a complete path name for @var{filename}, so you don't depend
8105 on the directory used to start the OpenOCD server.
8107 The @var{offset} must be an exact multiple of the device's page size.
8108 All data in the file will be read and compared to the contents of the
8109 flash, assuming it doesn't run past the end of the device.
8110 As with @command{nand write}, only full pages are verified, so any extra
8111 space in the last page will be filled with 0xff bytes.
8113 The same @var{options} accepted by @command{nand write},
8114 and the file will be processed similarly to produce the buffers that
8115 can be compared against the contents produced from @command{nand dump}.
8117 @b{NOTE:} This will not work when the underlying NAND controller
8118 driver's @code{write_page} routine must update the OOB with a
8119 hardware-computed ECC before the data is written. This limitation may
8120 be removed in a future release.
8123 @subsection Other NAND commands
8124 @cindex NAND other commands
8126 @deffn {Command} {nand check_bad_blocks} num [offset length]
8127 Checks for manufacturer bad block markers on the specified NAND
8128 device. If no parameters are provided, checks the whole
8129 device; otherwise, starts at the specified @var{offset} and
8130 continues for @var{length} bytes.
8131 Both of those values must be exact multiples of the device's
8132 block size, and the region they specify must fit entirely in the chip.
8133 The @var{num} parameter is the value shown by @command{nand list}.
8135 @b{NOTE:} Before using this command you should force raw access
8136 with @command{nand raw_access enable} to ensure that the underlying
8137 driver will not try to apply hardware ECC.
8140 @deffn {Command} {nand info} num
8141 The @var{num} parameter is the value shown by @command{nand list}.
8142 This prints the one-line summary from "nand list", plus for
8143 devices which have been probed this also prints any known
8144 status for each block.
8147 @deffn {Command} {nand raw_access} num (@option{enable}|@option{disable})
8148 Sets or clears an flag affecting how page I/O is done.
8149 The @var{num} parameter is the value shown by @command{nand list}.
8151 This flag is cleared (disabled) by default, but changing that
8152 value won't affect all NAND devices. The key factor is whether
8153 the underlying driver provides @code{read_page} or @code{write_page}
8154 methods. If it doesn't provide those methods, the setting of
8155 this flag is irrelevant; all access is effectively ``raw''.
8157 When those methods exist, they are normally used when reading
8158 data (@command{nand dump} or reading bad block markers) or
8159 writing it (@command{nand write}). However, enabling
8160 raw access (setting the flag) prevents use of those methods,
8161 bypassing hardware ECC logic.
8162 @i{This can be a dangerous option}, since writing blocks
8163 with the wrong ECC data can cause them to be marked as bad.
8166 @anchor{nanddriverlist}
8167 @subsection NAND Driver List
8168 As noted above, the @command{nand device} command allows
8169 driver-specific options and behaviors.
8170 Some controllers also activate controller-specific commands.
8172 @deffn {NAND Driver} {at91sam9}
8173 This driver handles the NAND controllers found on AT91SAM9 family chips from
8174 Atmel. It takes two extra parameters: address of the NAND chip;
8175 address of the ECC controller.
8177 nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
8179 AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
8180 @code{read_page} methods are used to utilize the ECC hardware unless they are
8181 disabled by using the @command{nand raw_access} command. There are four
8182 additional commands that are needed to fully configure the AT91SAM9 NAND
8183 controller. Two are optional; most boards use the same wiring for ALE/CLE:
8184 @deffn {Config Command} {at91sam9 cle} num addr_line
8185 Configure the address line used for latching commands. The @var{num}
8186 parameter is the value shown by @command{nand list}.
8188 @deffn {Config Command} {at91sam9 ale} num addr_line
8189 Configure the address line used for latching addresses. The @var{num}
8190 parameter is the value shown by @command{nand list}.
8193 For the next two commands, it is assumed that the pins have already been
8194 properly configured for input or output.
8195 @deffn {Config Command} {at91sam9 rdy_busy} num pio_base_addr pin
8196 Configure the RDY/nBUSY input from the NAND device. The @var{num}
8197 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
8198 is the base address of the PIO controller and @var{pin} is the pin number.
8200 @deffn {Config Command} {at91sam9 ce} num pio_base_addr pin
8201 Configure the chip enable input to the NAND device. The @var{num}
8202 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
8203 is the base address of the PIO controller and @var{pin} is the pin number.
8207 @deffn {NAND Driver} {davinci}
8208 This driver handles the NAND controllers found on DaVinci family
8209 chips from Texas Instruments.
8210 It takes three extra parameters:
8211 address of the NAND chip;
8212 hardware ECC mode to use (@option{hwecc1},
8213 @option{hwecc4}, @option{hwecc4_infix});
8214 address of the AEMIF controller on this processor.
8216 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
8218 All DaVinci processors support the single-bit ECC hardware,
8219 and newer ones also support the four-bit ECC hardware.
8220 The @code{write_page} and @code{read_page} methods are used
8221 to implement those ECC modes, unless they are disabled using
8222 the @command{nand raw_access} command.
8225 @deffn {NAND Driver} {lpc3180}
8226 These controllers require an extra @command{nand device}
8227 parameter: the clock rate used by the controller.
8228 @deffn {Command} {lpc3180 select} num [mlc|slc]
8229 Configures use of the MLC or SLC controller mode.
8230 MLC implies use of hardware ECC.
8231 The @var{num} parameter is the value shown by @command{nand list}.
8234 At this writing, this driver includes @code{write_page}
8235 and @code{read_page} methods. Using @command{nand raw_access}
8236 to disable those methods will prevent use of hardware ECC
8237 in the MLC controller mode, but won't change SLC behavior.
8239 @comment current lpc3180 code won't issue 5-byte address cycles
8241 @deffn {NAND Driver} {mx3}
8242 This driver handles the NAND controller in i.MX31. The mxc driver
8243 should work for this chip as well.
8246 @deffn {NAND Driver} {mxc}
8247 This driver handles the NAND controller found in Freescale i.MX
8248 chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
8249 The driver takes 3 extra arguments, chip (@option{mx27},
8250 @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
8251 and optionally if bad block information should be swapped between
8252 main area and spare area (@option{biswap}), defaults to off.
8254 nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
8256 @deffn {Command} {mxc biswap} bank_num [enable|disable]
8257 Turns on/off bad block information swapping from main area,
8258 without parameter query status.
8262 @deffn {NAND Driver} {orion}
8263 These controllers require an extra @command{nand device}
8264 parameter: the address of the controller.
8266 nand device orion 0xd8000000
8268 These controllers don't define any specialized commands.
8269 At this writing, their drivers don't include @code{write_page}
8270 or @code{read_page} methods, so @command{nand raw_access} won't
8271 change any behavior.
8274 @deffn {NAND Driver} {s3c2410}
8275 @deffnx {NAND Driver} {s3c2412}
8276 @deffnx {NAND Driver} {s3c2440}
8277 @deffnx {NAND Driver} {s3c2443}
8278 @deffnx {NAND Driver} {s3c6400}
8279 These S3C family controllers don't have any special
8280 @command{nand device} options, and don't define any
8281 specialized commands.
8282 At this writing, their drivers don't include @code{write_page}
8283 or @code{read_page} methods, so @command{nand raw_access} won't
8284 change any behavior.
8287 @node Flash Programming
8288 @chapter Flash Programming
8290 OpenOCD implements numerous ways to program the target flash, whether internal or external.
8291 Programming can be achieved by either using @ref{programmingusinggdb,,Programming using GDB},
8292 or using the commands given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
8294 @*To simplify using the flash commands directly a jimtcl script is available that handles the programming and verify stage.
8295 OpenOCD will program/verify/reset the target and optionally shutdown.
8297 The script is executed as follows and by default the following actions will be performed.
8299 @item 'init' is executed.
8300 @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
8301 @item @code{flash write_image} is called to erase and write any flash using the filename given.
8302 @item If the @option{preverify} parameter is given, the target is "verified" first and only flashed if this fails.
8303 @item @code{verify_image} is called if @option{verify} parameter is given.
8304 @item @code{reset run} is called if @option{reset} parameter is given.
8305 @item OpenOCD is shutdown if @option{exit} parameter is given.
8308 An example of usage is given below. @xref{program}.
8311 # program and verify using elf/hex/s19. verify and reset
8312 # are optional parameters
8313 openocd -f board/stm32f3discovery.cfg \
8314 -c "program filename.elf verify reset exit"
8316 # binary files need the flash address passing
8317 openocd -f board/stm32f3discovery.cfg \
8318 -c "program filename.bin exit 0x08000000"
8321 @node PLD/FPGA Commands
8322 @chapter PLD/FPGA Commands
8326 Programmable Logic Devices (PLDs) and the more flexible
8327 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
8328 OpenOCD can support programming them.
8329 Although PLDs are generally restrictive (cells are less functional, and
8330 there are no special purpose cells for memory or computational tasks),
8331 they share the same OpenOCD infrastructure.
8332 Accordingly, both are called PLDs here.
8334 @section PLD/FPGA Configuration and Commands
8336 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
8337 OpenOCD maintains a list of PLDs available for use in various commands.
8338 Also, each such PLD requires a driver.
8340 They are referenced by the number shown by the @command{pld devices} command,
8341 and new PLDs are defined by @command{pld device driver_name}.
8343 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
8344 Defines a new PLD device, supported by driver @var{driver_name},
8345 using the TAP named @var{tap_name}.
8346 The driver may make use of any @var{driver_options} to configure its
8350 @deffn {Command} {pld devices}
8351 Lists the PLDs and their numbers.
8354 @deffn {Command} {pld load} num filename
8355 Loads the file @file{filename} into the PLD identified by @var{num}.
8356 The file format must be inferred by the driver.
8359 @section PLD/FPGA Drivers, Options, and Commands
8361 Drivers may support PLD-specific options to the @command{pld device}
8362 definition command, and may also define commands usable only with
8363 that particular type of PLD.
8365 @deffn {FPGA Driver} {virtex2} [no_jstart]
8366 Virtex-II is a family of FPGAs sold by Xilinx.
8367 It supports the IEEE 1532 standard for In-System Configuration (ISC).
8369 If @var{no_jstart} is non-zero, the JSTART instruction is not used after
8370 loading the bitstream. While required for Series2, Series3, and Series6, it
8371 breaks bitstream loading on Series7.
8373 @deffn {Command} {virtex2 read_stat} num
8374 Reads and displays the Virtex-II status register (STAT)
8379 @node General Commands
8380 @chapter General Commands
8383 The commands documented in this chapter here are common commands that
8384 you, as a human, may want to type and see the output of. Configuration type
8385 commands are documented elsewhere.
8389 @item @b{Source Of Commands}
8390 @* OpenOCD commands can occur in a configuration script (discussed
8391 elsewhere) or typed manually by a human or supplied programmatically,
8392 or via one of several TCP/IP Ports.
8394 @item @b{From the human}
8395 @* A human should interact with the telnet interface (default port: 4444)
8396 or via GDB (default port 3333).
8398 To issue commands from within a GDB session, use the @option{monitor}
8399 command, e.g. use @option{monitor poll} to issue the @option{poll}
8400 command. All output is relayed through the GDB session.
8402 @item @b{Machine Interface}
8403 The Tcl interface's intent is to be a machine interface. The default Tcl
8408 @section Server Commands
8410 @deffn {Command} {exit}
8411 Exits the current telnet session.
8414 @deffn {Command} {help} [string]
8415 With no parameters, prints help text for all commands.
8416 Otherwise, prints each helptext containing @var{string}.
8417 Not every command provides helptext.
8419 Configuration commands, and commands valid at any time, are
8420 explicitly noted in parenthesis.
8421 In most cases, no such restriction is listed; this indicates commands
8422 which are only available after the configuration stage has completed.
8425 @deffn {Command} {usage} [string]
8426 With no parameters, prints usage text for all commands. Otherwise,
8427 prints all usage text of which command, help text, and usage text
8428 containing @var{string}.
8429 Not every command provides helptext.
8432 @deffn {Command} {sleep} msec [@option{busy}]
8433 Wait for at least @var{msec} milliseconds before resuming.
8434 If @option{busy} is passed, busy-wait instead of sleeping.
8435 (This option is strongly discouraged.)
8436 Useful in connection with script files
8437 (@command{script} command and @command{target_name} configuration).
8440 @deffn {Command} {shutdown} [@option{error}]
8441 Close the OpenOCD server, disconnecting all clients (GDB, telnet,
8442 other). If option @option{error} is used, OpenOCD will return a
8443 non-zero exit code to the parent process.
8445 If user types CTRL-C or kills OpenOCD, the command @command{shutdown}
8446 will be automatically executed to cause OpenOCD to exit.
8448 It is possible to specify, in the TCL list @var{pre_shutdown_commands} , a
8449 set of commands to be automatically executed before @command{shutdown} , e.g.:
8451 lappend pre_shutdown_commands @{echo "Goodbye, my friend ..."@}
8452 lappend pre_shutdown_commands @{echo "see you soon !"@}
8454 The commands in the list will be executed (in the same order they occupy
8455 in the list) before OpenOCD exits. If one of the commands in the list
8456 fails, then the remaining commands are not executed anymore while OpenOCD
8457 will proceed to quit.
8461 @deffn {Command} {debug_level} [n]
8462 @cindex message level
8463 Display debug level.
8464 If @var{n} (from 0..4) is provided, then set it to that level.
8465 This affects the kind of messages sent to the server log.
8466 Level 0 is error messages only;
8467 level 1 adds warnings;
8468 level 2 adds informational messages;
8469 level 3 adds debugging messages;
8470 and level 4 adds verbose low-level debug messages.
8471 The default is level 2, but that can be overridden on
8472 the command line along with the location of that log
8473 file (which is normally the server's standard output).
8477 @deffn {Command} {echo} [-n] message
8478 Logs a message at "user" priority.
8479 Option "-n" suppresses trailing newline.
8481 echo "Downloading kernel -- please wait"
8485 @deffn {Command} {log_output} [filename | "default"]
8486 Redirect logging to @var{filename} or set it back to default output;
8487 the default log output channel is stderr.
8490 @deffn {Command} {add_script_search_dir} [directory]
8491 Add @var{directory} to the file/script search path.
8494 @deffn {Config Command} {bindto} [@var{name}]
8495 Specify hostname or IPv4 address on which to listen for incoming
8496 TCP/IP connections. By default, OpenOCD will listen on the loopback
8497 interface only. If your network environment is safe, @code{bindto
8498 0.0.0.0} can be used to cover all available interfaces.
8501 @anchor{targetstatehandling}
8502 @section Target State handling
8505 @cindex target initialization
8507 In this section ``target'' refers to a CPU configured as
8508 shown earlier (@pxref{CPU Configuration}).
8509 These commands, like many, implicitly refer to
8510 a current target which is used to perform the
8511 various operations. The current target may be changed
8512 by using @command{targets} command with the name of the
8513 target which should become current.
8515 @deffn {Command} {reg} [(number|name) [(value|'force')]]
8516 Access a single register by @var{number} or by its @var{name}.
8517 The target must generally be halted before access to CPU core
8518 registers is allowed. Depending on the hardware, some other
8519 registers may be accessible while the target is running.
8521 @emph{With no arguments}:
8522 list all available registers for the current target,
8523 showing number, name, size, value, and cache status.
8524 For valid entries, a value is shown; valid entries
8525 which are also dirty (and will be written back later)
8526 are flagged as such.
8528 @emph{With number/name}: display that register's value.
8529 Use @var{force} argument to read directly from the target,
8530 bypassing any internal cache.
8532 @emph{With both number/name and value}: set register's value.
8533 Writes may be held in a writeback cache internal to OpenOCD,
8534 so that setting the value marks the register as dirty instead
8535 of immediately flushing that value. Resuming CPU execution
8536 (including by single stepping) or otherwise activating the
8537 relevant module will flush such values.
8539 Cores may have surprisingly many registers in their
8540 Debug and trace infrastructure:
8545 (0) r0 (/32): 0x0000D3C2 (dirty)
8546 (1) r1 (/32): 0xFD61F31C
8549 (164) ETM_contextid_comparator_mask (/32)
8554 @deffn {Command} {set_reg} dict
8555 Set register values of the target.
8558 @item @var{dict} ... Tcl dictionary with pairs of register names and values.
8561 For example, the following command sets the value 0 to the program counter (pc)
8562 register and 0x1000 to the stack pointer (sp) register:
8565 set_reg @{pc 0 sp 0x1000@}
8569 @deffn {Command} {get_reg} [-force] list
8570 Get register values from the target and return them as Tcl dictionary with pairs
8571 of register names and values.
8572 If option "-force" is set, the register values are read directly from the
8573 target, bypassing any caching.
8576 @item @var{list} ... List of register names
8579 For example, the following command retrieves the values from the program
8580 counter (pc) and stack pointer (sp) register:
8587 @deffn {Command} {write_memory} address width data ['phys']
8588 This function provides an efficient way to write to the target memory from a Tcl
8592 @item @var{address} ... target memory address
8593 @item @var{width} ... memory access bit size, can be 8, 16, 32 or 64
8594 @item @var{data} ... Tcl list with the elements to write
8595 @item ['phys'] ... treat the memory address as physical instead of virtual address
8598 For example, the following command writes two 32 bit words into the target
8599 memory at address 0x20000000:
8602 write_memory 0x20000000 32 @{0xdeadbeef 0x00230500@}
8606 @deffn {Command} {read_memory} address width count ['phys']
8607 This function provides an efficient way to read the target memory from a Tcl
8609 A Tcl list containing the requested memory elements is returned by this function.
8612 @item @var{address} ... target memory address
8613 @item @var{width} ... memory access bit size, can be 8, 16, 32 or 64
8614 @item @var{count} ... number of elements to read
8615 @item ['phys'] ... treat the memory address as physical instead of virtual address
8618 For example, the following command reads two 32 bit words from the target
8619 memory at address 0x20000000:
8622 read_memory 0x20000000 32 2
8626 @deffn {Command} {halt} [ms]
8627 @deffnx {Command} {wait_halt} [ms]
8628 The @command{halt} command first sends a halt request to the target,
8629 which @command{wait_halt} doesn't.
8630 Otherwise these behave the same: wait up to @var{ms} milliseconds,
8631 or 5 seconds if there is no parameter, for the target to halt
8632 (and enter debug mode).
8633 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
8636 On ARM cores, software using the @emph{wait for interrupt} operation
8637 often blocks the JTAG access needed by a @command{halt} command.
8638 This is because that operation also puts the core into a low
8639 power mode by gating the core clock;
8640 but the core clock is needed to detect JTAG clock transitions.
8642 One partial workaround uses adaptive clocking: when the core is
8643 interrupted the operation completes, then JTAG clocks are accepted
8644 at least until the interrupt handler completes.
8645 However, this workaround is often unusable since the processor, board,
8646 and JTAG adapter must all support adaptive JTAG clocking.
8647 Also, it can't work until an interrupt is issued.
8649 A more complete workaround is to not use that operation while you
8650 work with a JTAG debugger.
8651 Tasking environments generally have idle loops where the body is the
8652 @emph{wait for interrupt} operation.
8653 (On older cores, it is a coprocessor action;
8654 newer cores have a @option{wfi} instruction.)
8655 Such loops can just remove that operation, at the cost of higher
8656 power consumption (because the CPU is needlessly clocked).
8661 @deffn {Command} {resume} [address]
8662 Resume the target at its current code position,
8663 or the optional @var{address} if it is provided.
8664 OpenOCD will wait 5 seconds for the target to resume.
8667 @deffn {Command} {step} [address]
8668 Single-step the target at its current code position,
8669 or the optional @var{address} if it is provided.
8672 @anchor{resetcommand}
8673 @deffn {Command} {reset}
8674 @deffnx {Command} {reset run}
8675 @deffnx {Command} {reset halt}
8676 @deffnx {Command} {reset init}
8677 Perform as hard a reset as possible, using SRST if possible.
8678 @emph{All defined targets will be reset, and target
8679 events will fire during the reset sequence.}
8681 The optional parameter specifies what should
8682 happen after the reset.
8683 If there is no parameter, a @command{reset run} is executed.
8684 The other options will not work on all systems.
8685 @xref{Reset Configuration}.
8688 @item @b{run} Let the target run
8689 @item @b{halt} Immediately halt the target
8690 @item @b{init} Immediately halt the target, and execute the reset-init script
8694 @deffn {Command} {soft_reset_halt}
8695 Requesting target halt and executing a soft reset. This is often used
8696 when a target cannot be reset and halted. The target, after reset is
8697 released begins to execute code. OpenOCD attempts to stop the CPU and
8698 then sets the program counter back to the reset vector. Unfortunately
8699 the code that was executed may have left the hardware in an unknown
8703 @deffn {Command} {adapter assert} [signal [assert|deassert signal]]
8704 @deffnx {Command} {adapter deassert} [signal [assert|deassert signal]]
8705 Set values of reset signals.
8706 Without parameters returns current status of the signals.
8707 The @var{signal} parameter values may be
8708 @option{srst}, indicating that srst signal is to be asserted or deasserted,
8709 @option{trst}, indicating that trst signal is to be asserted or deasserted.
8711 The @command{reset_config} command should already have been used
8712 to configure how the board and the adapter treat these two
8713 signals, and to say if either signal is even present.
8714 @xref{Reset Configuration}.
8715 Trying to assert a signal that is not present triggers an error.
8716 If a signal is present on the adapter and not specified in the command,
8717 the signal will not be modified.
8720 TRST is specially handled.
8721 It actually signifies JTAG's @sc{reset} state.
8722 So if the board doesn't support the optional TRST signal,
8723 or it doesn't support it along with the specified SRST value,
8724 JTAG reset is triggered with TMS and TCK signals
8725 instead of the TRST signal.
8726 And no matter how that JTAG reset is triggered, once
8727 the scan chain enters @sc{reset} with TRST inactive,
8728 TAP @code{post-reset} events are delivered to all TAPs
8729 with handlers for that event.
8733 @anchor{memoryaccess}
8734 @section Memory access commands
8735 @cindex memory access
8737 These commands allow accesses of a specific size to the memory
8738 system. Often these are used to configure the current target in some
8739 special way. For example - one may need to write certain values to the
8740 SDRAM controller to enable SDRAM.
8743 @item Use the @command{targets} (plural) command
8744 to change the current target.
8745 @item In system level scripts these commands are deprecated.
8746 Please use their TARGET object siblings to avoid making assumptions
8747 about what TAP is the current target, or about MMU configuration.
8750 @deffn {Command} {mdd} [phys] addr [count]
8751 @deffnx {Command} {mdw} [phys] addr [count]
8752 @deffnx {Command} {mdh} [phys] addr [count]
8753 @deffnx {Command} {mdb} [phys] addr [count]
8754 Display contents of address @var{addr}, as
8755 64-bit doublewords (@command{mdd}),
8756 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
8757 or 8-bit bytes (@command{mdb}).
8758 When the current target has an MMU which is present and active,
8759 @var{addr} is interpreted as a virtual address.
8760 Otherwise, or if the optional @var{phys} flag is specified,
8761 @var{addr} is interpreted as a physical address.
8762 If @var{count} is specified, displays that many units.
8763 (If you want to process the data instead of displaying it,
8764 see the @code{read_memory} primitives.)
8767 @deffn {Command} {mwd} [phys] addr doubleword [count]
8768 @deffnx {Command} {mww} [phys] addr word [count]
8769 @deffnx {Command} {mwh} [phys] addr halfword [count]
8770 @deffnx {Command} {mwb} [phys] addr byte [count]
8771 Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
8772 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
8773 at the specified address @var{addr}.
8774 When the current target has an MMU which is present and active,
8775 @var{addr} is interpreted as a virtual address.
8776 Otherwise, or if the optional @var{phys} flag is specified,
8777 @var{addr} is interpreted as a physical address.
8778 If @var{count} is specified, fills that many units of consecutive address.
8781 @anchor{imageaccess}
8782 @section Image loading commands
8783 @cindex image loading
8784 @cindex image dumping
8786 @deffn {Command} {dump_image} filename address size
8787 Dump @var{size} bytes of target memory starting at @var{address} to the
8788 binary file named @var{filename}.
8791 @deffn {Command} {fast_load}
8792 Loads an image stored in memory by @command{fast_load_image} to the
8793 current target. Must be preceded by fast_load_image.
8796 @deffn {Command} {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
8797 Normally you should be using @command{load_image} or GDB load. However, for
8798 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
8799 host), storing the image in memory and uploading the image to the target
8800 can be a way to upload e.g. multiple debug sessions when the binary does not change.
8801 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
8802 memory, i.e. does not affect target. This approach is also useful when profiling
8803 target programming performance as I/O and target programming can easily be profiled
8807 @deffn {Command} {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
8808 Load image from file @var{filename} to target memory offset by @var{address} from its load address.
8809 The file format may optionally be specified
8810 (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
8811 In addition the following arguments may be specified:
8812 @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
8813 @var{max_length} - maximum number of bytes to load.
8815 proc load_image_bin @{fname foffset address length @} @{
8816 # Load data from fname filename at foffset offset to
8817 # target at address. Load at most length bytes.
8818 load_image $fname [expr @{$address - $foffset@}] bin \
8824 @deffn {Command} {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
8825 Displays image section sizes and addresses
8826 as if @var{filename} were loaded into target memory
8827 starting at @var{address} (defaults to zero).
8828 The file format may optionally be specified
8829 (@option{bin}, @option{ihex}, or @option{elf})
8832 @deffn {Command} {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
8833 Verify @var{filename} against target memory starting at @var{address}.
8834 The file format may optionally be specified
8835 (@option{bin}, @option{ihex}, or @option{elf})
8836 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
8839 @deffn {Command} {verify_image_checksum} filename address [@option{bin}|@option{ihex}|@option{elf}]
8840 Verify @var{filename} against target memory starting at @var{address}.
8841 The file format may optionally be specified
8842 (@option{bin}, @option{ihex}, or @option{elf})
8843 This perform a comparison using a CRC checksum only
8847 @section Breakpoint and Watchpoint commands
8851 CPUs often make debug modules accessible through JTAG, with
8852 hardware support for a handful of code breakpoints and data
8854 In addition, CPUs almost always support software breakpoints.
8856 @deffn {Command} {bp} [address len [@option{hw}]]
8857 With no parameters, lists all active breakpoints.
8858 Else sets a breakpoint on code execution starting
8859 at @var{address} for @var{length} bytes.
8860 This is a software breakpoint, unless @option{hw} is specified
8861 in which case it will be a hardware breakpoint.
8863 (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
8864 for similar mechanisms that do not consume hardware breakpoints.)
8867 @deffn {Command} {rbp} @option{all} | address
8868 Remove the breakpoint at @var{address} or all breakpoints.
8871 @deffn {Command} {rwp} address
8872 Remove data watchpoint on @var{address}
8875 @deffn {Command} {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
8876 With no parameters, lists all active watchpoints.
8877 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
8878 The watch point is an "access" watchpoint unless
8879 the @option{r} or @option{w} parameter is provided,
8880 defining it as respectively a read or write watchpoint.
8881 If a @var{value} is provided, that value is used when determining if
8882 the watchpoint should trigger. The value may be first be masked
8883 using @var{mask} to mark ``don't care'' fields.
8887 @section Real Time Transfer (RTT)
8889 Real Time Transfer (RTT) is an interface specified by SEGGER based on basic
8890 memory reads and writes to transfer data bidirectionally between target and host.
8891 The specification is independent of the target architecture.
8892 Every target that supports so called "background memory access", which means
8893 that the target memory can be accessed by the debugger while the target is
8894 running, can be used.
8895 This interface is especially of interest for targets without
8896 Serial Wire Output (SWO), such as ARM Cortex-M0, or where semihosting is not
8897 applicable because of real-time constraints.
8900 The current implementation supports only single target devices.
8903 The data transfer between host and target device is organized through
8904 unidirectional up/down-channels for target-to-host and host-to-target
8905 communication, respectively.
8908 The current implementation does not respect channel buffer flags.
8909 They are used to determine what happens when writing to a full buffer, for
8913 Channels are exposed via raw TCP/IP connections. One or more RTT servers can be
8914 assigned to each channel to make them accessible to an unlimited number
8915 of TCP/IP connections.
8917 @deffn {Command} {rtt setup} address size ID
8918 Configure RTT for the currently selected target.
8919 Once RTT is started, OpenOCD searches for a control block with the
8920 identifier @var{ID} starting at the memory address @var{address} within the next
8924 @deffn {Command} {rtt start}
8926 If the control block location is not known, OpenOCD starts searching for it.
8929 @deffn {Command} {rtt stop}
8933 @deffn {Command} {rtt polling_interval} [interval]
8934 Display the polling interval.
8935 If @var{interval} is provided, set the polling interval.
8936 The polling interval determines (in milliseconds) how often the up-channels are
8937 checked for new data.
8940 @deffn {Command} {rtt channels}
8941 Display a list of all channels and their properties.
8944 @deffn {Command} {rtt channellist}
8945 Return a list of all channels and their properties as Tcl list.
8946 The list can be manipulated easily from within scripts.
8949 @deffn {Command} {rtt server start} port channel
8950 Start a TCP server on @var{port} for the channel @var{channel}.
8953 @deffn {Command} {rtt server stop} port
8954 Stop the TCP sever with port @var{port}.
8957 The following example shows how to setup RTT using the SEGGER RTT implementation
8958 on the target device.
8963 rtt setup 0x20000000 2048 "SEGGER RTT"
8966 rtt server start 9090 0
8969 In this example, OpenOCD searches the control block with the ID "SEGGER RTT"
8970 starting at 0x20000000 for 2048 bytes. The RTT channel 0 is exposed through the
8974 @section Misc Commands
8977 @deffn {Command} {profile} seconds filename [start end]
8978 Profiling samples the CPU's program counter as quickly as possible,
8979 which is useful for non-intrusive stochastic profiling.
8980 Saves up to 10000 samples in @file{filename} using ``gmon.out''
8981 format. Optional @option{start} and @option{end} parameters allow to
8982 limit the address range.
8985 @deffn {Command} {version}
8986 Displays a string identifying the version of this OpenOCD server.
8989 @deffn {Command} {virt2phys} virtual_address
8990 Requests the current target to map the specified @var{virtual_address}
8991 to its corresponding physical address, and displays the result.
8994 @deffn {Command} {add_help_text} 'command_name' 'help-string'
8995 Add or replace help text on the given @var{command_name}.
8998 @deffn {Command} {add_usage_text} 'command_name' 'help-string'
8999 Add or replace usage text on the given @var{command_name}.
9002 @node Architecture and Core Commands
9003 @chapter Architecture and Core Commands
9004 @cindex Architecture Specific Commands
9005 @cindex Core Specific Commands
9007 Most CPUs have specialized JTAG operations to support debugging.
9008 OpenOCD packages most such operations in its standard command framework.
9009 Some of those operations don't fit well in that framework, so they are
9010 exposed here as architecture or implementation (core) specific commands.
9012 @anchor{armhardwaretracing}
9013 @section ARM Hardware Tracing
9018 CPUs based on ARM cores may include standard tracing interfaces,
9019 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
9020 address and data bus trace records to a ``Trace Port''.
9024 Development-oriented boards will sometimes provide a high speed
9025 trace connector for collecting that data, when the particular CPU
9026 supports such an interface.
9027 (The standard connector is a 38-pin Mictor, with both JTAG
9028 and trace port support.)
9029 Those trace connectors are supported by higher end JTAG adapters
9030 and some logic analyzer modules; frequently those modules can
9031 buffer several megabytes of trace data.
9032 Configuring an ETM coupled to such an external trace port belongs
9033 in the board-specific configuration file.
9035 If the CPU doesn't provide an external interface, it probably
9036 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
9037 dedicated SRAM. 4KBytes is one common ETB size.
9038 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
9039 (target) configuration file, since it works the same on all boards.
9042 ETM support in OpenOCD doesn't seem to be widely used yet.
9045 ETM support may be buggy, and at least some @command{etm config}
9046 parameters should be detected by asking the ETM for them.
9048 ETM trigger events could also implement a kind of complex
9049 hardware breakpoint, much more powerful than the simple
9050 watchpoint hardware exported by EmbeddedICE modules.
9051 @emph{Such breakpoints can be triggered even when using the
9052 dummy trace port driver}.
9054 It seems like a GDB hookup should be possible,
9055 as well as tracing only during specific states
9056 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
9058 There should be GUI tools to manipulate saved trace data and help
9059 analyse it in conjunction with the source code.
9060 It's unclear how much of a common interface is shared
9061 with the current XScale trace support, or should be
9062 shared with eventual Nexus-style trace module support.
9064 At this writing (November 2009) only ARM7, ARM9, and ARM11 support
9065 for ETM modules is available. The code should be able to
9066 work with some newer cores; but not all of them support
9067 this original style of JTAG access.
9070 @subsection ETM Configuration
9071 ETM setup is coupled with the trace port driver configuration.
9073 @deffn {Config Command} {etm config} target width mode clocking driver
9074 Declares the ETM associated with @var{target}, and associates it
9075 with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
9077 Several of the parameters must reflect the trace port capabilities,
9078 which are a function of silicon capabilities (exposed later
9079 using @command{etm info}) and of what hardware is connected to
9080 that port (such as an external pod, or ETB).
9081 The @var{width} must be either 4, 8, or 16,
9082 except with ETMv3.0 and newer modules which may also
9083 support 1, 2, 24, 32, 48, and 64 bit widths.
9084 (With those versions, @command{etm info} also shows whether
9085 the selected port width and mode are supported.)
9087 The @var{mode} must be @option{normal}, @option{multiplexed},
9088 or @option{demultiplexed}.
9089 The @var{clocking} must be @option{half} or @option{full}.
9092 With ETMv3.0 and newer, the bits set with the @var{mode} and
9093 @var{clocking} parameters both control the mode.
9094 This modified mode does not map to the values supported by
9095 previous ETM modules, so this syntax is subject to change.
9099 You can see the ETM registers using the @command{reg} command.
9100 Not all possible registers are present in every ETM.
9101 Most of the registers are write-only, and are used to configure
9102 what CPU activities are traced.
9106 @deffn {Command} {etm info}
9107 Displays information about the current target's ETM.
9108 This includes resource counts from the @code{ETM_CONFIG} register,
9109 as well as silicon capabilities (except on rather old modules).
9110 from the @code{ETM_SYS_CONFIG} register.
9113 @deffn {Command} {etm status}
9114 Displays status of the current target's ETM and trace port driver:
9115 is the ETM idle, or is it collecting data?
9116 Did trace data overflow?
9120 @deffn {Command} {etm tracemode} [type context_id_bits cycle_accurate branch_output]
9121 Displays what data that ETM will collect.
9122 If arguments are provided, first configures that data.
9123 When the configuration changes, tracing is stopped
9124 and any buffered trace data is invalidated.
9127 @item @var{type} ... describing how data accesses are traced,
9128 when they pass any ViewData filtering that was set up.
9130 @option{none} (save nothing),
9131 @option{data} (save data),
9132 @option{address} (save addresses),
9133 @option{all} (save data and addresses)
9134 @item @var{context_id_bits} ... 0, 8, 16, or 32
9135 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
9136 cycle-accurate instruction tracing.
9137 Before ETMv3, enabling this causes much extra data to be recorded.
9138 @item @var{branch_output} ... @option{enable} or @option{disable}.
9139 Disable this unless you need to try reconstructing the instruction
9140 trace stream without an image of the code.
9144 @deffn {Command} {etm trigger_debug} (@option{enable}|@option{disable})
9145 Displays whether ETM triggering debug entry (like a breakpoint) is
9146 enabled or disabled, after optionally modifying that configuration.
9147 The default behaviour is @option{disable}.
9148 Any change takes effect after the next @command{etm start}.
9150 By using script commands to configure ETM registers, you can make the
9151 processor enter debug state automatically when certain conditions,
9152 more complex than supported by the breakpoint hardware, happen.
9155 @subsection ETM Trace Operation
9157 After setting up the ETM, you can use it to collect data.
9158 That data can be exported to files for later analysis.
9159 It can also be parsed with OpenOCD, for basic sanity checking.
9161 To configure what is being traced, you will need to write
9162 various trace registers using @command{reg ETM_*} commands.
9163 For the definitions of these registers, read ARM publication
9164 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
9165 Be aware that most of the relevant registers are write-only,
9166 and that ETM resources are limited. There are only a handful
9167 of address comparators, data comparators, counters, and so on.
9169 Examples of scenarios you might arrange to trace include:
9172 @item Code flow within a function, @emph{excluding} subroutines
9173 it calls. Use address range comparators to enable tracing
9174 for instruction access within that function's body.
9175 @item Code flow within a function, @emph{including} subroutines
9176 it calls. Use the sequencer and address comparators to activate
9177 tracing on an ``entered function'' state, then deactivate it by
9178 exiting that state when the function's exit code is invoked.
9179 @item Code flow starting at the fifth invocation of a function,
9180 combining one of the above models with a counter.
9181 @item CPU data accesses to the registers for a particular device,
9182 using address range comparators and the ViewData logic.
9183 @item Such data accesses only during IRQ handling, combining the above
9184 model with sequencer triggers which on entry and exit to the IRQ handler.
9185 @item @emph{... more}
9188 At this writing, September 2009, there are no Tcl utility
9189 procedures to help set up any common tracing scenarios.
9191 @deffn {Command} {etm analyze}
9192 Reads trace data into memory, if it wasn't already present.
9193 Decodes and prints the data that was collected.
9196 @deffn {Command} {etm dump} filename
9197 Stores the captured trace data in @file{filename}.
9200 @deffn {Command} {etm image} filename [base_address] [type]
9201 Opens an image file.
9204 @deffn {Command} {etm load} filename
9205 Loads captured trace data from @file{filename}.
9208 @deffn {Command} {etm start}
9209 Starts trace data collection.
9212 @deffn {Command} {etm stop}
9213 Stops trace data collection.
9216 @anchor{traceportdrivers}
9217 @subsection Trace Port Drivers
9219 To use an ETM trace port it must be associated with a driver.
9221 @deffn {Trace Port Driver} {dummy}
9222 Use the @option{dummy} driver if you are configuring an ETM that's
9223 not connected to anything (on-chip ETB or off-chip trace connector).
9224 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
9225 any trace data collection.}
9226 @deffn {Config Command} {etm_dummy config} target
9227 Associates the ETM for @var{target} with a dummy driver.
9231 @deffn {Trace Port Driver} {etb}
9232 Use the @option{etb} driver if you are configuring an ETM
9233 to use on-chip ETB memory.
9234 @deffn {Config Command} {etb config} target etb_tap
9235 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
9236 You can see the ETB registers using the @command{reg} command.
9238 @deffn {Command} {etb trigger_percent} [percent]
9239 This displays, or optionally changes, ETB behavior after the
9240 ETM's configured @emph{trigger} event fires.
9241 It controls how much more trace data is saved after the (single)
9242 trace trigger becomes active.
9245 @item The default corresponds to @emph{trace around} usage,
9246 recording 50 percent data before the event and the rest
9248 @item The minimum value of @var{percent} is 2 percent,
9249 recording almost exclusively data before the trigger.
9250 Such extreme @emph{trace before} usage can help figure out
9251 what caused that event to happen.
9252 @item The maximum value of @var{percent} is 100 percent,
9253 recording data almost exclusively after the event.
9254 This extreme @emph{trace after} usage might help sort out
9255 how the event caused trouble.
9257 @c REVISIT allow "break" too -- enter debug mode.
9262 @anchor{armcrosstrigger}
9263 @section ARM Cross-Trigger Interface
9266 The ARM Cross-Trigger Interface (CTI) is a generic CoreSight component
9267 that connects event sources like tracing components or CPU cores with each
9268 other through a common trigger matrix (CTM). For ARMv8 architecture, a
9269 CTI is mandatory for core run control and each core has an individual
9270 CTI instance attached to it. OpenOCD has limited support for CTI using
9271 the @emph{cti} group of commands.
9273 @deffn {Command} {cti create} cti_name @option{-dap} dap_name @option{-ap-num} apn @option{-baseaddr} base_address
9274 Creates a CTI instance @var{cti_name} on the DAP instance @var{dap_name} on MEM-AP
9275 @var{apn}. The @var{base_address} must match the base address of the CTI
9276 on the respective MEM-AP. All arguments are mandatory. This creates a
9277 new command @command{$cti_name} which is used for various purposes
9278 including additional configuration.
9281 @deffn {Command} {$cti_name enable} @option{on|off}
9282 Enable (@option{on}) or disable (@option{off}) the CTI.
9285 @deffn {Command} {$cti_name dump}
9286 Displays a register dump of the CTI.
9289 @deffn {Command} {$cti_name write} @var{reg_name} @var{value}
9290 Write @var{value} to the CTI register with the symbolic name @var{reg_name}.
9293 @deffn {Command} {$cti_name read} @var{reg_name}
9294 Print the value read from the CTI register with the symbolic name @var{reg_name}.
9297 @deffn {Command} {$cti_name ack} @var{event}
9298 Acknowledge a CTI @var{event}.
9301 @deffn {Command} {$cti_name channel} @var{channel_number} @var{operation}
9302 Perform a specific channel operation, the possible operations are:
9303 gate, ungate, set, clear and pulse
9306 @deffn {Command} {$cti_name testmode} @option{on|off}
9307 Enable (@option{on}) or disable (@option{off}) the integration test mode
9311 @deffn {Command} {cti names}
9312 Prints a list of names of all CTI objects created. This command is mainly
9313 useful in TCL scripting.
9316 @section Generic ARM
9319 These commands should be available on all ARM processors.
9320 They are available in addition to other core-specific
9321 commands that may be available.
9323 @deffn {Command} {arm core_state} [@option{arm}|@option{thumb}]
9324 Displays the core_state, optionally changing it to process
9325 either @option{arm} or @option{thumb} instructions.
9326 The target may later be resumed in the currently set core_state.
9327 (Processors may also support the Jazelle state, but
9328 that is not currently supported in OpenOCD.)
9331 @deffn {Command} {arm disassemble} address [count [@option{thumb}]]
9333 Disassembles @var{count} instructions starting at @var{address}.
9334 If @var{count} is not specified, a single instruction is disassembled.
9335 If @option{thumb} is specified, or the low bit of the address is set,
9336 Thumb2 (mixed 16/32-bit) instructions are used;
9337 else ARM (32-bit) instructions are used.
9338 (Processors may also support the Jazelle state, but
9339 those instructions are not currently understood by OpenOCD.)
9341 Note that all Thumb instructions are Thumb2 instructions,
9342 so older processors (without Thumb2 support) will still
9343 see correct disassembly of Thumb code.
9344 Also, ThumbEE opcodes are the same as Thumb2,
9345 with a handful of exceptions.
9346 ThumbEE disassembly currently has no explicit support.
9349 @deffn {Command} {arm mcr} pX op1 CRn CRm op2 value
9350 Write @var{value} to a coprocessor @var{pX} register
9351 passing parameters @var{CRn},
9352 @var{CRm}, opcodes @var{opc1} and @var{opc2},
9353 and using the MCR instruction.
9354 (Parameter sequence matches the ARM instruction, but omits
9358 @deffn {Command} {arm mrc} pX coproc op1 CRn CRm op2
9359 Read a coprocessor @var{pX} register passing parameters @var{CRn},
9360 @var{CRm}, opcodes @var{opc1} and @var{opc2},
9361 and the MRC instruction.
9362 Returns the result so it can be manipulated by Jim scripts.
9363 (Parameter sequence matches the ARM instruction, but omits
9367 @deffn {Command} {arm reg}
9368 Display a table of all banked core registers, fetching the current value from every
9369 core mode if necessary.
9372 @deffn {Command} {arm semihosting} [@option{enable}|@option{disable}]
9373 @cindex ARM semihosting
9374 Display status of semihosting, after optionally changing that status.
9376 Semihosting allows for code executing on an ARM target to use the
9377 I/O facilities on the host computer i.e. the system where OpenOCD
9378 is running. The target application must be linked against a library
9379 implementing the ARM semihosting convention that forwards operation
9380 requests by using a special SVC instruction that is trapped at the
9381 Supervisor Call vector by OpenOCD.
9384 @deffn {Command} {arm semihosting_redirect} (@option{disable} | @option{tcp} <port>
9385 [@option{debug}|@option{stdio}|@option{all})
9386 @cindex ARM semihosting
9387 Redirect semihosting messages to a specified TCP port.
9389 This command redirects debug (READC, WRITEC and WRITE0) and stdio (READ, WRITE)
9390 semihosting operations to the specified TCP port.
9391 The command allows to select which type of operations to redirect (debug, stdio, all (default)).
9392 Note: for stdio operations, only I/O from/to ':tt' file descriptors are redirected.
9395 @deffn {Command} {arm semihosting_cmdline} [@option{enable}|@option{disable}]
9396 @cindex ARM semihosting
9397 Set the command line to be passed to the debugger.
9400 arm semihosting_cmdline argv0 argv1 argv2 ...
9403 This option lets one set the command line arguments to be passed to
9404 the program. The first argument (argv0) is the program name in a
9405 standard C environment (argv[0]). Depending on the program (not much
9406 programs look at argv[0]), argv0 is ignored and can be any string.
9409 @deffn {Command} {arm semihosting_fileio} [@option{enable}|@option{disable}]
9410 @cindex ARM semihosting
9411 Display status of semihosting fileio, after optionally changing that
9414 Enabling this option forwards semihosting I/O to GDB process using the
9415 File-I/O remote protocol extension. This is especially useful for
9416 interacting with remote files or displaying console messages in the
9420 @deffn {Command} {arm semihosting_resexit} [@option{enable}|@option{disable}]
9421 @cindex ARM semihosting
9422 Enable resumable SEMIHOSTING_SYS_EXIT.
9424 When SEMIHOSTING_SYS_EXIT is called outside a debug session,
9425 things are simple, the openocd process calls exit() and passes
9426 the value returned by the target.
9428 When SEMIHOSTING_SYS_EXIT is called during a debug session,
9429 by default execution returns to the debugger, leaving the
9430 debugger in a HALT state, similar to the state entered when
9431 encountering a break.
9433 In some use cases, it is useful to have SEMIHOSTING_SYS_EXIT
9434 return normally, as any semihosting call, and do not break
9436 The standard allows this to happen, but the condition
9437 to trigger it is a bit obscure ("by performing an RDI_Execute
9438 request or equivalent").
9440 To make the SEMIHOSTING_SYS_EXIT call return normally, enable
9441 this option (default: disabled).
9444 @deffn {Command} {arm semihosting_read_user_param}
9445 @cindex ARM semihosting
9446 Read parameter of the semihosting call from the target. Usable in
9447 semihosting-user-cmd-0x10* event handlers, returning a string.
9449 When the target makes semihosting call with operation number from range 0x100-
9450 0x107, an optional string parameter can be passed to the server. This parameter
9451 is valid during the run of the event handlers and is accessible with this
9455 @section ARMv4 and ARMv5 Architecture
9459 The ARMv4 and ARMv5 architectures are widely used in embedded systems,
9460 and introduced core parts of the instruction set in use today.
9461 That includes the Thumb instruction set, introduced in the ARMv4T
9464 @subsection ARM7 and ARM9 specific commands
9468 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
9469 ARM9TDMI, ARM920T or ARM926EJ-S.
9470 They are available in addition to the ARM commands,
9471 and any other core-specific commands that may be available.
9473 @deffn {Command} {arm7_9 dbgrq} [@option{enable}|@option{disable}]
9474 Displays the value of the flag controlling use of the
9475 EmbeddedIce DBGRQ signal to force entry into debug mode,
9476 instead of breakpoints.
9477 If a boolean parameter is provided, first assigns that flag.
9480 safe for all but ARM7TDMI-S cores (like NXP LPC).
9481 This feature is enabled by default on most ARM9 cores,
9482 including ARM9TDMI, ARM920T, and ARM926EJ-S.
9485 @deffn {Command} {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
9487 Displays the value of the flag controlling use of the debug communications
9488 channel (DCC) to write larger (>128 byte) amounts of memory.
9489 If a boolean parameter is provided, first assigns that flag.
9491 DCC downloads offer a huge speed increase, but might be
9492 unsafe, especially with targets running at very low speeds. This command was introduced
9493 with OpenOCD rev. 60, and requires a few bytes of working area.
9496 @deffn {Command} {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
9497 Displays the value of the flag controlling use of memory writes and reads
9498 that don't check completion of the operation.
9499 If a boolean parameter is provided, first assigns that flag.
9501 This provides a huge speed increase, especially with USB JTAG
9502 cables (FT2232), but might be unsafe if used with targets running at very low
9503 speeds, like the 32kHz startup clock of an AT91RM9200.
9506 @subsection ARM9 specific commands
9509 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
9511 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
9513 @c 9-june-2009: tried this on arm920t, it didn't work.
9514 @c no-params always lists nothing caught, and that's how it acts.
9515 @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
9516 @c versions have different rules about when they commit writes.
9518 @anchor{arm9vectorcatch}
9519 @deffn {Command} {arm9 vector_catch} [@option{all}|@option{none}|list]
9520 @cindex vector_catch
9521 Vector Catch hardware provides a sort of dedicated breakpoint
9522 for hardware events such as reset, interrupt, and abort.
9523 You can use this to conserve normal breakpoint resources,
9524 so long as you're not concerned with code that branches directly
9525 to those hardware vectors.
9527 This always finishes by listing the current configuration.
9528 If parameters are provided, it first reconfigures the
9529 vector catch hardware to intercept
9530 @option{all} of the hardware vectors,
9531 @option{none} of them,
9532 or a list with one or more of the following:
9533 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
9534 @option{irq} @option{fiq}.
9537 @subsection ARM920T specific commands
9540 These commands are available to ARM920T based CPUs,
9541 which are implementations of the ARMv4T architecture
9542 built using the ARM9TDMI integer core.
9543 They are available in addition to the ARM, ARM7/ARM9,
9546 @deffn {Command} {arm920t cache_info}
9547 Print information about the caches found. This allows to see whether your target
9548 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
9551 @deffn {Command} {arm920t cp15} regnum [value]
9552 Display cp15 register @var{regnum};
9553 else if a @var{value} is provided, that value is written to that register.
9554 This uses "physical access" and the register number is as
9555 shown in bits 38..33 of table 9-9 in the ARM920T TRM.
9556 (Not all registers can be written.)
9559 @deffn {Command} {arm920t read_cache} filename
9560 Dump the content of ICache and DCache to a file named @file{filename}.
9563 @deffn {Command} {arm920t read_mmu} filename
9564 Dump the content of the ITLB and DTLB to a file named @file{filename}.
9567 @subsection ARM926ej-s specific commands
9570 These commands are available to ARM926ej-s based CPUs,
9571 which are implementations of the ARMv5TEJ architecture
9572 based on the ARM9EJ-S integer core.
9573 They are available in addition to the ARM, ARM7/ARM9,
9576 The Feroceon cores also support these commands, although
9577 they are not built from ARM926ej-s designs.
9579 @deffn {Command} {arm926ejs cache_info}
9580 Print information about the caches found.
9583 @subsection ARM966E specific commands
9586 These commands are available to ARM966 based CPUs,
9587 which are implementations of the ARMv5TE architecture.
9588 They are available in addition to the ARM, ARM7/ARM9,
9591 @deffn {Command} {arm966e cp15} regnum [value]
9592 Display cp15 register @var{regnum};
9593 else if a @var{value} is provided, that value is written to that register.
9594 The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
9596 There is no current control over bits 31..30 from that table,
9597 as required for BIST support.
9600 @subsection XScale specific commands
9603 Some notes about the debug implementation on the XScale CPUs:
9605 The XScale CPU provides a special debug-only mini-instruction cache
9606 (mini-IC) in which exception vectors and target-resident debug handler
9607 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
9608 must point vector 0 (the reset vector) to the entry of the debug
9609 handler. However, this means that the complete first cacheline in the
9610 mini-IC is marked valid, which makes the CPU fetch all exception
9611 handlers from the mini-IC, ignoring the code in RAM.
9613 To address this situation, OpenOCD provides the @code{xscale
9614 vector_table} command, which allows the user to explicitly write
9615 individual entries to either the high or low vector table stored in
9618 It is recommended to place a pc-relative indirect branch in the vector
9619 table, and put the branch destination somewhere in memory. Doing so
9620 makes sure the code in the vector table stays constant regardless of
9621 code layout in memory:
9624 ldr pc,[pc,#0x100-8]
9625 ldr pc,[pc,#0x100-8]
9626 ldr pc,[pc,#0x100-8]
9627 ldr pc,[pc,#0x100-8]
9628 ldr pc,[pc,#0x100-8]
9629 ldr pc,[pc,#0x100-8]
9630 ldr pc,[pc,#0x100-8]
9631 ldr pc,[pc,#0x100-8]
9633 .long real_reset_vector
9634 .long real_ui_handler
9635 .long real_swi_handler
9637 .long real_data_abort
9638 .long 0 /* unused */
9639 .long real_irq_handler
9640 .long real_fiq_handler
9643 Alternatively, you may choose to keep some or all of the mini-IC
9644 vector table entries synced with those written to memory by your
9645 system software. The mini-IC can not be modified while the processor
9646 is executing, but for each vector table entry not previously defined
9647 using the @code{xscale vector_table} command, OpenOCD will copy the
9648 value from memory to the mini-IC every time execution resumes from a
9649 halt. This is done for both high and low vector tables (although the
9650 table not in use may not be mapped to valid memory, and in this case
9651 that copy operation will silently fail). This means that you will
9652 need to briefly halt execution at some strategic point during system
9653 start-up; e.g., after the software has initialized the vector table,
9654 but before exceptions are enabled. A breakpoint can be used to
9655 accomplish this once the appropriate location in the start-up code has
9656 been identified. A watchpoint over the vector table region is helpful
9657 in finding the location if you're not sure. Note that the same
9658 situation exists any time the vector table is modified by the system
9661 The debug handler must be placed somewhere in the address space using
9662 the @code{xscale debug_handler} command. The allowed locations for the
9663 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
9664 0xfffff800). The default value is 0xfe000800.
9666 XScale has resources to support two hardware breakpoints and two
9667 watchpoints. However, the following restrictions on watchpoint
9668 functionality apply: (1) the value and mask arguments to the @code{wp}
9669 command are not supported, (2) the watchpoint length must be a
9670 power of two and not less than four, and can not be greater than the
9671 watchpoint address, and (3) a watchpoint with a length greater than
9672 four consumes all the watchpoint hardware resources. This means that
9673 at any one time, you can have enabled either two watchpoints with a
9674 length of four, or one watchpoint with a length greater than four.
9676 These commands are available to XScale based CPUs,
9677 which are implementations of the ARMv5TE architecture.
9679 @deffn {Command} {xscale analyze_trace}
9680 Displays the contents of the trace buffer.
9683 @deffn {Command} {xscale cache_clean_address} address
9684 Changes the address used when cleaning the data cache.
9687 @deffn {Command} {xscale cache_info}
9688 Displays information about the CPU caches.
9691 @deffn {Command} {xscale cp15} regnum [value]
9692 Display cp15 register @var{regnum};
9693 else if a @var{value} is provided, that value is written to that register.
9696 @deffn {Command} {xscale debug_handler} target address
9697 Changes the address used for the specified target's debug handler.
9700 @deffn {Command} {xscale dcache} [@option{enable}|@option{disable}]
9701 Enables or disable the CPU's data cache.
9704 @deffn {Command} {xscale dump_trace} filename
9705 Dumps the raw contents of the trace buffer to @file{filename}.
9708 @deffn {Command} {xscale icache} [@option{enable}|@option{disable}]
9709 Enables or disable the CPU's instruction cache.
9712 @deffn {Command} {xscale mmu} [@option{enable}|@option{disable}]
9713 Enables or disable the CPU's memory management unit.
9716 @deffn {Command} {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
9717 Displays the trace buffer status, after optionally
9718 enabling or disabling the trace buffer
9719 and modifying how it is emptied.
9722 @deffn {Command} {xscale trace_image} filename [offset [type]]
9723 Opens a trace image from @file{filename}, optionally rebasing
9724 its segment addresses by @var{offset}.
9725 The image @var{type} may be one of
9726 @option{bin} (binary), @option{ihex} (Intel hex),
9727 @option{elf} (ELF file), @option{s19} (Motorola s19),
9728 @option{mem}, or @option{builder}.
9731 @anchor{xscalevectorcatch}
9732 @deffn {Command} {xscale vector_catch} [mask]
9733 @cindex vector_catch
9734 Display a bitmask showing the hardware vectors to catch.
9735 If the optional parameter is provided, first set the bitmask to that value.
9737 The mask bits correspond with bit 16..23 in the DCSR:
9740 0x02 Trap Undefined Instructions
9741 0x04 Trap Software Interrupt
9742 0x08 Trap Prefetch Abort
9743 0x10 Trap Data Abort
9750 @deffn {Command} {xscale vector_table} [(@option{low}|@option{high}) index value]
9751 @cindex vector_table
9753 Set an entry in the mini-IC vector table. There are two tables: one for
9754 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
9755 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
9756 points to the debug handler entry and can not be overwritten.
9757 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
9759 Without arguments, the current settings are displayed.
9763 @section ARMv6 Architecture
9766 @subsection ARM11 specific commands
9769 @deffn {Command} {arm11 memwrite burst} [@option{enable}|@option{disable}]
9770 Displays the value of the memwrite burst-enable flag,
9771 which is enabled by default.
9772 If a boolean parameter is provided, first assigns that flag.
9773 Burst writes are only used for memory writes larger than 1 word.
9774 They improve performance by assuming that the CPU has read each data
9775 word over JTAG and completed its write before the next word arrives,
9776 instead of polling for a status flag to verify that completion.
9777 This is usually safe, because JTAG runs much slower than the CPU.
9780 @deffn {Command} {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
9781 Displays the value of the memwrite error_fatal flag,
9782 which is enabled by default.
9783 If a boolean parameter is provided, first assigns that flag.
9784 When set, certain memory write errors cause earlier transfer termination.
9787 @deffn {Command} {arm11 step_irq_enable} [@option{enable}|@option{disable}]
9788 Displays the value of the flag controlling whether
9789 IRQs are enabled during single stepping;
9790 they are disabled by default.
9791 If a boolean parameter is provided, first assigns that.
9794 @deffn {Command} {arm11 vcr} [value]
9795 @cindex vector_catch
9796 Displays the value of the @emph{Vector Catch Register (VCR)},
9797 coprocessor 14 register 7.
9798 If @var{value} is defined, first assigns that.
9800 Vector Catch hardware provides dedicated breakpoints
9801 for certain hardware events.
9802 The specific bit values are core-specific (as in fact is using
9803 coprocessor 14 register 7 itself) but all current ARM11
9804 cores @emph{except the ARM1176} use the same six bits.
9807 @section ARMv7 and ARMv8 Architecture
9811 @subsection ARMv7-A specific commands
9814 @deffn {Command} {cortex_a cache_info}
9815 display information about target caches
9818 @deffn {Command} {cortex_a dacrfixup} [@option{on}|@option{off}]
9819 Work around issues with software breakpoints when the program text is
9820 mapped read-only by the operating system. This option sets the CP15 DACR
9821 to "all-manager" to bypass MMU permission checks on memory access.
9825 @deffn {Command} {cortex_a dbginit}
9826 Initialize core debug
9827 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
9830 @deffn {Command} {cortex_a smp} [on|off]
9831 Display/set the current SMP mode
9834 @deffn {Command} {cortex_a smp_gdb} [core_id]
9835 Display/set the current core displayed in GDB
9838 @deffn {Command} {cortex_a maskisr} [@option{on}|@option{off}]
9839 Selects whether interrupts will be processed when single stepping
9842 @deffn {Command} {cache_config l2x} [base way]
9846 @deffn {Command} {cortex_a mmu dump} [@option{0}|@option{1}|@option{addr} address [@option{num_entries}]]
9847 Dump the MMU translation table from TTB0 or TTB1 register, or from physical
9848 memory location @var{address}. When dumping the table from @var{address}, print at most
9849 @var{num_entries} page table entries. @var{num_entries} is optional, if omitted, the maximum
9850 possible (4096) entries are printed.
9853 @subsection ARMv7-R specific commands
9856 @deffn {Command} {cortex_r4 dbginit}
9857 Initialize core debug
9858 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
9861 @deffn {Command} {cortex_r4 maskisr} [@option{on}|@option{off}]
9862 Selects whether interrupts will be processed when single stepping
9866 @subsection ARM CoreSight TPIU and SWO specific commands
9872 ARM CoreSight provides several modules to generate debugging
9873 information internally (ITM, DWT and ETM). Their output is directed
9874 through TPIU or SWO modules to be captured externally either on an SWO pin (this
9875 configuration is called SWV) or on a synchronous parallel trace port.
9877 ARM CoreSight provides independent HW blocks named TPIU and SWO each with its
9878 own functionality. Embedded in Cortex-M3 and M4, ARM provides an optional HW
9879 block that includes both TPIU and SWO functionalities and is again named TPIU,
9880 which causes quite some confusion.
9881 The registers map of all the TPIU and SWO implementations allows using a single
9882 driver that detects at runtime the features available.
9884 The @command{tpiu} is used for either TPIU or SWO.
9885 A convenient alias @command{swo} is available to help distinguish, in scripts,
9886 the commands for SWO from the commands for TPIU.
9888 @deffn {Command} {swo} ...
9889 Alias of @command{tpiu ...}. Can be used in scripts to distinguish the commands
9890 for SWO from the commands for TPIU.
9893 @deffn {Command} {tpiu create} tpiu_name configparams...
9894 Creates a TPIU or a SWO object. The two commands are equivalent.
9895 Add the object in a list and add new commands (@command{@var{tpiu_name}})
9896 which are used for various purposes including additional configuration.
9899 @item @var{tpiu_name} -- the name of the TPIU or SWO object.
9900 This name is also used to create the object's command, referred to here
9901 as @command{$tpiu_name}, and in other places where the TPIU or SWO needs to be identified.
9902 @item @var{configparams} -- all parameters accepted by @command{$tpiu_name configure} are permitted.
9904 You @emph{must} set here the AP and MEM_AP base_address through @code{-dap @var{dap_name}},
9905 @code{-ap-num @var{ap_number}} and @code{-baseaddr @var{base_address}}.
9909 @deffn {Command} {tpiu names}
9910 Lists all the TPIU or SWO objects created so far. The two commands are equivalent.
9913 @deffn {Command} {tpiu init}
9914 Initialize all registered TPIU and SWO. The two commands are equivalent.
9915 These commands are used internally during initialization. They can be issued
9916 at any time after the initialization, too.
9919 @deffn {Command} {$tpiu_name cget} queryparm
9920 Each configuration parameter accepted by @command{$tpiu_name configure} can be
9921 individually queried, to return its current value.
9922 The @var{queryparm} is a parameter name accepted by that command, such as @code{-dap}.
9925 @deffn {Command} {$tpiu_name configure} configparams...
9926 The options accepted by this command may also be specified as parameters
9927 to @command{tpiu create}. Their values can later be queried one at a time by
9928 using the @command{$tpiu_name cget} command.
9931 @item @code{-dap} @var{dap_name} -- names the DAP used to access this
9932 TPIU. @xref{dapdeclaration,,DAP declaration}, on how to create and manage DAP instances.
9934 @item @code{-ap-num} @var{ap_number} -- sets DAP access port for TPIU,
9935 @var{ap_number} is the numeric index of the DAP AP the TPIU is connected to.
9937 @item @code{-baseaddr} @var{base_address} -- sets the TPIU @var{base_address} where
9938 to access the TPIU in the DAP AP memory space.
9940 @item @code{-protocol} (@option{sync}|@option{uart}|@option{manchester}) -- sets the
9941 protocol used for trace data:
9943 @item @option{sync} -- synchronous parallel trace output mode, using @var{port_width}
9944 data bits (default);
9945 @item @option{uart} -- use asynchronous SWO mode with NRZ (same as regular UART 8N1) coding;
9946 @item @option{manchester} -- use asynchronous SWO mode with Manchester coding.
9949 @item @code{-event} @var{event_name} @var{event_body} -- assigns an event handler,
9950 a TCL string which is evaluated when the event is triggered. The events
9951 @code{pre-enable}, @code{post-enable}, @code{pre-disable} and @code{post-disable}
9952 are defined for TPIU/SWO.
9953 A typical use case for the event @code{pre-enable} is to enable the trace clock
9956 @item @code{-output} (@option{external}|@option{:}@var{port}|@var{filename}|@option{-}) -- specifies
9957 the destination of the trace data:
9959 @item @option{external} -- configure TPIU/SWO to let user capture trace
9960 output externally, either with an additional UART or with a logic analyzer (default);
9961 @item @option{-} -- configure TPIU/SWO and debug adapter to gather trace data
9962 and forward it to @command{tcl_trace} command;
9963 @item @option{:}@var{port} -- configure TPIU/SWO and debug adapter to gather
9964 trace data, open a TCP server at port @var{port} and send the trace data to
9965 each connected client;
9966 @item @var{filename} -- configure TPIU/SWO and debug adapter to
9967 gather trace data and append it to @var{filename}, which can be
9968 either a regular file or a named pipe.
9971 @item @code{-traceclk} @var{TRACECLKIN_freq} -- mandatory parameter.
9972 Specifies the frequency in Hz of the trace clock. For the TPIU embedded in
9973 Cortex-M3 or M4, this is usually the same frequency as HCLK. For protocol
9974 @option{sync} this is twice the frequency of the pin data rate.
9976 @item @code{-pin-freq} @var{trace_freq} -- specifies the expected data rate
9977 in Hz of the SWO pin. Parameter used only on protocols @option{uart} and
9978 @option{manchester}. Can be omitted to let the adapter driver select the
9979 maximum supported rate automatically.
9981 @item @code{-port-width} @var{port_width} -- sets to @var{port_width} the width
9982 of the synchronous parallel port used for trace output. Parameter used only on
9983 protocol @option{sync}. If not specified, default value is @var{1}.
9985 @item @code{-formatter} (@option{0}|@option{1}) -- specifies if the formatter
9986 should be enabled. Parameter used only on protocol @option{sync}. If not specified,
9987 default value is @var{0}.
9991 @deffn {Command} {$tpiu_name enable}
9992 Uses the parameters specified by the previous @command{$tpiu_name configure}
9993 to configure and enable the TPIU or the SWO.
9994 If required, the adapter is also configured and enabled to receive the trace
9996 This command can be used before @command{init}, but it will take effect only
9997 after the @command{init}.
10000 @deffn {Command} {$tpiu_name disable}
10001 Disable the TPIU or the SWO, terminating the receiving of the trace data.
10008 @item STM32L152 board is programmed with an application that configures
10009 PLL to provide core clock with 24MHz frequency; to use ITM output it's
10012 #include <libopencm3/cm3/itm.h>
10017 (the most obvious way is to use the first stimulus port for printf,
10018 for that this ITM_STIM8 assignment can be used inside _write(); to make it
10019 blocking to avoid data loss, add @code{while (!(ITM_STIM8(0) &
10020 ITM_STIM_FIFOREADY));});
10021 @item An FT2232H UART is connected to the SWO pin of the board;
10022 @item Commands to configure UART for 12MHz baud rate:
10024 $ setserial /dev/ttyUSB1 spd_cust divisor 5
10025 $ stty -F /dev/ttyUSB1 38400
10027 (FT2232H's base frequency is 60MHz, spd_cust allows to alias 38400
10028 baud with our custom divisor to get 12MHz)
10029 @item @code{itmdump -f /dev/ttyUSB1 -d1}
10030 @item OpenOCD invocation line:
10032 openocd -f interface/stlink.cfg \
10033 -c "transport select hla_swd" \
10034 -f target/stm32l1.cfg \
10035 -c "stm32l1.tpiu configure -protocol uart" \
10036 -c "stm32l1.tpiu configure -traceclk 24000000 -pin-freq 12000000" \
10037 -c "stm32l1.tpiu enable"
10041 @subsection ARMv7-M specific commands
10048 @deffn {Command} {itm port} @var{port} (@option{0}|@option{1}|@option{on}|@option{off})
10049 Enable or disable trace output for ITM stimulus @var{port} (counting
10050 from 0). Port 0 is enabled on target creation automatically.
10053 @deffn {Command} {itm ports} (@option{0}|@option{1}|@option{on}|@option{off})
10054 Enable or disable trace output for all ITM stimulus ports.
10057 @subsection Cortex-M specific commands
10060 @deffn {Command} {cortex_m maskisr} (@option{auto}|@option{on}|@option{off}|@option{steponly})
10061 Control masking (disabling) interrupts during target step/resume.
10063 The @option{auto} option handles interrupts during stepping in a way that they
10064 get served but don't disturb the program flow. The step command first allows
10065 pending interrupt handlers to execute, then disables interrupts and steps over
10066 the next instruction where the core was halted. After the step interrupts
10067 are enabled again. If the interrupt handlers don't complete within 500ms,
10068 the step command leaves with the core running.
10070 The @option{steponly} option disables interrupts during single-stepping but
10071 enables them during normal execution. This can be used as a partial workaround
10072 for 702596 erratum in Cortex-M7 r0p1. See "Cortex-M7 (AT610) and Cortex-M7 with
10073 FPU (AT611) Software Developer Errata Notice" from ARM for further details.
10075 Note that a free hardware (FPB) breakpoint is required for the @option{auto}
10076 option. If no breakpoint is available at the time of the step, then the step
10077 is taken with interrupts enabled, i.e. the same way the @option{off} option
10080 Default is @option{auto}.
10083 @deffn {Command} {cortex_m vector_catch} [@option{all}|@option{none}|list]
10084 @cindex vector_catch
10085 Vector Catch hardware provides dedicated breakpoints
10086 for certain hardware events.
10088 Parameters request interception of
10089 @option{all} of these hardware event vectors,
10090 @option{none} of them,
10091 or one or more of the following:
10092 @option{hard_err} for a HardFault exception;
10093 @option{mm_err} for a MemManage exception;
10094 @option{bus_err} for a BusFault exception;
10096 @option{state_err},
10097 @option{chk_err}, or
10098 @option{nocp_err} for various UsageFault exceptions; or
10100 If NVIC setup code does not enable them,
10101 MemManage, BusFault, and UsageFault exceptions
10102 are mapped to HardFault.
10103 UsageFault checks for
10104 divide-by-zero and unaligned access
10105 must also be explicitly enabled.
10107 This finishes by listing the current vector catch configuration.
10110 @deffn {Command} {cortex_m reset_config} (@option{sysresetreq}|@option{vectreset})
10111 Control reset handling if hardware srst is not fitted
10112 @xref{reset_config,,reset_config}.
10115 @item @option{sysresetreq} use AIRCR SYSRESETREQ to reset system.
10116 @item @option{vectreset} use AIRCR VECTRESET to reset system (default).
10119 Using @option{vectreset} is a safe option for Cortex-M3, M4 and M7 cores.
10120 This however has the disadvantage of only resetting the core, all peripherals
10121 are unaffected. A solution would be to use a @code{reset-init} event handler
10122 to manually reset the peripherals.
10123 @xref{targetevents,,Target Events}.
10125 Cortex-M0, M0+ and M1 do not support @option{vectreset}, use @option{sysresetreq}
10129 @subsection ARMv8-A specific commands
10133 @deffn {Command} {aarch64 cache_info}
10134 Display information about target caches
10137 @deffn {Command} {aarch64 dbginit}
10138 This command enables debugging by clearing the OS Lock and sticky power-down and reset
10139 indications. It also establishes the expected, basic cross-trigger configuration the aarch64
10140 target code relies on. In a configuration file, the command would typically be called from a
10141 @code{reset-end} or @code{reset-deassert-post} handler, to re-enable debugging after a system reset.
10142 However, normally it is not necessary to use the command at all.
10145 @deffn {Command} {aarch64 disassemble} address [count]
10146 @cindex disassemble
10147 Disassembles @var{count} instructions starting at @var{address}.
10148 If @var{count} is not specified, a single instruction is disassembled.
10151 @deffn {Command} {aarch64 smp} [on|off]
10152 Display, enable or disable SMP handling mode. The state of SMP handling influences the way targets in an SMP group
10153 are handled by the run control. With SMP handling enabled, issuing halt or resume to one core will trigger
10154 halting or resuming of all cores in the group. The command @code{target smp} defines which targets are in the SMP
10155 group. With SMP handling disabled, all targets need to be treated individually.
10158 @deffn {Command} {aarch64 maskisr} [@option{on}|@option{off}]
10159 Selects whether interrupts will be processed when single stepping. The default configuration is
10163 @deffn {Command} {$target_name catch_exc} [@option{off}|@option{sec_el1}|@option{sec_el3}|@option{nsec_el1}|@option{nsec_el2}]+
10164 Cause @command{$target_name} to halt when an exception is taken. Any combination of
10165 Secure (sec) EL1/EL3 or Non-Secure (nsec) EL1/EL2 is valid. The target
10166 @command{$target_name} will halt before taking the exception. In order to resume
10167 the target, the exception catch must be disabled again with @command{$target_name catch_exc off}.
10168 Issuing the command without options prints the current configuration.
10171 @section EnSilica eSi-RISC Architecture
10173 eSi-RISC is a highly configurable microprocessor architecture for embedded systems
10174 provided by EnSilica. (See: @url{http://www.ensilica.com/risc-ip/}.)
10176 @subsection eSi-RISC Configuration
10178 @deffn {Command} {esirisc cache_arch} (@option{harvard}|@option{von_neumann})
10179 Configure the caching architecture. Targets with the @code{UNIFIED_ADDRESS_SPACE}
10180 option disabled employ a Harvard architecture. By default, @option{von_neumann} is assumed.
10183 @deffn {Command} {esirisc hwdc} (@option{all}|@option{none}|mask ...)
10184 Configure hardware debug control. The HWDC register controls which exceptions return
10185 control back to the debugger. Possible masks are @option{all}, @option{none},
10186 @option{reset}, @option{interrupt}, @option{syscall}, @option{error}, and @option{debug}.
10187 By default, @option{reset}, @option{error}, and @option{debug} are enabled.
10190 @subsection eSi-RISC Operation
10192 @deffn {Command} {esirisc flush_caches}
10193 Flush instruction and data caches. This command requires that the target is halted
10194 when the command is issued and configured with an instruction or data cache.
10197 @subsection eSi-Trace Configuration
10199 eSi-RISC targets may be configured with support for instruction tracing. Trace
10200 data may be written to an in-memory buffer or FIFO. If a FIFO is configured, DMA
10201 is typically employed to move trace data off-device using a high-speed
10202 peripheral (eg. SPI). Collected trace data is encoded in one of three different
10203 formats. At a minimum, @command{esirisc trace buffer} or @command{esirisc trace
10204 fifo} must be issued along with @command{esirisc trace format} before trace data
10207 OpenOCD provides rudimentary analysis of collected trace data. If more detail is
10208 needed, collected trace data can be dumped to a file and processed by external
10212 OpenOCD is unable to process trace data sent to a FIFO. A potential workaround
10213 for this issue is to configure DMA to copy trace data to an in-memory buffer,
10214 which can then be passed to the @command{esirisc trace analyze} and
10215 @command{esirisc trace dump} commands.
10217 It is possible to corrupt trace data when using a FIFO if the peripheral
10218 responsible for draining data from the FIFO is not fast enough. This can be
10219 managed by enabling flow control, however this can impact timing-sensitive
10220 software operation on the CPU.
10223 @deffn {Command} {esirisc trace buffer} address size [@option{wrap}]
10224 Configure trace buffer using the provided address and size. If the @option{wrap}
10225 option is specified, trace collection will continue once the end of the buffer
10226 is reached. By default, wrap is disabled.
10229 @deffn {Command} {esirisc trace fifo} address
10230 Configure trace FIFO using the provided address.
10233 @deffn {Command} {esirisc trace flow_control} (@option{enable}|@option{disable})
10234 Enable or disable stalling the CPU to collect trace data. By default, flow
10235 control is disabled.
10238 @deffn {Command} {esirisc trace format} (@option{full}|@option{branch}|@option{icache}) pc_bits
10239 Configure trace format and number of PC bits to be captured. @option{pc_bits}
10240 must be within 1 and 31 as the LSB is not collected. If external tooling is used
10241 to analyze collected trace data, these values must match.
10243 Supported trace formats:
10245 @item @option{full} capture full trace data, allowing execution history and
10246 timing to be determined.
10247 @item @option{branch} capture taken branch instructions and branch target
10249 @item @option{icache} capture instruction cache misses.
10253 @deffn {Command} {esirisc trace trigger start} (@option{condition}) [start_data start_mask]
10254 Configure trigger start condition using the provided start data and mask. A
10255 brief description of each condition is provided below; for more detail on how
10256 these values are used, see the eSi-RISC Architecture Manual.
10258 Supported conditions:
10260 @item @option{none} manual tracing (see @command{esirisc trace start}).
10261 @item @option{pc} start tracing if the PC matches start data and mask.
10262 @item @option{load} start tracing if the effective address of a load
10263 instruction matches start data and mask.
10264 @item @option{store} start tracing if the effective address of a store
10265 instruction matches start data and mask.
10266 @item @option{exception} start tracing if the EID of an exception matches start
10268 @item @option{eret} start tracing when an @code{ERET} instruction is executed.
10269 @item @option{wait} start tracing when a @code{WAIT} instruction is executed.
10270 @item @option{stop} start tracing when a @code{STOP} instruction is executed.
10271 @item @option{high} start tracing when an external signal is a logical high.
10272 @item @option{low} start tracing when an external signal is a logical low.
10276 @deffn {Command} {esirisc trace trigger stop} (@option{condition}) [stop_data stop_mask]
10277 Configure trigger stop condition using the provided stop data and mask. A brief
10278 description of each condition is provided below; for more detail on how these
10279 values are used, see the eSi-RISC Architecture Manual.
10281 Supported conditions:
10283 @item @option{none} manual tracing (see @command{esirisc trace stop}).
10284 @item @option{pc} stop tracing if the PC matches stop data and mask.
10285 @item @option{load} stop tracing if the effective address of a load
10286 instruction matches stop data and mask.
10287 @item @option{store} stop tracing if the effective address of a store
10288 instruction matches stop data and mask.
10289 @item @option{exception} stop tracing if the EID of an exception matches stop
10291 @item @option{eret} stop tracing when an @code{ERET} instruction is executed.
10292 @item @option{wait} stop tracing when a @code{WAIT} instruction is executed.
10293 @item @option{stop} stop tracing when a @code{STOP} instruction is executed.
10297 @deffn {Command} {esirisc trace trigger delay} (@option{trigger}) [cycles]
10298 Configure trigger start/stop delay in clock cycles.
10300 Supported triggers:
10302 @item @option{none} no delay to start or stop collection.
10303 @item @option{start} delay @option{cycles} after trigger to start collection.
10304 @item @option{stop} delay @option{cycles} after trigger to stop collection.
10305 @item @option{both} delay @option{cycles} after both triggers to start or stop
10310 @subsection eSi-Trace Operation
10312 @deffn {Command} {esirisc trace init}
10313 Initialize trace collection. This command must be called any time the
10314 configuration changes. If a trace buffer has been configured, the contents will
10315 be overwritten when trace collection starts.
10318 @deffn {Command} {esirisc trace info}
10319 Display trace configuration.
10322 @deffn {Command} {esirisc trace status}
10323 Display trace collection status.
10326 @deffn {Command} {esirisc trace start}
10327 Start manual trace collection.
10330 @deffn {Command} {esirisc trace stop}
10331 Stop manual trace collection.
10334 @deffn {Command} {esirisc trace analyze} [address size]
10335 Analyze collected trace data. This command may only be used if a trace buffer
10336 has been configured. If a trace FIFO has been configured, trace data must be
10337 copied to an in-memory buffer identified by the @option{address} and
10338 @option{size} options using DMA.
10341 @deffn {Command} {esirisc trace dump} [address size] @file{filename}
10342 Dump collected trace data to file. This command may only be used if a trace
10343 buffer has been configured. If a trace FIFO has been configured, trace data must
10344 be copied to an in-memory buffer identified by the @option{address} and
10345 @option{size} options using DMA.
10348 @section Intel Architecture
10350 Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
10351 (Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
10352 Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
10353 software debug and the CLTAP is used for SoC level operations.
10354 Useful docs are here: https://communities.intel.com/community/makers/documentation
10356 @item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
10357 @item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
10358 @item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
10361 @subsection x86 32-bit specific commands
10362 The three main address spaces for x86 are memory, I/O and configuration space.
10363 These commands allow a user to read and write to the 64Kbyte I/O address space.
10365 @deffn {Command} {x86_32 idw} address
10366 Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
10369 @deffn {Command} {x86_32 idh} address
10370 Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
10373 @deffn {Command} {x86_32 idb} address
10374 Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
10377 @deffn {Command} {x86_32 iww} address
10378 Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
10381 @deffn {Command} {x86_32 iwh} address
10382 Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
10385 @deffn {Command} {x86_32 iwb} address
10386 Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
10389 @section OpenRISC Architecture
10391 The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
10392 configured with any of the TAP / Debug Unit available.
10394 @subsection TAP and Debug Unit selection commands
10395 @deffn {Command} {tap_select} (@option{vjtag}|@option{mohor}|@option{xilinx_bscan})
10396 Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and Mohor TAP.
10398 @deffn {Command} {du_select} (@option{adv}|@option{mohor}) [option]
10399 Select between the Advanced Debug Interface and the classic one.
10401 An option can be passed as a second argument to the debug unit.
10403 When using the Advanced Debug Interface, option = 1 means the RTL core is
10404 configured with ADBG_USE_HISPEED = 1. This configuration skips status checking
10405 between bytes while doing read or write bursts.
10408 @subsection Registers commands
10409 @deffn {Command} {addreg} [name] [address] [feature] [reg_group]
10410 Add a new register in the cpu register list. This register will be
10411 included in the generated target descriptor file.
10413 @strong{[feature]} must be "org.gnu.gdb.or1k.group[0..10]".
10415 @strong{[reg_group]} can be anything. The default register list defines "system",
10416 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic"
10417 and "timer" groups.
10421 addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
10426 @section RISC-V Architecture
10428 @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG
10429 debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32
10430 harts. (It's possible to increase this limit to 1024 by changing
10431 RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V
10432 Debug Specification, but there is also support for legacy targets that
10433 implement version 0.11.
10435 @subsection RISC-V Terminology
10437 A @emph{hart} is a hardware thread. A hart may share resources (eg. FPU) with
10438 another hart, or may be a separate core. RISC-V treats those the same, and
10439 OpenOCD exposes each hart as a separate core.
10441 @subsection Vector Registers
10443 For harts that implement the vector extension, OpenOCD provides access to the
10444 relevant CSRs, as well as the vector registers (v0-v31). The size of each
10445 vector register is dependent on the value of vlenb. RISC-V allows each vector
10446 register to be divided into selected-width elements, and this division can be
10447 changed at run-time. Because OpenOCD cannot update register definitions at
10448 run-time, it exposes each vector register to gdb as a union of fields of
10449 vectors so that users can easily access individual bytes, shorts, words,
10450 longs, and quads inside each vector register. It is left to gdb or
10451 higher-level debuggers to present this data in a more intuitive format.
10453 In the XML register description, the vector registers (when vlenb=16) look as
10457 <feature name="org.gnu.gdb.riscv.vector">
10458 <vector id="bytes" type="uint8" count="16"/>
10459 <vector id="shorts" type="uint16" count="8"/>
10460 <vector id="words" type="uint32" count="4"/>
10461 <vector id="longs" type="uint64" count="2"/>
10462 <vector id="quads" type="uint128" count="1"/>
10463 <union id="riscv_vector">
10464 <field name="b" type="bytes"/>
10465 <field name="s" type="shorts"/>
10466 <field name="w" type="words"/>
10467 <field name="l" type="longs"/>
10468 <field name="q" type="quads"/>
10470 <reg name="v0" bitsize="128" regnum="4162" save-restore="no"
10471 type="riscv_vector" group="vector"/>
10473 <reg name="v31" bitsize="128" regnum="4193" save-restore="no"
10474 type="riscv_vector" group="vector"/>
10478 @subsection RISC-V Debug Configuration Commands
10480 @deffn {Config Command} {riscv expose_csrs} n[-m|=name] [...]
10481 Configure which CSRs to expose in addition to the standard ones. The CSRs to expose
10482 can be specified as individual register numbers or register ranges (inclusive). For the
10483 individually listed CSRs, a human-readable name can optionally be set using the @code{n=name}
10484 syntax, which will get @code{csr_} prepended to it. If no name is provided, the register will be
10485 named @code{csr<n>}.
10487 By default OpenOCD attempts to expose only CSRs that are mentioned in a spec,
10488 and then only if the corresponding extension appears to be implemented. This
10489 command can be used if OpenOCD gets this wrong, or if the target implements custom
10493 # Expose a single RISC-V CSR number 128 under the name "csr128":
10494 $_TARGETNAME expose_csrs 128
10496 # Expose multiple RISC-V CSRs 128..132 under names "csr128" through "csr132":
10497 $_TARGETNAME expose_csrs 128-132
10499 # Expose a single RISC-V CSR number 1996 under custom name "csr_myregister":
10500 $_TARGETNAME expose_csrs 1996=myregister
10504 @deffn {Config Command} {riscv expose_custom} n[-m|=name] [...]
10505 The RISC-V Debug Specification allows targets to expose custom registers
10506 through abstract commands. (See Section 3.5.1.1 in that document.) This command
10507 configures individual registers or register ranges (inclusive) that shall be exposed.
10508 Number 0 indicates the first custom register, whose abstract command number is 0xc000.
10509 For individually listed registers, a human-readable name can be optionally provided
10510 using the @code{n=name} syntax, which will get @code{custom_} prepended to it. If no
10511 name is provided, the register will be named @code{custom<n>}.
10514 # Expose one RISC-V custom register with number 0xc010 (0xc000 + 16)
10515 # under the name "custom16":
10516 $_TARGETNAME expose_custom 16
10518 # Expose a range of RISC-V custom registers with numbers 0xc010 .. 0xc018
10519 # (0xc000+16 .. 0xc000+24) under the names "custom16" through "custom24":
10520 $_TARGETNAME expose_custom 16-24
10522 # Expose one RISC-V custom register with number 0xc020 (0xc000 + 32) under
10523 # user-defined name "custom_myregister":
10524 $_TARGETNAME expose_custom 32=myregister
10528 @deffn {Command} {riscv set_command_timeout_sec} [seconds]
10529 Set the wall-clock timeout (in seconds) for individual commands. The default
10530 should work fine for all but the slowest targets (eg. simulators).
10533 @deffn {Command} {riscv set_reset_timeout_sec} [seconds]
10534 Set the maximum time to wait for a hart to come out of reset after reset is
10538 @deffn {Command} {riscv set_scratch_ram} none|[address]
10539 Set the address of 16 bytes of scratch RAM the debugger can use, or 'none'.
10540 This is used to access 64-bit floating point registers on 32-bit targets.
10543 @deffn Command {riscv set_mem_access} method1 [method2] [method3]
10544 Specify which RISC-V memory access method(s) shall be used, and in which order
10545 of priority. At least one method must be specified.
10547 Available methods are:
10549 @item @code{progbuf} - Use RISC-V Debug Program Buffer to access memory.
10550 @item @code{sysbus} - Access memory via RISC-V Debug System Bus interface.
10551 @item @code{abstract} - Access memory via RISC-V Debug abstract commands.
10554 By default, all memory access methods are enabled in the following order:
10555 @code{progbuf sysbus abstract}.
10557 This command can be used to change the memory access methods if the default
10558 behavior is not suitable for a particular target.
10561 @deffn {Command} {riscv set_enable_virtual} on|off
10562 When on, memory accesses are performed on physical or virtual memory depending
10563 on the current system configuration. When off (default), all memory accessses are performed
10564 on physical memory.
10567 @deffn {Command} {riscv set_enable_virt2phys} on|off
10568 When on (default), memory accesses are performed on physical or virtual memory
10569 depending on the current satp configuration. When off, all memory accessses are
10570 performed on physical memory.
10573 @deffn {Command} {riscv resume_order} normal|reversed
10574 Some software assumes all harts are executing nearly continuously. Such
10575 software may be sensitive to the order that harts are resumed in. On harts
10576 that don't support hasel, this option allows the user to choose the order the
10577 harts are resumed in. If you are using this option, it's probably masking a
10578 race condition problem in your code.
10580 Normal order is from lowest hart index to highest. This is the default
10581 behavior. Reversed order is from highest hart index to lowest.
10584 @deffn {Command} {riscv set_ir} (@option{idcode}|@option{dtmcs}|@option{dmi}) [value]
10585 Set the IR value for the specified JTAG register. This is useful, for
10586 example, when using the existing JTAG interface on a Xilinx FPGA by
10587 way of BSCANE2 primitives that only permit a limited selection of IR
10590 When utilizing version 0.11 of the RISC-V Debug Specification,
10591 @option{dtmcs} and @option{dmi} set the IR values for the DTMCONTROL
10592 and DBUS registers, respectively.
10595 @deffn {Command} {riscv use_bscan_tunnel} value
10596 Enable or disable use of a BSCAN tunnel to reach DM. Supply the width of
10597 the DM transport TAP's instruction register to enable. Supply a value of 0 to disable.
10600 @deffn {Command} {riscv set_ebreakm} on|off
10601 Control dcsr.ebreakm. When on (default), M-mode ebreak instructions trap to
10602 OpenOCD. When off, they generate a breakpoint exception handled internally.
10605 @deffn {Command} {riscv set_ebreaks} on|off
10606 Control dcsr.ebreaks. When on (default), S-mode ebreak instructions trap to
10607 OpenOCD. When off, they generate a breakpoint exception handled internally.
10610 @deffn {Command} {riscv set_ebreaku} on|off
10611 Control dcsr.ebreaku. When on (default), U-mode ebreak instructions trap to
10612 OpenOCD. When off, they generate a breakpoint exception handled internally.
10615 @subsection RISC-V Authentication Commands
10617 The following commands can be used to authenticate to a RISC-V system. Eg. a
10618 trivial challenge-response protocol could be implemented as follows in a
10619 configuration file, immediately following @command{init}:
10621 set challenge [riscv authdata_read]
10622 riscv authdata_write [expr @{$challenge + 1@}]
10625 @deffn {Command} {riscv authdata_read}
10626 Return the 32-bit value read from authdata.
10629 @deffn {Command} {riscv authdata_write} value
10630 Write the 32-bit value to authdata.
10633 @subsection RISC-V DMI Commands
10635 The following commands allow direct access to the Debug Module Interface, which
10636 can be used to interact with custom debug features.
10638 @deffn {Command} {riscv dmi_read} address
10639 Perform a 32-bit DMI read at address, returning the value.
10642 @deffn {Command} {riscv dmi_write} address value
10643 Perform a 32-bit DMI write of value at address.
10646 @section ARC Architecture
10649 Synopsys DesignWare ARC Processors are a family of 32-bit CPUs that SoC
10650 designers can optimize for a wide range of uses, from deeply embedded to
10651 high-performance host applications in a variety of market segments. See more
10652 at: @url{http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx}.
10653 OpenOCD currently supports ARC EM processors.
10654 There is a set ARC-specific OpenOCD commands that allow low-level
10655 access to the core and provide necessary support for ARC extensibility and
10656 configurability capabilities. ARC processors has much more configuration
10657 capabilities than most of the other processors and in addition there is an
10658 extension interface that allows SoC designers to add custom registers and
10659 instructions. For the OpenOCD that mostly means that set of core and AUX
10660 registers in target will vary and is not fixed for a particular processor
10661 model. To enable extensibility several TCL commands are provided that allow to
10662 describe those optional registers in OpenOCD configuration files. Moreover
10663 those commands allow for a dynamic target features discovery.
10666 @subsection General ARC commands
10668 @deffn {Config Command} {arc add-reg} configparams
10670 Add a new register to processor target. By default newly created register is
10671 marked as not existing. @var{configparams} must have following required
10676 @item @code{-name} name
10677 @*Name of a register.
10679 @item @code{-num} number
10680 @*Architectural register number: core register number or AUX register number.
10682 @item @code{-feature} XML_feature
10683 @*Name of GDB XML target description feature.
10687 @var{configparams} may have following optional arguments:
10691 @item @code{-gdbnum} number
10692 @*GDB register number. It is recommended to not assign GDB register number
10693 manually, because there would be a risk that two register will have same
10694 number. When register GDB number is not set with this option, then register
10695 will get a previous register number + 1. This option is required only for those
10696 registers that must be at particular address expected by GDB.
10699 @*This option specifies that register is a core registers. If not - this is an
10700 AUX register. AUX registers and core registers reside in different address
10704 @*This options specifies that register is a BCR register. BCR means Build
10705 Configuration Registers - this is a special type of AUX registers that are read
10706 only and non-volatile, that is - they never change their value. Therefore OpenOCD
10707 never invalidates values of those registers in internal caches. Because BCR is a
10708 type of AUX registers, this option cannot be used with @code{-core}.
10710 @item @code{-type} type_name
10711 @*Name of type of this register. This can be either one of the basic GDB types,
10712 or a custom types described with @command{arc add-reg-type-[flags|struct]}.
10715 @* If specified then this is a "general" register. General registers are always
10716 read by OpenOCD on context save (when core has just been halted) and is always
10717 transferred to GDB client in a response to g-packet. Contrary to this,
10718 non-general registers are read and sent to GDB client on-demand. In general it
10719 is not recommended to apply this option to custom registers.
10725 @deffn {Config Command} {arc add-reg-type-flags} -name name flags...
10726 Adds new register type of ``flags'' class. ``Flags'' types can contain only
10727 one-bit fields. Each flag definition looks like @code{-flag name bit-position}.
10730 @anchor{add-reg-type-struct}
10731 @deffn {Config Command} {arc add-reg-type-struct} -name name structs...
10732 Adds new register type of ``struct'' class. ``Struct'' types can contain either
10733 bit-fields or fields of other types, however at the moment only bit fields are
10734 supported. Structure bit field definition looks like @code{-bitfield name
10738 @deffn {Command} {arc get-reg-field} reg-name field-name
10739 Returns value of bit-field in a register. Register must be ``struct'' register
10740 type, @xref{add-reg-type-struct}. command definition.
10743 @deffn {Command} {arc set-reg-exists} reg-names...
10744 Specify that some register exists. Any amount of names can be passed
10745 as an argument for a single command invocation.
10748 @subsection ARC JTAG commands
10750 @deffn {Command} {arc jtag set-aux-reg} regnum value
10751 This command writes value to AUX register via its number. This command access
10752 register in target directly via JTAG, bypassing any OpenOCD internal caches,
10753 therefore it is unsafe to use if that register can be operated by other means.
10757 @deffn {Command} {arc jtag set-core-reg} regnum value
10758 This command is similar to @command{arc jtag set-aux-reg} but is for core
10762 @deffn {Command} {arc jtag get-aux-reg} regnum
10763 This command returns the value storded in AUX register via its number. This commands access
10764 register in target directly via JTAG, bypassing any OpenOCD internal caches,
10765 therefore it is unsafe to use if that register can be operated by other means.
10769 @deffn {Command} {arc jtag get-core-reg} regnum
10770 This command is similar to @command{arc jtag get-aux-reg} but is for core
10774 @section STM8 Architecture
10775 @uref{http://st.com/stm8/, STM8} is a 8-bit microcontroller platform from
10776 STMicroelectronics, based on a proprietary 8-bit core architecture.
10778 OpenOCD supports debugging STM8 through the STMicroelectronics debug
10779 protocol SWIM, @pxref{swimtransport,,SWIM}.
10781 @anchor{softwaredebugmessagesandtracing}
10782 @section Software Debug Messages and Tracing
10783 @cindex Linux-ARM DCC support
10787 OpenOCD can process certain requests from target software, when
10788 the target uses appropriate libraries.
10789 The most powerful mechanism is semihosting, but there is also
10790 a lighter weight mechanism using only the DCC channel.
10792 Currently @command{target_request debugmsgs}
10793 is supported only for @option{arm7_9} and @option{cortex_m} cores.
10794 These messages are received as part of target polling, so
10795 you need to have @command{poll on} active to receive them.
10796 They are intrusive in that they will affect program execution
10797 times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
10799 See @file{libdcc} in the contrib dir for more details.
10800 In addition to sending strings, characters, and
10801 arrays of various size integers from the target,
10802 @file{libdcc} also exports a software trace point mechanism.
10803 The target being debugged may
10804 issue trace messages which include a 24-bit @dfn{trace point} number.
10805 Trace point support includes two distinct mechanisms,
10806 each supported by a command:
10809 @item @emph{History} ... A circular buffer of trace points
10810 can be set up, and then displayed at any time.
10811 This tracks where code has been, which can be invaluable in
10812 finding out how some fault was triggered.
10814 The buffer may overflow, since it collects records continuously.
10815 It may be useful to use some of the 24 bits to represent a
10816 particular event, and other bits to hold data.
10818 @item @emph{Counting} ... An array of counters can be set up,
10819 and then displayed at any time.
10820 This can help establish code coverage and identify hot spots.
10822 The array of counters is directly indexed by the trace point
10823 number, so trace points with higher numbers are not counted.
10826 Linux-ARM kernels have a ``Kernel low-level debugging
10827 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
10828 depends on CONFIG_DEBUG_LL) which uses this mechanism to
10829 deliver messages before a serial console can be activated.
10830 This is not the same format used by @file{libdcc}.
10831 Other software, such as the U-Boot boot loader, sometimes
10832 does the same thing.
10834 @deffn {Command} {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
10835 Displays current handling of target DCC message requests.
10836 These messages may be sent to the debugger while the target is running.
10837 The optional @option{enable} and @option{charmsg} parameters
10838 both enable the messages, while @option{disable} disables them.
10840 With @option{charmsg} the DCC words each contain one character,
10841 as used by Linux with CONFIG_DEBUG_ICEDCC;
10842 otherwise the libdcc format is used.
10845 @deffn {Command} {trace history} [@option{clear}|count]
10846 With no parameter, displays all the trace points that have triggered
10847 in the order they triggered.
10848 With the parameter @option{clear}, erases all current trace history records.
10849 With a @var{count} parameter, allocates space for that many
10853 @deffn {Command} {trace point} [@option{clear}|identifier]
10854 With no parameter, displays all trace point identifiers and how many times
10855 they have been triggered.
10856 With the parameter @option{clear}, erases all current trace point counters.
10857 With a numeric @var{identifier} parameter, creates a new a trace point counter
10858 and associates it with that identifier.
10860 @emph{Important:} The identifier and the trace point number
10861 are not related except by this command.
10862 These trace point numbers always start at zero (from server startup,
10863 or after @command{trace point clear}) and count up from there.
10867 @node JTAG Commands
10868 @chapter JTAG Commands
10869 @cindex JTAG Commands
10870 Most general purpose JTAG commands have been presented earlier.
10871 (@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
10872 Lower level JTAG commands, as presented here,
10873 may be needed to work with targets which require special
10874 attention during operations such as reset or initialization.
10876 To use these commands you will need to understand some
10877 of the basics of JTAG, including:
10880 @item A JTAG scan chain consists of a sequence of individual TAP
10881 devices such as a CPUs.
10882 @item Control operations involve moving each TAP through the same
10883 standard state machine (in parallel)
10884 using their shared TMS and clock signals.
10885 @item Data transfer involves shifting data through the chain of
10886 instruction or data registers of each TAP, writing new register values
10887 while the reading previous ones.
10888 @item Data register sizes are a function of the instruction active in
10889 a given TAP, while instruction register sizes are fixed for each TAP.
10890 All TAPs support a BYPASS instruction with a single bit data register.
10891 @item The way OpenOCD differentiates between TAP devices is by
10892 shifting different instructions into (and out of) their instruction
10896 @section Low Level JTAG Commands
10898 These commands are used by developers who need to access
10899 JTAG instruction or data registers, possibly controlling
10900 the order of TAP state transitions.
10901 If you're not debugging OpenOCD internals, or bringing up a
10902 new JTAG adapter or a new type of TAP device (like a CPU or
10903 JTAG router), you probably won't need to use these commands.
10904 In a debug session that doesn't use JTAG for its transport protocol,
10905 these commands are not available.
10907 @deffn {Command} {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
10908 Loads the data register of @var{tap} with a series of bit fields
10909 that specify the entire register.
10910 Each field is @var{numbits} bits long with
10911 a numeric @var{value} (hexadecimal encouraged).
10912 The return value holds the original value of each
10915 For example, a 38 bit number might be specified as one
10916 field of 32 bits then one of 6 bits.
10917 @emph{For portability, never pass fields which are more
10918 than 32 bits long. Many OpenOCD implementations do not
10919 support 64-bit (or larger) integer values.}
10921 All TAPs other than @var{tap} must be in BYPASS mode.
10922 The single bit in their data registers does not matter.
10924 When @var{tap_state} is specified, the JTAG state machine is left
10926 For example @sc{drpause} might be specified, so that more
10927 instructions can be issued before re-entering the @sc{run/idle} state.
10928 If the end state is not specified, the @sc{run/idle} state is entered.
10931 OpenOCD does not record information about data register lengths,
10932 so @emph{it is important that you get the bit field lengths right}.
10933 Remember that different JTAG instructions refer to different
10934 data registers, which may have different lengths.
10935 Moreover, those lengths may not be fixed;
10936 the SCAN_N instruction can change the length of
10937 the register accessed by the INTEST instruction
10938 (by connecting a different scan chain).
10942 @deffn {Command} {flush_count}
10943 Returns the number of times the JTAG queue has been flushed.
10944 This may be used for performance tuning.
10946 For example, flushing a queue over USB involves a
10947 minimum latency, often several milliseconds, which does
10948 not change with the amount of data which is written.
10949 You may be able to identify performance problems by finding
10950 tasks which waste bandwidth by flushing small transfers too often,
10951 instead of batching them into larger operations.
10954 @deffn {Command} {irscan} [tap instruction]+ [@option{-endstate} tap_state]
10955 For each @var{tap} listed, loads the instruction register
10956 with its associated numeric @var{instruction}.
10957 (The number of bits in that instruction may be displayed
10958 using the @command{scan_chain} command.)
10959 For other TAPs, a BYPASS instruction is loaded.
10961 When @var{tap_state} is specified, the JTAG state machine is left
10963 For example @sc{irpause} might be specified, so the data register
10964 can be loaded before re-entering the @sc{run/idle} state.
10965 If the end state is not specified, the @sc{run/idle} state is entered.
10968 OpenOCD currently supports only a single field for instruction
10969 register values, unlike data register values.
10970 For TAPs where the instruction register length is more than 32 bits,
10971 portable scripts currently must issue only BYPASS instructions.
10975 @deffn {Command} {pathmove} start_state [next_state ...]
10976 Start by moving to @var{start_state}, which
10977 must be one of the @emph{stable} states.
10978 Unless it is the only state given, this will often be the
10979 current state, so that no TCK transitions are needed.
10980 Then, in a series of single state transitions
10981 (conforming to the JTAG state machine) shift to
10982 each @var{next_state} in sequence, one per TCK cycle.
10983 The final state must also be stable.
10986 @deffn {Command} {runtest} @var{num_cycles}
10987 Move to the @sc{run/idle} state, and execute at least
10988 @var{num_cycles} of the JTAG clock (TCK).
10989 Instructions often need some time
10990 to execute before they take effect.
10993 @c tms_sequence (short|long)
10994 @c ... temporary, debug-only, other than USBprog bug workaround...
10996 @deffn {Command} {verify_ircapture} (@option{enable}|@option{disable})
10997 Verify values captured during @sc{ircapture} and returned
10998 during IR scans. Default is enabled, but this can be
10999 overridden by @command{verify_jtag}.
11000 This flag is ignored when validating JTAG chain configuration.
11003 @deffn {Command} {verify_jtag} (@option{enable}|@option{disable})
11004 Enables verification of DR and IR scans, to help detect
11005 programming errors. For IR scans, @command{verify_ircapture}
11006 must also be enabled.
11007 Default is enabled.
11010 @section TAP state names
11011 @cindex TAP state names
11013 The @var{tap_state} names used by OpenOCD in the @command{drscan},
11014 @command{irscan}, and @command{pathmove} commands are the same
11015 as those used in SVF boundary scan documents, except that
11016 SVF uses @sc{idle} instead of @sc{run/idle}.
11019 @item @b{RESET} ... @emph{stable} (with TMS high);
11020 acts as if TRST were pulsed
11021 @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
11023 @item @b{DRCAPTURE}
11024 @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
11025 through the data register
11027 @item @b{DRPAUSE} ... @emph{stable}; data register ready
11028 for update or more shifting
11032 @item @b{IRCAPTURE}
11033 @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
11034 through the instruction register
11036 @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
11037 for update or more shifting
11042 Note that only six of those states are fully ``stable'' in the
11043 face of TMS fixed (low except for @sc{reset})
11044 and a free-running JTAG clock. For all the
11045 others, the next TCK transition changes to a new state.
11048 @item From @sc{drshift} and @sc{irshift}, clock transitions will
11049 produce side effects by changing register contents. The values
11050 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
11051 may not be as expected.
11052 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
11053 choices after @command{drscan} or @command{irscan} commands,
11054 since they are free of JTAG side effects.
11055 @item @sc{run/idle} may have side effects that appear at non-JTAG
11056 levels, such as advancing the ARM9E-S instruction pipeline.
11057 Consult the documentation for the TAP(s) you are working with.
11060 @node Boundary Scan Commands
11061 @chapter Boundary Scan Commands
11063 One of the original purposes of JTAG was to support
11064 boundary scan based hardware testing.
11065 Although its primary focus is to support On-Chip Debugging,
11066 OpenOCD also includes some boundary scan commands.
11068 @section SVF: Serial Vector Format
11069 @cindex Serial Vector Format
11072 The Serial Vector Format, better known as @dfn{SVF}, is a
11073 way to represent JTAG test patterns in text files.
11074 In a debug session using JTAG for its transport protocol,
11075 OpenOCD supports running such test files.
11077 @deffn {Command} {svf} @file{filename} [@option{-tap @var{tapname}}] [@option{[-]quiet}] @
11078 [@option{[-]nil}] [@option{[-]progress}] [@option{[-]ignore_error}]
11079 This issues a JTAG reset (Test-Logic-Reset) and then
11080 runs the SVF script from @file{filename}.
11082 Arguments can be specified in any order; the optional dash doesn't
11083 affect their semantics.
11087 @item @option{-tap @var{tapname}} ignore IR and DR headers and footers
11088 specified by the SVF file with HIR, TIR, HDR and TDR commands;
11089 instead, calculate them automatically according to the current JTAG
11090 chain configuration, targeting @var{tapname};
11091 @item @option{[-]quiet} do not log every command before execution;
11092 @item @option{[-]nil} ``dry run'', i.e., do not perform any operations
11093 on the real interface;
11094 @item @option{[-]progress} enable progress indication;
11095 @item @option{[-]ignore_error} continue execution despite TDO check
11100 @section XSVF: Xilinx Serial Vector Format
11101 @cindex Xilinx Serial Vector Format
11104 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
11105 binary representation of SVF which is optimized for use with
11107 In a debug session using JTAG for its transport protocol,
11108 OpenOCD supports running such test files.
11110 @quotation Important
11111 Not all XSVF commands are supported.
11114 @deffn {Command} {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
11115 This issues a JTAG reset (Test-Logic-Reset) and then
11116 runs the XSVF script from @file{filename}.
11117 When a @var{tapname} is specified, the commands are directed at
11119 When @option{virt2} is specified, the @sc{xruntest} command counts
11120 are interpreted as TCK cycles instead of microseconds.
11121 Unless the @option{quiet} option is specified,
11122 messages are logged for comments and some retries.
11125 The OpenOCD sources also include two utility scripts
11126 for working with XSVF; they are not currently installed
11127 after building the software.
11128 You may find them useful:
11131 @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
11132 syntax understood by the @command{xsvf} command; see notes below.
11133 @item @emph{xsvfdump} ... converts XSVF files into a text output format;
11134 understands the OpenOCD extensions.
11137 The input format accepts a handful of non-standard extensions.
11138 These include three opcodes corresponding to SVF extensions
11139 from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
11140 two opcodes supporting a more accurate translation of SVF
11141 (XTRST, XWAITSTATE).
11142 If @emph{xsvfdump} shows a file is using those opcodes, it
11143 probably will not be usable with other XSVF tools.
11146 @section IPDBG: JTAG-Host server
11147 @cindex IPDBG JTAG-Host server
11150 IPDBG is a set of tools to debug IP-Cores. It comprises, among others, a logic analyzer and an arbitrary
11151 waveform generator. These are synthesize-able hardware descriptions of
11152 logic circuits in addition to software for control, visualization and further analysis.
11153 In a session using JTAG for its transport protocol, OpenOCD supports the function
11154 of a JTAG-Host. The JTAG-Host is needed to connect the circuit over JTAG to the
11155 control-software. For more details see @url{http://ipdbg.org}.
11157 @deffn {Command} {ipdbg} [@option{-start|-stop}] @option{-tap @var{tapname}} @option{-hub @var{ir_value} [@var{dr_length}]} [@option{-port @var{number}}] [@option{-tool @var{number}}] [@option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]}]
11158 Starts or stops a IPDBG JTAG-Host server. Arguments can be specified in any order.
11162 @item @option{-start|-stop} starts or stops a IPDBG JTAG-Host server (default: start).
11163 @item @option{-tap @var{tapname}} targeting the TAP @var{tapname}.
11164 @item @option{-hub @var{ir_value}} states that the JTAG hub is
11165 reachable with dr-scans while the JTAG instruction register has the value @var{ir_value}.
11166 @item @option{-port @var{number}} tcp port number where the JTAG-Host is listening.
11167 @item @option{-tool @var{number}} number of the tool/feature. These corresponds to the ports "data_(up/down)_(0..6)" at the JtagHub.
11168 @item @option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]} On some devices, the user data-register is only reachable if there is a
11169 specific value in a second dr. This second dr is called vir (virtual ir). With this parameter given, the IPDBG satisfies this condition prior an
11170 access to the IPDBG-Hub. The value shifted into the vir is given by the first parameter @var{vir_value} (default: 0x11). The second
11171 parameter @var{length} is the length of the vir data register (default: 5). With the @var{instr_code} (default: 0x00e) parameter the ir value to
11172 shift data through vir can be configured.
11178 ipdbg -start -tap xc6s.tap -hub 0x02 -port 4242 -tool 4
11180 Starts a server listening on tcp-port 4242 which connects to tool 4.
11181 The connection is through the TAP of a Xilinx Spartan 6 on USER1 instruction (tested with a papillion pro board).
11184 ipdbg -start -tap 10m50.tap -hub 0x00C -vir -port 60000 -tool 1
11186 Starts a server listening on tcp-port 60000 which connects to tool 1 (data_up_1/data_down_1).
11187 The connection is through the TAP of a Intel MAX10 virtual jtag component (sld_instance_index is 0; sld_ir_width is smaller than 5).
11189 @node Utility Commands
11190 @chapter Utility Commands
11191 @cindex Utility Commands
11193 @section RAM testing
11194 @cindex RAM testing
11196 There is often a need to stress-test random access memory (RAM) for
11197 errors. OpenOCD comes with a Tcl implementation of well-known memory
11198 testing procedures allowing the detection of all sorts of issues with
11199 electrical wiring, defective chips, PCB layout and other common
11202 To use them, you usually need to initialise your RAM controller first;
11203 consult your SoC's documentation to get the recommended list of
11204 register operations and translate them to the corresponding
11205 @command{mww}/@command{mwb} commands.
11207 Load the memory testing functions with
11210 source [find tools/memtest.tcl]
11213 to get access to the following facilities:
11215 @deffn {Command} {memTestDataBus} address
11216 Test the data bus wiring in a memory region by performing a walking
11217 1's test at a fixed address within that region.
11220 @deffn {Command} {memTestAddressBus} baseaddress size
11221 Perform a walking 1's test on the relevant bits of the address and
11222 check for aliasing. This test will find single-bit address failures
11223 such as stuck-high, stuck-low, and shorted pins.
11226 @deffn {Command} {memTestDevice} baseaddress size
11227 Test the integrity of a physical memory device by performing an
11228 increment/decrement test over the entire region. In the process every
11229 storage bit in the device is tested as zero and as one.
11232 @deffn {Command} {runAllMemTests} baseaddress size
11233 Run all of the above tests over a specified memory region.
11236 @section Firmware recovery helpers
11237 @cindex Firmware recovery
11239 OpenOCD includes an easy-to-use script to facilitate mass-market
11240 devices recovery with JTAG.
11242 For quickstart instructions run:
11244 openocd -f tools/firmware-recovery.tcl -c firmware_help
11247 @node GDB and OpenOCD
11248 @chapter GDB and OpenOCD
11250 OpenOCD complies with the remote gdbserver protocol and, as such, can be used
11251 to debug remote targets.
11252 Setting up GDB to work with OpenOCD can involve several components:
11255 @item The OpenOCD server support for GDB may need to be configured.
11256 @xref{gdbconfiguration,,GDB Configuration}.
11257 @item GDB's support for OpenOCD may need configuration,
11258 as shown in this chapter.
11259 @item If you have a GUI environment like Eclipse,
11260 that also will probably need to be configured.
11263 Of course, the version of GDB you use will need to be one which has
11264 been built to know about the target CPU you're using. It's probably
11265 part of the tool chain you're using. For example, if you are doing
11266 cross-development for ARM on an x86 PC, instead of using the native
11267 x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
11268 if that's the tool chain used to compile your code.
11270 @section Connecting to GDB
11271 @cindex Connecting to GDB
11272 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
11273 instance GDB 6.3 has a known bug that produces bogus memory access
11274 errors, which has since been fixed; see
11275 @url{http://osdir.com/ml/gdb.bugs.discuss/2004-12/msg00018.html}
11277 OpenOCD can communicate with GDB in two ways:
11281 A socket (TCP/IP) connection is typically started as follows:
11283 target extended-remote localhost:3333
11285 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
11287 The extended remote protocol is a super-set of the remote protocol and should
11288 be the preferred choice. More details are available in GDB documentation
11289 @url{https://sourceware.org/gdb/onlinedocs/gdb/Connecting.html}
11291 To speed-up typing, any GDB command can be abbreviated, including the extended
11292 remote command above that becomes:
11297 @b{Note:} If any backward compatibility issue requires using the old remote
11298 protocol in place of the extended remote one, the former protocol is still
11299 available through the command:
11301 target remote localhost:3333
11305 A pipe connection is typically started as follows:
11307 target extended-remote | \
11308 openocd -c "gdb_port pipe; log_output openocd.log"
11310 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
11311 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
11312 session. log_output sends the log output to a file to ensure that the pipe is
11313 not saturated when using higher debug level outputs.
11316 To list the available OpenOCD commands type @command{monitor help} on the
11319 @section Sample GDB session startup
11321 With the remote protocol, GDB sessions start a little differently
11322 than they do when you're debugging locally.
11323 Here's an example showing how to start a debug session with a
11325 In this case the program was linked to be loaded into SRAM on a Cortex-M3.
11326 Most programs would be written into flash (address 0) and run from there.
11329 $ arm-none-eabi-gdb example.elf
11330 (gdb) target extended-remote localhost:3333
11331 Remote debugging using localhost:3333
11333 (gdb) monitor reset halt
11336 Loading section .vectors, size 0x100 lma 0x20000000
11337 Loading section .text, size 0x5a0 lma 0x20000100
11338 Loading section .data, size 0x18 lma 0x200006a0
11339 Start address 0x2000061c, load size 1720
11340 Transfer rate: 22 KB/sec, 573 bytes/write.
11346 You could then interrupt the GDB session to make the program break,
11347 type @command{where} to show the stack, @command{list} to show the
11348 code around the program counter, @command{step} through code,
11349 set breakpoints or watchpoints, and so on.
11351 @section Configuring GDB for OpenOCD
11353 OpenOCD supports the gdb @option{qSupported} packet, this enables information
11354 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
11355 packet size and the device's memory map.
11356 You do not need to configure the packet size by hand,
11357 and the relevant parts of the memory map should be automatically
11358 set up when you declare (NOR) flash banks.
11360 However, there are other things which GDB can't currently query.
11361 You may need to set those up by hand.
11362 As OpenOCD starts up, you will often see a line reporting
11366 Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
11369 You can pass that information to GDB with these commands:
11372 set remote hardware-breakpoint-limit 6
11373 set remote hardware-watchpoint-limit 4
11376 With that particular hardware (Cortex-M3) the hardware breakpoints
11377 only work for code running from flash memory. Most other ARM systems
11378 do not have such restrictions.
11380 Rather than typing such commands interactively, you may prefer to
11381 save them in a file and have GDB execute them as it starts, perhaps
11382 using a @file{.gdbinit} in your project directory or starting GDB
11383 using @command{gdb -x filename}.
11385 @section Programming using GDB
11386 @cindex Programming using GDB
11387 @anchor{programmingusinggdb}
11389 By default the target memory map is sent to GDB. This can be disabled by
11390 the following OpenOCD configuration option:
11392 gdb_memory_map disable
11394 For this to function correctly a valid flash configuration must also be set
11395 in OpenOCD. For faster performance you should also configure a valid
11398 Informing GDB of the memory map of the target will enable GDB to protect any
11399 flash areas of the target and use hardware breakpoints by default. This means
11400 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
11401 using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}.
11403 To view the configured memory map in GDB, use the GDB command @option{info mem}.
11404 All other unassigned addresses within GDB are treated as RAM.
11406 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
11407 This can be changed to the old behaviour by using the following GDB command
11409 set mem inaccessible-by-default off
11412 If @command{gdb_flash_program enable} is also used, GDB will be able to
11413 program any flash memory using the vFlash interface.
11415 GDB will look at the target memory map when a load command is given, if any
11416 areas to be programmed lie within the target flash area the vFlash packets
11419 If the target needs configuring before GDB programming, set target
11420 event gdb-flash-erase-start:
11422 $_TARGETNAME configure -event gdb-flash-erase-start BODY
11424 @xref{targetevents,,Target Events}, for other GDB programming related events.
11426 To verify any flash programming the GDB command @option{compare-sections}
11429 @section Using GDB as a non-intrusive memory inspector
11430 @cindex Using GDB as a non-intrusive memory inspector
11431 @anchor{gdbmeminspect}
11433 If your project controls more than a blinking LED, let's say a heavy industrial
11434 robot or an experimental nuclear reactor, stopping the controlling process
11435 just because you want to attach GDB is not a good option.
11437 OpenOCD does not support GDB non-stop mode (might be implemented in the future).
11438 Though there is a possible setup where the target does not get stopped
11439 and GDB treats it as it were running.
11440 If the target supports background access to memory while it is running,
11441 you can use GDB in this mode to inspect memory (mainly global variables)
11442 without any intrusion of the target process.
11444 Remove default setting of gdb-attach event. @xref{targetevents,,Target Events}.
11445 Place following command after target configuration:
11447 $_TARGETNAME configure -event gdb-attach @{@}
11450 If any of installed flash banks does not support probe on running target,
11451 switch off gdb_memory_map:
11453 gdb_memory_map disable
11456 Ensure GDB is configured without interrupt-on-connect.
11457 Some GDB versions set it by default, some does not.
11459 set remote interrupt-on-connect off
11462 If you switched gdb_memory_map off, you may want to setup GDB memory map
11463 manually or issue @command{set mem inaccessible-by-default off}
11465 Now you can issue GDB command @command{target extended-remote ...} and inspect memory
11466 of a running target. Do not use GDB commands @command{continue},
11467 @command{step} or @command{next} as they synchronize GDB with your target
11468 and GDB would require stopping the target to get the prompt back.
11470 Do not use this mode under an IDE like Eclipse as it caches values of
11471 previously shown variables.
11473 It's also possible to connect more than one GDB to the same target by the
11474 target's configuration option @code{-gdb-max-connections}. This allows, for
11475 example, one GDB to run a script that continuously polls a set of variables
11476 while other GDB can be used interactively. Be extremely careful in this case,
11477 because the two GDB can easily get out-of-sync.
11479 @section RTOS Support
11480 @cindex RTOS Support
11481 @anchor{gdbrtossupport}
11483 OpenOCD includes RTOS support, this will however need enabling as it defaults to disabled.
11484 It can be enabled by passing @option{-rtos} arg to the target. @xref{rtostype,,RTOS Type}.
11486 @xref{Threads, Debugging Programs with Multiple Threads,
11487 Debugging Programs with Multiple Threads, gdb, GDB manual}, for details about relevant
11490 @* An example setup is below:
11493 $_TARGETNAME configure -rtos auto
11496 This will attempt to auto detect the RTOS within your application.
11498 Currently supported rtos's include:
11500 @item @option{eCos}
11501 @item @option{ThreadX}
11502 @item @option{FreeRTOS}
11503 @item @option{linux}
11504 @item @option{ChibiOS}
11505 @item @option{embKernel}
11507 @item @option{uCOS-III}
11508 @item @option{nuttx}
11509 @item @option{RIOT}
11510 @item @option{hwthread} (This is not an actual RTOS. @xref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.)
11511 @item @option{Zephyr}
11514 Before an RTOS can be detected, it must export certain symbols; otherwise, it cannot
11515 be used by OpenOCD. Below is a list of the required symbols for each supported RTOS.
11519 Cyg_Thread::thread_list, Cyg_Scheduler_Base::current_thread.
11520 @item ThreadX symbols
11521 _tx_thread_current_ptr, _tx_thread_created_ptr, _tx_thread_created_count.
11522 @item FreeRTOS symbols
11524 pxCurrentTCB, pxReadyTasksLists, xDelayedTaskList1, xDelayedTaskList2,
11525 pxDelayedTaskList, pxOverflowDelayedTaskList, xPendingReadyList,
11526 uxCurrentNumberOfTasks, uxTopUsedPriority.
11528 @item linux symbols
11530 @item ChibiOS symbols
11531 rlist, ch_debug, chSysInit.
11532 @item embKernel symbols
11533 Rtos::sCurrentTask, Rtos::sListReady, Rtos::sListSleep,
11534 Rtos::sListSuspended, Rtos::sMaxPriorities, Rtos::sCurrentTaskCount.
11536 _mqx_kernel_data, MQX_init_struct.
11537 @item uC/OS-III symbols
11538 OSRunning, OSTCBCurPtr, OSTaskDbgListPtr, OSTaskQty.
11539 @item nuttx symbols
11540 g_readytorun, g_tasklisttable.
11543 sched_threads, sched_num_threads, sched_active_pid, max_threads,
11546 @item Zephyr symbols
11547 _kernel, _kernel_openocd_offsets, _kernel_openocd_size_t_size
11550 For most RTOS supported the above symbols will be exported by default. However for
11551 some, eg. FreeRTOS, uC/OS-III and Zephyr, extra steps must be taken.
11553 Zephyr must be compiled with the DEBUG_THREAD_INFO option. This will generate some symbols
11554 with information needed in order to build the list of threads.
11556 FreeRTOS and uC/OS-III RTOSes may require additional OpenOCD-specific file to be linked
11557 along with the project:
11561 contrib/rtos-helpers/FreeRTOS-openocd.c
11563 contrib/rtos-helpers/uCOS-III-openocd.c
11566 @anchor{usingopenocdsmpwithgdb}
11567 @section Using OpenOCD SMP with GDB
11571 OpenOCD includes a pseudo RTOS called @emph{hwthread} that presents CPU cores
11572 ("hardware threads") in an SMP system as threads to GDB. With this extension,
11573 GDB can be used to inspect the state of an SMP system in a natural way.
11574 After halting the system, using the GDB command @command{info threads} will
11575 list the context of each active CPU core in the system. GDB's @command{thread}
11576 command can be used to switch the view to a different CPU core.
11577 The @command{step} and @command{stepi} commands can be used to step a specific core
11578 while other cores are free-running or remain halted, depending on the
11579 scheduler-locking mode configured in GDB.
11581 @node Tcl Scripting API
11582 @chapter Tcl Scripting API
11583 @cindex Tcl Scripting API
11584 @cindex Tcl scripts
11587 Tcl commands are stateless; e.g. the @command{telnet} command has
11588 a concept of currently active target, the Tcl API proc's take this sort
11589 of state information as an argument to each proc.
11591 There are three main types of return values: single value, name value
11592 pair list and lists.
11594 Name value pair. The proc 'foo' below returns a name/value pair
11598 > set foo(me) Duane
11599 > set foo(you) Oyvind
11600 > set foo(mouse) Micky
11601 > set foo(duck) Donald
11613 me Duane you Oyvind mouse Micky duck Donald
11616 Thus, to get the names of the associative array is easy:
11619 foreach { name value } [set foo] {
11620 puts "Name: $name, Value: $value"
11624 Lists returned should be relatively small. Otherwise, a range
11625 should be passed in to the proc in question.
11627 @section Internal low-level Commands
11629 By "low-level", we mean commands that a human would typically not
11633 @item @b{flash banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
11635 Return information about the flash banks
11637 @item @b{capture} <@var{command}>
11639 Run <@var{command}> and return full log output that was produced during
11640 its execution. Example:
11643 > capture "reset init"
11648 OpenOCD commands can consist of two words, e.g. "flash banks". The
11649 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
11650 called "flash_banks".
11652 @section Tcl RPC server
11655 OpenOCD provides a simple RPC server that allows to run arbitrary Tcl
11656 commands and receive the results.
11658 To access it, your application needs to connect to a configured TCP port
11659 (see @command{tcl_port}). Then it can pass any string to the
11660 interpreter terminating it with @code{0x1a} and wait for the return
11661 value (it will be terminated with @code{0x1a} as well). This can be
11662 repeated as many times as desired without reopening the connection.
11664 It is not needed anymore to prefix the OpenOCD commands with
11665 @code{ocd_} to get the results back. But sometimes you might need the
11666 @command{capture} command.
11668 See @file{contrib/rpc_examples/} for specific client implementations.
11670 @section Tcl RPC server notifications
11671 @cindex RPC Notifications
11673 Notifications are sent asynchronously to other commands being executed over
11674 the RPC server, so the port must be polled continuously.
11676 Target event, state and reset notifications are emitted as Tcl associative arrays
11677 in the following format.
11680 type target_event event [event-name]
11681 type target_state state [state-name]
11682 type target_reset mode [reset-mode]
11685 @deffn {Command} {tcl_notifications} [on/off]
11686 Toggle output of target notifications to the current Tcl RPC server.
11687 Only available from the Tcl RPC server.
11692 @section Tcl RPC server trace output
11693 @cindex RPC trace output
11695 Trace data is sent asynchronously to other commands being executed over
11696 the RPC server, so the port must be polled continuously.
11698 Target trace data is emitted as a Tcl associative array in the following format.
11701 type target_trace data [trace-data-hex-encoded]
11704 @deffn {Command} {tcl_trace} [on/off]
11705 Toggle output of target trace data to the current Tcl RPC server.
11706 Only available from the Tcl RPC server.
11709 See an example application here:
11710 @url{https://github.com/apmorton/OpenOcdTraceUtil} [OpenOcdTraceUtil]
11719 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
11721 @cindex adaptive clocking
11724 In digital circuit design it is often referred to as ``clock
11725 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
11726 operating at some speed, your CPU target is operating at another.
11727 The two clocks are not synchronised, they are ``asynchronous''
11729 In order for the two to work together they must be synchronised
11730 well enough to work; JTAG can't go ten times faster than the CPU,
11731 for example. There are 2 basic options:
11734 Use a special "adaptive clocking" circuit to change the JTAG
11735 clock rate to match what the CPU currently supports.
11737 The JTAG clock must be fixed at some speed that's enough slower than
11738 the CPU clock that all TMS and TDI transitions can be detected.
11741 @b{Does this really matter?} For some chips and some situations, this
11742 is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
11743 the CPU has no difficulty keeping up with JTAG.
11744 Startup sequences are often problematic though, as are other
11745 situations where the CPU clock rate changes (perhaps to save
11748 For example, Atmel AT91SAM chips start operation from reset with
11749 a 32kHz system clock. Boot firmware may activate the main oscillator
11750 and PLL before switching to a faster clock (perhaps that 500 MHz
11752 If you're using JTAG to debug that startup sequence, you must slow
11753 the JTAG clock to sometimes 1 to 4kHz. After startup completes,
11754 JTAG can use a faster clock.
11756 Consider also debugging a 500MHz ARM926 hand held battery powered
11757 device that enters a low power ``deep sleep'' mode, at 32kHz CPU
11758 clock, between keystrokes unless it has work to do. When would
11759 that 5 MHz JTAG clock be usable?
11761 @b{Solution #1 - A special circuit}
11763 In order to make use of this,
11764 your CPU, board, and JTAG adapter must all support the RTCK
11765 feature. Not all of them support this; keep reading!
11767 The RTCK ("Return TCK") signal in some ARM chips is used to help with
11768 this problem. ARM has a good description of the problem described at
11769 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
11770 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
11771 work? / how does adaptive clocking work?''.
11773 The nice thing about adaptive clocking is that ``battery powered hand
11774 held device example'' - the adaptiveness works perfectly all the
11775 time. One can set a break point or halt the system in the deep power
11776 down code, slow step out until the system speeds up.
11778 Note that adaptive clocking may also need to work at the board level,
11779 when a board-level scan chain has multiple chips.
11780 Parallel clock voting schemes are good way to implement this,
11781 both within and between chips, and can easily be implemented
11783 It's not difficult to have logic fan a module's input TCK signal out
11784 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
11785 back with the right polarity before changing the output RTCK signal.
11786 Texas Instruments makes some clock voting logic available
11787 for free (with no support) in VHDL form; see
11788 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
11790 @b{Solution #2 - Always works - but may be slower}
11792 Often this is a perfectly acceptable solution.
11794 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
11795 the target clock speed. But what that ``magic division'' is varies
11796 depending on the chips on your board.
11797 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
11798 ARM11 cores use an 8:1 division.
11799 @b{Xilinx rule of thumb} is 1/12 the clock speed.
11801 Note: most full speed FT2232 based JTAG adapters are limited to a
11802 maximum of 6MHz. The ones using USB high speed chips (FT2232H)
11803 often support faster clock rates (and adaptive clocking).
11805 You can still debug the 'low power' situations - you just need to
11806 either use a fixed and very slow JTAG clock rate ... or else
11807 manually adjust the clock speed at every step. (Adjusting is painful
11808 and tedious, and is not always practical.)
11810 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
11811 have a special debug mode in your application that does a ``high power
11812 sleep''. If you are careful - 98% of your problems can be debugged
11815 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
11816 operation in your idle loops even if you don't otherwise change the CPU
11818 That operation gates the CPU clock, and thus the JTAG clock; which
11819 prevents JTAG access. One consequence is not being able to @command{halt}
11820 cores which are executing that @emph{wait for interrupt} operation.
11822 To set the JTAG frequency use the command:
11825 # Example: 1.234MHz
11830 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
11832 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
11833 around Windows filenames.
11846 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
11848 Make sure you have Cygwin installed, or at least a version of OpenOCD that
11849 claims to come with all the necessary DLLs. When using Cygwin, try launching
11850 OpenOCD from the Cygwin shell.
11852 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a front-end like Insight or
11853 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
11854 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
11856 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
11857 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
11858 software breakpoints consume one of the two available hardware breakpoints.
11860 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
11862 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
11863 clock at the time you're programming the flash. If you've specified the crystal's
11864 frequency, make sure the PLL is disabled. If you've specified the full core speed
11865 (e.g. 60MHz), make sure the PLL is enabled.
11867 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
11868 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
11869 out while waiting for end of scan, rtck was disabled".
11871 Make sure your PC's parallel port operates in EPP mode. You might have to try several
11872 settings in your PC BIOS (ECP, EPP, and different versions of those).
11874 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
11875 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
11876 memory read caused data abort".
11878 The errors are non-fatal, and are the result of GDB trying to trace stack frames
11879 beyond the last valid frame. It might be possible to prevent this by setting up
11880 a proper "initial" stack frame, if you happen to know what exactly has to
11881 be done, feel free to add this here.
11883 @b{Simple:} In your startup code - push 8 registers of zeros onto the
11884 stack before calling main(). What GDB is doing is ``climbing'' the run
11885 time stack by reading various values on the stack using the standard
11886 call frame for the target. GDB keeps going - until one of 2 things
11887 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
11888 stackframes have been processed. By pushing zeros on the stack, GDB
11891 @b{Debugging Interrupt Service Routines} - In your ISR before you call
11892 your C code, do the same - artificially push some zeros onto the stack,
11893 remember to pop them off when the ISR is done.
11895 @b{Also note:} If you have a multi-threaded operating system, they
11896 often do not @b{in the interest of saving memory} waste these few
11900 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
11901 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
11903 This warning doesn't indicate any serious problem, as long as you don't want to
11904 debug your core right out of reset. Your .cfg file specified @option{reset_config
11905 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
11906 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
11907 independently. With this setup, it's not possible to halt the core right out of
11908 reset, everything else should work fine.
11910 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
11911 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
11912 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
11913 quit with an error message. Is there a stability issue with OpenOCD?
11915 No, this is not a stability issue concerning OpenOCD. Most users have solved
11916 this issue by simply using a self-powered USB hub, which they connect their
11917 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
11918 supply stable enough for the Amontec JTAGkey to be operated.
11920 @b{Laptops running on battery have this problem too...}
11922 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
11923 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
11924 What does that mean and what might be the reason for this?
11926 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
11927 has closed the connection to OpenOCD. This might be a GDB issue.
11929 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
11930 are described, there is a parameter for specifying the clock frequency
11931 for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
11932 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
11933 specified in kilohertz. However, I do have a quartz crystal of a
11934 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
11935 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
11938 No. The clock frequency specified here must be given as an integral number.
11939 However, this clock frequency is used by the In-Application-Programming (IAP)
11940 routines of the LPC2000 family only, which seems to be very tolerant concerning
11941 the given clock frequency, so a slight difference between the specified clock
11942 frequency and the actual clock frequency will not cause any trouble.
11944 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
11946 Well, yes and no. Commands can be given in arbitrary order, yet the
11947 devices listed for the JTAG scan chain must be given in the right
11948 order (jtag newdevice), with the device closest to the TDO-Pin being
11949 listed first. In general, whenever objects of the same type exist
11950 which require an index number, then these objects must be given in the
11951 right order (jtag newtap, targets and flash banks - a target
11952 references a jtag newtap and a flash bank references a target).
11954 You can use the ``scan_chain'' command to verify and display the tap order.
11956 Also, some commands can't execute until after @command{init} has been
11957 processed. Such commands include @command{nand probe} and everything
11958 else that needs to write to controller registers, perhaps for setting
11959 up DRAM and loading it with code.
11961 @anchor{faqtaporder}
11962 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
11965 Yes; whenever you have more than one, you must declare them in
11966 the same order used by the hardware.
11968 Many newer devices have multiple JTAG TAPs. For example:
11969 STMicroelectronics STM32 chips have two TAPs, a ``boundary scan TAP'' and
11970 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
11971 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
11972 connected to the boundary scan TAP, which then connects to the
11973 Cortex-M3 TAP, which then connects to the TDO pin.
11975 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
11976 (2) The boundary scan TAP. If your board includes an additional JTAG
11977 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
11978 place it before or after the STM32 chip in the chain. For example:
11981 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
11982 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
11983 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
11984 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
11985 @item Xilinx TDO Pin -> OpenOCD TDO (input)
11988 The ``jtag device'' commands would thus be in the order shown below. Note:
11991 @item jtag newtap Xilinx tap -irlen ...
11992 @item jtag newtap stm32 cpu -irlen ...
11993 @item jtag newtap stm32 bs -irlen ...
11994 @item # Create the debug target and say where it is
11995 @item target create stm32.cpu -chain-position stm32.cpu ...
11999 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
12000 log file, I can see these error messages: Error: arm7_9_common.c:561
12001 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
12007 @node Tcl Crash Course
12008 @chapter Tcl Crash Course
12011 Not everyone knows Tcl - this is not intended to be a replacement for
12012 learning Tcl, the intent of this chapter is to give you some idea of
12013 how the Tcl scripts work.
12015 This chapter is written with two audiences in mind. (1) OpenOCD users
12016 who need to understand a bit more of how Jim-Tcl works so they can do
12017 something useful, and (2) those that want to add a new command to
12020 @section Tcl Rule #1
12021 There is a famous joke, it goes like this:
12023 @item Rule #1: The wife is always correct
12024 @item Rule #2: If you think otherwise, See Rule #1
12027 The Tcl equal is this:
12030 @item Rule #1: Everything is a string
12031 @item Rule #2: If you think otherwise, See Rule #1
12034 As in the famous joke, the consequences of Rule #1 are profound. Once
12035 you understand Rule #1, you will understand Tcl.
12037 @section Tcl Rule #1b
12038 There is a second pair of rules.
12040 @item Rule #1: Control flow does not exist. Only commands
12041 @* For example: the classic FOR loop or IF statement is not a control
12042 flow item, they are commands, there is no such thing as control flow
12044 @item Rule #2: If you think otherwise, See Rule #1
12045 @* Actually what happens is this: There are commands that by
12046 convention, act like control flow key words in other languages. One of
12047 those commands is the word ``for'', another command is ``if''.
12050 @section Per Rule #1 - All Results are strings
12051 Every Tcl command results in a string. The word ``result'' is used
12052 deliberately. No result is just an empty string. Remember: @i{Rule #1 -
12053 Everything is a string}
12055 @section Tcl Quoting Operators
12056 In life of a Tcl script, there are two important periods of time, the
12057 difference is subtle.
12060 @item Evaluation Time
12063 The two key items here are how ``quoted things'' work in Tcl. Tcl has
12064 three primary quoting constructs, the [square-brackets] the
12065 @{curly-braces@} and ``double-quotes''
12067 By now you should know $VARIABLES always start with a $DOLLAR
12068 sign. BTW: To set a variable, you actually use the command ``set'', as
12069 in ``set VARNAME VALUE'' much like the ancient BASIC language ``let x
12070 = 1'' statement, but without the equal sign.
12073 @item @b{[square-brackets]}
12074 @* @b{[square-brackets]} are command substitutions. It operates much
12075 like Unix Shell `back-ticks`. The result of a [square-bracket]
12076 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
12077 string}. These two statements are roughly identical:
12081 echo "The Date is: $X"
12084 puts "The Date is: $X"
12086 @item @b{``double-quoted-things''}
12087 @* @b{``double-quoted-things''} are just simply quoted
12088 text. $VARIABLES and [square-brackets] are expanded in place - the
12089 result however is exactly 1 string. @i{Remember Rule #1 - Everything
12093 puts "It is now \"[date]\", $x is in 1 hour"
12095 @item @b{@{Curly-Braces@}}
12096 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
12097 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
12098 'single-quote' operators in BASH shell scripts, with the added
12099 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
12100 nested 3 times@}@}@} NOTE: [date] is a bad example;
12101 at this writing, Jim/OpenOCD does not have a date command.
12104 @section Consequences of Rule 1/2/3/4
12106 The consequences of Rule 1 are profound.
12108 @subsection Tokenisation & Execution.
12110 Of course, whitespace, blank lines and #comment lines are handled in
12113 As a script is parsed, each (multi) line in the script file is
12114 tokenised and according to the quoting rules. After tokenisation, that
12115 line is immediately executed.
12117 Multi line statements end with one or more ``still-open''
12118 @{curly-braces@} which - eventually - closes a few lines later.
12120 @subsection Command Execution
12122 Remember earlier: There are no ``control flow''
12123 statements in Tcl. Instead there are COMMANDS that simply act like
12124 control flow operators.
12126 Commands are executed like this:
12129 @item Parse the next line into (argc) and (argv[]).
12130 @item Look up (argv[0]) in a table and call its function.
12131 @item Repeat until End Of File.
12134 It sort of works like this:
12137 ReadAndParse( &argc, &argv );
12139 cmdPtr = LookupCommand( argv[0] );
12141 (*cmdPtr->Execute)( argc, argv );
12145 When the command ``proc'' is parsed (which creates a procedure
12146 function) it gets 3 parameters on the command line. @b{1} the name of
12147 the proc (function), @b{2} the list of parameters, and @b{3} the body
12148 of the function. Note the choice of words: LIST and BODY. The PROC
12149 command stores these items in a table somewhere so it can be found by
12150 ``LookupCommand()''
12152 @subsection The FOR command
12154 The most interesting command to look at is the FOR command. In Tcl,
12155 the FOR command is normally implemented in C. Remember, FOR is a
12156 command just like any other command.
12158 When the ascii text containing the FOR command is parsed, the parser
12159 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
12163 @item The ascii text 'for'
12164 @item The start text
12165 @item The test expression
12166 @item The next text
12167 @item The body text
12170 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
12171 Remember @i{Rule #1 - Everything is a string.} The key point is this:
12172 Often many of those parameters are in @{curly-braces@} - thus the
12173 variables inside are not expanded or replaced until later.
12175 Remember that every Tcl command looks like the classic ``main( argc,
12176 argv )'' function in C. In JimTCL - they actually look like this:
12180 MyCommand( Jim_Interp *interp,
12182 Jim_Obj * const *argvs );
12185 Real Tcl is nearly identical. Although the newer versions have
12186 introduced a byte-code parser and interpreter, but at the core, it
12187 still operates in the same basic way.
12189 @subsection FOR command implementation
12191 To understand Tcl it is perhaps most helpful to see the FOR
12192 command. Remember, it is a COMMAND not a control flow structure.
12194 In Tcl there are two underlying C helper functions.
12196 Remember Rule #1 - You are a string.
12198 The @b{first} helper parses and executes commands found in an ascii
12199 string. Commands can be separated by semicolons, or newlines. While
12200 parsing, variables are expanded via the quoting rules.
12202 The @b{second} helper evaluates an ascii string as a numerical
12203 expression and returns a value.
12205 Here is an example of how the @b{FOR} command could be
12206 implemented. The pseudo code below does not show error handling.
12208 void Execute_AsciiString( void *interp, const char *string );
12210 int Evaluate_AsciiExpression( void *interp, const char *string );
12213 MyForCommand( void *interp,
12218 SetResult( interp, "WRONG number of parameters");
12222 // argv[0] = the ascii string just like C
12224 // Execute the start statement.
12225 Execute_AsciiString( interp, argv[1] );
12227 // Top of loop test
12229 i = Evaluate_AsciiExpression(interp, argv[2]);
12233 // Execute the body
12234 Execute_AsciiString( interp, argv[3] );
12236 // Execute the LOOP part
12237 Execute_AsciiString( interp, argv[4] );
12241 SetResult( interp, "" );
12246 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
12247 in the same basic way.
12249 @section OpenOCD Tcl Usage
12251 @subsection source and find commands
12252 @b{Where:} In many configuration files
12253 @* Example: @b{ source [find FILENAME] }
12254 @*Remember the parsing rules
12256 @item The @command{find} command is in square brackets,
12257 and is executed with the parameter FILENAME. It should find and return
12258 the full path to a file with that name; it uses an internal search path.
12259 The RESULT is a string, which is substituted into the command line in
12260 place of the bracketed @command{find} command.
12261 (Don't try to use a FILENAME which includes the "#" character.
12262 That character begins Tcl comments.)
12263 @item The @command{source} command is executed with the resulting filename;
12264 it reads a file and executes as a script.
12266 @subsection format command
12267 @b{Where:} Generally occurs in numerous places.
12268 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
12274 puts [format "The answer: %d" [expr @{$x * $y@}]]
12277 @item The SET command creates 2 variables, X and Y.
12278 @item The double [nested] EXPR command performs math
12279 @* The EXPR command produces numerical result as a string.
12280 @* Refer to Rule #1
12281 @item The format command is executed, producing a single string
12282 @* Refer to Rule #1.
12283 @item The PUTS command outputs the text.
12285 @subsection Body or Inlined Text
12286 @b{Where:} Various TARGET scripts.
12289 proc someproc @{@} @{
12290 ... multiple lines of stuff ...
12292 $_TARGETNAME configure -event FOO someproc
12293 #2 Good - no variables
12294 $_TARGETNAME configure -event foo "this ; that;"
12295 #3 Good Curly Braces
12296 $_TARGETNAME configure -event FOO @{
12297 puts "Time: [date]"
12299 #4 DANGER DANGER DANGER
12300 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
12303 @item The $_TARGETNAME is an OpenOCD variable convention.
12304 @*@b{$_TARGETNAME} represents the last target created, the value changes
12305 each time a new target is created. Remember the parsing rules. When
12306 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
12307 the name of the target which happens to be a TARGET (object)
12309 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
12310 @*There are 4 examples:
12312 @item The TCLBODY is a simple string that happens to be a proc name
12313 @item The TCLBODY is several simple commands separated by semicolons
12314 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
12315 @item The TCLBODY is a string with variables that get expanded.
12318 In the end, when the target event FOO occurs the TCLBODY is
12319 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
12320 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
12322 Remember the parsing rules. In case #3, @{curly-braces@} mean the
12323 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
12324 and the text is evaluated. In case #4, they are replaced before the
12325 ``Target Object Command'' is executed. This occurs at the same time
12326 $_TARGETNAME is replaced. In case #4 the date will never
12327 change. @{BTW: [date] is a bad example; at this writing,
12328 Jim/OpenOCD does not have a date command@}
12330 @subsection Global Variables
12331 @b{Where:} You might discover this when writing your own procs @* In
12332 simple terms: Inside a PROC, if you need to access a global variable
12333 you must say so. See also ``upvar''. Example:
12335 proc myproc @{ @} @{
12336 set y 0 #Local variable Y
12337 global x #Global variable X
12338 puts [format "X=%d, Y=%d" $x $y]
12341 @section Other Tcl Hacks
12342 @b{Dynamic variable creation}
12344 # Dynamically create a bunch of variables.
12345 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr @{$x + 1@}]@} @{
12347 set vn [format "BIT%d" $x]
12351 set $vn [expr @{1 << $x@}]
12354 @b{Dynamic proc/command creation}
12356 # One "X" function - 5 uart functions.
12357 foreach who @{A B C D E@}
12358 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
12363 @appendix The GNU Free Documentation License.
12366 @node OpenOCD Concept Index
12367 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
12368 @comment case issue with ``Index.html'' and ``index.html''
12369 @comment Occurs when creating ``--html --no-split'' output
12370 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
12371 @unnumbered OpenOCD Concept Index
12375 @node Command and Driver Index
12376 @unnumbered Command and Driver Index