1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
29 Permission is granted to copy, distribute and/or modify this document
30 under the terms of the GNU Free Documentation License, Version 1.2 or
31 any later version published by the Free Software Foundation; with no
32 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
33 Texts. A copy of the license is included in the section entitled ``GNU
34 Free Documentation License''.
39 @titlefont{@emph{Open On-Chip Debugger:}}
41 @title OpenOCD User's Guide
42 @subtitle for release @value{VERSION}
43 @subtitle @value{UPDATED}
46 @vskip 0pt plus 1filll
55 @top OpenOCD User's Guide
61 * About:: About OpenOCD
62 * Developers:: OpenOCD Developers
63 * Building OpenOCD:: Building OpenOCD From SVN
64 * JTAG Hardware Dongles:: JTAG Hardware Dongles
65 * Running:: Running OpenOCD
66 * Simple Configuration Files:: Simple Configuration Files
67 * Config File Guidelines:: Config File Guidelines
68 * About JIM-Tcl:: About JIM-Tcl
69 * Daemon Configuration:: Daemon Configuration
70 * Interface - Dongle Configuration:: Interface - Dongle Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * General Commands:: General Commands
77 * Architecture and Core Commands:: Architecture and Core Commands
78 * JTAG Commands:: JTAG Commands
79 * Sample Scripts:: Sample Target Scripts
81 * GDB and OpenOCD:: Using GDB and OpenOCD
82 * Tcl Scripting API:: Tcl Scripting API
83 * Upgrading:: Deprecated/Removed Commands
84 * Target Library:: Target Library
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
101 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
102 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
107 @section What is OpenOCD?
109 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
110 in-system programming and boundary-scan testing for embedded target
113 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
114 with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
115 A @dfn{TAP} is a ``Test Access Port'', a module which processes
116 special instructions and data. TAPs are daisy-chained within and
117 between chips and boards.
119 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
120 based, parallel port based, and other standalone boxes that run
121 OpenOCD internally. @xref{JTAG Hardware Dongles}.
123 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
124 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
125 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
126 debugged via the GDB protocol.
128 @b{Flash Programing:} Flash writing is supported for external CFI
129 compatible NOR flashes (Intel and AMD/Spansion command set) and several
130 internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3, and
131 STM32x). Preliminary support for various NAND flash controllers
132 (LPC3180, Orion, S3C24xx, more) controller is included.
134 @section OpenOCD Web Site
136 The OpenOCD web site provides the latest public news from the community:
138 @uref{http://openocd.berlios.de/web/}
140 @section Latest User's Guide:
142 The user's guide you are now reading may not be the latest one
143 available. A version for more recent code may be available.
144 Its HTML form is published irregularly at:
146 @uref{http://openocd.berlios.de/doc/}
148 PDF form is likewise published at:
150 @uref{http://openocd.berlios.de/doc/pdf/}
152 @section OpenOCD User's Forum
154 There is an OpenOCD forum (phpBB) hosted by SparkFun:
156 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
160 @chapter OpenOCD Developer Resources
163 If you are interested in improving the state of OpenOCD's debugging and
164 testing support, new contributions will be welcome. Motivated developers
165 can produce new target, flash or interface drivers, improve the
166 documentation, as well as more conventional bug fixes and enhancements.
168 The resources in this chapter are available for developers wishing to explore
169 or expand the OpenOCD source code.
171 @section OpenOCD Subversion Repository
173 The ``Building From Source'' section provides instructions to retrieve
174 and and build the latest version of the OpenOCD source code.
175 @xref{Building OpenOCD}.
177 Developers that want to contribute patches to the OpenOCD system are
178 @b{strongly} encouraged to base their work off of the most recent trunk
179 revision. Patches created against older versions may require additional
180 work from their submitter in order to be updated for newer releases.
182 @section Doxygen Developer Manual
184 During the development of the 0.2.0 release, the OpenOCD project began
185 providing a Doxygen reference manual. This document contains more
186 technical information about the software internals, development
187 processes, and similar documentation:
189 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
191 This document is a work-in-progress, but contributions would be welcome
192 to fill in the gaps. All of the source files are provided in-tree,
193 listed in the Doxyfile configuration in the top of the repository trunk.
195 @section OpenOCD Developer Mailing List
197 The OpenOCD Developer Mailing List provides the primary means of
198 communication between developers:
200 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
202 All drivers developers are enouraged to also subscribe to the list of
203 SVN commits to keep pace with the ongoing changes:
205 @uref{https://lists.berlios.de/mailman/listinfo/openocd-svn}
208 @node Building OpenOCD
209 @chapter Building OpenOCD
212 @section Pre-Built Tools
213 If you are interested in getting actual work done rather than building
214 OpenOCD, then check if your interface supplier provides binaries for
215 you. Chances are that that binary is from some SVN version that is more
216 stable than SVN trunk where bleeding edge development takes place.
218 @section Packagers Please Read!
220 You are a @b{PACKAGER} of OpenOCD if you
223 @item @b{Sell dongles} and include pre-built binaries
224 @item @b{Supply tools} i.e.: A complete development solution
225 @item @b{Supply IDEs} like Eclipse, or RHIDE, etc.
226 @item @b{Build packages} i.e.: RPM files, or DEB files for a Linux Distro
229 As a @b{PACKAGER}, you will experience first reports of most issues.
230 When you fix those problems for your users, your solution may help
231 prevent hundreds (if not thousands) of other questions from other users.
233 If something does not work for you, please work to inform the OpenOCD
234 developers know how to improve the system or documentation to avoid
235 future problems, and follow-up to help us ensure the issue will be fully
236 resolved in our future releases.
238 That said, the OpenOCD developers would also like you to follow a few
242 @item @b{Always build with printer ports enabled.}
243 @item @b{Try to use LIBFTDI + LIBUSB where possible. You cover more bases.}
247 @item @b{Why YES to LIBFTDI + LIBUSB?}
249 @item @b{LESS} work - libusb perhaps already there
250 @item @b{LESS} work - identical code, multiple platforms
251 @item @b{MORE} dongles are supported
252 @item @b{MORE} platforms are supported
253 @item @b{MORE} complete solution
255 @item @b{Why not LIBFTDI + LIBUSB} (i.e.: ftd2xx instead)?
257 @item @b{LESS} speed - some say it is slower
258 @item @b{LESS} complex to distribute (external dependencies)
262 @section Building From Source
264 You can download the current SVN version with an SVN client of your choice from the
265 following repositories:
267 @uref{svn://svn.berlios.de/openocd/trunk}
271 @uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
273 Using the SVN command line client, you can use the following command to fetch the
274 latest version (make sure there is no (non-svn) directory called "openocd" in the
278 svn checkout svn://svn.berlios.de/openocd/trunk openocd
281 If you prefer GIT based tools, the @command{git-svn} package works too:
284 git svn clone -s svn://svn.berlios.de/openocd
287 Building OpenOCD from a repository requires a recent version of the
288 GNU autotools (autoconf >= 2.59 and automake >= 1.9).
289 For building on Windows,
290 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
291 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
292 paths, resulting in obscure dependency errors (This is an observation I've gathered
293 from the logs of one user - correct me if I'm wrong).
295 You further need the appropriate driver files, if you want to build support for
296 a FTDI FT2232 based interface:
299 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
300 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
301 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
302 homepage (@uref{http://www.amontec.com}). The JTAGkey uses a non-standard VID/PID.
305 libftdi is supported under Windows. Do not use versions earlier than 0.14.
307 In general, the D2XX driver provides superior performance (several times as fast),
308 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
309 a kernel module, only a user space library.
311 To build OpenOCD (on both Linux and Cygwin), use the following commands:
317 Bootstrap generates the configure script, and prepares building on your system.
320 ./configure [options, see below]
323 Configure generates the Makefiles used to build OpenOCD.
330 Make builds OpenOCD, and places the final executable in ./src/, the last step, ``make install'' is optional.
332 The configure script takes several options, specifying which JTAG interfaces
333 should be included (among other things):
337 @option{--enable-parport} - Enable building the PC parallel port driver.
339 @option{--enable-parport_ppdev} - Enable use of ppdev (/dev/parportN) for parport.
341 @option{--enable-parport_giveio} - Enable use of giveio for parport instead of ioperm.
343 @option{--enable-amtjtagaccel} - Enable building the Amontec JTAG-Accelerator driver.
345 @option{--enable-ecosboard} - Enable building support for eCosBoard based JTAG debugger.
347 @option{--enable-ioutil} - Enable ioutil functions - useful for standalone OpenOCD implementations.
349 @option{--enable-httpd} - Enable builtin httpd server - useful for standalone OpenOCD implementations.
351 @option{--enable-ep93xx} - Enable building support for EP93xx based SBCs.
353 @option{--enable-at91rm9200} - Enable building support for AT91RM9200 based SBCs.
355 @option{--enable-gw16012} - Enable building support for the Gateworks GW16012 JTAG programmer.
357 @option{--enable-ft2232_ftd2xx} - Numerous USB type ARM JTAG dongles use the FT2232C chip from this FTDICHIP.COM chip (closed source).
359 @option{--enable-ft2232_libftdi} - An open source (free) alternative to FTDICHIP.COM ftd2xx solution (Linux, MacOS, Cygwin).
361 @option{--with-ftd2xx-win32-zipdir=PATH} - If using FTDICHIP.COM ft2232c driver,
362 give the directory where the Win32 FTDICHIP.COM 'CDM' driver zip file was unpacked.
364 @option{--with-ftd2xx-linux-tardir=PATH} - If using FTDICHIP.COM ft2232c driver
365 on Linux, give the directory where the Linux driver's TAR.GZ file was unpacked.
367 @option{--with-ftd2xx-lib=shared|static} - Linux only. Default: static. Specifies how the FTDICHIP.COM libftd2xx driver should be linked. Note: 'static' only works in conjunction with @option{--with-ftd2xx-linux-tardir}. The 'shared' value is supported (12/26/2008), however you must manually install the required header files and shared libraries in an appropriate place. This uses ``libusb'' internally.
369 @option{--enable-presto_libftdi} - Enable building support for ASIX Presto programmer using the libftdi driver.
371 @option{--enable-presto_ftd2xx} - Enable building support for ASIX Presto programmer using the FTD2XX driver.
373 @option{--enable-usbprog} - Enable building support for the USBprog JTAG programmer.
375 @option{--enable-oocd_trace} - Enable building support for the OpenOCD+trace ETM capture device.
377 @option{--enable-jlink} - Enable building support for the Segger J-Link JTAG programmer.
379 @option{--enable-vsllink} - Enable building support for the Versaloon-Link JTAG programmer.
381 @option{--enable-rlink} - Enable building support for the Raisonance RLink JTAG programmer.
383 @option{--enable-arm-jtag-ew} - Enable building support for the Olimex ARM-JTAG-EW programmer.
385 @option{--enable-dummy} - Enable building the dummy port driver.
388 @section Parallel Port Dongles
390 If you want to access the parallel port using the PPDEV interface you have to specify
391 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
392 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
393 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
395 The same is true for the @option{--enable-parport_giveio} option, you have to
396 use both the @option{--enable-parport} AND the @option{--enable-parport_giveio} option if you want to use giveio instead of ioperm parallel port access method.
398 @section FT2232C Based USB Dongles
400 There are 2 methods of using the FTD2232, either (1) using the
401 FTDICHIP.COM closed source driver, or (2) the open (and free) driver
402 libftdi. Some claim the (closed) FTDICHIP.COM solution is faster.
404 The FTDICHIP drivers come as either a (win32) ZIP file, or a (Linux)
405 TAR.GZ file. You must unpack them ``some where'' convient. As of this
406 writing (12/26/2008) FTDICHIP does not supply means to install these
407 files ``in an appropriate place'' As a result, there are two
408 ``./configure'' options that help.
410 Below is an example build process:
413 @item Check out the latest version of ``openocd'' from SVN.
415 @item If you are using the FTDICHIP.COM driver, download
416 and unpack the Windows or Linux FTD2xx drivers
417 (@uref{http://www.ftdichip.com/Drivers/D2XX.htm}).
418 If you are using the libftdi driver, install that package
419 (e.g. @command{apt-get install libftdi} on systems with APT).
422 /home/duane/ftd2xx.win32 => the Cygwin/Win32 ZIP file contents
423 /home/duane/libftd2xx0.4.16 => the Linux TAR.GZ file contents
426 @item Configure with options resembling the following.
429 @item Cygwin FTDICHIP solution:
431 ./configure --prefix=/home/duane/mytools \
432 --enable-ft2232_ftd2xx \
433 --with-ftd2xx-win32-zipdir=/home/duane/ftd2xx.win32
436 @item Linux FTDICHIP solution:
438 ./configure --prefix=/home/duane/mytools \
439 --enable-ft2232_ftd2xx \
440 --with-ft2xx-linux-tardir=/home/duane/libftd2xx0.4.16
443 @item Cygwin/Linux LIBFTDI solution ... assuming that
445 @item For Windows -- that the Windows port of LIBUSB is in place.
446 @item For Linux -- that libusb has been built/installed and is in place.
447 @item That libftdi has been built and installed (relies on libusb).
450 Then configure the libftdi solution like this:
453 ./configure --prefix=/home/duane/mytools \
454 --enable-ft2232_libftdi
458 @item Then just type ``make'', and perhaps ``make install''.
462 @section Miscellaneous Configure Options
466 @option{--disable-option-checking} - Ignore unrecognized @option{--enable} and @option{--with} options.
468 @option{--enable-gccwarnings} - Enable extra gcc warnings during build.
471 @option{--enable-release} - Enable building of an OpenOCD release, generally
472 this is for developers. It simply omits the svn version string when the
473 openocd @option{-v} is executed.
476 @node JTAG Hardware Dongles
477 @chapter JTAG Hardware Dongles
486 Defined: @b{dongle}: A small device that plugins into a computer and serves as
487 an adapter .... [snip]
489 In the OpenOCD case, this generally refers to @b{a small adapater} one
490 attaches to your computer via USB or the Parallel Printer Port. The
491 execption being the Zylin ZY1000 which is a small box you attach via
492 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
493 require any drivers to be installed on the developer PC. It also has
494 a built in web interface. It supports RTCK/RCLK or adaptive clocking
495 and has a built in relay to power cycle targets remotely.
498 @section Choosing a Dongle
500 There are three things you should keep in mind when choosing a dongle.
503 @item @b{Voltage} What voltage is your target? 1.8, 2.8, 3.3, or 5V? Does your dongle support it?
504 @item @b{Connection} Printer Ports - Does your computer have one?
505 @item @b{Connection} Is that long printer bit-bang cable practical?
506 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
509 @section Stand alone Systems
511 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
512 dongle, but a standalone box. The ZY1000 has the advantage that it does
513 not require any drivers installed on the developer PC. It also has
514 a built in web interface. It supports RTCK/RCLK or adaptive clocking
515 and has a built in relay to power cycle targets remotely.
517 @section USB FT2232 Based
519 There are many USB JTAG dongles on the market, many of them are based
520 on a chip from ``Future Technology Devices International'' (FTDI)
521 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
522 See: @url{http://www.ftdichip.com} for more information.
523 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
524 chips are starting to become available in JTAG adapters.
526 As of 28/Nov/2008, the following are supported:
530 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
532 @* See: @url{http://www.amontec.com/jtagkey.shtml}
534 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
536 @* See: @url{http://www.signalyzer.com}
537 @item @b{evb_lm3s811}
538 @* See: @url{http://www.luminarymicro.com} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
539 @item @b{olimex-jtag}
540 @* See: @url{http://www.olimex.com}
542 @* See: @url{http://www.tincantools.com}
543 @item @b{turtelizer2}
545 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
546 @url{http://www.ethernut.de}
548 @* Link: @url{http://www.hitex.com/index.php?id=383}
550 @* Link @url{http://www.hitex.com/stm32-stick}
551 @item @b{axm0432_jtag}
552 @* Axiom AXM-0432 Link @url{http://www.axman.com}
554 @* Link @url{http://www.hitex.com/index.php?id=cortino}
557 @section USB JLINK based
558 There are several OEM versions of the Segger @b{JLINK} adapter. It is
559 an example of a micro controller based JTAG adapter, it uses an
560 AT91SAM764 internally.
563 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
564 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
565 @item @b{SEGGER JLINK}
566 @* Link: @url{http://www.segger.com/jlink.html}
568 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
571 @section USB RLINK based
572 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
575 @item @b{Raisonance RLink}
576 @* Link: @url{http://www.raisonance.com/products/RLink.php}
577 @item @b{STM32 Primer}
578 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
579 @item @b{STM32 Primer2}
580 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
586 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
588 @item @b{USB - Presto}
589 @* Link: @url{http://tools.asix.net/prg_presto.htm}
591 @item @b{Versaloon-Link}
592 @* Link: @url{http://www.simonqian.com/en/Versaloon}
594 @item @b{ARM-JTAG-EW}
595 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
598 @section IBM PC Parallel Printer Port Based
600 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
601 and the MacGraigor Wiggler. There are many clones and variations of
606 @item @b{Wiggler} - There are many clones of this.
607 @* Link: @url{http://www.macraigor.com/wiggler.htm}
609 @item @b{DLC5} - From XILINX - There are many clones of this
610 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
611 produced, PDF schematics are easily found and it is easy to make.
613 @item @b{Amontec - JTAG Accelerator}
614 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
617 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
620 @*@uref{http://www.ccac.rwth-aachen.de/@/~michaels/@/index.php/hardware/@/armjtag,
621 Improved parallel-port wiggler-style JTAG adapter}
623 @item @b{Wiggler_ntrst_inverted}
624 @* Yet another variation - See the source code, src/jtag/parport.c
626 @item @b{old_amt_wiggler}
627 @* Unknown - probably not on the market today
630 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
633 @* Link: @url{http://www.amontec.com/chameleon.shtml}
639 @* ispDownload from Lattice Semiconductor
640 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
643 @* From ST Microsystems;
644 @uref{http://www.st.com/stonline/@/products/literature/um/7889.pdf,
645 FlashLINK JTAG programing cable for PSD and uPSD}
653 @* An EP93xx based Linux machine using the GPIO pins directly.
656 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
662 @cindex running OpenOCD
664 @cindex --debug_level
668 The @option{--help} option shows:
672 --help | -h display this help
673 --version | -v display OpenOCD version
674 --file | -f use configuration file <name>
675 --search | -s dir to search for config files and scripts
676 --debug | -d set debug level <0-3>
677 --log_output | -l redirect log output to file <name>
678 --command | -c run <command>
679 --pipe | -p use pipes when talking to gdb
682 By default OpenOCD reads the file configuration file ``openocd.cfg''
683 in the current directory. To specify a different (or multiple)
684 configuration file, you can use the ``-f'' option. For example:
687 openocd -f config1.cfg -f config2.cfg -f config3.cfg
690 Once started, OpenOCD runs as a daemon, waiting for connections from
691 clients (Telnet, GDB, Other).
693 If you are having problems, you can enable internal debug messages via
696 Also it is possible to interleave commands w/config scripts using the
697 @option{-c} command line switch.
699 To enable debug output (when reporting problems or working on OpenOCD
700 itself), use the @option{-d} command line switch. This sets the
701 @option{debug_level} to "3", outputting the most information,
702 including debug messages. The default setting is "2", outputting only
703 informational messages, warnings and errors. You can also change this
704 setting from within a telnet or gdb session using @option{debug_level
705 <n>} @xref{debug_level}.
707 You can redirect all output from the daemon to a file using the
708 @option{-l <logfile>} switch.
710 Search paths for config/script files can be added to OpenOCD by using
711 the @option{-s <search>} switch. The current directory and the OpenOCD
712 target library is in the search path by default.
714 For details on the @option{-p} option. @xref{Connecting to GDB}.
716 Note! OpenOCD will launch the GDB & telnet server even if it can not
717 establish a connection with the target. In general, it is possible for
718 the JTAG controller to be unresponsive until the target is set up
719 correctly via e.g. GDB monitor commands in a GDB init script.
721 @node Simple Configuration Files
722 @chapter Simple Configuration Files
723 @cindex configuration
726 There are 4 basic ways of ``configurating'' OpenOCD to run, they are:
729 @item A small openocd.cfg file which ``sources'' other configuration files
730 @item A monolithic openocd.cfg file
731 @item Many -f filename options on the command line
732 @item Your Mixed Solution
735 @section Small configuration file method
737 This is the preferred method. It is simple and works well for many
738 people. The developers of OpenOCD would encourage you to use this
739 method. If you create a new configuration please email new
740 configurations to the development list.
742 Here is an example of an openocd.cfg file for an ATMEL at91sam7x256
745 source [find interface/signalyzer.cfg]
747 # GDB can also flash my flash!
748 gdb_memory_map enable
749 gdb_flash_program enable
751 source [find target/sam7x256.cfg]
754 There are many example configuration scripts you can work with. You
755 should look in the directory: @t{$(INSTALLDIR)/lib/openocd}. You
759 @item @b{board} - eval board level configurations
760 @item @b{interface} - specific dongle configurations
761 @item @b{target} - the target chips
762 @item @b{tcl} - helper scripts
763 @item @b{xscale} - things specific to the xscale.
766 Look first in the ``boards'' area, then the ``targets'' area. Often a board
767 configuration is a good example to work from.
769 @section Many -f filename options
770 Some believe this is a wonderful solution, others find it painful.
772 You can use a series of ``-f filename'' options on the command line,
773 OpenOCD will read each filename in sequence, for example:
776 openocd -f file1.cfg -f file2.cfg -f file2.cfg
779 You can also intermix various commands with the ``-c'' command line
782 @section Monolithic file
783 The ``Monolithic File'' dispenses with all ``source'' statements and
784 puts everything in one self contained (monolithic) file. This is not
787 Please try to ``source'' various files or use the multiple -f
790 @section Advice for you
791 Often, one uses a ``mixed approach''. Where possible, please try to
792 ``source'' common things, and if needed cut/paste parts of the
793 standard distribution configuration files as needed.
795 @b{REMEMBER:} The ``important parts'' of your configuration file are:
798 @item @b{Interface} - Defines the dongle
799 @item @b{Taps} - Defines the JTAG Taps
800 @item @b{GDB Targets} - What GDB talks to
801 @item @b{Flash Programing} - Very Helpful
804 Some key things you should look at and understand are:
807 @item The reset configuration of your debug environment as a whole
808 @item Is there a ``work area'' that OpenOCD can use?
809 @* For ARM - work areas mean up to 10x faster downloads.
810 @item For MMU/MPU based ARM chips (i.e.: ARM9 and later) will that work area still be available?
811 @item For complex targets (multiple chips) the JTAG SPEED becomes an issue.
816 @node Config File Guidelines
817 @chapter Config File Guidelines
819 This section/chapter is aimed at developers and integrators of
820 OpenOCD. These are guidelines for creating new boards and new target
821 configurations as of 28/Nov/2008.
823 However, you, the user of OpenOCD, should be somewhat familiar with
824 this section as it should help explain some of the internals of what
825 you might be looking at.
827 The user should find the following directories under @t{$(INSTALLDIR)/lib/openocd} :
831 @*Think JTAG Dongle. Files that configure the JTAG dongle go here.
833 @* Think Circuit Board, PWA, PCB, they go by many names. Board files
834 contain initialization items that are specific to a board - for
835 example: The SDRAM initialization sequence for the board, or the type
836 of external flash and what address it is found at. Any initialization
837 sequence to enable that external flash or SDRAM should be found in the
838 board file. Boards may also contain multiple targets, i.e.: Two CPUs, or
839 a CPU and an FPGA or CPLD.
841 @* Think chip. The ``target'' directory represents the JTAG TAPs
843 which OpenOCD should control, not a board. Two common types of targets
844 are ARM chips and FPGA or CPLD chips.
845 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
846 the target config file defines all of them.
849 @b{If needed...} The user in their ``openocd.cfg'' file or the board
850 file might override a specific feature in any of the above files by
851 setting a variable or two before sourcing the target file. Or adding
852 various commands specific to their situation.
854 @section Interface Config Files
856 The user should be able to source one of these files via a command like this:
859 source [find interface/FOOBAR.cfg]
861 openocd -f interface/FOOBAR.cfg
864 A preconfigured interface file should exist for every interface in use
865 today, that said, perhaps some interfaces have only been used by the
866 sole developer who created it.
868 Interface files should be found in @t{$(INSTALLDIR)/lib/openocd/interface}
870 @section Board Config Files
872 @b{Note: BOARD directory NEW as of 28/nov/2008}
874 The user should be able to source one of these files via a command like this:
877 source [find board/FOOBAR.cfg]
879 openocd -f board/FOOBAR.cfg
883 The board file should contain one or more @t{source [find
884 target/FOO.cfg]} statements along with any board specific things.
886 In summary the board files should contain (if present)
889 @item External flash configuration (i.e.: NOR flash on CS0, two NANDs on CS2)
890 @item SDRAM configuration (size, speed, etc.
891 @item Board specific IO configuration (i.e.: GPIO pins might disable a 2nd flash)
892 @item Multiple TARGET source statements
893 @item Reset configuration
894 @item All things that are not ``inside a chip''
895 @item Things inside a chip go in a 'target' file
898 @section Target Config Files
900 The user should be able to source one of these files via a command like this:
903 source [find target/FOOBAR.cfg]
905 openocd -f target/FOOBAR.cfg
908 In summary the target files should contain
912 @item Add TAPs to the scan chain
913 @item Add CPU targets
914 @item CPU/Chip/CPU-Core specific features
918 @subsection Important variable names
920 By default, the end user should never need to set these
921 variables. However, if the user needs to override a setting they only
922 need to set the variable in a simple way.
926 @* This gives a name to the overall chip, and is used as part of the
927 tap identifier dotted name.
929 @* By default little - unless the chip or board is not normally used that way.
931 @* When OpenOCD examines the JTAG chain, it will attempt to identify
932 every chip. If the @t{-expected-id} is nonzero, OpenOCD attempts
933 to verify the tap id number verses configuration file and may issue an
934 error or warning like this. The hope is that this will help to pinpoint
935 problems in OpenOCD configurations.
938 Info: JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
939 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
940 Error: ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678,
942 Error: ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
943 Error: ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
946 @item @b{_TARGETNAME}
947 @* By convention, this variable is created by the target configuration
948 script. The board configuration file may make use of this variable to
949 configure things like a ``reset init'' script, or other things
950 specific to that board and that target.
952 If the chip has 2 targets, use the names @b{_TARGETNAME0},
953 @b{_TARGETNAME1}, ... etc.
955 @b{Remember:} The ``board file'' may include multiple targets.
957 At no time should the name ``target0'' (the default target name if
958 none was specified) be used. The name ``target0'' is a hard coded name
959 - the next target on the board will be some other number.
960 In the same way, avoid using target numbers even when they are
961 permitted; use the right target name(s) for your board.
963 The user (or board file) should reasonably be able to:
966 source [find target/FOO.cfg]
967 $_TARGETNAME configure ... FOO specific parameters
969 source [find target/BAR.cfg]
970 $_TARGETNAME configure ... BAR specific parameters
975 @subsection Tcl Variables Guide Line
976 The Full Tcl/Tk language supports ``namespaces'' - JIM-Tcl does not.
978 Thus the rule we follow in OpenOCD is this: Variables that begin with
979 a leading underscore are temporary in nature, and can be modified and
980 used at will within a ?TARGET? configuration file.
982 @b{EXAMPLE:} The user should be able to do this:
986 # PXA270 #1 network side, big endian
987 # PXA270 #2 video side, little endian
991 source [find target/pxa270.cfg]
992 # variable: _TARGETNAME = network.cpu
993 # other commands can refer to the "network.cpu" tap.
994 $_TARGETNAME configure .... params for this CPU..
998 source [find target/pxa270.cfg]
999 # variable: _TARGETNAME = video.cpu
1000 # other commands can refer to the "video.cpu" tap.
1001 $_TARGETNAME configure .... params for this CPU..
1005 source [find target/spartan3.cfg]
1007 # Since $_TARGETNAME is temporal..
1008 # these names still work!
1009 network.cpu configure ... params
1010 video.cpu configure ... params
1013 @subsection Default Value Boiler Plate Code
1015 All target configuration files should start with this (or a modified form)
1019 if @{ [info exists CHIPNAME] @} @{
1020 set _CHIPNAME $CHIPNAME
1022 set _CHIPNAME sam7x256
1025 if @{ [info exists ENDIAN] @} @{
1031 if @{ [info exists CPUTAPID ] @} @{
1032 set _CPUTAPID $CPUTAPID
1034 set _CPUTAPID 0x3f0f0f0f
1038 @subsection Adding TAPs to the Scan Chain
1039 After the ``defaults'' are set up,
1040 add the TAPs on each chip to the JTAG scan chain.
1041 @xref{TAP Declaration}, and the naming convention
1044 In the simplest case the chip has only one TAP,
1045 probably for a CPU or FPGA.
1046 The config file for the Atmel AT91SAM7X256
1047 looks (in part) like this:
1050 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
1051 -expected-id $_CPUTAPID
1054 A board with two such at91sam7 chips would be able
1055 to source such a config file twice, with different
1056 values for @code{CHIPNAME}, so
1057 it adds a different TAP each time.
1059 There are more complex examples too, with chips that have
1060 multiple TAPs. Ones worth looking at include:
1063 @item @file{target/omap3530.cfg} -- with a disabled ARM, and a JRC
1064 (there's a DSP too, which is not listed)
1065 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1066 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1067 is not currently used)
1070 @subsection Add CPU targets
1072 After adding a TAP for a CPU, you should set it up so that
1073 GDB and other commands can use it.
1074 @xref{CPU Configuration}.
1075 For the at91sam7 example above, the command can look like this:
1078 set _TARGETNAME $_CHIPNAME.cpu
1079 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1082 Work areas are small RAM areas associated with CPU targets.
1083 They are used by OpenOCD to speed up downloads,
1084 and to download small snippets of code to program flash chips.
1085 If the chip includes a form of ``on-chip-ram'' - and many do - define
1086 a work area if you can.
1087 Again using the at91sam7 as an example, this can look like:
1090 $_TARGETNAME configure -work-area-phys 0x00200000 \
1091 -work-area-size 0x4000 -work-area-backup 0
1094 @subsection Reset Configuration
1096 As a rule, you should put the @command{reset_config} command
1097 into the board file. Most things you think you know about a
1098 chip can be tweaked by the board.
1100 Some chips have specific ways the TRST and SRST signals are
1101 managed. In the unusual case that these are @emph{chip specific}
1102 and can never be changed by board wiring, they could go here.
1104 @subsection ARM Core Specific Hacks
1106 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1107 special high speed download features - enable it.
1109 If the chip has an ARM ``vector catch'' feature - by default enable
1110 it for Undefined Instructions, Data Abort, and Prefetch Abort, if the
1111 user is really writing a handler for those situations - they can
1112 easily disable it. Experiance has shown the ``vector catch'' is
1113 helpful - for common programing errors.
1115 If present, the MMU, the MPU and the CACHE should be disabled.
1117 Some ARM cores are equipped with trace support, which permits
1118 examination of the instruction and data bus activity. Trace
1119 activity is controlled through an ``Embedded Trace Module'' (ETM)
1120 on one of the core's scan chains. The ETM emits voluminous data
1121 through a ``trace port''. (@xref{ARM Tracing}.)
1122 If you are using an external trace port,
1123 configure it in your board config file.
1124 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1125 configure it in your target config file.
1128 etm config $_TARGETNAME 16 normal full etb
1129 etb config $_TARGETNAME $_CHIPNAME.etb
1132 @subsection Internal Flash Configuration
1134 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1136 @b{Never ever} in the ``target configuration file'' define any type of
1137 flash that is external to the chip. (For example a BOOT flash on
1138 Chip Select 0.) Such flash information goes in a board file - not
1139 the TARGET (chip) file.
1143 @item at91sam7x256 - has 256K flash YES enable it.
1144 @item str912 - has flash internal YES enable it.
1145 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1146 @item pxa270 - again - CS0 flash - it goes in the board file.
1150 @chapter About JIM-Tcl
1154 OpenOCD includes a small ``TCL Interpreter'' known as JIM-TCL. You can
1155 learn more about JIM here: @url{http://jim.berlios.de}
1158 @item @b{JIM vs. Tcl}
1159 @* JIM-TCL is a stripped down version of the well known Tcl language,
1160 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
1161 fewer features. JIM-Tcl is a single .C file and a single .H file and
1162 impliments the basic Tcl command set along. In contrast: Tcl 8.6 is a
1163 4.2 MB .zip file containing 1540 files.
1165 @item @b{Missing Features}
1166 @* Our practice has been: Add/clone the real Tcl feature if/when
1167 needed. We welcome JIM Tcl improvements, not bloat.
1170 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
1171 command interpreter today (28/nov/2008) is a mixture of (newer)
1172 JIM-Tcl commands, and (older) the orginal command interpreter.
1175 @* At the OpenOCD telnet command line (or via the GDB mon command) one
1176 can type a Tcl for() loop, set variables, etc.
1178 @item @b{Historical Note}
1179 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
1181 @item @b{Need a crash course in Tcl?}
1182 @*@xref{Tcl Crash Course}.
1185 @node Daemon Configuration
1186 @chapter Daemon Configuration
1187 @cindex initialization
1188 The commands here are commonly found in the openocd.cfg file and are
1189 used to specify what TCP/IP ports are used, and how GDB should be
1192 @section Configuration Stage
1193 @cindex configuration stage
1194 @cindex configuration command
1196 When the OpenOCD server process starts up, it enters a
1197 @emph{configuration stage} which is the only time that
1198 certain commands, @emph{configuration commands}, may be issued.
1199 Those configuration commands include declaration of TAPs
1200 and other basic setup.
1201 The server must leave the configuration stage before it
1202 may access or activate TAPs.
1203 After it leaves this stage, configuration commands may no
1206 @deffn {Config Command} init
1207 This command terminates the configuration stage and
1208 enters the normal command mode. This can be useful to add commands to
1209 the startup scripts and commands such as resetting the target,
1210 programming flash, etc. To reset the CPU upon startup, add "init" and
1211 "reset" at the end of the config script or at the end of the OpenOCD
1212 command line using the @option{-c} command line switch.
1214 If this command does not appear in any startup/configuration file
1215 OpenOCD executes the command for you after processing all
1216 configuration files and/or command line options.
1218 @b{NOTE:} This command normally occurs at or near the end of your
1219 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1220 targets ready. For example: If your openocd.cfg file needs to
1221 read/write memory on your target, @command{init} must occur before
1222 the memory read/write commands. This includes @command{nand probe}.
1225 @section TCP/IP Ports
1229 The OpenOCD server accepts remote commands in several syntaxes.
1230 Each syntax uses a different TCP/IP port, which you may specify
1231 only during configuration (before those ports are opened).
1233 @deffn {Command} gdb_port (number)
1235 Specify or query the first port used for incoming GDB connections.
1236 The GDB port for the
1237 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1238 When not specified during the configuration stage,
1239 the port @var{number} defaults to 3333.
1242 @deffn {Command} tcl_port (number)
1243 Specify or query the port used for a simplified RPC
1244 connection that can be used by clients to issue TCL commands and get the
1245 output from the Tcl engine.
1246 Intended as a machine interface.
1247 When not specified during the configuration stage,
1248 the port @var{number} defaults to 6666.
1251 @deffn {Command} telnet_port (number)
1252 Specify or query the
1253 port on which to listen for incoming telnet connections.
1254 This port is intended for interaction with one human through TCL commands.
1255 When not specified during the configuration stage,
1256 the port @var{number} defaults to 4444.
1259 @anchor{GDB Configuration}
1260 @section GDB Configuration
1262 @cindex GDB configuration
1263 You can reconfigure some GDB behaviors if needed.
1264 The ones listed here are static and global.
1265 @xref{Target Configuration}, about configuring individual targets.
1266 @xref{Target Events}, about configuring target-specific event handling.
1268 @anchor{gdb_breakpoint_override}
1269 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
1270 Force breakpoint type for gdb @command{break} commands.
1271 This option supports GDB GUIs which don't
1272 distinguish hard versus soft breakpoints, if the default OpenOCD and
1273 GDB behaviour is not sufficient. GDB normally uses hardware
1274 breakpoints if the memory map has been set up for flash regions.
1277 @deffn {Config command} gdb_detach (@option{resume}|@option{reset}|@option{halt}|@option{nothing})
1278 Configures what OpenOCD will do when GDB detaches from the daemon.
1279 Default behaviour is @option{resume}.
1282 @anchor{gdb_flash_program}
1283 @deffn {Config command} gdb_flash_program (@option{enable}|@option{disable})
1284 Set to @option{enable} to cause OpenOCD to program the flash memory when a
1285 vFlash packet is received.
1286 The default behaviour is @option{enable}.
1289 @deffn {Config command} gdb_memory_map (@option{enable}|@option{disable})
1290 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
1291 requested. GDB will then know when to set hardware breakpoints, and program flash
1292 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1293 for flash programming to work.
1294 Default behaviour is @option{enable}.
1295 @xref{gdb_flash_program}.
1298 @deffn {Config command} gdb_report_data_abort (@option{enable}|@option{disable})
1299 Specifies whether data aborts cause an error to be reported
1300 by GDB memory read packets.
1301 The default behaviour is @option{disable};
1302 use @option{enable} see these errors reported.
1305 @node Interface - Dongle Configuration
1306 @chapter Interface - Dongle Configuration
1307 JTAG Adapters/Interfaces/Dongles are normally configured
1308 through commands in an interface configuration
1309 file which is sourced by your @file{openocd.cfg} file, or
1310 through a command line @option{-f interface/....cfg} option.
1313 source [find interface/olimex-jtag-tiny.cfg]
1317 OpenOCD what type of JTAG adapter you have, and how to talk to it.
1318 A few cases are so simple that you only need to say what driver to use:
1325 Most adapters need a bit more configuration than that.
1328 @section Interface Configuration
1330 The interface command tells OpenOCD what type of JTAG dongle you are
1331 using. Depending on the type of dongle, you may need to have one or
1332 more additional commands.
1334 @deffn {Config Command} {interface} name
1335 Use the interface driver @var{name} to connect to the
1339 @deffn Command {jtag interface}
1340 Returns the name of the interface driver being used.
1343 @section Interface Drivers
1345 Each of the interface drivers listed here must be explicitly
1346 enabled when OpenOCD is configured, in order to be made
1347 available at run time.
1349 @deffn {Interface Driver} {amt_jtagaccel}
1350 Amontec Chameleon in its JTAG Accelerator configuration,
1351 connected to a PC's EPP mode parallel port.
1352 This defines some driver-specific commands:
1354 @deffn {Config Command} {parport_port} number
1355 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1356 the number of the @file{/dev/parport} device.
1359 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
1360 Displays status of RTCK option.
1361 Optionally sets that option first.
1365 @deffn {Interface Driver} {arm-jtag-ew}
1366 Olimex ARM-JTAG-EW USB adapter
1367 This has one driver-specific command:
1369 @deffn Command {armjtagew_info}
1374 @deffn {Interface Driver} {at91rm9200}
1375 Supports bitbanged JTAG from the local system,
1376 presuming that system is an Atmel AT91rm9200
1377 and a specific set of GPIOs is used.
1378 @c command: at91rm9200_device NAME
1379 @c chooses among list of bit configs ... only one option
1382 @deffn {Interface Driver} {dummy}
1383 A dummy software-only driver for debugging.
1386 @deffn {Interface Driver} {ep93xx}
1387 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1390 @deffn {Interface Driver} {ft2232}
1391 FTDI FT2232 (USB) based devices over one of the userspace libraries.
1392 These interfaces have several commands, used to configure the driver
1393 before initializing the JTAG scan chain:
1395 @deffn {Config Command} {ft2232_device_desc} description
1396 Provides the USB device description (the @emph{iProduct string})
1397 of the FTDI FT2232 device. If not
1398 specified, the FTDI default value is used. This setting is only valid
1399 if compiled with FTD2XX support.
1402 @deffn {Config Command} {ft2232_serial} serial-number
1403 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
1404 in case the vendor provides unique IDs and more than one FT2232 device
1405 is connected to the host.
1406 If not specified, serial numbers are not considered.
1409 @deffn {Config Command} {ft2232_layout} name
1410 Each vendor's FT2232 device can use different GPIO signals
1411 to control output-enables, reset signals, and LEDs.
1412 Currently valid layout @var{name} values include:
1414 @item @b{axm0432_jtag} Axiom AXM-0432
1415 @item @b{comstick} Hitex STR9 comstick
1416 @item @b{cortino} Hitex Cortino JTAG interface
1417 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
1418 either for the local Cortex-M3 (SRST only)
1419 or in a passthrough mode (neither SRST nor TRST)
1420 @item @b{flyswatter} Tin Can Tools Flyswatter
1421 @item @b{icebear} ICEbear JTAG adapter from Section 5
1422 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
1423 @item @b{m5960} American Microsystems M5960
1424 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
1425 @item @b{oocdlink} OOCDLink
1426 @c oocdlink ~= jtagkey_prototype_v1
1427 @item @b{sheevaplug} Marvell Sheevaplug development kit
1428 @item @b{signalyzer} Xverve Signalyzer
1429 @item @b{stm32stick} Hitex STM32 Performance Stick
1430 @item @b{turtelizer2} egnite Software turtelizer2
1431 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
1435 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
1436 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1437 default values are used.
1438 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
1440 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1444 @deffn {Config Command} {ft2232_latency} ms
1445 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1446 ft2232_read() fails to return the expected number of bytes. This can be caused by
1447 USB communication delays and has proved hard to reproduce and debug. Setting the
1448 FT2232 latency timer to a larger value increases delays for short USB packets but it
1449 also reduces the risk of timeouts before receiving the expected number of bytes.
1450 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1453 For example, the interface config file for a
1454 Turtelizer JTAG Adapter looks something like this:
1458 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
1459 ft2232_layout turtelizer2
1460 ft2232_vid_pid 0x0403 0xbdc8
1464 @deffn {Interface Driver} {gw16012}
1465 Gateworks GW16012 JTAG programmer.
1466 This has one driver-specific command:
1468 @deffn {Config Command} {parport_port} number
1469 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1470 the number of the @file{/dev/parport} device.
1474 @deffn {Interface Driver} {jlink}
1475 Segger jlink USB adapter
1476 @c command: jlink_info
1478 @c command: jlink_hw_jtag (2|3)
1479 @c sets version 2 or 3
1482 @deffn {Interface Driver} {parport}
1483 Supports PC parallel port bit-banging cables:
1484 Wigglers, PLD download cable, and more.
1485 These interfaces have several commands, used to configure the driver
1486 before initializing the JTAG scan chain:
1488 @deffn {Config Command} {parport_cable} name
1489 The layout of the parallel port cable used to connect to the target.
1490 Currently valid cable @var{name} values include:
1493 @item @b{altium} Altium Universal JTAG cable.
1494 @item @b{arm-jtag} Same as original wiggler except SRST and
1495 TRST connections reversed and TRST is also inverted.
1496 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
1497 in configuration mode. This is only used to
1498 program the Chameleon itself, not a connected target.
1499 @item @b{dlc5} The Xilinx Parallel cable III.
1500 @item @b{flashlink} The ST Parallel cable.
1501 @item @b{lattice} Lattice ispDOWNLOAD Cable
1502 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
1504 Amontec's Chameleon Programmer. The new version available from
1505 the website uses the original Wiggler layout ('@var{wiggler}')
1506 @item @b{triton} The parallel port adapter found on the
1507 ``Karo Triton 1 Development Board''.
1508 This is also the layout used by the HollyGates design
1509 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1510 @item @b{wiggler} The original Wiggler layout, also supported by
1511 several clones, such as the Olimex ARM-JTAG
1512 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
1513 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
1517 @deffn {Config Command} {parport_port} number
1518 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1519 the @file{/dev/parport} device
1521 When using PPDEV to access the parallel port, use the number of the parallel port:
1522 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1523 you may encounter a problem.
1526 @deffn {Config Command} {parport_write_on_exit} (on|off)
1527 This will configure the parallel driver to write a known
1528 cable-specific value to the parallel interface on exiting OpenOCD
1531 For example, the interface configuration file for a
1532 classic ``Wiggler'' cable might look something like this:
1537 parport_cable wiggler
1541 @deffn {Interface Driver} {presto}
1542 ASIX PRESTO USB JTAG programmer.
1543 @c command: presto_serial str
1544 @c sets serial number
1547 @deffn {Interface Driver} {rlink}
1548 Raisonance RLink USB adapter
1551 @deffn {Interface Driver} {usbprog}
1552 usbprog is a freely programmable USB adapter.
1555 @deffn {Interface Driver} {vsllink}
1556 vsllink is part of Versaloon which is a versatile USB programmer.
1559 This defines quite a few driver-specific commands,
1560 which are not currently documented here.
1564 @deffn {Interface Driver} {ZY1000}
1565 This is the Zylin ZY1000 JTAG debugger.
1568 This defines some driver-specific commands,
1569 which are not currently documented here.
1572 @deffn Command power [@option{on}|@option{off}]
1573 Turn power switch to target on/off.
1574 No arguments: print status.
1581 JTAG clock setup is part of system setup.
1582 It @emph{does not belong with interface setup} since any interface
1583 only knows a few of the constraints for the JTAG clock speed.
1584 Sometimes the JTAG speed is
1585 changed during the target initialization process: (1) slow at
1586 reset, (2) program the CPU clocks, (3) run fast.
1587 Both the "slow" and "fast" clock rates are functions of the
1588 oscillators used, the chip, the board design, and sometimes
1589 power management software that may be active.
1591 The speed used during reset can be adjusted using pre_reset
1592 and post_reset event handlers.
1593 @xref{Target Events}.
1595 If your system supports adaptive clocking (RTCK), configuring
1596 JTAG to use that is probably the most robust approach.
1597 However, it introduces delays to synchronize clocks; so it
1598 may not be the fastest solution.
1600 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
1601 instead of @command{jtag_khz}.
1603 @deffn {Command} jtag_khz max_speed_kHz
1604 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
1605 JTAG interfaces usually support a limited number of
1606 speeds. The speed actually used won't be faster
1607 than the speed specified.
1609 As a rule of thumb, if you specify a clock rate make
1610 sure the JTAG clock is no more than @math{1/6th CPU-Clock}.
1611 This is especially true for synthesized cores (ARMxxx-S).
1613 Speed 0 (khz) selects RTCK method.
1615 If your system uses RTCK, you won't need to change the
1616 JTAG clocking after setup.
1617 Not all interfaces, boards, or targets support ``rtck''.
1618 If the interface device can not
1619 support it, an error is returned when you try to use RTCK.
1622 @defun jtag_rclk fallback_speed_kHz
1624 This Tcl proc (defined in startup.tcl) attempts to enable RTCK/RCLK.
1625 If that fails (maybe the interface, board, or target doesn't
1626 support it), falls back to the specified frequency.
1628 # Fall back to 3mhz if RTCK is not supported
1633 @node Reset Configuration
1634 @chapter Reset Configuration
1635 @cindex Reset Configuration
1637 Every system configuration may require a different reset
1638 configuration. This can also be quite confusing.
1639 Resets also interact with @var{reset-init} event handlers,
1640 which do things like setting up clocks and DRAM, and
1641 JTAG clock rates. (@xref{JTAG Speed}.)
1642 Please see the various board files for examples.
1645 To maintainers and integrators:
1646 Reset configuration touches several things at once.
1647 Normally the board configuration file
1648 should define it and assume that the JTAG adapter supports
1649 everything that's wired up to the board's JTAG connector.
1650 However, the target configuration file could also make note
1651 of something the silicon vendor has done inside the chip,
1652 which will be true for most (or all) boards using that chip.
1653 And when the JTAG adapter doesn't support everything, the
1654 system configuration file will need to override parts of
1655 the reset configuration provided by other files.
1658 @section Types of Reset
1660 There are many kinds of reset possible through JTAG, but
1661 they may not all work with a given board and adapter.
1662 That's part of why reset configuration can be error prone.
1666 @emph{System Reset} ... the @emph{SRST} hardware signal
1667 resets all chips connected to the JTAG adapter, such as processors,
1668 power management chips, and I/O controllers. Normally resets triggered
1669 with this signal behave exactly like pressing a RESET button.
1671 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
1672 just the TAP controllers connected to the JTAG adapter.
1673 Such resets should not be visible to the rest of the system; resetting a
1674 device's the TAP controller just puts that controller into a known state.
1676 @emph{Emulation Reset} ... many devices can be reset through JTAG
1677 commands. These resets are often distinguishable from system
1678 resets, either explicitly (a "reset reason" register says so)
1679 or implicitly (not all parts of the chip get reset).
1681 @emph{Other Resets} ... system-on-chip devices often support
1682 several other types of reset.
1683 You may need to arrange that a watchdog timer stops
1684 while debugging, preventing a watchdog reset.
1685 There may be individual module resets.
1688 In the best case, OpenOCD can hold SRST, then reset
1689 the TAPs via TRST and send commands through JTAG to halt the
1690 CPU at the reset vector before the 1st instruction is executed.
1691 Then when it finally releases the SRST signal, the system is
1692 halted under debugger control before any code has executed.
1693 This is the behavior required to support the @command{reset halt}
1694 and @command{reset init} commands; after @command{reset init} a
1695 board-specific script might do things like setting up DRAM.
1696 (@xref{Reset Command}.)
1698 @section SRST and TRST Issues
1700 Because SRST and TRST are hardware signals, they can have a
1701 variety of system-specific constraints. Some of the most
1706 @item @emph{Signal not available} ... Some boards don't wire
1707 SRST or TRST to the JTAG connector. Some JTAG adapters don't
1708 support such signals even if they are wired up.
1709 Use the @command{reset_config} @var{signals} options to say
1710 when one of those signals is not connected.
1711 When SRST is not available, your code might not be able to rely
1712 on controllers having been fully reset during code startup.
1714 @item @emph{Signals shorted} ... Sometimes a chip, board, or
1715 adapter will connect SRST to TRST, instead of keeping them separate.
1716 Use the @command{reset_config} @var{combination} options to say
1717 when those signals aren't properly independent.
1719 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
1720 delay circuit, reset supervisor, or on-chip features can extend
1721 the effect of a JTAG adapter's reset for some time after the adapter
1722 stops issuing the reset. For example, there may be chip or board
1723 requirements that all reset pulses last for at least a
1724 certain amount of time; and reset buttons commonly have
1725 hardware debouncing.
1726 Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
1727 commands to say when extra delays are needed.
1729 @item @emph{Drive type} ... Reset lines often have a pullup
1730 resistor, letting the JTAG interface treat them as open-drain
1731 signals. But that's not a requirement, so the adapter may need
1732 to use push/pull output drivers.
1733 Also, with weak pullups it may be advisable to drive
1734 signals to both levels (push/pull) to minimize rise times.
1735 Use the @command{reset_config} @var{trst_type} and
1736 @var{srst_type} parameters to say how to drive reset signals.
1738 @item @emph{Special initialization} ... Targets sometimes need
1739 special JTAG initialization sequences to handle chip-specific
1740 issues (not limited to errata).
1741 For example, certain JTAG commands might need to be issued while
1742 the system as a whole is in a reset state (SRST active)
1743 but the JTAG scan chain is usable (TRST inactive).
1744 (@xref{JTAG Commands}, where the @command{jtag_reset}
1745 command is presented.)
1748 There can also be other issues.
1749 Some devices don't fully conform to the JTAG specifications.
1750 Trivial system-specific differences are common, such as
1751 SRST and TRST using slightly different names.
1752 There are also vendors who distribute key JTAG documentation for
1753 their chips only to developers who have signed a Non-Disclosure
1756 Sometimes there are chip-specific extensions like a requirement to use
1757 the normally-optional TRST signal (precluding use of JTAG adapters which
1758 don't pass TRST through), or needing extra steps to complete a TAP reset.
1760 In short, SRST and especially TRST handling may be very finicky,
1761 needing to cope with both architecture and board specific constraints.
1763 @section Commands for Handling Resets
1765 @deffn {Command} jtag_nsrst_delay milliseconds
1766 How long (in milliseconds) OpenOCD should wait after deasserting
1767 nSRST (active-low system reset) before starting new JTAG operations.
1768 When a board has a reset button connected to SRST line it will
1769 probably have hardware debouncing, implying you should use this.
1772 @deffn {Command} jtag_ntrst_delay milliseconds
1773 How long (in milliseconds) OpenOCD should wait after deasserting
1774 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
1777 @deffn {Command} reset_config mode_flag ...
1778 This command tells OpenOCD the reset configuration
1779 of your combination of JTAG board and target in target
1780 configuration scripts.
1782 If you have an interface that does not support SRST and
1783 TRST(unlikely), then you may be able to work around that
1784 problem by using a reset_config command to override any
1785 settings in the target configuration script.
1787 SRST and TRST has a fairly well understood definition and
1788 behaviour in the JTAG specification, but vendors take
1789 liberties to achieve various more or less clearly understood
1790 goals. Sometimes documentation is available, other times it
1791 is not. OpenOCD has the reset_config command to allow OpenOCD
1792 to deal with the various common cases.
1794 The @var{mode_flag} options can be specified in any order, but only one
1795 of each type -- @var{signals}, @var{combination}, @var{trst_type},
1796 and @var{srst_type} -- may be specified at a time.
1797 If you don't provide a new value for a given type, its previous
1798 value (perhaps the default) is unchanged.
1799 For example, this means that you don't need to say anything at all about
1800 TRST just to declare that if the JTAG adapter should want to drive SRST,
1801 it must explicitly be driven high (@option{srst_push_pull}).
1803 @var{signals} can specify which of the reset signals are connected.
1804 For example, If the JTAG interface provides SRST, but the board doesn't
1805 connect that signal properly, then OpenOCD can't use it.
1806 Possible values are @option{none} (the default), @option{trst_only},
1807 @option{srst_only} and @option{trst_and_srst}.
1810 If your board provides SRST or TRST through the JTAG connector,
1811 you must declare that or else those signals will not be used.
1814 The @var{combination} is an optional value specifying broken reset
1815 signal implementations.
1816 The default behaviour if no option given is @option{separate},
1817 indicating everything behaves normally.
1818 @option{srst_pulls_trst} states that the
1819 test logic is reset together with the reset of the system (e.g. Philips
1820 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
1821 the system is reset together with the test logic (only hypothetical, I
1822 haven't seen hardware with such a bug, and can be worked around).
1823 @option{combined} implies both @option{srst_pulls_trst} and
1824 @option{trst_pulls_srst}.
1826 The optional @var{trst_type} and @var{srst_type} parameters allow the
1827 driver mode of each reset line to be specified. These values only affect
1828 JTAG interfaces with support for different driver modes, like the Amontec
1829 JTAGkey and JTAGAccelerator. Also, they are necessarily ignored if the
1830 relevant signal (TRST or SRST) is not connected.
1832 Possible @var{trst_type} driver modes for the test reset signal (TRST)
1833 are @option{trst_push_pull} (default) and @option{trst_open_drain}.
1834 Most boards connect this signal to a pulldown, so the JTAG TAPs
1835 never leave reset unless they are hooked up to a JTAG adapter.
1837 Possible @var{srst_type} driver modes for the system reset signal (SRST)
1838 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
1839 Most boards connect this signal to a pullup, and allow the
1840 signal to be pulled low by various events including system
1841 powerup and pressing a reset button.
1845 @node TAP Declaration
1846 @chapter TAP Declaration
1847 @cindex TAP declaration
1848 @cindex TAP configuration
1850 @emph{Test Access Ports} (TAPs) are the core of JTAG.
1851 TAPs serve many roles, including:
1854 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
1855 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
1856 Others do it indirectly, making a CPU do it.
1857 @item @b{Program Download} Using the same CPU support GDB uses,
1858 you can initialize a DRAM controller, download code to DRAM, and then
1859 start running that code.
1860 @item @b{Boundary Scan} Most chips support boundary scan, which
1861 helps test for board assembly problems like solder bridges
1862 and missing connections
1865 OpenOCD must know about the active TAPs on your board(s).
1866 Setting up the TAPs is the core task of your configuration files.
1867 Once those TAPs are set up, you can pass their names to code
1868 which sets up CPUs and exports them as GDB targets,
1869 probes flash memory, performs low-level JTAG operations, and more.
1871 @section Scan Chains
1873 OpenOCD uses a JTAG adapter (interface) to talk to your board,
1874 which has a daisy chain of TAPs.
1875 That daisy chain is called a @dfn{scan chain}.
1876 Simple configurations may have a single TAP in the scan chain,
1877 perhaps for a microcontroller.
1878 Complex configurations might have a dozen or more TAPs:
1879 several in one chip, more in the next, and connecting
1880 to other boards with their own chips and TAPs.
1882 Unfortunately those TAPs can't always be autoconfigured,
1883 because not all devices provide good support for that.
1884 (JTAG doesn't require supporting IDCODE instructions.)
1885 The configuration mechanism currently supported by OpenOCD
1886 requires explicit configuration of all TAP devices using
1887 @command{jtag newtap} commands.
1888 One like this would declare a tap and name it @code{chip1.cpu}:
1891 jtag newtap chip1 cpu -irlen 7 -ircapture 0x01 -irmask 0x55
1894 Each target configuration file lists the TAPs provided
1896 Board configuration files combine all the targets on a board,
1898 Note that @emph{the order in which TAPs are declared is very important.}
1899 It must match the order in the JTAG scan chain, both inside
1900 a single chip and between them.
1901 @xref{FAQ TAP Order}.
1903 For example, the ST Microsystems STR912 chip has
1904 three separate TAPs@footnote{See the ST
1905 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
1906 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
1907 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
1908 To configure those taps, @file{target/str912.cfg}
1909 includes commands something like this:
1912 jtag newtap str912 flash ... params ...
1913 jtag newtap str912 cpu ... params ...
1914 jtag newtap str912 bs ... params ...
1917 Actual config files use a variable instead of literals like
1918 @option{str912}, to support more than one chip of each type.
1919 @xref{Config File Guidelines}.
1923 When TAP objects are declared with @command{jtag newtap},
1924 a @dfn{dotted.name} is created for the TAP, combining the
1925 name of a module (usually a chip) and a label for the TAP.
1926 For example: @code{xilinx.tap}, @code{str912.flash},
1927 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
1928 Many other commands use that dotted.name to manipulate or
1929 refer to the TAP. For example, CPU configuration uses the
1930 name, as does declaration of NAND or NOR flash banks.
1932 The components of a dotted name should follow ``C'' symbol
1933 name rules: start with an alphabetic character, then numbers
1934 and underscores are OK; while others (including dots!) are not.
1937 In older code, JTAG TAPs were numbered from 0..N.
1938 This feature is still present.
1939 However its use is highly discouraged, and
1940 should not be counted upon.
1941 Update all of your scripts to use TAP names rather than numbers.
1942 Using TAP numbers in target configuration scripts prevents
1943 reusing on boards with multiple targets.
1946 @section TAP Declaration Commands
1948 @c shouldn't this be(come) a {Config Command}?
1949 @anchor{jtag newtap}
1950 @deffn Command {jtag newtap} chipname tapname configparams...
1951 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
1952 and configured according to the various @var{configparams}.
1954 The @var{chipname} is a symbolic name for the chip.
1955 Conventionally target config files use @code{$_CHIPNAME},
1956 defaulting to the model name given by the chip vendor but
1959 @cindex TAP naming convention
1960 The @var{tapname} reflects the role of that TAP,
1961 and should follow this convention:
1964 @item @code{bs} -- For boundary scan if this is a seperate TAP;
1965 @item @code{cpu} -- The main CPU of the chip, alternatively
1966 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
1967 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
1968 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
1969 @item @code{flash} -- If the chip has a flash TAP, like the str912;
1970 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
1971 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
1972 @item @code{tap} -- Should be used only FPGA or CPLD like devices
1974 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
1975 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
1976 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
1977 a JTAG TAP; that TAP should be named @code{sdma}.
1980 Every TAP requires at least the following @var{configparams}:
1983 @item @code{-ircapture} @var{NUMBER}
1984 @*The IDCODE capture command, such as 0x01.
1985 @item @code{-irlen} @var{NUMBER}
1986 @*The length in bits of the
1987 instruction register, such as 4 or 5 bits.
1988 @item @code{-irmask} @var{NUMBER}
1989 @*A mask for the IR register.
1990 For some devices, there are bits in the IR that aren't used.
1991 This lets OpenOCD mask them off when doing IDCODE comparisons.
1992 In general, this should just be all ones for the size of the IR.
1995 A TAP may also provide optional @var{configparams}:
1998 @item @code{-disable} (or @code{-enable})
1999 @*Use the @code{-disable} paramater to flag a TAP which is not
2000 linked in to the scan chain when it is declared.
2001 You may use @code{-enable} to highlight the default state
2002 (the TAP is linked in).
2003 @xref{Enabling and Disabling TAPs}.
2004 @item @code{-expected-id} @var{number}
2005 @*A non-zero value represents the expected 32-bit IDCODE
2006 found when the JTAG chain is examined.
2007 These codes are not required by all JTAG devices.
2008 @emph{Repeat the option} as many times as required if more than one
2009 ID code could appear (for example, multiple versions).
2013 @c @deffn Command {jtag arp_init-reset}
2014 @c ... more or less "init" ?
2016 @anchor{Enabling and Disabling TAPs}
2017 @section Enabling and Disabling TAPs
2020 In some systems, a @dfn{JTAG Route Controller} (JRC)
2021 is used to enable and/or disable specific JTAG TAPs.
2022 Many ARM based chips from Texas Instruments include
2023 an ``ICEpick'' module, which is a JRC.
2024 Such chips include DaVinci and OMAP3 processors.
2026 A given TAP may not be visible until the JRC has been
2027 told to link it into the scan chain; and if the JRC
2028 has been told to unlink that TAP, it will no longer
2030 Such routers address problems that JTAG ``bypass mode''
2034 @item The scan chain can only go as fast as its slowest TAP.
2035 @item Having many TAPs slows instruction scans, since all
2036 TAPs receive new instructions.
2037 @item TAPs in the scan chain must be powered up, which wastes
2038 power and prevents debugging some power management mechanisms.
2041 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
2042 as implied by the existence of JTAG routers.
2043 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
2044 does include a kind of JTAG router functionality.
2046 @c (a) currently the event handlers don't seem to be able to
2047 @c fail in a way that could lead to no-change-of-state.
2048 @c (b) eventually non-event configuration should be possible,
2049 @c in which case some this documentation must move.
2051 @deffn Command {jtag cget} dotted.name @option{-event} name
2052 @deffnx Command {jtag configure} dotted.name @option{-event} name string
2053 At this writing this mechanism is used only for event handling,
2054 and the only two events relate to TAP enabling and disabling.
2056 The @code{configure} subcommand assigns an event handler,
2057 a TCL string which is evaluated when the event is triggered.
2058 The @code{cget} subcommand returns that handler.
2059 The two possible values for an event @var{name}
2060 are @option{tap-disable} and @option{tap-enable}.
2062 So for example, when defining a TAP for a CPU connected to
2063 a JTAG router, you should define TAP event handlers using
2064 code that looks something like this:
2067 jtag configure CHIP.cpu -event tap-enable @{
2068 echo "Enabling CPU TAP"
2069 ... jtag operations using CHIP.jrc
2071 jtag configure CHIP.cpu -event tap-disable @{
2072 echo "Disabling CPU TAP"
2073 ... jtag operations using CHIP.jrc
2078 @deffn Command {jtag tapdisable} dotted.name
2079 @deffnx Command {jtag tapenable} dotted.name
2080 @deffnx Command {jtag tapisenabled} dotted.name
2081 These three commands all return the string "1" if the tap
2082 specified by @var{dotted.name} is enabled,
2083 and "0" if it is disbabled.
2084 The @command{tapenable} variant first enables the tap
2085 by sending it a @option{tap-enable} event.
2086 The @command{tapdisable} variant first disables the tap
2087 by sending it a @option{tap-disable} event.
2090 Humans will find the @command{scan_chain} command more helpful
2091 than the script-oriented @command{tapisenabled}
2092 for querying the state of the JTAG taps.
2096 @node CPU Configuration
2097 @chapter CPU Configuration
2100 This chapter discusses how to set up GDB debug targets for CPUs.
2101 You can also access these targets without GDB
2102 (@pxref{Architecture and Core Commands},
2103 and @ref{Target State handling}) and
2104 through various kinds of NAND and NOR flash commands.
2105 If you have multiple CPUs you can have multiple such targets.
2107 We'll start by looking at how to examine the targets you have,
2108 then look at how to add one more target and how to configure it.
2110 @section Target List
2112 All targets that have been set up are part of a list,
2113 where each member has a name.
2114 That name should normally be the same as the TAP name.
2115 You can display the list with the @command{targets}
2117 This display often has only one CPU; here's what it might
2118 look like with more than one:
2120 CmdName Type Endian AbsChainPos Name State
2121 -- ---------- ---------- ---------- ----------- ------------- ----------
2122 0: rm9200.cpu arm920t little 2 rm9200.cpu running
2123 1: MyTarget cortex_m3 little 0 mychip.cpu halted
2126 One member of that list is the @dfn{current target}, which
2127 is implicitly referenced by many commands.
2128 In particular, memory addresses often refer to the address
2129 space seen by that current target.
2130 Commands like @command{mdw} (memory display words)
2131 and @command{flash erase_address} (erase NOR flash blocks)
2132 are examples; and there are many more.
2134 Several commands let you examine the list of targets:
2136 @deffn Command {target count}
2137 Returns the number of targets, @math{N}.
2138 The highest numbered target is @math{N - 1}.
2140 set c [target count]
2141 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
2142 # Assuming you have created this function
2143 print_target_details $x
2148 @deffn Command {target current}
2149 Returns the name of the current target.
2152 @deffn Command {target names}
2153 Lists the names of all current targets in the list.
2155 foreach t [target names] @{
2156 puts [format "Target: %s\n" $t]
2161 @deffn Command {target number} number
2162 The list of targets is numbered starting at zero.
2163 This command returns the name of the target at index @var{number}.
2165 set thename [target number $x]
2166 puts [format "Target %d is: %s\n" $x $thename]
2170 @c yep, "target list" would have been better.
2171 @c plus maybe "target setdefault".
2173 @deffn Command targets [name]
2174 @emph{Note: the name of this command is plural. Other target
2175 command names are singular.}
2177 With no parameter, this command displays a table of all known
2178 targets in a user friendly form.
2180 With a parameter, this command sets the current target to
2181 the given target with the given @var{name}; this is
2182 only relevant on boards which have more than one target.
2185 @section Target CPU Types and Variants
2187 Each target has a @dfn{CPU type}, as shown in the output of
2188 the @command{targets} command. You need to specify that type
2189 when calling @command{target create}.
2190 The CPU type indicates more than just the instruction set.
2191 It also indicates how that instruction set is implemented,
2192 what kind of debug support it integrates,
2193 whether it has an MMU (and if so, what kind),
2194 what core-specific commands may be available
2195 (@pxref{Architecture and Core Commands}),
2198 For some CPU types, OpenOCD also defines @dfn{variants} which
2199 indicate differences that affect their handling.
2200 For example, a particular implementation bug might need to be
2201 worked around in some chip versions.
2203 It's easy to see what target types are supported,
2204 since there's a command to list them.
2205 However, there is currently no way to list what target variants
2206 are supported (other than by reading the OpenOCD source code).
2208 @anchor{target types}
2209 @deffn Command {target types}
2210 Lists all supported target types.
2211 At this writing, the supported CPU types and variants are:
2214 @item @code{arm11} -- this is a generation of ARMv6 cores
2215 @item @code{arm720t} -- this is an ARMv4 core
2216 @item @code{arm7tdmi} -- this is an ARMv4 core
2217 @item @code{arm920t} -- this is an ARMv5 core
2218 @item @code{arm926ejs} -- this is an ARMv5 core
2219 @item @code{arm966e} -- this is an ARMv5 core
2220 @item @code{arm9tdmi} -- this is an ARMv4 core
2221 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
2222 (Support for this is preliminary and incomplete.)
2223 @item @code{cortex_a8} -- this is an ARMv7 core
2224 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
2225 compact Thumb2 instruction set. It supports one variant:
2227 @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
2228 This will cause OpenOCD to use a software reset rather than asserting
2229 SRST, to avoid a issue with clearing the debug registers.
2230 This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
2231 be detected and the normal reset behaviour used.
2233 @item @code{feroceon} -- resembles arm926
2234 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
2236 @item @code{ejtag_srst} ... Use this when debugging targets that do not
2237 provide a functional SRST line on the EJTAG connector. This causes
2238 OpenOCD to instead use an EJTAG software reset command to reset the
2240 You still need to enable @option{srst} on the @command{reset_config}
2241 command to enable OpenOCD hardware reset functionality.
2243 @item @code{xscale} -- this is actually an architecture,
2244 not a CPU type. It is based on the ARMv5 architecture.
2245 There are several variants defined:
2247 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
2248 @code{pxa27x} ... instruction register length is 7 bits
2249 @item @code{pxa250}, @code{pxa255},
2250 @code{pxa26x} ... instruction register length is 5 bits
2255 To avoid being confused by the variety of ARM based cores, remember
2256 this key point: @emph{ARM is a technology licencing company}.
2257 (See: @url{http://www.arm.com}.)
2258 The CPU name used by OpenOCD will reflect the CPU design that was
2259 licenced, not a vendor brand which incorporates that design.
2260 Name prefixes like arm7, arm9, arm11, and cortex
2261 reflect design generations;
2262 while names like ARMv4, ARMv5, ARMv6, and ARMv7
2263 reflect an architecture version implemented by a CPU design.
2265 @anchor{Target Configuration}
2266 @section Target Configuration
2268 Before creating a ``target'', you must have added its TAP to the scan chain.
2269 When you've added that TAP, you will have a @code{dotted.name}
2270 which is used to set up the CPU support.
2271 The chip-specific configuration file will normally configure its CPU(s)
2272 right after it adds all of the chip's TAPs to the scan chain.
2274 Although you can set up a target in one step, it's often clearer if you
2275 use shorter commands and do it in two steps: create it, then configure
2277 All operations on the target after it's created will use a new
2278 command, created as part of target creation.
2280 The two main things to configure after target creation are
2281 a work area, which usually has target-specific defaults even
2282 if the board setup code overrides them later;
2283 and event handlers (@pxref{Target Events}), which tend
2284 to be much more board-specific.
2285 The key steps you use might look something like this
2288 target create MyTarget cortex_m3 -chain-position mychip.cpu
2289 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
2290 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
2291 $MyTarget configure -event reset-init @{ myboard_reinit @}
2294 You should specify a working area if you can; typically it uses some
2296 Such a working area can speed up many things, including bulk
2297 writes to target memory;
2298 flash operations like checking to see if memory needs to be erased;
2299 GDB memory checksumming;
2303 On more complex chips, the work area can become
2304 inaccessible when application code
2305 (such as an operating system)
2306 enables or disables the MMU.
2307 For example, the particular MMU context used to acess the virtual
2308 address will probably matter ... and that context might not have
2309 easy access to other addresses needed.
2310 At this writing, OpenOCD doesn't have much MMU intelligence.
2313 It's often very useful to define a @code{reset-init} event handler.
2314 For systems that are normally used with a boot loader,
2315 common tasks include updating clocks and initializing memory
2317 That may be needed to let you write the boot loader into flash,
2318 in order to ``de-brick'' your board; or to load programs into
2319 external DDR memory without having run the boot loader.
2321 @deffn Command {target create} target_name type configparams...
2322 This command creates a GDB debug target that refers to a specific JTAG tap.
2323 It enters that target into a list, and creates a new
2324 command (@command{@var{target_name}}) which is used for various
2325 purposes including additional configuration.
2328 @item @var{target_name} ... is the name of the debug target.
2329 By convention this should be the same as the @emph{dotted.name}
2330 of the TAP associated with this target, which must be specified here
2331 using the @code{-chain-position @var{dotted.name}} configparam.
2333 This name is also used to create the target object command,
2334 referred to here as @command{$target_name},
2335 and in other places the target needs to be identified.
2336 @item @var{type} ... specifies the target type. @xref{target types}.
2337 @item @var{configparams} ... all parameters accepted by
2338 @command{$target_name configure} are permitted.
2339 If the target is big-endian, set it here with @code{-endian big}.
2340 If the variant matters, set it here with @code{-variant}.
2342 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
2346 @deffn Command {$target_name configure} configparams...
2347 The options accepted by this command may also be
2348 specified as parameters to @command{target create}.
2349 Their values can later be queried one at a time by
2350 using the @command{$target_name cget} command.
2352 @emph{Warning:} changing some of these after setup is dangerous.
2353 For example, moving a target from one TAP to another;
2354 and changing its endianness or variant.
2358 @item @code{-chain-position} @var{dotted.name} -- names the TAP
2359 used to access this target.
2361 @item @code{-endian} (@option{big}|@option{little}) -- specifies
2362 whether the CPU uses big or little endian conventions
2364 @item @code{-event} @var{event_name} @var{event_body} --
2365 @xref{Target Events}.
2366 Note that this updates a list of named event handlers.
2367 Calling this twice with two different event names assigns
2368 two different handlers, but calling it twice with the
2369 same event name assigns only one handler.
2371 @item @code{-variant} @var{name} -- specifies a variant of the target,
2372 which OpenOCD needs to know about.
2374 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
2375 whether the work area gets backed up; by default, it doesn't.
2376 When possible, use a working_area that doesn't need to be backed up,
2377 since performing a backup slows down operations.
2379 @item @code{-work-area-size} @var{size} -- specify/set the work area
2381 @item @code{-work-area-phys} @var{address} -- set the work area
2382 base @var{address} to be used when no MMU is active.
2384 @item @code{-work-area-virt} @var{address} -- set the work area
2385 base @var{address} to be used when an MMU is active.
2390 @section Other $target_name Commands
2391 @cindex object command
2393 The Tcl/Tk language has the concept of object commands,
2394 and OpenOCD adopts that same model for targets.
2396 A good Tk example is a on screen button.
2397 Once a button is created a button
2398 has a name (a path in Tk terms) and that name is useable as a first
2399 class command. For example in Tk, one can create a button and later
2400 configure it like this:
2404 button .foobar -background red -command @{ foo @}
2406 .foobar configure -foreground blue
2408 set x [.foobar cget -background]
2410 puts [format "The button is %s" $x]
2413 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
2414 button, and its object commands are invoked the same way.
2417 str912.cpu mww 0x1234 0x42
2418 omap3530.cpu mww 0x5555 123
2421 The commands supported by OpenOCD target objects are:
2423 @deffn Command {$target_name arp_examine}
2424 @deffnx Command {$target_name arp_halt}
2425 @deffnx Command {$target_name arp_poll}
2426 @deffnx Command {$target_name arp_reset}
2427 @deffnx Command {$target_name arp_waitstate}
2428 Internal OpenOCD scripts (most notably @file{startup.tcl})
2429 use these to deal with specific reset cases.
2430 They are not otherwise documented here.
2433 @deffn Command {$target_name array2mem} arrayname width address count
2434 @deffnx Command {$target_name mem2array} arrayname width address count
2435 These provide an efficient script-oriented interface to memory.
2436 The @code{array2mem} primitive writes bytes, halfwords, or words;
2437 while @code{mem2array} reads them.
2438 In both cases, the TCL side uses an array, and
2439 the target side uses raw memory.
2441 The efficiency comes from enabling the use of
2442 bulk JTAG data transfer operations.
2443 The script orientation comes from working with data
2444 values that are packaged for use by TCL scripts;
2445 @command{mdw} type primitives only print data they retrieve,
2446 and neither store nor return those values.
2449 @item @var{arrayname} ... is the name of an array variable
2450 @item @var{width} ... is 8/16/32 - indicating the memory access size
2451 @item @var{address} ... is the target memory address
2452 @item @var{count} ... is the number of elements to process
2456 @deffn Command {$target_name cget} queryparm
2457 Each configuration parameter accepted by
2458 @command{$target_name configure}
2459 can be individually queried, to return its current value.
2460 The @var{queryparm} is a parameter name
2461 accepted by that command, such as @code{-work-area-phys}.
2462 There are a few special cases:
2465 @item @code{-event} @var{event_name} -- returns the handler for the
2466 event named @var{event_name}.
2467 This is a special case because setting a handler requires
2469 @item @code{-type} -- returns the target type.
2470 This is a special case because this is set using
2471 @command{target create} and can't be changed
2472 using @command{$target_name configure}.
2475 For example, if you wanted to summarize information about
2476 all the targets you might use something like this:
2479 for @{ set x 0 @} @{ $x < [target count] @} @{ incr x @} @{
2480 set name [target number $x]
2481 set y [$name cget -endian]
2482 set z [$name cget -type]
2483 puts [format "Chip %d is %s, Endian: %s, type: %s" \
2489 @deffn Command {$target_name curstate}
2490 Displays the current target state:
2491 @code{debug-running},
2494 @code{running}, or @code{unknown}.
2497 @deffn Command {$target_name eventlist}
2498 Displays a table listing all event handlers
2499 currently associated with this target.
2500 @xref{Target Events}.
2503 @deffn Command {$target_name invoke-event} event_name
2504 Invokes the handler for the event named @var{event_name}.
2505 (This is primarily intended for use by OpenOCD framework
2506 code, for example by the reset code in @file{startup.tcl}.)
2509 @deffn Command {$target_name mdw} addr [count]
2510 @deffnx Command {$target_name mdh} addr [count]
2511 @deffnx Command {$target_name mdb} addr [count]
2512 Display contents of address @var{addr}, as
2513 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
2514 or 8-bit bytes (@command{mdb}).
2515 If @var{count} is specified, displays that many units.
2516 (If you want to manipulate the data instead of displaying it,
2517 see the @code{mem2array} primitives.)
2520 @deffn Command {$target_name mww} addr word
2521 @deffnx Command {$target_name mwh} addr halfword
2522 @deffnx Command {$target_name mwb} addr byte
2523 Writes the specified @var{word} (32 bits),
2524 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
2525 at the specified address @var{addr}.
2528 @anchor{Target Events}
2529 @section Target Events
2531 At various times, certain things can happen, or you want them to happen.
2534 @item What should happen when GDB connects? Should your target reset?
2535 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
2536 @item During reset, do you need to write to certain memory locations
2537 to set up system clocks or
2538 to reconfigure the SDRAM?
2541 All of the above items can be addressed by target event handlers.
2542 These are set up by @command{$target_name configure -event} or
2543 @command{target create ... -event}.
2545 The programmer's model matches the @code{-command} option used in Tcl/Tk
2546 buttons and events. The two examples below act the same, but one creates
2547 and invokes a small procedure while the other inlines it.
2550 proc my_attach_proc @{ @} @{
2554 mychip.cpu configure -event gdb-attach my_attach_proc
2555 mychip.cpu configure -event gdb-attach @{
2561 The following target events are defined:
2564 @item @b{debug-halted}
2565 @* The target has halted for debug reasons (i.e.: breakpoint)
2566 @item @b{debug-resumed}
2567 @* The target has resumed (i.e.: gdb said run)
2568 @item @b{early-halted}
2569 @* Occurs early in the halt process
2570 @item @b{examine-end}
2571 @* Currently not used (goal: when JTAG examine completes)
2572 @item @b{examine-start}
2573 @* Currently not used (goal: when JTAG examine starts)
2574 @item @b{gdb-attach}
2575 @* When GDB connects
2576 @item @b{gdb-detach}
2577 @* When GDB disconnects
2579 @* When the taret has halted and GDB is not doing anything (see early halt)
2580 @item @b{gdb-flash-erase-start}
2581 @* Before the GDB flash process tries to erase the flash
2582 @item @b{gdb-flash-erase-end}
2583 @* After the GDB flash process has finished erasing the flash
2584 @item @b{gdb-flash-write-start}
2585 @* Before GDB writes to the flash
2586 @item @b{gdb-flash-write-end}
2587 @* After GDB writes to the flash
2589 @* Before the taret steps, gdb is trying to start/resume the target
2591 @* The target has halted
2592 @item @b{old-gdb_program_config}
2593 @* DO NOT USE THIS: Used internally
2594 @item @b{old-pre_resume}
2595 @* DO NOT USE THIS: Used internally
2596 @item @b{reset-assert-pre}
2597 @* Issued as part of @command{reset} processing
2598 after SRST and/or TRST were activated and deactivated,
2599 but before reset is asserted on the tap.
2600 @item @b{reset-assert-post}
2601 @* Issued as part of @command{reset} processing
2602 when reset is asserted on the tap.
2603 @item @b{reset-deassert-pre}
2604 @* Issued as part of @command{reset} processing
2605 when reset is about to be released on the tap.
2607 For some chips, this may be a good place to make sure
2608 the JTAG clock is slow enough to work before the PLL
2609 has been set up to allow faster JTAG speeds.
2610 @item @b{reset-deassert-post}
2611 @* Issued as part of @command{reset} processing
2612 when reset has been released on the tap.
2614 @* Issued as the final step in @command{reset} processing.
2615 @item @b{reset-halt-post}
2616 @* Currently not usd
2617 @item @b{reset-halt-pre}
2618 @* Currently not used
2619 @item @b{reset-init}
2620 @* Used by @b{reset init} command for board-specific initialization.
2621 This event fires after @emph{reset-deassert-post}.
2623 This is where you would configure PLLs and clocking, set up DRAM so
2624 you can download programs that don't fit in on-chip SRAM, set up pin
2625 multiplexing, and so on.
2626 @item @b{reset-start}
2627 @* Issued as part of @command{reset} processing
2628 before either SRST or TRST are activated.
2629 @item @b{reset-wait-pos}
2630 @* Currently not used
2631 @item @b{reset-wait-pre}
2632 @* Currently not used
2633 @item @b{resume-start}
2634 @* Before any target is resumed
2635 @item @b{resume-end}
2636 @* After all targets have resumed
2640 @* Target has resumed
2644 @node Flash Commands
2645 @chapter Flash Commands
2647 OpenOCD has different commands for NOR and NAND flash;
2648 the ``flash'' command works with NOR flash, while
2649 the ``nand'' command works with NAND flash.
2650 This partially reflects different hardware technologies:
2651 NOR flash usually supports direct CPU instruction and data bus access,
2652 while data from a NAND flash must be copied to memory before it can be
2653 used. (SPI flash must also be copied to memory before use.)
2654 However, the documentation also uses ``flash'' as a generic term;
2655 for example, ``Put flash configuration in board-specific files''.
2658 As of 28-nov-2008 OpenOCD does not know how to program a SPI
2659 flash that a micro may boot from. Perhaps you, the reader, would like to
2660 contribute support for this.
2665 @item Configure via the command @command{flash bank}
2666 @* Do this in a board-specific configuration file,
2667 passing parameters as needed by the driver.
2668 @item Operate on the flash via @command{flash subcommand}
2669 @* Often commands to manipulate the flash are typed by a human, or run
2670 via a script in some automated way. Common tasks include writing a
2671 boot loader, operating system, or other data.
2673 @* Flashing via GDB requires the flash be configured via ``flash
2674 bank'', and the GDB flash features be enabled.
2675 @xref{GDB Configuration}.
2678 Many CPUs have the ablity to ``boot'' from the first flash bank.
2679 This means that misprograming that bank can ``brick'' a system,
2680 so that it can't boot.
2681 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
2682 board by (re)installing working boot firmware.
2684 @section Flash Configuration Commands
2685 @cindex flash configuration
2687 @deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
2688 Configures a flash bank which provides persistent storage
2689 for addresses from @math{base} to @math{base + size - 1}.
2690 These banks will often be visible to GDB through the target's memory map.
2691 In some cases, configuring a flash bank will activate extra commands;
2692 see the driver-specific documentation.
2695 @item @var{driver} ... identifies the controller driver
2696 associated with the flash bank being declared.
2697 This is usually @code{cfi} for external flash, or else
2698 the name of a microcontroller with embedded flash memory.
2699 @xref{Flash Driver List}.
2700 @item @var{base} ... Base address of the flash chip.
2701 @item @var{size} ... Size of the chip, in bytes.
2702 For some drivers, this value is detected from the hardware.
2703 @item @var{chip_width} ... Width of the flash chip, in bytes;
2704 ignored for most microcontroller drivers.
2705 @item @var{bus_width} ... Width of the data bus used to access the
2706 chip, in bytes; ignored for most microcontroller drivers.
2707 @item @var{target} ... Names the target used to issue
2708 commands to the flash controller.
2709 @comment Actually, it's currently a controller-specific parameter...
2710 @item @var{driver_options} ... drivers may support, or require,
2711 additional parameters. See the driver-specific documentation
2712 for more information.
2715 This command is not available after OpenOCD initialization has completed.
2716 Use it in board specific configuration files, not interactively.
2720 @comment the REAL name for this command is "ocd_flash_banks"
2721 @comment less confusing would be: "flash list" (like "nand list")
2722 @deffn Command {flash banks}
2723 Prints a one-line summary of each device declared
2724 using @command{flash bank}, numbered from zero.
2725 Note that this is the @emph{plural} form;
2726 the @emph{singular} form is a very different command.
2729 @deffn Command {flash probe} num
2730 Identify the flash, or validate the parameters of the configured flash. Operation
2731 depends on the flash type.
2732 The @var{num} parameter is a value shown by @command{flash banks}.
2733 Most flash commands will implicitly @emph{autoprobe} the bank;
2734 flash drivers can distinguish between probing and autoprobing,
2735 but most don't bother.
2738 @section Erasing, Reading, Writing to Flash
2739 @cindex flash erasing
2740 @cindex flash reading
2741 @cindex flash writing
2742 @cindex flash programming
2744 One feature distinguishing NOR flash from NAND or serial flash technologies
2745 is that for read access, it acts exactly like any other addressible memory.
2746 This means you can use normal memory read commands like @command{mdw} or
2747 @command{dump_image} with it, with no special @command{flash} subcommands.
2748 @xref{Memory access}, and @ref{Image access}.
2750 Write access works differently. Flash memory normally needs to be erased
2751 before it's written. Erasing a sector turns all of its bits to ones, and
2752 writing can turn ones into zeroes. This is why there are special commands
2753 for interactive erasing and writing, and why GDB needs to know which parts
2754 of the address space hold NOR flash memory.
2757 Most of these erase and write commands leverage the fact that NOR flash
2758 chips consume target address space. They implicitly refer to the current
2759 JTAG target, and map from an address in that target's address space
2760 back to a flash bank.
2761 @comment In May 2009, those mappings may fail if any bank associated
2762 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
2763 A few commands use abstract addressing based on bank and sector numbers,
2764 and don't depend on searching the current target and its address space.
2765 Avoid confusing the two command models.
2768 Some flash chips implement software protection against accidental writes,
2769 since such buggy writes could in some cases ``brick'' a system.
2770 For such systems, erasing and writing may require sector protection to be
2772 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
2773 and AT91SAM7 on-chip flash.
2774 @xref{flash protect}.
2776 @anchor{flash erase_sector}
2777 @deffn Command {flash erase_sector} num first last
2778 Erase sectors in bank @var{num}, starting at sector @var{first} up to and including
2779 @var{last}. Sector numbering starts at 0.
2780 The @var{num} parameter is a value shown by @command{flash banks}.
2783 @deffn Command {flash erase_address} address length
2784 Erase sectors starting at @var{address} for @var{length} bytes.
2785 The flash bank to use is inferred from the @var{address}, and
2786 the specified length must stay within that bank.
2787 As a special case, when @var{length} is zero and @var{address} is
2788 the start of the bank, the whole flash is erased.
2791 @deffn Command {flash fillw} address word length
2792 @deffnx Command {flash fillh} address halfword length
2793 @deffnx Command {flash fillb} address byte length
2794 Fills flash memory with the specified @var{word} (32 bits),
2795 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
2796 starting at @var{address} and continuing
2797 for @var{length} units (word/halfword/byte).
2798 No erasure is done before writing; when needed, that must be done
2799 before issuing this command.
2800 Writes are done in blocks of up to 1024 bytes, and each write is
2801 verified by reading back the data and comparing it to what was written.
2802 The flash bank to use is inferred from the @var{address} of
2803 each block, and the specified length must stay within that bank.
2805 @comment no current checks for errors if fill blocks touch multiple banks!
2807 @anchor{flash write_bank}
2808 @deffn Command {flash write_bank} num filename offset
2809 Write the binary @file{filename} to flash bank @var{num},
2810 starting at @var{offset} bytes from the beginning of the bank.
2811 The @var{num} parameter is a value shown by @command{flash banks}.
2814 @anchor{flash write_image}
2815 @deffn Command {flash write_image} [erase] filename [offset] [type]
2816 Write the image @file{filename} to the current target's flash bank(s).
2817 A relocation @var{offset} may be specified, in which case it is added
2818 to the base address for each section in the image.
2819 The file [@var{type}] can be specified
2820 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
2821 @option{elf} (ELF file), @option{s19} (Motorola s19).
2822 @option{mem}, or @option{builder}.
2823 The relevant flash sectors will be erased prior to programming
2824 if the @option{erase} parameter is given.
2825 The flash bank to use is inferred from the @var{address} of
2829 @section Other Flash commands
2830 @cindex flash protection
2832 @deffn Command {flash erase_check} num
2833 Check erase state of sectors in flash bank @var{num},
2834 and display that status.
2835 The @var{num} parameter is a value shown by @command{flash banks}.
2836 This is the only operation that
2837 updates the erase state information displayed by @option{flash info}. That means you have
2838 to issue an @command{flash erase_check} command after erasing or programming the device
2839 to get updated information.
2840 (Code execution may have invalidated any state records kept by OpenOCD.)
2843 @deffn Command {flash info} num
2844 Print info about flash bank @var{num}
2845 The @var{num} parameter is a value shown by @command{flash banks}.
2846 The information includes per-sector protect status.
2849 @anchor{flash protect}
2850 @deffn Command {flash protect} num first last (on|off)
2851 Enable (@var{on}) or disable (@var{off}) protection of flash sectors
2852 @var{first} to @var{last} of flash bank @var{num}.
2853 The @var{num} parameter is a value shown by @command{flash banks}.
2856 @deffn Command {flash protect_check} num
2857 Check protection state of sectors in flash bank @var{num}.
2858 The @var{num} parameter is a value shown by @command{flash banks}.
2859 @comment @option{flash erase_sector} using the same syntax.
2862 @anchor{Flash Driver List}
2863 @section Flash Drivers, Options, and Commands
2864 As noted above, the @command{flash bank} command requires a driver name,
2865 and allows driver-specific options and behaviors.
2866 Some drivers also activate driver-specific commands.
2868 @subsection External Flash
2870 @deffn {Flash Driver} cfi
2871 @cindex Common Flash Interface
2873 The ``Common Flash Interface'' (CFI) is the main standard for
2874 external NOR flash chips, each of which connects to a
2875 specific external chip select on the CPU.
2876 Frequently the first such chip is used to boot the system.
2877 Your board's @code{reset-init} handler might need to
2878 configure additional chip selects using other commands (like: @command{mww} to
2879 configure a bus and its timings) , or
2880 perhaps configure a GPIO pin that controls the ``write protect'' pin
2882 The CFI driver can use a target-specific working area to significantly
2885 The CFI driver can accept the following optional parameters, in any order:
2888 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
2889 like AM29LV010 and similar types.
2890 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
2893 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
2894 wide on a sixteen bit bus:
2897 flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
2898 flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
2902 @subsection Internal Flash (Microcontrollers)
2904 @deffn {Flash Driver} aduc702x
2905 The ADUC702x analog microcontrollers from ST Micro
2906 include internal flash and use ARM7TDMI cores.
2907 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
2908 The setup command only requires the @var{target} argument
2909 since all devices in this family have the same memory layout.
2912 flash bank aduc702x 0 0 0 0 $_TARGETNAME
2916 @deffn {Flash Driver} at91sam7
2917 All members of the AT91SAM7 microcontroller family from Atmel
2918 include internal flash and use ARM7TDMI cores.
2919 The driver automatically recognizes a number of these chips using
2920 the chip identification register, and autoconfigures itself.
2923 flash bank at91sam7 0 0 0 0 $_TARGETNAME
2926 For chips which are not recognized by the controller driver, you must
2927 provide additional parameters in the following order:
2930 @item @var{chip_model} ... label used with @command{flash info}
2932 @item @var{sectors_per_bank}
2933 @item @var{pages_per_sector}
2934 @item @var{pages_size}
2935 @item @var{num_nvm_bits}
2936 @item @var{freq_khz} ... required if an external clock is provided,
2937 optional (but recommended) when the oscillator frequency is known
2940 It is recommended that you provide zeroes for all of those values
2941 except the clock frequency, so that everything except that frequency
2942 will be autoconfigured.
2943 Knowing the frequency helps ensure correct timings for flash access.
2945 The flash controller handles erases automatically on a page (128/256 byte)
2946 basis, so explicit erase commands are not necessary for flash programming.
2947 However, there is an ``EraseAll`` command that can erase an entire flash
2948 plane (of up to 256KB), and it will be used automatically when you issue
2949 @command{flash erase_sector} or @command{flash erase_address} commands.
2951 @deffn Command {at91sam7 gpnvm} bitnum (set|clear)
2952 Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
2953 bit for the processor. Each processor has a number of such bits,
2954 used for controlling features such as brownout detection (so they
2955 are not truly general purpose).
2957 This assumes that the first flash bank (number 0) is associated with
2958 the appropriate at91sam7 target.
2963 @deffn {Flash Driver} avr
2964 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
2965 @emph{The current implementation is incomplete.}
2966 @comment - defines mass_erase ... pointless given flash_erase_address
2969 @deffn {Flash Driver} ecosflash
2970 @emph{No idea what this is...}
2971 The @var{ecosflash} driver defines one mandatory parameter,
2972 the name of a modules of target code which is downloaded
2976 @deffn {Flash Driver} lpc2000
2977 Most members of the LPC2000 microcontroller family from NXP
2978 include internal flash and use ARM7TDMI cores.
2979 The @var{lpc2000} driver defines two mandatory and one optional parameters,
2980 which must appear in the following order:
2983 @item @var{variant} ... required, may be
2984 @var{lpc2000_v1} (older LPC21xx and LPC22xx)
2985 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
2986 @item @var{clock_kHz} ... the frequency, in kiloHertz,
2987 at which the core is running
2988 @item @var{calc_checksum} ... optional (but you probably want to provide this!),
2989 telling the driver to calculate a valid checksum for the exception vector table.
2992 LPC flashes don't require the chip and bus width to be specified.
2995 flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
2996 lpc2000_v2 14765 calc_checksum
3000 @deffn {Flash Driver} lpc288x
3001 The LPC2888 microcontroller from NXP needs slightly different flash
3002 support from its lpc2000 siblings.
3003 The @var{lpc288x} driver defines one mandatory parameter,
3004 the programming clock rate in Hz.
3005 LPC flashes don't require the chip and bus width to be specified.
3008 flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
3012 @deffn {Flash Driver} ocl
3013 @emph{No idea what this is, other than using some arm7/arm9 core.}
3016 flash bank ocl 0 0 0 0 $_TARGETNAME
3020 @deffn {Flash Driver} pic32mx
3021 The PIC32MX microcontrollers are based on the MIPS 4K cores,
3022 and integrate flash memory.
3023 @emph{The current implementation is incomplete.}
3026 flash bank pix32mx 0 0 0 0 $_TARGETNAME
3029 @comment numerous *disabled* commands are defined:
3030 @comment - chip_erase ... pointless given flash_erase_address
3031 @comment - lock, unlock ... pointless given protect on/off (yes?)
3032 @comment - pgm_word ... shouldn't bank be deduced from address??
3033 Some pic32mx-specific commands are defined:
3034 @deffn Command {pic32mx pgm_word} address value bank
3035 Programs the specified 32-bit @var{value} at the given @var{address}
3036 in the specified chip @var{bank}.
3040 @deffn {Flash Driver} stellaris
3041 All members of the Stellaris LM3Sxxx microcontroller family from
3043 include internal flash and use ARM Cortex M3 cores.
3044 The driver automatically recognizes a number of these chips using
3045 the chip identification register, and autoconfigures itself.
3046 @footnote{Currently there is a @command{stellaris mass_erase} command.
3047 That seems pointless since the same effect can be had using the
3048 standard @command{flash erase_address} command.}
3051 flash bank stellaris 0 0 0 0 $_TARGETNAME
3055 @deffn {Flash Driver} stm32x
3056 All members of the STM32 microcontroller family from ST Microelectronics
3057 include internal flash and use ARM Cortex M3 cores.
3058 The driver automatically recognizes a number of these chips using
3059 the chip identification register, and autoconfigures itself.
3062 flash bank stm32x 0 0 0 0 $_TARGETNAME
3065 Some stm32x-specific commands
3066 @footnote{Currently there is a @command{stm32x mass_erase} command.
3067 That seems pointless since the same effect can be had using the
3068 standard @command{flash erase_address} command.}
3071 @deffn Command {stm32x lock} num
3072 Locks the entire stm32 device.
3073 The @var{num} parameter is a value shown by @command{flash banks}.
3076 @deffn Command {stm32x unlock} num
3077 Unlocks the entire stm32 device.
3078 The @var{num} parameter is a value shown by @command{flash banks}.
3081 @deffn Command {stm32x options_read} num
3082 Read and display the stm32 option bytes written by
3083 the @command{stm32x options_write} command.
3084 The @var{num} parameter is a value shown by @command{flash banks}.
3087 @deffn Command {stm32x options_write} num (SWWDG|HWWDG) (RSTSTNDBY|NORSTSTNDBY) (RSTSTOP|NORSTSTOP)
3088 Writes the stm32 option byte with the specified values.
3089 The @var{num} parameter is a value shown by @command{flash banks}.
3093 @deffn {Flash Driver} str7x
3094 All members of the STR7 microcontroller family from ST Microelectronics
3095 include internal flash and use ARM7TDMI cores.
3096 The @var{str7x} driver defines one mandatory parameter, @var{variant},
3097 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
3100 flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
3104 @deffn {Flash Driver} str9x
3105 Most members of the STR9 microcontroller family from ST Microelectronics
3106 include internal flash and use ARM966E cores.
3107 The str9 needs the flash controller to be configured using
3108 the @command{str9x flash_config} command prior to Flash programming.
3111 flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
3112 str9x flash_config 0 4 2 0 0x80000
3115 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
3116 Configures the str9 flash controller.
3117 The @var{num} parameter is a value shown by @command{flash banks}.
3120 @item @var{bbsr} - Boot Bank Size register
3121 @item @var{nbbsr} - Non Boot Bank Size register
3122 @item @var{bbadr} - Boot Bank Start Address register
3123 @item @var{nbbadr} - Boot Bank Start Address register
3129 @deffn {Flash Driver} tms470
3130 Most members of the TMS470 microcontroller family from Texas Instruments
3131 include internal flash and use ARM7TDMI cores.
3132 This driver doesn't require the chip and bus width to be specified.
3134 Some tms470-specific commands are defined:
3136 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
3137 Saves programming keys in a register, to enable flash erase and write commands.
3140 @deffn Command {tms470 osc_mhz} clock_mhz
3141 Reports the clock speed, which is used to calculate timings.
3144 @deffn Command {tms470 plldis} (0|1)
3145 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
3150 @subsection str9xpec driver
3153 Here is some background info to help
3154 you better understand how this driver works. OpenOCD has two flash drivers for
3158 Standard driver @option{str9x} programmed via the str9 core. Normally used for
3159 flash programming as it is faster than the @option{str9xpec} driver.
3161 Direct programming @option{str9xpec} using the flash controller. This is an
3162 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
3163 core does not need to be running to program using this flash driver. Typical use
3164 for this driver is locking/unlocking the target and programming the option bytes.
3167 Before we run any commands using the @option{str9xpec} driver we must first disable
3168 the str9 core. This example assumes the @option{str9xpec} driver has been
3169 configured for flash bank 0.
3171 # assert srst, we do not want core running
3172 # while accessing str9xpec flash driver
3174 # turn off target polling
3177 str9xpec enable_turbo 0
3179 str9xpec options_read 0
3180 # re-enable str9 core
3181 str9xpec disable_turbo 0
3185 The above example will read the str9 option bytes.
3186 When performing a unlock remember that you will not be able to halt the str9 - it
3187 has been locked. Halting the core is not required for the @option{str9xpec} driver
3188 as mentioned above, just issue the commands above manually or from a telnet prompt.
3190 @deffn {Flash Driver} str9xpec
3191 Only use this driver for locking/unlocking the device or configuring the option bytes.
3192 Use the standard str9 driver for programming.
3193 Before using the flash commands the turbo mode must be enabled using the
3194 @command{str9xpec enable_turbo} command.
3196 Several str9xpec-specific commands are defined:
3198 @deffn Command {str9xpec disable_turbo} num
3199 Restore the str9 into JTAG chain.
3202 @deffn Command {str9xpec enable_turbo} num
3203 Enable turbo mode, will simply remove the str9 from the chain and talk
3204 directly to the embedded flash controller.
3207 @deffn Command {str9xpec lock} num
3208 Lock str9 device. The str9 will only respond to an unlock command that will
3212 @deffn Command {str9xpec part_id} num
3213 Prints the part identifier for bank @var{num}.
3216 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
3217 Configure str9 boot bank.
3220 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
3221 Configure str9 lvd source.
3224 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
3225 Configure str9 lvd threshold.
3228 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
3229 Configure str9 lvd reset warning source.
3232 @deffn Command {str9xpec options_read} num
3233 Read str9 option bytes.
3236 @deffn Command {str9xpec options_write} num
3237 Write str9 option bytes.
3240 @deffn Command {str9xpec unlock} num
3249 @subsection mFlash Configuration
3250 @cindex mFlash Configuration
3252 @deffn {Config Command} {mflash bank} soc base RST_pin target
3253 Configures a mflash for @var{soc} host bank at
3255 The pin number format depends on the host GPIO naming convention.
3256 Currently, the mflash driver supports s3c2440 and pxa270.
3258 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
3261 mflash bank s3c2440 0x10000000 1b 0
3264 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
3267 mflash bank pxa270 0x08000000 43 0
3271 @subsection mFlash commands
3272 @cindex mFlash commands
3274 @deffn Command {mflash config pll} frequency
3275 Configure mflash PLL.
3276 The @var{frequency} is the mflash input frequency, in Hz.
3277 Issuing this command will erase mflash's whole internal nand and write new pll.
3278 After this command, mflash needs power-on-reset for normal operation.
3279 If pll was newly configured, storage and boot(optional) info also need to be update.
3282 @deffn Command {mflash config boot}
3283 Configure bootable option.
3284 If bootable option is set, mflash offer the first 8 sectors
3288 @deffn Command {mflash config storage}
3289 Configure storage information.
3290 For the normal storage operation, this information must be
3294 @deffn Command {mflash dump} num filename offset size
3295 Dump @var{size} bytes, starting at @var{offset} bytes from the
3296 beginning of the bank @var{num}, to the file named @var{filename}.
3299 @deffn Command {mflash probe}
3303 @deffn Command {mflash write} num filename offset
3304 Write the binary file @var{filename} to mflash bank @var{num}, starting at
3305 @var{offset} bytes from the beginning of the bank.
3308 @node NAND Flash Commands
3309 @chapter NAND Flash Commands
3312 Compared to NOR or SPI flash, NAND devices are inexpensive
3313 and high density. Today's NAND chips, and multi-chip modules,
3314 commonly hold multiple GigaBytes of data.
3316 NAND chips consist of a number of ``erase blocks'' of a given
3317 size (such as 128 KBytes), each of which is divided into a
3318 number of pages (of perhaps 512 or 2048 bytes each). Each
3319 page of a NAND flash has an ``out of band'' (OOB) area to hold
3320 Error Correcting Code (ECC) and other metadata, usually 16 bytes
3321 of OOB for every 512 bytes of page data.
3323 One key characteristic of NAND flash is that its error rate
3324 is higher than that of NOR flash. In normal operation, that
3325 ECC is used to correct and detect errors. However, NAND
3326 blocks can also wear out and become unusable; those blocks
3327 are then marked "bad". NAND chips are even shipped from the
3328 manufacturer with a few bad blocks. The highest density chips
3329 use a technology (MLC) that wears out more quickly, so ECC
3330 support is increasingly important as a way to detect blocks
3331 that have begun to fail, and help to preserve data integrity
3332 with techniques such as wear leveling.
3334 Software is used to manage the ECC. Some controllers don't
3335 support ECC directly; in those cases, software ECC is used.
3336 Other controllers speed up the ECC calculations with hardware.
3337 Single-bit error correction hardware is routine. Controllers
3338 geared for newer MLC chips may correct 4 or more errors for
3339 every 512 bytes of data.
3341 You will need to make sure that any data you write using
3342 OpenOCD includes the apppropriate kind of ECC. For example,
3343 that may mean passing the @code{oob_softecc} flag when
3344 writing NAND data, or ensuring that the correct hardware
3347 The basic steps for using NAND devices include:
3349 @item Declare via the command @command{nand device}
3350 @* Do this in a board-specific configuration file,
3351 passing parameters as needed by the controller.
3352 @item Configure each device using @command{nand probe}.
3353 @* Do this only after the associated target is set up,
3354 such as in its reset-init script or in procures defined
3355 to access that device.
3356 @item Operate on the flash via @command{nand subcommand}
3357 @* Often commands to manipulate the flash are typed by a human, or run
3358 via a script in some automated way. Common task include writing a
3359 boot loader, operating system, or other data needed to initialize or
3363 @b{NOTE:} At the time this text was written, the largest NAND
3364 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
3365 This is because the variables used to hold offsets and lengths
3366 are only 32 bits wide.
3367 (Larger chips may work in some cases, unless an offset or length
3368 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
3369 Some larger devices will work, since they are actually multi-chip
3370 modules with two smaller chips and individual chipselect lines.
3372 @section NAND Configuration Commands
3373 @cindex NAND configuration
3375 NAND chips must be declared in configuration scripts,
3376 plus some additional configuration that's done after
3377 OpenOCD has initialized.
3379 @deffn {Config Command} {nand device} controller target [configparams...]
3380 Declares a NAND device, which can be read and written to
3381 after it has been configured through @command{nand probe}.
3382 In OpenOCD, devices are single chips; this is unlike some
3383 operating systems, which may manage multiple chips as if
3384 they were a single (larger) device.
3385 In some cases, configuring a device will activate extra
3386 commands; see the controller-specific documentation.
3388 @b{NOTE:} This command is not available after OpenOCD
3389 initialization has completed. Use it in board specific
3390 configuration files, not interactively.
3393 @item @var{controller} ... identifies the controller driver
3394 associated with the NAND device being declared.
3395 @xref{NAND Driver List}.
3396 @item @var{target} ... names the target used when issuing
3397 commands to the NAND controller.
3398 @comment Actually, it's currently a controller-specific parameter...
3399 @item @var{configparams} ... controllers may support, or require,
3400 additional parameters. See the controller-specific documentation
3401 for more information.
3405 @deffn Command {nand list}
3406 Prints a one-line summary of each device declared
3407 using @command{nand device}, numbered from zero.
3408 Note that un-probed devices show no details.
3411 @deffn Command {nand probe} num
3412 Probes the specified device to determine key characteristics
3413 like its page and block sizes, and how many blocks it has.
3414 The @var{num} parameter is the value shown by @command{nand list}.
3415 You must (successfully) probe a device before you can use
3416 it with most other NAND commands.
3419 @section Erasing, Reading, Writing to NAND Flash
3421 @deffn Command {nand dump} num filename offset length [oob_option]
3422 @cindex NAND reading
3423 Reads binary data from the NAND device and writes it to the file,
3424 starting at the specified offset.
3425 The @var{num} parameter is the value shown by @command{nand list}.
3427 Use a complete path name for @var{filename}, so you don't depend
3428 on the directory used to start the OpenOCD server.
3430 The @var{offset} and @var{length} must be exact multiples of the
3431 device's page size. They describe a data region; the OOB data
3432 associated with each such page may also be accessed.
3434 @b{NOTE:} At the time this text was written, no error correction
3435 was done on the data that's read, unless raw access was disabled
3436 and the underlying NAND controller driver had a @code{read_page}
3437 method which handled that error correction.
3439 By default, only page data is saved to the specified file.
3440 Use an @var{oob_option} parameter to save OOB data:
3442 @item no oob_* parameter
3443 @*Output file holds only page data; OOB is discarded.
3444 @item @code{oob_raw}
3445 @*Output file interleaves page data and OOB data;
3446 the file will be longer than "length" by the size of the
3447 spare areas associated with each data page.
3448 Note that this kind of "raw" access is different from
3449 what's implied by @command{nand raw_access}, which just
3450 controls whether a hardware-aware access method is used.
3451 @item @code{oob_only}
3452 @*Output file has only raw OOB data, and will
3453 be smaller than "length" since it will contain only the
3454 spare areas associated with each data page.
3458 @deffn Command {nand erase} num offset length
3459 @cindex NAND erasing
3460 @cindex NAND programming
3461 Erases blocks on the specified NAND device, starting at the
3462 specified @var{offset} and continuing for @var{length} bytes.
3463 Both of those values must be exact multiples of the device's
3464 block size, and the region they specify must fit entirely in the chip.
3465 The @var{num} parameter is the value shown by @command{nand list}.
3467 @b{NOTE:} This command will try to erase bad blocks, when told
3468 to do so, which will probably invalidate the manufacturer's bad
3470 For the remainder of the current server session, @command{nand info}
3471 will still report that the block ``is'' bad.
3474 @deffn Command {nand write} num filename offset [option...]
3475 @cindex NAND writing
3476 @cindex NAND programming
3477 Writes binary data from the file into the specified NAND device,
3478 starting at the specified offset. Those pages should already
3479 have been erased; you can't change zero bits to one bits.
3480 The @var{num} parameter is the value shown by @command{nand list}.
3482 Use a complete path name for @var{filename}, so you don't depend
3483 on the directory used to start the OpenOCD server.
3485 The @var{offset} must be an exact multiple of the device's page size.
3486 All data in the file will be written, assuming it doesn't run
3487 past the end of the device.
3488 Only full pages are written, and any extra space in the last
3489 page will be filled with 0xff bytes. (That includes OOB data,
3490 if that's being written.)
3492 @b{NOTE:} At the time this text was written, bad blocks are
3493 ignored. That is, this routine will not skip bad blocks,
3494 but will instead try to write them. This can cause problems.
3496 Provide at most one @var{option} parameter. With some
3497 NAND drivers, the meanings of these parameters may change
3498 if @command{nand raw_access} was used to disable hardware ECC.
3500 @item no oob_* parameter
3501 @*File has only page data, which is written.
3502 If raw acccess is in use, the OOB area will not be written.
3503 Otherwise, if the underlying NAND controller driver has
3504 a @code{write_page} routine, that routine may write the OOB
3505 with hardware-computed ECC data.
3506 @item @code{oob_only}
3507 @*File has only raw OOB data, which is written to the OOB area.
3508 Each page's data area stays untouched. @i{This can be a dangerous
3509 option}, since it can invalidate the ECC data.
3510 You may need to force raw access to use this mode.
3511 @item @code{oob_raw}
3512 @*File interleaves data and OOB data, both of which are written
3513 If raw access is enabled, the data is written first, then the
3515 Otherwise, if the underlying NAND controller driver has
3516 a @code{write_page} routine, that routine may modify the OOB
3517 before it's written, to include hardware-computed ECC data.
3518 @item @code{oob_softecc}
3519 @*File has only page data, which is written.
3520 The OOB area is filled with 0xff, except for a standard 1-bit
3521 software ECC code stored in conventional locations.
3522 You might need to force raw access to use this mode, to prevent
3523 the underlying driver from applying hardware ECC.
3524 @item @code{oob_softecc_kw}
3525 @*File has only page data, which is written.
3526 The OOB area is filled with 0xff, except for a 4-bit software ECC
3527 specific to the boot ROM in Marvell Kirkwood SoCs.
3528 You might need to force raw access to use this mode, to prevent
3529 the underlying driver from applying hardware ECC.
3533 @section Other NAND commands
3534 @cindex NAND other commands
3536 @deffn Command {nand check_bad_blocks} [offset length]
3537 Checks for manufacturer bad block markers on the specified NAND
3538 device. If no parameters are provided, checks the whole
3539 device; otherwise, starts at the specified @var{offset} and
3540 continues for @var{length} bytes.
3541 Both of those values must be exact multiples of the device's
3542 block size, and the region they specify must fit entirely in the chip.
3543 The @var{num} parameter is the value shown by @command{nand list}.
3545 @b{NOTE:} Before using this command you should force raw access
3546 with @command{nand raw_access enable} to ensure that the underlying
3547 driver will not try to apply hardware ECC.
3550 @deffn Command {nand info} num
3551 The @var{num} parameter is the value shown by @command{nand list}.
3552 This prints the one-line summary from "nand list", plus for
3553 devices which have been probed this also prints any known
3554 status for each block.
3557 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
3558 Sets or clears an flag affecting how page I/O is done.
3559 The @var{num} parameter is the value shown by @command{nand list}.
3561 This flag is cleared (disabled) by default, but changing that
3562 value won't affect all NAND devices. The key factor is whether
3563 the underlying driver provides @code{read_page} or @code{write_page}
3564 methods. If it doesn't provide those methods, the setting of
3565 this flag is irrelevant; all access is effectively ``raw''.
3567 When those methods exist, they are normally used when reading
3568 data (@command{nand dump} or reading bad block markers) or
3569 writing it (@command{nand write}). However, enabling
3570 raw access (setting the flag) prevents use of those methods,
3571 bypassing hardware ECC logic.
3572 @i{This can be a dangerous option}, since writing blocks
3573 with the wrong ECC data can cause them to be marked as bad.
3576 @anchor{NAND Driver List}
3577 @section NAND Drivers, Options, and Commands
3578 As noted above, the @command{nand device} command allows
3579 driver-specific options and behaviors.
3580 Some controllers also activate controller-specific commands.
3582 @deffn {NAND Driver} davinci
3583 This driver handles the NAND controllers found on DaVinci family
3584 chips from Texas Instruments.
3585 It takes three extra parameters:
3586 address of the NAND chip;
3587 hardware ECC mode to use (hwecc1, hwecc4, hwecc4_infix);
3588 address of the AEMIF controller on this processor.
3590 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
3592 All DaVinci processors support the single-bit ECC hardware,
3593 and newer ones also support the four-bit ECC hardware.
3594 The @code{write_page} and @code{read_page} methods are used
3595 to implement those ECC modes, unless they are disabled using
3596 the @command{nand raw_access} command.
3599 @deffn {NAND Driver} lpc3180
3600 These controllers require an extra @command{nand device}
3601 parameter: the clock rate used by the controller.
3602 @deffn Command {lpc3180 select} num [mlc|slc]
3603 Configures use of the MLC or SLC controller mode.
3604 MLC implies use of hardware ECC.
3605 The @var{num} parameter is the value shown by @command{nand list}.
3608 At this writing, this driver includes @code{write_page}
3609 and @code{read_page} methods. Using @command{nand raw_access}
3610 to disable those methods will prevent use of hardware ECC
3611 in the MLC controller mode, but won't change SLC behavior.
3613 @comment current lpc3180 code won't issue 5-byte address cycles
3615 @deffn {NAND Driver} orion
3616 These controllers require an extra @command{nand device}
3617 parameter: the address of the controller.
3619 nand device orion 0xd8000000
3621 These controllers don't define any specialized commands.
3622 At this writing, their drivers don't include @code{write_page}
3623 or @code{read_page} methods, so @command{nand raw_access} won't
3624 change any behavior.
3627 @deffn {NAND Driver} s3c2410
3628 @deffnx {NAND Driver} s3c2412
3629 @deffnx {NAND Driver} s3c2440
3630 @deffnx {NAND Driver} s3c2443
3631 These S3C24xx family controllers don't have any special
3632 @command{nand device} options, and don't define any
3633 specialized commands.
3634 At this writing, their drivers don't include @code{write_page}
3635 or @code{read_page} methods, so @command{nand raw_access} won't
3636 change any behavior.
3639 @node General Commands
3640 @chapter General Commands
3643 The commands documented in this chapter here are common commands that
3644 you, as a human, may want to type and see the output of. Configuration type
3645 commands are documented elsewhere.
3649 @item @b{Source Of Commands}
3650 @* OpenOCD commands can occur in a configuration script (discussed
3651 elsewhere) or typed manually by a human or supplied programatically,
3652 or via one of several TCP/IP Ports.
3654 @item @b{From the human}
3655 @* A human should interact with the telnet interface (default port: 4444)
3656 or via GDB (default port 3333).
3658 To issue commands from within a GDB session, use the @option{monitor}
3659 command, e.g. use @option{monitor poll} to issue the @option{poll}
3660 command. All output is relayed through the GDB session.
3662 @item @b{Machine Interface}
3663 The Tcl interface's intent is to be a machine interface. The default Tcl
3668 @section Daemon Commands
3670 @deffn Command sleep msec [@option{busy}]
3671 Wait for at least @var{msec} milliseconds before resuming.
3672 If @option{busy} is passed, busy-wait instead of sleeping.
3673 (This option is strongly discouraged.)
3674 Useful in connection with script files
3675 (@command{script} command and @command{target_name} configuration).
3678 @deffn Command shutdown
3679 Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
3682 @anchor{debug_level}
3683 @deffn Command debug_level [n]
3684 @cindex message level
3685 Display debug level.
3686 If @var{n} (from 0..3) is provided, then set it to that level.
3687 This affects the kind of messages sent to the server log.
3688 Level 0 is error messages only;
3689 level 1 adds warnings;
3690 level 2 (the default) adds informational messages;
3691 and level 3 adds debugging messages.
3694 @deffn Command fast (@option{enable}|@option{disable})
3696 Set default behaviour of OpenOCD to be "fast and dangerous".
3698 At this writing, this only affects the defaults for two ARM7/ARM9 parameters:
3699 fast memory access, and DCC downloads. Those parameters may still be
3700 individually overridden.
3702 The target specific "dangerous" optimisation tweaking options may come and go
3703 as more robust and user friendly ways are found to ensure maximum throughput
3704 and robustness with a minimum of configuration.
3706 Typically the "fast enable" is specified first on the command line:
3709 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
3713 @deffn Command echo message
3714 Logs a message at "user" priority.
3715 Output @var{message} to stdout.
3717 echo "Downloading kernel -- please wait"
3721 @deffn Command log_output [filename]
3722 Redirect logging to @var{filename};
3723 the initial log output channel is stderr.
3726 @anchor{Target State handling}
3727 @section Target State handling
3730 @cindex target initialization
3732 In this section ``target'' refers to a CPU configured as
3733 shown earlier (@pxref{CPU Configuration}).
3734 These commands, like many, implicitly refer to
3735 a @dfn{current target} which is used to perform the
3736 various operations. The current target may be changed
3737 by using @command{targets} command with the name of the
3738 target which should become current.
3740 @deffn Command reg [(number|name) [value]]
3741 Access a single register by @var{number} or by its @var{name}.
3743 @emph{With no arguments}:
3744 list all available registers for the current target,
3745 showing number, name, size, value, and cache status.
3747 @emph{With number/name}: display that register's value.
3749 @emph{With both number/name and value}: set register's value.
3751 Cores may have surprisingly many registers in their
3752 Debug and trace infrastructure:
3756 (0) r0 (/32): 0x0000D3C2 (dirty: 1, valid: 1)
3757 (1) r1 (/32): 0xFD61F31C (dirty: 0, valid: 1)
3758 (2) r2 (/32): 0x00022551 (dirty: 0, valid: 1)
3760 (164) ETM_CONTEXTID_COMPARATOR_MASK (/32): \
3761 0x00000000 (dirty: 0, valid: 0)
3766 @deffn Command poll [@option{on}|@option{off}]
3767 Poll the current target for its current state.
3768 If that target is in debug mode, architecture
3769 specific information about the current state is printed. An optional parameter
3770 allows continuous polling to be enabled and disabled.
3774 target state: halted
3775 target halted in ARM state due to debug-request, \
3776 current mode: Supervisor
3777 cpsr: 0x800000d3 pc: 0x11081bfc
3778 MMU: disabled, D-Cache: disabled, I-Cache: enabled
3783 @deffn Command halt [ms]
3784 @deffnx Command wait_halt [ms]
3785 The @command{halt} command first sends a halt request to the target,
3786 which @command{wait_halt} doesn't.
3787 Otherwise these behave the same: wait up to @var{ms} milliseconds,
3788 or 5 seconds if there is no parameter, for the target to halt
3789 (and enter debug mode).
3790 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
3793 @deffn Command resume [address]
3794 Resume the target at its current code position,
3795 or the optional @var{address} if it is provided.
3796 OpenOCD will wait 5 seconds for the target to resume.
3799 @deffn Command step [address]
3800 Single-step the target at its current code position,
3801 or the optional @var{address} if it is provided.
3804 @anchor{Reset Command}
3805 @deffn Command reset
3806 @deffnx Command {reset run}
3807 @deffnx Command {reset halt}
3808 @deffnx Command {reset init}
3809 Perform as hard a reset as possible, using SRST if possible.
3810 @emph{All defined targets will be reset, and target
3811 events will fire during the reset sequence.}
3813 The optional parameter specifies what should
3814 happen after the reset.
3815 If there is no parameter, a @command{reset run} is executed.
3816 The other options will not work on all systems.
3817 @xref{Reset Configuration}.
3820 @item @b{run} Let the target run
3821 @item @b{halt} Immediately halt the target
3822 @item @b{init} Immediately halt the target, and execute the reset-init script
3826 @deffn Command soft_reset_halt
3827 Requesting target halt and executing a soft reset. This is often used
3828 when a target cannot be reset and halted. The target, after reset is
3829 released begins to execute code. OpenOCD attempts to stop the CPU and
3830 then sets the program counter back to the reset vector. Unfortunately
3831 the code that was executed may have left the hardware in an unknown
3835 @section I/O Utilities
3837 These commands are available when
3838 OpenOCD is built with @option{--enable-ioutil}.
3839 They are mainly useful on embedded targets;
3840 PC type hosts have complimentary tools.
3842 @emph{Note:} there are several more such commands.
3844 @deffn Command meminfo
3845 Display available RAM memory on OpenOCD host.
3846 Used in OpenOCD regression testing scripts.
3849 @anchor{Memory access}
3850 @section Memory access commands
3851 @cindex memory access
3853 These commands allow accesses of a specific size to the memory
3854 system. Often these are used to configure the current target in some
3855 special way. For example - one may need to write certain values to the
3856 SDRAM controller to enable SDRAM.
3859 @item Use the @command{targets} (plural) command
3860 to change the current target.
3861 @item In system level scripts these commands are deprecated.
3862 Please use their TARGET object siblings to avoid making assumptions
3863 about what TAP is the current target, or about MMU configuration.
3866 @deffn Command mdw addr [count]
3867 @deffnx Command mdh addr [count]
3868 @deffnx Command mdb addr [count]
3869 Display contents of address @var{addr}, as
3870 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
3871 or 8-bit bytes (@command{mdb}).
3872 If @var{count} is specified, displays that many units.
3873 (If you want to manipulate the data instead of displaying it,
3874 see the @code{mem2array} primitives.)
3877 @deffn Command mww addr word
3878 @deffnx Command mwh addr halfword
3879 @deffnx Command mwb addr byte
3880 Writes the specified @var{word} (32 bits),
3881 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3882 at the specified address @var{addr}.
3886 @anchor{Image access}
3887 @section Image loading commands
3888 @cindex image loading
3889 @cindex image dumping
3892 @deffn Command {dump_image} filename address size
3893 Dump @var{size} bytes of target memory starting at @var{address} to the
3894 binary file named @var{filename}.
3897 @deffn Command {fast_load}
3898 Loads an image stored in memory by @command{fast_load_image} to the
3899 current target. Must be preceeded by fast_load_image.
3902 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
3903 Normally you should be using @command{load_image} or GDB load. However, for
3904 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
3905 host), storing the image in memory and uploading the image to the target
3906 can be a way to upload e.g. multiple debug sessions when the binary does not change.
3907 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
3908 memory, i.e. does not affect target. This approach is also useful when profiling
3909 target programming performance as I/O and target programming can easily be profiled
3914 @deffn Command {load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
3915 Load image from file @var{filename} to target memory at @var{address}.
3916 The file format may optionally be specified
3917 (@option{bin}, @option{ihex}, or @option{elf})
3920 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
3921 Verify @var{filename} against target memory starting at @var{address}.
3922 The file format may optionally be specified
3923 (@option{bin}, @option{ihex}, or @option{elf})
3924 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
3928 @section Breakpoint and Watchpoint commands
3932 CPUs often make debug modules accessible through JTAG, with
3933 hardware support for a handful of code breakpoints and data
3935 In addition, CPUs almost always support software breakpoints.
3937 @deffn Command {bp} [address len [@option{hw}]]
3938 With no parameters, lists all active breakpoints.
3939 Else sets a breakpoint on code execution starting
3940 at @var{address} for @var{length} bytes.
3941 This is a software breakpoint, unless @option{hw} is specified
3942 in which case it will be a hardware breakpoint.
3945 @deffn Command {rbp} address
3946 Remove the breakpoint at @var{address}.
3949 @deffn Command {rwp} address
3950 Remove data watchpoint on @var{address}
3953 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]
3954 With no parameters, lists all active watchpoints.
3955 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
3956 The watch point is an "access" watchpoint unless
3957 the @option{r} or @option{w} parameter is provided,
3958 defining it as respectively a read or write watchpoint.
3959 If a @var{value} is provided, that value is used when determining if
3960 the watchpoint should trigger. The value may be first be masked
3961 using @var{mask} to mark ``don't care'' fields.
3964 @section Misc Commands
3967 @deffn Command {profile} seconds filename
3968 Profiling samples the CPU's program counter as quickly as possible,
3969 which is useful for non-intrusive stochastic profiling.
3970 Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
3973 @node Architecture and Core Commands
3974 @chapter Architecture and Core Commands
3975 @cindex Architecture Specific Commands
3976 @cindex Core Specific Commands
3978 Most CPUs have specialized JTAG operations to support debugging.
3979 OpenOCD packages most such operations in its standard command framework.
3980 Some of those operations don't fit well in that framework, so they are
3981 exposed here as architecture or implementation (core) specific commands.
3983 @anchor{ARM Tracing}
3984 @section ARM Tracing
3988 CPUs based on ARM cores may include standard tracing interfaces,
3989 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
3990 address and data bus trace records to a ``Trace Port''.
3994 Development-oriented boards will sometimes provide a high speed
3995 trace connector for collecting that data, when the particular CPU
3996 supports such an interface.
3997 (The standard connector is a 38-pin Mictor, with both JTAG
3998 and trace port support.)
3999 Those trace connectors are supported by higher end JTAG adapters
4000 and some logic analyzer modules; frequently those modules can
4001 buffer several megabytes of trace data.
4002 Configuring an ETM coupled to such an external trace port belongs
4003 in the board-specific configuration file.
4005 If the CPU doesn't provide an external interface, it probably
4006 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
4007 dedicated SRAM. 4KBytes is one common ETB size.
4008 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
4009 (target) configuration file, since it works the same on all boards.
4012 ETM support in OpenOCD doesn't seem to be widely used yet.
4015 ETM support may be buggy, and at least some @command{etm config}
4016 parameters should be detected by asking the ETM for them.
4017 It seems like a GDB hookup should be possible,
4018 as well as triggering trace on specific events
4019 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
4020 There should be GUI tools to manipulate saved trace data and help
4021 analyse it in conjunction with the source code.
4022 It's unclear how much of a common interface is shared
4023 with the current XScale trace support, or should be
4024 shared with eventual Nexus-style trace module support.
4027 @subsection ETM Configuration
4028 ETM setup is coupled with the trace port driver configuration.
4030 @deffn {Config Command} {etm config} target width mode clocking driver
4031 Declares the ETM associated with @var{target}, and associates it
4032 with a given trace port @var{driver}. @xref{Trace Port Drivers}.
4034 Several of the parameters must reflect the trace port configuration.
4035 The @var{width} must be either 4, 8, or 16.
4036 The @var{mode} must be @option{normal}, @option{multiplexted},
4037 or @option{demultiplexted}.
4038 The @var{clocking} must be @option{half} or @option{full}.
4041 You can see the ETM registers using the @command{reg} command, although
4042 not all of those possible registers are present in every ETM.
4046 @deffn Command {etm info}
4047 Displays information about the current target's ETM.
4050 @deffn Command {etm status}
4051 Displays status of the current target's ETM:
4052 is the ETM idle, or is it collecting data?
4053 Did trace data overflow?
4057 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
4058 Displays what data that ETM will collect.
4059 If arguments are provided, first configures that data.
4060 When the configuration changes, tracing is stopped
4061 and any buffered trace data is invalidated.
4064 @item @var{type} ... one of
4065 @option{none} (save nothing),
4066 @option{data} (save data),
4067 @option{address} (save addresses),
4068 @option{all} (save data and addresses)
4069 @item @var{context_id_bits} ... 0, 8, 16, or 32
4070 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
4071 @item @var{branch_output} ... @option{enable} or @option{disable}
4075 @deffn Command {etm trigger_percent} percent
4076 @emph{Buggy and effectively a NOP ... @var{percent} from 2..100}
4079 @subsection ETM Trace Operation
4081 After setting up the ETM, you can use it to collect data.
4082 That data can be exported to files for later analysis.
4083 It can also be parsed with OpenOCD, for basic sanity checking.
4085 @deffn Command {etm analyze}
4086 Reads trace data into memory, if it wasn't already present.
4087 Decodes and prints the data that was collected.
4090 @deffn Command {etm dump} filename
4091 Stores the captured trace data in @file{filename}.
4094 @deffn Command {etm image} filename [base_address] [type]
4095 Opens an image file.
4098 @deffn Command {etm load} filename
4099 Loads captured trace data from @file{filename}.
4102 @deffn Command {etm start}
4103 Starts trace data collection.
4106 @deffn Command {etm stop}
4107 Stops trace data collection.
4110 @anchor{Trace Port Drivers}
4111 @subsection Trace Port Drivers
4113 To use an ETM trace port it must be associated with a driver.
4115 @deffn {Trace Port Driver} dummy
4116 Use the @option{dummy} driver if you are configuring an ETM that's
4117 not connected to anything (on-chip ETB or off-chip trace connector).
4118 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
4119 any trace data collection.}
4120 @deffn {Config Command} {etm_dummy config} target
4121 Associates the ETM for @var{target} with a dummy driver.
4125 @deffn {Trace Port Driver} etb
4126 Use the @option{etb} driver if you are configuring an ETM
4127 to use on-chip ETB memory.
4128 @deffn {Config Command} {etb config} target etb_tap
4129 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
4130 You can see the ETB registers using the @command{reg} command.
4134 @deffn {Trace Port Driver} oocd_trace
4135 This driver isn't available unless OpenOCD was explicitly configured
4136 with the @option{--enable-oocd_trace} option. You probably don't want
4137 to configure it unless you've built the appropriate prototype hardware;
4138 it's @emph{proof-of-concept} software.
4140 Use the @option{oocd_trace} driver if you are configuring an ETM that's
4141 connected to an off-chip trace connector.
4143 @deffn {Config Command} {oocd_trace config} target tty
4144 Associates the ETM for @var{target} with a trace driver which
4145 collects data through the serial port @var{tty}.
4148 @deffn Command {oocd_trace resync}
4149 Re-synchronizes with the capture clock.
4152 @deffn Command {oocd_trace status}
4153 Reports whether the capture clock is locked or not.
4158 @section ARMv4 and ARMv5 Architecture
4162 These commands are specific to ARM architecture v4 and v5,
4163 including all ARM7 or ARM9 systems and Intel XScale.
4164 They are available in addition to other core-specific
4165 commands that may be available.
4167 @deffn Command {armv4_5 core_state} [@option{arm}|@option{thumb}]
4168 Displays the core_state, optionally changing it to process
4169 either @option{arm} or @option{thumb} instructions.
4170 The target may later be resumed in the currently set core_state.
4171 (Processors may also support the Jazelle state, but
4172 that is not currently supported in OpenOCD.)
4175 @deffn Command {armv4_5 disassemble} address count [thumb]
4177 Disassembles @var{count} instructions starting at @var{address}.
4178 If @option{thumb} is specified, Thumb (16-bit) instructions are used;
4179 else ARM (32-bit) instructions are used.
4180 (Processors may also support the Jazelle state, but
4181 those instructions are not currently understood by OpenOCD.)
4184 @deffn Command {armv4_5 reg}
4185 Display a table of all banked core registers, fetching the current value from every
4186 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
4190 @subsection ARM7 and ARM9 specific commands
4194 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
4195 ARM9TDMI, ARM920T or ARM926EJ-S.
4196 They are available in addition to the ARMv4/5 commands,
4197 and any other core-specific commands that may be available.
4199 @deffn Command {arm7_9 dbgrq} (@option{enable}|@option{disable})
4200 Control use of the EmbeddedIce DBGRQ signal to force entry into debug mode,
4201 instead of breakpoints. This should be
4202 safe for all but ARM7TDMI--S cores (like Philips LPC).
4205 @deffn Command {arm7_9 dcc_downloads} (@option{enable}|@option{disable})
4207 Control the use of the debug communications channel (DCC) to write larger (>128 byte)
4208 amounts of memory. DCC downloads offer a huge speed increase, but might be
4209 unsafe, especially with targets running at very low speeds. This command was introduced
4210 with OpenOCD rev. 60, and requires a few bytes of working area.
4213 @anchor{arm7_9 fast_memory_access}
4214 @deffn Command {arm7_9 fast_memory_access} (@option{enable}|@option{disable})
4215 Enable or disable memory writes and reads that don't check completion of
4216 the operation. This provides a huge speed increase, especially with USB JTAG
4217 cables (FT2232), but might be unsafe if used with targets running at very low
4218 speeds, like the 32kHz startup clock of an AT91RM9200.
4221 @deffn {Debug Command} {arm7_9 write_core_reg} num mode word
4222 @emph{This is intended for use while debugging OpenOCD; you probably
4225 Writes a 32-bit @var{word} to register @var{num} (from 0 to 16)
4226 as used in the specified @var{mode}
4227 (where e.g. mode 16 is "user" and mode 19 is "supervisor";
4228 the M4..M0 bits of the PSR).
4229 Registers 0..15 are the normal CPU registers such as r0(0), r1(1) ... pc(15).
4230 Register 16 is the mode-specific SPSR,
4231 unless the specified mode is 0xffffffff (32-bit all-ones)
4232 in which case register 16 is the CPSR.
4233 The write goes directly to the CPU, bypassing the register cache.
4236 @deffn {Debug Command} {arm7_9 write_xpsr} word (@option{0}|@option{1})
4237 @emph{This is intended for use while debugging OpenOCD; you probably
4240 If the second parameter is zero, writes @var{word} to the
4241 Current Program Status register (CPSR).
4242 Else writes @var{word} to the current mode's Saved PSR (SPSR).
4243 In both cases, this bypasses the register cache.
4246 @deffn {Debug Command} {arm7_9 write_xpsr_im8} byte rotate (@option{0}|@option{1})
4247 @emph{This is intended for use while debugging OpenOCD; you probably
4250 Writes eight bits to the CPSR or SPSR,
4251 first rotating them by @math{2*rotate} bits,
4252 and bypassing the register cache.
4253 This has lower JTAG overhead than writing the entire CPSR or SPSR
4254 with @command{arm7_9 write_xpsr}.
4257 @subsection ARM720T specific commands
4260 These commands are available to ARM720T based CPUs,
4261 which are implementations of the ARMv4T architecture
4262 based on the ARM7TDMI-S integer core.
4263 They are available in addition to the ARMv4/5 and ARM7/ARM9 commands.
4265 @deffn Command {arm720t cp15} regnum [value]
4266 Display cp15 register @var{regnum};
4267 else if a @var{value} is provided, that value is written to that register.
4270 @deffn Command {arm720t mdw_phys} addr [count]
4271 @deffnx Command {arm720t mdh_phys} addr [count]
4272 @deffnx Command {arm720t mdb_phys} addr [count]
4273 Display contents of physical address @var{addr}, as
4274 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
4275 or 8-bit bytes (@command{mdb_phys}).
4276 If @var{count} is specified, displays that many units.
4279 @deffn Command {arm720t mww_phys} addr word
4280 @deffnx Command {arm720t mwh_phys} addr halfword
4281 @deffnx Command {arm720t mwb_phys} addr byte
4282 Writes the specified @var{word} (32 bits),
4283 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4284 at the specified physical address @var{addr}.
4287 @deffn Command {arm720t virt2phys} va
4288 Translate a virtual address @var{va} to a physical address
4289 and display the result.
4292 @subsection ARM9TDMI specific commands
4295 Many ARM9-family CPUs are built around ARM9TDMI integer cores,
4296 or processors resembling ARM9TDMI, and can use these commands.
4297 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
4299 @deffn Command {arm9tdmi vector_catch} (@option{all}|@option{none}|list)
4300 Catch arm9 interrupt vectors, can be @option{all}, @option{none},
4301 or a list with one or more of the following:
4302 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
4303 @option{irq} @option{fiq}.
4306 @subsection ARM920T specific commands
4309 These commands are available to ARM920T based CPUs,
4310 which are implementations of the ARMv4T architecture
4311 built using the ARM9TDMI integer core.
4312 They are available in addition to the ARMv4/5, ARM7/ARM9,
4313 and ARM9TDMI commands.
4315 @deffn Command {arm920t cache_info}
4316 Print information about the caches found. This allows to see whether your target
4317 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
4320 @deffn Command {arm920t cp15} regnum [value]
4321 Display cp15 register @var{regnum};
4322 else if a @var{value} is provided, that value is written to that register.
4325 @deffn Command {arm920t cp15i} opcode [value [address]]
4326 Interpreted access using cp15 @var{opcode}.
4327 If no @var{value} is provided, the result is displayed.
4328 Else if that value is written using the specified @var{address},
4329 or using zero if no other address is not provided.
4332 @deffn Command {arm920t mdw_phys} addr [count]
4333 @deffnx Command {arm920t mdh_phys} addr [count]
4334 @deffnx Command {arm920t mdb_phys} addr [count]
4335 Display contents of physical address @var{addr}, as
4336 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
4337 or 8-bit bytes (@command{mdb_phys}).
4338 If @var{count} is specified, displays that many units.
4341 @deffn Command {arm920t mww_phys} addr word
4342 @deffnx Command {arm920t mwh_phys} addr halfword
4343 @deffnx Command {arm920t mwb_phys} addr byte
4344 Writes the specified @var{word} (32 bits),
4345 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4346 at the specified physical address @var{addr}.
4349 @deffn Command {arm920t read_cache} filename
4350 Dump the content of ICache and DCache to a file named @file{filename}.
4353 @deffn Command {arm920t read_mmu} filename
4354 Dump the content of the ITLB and DTLB to a file named @file{filename}.
4357 @deffn Command {arm920t virt2phys} va
4358 Translate a virtual address @var{va} to a physical address
4359 and display the result.
4362 @subsection ARM926ej-s specific commands
4365 These commands are available to ARM926ej-s based CPUs,
4366 which are implementations of the ARMv5TEJ architecture
4367 based on the ARM9EJ-S integer core.
4368 They are available in addition to the ARMv4/5, ARM7/ARM9,
4369 and ARM9TDMI commands.
4371 The Feroceon cores also support these commands, although
4372 they are not built from ARM926ej-s designs.
4374 @deffn Command {arm926ejs cache_info}
4375 Print information about the caches found.
4378 @deffn Command {arm926ejs cp15} opcode1 opcode2 CRn CRm regnum [value]
4379 Accesses cp15 register @var{regnum} using
4380 @var{opcode1}, @var{opcode2}, @var{CRn}, and @var{CRm}.
4381 If a @var{value} is provided, that value is written to that register.
4382 Else that register is read and displayed.
4385 @deffn Command {arm926ejs mdw_phys} addr [count]
4386 @deffnx Command {arm926ejs mdh_phys} addr [count]
4387 @deffnx Command {arm926ejs mdb_phys} addr [count]
4388 Display contents of physical address @var{addr}, as
4389 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
4390 or 8-bit bytes (@command{mdb_phys}).
4391 If @var{count} is specified, displays that many units.
4394 @deffn Command {arm926ejs mww_phys} addr word
4395 @deffnx Command {arm926ejs mwh_phys} addr halfword
4396 @deffnx Command {arm926ejs mwb_phys} addr byte
4397 Writes the specified @var{word} (32 bits),
4398 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4399 at the specified physical address @var{addr}.
4402 @deffn Command {arm926ejs virt2phys} va
4403 Translate a virtual address @var{va} to a physical address
4404 and display the result.
4407 @subsection ARM966E specific commands
4410 These commands are available to ARM966 based CPUs,
4411 which are implementations of the ARMv5TE architecture.
4412 They are available in addition to the ARMv4/5, ARM7/ARM9,
4413 and ARM9TDMI commands.
4415 @deffn Command {arm966e cp15} regnum [value]
4416 Display cp15 register @var{regnum};
4417 else if a @var{value} is provided, that value is written to that register.
4420 @subsection XScale specific commands
4423 These commands are available to XScale based CPUs,
4424 which are implementations of the ARMv5TE architecture.
4426 @deffn Command {xscale analyze_trace}
4427 Displays the contents of the trace buffer.
4430 @deffn Command {xscale cache_clean_address} address
4431 Changes the address used when cleaning the data cache.
4434 @deffn Command {xscale cache_info}
4435 Displays information about the CPU caches.
4438 @deffn Command {xscale cp15} regnum [value]
4439 Display cp15 register @var{regnum};
4440 else if a @var{value} is provided, that value is written to that register.
4443 @deffn Command {xscale debug_handler} target address
4444 Changes the address used for the specified target's debug handler.
4447 @deffn Command {xscale dcache} (@option{enable}|@option{disable})
4448 Enables or disable the CPU's data cache.
4451 @deffn Command {xscale dump_trace} filename
4452 Dumps the raw contents of the trace buffer to @file{filename}.
4455 @deffn Command {xscale icache} (@option{enable}|@option{disable})
4456 Enables or disable the CPU's instruction cache.
4459 @deffn Command {xscale mmu} (@option{enable}|@option{disable})
4460 Enables or disable the CPU's memory management unit.
4463 @deffn Command {xscale trace_buffer} (@option{enable}|@option{disable}) [@option{fill} [n] | @option{wrap}]
4464 Enables or disables the trace buffer,
4465 and controls how it is emptied.
4468 @deffn Command {xscale trace_image} filename [offset [type]]
4469 Opens a trace image from @file{filename}, optionally rebasing
4470 its segment addresses by @var{offset}.
4471 The image @var{type} may be one of
4472 @option{bin} (binary), @option{ihex} (Intel hex),
4473 @option{elf} (ELF file), @option{s19} (Motorola s19),
4474 @option{mem}, or @option{builder}.
4477 @deffn Command {xscale vector_catch} mask
4478 Provide a bitmask showing the vectors to catch.
4481 @section ARMv6 Architecture
4484 @subsection ARM11 specific commands
4487 @deffn Command {arm11 mcr} p1 p2 p3 p4 p5
4488 Read coprocessor register
4491 @deffn Command {arm11 memwrite burst} [value]
4492 Displays the value of the memwrite burst-enable flag,
4493 which is enabled by default.
4494 If @var{value} is defined, first assigns that.
4497 @deffn Command {arm11 memwrite error_fatal} [value]
4498 Displays the value of the memwrite error_fatal flag,
4499 which is enabled by default.
4500 If @var{value} is defined, first assigns that.
4503 @deffn Command {arm11 mrc} p1 p2 p3 p4 p5 value
4504 Write coprocessor register
4507 @deffn Command {arm11 no_increment} [value]
4508 Displays the value of the flag controlling whether
4509 some read or write operations increment the pointer
4510 (the default behavior) or not (acting like a FIFO).
4511 If @var{value} is defined, first assigns that.
4514 @deffn Command {arm11 step_irq_enable} [value]
4515 Displays the value of the flag controlling whether
4516 IRQs are enabled during single stepping;
4517 they is disabled by default.
4518 If @var{value} is defined, first assigns that.
4521 @section ARMv7 Architecture
4524 @subsection ARMv7 Debug Access Port (DAP) specific commands
4525 @cindex Debug Access Port
4527 These commands are specific to ARM architecture v7 Debug Access Port (DAP),
4528 included on cortex-m3 and cortex-a8 systems.
4529 They are available in addition to other core-specific commands that may be available.
4531 @deffn Command {dap info} [num]
4532 Displays dap info for ap @var{num}, defaulting to the currently selected AP.
4535 @deffn Command {dap apsel} [num]
4536 Select AP @var{num}, defaulting to 0.
4539 @deffn Command {dap apid} [num]
4540 Displays id register from AP @var{num},
4541 defaulting to the currently selected AP.
4544 @deffn Command {dap baseaddr} [num]
4545 Displays debug base address from AP @var{num},
4546 defaulting to the currently selected AP.
4549 @deffn Command {dap memaccess} [value]
4550 Displays the number of extra tck for mem-ap memory bus access [0-255].
4551 If @var{value} is defined, first assigns that.
4554 @subsection Cortex-M3 specific commands
4557 @deffn Command {cortex_m3 maskisr} (@option{on}|@option{off})
4558 Control masking (disabling) interrupts during target step/resume.
4561 @section Target DCC Requests
4562 @cindex Linux-ARM DCC support
4565 OpenOCD can handle certain target requests; currently debugmsgs
4566 @command{target_request debugmsgs}
4567 are only supported for arm7_9 and cortex_m3.
4569 See libdcc in the contrib dir for more details.
4570 Linux-ARM kernels have a ``Kernel low-level debugging
4571 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
4572 depends on CONFIG_DEBUG_LL) which uses this mechanism to
4573 deliver messages before a serial console can be activated.
4575 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
4576 Displays current handling of target DCC message requests.
4577 These messages may be sent to the debugger while the target is running.
4578 The optional @option{enable} and @option{charmsg} parameters
4579 both enable the messages, while @option{disable} disables them.
4580 With @option{charmsg} the DCC words each contain one character,
4581 as used by Linux with CONFIG_DEBUG_ICEDCC;
4582 otherwise the libdcc format is used.
4586 @chapter JTAG Commands
4587 @cindex JTAG Commands
4588 Most general purpose JTAG commands have been presented earlier.
4589 (@xref{JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
4590 Lower level JTAG commands, as presented here,
4591 may be needed to work with targets which require special
4592 attention during operations such as reset or initialization.
4594 To use these commands you will need to understand some
4595 of the basics of JTAG, including:
4598 @item A JTAG scan chain consists of a sequence of individual TAP
4599 devices such as a CPUs.
4600 @item Control operations involve moving each TAP through the same
4601 standard state machine (in parallel)
4602 using their shared TMS and clock signals.
4603 @item Data transfer involves shifting data through the chain of
4604 instruction or data registers of each TAP, writing new register values
4605 while the reading previous ones.
4606 @item Data register sizes are a function of the instruction active in
4607 a given TAP, while instruction register sizes are fixed for each TAP.
4608 All TAPs support a BYPASS instruction with a single bit data register.
4609 @item The way OpenOCD differentiates between TAP devices is by
4610 shifting different instructions into (and out of) their instruction
4614 @section Low Level JTAG Commands
4616 These commands are used by developers who need to access
4617 JTAG instruction or data registers, possibly controlling
4618 the order of TAP state transitions.
4619 If you're not debugging OpenOCD internals, or bringing up a
4620 new JTAG adapter or a new type of TAP device (like a CPU or
4621 JTAG router), you probably won't need to use these commands.
4623 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
4624 Loads the data register of @var{tap} with a series of bit fields
4625 that specify the entire register.
4626 Each field is @var{numbits} bits long with
4627 a numeric @var{value} (hexadecimal encouraged).
4628 The return value holds the original value of each
4631 For example, a 38 bit number might be specified as one
4632 field of 32 bits then one of 6 bits.
4633 @emph{For portability, never pass fields which are more
4634 than 32 bits long. Many OpenOCD implementations do not
4635 support 64-bit (or larger) integer values.}
4637 All TAPs other than @var{tap} must be in BYPASS mode.
4638 The single bit in their data registers does not matter.
4640 When @var{tap_state} is specified, the JTAG state machine is left
4642 For example @sc{drpause} might be specified, so that more
4643 instructions can be issued before re-entering the @sc{run/idle} state.
4644 If the end state is not specified, the @sc{run/idle} state is entered.
4647 OpenOCD does not record information about data register lengths,
4648 so @emph{it is important that you get the bit field lengths right}.
4649 Remember that different JTAG instructions refer to different
4650 data registers, which may have different lengths.
4651 Moreover, those lengths may not be fixed;
4652 the SCAN_N instruction can change the length of
4653 the register accessed by the INTEST instruction
4654 (by connecting a different scan chain).
4658 @deffn Command {flush_count}
4659 Returns the number of times the JTAG queue has been flushed.
4660 This may be used for performance tuning.
4662 For example, flushing a queue over USB involves a
4663 minimum latency, often several milliseconds, which does
4664 not change with the amount of data which is written.
4665 You may be able to identify performance problems by finding
4666 tasks which waste bandwidth by flushing small transfers too often,
4667 instead of batching them into larger operations.
4670 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
4671 For each @var{tap} listed, loads the instruction register
4672 with its associated numeric @var{instruction}.
4673 (The number of bits in that instruction may be displayed
4674 using the @command{scan_chain} command.)
4675 For other TAPs, a BYPASS instruction is loaded.
4677 When @var{tap_state} is specified, the JTAG state machine is left
4679 For example @sc{irpause} might be specified, so the data register
4680 can be loaded before re-entering the @sc{run/idle} state.
4681 If the end state is not specified, the @sc{run/idle} state is entered.
4684 OpenOCD currently supports only a single field for instruction
4685 register values, unlike data register values.
4686 For TAPs where the instruction register length is more than 32 bits,
4687 portable scripts currently must issue only BYPASS instructions.
4691 @deffn Command {jtag_reset} trst srst
4692 Set values of reset signals.
4693 The @var{trst} and @var{srst} parameter values may be
4694 @option{0}, indicating that reset is inactive (pulled or driven high),
4695 or @option{1}, indicating it is active (pulled or driven low).
4696 The @command{reset_config} command should already have been used
4697 to configure how the board and JTAG adapter treat these two
4698 signals, and to say if either signal is even present.
4699 @xref{Reset Configuration}.
4702 @deffn Command {runtest} @var{num_cycles}
4703 Move to the @sc{run/idle} state, and execute at least
4704 @var{num_cycles} of the JTAG clock (TCK).
4705 Instructions often need some time
4706 to execute before they take effect.
4709 @deffn Command {scan_chain}
4710 Displays the TAPs in the scan chain configuration,
4712 The set of TAPs listed by this command is fixed by
4713 exiting the OpenOCD configuration stage,
4714 but systems with a JTAG router can
4715 enable or disable TAPs dynamically.
4716 In addition to the enable/disable status, the contents of
4717 each TAP's instruction register can also change.
4720 @c tms_sequence (short|long)
4721 @c ... temporary, debug-only, probably gone before 0.2 ships
4723 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
4724 Verify values captured during @sc{ircapture} and returned
4725 during IR scans. Default is enabled, but this can be
4726 overridden by @command{verify_jtag}.
4729 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
4730 Enables verification of DR and IR scans, to help detect
4731 programming errors. For IR scans, @command{verify_ircapture}
4732 must also be enabled.
4736 @section TAP state names
4737 @cindex TAP state names
4739 The @var{tap_state} names used by OpenOCD in the @command{drscan},
4740 and @command{irscan} commands are:
4743 @item @b{RESET} ... should act as if TRST were active
4744 @item @b{RUN/IDLE} ... don't assume this always means IDLE
4747 @item @b{DRSHIFT} ... TDI/TDO shifting through the data register
4749 @item @b{DRPAUSE} ... data register ready for update or more shifting
4754 @item @b{IRSHIFT} ... TDI/TDO shifting through the instruction register
4756 @item @b{IRPAUSE} ... instruction register ready for update or more shifting
4761 Note that only six of those states are fully ``stable'' in the
4762 face of TMS fixed (usually low)
4763 and a free-running JTAG clock. For all the
4764 others, the next TCK transition changes to a new state.
4767 @item From @sc{drshift} and @sc{irshift}, clock transitions will
4768 produce side effects by changing register contents. The values
4769 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
4770 may not be as expected.
4771 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
4772 choices after @command{drscan} or @command{irscan} commands,
4773 since they are free of JTAG side effects.
4774 However, @sc{run/idle} may have side effects that appear at other
4775 levels, such as advancing the ARM9E-S instruction pipeline.
4776 Consult the documentation for the TAP(s) you are working with.
4782 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
4783 be used to access files on PCs (either the developer's PC or some other PC).
4785 The way this works on the ZY1000 is to prefix a filename by
4786 "/tftp/ip/" and append the TFTP path on the TFTP
4787 server (tftpd). For example,
4790 load_image /tftp/10.0.0.96/c:\temp\abc.elf
4793 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
4794 if the file was hosted on the embedded host.
4796 In order to achieve decent performance, you must choose a TFTP server
4797 that supports a packet size bigger than the default packet size (512 bytes). There
4798 are numerous TFTP servers out there (free and commercial) and you will have to do
4799 a bit of googling to find something that fits your requirements.
4801 @node Sample Scripts
4802 @chapter Sample Scripts
4805 This page shows how to use the Target Library.
4807 The configuration script can be divided into the following sections:
4809 @item Daemon configuration
4811 @item JTAG scan chain
4812 @item Target configuration
4813 @item Flash configuration
4816 Detailed information about each section can be found at OpenOCD configuration.
4818 @section AT91R40008 example
4819 @cindex AT91R40008 example
4820 To start OpenOCD with a target script for the AT91R40008 CPU and reset
4821 the CPU upon startup of the OpenOCD daemon.
4823 openocd -f interface/parport.cfg -f target/at91r40008.cfg \
4824 -c "init" -c "reset"
4828 @node GDB and OpenOCD
4829 @chapter GDB and OpenOCD
4831 OpenOCD complies with the remote gdbserver protocol, and as such can be used
4832 to debug remote targets.
4834 @anchor{Connecting to GDB}
4835 @section Connecting to GDB
4836 @cindex Connecting to GDB
4837 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
4838 instance GDB 6.3 has a known bug that produces bogus memory access
4839 errors, which has since been fixed: look up 1836 in
4840 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
4842 OpenOCD can communicate with GDB in two ways:
4846 A socket (TCP/IP) connection is typically started as follows:
4848 target remote localhost:3333
4850 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
4852 A pipe connection is typically started as follows:
4854 target remote | openocd --pipe
4856 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
4857 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
4861 To list the available OpenOCD commands type @command{monitor help} on the
4864 OpenOCD supports the gdb @option{qSupported} packet, this enables information
4865 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
4866 packet size and the device's memory map.
4868 Previous versions of OpenOCD required the following GDB options to increase
4869 the packet size and speed up GDB communication:
4871 set remote memory-write-packet-size 1024
4872 set remote memory-write-packet-size fixed
4873 set remote memory-read-packet-size 1024
4874 set remote memory-read-packet-size fixed
4876 This is now handled in the @option{qSupported} PacketSize and should not be required.
4878 @section Programming using GDB
4879 @cindex Programming using GDB
4881 By default the target memory map is sent to GDB. This can be disabled by
4882 the following OpenOCD configuration option:
4884 gdb_memory_map disable
4886 For this to function correctly a valid flash configuration must also be set
4887 in OpenOCD. For faster performance you should also configure a valid
4890 Informing GDB of the memory map of the target will enable GDB to protect any
4891 flash areas of the target and use hardware breakpoints by default. This means
4892 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
4893 using a memory map. @xref{gdb_breakpoint_override}.
4895 To view the configured memory map in GDB, use the GDB command @option{info mem}
4896 All other unassigned addresses within GDB are treated as RAM.
4898 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
4899 This can be changed to the old behaviour by using the following GDB command
4901 set mem inaccessible-by-default off
4904 If @command{gdb_flash_program enable} is also used, GDB will be able to
4905 program any flash memory using the vFlash interface.
4907 GDB will look at the target memory map when a load command is given, if any
4908 areas to be programmed lie within the target flash area the vFlash packets
4911 If the target needs configuring before GDB programming, an event
4912 script can be executed:
4914 $_TARGETNAME configure -event EVENTNAME BODY
4917 To verify any flash programming the GDB command @option{compare-sections}
4920 @node Tcl Scripting API
4921 @chapter Tcl Scripting API
4922 @cindex Tcl Scripting API
4926 The commands are stateless. E.g. the telnet command line has a concept
4927 of currently active target, the Tcl API proc's take this sort of state
4928 information as an argument to each proc.
4930 There are three main types of return values: single value, name value
4931 pair list and lists.
4933 Name value pair. The proc 'foo' below returns a name/value pair
4939 > set foo(you) Oyvind
4940 > set foo(mouse) Micky
4941 > set foo(duck) Donald
4949 me Duane you Oyvind mouse Micky duck Donald
4951 Thus, to get the names of the associative array is easy:
4953 foreach { name value } [set foo] {
4954 puts "Name: $name, Value: $value"
4958 Lists returned must be relatively small. Otherwise a range
4959 should be passed in to the proc in question.
4961 @section Internal low-level Commands
4963 By low-level, the intent is a human would not directly use these commands.
4965 Low-level commands are (should be) prefixed with "ocd_", e.g.
4966 @command{ocd_flash_banks}
4967 is the low level API upon which @command{flash banks} is implemented.
4970 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
4972 Read memory and return as a Tcl array for script processing
4973 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
4975 Convert a Tcl array to memory locations and write the values
4976 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
4978 Return information about the flash banks
4981 OpenOCD commands can consist of two words, e.g. "flash banks". The
4982 startup.tcl "unknown" proc will translate this into a Tcl proc
4983 called "flash_banks".
4985 @section OpenOCD specific Global Variables
4989 Real Tcl has ::tcl_platform(), and platform::identify, and many other
4990 variables. JimTCL, as implemented in OpenOCD creates $HostOS which
4991 holds one of the following values:
4994 @item @b{winxx} Built using Microsoft Visual Studio
4995 @item @b{linux} Linux is the underlying operating sytem
4996 @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
4997 @item @b{cygwin} Running under Cygwin
4998 @item @b{mingw32} Running under MingW32
4999 @item @b{other} Unknown, none of the above.
5002 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
5005 We should add support for a variable like Tcl variable
5006 @code{tcl_platform(platform)}, it should be called
5007 @code{jim_platform} (because it
5008 is jim, not real tcl).
5012 @chapter Deprecated/Removed Commands
5013 @cindex Deprecated/Removed Commands
5014 Certain OpenOCD commands have been deprecated or
5015 removed during the various revisions.
5017 Upgrade your scripts as soon as possible.
5018 These descriptions for old commands may be removed
5019 a year after the command itself was removed.
5020 This means that in January 2010 this chapter may
5021 become much shorter.
5024 @item @b{arm7_9 fast_writes}
5025 @cindex arm7_9 fast_writes
5026 @*Use @command{arm7_9 fast_memory_access} instead.
5029 @*An buggy old command that would not really work since background polling would wipe out the global endstate
5030 @xref{arm7_9 fast_memory_access}.
5031 @item @b{arm7_9 force_hw_bkpts}
5032 @*Use @command{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
5033 for flash if the GDB memory map has been set up(default when flash is declared in
5034 target configuration). @xref{gdb_breakpoint_override}.
5035 @item @b{arm7_9 sw_bkpts}
5036 @*On by default. @xref{gdb_breakpoint_override}.
5037 @item @b{daemon_startup}
5038 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
5039 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
5040 and @option{target cortex_m3 little reset_halt 0}.
5041 @item @b{dump_binary}
5042 @*use @option{dump_image} command with same args. @xref{dump_image}.
5043 @item @b{flash erase}
5044 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
5045 @item @b{flash write}
5046 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
5047 @item @b{flash write_binary}
5048 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
5049 @item @b{flash auto_erase}
5050 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
5052 @item @b{jtag_device}
5053 @*use the @command{jtag newtap} command, converting from positional syntax
5054 to named prefixes, and naming the TAP.
5056 Note that if you try to use the old command, a message will tell you the
5057 right new command to use; and that the fourth parameter in the old syntax
5058 was never actually used.
5060 OLD: jtag_device 8 0x01 0xe3 0xfe
5061 NEW: jtag newtap CHIPNAME TAPNAME \
5062 -irlen 8 -ircapture 0x01 -irmask 0xe3
5065 @item @b{jtag_speed} value
5066 @*@xref{JTAG Speed}.
5067 Usually, a value of zero means maximum
5068 speed. The actual effect of this option depends on the JTAG interface used.
5070 @item wiggler: maximum speed / @var{number}
5071 @item ft2232: 6MHz / (@var{number}+1)
5072 @item amt jtagaccel: 8 / 2**@var{number}
5073 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
5074 @item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
5075 @comment end speed list.
5078 @item @b{load_binary}
5079 @*use @option{load_image} command with same args. @xref{load_image}.
5080 @item @b{run_and_halt_time}
5081 @*This command has been removed for simpler reset behaviour, it can be simulated with the
5088 @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
5089 @*use the create subcommand of @option{target}.
5090 @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
5091 @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
5092 @item @b{working_area}
5093 @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
5101 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
5103 @cindex adaptive clocking
5106 In digital circuit design it is often refered to as ``clock
5107 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
5108 operating at some speed, your target is operating at another. The two
5109 clocks are not synchronised, they are ``asynchronous''
5111 In order for the two to work together they must be synchronised. Otherwise
5112 the two systems will get out of sync with each other and nothing will
5113 work. There are 2 basic options:
5116 Use a special circuit.
5118 One clock must be some multiple slower than the other.
5121 @b{Does this really matter?} For some chips and some situations, this
5122 is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
5123 Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
5124 program/enable the oscillators and eventually the main clock. It is in
5125 those critical times you must slow the JTAG clock to sometimes 1 to
5128 Imagine debugging a 500MHz ARM926 hand held battery powered device
5129 that ``deep sleeps'' at 32kHz between every keystroke. It can be
5132 @b{Solution #1 - A special circuit}
5134 In order to make use of this, your JTAG dongle must support the RTCK
5135 feature. Not all dongles support this - keep reading!
5137 The RTCK signal often found in some ARM chips is used to help with
5138 this problem. ARM has a good description of the problem described at
5139 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
5140 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
5141 work? / how does adaptive clocking work?''.
5143 The nice thing about adaptive clocking is that ``battery powered hand
5144 held device example'' - the adaptiveness works perfectly all the
5145 time. One can set a break point or halt the system in the deep power
5146 down code, slow step out until the system speeds up.
5148 @b{Solution #2 - Always works - but may be slower}
5150 Often this is a perfectly acceptable solution.
5152 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
5153 the target clock speed. But what that ``magic division'' is varies
5154 depending on the chips on your board. @b{ARM rule of thumb} Most ARM
5155 based systems require an 8:1 division. @b{Xilinx rule of thumb} is
5156 1/12 the clock speed.
5158 Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
5160 You can still debug the 'low power' situations - you just need to
5161 manually adjust the clock speed at every step. While painful and
5162 tedious, it is not always practical.
5164 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
5165 have a special debug mode in your application that does a ``high power
5166 sleep''. If you are careful - 98% of your problems can be debugged
5169 To set the JTAG frequency use the command:
5177 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
5179 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
5180 around Windows filenames.
5193 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
5195 Make sure you have Cygwin installed, or at least a version of OpenOCD that
5196 claims to come with all the necessary DLLs. When using Cygwin, try launching
5197 OpenOCD from the Cygwin shell.
5199 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
5200 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
5201 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
5203 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
5204 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
5205 software breakpoints consume one of the two available hardware breakpoints.
5207 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
5209 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
5210 clock at the time you're programming the flash. If you've specified the crystal's
5211 frequency, make sure the PLL is disabled. If you've specified the full core speed
5212 (e.g. 60MHz), make sure the PLL is enabled.
5214 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
5215 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
5216 out while waiting for end of scan, rtck was disabled".
5218 Make sure your PC's parallel port operates in EPP mode. You might have to try several
5219 settings in your PC BIOS (ECP, EPP, and different versions of those).
5221 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
5222 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
5223 memory read caused data abort".
5225 The errors are non-fatal, and are the result of GDB trying to trace stack frames
5226 beyond the last valid frame. It might be possible to prevent this by setting up
5227 a proper "initial" stack frame, if you happen to know what exactly has to
5228 be done, feel free to add this here.
5230 @b{Simple:} In your startup code - push 8 registers of zeros onto the
5231 stack before calling main(). What GDB is doing is ``climbing'' the run
5232 time stack by reading various values on the stack using the standard
5233 call frame for the target. GDB keeps going - until one of 2 things
5234 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
5235 stackframes have been processed. By pushing zeros on the stack, GDB
5238 @b{Debugging Interrupt Service Routines} - In your ISR before you call
5239 your C code, do the same - artifically push some zeros onto the stack,
5240 remember to pop them off when the ISR is done.
5242 @b{Also note:} If you have a multi-threaded operating system, they
5243 often do not @b{in the intrest of saving memory} waste these few
5247 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
5248 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
5250 This warning doesn't indicate any serious problem, as long as you don't want to
5251 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
5252 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
5253 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
5254 independently. With this setup, it's not possible to halt the core right out of
5255 reset, everything else should work fine.
5257 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
5258 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
5259 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
5260 quit with an error message. Is there a stability issue with OpenOCD?
5262 No, this is not a stability issue concerning OpenOCD. Most users have solved
5263 this issue by simply using a self-powered USB hub, which they connect their
5264 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
5265 supply stable enough for the Amontec JTAGkey to be operated.
5267 @b{Laptops running on battery have this problem too...}
5269 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
5270 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
5271 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
5272 What does that mean and what might be the reason for this?
5274 First of all, the reason might be the USB power supply. Try using a self-powered
5275 hub instead of a direct connection to your computer. Secondly, the error code 4
5276 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
5277 chip ran into some sort of error - this points us to a USB problem.
5279 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
5280 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
5281 What does that mean and what might be the reason for this?
5283 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
5284 has closed the connection to OpenOCD. This might be a GDB issue.
5286 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
5287 are described, there is a parameter for specifying the clock frequency
5288 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
5289 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
5290 specified in kilohertz. However, I do have a quartz crystal of a
5291 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
5292 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
5295 No. The clock frequency specified here must be given as an integral number.
5296 However, this clock frequency is used by the In-Application-Programming (IAP)
5297 routines of the LPC2000 family only, which seems to be very tolerant concerning
5298 the given clock frequency, so a slight difference between the specified clock
5299 frequency and the actual clock frequency will not cause any trouble.
5301 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
5303 Well, yes and no. Commands can be given in arbitrary order, yet the
5304 devices listed for the JTAG scan chain must be given in the right
5305 order (jtag newdevice), with the device closest to the TDO-Pin being
5306 listed first. In general, whenever objects of the same type exist
5307 which require an index number, then these objects must be given in the
5308 right order (jtag newtap, targets and flash banks - a target
5309 references a jtag newtap and a flash bank references a target).
5311 You can use the ``scan_chain'' command to verify and display the tap order.
5313 Also, some commands can't execute until after @command{init} has been
5314 processed. Such commands include @command{nand probe} and everything
5315 else that needs to write to controller registers, perhaps for setting
5316 up DRAM and loading it with code.
5318 @anchor{FAQ TAP Order}
5319 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
5322 Yes; whenever you have more than one, you must declare them in
5323 the same order used by the hardware.
5325 Many newer devices have multiple JTAG TAPs. For example: ST
5326 Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
5327 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
5328 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
5329 connected to the boundary scan TAP, which then connects to the
5330 Cortex-M3 TAP, which then connects to the TDO pin.
5332 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
5333 (2) The boundary scan TAP. If your board includes an additional JTAG
5334 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
5335 place it before or after the STM32 chip in the chain. For example:
5338 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
5339 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
5340 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
5341 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
5342 @item Xilinx TDO Pin -> OpenOCD TDO (input)
5345 The ``jtag device'' commands would thus be in the order shown below. Note:
5348 @item jtag newtap Xilinx tap -irlen ...
5349 @item jtag newtap stm32 cpu -irlen ...
5350 @item jtag newtap stm32 bs -irlen ...
5351 @item # Create the debug target and say where it is
5352 @item target create stm32.cpu -chain-position stm32.cpu ...
5356 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
5357 log file, I can see these error messages: Error: arm7_9_common.c:561
5358 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
5364 @node Tcl Crash Course
5365 @chapter Tcl Crash Course
5368 Not everyone knows Tcl - this is not intended to be a replacement for
5369 learning Tcl, the intent of this chapter is to give you some idea of
5370 how the Tcl scripts work.
5372 This chapter is written with two audiences in mind. (1) OpenOCD users
5373 who need to understand a bit more of how JIM-Tcl works so they can do
5374 something useful, and (2) those that want to add a new command to
5377 @section Tcl Rule #1
5378 There is a famous joke, it goes like this:
5380 @item Rule #1: The wife is always correct
5381 @item Rule #2: If you think otherwise, See Rule #1
5384 The Tcl equal is this:
5387 @item Rule #1: Everything is a string
5388 @item Rule #2: If you think otherwise, See Rule #1
5391 As in the famous joke, the consequences of Rule #1 are profound. Once
5392 you understand Rule #1, you will understand Tcl.
5394 @section Tcl Rule #1b
5395 There is a second pair of rules.
5397 @item Rule #1: Control flow does not exist. Only commands
5398 @* For example: the classic FOR loop or IF statement is not a control
5399 flow item, they are commands, there is no such thing as control flow
5401 @item Rule #2: If you think otherwise, See Rule #1
5402 @* Actually what happens is this: There are commands that by
5403 convention, act like control flow key words in other languages. One of
5404 those commands is the word ``for'', another command is ``if''.
5407 @section Per Rule #1 - All Results are strings
5408 Every Tcl command results in a string. The word ``result'' is used
5409 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
5410 Everything is a string}
5412 @section Tcl Quoting Operators
5413 In life of a Tcl script, there are two important periods of time, the
5414 difference is subtle.
5417 @item Evaluation Time
5420 The two key items here are how ``quoted things'' work in Tcl. Tcl has
5421 three primary quoting constructs, the [square-brackets] the
5422 @{curly-braces@} and ``double-quotes''
5424 By now you should know $VARIABLES always start with a $DOLLAR
5425 sign. BTW: To set a variable, you actually use the command ``set'', as
5426 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
5427 = 1'' statement, but without the equal sign.
5430 @item @b{[square-brackets]}
5431 @* @b{[square-brackets]} are command substitutions. It operates much
5432 like Unix Shell `back-ticks`. The result of a [square-bracket]
5433 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
5434 string}. These two statements are roughly identical:
5438 echo "The Date is: $X"
5441 puts "The Date is: $X"
5443 @item @b{``double-quoted-things''}
5444 @* @b{``double-quoted-things''} are just simply quoted
5445 text. $VARIABLES and [square-brackets] are expanded in place - the
5446 result however is exactly 1 string. @i{Remember Rule #1 - Everything
5450 puts "It is now \"[date]\", $x is in 1 hour"
5452 @item @b{@{Curly-Braces@}}
5453 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
5454 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
5455 'single-quote' operators in BASH shell scripts, with the added
5456 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
5457 nested 3 times@}@}@} NOTE: [date] is perhaps a bad example, as of
5458 28/nov/2008, Jim/OpenOCD does not have a date command.
5461 @section Consequences of Rule 1/2/3/4
5463 The consequences of Rule 1 are profound.
5465 @subsection Tokenisation & Execution.
5467 Of course, whitespace, blank lines and #comment lines are handled in
5470 As a script is parsed, each (multi) line in the script file is
5471 tokenised and according to the quoting rules. After tokenisation, that
5472 line is immedatly executed.
5474 Multi line statements end with one or more ``still-open''
5475 @{curly-braces@} which - eventually - closes a few lines later.
5477 @subsection Command Execution
5479 Remember earlier: There are no ``control flow''
5480 statements in Tcl. Instead there are COMMANDS that simply act like
5481 control flow operators.
5483 Commands are executed like this:
5486 @item Parse the next line into (argc) and (argv[]).
5487 @item Look up (argv[0]) in a table and call its function.
5488 @item Repeat until End Of File.
5491 It sort of works like this:
5494 ReadAndParse( &argc, &argv );
5496 cmdPtr = LookupCommand( argv[0] );
5498 (*cmdPtr->Execute)( argc, argv );
5502 When the command ``proc'' is parsed (which creates a procedure
5503 function) it gets 3 parameters on the command line. @b{1} the name of
5504 the proc (function), @b{2} the list of parameters, and @b{3} the body
5505 of the function. Not the choice of words: LIST and BODY. The PROC
5506 command stores these items in a table somewhere so it can be found by
5509 @subsection The FOR command
5511 The most interesting command to look at is the FOR command. In Tcl,
5512 the FOR command is normally implemented in C. Remember, FOR is a
5513 command just like any other command.
5515 When the ascii text containing the FOR command is parsed, the parser
5516 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
5520 @item The ascii text 'for'
5521 @item The start text
5522 @item The test expression
5527 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
5528 Remember @i{Rule #1 - Everything is a string.} The key point is this:
5529 Often many of those parameters are in @{curly-braces@} - thus the
5530 variables inside are not expanded or replaced until later.
5532 Remember that every Tcl command looks like the classic ``main( argc,
5533 argv )'' function in C. In JimTCL - they actually look like this:
5537 MyCommand( Jim_Interp *interp,
5539 Jim_Obj * const *argvs );
5542 Real Tcl is nearly identical. Although the newer versions have
5543 introduced a byte-code parser and intepreter, but at the core, it
5544 still operates in the same basic way.
5546 @subsection FOR command implementation
5548 To understand Tcl it is perhaps most helpful to see the FOR
5549 command. Remember, it is a COMMAND not a control flow structure.
5551 In Tcl there are two underlying C helper functions.
5553 Remember Rule #1 - You are a string.
5555 The @b{first} helper parses and executes commands found in an ascii
5556 string. Commands can be seperated by semicolons, or newlines. While
5557 parsing, variables are expanded via the quoting rules.
5559 The @b{second} helper evaluates an ascii string as a numerical
5560 expression and returns a value.
5562 Here is an example of how the @b{FOR} command could be
5563 implemented. The pseudo code below does not show error handling.
5565 void Execute_AsciiString( void *interp, const char *string );
5567 int Evaluate_AsciiExpression( void *interp, const char *string );
5570 MyForCommand( void *interp,
5575 SetResult( interp, "WRONG number of parameters");
5579 // argv[0] = the ascii string just like C
5581 // Execute the start statement.
5582 Execute_AsciiString( interp, argv[1] );
5586 i = Evaluate_AsciiExpression(interp, argv[2]);
5591 Execute_AsciiString( interp, argv[3] );
5593 // Execute the LOOP part
5594 Execute_AsciiString( interp, argv[4] );
5598 SetResult( interp, "" );
5603 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
5604 in the same basic way.
5606 @section OpenOCD Tcl Usage
5608 @subsection source and find commands
5609 @b{Where:} In many configuration files
5610 @* Example: @b{ source [find FILENAME] }
5611 @*Remember the parsing rules
5613 @item The FIND command is in square brackets.
5614 @* The FIND command is executed with the parameter FILENAME. It should
5615 find the full path to the named file. The RESULT is a string, which is
5616 substituted on the orginal command line.
5617 @item The command source is executed with the resulting filename.
5618 @* SOURCE reads a file and executes as a script.
5620 @subsection format command
5621 @b{Where:} Generally occurs in numerous places.
5622 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
5628 puts [format "The answer: %d" [expr $x * $y]]
5631 @item The SET command creates 2 variables, X and Y.
5632 @item The double [nested] EXPR command performs math
5633 @* The EXPR command produces numerical result as a string.
5635 @item The format command is executed, producing a single string
5636 @* Refer to Rule #1.
5637 @item The PUTS command outputs the text.
5639 @subsection Body or Inlined Text
5640 @b{Where:} Various TARGET scripts.
5643 proc someproc @{@} @{
5644 ... multiple lines of stuff ...
5646 $_TARGETNAME configure -event FOO someproc
5647 #2 Good - no variables
5648 $_TARGETNAME confgure -event foo "this ; that;"
5649 #3 Good Curly Braces
5650 $_TARGETNAME configure -event FOO @{
5653 #4 DANGER DANGER DANGER
5654 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
5657 @item The $_TARGETNAME is an OpenOCD variable convention.
5658 @*@b{$_TARGETNAME} represents the last target created, the value changes
5659 each time a new target is created. Remember the parsing rules. When
5660 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
5661 the name of the target which happens to be a TARGET (object)
5663 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
5664 @*There are 4 examples:
5666 @item The TCLBODY is a simple string that happens to be a proc name
5667 @item The TCLBODY is several simple commands seperated by semicolons
5668 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
5669 @item The TCLBODY is a string with variables that get expanded.
5672 In the end, when the target event FOO occurs the TCLBODY is
5673 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
5674 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
5676 Remember the parsing rules. In case #3, @{curly-braces@} mean the
5677 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
5678 and the text is evaluated. In case #4, they are replaced before the
5679 ``Target Object Command'' is executed. This occurs at the same time
5680 $_TARGETNAME is replaced. In case #4 the date will never
5681 change. @{BTW: [date] is perhaps a bad example, as of 28/nov/2008,
5682 Jim/OpenOCD does not have a date command@}
5684 @subsection Global Variables
5685 @b{Where:} You might discover this when writing your own procs @* In
5686 simple terms: Inside a PROC, if you need to access a global variable
5687 you must say so. See also ``upvar''. Example:
5689 proc myproc @{ @} @{
5690 set y 0 #Local variable Y
5691 global x #Global variable X
5692 puts [format "X=%d, Y=%d" $x $y]
5695 @section Other Tcl Hacks
5696 @b{Dynamic variable creation}
5698 # Dynamically create a bunch of variables.
5699 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
5701 set vn [format "BIT%d" $x]
5705 set $vn [expr (1 << $x)]
5708 @b{Dynamic proc/command creation}
5710 # One "X" function - 5 uart functions.
5711 foreach who @{A B C D E@}
5712 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
5716 @node Target Library
5717 @chapter Target Library
5718 @cindex Target Library
5720 OpenOCD comes with a target configuration script library. These scripts can be
5721 used as-is or serve as a starting point.
5723 The target library is published together with the OpenOCD executable and
5724 the path to the target library is in the OpenOCD script search path.
5725 Similarly there are example scripts for configuring the JTAG interface.
5727 The command line below uses the example parport configuration script
5728 that ship with OpenOCD, then configures the str710.cfg target and
5729 finally issues the init and reset commands. The communication speed
5730 is set to 10kHz for reset and 8MHz for post reset.
5733 openocd -f interface/parport.cfg -f target/str710.cfg \
5734 -c "init" -c "reset"
5737 To list the target scripts available:
5740 $ ls /usr/local/lib/openocd/target
5742 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
5743 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
5744 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
5745 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
5750 @node OpenOCD Concept Index
5751 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
5752 @comment case issue with ``Index.html'' and ``index.html''
5753 @comment Occurs when creating ``--html --no-split'' output
5754 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
5755 @unnumbered OpenOCD Concept Index
5759 @node Command and Driver Index
5760 @unnumbered Command and Driver Index