1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (openocd)
8 @title Open On-Chip Debugger (openocd)
10 @vskip 0pt plus 1filll
15 @node Top, About, , (dir)
18 The Manual always document the latest version of OpenOCD available from SVN.
21 * About:: About Openocd.
23 * Building:: Building Openocd
24 * Running:: Running Openocd
25 * Configuration:: Openocd Configuration.
26 * Commands:: Openocd Commands
27 * Sample Scripts:: Sample Target Scripts
28 * FAQ:: Frequently Asked Questions
29 * License:: GNU Free Documentation License
37 The Open On-Chip Debugger (openocd) aims to provide debugging, in-system programming
38 and boundary-scan testing for embedded target devices. The targets are interfaced
39 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
40 connection types in the future.
42 Openocd currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
43 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
44 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
45 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
47 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
48 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
49 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
55 Openocd has been created by Dominic Rath as part of a diploma thesis written at the
56 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
57 Others interested in improving the state of free and open debug and testing technology
58 are welcome to participate.
60 Other developers have contributed support for additional targets and flashes as well
61 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
65 @cindex building openocd
67 You can download the current SVN version with SVN client of your choice from the
68 following repositories:
70 (@uref{svn://svn.berlios.de/openocd/trunk}
74 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
76 Using the SVN command line client, you could use the following command to fetch the
77 latest version (make sure there is no (non-svn) directory called "openocd" in the
81 svn checkout svn://svn.berlios.de/openocd/trunk
84 Building the OpenOCD requires a recent version of the GNU autotools.
85 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
86 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
87 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
88 paths, resulting in obscure dependency errors (This is an observation I've gathered
89 from the logs of one user - correct me if I'm wrong).
91 You further need the appropriate driver files, if you want to build support for
92 a FTDI FT2232 based interface:
94 @item @b{ftdi2232} libftdi ((@uref{http://www.intra2net.com/opensource/ftdi/})
95 @item @b{ftd2xx} libftd2xx ((@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
96 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
97 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
100 Please note that the ftdi2232 variant (using libftdi) isn't supported under Cygwin.
101 You have to use the ftd2xx variant (using FTDI's D2XX) on Cygwin.
103 In general, the D2XX driver provides superior performance (several times as fast),
104 but has the draw-back of being binary-only - though that isn't as worse, as it isn't
105 a kernel module, only a user space library.
107 To build OpenOCD (on both Linux and Cygwin), use the following commands:
111 Bootstrap generates the configure script, and prepares building on your system.
115 Configure generates the Makefiles used to build OpenOCD
119 Make builds the OpenOCD, and places the final executable in ./src/
121 The configure script takes several options, specifying which JTAG interfaces
128 --enable-parport_ppdev
130 --enable-amtjtagaccel
132 --enable-ft2232_ftd2xx
133 @footnote{Using the latest D2XX drivers from FTDI and following their installation
134 instructions, I had to use @option{--enable-ft2232_libftd2xx} for the OpenOCD to
137 --enable-ft2232_libftdi
139 --with-ftd2xx=/path/to/d2xx/
142 If you want to access the parallel port using the PPDEV interface you have to specify
143 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
144 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
145 (see (@uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
147 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
148 absolute path containing no spaces.
150 Linux users should copy the various parts of the D2XX package to the appropriate
151 locations, i.e. /usr/include, /usr/lib.
155 @cindex running openocd
156 The OpenOCD runs as a daemon, waiting for connections from clients (Telnet or GDB).
157 Run with @option{--help} or @option{-h} to view the available command line arguments.
159 It reads its configuration by default from the file openocd.cfg located in the current
160 working directory. This may be overwritten with the @option{-f <configfile>} command line
163 To enable debug output (when reporting problems or working on OpenOCD itself), use
164 the @option{-d} command line switch. This sets the debug_level to "3", outputting
165 the most information, including debug messages. The default setting is "2", outputting
166 only informational messages, warnings and errors. You can also change this setting
167 from within a telnet or gdb session (@option{debug_level <n>}).
169 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
172 @chapter Configuration
173 @cindex configuration
174 The Open On-Chip Debugger (OpenOCD) runs as a daemon, and reads it current configuration
175 by default from the file openocd.cfg in the current directory. A different configuration
176 file can be specified with the @option{-f <conf.file>} given at the openocd command line.
178 The configuration file is used to specify on which ports the daemon listens for new
179 connections, the JTAG interface used to connect to the target, the layout of the JTAG
180 chain, the targets that should be debugged, and connected flashes.
182 @section Daemon configuration
185 @item @b{telnet_port} <@var{number}>
187 Port on which to listen for incoming telnet connections
188 @item @b{gdb_port} <@var{number}>
190 First port on which to listen for incoming GDB connections. The GDB port for the
191 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
192 @item @b{daemon_startup} <@var{mode}> either @samp{attach} or @samp{reset}
193 @cindex daemon_startup
194 Tells the OpenOCD whether it should reset the target when the daemon is launched, or
195 if it should just attach to the target.
198 @section JTAG interface configuration
201 @item @b{interface} <@var{name}>
203 Use the interface driver <@var{name}> to connect to the target. Currently supported
207 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
211 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
216 FTDI FT2232 based devices using either the open-source libftdi or the binary only
217 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
218 platform. The libftdi uses libusb, and should be portable to all systems that provide
223 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
228 @item @b{jtag_speed} <@var{number}>
230 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
231 speed. The actual effect of this option depends on the JTAG interface used.
233 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
235 The configuration of the reset signals available on the JTAG interface AND the target.
236 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
237 then OpenOCD can't use it. <@var{signals}> can be @samp{none}, @samp{trst_only},
238 @samp{srst_only} or @samp{trst_and_srst}.
239 [@var{combination}] is an optional value specifying broken reset signal implementations.
240 @samp{srst_pulls_trst} states that the testlogic is reset together with the reset of
241 the system (e.g. Philips LPC2000, "broken" board layout), @samp{trst_pulls_srst} says
242 that the system is reset together with the test logic (only hypothetical, I haven't
243 seen hardware with such a bug, and can be worked around).
245 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
246 reset lines to be specified. Possible values are @samp{trst_push_pull} (default)
247 and @samp{trst_open_drain} for the test reset signal, and @samp{srst_open_drain}
248 (default) and @samp{srst_push_pull} for the system reset. These values only affect
249 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
251 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
253 Describes the devices that form the JTAG daisy chain, with the first device being
254 the one closest to TDO. The parameters are the length of the instruction register
255 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
256 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
257 The IDCODE instruction will in future be used to query devices for their JTAG
258 identification code. This line is the same for all ARM7 and ARM9 devices.
259 Other devices, like CPLDs, require different parameters. An example configuration
260 line for a Xilinx XC9500 CPLD would look like this:
262 jtag_device 8 0x01 0x0e3 0xfe
264 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
265 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
266 The IDCODE instruction is 0xfe.
268 @item @b{jtag_nsrst_delay} <@var{ms}>
269 @cindex jtag_nsrst_delay
270 How long (in miliseconds) the OpenOCD should wait after deasserting nSRST before
271 starting new JTAG operations.
272 @item @b{jtag_ntrst_delay} <@var{ms}>
273 @cindex jtag_ntrst_delay
274 How long (in miliseconds) the OpenOCD should wait after deasserting nTRST before
275 starting new JTAG operations.
277 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
278 or on-chip features) keep a reset line asserted for some time after the external reset
282 @section parport options
285 @item @b{parport_port} <@var{number}>
287 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
288 the @file{/dev/parport} device
290 When using PPDEV to access the parallel port, use the number of the parallel port:
291 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
292 you may encounter a problem.
293 @item @b{parport_cable} <@var{name}>
294 @cindex parport_cable
295 The layout of the parallel port cable used to connect to the target.
296 Currently supported cables are
300 Original Wiggler layout, also supported by several clones, such
301 as the Olimex ARM-JTAG
302 @item old_amt_wiggler
303 @cindex old_amt_wiggler
304 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
305 version available from the website uses the original Wiggler layout ('@var{wiggler}')
308 Describes the connection of the Amontec Chameleon's CPLD when operated in
309 configuration mode. This is only used to program the Chameleon itself, not
313 Xilinx Parallel cable III.
316 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
317 This is also the layout used by the HollyGates design
318 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
325 @section amt_jtagaccel options
327 @item @b{parport_port} <@var{number}>
329 Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
330 @file{/dev/parport} device
332 @section ft2232 options
335 @item @b{ft2232_device_desc} <@var{description}>
336 @cindex ft2232_device_desc
337 The USB device description of the FTDI FT2232 device. If not specified, the FTDI
338 default value is used. This setting is only valid if compiled with FTD2XX support.
339 @item @b{ft2232_layout} <@var{name}>
340 @cindex ft2232_layout
341 The layout of the FT2232 GPIO signals used to control output-enables and reset
342 signals. Valid layouts are
345 The "USBJTAG-1" layout described in the original OpenOCD diploma thesis
347 Amontec JTAGkey and JTAGkey-tiny
353 American Microsystems M5960
355 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
356 SRST signals on external connector
360 Hitex STM32 Performance Stick
363 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
364 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
365 default values are used. This command is not available on Windows.
366 @item @b{ft2232_latency} <@var{ms}>
367 On some systems using ft2232 based JTAG interfaces the FT_Read function call in
368 ft2232_read() fails to return the expected number of bytes. This can be caused by
369 USB communication delays and has proved hard to reproduce and debug. Setting the
370 FT2232 latency timer to a larger value increases delays for short USB packages but it
371 also reduces the risk of timeouts before receiving the expected number of bytes.
372 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
375 @section ep93xx options
376 @cindex ep93xx options
377 Currently, there are no options available for the ep93xx interface.
380 @section Target configuration
383 @item @b{target} <@var{type}> <@var{endianess}> <@var{reset_mode}> <@var{JTAG pos}>
386 Defines a target that should be debugged. Currently supported types are:
399 If you want to use a target board that is not on this list, see Adding a new
402 Endianess may be @option{little} or @option{big}.
404 The reset_mode specifies what should happen to the target when a reset occurs:
408 Immediately request a target halt after reset. This allows targets to be debugged
409 from the very first instruction. This is only possible with targets and JTAG
410 interfaces that correctly implement the reset signals.
413 Similar to @option{reset_halt}, but executes the script file defined to handle the
414 'reset' event for the target. Like @option{reset_halt} this only works with
415 correct reset implementations.
418 Simply let the target run after a reset.
421 Let the target run for some time (default: 1s), and then request halt.
424 A combination of @option{reset_init} and @option{run_and_halt}. The target is allowed
425 to run for some time, then halted, and the @option{reset} event script is executed.
428 On JTAG interfaces / targets where system reset and test-logic reset can't be driven
429 completely independent (like the LPC2000 series), or where the JTAG interface is
430 unavailable for some time during startup (like the STR7 series), you can't use
431 @option{reset_halt} or @option{reset_init}.
433 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
434 @cindex target_script
435 Event is either @var{reset} or @var{post_halt} or @var{pre_resume}.
436 TODO: describe exact semantic of events
437 @item @b{run_and_halt_time} <@var{target#}> <@var{time_in_ms}>
438 @cindex run_and_halt_time
439 The amount of time the debugger should wait after releasing reset before it asserts
440 a debug request. This is used by the @option{run_and_halt} and @option{run_and_init}
442 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
443 <@var{backup}|@var{nobackup}>
445 Specifies a working area for the debugger to use. This may be used to speed-up
446 downloads to target memory and flash operations, or to perform otherwise unavailable
447 operations (some coprocessor operations on ARM7/9 systems, for example). The last
448 parameter decides whether the memory should be preserved <@var{backup}>. If possible, use
449 a working_area that doesn't need to be backed up, as that slows down operation.
452 @subsection arm7tdmi options
453 @cindex arm7tdmi options
454 target arm7tdmi <@var{endianess}> <@var{reset_mode}> <@var{jtag#}>
455 The arm7tdmi target definition requires at least one additional argument, specifying
456 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
457 The optional [@var{variant}] parameter has been removed in recent versions.
458 The correct feature set is determined at runtime.
460 @subsection arm720t options
461 @cindex arm720t options
462 ARM720t options are similar to ARM7TDMI options.
464 @subsection arm9tdmi options
465 @cindex arm9tdmi options
466 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
467 @option{arm920t}, @option{arm922t} and @option{arm940t}.
468 This enables the hardware single-stepping support found on these cores.
470 @subsection arm920t options
471 @cindex arm920t options
472 ARM920t options are similar to ARM9TDMI options.
474 @subsection arm966e options
475 @cindex arm966e options
476 ARM966e options are similar to ARM9TDMI options.
478 @subsection xscale options
479 @cindex xscale options
480 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
481 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
483 @section Flash configuration
484 @cindex Flash configuration
487 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
488 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
490 Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
491 and <@var{bus_width}> bytes using the selected flash <driver>.
493 @item @b{flash autoerase} <@option{on}|@option{off}>
494 @cindex flash autoerase
495 auto erase flash banks prior to writing. Currently only works when using
496 @option{flash write_image} command. Default is @option{off}.
499 @subsection lpc2000 options
500 @cindex lpc2000 options
502 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
503 <@var{clock}> [@var{calc_checksum}]
504 LPC flashes don't require the chip and bus width to be specified. Additional
505 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
506 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
507 of the target this flash belongs to (first is 0), the frequency at which the core
508 is currently running (in kHz - must be an integral number), and the optional keyword
509 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
512 @subsection cfi options
515 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
517 CFI flashes require the number of the target they're connected to as an additional
518 argument. The CFI driver makes use of a working area (specified for the target)
519 to significantly speed up operation.
521 @subsection at91sam7 options
522 @cindex at91sam7 options
524 @b{flash bank at91sam7} 0 0 0 0 <@var{target#>}>
525 AT91SAM7 flashes only require the target#, all other values are looked up after
526 reading the chip-id and type.
528 @subsection str7 options
531 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
532 variant can be either STR71x, STR73x or STR75x.
534 @subsection str9 options
537 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
538 The str9 needs the flash controller to be configured prior to Flash programming, eg.
540 str9x flash_config 0 4 2 0 0x80000
542 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
544 @subsection str9 options (str9xpec driver)
546 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
547 Before using the flash commands the turbo mode will need enabling using str9xpec
548 @option{enable_turbo} <@var{num>.}
550 Only use this driver for locking/unlocking the device or configuring the option bytes.
551 Use the standard str9 driver for programming.
553 @subsection stellaris (LM3Sxxx) options
554 @cindex stellaris (LM3Sxxx) options
556 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
557 stellaris flash plugin only require the target#.
559 @subsection stm32x options
560 @cindex stm32x options
562 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
563 stm32x flash plugin only require the target#.
569 The Open On-Chip Debugger (OpenOCD) allows user interaction through a telnet interface
570 (default: port 4444) and a GDB server (default: port 3333). The command line interpreter
571 is available from both the telnet interface and a GDB session. To issue commands to the
572 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
573 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
579 @item @b{sleep} <@var{msec}>
581 Wait for n milliseconds before resuming. Useful in connection with script files
582 (@var{script} command and @var{target_script} configuration).
586 Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet).
588 @item @b{debug_level} [@var{n}]
590 Display or adjust debug level to n<0-3>
592 @item @b{log_output} <@var{file}>
594 Redirect logging to <file> (default: stderr)
596 @item @b{script} <@var{file}>
598 Execute commands from <file>
602 @subsection Target state handling
604 @item @b{poll} [@option{on}|@option{off}]
606 Poll the target for its current state. If the target is in debug mode, architecture
607 specific information about the current state are printed. An optional parameter
608 allows continuous polling to be enabled and disabled.
612 Send a halt request to the target. The debugger signals the debug request,
613 and waits for the target to enter debug mode.
615 @item @b{resume} [@var{address}]
617 Resume the target at its current code position, or at an optional address.
619 @item @b{step} [@var{address}]
621 Single-step the target at its current code position, or at an optional address.
623 @item @b{reset} [@option{run}|@option{halt}|@option{init}|@option{run_and_halt}
624 |@option{run_and_init}]
626 Do a hard-reset. The optional parameter specifies what should happen after the reset.
627 This optional parameter overwrites the setting specified in the configuration file,
628 making the new behaviour the default for the @option{reset} command.
635 Immediately halt the target (works only with certain configurations).
638 Immediately halt the target, and execute the reset script (works only with certain
641 @cindex reset run_and_halt
642 Let the target run for a certain amount of time, then request a halt.
644 @cindex reset run_and_init
645 Let the target run for a certain amount of time, then request a halt. Execute the
646 reset script once the target entered debug mode.
650 @subsection Memory access commands
651 These commands allow accesses of a specific size to the memory system:
653 @item @b{mdw} <@var{addr}> [@var{count}]
656 @item @b{mdh} <@var{addr}> [@var{count}]
658 display memory half-words
659 @item @b{mdb} <@var{addr}> [@var{count}]
662 @item @b{mww} <@var{addr}> <@var{value}>
665 @item @b{mwh} <@var{addr}> <@var{value}>
667 write memory half-word
668 @item @b{mwb} <@var{addr}> <@var{value}>
672 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
674 Load image <@var{file}> to target memory at <@var{address}>
675 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
677 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
678 (binary) <@var{file}>.
679 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
681 Verify <@var{file}> to target memory starting at <@var{address}>.
682 @item @b{load_binary} <@var{file}> <@var{address}> [DEPRECATED]
684 Load binary <@var{file}> to target memory at <@var{address}>
685 @item @b{dump_binary} <@var{file}> <@var{address}> <@var{size}> [DEPRECATED]
687 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
688 (binary) <@var{file}>.
691 @subsection Flash commands
692 @cindex Flash commands
694 @item @b{flash banks}
696 List configured flash banks
697 @item @b{flash info} <@var{num}>
699 Print info about flash bank <@option{num}>
700 @item @b{flash probe} <@var{num}>
702 Identify the flash, or validate the parameters of the configured flash. Operation
703 depends on the flash type.
704 @item @b{flash erase_check} <@var{num}>
705 @cindex flash erase_check
706 Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
707 updates the erase state information displayed by @option{flash info}. That means you have
708 to issue an @option{erase_check} command after erasing or programming the device to get
710 @item @b{flash protect_check} <@var{num}>
711 @cindex flash protect_check
712 Check protection state of sectors in flash bank <num>.
713 @item @b{flash erase} <@var{num}> <@var{first}> <@var{last}>
715 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
716 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
717 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
719 @item @b{flash write} <@var{num}> <@var{file}> <@var{offset}> [DEPRECATED]
721 Write the binary <@var{file}> to flash bank <@var{num}>, starting at <@var{offset}>
722 bytes from the beginning of the bank. This command was replaced by the new command
723 @option{flash write_binary} using the same syntax.
724 @item @b{flash write_binary} <@var{num}> <@var{file}> <@var{offset}>
725 @cindex flash write_binary
726 Write the binary <@var{file}> to flash bank <@var{num}>, starting at
727 <@option{offset}> bytes from the beginning of the bank.
728 @item @b{flash write_image} <@var{file}> [@var{offset}] [@var{type}]
729 @cindex flash write_image
730 Write the image <@var{file}> to the current target's flash bank(s). A relocation
731 [@var{offset}] can be specified and the file [@var{type}] can be specified
732 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
733 (ELF file) or @option{s19} (Motorola s19).
734 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
735 @cindex flash protect
736 Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
737 <@var{last}> of @option{flash bank} <@var{num}>.
738 @item @b{flash auto_erase} <@var{on}|@var{off}>
739 @cindex flash auto_erase
740 Enable (@option{on}) to erase flash banks prior to writing using the flash @option{write_image} command
741 only. Default is (@option{off}), flash banks have to be erased using @option{flash erase} command.
745 @section Target Specific Commands
746 @cindex Target Specific Commands
748 @subsection AT91SAM7 specific commands
749 @cindex AT91SAM7 specific commands
750 The flash configuration is deduced from the chip identification register. The flash
751 controller handles erases automatically on a page (128/265 byte) basis so erase is
752 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
753 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
754 that can be erased separatly.Only an EraseAll command is supported by the controller
755 for each flash plane and this is called with
757 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
758 bulk erase flash planes first_plane to last_plane.
759 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
760 @cindex at91sam7 gpnvm
761 set or clear a gpnvm bit for the processor
764 @subsection STR9 specific commands
765 @cindex STR9 specific commands
766 These are flash specific commands when using the str9xpec driver.
768 @item @b{str9xpec enable_turbo} <@var{num}>
769 @cindex str9xpec enable_turbo
770 enable turbo mode, simply this will remove the str9 from the chain and talk
771 directly to the embedded flash controller.
772 @item @b{str9xpec disable_turbo} <@var{num}>
773 @cindex str9xpec disable_turbo
774 restore the str9 into jtag chain.
775 @item @b{str9xpec lock} <@var{num}>
776 @cindex str9xpec lock
777 lock str9 device. The str9 will only respond to an unlock command that will
779 @item @b{str9xpec unlock} <@var{num}>
780 @cindex str9xpec unlock
782 @item @b{str9xpec options_read} <@var{num}>
783 @cindex str9xpec options_read
784 read str9 option bytes.
785 @item @b{str9xpec options_write} <@var{num}>
786 @cindex str9xpec options_write
787 write str9 option bytes.
790 @subsection STR9 configuration
791 @cindex STR9 configuration
793 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
794 <@var{BBADR}> <@var{NBBADR}>
795 @cindex str9x flash_config
796 Configure str9 flash controller.
798 eg. str9x flash_config 0 4 2 0 0x80000
800 BBSR - Boot Bank Size register
801 NBBSR - Non Boot Bank Size register
802 BBADR - Boot Bank Start Address register
803 NBBADR - Boot Bank Start Address register
807 @subsection STR9 option byte configuration
808 @cindex STR9 option byte configuration
810 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
811 @cindex str9xpec options_cmap
812 configure str9 boot bank.
813 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
814 @cindex str9xpec options_lvdthd
815 configure str9 lvd threshold.
816 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
817 @cindex str9xpec options_lvdsel
818 configure str9 lvd source.
819 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
820 @cindex str9xpec options_lvdwarn
821 configure str9 lvd reset warning source.
824 @subsection STM32x specific commands
825 @cindex STM32x specific commands
827 These are flash specific commands when using the stm32x driver.
829 @item @b{stm32x lock} <@var{num}>
832 @item @b{stm32x unlock} <@var{num}>
833 @cindex stm32x unlock
835 @item @b{stm32x options_read} <@var{num}>
836 @cindex stm32x options_read
837 read stm32 option bytes.
838 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
839 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
840 @cindex stm32x options_write
841 write stm32 option bytes.
842 @item @b{stm32x mass_erase} <@var{num}>
843 @cindex stm32x mass_erase
844 mass erase flash memory.
848 @section Arcitecture Specific Commands
849 @cindex Arcitecture Specific Commands
851 @subsection ARMV4/5 specific commands
852 @cindex ARMV4/5 specific commands
854 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
855 or Intel XScale (XScale isn't supported yet).
857 @item @b{armv4_5 reg}
859 Display a list of all banked core registers, fetching the current value from every
860 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
862 @item @b{armv4_5 core_mode} [@option{arm}|@option{thumb}]
863 @cindex armv4_5 core_mode
864 Displays the core_mode, optionally changing it to either ARM or Thumb mode.
865 The target is resumed in the currently set @option{core_mode}.
868 @subsection ARM7/9 specific commands
869 @cindex ARM7/9 specific commands
871 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
872 ARM920t or ARM926EJ-S.
874 @item @b{arm7_9 sw_bkpts} <@option{enable}|@option{disable}>
875 @cindex arm7_9 sw_bkpts
876 Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
877 one of the watchpoint registers to implement software breakpoints. Disabling
878 SW Bkpts frees that register again.
879 @item @b{arm7_9 force_hw_bkpts} <@option{enable}|@option{disable}>
880 @cindex arm7_9 force_hw_bkpts
881 When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
882 breakpoints are turned into hardware breakpoints.
883 @item @b{arm7_9 dbgrq} <@option{enable}|@option{disable}>
885 Enable use of the DBGRQ bit to force entry into debug mode. This should be
886 safe for all but ARM7TDMI--S cores (like Philips LPC).
887 @item @b{arm7_9 fast_writes} <@option{enable}|@option{disable}>
888 @cindex arm7_9 fast_writes [DEPRECATED]
889 See @option{arm7_9 fast_memory_access} instead.
890 @item @b{arm7_9 fast_memory_access} <@option{enable}|@option{disable}>
891 @cindex arm7_9 fast_memory_access
892 Allow the OpenOCD to read and write memory without checking completion of
893 the operation. This provides a huge speed increase, especially with USB JTAG
894 cables (FT2232), but might be unsafe if used with targets running at a very low
895 speed, like the 32kHz startup clock of an AT91RM9200.
896 @item @b{arm7_9 dcc_downloads} <@option{enable}|@option{disable}>
897 @cindex arm7_9 dcc_downloads
898 Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
899 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
900 unsafe, especially with targets running at a very low speed. This command was introduced
901 with OpenOCD rev. 60.
904 @subsection ARM920T specific commands
905 @cindex ARM920T specific commands
908 @item @b{arm920t cache_info}
909 @cindex arm920t cache_info
910 Print information about the caches found. This allows you to see if your target
911 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
912 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
913 @cindex arm920t md<bhw>_phys
914 Display memory at physical address addr.
915 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
916 @cindex arm920t mw<bhw>_phys
917 Write memory at physical address addr.
918 @item @b{arm920t read_cache} <@var{filename}>
919 @cindex arm920t read_cache
920 Dump the content of ICache and DCache to a file.
921 @item @b{arm920t read_mmu} <@var{filename}>
922 @cindex arm920t read_mmu
923 Dump the content of the ITLB and DTLB to a file.
924 @item @b{arm920t virt2phys} <@var{VA}>
925 @cindex arm920t virt2phys
926 Translate a virtual address to a physical address.
930 @section Debug commands
931 @cindex Debug commands
932 The following commands give direct access to the core, and are most likely
933 only useful while debugging the OpenOCD.
935 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
936 @cindex arm7_9 write_xpsr
937 Immediately write either the current program status register (CPSR) or the saved
938 program status register (SPSR), without changing the register cache (as displayed
939 by the @option{reg} and @option{armv4_5 reg} commands).
940 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
941 <@var{0=cpsr},@var{1=spsr}>
942 @cindex arm7_9 write_xpsr_im8
943 Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
944 operation (similar to @option{write_xpsr}).
945 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
946 @cindex arm7_9 write_core_reg
947 Write a core register, without changing the register cache (as displayed by the
948 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
949 encoding of the [M4:M0] bits of the PSR.
953 @section JTAG commands
954 @cindex JTAG commands
958 Print current scan chain configuration.
961 Toggle reset lines <@var{trst}> <@var{srst}>.
962 @item @b{endstate} <@var{tap_state}>
964 Finish JTAG operations in <@var{tap_state}>.
965 @item @b{runtest} <@var{num_cycles}>
967 Move to Run-Test/Idle, and execute <@var{num_cycles}>
968 @item @b{statemove} [@var{tap_state}]
970 Move to current endstate or [@var{tap_state}]
973 Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
976 Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
977 @item @b{verify_ircapture}
978 @cindex verify_ircapture
979 Verify value captured during Capture-IR <@option{enable}|@option{disable}>
982 Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
985 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}]
989 @chapter Sample Scripts
992 This page will collect some script examples for different CPUs.
994 The configuration script can be divided in the following section:
996 @item deamon configuration
998 @item jtag scan chain
999 @item target configuration
1000 @item flash configuration
1003 Detailed information about each section can be found at OpenOCD configuration
1005 @section OMAP5912 Flash Debug
1006 @cindex OMAP5912 Flash Debug
1007 The following two scripts was used with an wiggler PP and and a TI OMAP5912
1008 dual core processor (@uref{http://www.ti.com}) on a OMAP5912 OSK board
1009 @uref{(http://www.spectrumdigital.com}).
1010 @subsection Openocd config
1012 #daemon configuration
1019 parport_cable wiggler
1022 #use combined on interfaces or targets that can't set TRST/SRST separately
1023 reset_config trst_and_srst
1026 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1027 jtag_device 38 0x0 0x0 0x0
1028 jtag_device 4 0x1 0x0 0xe
1029 jtag_device 8 0x0 0x0 0x0
1031 #target configuration
1032 daemon_startup reset
1034 #target <type> <endianness> <reset mode> <chainpos> <variant>
1035 target arm926ejs little run_and_init 1 arm926ejs
1036 target_script 0 reset omap5912_osk.init
1037 run_and_halt_time 0 30
1039 # omap5912 lcd frame buffer as working area
1040 working_area 0 0x20000000 0x3e800 nobackup
1042 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1043 flash bank cfi 0x00000000 0x1000000 2 2 0
1046 @subsection Openocd init
1058 mww 0xfffec808 0x000000f5
1059 mww 0xfffec808 0x000000a0
1061 mww 0xfffeb048 0x0000aaaa
1063 mww 0xfffeb048 0x00005555
1072 @section STR71x Script
1073 @cindex STR71x Script
1074 The following script was used with an Amontec JTAGkey and a STR710 / STR711 cpu:
1076 #daemon configuration
1082 ft2232_device_desc "Amontec JTAGkey A"
1083 ft2232_layout jtagkey
1084 ft2232_vid_pid 0x0403 0xcff8
1087 #use combined on interfaces or targets that can't set TRST/SRST separately
1088 reset_config trst_and_srst srst_pulls_trst
1091 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1092 jtag_device 4 0x1 0xf 0xe
1094 #target configuration
1095 daemon_startup reset
1097 #target <type> <startup mode>
1098 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1099 target arm7tdmi little run_and_halt 0 arm7tdmi
1100 run_and_halt_time 0 30
1102 working_area 0 0x2000C000 0x4000 nobackup
1104 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1105 flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
1108 @section STR750 Script
1109 @cindex STR750 Script
1110 The following script was used with an Amontec JTAGkey and a STR750 cpu:
1112 #daemon configuration
1118 ft2232_device_desc "Amontec JTAGkey A"
1119 ft2232_layout jtagkey
1120 ft2232_vid_pid 0x0403 0xcff8
1123 #use combined on interfaces or targets that can't set TRST/SRST separately
1124 #reset_config trst_and_srst srst_pulls_trst
1125 reset_config trst_and_srst srst_pulls_trst
1128 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1129 jtag_device 4 0x1 0xf 0xe
1131 #jtag nTRST and nSRST delay
1132 jtag_nsrst_delay 500
1133 jtag_ntrst_delay 500
1135 #target configuration
1136 daemon_startup reset
1138 #target <type> <startup mode>
1139 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1140 target arm7tdmi little run_and_halt 0 arm7tdmi
1141 run_and_halt_time 0 30
1143 working_area 0 0x40000000 0x4000 nobackup
1145 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1146 flash bank str7x 0x20000000 0x000040000 0 0 0 STR75x
1149 @section STR912 Script
1150 @cindex STR912 Script
1151 The following script was used with an Amontec JTAGkey and a STR912 cpu:
1153 #daemon configuration
1159 ft2232_device_desc "Amontec JTAGkey A"
1160 ft2232_layout jtagkey
1163 #use combined on interfaces or targets that can't set TRST/SRST separately
1164 reset_config trst_and_srst
1167 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1168 jtag_device 8 0x1 0x1 0xfe
1169 jtag_device 4 0x1 0xf 0xe
1170 jtag_device 5 0x1 0x1 0x1e
1172 #target configuration
1173 daemon_startup reset
1175 #target <type> <startup mode>
1176 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1177 target arm966e little reset_halt 1 arm966e
1178 run_and_halt_time 0 30
1180 working_area 0 0x50000000 16384 nobackup
1182 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1183 flash bank str9x 0x00000000 0x00080000 0 0 0
1186 @section STR912 comstick
1187 @cindex STR912 comstick Script
1188 The following script was used with a Hitex STR9 Comstick:
1190 #daemon configuration
1196 ft2232_device_desc "STR9-comStick A"
1197 ft2232_layout comstick
1200 jtag_nsrst_delay 100
1201 jtag_ntrst_delay 100
1203 #use combined on interfaces or targets that can't set TRST/SRST separately
1204 reset_config trst_and_srst
1207 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1208 jtag_device 8 0x1 0x1 0xfe
1209 jtag_device 4 0x1 0xf 0xe
1210 jtag_device 5 0x1 0x1 0x1e
1212 #target configuration
1213 daemon_startup reset
1215 #target <type> <startup mode>
1216 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1217 target arm966e little reset_halt 1 arm966e
1218 run_and_halt_time 0 30
1220 working_area 0 0x50000000 16384 nobackup
1222 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1223 flash bank str9x 0x00000000 0x00080000 0 0 0
1226 @section STM32x Script
1227 @cindex STM32x Script
1228 The following script was used with an Amontec JTAGkey and a STM32x cpu:
1230 #daemon configuration
1236 ft2232_device_desc "Amontec JTAGkey A"
1237 ft2232_layout jtagkey
1240 jtag_nsrst_delay 100
1241 jtag_ntrst_delay 100
1243 #use combined on interfaces or targets that can't set TRST/SRST separately
1244 reset_config trst_and_srst
1247 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1248 jtag_device 4 0x1 0xf 0xe
1249 jtag_device 5 0x1 0x1 0x1e
1251 #target configuration
1252 daemon_startup reset
1254 #target <type> <startup mode>
1255 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1256 target cortex_m3 little run_and_halt 0
1257 run_and_halt_time 0 30
1259 working_area 0 0x20000000 16384 nobackup
1261 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1262 flash bank stm32x 0x08000000 0x00010000 0 0 0
1265 @section STM32x Performance Stick
1266 @cindex STM32x Performance Stick Script
1267 The following script was used with the Hitex STM32 Performance Stick
1269 #daemon configuration
1275 ft2232_device_desc "STM32-PerformanceStick A"
1276 ft2232_layout stm32stick
1279 jtag_nsrst_delay 100
1280 jtag_ntrst_delay 100
1282 #use combined on interfaces or targets that can't set TRST/SRST separately
1283 reset_config trst_and_srst
1286 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1287 jtag_device 4 0x1 0xf 0xe
1288 jtag_device 5 0x1 0x1 0x1e
1289 jtag_device 4 0x1 0xf 0xe
1291 #target configuration
1292 daemon_startup reset
1294 #target <type> <startup mode>
1295 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1296 target cortex_m3 little run_and_halt 0
1297 run_and_halt_time 0 30
1299 working_area 0 0x20000000 16384 nobackup
1301 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1302 flash bank stm32x 0x08000000 0x00010000 0 0 0
1305 @section LPC2294 Script
1306 @cindex LPC2294 Script
1307 The following script was used with an Amontec JTAGkey and a LPC2294 cpu:
1309 #daemon configuration
1315 ft2232_device_desc "Amontec JTAGkey A"
1316 ft2232_layout jtagkey
1317 ft2232_vid_pid 0x0403 0xcff8
1320 #use combined on interfaces or targets that can't set TRST/SRST separately
1321 reset_config trst_and_srst srst_pulls_trst
1324 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1325 jtag_device 4 0x1 0xf 0xe
1327 #target configuration
1328 daemon_startup reset
1330 #target <type> <startup mode>
1331 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1332 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1333 run_and_halt_time 0 30
1335 working_area 0 0x40000000 0x40000 nobackup
1337 #flash configuration
1338 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1341 @section AT91R40008 Script
1342 @cindex AT91R40008 Script
1343 The following script was used with an Amontec JTAGkey and a AT91R40008 cpu:
1345 #daemon configuration
1351 ft2232_device_desc "Amontec JTAGkey A"
1352 ft2232_layout jtagkey
1353 ft2232_vid_pid 0x0403 0xcff8
1355 jtag_nsrst_delay 200
1356 jtag_ntrst_delay 200
1358 #use combined on interfaces or targets that can't set TRST/SRST separately
1359 reset_config srst_only srst_pulls_trst
1362 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1363 jtag_device 4 0x1 0xf 0xe
1365 #target configuration
1366 daemon_startup reset
1368 #target <type> <startup mode>
1369 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1370 target arm7tdmi little run_and_halt 0 arm7tdmi
1371 run_and_halt_time 0 30
1374 @section LPC2129 Script
1375 @cindex LPC2129 Script
1376 The following script was used with an wiggler PP and a LPC-2129 cpu:
1378 #daemon configuration
1385 parport_cable wiggler
1388 #use combined on interfaces or targets that can't set TRST/SRST separately
1389 reset_config trst_and_srst srst_pulls_trst
1392 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1393 jtag_device 4 0x1 0xf 0xe
1395 #target configuration
1396 daemon_startup reset
1398 #target <type> <startup mode>
1399 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1400 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1401 run_and_halt_time 0 30
1403 working_area 0 0x00000000 0x400000 nobackup
1405 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1406 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1409 @section AT91SAM7s Script
1410 @cindex AT91SAM7s Script
1411 The following script was used with an Olimex ARM-JTAG-OCD and a AT91SAM7S64 cpu:
1413 #daemon configuration
1419 ft2232_device_desc "Olimex OpenOCD JTAG A"
1420 ft2232_layout olimex-jtag
1421 ft2232_vid_pid 0x15BA 0x0003
1423 jtag_nsrst_delay 200
1424 jtag_ntrst_delay 200
1426 #use combined on interfaces or targets that can't set TRST/SRST separately
1427 reset_config srst_only srst_pulls_trst
1430 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1431 jtag_device 4 0x1 0xf 0xe
1433 #target configuration
1434 daemon_startup reset
1436 #target <type> <startup mode>
1437 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1438 target arm7tdmi little run_and_halt 0 arm7tdmi
1439 run_and_halt_time 0 30
1441 # flash-options AT91
1442 working_area 0 0x00200000 0x4000 nobackup
1443 flash bank at91sam7 0 0 0 0 0
1446 # erase command (telnet-interface) for complete flash:
1447 # flash erase <num> 0 numlockbits-1 (can be seen from output of flash info 0)
1448 # SAM7S64 with 16 lockbits and bank 0: flash erase 0 0 15
1449 # set/clear NVM-Bits:
1450 # at91sam7 gpnvm <num> <bit> <set|clear>
1451 # disable locking from SAM-BA:
1452 # flash protect 0 0 1 off
1455 @section XSCALE IXP42x Script
1456 @cindex XSCALE IXP42x Script
1457 The following script was used with an Amontec JTAGkey-Tiny and a xscale ixp42x cpu:
1459 #daemon configuration
1465 ft2232_device_desc "Amontec JTAGkey A"
1466 ft2232_layout jtagkey
1467 ft2232_vid_pid 0x0403 0xcff8
1469 jtag_nsrst_delay 200
1470 jtag_ntrst_delay 200
1472 #use combined on interfaces or targets that can't set TRST/SRST separately
1473 reset_config srst_only srst_pulls_trst
1476 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1477 jtag_device 7 0x1 0x7f 0x7e
1479 #target configuration
1480 daemon_startup reset
1482 #target <type> <startup mode>
1483 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1484 target xscale big run_and_halt 0 IXP42x
1485 run_and_halt_time 0 30
1488 @section Cirrus Logic EP9301 Script
1489 @cindex Cirrus Logic EP9301 Script
1490 The following script was used with FT2232 based JTAG interfaces and a
1491 Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
1493 #daemon configuration
1501 #ft2232_device_desc "Olimex OpenOCD JTAG"
1502 #ft2232_layout olimex-jtag
1503 #ft2232_vid_pid 0x15ba 0x0003
1505 #Amontec JTAGkey (and JTAGkey-Tiny)
1506 #Serial is only necessary if more than one JTAGkey is connected
1507 ft2232_device_desc "Amontec JTAGkey A"
1508 #ft2232_serial AMTJKV31
1509 #ft2232_serial T1P3S2W8
1510 ft2232_layout jtagkey
1511 ft2232_vid_pid 0x0403 0xcff8
1513 #wiggler/parallel port interface
1516 #parport_cable wiggler
1519 reset_config trst_and_srst
1522 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1523 jtag_device 4 0x1 0xf 0xe
1525 jtag_nsrst_delay 100
1526 jtag_ntrst_delay 100
1528 #target configuration
1529 daemon_startup attach
1531 #target <type> <endianess> <reset mode>
1532 target arm920t little reset_halt 0
1533 working_area 0 0x80014000 0x1000 backup
1535 #flash configuration
1536 #flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
1537 flash bank cfi 0x60000000 0x1000000 2 2 0
1540 @section Hilscher netX 100 / 500 Script
1541 @cindex Hilscher netX 100 / 500 Script
1542 The following script was used with an Amontec JTAGkey and a Hilscher
1545 #daemon configuration
1551 ft2232_device_desc "Amontec JTAGkey A"
1552 ft2232_layout jtagkey
1553 ft2232_vid_pid 0x0403 0xcff8
1556 #use combined on interfaces or targets that can't set TRST/SRST separately
1557 reset_config trst_and_srst
1560 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1561 jtag_device 4 0x1 0xf 0xe
1563 jtag_nsrst_delay 100
1564 jtag_ntrst_delay 100
1566 #target configuration
1567 daemon_startup reset
1569 #target <type> <endianness> <startup mode> <chainpos> <variant>
1570 target arm926ejs little run_and_halt 0 arm926ejs
1571 run_and_halt_time 0 500
1574 @section Marvell/Intel PXA270 Script
1575 @cindex Marvell/Intel PXA270 Script
1577 # config for Intel PXA270
1578 # not, as of 2007-06-22, openocd only works with the
1579 # libftd2xx library from ftdi. libftdi does not work.
1585 ft2232_layout olimex-jtag
1586 ft2232_vid_pid 0x15BA 0x0003
1587 ft2232_device_desc "Olimex OpenOCD JTAG"
1589 # set jtag_nsrst_delay to the delay introduced by your reset circuit
1590 # the rest of the needed delays are built into the openocd program
1591 jtag_nsrst_delay 260
1592 # set the jtag_ntrst_delay to the delay introduced by a reset circuit
1593 # the rest of the needed delays are built into the openocd program
1596 #use combined on interfaces or targets that can't set TRST/SRST separately
1597 reset_config trst_and_srst separate
1600 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1601 jtag_device 7 0x1 0x7f 0x7e
1603 #target configuration
1604 daemon_startup reset
1606 target xscale little reset_halt 0 pxa27x
1608 # maps to PXA internal RAM. If you are using a PXA255
1609 # you must initialize SDRAM or leave this option off
1610 working_area 0 0x5c000000 0x10000 nobackup
1612 run_and_halt_time 0 30
1614 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1615 # works for P30 flash
1616 flash bank cfi 0x00000000 0x1000000 2 4 0
1623 @item OpenOCD complains about a missing cygwin1.dll
1625 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1626 claims to come with all the necessary dlls. When using Cygwin, try launching
1627 the OpenOCD from the Cygwin shell.
1629 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1630 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1631 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1633 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1634 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1635 software breakpoints consume one of the two available hardware breakpoints,
1636 and are therefor disabled by default. If your code is running from RAM, you
1637 can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
1638 your code resides in Flash, you can't use software breakpoints, but you can force
1639 OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
1641 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
1642 and works sometimes fine.
1644 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
1645 clock at the time you're programming the flash. If you've specified the crystal's
1646 frequency, make sure the PLL is disabled, if you've specified the full core speed
1647 (e.g. 60MHz), make sure the PLL is enabled.
1649 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
1650 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
1651 out while waiting for end of scan, rtck was disabled".
1653 Make sure your PC's parallel port operates in EPP mode. You might have to try several
1654 settings in your PC Bios (ECP, EPP, and different versions of those).
1656 @item When debugging with the OpenOCD and GDB (plain GDB, Insight, or Eclipse),
1657 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
1658 memory read caused data abort".
1660 The errors are non-fatal, and are the result of GDB trying to trace stack frames
1661 beyond the last valid frame. It might be possible to prevent this by setting up
1662 a proper "initial" stack frame, if you happen to know what exactly has to
1663 be done, feel free to add this here.
1665 @item I get the following message in the OpenOCD console (or log file):
1666 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
1668 This warning doesn't indicate any serious problem, as long as you don't want to
1669 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
1670 trst_and_srst srst_pulls_trst} to tell the OpenOCD that either your board,
1671 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
1672 independently. With this setup, it's not possible to halt the core right out of
1673 reset, everything else should work fine.
1675 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
1676 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
1677 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
1678 quit with an error message. Is there a stability issue with OpenOCD?
1680 No, this is not a stability issue concering OpenOCD. Most users have solved
1681 this issue by simply using a self-powered USB Hub, which they connect their
1682 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
1683 supply stable enough for the Amontec JTAGkey to be operated.
1685 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
1686 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
1687 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
1688 What does that mean and what might be the reason for this?
1690 First of all, the reason might be the USB power supply. Try using a self-powered
1691 hub instead of a direct connection to your computer. Secondly, the error code 4
1692 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
1693 Chip ran into some sort of error - this points us to a USB problem.
1695 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
1696 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
1697 What does that mean and what might be the reason for this?
1699 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
1700 has closed the connection to OpenOCD. This might be a GDB issue.
1702 @item In the configuration file in the section where flash device configurations
1703 are described, there is a parameter for specifying the clock frequency for
1704 LPC2000 internal flash devices (e.g.
1705 @option{flash bank lpc2000 0x0 0x40000 0 0 lpc2000_v1 0 14746 calc_checksum}),
1706 which must be sepcified in kilohertz. However, I do have a quartz crystal of a
1707 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
1708 Is it possible to specify real numbers for the clock frequency?
1710 No. The clock frequency specified here must be given as an integral number.
1711 However, this clock frequency is used by the In-Application-Programming (IAP)
1712 routines of the LPC2000 family only, which seems to be very tolerant concerning
1713 the given clock frequency, so a slight difference between the specified clock
1714 frequency and the actual clock frequency will not cause any trouble.
1716 @item Do I have to keep a specific order for the commands in the configuration file?
1718 Well, yes and no. Commands can be given in arbitrary order, yet the devices
1719 listed for the JTAG scan chain must be given in the right order (jtag_device),
1720 with the device closest to the TDO-Pin being listed first. In general,
1721 whenever objects of the same type exist which require an index number, then
1722 these objects must be given in the right order (jtag_devices, targets and flash
1723 banks - a target references a jtag_device and a flash bank references a target).
1725 @item Sometimes my debugging session terminates with an error. When I look into the
1726 log file, I can see these error messages: Error: arm7_9_common.c:561
1727 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP