1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * NAND Flash Commands:: NAND Flash Commands
77 * PLD/FPGA Commands:: PLD/FPGA Commands
78 * General Commands:: General Commands
79 * Architecture and Core Commands:: Architecture and Core Commands
80 * JTAG Commands:: JTAG Commands
81 * Boundary Scan Commands:: Boundary Scan Commands
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
101 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
102 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
107 @section What is OpenOCD?
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board can be directly connected to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD only supports
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
154 based, parallel port based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
159 Cortex-M3 (Stellaris LM3, ST STM32 and Energy Micro EFM32) based cores to be
160 debugged via the GDB protocol.
162 @b{Flash Programing:} Flash writing is supported for external CFI
163 compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) controller is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{http://openocd.sourceforge.net/}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{http://openocd.sourceforge.net/doc/html/index.html}
182 PDF form is likewise published at:
184 @uref{http://openocd.sourceforge.net/doc/pdf/openocd.pdf}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
209 @chapter OpenOCD Developer Resources
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD GIT Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a GIT repository hosted at SourceForge. The repository URL is:
225 @uref{git://git.code.sf.net/p/openocd/code}
229 @uref{http://git.code.sf.net/p/openocd/code}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{http://repo.or.cz/r/openocd.git}
235 With standard GIT tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a GIT client:
241 @uref{http://repo.or.cz/w/openocd.git}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{http://openocd.sourceforge.net/doc/doxygen/html/index.html}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration in the top of the source tree.
264 @section OpenOCD Developer Mailing List
266 The OpenOCD Developer Mailing List provides the primary means of
267 communication between developers:
269 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
271 Discuss and submit patches to this list.
272 The @file{HACKING} file contains basic information about how
275 @section OpenOCD Bug Database
277 During the 0.4.x release cycle the OpenOCD project team began
278 using Trac for its bug database:
280 @uref{https://sourceforge.net/apps/trac/openocd}
283 @node Debug Adapter Hardware
284 @chapter Debug Adapter Hardware
293 Defined: @b{dongle}: A small device that plugins into a computer and serves as
294 an adapter .... [snip]
296 In the OpenOCD case, this generally refers to @b{a small adapter} that
297 attaches to your computer via USB or the Parallel Printer Port. One
298 exception is the Zylin ZY1000, packaged as a small box you attach via
299 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
300 require any drivers to be installed on the developer PC. It also has
301 a built in web interface. It supports RTCK/RCLK or adaptive clocking
302 and has a built in relay to power cycle targets remotely.
305 @section Choosing a Dongle
307 There are several things you should keep in mind when choosing a dongle.
310 @item @b{Transport} Does it support the kind of communication that you need?
311 OpenOCD focusses mostly on JTAG. Your version may also support
312 other ways to communicate with target devices.
313 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
314 Does your dongle support it? You might need a level converter.
315 @item @b{Pinout} What pinout does your target board use?
316 Does your dongle support it? You may be able to use jumper
317 wires, or an "octopus" connector, to convert pinouts.
318 @item @b{Connection} Does your computer have the USB, printer, or
319 Ethernet port needed?
320 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
321 RTCK support? Also known as ``adaptive clocking''
324 @section Stand-alone JTAG Probe
326 The ZY1000 from Ultimate Solutions is technically not a dongle but a
327 stand-alone JTAG probe that unlikemost dongles doesn’t require any drivers
328 running on the developers host computer.
329 Once installed on a network using DHCP or a static IP assignment, users can
330 access the ZY1000 probe locally or remotely from any host with access to the
331 IP address assigned to the probe.
332 The ZY1000 provides an intuitive web interface with direct access to the
334 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
335 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
337 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
338 to power cycle the target remotely.
340 For more information, visit:
342 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/33-zylin-zy1000-jtag-probe}
344 @section USB FT2232 Based
346 There are many USB JTAG dongles on the market, many of them are based
347 on a chip from ``Future Technology Devices International'' (FTDI)
348 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
349 See: @url{http://www.ftdichip.com} for more information.
350 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
351 chips are starting to become available in JTAG adapters. Around 2012 a new
352 variant appeared - FT232H - this is a single-channel version of FT2232H.
353 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
356 The FT2232 chips are flexible enough to support some other
357 transport options, such as SWD or the SPI variants used to
358 program some chips. They have two communications channels,
359 and one can be used for a UART adapter at the same time the
360 other one is used to provide a debug adapter.
362 Also, some development boards integrate an FT2232 chip to serve as
363 a built-in low cost debug adapter and usb-to-serial solution.
367 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
369 @* See: @url{http://www.amontec.com/jtagkey.shtml}
371 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
373 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
375 @* See: @url{http://www.signalyzer.com}
376 @item @b{Stellaris Eval Boards}
377 @* See: @url{http://www.ti.com} - The Stellaris eval boards
378 bundle FT2232-based JTAG and SWD support, which can be used to debug
379 the Stellaris chips. Using separate JTAG adapters is optional.
380 These boards can also be used in a "pass through" mode as JTAG adapters
381 to other target boards, disabling the Stellaris chip.
382 @item @b{TI/Luminary ICDI}
383 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
384 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
385 Evaluation Kits. Like the non-detachable FT2232 support on the other
386 Stellaris eval boards, they can be used to debug other target boards.
387 @item @b{olimex-jtag}
388 @* See: @url{http://www.olimex.com}
389 @item @b{Flyswatter/Flyswatter2}
390 @* See: @url{http://www.tincantools.com}
391 @item @b{turtelizer2}
393 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
394 @url{http://www.ethernut.de}
396 @* Link: @url{http://www.hitex.com/index.php?id=383}
398 @* Link @url{http://www.hitex.com/stm32-stick}
399 @item @b{axm0432_jtag}
400 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
401 to be available anymore as of April 2012.
403 @* Link @url{http://www.hitex.com/index.php?id=cortino}
404 @item @b{dlp-usb1232h}
405 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
406 @item @b{digilent-hs1}
407 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
409 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
411 @item @b{JTAG-lock-pick Tiny 2}
412 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
415 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
419 @section USB-JTAG / Altera USB-Blaster compatibles
421 These devices also show up as FTDI devices, but are not
422 protocol-compatible with the FT2232 devices. They are, however,
423 protocol-compatible among themselves. USB-JTAG devices typically consist
424 of a FT245 followed by a CPLD that understands a particular protocol,
425 or emulate this protocol using some other hardware.
427 They may appear under different USB VID/PID depending on the particular
428 product. The driver can be configured to search for any VID/PID pair
429 (see the section on driver commands).
432 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
433 @* Link: @url{http://ixo-jtag.sourceforge.net/}
434 @item @b{Altera USB-Blaster}
435 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
438 @section USB JLINK based
439 There are several OEM versions of the Segger @b{JLINK} adapter. It is
440 an example of a micro controller based JTAG adapter, it uses an
441 AT91SAM764 internally.
444 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
445 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
446 @item @b{SEGGER JLINK}
447 @* Link: @url{http://www.segger.com/jlink.html}
449 @* Link: @url{http://www.iar.com/en/products/hardware-debug-probes/iar-j-link/}
452 @section USB RLINK based
453 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
454 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
455 SWD and not JTAG, thus not supported.
458 @item @b{Raisonance RLink}
459 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
460 @item @b{STM32 Primer}
461 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
462 @item @b{STM32 Primer2}
463 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
466 @section USB ST-LINK based
467 ST Micro has an adapter called @b{ST-LINK}.
468 They only work with ST Micro chips, notably STM32 and STM8.
472 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
473 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
475 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
476 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
479 For info the original ST-LINK enumerates using the mass storage usb class, however
480 it's implementation is completely broken. The result is this causes issues under linux.
481 The simplest solution is to get linux to ignore the ST-LINK using one of the following methods:
483 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
484 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
487 @section USB TI/Stellaris ICDI based
488 Texas Instruments has an adapter called @b{ICDI}.
489 It is not to be confused with the FTDI based adapters that were originally fitted to their
490 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
495 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
497 @item @b{USB - Presto}
498 @* Link: @url{http://tools.asix.net/prg_presto.htm}
500 @item @b{Versaloon-Link}
501 @* Link: @url{http://www.versaloon.com}
503 @item @b{ARM-JTAG-EW}
504 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
507 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
510 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
513 @* Link: @url{http://code.google.com/p/estick-jtag/}
515 @item @b{Keil ULINK v1}
516 @* Link: @url{http://www.keil.com/ulink1/}
519 @section IBM PC Parallel Printer Port Based
521 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
522 and the Macraigor Wiggler. There are many clones and variations of
525 Note that parallel ports are becoming much less common, so if you
526 have the choice you should probably avoid these adapters in favor
531 @item @b{Wiggler} - There are many clones of this.
532 @* Link: @url{http://www.macraigor.com/wiggler.htm}
534 @item @b{DLC5} - From XILINX - There are many clones of this
535 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
536 produced, PDF schematics are easily found and it is easy to make.
538 @item @b{Amontec - JTAG Accelerator}
539 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
542 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
544 @item @b{Wiggler_ntrst_inverted}
545 @* Yet another variation - See the source code, src/jtag/parport.c
547 @item @b{old_amt_wiggler}
548 @* Unknown - probably not on the market today
551 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
554 @* Link: @url{http://www.amontec.com/chameleon.shtml}
560 @* ispDownload from Lattice Semiconductor
561 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
564 @* From ST Microsystems;
565 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
573 @* An EP93xx based Linux machine using the GPIO pins directly.
576 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
578 @item @b{bcm2835gpio}
579 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
584 @chapter About Jim-Tcl
588 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
589 This programming language provides a simple and extensible
592 All commands presented in this Guide are extensions to Jim-Tcl.
593 You can use them as simple commands, without needing to learn
594 much of anything about Tcl.
595 Alternatively, can write Tcl programs with them.
597 You can learn more about Jim at its website, @url{http://jim.berlios.de}.
598 There is an active and responsive community, get on the mailing list
599 if you have any questions. Jim-Tcl maintainers also lurk on the
600 OpenOCD mailing list.
603 @item @b{Jim vs. Tcl}
604 @* Jim-Tcl is a stripped down version of the well known Tcl language,
605 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
606 fewer features. Jim-Tcl is several dozens of .C files and .H files and
607 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
608 4.2 MB .zip file containing 1540 files.
610 @item @b{Missing Features}
611 @* Our practice has been: Add/clone the real Tcl feature if/when
612 needed. We welcome Jim-Tcl improvements, not bloat. Also there
613 are a large number of optional Jim-Tcl features that are not
617 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
618 command interpreter today is a mixture of (newer)
619 Jim-Tcl commands, and (older) the orginal command interpreter.
622 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
623 can type a Tcl for() loop, set variables, etc.
624 Some of the commands documented in this guide are implemented
625 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
627 @item @b{Historical Note}
628 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
629 before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
630 as a git submodule, which greatly simplified upgrading Jim Tcl
631 to benefit from new features and bugfixes in Jim Tcl.
633 @item @b{Need a crash course in Tcl?}
634 @*@xref{Tcl Crash Course}.
639 @cindex command line options
641 @cindex directory search
643 Properly installing OpenOCD sets up your operating system to grant it access
644 to the debug adapters. On Linux, this usually involves installing a file
645 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
646 complex and confusing driver configuration for every peripheral. Such issues
647 are unique to each operating system, and are not detailed in this User's Guide.
649 Then later you will invoke the OpenOCD server, with various options to
650 tell it how each debug session should work.
651 The @option{--help} option shows:
655 --help | -h display this help
656 --version | -v display OpenOCD version
657 --file | -f use configuration file <name>
658 --search | -s dir to search for config files and scripts
659 --debug | -d set debug level <0-3>
660 --log_output | -l redirect log output to file <name>
661 --command | -c run <command>
664 If you don't give any @option{-f} or @option{-c} options,
665 OpenOCD tries to read the configuration file @file{openocd.cfg}.
666 To specify one or more different
667 configuration files, use @option{-f} options. For example:
670 openocd -f config1.cfg -f config2.cfg -f config3.cfg
673 Configuration files and scripts are searched for in
675 @item the current directory,
676 @item any search dir specified on the command line using the @option{-s} option,
677 @item any search dir specified using the @command{add_script_search_dir} command,
678 @item @file{$HOME/.openocd} (not on Windows),
679 @item the site wide script library @file{$pkgdatadir/site} and
680 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
682 The first found file with a matching file name will be used.
685 Don't try to use configuration script names or paths which
686 include the "#" character. That character begins Tcl comments.
689 @section Simple setup, no customization
691 In the best case, you can use two scripts from one of the script
692 libraries, hook up your JTAG adapter, and start the server ... and
693 your JTAG setup will just work "out of the box". Always try to
694 start by reusing those scripts, but assume you'll need more
695 customization even if this works. @xref{OpenOCD Project Setup}.
697 If you find a script for your JTAG adapter, and for your board or
698 target, you may be able to hook up your JTAG adapter then start
702 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
705 You might also need to configure which reset signals are present,
706 using @option{-c 'reset_config trst_and_srst'} or something similar.
707 If all goes well you'll see output something like
710 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
711 For bug reports, read
712 http://openocd.sourceforge.net/doc/doxygen/bugs.html
713 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
714 (mfg: 0x23b, part: 0xba00, ver: 0x3)
717 Seeing that "tap/device found" message, and no warnings, means
718 the JTAG communication is working. That's a key milestone, but
719 you'll probably need more project-specific setup.
721 @section What OpenOCD does as it starts
723 OpenOCD starts by processing the configuration commands provided
724 on the command line or, if there were no @option{-c command} or
725 @option{-f file.cfg} options given, in @file{openocd.cfg}.
726 @xref{configurationstage,,Configuration Stage}.
727 At the end of the configuration stage it verifies the JTAG scan
728 chain defined using those commands; your configuration should
729 ensure that this always succeeds.
730 Normally, OpenOCD then starts running as a daemon.
731 Alternatively, commands may be used to terminate the configuration
732 stage early, perform work (such as updating some flash memory),
733 and then shut down without acting as a daemon.
735 Once OpenOCD starts running as a daemon, it waits for connections from
736 clients (Telnet, GDB, Other) and processes the commands issued through
739 If you are having problems, you can enable internal debug messages via
740 the @option{-d} option.
742 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
743 @option{-c} command line switch.
745 To enable debug output (when reporting problems or working on OpenOCD
746 itself), use the @option{-d} command line switch. This sets the
747 @option{debug_level} to "3", outputting the most information,
748 including debug messages. The default setting is "2", outputting only
749 informational messages, warnings and errors. You can also change this
750 setting from within a telnet or gdb session using @command{debug_level<n>}
751 (@pxref{debuglevel,,debug_level}).
753 You can redirect all output from the daemon to a file using the
754 @option{-l <logfile>} switch.
756 Note! OpenOCD will launch the GDB & telnet server even if it can not
757 establish a connection with the target. In general, it is possible for
758 the JTAG controller to be unresponsive until the target is set up
759 correctly via e.g. GDB monitor commands in a GDB init script.
761 @node OpenOCD Project Setup
762 @chapter OpenOCD Project Setup
764 To use OpenOCD with your development projects, you need to do more than
765 just connecting the JTAG adapter hardware (dongle) to your development board
766 and then starting the OpenOCD server.
767 You also need to configure that server so that it knows
768 about that adapter and board, and helps your work.
769 You may also want to connect OpenOCD to GDB, possibly
770 using Eclipse or some other GUI.
772 @section Hooking up the JTAG Adapter
774 Today's most common case is a dongle with a JTAG cable on one side
775 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
776 and a USB cable on the other.
777 Instead of USB, some cables use Ethernet;
778 older ones may use a PC parallel port, or even a serial port.
781 @item @emph{Start with power to your target board turned off},
782 and nothing connected to your JTAG adapter.
783 If you're particularly paranoid, unplug power to the board.
784 It's important to have the ground signal properly set up,
785 unless you are using a JTAG adapter which provides
786 galvanic isolation between the target board and the
789 @item @emph{Be sure it's the right kind of JTAG connector.}
790 If your dongle has a 20-pin ARM connector, you need some kind
791 of adapter (or octopus, see below) to hook it up to
792 boards using 14-pin or 10-pin connectors ... or to 20-pin
793 connectors which don't use ARM's pinout.
795 In the same vein, make sure the voltage levels are compatible.
796 Not all JTAG adapters have the level shifters needed to work
797 with 1.2 Volt boards.
799 @item @emph{Be certain the cable is properly oriented} or you might
800 damage your board. In most cases there are only two possible
801 ways to connect the cable.
802 Connect the JTAG cable from your adapter to the board.
803 Be sure it's firmly connected.
805 In the best case, the connector is keyed to physically
806 prevent you from inserting it wrong.
807 This is most often done using a slot on the board's male connector
808 housing, which must match a key on the JTAG cable's female connector.
809 If there's no housing, then you must look carefully and
810 make sure pin 1 on the cable hooks up to pin 1 on the board.
811 Ribbon cables are frequently all grey except for a wire on one
812 edge, which is red. The red wire is pin 1.
814 Sometimes dongles provide cables where one end is an ``octopus'' of
815 color coded single-wire connectors, instead of a connector block.
816 These are great when converting from one JTAG pinout to another,
817 but are tedious to set up.
818 Use these with connector pinout diagrams to help you match up the
819 adapter signals to the right board pins.
821 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
822 A USB, parallel, or serial port connector will go to the host which
823 you are using to run OpenOCD.
824 For Ethernet, consult the documentation and your network administrator.
826 For USB based JTAG adapters you have an easy sanity check at this point:
827 does the host operating system see the JTAG adapter? If that host is an
828 MS-Windows host, you'll need to install a driver before OpenOCD works.
830 @item @emph{Connect the adapter's power supply, if needed.}
831 This step is primarily for non-USB adapters,
832 but sometimes USB adapters need extra power.
834 @item @emph{Power up the target board.}
835 Unless you just let the magic smoke escape,
836 you're now ready to set up the OpenOCD server
837 so you can use JTAG to work with that board.
841 Talk with the OpenOCD server using
842 telnet (@code{telnet localhost 4444} on many systems) or GDB.
843 @xref{GDB and OpenOCD}.
845 @section Project Directory
847 There are many ways you can configure OpenOCD and start it up.
849 A simple way to organize them all involves keeping a
850 single directory for your work with a given board.
851 When you start OpenOCD from that directory,
852 it searches there first for configuration files, scripts,
853 files accessed through semihosting,
854 and for code you upload to the target board.
855 It is also the natural place to write files,
856 such as log files and data you download from the board.
858 @section Configuration Basics
860 There are two basic ways of configuring OpenOCD, and
861 a variety of ways you can mix them.
862 Think of the difference as just being how you start the server:
865 @item Many @option{-f file} or @option{-c command} options on the command line
866 @item No options, but a @dfn{user config file}
867 in the current directory named @file{openocd.cfg}
870 Here is an example @file{openocd.cfg} file for a setup
871 using a Signalyzer FT2232-based JTAG adapter to talk to
872 a board with an Atmel AT91SAM7X256 microcontroller:
875 source [find interface/signalyzer.cfg]
877 # GDB can also flash my flash!
878 gdb_memory_map enable
879 gdb_flash_program enable
881 source [find target/sam7x256.cfg]
884 Here is the command line equivalent of that configuration:
887 openocd -f interface/signalyzer.cfg \
888 -c "gdb_memory_map enable" \
889 -c "gdb_flash_program enable" \
890 -f target/sam7x256.cfg
893 You could wrap such long command lines in shell scripts,
894 each supporting a different development task.
895 One might re-flash the board with a specific firmware version.
896 Another might set up a particular debugging or run-time environment.
899 At this writing (October 2009) the command line method has
900 problems with how it treats variables.
901 For example, after @option{-c "set VAR value"}, or doing the
902 same in a script, the variable @var{VAR} will have no value
903 that can be tested in a later script.
906 Here we will focus on the simpler solution: one user config
907 file, including basic configuration plus any TCL procedures
908 to simplify your work.
910 @section User Config Files
911 @cindex config file, user
912 @cindex user config file
913 @cindex config file, overview
915 A user configuration file ties together all the parts of a project
917 One of the following will match your situation best:
920 @item Ideally almost everything comes from configuration files
921 provided by someone else.
922 For example, OpenOCD distributes a @file{scripts} directory
923 (probably in @file{/usr/share/openocd/scripts} on Linux).
924 Board and tool vendors can provide these too, as can individual
925 user sites; the @option{-s} command line option lets you say
926 where to find these files. (@xref{Running}.)
927 The AT91SAM7X256 example above works this way.
929 Three main types of non-user configuration file each have their
930 own subdirectory in the @file{scripts} directory:
933 @item @b{interface} -- one for each different debug adapter;
934 @item @b{board} -- one for each different board
935 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
938 Best case: include just two files, and they handle everything else.
939 The first is an interface config file.
940 The second is board-specific, and it sets up the JTAG TAPs and
941 their GDB targets (by deferring to some @file{target.cfg} file),
942 declares all flash memory, and leaves you nothing to do except
946 source [find interface/olimex-jtag-tiny.cfg]
947 source [find board/csb337.cfg]
950 Boards with a single microcontroller often won't need more
951 than the target config file, as in the AT91SAM7X256 example.
952 That's because there is no external memory (flash, DDR RAM), and
953 the board differences are encapsulated by application code.
955 @item Maybe you don't know yet what your board looks like to JTAG.
956 Once you know the @file{interface.cfg} file to use, you may
957 need help from OpenOCD to discover what's on the board.
958 Once you find the JTAG TAPs, you can just search for appropriate
960 configuration files ... or write your own, from the bottom up.
961 @xref{autoprobing,,Autoprobing}.
963 @item You can often reuse some standard config files but
964 need to write a few new ones, probably a @file{board.cfg} file.
965 You will be using commands described later in this User's Guide,
966 and working with the guidelines in the next chapter.
968 For example, there may be configuration files for your JTAG adapter
969 and target chip, but you need a new board-specific config file
970 giving access to your particular flash chips.
971 Or you might need to write another target chip configuration file
972 for a new chip built around the Cortex M3 core.
975 When you write new configuration files, please submit
976 them for inclusion in the next OpenOCD release.
977 For example, a @file{board/newboard.cfg} file will help the
978 next users of that board, and a @file{target/newcpu.cfg}
979 will help support users of any board using that chip.
983 You may may need to write some C code.
984 It may be as simple as a supporting a new ft2232 or parport
985 based adapter; a bit more involved, like a NAND or NOR flash
986 controller driver; or a big piece of work like supporting
987 a new chip architecture.
990 Reuse the existing config files when you can.
991 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
992 You may find a board configuration that's a good example to follow.
994 When you write config files, separate the reusable parts
995 (things every user of that interface, chip, or board needs)
996 from ones specific to your environment and debugging approach.
1000 For example, a @code{gdb-attach} event handler that invokes
1001 the @command{reset init} command will interfere with debugging
1002 early boot code, which performs some of the same actions
1003 that the @code{reset-init} event handler does.
1006 Likewise, the @command{arm9 vector_catch} command (or
1007 @cindex vector_catch
1008 its siblings @command{xscale vector_catch}
1009 and @command{cortex_m vector_catch}) can be a timesaver
1010 during some debug sessions, but don't make everyone use that either.
1011 Keep those kinds of debugging aids in your user config file,
1012 along with messaging and tracing setup.
1013 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1016 You might need to override some defaults.
1017 For example, you might need to move, shrink, or back up the target's
1018 work area if your application needs much SRAM.
1021 TCP/IP port configuration is another example of something which
1022 is environment-specific, and should only appear in
1023 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1026 @section Project-Specific Utilities
1028 A few project-specific utility
1029 routines may well speed up your work.
1030 Write them, and keep them in your project's user config file.
1032 For example, if you are making a boot loader work on a
1033 board, it's nice to be able to debug the ``after it's
1034 loaded to RAM'' parts separately from the finicky early
1035 code which sets up the DDR RAM controller and clocks.
1036 A script like this one, or a more GDB-aware sibling,
1040 proc ramboot @{ @} @{
1041 # Reset, running the target's "reset-init" scripts
1042 # to initialize clocks and the DDR RAM controller.
1043 # Leave the CPU halted.
1046 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1047 load_image u-boot.bin 0x20000000
1054 Then once that code is working you will need to make it
1055 boot from NOR flash; a different utility would help.
1056 Alternatively, some developers write to flash using GDB.
1057 (You might use a similar script if you're working with a flash
1058 based microcontroller application instead of a boot loader.)
1061 proc newboot @{ @} @{
1062 # Reset, leaving the CPU halted. The "reset-init" event
1063 # proc gives faster access to the CPU and to NOR flash;
1064 # "reset halt" would be slower.
1067 # Write standard version of U-Boot into the first two
1068 # sectors of NOR flash ... the standard version should
1069 # do the same lowlevel init as "reset-init".
1070 flash protect 0 0 1 off
1071 flash erase_sector 0 0 1
1072 flash write_bank 0 u-boot.bin 0x0
1073 flash protect 0 0 1 on
1075 # Reboot from scratch using that new boot loader.
1080 You may need more complicated utility procedures when booting
1082 That often involves an extra bootloader stage,
1083 running from on-chip SRAM to perform DDR RAM setup so it can load
1084 the main bootloader code (which won't fit into that SRAM).
1086 Other helper scripts might be used to write production system images,
1087 involving considerably more than just a three stage bootloader.
1089 @section Target Software Changes
1091 Sometimes you may want to make some small changes to the software
1092 you're developing, to help make JTAG debugging work better.
1093 For example, in C or assembly language code you might
1094 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1095 handling issues like:
1099 @item @b{Watchdog Timers}...
1100 Watchog timers are typically used to automatically reset systems if
1101 some application task doesn't periodically reset the timer. (The
1102 assumption is that the system has locked up if the task can't run.)
1103 When a JTAG debugger halts the system, that task won't be able to run
1104 and reset the timer ... potentially causing resets in the middle of
1105 your debug sessions.
1107 It's rarely a good idea to disable such watchdogs, since their usage
1108 needs to be debugged just like all other parts of your firmware.
1109 That might however be your only option.
1111 Look instead for chip-specific ways to stop the watchdog from counting
1112 while the system is in a debug halt state. It may be simplest to set
1113 that non-counting mode in your debugger startup scripts. You may however
1114 need a different approach when, for example, a motor could be physically
1115 damaged by firmware remaining inactive in a debug halt state. That might
1116 involve a type of firmware mode where that "non-counting" mode is disabled
1117 at the beginning then re-enabled at the end; a watchdog reset might fire
1118 and complicate the debug session, but hardware (or people) would be
1119 protected.@footnote{Note that many systems support a "monitor mode" debug
1120 that is a somewhat cleaner way to address such issues. You can think of
1121 it as only halting part of the system, maybe just one task,
1122 instead of the whole thing.
1123 At this writing, January 2010, OpenOCD based debugging does not support
1124 monitor mode debug, only "halt mode" debug.}
1126 @item @b{ARM Semihosting}...
1127 @cindex ARM semihosting
1128 When linked with a special runtime library provided with many
1129 toolchains@footnote{See chapter 8 "Semihosting" in
1130 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1131 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1132 The CodeSourcery EABI toolchain also includes a semihosting library.},
1133 your target code can use I/O facilities on the debug host. That library
1134 provides a small set of system calls which are handled by OpenOCD.
1135 It can let the debugger provide your system console and a file system,
1136 helping with early debugging or providing a more capable environment
1137 for sometimes-complex tasks like installing system firmware onto
1140 @item @b{ARM Wait-For-Interrupt}...
1141 Many ARM chips synchronize the JTAG clock using the core clock.
1142 Low power states which stop that core clock thus prevent JTAG access.
1143 Idle loops in tasking environments often enter those low power states
1144 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1146 You may want to @emph{disable that instruction} in source code,
1147 or otherwise prevent using that state,
1148 to ensure you can get JTAG access at any time.@footnote{As a more
1149 polite alternative, some processors have special debug-oriented
1150 registers which can be used to change various features including
1151 how the low power states are clocked while debugging.
1152 The STM32 DBGMCU_CR register is an example; at the cost of extra
1153 power consumption, JTAG can be used during low power states.}
1154 For example, the OpenOCD @command{halt} command may not
1155 work for an idle processor otherwise.
1157 @item @b{Delay after reset}...
1158 Not all chips have good support for debugger access
1159 right after reset; many LPC2xxx chips have issues here.
1160 Similarly, applications that reconfigure pins used for
1161 JTAG access as they start will also block debugger access.
1163 To work with boards like this, @emph{enable a short delay loop}
1164 the first thing after reset, before "real" startup activities.
1165 For example, one second's delay is usually more than enough
1166 time for a JTAG debugger to attach, so that
1167 early code execution can be debugged
1168 or firmware can be replaced.
1170 @item @b{Debug Communications Channel (DCC)}...
1171 Some processors include mechanisms to send messages over JTAG.
1172 Many ARM cores support these, as do some cores from other vendors.
1173 (OpenOCD may be able to use this DCC internally, speeding up some
1174 operations like writing to memory.)
1176 Your application may want to deliver various debugging messages
1177 over JTAG, by @emph{linking with a small library of code}
1178 provided with OpenOCD and using the utilities there to send
1179 various kinds of message.
1180 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1184 @section Target Hardware Setup
1186 Chip vendors often provide software development boards which
1187 are highly configurable, so that they can support all options
1188 that product boards may require. @emph{Make sure that any
1189 jumpers or switches match the system configuration you are
1192 Common issues include:
1196 @item @b{JTAG setup} ...
1197 Boards may support more than one JTAG configuration.
1198 Examples include jumpers controlling pullups versus pulldowns
1199 on the nTRST and/or nSRST signals, and choice of connectors
1200 (e.g. which of two headers on the base board,
1201 or one from a daughtercard).
1202 For some Texas Instruments boards, you may need to jumper the
1203 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1205 @item @b{Boot Modes} ...
1206 Complex chips often support multiple boot modes, controlled
1207 by external jumpers. Make sure this is set up correctly.
1208 For example many i.MX boards from NXP need to be jumpered
1209 to "ATX mode" to start booting using the on-chip ROM, when
1210 using second stage bootloader code stored in a NAND flash chip.
1212 Such explicit configuration is common, and not limited to
1213 booting from NAND. You might also need to set jumpers to
1214 start booting using code loaded from an MMC/SD card; external
1215 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1216 flash; some external host; or various other sources.
1219 @item @b{Memory Addressing} ...
1220 Boards which support multiple boot modes may also have jumpers
1221 to configure memory addressing. One board, for example, jumpers
1222 external chipselect 0 (used for booting) to address either
1223 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1224 or NAND flash. When it's jumpered to address NAND flash, that
1225 board must also be told to start booting from on-chip ROM.
1227 Your @file{board.cfg} file may also need to be told this jumper
1228 configuration, so that it can know whether to declare NOR flash
1229 using @command{flash bank} or instead declare NAND flash with
1230 @command{nand device}; and likewise which probe to perform in
1231 its @code{reset-init} handler.
1233 A closely related issue is bus width. Jumpers might need to
1234 distinguish between 8 bit or 16 bit bus access for the flash
1235 used to start booting.
1237 @item @b{Peripheral Access} ...
1238 Development boards generally provide access to every peripheral
1239 on the chip, sometimes in multiple modes (such as by providing
1240 multiple audio codec chips).
1241 This interacts with software
1242 configuration of pin multiplexing, where for example a
1243 given pin may be routed either to the MMC/SD controller
1244 or the GPIO controller. It also often interacts with
1245 configuration jumpers. One jumper may be used to route
1246 signals to an MMC/SD card slot or an expansion bus (which
1247 might in turn affect booting); others might control which
1248 audio or video codecs are used.
1252 Plus you should of course have @code{reset-init} event handlers
1253 which set up the hardware to match that jumper configuration.
1254 That includes in particular any oscillator or PLL used to clock
1255 the CPU, and any memory controllers needed to access external
1256 memory and peripherals. Without such handlers, you won't be
1257 able to access those resources without working target firmware
1258 which can do that setup ... this can be awkward when you're
1259 trying to debug that target firmware. Even if there's a ROM
1260 bootloader which handles a few issues, it rarely provides full
1261 access to all board-specific capabilities.
1264 @node Config File Guidelines
1265 @chapter Config File Guidelines
1267 This chapter is aimed at any user who needs to write a config file,
1268 including developers and integrators of OpenOCD and any user who
1269 needs to get a new board working smoothly.
1270 It provides guidelines for creating those files.
1272 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1273 with files including the ones listed here.
1274 Use them as-is where you can; or as models for new files.
1276 @item @file{interface} ...
1277 These are for debug adapters.
1278 Files that configure JTAG adapters go here.
1282 altera-usb-blaster.cfg hilscher_nxhx50_re.cfg openocd-usb-hs.cfg
1283 arm-jtag-ew.cfg hitex_str9-comstick.cfg openrd.cfg
1284 at91rm9200.cfg icebear.cfg osbdm.cfg
1285 axm0432.cfg jlink.cfg parport.cfg
1286 busblaster.cfg jtagkey2.cfg parport_dlc5.cfg
1287 buspirate.cfg jtagkey2p.cfg redbee-econotag.cfg
1288 calao-usb-a9260-c01.cfg jtagkey.cfg redbee-usb.cfg
1289 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg rlink.cfg
1290 calao-usb-a9260.cfg jtag-lock-pick_tiny_2.cfg sheevaplug.cfg
1291 chameleon.cfg kt-link.cfg signalyzer.cfg
1292 cortino.cfg lisa-l.cfg signalyzer-h2.cfg
1293 digilent-hs1.cfg luminary.cfg signalyzer-h4.cfg
1294 dlp-usb1232h.cfg luminary-icdi.cfg signalyzer-lite.cfg
1295 dummy.cfg luminary-lm3s811.cfg stlink-v1.cfg
1296 estick.cfg minimodule.cfg stlink-v2.cfg
1297 flashlink.cfg neodb.cfg stm32-stick.cfg
1298 flossjtag.cfg ngxtech.cfg sysfsgpio-raspberrypi.cfg
1299 flossjtag-noeeprom.cfg olimex-arm-usb-ocd.cfg ti-icdi.cfg
1300 flyswatter2.cfg olimex-arm-usb-ocd-h.cfg turtelizer2.cfg
1301 flyswatter.cfg olimex-arm-usb-tiny-h.cfg ulink.cfg
1302 ftdi olimex-jtag-tiny.cfg usb-jtag.cfg
1303 hilscher_nxhx10_etm.cfg oocdlink.cfg usbprog.cfg
1304 hilscher_nxhx500_etm.cfg opendous.cfg vpaclink.cfg
1305 hilscher_nxhx500_re.cfg opendous_ftdi.cfg vsllink.cfg
1306 hilscher_nxhx50_etm.cfg openocd-usb.cfg xds100v2.cfg
1309 axm0432.cfg hitex_str9-comstick.cfg olimex-jtag-tiny.cfg
1310 calao-usb-a9260-c01.cfg icebear.cfg oocdlink.cfg
1311 calao-usb-a9260-c02.cfg jtagkey2.cfg opendous_ftdi.cfg
1312 cortino.cfg jtagkey2p.cfg openocd-usb.cfg
1313 dlp-usb1232h.cfg jtagkey.cfg openocd-usb-hs.cfg
1314 dp_busblaster.cfg jtag-lock-pick_tiny_2.cfg openrd.cfg
1315 flossjtag.cfg kt-link.cfg redbee-econotag.cfg
1316 flossjtag-noeeprom.cfg lisa-l.cfg redbee-usb.cfg
1317 flyswatter2.cfg luminary.cfg sheevaplug.cfg
1318 flyswatter.cfg luminary-icdi.cfg signalyzer.cfg
1319 gw16042.cfg luminary-lm3s811.cfg signalyzer-lite.cfg
1320 hilscher_nxhx10_etm.cfg minimodule.cfg stm32-stick.cfg
1321 hilscher_nxhx500_etm.cfg neodb.cfg turtelizer2-revB.cfg
1322 hilscher_nxhx500_re.cfg ngxtech.cfg turtelizer2-revC.cfg
1323 hilscher_nxhx50_etm.cfg olimex-arm-usb-ocd.cfg vpaclink.cfg
1324 hilscher_nxhx50_re.cfg olimex-arm-usb-ocd-h.cfg xds100v2.cfg
1325 hitex_lpc1768stick.cfg olimex-arm-usb-tiny-h.cfg
1328 @item @file{board} ...
1329 think Circuit Board, PWA, PCB, they go by many names. Board files
1330 contain initialization items that are specific to a board.
1331 They reuse target configuration files, since the same
1332 microprocessor chips are used on many boards,
1333 but support for external parts varies widely. For
1334 example, the SDRAM initialization sequence for the board, or the type
1335 of external flash and what address it uses. Any initialization
1336 sequence to enable that external flash or SDRAM should be found in the
1337 board file. Boards may also contain multiple targets: two CPUs; or
1341 actux3.cfg lpc1850_spifi_generic.cfg
1342 am3517evm.cfg lpc4350_spifi_generic.cfg
1343 arm_evaluator7t.cfg lubbock.cfg
1344 at91cap7a-stk-sdram.cfg mcb1700.cfg
1345 at91eb40a.cfg microchip_explorer16.cfg
1346 at91rm9200-dk.cfg mini2440.cfg
1347 at91rm9200-ek.cfg mini6410.cfg
1348 at91sam9261-ek.cfg netgear-dg834v3.cfg
1349 at91sam9263-ek.cfg olimex_LPC2378STK.cfg
1350 at91sam9g20-ek.cfg olimex_lpc_h2148.cfg
1351 atmel_at91sam7s-ek.cfg olimex_sam7_ex256.cfg
1352 atmel_at91sam9260-ek.cfg olimex_sam9_l9260.cfg
1353 atmel_at91sam9rl-ek.cfg olimex_stm32_h103.cfg
1354 atmel_sam3n_ek.cfg olimex_stm32_h107.cfg
1355 atmel_sam3s_ek.cfg olimex_stm32_p107.cfg
1356 atmel_sam3u_ek.cfg omap2420_h4.cfg
1357 atmel_sam3x_ek.cfg open-bldc.cfg
1358 atmel_sam4s_ek.cfg openrd.cfg
1359 balloon3-cpu.cfg osk5912.cfg
1360 colibri.cfg phone_se_j100i.cfg
1361 crossbow_tech_imote2.cfg phytec_lpc3250.cfg
1362 csb337.cfg pic-p32mx.cfg
1363 csb732.cfg propox_mmnet1001.cfg
1364 da850evm.cfg pxa255_sst.cfg
1365 digi_connectcore_wi-9c.cfg redbee.cfg
1366 diolan_lpc4350-db1.cfg rsc-w910.cfg
1367 dm355evm.cfg sheevaplug.cfg
1368 dm365evm.cfg smdk6410.cfg
1369 dm6446evm.cfg spear300evb.cfg
1370 efikamx.cfg spear300evb_mod.cfg
1371 eir.cfg spear310evb20.cfg
1372 ek-lm3s1968.cfg spear310evb20_mod.cfg
1373 ek-lm3s3748.cfg spear320cpu.cfg
1374 ek-lm3s6965.cfg spear320cpu_mod.cfg
1375 ek-lm3s811.cfg steval_pcc010.cfg
1376 ek-lm3s811-revb.cfg stm320518_eval_stlink.cfg
1377 ek-lm3s8962.cfg stm32100b_eval.cfg
1378 ek-lm3s9b9x.cfg stm3210b_eval.cfg
1379 ek-lm3s9d92.cfg stm3210c_eval.cfg
1380 ek-lm4f120xl.cfg stm3210e_eval.cfg
1381 ek-lm4f232.cfg stm3220g_eval.cfg
1382 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1383 ethernut3.cfg stm3241g_eval.cfg
1384 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1385 hammer.cfg stm32f0discovery.cfg
1386 hilscher_nxdb500sys.cfg stm32f3discovery.cfg
1387 hilscher_nxeb500hmi.cfg stm32f4discovery.cfg
1388 hilscher_nxhx10.cfg stm32ldiscovery.cfg
1389 hilscher_nxhx500.cfg stm32vldiscovery.cfg
1390 hilscher_nxhx50.cfg str910-eval.cfg
1391 hilscher_nxsb100.cfg telo.cfg
1392 hitex_lpc1768stick.cfg ti_am335xevm.cfg
1393 hitex_lpc2929.cfg ti_beagleboard.cfg
1394 hitex_stm32-performancestick.cfg ti_beagleboard_xm.cfg
1395 hitex_str9-comstick.cfg ti_beaglebone.cfg
1396 iar_lpc1768.cfg ti_blaze.cfg
1397 iar_str912_sk.cfg ti_pandaboard.cfg
1398 icnova_imx53_sodimm.cfg ti_pandaboard_es.cfg
1399 icnova_sam9g45_sodimm.cfg topas910.cfg
1400 imx27ads.cfg topasa900.cfg
1401 imx27lnst.cfg twr-k60f120m.cfg
1402 imx28evk.cfg twr-k60n512.cfg
1403 imx31pdk.cfg tx25_stk5.cfg
1404 imx35pdk.cfg tx27_stk5.cfg
1405 imx53loco.cfg unknown_at91sam9260.cfg
1406 keil_mcb1700.cfg uptech_2410.cfg
1407 keil_mcb2140.cfg verdex.cfg
1408 kwikstik.cfg voipac.cfg
1409 linksys_nslu2.cfg voltcraft_dso-3062c.cfg
1410 lisa-l.cfg x300t.cfg
1411 logicpd_imx27.cfg zy1000.cfg
1414 @item @file{target} ...
1415 think chip. The ``target'' directory represents the JTAG TAPs
1417 which OpenOCD should control, not a board. Two common types of targets
1418 are ARM chips and FPGA or CPLD chips.
1419 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1420 the target config file defines all of them.
1423 aduc702x.cfg lpc1763.cfg
1424 am335x.cfg lpc1764.cfg
1425 amdm37x.cfg lpc1765.cfg
1426 ar71xx.cfg lpc1766.cfg
1427 at32ap7000.cfg lpc1767.cfg
1428 at91r40008.cfg lpc1768.cfg
1429 at91rm9200.cfg lpc1769.cfg
1430 at91sam3ax_4x.cfg lpc1788.cfg
1431 at91sam3ax_8x.cfg lpc17xx.cfg
1432 at91sam3ax_xx.cfg lpc1850.cfg
1433 at91sam3nXX.cfg lpc2103.cfg
1434 at91sam3sXX.cfg lpc2124.cfg
1435 at91sam3u1c.cfg lpc2129.cfg
1436 at91sam3u1e.cfg lpc2148.cfg
1437 at91sam3u2c.cfg lpc2294.cfg
1438 at91sam3u2e.cfg lpc2378.cfg
1439 at91sam3u4c.cfg lpc2460.cfg
1440 at91sam3u4e.cfg lpc2478.cfg
1441 at91sam3uxx.cfg lpc2900.cfg
1442 at91sam3XXX.cfg lpc2xxx.cfg
1443 at91sam4sd32x.cfg lpc3131.cfg
1444 at91sam4sXX.cfg lpc3250.cfg
1445 at91sam4XXX.cfg lpc4350.cfg
1446 at91sam7se512.cfg lpc4350.cfg.orig
1447 at91sam7sx.cfg mc13224v.cfg
1448 at91sam7x256.cfg nuc910.cfg
1449 at91sam7x512.cfg omap2420.cfg
1450 at91sam9260.cfg omap3530.cfg
1451 at91sam9260_ext_RAM_ext_flash.cfg omap4430.cfg
1452 at91sam9261.cfg omap4460.cfg
1453 at91sam9263.cfg omap5912.cfg
1454 at91sam9.cfg omapl138.cfg
1455 at91sam9g10.cfg pic32mx.cfg
1456 at91sam9g20.cfg pxa255.cfg
1457 at91sam9g45.cfg pxa270.cfg
1458 at91sam9rl.cfg pxa3xx.cfg
1459 atmega128.cfg readme.txt
1460 avr32.cfg samsung_s3c2410.cfg
1461 c100.cfg samsung_s3c2440.cfg
1462 c100config.tcl samsung_s3c2450.cfg
1463 c100helper.tcl samsung_s3c4510.cfg
1464 c100regs.tcl samsung_s3c6410.cfg
1465 cs351x.cfg sharp_lh79532.cfg
1466 davinci.cfg smp8634.cfg
1467 dragonite.cfg spear3xx.cfg
1468 dsp56321.cfg stellaris.cfg
1469 dsp568013.cfg stellaris_icdi.cfg
1470 dsp568037.cfg stm32f0x_stlink.cfg
1471 efm32_stlink.cfg stm32f1x.cfg
1472 epc9301.cfg stm32f1x_stlink.cfg
1473 faux.cfg stm32f2x.cfg
1474 feroceon.cfg stm32f2x_stlink.cfg
1475 fm3.cfg stm32f3x.cfg
1476 hilscher_netx10.cfg stm32f3x_stlink.cfg
1477 hilscher_netx500.cfg stm32f4x.cfg
1478 hilscher_netx50.cfg stm32f4x_stlink.cfg
1479 icepick.cfg stm32l.cfg
1480 imx21.cfg stm32lx_dual_bank.cfg
1481 imx25.cfg stm32lx_stlink.cfg
1482 imx27.cfg stm32_stlink.cfg
1483 imx28.cfg stm32w108_stlink.cfg
1484 imx31.cfg stm32xl.cfg
1485 imx35.cfg str710.cfg
1486 imx51.cfg str730.cfg
1487 imx53.cfg str750.cfg
1490 is5114.cfg test_reset_syntax_error.cfg
1491 ixp42x.cfg test_syntax_error.cfg
1493 k60.cfg ti_calypso.cfg
1494 lpc1751.cfg ti_dm355.cfg
1495 lpc1752.cfg ti_dm365.cfg
1496 lpc1754.cfg ti_dm6446.cfg
1497 lpc1756.cfg tmpa900.cfg
1498 lpc1758.cfg tmpa910.cfg
1499 lpc1759.cfg u8500.cfg
1501 @item @emph{more} ... browse for other library files which may be useful.
1502 For example, there are various generic and CPU-specific utilities.
1505 The @file{openocd.cfg} user config
1506 file may override features in any of the above files by
1507 setting variables before sourcing the target file, or by adding
1508 commands specific to their situation.
1510 @section Interface Config Files
1512 The user config file
1513 should be able to source one of these files with a command like this:
1516 source [find interface/FOOBAR.cfg]
1519 A preconfigured interface file should exist for every debug adapter
1520 in use today with OpenOCD.
1521 That said, perhaps some of these config files
1522 have only been used by the developer who created it.
1524 A separate chapter gives information about how to set these up.
1525 @xref{Debug Adapter Configuration}.
1526 Read the OpenOCD source code (and Developer's Guide)
1527 if you have a new kind of hardware interface
1528 and need to provide a driver for it.
1530 @section Board Config Files
1531 @cindex config file, board
1532 @cindex board config file
1534 The user config file
1535 should be able to source one of these files with a command like this:
1538 source [find board/FOOBAR.cfg]
1541 The point of a board config file is to package everything
1542 about a given board that user config files need to know.
1543 In summary the board files should contain (if present)
1546 @item One or more @command{source [target/...cfg]} statements
1547 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1548 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1549 @item Target @code{reset} handlers for SDRAM and I/O configuration
1550 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1551 @item All things that are not ``inside a chip''
1554 Generic things inside target chips belong in target config files,
1555 not board config files. So for example a @code{reset-init} event
1556 handler should know board-specific oscillator and PLL parameters,
1557 which it passes to target-specific utility code.
1559 The most complex task of a board config file is creating such a
1560 @code{reset-init} event handler.
1561 Define those handlers last, after you verify the rest of the board
1562 configuration works.
1564 @subsection Communication Between Config files
1566 In addition to target-specific utility code, another way that
1567 board and target config files communicate is by following a
1568 convention on how to use certain variables.
1570 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1571 Thus the rule we follow in OpenOCD is this: Variables that begin with
1572 a leading underscore are temporary in nature, and can be modified and
1573 used at will within a target configuration file.
1575 Complex board config files can do the things like this,
1576 for a board with three chips:
1579 # Chip #1: PXA270 for network side, big endian
1580 set CHIPNAME network
1582 source [find target/pxa270.cfg]
1583 # on return: _TARGETNAME = network.cpu
1584 # other commands can refer to the "network.cpu" target.
1585 $_TARGETNAME configure .... events for this CPU..
1587 # Chip #2: PXA270 for video side, little endian
1590 source [find target/pxa270.cfg]
1591 # on return: _TARGETNAME = video.cpu
1592 # other commands can refer to the "video.cpu" target.
1593 $_TARGETNAME configure .... events for this CPU..
1595 # Chip #3: Xilinx FPGA for glue logic
1598 source [find target/spartan3.cfg]
1601 That example is oversimplified because it doesn't show any flash memory,
1602 or the @code{reset-init} event handlers to initialize external DRAM
1603 or (assuming it needs it) load a configuration into the FPGA.
1604 Such features are usually needed for low-level work with many boards,
1605 where ``low level'' implies that the board initialization software may
1606 not be working. (That's a common reason to need JTAG tools. Another
1607 is to enable working with microcontroller-based systems, which often
1608 have no debugging support except a JTAG connector.)
1610 Target config files may also export utility functions to board and user
1611 config files. Such functions should use name prefixes, to help avoid
1614 Board files could also accept input variables from user config files.
1615 For example, there might be a @code{J4_JUMPER} setting used to identify
1616 what kind of flash memory a development board is using, or how to set
1617 up other clocks and peripherals.
1619 @subsection Variable Naming Convention
1620 @cindex variable names
1622 Most boards have only one instance of a chip.
1623 However, it should be easy to create a board with more than
1624 one such chip (as shown above).
1625 Accordingly, we encourage these conventions for naming
1626 variables associated with different @file{target.cfg} files,
1627 to promote consistency and
1628 so that board files can override target defaults.
1630 Inputs to target config files include:
1633 @item @code{CHIPNAME} ...
1634 This gives a name to the overall chip, and is used as part of
1635 tap identifier dotted names.
1636 While the default is normally provided by the chip manufacturer,
1637 board files may need to distinguish between instances of a chip.
1638 @item @code{ENDIAN} ...
1639 By default @option{little} - although chips may hard-wire @option{big}.
1640 Chips that can't change endianness don't need to use this variable.
1641 @item @code{CPUTAPID} ...
1642 When OpenOCD examines the JTAG chain, it can be told verify the
1643 chips against the JTAG IDCODE register.
1644 The target file will hold one or more defaults, but sometimes the
1645 chip in a board will use a different ID (perhaps a newer revision).
1648 Outputs from target config files include:
1651 @item @code{_TARGETNAME} ...
1652 By convention, this variable is created by the target configuration
1653 script. The board configuration file may make use of this variable to
1654 configure things like a ``reset init'' script, or other things
1655 specific to that board and that target.
1656 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1657 @code{_TARGETNAME1}, ... etc.
1660 @subsection The reset-init Event Handler
1661 @cindex event, reset-init
1662 @cindex reset-init handler
1664 Board config files run in the OpenOCD configuration stage;
1665 they can't use TAPs or targets, since they haven't been
1667 This means you can't write memory or access chip registers;
1668 you can't even verify that a flash chip is present.
1669 That's done later in event handlers, of which the target @code{reset-init}
1670 handler is one of the most important.
1672 Except on microcontrollers, the basic job of @code{reset-init} event
1673 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1674 Microcontrollers rarely use boot loaders; they run right out of their
1675 on-chip flash and SRAM memory. But they may want to use one of these
1676 handlers too, if just for developer convenience.
1679 Because this is so very board-specific, and chip-specific, no examples
1681 Instead, look at the board config files distributed with OpenOCD.
1682 If you have a boot loader, its source code will help; so will
1683 configuration files for other JTAG tools
1684 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1687 Some of this code could probably be shared between different boards.
1688 For example, setting up a DRAM controller often doesn't differ by
1689 much except the bus width (16 bits or 32?) and memory timings, so a
1690 reusable TCL procedure loaded by the @file{target.cfg} file might take
1691 those as parameters.
1692 Similarly with oscillator, PLL, and clock setup;
1693 and disabling the watchdog.
1694 Structure the code cleanly, and provide comments to help
1695 the next developer doing such work.
1696 (@emph{You might be that next person} trying to reuse init code!)
1698 The last thing normally done in a @code{reset-init} handler is probing
1699 whatever flash memory was configured. For most chips that needs to be
1700 done while the associated target is halted, either because JTAG memory
1701 access uses the CPU or to prevent conflicting CPU access.
1703 @subsection JTAG Clock Rate
1705 Before your @code{reset-init} handler has set up
1706 the PLLs and clocking, you may need to run with
1707 a low JTAG clock rate.
1708 @xref{jtagspeed,,JTAG Speed}.
1709 Then you'd increase that rate after your handler has
1710 made it possible to use the faster JTAG clock.
1711 When the initial low speed is board-specific, for example
1712 because it depends on a board-specific oscillator speed, then
1713 you should probably set it up in the board config file;
1714 if it's target-specific, it belongs in the target config file.
1716 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1717 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1718 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1719 Consult chip documentation to determine the peak JTAG clock rate,
1720 which might be less than that.
1723 On most ARMs, JTAG clock detection is coupled to the core clock, so
1724 software using a @option{wait for interrupt} operation blocks JTAG access.
1725 Adaptive clocking provides a partial workaround, but a more complete
1726 solution just avoids using that instruction with JTAG debuggers.
1729 If both the chip and the board support adaptive clocking,
1730 use the @command{jtag_rclk}
1731 command, in case your board is used with JTAG adapter which
1732 also supports it. Otherwise use @command{adapter_khz}.
1733 Set the slow rate at the beginning of the reset sequence,
1734 and the faster rate as soon as the clocks are at full speed.
1736 @anchor{theinitboardprocedure}
1737 @subsection The init_board procedure
1738 @cindex init_board procedure
1740 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1741 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1742 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1743 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1744 spearate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1745 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1746 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1747 Additionally ``linear'' board config file will most likely fail when target config file uses
1748 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1749 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1750 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1751 need to override @code{init_targets} defined in target config files when they only need to to add some specifics.
1753 Just as @code{init_targets}, the @code{init_board} procedure can be overriden by ``next level'' script (which sources
1754 the original), allowing greater code reuse.
1757 ### board_file.cfg ###
1759 # source target file that does most of the config in init_targets
1760 source [find target/target.cfg]
1762 proc enable_fast_clock @{@} @{
1763 # enables fast on-board clock source
1764 # configures the chip to use it
1767 # initialize only board specifics - reset, clock, adapter frequency
1768 proc init_board @{@} @{
1769 reset_config trst_and_srst trst_pulls_srst
1771 $_TARGETNAME configure -event reset-init @{
1779 @section Target Config Files
1780 @cindex config file, target
1781 @cindex target config file
1783 Board config files communicate with target config files using
1784 naming conventions as described above, and may source one or
1785 more target config files like this:
1788 source [find target/FOOBAR.cfg]
1791 The point of a target config file is to package everything
1792 about a given chip that board config files need to know.
1793 In summary the target files should contain
1797 @item Add TAPs to the scan chain
1798 @item Add CPU targets (includes GDB support)
1799 @item CPU/Chip/CPU-Core specific features
1803 As a rule of thumb, a target file sets up only one chip.
1804 For a microcontroller, that will often include a single TAP,
1805 which is a CPU needing a GDB target, and its on-chip flash.
1807 More complex chips may include multiple TAPs, and the target
1808 config file may need to define them all before OpenOCD
1809 can talk to the chip.
1810 For example, some phone chips have JTAG scan chains that include
1811 an ARM core for operating system use, a DSP,
1812 another ARM core embedded in an image processing engine,
1813 and other processing engines.
1815 @subsection Default Value Boiler Plate Code
1817 All target configuration files should start with code like this,
1818 letting board config files express environment-specific
1819 differences in how things should be set up.
1822 # Boards may override chip names, perhaps based on role,
1823 # but the default should match what the vendor uses
1824 if @{ [info exists CHIPNAME] @} @{
1825 set _CHIPNAME $CHIPNAME
1827 set _CHIPNAME sam7x256
1830 # ONLY use ENDIAN with targets that can change it.
1831 if @{ [info exists ENDIAN] @} @{
1837 # TAP identifiers may change as chips mature, for example with
1838 # new revision fields (the "3" here). Pick a good default; you
1839 # can pass several such identifiers to the "jtag newtap" command.
1840 if @{ [info exists CPUTAPID ] @} @{
1841 set _CPUTAPID $CPUTAPID
1843 set _CPUTAPID 0x3f0f0f0f
1846 @c but 0x3f0f0f0f is for an str73x part ...
1848 @emph{Remember:} Board config files may include multiple target
1849 config files, or the same target file multiple times
1850 (changing at least @code{CHIPNAME}).
1852 Likewise, the target configuration file should define
1853 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1854 use it later on when defining debug targets:
1857 set _TARGETNAME $_CHIPNAME.cpu
1858 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1861 @subsection Adding TAPs to the Scan Chain
1862 After the ``defaults'' are set up,
1863 add the TAPs on each chip to the JTAG scan chain.
1864 @xref{TAP Declaration}, and the naming convention
1867 In the simplest case the chip has only one TAP,
1868 probably for a CPU or FPGA.
1869 The config file for the Atmel AT91SAM7X256
1870 looks (in part) like this:
1873 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1876 A board with two such at91sam7 chips would be able
1877 to source such a config file twice, with different
1878 values for @code{CHIPNAME}, so
1879 it adds a different TAP each time.
1881 If there are nonzero @option{-expected-id} values,
1882 OpenOCD attempts to verify the actual tap id against those values.
1883 It will issue error messages if there is mismatch, which
1884 can help to pinpoint problems in OpenOCD configurations.
1887 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1888 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1889 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1890 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1891 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1894 There are more complex examples too, with chips that have
1895 multiple TAPs. Ones worth looking at include:
1898 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1899 plus a JRC to enable them
1900 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1901 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1902 is not currently used)
1905 @subsection Add CPU targets
1907 After adding a TAP for a CPU, you should set it up so that
1908 GDB and other commands can use it.
1909 @xref{CPU Configuration}.
1910 For the at91sam7 example above, the command can look like this;
1911 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1912 to little endian, and this chip doesn't support changing that.
1915 set _TARGETNAME $_CHIPNAME.cpu
1916 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1919 Work areas are small RAM areas associated with CPU targets.
1920 They are used by OpenOCD to speed up downloads,
1921 and to download small snippets of code to program flash chips.
1922 If the chip includes a form of ``on-chip-ram'' - and many do - define
1923 a work area if you can.
1924 Again using the at91sam7 as an example, this can look like:
1927 $_TARGETNAME configure -work-area-phys 0x00200000 \
1928 -work-area-size 0x4000 -work-area-backup 0
1931 @anchor{definecputargetsworkinginsmp}
1932 @subsection Define CPU targets working in SMP
1934 After setting targets, you can define a list of targets working in SMP.
1937 set _TARGETNAME_1 $_CHIPNAME.cpu1
1938 set _TARGETNAME_2 $_CHIPNAME.cpu2
1939 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1940 -coreid 0 -dbgbase $_DAP_DBG1
1941 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1942 -coreid 1 -dbgbase $_DAP_DBG2
1943 #define 2 targets working in smp.
1944 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1946 In the above example on cortex_a, 2 cpus are working in SMP.
1947 In SMP only one GDB instance is created and :
1949 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1950 @item halt command triggers the halt of all targets in the list.
1951 @item resume command triggers the write context and the restart of all targets in the list.
1952 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1953 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1954 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1957 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1958 command have been implemented.
1960 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1961 @item cortex_a smp_off : disable SMP mode, the current target is the one
1962 displayed in the GDB session, only this target is now controlled by GDB
1963 session. This behaviour is useful during system boot up.
1964 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1971 #0 : coreid 0 is displayed to GDB ,
1972 #-> -1 : next resume triggers a real resume
1973 > cortex_a smp_gdb 1
1975 #0 :coreid 0 is displayed to GDB ,
1976 #->1 : next resume displays coreid 1 to GDB
1980 #1 :coreid 1 is displayed to GDB ,
1981 #->1 : next resume displays coreid 1 to GDB
1982 > cortex_a smp_gdb -1
1984 #1 :coreid 1 is displayed to GDB,
1985 #->-1 : next resume triggers a real resume
1989 @subsection Chip Reset Setup
1991 As a rule, you should put the @command{reset_config} command
1992 into the board file. Most things you think you know about a
1993 chip can be tweaked by the board.
1995 Some chips have specific ways the TRST and SRST signals are
1996 managed. In the unusual case that these are @emph{chip specific}
1997 and can never be changed by board wiring, they could go here.
1998 For example, some chips can't support JTAG debugging without
2001 Provide a @code{reset-assert} event handler if you can.
2002 Such a handler uses JTAG operations to reset the target,
2003 letting this target config be used in systems which don't
2004 provide the optional SRST signal, or on systems where you
2005 don't want to reset all targets at once.
2006 Such a handler might write to chip registers to force a reset,
2007 use a JRC to do that (preferable -- the target may be wedged!),
2008 or force a watchdog timer to trigger.
2009 (For Cortex-M targets, this is not necessary. The target
2010 driver knows how to use trigger an NVIC reset when SRST is
2013 Some chips need special attention during reset handling if
2014 they're going to be used with JTAG.
2015 An example might be needing to send some commands right
2016 after the target's TAP has been reset, providing a
2017 @code{reset-deassert-post} event handler that writes a chip
2018 register to report that JTAG debugging is being done.
2019 Another would be reconfiguring the watchdog so that it stops
2020 counting while the core is halted in the debugger.
2022 JTAG clocking constraints often change during reset, and in
2023 some cases target config files (rather than board config files)
2024 are the right places to handle some of those issues.
2025 For example, immediately after reset most chips run using a
2026 slower clock than they will use later.
2027 That means that after reset (and potentially, as OpenOCD
2028 first starts up) they must use a slower JTAG clock rate
2029 than they will use later.
2030 @xref{jtagspeed,,JTAG Speed}.
2032 @quotation Important
2033 When you are debugging code that runs right after chip
2034 reset, getting these issues right is critical.
2035 In particular, if you see intermittent failures when
2036 OpenOCD verifies the scan chain after reset,
2037 look at how you are setting up JTAG clocking.
2040 @anchor{theinittargetsprocedure}
2041 @subsection The init_targets procedure
2042 @cindex init_targets procedure
2044 Target config files can either be ``linear'' (script executed line-by-line when parsed in
2045 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
2046 procedure called @code{init_targets}, which will be executed when entering run stage
2047 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
2048 Such procedure can be overriden by ``next level'' script (which sources the original).
2049 This concept faciliates code reuse when basic target config files provide generic configuration
2050 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
2051 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
2052 because sourcing them executes every initialization commands they provide.
2055 ### generic_file.cfg ###
2057 proc setup_my_chip @{chip_name flash_size ram_size@} @{
2058 # basic initialization procedure ...
2061 proc init_targets @{@} @{
2062 # initializes generic chip with 4kB of flash and 1kB of RAM
2063 setup_my_chip MY_GENERIC_CHIP 4096 1024
2066 ### specific_file.cfg ###
2068 source [find target/generic_file.cfg]
2070 proc init_targets @{@} @{
2071 # initializes specific chip with 128kB of flash and 64kB of RAM
2072 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
2076 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
2077 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
2079 For an example of this scheme see LPC2000 target config files.
2081 The @code{init_boards} procedure is a similar concept concerning board config files
2082 (@xref{theinitboardprocedure,,The init_board procedure}.)
2084 @subsection ARM Core Specific Hacks
2086 If the chip has a DCC, enable it. If the chip is an ARM9 with some
2087 special high speed download features - enable it.
2089 If present, the MMU, the MPU and the CACHE should be disabled.
2091 Some ARM cores are equipped with trace support, which permits
2092 examination of the instruction and data bus activity. Trace
2093 activity is controlled through an ``Embedded Trace Module'' (ETM)
2094 on one of the core's scan chains. The ETM emits voluminous data
2095 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
2096 If you are using an external trace port,
2097 configure it in your board config file.
2098 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2099 configure it in your target config file.
2102 etm config $_TARGETNAME 16 normal full etb
2103 etb config $_TARGETNAME $_CHIPNAME.etb
2106 @subsection Internal Flash Configuration
2108 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2110 @b{Never ever} in the ``target configuration file'' define any type of
2111 flash that is external to the chip. (For example a BOOT flash on
2112 Chip Select 0.) Such flash information goes in a board file - not
2113 the TARGET (chip) file.
2117 @item at91sam7x256 - has 256K flash YES enable it.
2118 @item str912 - has flash internal YES enable it.
2119 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2120 @item pxa270 - again - CS0 flash - it goes in the board file.
2123 @anchor{translatingconfigurationfiles}
2124 @section Translating Configuration Files
2126 If you have a configuration file for another hardware debugger
2127 or toolset (Abatron, BDI2000, BDI3000, CCS,
2128 Lauterbach, Segger, Macraigor, etc.), translating
2129 it into OpenOCD syntax is often quite straightforward. The most tricky
2130 part of creating a configuration script is oftentimes the reset init
2131 sequence where e.g. PLLs, DRAM and the like is set up.
2133 One trick that you can use when translating is to write small
2134 Tcl procedures to translate the syntax into OpenOCD syntax. This
2135 can avoid manual translation errors and make it easier to
2136 convert other scripts later on.
2138 Example of transforming quirky arguments to a simple search and
2142 # Lauterbach syntax(?)
2144 # Data.Set c15:0x042f %long 0x40000015
2146 # OpenOCD syntax when using procedure below.
2148 # setc15 0x01 0x00050078
2150 proc setc15 @{regs value@} @{
2153 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2155 arm mcr 15 [expr ($regs>>12)&0x7] \
2156 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2157 [expr ($regs>>8)&0x7] $value
2163 @node Daemon Configuration
2164 @chapter Daemon Configuration
2165 @cindex initialization
2166 The commands here are commonly found in the openocd.cfg file and are
2167 used to specify what TCP/IP ports are used, and how GDB should be
2170 @anchor{configurationstage}
2171 @section Configuration Stage
2172 @cindex configuration stage
2173 @cindex config command
2175 When the OpenOCD server process starts up, it enters a
2176 @emph{configuration stage} which is the only time that
2177 certain commands, @emph{configuration commands}, may be issued.
2178 Normally, configuration commands are only available
2179 inside startup scripts.
2181 In this manual, the definition of a configuration command is
2182 presented as a @emph{Config Command}, not as a @emph{Command}
2183 which may be issued interactively.
2184 The runtime @command{help} command also highlights configuration
2185 commands, and those which may be issued at any time.
2187 Those configuration commands include declaration of TAPs,
2189 the interface used for JTAG communication,
2190 and other basic setup.
2191 The server must leave the configuration stage before it
2192 may access or activate TAPs.
2193 After it leaves this stage, configuration commands may no
2196 @anchor{enteringtherunstage}
2197 @section Entering the Run Stage
2199 The first thing OpenOCD does after leaving the configuration
2200 stage is to verify that it can talk to the scan chain
2201 (list of TAPs) which has been configured.
2202 It will warn if it doesn't find TAPs it expects to find,
2203 or finds TAPs that aren't supposed to be there.
2204 You should see no errors at this point.
2205 If you see errors, resolve them by correcting the
2206 commands you used to configure the server.
2207 Common errors include using an initial JTAG speed that's too
2208 fast, and not providing the right IDCODE values for the TAPs
2211 Once OpenOCD has entered the run stage, a number of commands
2213 A number of these relate to the debug targets you may have declared.
2214 For example, the @command{mww} command will not be available until
2215 a target has been successfuly instantiated.
2216 If you want to use those commands, you may need to force
2217 entry to the run stage.
2219 @deffn {Config Command} init
2220 This command terminates the configuration stage and
2221 enters the run stage. This helps when you need to have
2222 the startup scripts manage tasks such as resetting the target,
2223 programming flash, etc. To reset the CPU upon startup, add "init" and
2224 "reset" at the end of the config script or at the end of the OpenOCD
2225 command line using the @option{-c} command line switch.
2227 If this command does not appear in any startup/configuration file
2228 OpenOCD executes the command for you after processing all
2229 configuration files and/or command line options.
2231 @b{NOTE:} This command normally occurs at or near the end of your
2232 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2233 targets ready. For example: If your openocd.cfg file needs to
2234 read/write memory on your target, @command{init} must occur before
2235 the memory read/write commands. This includes @command{nand probe}.
2238 @deffn {Overridable Procedure} jtag_init
2239 This is invoked at server startup to verify that it can talk
2240 to the scan chain (list of TAPs) which has been configured.
2242 The default implementation first tries @command{jtag arp_init},
2243 which uses only a lightweight JTAG reset before examining the
2245 If that fails, it tries again, using a harder reset
2246 from the overridable procedure @command{init_reset}.
2248 Implementations must have verified the JTAG scan chain before
2250 This is done by calling @command{jtag arp_init}
2251 (or @command{jtag arp_init-reset}).
2255 @section TCP/IP Ports
2260 The OpenOCD server accepts remote commands in several syntaxes.
2261 Each syntax uses a different TCP/IP port, which you may specify
2262 only during configuration (before those ports are opened).
2264 For reasons including security, you may wish to prevent remote
2265 access using one or more of these ports.
2266 In such cases, just specify the relevant port number as zero.
2267 If you disable all access through TCP/IP, you will need to
2268 use the command line @option{-pipe} option.
2270 @deffn {Command} gdb_port [number]
2272 Normally gdb listens to a TCP/IP port, but GDB can also
2273 communicate via pipes(stdin/out or named pipes). The name
2274 "gdb_port" stuck because it covers probably more than 90% of
2275 the normal use cases.
2277 No arguments reports GDB port. "pipe" means listen to stdin
2278 output to stdout, an integer is base port number, "disable"
2279 disables the gdb server.
2281 When using "pipe", also use log_output to redirect the log
2282 output to a file so as not to flood the stdin/out pipes.
2284 The -p/--pipe option is deprecated and a warning is printed
2285 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2287 Any other string is interpreted as named pipe to listen to.
2288 Output pipe is the same name as input pipe, but with 'o' appended,
2289 e.g. /var/gdb, /var/gdbo.
2291 The GDB port for the first target will be the base port, the
2292 second target will listen on gdb_port + 1, and so on.
2293 When not specified during the configuration stage,
2294 the port @var{number} defaults to 3333.
2297 @deffn {Command} tcl_port [number]
2298 Specify or query the port used for a simplified RPC
2299 connection that can be used by clients to issue TCL commands and get the
2300 output from the Tcl engine.
2301 Intended as a machine interface.
2302 When not specified during the configuration stage,
2303 the port @var{number} defaults to 6666.
2307 @deffn {Command} telnet_port [number]
2308 Specify or query the
2309 port on which to listen for incoming telnet connections.
2310 This port is intended for interaction with one human through TCL commands.
2311 When not specified during the configuration stage,
2312 the port @var{number} defaults to 4444.
2313 When specified as zero, this port is not activated.
2316 @anchor{gdbconfiguration}
2317 @section GDB Configuration
2319 @cindex GDB configuration
2320 You can reconfigure some GDB behaviors if needed.
2321 The ones listed here are static and global.
2322 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2323 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2325 @anchor{gdbbreakpointoverride}
2326 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2327 Force breakpoint type for gdb @command{break} commands.
2328 This option supports GDB GUIs which don't
2329 distinguish hard versus soft breakpoints, if the default OpenOCD and
2330 GDB behaviour is not sufficient. GDB normally uses hardware
2331 breakpoints if the memory map has been set up for flash regions.
2334 @anchor{gdbflashprogram}
2335 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2336 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2337 vFlash packet is received.
2338 The default behaviour is @option{enable}.
2341 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2342 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2343 requested. GDB will then know when to set hardware breakpoints, and program flash
2344 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2345 for flash programming to work.
2346 Default behaviour is @option{enable}.
2347 @xref{gdbflashprogram,,gdb_flash_program}.
2350 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2351 Specifies whether data aborts cause an error to be reported
2352 by GDB memory read packets.
2353 The default behaviour is @option{disable};
2354 use @option{enable} see these errors reported.
2357 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2358 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2359 The default behaviour is @option{disable}.
2362 @deffn {Command} gdb_save_tdesc
2363 Saves the target descripton file to the local file system.
2365 The file name is @i{target_name}.xml.
2368 @anchor{eventpolling}
2369 @section Event Polling
2371 Hardware debuggers are parts of asynchronous systems,
2372 where significant events can happen at any time.
2373 The OpenOCD server needs to detect some of these events,
2374 so it can report them to through TCL command line
2377 Examples of such events include:
2380 @item One of the targets can stop running ... maybe it triggers
2381 a code breakpoint or data watchpoint, or halts itself.
2382 @item Messages may be sent over ``debug message'' channels ... many
2383 targets support such messages sent over JTAG,
2384 for receipt by the person debugging or tools.
2385 @item Loss of power ... some adapters can detect these events.
2386 @item Resets not issued through JTAG ... such reset sources
2387 can include button presses or other system hardware, sometimes
2388 including the target itself (perhaps through a watchdog).
2389 @item Debug instrumentation sometimes supports event triggering
2390 such as ``trace buffer full'' (so it can quickly be emptied)
2391 or other signals (to correlate with code behavior).
2394 None of those events are signaled through standard JTAG signals.
2395 However, most conventions for JTAG connectors include voltage
2396 level and system reset (SRST) signal detection.
2397 Some connectors also include instrumentation signals, which
2398 can imply events when those signals are inputs.
2400 In general, OpenOCD needs to periodically check for those events,
2401 either by looking at the status of signals on the JTAG connector
2402 or by sending synchronous ``tell me your status'' JTAG requests
2403 to the various active targets.
2404 There is a command to manage and monitor that polling,
2405 which is normally done in the background.
2407 @deffn Command poll [@option{on}|@option{off}]
2408 Poll the current target for its current state.
2409 (Also, @pxref{targetcurstate,,target curstate}.)
2410 If that target is in debug mode, architecture
2411 specific information about the current state is printed.
2412 An optional parameter
2413 allows background polling to be enabled and disabled.
2415 You could use this from the TCL command shell, or
2416 from GDB using @command{monitor poll} command.
2417 Leave background polling enabled while you're using GDB.
2420 background polling: on
2421 target state: halted
2422 target halted in ARM state due to debug-request, \
2423 current mode: Supervisor
2424 cpsr: 0x800000d3 pc: 0x11081bfc
2425 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2430 @node Debug Adapter Configuration
2431 @chapter Debug Adapter Configuration
2432 @cindex config file, interface
2433 @cindex interface config file
2435 Correctly installing OpenOCD includes making your operating system give
2436 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2437 are used to select which one is used, and to configure how it is used.
2440 Because OpenOCD started out with a focus purely on JTAG, you may find
2441 places where it wrongly presumes JTAG is the only transport protocol
2442 in use. Be aware that recent versions of OpenOCD are removing that
2443 limitation. JTAG remains more functional than most other transports.
2444 Other transports do not support boundary scan operations, or may be
2445 specific to a given chip vendor. Some might be usable only for
2446 programming flash memory, instead of also for debugging.
2449 Debug Adapters/Interfaces/Dongles are normally configured
2450 through commands in an interface configuration
2451 file which is sourced by your @file{openocd.cfg} file, or
2452 through a command line @option{-f interface/....cfg} option.
2455 source [find interface/olimex-jtag-tiny.cfg]
2459 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2460 A few cases are so simple that you only need to say what driver to use:
2467 Most adapters need a bit more configuration than that.
2470 @section Interface Configuration
2472 The interface command tells OpenOCD what type of debug adapter you are
2473 using. Depending on the type of adapter, you may need to use one or
2474 more additional commands to further identify or configure the adapter.
2476 @deffn {Config Command} {interface} name
2477 Use the interface driver @var{name} to connect to the
2481 @deffn Command {interface_list}
2482 List the debug adapter drivers that have been built into
2483 the running copy of OpenOCD.
2485 @deffn Command {interface transports} transport_name+
2486 Specifies the transports supported by this debug adapter.
2487 The adapter driver builds-in similar knowledge; use this only
2488 when external configuration (such as jumpering) changes what
2489 the hardware can support.
2494 @deffn Command {adapter_name}
2495 Returns the name of the debug adapter driver being used.
2498 @section Interface Drivers
2500 Each of the interface drivers listed here must be explicitly
2501 enabled when OpenOCD is configured, in order to be made
2502 available at run time.
2504 @deffn {Interface Driver} {amt_jtagaccel}
2505 Amontec Chameleon in its JTAG Accelerator configuration,
2506 connected to a PC's EPP mode parallel port.
2507 This defines some driver-specific commands:
2509 @deffn {Config Command} {parport_port} number
2510 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2511 the number of the @file{/dev/parport} device.
2514 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2515 Displays status of RTCK option.
2516 Optionally sets that option first.
2520 @deffn {Interface Driver} {arm-jtag-ew}
2521 Olimex ARM-JTAG-EW USB adapter
2522 This has one driver-specific command:
2524 @deffn Command {armjtagew_info}
2529 @deffn {Interface Driver} {at91rm9200}
2530 Supports bitbanged JTAG from the local system,
2531 presuming that system is an Atmel AT91rm9200
2532 and a specific set of GPIOs is used.
2533 @c command: at91rm9200_device NAME
2534 @c chooses among list of bit configs ... only one option
2537 @deffn {Interface Driver} {dummy}
2538 A dummy software-only driver for debugging.
2541 @deffn {Interface Driver} {ep93xx}
2542 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2545 @deffn {Interface Driver} {ft2232}
2546 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2548 Note that this driver has several flaws and the @command{ftdi} driver is
2549 recommended as its replacement.
2551 These interfaces have several commands, used to configure the driver
2552 before initializing the JTAG scan chain:
2554 @deffn {Config Command} {ft2232_device_desc} description
2555 Provides the USB device description (the @emph{iProduct string})
2556 of the FTDI FT2232 device. If not
2557 specified, the FTDI default value is used. This setting is only valid
2558 if compiled with FTD2XX support.
2561 @deffn {Config Command} {ft2232_serial} serial-number
2562 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2563 in case the vendor provides unique IDs and more than one FT2232 device
2564 is connected to the host.
2565 If not specified, serial numbers are not considered.
2566 (Note that USB serial numbers can be arbitrary Unicode strings,
2567 and are not restricted to containing only decimal digits.)
2570 @deffn {Config Command} {ft2232_layout} name
2571 Each vendor's FT2232 device can use different GPIO signals
2572 to control output-enables, reset signals, and LEDs.
2573 Currently valid layout @var{name} values include:
2575 @item @b{axm0432_jtag} Axiom AXM-0432
2576 @item @b{comstick} Hitex STR9 comstick
2577 @item @b{cortino} Hitex Cortino JTAG interface
2578 @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
2579 either for the local Cortex-M3 (SRST only)
2580 or in a passthrough mode (neither SRST nor TRST)
2581 This layout can not support the SWO trace mechanism, and should be
2582 used only for older boards (before rev C).
2583 @item @b{luminary_icdi} This layout should be used with most TI/Luminary
2584 eval boards, including Rev C LM3S811 eval boards and the eponymous
2585 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2586 to debug some other target. It can support the SWO trace mechanism.
2587 @item @b{flyswatter} Tin Can Tools Flyswatter
2588 @item @b{icebear} ICEbear JTAG adapter from Section 5
2589 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2590 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2591 @item @b{m5960} American Microsystems M5960
2592 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2593 @item @b{oocdlink} OOCDLink
2594 @c oocdlink ~= jtagkey_prototype_v1
2595 @item @b{redbee-econotag} Integrated with a Redbee development board.
2596 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2597 @item @b{sheevaplug} Marvell Sheevaplug development kit
2598 @item @b{signalyzer} Xverve Signalyzer
2599 @item @b{stm32stick} Hitex STM32 Performance Stick
2600 @item @b{turtelizer2} egnite Software turtelizer2
2601 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2605 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2606 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2607 default values are used.
2608 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2610 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2614 @deffn {Config Command} {ft2232_latency} ms
2615 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2616 ft2232_read() fails to return the expected number of bytes. This can be caused by
2617 USB communication delays and has proved hard to reproduce and debug. Setting the
2618 FT2232 latency timer to a larger value increases delays for short USB packets but it
2619 also reduces the risk of timeouts before receiving the expected number of bytes.
2620 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2623 @deffn {Config Command} {ft2232_channel} channel
2624 Used to select the channel of the ft2232 chip to use (between 1 and 4).
2625 The default value is 1.
2628 For example, the interface config file for a
2629 Turtelizer JTAG Adapter looks something like this:
2633 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2634 ft2232_layout turtelizer2
2635 ft2232_vid_pid 0x0403 0xbdc8
2639 @deffn {Interface Driver} {ftdi}
2640 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2641 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2642 It is a complete rewrite to address a large number of problems with the ft2232
2645 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2646 bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
2647 consistently faster than the ft2232 driver, sometimes several times faster.
2649 A major improvement of this driver is that support for new FTDI based adapters
2650 can be added competely through configuration files, without the need to patch
2651 and rebuild OpenOCD.
2653 The driver uses a signal abstraction to enable Tcl configuration files to
2654 define outputs for one or several FTDI GPIO. These outputs can then be
2655 controlled using the @command{ftdi_set_signal} command. Special signal names
2656 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2657 will be used for their customary purpose.
2659 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2660 be controlled differently. In order to support tristateable signals such as
2661 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2662 signal. The following output buffer configurations are supported:
2665 @item Push-pull with one FTDI output as (non-)inverted data line
2666 @item Open drain with one FTDI output as (non-)inverted output-enable
2667 @item Tristate with one FTDI output as (non-)inverted data line and another
2668 FTDI output as (non-)inverted output-enable
2669 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2670 switching data and direction as necessary
2673 These interfaces have several commands, used to configure the driver
2674 before initializing the JTAG scan chain:
2676 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2677 The vendor ID and product ID of the adapter. If not specified, the FTDI
2678 default values are used.
2679 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2681 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2685 @deffn {Config Command} {ftdi_device_desc} description
2686 Provides the USB device description (the @emph{iProduct string})
2687 of the adapter. If not specified, the device description is ignored
2688 during device selection.
2691 @deffn {Config Command} {ftdi_serial} serial-number
2692 Specifies the @var{serial-number} of the adapter to use,
2693 in case the vendor provides unique IDs and more than one adapter
2694 is connected to the host.
2695 If not specified, serial numbers are not considered.
2696 (Note that USB serial numbers can be arbitrary Unicode strings,
2697 and are not restricted to containing only decimal digits.)
2700 @deffn {Config Command} {ftdi_channel} channel
2701 Selects the channel of the FTDI device to use for MPSSE operations. Most
2702 adapters use the default, channel 0, but there are exceptions.
2705 @deffn {Config Command} {ftdi_layout_init} data direction
2706 Specifies the initial values of the FTDI GPIO data and direction registers.
2707 Each value is a 16-bit number corresponding to the concatenation of the high
2708 and low FTDI GPIO registers. The values should be selected based on the
2709 schematics of the adapter, such that all signals are set to safe levels with
2710 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2711 and initially asserted reset signals.
2714 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask]
2715 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2716 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2717 register bitmasks to tell the driver the connection and type of the output
2718 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2719 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2720 used with inverting data inputs and @option{-data} with non-inverting inputs.
2721 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2722 not-output-enable) input to the output buffer is connected.
2724 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2725 simple open-collector transistor driver would be specified with @option{-oe}
2726 only. In that case the signal can only be set to drive low or to Hi-Z and the
2727 driver will complain if the signal is set to drive high. Which means that if
2728 it's a reset signal, @command{reset_config} must be specified as
2729 @option{srst_open_drain}, not @option{srst_push_pull}.
2731 A special case is provided when @option{-data} and @option{-oe} is set to the
2732 same bitmask. Then the FTDI pin is considered being connected straight to the
2733 target without any buffer. The FTDI pin is then switched between output and
2734 input as necessary to provide the full set of low, high and Hi-Z
2735 characteristics. In all other cases, the pins specified in a signal definition
2736 are always driven by the FTDI.
2739 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2740 Set a previously defined signal to the specified level.
2742 @item @option{0}, drive low
2743 @item @option{1}, drive high
2744 @item @option{z}, set to high-impedance
2748 For example adapter definitions, see the configuration files shipped in the
2749 @file{interface/ftdi} directory.
2752 @deffn {Interface Driver} {remote_bitbang}
2753 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2754 with a remote process and sends ASCII encoded bitbang requests to that process
2755 instead of directly driving JTAG.
2757 The remote_bitbang driver is useful for debugging software running on
2758 processors which are being simulated.
2760 @deffn {Config Command} {remote_bitbang_port} number
2761 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2762 sockets instead of TCP.
2765 @deffn {Config Command} {remote_bitbang_host} hostname
2766 Specifies the hostname of the remote process to connect to using TCP, or the
2767 name of the UNIX socket to use if remote_bitbang_port is 0.
2770 For example, to connect remotely via TCP to the host foobar you might have
2774 interface remote_bitbang
2775 remote_bitbang_port 3335
2776 remote_bitbang_host foobar
2779 To connect to another process running locally via UNIX sockets with socket
2783 interface remote_bitbang
2784 remote_bitbang_port 0
2785 remote_bitbang_host mysocket
2789 @deffn {Interface Driver} {usb_blaster}
2790 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2791 for FTDI chips. These interfaces have several commands, used to
2792 configure the driver before initializing the JTAG scan chain:
2794 @deffn {Config Command} {usb_blaster_device_desc} description
2795 Provides the USB device description (the @emph{iProduct string})
2796 of the FTDI FT245 device. If not
2797 specified, the FTDI default value is used. This setting is only valid
2798 if compiled with FTD2XX support.
2801 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2802 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2803 default values are used.
2804 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2805 Altera USB-Blaster (default):
2807 usb_blaster_vid_pid 0x09FB 0x6001
2809 The following VID/PID is for Kolja Waschk's USB JTAG:
2811 usb_blaster_vid_pid 0x16C0 0x06AD
2815 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2816 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2817 female JTAG header). These pins can be used as SRST and/or TRST provided the
2818 appropriate connections are made on the target board.
2820 For example, to use pin 6 as SRST (as with an AVR board):
2822 $_TARGETNAME configure -event reset-assert \
2823 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2829 @deffn {Interface Driver} {gw16012}
2830 Gateworks GW16012 JTAG programmer.
2831 This has one driver-specific command:
2833 @deffn {Config Command} {parport_port} [port_number]
2834 Display either the address of the I/O port
2835 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2836 If a parameter is provided, first switch to use that port.
2837 This is a write-once setting.
2841 @deffn {Interface Driver} {jlink}
2842 Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
2844 @quotation Compatibility Note
2845 Segger released many firmware versions for the many harware versions they
2846 produced. OpenOCD was extensively tested and intended to run on all of them,
2847 but some combinations were reported as incompatible. As a general
2848 recommendation, it is advisable to use the latest firmware version
2849 available for each hardware version. However the current V8 is a moving
2850 target, and Segger firmware versions released after the OpenOCD was
2851 released may not be compatible. In such cases it is recommended to
2852 revert to the last known functional version. For 0.5.0, this is from
2853 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2854 version is from "May 3 2012 18:36:22", packed with 4.46f.
2857 @deffn {Command} {jlink caps}
2858 Display the device firmware capabilities.
2860 @deffn {Command} {jlink info}
2861 Display various device information, like hardware version, firmware version, current bus status.
2863 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2864 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2866 @deffn {Command} {jlink config}
2867 Display the J-Link configuration.
2869 @deffn {Command} {jlink config kickstart} [val]
2870 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2872 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2873 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2875 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2876 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2877 E the bit of the subnet mask and
2878 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2880 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2881 Set the USB address; this will also change the product id. Without argument, show the USB address.
2883 @deffn {Command} {jlink config reset}
2884 Reset the current configuration.
2886 @deffn {Command} {jlink config save}
2887 Save the current configuration to the internal persistent storage.
2889 @deffn {Config} {jlink pid} val
2890 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2894 @deffn {Interface Driver} {parport}
2895 Supports PC parallel port bit-banging cables:
2896 Wigglers, PLD download cable, and more.
2897 These interfaces have several commands, used to configure the driver
2898 before initializing the JTAG scan chain:
2900 @deffn {Config Command} {parport_cable} name
2901 Set the layout of the parallel port cable used to connect to the target.
2902 This is a write-once setting.
2903 Currently valid cable @var{name} values include:
2906 @item @b{altium} Altium Universal JTAG cable.
2907 @item @b{arm-jtag} Same as original wiggler except SRST and
2908 TRST connections reversed and TRST is also inverted.
2909 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2910 in configuration mode. This is only used to
2911 program the Chameleon itself, not a connected target.
2912 @item @b{dlc5} The Xilinx Parallel cable III.
2913 @item @b{flashlink} The ST Parallel cable.
2914 @item @b{lattice} Lattice ispDOWNLOAD Cable
2915 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2917 Amontec's Chameleon Programmer. The new version available from
2918 the website uses the original Wiggler layout ('@var{wiggler}')
2919 @item @b{triton} The parallel port adapter found on the
2920 ``Karo Triton 1 Development Board''.
2921 This is also the layout used by the HollyGates design
2922 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2923 @item @b{wiggler} The original Wiggler layout, also supported by
2924 several clones, such as the Olimex ARM-JTAG
2925 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2926 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2930 @deffn {Config Command} {parport_port} [port_number]
2931 Display either the address of the I/O port
2932 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2933 If a parameter is provided, first switch to use that port.
2934 This is a write-once setting.
2936 When using PPDEV to access the parallel port, use the number of the parallel port:
2937 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2938 you may encounter a problem.
2941 @deffn Command {parport_toggling_time} [nanoseconds]
2942 Displays how many nanoseconds the hardware needs to toggle TCK;
2943 the parport driver uses this value to obey the
2944 @command{adapter_khz} configuration.
2945 When the optional @var{nanoseconds} parameter is given,
2946 that setting is changed before displaying the current value.
2948 The default setting should work reasonably well on commodity PC hardware.
2949 However, you may want to calibrate for your specific hardware.
2951 To measure the toggling time with a logic analyzer or a digital storage
2952 oscilloscope, follow the procedure below:
2954 > parport_toggling_time 1000
2957 This sets the maximum JTAG clock speed of the hardware, but
2958 the actual speed probably deviates from the requested 500 kHz.
2959 Now, measure the time between the two closest spaced TCK transitions.
2960 You can use @command{runtest 1000} or something similar to generate a
2961 large set of samples.
2962 Update the setting to match your measurement:
2964 > parport_toggling_time <measured nanoseconds>
2966 Now the clock speed will be a better match for @command{adapter_khz rate}
2967 commands given in OpenOCD scripts and event handlers.
2969 You can do something similar with many digital multimeters, but note
2970 that you'll probably need to run the clock continuously for several
2971 seconds before it decides what clock rate to show. Adjust the
2972 toggling time up or down until the measured clock rate is a good
2973 match for the adapter_khz rate you specified; be conservative.
2977 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2978 This will configure the parallel driver to write a known
2979 cable-specific value to the parallel interface on exiting OpenOCD.
2982 For example, the interface configuration file for a
2983 classic ``Wiggler'' cable on LPT2 might look something like this:
2988 parport_cable wiggler
2992 @deffn {Interface Driver} {presto}
2993 ASIX PRESTO USB JTAG programmer.
2994 @deffn {Config Command} {presto_serial} serial_string
2995 Configures the USB serial number of the Presto device to use.
2999 @deffn {Interface Driver} {rlink}
3000 Raisonance RLink USB adapter
3003 @deffn {Interface Driver} {usbprog}
3004 usbprog is a freely programmable USB adapter.
3007 @deffn {Interface Driver} {vsllink}
3008 vsllink is part of Versaloon which is a versatile USB programmer.
3011 This defines quite a few driver-specific commands,
3012 which are not currently documented here.
3016 @deffn {Interface Driver} {hla}
3017 This is a driver that supports multiple High Level Adapters.
3018 This type of adapter does not expose some of the lower level api's
3019 that OpenOCD would normally use to access the target.
3021 Currently supported adapters include the ST STLINK and TI ICDI.
3023 @deffn {Config Command} {hla_device_desc} description
3024 Currently Not Supported.
3027 @deffn {Config Command} {hla_serial} serial
3028 Currently Not Supported.
3031 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
3032 Specifies the adapter layout to use.
3035 @deffn {Config Command} {hla_vid_pid} vid pid
3036 The vendor ID and product ID of the device.
3039 @deffn {Config Command} {stlink_api} api_level
3040 Manually sets the stlink api used, valid options are 1 or 2. (@b{STLINK Only}).
3043 @deffn {Config Command} {trace} output_file_path source_clock_hz
3044 Enable SWO tracing (if supported), trace data is appended to the specified
3045 output file and the file is created if it does not exist. The source clock
3046 rate for the trace port must be specified, this is typically the CPU clock
3051 @deffn {Interface Driver} {opendous}
3052 opendous-jtag is a freely programmable USB adapter.
3055 @deffn {Interface Driver} {ulink}
3056 This is the Keil ULINK v1 JTAG debugger.
3059 @deffn {Interface Driver} {ZY1000}
3060 This is the Zylin ZY1000 JTAG debugger.
3064 This defines some driver-specific commands,
3065 which are not currently documented here.
3068 @deffn Command power [@option{on}|@option{off}]
3069 Turn power switch to target on/off.
3070 No arguments: print status.
3073 @deffn {Interface Driver} {bcm2835gpio}
3074 This SoC is present in Raspberry Pi which is a cheap single-board computer
3075 exposing some GPIOs on its expansion header.
3077 The driver accesses memory-mapped GPIO peripheral registers directly
3078 for maximum performance, but the only possible race condition is for
3079 the pins' modes/muxing (which is highly unlikely), so it should be
3080 able to coexist nicely with both sysfs bitbanging and various
3081 peripherals' kernel drivers. The driver restores the previous
3082 configuration on exit.
3084 See @file{interface/raspberrypi-native.cfg} for a sample config and
3089 @section Transport Configuration
3091 As noted earlier, depending on the version of OpenOCD you use,
3092 and the debug adapter you are using,
3093 several transports may be available to
3094 communicate with debug targets (or perhaps to program flash memory).
3095 @deffn Command {transport list}
3096 displays the names of the transports supported by this
3100 @deffn Command {transport select} transport_name
3101 Select which of the supported transports to use in this OpenOCD session.
3102 The transport must be supported by the debug adapter hardware and by the
3103 version of OpenOCD you are using (including the adapter's driver).
3104 No arguments: returns name of session's selected transport.
3107 @subsection JTAG Transport
3109 JTAG is the original transport supported by OpenOCD, and most
3110 of the OpenOCD commands support it.
3111 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3112 each of which must be explicitly declared.
3113 JTAG supports both debugging and boundary scan testing.
3114 Flash programming support is built on top of debug support.
3115 @subsection SWD Transport
3117 @cindex Serial Wire Debug
3118 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3119 Debug Access Point (DAP, which must be explicitly declared.
3120 (SWD uses fewer signal wires than JTAG.)
3121 SWD is debug-oriented, and does not support boundary scan testing.
3122 Flash programming support is built on top of debug support.
3123 (Some processors support both JTAG and SWD.)
3124 @deffn Command {swd newdap} ...
3125 Declares a single DAP which uses SWD transport.
3126 Parameters are currently the same as "jtag newtap" but this is
3129 @deffn Command {swd wcr trn prescale}
3130 Updates TRN (turnaraound delay) and prescaling.fields of the
3131 Wire Control Register (WCR).
3132 No parameters: displays current settings.
3135 @subsection SPI Transport
3137 @cindex Serial Peripheral Interface
3138 The Serial Peripheral Interface (SPI) is a general purpose transport
3139 which uses four wire signaling. Some processors use it as part of a
3140 solution for flash programming.
3144 JTAG clock setup is part of system setup.
3145 It @emph{does not belong with interface setup} since any interface
3146 only knows a few of the constraints for the JTAG clock speed.
3147 Sometimes the JTAG speed is
3148 changed during the target initialization process: (1) slow at
3149 reset, (2) program the CPU clocks, (3) run fast.
3150 Both the "slow" and "fast" clock rates are functions of the
3151 oscillators used, the chip, the board design, and sometimes
3152 power management software that may be active.
3154 The speed used during reset, and the scan chain verification which
3155 follows reset, can be adjusted using a @code{reset-start}
3156 target event handler.
3157 It can then be reconfigured to a faster speed by a
3158 @code{reset-init} target event handler after it reprograms those
3159 CPU clocks, or manually (if something else, such as a boot loader,
3160 sets up those clocks).
3161 @xref{targetevents,,Target Events}.
3162 When the initial low JTAG speed is a chip characteristic, perhaps
3163 because of a required oscillator speed, provide such a handler
3164 in the target config file.
3165 When that speed is a function of a board-specific characteristic
3166 such as which speed oscillator is used, it belongs in the board
3167 config file instead.
3168 In both cases it's safest to also set the initial JTAG clock rate
3169 to that same slow speed, so that OpenOCD never starts up using a
3170 clock speed that's faster than the scan chain can support.
3174 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3177 If your system supports adaptive clocking (RTCK), configuring
3178 JTAG to use that is probably the most robust approach.
3179 However, it introduces delays to synchronize clocks; so it
3180 may not be the fastest solution.
3182 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3183 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3184 which support adaptive clocking.
3186 @deffn {Command} adapter_khz max_speed_kHz
3187 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3188 JTAG interfaces usually support a limited number of
3189 speeds. The speed actually used won't be faster
3190 than the speed specified.
3192 Chip data sheets generally include a top JTAG clock rate.
3193 The actual rate is often a function of a CPU core clock,
3194 and is normally less than that peak rate.
3195 For example, most ARM cores accept at most one sixth of the CPU clock.
3197 Speed 0 (khz) selects RTCK method.
3198 @xref{faqrtck,,FAQ RTCK}.
3199 If your system uses RTCK, you won't need to change the
3200 JTAG clocking after setup.
3201 Not all interfaces, boards, or targets support ``rtck''.
3202 If the interface device can not
3203 support it, an error is returned when you try to use RTCK.
3206 @defun jtag_rclk fallback_speed_kHz
3207 @cindex adaptive clocking
3209 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3210 If that fails (maybe the interface, board, or target doesn't
3211 support it), falls back to the specified frequency.
3213 # Fall back to 3mhz if RTCK is not supported
3218 @node Reset Configuration
3219 @chapter Reset Configuration
3220 @cindex Reset Configuration
3222 Every system configuration may require a different reset
3223 configuration. This can also be quite confusing.
3224 Resets also interact with @var{reset-init} event handlers,
3225 which do things like setting up clocks and DRAM, and
3226 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3227 They can also interact with JTAG routers.
3228 Please see the various board files for examples.
3231 To maintainers and integrators:
3232 Reset configuration touches several things at once.
3233 Normally the board configuration file
3234 should define it and assume that the JTAG adapter supports
3235 everything that's wired up to the board's JTAG connector.
3237 However, the target configuration file could also make note
3238 of something the silicon vendor has done inside the chip,
3239 which will be true for most (or all) boards using that chip.
3240 And when the JTAG adapter doesn't support everything, the
3241 user configuration file will need to override parts of
3242 the reset configuration provided by other files.
3245 @section Types of Reset
3247 There are many kinds of reset possible through JTAG, but
3248 they may not all work with a given board and adapter.
3249 That's part of why reset configuration can be error prone.
3253 @emph{System Reset} ... the @emph{SRST} hardware signal
3254 resets all chips connected to the JTAG adapter, such as processors,
3255 power management chips, and I/O controllers. Normally resets triggered
3256 with this signal behave exactly like pressing a RESET button.
3258 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3259 just the TAP controllers connected to the JTAG adapter.
3260 Such resets should not be visible to the rest of the system; resetting a
3261 device's TAP controller just puts that controller into a known state.
3263 @emph{Emulation Reset} ... many devices can be reset through JTAG
3264 commands. These resets are often distinguishable from system
3265 resets, either explicitly (a "reset reason" register says so)
3266 or implicitly (not all parts of the chip get reset).
3268 @emph{Other Resets} ... system-on-chip devices often support
3269 several other types of reset.
3270 You may need to arrange that a watchdog timer stops
3271 while debugging, preventing a watchdog reset.
3272 There may be individual module resets.
3275 In the best case, OpenOCD can hold SRST, then reset
3276 the TAPs via TRST and send commands through JTAG to halt the
3277 CPU at the reset vector before the 1st instruction is executed.
3278 Then when it finally releases the SRST signal, the system is
3279 halted under debugger control before any code has executed.
3280 This is the behavior required to support the @command{reset halt}
3281 and @command{reset init} commands; after @command{reset init} a
3282 board-specific script might do things like setting up DRAM.
3283 (@xref{resetcommand,,Reset Command}.)
3285 @anchor{srstandtrstissues}
3286 @section SRST and TRST Issues
3288 Because SRST and TRST are hardware signals, they can have a
3289 variety of system-specific constraints. Some of the most
3294 @item @emph{Signal not available} ... Some boards don't wire
3295 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3296 support such signals even if they are wired up.
3297 Use the @command{reset_config} @var{signals} options to say
3298 when either of those signals is not connected.
3299 When SRST is not available, your code might not be able to rely
3300 on controllers having been fully reset during code startup.
3301 Missing TRST is not a problem, since JTAG-level resets can
3302 be triggered using with TMS signaling.
3304 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3305 adapter will connect SRST to TRST, instead of keeping them separate.
3306 Use the @command{reset_config} @var{combination} options to say
3307 when those signals aren't properly independent.
3309 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3310 delay circuit, reset supervisor, or on-chip features can extend
3311 the effect of a JTAG adapter's reset for some time after the adapter
3312 stops issuing the reset. For example, there may be chip or board
3313 requirements that all reset pulses last for at least a
3314 certain amount of time; and reset buttons commonly have
3315 hardware debouncing.
3316 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3317 commands to say when extra delays are needed.
3319 @item @emph{Drive type} ... Reset lines often have a pullup
3320 resistor, letting the JTAG interface treat them as open-drain
3321 signals. But that's not a requirement, so the adapter may need
3322 to use push/pull output drivers.
3323 Also, with weak pullups it may be advisable to drive
3324 signals to both levels (push/pull) to minimize rise times.
3325 Use the @command{reset_config} @var{trst_type} and
3326 @var{srst_type} parameters to say how to drive reset signals.
3328 @item @emph{Special initialization} ... Targets sometimes need
3329 special JTAG initialization sequences to handle chip-specific
3330 issues (not limited to errata).
3331 For example, certain JTAG commands might need to be issued while
3332 the system as a whole is in a reset state (SRST active)
3333 but the JTAG scan chain is usable (TRST inactive).
3334 Many systems treat combined assertion of SRST and TRST as a
3335 trigger for a harder reset than SRST alone.
3336 Such custom reset handling is discussed later in this chapter.
3339 There can also be other issues.
3340 Some devices don't fully conform to the JTAG specifications.
3341 Trivial system-specific differences are common, such as
3342 SRST and TRST using slightly different names.
3343 There are also vendors who distribute key JTAG documentation for
3344 their chips only to developers who have signed a Non-Disclosure
3347 Sometimes there are chip-specific extensions like a requirement to use
3348 the normally-optional TRST signal (precluding use of JTAG adapters which
3349 don't pass TRST through), or needing extra steps to complete a TAP reset.
3351 In short, SRST and especially TRST handling may be very finicky,
3352 needing to cope with both architecture and board specific constraints.
3354 @section Commands for Handling Resets
3356 @deffn {Command} adapter_nsrst_assert_width milliseconds
3357 Minimum amount of time (in milliseconds) OpenOCD should wait
3358 after asserting nSRST (active-low system reset) before
3359 allowing it to be deasserted.
3362 @deffn {Command} adapter_nsrst_delay milliseconds
3363 How long (in milliseconds) OpenOCD should wait after deasserting
3364 nSRST (active-low system reset) before starting new JTAG operations.
3365 When a board has a reset button connected to SRST line it will
3366 probably have hardware debouncing, implying you should use this.
3369 @deffn {Command} jtag_ntrst_assert_width milliseconds
3370 Minimum amount of time (in milliseconds) OpenOCD should wait
3371 after asserting nTRST (active-low JTAG TAP reset) before
3372 allowing it to be deasserted.
3375 @deffn {Command} jtag_ntrst_delay milliseconds
3376 How long (in milliseconds) OpenOCD should wait after deasserting
3377 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3380 @deffn {Command} reset_config mode_flag ...
3381 This command displays or modifies the reset configuration
3382 of your combination of JTAG board and target in target
3383 configuration scripts.
3385 Information earlier in this section describes the kind of problems
3386 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3387 As a rule this command belongs only in board config files,
3388 describing issues like @emph{board doesn't connect TRST};
3389 or in user config files, addressing limitations derived
3390 from a particular combination of interface and board.
3391 (An unlikely example would be using a TRST-only adapter
3392 with a board that only wires up SRST.)
3394 The @var{mode_flag} options can be specified in any order, but only one
3395 of each type -- @var{signals}, @var{combination}, @var{gates},
3396 @var{trst_type}, @var{srst_type} and @var{connect_type}
3397 -- may be specified at a time.
3398 If you don't provide a new value for a given type, its previous
3399 value (perhaps the default) is unchanged.
3400 For example, this means that you don't need to say anything at all about
3401 TRST just to declare that if the JTAG adapter should want to drive SRST,
3402 it must explicitly be driven high (@option{srst_push_pull}).
3406 @var{signals} can specify which of the reset signals are connected.
3407 For example, If the JTAG interface provides SRST, but the board doesn't
3408 connect that signal properly, then OpenOCD can't use it.
3409 Possible values are @option{none} (the default), @option{trst_only},
3410 @option{srst_only} and @option{trst_and_srst}.
3413 If your board provides SRST and/or TRST through the JTAG connector,
3414 you must declare that so those signals can be used.
3418 The @var{combination} is an optional value specifying broken reset
3419 signal implementations.
3420 The default behaviour if no option given is @option{separate},
3421 indicating everything behaves normally.
3422 @option{srst_pulls_trst} states that the
3423 test logic is reset together with the reset of the system (e.g. NXP
3424 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3425 the system is reset together with the test logic (only hypothetical, I
3426 haven't seen hardware with such a bug, and can be worked around).
3427 @option{combined} implies both @option{srst_pulls_trst} and
3428 @option{trst_pulls_srst}.
3431 The @var{gates} tokens control flags that describe some cases where
3432 JTAG may be unvailable during reset.
3433 @option{srst_gates_jtag} (default)
3434 indicates that asserting SRST gates the
3435 JTAG clock. This means that no communication can happen on JTAG
3436 while SRST is asserted.
3437 Its converse is @option{srst_nogate}, indicating that JTAG commands
3438 can safely be issued while SRST is active.
3441 The @var{connect_type} tokens control flags that describe some cases where
3442 SRST is asserted while connecting to the target. @option{srst_nogate}
3443 is required to use this option.
3444 @option{connect_deassert_srst} (default)
3445 indicates that SRST will not be asserted while connecting to the target.
3446 Its converse is @option{connect_assert_srst}, indicating that SRST will
3447 be asserted before any target connection.
3448 Only some targets support this feature, STM32 and STR9 are examples.
3449 This feature is useful if you are unable to connect to your target due
3450 to incorrect options byte config or illegal program execution.
3453 The optional @var{trst_type} and @var{srst_type} parameters allow the
3454 driver mode of each reset line to be specified. These values only affect
3455 JTAG interfaces with support for different driver modes, like the Amontec
3456 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3457 relevant signal (TRST or SRST) is not connected.
3461 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3462 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3463 Most boards connect this signal to a pulldown, so the JTAG TAPs
3464 never leave reset unless they are hooked up to a JTAG adapter.
3467 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3468 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3469 Most boards connect this signal to a pullup, and allow the
3470 signal to be pulled low by various events including system
3471 powerup and pressing a reset button.
3475 @section Custom Reset Handling
3478 OpenOCD has several ways to help support the various reset
3479 mechanisms provided by chip and board vendors.
3480 The commands shown in the previous section give standard parameters.
3481 There are also @emph{event handlers} associated with TAPs or Targets.
3482 Those handlers are Tcl procedures you can provide, which are invoked
3483 at particular points in the reset sequence.
3485 @emph{When SRST is not an option} you must set
3486 up a @code{reset-assert} event handler for your target.
3487 For example, some JTAG adapters don't include the SRST signal;
3488 and some boards have multiple targets, and you won't always
3489 want to reset everything at once.
3491 After configuring those mechanisms, you might still
3492 find your board doesn't start up or reset correctly.
3493 For example, maybe it needs a slightly different sequence
3494 of SRST and/or TRST manipulations, because of quirks that
3495 the @command{reset_config} mechanism doesn't address;
3496 or asserting both might trigger a stronger reset, which
3497 needs special attention.
3499 Experiment with lower level operations, such as @command{jtag_reset}
3500 and the @command{jtag arp_*} operations shown here,
3501 to find a sequence of operations that works.
3502 @xref{JTAG Commands}.
3503 When you find a working sequence, it can be used to override
3504 @command{jtag_init}, which fires during OpenOCD startup
3505 (@pxref{configurationstage,,Configuration Stage});
3506 or @command{init_reset}, which fires during reset processing.
3508 You might also want to provide some project-specific reset
3509 schemes. For example, on a multi-target board the standard
3510 @command{reset} command would reset all targets, but you
3511 may need the ability to reset only one target at time and
3512 thus want to avoid using the board-wide SRST signal.
3514 @deffn {Overridable Procedure} init_reset mode
3515 This is invoked near the beginning of the @command{reset} command,
3516 usually to provide as much of a cold (power-up) reset as practical.
3517 By default it is also invoked from @command{jtag_init} if
3518 the scan chain does not respond to pure JTAG operations.
3519 The @var{mode} parameter is the parameter given to the
3520 low level reset command (@option{halt},
3521 @option{init}, or @option{run}), @option{setup},
3522 or potentially some other value.
3524 The default implementation just invokes @command{jtag arp_init-reset}.
3525 Replacements will normally build on low level JTAG
3526 operations such as @command{jtag_reset}.
3527 Operations here must not address individual TAPs
3528 (or their associated targets)
3529 until the JTAG scan chain has first been verified to work.
3531 Implementations must have verified the JTAG scan chain before
3533 This is done by calling @command{jtag arp_init}
3534 (or @command{jtag arp_init-reset}).
3537 @deffn Command {jtag arp_init}
3538 This validates the scan chain using just the four
3539 standard JTAG signals (TMS, TCK, TDI, TDO).
3540 It starts by issuing a JTAG-only reset.
3541 Then it performs checks to verify that the scan chain configuration
3542 matches the TAPs it can observe.
3543 Those checks include checking IDCODE values for each active TAP,
3544 and verifying the length of their instruction registers using
3545 TAP @code{-ircapture} and @code{-irmask} values.
3546 If these tests all pass, TAP @code{setup} events are
3547 issued to all TAPs with handlers for that event.
3550 @deffn Command {jtag arp_init-reset}
3551 This uses TRST and SRST to try resetting
3552 everything on the JTAG scan chain
3553 (and anything else connected to SRST).
3554 It then invokes the logic of @command{jtag arp_init}.
3558 @node TAP Declaration
3559 @chapter TAP Declaration
3560 @cindex TAP declaration
3561 @cindex TAP configuration
3563 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3564 TAPs serve many roles, including:
3567 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
3568 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
3569 Others do it indirectly, making a CPU do it.
3570 @item @b{Program Download} Using the same CPU support GDB uses,
3571 you can initialize a DRAM controller, download code to DRAM, and then
3572 start running that code.
3573 @item @b{Boundary Scan} Most chips support boundary scan, which
3574 helps test for board assembly problems like solder bridges
3575 and missing connections
3578 OpenOCD must know about the active TAPs on your board(s).
3579 Setting up the TAPs is the core task of your configuration files.
3580 Once those TAPs are set up, you can pass their names to code
3581 which sets up CPUs and exports them as GDB targets,
3582 probes flash memory, performs low-level JTAG operations, and more.
3584 @section Scan Chains
3587 TAPs are part of a hardware @dfn{scan chain},
3588 which is daisy chain of TAPs.
3589 They also need to be added to
3590 OpenOCD's software mirror of that hardware list,
3591 giving each member a name and associating other data with it.
3592 Simple scan chains, with a single TAP, are common in
3593 systems with a single microcontroller or microprocessor.
3594 More complex chips may have several TAPs internally.
3595 Very complex scan chains might have a dozen or more TAPs:
3596 several in one chip, more in the next, and connecting
3597 to other boards with their own chips and TAPs.
3599 You can display the list with the @command{scan_chain} command.
3600 (Don't confuse this with the list displayed by the @command{targets}
3601 command, presented in the next chapter.
3602 That only displays TAPs for CPUs which are configured as
3604 Here's what the scan chain might look like for a chip more than one TAP:
3607 TapName Enabled IdCode Expected IrLen IrCap IrMask
3608 -- ------------------ ------- ---------- ---------- ----- ----- ------
3609 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3610 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3611 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3614 OpenOCD can detect some of that information, but not all
3615 of it. @xref{autoprobing,,Autoprobing}.
3616 Unfortunately those TAPs can't always be autoconfigured,
3617 because not all devices provide good support for that.
3618 JTAG doesn't require supporting IDCODE instructions, and
3619 chips with JTAG routers may not link TAPs into the chain
3620 until they are told to do so.
3622 The configuration mechanism currently supported by OpenOCD
3623 requires explicit configuration of all TAP devices using
3624 @command{jtag newtap} commands, as detailed later in this chapter.
3625 A command like this would declare one tap and name it @code{chip1.cpu}:
3628 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3631 Each target configuration file lists the TAPs provided
3633 Board configuration files combine all the targets on a board,
3635 Note that @emph{the order in which TAPs are declared is very important.}
3636 It must match the order in the JTAG scan chain, both inside
3637 a single chip and between them.
3638 @xref{faqtaporder,,FAQ TAP Order}.
3640 For example, the ST Microsystems STR912 chip has
3641 three separate TAPs@footnote{See the ST
3642 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3643 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3644 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3645 To configure those taps, @file{target/str912.cfg}
3646 includes commands something like this:
3649 jtag newtap str912 flash ... params ...
3650 jtag newtap str912 cpu ... params ...
3651 jtag newtap str912 bs ... params ...
3654 Actual config files use a variable instead of literals like
3655 @option{str912}, to support more than one chip of each type.
3656 @xref{Config File Guidelines}.
3658 @deffn Command {jtag names}
3659 Returns the names of all current TAPs in the scan chain.
3660 Use @command{jtag cget} or @command{jtag tapisenabled}
3661 to examine attributes and state of each TAP.
3663 foreach t [jtag names] @{
3664 puts [format "TAP: %s\n" $t]
3669 @deffn Command {scan_chain}
3670 Displays the TAPs in the scan chain configuration,
3672 The set of TAPs listed by this command is fixed by
3673 exiting the OpenOCD configuration stage,
3674 but systems with a JTAG router can
3675 enable or disable TAPs dynamically.
3678 @c FIXME! "jtag cget" should be able to return all TAP
3679 @c attributes, like "$target_name cget" does for targets.
3681 @c Probably want "jtag eventlist", and a "tap-reset" event
3682 @c (on entry to RESET state).
3687 When TAP objects are declared with @command{jtag newtap},
3688 a @dfn{dotted.name} is created for the TAP, combining the
3689 name of a module (usually a chip) and a label for the TAP.
3690 For example: @code{xilinx.tap}, @code{str912.flash},
3691 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3692 Many other commands use that dotted.name to manipulate or
3693 refer to the TAP. For example, CPU configuration uses the
3694 name, as does declaration of NAND or NOR flash banks.
3696 The components of a dotted name should follow ``C'' symbol
3697 name rules: start with an alphabetic character, then numbers
3698 and underscores are OK; while others (including dots!) are not.
3701 In older code, JTAG TAPs were numbered from 0..N.
3702 This feature is still present.
3703 However its use is highly discouraged, and
3704 should not be relied on; it will be removed by mid-2010.
3705 Update all of your scripts to use TAP names rather than numbers,
3706 by paying attention to the runtime warnings they trigger.
3707 Using TAP numbers in target configuration scripts prevents
3708 reusing those scripts on boards with multiple targets.
3711 @section TAP Declaration Commands
3713 @c shouldn't this be(come) a {Config Command}?
3714 @deffn Command {jtag newtap} chipname tapname configparams...
3715 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3716 and configured according to the various @var{configparams}.
3718 The @var{chipname} is a symbolic name for the chip.
3719 Conventionally target config files use @code{$_CHIPNAME},
3720 defaulting to the model name given by the chip vendor but
3723 @cindex TAP naming convention
3724 The @var{tapname} reflects the role of that TAP,
3725 and should follow this convention:
3728 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3729 @item @code{cpu} -- The main CPU of the chip, alternatively
3730 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3731 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3732 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3733 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3734 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3735 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3736 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3738 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3739 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3740 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3741 a JTAG TAP; that TAP should be named @code{sdma}.
3744 Every TAP requires at least the following @var{configparams}:
3747 @item @code{-irlen} @var{NUMBER}
3748 @*The length in bits of the
3749 instruction register, such as 4 or 5 bits.
3752 A TAP may also provide optional @var{configparams}:
3755 @item @code{-disable} (or @code{-enable})
3756 @*Use the @code{-disable} parameter to flag a TAP which is not
3757 linked in to the scan chain after a reset using either TRST
3758 or the JTAG state machine's @sc{reset} state.
3759 You may use @code{-enable} to highlight the default state
3760 (the TAP is linked in).
3761 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3762 @item @code{-expected-id} @var{number}
3763 @*A non-zero @var{number} represents a 32-bit IDCODE
3764 which you expect to find when the scan chain is examined.
3765 These codes are not required by all JTAG devices.
3766 @emph{Repeat the option} as many times as required if more than one
3767 ID code could appear (for example, multiple versions).
3768 Specify @var{number} as zero to suppress warnings about IDCODE
3769 values that were found but not included in the list.
3771 Provide this value if at all possible, since it lets OpenOCD
3772 tell when the scan chain it sees isn't right. These values
3773 are provided in vendors' chip documentation, usually a technical
3774 reference manual. Sometimes you may need to probe the JTAG
3775 hardware to find these values.
3776 @xref{autoprobing,,Autoprobing}.
3777 @item @code{-ignore-version}
3778 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3779 option. When vendors put out multiple versions of a chip, or use the same
3780 JTAG-level ID for several largely-compatible chips, it may be more practical
3781 to ignore the version field than to update config files to handle all of
3782 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3783 @item @code{-ircapture} @var{NUMBER}
3784 @*The bit pattern loaded by the TAP into the JTAG shift register
3785 on entry to the @sc{ircapture} state, such as 0x01.
3786 JTAG requires the two LSBs of this value to be 01.
3787 By default, @code{-ircapture} and @code{-irmask} are set
3788 up to verify that two-bit value. You may provide
3789 additional bits, if you know them, or indicate that
3790 a TAP doesn't conform to the JTAG specification.
3791 @item @code{-irmask} @var{NUMBER}
3792 @*A mask used with @code{-ircapture}
3793 to verify that instruction scans work correctly.
3794 Such scans are not used by OpenOCD except to verify that
3795 there seems to be no problems with JTAG scan chain operations.
3799 @section Other TAP commands
3801 @deffn Command {jtag cget} dotted.name @option{-event} name
3802 @deffnx Command {jtag configure} dotted.name @option{-event} name string
3803 At this writing this TAP attribute
3804 mechanism is used only for event handling.
3805 (It is not a direct analogue of the @code{cget}/@code{configure}
3806 mechanism for debugger targets.)
3807 See the next section for information about the available events.
3809 The @code{configure} subcommand assigns an event handler,
3810 a TCL string which is evaluated when the event is triggered.
3811 The @code{cget} subcommand returns that handler.
3818 OpenOCD includes two event mechanisms.
3819 The one presented here applies to all JTAG TAPs.
3820 The other applies to debugger targets,
3821 which are associated with certain TAPs.
3823 The TAP events currently defined are:
3826 @item @b{post-reset}
3827 @* The TAP has just completed a JTAG reset.
3828 The tap may still be in the JTAG @sc{reset} state.
3829 Handlers for these events might perform initialization sequences
3830 such as issuing TCK cycles, TMS sequences to ensure
3831 exit from the ARM SWD mode, and more.
3833 Because the scan chain has not yet been verified, handlers for these events
3834 @emph{should not issue commands which scan the JTAG IR or DR registers}
3835 of any particular target.
3836 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3838 @* The scan chain has been reset and verified.
3839 This handler may enable TAPs as needed.
3840 @item @b{tap-disable}
3841 @* The TAP needs to be disabled. This handler should
3842 implement @command{jtag tapdisable}
3843 by issuing the relevant JTAG commands.
3844 @item @b{tap-enable}
3845 @* The TAP needs to be enabled. This handler should
3846 implement @command{jtag tapenable}
3847 by issuing the relevant JTAG commands.
3850 If you need some action after each JTAG reset, which isn't actually
3851 specific to any TAP (since you can't yet trust the scan chain's
3852 contents to be accurate), you might:
3855 jtag configure CHIP.jrc -event post-reset @{
3856 echo "JTAG Reset done"
3857 ... non-scan jtag operations to be done after reset
3862 @anchor{enablinganddisablingtaps}
3863 @section Enabling and Disabling TAPs
3864 @cindex JTAG Route Controller
3867 In some systems, a @dfn{JTAG Route Controller} (JRC)
3868 is used to enable and/or disable specific JTAG TAPs.
3869 Many ARM based chips from Texas Instruments include
3870 an ``ICEpick'' module, which is a JRC.
3871 Such chips include DaVinci and OMAP3 processors.
3873 A given TAP may not be visible until the JRC has been
3874 told to link it into the scan chain; and if the JRC
3875 has been told to unlink that TAP, it will no longer
3877 Such routers address problems that JTAG ``bypass mode''
3881 @item The scan chain can only go as fast as its slowest TAP.
3882 @item Having many TAPs slows instruction scans, since all
3883 TAPs receive new instructions.
3884 @item TAPs in the scan chain must be powered up, which wastes
3885 power and prevents debugging some power management mechanisms.
3888 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3889 as implied by the existence of JTAG routers.
3890 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3891 does include a kind of JTAG router functionality.
3893 @c (a) currently the event handlers don't seem to be able to
3894 @c fail in a way that could lead to no-change-of-state.
3896 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3897 shown below, and is implemented using TAP event handlers.
3898 So for example, when defining a TAP for a CPU connected to
3899 a JTAG router, your @file{target.cfg} file
3900 should define TAP event handlers using
3901 code that looks something like this:
3904 jtag configure CHIP.cpu -event tap-enable @{
3905 ... jtag operations using CHIP.jrc
3907 jtag configure CHIP.cpu -event tap-disable @{
3908 ... jtag operations using CHIP.jrc
3912 Then you might want that CPU's TAP enabled almost all the time:
3915 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3918 Note how that particular setup event handler declaration
3919 uses quotes to evaluate @code{$CHIP} when the event is configured.
3920 Using brackets @{ @} would cause it to be evaluated later,
3921 at runtime, when it might have a different value.
3923 @deffn Command {jtag tapdisable} dotted.name
3924 If necessary, disables the tap
3925 by sending it a @option{tap-disable} event.
3926 Returns the string "1" if the tap
3927 specified by @var{dotted.name} is enabled,
3928 and "0" if it is disabled.
3931 @deffn Command {jtag tapenable} dotted.name
3932 If necessary, enables the tap
3933 by sending it a @option{tap-enable} event.
3934 Returns the string "1" if the tap
3935 specified by @var{dotted.name} is enabled,
3936 and "0" if it is disabled.
3939 @deffn Command {jtag tapisenabled} dotted.name
3940 Returns the string "1" if the tap
3941 specified by @var{dotted.name} is enabled,
3942 and "0" if it is disabled.
3945 Humans will find the @command{scan_chain} command more helpful
3946 for querying the state of the JTAG taps.
3950 @anchor{autoprobing}
3951 @section Autoprobing
3953 @cindex JTAG autoprobe
3955 TAP configuration is the first thing that needs to be done
3956 after interface and reset configuration. Sometimes it's
3957 hard finding out what TAPs exist, or how they are identified.
3958 Vendor documentation is not always easy to find and use.
3960 To help you get past such problems, OpenOCD has a limited
3961 @emph{autoprobing} ability to look at the scan chain, doing
3962 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3963 To use this mechanism, start the OpenOCD server with only data
3964 that configures your JTAG interface, and arranges to come up
3965 with a slow clock (many devices don't support fast JTAG clocks
3966 right when they come out of reset).
3968 For example, your @file{openocd.cfg} file might have:
3971 source [find interface/olimex-arm-usb-tiny-h.cfg]
3972 reset_config trst_and_srst
3976 When you start the server without any TAPs configured, it will
3977 attempt to autoconfigure the TAPs. There are two parts to this:
3980 @item @emph{TAP discovery} ...
3981 After a JTAG reset (sometimes a system reset may be needed too),
3982 each TAP's data registers will hold the contents of either the
3983 IDCODE or BYPASS register.
3984 If JTAG communication is working, OpenOCD will see each TAP,
3985 and report what @option{-expected-id} to use with it.
3986 @item @emph{IR Length discovery} ...
3987 Unfortunately JTAG does not provide a reliable way to find out
3988 the value of the @option{-irlen} parameter to use with a TAP
3990 If OpenOCD can discover the length of a TAP's instruction
3991 register, it will report it.
3992 Otherwise you may need to consult vendor documentation, such
3993 as chip data sheets or BSDL files.
3996 In many cases your board will have a simple scan chain with just
3997 a single device. Here's what OpenOCD reported with one board
3998 that's a bit more complex:
4002 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4003 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4004 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4005 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4006 AUTO auto0.tap - use "... -irlen 4"
4007 AUTO auto1.tap - use "... -irlen 4"
4008 AUTO auto2.tap - use "... -irlen 6"
4009 no gdb ports allocated as no target has been specified
4012 Given that information, you should be able to either find some existing
4013 config files to use, or create your own. If you create your own, you
4014 would configure from the bottom up: first a @file{target.cfg} file
4015 with these TAPs, any targets associated with them, and any on-chip
4016 resources; then a @file{board.cfg} with off-chip resources, clocking,
4019 @node CPU Configuration
4020 @chapter CPU Configuration
4023 This chapter discusses how to set up GDB debug targets for CPUs.
4024 You can also access these targets without GDB
4025 (@pxref{Architecture and Core Commands},
4026 and @ref{targetstatehandling,,Target State handling}) and
4027 through various kinds of NAND and NOR flash commands.
4028 If you have multiple CPUs you can have multiple such targets.
4030 We'll start by looking at how to examine the targets you have,
4031 then look at how to add one more target and how to configure it.
4033 @section Target List
4034 @cindex target, current
4035 @cindex target, list
4037 All targets that have been set up are part of a list,
4038 where each member has a name.
4039 That name should normally be the same as the TAP name.
4040 You can display the list with the @command{targets}
4042 This display often has only one CPU; here's what it might
4043 look like with more than one:
4045 TargetName Type Endian TapName State
4046 -- ------------------ ---------- ------ ------------------ ------------
4047 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4048 1 MyTarget cortex_m little mychip.foo tap-disabled
4051 One member of that list is the @dfn{current target}, which
4052 is implicitly referenced by many commands.
4053 It's the one marked with a @code{*} near the target name.
4054 In particular, memory addresses often refer to the address
4055 space seen by that current target.
4056 Commands like @command{mdw} (memory display words)
4057 and @command{flash erase_address} (erase NOR flash blocks)
4058 are examples; and there are many more.
4060 Several commands let you examine the list of targets:
4062 @deffn Command {target count}
4063 @emph{Note: target numbers are deprecated; don't use them.
4064 They will be removed shortly after August 2010, including this command.
4065 Iterate target using @command{target names}, not by counting.}
4067 Returns the number of targets, @math{N}.
4068 The highest numbered target is @math{N - 1}.
4070 set c [target count]
4071 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
4072 # Assuming you have created this function
4073 print_target_details $x
4078 @deffn Command {target current}
4079 Returns the name of the current target.
4082 @deffn Command {target names}
4083 Lists the names of all current targets in the list.
4085 foreach t [target names] @{
4086 puts [format "Target: %s\n" $t]
4091 @deffn Command {target number} number
4092 @emph{Note: target numbers are deprecated; don't use them.
4093 They will be removed shortly after August 2010, including this command.}
4095 The list of targets is numbered starting at zero.
4096 This command returns the name of the target at index @var{number}.
4098 set thename [target number $x]
4099 puts [format "Target %d is: %s\n" $x $thename]
4103 @c yep, "target list" would have been better.
4104 @c plus maybe "target setdefault".
4106 @deffn Command targets [name]
4107 @emph{Note: the name of this command is plural. Other target
4108 command names are singular.}
4110 With no parameter, this command displays a table of all known
4111 targets in a user friendly form.
4113 With a parameter, this command sets the current target to
4114 the given target with the given @var{name}; this is
4115 only relevant on boards which have more than one target.
4118 @section Target CPU Types and Variants
4123 Each target has a @dfn{CPU type}, as shown in the output of
4124 the @command{targets} command. You need to specify that type
4125 when calling @command{target create}.
4126 The CPU type indicates more than just the instruction set.
4127 It also indicates how that instruction set is implemented,
4128 what kind of debug support it integrates,
4129 whether it has an MMU (and if so, what kind),
4130 what core-specific commands may be available
4131 (@pxref{Architecture and Core Commands}),
4134 For some CPU types, OpenOCD also defines @dfn{variants} which
4135 indicate differences that affect their handling.
4136 For example, a particular implementation bug might need to be
4137 worked around in some chip versions.
4139 It's easy to see what target types are supported,
4140 since there's a command to list them.
4141 However, there is currently no way to list what target variants
4142 are supported (other than by reading the OpenOCD source code).
4144 @anchor{targettypes}
4145 @deffn Command {target types}
4146 Lists all supported target types.
4147 At this writing, the supported CPU types and variants are:
4150 @item @code{arm11} -- this is a generation of ARMv6 cores
4151 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4152 @item @code{arm7tdmi} -- this is an ARMv4 core
4153 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4154 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4155 @item @code{arm966e} -- this is an ARMv5 core
4156 @item @code{arm9tdmi} -- this is an ARMv4 core
4157 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4158 (Support for this is preliminary and incomplete.)
4159 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4160 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4161 compact Thumb2 instruction set.
4162 @item @code{dragonite} -- resembles arm966e
4163 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4164 (Support for this is still incomplete.)
4165 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4166 @item @code{feroceon} -- resembles arm926
4167 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
4168 @item @code{xscale} -- this is actually an architecture,
4169 not a CPU type. It is based on the ARMv5 architecture.
4170 There are several variants defined:
4172 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
4173 @code{pxa27x} ... instruction register length is 7 bits
4174 @item @code{pxa250}, @code{pxa255},
4175 @code{pxa26x} ... instruction register length is 5 bits
4176 @item @code{pxa3xx} ... instruction register length is 11 bits
4181 To avoid being confused by the variety of ARM based cores, remember
4182 this key point: @emph{ARM is a technology licencing company}.
4183 (See: @url{http://www.arm.com}.)
4184 The CPU name used by OpenOCD will reflect the CPU design that was
4185 licenced, not a vendor brand which incorporates that design.
4186 Name prefixes like arm7, arm9, arm11, and cortex
4187 reflect design generations;
4188 while names like ARMv4, ARMv5, ARMv6, and ARMv7
4189 reflect an architecture version implemented by a CPU design.
4191 @anchor{targetconfiguration}
4192 @section Target Configuration
4194 Before creating a ``target'', you must have added its TAP to the scan chain.
4195 When you've added that TAP, you will have a @code{dotted.name}
4196 which is used to set up the CPU support.
4197 The chip-specific configuration file will normally configure its CPU(s)
4198 right after it adds all of the chip's TAPs to the scan chain.
4200 Although you can set up a target in one step, it's often clearer if you
4201 use shorter commands and do it in two steps: create it, then configure
4203 All operations on the target after it's created will use a new
4204 command, created as part of target creation.
4206 The two main things to configure after target creation are
4207 a work area, which usually has target-specific defaults even
4208 if the board setup code overrides them later;
4209 and event handlers (@pxref{targetevents,,Target Events}), which tend
4210 to be much more board-specific.
4211 The key steps you use might look something like this
4214 target create MyTarget cortex_m -chain-position mychip.cpu
4215 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4216 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4217 $MyTarget configure -event reset-init @{ myboard_reinit @}
4220 You should specify a working area if you can; typically it uses some
4222 Such a working area can speed up many things, including bulk
4223 writes to target memory;
4224 flash operations like checking to see if memory needs to be erased;
4225 GDB memory checksumming;
4229 On more complex chips, the work area can become
4230 inaccessible when application code
4231 (such as an operating system)
4232 enables or disables the MMU.
4233 For example, the particular MMU context used to acess the virtual
4234 address will probably matter ... and that context might not have
4235 easy access to other addresses needed.
4236 At this writing, OpenOCD doesn't have much MMU intelligence.
4239 It's often very useful to define a @code{reset-init} event handler.
4240 For systems that are normally used with a boot loader,
4241 common tasks include updating clocks and initializing memory
4243 That may be needed to let you write the boot loader into flash,
4244 in order to ``de-brick'' your board; or to load programs into
4245 external DDR memory without having run the boot loader.
4247 @deffn Command {target create} target_name type configparams...
4248 This command creates a GDB debug target that refers to a specific JTAG tap.
4249 It enters that target into a list, and creates a new
4250 command (@command{@var{target_name}}) which is used for various
4251 purposes including additional configuration.
4254 @item @var{target_name} ... is the name of the debug target.
4255 By convention this should be the same as the @emph{dotted.name}
4256 of the TAP associated with this target, which must be specified here
4257 using the @code{-chain-position @var{dotted.name}} configparam.
4259 This name is also used to create the target object command,
4260 referred to here as @command{$target_name},
4261 and in other places the target needs to be identified.
4262 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4263 @item @var{configparams} ... all parameters accepted by
4264 @command{$target_name configure} are permitted.
4265 If the target is big-endian, set it here with @code{-endian big}.
4266 If the variant matters, set it here with @code{-variant}.
4268 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
4272 @deffn Command {$target_name configure} configparams...
4273 The options accepted by this command may also be
4274 specified as parameters to @command{target create}.
4275 Their values can later be queried one at a time by
4276 using the @command{$target_name cget} command.
4278 @emph{Warning:} changing some of these after setup is dangerous.
4279 For example, moving a target from one TAP to another;
4280 and changing its endianness or variant.
4284 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4285 used to access this target.
4287 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4288 whether the CPU uses big or little endian conventions
4290 @item @code{-event} @var{event_name} @var{event_body} --
4291 @xref{targetevents,,Target Events}.
4292 Note that this updates a list of named event handlers.
4293 Calling this twice with two different event names assigns
4294 two different handlers, but calling it twice with the
4295 same event name assigns only one handler.
4297 @item @code{-variant} @var{name} -- specifies a variant of the target,
4298 which OpenOCD needs to know about.
4300 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4301 whether the work area gets backed up; by default,
4302 @emph{it is not backed up.}
4303 When possible, use a working_area that doesn't need to be backed up,
4304 since performing a backup slows down operations.
4305 For example, the beginning of an SRAM block is likely to
4306 be used by most build systems, but the end is often unused.
4308 @item @code{-work-area-size} @var{size} -- specify work are size,
4309 in bytes. The same size applies regardless of whether its physical
4310 or virtual address is being used.
4312 @item @code{-work-area-phys} @var{address} -- set the work area
4313 base @var{address} to be used when no MMU is active.
4315 @item @code{-work-area-virt} @var{address} -- set the work area
4316 base @var{address} to be used when an MMU is active.
4317 @emph{Do not specify a value for this except on targets with an MMU.}
4318 The value should normally correspond to a static mapping for the
4319 @code{-work-area-phys} address, set up by the current operating system.
4322 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4323 @var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}|
4324 @option{FreeRTOS}|@option{linux}|@option{ChibiOS}|@option{embKernel}
4325 @xref{gdbrtossupport,,RTOS Support}.
4330 @section Other $target_name Commands
4331 @cindex object command
4333 The Tcl/Tk language has the concept of object commands,
4334 and OpenOCD adopts that same model for targets.
4336 A good Tk example is a on screen button.
4337 Once a button is created a button
4338 has a name (a path in Tk terms) and that name is useable as a first
4339 class command. For example in Tk, one can create a button and later
4340 configure it like this:
4344 button .foobar -background red -command @{ foo @}
4346 .foobar configure -foreground blue
4348 set x [.foobar cget -background]
4350 puts [format "The button is %s" $x]
4353 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4354 button, and its object commands are invoked the same way.
4357 str912.cpu mww 0x1234 0x42
4358 omap3530.cpu mww 0x5555 123
4361 The commands supported by OpenOCD target objects are:
4363 @deffn Command {$target_name arp_examine}
4364 @deffnx Command {$target_name arp_halt}
4365 @deffnx Command {$target_name arp_poll}
4366 @deffnx Command {$target_name arp_reset}
4367 @deffnx Command {$target_name arp_waitstate}
4368 Internal OpenOCD scripts (most notably @file{startup.tcl})
4369 use these to deal with specific reset cases.
4370 They are not otherwise documented here.
4373 @deffn Command {$target_name array2mem} arrayname width address count
4374 @deffnx Command {$target_name mem2array} arrayname width address count
4375 These provide an efficient script-oriented interface to memory.
4376 The @code{array2mem} primitive writes bytes, halfwords, or words;
4377 while @code{mem2array} reads them.
4378 In both cases, the TCL side uses an array, and
4379 the target side uses raw memory.
4381 The efficiency comes from enabling the use of
4382 bulk JTAG data transfer operations.
4383 The script orientation comes from working with data
4384 values that are packaged for use by TCL scripts;
4385 @command{mdw} type primitives only print data they retrieve,
4386 and neither store nor return those values.
4389 @item @var{arrayname} ... is the name of an array variable
4390 @item @var{width} ... is 8/16/32 - indicating the memory access size
4391 @item @var{address} ... is the target memory address
4392 @item @var{count} ... is the number of elements to process
4396 @deffn Command {$target_name cget} queryparm
4397 Each configuration parameter accepted by
4398 @command{$target_name configure}
4399 can be individually queried, to return its current value.
4400 The @var{queryparm} is a parameter name
4401 accepted by that command, such as @code{-work-area-phys}.
4402 There are a few special cases:
4405 @item @code{-event} @var{event_name} -- returns the handler for the
4406 event named @var{event_name}.
4407 This is a special case because setting a handler requires
4409 @item @code{-type} -- returns the target type.
4410 This is a special case because this is set using
4411 @command{target create} and can't be changed
4412 using @command{$target_name configure}.
4415 For example, if you wanted to summarize information about
4416 all the targets you might use something like this:
4419 foreach name [target names] @{
4420 set y [$name cget -endian]
4421 set z [$name cget -type]
4422 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4428 @anchor{targetcurstate}
4429 @deffn Command {$target_name curstate}
4430 Displays the current target state:
4431 @code{debug-running},
4434 @code{running}, or @code{unknown}.
4435 (Also, @pxref{eventpolling,,Event Polling}.)
4438 @deffn Command {$target_name eventlist}
4439 Displays a table listing all event handlers
4440 currently associated with this target.
4441 @xref{targetevents,,Target Events}.
4444 @deffn Command {$target_name invoke-event} event_name
4445 Invokes the handler for the event named @var{event_name}.
4446 (This is primarily intended for use by OpenOCD framework
4447 code, for example by the reset code in @file{startup.tcl}.)
4450 @deffn Command {$target_name mdw} addr [count]
4451 @deffnx Command {$target_name mdh} addr [count]
4452 @deffnx Command {$target_name mdb} addr [count]
4453 Display contents of address @var{addr}, as
4454 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4455 or 8-bit bytes (@command{mdb}).
4456 If @var{count} is specified, displays that many units.
4457 (If you want to manipulate the data instead of displaying it,
4458 see the @code{mem2array} primitives.)
4461 @deffn Command {$target_name mww} addr word
4462 @deffnx Command {$target_name mwh} addr halfword
4463 @deffnx Command {$target_name mwb} addr byte
4464 Writes the specified @var{word} (32 bits),
4465 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4466 at the specified address @var{addr}.
4469 @anchor{targetevents}
4470 @section Target Events
4471 @cindex target events
4473 At various times, certain things can happen, or you want them to happen.
4476 @item What should happen when GDB connects? Should your target reset?
4477 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4478 @item Is using SRST appropriate (and possible) on your system?
4479 Or instead of that, do you need to issue JTAG commands to trigger reset?
4480 SRST usually resets everything on the scan chain, which can be inappropriate.
4481 @item During reset, do you need to write to certain memory locations
4482 to set up system clocks or
4483 to reconfigure the SDRAM?
4484 How about configuring the watchdog timer, or other peripherals,
4485 to stop running while you hold the core stopped for debugging?
4488 All of the above items can be addressed by target event handlers.
4489 These are set up by @command{$target_name configure -event} or
4490 @command{target create ... -event}.
4492 The programmer's model matches the @code{-command} option used in Tcl/Tk
4493 buttons and events. The two examples below act the same, but one creates
4494 and invokes a small procedure while the other inlines it.
4497 proc my_attach_proc @{ @} @{
4501 mychip.cpu configure -event gdb-attach my_attach_proc
4502 mychip.cpu configure -event gdb-attach @{
4504 # To make flash probe and gdb load to flash work we need a reset init.
4509 The following target events are defined:
4512 @item @b{debug-halted}
4513 @* The target has halted for debug reasons (i.e.: breakpoint)
4514 @item @b{debug-resumed}
4515 @* The target has resumed (i.e.: gdb said run)
4516 @item @b{early-halted}
4517 @* Occurs early in the halt process
4518 @item @b{examine-start}
4519 @* Before target examine is called.
4520 @item @b{examine-end}
4521 @* After target examine is called with no errors.
4522 @item @b{gdb-attach}
4523 @* When GDB connects. This is before any communication with the target, so this
4524 can be used to set up the target so it is possible to probe flash. Probing flash
4525 is necessary during gdb connect if gdb load is to write the image to flash. Another
4526 use of the flash memory map is for GDB to automatically hardware/software breakpoints
4527 depending on whether the breakpoint is in RAM or read only memory.
4528 @item @b{gdb-detach}
4529 @* When GDB disconnects
4531 @* When the target has halted and GDB is not doing anything (see early halt)
4532 @item @b{gdb-flash-erase-start}
4533 @* Before the GDB flash process tries to erase the flash
4534 @item @b{gdb-flash-erase-end}
4535 @* After the GDB flash process has finished erasing the flash
4536 @item @b{gdb-flash-write-start}
4537 @* Before GDB writes to the flash
4538 @item @b{gdb-flash-write-end}
4539 @* After GDB writes to the flash
4541 @* Before the target steps, gdb is trying to start/resume the target
4543 @* The target has halted
4544 @item @b{reset-assert-pre}
4545 @* Issued as part of @command{reset} processing
4546 after @command{reset_init} was triggered
4547 but before either SRST alone is re-asserted on the scan chain,
4548 or @code{reset-assert} is triggered.
4549 @item @b{reset-assert}
4550 @* Issued as part of @command{reset} processing
4551 after @command{reset-assert-pre} was triggered.
4552 When such a handler is present, cores which support this event will use
4553 it instead of asserting SRST.
4554 This support is essential for debugging with JTAG interfaces which
4555 don't include an SRST line (JTAG doesn't require SRST), and for
4556 selective reset on scan chains that have multiple targets.
4557 @item @b{reset-assert-post}
4558 @* Issued as part of @command{reset} processing
4559 after @code{reset-assert} has been triggered.
4560 or the target asserted SRST on the entire scan chain.
4561 @item @b{reset-deassert-pre}
4562 @* Issued as part of @command{reset} processing
4563 after @code{reset-assert-post} has been triggered.
4564 @item @b{reset-deassert-post}
4565 @* Issued as part of @command{reset} processing
4566 after @code{reset-deassert-pre} has been triggered
4567 and (if the target is using it) after SRST has been
4568 released on the scan chain.
4570 @* Issued as the final step in @command{reset} processing.
4572 @item @b{reset-halt-post}
4573 @* Currently not used
4574 @item @b{reset-halt-pre}
4575 @* Currently not used
4577 @item @b{reset-init}
4578 @* Used by @b{reset init} command for board-specific initialization.
4579 This event fires after @emph{reset-deassert-post}.
4581 This is where you would configure PLLs and clocking, set up DRAM so
4582 you can download programs that don't fit in on-chip SRAM, set up pin
4583 multiplexing, and so on.
4584 (You may be able to switch to a fast JTAG clock rate here, after
4585 the target clocks are fully set up.)
4586 @item @b{reset-start}
4587 @* Issued as part of @command{reset} processing
4588 before @command{reset_init} is called.
4590 This is the most robust place to use @command{jtag_rclk}
4591 or @command{adapter_khz} to switch to a low JTAG clock rate,
4592 when reset disables PLLs needed to use a fast clock.
4594 @item @b{reset-wait-pos}
4595 @* Currently not used
4596 @item @b{reset-wait-pre}
4597 @* Currently not used
4599 @item @b{resume-start}
4600 @* Before any target is resumed
4601 @item @b{resume-end}
4602 @* After all targets have resumed
4604 @* Target has resumed
4607 @node Flash Commands
4608 @chapter Flash Commands
4610 OpenOCD has different commands for NOR and NAND flash;
4611 the ``flash'' command works with NOR flash, while
4612 the ``nand'' command works with NAND flash.
4613 This partially reflects different hardware technologies:
4614 NOR flash usually supports direct CPU instruction and data bus access,
4615 while data from a NAND flash must be copied to memory before it can be
4616 used. (SPI flash must also be copied to memory before use.)
4617 However, the documentation also uses ``flash'' as a generic term;
4618 for example, ``Put flash configuration in board-specific files''.
4622 @item Configure via the command @command{flash bank}
4623 @* Do this in a board-specific configuration file,
4624 passing parameters as needed by the driver.
4625 @item Operate on the flash via @command{flash subcommand}
4626 @* Often commands to manipulate the flash are typed by a human, or run
4627 via a script in some automated way. Common tasks include writing a
4628 boot loader, operating system, or other data.
4630 @* Flashing via GDB requires the flash be configured via ``flash
4631 bank'', and the GDB flash features be enabled.
4632 @xref{gdbconfiguration,,GDB Configuration}.
4635 Many CPUs have the ablity to ``boot'' from the first flash bank.
4636 This means that misprogramming that bank can ``brick'' a system,
4637 so that it can't boot.
4638 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4639 board by (re)installing working boot firmware.
4641 @anchor{norconfiguration}
4642 @section Flash Configuration Commands
4643 @cindex flash configuration
4645 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4646 Configures a flash bank which provides persistent storage
4647 for addresses from @math{base} to @math{base + size - 1}.
4648 These banks will often be visible to GDB through the target's memory map.
4649 In some cases, configuring a flash bank will activate extra commands;
4650 see the driver-specific documentation.
4653 @item @var{name} ... may be used to reference the flash bank
4654 in other flash commands. A number is also available.
4655 @item @var{driver} ... identifies the controller driver
4656 associated with the flash bank being declared.
4657 This is usually @code{cfi} for external flash, or else
4658 the name of a microcontroller with embedded flash memory.
4659 @xref{flashdriverlist,,Flash Driver List}.
4660 @item @var{base} ... Base address of the flash chip.
4661 @item @var{size} ... Size of the chip, in bytes.
4662 For some drivers, this value is detected from the hardware.
4663 @item @var{chip_width} ... Width of the flash chip, in bytes;
4664 ignored for most microcontroller drivers.
4665 @item @var{bus_width} ... Width of the data bus used to access the
4666 chip, in bytes; ignored for most microcontroller drivers.
4667 @item @var{target} ... Names the target used to issue
4668 commands to the flash controller.
4669 @comment Actually, it's currently a controller-specific parameter...
4670 @item @var{driver_options} ... drivers may support, or require,
4671 additional parameters. See the driver-specific documentation
4672 for more information.
4675 This command is not available after OpenOCD initialization has completed.
4676 Use it in board specific configuration files, not interactively.
4680 @comment the REAL name for this command is "ocd_flash_banks"
4681 @comment less confusing would be: "flash list" (like "nand list")
4682 @deffn Command {flash banks}
4683 Prints a one-line summary of each device that was
4684 declared using @command{flash bank}, numbered from zero.
4685 Note that this is the @emph{plural} form;
4686 the @emph{singular} form is a very different command.
4689 @deffn Command {flash list}
4690 Retrieves a list of associative arrays for each device that was
4691 declared using @command{flash bank}, numbered from zero.
4692 This returned list can be manipulated easily from within scripts.
4695 @deffn Command {flash probe} num
4696 Identify the flash, or validate the parameters of the configured flash. Operation
4697 depends on the flash type.
4698 The @var{num} parameter is a value shown by @command{flash banks}.
4699 Most flash commands will implicitly @emph{autoprobe} the bank;
4700 flash drivers can distinguish between probing and autoprobing,
4701 but most don't bother.
4704 @section Erasing, Reading, Writing to Flash
4705 @cindex flash erasing
4706 @cindex flash reading
4707 @cindex flash writing
4708 @cindex flash programming
4709 @anchor{flashprogrammingcommands}
4711 One feature distinguishing NOR flash from NAND or serial flash technologies
4712 is that for read access, it acts exactly like any other addressible memory.
4713 This means you can use normal memory read commands like @command{mdw} or
4714 @command{dump_image} with it, with no special @command{flash} subcommands.
4715 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
4717 Write access works differently. Flash memory normally needs to be erased
4718 before it's written. Erasing a sector turns all of its bits to ones, and
4719 writing can turn ones into zeroes. This is why there are special commands
4720 for interactive erasing and writing, and why GDB needs to know which parts
4721 of the address space hold NOR flash memory.
4724 Most of these erase and write commands leverage the fact that NOR flash
4725 chips consume target address space. They implicitly refer to the current
4726 JTAG target, and map from an address in that target's address space
4727 back to a flash bank.
4728 @comment In May 2009, those mappings may fail if any bank associated
4729 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
4730 A few commands use abstract addressing based on bank and sector numbers,
4731 and don't depend on searching the current target and its address space.
4732 Avoid confusing the two command models.
4735 Some flash chips implement software protection against accidental writes,
4736 since such buggy writes could in some cases ``brick'' a system.
4737 For such systems, erasing and writing may require sector protection to be
4739 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4740 and AT91SAM7 on-chip flash.
4741 @xref{flashprotect,,flash protect}.
4743 @deffn Command {flash erase_sector} num first last
4744 Erase sectors in bank @var{num}, starting at sector @var{first}
4745 up to and including @var{last}.
4746 Sector numbering starts at 0.
4747 Providing a @var{last} sector of @option{last}
4748 specifies "to the end of the flash bank".
4749 The @var{num} parameter is a value shown by @command{flash banks}.
4752 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4753 Erase sectors starting at @var{address} for @var{length} bytes.
4754 Unless @option{pad} is specified, @math{address} must begin a
4755 flash sector, and @math{address + length - 1} must end a sector.
4756 Specifying @option{pad} erases extra data at the beginning and/or
4757 end of the specified region, as needed to erase only full sectors.
4758 The flash bank to use is inferred from the @var{address}, and
4759 the specified length must stay within that bank.
4760 As a special case, when @var{length} is zero and @var{address} is
4761 the start of the bank, the whole flash is erased.
4762 If @option{unlock} is specified, then the flash is unprotected
4763 before erase starts.
4766 @deffn Command {flash fillw} address word length
4767 @deffnx Command {flash fillh} address halfword length
4768 @deffnx Command {flash fillb} address byte length
4769 Fills flash memory with the specified @var{word} (32 bits),
4770 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4771 starting at @var{address} and continuing
4772 for @var{length} units (word/halfword/byte).
4773 No erasure is done before writing; when needed, that must be done
4774 before issuing this command.
4775 Writes are done in blocks of up to 1024 bytes, and each write is
4776 verified by reading back the data and comparing it to what was written.
4777 The flash bank to use is inferred from the @var{address} of
4778 each block, and the specified length must stay within that bank.
4780 @comment no current checks for errors if fill blocks touch multiple banks!
4782 @deffn Command {flash write_bank} num filename offset
4783 Write the binary @file{filename} to flash bank @var{num},
4784 starting at @var{offset} bytes from the beginning of the bank.
4785 The @var{num} parameter is a value shown by @command{flash banks}.
4788 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4789 Write the image @file{filename} to the current target's flash bank(s).
4790 A relocation @var{offset} may be specified, in which case it is added
4791 to the base address for each section in the image.
4792 The file [@var{type}] can be specified
4793 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4794 @option{elf} (ELF file), @option{s19} (Motorola s19).
4795 @option{mem}, or @option{builder}.
4796 The relevant flash sectors will be erased prior to programming
4797 if the @option{erase} parameter is given. If @option{unlock} is
4798 provided, then the flash banks are unlocked before erase and
4799 program. The flash bank to use is inferred from the address of
4803 Be careful using the @option{erase} flag when the flash is holding
4804 data you want to preserve.
4805 Portions of the flash outside those described in the image's
4806 sections might be erased with no notice.
4809 When a section of the image being written does not fill out all the
4810 sectors it uses, the unwritten parts of those sectors are necessarily
4811 also erased, because sectors can't be partially erased.
4813 Data stored in sector "holes" between image sections are also affected.
4814 For example, "@command{flash write_image erase ...}" of an image with
4815 one byte at the beginning of a flash bank and one byte at the end
4816 erases the entire bank -- not just the two sectors being written.
4818 Also, when flash protection is important, you must re-apply it after
4819 it has been removed by the @option{unlock} flag.
4824 @section Other Flash commands
4825 @cindex flash protection
4827 @deffn Command {flash erase_check} num
4828 Check erase state of sectors in flash bank @var{num},
4829 and display that status.
4830 The @var{num} parameter is a value shown by @command{flash banks}.
4833 @deffn Command {flash info} num
4834 Print info about flash bank @var{num}
4835 The @var{num} parameter is a value shown by @command{flash banks}.
4836 This command will first query the hardware, it does not print cached
4837 and possibly stale information.
4840 @anchor{flashprotect}
4841 @deffn Command {flash protect} num first last (@option{on}|@option{off})
4842 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
4843 in flash bank @var{num}, starting at sector @var{first}
4844 and continuing up to and including @var{last}.
4845 Providing a @var{last} sector of @option{last}
4846 specifies "to the end of the flash bank".
4847 The @var{num} parameter is a value shown by @command{flash banks}.
4851 @deffn Command {program} filename [verify] [reset] [offset]
4852 This is a helper script that simplifies using OpenOCD as a standalone
4853 programmer. The only required parameter is @option{filename}, the others are optional.
4854 @xref{Flash Programming}.
4857 @anchor{flashdriverlist}
4858 @section Flash Driver List
4859 As noted above, the @command{flash bank} command requires a driver name,
4860 and allows driver-specific options and behaviors.
4861 Some drivers also activate driver-specific commands.
4863 @subsection External Flash
4865 @deffn {Flash Driver} cfi
4866 @cindex Common Flash Interface
4868 The ``Common Flash Interface'' (CFI) is the main standard for
4869 external NOR flash chips, each of which connects to a
4870 specific external chip select on the CPU.
4871 Frequently the first such chip is used to boot the system.
4872 Your board's @code{reset-init} handler might need to
4873 configure additional chip selects using other commands (like: @command{mww} to
4874 configure a bus and its timings), or
4875 perhaps configure a GPIO pin that controls the ``write protect'' pin
4877 The CFI driver can use a target-specific working area to significantly
4880 The CFI driver can accept the following optional parameters, in any order:
4883 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
4884 like AM29LV010 and similar types.
4885 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
4888 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
4889 wide on a sixteen bit bus:
4892 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
4893 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
4896 To configure one bank of 32 MBytes
4897 built from two sixteen bit (two byte) wide parts wired in parallel
4898 to create a thirty-two bit (four byte) bus with doubled throughput:
4901 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
4904 @c "cfi part_id" disabled
4907 @deffn {Flash Driver} lpcspifi
4908 @cindex NXP SPI Flash Interface
4911 NXP's LPC43xx and LPC18xx families include a proprietary SPI
4912 Flash Interface (SPIFI) peripheral that can drive and provide
4913 memory mapped access to external SPI flash devices.
4915 The lpcspifi driver initializes this interface and provides
4916 program and erase functionality for these serial flash devices.
4917 Use of this driver @b{requires} a working area of at least 1kB
4918 to be configured on the target device; more than this will
4919 significantly reduce flash programming times.
4921 The setup command only requires the @var{base} parameter. All
4922 other parameters are ignored, and the flash size and layout
4923 are configured by the driver.
4926 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
4931 @deffn {Flash Driver} stmsmi
4932 @cindex STMicroelectronics Serial Memory Interface
4935 Some devices form STMicroelectronics (e.g. STR75x MCU family,
4936 SPEAr MPU family) include a proprietary
4937 ``Serial Memory Interface'' (SMI) controller able to drive external
4939 Depending on specific device and board configuration, up to 4 external
4940 flash devices can be connected.
4942 SMI makes the flash content directly accessible in the CPU address
4943 space; each external device is mapped in a memory bank.
4944 CPU can directly read data, execute code and boot from SMI banks.
4945 Normal OpenOCD commands like @command{mdw} can be used to display
4948 The setup command only requires the @var{base} parameter in order
4949 to identify the memory bank.
4950 All other parameters are ignored. Additional information, like
4951 flash size, are detected automatically.
4954 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
4959 @subsection Internal Flash (Microcontrollers)
4961 @deffn {Flash Driver} aduc702x
4962 The ADUC702x analog microcontrollers from Analog Devices
4963 include internal flash and use ARM7TDMI cores.
4964 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
4965 The setup command only requires the @var{target} argument
4966 since all devices in this family have the same memory layout.
4969 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
4974 @deffn {Flash Driver} at91sam3
4976 All members of the AT91SAM3 microcontroller family from
4977 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
4978 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
4979 that the driver was orginaly developed and tested using the
4980 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
4981 the family was cribbed from the data sheet. @emph{Note to future
4982 readers/updaters: Please remove this worrysome comment after other
4983 chips are confirmed.}
4985 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
4986 have one flash bank. In all cases the flash banks are at
4987 the following fixed locations:
4990 # Flash bank 0 - all chips
4991 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
4992 # Flash bank 1 - only 256K chips
4993 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
4996 Internally, the AT91SAM3 flash memory is organized as follows.
4997 Unlike the AT91SAM7 chips, these are not used as parameters
4998 to the @command{flash bank} command:
5001 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
5002 @item @emph{Bank Size:} 128K/64K Per flash bank
5003 @item @emph{Sectors:} 16 or 8 per bank
5004 @item @emph{SectorSize:} 8K Per Sector
5005 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
5008 The AT91SAM3 driver adds some additional commands:
5010 @deffn Command {at91sam3 gpnvm}
5011 @deffnx Command {at91sam3 gpnvm clear} number
5012 @deffnx Command {at91sam3 gpnvm set} number
5013 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
5014 With no parameters, @command{show} or @command{show all},
5015 shows the status of all GPNVM bits.
5016 With @command{show} @var{number}, displays that bit.
5018 With @command{set} @var{number} or @command{clear} @var{number},
5019 modifies that GPNVM bit.
5022 @deffn Command {at91sam3 info}
5023 This command attempts to display information about the AT91SAM3
5024 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
5025 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
5026 document id: doc6430A] and decodes the values. @emph{Second} it reads the
5027 various clock configuration registers and attempts to display how it
5028 believes the chip is configured. By default, the SLOWCLK is assumed to
5029 be 32768 Hz, see the command @command{at91sam3 slowclk}.
5032 @deffn Command {at91sam3 slowclk} [value]
5033 This command shows/sets the slow clock frequency used in the
5034 @command{at91sam3 info} command calculations above.
5038 @deffn {Flash Driver} at91sam4
5040 All members of the AT91SAM4 microcontroller family from
5041 Atmel include internal flash and use ARM's Cortex-M4 core.
5042 This driver uses the same cmd names/syntax as @xref{at91sam3}.
5045 @deffn {Flash Driver} at91sam7
5046 All members of the AT91SAM7 microcontroller family from Atmel include
5047 internal flash and use ARM7TDMI cores. The driver automatically
5048 recognizes a number of these chips using the chip identification
5049 register, and autoconfigures itself.
5052 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
5055 For chips which are not recognized by the controller driver, you must
5056 provide additional parameters in the following order:
5059 @item @var{chip_model} ... label used with @command{flash info}
5061 @item @var{sectors_per_bank}
5062 @item @var{pages_per_sector}
5063 @item @var{pages_size}
5064 @item @var{num_nvm_bits}
5065 @item @var{freq_khz} ... required if an external clock is provided,
5066 optional (but recommended) when the oscillator frequency is known
5069 It is recommended that you provide zeroes for all of those values
5070 except the clock frequency, so that everything except that frequency
5071 will be autoconfigured.
5072 Knowing the frequency helps ensure correct timings for flash access.
5074 The flash controller handles erases automatically on a page (128/256 byte)
5075 basis, so explicit erase commands are not necessary for flash programming.
5076 However, there is an ``EraseAll`` command that can erase an entire flash
5077 plane (of up to 256KB), and it will be used automatically when you issue
5078 @command{flash erase_sector} or @command{flash erase_address} commands.
5080 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
5081 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
5082 bit for the processor. Each processor has a number of such bits,
5083 used for controlling features such as brownout detection (so they
5084 are not truly general purpose).
5086 This assumes that the first flash bank (number 0) is associated with
5087 the appropriate at91sam7 target.
5092 @deffn {Flash Driver} avr
5093 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
5094 @emph{The current implementation is incomplete.}
5095 @comment - defines mass_erase ... pointless given flash_erase_address
5098 @deffn {Flash Driver} efm32
5099 All members of the EFM32 microcontroller family from Energy Micro include
5100 internal flash and use ARM Cortex M3 cores. The driver automatically recognizes
5101 a number of these chips using the chip identification register, and
5102 autoconfigures itself.
5104 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
5106 @emph{The current implementation is incomplete. Unprotecting flash pages is not
5110 @deffn {Flash Driver} lpc2000
5111 Most members of the LPC1700, LPC1800, LPC2000 and LPC4300 microcontroller
5112 families from NXP include internal flash and use Cortex-M3 (LPC1700, LPC1800),
5113 Cortex-M4 (LPC4300) or ARM7TDMI (LPC2000) cores.
5116 There are LPC2000 devices which are not supported by the @var{lpc2000}
5118 The LPC2888 is supported by the @var{lpc288x} driver.
5119 The LPC29xx family is supported by the @var{lpc2900} driver.
5122 The @var{lpc2000} driver defines two mandatory and one optional parameters,
5123 which must appear in the following order:
5126 @item @var{variant} ... required, may be
5127 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
5128 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
5129 @option{lpc1700} (LPC175x and LPC176x)
5130 or @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
5132 @item @var{clock_kHz} ... the frequency, in kiloHertz,
5133 at which the core is running
5134 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
5135 telling the driver to calculate a valid checksum for the exception vector table.
5137 If you don't provide @option{calc_checksum} when you're writing the vector
5138 table, the boot ROM will almost certainly ignore your flash image.
5139 However, if you do provide it,
5140 with most tool chains @command{verify_image} will fail.
5144 LPC flashes don't require the chip and bus width to be specified.
5147 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
5148 lpc2000_v2 14765 calc_checksum
5151 @deffn {Command} {lpc2000 part_id} bank
5152 Displays the four byte part identifier associated with
5153 the specified flash @var{bank}.
5157 @deffn {Flash Driver} lpc288x
5158 The LPC2888 microcontroller from NXP needs slightly different flash
5159 support from its lpc2000 siblings.
5160 The @var{lpc288x} driver defines one mandatory parameter,
5161 the programming clock rate in Hz.
5162 LPC flashes don't require the chip and bus width to be specified.
5165 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
5169 @deffn {Flash Driver} lpc2900
5170 This driver supports the LPC29xx ARM968E based microcontroller family
5173 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
5174 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
5175 sector layout are auto-configured by the driver.
5176 The driver has one additional mandatory parameter: The CPU clock rate
5177 (in kHz) at the time the flash operations will take place. Most of the time this
5178 will not be the crystal frequency, but a higher PLL frequency. The
5179 @code{reset-init} event handler in the board script is usually the place where
5182 The driver rejects flashless devices (currently the LPC2930).
5184 The EEPROM in LPC2900 devices is not mapped directly into the address space.
5185 It must be handled much more like NAND flash memory, and will therefore be
5186 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
5188 Sector protection in terms of the LPC2900 is handled transparently. Every time a
5189 sector needs to be erased or programmed, it is automatically unprotected.
5190 What is shown as protection status in the @code{flash info} command, is
5191 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
5192 sector from ever being erased or programmed again. As this is an irreversible
5193 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
5194 and not by the standard @code{flash protect} command.
5196 Example for a 125 MHz clock frequency:
5198 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
5201 Some @code{lpc2900}-specific commands are defined. In the following command list,
5202 the @var{bank} parameter is the bank number as obtained by the
5203 @code{flash banks} command.
5205 @deffn Command {lpc2900 signature} bank
5206 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
5207 content. This is a hardware feature of the flash block, hence the calculation is
5208 very fast. You may use this to verify the content of a programmed device against
5213 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
5217 @deffn Command {lpc2900 read_custom} bank filename
5218 Reads the 912 bytes of customer information from the flash index sector, and
5219 saves it to a file in binary format.
5222 lpc2900 read_custom 0 /path_to/customer_info.bin
5226 The index sector of the flash is a @emph{write-only} sector. It cannot be
5227 erased! In order to guard against unintentional write access, all following
5228 commands need to be preceeded by a successful call to the @code{password}
5231 @deffn Command {lpc2900 password} bank password
5232 You need to use this command right before each of the following commands:
5233 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
5234 @code{lpc2900 secure_jtag}.
5236 The password string is fixed to "I_know_what_I_am_doing".
5239 lpc2900 password 0 I_know_what_I_am_doing
5240 Potentially dangerous operation allowed in next command!
5244 @deffn Command {lpc2900 write_custom} bank filename type
5245 Writes the content of the file into the customer info space of the flash index
5246 sector. The filetype can be specified with the @var{type} field. Possible values
5247 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
5248 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
5249 contain a single section, and the contained data length must be exactly
5251 @quotation Attention
5252 This cannot be reverted! Be careful!
5256 lpc2900 write_custom 0 /path_to/customer_info.bin bin
5260 @deffn Command {lpc2900 secure_sector} bank first last
5261 Secures the sector range from @var{first} to @var{last} (including) against
5262 further program and erase operations. The sector security will be effective
5263 after the next power cycle.
5264 @quotation Attention
5265 This cannot be reverted! Be careful!
5267 Secured sectors appear as @emph{protected} in the @code{flash info} command.
5270 lpc2900 secure_sector 0 1 1
5272 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
5273 # 0: 0x00000000 (0x2000 8kB) not protected
5274 # 1: 0x00002000 (0x2000 8kB) protected
5275 # 2: 0x00004000 (0x2000 8kB) not protected
5279 @deffn Command {lpc2900 secure_jtag} bank
5280 Irreversibly disable the JTAG port. The new JTAG security setting will be
5281 effective after the next power cycle.
5282 @quotation Attention
5283 This cannot be reverted! Be careful!
5287 lpc2900 secure_jtag 0
5292 @deffn {Flash Driver} ocl
5293 @emph{No idea what this is, other than using some arm7/arm9 core.}
5296 flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
5300 @deffn {Flash Driver} pic32mx
5301 The PIC32MX microcontrollers are based on the MIPS 4K cores,
5302 and integrate flash memory.
5305 flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
5306 flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
5309 @comment numerous *disabled* commands are defined:
5310 @comment - chip_erase ... pointless given flash_erase_address
5311 @comment - lock, unlock ... pointless given protect on/off (yes?)
5312 @comment - pgm_word ... shouldn't bank be deduced from address??
5313 Some pic32mx-specific commands are defined:
5314 @deffn Command {pic32mx pgm_word} address value bank
5315 Programs the specified 32-bit @var{value} at the given @var{address}
5316 in the specified chip @var{bank}.
5318 @deffn Command {pic32mx unlock} bank
5319 Unlock and erase specified chip @var{bank}.
5320 This will remove any Code Protection.
5324 @deffn {Flash Driver} stellaris
5325 All members of the Stellaris LM3Sxxx microcontroller family from
5327 include internal flash and use ARM Cortex M3 cores.
5328 The driver automatically recognizes a number of these chips using
5329 the chip identification register, and autoconfigures itself.
5330 @footnote{Currently there is a @command{stellaris mass_erase} command.
5331 That seems pointless since the same effect can be had using the
5332 standard @command{flash erase_address} command.}
5335 flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
5338 @deffn Command {stellaris recover bank_id}
5339 Performs the @emph{Recovering a "Locked" Device} procedure to
5340 restore the flash specified by @var{bank_id} and its associated
5341 nonvolatile registers to their factory default values (erased).
5342 This is the only way to remove flash protection or re-enable
5343 debugging if that capability has been disabled.
5345 Note that the final "power cycle the chip" step in this procedure
5346 must be performed by hand, since OpenOCD can't do it.
5348 if more than one Stellaris chip is connected, the procedure is
5349 applied to all of them.
5354 @deffn {Flash Driver} stm32f1x
5355 All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
5356 from ST Microelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores.
5357 The driver automatically recognizes a number of these chips using
5358 the chip identification register, and autoconfigures itself.
5361 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
5364 Note that some devices have been found that have a flash size register that contains
5365 an invalid value, to workaround this issue you can override the probed value used by
5369 flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
5372 If you have a target with dual flash banks then define the second bank
5373 as per the following example.
5375 flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
5378 Some stm32f1x-specific commands
5379 @footnote{Currently there is a @command{stm32f1x mass_erase} command.
5380 That seems pointless since the same effect can be had using the
5381 standard @command{flash erase_address} command.}
5384 @deffn Command {stm32f1x lock} num
5385 Locks the entire stm32 device.
5386 The @var{num} parameter is a value shown by @command{flash banks}.
5389 @deffn Command {stm32f1x unlock} num
5390 Unlocks the entire stm32 device.
5391 The @var{num} parameter is a value shown by @command{flash banks}.
5394 @deffn Command {stm32f1x options_read} num
5395 Read and display the stm32 option bytes written by
5396 the @command{stm32f1x options_write} command.
5397 The @var{num} parameter is a value shown by @command{flash banks}.
5400 @deffn Command {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
5401 Writes the stm32 option byte with the specified values.
5402 The @var{num} parameter is a value shown by @command{flash banks}.
5406 @deffn {Flash Driver} stm32f2x
5407 All members of the STM32F2 and STM32F4 microcontroller families from ST Microelectronics
5408 include internal flash and use ARM Cortex-M3/M4 cores.
5409 The driver automatically recognizes a number of these chips using
5410 the chip identification register, and autoconfigures itself.
5412 Note that some devices have been found that have a flash size register that contains
5413 an invalid value, to workaround this issue you can override the probed value used by
5417 flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
5420 Some stm32f2x-specific commands are defined:
5422 @deffn Command {stm32f2x lock} num
5423 Locks the entire stm32 device.
5424 The @var{num} parameter is a value shown by @command{flash banks}.
5427 @deffn Command {stm32f2x unlock} num
5428 Unlocks the entire stm32 device.
5429 The @var{num} parameter is a value shown by @command{flash banks}.
5433 @deffn {Flash Driver} stm32lx
5434 All members of the STM32L microcontroller families from ST Microelectronics
5435 include internal flash and use ARM Cortex-M3 cores.
5436 The driver automatically recognizes a number of these chips using
5437 the chip identification register, and autoconfigures itself.
5439 Note that some devices have been found that have a flash size register that contains
5440 an invalid value, to workaround this issue you can override the probed value used by
5444 flash bank $_FLASHNAME stm32lx 0 0x20000 0 0 $_TARGETNAME
5448 @deffn {Flash Driver} str7x
5449 All members of the STR7 microcontroller family from ST Microelectronics
5450 include internal flash and use ARM7TDMI cores.
5451 The @var{str7x} driver defines one mandatory parameter, @var{variant},
5452 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
5455 flash bank $_FLASHNAME str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
5458 @deffn Command {str7x disable_jtag} bank
5459 Activate the Debug/Readout protection mechanism
5460 for the specified flash bank.
5464 @deffn {Flash Driver} str9x
5465 Most members of the STR9 microcontroller family from ST Microelectronics
5466 include internal flash and use ARM966E cores.
5467 The str9 needs the flash controller to be configured using
5468 the @command{str9x flash_config} command prior to Flash programming.
5471 flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
5472 str9x flash_config 0 4 2 0 0x80000
5475 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
5476 Configures the str9 flash controller.
5477 The @var{num} parameter is a value shown by @command{flash banks}.
5480 @item @var{bbsr} - Boot Bank Size register
5481 @item @var{nbbsr} - Non Boot Bank Size register
5482 @item @var{bbadr} - Boot Bank Start Address register
5483 @item @var{nbbadr} - Boot Bank Start Address register
5489 @deffn {Flash Driver} tms470
5490 Most members of the TMS470 microcontroller family from Texas Instruments
5491 include internal flash and use ARM7TDMI cores.
5492 This driver doesn't require the chip and bus width to be specified.
5494 Some tms470-specific commands are defined:
5496 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
5497 Saves programming keys in a register, to enable flash erase and write commands.
5500 @deffn Command {tms470 osc_mhz} clock_mhz
5501 Reports the clock speed, which is used to calculate timings.
5504 @deffn Command {tms470 plldis} (0|1)
5505 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
5510 @deffn {Flash Driver} virtual
5511 This is a special driver that maps a previously defined bank to another
5512 address. All bank settings will be copied from the master physical bank.
5514 The @var{virtual} driver defines one mandatory parameters,
5517 @item @var{master_bank} The bank that this virtual address refers to.
5520 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
5521 the flash bank defined at address 0x1fc00000. Any cmds executed on
5522 the virtual banks are actually performed on the physical banks.
5524 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
5525 flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
5526 flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
5530 @deffn {Flash Driver} fm3
5531 All members of the FM3 microcontroller family from Fujitsu
5532 include internal flash and use ARM Cortex M3 cores.
5533 The @var{fm3} driver uses the @var{target} parameter to select the
5534 correct bank config, it can currently be one of the following:
5535 @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
5536 @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
5539 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
5543 @subsection str9xpec driver
5546 Here is some background info to help
5547 you better understand how this driver works. OpenOCD has two flash drivers for
5551 Standard driver @option{str9x} programmed via the str9 core. Normally used for
5552 flash programming as it is faster than the @option{str9xpec} driver.
5554 Direct programming @option{str9xpec} using the flash controller. This is an
5555 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
5556 core does not need to be running to program using this flash driver. Typical use
5557 for this driver is locking/unlocking the target and programming the option bytes.
5560 Before we run any commands using the @option{str9xpec} driver we must first disable
5561 the str9 core. This example assumes the @option{str9xpec} driver has been
5562 configured for flash bank 0.
5564 # assert srst, we do not want core running
5565 # while accessing str9xpec flash driver
5567 # turn off target polling
5570 str9xpec enable_turbo 0
5572 str9xpec options_read 0
5573 # re-enable str9 core
5574 str9xpec disable_turbo 0
5578 The above example will read the str9 option bytes.
5579 When performing a unlock remember that you will not be able to halt the str9 - it
5580 has been locked. Halting the core is not required for the @option{str9xpec} driver
5581 as mentioned above, just issue the commands above manually or from a telnet prompt.
5583 @deffn {Flash Driver} str9xpec
5584 Only use this driver for locking/unlocking the device or configuring the option bytes.
5585 Use the standard str9 driver for programming.
5586 Before using the flash commands the turbo mode must be enabled using the
5587 @command{str9xpec enable_turbo} command.
5589 Several str9xpec-specific commands are defined:
5591 @deffn Command {str9xpec disable_turbo} num
5592 Restore the str9 into JTAG chain.
5595 @deffn Command {str9xpec enable_turbo} num
5596 Enable turbo mode, will simply remove the str9 from the chain and talk
5597 directly to the embedded flash controller.
5600 @deffn Command {str9xpec lock} num
5601 Lock str9 device. The str9 will only respond to an unlock command that will
5605 @deffn Command {str9xpec part_id} num
5606 Prints the part identifier for bank @var{num}.
5609 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
5610 Configure str9 boot bank.
5613 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
5614 Configure str9 lvd source.
5617 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
5618 Configure str9 lvd threshold.
5621 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
5622 Configure str9 lvd reset warning source.
5625 @deffn Command {str9xpec options_read} num
5626 Read str9 option bytes.
5629 @deffn Command {str9xpec options_write} num
5630 Write str9 option bytes.
5633 @deffn Command {str9xpec unlock} num
5642 @subsection mFlash Configuration
5643 @cindex mFlash Configuration
5645 @deffn {Config Command} {mflash bank} soc base RST_pin target
5646 Configures a mflash for @var{soc} host bank at
5648 The pin number format depends on the host GPIO naming convention.
5649 Currently, the mflash driver supports s3c2440 and pxa270.
5651 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
5654 mflash bank $_FLASHNAME s3c2440 0x10000000 1b 0
5657 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
5660 mflash bank $_FLASHNAME pxa270 0x08000000 43 0
5664 @subsection mFlash commands
5665 @cindex mFlash commands
5667 @deffn Command {mflash config pll} frequency
5668 Configure mflash PLL.
5669 The @var{frequency} is the mflash input frequency, in Hz.
5670 Issuing this command will erase mflash's whole internal nand and write new pll.
5671 After this command, mflash needs power-on-reset for normal operation.
5672 If pll was newly configured, storage and boot(optional) info also need to be update.
5675 @deffn Command {mflash config boot}
5676 Configure bootable option.
5677 If bootable option is set, mflash offer the first 8 sectors
5681 @deffn Command {mflash config storage}
5682 Configure storage information.
5683 For the normal storage operation, this information must be
5687 @deffn Command {mflash dump} num filename offset size
5688 Dump @var{size} bytes, starting at @var{offset} bytes from the
5689 beginning of the bank @var{num}, to the file named @var{filename}.
5692 @deffn Command {mflash probe}
5696 @deffn Command {mflash write} num filename offset
5697 Write the binary file @var{filename} to mflash bank @var{num}, starting at
5698 @var{offset} bytes from the beginning of the bank.
5701 @node Flash Programming
5702 @chapter Flash Programming
5704 OpenOCD implements numerous ways to program the target flash, whether internal or external.
5705 Programming can be acheived by either using GDB @ref{programmingusinggdb,,Programming using GDB},
5706 or using the cmds given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
5708 @*To simplify using the flash cmds directly a jimtcl script is available that handles the programming and verify stage.
5709 OpenOCD will program/verify/reset the target and shutdown.
5711 The script is executed as follows and by default the following actions will be peformed.
5713 @item 'init' is executed.
5714 @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
5715 @item @code{flash write_image} is called to erase and write any flash using the filename given.
5716 @item @code{verify_image} is called if @option{verify} parameter is given.
5717 @item @code{reset run} is called if @option{reset} parameter is given.
5718 @item OpenOCD is shutdown.
5721 An example of usage is given below. @xref{program}.
5724 # program and verify using elf/hex/s19. verify and reset
5725 # are optional parameters
5726 openocd -f board/stm32f3discovery.cfg \
5727 -c "program filename.elf verify reset"
5729 # binary files need the flash address passing
5730 openocd -f board/stm32f3discovery.cfg \
5731 -c "program filename.bin 0x08000000"
5734 @node NAND Flash Commands
5735 @chapter NAND Flash Commands
5738 Compared to NOR or SPI flash, NAND devices are inexpensive
5739 and high density. Today's NAND chips, and multi-chip modules,
5740 commonly hold multiple GigaBytes of data.
5742 NAND chips consist of a number of ``erase blocks'' of a given
5743 size (such as 128 KBytes), each of which is divided into a
5744 number of pages (of perhaps 512 or 2048 bytes each). Each
5745 page of a NAND flash has an ``out of band'' (OOB) area to hold
5746 Error Correcting Code (ECC) and other metadata, usually 16 bytes
5747 of OOB for every 512 bytes of page data.
5749 One key characteristic of NAND flash is that its error rate
5750 is higher than that of NOR flash. In normal operation, that
5751 ECC is used to correct and detect errors. However, NAND
5752 blocks can also wear out and become unusable; those blocks
5753 are then marked "bad". NAND chips are even shipped from the
5754 manufacturer with a few bad blocks. The highest density chips
5755 use a technology (MLC) that wears out more quickly, so ECC
5756 support is increasingly important as a way to detect blocks
5757 that have begun to fail, and help to preserve data integrity
5758 with techniques such as wear leveling.
5760 Software is used to manage the ECC. Some controllers don't
5761 support ECC directly; in those cases, software ECC is used.
5762 Other controllers speed up the ECC calculations with hardware.
5763 Single-bit error correction hardware is routine. Controllers
5764 geared for newer MLC chips may correct 4 or more errors for
5765 every 512 bytes of data.
5767 You will need to make sure that any data you write using
5768 OpenOCD includes the apppropriate kind of ECC. For example,
5769 that may mean passing the @code{oob_softecc} flag when
5770 writing NAND data, or ensuring that the correct hardware
5773 The basic steps for using NAND devices include:
5775 @item Declare via the command @command{nand device}
5776 @* Do this in a board-specific configuration file,
5777 passing parameters as needed by the controller.
5778 @item Configure each device using @command{nand probe}.
5779 @* Do this only after the associated target is set up,
5780 such as in its reset-init script or in procures defined
5781 to access that device.
5782 @item Operate on the flash via @command{nand subcommand}
5783 @* Often commands to manipulate the flash are typed by a human, or run
5784 via a script in some automated way. Common task include writing a
5785 boot loader, operating system, or other data needed to initialize or
5789 @b{NOTE:} At the time this text was written, the largest NAND
5790 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
5791 This is because the variables used to hold offsets and lengths
5792 are only 32 bits wide.
5793 (Larger chips may work in some cases, unless an offset or length
5794 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
5795 Some larger devices will work, since they are actually multi-chip
5796 modules with two smaller chips and individual chipselect lines.
5798 @anchor{nandconfiguration}
5799 @section NAND Configuration Commands
5800 @cindex NAND configuration
5802 NAND chips must be declared in configuration scripts,
5803 plus some additional configuration that's done after
5804 OpenOCD has initialized.
5806 @deffn {Config Command} {nand device} name driver target [configparams...]
5807 Declares a NAND device, which can be read and written to
5808 after it has been configured through @command{nand probe}.
5809 In OpenOCD, devices are single chips; this is unlike some
5810 operating systems, which may manage multiple chips as if
5811 they were a single (larger) device.
5812 In some cases, configuring a device will activate extra
5813 commands; see the controller-specific documentation.
5815 @b{NOTE:} This command is not available after OpenOCD
5816 initialization has completed. Use it in board specific
5817 configuration files, not interactively.
5820 @item @var{name} ... may be used to reference the NAND bank
5821 in most other NAND commands. A number is also available.
5822 @item @var{driver} ... identifies the NAND controller driver
5823 associated with the NAND device being declared.
5824 @xref{nanddriverlist,,NAND Driver List}.
5825 @item @var{target} ... names the target used when issuing
5826 commands to the NAND controller.
5827 @comment Actually, it's currently a controller-specific parameter...
5828 @item @var{configparams} ... controllers may support, or require,
5829 additional parameters. See the controller-specific documentation
5830 for more information.
5834 @deffn Command {nand list}
5835 Prints a summary of each device declared
5836 using @command{nand device}, numbered from zero.
5837 Note that un-probed devices show no details.
5840 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
5841 blocksize: 131072, blocks: 8192
5842 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
5843 blocksize: 131072, blocks: 8192
5848 @deffn Command {nand probe} num
5849 Probes the specified device to determine key characteristics
5850 like its page and block sizes, and how many blocks it has.
5851 The @var{num} parameter is the value shown by @command{nand list}.
5852 You must (successfully) probe a device before you can use
5853 it with most other NAND commands.
5856 @section Erasing, Reading, Writing to NAND Flash
5858 @deffn Command {nand dump} num filename offset length [oob_option]
5859 @cindex NAND reading
5860 Reads binary data from the NAND device and writes it to the file,
5861 starting at the specified offset.
5862 The @var{num} parameter is the value shown by @command{nand list}.
5864 Use a complete path name for @var{filename}, so you don't depend
5865 on the directory used to start the OpenOCD server.
5867 The @var{offset} and @var{length} must be exact multiples of the
5868 device's page size. They describe a data region; the OOB data
5869 associated with each such page may also be accessed.
5871 @b{NOTE:} At the time this text was written, no error correction
5872 was done on the data that's read, unless raw access was disabled
5873 and the underlying NAND controller driver had a @code{read_page}
5874 method which handled that error correction.
5876 By default, only page data is saved to the specified file.
5877 Use an @var{oob_option} parameter to save OOB data:
5879 @item no oob_* parameter
5880 @*Output file holds only page data; OOB is discarded.
5881 @item @code{oob_raw}
5882 @*Output file interleaves page data and OOB data;
5883 the file will be longer than "length" by the size of the
5884 spare areas associated with each data page.
5885 Note that this kind of "raw" access is different from
5886 what's implied by @command{nand raw_access}, which just
5887 controls whether a hardware-aware access method is used.
5888 @item @code{oob_only}
5889 @*Output file has only raw OOB data, and will
5890 be smaller than "length" since it will contain only the
5891 spare areas associated with each data page.
5895 @deffn Command {nand erase} num [offset length]
5896 @cindex NAND erasing
5897 @cindex NAND programming
5898 Erases blocks on the specified NAND device, starting at the
5899 specified @var{offset} and continuing for @var{length} bytes.
5900 Both of those values must be exact multiples of the device's
5901 block size, and the region they specify must fit entirely in the chip.
5902 If those parameters are not specified,
5903 the whole NAND chip will be erased.
5904 The @var{num} parameter is the value shown by @command{nand list}.
5906 @b{NOTE:} This command will try to erase bad blocks, when told
5907 to do so, which will probably invalidate the manufacturer's bad
5909 For the remainder of the current server session, @command{nand info}
5910 will still report that the block ``is'' bad.
5913 @deffn Command {nand write} num filename offset [option...]
5914 @cindex NAND writing
5915 @cindex NAND programming
5916 Writes binary data from the file into the specified NAND device,
5917 starting at the specified offset. Those pages should already
5918 have been erased; you can't change zero bits to one bits.
5919 The @var{num} parameter is the value shown by @command{nand list}.
5921 Use a complete path name for @var{filename}, so you don't depend
5922 on the directory used to start the OpenOCD server.
5924 The @var{offset} must be an exact multiple of the device's page size.
5925 All data in the file will be written, assuming it doesn't run
5926 past the end of the device.
5927 Only full pages are written, and any extra space in the last
5928 page will be filled with 0xff bytes. (That includes OOB data,
5929 if that's being written.)
5931 @b{NOTE:} At the time this text was written, bad blocks are
5932 ignored. That is, this routine will not skip bad blocks,
5933 but will instead try to write them. This can cause problems.
5935 Provide at most one @var{option} parameter. With some
5936 NAND drivers, the meanings of these parameters may change
5937 if @command{nand raw_access} was used to disable hardware ECC.
5939 @item no oob_* parameter
5940 @*File has only page data, which is written.
5941 If raw acccess is in use, the OOB area will not be written.
5942 Otherwise, if the underlying NAND controller driver has
5943 a @code{write_page} routine, that routine may write the OOB
5944 with hardware-computed ECC data.
5945 @item @code{oob_only}
5946 @*File has only raw OOB data, which is written to the OOB area.
5947 Each page's data area stays untouched. @i{This can be a dangerous
5948 option}, since it can invalidate the ECC data.
5949 You may need to force raw access to use this mode.
5950 @item @code{oob_raw}
5951 @*File interleaves data and OOB data, both of which are written
5952 If raw access is enabled, the data is written first, then the
5954 Otherwise, if the underlying NAND controller driver has
5955 a @code{write_page} routine, that routine may modify the OOB
5956 before it's written, to include hardware-computed ECC data.
5957 @item @code{oob_softecc}
5958 @*File has only page data, which is written.
5959 The OOB area is filled with 0xff, except for a standard 1-bit
5960 software ECC code stored in conventional locations.
5961 You might need to force raw access to use this mode, to prevent
5962 the underlying driver from applying hardware ECC.
5963 @item @code{oob_softecc_kw}
5964 @*File has only page data, which is written.
5965 The OOB area is filled with 0xff, except for a 4-bit software ECC
5966 specific to the boot ROM in Marvell Kirkwood SoCs.
5967 You might need to force raw access to use this mode, to prevent
5968 the underlying driver from applying hardware ECC.
5972 @deffn Command {nand verify} num filename offset [option...]
5973 @cindex NAND verification
5974 @cindex NAND programming
5975 Verify the binary data in the file has been programmed to the
5976 specified NAND device, starting at the specified offset.
5977 The @var{num} parameter is the value shown by @command{nand list}.
5979 Use a complete path name for @var{filename}, so you don't depend
5980 on the directory used to start the OpenOCD server.
5982 The @var{offset} must be an exact multiple of the device's page size.
5983 All data in the file will be read and compared to the contents of the
5984 flash, assuming it doesn't run past the end of the device.
5985 As with @command{nand write}, only full pages are verified, so any extra
5986 space in the last page will be filled with 0xff bytes.
5988 The same @var{options} accepted by @command{nand write},
5989 and the file will be processed similarly to produce the buffers that
5990 can be compared against the contents produced from @command{nand dump}.
5992 @b{NOTE:} This will not work when the underlying NAND controller
5993 driver's @code{write_page} routine must update the OOB with a
5994 hardward-computed ECC before the data is written. This limitation may
5995 be removed in a future release.
5998 @section Other NAND commands
5999 @cindex NAND other commands
6001 @deffn Command {nand check_bad_blocks} num [offset length]
6002 Checks for manufacturer bad block markers on the specified NAND
6003 device. If no parameters are provided, checks the whole
6004 device; otherwise, starts at the specified @var{offset} and
6005 continues for @var{length} bytes.
6006 Both of those values must be exact multiples of the device's
6007 block size, and the region they specify must fit entirely in the chip.
6008 The @var{num} parameter is the value shown by @command{nand list}.
6010 @b{NOTE:} Before using this command you should force raw access
6011 with @command{nand raw_access enable} to ensure that the underlying
6012 driver will not try to apply hardware ECC.
6015 @deffn Command {nand info} num
6016 The @var{num} parameter is the value shown by @command{nand list}.
6017 This prints the one-line summary from "nand list", plus for
6018 devices which have been probed this also prints any known
6019 status for each block.
6022 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
6023 Sets or clears an flag affecting how page I/O is done.
6024 The @var{num} parameter is the value shown by @command{nand list}.
6026 This flag is cleared (disabled) by default, but changing that
6027 value won't affect all NAND devices. The key factor is whether
6028 the underlying driver provides @code{read_page} or @code{write_page}
6029 methods. If it doesn't provide those methods, the setting of
6030 this flag is irrelevant; all access is effectively ``raw''.
6032 When those methods exist, they are normally used when reading
6033 data (@command{nand dump} or reading bad block markers) or
6034 writing it (@command{nand write}). However, enabling
6035 raw access (setting the flag) prevents use of those methods,
6036 bypassing hardware ECC logic.
6037 @i{This can be a dangerous option}, since writing blocks
6038 with the wrong ECC data can cause them to be marked as bad.
6041 @anchor{nanddriverlist}
6042 @section NAND Driver List
6043 As noted above, the @command{nand device} command allows
6044 driver-specific options and behaviors.
6045 Some controllers also activate controller-specific commands.
6047 @deffn {NAND Driver} at91sam9
6048 This driver handles the NAND controllers found on AT91SAM9 family chips from
6049 Atmel. It takes two extra parameters: address of the NAND chip;
6050 address of the ECC controller.
6052 nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
6054 AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
6055 @code{read_page} methods are used to utilize the ECC hardware unless they are
6056 disabled by using the @command{nand raw_access} command. There are four
6057 additional commands that are needed to fully configure the AT91SAM9 NAND
6058 controller. Two are optional; most boards use the same wiring for ALE/CLE:
6059 @deffn Command {at91sam9 cle} num addr_line
6060 Configure the address line used for latching commands. The @var{num}
6061 parameter is the value shown by @command{nand list}.
6063 @deffn Command {at91sam9 ale} num addr_line
6064 Configure the address line used for latching addresses. The @var{num}
6065 parameter is the value shown by @command{nand list}.
6068 For the next two commands, it is assumed that the pins have already been
6069 properly configured for input or output.
6070 @deffn Command {at91sam9 rdy_busy} num pio_base_addr pin
6071 Configure the RDY/nBUSY input from the NAND device. The @var{num}
6072 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
6073 is the base address of the PIO controller and @var{pin} is the pin number.
6075 @deffn Command {at91sam9 ce} num pio_base_addr pin
6076 Configure the chip enable input to the NAND device. The @var{num}
6077 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
6078 is the base address of the PIO controller and @var{pin} is the pin number.
6082 @deffn {NAND Driver} davinci
6083 This driver handles the NAND controllers found on DaVinci family
6084 chips from Texas Instruments.
6085 It takes three extra parameters:
6086 address of the NAND chip;
6087 hardware ECC mode to use (@option{hwecc1},
6088 @option{hwecc4}, @option{hwecc4_infix});
6089 address of the AEMIF controller on this processor.
6091 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
6093 All DaVinci processors support the single-bit ECC hardware,
6094 and newer ones also support the four-bit ECC hardware.
6095 The @code{write_page} and @code{read_page} methods are used
6096 to implement those ECC modes, unless they are disabled using
6097 the @command{nand raw_access} command.
6100 @deffn {NAND Driver} lpc3180
6101 These controllers require an extra @command{nand device}
6102 parameter: the clock rate used by the controller.
6103 @deffn Command {lpc3180 select} num [mlc|slc]
6104 Configures use of the MLC or SLC controller mode.
6105 MLC implies use of hardware ECC.
6106 The @var{num} parameter is the value shown by @command{nand list}.
6109 At this writing, this driver includes @code{write_page}
6110 and @code{read_page} methods. Using @command{nand raw_access}
6111 to disable those methods will prevent use of hardware ECC
6112 in the MLC controller mode, but won't change SLC behavior.
6114 @comment current lpc3180 code won't issue 5-byte address cycles
6116 @deffn {NAND Driver} mx3
6117 This driver handles the NAND controller in i.MX31. The mxc driver
6118 should work for this chip aswell.
6121 @deffn {NAND Driver} mxc
6122 This driver handles the NAND controller found in Freescale i.MX
6123 chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
6124 The driver takes 3 extra arguments, chip (@option{mx27},
6125 @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
6126 and optionally if bad block information should be swapped between
6127 main area and spare area (@option{biswap}), defaults to off.
6129 nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
6131 @deffn Command {mxc biswap} bank_num [enable|disable]
6132 Turns on/off bad block information swaping from main area,
6133 without parameter query status.
6137 @deffn {NAND Driver} orion
6138 These controllers require an extra @command{nand device}
6139 parameter: the address of the controller.
6141 nand device orion 0xd8000000
6143 These controllers don't define any specialized commands.
6144 At this writing, their drivers don't include @code{write_page}
6145 or @code{read_page} methods, so @command{nand raw_access} won't
6146 change any behavior.
6149 @deffn {NAND Driver} s3c2410
6150 @deffnx {NAND Driver} s3c2412
6151 @deffnx {NAND Driver} s3c2440
6152 @deffnx {NAND Driver} s3c2443
6153 @deffnx {NAND Driver} s3c6400
6154 These S3C family controllers don't have any special
6155 @command{nand device} options, and don't define any
6156 specialized commands.
6157 At this writing, their drivers don't include @code{write_page}
6158 or @code{read_page} methods, so @command{nand raw_access} won't
6159 change any behavior.
6162 @node PLD/FPGA Commands
6163 @chapter PLD/FPGA Commands
6167 Programmable Logic Devices (PLDs) and the more flexible
6168 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
6169 OpenOCD can support programming them.
6170 Although PLDs are generally restrictive (cells are less functional, and
6171 there are no special purpose cells for memory or computational tasks),
6172 they share the same OpenOCD infrastructure.
6173 Accordingly, both are called PLDs here.
6175 @section PLD/FPGA Configuration and Commands
6177 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
6178 OpenOCD maintains a list of PLDs available for use in various commands.
6179 Also, each such PLD requires a driver.
6181 They are referenced by the number shown by the @command{pld devices} command,
6182 and new PLDs are defined by @command{pld device driver_name}.
6184 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
6185 Defines a new PLD device, supported by driver @var{driver_name},
6186 using the TAP named @var{tap_name}.
6187 The driver may make use of any @var{driver_options} to configure its
6191 @deffn {Command} {pld devices}
6192 Lists the PLDs and their numbers.
6195 @deffn {Command} {pld load} num filename
6196 Loads the file @file{filename} into the PLD identified by @var{num}.
6197 The file format must be inferred by the driver.
6200 @section PLD/FPGA Drivers, Options, and Commands
6202 Drivers may support PLD-specific options to the @command{pld device}
6203 definition command, and may also define commands usable only with
6204 that particular type of PLD.
6206 @deffn {FPGA Driver} virtex2
6207 Virtex-II is a family of FPGAs sold by Xilinx.
6208 It supports the IEEE 1532 standard for In-System Configuration (ISC).
6209 No driver-specific PLD definition options are used,
6210 and one driver-specific command is defined.
6212 @deffn {Command} {virtex2 read_stat} num
6213 Reads and displays the Virtex-II status register (STAT)
6218 @node General Commands
6219 @chapter General Commands
6222 The commands documented in this chapter here are common commands that
6223 you, as a human, may want to type and see the output of. Configuration type
6224 commands are documented elsewhere.
6228 @item @b{Source Of Commands}
6229 @* OpenOCD commands can occur in a configuration script (discussed
6230 elsewhere) or typed manually by a human or supplied programatically,
6231 or via one of several TCP/IP Ports.
6233 @item @b{From the human}
6234 @* A human should interact with the telnet interface (default port: 4444)
6235 or via GDB (default port 3333).
6237 To issue commands from within a GDB session, use the @option{monitor}
6238 command, e.g. use @option{monitor poll} to issue the @option{poll}
6239 command. All output is relayed through the GDB session.
6241 @item @b{Machine Interface}
6242 The Tcl interface's intent is to be a machine interface. The default Tcl
6247 @section Daemon Commands
6249 @deffn {Command} exit
6250 Exits the current telnet session.
6253 @deffn {Command} help [string]
6254 With no parameters, prints help text for all commands.
6255 Otherwise, prints each helptext containing @var{string}.
6256 Not every command provides helptext.
6258 Configuration commands, and commands valid at any time, are
6259 explicitly noted in parenthesis.
6260 In most cases, no such restriction is listed; this indicates commands
6261 which are only available after the configuration stage has completed.
6264 @deffn Command sleep msec [@option{busy}]
6265 Wait for at least @var{msec} milliseconds before resuming.
6266 If @option{busy} is passed, busy-wait instead of sleeping.
6267 (This option is strongly discouraged.)
6268 Useful in connection with script files
6269 (@command{script} command and @command{target_name} configuration).
6272 @deffn Command shutdown
6273 Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
6277 @deffn Command debug_level [n]
6278 @cindex message level
6279 Display debug level.
6280 If @var{n} (from 0..3) is provided, then set it to that level.
6281 This affects the kind of messages sent to the server log.
6282 Level 0 is error messages only;
6283 level 1 adds warnings;
6284 level 2 adds informational messages;
6285 and level 3 adds debugging messages.
6286 The default is level 2, but that can be overridden on
6287 the command line along with the location of that log
6288 file (which is normally the server's standard output).
6292 @deffn Command echo [-n] message
6293 Logs a message at "user" priority.
6294 Output @var{message} to stdout.
6295 Option "-n" suppresses trailing newline.
6297 echo "Downloading kernel -- please wait"
6301 @deffn Command log_output [filename]
6302 Redirect logging to @var{filename};
6303 the initial log output channel is stderr.
6306 @deffn Command add_script_search_dir [directory]
6307 Add @var{directory} to the file/script search path.
6310 @anchor{targetstatehandling}
6311 @section Target State handling
6314 @cindex target initialization
6316 In this section ``target'' refers to a CPU configured as
6317 shown earlier (@pxref{CPU Configuration}).
6318 These commands, like many, implicitly refer to
6319 a current target which is used to perform the
6320 various operations. The current target may be changed
6321 by using @command{targets} command with the name of the
6322 target which should become current.
6324 @deffn Command reg [(number|name) [value]]
6325 Access a single register by @var{number} or by its @var{name}.
6326 The target must generally be halted before access to CPU core
6327 registers is allowed. Depending on the hardware, some other
6328 registers may be accessible while the target is running.
6330 @emph{With no arguments}:
6331 list all available registers for the current target,
6332 showing number, name, size, value, and cache status.
6333 For valid entries, a value is shown; valid entries
6334 which are also dirty (and will be written back later)
6335 are flagged as such.
6337 @emph{With number/name}: display that register's value.
6339 @emph{With both number/name and value}: set register's value.
6340 Writes may be held in a writeback cache internal to OpenOCD,
6341 so that setting the value marks the register as dirty instead
6342 of immediately flushing that value. Resuming CPU execution
6343 (including by single stepping) or otherwise activating the
6344 relevant module will flush such values.
6346 Cores may have surprisingly many registers in their
6347 Debug and trace infrastructure:
6352 (0) r0 (/32): 0x0000D3C2 (dirty)
6353 (1) r1 (/32): 0xFD61F31C
6356 (164) ETM_contextid_comparator_mask (/32)
6361 @deffn Command halt [ms]
6362 @deffnx Command wait_halt [ms]
6363 The @command{halt} command first sends a halt request to the target,
6364 which @command{wait_halt} doesn't.
6365 Otherwise these behave the same: wait up to @var{ms} milliseconds,
6366 or 5 seconds if there is no parameter, for the target to halt
6367 (and enter debug mode).
6368 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
6371 On ARM cores, software using the @emph{wait for interrupt} operation
6372 often blocks the JTAG access needed by a @command{halt} command.
6373 This is because that operation also puts the core into a low
6374 power mode by gating the core clock;
6375 but the core clock is needed to detect JTAG clock transitions.
6377 One partial workaround uses adaptive clocking: when the core is
6378 interrupted the operation completes, then JTAG clocks are accepted
6379 at least until the interrupt handler completes.
6380 However, this workaround is often unusable since the processor, board,
6381 and JTAG adapter must all support adaptive JTAG clocking.
6382 Also, it can't work until an interrupt is issued.
6384 A more complete workaround is to not use that operation while you
6385 work with a JTAG debugger.
6386 Tasking environments generaly have idle loops where the body is the
6387 @emph{wait for interrupt} operation.
6388 (On older cores, it is a coprocessor action;
6389 newer cores have a @option{wfi} instruction.)
6390 Such loops can just remove that operation, at the cost of higher
6391 power consumption (because the CPU is needlessly clocked).
6396 @deffn Command resume [address]
6397 Resume the target at its current code position,
6398 or the optional @var{address} if it is provided.
6399 OpenOCD will wait 5 seconds for the target to resume.
6402 @deffn Command step [address]
6403 Single-step the target at its current code position,
6404 or the optional @var{address} if it is provided.
6407 @anchor{resetcommand}
6408 @deffn Command reset
6409 @deffnx Command {reset run}
6410 @deffnx Command {reset halt}
6411 @deffnx Command {reset init}
6412 Perform as hard a reset as possible, using SRST if possible.
6413 @emph{All defined targets will be reset, and target
6414 events will fire during the reset sequence.}
6416 The optional parameter specifies what should
6417 happen after the reset.
6418 If there is no parameter, a @command{reset run} is executed.
6419 The other options will not work on all systems.
6420 @xref{Reset Configuration}.
6423 @item @b{run} Let the target run
6424 @item @b{halt} Immediately halt the target
6425 @item @b{init} Immediately halt the target, and execute the reset-init script
6429 @deffn Command soft_reset_halt
6430 Requesting target halt and executing a soft reset. This is often used
6431 when a target cannot be reset and halted. The target, after reset is
6432 released begins to execute code. OpenOCD attempts to stop the CPU and
6433 then sets the program counter back to the reset vector. Unfortunately
6434 the code that was executed may have left the hardware in an unknown
6438 @section I/O Utilities
6440 These commands are available when
6441 OpenOCD is built with @option{--enable-ioutil}.
6442 They are mainly useful on embedded targets,
6444 Hosts with operating systems have complementary tools.
6446 @emph{Note:} there are several more such commands.
6448 @deffn Command append_file filename [string]*
6449 Appends the @var{string} parameters to
6450 the text file @file{filename}.
6451 Each string except the last one is followed by one space.
6452 The last string is followed by a newline.
6455 @deffn Command cat filename
6456 Reads and displays the text file @file{filename}.
6459 @deffn Command cp src_filename dest_filename
6460 Copies contents from the file @file{src_filename}
6461 into @file{dest_filename}.
6465 @emph{No description provided.}
6469 @emph{No description provided.}
6473 @emph{No description provided.}
6476 @deffn Command meminfo
6477 Display available RAM memory on OpenOCD host.
6478 Used in OpenOCD regression testing scripts.
6482 @emph{No description provided.}
6486 @emph{No description provided.}
6489 @deffn Command rm filename
6490 @c "rm" has both normal and Jim-level versions??
6491 Unlinks the file @file{filename}.
6494 @deffn Command trunc filename
6495 Removes all data in the file @file{filename}.
6498 @anchor{memoryaccess}
6499 @section Memory access commands
6500 @cindex memory access
6502 These commands allow accesses of a specific size to the memory
6503 system. Often these are used to configure the current target in some
6504 special way. For example - one may need to write certain values to the
6505 SDRAM controller to enable SDRAM.
6508 @item Use the @command{targets} (plural) command
6509 to change the current target.
6510 @item In system level scripts these commands are deprecated.
6511 Please use their TARGET object siblings to avoid making assumptions
6512 about what TAP is the current target, or about MMU configuration.
6515 @deffn Command mdw [phys] addr [count]
6516 @deffnx Command mdh [phys] addr [count]
6517 @deffnx Command mdb [phys] addr [count]
6518 Display contents of address @var{addr}, as
6519 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
6520 or 8-bit bytes (@command{mdb}).
6521 When the current target has an MMU which is present and active,
6522 @var{addr} is interpreted as a virtual address.
6523 Otherwise, or if the optional @var{phys} flag is specified,
6524 @var{addr} is interpreted as a physical address.
6525 If @var{count} is specified, displays that many units.
6526 (If you want to manipulate the data instead of displaying it,
6527 see the @code{mem2array} primitives.)
6530 @deffn Command mww [phys] addr word
6531 @deffnx Command mwh [phys] addr halfword
6532 @deffnx Command mwb [phys] addr byte
6533 Writes the specified @var{word} (32 bits),
6534 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
6535 at the specified address @var{addr}.
6536 When the current target has an MMU which is present and active,
6537 @var{addr} is interpreted as a virtual address.
6538 Otherwise, or if the optional @var{phys} flag is specified,
6539 @var{addr} is interpreted as a physical address.
6542 @anchor{imageaccess}
6543 @section Image loading commands
6544 @cindex image loading
6545 @cindex image dumping
6547 @deffn Command {dump_image} filename address size
6548 Dump @var{size} bytes of target memory starting at @var{address} to the
6549 binary file named @var{filename}.
6552 @deffn Command {fast_load}
6553 Loads an image stored in memory by @command{fast_load_image} to the
6554 current target. Must be preceeded by fast_load_image.
6557 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
6558 Normally you should be using @command{load_image} or GDB load. However, for
6559 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
6560 host), storing the image in memory and uploading the image to the target
6561 can be a way to upload e.g. multiple debug sessions when the binary does not change.
6562 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
6563 memory, i.e. does not affect target. This approach is also useful when profiling
6564 target programming performance as I/O and target programming can easily be profiled
6568 @deffn Command {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
6569 Load image from file @var{filename} to target memory offset by @var{address} from its load address.
6570 The file format may optionally be specified
6571 (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
6572 In addition the following arguments may be specifed:
6573 @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
6574 @var{max_length} - maximum number of bytes to load.
6576 proc load_image_bin @{fname foffset address length @} @{
6577 # Load data from fname filename at foffset offset to
6578 # target at address. Load at most length bytes.
6579 load_image $fname [expr $address - $foffset] bin $address $length
6584 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
6585 Displays image section sizes and addresses
6586 as if @var{filename} were loaded into target memory
6587 starting at @var{address} (defaults to zero).
6588 The file format may optionally be specified
6589 (@option{bin}, @option{ihex}, or @option{elf})
6592 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
6593 Verify @var{filename} against target memory starting at @var{address}.
6594 The file format may optionally be specified
6595 (@option{bin}, @option{ihex}, or @option{elf})
6596 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
6600 @section Breakpoint and Watchpoint commands
6604 CPUs often make debug modules accessible through JTAG, with
6605 hardware support for a handful of code breakpoints and data
6607 In addition, CPUs almost always support software breakpoints.
6609 @deffn Command {bp} [address len [@option{hw}]]
6610 With no parameters, lists all active breakpoints.
6611 Else sets a breakpoint on code execution starting
6612 at @var{address} for @var{length} bytes.
6613 This is a software breakpoint, unless @option{hw} is specified
6614 in which case it will be a hardware breakpoint.
6616 (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
6617 for similar mechanisms that do not consume hardware breakpoints.)
6620 @deffn Command {rbp} address
6621 Remove the breakpoint at @var{address}.
6624 @deffn Command {rwp} address
6625 Remove data watchpoint on @var{address}
6628 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
6629 With no parameters, lists all active watchpoints.
6630 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
6631 The watch point is an "access" watchpoint unless
6632 the @option{r} or @option{w} parameter is provided,
6633 defining it as respectively a read or write watchpoint.
6634 If a @var{value} is provided, that value is used when determining if
6635 the watchpoint should trigger. The value may be first be masked
6636 using @var{mask} to mark ``don't care'' fields.
6639 @section Misc Commands
6642 @deffn Command {profile} seconds filename
6643 Profiling samples the CPU's program counter as quickly as possible,
6644 which is useful for non-intrusive stochastic profiling.
6645 Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
6648 @deffn Command {version}
6649 Displays a string identifying the version of this OpenOCD server.
6652 @deffn Command {virt2phys} virtual_address
6653 Requests the current target to map the specified @var{virtual_address}
6654 to its corresponding physical address, and displays the result.
6657 @node Architecture and Core Commands
6658 @chapter Architecture and Core Commands
6659 @cindex Architecture Specific Commands
6660 @cindex Core Specific Commands
6662 Most CPUs have specialized JTAG operations to support debugging.
6663 OpenOCD packages most such operations in its standard command framework.
6664 Some of those operations don't fit well in that framework, so they are
6665 exposed here as architecture or implementation (core) specific commands.
6667 @anchor{armhardwaretracing}
6668 @section ARM Hardware Tracing
6673 CPUs based on ARM cores may include standard tracing interfaces,
6674 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
6675 address and data bus trace records to a ``Trace Port''.
6679 Development-oriented boards will sometimes provide a high speed
6680 trace connector for collecting that data, when the particular CPU
6681 supports such an interface.
6682 (The standard connector is a 38-pin Mictor, with both JTAG
6683 and trace port support.)
6684 Those trace connectors are supported by higher end JTAG adapters
6685 and some logic analyzer modules; frequently those modules can
6686 buffer several megabytes of trace data.
6687 Configuring an ETM coupled to such an external trace port belongs
6688 in the board-specific configuration file.
6690 If the CPU doesn't provide an external interface, it probably
6691 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
6692 dedicated SRAM. 4KBytes is one common ETB size.
6693 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
6694 (target) configuration file, since it works the same on all boards.
6697 ETM support in OpenOCD doesn't seem to be widely used yet.
6700 ETM support may be buggy, and at least some @command{etm config}
6701 parameters should be detected by asking the ETM for them.
6703 ETM trigger events could also implement a kind of complex
6704 hardware breakpoint, much more powerful than the simple
6705 watchpoint hardware exported by EmbeddedICE modules.
6706 @emph{Such breakpoints can be triggered even when using the
6707 dummy trace port driver}.
6709 It seems like a GDB hookup should be possible,
6710 as well as tracing only during specific states
6711 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
6713 There should be GUI tools to manipulate saved trace data and help
6714 analyse it in conjunction with the source code.
6715 It's unclear how much of a common interface is shared
6716 with the current XScale trace support, or should be
6717 shared with eventual Nexus-style trace module support.
6719 At this writing (November 2009) only ARM7, ARM9, and ARM11 support
6720 for ETM modules is available. The code should be able to
6721 work with some newer cores; but not all of them support
6722 this original style of JTAG access.
6725 @subsection ETM Configuration
6726 ETM setup is coupled with the trace port driver configuration.
6728 @deffn {Config Command} {etm config} target width mode clocking driver
6729 Declares the ETM associated with @var{target}, and associates it
6730 with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
6732 Several of the parameters must reflect the trace port capabilities,
6733 which are a function of silicon capabilties (exposed later
6734 using @command{etm info}) and of what hardware is connected to
6735 that port (such as an external pod, or ETB).
6736 The @var{width} must be either 4, 8, or 16,
6737 except with ETMv3.0 and newer modules which may also
6738 support 1, 2, 24, 32, 48, and 64 bit widths.
6739 (With those versions, @command{etm info} also shows whether
6740 the selected port width and mode are supported.)
6742 The @var{mode} must be @option{normal}, @option{multiplexed},
6743 or @option{demultiplexed}.
6744 The @var{clocking} must be @option{half} or @option{full}.
6747 With ETMv3.0 and newer, the bits set with the @var{mode} and
6748 @var{clocking} parameters both control the mode.
6749 This modified mode does not map to the values supported by
6750 previous ETM modules, so this syntax is subject to change.
6754 You can see the ETM registers using the @command{reg} command.
6755 Not all possible registers are present in every ETM.
6756 Most of the registers are write-only, and are used to configure
6757 what CPU activities are traced.
6761 @deffn Command {etm info}
6762 Displays information about the current target's ETM.
6763 This includes resource counts from the @code{ETM_CONFIG} register,
6764 as well as silicon capabilities (except on rather old modules).
6765 from the @code{ETM_SYS_CONFIG} register.
6768 @deffn Command {etm status}
6769 Displays status of the current target's ETM and trace port driver:
6770 is the ETM idle, or is it collecting data?
6771 Did trace data overflow?
6775 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
6776 Displays what data that ETM will collect.
6777 If arguments are provided, first configures that data.
6778 When the configuration changes, tracing is stopped
6779 and any buffered trace data is invalidated.
6782 @item @var{type} ... describing how data accesses are traced,
6783 when they pass any ViewData filtering that that was set up.
6785 @option{none} (save nothing),
6786 @option{data} (save data),
6787 @option{address} (save addresses),
6788 @option{all} (save data and addresses)
6789 @item @var{context_id_bits} ... 0, 8, 16, or 32
6790 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
6791 cycle-accurate instruction tracing.
6792 Before ETMv3, enabling this causes much extra data to be recorded.
6793 @item @var{branch_output} ... @option{enable} or @option{disable}.
6794 Disable this unless you need to try reconstructing the instruction
6795 trace stream without an image of the code.
6799 @deffn Command {etm trigger_debug} (@option{enable}|@option{disable})
6800 Displays whether ETM triggering debug entry (like a breakpoint) is
6801 enabled or disabled, after optionally modifying that configuration.
6802 The default behaviour is @option{disable}.
6803 Any change takes effect after the next @command{etm start}.
6805 By using script commands to configure ETM registers, you can make the
6806 processor enter debug state automatically when certain conditions,
6807 more complex than supported by the breakpoint hardware, happen.
6810 @subsection ETM Trace Operation
6812 After setting up the ETM, you can use it to collect data.
6813 That data can be exported to files for later analysis.
6814 It can also be parsed with OpenOCD, for basic sanity checking.
6816 To configure what is being traced, you will need to write
6817 various trace registers using @command{reg ETM_*} commands.
6818 For the definitions of these registers, read ARM publication
6819 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
6820 Be aware that most of the relevant registers are write-only,
6821 and that ETM resources are limited. There are only a handful
6822 of address comparators, data comparators, counters, and so on.
6824 Examples of scenarios you might arrange to trace include:
6827 @item Code flow within a function, @emph{excluding} subroutines
6828 it calls. Use address range comparators to enable tracing
6829 for instruction access within that function's body.
6830 @item Code flow within a function, @emph{including} subroutines
6831 it calls. Use the sequencer and address comparators to activate
6832 tracing on an ``entered function'' state, then deactivate it by
6833 exiting that state when the function's exit code is invoked.
6834 @item Code flow starting at the fifth invocation of a function,
6835 combining one of the above models with a counter.
6836 @item CPU data accesses to the registers for a particular device,
6837 using address range comparators and the ViewData logic.
6838 @item Such data accesses only during IRQ handling, combining the above
6839 model with sequencer triggers which on entry and exit to the IRQ handler.
6840 @item @emph{... more}
6843 At this writing, September 2009, there are no Tcl utility
6844 procedures to help set up any common tracing scenarios.
6846 @deffn Command {etm analyze}
6847 Reads trace data into memory, if it wasn't already present.
6848 Decodes and prints the data that was collected.
6851 @deffn Command {etm dump} filename
6852 Stores the captured trace data in @file{filename}.
6855 @deffn Command {etm image} filename [base_address] [type]
6856 Opens an image file.
6859 @deffn Command {etm load} filename
6860 Loads captured trace data from @file{filename}.
6863 @deffn Command {etm start}
6864 Starts trace data collection.
6867 @deffn Command {etm stop}
6868 Stops trace data collection.
6871 @anchor{traceportdrivers}
6872 @subsection Trace Port Drivers
6874 To use an ETM trace port it must be associated with a driver.
6876 @deffn {Trace Port Driver} dummy
6877 Use the @option{dummy} driver if you are configuring an ETM that's
6878 not connected to anything (on-chip ETB or off-chip trace connector).
6879 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
6880 any trace data collection.}
6881 @deffn {Config Command} {etm_dummy config} target
6882 Associates the ETM for @var{target} with a dummy driver.
6886 @deffn {Trace Port Driver} etb
6887 Use the @option{etb} driver if you are configuring an ETM
6888 to use on-chip ETB memory.
6889 @deffn {Config Command} {etb config} target etb_tap
6890 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
6891 You can see the ETB registers using the @command{reg} command.
6893 @deffn Command {etb trigger_percent} [percent]
6894 This displays, or optionally changes, ETB behavior after the
6895 ETM's configured @emph{trigger} event fires.
6896 It controls how much more trace data is saved after the (single)
6897 trace trigger becomes active.
6900 @item The default corresponds to @emph{trace around} usage,
6901 recording 50 percent data before the event and the rest
6903 @item The minimum value of @var{percent} is 2 percent,
6904 recording almost exclusively data before the trigger.
6905 Such extreme @emph{trace before} usage can help figure out
6906 what caused that event to happen.
6907 @item The maximum value of @var{percent} is 100 percent,
6908 recording data almost exclusively after the event.
6909 This extreme @emph{trace after} usage might help sort out
6910 how the event caused trouble.
6912 @c REVISIT allow "break" too -- enter debug mode.
6917 @deffn {Trace Port Driver} oocd_trace
6918 This driver isn't available unless OpenOCD was explicitly configured
6919 with the @option{--enable-oocd_trace} option. You probably don't want
6920 to configure it unless you've built the appropriate prototype hardware;
6921 it's @emph{proof-of-concept} software.
6923 Use the @option{oocd_trace} driver if you are configuring an ETM that's
6924 connected to an off-chip trace connector.
6926 @deffn {Config Command} {oocd_trace config} target tty
6927 Associates the ETM for @var{target} with a trace driver which
6928 collects data through the serial port @var{tty}.
6931 @deffn Command {oocd_trace resync}
6932 Re-synchronizes with the capture clock.
6935 @deffn Command {oocd_trace status}
6936 Reports whether the capture clock is locked or not.
6941 @section Generic ARM
6944 These commands should be available on all ARM processors.
6945 They are available in addition to other core-specific
6946 commands that may be available.
6948 @deffn Command {arm core_state} [@option{arm}|@option{thumb}]
6949 Displays the core_state, optionally changing it to process
6950 either @option{arm} or @option{thumb} instructions.
6951 The target may later be resumed in the currently set core_state.
6952 (Processors may also support the Jazelle state, but
6953 that is not currently supported in OpenOCD.)
6956 @deffn Command {arm disassemble} address [count [@option{thumb}]]
6958 Disassembles @var{count} instructions starting at @var{address}.
6959 If @var{count} is not specified, a single instruction is disassembled.
6960 If @option{thumb} is specified, or the low bit of the address is set,
6961 Thumb2 (mixed 16/32-bit) instructions are used;
6962 else ARM (32-bit) instructions are used.
6963 (Processors may also support the Jazelle state, but
6964 those instructions are not currently understood by OpenOCD.)
6966 Note that all Thumb instructions are Thumb2 instructions,
6967 so older processors (without Thumb2 support) will still
6968 see correct disassembly of Thumb code.
6969 Also, ThumbEE opcodes are the same as Thumb2,
6970 with a handful of exceptions.
6971 ThumbEE disassembly currently has no explicit support.
6974 @deffn Command {arm mcr} pX op1 CRn CRm op2 value
6975 Write @var{value} to a coprocessor @var{pX} register
6976 passing parameters @var{CRn},
6977 @var{CRm}, opcodes @var{opc1} and @var{opc2},
6978 and using the MCR instruction.
6979 (Parameter sequence matches the ARM instruction, but omits
6983 @deffn Command {arm mrc} pX coproc op1 CRn CRm op2
6984 Read a coprocessor @var{pX} register passing parameters @var{CRn},
6985 @var{CRm}, opcodes @var{opc1} and @var{opc2},
6986 and the MRC instruction.
6987 Returns the result so it can be manipulated by Jim scripts.
6988 (Parameter sequence matches the ARM instruction, but omits
6992 @deffn Command {arm reg}
6993 Display a table of all banked core registers, fetching the current value from every
6994 core mode if necessary.
6997 @deffn Command {arm semihosting} [@option{enable}|@option{disable}]
6998 @cindex ARM semihosting
6999 Display status of semihosting, after optionally changing that status.
7001 Semihosting allows for code executing on an ARM target to use the
7002 I/O facilities on the host computer i.e. the system where OpenOCD
7003 is running. The target application must be linked against a library
7004 implementing the ARM semihosting convention that forwards operation
7005 requests by using a special SVC instruction that is trapped at the
7006 Supervisor Call vector by OpenOCD.
7009 @section ARMv4 and ARMv5 Architecture
7013 The ARMv4 and ARMv5 architectures are widely used in embedded systems,
7014 and introduced core parts of the instruction set in use today.
7015 That includes the Thumb instruction set, introduced in the ARMv4T
7018 @subsection ARM7 and ARM9 specific commands
7022 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
7023 ARM9TDMI, ARM920T or ARM926EJ-S.
7024 They are available in addition to the ARM commands,
7025 and any other core-specific commands that may be available.
7027 @deffn Command {arm7_9 dbgrq} [@option{enable}|@option{disable}]
7028 Displays the value of the flag controlling use of the
7029 the EmbeddedIce DBGRQ signal to force entry into debug mode,
7030 instead of breakpoints.
7031 If a boolean parameter is provided, first assigns that flag.
7034 safe for all but ARM7TDMI-S cores (like NXP LPC).
7035 This feature is enabled by default on most ARM9 cores,
7036 including ARM9TDMI, ARM920T, and ARM926EJ-S.
7039 @deffn Command {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
7041 Displays the value of the flag controlling use of the debug communications
7042 channel (DCC) to write larger (>128 byte) amounts of memory.
7043 If a boolean parameter is provided, first assigns that flag.
7045 DCC downloads offer a huge speed increase, but might be
7046 unsafe, especially with targets running at very low speeds. This command was introduced
7047 with OpenOCD rev. 60, and requires a few bytes of working area.
7050 @deffn Command {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
7051 Displays the value of the flag controlling use of memory writes and reads
7052 that don't check completion of the operation.
7053 If a boolean parameter is provided, first assigns that flag.
7055 This provides a huge speed increase, especially with USB JTAG
7056 cables (FT2232), but might be unsafe if used with targets running at very low
7057 speeds, like the 32kHz startup clock of an AT91RM9200.
7060 @subsection ARM720T specific commands
7063 These commands are available to ARM720T based CPUs,
7064 which are implementations of the ARMv4T architecture
7065 based on the ARM7TDMI-S integer core.
7066 They are available in addition to the ARM and ARM7/ARM9 commands.
7068 @deffn Command {arm720t cp15} opcode [value]
7069 @emph{DEPRECATED -- avoid using this.
7070 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
7072 Display cp15 register returned by the ARM instruction @var{opcode};
7073 else if a @var{value} is provided, that value is written to that register.
7074 The @var{opcode} should be the value of either an MRC or MCR instruction.
7077 @subsection ARM9 specific commands
7080 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
7082 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
7084 @c 9-june-2009: tried this on arm920t, it didn't work.
7085 @c no-params always lists nothing caught, and that's how it acts.
7086 @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
7087 @c versions have different rules about when they commit writes.
7089 @anchor{arm9vectorcatch}
7090 @deffn Command {arm9 vector_catch} [@option{all}|@option{none}|list]
7091 @cindex vector_catch
7092 Vector Catch hardware provides a sort of dedicated breakpoint
7093 for hardware events such as reset, interrupt, and abort.
7094 You can use this to conserve normal breakpoint resources,
7095 so long as you're not concerned with code that branches directly
7096 to those hardware vectors.
7098 This always finishes by listing the current configuration.
7099 If parameters are provided, it first reconfigures the
7100 vector catch hardware to intercept
7101 @option{all} of the hardware vectors,
7102 @option{none} of them,
7103 or a list with one or more of the following:
7104 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
7105 @option{irq} @option{fiq}.
7108 @subsection ARM920T specific commands
7111 These commands are available to ARM920T based CPUs,
7112 which are implementations of the ARMv4T architecture
7113 built using the ARM9TDMI integer core.
7114 They are available in addition to the ARM, ARM7/ARM9,
7117 @deffn Command {arm920t cache_info}
7118 Print information about the caches found. This allows to see whether your target
7119 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
7122 @deffn Command {arm920t cp15} regnum [value]
7123 Display cp15 register @var{regnum};
7124 else if a @var{value} is provided, that value is written to that register.
7125 This uses "physical access" and the register number is as
7126 shown in bits 38..33 of table 9-9 in the ARM920T TRM.
7127 (Not all registers can be written.)
7130 @deffn Command {arm920t cp15i} opcode [value [address]]
7131 @emph{DEPRECATED -- avoid using this.
7132 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
7134 Interpreted access using ARM instruction @var{opcode}, which should
7135 be the value of either an MRC or MCR instruction
7136 (as shown tables 9-11, 9-12, and 9-13 in the ARM920T TRM).
7137 If no @var{value} is provided, the result is displayed.
7138 Else if that value is written using the specified @var{address},
7139 or using zero if no other address is provided.
7142 @deffn Command {arm920t read_cache} filename
7143 Dump the content of ICache and DCache to a file named @file{filename}.
7146 @deffn Command {arm920t read_mmu} filename
7147 Dump the content of the ITLB and DTLB to a file named @file{filename}.
7150 @subsection ARM926ej-s specific commands
7153 These commands are available to ARM926ej-s based CPUs,
7154 which are implementations of the ARMv5TEJ architecture
7155 based on the ARM9EJ-S integer core.
7156 They are available in addition to the ARM, ARM7/ARM9,
7159 The Feroceon cores also support these commands, although
7160 they are not built from ARM926ej-s designs.
7162 @deffn Command {arm926ejs cache_info}
7163 Print information about the caches found.
7166 @subsection ARM966E specific commands
7169 These commands are available to ARM966 based CPUs,
7170 which are implementations of the ARMv5TE architecture.
7171 They are available in addition to the ARM, ARM7/ARM9,
7174 @deffn Command {arm966e cp15} regnum [value]
7175 Display cp15 register @var{regnum};
7176 else if a @var{value} is provided, that value is written to that register.
7177 The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
7179 There is no current control over bits 31..30 from that table,
7180 as required for BIST support.
7183 @subsection XScale specific commands
7186 Some notes about the debug implementation on the XScale CPUs:
7188 The XScale CPU provides a special debug-only mini-instruction cache
7189 (mini-IC) in which exception vectors and target-resident debug handler
7190 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
7191 must point vector 0 (the reset vector) to the entry of the debug
7192 handler. However, this means that the complete first cacheline in the
7193 mini-IC is marked valid, which makes the CPU fetch all exception
7194 handlers from the mini-IC, ignoring the code in RAM.
7196 To address this situation, OpenOCD provides the @code{xscale
7197 vector_table} command, which allows the user to explicity write
7198 individual entries to either the high or low vector table stored in
7201 It is recommended to place a pc-relative indirect branch in the vector
7202 table, and put the branch destination somewhere in memory. Doing so
7203 makes sure the code in the vector table stays constant regardless of
7204 code layout in memory:
7207 ldr pc,[pc,#0x100-8]
7208 ldr pc,[pc,#0x100-8]
7209 ldr pc,[pc,#0x100-8]
7210 ldr pc,[pc,#0x100-8]
7211 ldr pc,[pc,#0x100-8]
7212 ldr pc,[pc,#0x100-8]
7213 ldr pc,[pc,#0x100-8]
7214 ldr pc,[pc,#0x100-8]
7216 .long real_reset_vector
7217 .long real_ui_handler
7218 .long real_swi_handler
7220 .long real_data_abort
7221 .long 0 /* unused */
7222 .long real_irq_handler
7223 .long real_fiq_handler
7226 Alternatively, you may choose to keep some or all of the mini-IC
7227 vector table entries synced with those written to memory by your
7228 system software. The mini-IC can not be modified while the processor
7229 is executing, but for each vector table entry not previously defined
7230 using the @code{xscale vector_table} command, OpenOCD will copy the
7231 value from memory to the mini-IC every time execution resumes from a
7232 halt. This is done for both high and low vector tables (although the
7233 table not in use may not be mapped to valid memory, and in this case
7234 that copy operation will silently fail). This means that you will
7235 need to briefly halt execution at some strategic point during system
7236 start-up; e.g., after the software has initialized the vector table,
7237 but before exceptions are enabled. A breakpoint can be used to
7238 accomplish this once the appropriate location in the start-up code has
7239 been identified. A watchpoint over the vector table region is helpful
7240 in finding the location if you're not sure. Note that the same
7241 situation exists any time the vector table is modified by the system
7244 The debug handler must be placed somewhere in the address space using
7245 the @code{xscale debug_handler} command. The allowed locations for the
7246 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
7247 0xfffff800). The default value is 0xfe000800.
7249 XScale has resources to support two hardware breakpoints and two
7250 watchpoints. However, the following restrictions on watchpoint
7251 functionality apply: (1) the value and mask arguments to the @code{wp}
7252 command are not supported, (2) the watchpoint length must be a
7253 power of two and not less than four, and can not be greater than the
7254 watchpoint address, and (3) a watchpoint with a length greater than
7255 four consumes all the watchpoint hardware resources. This means that
7256 at any one time, you can have enabled either two watchpoints with a
7257 length of four, or one watchpoint with a length greater than four.
7259 These commands are available to XScale based CPUs,
7260 which are implementations of the ARMv5TE architecture.
7262 @deffn Command {xscale analyze_trace}
7263 Displays the contents of the trace buffer.
7266 @deffn Command {xscale cache_clean_address} address
7267 Changes the address used when cleaning the data cache.
7270 @deffn Command {xscale cache_info}
7271 Displays information about the CPU caches.
7274 @deffn Command {xscale cp15} regnum [value]
7275 Display cp15 register @var{regnum};
7276 else if a @var{value} is provided, that value is written to that register.
7279 @deffn Command {xscale debug_handler} target address
7280 Changes the address used for the specified target's debug handler.
7283 @deffn Command {xscale dcache} [@option{enable}|@option{disable}]
7284 Enables or disable the CPU's data cache.
7287 @deffn Command {xscale dump_trace} filename
7288 Dumps the raw contents of the trace buffer to @file{filename}.
7291 @deffn Command {xscale icache} [@option{enable}|@option{disable}]
7292 Enables or disable the CPU's instruction cache.
7295 @deffn Command {xscale mmu} [@option{enable}|@option{disable}]
7296 Enables or disable the CPU's memory management unit.
7299 @deffn Command {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
7300 Displays the trace buffer status, after optionally
7301 enabling or disabling the trace buffer
7302 and modifying how it is emptied.
7305 @deffn Command {xscale trace_image} filename [offset [type]]
7306 Opens a trace image from @file{filename}, optionally rebasing
7307 its segment addresses by @var{offset}.
7308 The image @var{type} may be one of
7309 @option{bin} (binary), @option{ihex} (Intel hex),
7310 @option{elf} (ELF file), @option{s19} (Motorola s19),
7311 @option{mem}, or @option{builder}.
7314 @anchor{xscalevectorcatch}
7315 @deffn Command {xscale vector_catch} [mask]
7316 @cindex vector_catch
7317 Display a bitmask showing the hardware vectors to catch.
7318 If the optional parameter is provided, first set the bitmask to that value.
7320 The mask bits correspond with bit 16..23 in the DCSR:
7323 0x02 Trap Undefined Instructions
7324 0x04 Trap Software Interrupt
7325 0x08 Trap Prefetch Abort
7326 0x10 Trap Data Abort
7333 @deffn Command {xscale vector_table} [(@option{low}|@option{high}) index value]
7334 @cindex vector_table
7336 Set an entry in the mini-IC vector table. There are two tables: one for
7337 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
7338 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
7339 points to the debug handler entry and can not be overwritten.
7340 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
7342 Without arguments, the current settings are displayed.
7346 @section ARMv6 Architecture
7349 @subsection ARM11 specific commands
7352 @deffn Command {arm11 memwrite burst} [@option{enable}|@option{disable}]
7353 Displays the value of the memwrite burst-enable flag,
7354 which is enabled by default.
7355 If a boolean parameter is provided, first assigns that flag.
7356 Burst writes are only used for memory writes larger than 1 word.
7357 They improve performance by assuming that the CPU has read each data
7358 word over JTAG and completed its write before the next word arrives,
7359 instead of polling for a status flag to verify that completion.
7360 This is usually safe, because JTAG runs much slower than the CPU.
7363 @deffn Command {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
7364 Displays the value of the memwrite error_fatal flag,
7365 which is enabled by default.
7366 If a boolean parameter is provided, first assigns that flag.
7367 When set, certain memory write errors cause earlier transfer termination.
7370 @deffn Command {arm11 step_irq_enable} [@option{enable}|@option{disable}]
7371 Displays the value of the flag controlling whether
7372 IRQs are enabled during single stepping;
7373 they are disabled by default.
7374 If a boolean parameter is provided, first assigns that.
7377 @deffn Command {arm11 vcr} [value]
7378 @cindex vector_catch
7379 Displays the value of the @emph{Vector Catch Register (VCR)},
7380 coprocessor 14 register 7.
7381 If @var{value} is defined, first assigns that.
7383 Vector Catch hardware provides dedicated breakpoints
7384 for certain hardware events.
7385 The specific bit values are core-specific (as in fact is using
7386 coprocessor 14 register 7 itself) but all current ARM11
7387 cores @emph{except the ARM1176} use the same six bits.
7390 @section ARMv7 Architecture
7393 @subsection ARMv7 Debug Access Port (DAP) specific commands
7394 @cindex Debug Access Port
7396 These commands are specific to ARM architecture v7 Debug Access Port (DAP),
7397 included on Cortex-M and Cortex-A systems.
7398 They are available in addition to other core-specific commands that may be available.
7400 @deffn Command {dap apid} [num]
7401 Displays ID register from AP @var{num},
7402 defaulting to the currently selected AP.
7405 @deffn Command {dap apsel} [num]
7406 Select AP @var{num}, defaulting to 0.
7409 @deffn Command {dap baseaddr} [num]
7410 Displays debug base address from MEM-AP @var{num},
7411 defaulting to the currently selected AP.
7414 @deffn Command {dap info} [num]
7415 Displays the ROM table for MEM-AP @var{num},
7416 defaulting to the currently selected AP.
7419 @deffn Command {dap memaccess} [value]
7420 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
7421 memory bus access [0-255], giving additional time to respond to reads.
7422 If @var{value} is defined, first assigns that.
7425 @deffn Command {dap apcsw} [0 / 1]
7426 fix CSW_SPROT from register AP_REG_CSW on selected dap.
7430 @subsection Cortex-M specific commands
7433 @deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off})
7434 Control masking (disabling) interrupts during target step/resume.
7436 The @option{auto} option handles interrupts during stepping a way they get
7437 served but don't disturb the program flow. The step command first allows
7438 pending interrupt handlers to execute, then disables interrupts and steps over
7439 the next instruction where the core was halted. After the step interrupts
7440 are enabled again. If the interrupt handlers don't complete within 500ms,
7441 the step command leaves with the core running.
7443 Note that a free breakpoint is required for the @option{auto} option. If no
7444 breakpoint is available at the time of the step, then the step is taken
7445 with interrupts enabled, i.e. the same way the @option{off} option does.
7447 Default is @option{auto}.
7450 @deffn Command {cortex_m vector_catch} [@option{all}|@option{none}|list]
7451 @cindex vector_catch
7452 Vector Catch hardware provides dedicated breakpoints
7453 for certain hardware events.
7455 Parameters request interception of
7456 @option{all} of these hardware event vectors,
7457 @option{none} of them,
7458 or one or more of the following:
7459 @option{hard_err} for a HardFault exception;
7460 @option{mm_err} for a MemManage exception;
7461 @option{bus_err} for a BusFault exception;
7464 @option{chk_err}, or
7465 @option{nocp_err} for various UsageFault exceptions; or
7467 If NVIC setup code does not enable them,
7468 MemManage, BusFault, and UsageFault exceptions
7469 are mapped to HardFault.
7470 UsageFault checks for
7471 divide-by-zero and unaligned access
7472 must also be explicitly enabled.
7474 This finishes by listing the current vector catch configuration.
7477 @deffn Command {cortex_m reset_config} (@option{srst}|@option{sysresetreq}|@option{vectreset})
7478 Control reset handling. The default @option{srst} is to use srst if fitted,
7479 otherwise fallback to @option{vectreset}.
7481 @item @option{srst} use hardware srst if fitted otherwise fallback to @option{vectreset}.
7482 @item @option{sysresetreq} use NVIC SYSRESETREQ to reset system.
7483 @item @option{vectreset} use NVIC VECTRESET to reset system.
7485 Using @option{vectreset} is a safe option for all current Cortex-M cores.
7486 This however has the disadvantage of only resetting the core, all peripherals
7487 are uneffected. A solution would be to use a @code{reset-init} event handler to manually reset
7489 @xref{targetevents,,Target Events}.
7492 @anchor{softwaredebugmessagesandtracing}
7493 @section Software Debug Messages and Tracing
7494 @cindex Linux-ARM DCC support
7498 OpenOCD can process certain requests from target software, when
7499 the target uses appropriate libraries.
7500 The most powerful mechanism is semihosting, but there is also
7501 a lighter weight mechanism using only the DCC channel.
7503 Currently @command{target_request debugmsgs}
7504 is supported only for @option{arm7_9} and @option{cortex_m} cores.
7505 These messages are received as part of target polling, so
7506 you need to have @command{poll on} active to receive them.
7507 They are intrusive in that they will affect program execution
7508 times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
7510 See @file{libdcc} in the contrib dir for more details.
7511 In addition to sending strings, characters, and
7512 arrays of various size integers from the target,
7513 @file{libdcc} also exports a software trace point mechanism.
7514 The target being debugged may
7515 issue trace messages which include a 24-bit @dfn{trace point} number.
7516 Trace point support includes two distinct mechanisms,
7517 each supported by a command:
7520 @item @emph{History} ... A circular buffer of trace points
7521 can be set up, and then displayed at any time.
7522 This tracks where code has been, which can be invaluable in
7523 finding out how some fault was triggered.
7525 The buffer may overflow, since it collects records continuously.
7526 It may be useful to use some of the 24 bits to represent a
7527 particular event, and other bits to hold data.
7529 @item @emph{Counting} ... An array of counters can be set up,
7530 and then displayed at any time.
7531 This can help establish code coverage and identify hot spots.
7533 The array of counters is directly indexed by the trace point
7534 number, so trace points with higher numbers are not counted.
7537 Linux-ARM kernels have a ``Kernel low-level debugging
7538 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
7539 depends on CONFIG_DEBUG_LL) which uses this mechanism to
7540 deliver messages before a serial console can be activated.
7541 This is not the same format used by @file{libdcc}.
7542 Other software, such as the U-Boot boot loader, sometimes
7543 does the same thing.
7545 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
7546 Displays current handling of target DCC message requests.
7547 These messages may be sent to the debugger while the target is running.
7548 The optional @option{enable} and @option{charmsg} parameters
7549 both enable the messages, while @option{disable} disables them.
7551 With @option{charmsg} the DCC words each contain one character,
7552 as used by Linux with CONFIG_DEBUG_ICEDCC;
7553 otherwise the libdcc format is used.
7556 @deffn Command {trace history} [@option{clear}|count]
7557 With no parameter, displays all the trace points that have triggered
7558 in the order they triggered.
7559 With the parameter @option{clear}, erases all current trace history records.
7560 With a @var{count} parameter, allocates space for that many
7564 @deffn Command {trace point} [@option{clear}|identifier]
7565 With no parameter, displays all trace point identifiers and how many times
7566 they have been triggered.
7567 With the parameter @option{clear}, erases all current trace point counters.
7568 With a numeric @var{identifier} parameter, creates a new a trace point counter
7569 and associates it with that identifier.
7571 @emph{Important:} The identifier and the trace point number
7572 are not related except by this command.
7573 These trace point numbers always start at zero (from server startup,
7574 or after @command{trace point clear}) and count up from there.
7579 @chapter JTAG Commands
7580 @cindex JTAG Commands
7581 Most general purpose JTAG commands have been presented earlier.
7582 (@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
7583 Lower level JTAG commands, as presented here,
7584 may be needed to work with targets which require special
7585 attention during operations such as reset or initialization.
7587 To use these commands you will need to understand some
7588 of the basics of JTAG, including:
7591 @item A JTAG scan chain consists of a sequence of individual TAP
7592 devices such as a CPUs.
7593 @item Control operations involve moving each TAP through the same
7594 standard state machine (in parallel)
7595 using their shared TMS and clock signals.
7596 @item Data transfer involves shifting data through the chain of
7597 instruction or data registers of each TAP, writing new register values
7598 while the reading previous ones.
7599 @item Data register sizes are a function of the instruction active in
7600 a given TAP, while instruction register sizes are fixed for each TAP.
7601 All TAPs support a BYPASS instruction with a single bit data register.
7602 @item The way OpenOCD differentiates between TAP devices is by
7603 shifting different instructions into (and out of) their instruction
7607 @section Low Level JTAG Commands
7609 These commands are used by developers who need to access
7610 JTAG instruction or data registers, possibly controlling
7611 the order of TAP state transitions.
7612 If you're not debugging OpenOCD internals, or bringing up a
7613 new JTAG adapter or a new type of TAP device (like a CPU or
7614 JTAG router), you probably won't need to use these commands.
7615 In a debug session that doesn't use JTAG for its transport protocol,
7616 these commands are not available.
7618 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
7619 Loads the data register of @var{tap} with a series of bit fields
7620 that specify the entire register.
7621 Each field is @var{numbits} bits long with
7622 a numeric @var{value} (hexadecimal encouraged).
7623 The return value holds the original value of each
7626 For example, a 38 bit number might be specified as one
7627 field of 32 bits then one of 6 bits.
7628 @emph{For portability, never pass fields which are more
7629 than 32 bits long. Many OpenOCD implementations do not
7630 support 64-bit (or larger) integer values.}
7632 All TAPs other than @var{tap} must be in BYPASS mode.
7633 The single bit in their data registers does not matter.
7635 When @var{tap_state} is specified, the JTAG state machine is left
7637 For example @sc{drpause} might be specified, so that more
7638 instructions can be issued before re-entering the @sc{run/idle} state.
7639 If the end state is not specified, the @sc{run/idle} state is entered.
7642 OpenOCD does not record information about data register lengths,
7643 so @emph{it is important that you get the bit field lengths right}.
7644 Remember that different JTAG instructions refer to different
7645 data registers, which may have different lengths.
7646 Moreover, those lengths may not be fixed;
7647 the SCAN_N instruction can change the length of
7648 the register accessed by the INTEST instruction
7649 (by connecting a different scan chain).
7653 @deffn Command {flush_count}
7654 Returns the number of times the JTAG queue has been flushed.
7655 This may be used for performance tuning.
7657 For example, flushing a queue over USB involves a
7658 minimum latency, often several milliseconds, which does
7659 not change with the amount of data which is written.
7660 You may be able to identify performance problems by finding
7661 tasks which waste bandwidth by flushing small transfers too often,
7662 instead of batching them into larger operations.
7665 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
7666 For each @var{tap} listed, loads the instruction register
7667 with its associated numeric @var{instruction}.
7668 (The number of bits in that instruction may be displayed
7669 using the @command{scan_chain} command.)
7670 For other TAPs, a BYPASS instruction is loaded.
7672 When @var{tap_state} is specified, the JTAG state machine is left
7674 For example @sc{irpause} might be specified, so the data register
7675 can be loaded before re-entering the @sc{run/idle} state.
7676 If the end state is not specified, the @sc{run/idle} state is entered.
7679 OpenOCD currently supports only a single field for instruction
7680 register values, unlike data register values.
7681 For TAPs where the instruction register length is more than 32 bits,
7682 portable scripts currently must issue only BYPASS instructions.
7686 @deffn Command {jtag_reset} trst srst
7687 Set values of reset signals.
7688 The @var{trst} and @var{srst} parameter values may be
7689 @option{0}, indicating that reset is inactive (pulled or driven high),
7690 or @option{1}, indicating it is active (pulled or driven low).
7691 The @command{reset_config} command should already have been used
7692 to configure how the board and JTAG adapter treat these two
7693 signals, and to say if either signal is even present.
7694 @xref{Reset Configuration}.
7696 Note that TRST is specially handled.
7697 It actually signifies JTAG's @sc{reset} state.
7698 So if the board doesn't support the optional TRST signal,
7699 or it doesn't support it along with the specified SRST value,
7700 JTAG reset is triggered with TMS and TCK signals
7701 instead of the TRST signal.
7702 And no matter how that JTAG reset is triggered, once
7703 the scan chain enters @sc{reset} with TRST inactive,
7704 TAP @code{post-reset} events are delivered to all TAPs
7705 with handlers for that event.
7708 @deffn Command {pathmove} start_state [next_state ...]
7709 Start by moving to @var{start_state}, which
7710 must be one of the @emph{stable} states.
7711 Unless it is the only state given, this will often be the
7712 current state, so that no TCK transitions are needed.
7713 Then, in a series of single state transitions
7714 (conforming to the JTAG state machine) shift to
7715 each @var{next_state} in sequence, one per TCK cycle.
7716 The final state must also be stable.
7719 @deffn Command {runtest} @var{num_cycles}
7720 Move to the @sc{run/idle} state, and execute at least
7721 @var{num_cycles} of the JTAG clock (TCK).
7722 Instructions often need some time
7723 to execute before they take effect.
7726 @c tms_sequence (short|long)
7727 @c ... temporary, debug-only, other than USBprog bug workaround...
7729 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
7730 Verify values captured during @sc{ircapture} and returned
7731 during IR scans. Default is enabled, but this can be
7732 overridden by @command{verify_jtag}.
7733 This flag is ignored when validating JTAG chain configuration.
7736 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
7737 Enables verification of DR and IR scans, to help detect
7738 programming errors. For IR scans, @command{verify_ircapture}
7739 must also be enabled.
7743 @section TAP state names
7744 @cindex TAP state names
7746 The @var{tap_state} names used by OpenOCD in the @command{drscan},
7747 @command{irscan}, and @command{pathmove} commands are the same
7748 as those used in SVF boundary scan documents, except that
7749 SVF uses @sc{idle} instead of @sc{run/idle}.
7752 @item @b{RESET} ... @emph{stable} (with TMS high);
7753 acts as if TRST were pulsed
7754 @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
7757 @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
7758 through the data register
7760 @item @b{DRPAUSE} ... @emph{stable}; data register ready
7761 for update or more shifting
7766 @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
7767 through the instruction register
7769 @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
7770 for update or more shifting
7775 Note that only six of those states are fully ``stable'' in the
7776 face of TMS fixed (low except for @sc{reset})
7777 and a free-running JTAG clock. For all the
7778 others, the next TCK transition changes to a new state.
7781 @item From @sc{drshift} and @sc{irshift}, clock transitions will
7782 produce side effects by changing register contents. The values
7783 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
7784 may not be as expected.
7785 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
7786 choices after @command{drscan} or @command{irscan} commands,
7787 since they are free of JTAG side effects.
7788 @item @sc{run/idle} may have side effects that appear at non-JTAG
7789 levels, such as advancing the ARM9E-S instruction pipeline.
7790 Consult the documentation for the TAP(s) you are working with.
7793 @node Boundary Scan Commands
7794 @chapter Boundary Scan Commands
7796 One of the original purposes of JTAG was to support
7797 boundary scan based hardware testing.
7798 Although its primary focus is to support On-Chip Debugging,
7799 OpenOCD also includes some boundary scan commands.
7801 @section SVF: Serial Vector Format
7802 @cindex Serial Vector Format
7805 The Serial Vector Format, better known as @dfn{SVF}, is a
7806 way to represent JTAG test patterns in text files.
7807 In a debug session using JTAG for its transport protocol,
7808 OpenOCD supports running such test files.
7810 @deffn Command {svf} filename [@option{quiet}]
7811 This issues a JTAG reset (Test-Logic-Reset) and then
7812 runs the SVF script from @file{filename}.
7813 Unless the @option{quiet} option is specified,
7814 each command is logged before it is executed.
7817 @section XSVF: Xilinx Serial Vector Format
7818 @cindex Xilinx Serial Vector Format
7821 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
7822 binary representation of SVF which is optimized for use with
7824 In a debug session using JTAG for its transport protocol,
7825 OpenOCD supports running such test files.
7827 @quotation Important
7828 Not all XSVF commands are supported.
7831 @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
7832 This issues a JTAG reset (Test-Logic-Reset) and then
7833 runs the XSVF script from @file{filename}.
7834 When a @var{tapname} is specified, the commands are directed at
7836 When @option{virt2} is specified, the @sc{xruntest} command counts
7837 are interpreted as TCK cycles instead of microseconds.
7838 Unless the @option{quiet} option is specified,
7839 messages are logged for comments and some retries.
7842 The OpenOCD sources also include two utility scripts
7843 for working with XSVF; they are not currently installed
7844 after building the software.
7845 You may find them useful:
7848 @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
7849 syntax understood by the @command{xsvf} command; see notes below.
7850 @item @emph{xsvfdump} ... converts XSVF files into a text output format;
7851 understands the OpenOCD extensions.
7854 The input format accepts a handful of non-standard extensions.
7855 These include three opcodes corresponding to SVF extensions
7856 from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
7857 two opcodes supporting a more accurate translation of SVF
7858 (XTRST, XWAITSTATE).
7859 If @emph{xsvfdump} shows a file is using those opcodes, it
7860 probably will not be usable with other XSVF tools.
7866 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
7867 be used to access files on PCs (either the developer's PC or some other PC).
7869 The way this works on the ZY1000 is to prefix a filename by
7870 "/tftp/ip/" and append the TFTP path on the TFTP
7871 server (tftpd). For example,
7874 load_image /tftp/10.0.0.96/c:\temp\abc.elf
7877 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
7878 if the file was hosted on the embedded host.
7880 In order to achieve decent performance, you must choose a TFTP server
7881 that supports a packet size bigger than the default packet size (512 bytes). There
7882 are numerous TFTP servers out there (free and commercial) and you will have to do
7883 a bit of googling to find something that fits your requirements.
7885 @node GDB and OpenOCD
7886 @chapter GDB and OpenOCD
7888 OpenOCD complies with the remote gdbserver protocol, and as such can be used
7889 to debug remote targets.
7890 Setting up GDB to work with OpenOCD can involve several components:
7893 @item The OpenOCD server support for GDB may need to be configured.
7894 @xref{gdbconfiguration,,GDB Configuration}.
7895 @item GDB's support for OpenOCD may need configuration,
7896 as shown in this chapter.
7897 @item If you have a GUI environment like Eclipse,
7898 that also will probably need to be configured.
7901 Of course, the version of GDB you use will need to be one which has
7902 been built to know about the target CPU you're using. It's probably
7903 part of the tool chain you're using. For example, if you are doing
7904 cross-development for ARM on an x86 PC, instead of using the native
7905 x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
7906 if that's the tool chain used to compile your code.
7908 @section Connecting to GDB
7909 @cindex Connecting to GDB
7910 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
7911 instance GDB 6.3 has a known bug that produces bogus memory access
7912 errors, which has since been fixed; see
7913 @url{http://osdir.com/ml/gdb.bugs.discuss/2004-12/msg00018.html}
7915 OpenOCD can communicate with GDB in two ways:
7919 A socket (TCP/IP) connection is typically started as follows:
7921 target remote localhost:3333
7923 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
7925 It is also possible to use the GDB extended remote protocol as follows:
7927 target extended-remote localhost:3333
7930 A pipe connection is typically started as follows:
7932 target remote | openocd -c "gdb_port pipe; log_output openocd.log"
7934 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
7935 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
7936 session. log_output sends the log output to a file to ensure that the pipe is
7937 not saturated when using higher debug level outputs.
7940 To list the available OpenOCD commands type @command{monitor help} on the
7943 @section Sample GDB session startup
7945 With the remote protocol, GDB sessions start a little differently
7946 than they do when you're debugging locally.
7947 Here's an examples showing how to start a debug session with a
7949 In this case the program was linked to be loaded into SRAM on a Cortex-M3.
7950 Most programs would be written into flash (address 0) and run from there.
7953 $ arm-none-eabi-gdb example.elf
7954 (gdb) target remote localhost:3333
7955 Remote debugging using localhost:3333
7957 (gdb) monitor reset halt
7960 Loading section .vectors, size 0x100 lma 0x20000000
7961 Loading section .text, size 0x5a0 lma 0x20000100
7962 Loading section .data, size 0x18 lma 0x200006a0
7963 Start address 0x2000061c, load size 1720
7964 Transfer rate: 22 KB/sec, 573 bytes/write.
7970 You could then interrupt the GDB session to make the program break,
7971 type @command{where} to show the stack, @command{list} to show the
7972 code around the program counter, @command{step} through code,
7973 set breakpoints or watchpoints, and so on.
7975 @section Configuring GDB for OpenOCD
7977 OpenOCD supports the gdb @option{qSupported} packet, this enables information
7978 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
7979 packet size and the device's memory map.
7980 You do not need to configure the packet size by hand,
7981 and the relevant parts of the memory map should be automatically
7982 set up when you declare (NOR) flash banks.
7984 However, there are other things which GDB can't currently query.
7985 You may need to set those up by hand.
7986 As OpenOCD starts up, you will often see a line reporting
7990 Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
7993 You can pass that information to GDB with these commands:
7996 set remote hardware-breakpoint-limit 6
7997 set remote hardware-watchpoint-limit 4
8000 With that particular hardware (Cortex-M3) the hardware breakpoints
8001 only work for code running from flash memory. Most other ARM systems
8002 do not have such restrictions.
8004 Another example of useful GDB configuration came from a user who
8005 found that single stepping his Cortex-M3 didn't work well with IRQs
8006 and an RTOS until he told GDB to disable the IRQs while stepping:
8010 mon cortex_m maskisr on
8012 define hookpost-step
8013 mon cortex_m maskisr off
8017 Rather than typing such commands interactively, you may prefer to
8018 save them in a file and have GDB execute them as it starts, perhaps
8019 using a @file{.gdbinit} in your project directory or starting GDB
8020 using @command{gdb -x filename}.
8022 @section Programming using GDB
8023 @cindex Programming using GDB
8024 @anchor{programmingusinggdb}
8026 By default the target memory map is sent to GDB. This can be disabled by
8027 the following OpenOCD configuration option:
8029 gdb_memory_map disable
8031 For this to function correctly a valid flash configuration must also be set
8032 in OpenOCD. For faster performance you should also configure a valid
8035 Informing GDB of the memory map of the target will enable GDB to protect any
8036 flash areas of the target and use hardware breakpoints by default. This means
8037 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
8038 using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}.
8040 To view the configured memory map in GDB, use the GDB command @option{info mem}
8041 All other unassigned addresses within GDB are treated as RAM.
8043 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
8044 This can be changed to the old behaviour by using the following GDB command
8046 set mem inaccessible-by-default off
8049 If @command{gdb_flash_program enable} is also used, GDB will be able to
8050 program any flash memory using the vFlash interface.
8052 GDB will look at the target memory map when a load command is given, if any
8053 areas to be programmed lie within the target flash area the vFlash packets
8056 If the target needs configuring before GDB programming, an event
8057 script can be executed:
8059 $_TARGETNAME configure -event EVENTNAME BODY
8062 To verify any flash programming the GDB command @option{compare-sections}
8064 @anchor{usingopenocdsmpwithgdb}
8065 @section Using OpenOCD SMP with GDB
8067 For SMP support following GDB serial protocol packet have been defined :
8069 @item j - smp status request
8070 @item J - smp set request
8073 OpenOCD implements :
8075 @item @option{jc} packet for reading core id displayed by
8076 GDB connection. Reply is @option{XXXXXXXX} (8 hex digits giving core id) or
8077 @option{E01} for target not smp.
8078 @item @option{JcXXXXXXXX} (8 hex digits) packet for setting core id displayed at next GDB continue
8079 (core id -1 is reserved for returning to normal resume mode). Reply @option{E01}
8080 for target not smp or @option{OK} on success.
8083 Handling of this packet within GDB can be done :
8085 @item by the creation of an internal variable (i.e @option{_core}) by mean
8086 of function allocate_computed_value allowing following GDB command.
8089 #Jc01 packet is sent
8091 #jc packet is sent and result is affected in $
8094 @item by the usage of GDB maintenance command as described in following example (2 cpus in SMP with
8095 core id 0 and 1 @pxref{definecputargetsworkinginsmp,,Define CPU targets working in SMP}).
8098 # toggle0 : force display of coreid 0
8104 # toggle1 : force display of coreid 1
8113 @section RTOS Support
8114 @cindex RTOS Support
8115 @anchor{gdbrtossupport}
8117 OpenOCD includes RTOS support, this will however need enabling as it defaults to disabled.
8118 It can be enabled by passing @option{-rtos} arg to the target @xref{rtostype,,RTOS Type}
8120 @* An example setup is below:
8123 $_TARGETNAME configure -rtos auto
8126 This will attempt to auto detect the RTOS within your application.
8128 Currently supported rtos's include:
8131 @item @option{ThreadX}
8132 @item @option{FreeRTOS}
8133 @item @option{linux}
8134 @item @option{ChibiOS}
8135 @item @option{embKernel}
8139 Before an RTOS can be detected it must export certain symbols otherwise it cannot be used by
8140 OpenOCD. Below is a list of the required symbols for each supported RTOS.
8145 Cyg_Thread::thread_list, Cyg_Scheduler_Base::current_thread.
8146 @item ThreadX symbols
8147 _tx_thread_current_ptr, _tx_thread_created_ptr, _tx_thread_created_count.
8148 @item FreeRTOS symbols
8149 pxCurrentTCB, pxReadyTasksLists, xDelayedTaskList1, xDelayedTaskList2,
8150 pxDelayedTaskList, pxOverflowDelayedTaskList, xPendingReadyList,
8151 xTasksWaitingTermination, xSuspendedTaskList, uxCurrentNumberOfTasks, uxTopUsedPriority.
8154 @item ChibiOS symbols
8155 rlist, ch_debug, chSysInit.
8156 @item embKernel symbols
8157 Rtos::sCurrentTask, Rtos::sListReady, Rtos::sListSleep,
8158 Rtos::sListSuspended, Rtos::sMaxPriorities, Rtos::sCurrentTaskCount.
8161 For most RTOS supported the above symbols will be exported by default. However for
8162 some, eg. FreeRTOS @option{xTasksWaitingTermination} is only exported
8163 if @option{INCLUDE_vTaskDelete} is defined during the build.
8165 @node Tcl Scripting API
8166 @chapter Tcl Scripting API
8167 @cindex Tcl Scripting API
8171 The commands are stateless. E.g. the telnet command line has a concept
8172 of currently active target, the Tcl API proc's take this sort of state
8173 information as an argument to each proc.
8175 There are three main types of return values: single value, name value
8176 pair list and lists.
8178 Name value pair. The proc 'foo' below returns a name/value pair
8184 > set foo(you) Oyvind
8185 > set foo(mouse) Micky
8186 > set foo(duck) Donald
8194 me Duane you Oyvind mouse Micky duck Donald
8196 Thus, to get the names of the associative array is easy:
8198 foreach { name value } [set foo] {
8199 puts "Name: $name, Value: $value"
8203 Lists returned must be relatively small. Otherwise a range
8204 should be passed in to the proc in question.
8206 @section Internal low-level Commands
8208 By low-level, the intent is a human would not directly use these commands.
8210 Low-level commands are (should be) prefixed with "ocd_", e.g.
8211 @command{ocd_flash_banks}
8212 is the low level API upon which @command{flash banks} is implemented.
8215 @item @b{mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
8217 Read memory and return as a Tcl array for script processing
8218 @item @b{array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
8220 Convert a Tcl array to memory locations and write the values
8221 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
8223 Return information about the flash banks
8226 OpenOCD commands can consist of two words, e.g. "flash banks". The
8227 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
8228 called "flash_banks".
8230 @section OpenOCD specific Global Variables
8232 Real Tcl has ::tcl_platform(), and platform::identify, and many other
8233 variables. JimTCL, as implemented in OpenOCD creates $ocd_HOSTOS which
8234 holds one of the following values:
8237 @item @b{cygwin} Running under Cygwin
8238 @item @b{darwin} Darwin (Mac-OS) is the underlying operating sytem.
8239 @item @b{freebsd} Running under FreeBSD
8240 @item @b{linux} Linux is the underlying operating sytem
8241 @item @b{mingw32} Running under MingW32
8242 @item @b{winxx} Built using Microsoft Visual Studio
8243 @item @b{other} Unknown, none of the above.
8246 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
8249 We should add support for a variable like Tcl variable
8250 @code{tcl_platform(platform)}, it should be called
8251 @code{jim_platform} (because it
8252 is jim, not real tcl).
8260 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
8262 @cindex adaptive clocking
8265 In digital circuit design it is often refered to as ``clock
8266 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
8267 operating at some speed, your CPU target is operating at another.
8268 The two clocks are not synchronised, they are ``asynchronous''
8270 In order for the two to work together they must be synchronised
8271 well enough to work; JTAG can't go ten times faster than the CPU,
8272 for example. There are 2 basic options:
8275 Use a special "adaptive clocking" circuit to change the JTAG
8276 clock rate to match what the CPU currently supports.
8278 The JTAG clock must be fixed at some speed that's enough slower than
8279 the CPU clock that all TMS and TDI transitions can be detected.
8282 @b{Does this really matter?} For some chips and some situations, this
8283 is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
8284 the CPU has no difficulty keeping up with JTAG.
8285 Startup sequences are often problematic though, as are other
8286 situations where the CPU clock rate changes (perhaps to save
8289 For example, Atmel AT91SAM chips start operation from reset with
8290 a 32kHz system clock. Boot firmware may activate the main oscillator
8291 and PLL before switching to a faster clock (perhaps that 500 MHz
8293 If you're using JTAG to debug that startup sequence, you must slow
8294 the JTAG clock to sometimes 1 to 4kHz. After startup completes,
8295 JTAG can use a faster clock.
8297 Consider also debugging a 500MHz ARM926 hand held battery powered
8298 device that enters a low power ``deep sleep'' mode, at 32kHz CPU
8299 clock, between keystrokes unless it has work to do. When would
8300 that 5 MHz JTAG clock be usable?
8302 @b{Solution #1 - A special circuit}
8304 In order to make use of this,
8305 your CPU, board, and JTAG adapter must all support the RTCK
8306 feature. Not all of them support this; keep reading!
8308 The RTCK ("Return TCK") signal in some ARM chips is used to help with
8309 this problem. ARM has a good description of the problem described at
8310 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
8311 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
8312 work? / how does adaptive clocking work?''.
8314 The nice thing about adaptive clocking is that ``battery powered hand
8315 held device example'' - the adaptiveness works perfectly all the
8316 time. One can set a break point or halt the system in the deep power
8317 down code, slow step out until the system speeds up.
8319 Note that adaptive clocking may also need to work at the board level,
8320 when a board-level scan chain has multiple chips.
8321 Parallel clock voting schemes are good way to implement this,
8322 both within and between chips, and can easily be implemented
8324 It's not difficult to have logic fan a module's input TCK signal out
8325 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
8326 back with the right polarity before changing the output RTCK signal.
8327 Texas Instruments makes some clock voting logic available
8328 for free (with no support) in VHDL form; see
8329 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
8331 @b{Solution #2 - Always works - but may be slower}
8333 Often this is a perfectly acceptable solution.
8335 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
8336 the target clock speed. But what that ``magic division'' is varies
8337 depending on the chips on your board.
8338 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
8339 ARM11 cores use an 8:1 division.
8340 @b{Xilinx rule of thumb} is 1/12 the clock speed.
8342 Note: most full speed FT2232 based JTAG adapters are limited to a
8343 maximum of 6MHz. The ones using USB high speed chips (FT2232H)
8344 often support faster clock rates (and adaptive clocking).
8346 You can still debug the 'low power' situations - you just need to
8347 either use a fixed and very slow JTAG clock rate ... or else
8348 manually adjust the clock speed at every step. (Adjusting is painful
8349 and tedious, and is not always practical.)
8351 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
8352 have a special debug mode in your application that does a ``high power
8353 sleep''. If you are careful - 98% of your problems can be debugged
8356 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
8357 operation in your idle loops even if you don't otherwise change the CPU
8359 That operation gates the CPU clock, and thus the JTAG clock; which
8360 prevents JTAG access. One consequence is not being able to @command{halt}
8361 cores which are executing that @emph{wait for interrupt} operation.
8363 To set the JTAG frequency use the command:
8371 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
8373 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
8374 around Windows filenames.
8387 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
8389 Make sure you have Cygwin installed, or at least a version of OpenOCD that
8390 claims to come with all the necessary DLLs. When using Cygwin, try launching
8391 OpenOCD from the Cygwin shell.
8393 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
8394 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
8395 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
8397 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
8398 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
8399 software breakpoints consume one of the two available hardware breakpoints.
8401 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
8403 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
8404 clock at the time you're programming the flash. If you've specified the crystal's
8405 frequency, make sure the PLL is disabled. If you've specified the full core speed
8406 (e.g. 60MHz), make sure the PLL is enabled.
8408 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
8409 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
8410 out while waiting for end of scan, rtck was disabled".
8412 Make sure your PC's parallel port operates in EPP mode. You might have to try several
8413 settings in your PC BIOS (ECP, EPP, and different versions of those).
8415 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
8416 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
8417 memory read caused data abort".
8419 The errors are non-fatal, and are the result of GDB trying to trace stack frames
8420 beyond the last valid frame. It might be possible to prevent this by setting up
8421 a proper "initial" stack frame, if you happen to know what exactly has to
8422 be done, feel free to add this here.
8424 @b{Simple:} In your startup code - push 8 registers of zeros onto the
8425 stack before calling main(). What GDB is doing is ``climbing'' the run
8426 time stack by reading various values on the stack using the standard
8427 call frame for the target. GDB keeps going - until one of 2 things
8428 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
8429 stackframes have been processed. By pushing zeros on the stack, GDB
8432 @b{Debugging Interrupt Service Routines} - In your ISR before you call
8433 your C code, do the same - artifically push some zeros onto the stack,
8434 remember to pop them off when the ISR is done.
8436 @b{Also note:} If you have a multi-threaded operating system, they
8437 often do not @b{in the intrest of saving memory} waste these few
8441 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
8442 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
8444 This warning doesn't indicate any serious problem, as long as you don't want to
8445 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
8446 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
8447 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
8448 independently. With this setup, it's not possible to halt the core right out of
8449 reset, everything else should work fine.
8451 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
8452 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
8453 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
8454 quit with an error message. Is there a stability issue with OpenOCD?
8456 No, this is not a stability issue concerning OpenOCD. Most users have solved
8457 this issue by simply using a self-powered USB hub, which they connect their
8458 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
8459 supply stable enough for the Amontec JTAGkey to be operated.
8461 @b{Laptops running on battery have this problem too...}
8463 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
8464 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
8465 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
8466 What does that mean and what might be the reason for this?
8468 First of all, the reason might be the USB power supply. Try using a self-powered
8469 hub instead of a direct connection to your computer. Secondly, the error code 4
8470 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
8471 chip ran into some sort of error - this points us to a USB problem.
8473 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
8474 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
8475 What does that mean and what might be the reason for this?
8477 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
8478 has closed the connection to OpenOCD. This might be a GDB issue.
8480 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
8481 are described, there is a parameter for specifying the clock frequency
8482 for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
8483 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
8484 specified in kilohertz. However, I do have a quartz crystal of a
8485 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
8486 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
8489 No. The clock frequency specified here must be given as an integral number.
8490 However, this clock frequency is used by the In-Application-Programming (IAP)
8491 routines of the LPC2000 family only, which seems to be very tolerant concerning
8492 the given clock frequency, so a slight difference between the specified clock
8493 frequency and the actual clock frequency will not cause any trouble.
8495 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
8497 Well, yes and no. Commands can be given in arbitrary order, yet the
8498 devices listed for the JTAG scan chain must be given in the right
8499 order (jtag newdevice), with the device closest to the TDO-Pin being
8500 listed first. In general, whenever objects of the same type exist
8501 which require an index number, then these objects must be given in the
8502 right order (jtag newtap, targets and flash banks - a target
8503 references a jtag newtap and a flash bank references a target).
8505 You can use the ``scan_chain'' command to verify and display the tap order.
8507 Also, some commands can't execute until after @command{init} has been
8508 processed. Such commands include @command{nand probe} and everything
8509 else that needs to write to controller registers, perhaps for setting
8510 up DRAM and loading it with code.
8512 @anchor{faqtaporder}
8513 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
8516 Yes; whenever you have more than one, you must declare them in
8517 the same order used by the hardware.
8519 Many newer devices have multiple JTAG TAPs. For example: ST
8520 Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
8521 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
8522 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
8523 connected to the boundary scan TAP, which then connects to the
8524 Cortex-M3 TAP, which then connects to the TDO pin.
8526 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
8527 (2) The boundary scan TAP. If your board includes an additional JTAG
8528 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
8529 place it before or after the STM32 chip in the chain. For example:
8532 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
8533 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
8534 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
8535 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
8536 @item Xilinx TDO Pin -> OpenOCD TDO (input)
8539 The ``jtag device'' commands would thus be in the order shown below. Note:
8542 @item jtag newtap Xilinx tap -irlen ...
8543 @item jtag newtap stm32 cpu -irlen ...
8544 @item jtag newtap stm32 bs -irlen ...
8545 @item # Create the debug target and say where it is
8546 @item target create stm32.cpu -chain-position stm32.cpu ...
8550 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
8551 log file, I can see these error messages: Error: arm7_9_common.c:561
8552 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
8558 @node Tcl Crash Course
8559 @chapter Tcl Crash Course
8562 Not everyone knows Tcl - this is not intended to be a replacement for
8563 learning Tcl, the intent of this chapter is to give you some idea of
8564 how the Tcl scripts work.
8566 This chapter is written with two audiences in mind. (1) OpenOCD users
8567 who need to understand a bit more of how Jim-Tcl works so they can do
8568 something useful, and (2) those that want to add a new command to
8571 @section Tcl Rule #1
8572 There is a famous joke, it goes like this:
8574 @item Rule #1: The wife is always correct
8575 @item Rule #2: If you think otherwise, See Rule #1
8578 The Tcl equal is this:
8581 @item Rule #1: Everything is a string
8582 @item Rule #2: If you think otherwise, See Rule #1
8585 As in the famous joke, the consequences of Rule #1 are profound. Once
8586 you understand Rule #1, you will understand Tcl.
8588 @section Tcl Rule #1b
8589 There is a second pair of rules.
8591 @item Rule #1: Control flow does not exist. Only commands
8592 @* For example: the classic FOR loop or IF statement is not a control
8593 flow item, they are commands, there is no such thing as control flow
8595 @item Rule #2: If you think otherwise, See Rule #1
8596 @* Actually what happens is this: There are commands that by
8597 convention, act like control flow key words in other languages. One of
8598 those commands is the word ``for'', another command is ``if''.
8601 @section Per Rule #1 - All Results are strings
8602 Every Tcl command results in a string. The word ``result'' is used
8603 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
8604 Everything is a string}
8606 @section Tcl Quoting Operators
8607 In life of a Tcl script, there are two important periods of time, the
8608 difference is subtle.
8611 @item Evaluation Time
8614 The two key items here are how ``quoted things'' work in Tcl. Tcl has
8615 three primary quoting constructs, the [square-brackets] the
8616 @{curly-braces@} and ``double-quotes''
8618 By now you should know $VARIABLES always start with a $DOLLAR
8619 sign. BTW: To set a variable, you actually use the command ``set'', as
8620 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
8621 = 1'' statement, but without the equal sign.
8624 @item @b{[square-brackets]}
8625 @* @b{[square-brackets]} are command substitutions. It operates much
8626 like Unix Shell `back-ticks`. The result of a [square-bracket]
8627 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
8628 string}. These two statements are roughly identical:
8632 echo "The Date is: $X"
8635 puts "The Date is: $X"
8637 @item @b{``double-quoted-things''}
8638 @* @b{``double-quoted-things''} are just simply quoted
8639 text. $VARIABLES and [square-brackets] are expanded in place - the
8640 result however is exactly 1 string. @i{Remember Rule #1 - Everything
8644 puts "It is now \"[date]\", $x is in 1 hour"
8646 @item @b{@{Curly-Braces@}}
8647 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
8648 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
8649 'single-quote' operators in BASH shell scripts, with the added
8650 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
8651 nested 3 times@}@}@} NOTE: [date] is a bad example;
8652 at this writing, Jim/OpenOCD does not have a date command.
8655 @section Consequences of Rule 1/2/3/4
8657 The consequences of Rule 1 are profound.
8659 @subsection Tokenisation & Execution.
8661 Of course, whitespace, blank lines and #comment lines are handled in
8664 As a script is parsed, each (multi) line in the script file is
8665 tokenised and according to the quoting rules. After tokenisation, that
8666 line is immedatly executed.
8668 Multi line statements end with one or more ``still-open''
8669 @{curly-braces@} which - eventually - closes a few lines later.
8671 @subsection Command Execution
8673 Remember earlier: There are no ``control flow''
8674 statements in Tcl. Instead there are COMMANDS that simply act like
8675 control flow operators.
8677 Commands are executed like this:
8680 @item Parse the next line into (argc) and (argv[]).
8681 @item Look up (argv[0]) in a table and call its function.
8682 @item Repeat until End Of File.
8685 It sort of works like this:
8688 ReadAndParse( &argc, &argv );
8690 cmdPtr = LookupCommand( argv[0] );
8692 (*cmdPtr->Execute)( argc, argv );
8696 When the command ``proc'' is parsed (which creates a procedure
8697 function) it gets 3 parameters on the command line. @b{1} the name of
8698 the proc (function), @b{2} the list of parameters, and @b{3} the body
8699 of the function. Not the choice of words: LIST and BODY. The PROC
8700 command stores these items in a table somewhere so it can be found by
8703 @subsection The FOR command
8705 The most interesting command to look at is the FOR command. In Tcl,
8706 the FOR command is normally implemented in C. Remember, FOR is a
8707 command just like any other command.
8709 When the ascii text containing the FOR command is parsed, the parser
8710 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
8714 @item The ascii text 'for'
8715 @item The start text
8716 @item The test expression
8721 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
8722 Remember @i{Rule #1 - Everything is a string.} The key point is this:
8723 Often many of those parameters are in @{curly-braces@} - thus the
8724 variables inside are not expanded or replaced until later.
8726 Remember that every Tcl command looks like the classic ``main( argc,
8727 argv )'' function in C. In JimTCL - they actually look like this:
8731 MyCommand( Jim_Interp *interp,
8733 Jim_Obj * const *argvs );
8736 Real Tcl is nearly identical. Although the newer versions have
8737 introduced a byte-code parser and intepreter, but at the core, it
8738 still operates in the same basic way.
8740 @subsection FOR command implementation
8742 To understand Tcl it is perhaps most helpful to see the FOR
8743 command. Remember, it is a COMMAND not a control flow structure.
8745 In Tcl there are two underlying C helper functions.
8747 Remember Rule #1 - You are a string.
8749 The @b{first} helper parses and executes commands found in an ascii
8750 string. Commands can be seperated by semicolons, or newlines. While
8751 parsing, variables are expanded via the quoting rules.
8753 The @b{second} helper evaluates an ascii string as a numerical
8754 expression and returns a value.
8756 Here is an example of how the @b{FOR} command could be
8757 implemented. The pseudo code below does not show error handling.
8759 void Execute_AsciiString( void *interp, const char *string );
8761 int Evaluate_AsciiExpression( void *interp, const char *string );
8764 MyForCommand( void *interp,
8769 SetResult( interp, "WRONG number of parameters");
8773 // argv[0] = the ascii string just like C
8775 // Execute the start statement.
8776 Execute_AsciiString( interp, argv[1] );
8780 i = Evaluate_AsciiExpression(interp, argv[2]);
8785 Execute_AsciiString( interp, argv[3] );
8787 // Execute the LOOP part
8788 Execute_AsciiString( interp, argv[4] );
8792 SetResult( interp, "" );
8797 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
8798 in the same basic way.
8800 @section OpenOCD Tcl Usage
8802 @subsection source and find commands
8803 @b{Where:} In many configuration files
8804 @* Example: @b{ source [find FILENAME] }
8805 @*Remember the parsing rules
8807 @item The @command{find} command is in square brackets,
8808 and is executed with the parameter FILENAME. It should find and return
8809 the full path to a file with that name; it uses an internal search path.
8810 The RESULT is a string, which is substituted into the command line in
8811 place of the bracketed @command{find} command.
8812 (Don't try to use a FILENAME which includes the "#" character.
8813 That character begins Tcl comments.)
8814 @item The @command{source} command is executed with the resulting filename;
8815 it reads a file and executes as a script.
8817 @subsection format command
8818 @b{Where:} Generally occurs in numerous places.
8819 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
8825 puts [format "The answer: %d" [expr $x * $y]]
8828 @item The SET command creates 2 variables, X and Y.
8829 @item The double [nested] EXPR command performs math
8830 @* The EXPR command produces numerical result as a string.
8832 @item The format command is executed, producing a single string
8833 @* Refer to Rule #1.
8834 @item The PUTS command outputs the text.
8836 @subsection Body or Inlined Text
8837 @b{Where:} Various TARGET scripts.
8840 proc someproc @{@} @{
8841 ... multiple lines of stuff ...
8843 $_TARGETNAME configure -event FOO someproc
8844 #2 Good - no variables
8845 $_TARGETNAME confgure -event foo "this ; that;"
8846 #3 Good Curly Braces
8847 $_TARGETNAME configure -event FOO @{
8850 #4 DANGER DANGER DANGER
8851 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
8854 @item The $_TARGETNAME is an OpenOCD variable convention.
8855 @*@b{$_TARGETNAME} represents the last target created, the value changes
8856 each time a new target is created. Remember the parsing rules. When
8857 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
8858 the name of the target which happens to be a TARGET (object)
8860 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
8861 @*There are 4 examples:
8863 @item The TCLBODY is a simple string that happens to be a proc name
8864 @item The TCLBODY is several simple commands seperated by semicolons
8865 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
8866 @item The TCLBODY is a string with variables that get expanded.
8869 In the end, when the target event FOO occurs the TCLBODY is
8870 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
8871 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
8873 Remember the parsing rules. In case #3, @{curly-braces@} mean the
8874 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
8875 and the text is evaluated. In case #4, they are replaced before the
8876 ``Target Object Command'' is executed. This occurs at the same time
8877 $_TARGETNAME is replaced. In case #4 the date will never
8878 change. @{BTW: [date] is a bad example; at this writing,
8879 Jim/OpenOCD does not have a date command@}
8881 @subsection Global Variables
8882 @b{Where:} You might discover this when writing your own procs @* In
8883 simple terms: Inside a PROC, if you need to access a global variable
8884 you must say so. See also ``upvar''. Example:
8886 proc myproc @{ @} @{
8887 set y 0 #Local variable Y
8888 global x #Global variable X
8889 puts [format "X=%d, Y=%d" $x $y]
8892 @section Other Tcl Hacks
8893 @b{Dynamic variable creation}
8895 # Dynamically create a bunch of variables.
8896 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
8898 set vn [format "BIT%d" $x]
8902 set $vn [expr (1 << $x)]
8905 @b{Dynamic proc/command creation}
8907 # One "X" function - 5 uart functions.
8908 foreach who @{A B C D E@}
8909 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
8915 @node OpenOCD Concept Index
8916 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
8917 @comment case issue with ``Index.html'' and ``index.html''
8918 @comment Occurs when creating ``--html --no-split'' output
8919 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
8920 @unnumbered OpenOCD Concept Index
8924 @node Command and Driver Index
8925 @unnumbered Command and Driver Index