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[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
12 @include version.texi
14 @copying
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
51 @summarycontents
52 @contents
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
58 @insertcopying
59 @end ifnottex
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * NAND Flash Commands:: NAND Flash Commands
77 * PLD/FPGA Commands:: PLD/FPGA Commands
78 * General Commands:: General Commands
79 * Architecture and Core Commands:: Architecture and Core Commands
80 * JTAG Commands:: JTAG Commands
81 * Boundary Scan Commands:: Boundary Scan Commands
82 * Utility Commands:: Utility Commands
83 * TFTP:: TFTP
84 * GDB and OpenOCD:: Using GDB and OpenOCD
85 * Tcl Scripting API:: Tcl Scripting API
86 * FAQ:: Frequently Asked Questions
87 * Tcl Crash Course:: Tcl Crash Course
88 * License:: GNU Free Documentation License
90 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
91 @comment case issue with ``Index.html'' and ``index.html''
92 @comment Occurs when creating ``--html --no-split'' output
93 @comment This fix is based on:
94 * OpenOCD Concept Index:: Concept Index
95 * Command and Driver Index:: Command and Driver Index
96 @end menu
98 @node About
99 @unnumbered About
100 @cindex about
102 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
103 at the University of Applied Sciences Augsburg (@uref{}).
104 Since that time, the project has grown into an active open-source project,
105 supported by a diverse community of software and hardware developers from
106 around the world.
108 @section What is OpenOCD?
109 @cindex TAP
110 @cindex JTAG
112 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
113 in-system programming and boundary-scan testing for embedded target
114 devices.
116 It does so with the assistance of a @dfn{debug adapter}, which is
117 a small hardware module which helps provide the right kind of
118 electrical signaling to the target being debugged. These are
119 required since the debug host (on which OpenOCD runs) won't
120 usually have native support for such signaling, or the connector
121 needed to hook up to the target.
123 Such debug adapters support one or more @dfn{transport} protocols,
124 each of which involves different electrical signaling (and uses
125 different messaging protocols on top of that signaling). There
126 are many types of debug adapter, and little uniformity in what
127 they are called. (There are also product naming differences.)
129 These adapters are sometimes packaged as discrete dongles, which
130 may generically be called @dfn{hardware interface dongles}.
131 Some development boards also integrate them directly, which may
132 let the development board connect directly to the debug
133 host over USB (and sometimes also to power it over USB).
135 For example, a @dfn{JTAG Adapter} supports JTAG
136 signaling, and is used to communicate
137 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
138 A @dfn{TAP} is a ``Test Access Port'', a module which processes
139 special instructions and data. TAPs are daisy-chained within and
140 between chips and boards. JTAG supports debugging and boundary
141 scan operations.
143 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
144 signaling to communicate with some newer ARM cores, as well as debug
145 adapters which support both JTAG and SWD transports. SWD supports only
146 debugging, whereas JTAG also supports boundary scan operations.
148 For some chips, there are also @dfn{Programming Adapters} supporting
149 special transports used only to write code to flash memory, without
150 support for on-chip debugging or boundary scan.
151 (At this writing, OpenOCD does not support such non-debug adapters.)
154 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
155 USB-based, parallel port-based, and other standalone boxes that run
156 OpenOCD internally. @xref{Debug Adapter Hardware}.
158 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
159 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
160 (Stellaris LM3, ST STM32 and Energy Micro EFM32) and Intel Quark (x10xx)
161 based cores to be debugged via the GDB protocol.
163 @b{Flash Programming:} Flash writing is supported for external
164 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
165 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
166 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
167 controllers (LPC3180, Orion, S3C24xx, more) is included.
169 @section OpenOCD Web Site
171 The OpenOCD web site provides the latest public news from the community:
173 @uref{}
175 @section Latest User's Guide:
177 The user's guide you are now reading may not be the latest one
178 available. A version for more recent code may be available.
179 Its HTML form is published regularly at:
181 @uref{}
183 PDF form is likewise published at:
185 @uref{}
187 @section OpenOCD User's Forum
189 There is an OpenOCD forum (phpBB) hosted by SparkFun,
190 which might be helpful to you. Note that if you want
191 anything to come to the attention of developers, you
192 should post it to the OpenOCD Developer Mailing List
193 instead of this forum.
195 @uref{}
197 @section OpenOCD User's Mailing List
199 The OpenOCD User Mailing List provides the primary means of
200 communication between users:
202 @uref{}
204 @section OpenOCD IRC
206 Support can also be found on irc:
207 @uref{irc://}
209 @node Developers
210 @chapter OpenOCD Developer Resources
211 @cindex developers
213 If you are interested in improving the state of OpenOCD's debugging and
214 testing support, new contributions will be welcome. Motivated developers
215 can produce new target, flash or interface drivers, improve the
216 documentation, as well as more conventional bug fixes and enhancements.
218 The resources in this chapter are available for developers wishing to explore
219 or expand the OpenOCD source code.
221 @section OpenOCD Git Repository
223 During the 0.3.x release cycle, OpenOCD switched from Subversion to
224 a Git repository hosted at SourceForge. The repository URL is:
226 @uref{git://}
228 or via http
230 @uref{}
232 You may prefer to use a mirror and the HTTP protocol:
234 @uref{}
236 With standard Git tools, use @command{git clone} to initialize
237 a local repository, and @command{git pull} to update it.
238 There are also gitweb pages letting you browse the repository
239 with a web browser, or download arbitrary snapshots without
240 needing a Git client:
242 @uref{}
244 The @file{README} file contains the instructions for building the project
245 from the repository or a snapshot.
247 Developers that want to contribute patches to the OpenOCD system are
248 @b{strongly} encouraged to work against mainline.
249 Patches created against older versions may require additional
250 work from their submitter in order to be updated for newer releases.
252 @section Doxygen Developer Manual
254 During the 0.2.x release cycle, the OpenOCD project began
255 providing a Doxygen reference manual. This document contains more
256 technical information about the software internals, development
257 processes, and similar documentation:
259 @uref{}
261 This document is a work-in-progress, but contributions would be welcome
262 to fill in the gaps. All of the source files are provided in-tree,
263 listed in the Doxyfile configuration at the top of the source tree.
265 @section Gerrit Review System
267 All changes in the OpenOCD Git repository go through the web-based Gerrit
268 Code Review System:
270 @uref{}
272 After a one-time registration and repository setup, anyone can push commits
273 from their local Git repository directly into Gerrit.
274 All users and developers are encouraged to review, test, discuss and vote
275 for changes in Gerrit. The feedback provides the basis for a maintainer to
276 eventually submit the change to the main Git repository.
278 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
279 Developer Manual, contains basic information about how to connect a
280 repository to Gerrit, prepare and push patches. Patch authors are expected to
281 maintain their changes while they're in Gerrit, respond to feedback and if
282 necessary rework and push improved versions of the change.
284 @section OpenOCD Developer Mailing List
286 The OpenOCD Developer Mailing List provides the primary means of
287 communication between developers:
289 @uref{}
291 @section OpenOCD Bug Database
293 During the 0.4.x release cycle the OpenOCD project team began
294 using Trac for its bug database:
296 @uref{}
299 @node Debug Adapter Hardware
300 @chapter Debug Adapter Hardware
301 @cindex dongles
302 @cindex FTDI
303 @cindex wiggler
304 @cindex zy1000
305 @cindex printer port
306 @cindex USB Adapter
307 @cindex RTCK
309 Defined: @b{dongle}: A small device that plugs into a computer and serves as
310 an adapter .... [snip]
312 In the OpenOCD case, this generally refers to @b{a small adapter} that
313 attaches to your computer via USB or the parallel port. One
314 exception is the Ultimate Solutions ZY1000, packaged as a small box you
315 attach via an ethernet cable. The ZY1000 has the advantage that it does not
316 require any drivers to be installed on the developer PC. It also has
317 a built in web interface. It supports RTCK/RCLK or adaptive clocking
318 and has a built-in relay to power cycle targets remotely.
321 @section Choosing a Dongle
323 There are several things you should keep in mind when choosing a dongle.
325 @enumerate
326 @item @b{Transport} Does it support the kind of communication that you need?
327 OpenOCD focusses mostly on JTAG. Your version may also support
328 other ways to communicate with target devices.
329 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
330 Does your dongle support it? You might need a level converter.
331 @item @b{Pinout} What pinout does your target board use?
332 Does your dongle support it? You may be able to use jumper
333 wires, or an "octopus" connector, to convert pinouts.
334 @item @b{Connection} Does your computer have the USB, parallel, or
335 Ethernet port needed?
336 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
337 RTCK support (also known as ``adaptive clocking'')?
338 @end enumerate
340 @section Stand-alone JTAG Probe
342 The ZY1000 from Ultimate Solutions is technically not a dongle but a
343 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
344 running on the developer's host computer.
345 Once installed on a network using DHCP or a static IP assignment, users can
346 access the ZY1000 probe locally or remotely from any host with access to the
347 IP address assigned to the probe.
348 The ZY1000 provides an intuitive web interface with direct access to the
349 OpenOCD debugger.
350 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
351 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
352 the target.
353 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
354 to power cycle the target remotely.
356 For more information, visit:
358 @b{ZY1000} See: @url{}
360 @section USB FT2232 Based
362 There are many USB JTAG dongles on the market, many of them based
363 on a chip from ``Future Technology Devices International'' (FTDI)
364 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
365 See: @url{} for more information.
366 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
367 chips started to become available in JTAG adapters. Around 2012, a new
368 variant appeared - FT232H - this is a single-channel version of FT2232H.
369 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
370 clocking.)
372 The FT2232 chips are flexible enough to support some other
373 transport options, such as SWD or the SPI variants used to
374 program some chips. They have two communications channels,
375 and one can be used for a UART adapter at the same time the
376 other one is used to provide a debug adapter.
378 Also, some development boards integrate an FT2232 chip to serve as
379 a built-in low-cost debug adapter and USB-to-serial solution.
381 @itemize @bullet
382 @item @b{usbjtag}
383 @* Link @url{}
384 @item @b{jtagkey}
385 @* See: @url{}
386 @item @b{jtagkey2}
387 @* See: @url{}
388 @item @b{oocdlink}
389 @* See: @url{} By Joern Kaipf
390 @item @b{signalyzer}
391 @* See: @url{}
392 @item @b{Stellaris Eval Boards}
393 @* See: @url{} - The Stellaris eval boards
394 bundle FT2232-based JTAG and SWD support, which can be used to debug
395 the Stellaris chips. Using separate JTAG adapters is optional.
396 These boards can also be used in a "pass through" mode as JTAG adapters
397 to other target boards, disabling the Stellaris chip.
398 @item @b{TI/Luminary ICDI}
399 @* See: @url{} - TI/Luminary In-Circuit Debug
400 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
401 Evaluation Kits. Like the non-detachable FT2232 support on the other
402 Stellaris eval boards, they can be used to debug other target boards.
403 @item @b{olimex-jtag}
404 @* See: @url{}
405 @item @b{Flyswatter/Flyswatter2}
406 @* See: @url{}
407 @item @b{turtelizer2}
408 @* See:
409 @uref{, Turtelizer 2}, or
410 @url{}
411 @item @b{comstick}
412 @* Link: @url{}
413 @item @b{stm32stick}
414 @* Link @url{}
415 @item @b{axm0432_jtag}
416 @* Axiom AXM-0432 Link @url{} - NOTE: This JTAG does not appear
417 to be available anymore as of April 2012.
418 @item @b{cortino}
419 @* Link @url{}
420 @item @b{dlp-usb1232h}
421 @* Link @url{}
422 @item @b{digilent-hs1}
423 @* Link @url{}
424 @item @b{opendous}
425 @* Link @url{} FT2232H-based
426 (OpenHardware).
427 @item @b{JTAG-lock-pick Tiny 2}
428 @* Link @url{} FT232H-based
430 @item @b{GW16042}
431 @* Link: @url{}
432 FT2232H-based
434 @end itemize
435 @section USB-JTAG / Altera USB-Blaster compatibles
437 These devices also show up as FTDI devices, but are not
438 protocol-compatible with the FT2232 devices. They are, however,
439 protocol-compatible among themselves. USB-JTAG devices typically consist
440 of a FT245 followed by a CPLD that understands a particular protocol,
441 or emulates this protocol using some other hardware.
443 They may appear under different USB VID/PID depending on the particular
444 product. The driver can be configured to search for any VID/PID pair
445 (see the section on driver commands).
447 @itemize
448 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
449 @* Link: @url{}
450 @item @b{Altera USB-Blaster}
451 @* Link: @url{}
452 @end itemize
454 @section USB JLINK based
455 There are several OEM versions of the Segger @b{JLINK} adapter. It is
456 an example of a micro controller based JTAG adapter, it uses an
457 AT91SAM764 internally.
459 @itemize @bullet
460 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
461 @* Link: @url{}
462 @item @b{SEGGER JLINK}
463 @* Link: @url{}
464 @item @b{IAR J-Link}
465 @* Link: @url{}
466 @end itemize
468 @section USB RLINK based
469 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
470 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
471 SWD and not JTAG, thus not supported.
473 @itemize @bullet
474 @item @b{Raisonance RLink}
475 @* Link: @url{}
476 @item @b{STM32 Primer}
477 @* Link: @url{}
478 @item @b{STM32 Primer2}
479 @* Link: @url{}
480 @end itemize
482 @section USB ST-LINK based
483 ST Micro has an adapter called @b{ST-LINK}.
484 They only work with ST Micro chips, notably STM32 and STM8.
486 @itemize @bullet
487 @item @b{ST-LINK}
488 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
489 @* Link: @url{}
490 @item @b{ST-LINK/V2}
491 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
492 @* Link: @url{}
493 @end itemize
495 For info the original ST-LINK enumerates using the mass storage usb class; however,
496 its implementation is completely broken. The result is this causes issues under Linux.
497 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
498 @itemize @bullet
499 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
500 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
501 @end itemize
503 @section USB TI/Stellaris ICDI based
504 Texas Instruments has an adapter called @b{ICDI}.
505 It is not to be confused with the FTDI based adapters that were originally fitted to their
506 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
508 @section USB CMSIS-DAP based
509 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
510 debuggers to ARM Cortex based targets @url{}.
512 @section USB Other
513 @itemize @bullet
514 @item @b{USBprog}
515 @* Link: @url{} - which uses an Atmel MEGA32 and a UBN9604
517 @item @b{USB - Presto}
518 @* Link: @url{}
520 @item @b{Versaloon-Link}
521 @* Link: @url{}
523 @item @b{ARM-JTAG-EW}
524 @* Link: @url{}
526 @item @b{Buspirate}
527 @* Link: @url{}
529 @item @b{opendous}
530 @* Link: @url{} - which uses an AT90USB162
532 @item @b{estick}
533 @* Link: @url{}
535 @item @b{Keil ULINK v1}
536 @* Link: @url{}
537 @end itemize
539 @section IBM PC Parallel Printer Port Based
541 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
542 and the Macraigor Wiggler. There are many clones and variations of
543 these on the market.
545 Note that parallel ports are becoming much less common, so if you
546 have the choice you should probably avoid these adapters in favor
547 of USB-based ones.
549 @itemize @bullet
551 @item @b{Wiggler} - There are many clones of this.
552 @* Link: @url{}
554 @item @b{DLC5} - From XILINX - There are many clones of this
555 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
556 produced, PDF schematics are easily found and it is easy to make.
558 @item @b{Amontec - JTAG Accelerator}
559 @* Link: @url{}
561 @item @b{Wiggler2}
562 @* Link: @url{}
564 @item @b{Wiggler_ntrst_inverted}
565 @* Yet another variation - See the source code, src/jtag/parport.c
567 @item @b{old_amt_wiggler}
568 @* Unknown - probably not on the market today
570 @item @b{arm-jtag}
571 @* Link: Most likely @url{} [another wiggler clone]
573 @item @b{chameleon}
574 @* Link: @url{}
576 @item @b{Triton}
577 @* Unknown.
579 @item @b{Lattice}
580 @* ispDownload from Lattice Semiconductor
581 @url{}
583 @item @b{flashlink}
584 @* From ST Microsystems;
585 @* Link: @url{}
587 @end itemize
589 @section Other...
590 @itemize @bullet
592 @item @b{ep93xx}
593 @* An EP93xx based Linux machine using the GPIO pins directly.
595 @item @b{at91rm9200}
596 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
598 @item @b{bcm2835gpio}
599 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
601 @item @b{jtag_vpi}
602 @* A JTAG driver acting as a client for the JTAG VPI server interface.
603 @* Link: @url{}
605 @end itemize
607 @node About Jim-Tcl
608 @chapter About Jim-Tcl
609 @cindex Jim-Tcl
610 @cindex tcl
612 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
613 This programming language provides a simple and extensible
614 command interpreter.
616 All commands presented in this Guide are extensions to Jim-Tcl.
617 You can use them as simple commands, without needing to learn
618 much of anything about Tcl.
619 Alternatively, you can write Tcl programs with them.
621 You can learn more about Jim at its website, @url{}.
622 There is an active and responsive community, get on the mailing list
623 if you have any questions. Jim-Tcl maintainers also lurk on the
624 OpenOCD mailing list.
626 @itemize @bullet
627 @item @b{Jim vs. Tcl}
628 @* Jim-Tcl is a stripped down version of the well known Tcl language,
629 which can be found here: @url{}. Jim-Tcl has far
630 fewer features. Jim-Tcl is several dozens of .C files and .H files and
631 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
632 4.2 MB .zip file containing 1540 files.
634 @item @b{Missing Features}
635 @* Our practice has been: Add/clone the real Tcl feature if/when
636 needed. We welcome Jim-Tcl improvements, not bloat. Also there
637 are a large number of optional Jim-Tcl features that are not
638 enabled in OpenOCD.
640 @item @b{Scripts}
641 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
642 command interpreter today is a mixture of (newer)
643 Jim-Tcl commands, and the (older) original command interpreter.
645 @item @b{Commands}
646 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
647 can type a Tcl for() loop, set variables, etc.
648 Some of the commands documented in this guide are implemented
649 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
651 @item @b{Historical Note}
652 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
653 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
654 as a Git submodule, which greatly simplified upgrading Jim-Tcl
655 to benefit from new features and bugfixes in Jim-Tcl.
657 @item @b{Need a crash course in Tcl?}
658 @*@xref{Tcl Crash Course}.
659 @end itemize
661 @node Running
662 @chapter Running
663 @cindex command line options
664 @cindex logfile
665 @cindex directory search
667 Properly installing OpenOCD sets up your operating system to grant it access
668 to the debug adapters. On Linux, this usually involves installing a file
669 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
670 that works for many common adapters is shipped with OpenOCD in the
671 @file{contrib} directory. MS-Windows needs
672 complex and confusing driver configuration for every peripheral. Such issues
673 are unique to each operating system, and are not detailed in this User's Guide.
675 Then later you will invoke the OpenOCD server, with various options to
676 tell it how each debug session should work.
677 The @option{--help} option shows:
678 @verbatim
679 bash$ openocd --help
681 --help | -h display this help
682 --version | -v display OpenOCD version
683 --file | -f use configuration file <name>
684 --search | -s dir to search for config files and scripts
685 --debug | -d set debug level <0-3>
686 --log_output | -l redirect log output to file <name>
687 --command | -c run <command>
688 @end verbatim
690 If you don't give any @option{-f} or @option{-c} options,
691 OpenOCD tries to read the configuration file @file{openocd.cfg}.
692 To specify one or more different
693 configuration files, use @option{-f} options. For example:
695 @example
696 openocd -f config1.cfg -f config2.cfg -f config3.cfg
697 @end example
699 Configuration files and scripts are searched for in
700 @enumerate
701 @item the current directory,
702 @item any search dir specified on the command line using the @option{-s} option,
703 @item any search dir specified using the @command{add_script_search_dir} command,
704 @item @file{$HOME/.openocd} (not on Windows),
705 @item the site wide script library @file{$pkgdatadir/site} and
706 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
707 @end enumerate
708 The first found file with a matching file name will be used.
710 @quotation Note
711 Don't try to use configuration script names or paths which
712 include the "#" character. That character begins Tcl comments.
713 @end quotation
715 @section Simple setup, no customization
717 In the best case, you can use two scripts from one of the script
718 libraries, hook up your JTAG adapter, and start the server ... and
719 your JTAG setup will just work "out of the box". Always try to
720 start by reusing those scripts, but assume you'll need more
721 customization even if this works. @xref{OpenOCD Project Setup}.
723 If you find a script for your JTAG adapter, and for your board or
724 target, you may be able to hook up your JTAG adapter then start
725 the server with some variation of one of the following:
727 @example
728 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
729 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
730 @end example
732 You might also need to configure which reset signals are present,
733 using @option{-c 'reset_config trst_and_srst'} or something similar.
734 If all goes well you'll see output something like
736 @example
737 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
738 For bug reports, read
740 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
741 (mfg: 0x23b, part: 0xba00, ver: 0x3)
742 @end example
744 Seeing that "tap/device found" message, and no warnings, means
745 the JTAG communication is working. That's a key milestone, but
746 you'll probably need more project-specific setup.
748 @section What OpenOCD does as it starts
750 OpenOCD starts by processing the configuration commands provided
751 on the command line or, if there were no @option{-c command} or
752 @option{-f file.cfg} options given, in @file{openocd.cfg}.
753 @xref{configurationstage,,Configuration Stage}.
754 At the end of the configuration stage it verifies the JTAG scan
755 chain defined using those commands; your configuration should
756 ensure that this always succeeds.
757 Normally, OpenOCD then starts running as a daemon.
758 Alternatively, commands may be used to terminate the configuration
759 stage early, perform work (such as updating some flash memory),
760 and then shut down without acting as a daemon.
762 Once OpenOCD starts running as a daemon, it waits for connections from
763 clients (Telnet, GDB, Other) and processes the commands issued through
764 those channels.
766 If you are having problems, you can enable internal debug messages via
767 the @option{-d} option.
769 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
770 @option{-c} command line switch.
772 To enable debug output (when reporting problems or working on OpenOCD
773 itself), use the @option{-d} command line switch. This sets the
774 @option{debug_level} to "3", outputting the most information,
775 including debug messages. The default setting is "2", outputting only
776 informational messages, warnings and errors. You can also change this
777 setting from within a telnet or gdb session using @command{debug_level<n>}
778 (@pxref{debuglevel,,debug_level}).
780 You can redirect all output from the daemon to a file using the
781 @option{-l <logfile>} switch.
783 Note! OpenOCD will launch the GDB & telnet server even if it can not
784 establish a connection with the target. In general, it is possible for
785 the JTAG controller to be unresponsive until the target is set up
786 correctly via e.g. GDB monitor commands in a GDB init script.
788 @node OpenOCD Project Setup
789 @chapter OpenOCD Project Setup
791 To use OpenOCD with your development projects, you need to do more than
792 just connect the JTAG adapter hardware (dongle) to your development board
793 and start the OpenOCD server.
794 You also need to configure your OpenOCD server so that it knows
795 about your adapter and board, and helps your work.
796 You may also want to connect OpenOCD to GDB, possibly
797 using Eclipse or some other GUI.
799 @section Hooking up the JTAG Adapter
801 Today's most common case is a dongle with a JTAG cable on one side
802 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
803 and a USB cable on the other.
804 Instead of USB, some cables use Ethernet;
805 older ones may use a PC parallel port, or even a serial port.
807 @enumerate
808 @item @emph{Start with power to your target board turned off},
809 and nothing connected to your JTAG adapter.
810 If you're particularly paranoid, unplug power to the board.
811 It's important to have the ground signal properly set up,
812 unless you are using a JTAG adapter which provides
813 galvanic isolation between the target board and the
814 debugging host.
816 @item @emph{Be sure it's the right kind of JTAG connector.}
817 If your dongle has a 20-pin ARM connector, you need some kind
818 of adapter (or octopus, see below) to hook it up to
819 boards using 14-pin or 10-pin connectors ... or to 20-pin
820 connectors which don't use ARM's pinout.
822 In the same vein, make sure the voltage levels are compatible.
823 Not all JTAG adapters have the level shifters needed to work
824 with 1.2 Volt boards.
826 @item @emph{Be certain the cable is properly oriented} or you might
827 damage your board. In most cases there are only two possible
828 ways to connect the cable.
829 Connect the JTAG cable from your adapter to the board.
830 Be sure it's firmly connected.
832 In the best case, the connector is keyed to physically
833 prevent you from inserting it wrong.
834 This is most often done using a slot on the board's male connector
835 housing, which must match a key on the JTAG cable's female connector.
836 If there's no housing, then you must look carefully and
837 make sure pin 1 on the cable hooks up to pin 1 on the board.
838 Ribbon cables are frequently all grey except for a wire on one
839 edge, which is red. The red wire is pin 1.
841 Sometimes dongles provide cables where one end is an ``octopus'' of
842 color coded single-wire connectors, instead of a connector block.
843 These are great when converting from one JTAG pinout to another,
844 but are tedious to set up.
845 Use these with connector pinout diagrams to help you match up the
846 adapter signals to the right board pins.
848 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
849 A USB, parallel, or serial port connector will go to the host which
850 you are using to run OpenOCD.
851 For Ethernet, consult the documentation and your network administrator.
853 For USB-based JTAG adapters you have an easy sanity check at this point:
854 does the host operating system see the JTAG adapter? If you're running
855 Linux, try the @command{lsusb} command. If that host is an
856 MS-Windows host, you'll need to install a driver before OpenOCD works.
858 @item @emph{Connect the adapter's power supply, if needed.}
859 This step is primarily for non-USB adapters,
860 but sometimes USB adapters need extra power.
862 @item @emph{Power up the target board.}
863 Unless you just let the magic smoke escape,
864 you're now ready to set up the OpenOCD server
865 so you can use JTAG to work with that board.
867 @end enumerate
869 Talk with the OpenOCD server using
870 telnet (@code{telnet localhost 4444} on many systems) or GDB.
871 @xref{GDB and OpenOCD}.
873 @section Project Directory
875 There are many ways you can configure OpenOCD and start it up.
877 A simple way to organize them all involves keeping a
878 single directory for your work with a given board.
879 When you start OpenOCD from that directory,
880 it searches there first for configuration files, scripts,
881 files accessed through semihosting,
882 and for code you upload to the target board.
883 It is also the natural place to write files,
884 such as log files and data you download from the board.
886 @section Configuration Basics
888 There are two basic ways of configuring OpenOCD, and
889 a variety of ways you can mix them.
890 Think of the difference as just being how you start the server:
892 @itemize
893 @item Many @option{-f file} or @option{-c command} options on the command line
894 @item No options, but a @dfn{user config file}
895 in the current directory named @file{openocd.cfg}
896 @end itemize
898 Here is an example @file{openocd.cfg} file for a setup
899 using a Signalyzer FT2232-based JTAG adapter to talk to
900 a board with an Atmel AT91SAM7X256 microcontroller:
902 @example
903 source [find interface/signalyzer.cfg]
905 # GDB can also flash my flash!
906 gdb_memory_map enable
907 gdb_flash_program enable
909 source [find target/sam7x256.cfg]
910 @end example
912 Here is the command line equivalent of that configuration:
914 @example
915 openocd -f interface/signalyzer.cfg \
916 -c "gdb_memory_map enable" \
917 -c "gdb_flash_program enable" \
918 -f target/sam7x256.cfg
919 @end example
921 You could wrap such long command lines in shell scripts,
922 each supporting a different development task.
923 One might re-flash the board with a specific firmware version.
924 Another might set up a particular debugging or run-time environment.
926 @quotation Important
927 At this writing (October 2009) the command line method has
928 problems with how it treats variables.
929 For example, after @option{-c "set VAR value"}, or doing the
930 same in a script, the variable @var{VAR} will have no value
931 that can be tested in a later script.
932 @end quotation
934 Here we will focus on the simpler solution: one user config
935 file, including basic configuration plus any TCL procedures
936 to simplify your work.
938 @section User Config Files
939 @cindex config file, user
940 @cindex user config file
941 @cindex config file, overview
943 A user configuration file ties together all the parts of a project
944 in one place.
945 One of the following will match your situation best:
947 @itemize
948 @item Ideally almost everything comes from configuration files
949 provided by someone else.
950 For example, OpenOCD distributes a @file{scripts} directory
951 (probably in @file{/usr/share/openocd/scripts} on Linux).
952 Board and tool vendors can provide these too, as can individual
953 user sites; the @option{-s} command line option lets you say
954 where to find these files. (@xref{Running}.)
955 The AT91SAM7X256 example above works this way.
957 Three main types of non-user configuration file each have their
958 own subdirectory in the @file{scripts} directory:
960 @enumerate
961 @item @b{interface} -- one for each different debug adapter;
962 @item @b{board} -- one for each different board
963 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
964 @end enumerate
966 Best case: include just two files, and they handle everything else.
967 The first is an interface config file.
968 The second is board-specific, and it sets up the JTAG TAPs and
969 their GDB targets (by deferring to some @file{target.cfg} file),
970 declares all flash memory, and leaves you nothing to do except
971 meet your deadline:
973 @example
974 source [find interface/olimex-jtag-tiny.cfg]
975 source [find board/csb337.cfg]
976 @end example
978 Boards with a single microcontroller often won't need more
979 than the target config file, as in the AT91SAM7X256 example.
980 That's because there is no external memory (flash, DDR RAM), and
981 the board differences are encapsulated by application code.
983 @item Maybe you don't know yet what your board looks like to JTAG.
984 Once you know the @file{interface.cfg} file to use, you may
985 need help from OpenOCD to discover what's on the board.
986 Once you find the JTAG TAPs, you can just search for appropriate
987 target and board
988 configuration files ... or write your own, from the bottom up.
989 @xref{autoprobing,,Autoprobing}.
991 @item You can often reuse some standard config files but
992 need to write a few new ones, probably a @file{board.cfg} file.
993 You will be using commands described later in this User's Guide,
994 and working with the guidelines in the next chapter.
996 For example, there may be configuration files for your JTAG adapter
997 and target chip, but you need a new board-specific config file
998 giving access to your particular flash chips.
999 Or you might need to write another target chip configuration file
1000 for a new chip built around the Cortex M3 core.
1002 @quotation Note
1003 When you write new configuration files, please submit
1004 them for inclusion in the next OpenOCD release.
1005 For example, a @file{board/newboard.cfg} file will help the
1006 next users of that board, and a @file{target/newcpu.cfg}
1007 will help support users of any board using that chip.
1008 @end quotation
1010 @item
1011 You may may need to write some C code.
1012 It may be as simple as supporting a new FT2232 or parport
1013 based adapter; a bit more involved, like a NAND or NOR flash
1014 controller driver; or a big piece of work like supporting
1015 a new chip architecture.
1016 @end itemize
1018 Reuse the existing config files when you can.
1019 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1020 You may find a board configuration that's a good example to follow.
1022 When you write config files, separate the reusable parts
1023 (things every user of that interface, chip, or board needs)
1024 from ones specific to your environment and debugging approach.
1025 @itemize
1027 @item
1028 For example, a @code{gdb-attach} event handler that invokes
1029 the @command{reset init} command will interfere with debugging
1030 early boot code, which performs some of the same actions
1031 that the @code{reset-init} event handler does.
1033 @item
1034 Likewise, the @command{arm9 vector_catch} command (or
1035 @cindex vector_catch
1036 its siblings @command{xscale vector_catch}
1037 and @command{cortex_m vector_catch}) can be a timesaver
1038 during some debug sessions, but don't make everyone use that either.
1039 Keep those kinds of debugging aids in your user config file,
1040 along with messaging and tracing setup.
1041 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1043 @item
1044 You might need to override some defaults.
1045 For example, you might need to move, shrink, or back up the target's
1046 work area if your application needs much SRAM.
1048 @item
1049 TCP/IP port configuration is another example of something which
1050 is environment-specific, and should only appear in
1051 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1052 @end itemize
1054 @section Project-Specific Utilities
1056 A few project-specific utility
1057 routines may well speed up your work.
1058 Write them, and keep them in your project's user config file.
1060 For example, if you are making a boot loader work on a
1061 board, it's nice to be able to debug the ``after it's
1062 loaded to RAM'' parts separately from the finicky early
1063 code which sets up the DDR RAM controller and clocks.
1064 A script like this one, or a more GDB-aware sibling,
1065 may help:
1067 @example
1068 proc ramboot @{ @} @{
1069 # Reset, running the target's "reset-init" scripts
1070 # to initialize clocks and the DDR RAM controller.
1071 # Leave the CPU halted.
1072 reset init
1074 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1075 load_image u-boot.bin 0x20000000
1077 # Start running.
1078 resume 0x20000000
1079 @}
1080 @end example
1082 Then once that code is working you will need to make it
1083 boot from NOR flash; a different utility would help.
1084 Alternatively, some developers write to flash using GDB.
1085 (You might use a similar script if you're working with a flash
1086 based microcontroller application instead of a boot loader.)
1088 @example
1089 proc newboot @{ @} @{
1090 # Reset, leaving the CPU halted. The "reset-init" event
1091 # proc gives faster access to the CPU and to NOR flash;
1092 # "reset halt" would be slower.
1093 reset init
1095 # Write standard version of U-Boot into the first two
1096 # sectors of NOR flash ... the standard version should
1097 # do the same lowlevel init as "reset-init".
1098 flash protect 0 0 1 off
1099 flash erase_sector 0 0 1
1100 flash write_bank 0 u-boot.bin 0x0
1101 flash protect 0 0 1 on
1103 # Reboot from scratch using that new boot loader.
1104 reset run
1105 @}
1106 @end example
1108 You may need more complicated utility procedures when booting
1109 from NAND.
1110 That often involves an extra bootloader stage,
1111 running from on-chip SRAM to perform DDR RAM setup so it can load
1112 the main bootloader code (which won't fit into that SRAM).
1114 Other helper scripts might be used to write production system images,
1115 involving considerably more than just a three stage bootloader.
1117 @section Target Software Changes
1119 Sometimes you may want to make some small changes to the software
1120 you're developing, to help make JTAG debugging work better.
1121 For example, in C or assembly language code you might
1122 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1123 handling issues like:
1125 @itemize @bullet
1127 @item @b{Watchdog Timers}...
1128 Watchog timers are typically used to automatically reset systems if
1129 some application task doesn't periodically reset the timer. (The
1130 assumption is that the system has locked up if the task can't run.)
1131 When a JTAG debugger halts the system, that task won't be able to run
1132 and reset the timer ... potentially causing resets in the middle of
1133 your debug sessions.
1135 It's rarely a good idea to disable such watchdogs, since their usage
1136 needs to be debugged just like all other parts of your firmware.
1137 That might however be your only option.
1139 Look instead for chip-specific ways to stop the watchdog from counting
1140 while the system is in a debug halt state. It may be simplest to set
1141 that non-counting mode in your debugger startup scripts. You may however
1142 need a different approach when, for example, a motor could be physically
1143 damaged by firmware remaining inactive in a debug halt state. That might
1144 involve a type of firmware mode where that "non-counting" mode is disabled
1145 at the beginning then re-enabled at the end; a watchdog reset might fire
1146 and complicate the debug session, but hardware (or people) would be
1147 protected.@footnote{Note that many systems support a "monitor mode" debug
1148 that is a somewhat cleaner way to address such issues. You can think of
1149 it as only halting part of the system, maybe just one task,
1150 instead of the whole thing.
1151 At this writing, January 2010, OpenOCD based debugging does not support
1152 monitor mode debug, only "halt mode" debug.}
1154 @item @b{ARM Semihosting}...
1155 @cindex ARM semihosting
1156 When linked with a special runtime library provided with many
1157 toolchains@footnote{See chapter 8 "Semihosting" in
1158 @uref{,
1159 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1160 The CodeSourcery EABI toolchain also includes a semihosting library.},
1161 your target code can use I/O facilities on the debug host. That library
1162 provides a small set of system calls which are handled by OpenOCD.
1163 It can let the debugger provide your system console and a file system,
1164 helping with early debugging or providing a more capable environment
1165 for sometimes-complex tasks like installing system firmware onto
1166 NAND or SPI flash.
1168 @item @b{ARM Wait-For-Interrupt}...
1169 Many ARM chips synchronize the JTAG clock using the core clock.
1170 Low power states which stop that core clock thus prevent JTAG access.
1171 Idle loops in tasking environments often enter those low power states
1172 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1174 You may want to @emph{disable that instruction} in source code,
1175 or otherwise prevent using that state,
1176 to ensure you can get JTAG access at any time.@footnote{As a more
1177 polite alternative, some processors have special debug-oriented
1178 registers which can be used to change various features including
1179 how the low power states are clocked while debugging.
1180 The STM32 DBGMCU_CR register is an example; at the cost of extra
1181 power consumption, JTAG can be used during low power states.}
1182 For example, the OpenOCD @command{halt} command may not
1183 work for an idle processor otherwise.
1185 @item @b{Delay after reset}...
1186 Not all chips have good support for debugger access
1187 right after reset; many LPC2xxx chips have issues here.
1188 Similarly, applications that reconfigure pins used for
1189 JTAG access as they start will also block debugger access.
1191 To work with boards like this, @emph{enable a short delay loop}
1192 the first thing after reset, before "real" startup activities.
1193 For example, one second's delay is usually more than enough
1194 time for a JTAG debugger to attach, so that
1195 early code execution can be debugged
1196 or firmware can be replaced.
1198 @item @b{Debug Communications Channel (DCC)}...
1199 Some processors include mechanisms to send messages over JTAG.
1200 Many ARM cores support these, as do some cores from other vendors.
1201 (OpenOCD may be able to use this DCC internally, speeding up some
1202 operations like writing to memory.)
1204 Your application may want to deliver various debugging messages
1205 over JTAG, by @emph{linking with a small library of code}
1206 provided with OpenOCD and using the utilities there to send
1207 various kinds of message.
1208 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1210 @end itemize
1212 @section Target Hardware Setup
1214 Chip vendors often provide software development boards which
1215 are highly configurable, so that they can support all options
1216 that product boards may require. @emph{Make sure that any
1217 jumpers or switches match the system configuration you are
1218 working with.}
1220 Common issues include:
1222 @itemize @bullet
1224 @item @b{JTAG setup} ...
1225 Boards may support more than one JTAG configuration.
1226 Examples include jumpers controlling pullups versus pulldowns
1227 on the nTRST and/or nSRST signals, and choice of connectors
1228 (e.g. which of two headers on the base board,
1229 or one from a daughtercard).
1230 For some Texas Instruments boards, you may need to jumper the
1231 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1233 @item @b{Boot Modes} ...
1234 Complex chips often support multiple boot modes, controlled
1235 by external jumpers. Make sure this is set up correctly.
1236 For example many i.MX boards from NXP need to be jumpered
1237 to "ATX mode" to start booting using the on-chip ROM, when
1238 using second stage bootloader code stored in a NAND flash chip.
1240 Such explicit configuration is common, and not limited to
1241 booting from NAND. You might also need to set jumpers to
1242 start booting using code loaded from an MMC/SD card; external
1243 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1244 flash; some external host; or various other sources.
1247 @item @b{Memory Addressing} ...
1248 Boards which support multiple boot modes may also have jumpers
1249 to configure memory addressing. One board, for example, jumpers
1250 external chipselect 0 (used for booting) to address either
1251 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1252 or NAND flash. When it's jumpered to address NAND flash, that
1253 board must also be told to start booting from on-chip ROM.
1255 Your @file{board.cfg} file may also need to be told this jumper
1256 configuration, so that it can know whether to declare NOR flash
1257 using @command{flash bank} or instead declare NAND flash with
1258 @command{nand device}; and likewise which probe to perform in
1259 its @code{reset-init} handler.
1261 A closely related issue is bus width. Jumpers might need to
1262 distinguish between 8 bit or 16 bit bus access for the flash
1263 used to start booting.
1265 @item @b{Peripheral Access} ...
1266 Development boards generally provide access to every peripheral
1267 on the chip, sometimes in multiple modes (such as by providing
1268 multiple audio codec chips).
1269 This interacts with software
1270 configuration of pin multiplexing, where for example a
1271 given pin may be routed either to the MMC/SD controller
1272 or the GPIO controller. It also often interacts with
1273 configuration jumpers. One jumper may be used to route
1274 signals to an MMC/SD card slot or an expansion bus (which
1275 might in turn affect booting); others might control which
1276 audio or video codecs are used.
1278 @end itemize
1280 Plus you should of course have @code{reset-init} event handlers
1281 which set up the hardware to match that jumper configuration.
1282 That includes in particular any oscillator or PLL used to clock
1283 the CPU, and any memory controllers needed to access external
1284 memory and peripherals. Without such handlers, you won't be
1285 able to access those resources without working target firmware
1286 which can do that setup ... this can be awkward when you're
1287 trying to debug that target firmware. Even if there's a ROM
1288 bootloader which handles a few issues, it rarely provides full
1289 access to all board-specific capabilities.
1292 @node Config File Guidelines
1293 @chapter Config File Guidelines
1295 This chapter is aimed at any user who needs to write a config file,
1296 including developers and integrators of OpenOCD and any user who
1297 needs to get a new board working smoothly.
1298 It provides guidelines for creating those files.
1300 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1301 with files including the ones listed here.
1302 Use them as-is where you can; or as models for new files.
1303 @itemize @bullet
1304 @item @file{interface} ...
1305 These are for debug adapters.
1306 Files that configure JTAG adapters go here.
1307 @example
1308 $ ls interface -R
1309 interface/:
1310 altera-usb-blaster.cfg hilscher_nxhx50_re.cfg openocd-usb-hs.cfg
1311 arm-jtag-ew.cfg hitex_str9-comstick.cfg openrd.cfg
1312 at91rm9200.cfg icebear.cfg osbdm.cfg
1313 axm0432.cfg jlink.cfg parport.cfg
1314 busblaster.cfg jtagkey2.cfg parport_dlc5.cfg
1315 buspirate.cfg jtagkey2p.cfg redbee-econotag.cfg
1316 calao-usb-a9260-c01.cfg jtagkey.cfg redbee-usb.cfg
1317 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg rlink.cfg
1318 calao-usb-a9260.cfg jtag-lock-pick_tiny_2.cfg sheevaplug.cfg
1319 chameleon.cfg kt-link.cfg signalyzer.cfg
1320 cortino.cfg lisa-l.cfg signalyzer-h2.cfg
1321 digilent-hs1.cfg luminary.cfg signalyzer-h4.cfg
1322 dlp-usb1232h.cfg luminary-icdi.cfg signalyzer-lite.cfg
1323 dummy.cfg luminary-lm3s811.cfg stlink-v1.cfg
1324 estick.cfg minimodule.cfg stlink-v2.cfg
1325 flashlink.cfg neodb.cfg stm32-stick.cfg
1326 flossjtag.cfg ngxtech.cfg sysfsgpio-raspberrypi.cfg
1327 flossjtag-noeeprom.cfg olimex-arm-usb-ocd.cfg ti-icdi.cfg
1328 flyswatter2.cfg olimex-arm-usb-ocd-h.cfg turtelizer2.cfg
1329 flyswatter.cfg olimex-arm-usb-tiny-h.cfg ulink.cfg
1330 ftdi olimex-jtag-tiny.cfg usb-jtag.cfg
1331 hilscher_nxhx10_etm.cfg oocdlink.cfg usbprog.cfg
1332 hilscher_nxhx500_etm.cfg opendous.cfg vpaclink.cfg
1333 hilscher_nxhx500_re.cfg opendous_ftdi.cfg vsllink.cfg
1334 hilscher_nxhx50_etm.cfg openocd-usb.cfg xds100v2.cfg
1336 interface/ftdi:
1337 axm0432.cfg hitex_str9-comstick.cfg olimex-jtag-tiny.cfg
1338 calao-usb-a9260-c01.cfg icebear.cfg oocdlink.cfg
1339 calao-usb-a9260-c02.cfg jtagkey2.cfg opendous_ftdi.cfg
1340 cortino.cfg jtagkey2p.cfg openocd-usb.cfg
1341 dlp-usb1232h.cfg jtagkey.cfg openocd-usb-hs.cfg
1342 dp_busblaster.cfg jtag-lock-pick_tiny_2.cfg openrd.cfg
1343 flossjtag.cfg kt-link.cfg redbee-econotag.cfg
1344 flossjtag-noeeprom.cfg lisa-l.cfg redbee-usb.cfg
1345 flyswatter2.cfg luminary.cfg sheevaplug.cfg
1346 flyswatter.cfg luminary-icdi.cfg signalyzer.cfg
1347 gw16042.cfg luminary-lm3s811.cfg signalyzer-lite.cfg
1348 hilscher_nxhx10_etm.cfg minimodule.cfg stm32-stick.cfg
1349 hilscher_nxhx500_etm.cfg neodb.cfg turtelizer2-revB.cfg
1350 hilscher_nxhx500_re.cfg ngxtech.cfg turtelizer2-revC.cfg
1351 hilscher_nxhx50_etm.cfg olimex-arm-usb-ocd.cfg vpaclink.cfg
1352 hilscher_nxhx50_re.cfg olimex-arm-usb-ocd-h.cfg xds100v2.cfg
1353 hitex_lpc1768stick.cfg olimex-arm-usb-tiny-h.cfg
1354 $
1355 @end example
1356 @item @file{board} ...
1357 think Circuit Board, PWA, PCB, they go by many names. Board files
1358 contain initialization items that are specific to a board.
1359 They reuse target configuration files, since the same
1360 microprocessor chips are used on many boards,
1361 but support for external parts varies widely. For
1362 example, the SDRAM initialization sequence for the board, or the type
1363 of external flash and what address it uses. Any initialization
1364 sequence to enable that external flash or SDRAM should be found in the
1365 board file. Boards may also contain multiple targets: two CPUs; or
1366 a CPU and an FPGA.
1367 @example
1368 $ ls board
1369 actux3.cfg lpc1850_spifi_generic.cfg
1370 am3517evm.cfg lpc4350_spifi_generic.cfg
1371 arm_evaluator7t.cfg lubbock.cfg
1372 at91cap7a-stk-sdram.cfg mcb1700.cfg
1373 at91eb40a.cfg microchip_explorer16.cfg
1374 at91rm9200-dk.cfg mini2440.cfg
1375 at91rm9200-ek.cfg mini6410.cfg
1376 at91sam9261-ek.cfg netgear-dg834v3.cfg
1377 at91sam9263-ek.cfg olimex_LPC2378STK.cfg
1378 at91sam9g20-ek.cfg olimex_lpc_h2148.cfg
1379 atmel_at91sam7s-ek.cfg olimex_sam7_ex256.cfg
1380 atmel_at91sam9260-ek.cfg olimex_sam9_l9260.cfg
1381 atmel_at91sam9rl-ek.cfg olimex_stm32_h103.cfg
1382 atmel_sam3n_ek.cfg olimex_stm32_h107.cfg
1383 atmel_sam3s_ek.cfg olimex_stm32_p107.cfg
1384 atmel_sam3u_ek.cfg omap2420_h4.cfg
1385 atmel_sam3x_ek.cfg open-bldc.cfg
1386 atmel_sam4s_ek.cfg openrd.cfg
1387 balloon3-cpu.cfg osk5912.cfg
1388 colibri.cfg phone_se_j100i.cfg
1389 crossbow_tech_imote2.cfg phytec_lpc3250.cfg
1390 csb337.cfg pic-p32mx.cfg
1391 csb732.cfg propox_mmnet1001.cfg
1392 da850evm.cfg pxa255_sst.cfg
1393 digi_connectcore_wi-9c.cfg redbee.cfg
1394 diolan_lpc4350-db1.cfg rsc-w910.cfg
1395 dm355evm.cfg sheevaplug.cfg
1396 dm365evm.cfg smdk6410.cfg
1397 dm6446evm.cfg spear300evb.cfg
1398 efikamx.cfg spear300evb_mod.cfg
1399 eir.cfg spear310evb20.cfg
1400 ek-lm3s1968.cfg spear310evb20_mod.cfg
1401 ek-lm3s3748.cfg spear320cpu.cfg
1402 ek-lm3s6965.cfg spear320cpu_mod.cfg
1403 ek-lm3s811.cfg steval_pcc010.cfg
1404 ek-lm3s811-revb.cfg stm320518_eval_stlink.cfg
1405 ek-lm3s8962.cfg stm32100b_eval.cfg
1406 ek-lm3s9b9x.cfg stm3210b_eval.cfg
1407 ek-lm3s9d92.cfg stm3210c_eval.cfg
1408 ek-lm4f120xl.cfg stm3210e_eval.cfg
1409 ek-lm4f232.cfg stm3220g_eval.cfg
1410 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1411 ethernut3.cfg stm3241g_eval.cfg
1412 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1413 hammer.cfg stm32f0discovery.cfg
1414 hilscher_nxdb500sys.cfg stm32f3discovery.cfg
1415 hilscher_nxeb500hmi.cfg stm32f4discovery.cfg
1416 hilscher_nxhx10.cfg stm32ldiscovery.cfg
1417 hilscher_nxhx500.cfg stm32vldiscovery.cfg
1418 hilscher_nxhx50.cfg str910-eval.cfg
1419 hilscher_nxsb100.cfg telo.cfg
1420 hitex_lpc1768stick.cfg ti_am335xevm.cfg
1421 hitex_lpc2929.cfg ti_beagleboard.cfg
1422 hitex_stm32-performancestick.cfg ti_beagleboard_xm.cfg
1423 hitex_str9-comstick.cfg ti_beaglebone.cfg
1424 iar_lpc1768.cfg ti_blaze.cfg
1425 iar_str912_sk.cfg ti_pandaboard.cfg
1426 icnova_imx53_sodimm.cfg ti_pandaboard_es.cfg
1427 icnova_sam9g45_sodimm.cfg topas910.cfg
1428 imx27ads.cfg topasa900.cfg
1429 imx27lnst.cfg twr-k60f120m.cfg
1430 imx28evk.cfg twr-k60n512.cfg
1431 imx31pdk.cfg tx25_stk5.cfg
1432 imx35pdk.cfg tx27_stk5.cfg
1433 imx53loco.cfg unknown_at91sam9260.cfg
1434 keil_mcb1700.cfg uptech_2410.cfg
1435 keil_mcb2140.cfg verdex.cfg
1436 kwikstik.cfg voipac.cfg
1437 linksys_nslu2.cfg voltcraft_dso-3062c.cfg
1438 lisa-l.cfg x300t.cfg
1439 logicpd_imx27.cfg zy1000.cfg
1440 $
1441 @end example
1442 @item @file{target} ...
1443 think chip. The ``target'' directory represents the JTAG TAPs
1444 on a chip
1445 which OpenOCD should control, not a board. Two common types of targets
1446 are ARM chips and FPGA or CPLD chips.
1447 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1448 the target config file defines all of them.
1449 @example
1450 $ ls target
1451 aduc702x.cfg lpc1763.cfg
1452 am335x.cfg lpc1764.cfg
1453 amdm37x.cfg lpc1765.cfg
1454 ar71xx.cfg lpc1766.cfg
1455 at32ap7000.cfg lpc1767.cfg
1456 at91r40008.cfg lpc1768.cfg
1457 at91rm9200.cfg lpc1769.cfg
1458 at91sam3ax_4x.cfg lpc1788.cfg
1459 at91sam3ax_8x.cfg lpc17xx.cfg
1460 at91sam3ax_xx.cfg lpc1850.cfg
1461 at91sam3nXX.cfg lpc2103.cfg
1462 at91sam3sXX.cfg lpc2124.cfg
1463 at91sam3u1c.cfg lpc2129.cfg
1464 at91sam3u1e.cfg lpc2148.cfg
1465 at91sam3u2c.cfg lpc2294.cfg
1466 at91sam3u2e.cfg lpc2378.cfg
1467 at91sam3u4c.cfg lpc2460.cfg
1468 at91sam3u4e.cfg lpc2478.cfg
1469 at91sam3uxx.cfg lpc2900.cfg
1470 at91sam3XXX.cfg lpc2xxx.cfg
1471 at91sam4sd32x.cfg lpc3131.cfg
1472 at91sam4sXX.cfg lpc3250.cfg
1473 at91sam4XXX.cfg lpc4350.cfg
1474 at91sam7se512.cfg lpc4350.cfg.orig
1475 at91sam7sx.cfg mc13224v.cfg
1476 at91sam7x256.cfg nuc910.cfg
1477 at91sam7x512.cfg omap2420.cfg
1478 at91sam9260.cfg omap3530.cfg
1479 at91sam9260_ext_RAM_ext_flash.cfg omap4430.cfg
1480 at91sam9261.cfg omap4460.cfg
1481 at91sam9263.cfg omap5912.cfg
1482 at91sam9.cfg omapl138.cfg
1483 at91sam9g10.cfg pic32mx.cfg
1484 at91sam9g20.cfg pxa255.cfg
1485 at91sam9g45.cfg pxa270.cfg
1486 at91sam9rl.cfg pxa3xx.cfg
1487 atmega128.cfg readme.txt
1488 avr32.cfg samsung_s3c2410.cfg
1489 c100.cfg samsung_s3c2440.cfg
1490 c100config.tcl samsung_s3c2450.cfg
1491 c100helper.tcl samsung_s3c4510.cfg
1492 c100regs.tcl samsung_s3c6410.cfg
1493 cs351x.cfg sharp_lh79532.cfg
1494 davinci.cfg smp8634.cfg
1495 dragonite.cfg spear3xx.cfg
1496 dsp56321.cfg stellaris.cfg
1497 dsp568013.cfg stellaris_icdi.cfg
1498 dsp568037.cfg stm32f0x_stlink.cfg
1499 efm32_stlink.cfg stm32f1x.cfg
1500 epc9301.cfg stm32f1x_stlink.cfg
1501 faux.cfg stm32f2x.cfg
1502 feroceon.cfg stm32f2x_stlink.cfg
1503 fm3.cfg stm32f3x.cfg
1504 hilscher_netx10.cfg stm32f3x_stlink.cfg
1505 hilscher_netx500.cfg stm32f4x.cfg
1506 hilscher_netx50.cfg stm32f4x_stlink.cfg
1507 icepick.cfg stm32l.cfg
1508 imx21.cfg stm32lx_dual_bank.cfg
1509 imx25.cfg stm32lx_stlink.cfg
1510 imx27.cfg stm32_stlink.cfg
1511 imx28.cfg stm32w108_stlink.cfg
1512 imx31.cfg stm32xl.cfg
1513 imx35.cfg str710.cfg
1514 imx51.cfg str730.cfg
1515 imx53.cfg str750.cfg
1516 imx6.cfg str912.cfg
1517 imx.cfg swj-dp.tcl
1518 is5114.cfg test_reset_syntax_error.cfg
1519 ixp42x.cfg test_syntax_error.cfg
1520 k40.cfg ti-ar7.cfg
1521 k60.cfg ti_calypso.cfg
1522 lpc1751.cfg ti_dm355.cfg
1523 lpc1752.cfg ti_dm365.cfg
1524 lpc1754.cfg ti_dm6446.cfg
1525 lpc1756.cfg tmpa900.cfg
1526 lpc1758.cfg tmpa910.cfg
1527 lpc1759.cfg u8500.cfg
1528 @end example
1529 @item @emph{more} ... browse for other library files which may be useful.
1530 For example, there are various generic and CPU-specific utilities.
1531 @end itemize
1533 The @file{openocd.cfg} user config
1534 file may override features in any of the above files by
1535 setting variables before sourcing the target file, or by adding
1536 commands specific to their situation.
1538 @section Interface Config Files
1540 The user config file
1541 should be able to source one of these files with a command like this:
1543 @example
1544 source [find interface/FOOBAR.cfg]
1545 @end example
1547 A preconfigured interface file should exist for every debug adapter
1548 in use today with OpenOCD.
1549 That said, perhaps some of these config files
1550 have only been used by the developer who created it.
1552 A separate chapter gives information about how to set these up.
1553 @xref{Debug Adapter Configuration}.
1554 Read the OpenOCD source code (and Developer's Guide)
1555 if you have a new kind of hardware interface
1556 and need to provide a driver for it.
1558 @section Board Config Files
1559 @cindex config file, board
1560 @cindex board config file
1562 The user config file
1563 should be able to source one of these files with a command like this:
1565 @example
1566 source [find board/FOOBAR.cfg]
1567 @end example
1569 The point of a board config file is to package everything
1570 about a given board that user config files need to know.
1571 In summary the board files should contain (if present)
1573 @enumerate
1574 @item One or more @command{source [find target/...cfg]} statements
1575 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1576 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1577 @item Target @code{reset} handlers for SDRAM and I/O configuration
1578 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1579 @item All things that are not ``inside a chip''
1580 @end enumerate
1582 Generic things inside target chips belong in target config files,
1583 not board config files. So for example a @code{reset-init} event
1584 handler should know board-specific oscillator and PLL parameters,
1585 which it passes to target-specific utility code.
1587 The most complex task of a board config file is creating such a
1588 @code{reset-init} event handler.
1589 Define those handlers last, after you verify the rest of the board
1590 configuration works.
1592 @subsection Communication Between Config files
1594 In addition to target-specific utility code, another way that
1595 board and target config files communicate is by following a
1596 convention on how to use certain variables.
1598 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1599 Thus the rule we follow in OpenOCD is this: Variables that begin with
1600 a leading underscore are temporary in nature, and can be modified and
1601 used at will within a target configuration file.
1603 Complex board config files can do the things like this,
1604 for a board with three chips:
1606 @example
1607 # Chip #1: PXA270 for network side, big endian
1608 set CHIPNAME network
1609 set ENDIAN big
1610 source [find target/pxa270.cfg]
1611 # on return: _TARGETNAME = network.cpu
1612 # other commands can refer to the "network.cpu" target.
1613 $_TARGETNAME configure .... events for this CPU..
1615 # Chip #2: PXA270 for video side, little endian
1616 set CHIPNAME video
1617 set ENDIAN little
1618 source [find target/pxa270.cfg]
1619 # on return: _TARGETNAME = video.cpu
1620 # other commands can refer to the "video.cpu" target.
1621 $_TARGETNAME configure .... events for this CPU..
1623 # Chip #3: Xilinx FPGA for glue logic
1624 set CHIPNAME xilinx
1625 unset ENDIAN
1626 source [find target/spartan3.cfg]
1627 @end example
1629 That example is oversimplified because it doesn't show any flash memory,
1630 or the @code{reset-init} event handlers to initialize external DRAM
1631 or (assuming it needs it) load a configuration into the FPGA.
1632 Such features are usually needed for low-level work with many boards,
1633 where ``low level'' implies that the board initialization software may
1634 not be working. (That's a common reason to need JTAG tools. Another
1635 is to enable working with microcontroller-based systems, which often
1636 have no debugging support except a JTAG connector.)
1638 Target config files may also export utility functions to board and user
1639 config files. Such functions should use name prefixes, to help avoid
1640 naming collisions.
1642 Board files could also accept input variables from user config files.
1643 For example, there might be a @code{J4_JUMPER} setting used to identify
1644 what kind of flash memory a development board is using, or how to set
1645 up other clocks and peripherals.
1647 @subsection Variable Naming Convention
1648 @cindex variable names
1650 Most boards have only one instance of a chip.
1651 However, it should be easy to create a board with more than
1652 one such chip (as shown above).
1653 Accordingly, we encourage these conventions for naming
1654 variables associated with different @file{target.cfg} files,
1655 to promote consistency and
1656 so that board files can override target defaults.
1658 Inputs to target config files include:
1660 @itemize @bullet
1661 @item @code{CHIPNAME} ...
1662 This gives a name to the overall chip, and is used as part of
1663 tap identifier dotted names.
1664 While the default is normally provided by the chip manufacturer,
1665 board files may need to distinguish between instances of a chip.
1666 @item @code{ENDIAN} ...
1667 By default @option{little} - although chips may hard-wire @option{big}.
1668 Chips that can't change endianness don't need to use this variable.
1669 @item @code{CPUTAPID} ...
1670 When OpenOCD examines the JTAG chain, it can be told verify the
1671 chips against the JTAG IDCODE register.
1672 The target file will hold one or more defaults, but sometimes the
1673 chip in a board will use a different ID (perhaps a newer revision).
1674 @end itemize
1676 Outputs from target config files include:
1678 @itemize @bullet
1679 @item @code{_TARGETNAME} ...
1680 By convention, this variable is created by the target configuration
1681 script. The board configuration file may make use of this variable to
1682 configure things like a ``reset init'' script, or other things
1683 specific to that board and that target.
1684 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1685 @code{_TARGETNAME1}, ... etc.
1686 @end itemize
1688 @subsection The reset-init Event Handler
1689 @cindex event, reset-init
1690 @cindex reset-init handler
1692 Board config files run in the OpenOCD configuration stage;
1693 they can't use TAPs or targets, since they haven't been
1694 fully set up yet.
1695 This means you can't write memory or access chip registers;
1696 you can't even verify that a flash chip is present.
1697 That's done later in event handlers, of which the target @code{reset-init}
1698 handler is one of the most important.
1700 Except on microcontrollers, the basic job of @code{reset-init} event
1701 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1702 Microcontrollers rarely use boot loaders; they run right out of their
1703 on-chip flash and SRAM memory. But they may want to use one of these
1704 handlers too, if just for developer convenience.
1706 @quotation Note
1707 Because this is so very board-specific, and chip-specific, no examples
1708 are included here.
1709 Instead, look at the board config files distributed with OpenOCD.
1710 If you have a boot loader, its source code will help; so will
1711 configuration files for other JTAG tools
1712 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1713 @end quotation
1715 Some of this code could probably be shared between different boards.
1716 For example, setting up a DRAM controller often doesn't differ by
1717 much except the bus width (16 bits or 32?) and memory timings, so a
1718 reusable TCL procedure loaded by the @file{target.cfg} file might take
1719 those as parameters.
1720 Similarly with oscillator, PLL, and clock setup;
1721 and disabling the watchdog.
1722 Structure the code cleanly, and provide comments to help
1723 the next developer doing such work.
1724 (@emph{You might be that next person} trying to reuse init code!)
1726 The last thing normally done in a @code{reset-init} handler is probing
1727 whatever flash memory was configured. For most chips that needs to be
1728 done while the associated target is halted, either because JTAG memory
1729 access uses the CPU or to prevent conflicting CPU access.
1731 @subsection JTAG Clock Rate
1733 Before your @code{reset-init} handler has set up
1734 the PLLs and clocking, you may need to run with
1735 a low JTAG clock rate.
1736 @xref{jtagspeed,,JTAG Speed}.
1737 Then you'd increase that rate after your handler has
1738 made it possible to use the faster JTAG clock.
1739 When the initial low speed is board-specific, for example
1740 because it depends on a board-specific oscillator speed, then
1741 you should probably set it up in the board config file;
1742 if it's target-specific, it belongs in the target config file.
1744 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1745 @uref{} gives details.}
1746 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1747 Consult chip documentation to determine the peak JTAG clock rate,
1748 which might be less than that.
1750 @quotation Warning
1751 On most ARMs, JTAG clock detection is coupled to the core clock, so
1752 software using a @option{wait for interrupt} operation blocks JTAG access.
1753 Adaptive clocking provides a partial workaround, but a more complete
1754 solution just avoids using that instruction with JTAG debuggers.
1755 @end quotation
1757 If both the chip and the board support adaptive clocking,
1758 use the @command{jtag_rclk}
1759 command, in case your board is used with JTAG adapter which
1760 also supports it. Otherwise use @command{adapter_khz}.
1761 Set the slow rate at the beginning of the reset sequence,
1762 and the faster rate as soon as the clocks are at full speed.
1764 @anchor{theinitboardprocedure}
1765 @subsection The init_board procedure
1766 @cindex init_board procedure
1768 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1769 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1770 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1771 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1772 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1773 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1774 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1775 Additionally ``linear'' board config file will most likely fail when target config file uses
1776 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1777 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1778 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1779 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1781 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1782 the original), allowing greater code reuse.
1784 @example
1785 ### board_file.cfg ###
1787 # source target file that does most of the config in init_targets
1788 source [find target/target.cfg]
1790 proc enable_fast_clock @{@} @{
1791 # enables fast on-board clock source
1792 # configures the chip to use it
1793 @}
1795 # initialize only board specifics - reset, clock, adapter frequency
1796 proc init_board @{@} @{
1797 reset_config trst_and_srst trst_pulls_srst
1799 $_TARGETNAME configure -event reset-init @{
1800 adapter_khz 1
1801 enable_fast_clock
1802 adapter_khz 10000
1803 @}
1804 @}
1805 @end example
1807 @section Target Config Files
1808 @cindex config file, target
1809 @cindex target config file
1811 Board config files communicate with target config files using
1812 naming conventions as described above, and may source one or
1813 more target config files like this:
1815 @example
1816 source [find target/FOOBAR.cfg]
1817 @end example
1819 The point of a target config file is to package everything
1820 about a given chip that board config files need to know.
1821 In summary the target files should contain
1823 @enumerate
1824 @item Set defaults
1825 @item Add TAPs to the scan chain
1826 @item Add CPU targets (includes GDB support)
1827 @item CPU/Chip/CPU-Core specific features
1828 @item On-Chip flash
1829 @end enumerate
1831 As a rule of thumb, a target file sets up only one chip.
1832 For a microcontroller, that will often include a single TAP,
1833 which is a CPU needing a GDB target, and its on-chip flash.
1835 More complex chips may include multiple TAPs, and the target
1836 config file may need to define them all before OpenOCD
1837 can talk to the chip.
1838 For example, some phone chips have JTAG scan chains that include
1839 an ARM core for operating system use, a DSP,
1840 another ARM core embedded in an image processing engine,
1841 and other processing engines.
1843 @subsection Default Value Boiler Plate Code
1845 All target configuration files should start with code like this,
1846 letting board config files express environment-specific
1847 differences in how things should be set up.
1849 @example
1850 # Boards may override chip names, perhaps based on role,
1851 # but the default should match what the vendor uses
1852 if @{ [info exists CHIPNAME] @} @{
1854 @} else @{
1855 set _CHIPNAME sam7x256
1856 @}
1858 # ONLY use ENDIAN with targets that can change it.
1859 if @{ [info exists ENDIAN] @} @{
1860 set _ENDIAN $ENDIAN
1861 @} else @{
1862 set _ENDIAN little
1863 @}
1865 # TAP identifiers may change as chips mature, for example with
1866 # new revision fields (the "3" here). Pick a good default; you
1867 # can pass several such identifiers to the "jtag newtap" command.
1868 if @{ [info exists CPUTAPID ] @} @{
1870 @} else @{
1871 set _CPUTAPID 0x3f0f0f0f
1872 @}
1873 @end example
1874 @c but 0x3f0f0f0f is for an str73x part ...
1876 @emph{Remember:} Board config files may include multiple target
1877 config files, or the same target file multiple times
1878 (changing at least @code{CHIPNAME}).
1880 Likewise, the target configuration file should define
1881 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1882 use it later on when defining debug targets:
1884 @example
1886 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1887 @end example
1889 @subsection Adding TAPs to the Scan Chain
1890 After the ``defaults'' are set up,
1891 add the TAPs on each chip to the JTAG scan chain.
1892 @xref{TAP Declaration}, and the naming convention
1893 for taps.
1895 In the simplest case the chip has only one TAP,
1896 probably for a CPU or FPGA.
1897 The config file for the Atmel AT91SAM7X256
1898 looks (in part) like this:
1900 @example
1901 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1902 @end example
1904 A board with two such at91sam7 chips would be able
1905 to source such a config file twice, with different
1906 values for @code{CHIPNAME}, so
1907 it adds a different TAP each time.
1909 If there are nonzero @option{-expected-id} values,
1910 OpenOCD attempts to verify the actual tap id against those values.
1911 It will issue error messages if there is mismatch, which
1912 can help to pinpoint problems in OpenOCD configurations.
1914 @example
1915 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1916 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1917 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1918 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1919 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1920 @end example
1922 There are more complex examples too, with chips that have
1923 multiple TAPs. Ones worth looking at include:
1925 @itemize
1926 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1927 plus a JRC to enable them
1928 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1929 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1930 is not currently used)
1931 @end itemize
1933 @subsection Add CPU targets
1935 After adding a TAP for a CPU, you should set it up so that
1936 GDB and other commands can use it.
1937 @xref{CPU Configuration}.
1938 For the at91sam7 example above, the command can look like this;
1939 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1940 to little endian, and this chip doesn't support changing that.
1942 @example
1944 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1945 @end example
1947 Work areas are small RAM areas associated with CPU targets.
1948 They are used by OpenOCD to speed up downloads,
1949 and to download small snippets of code to program flash chips.
1950 If the chip includes a form of ``on-chip-ram'' - and many do - define
1951 a work area if you can.
1952 Again using the at91sam7 as an example, this can look like:
1954 @example
1955 $_TARGETNAME configure -work-area-phys 0x00200000 \
1956 -work-area-size 0x4000 -work-area-backup 0
1957 @end example
1959 @anchor{definecputargetsworkinginsmp}
1960 @subsection Define CPU targets working in SMP
1961 @cindex SMP
1962 After setting targets, you can define a list of targets working in SMP.
1964 @example
1965 set _TARGETNAME_1 $_CHIPNAME.cpu1
1966 set _TARGETNAME_2 $_CHIPNAME.cpu2
1967 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1968 -coreid 0 -dbgbase $_DAP_DBG1
1969 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1970 -coreid 1 -dbgbase $_DAP_DBG2
1971 #define 2 targets working in smp.
1972 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1973 @end example
1974 In the above example on cortex_a, 2 cpus are working in SMP.
1975 In SMP only one GDB instance is created and :
1976 @itemize @bullet
1977 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1978 @item halt command triggers the halt of all targets in the list.
1979 @item resume command triggers the write context and the restart of all targets in the list.
1980 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1981 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1982 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1983 @end itemize
1985 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1986 command have been implemented.
1987 @itemize @bullet
1988 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1989 @item cortex_a smp_off : disable SMP mode, the current target is the one
1990 displayed in the GDB session, only this target is now controlled by GDB
1991 session. This behaviour is useful during system boot up.
1992 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1993 following example.
1994 @end itemize
1996 @example
1997 >cortex_a smp_gdb
1998 gdb coreid 0 -> -1
1999 #0 : coreid 0 is displayed to GDB ,
2000 #-> -1 : next resume triggers a real resume
2001 > cortex_a smp_gdb 1
2002 gdb coreid 0 -> 1
2003 #0 :coreid 0 is displayed to GDB ,
2004 #->1 : next resume displays coreid 1 to GDB
2005 > resume
2006 > cortex_a smp_gdb
2007 gdb coreid 1 -> 1
2008 #1 :coreid 1 is displayed to GDB ,
2009 #->1 : next resume displays coreid 1 to GDB
2010 > cortex_a smp_gdb -1
2011 gdb coreid 1 -> -1
2012 #1 :coreid 1 is displayed to GDB,
2013 #->-1 : next resume triggers a real resume
2014 @end example
2017 @subsection Chip Reset Setup
2019 As a rule, you should put the @command{reset_config} command
2020 into the board file. Most things you think you know about a
2021 chip can be tweaked by the board.
2023 Some chips have specific ways the TRST and SRST signals are
2024 managed. In the unusual case that these are @emph{chip specific}
2025 and can never be changed by board wiring, they could go here.
2026 For example, some chips can't support JTAG debugging without
2027 both signals.
2029 Provide a @code{reset-assert} event handler if you can.
2030 Such a handler uses JTAG operations to reset the target,
2031 letting this target config be used in systems which don't
2032 provide the optional SRST signal, or on systems where you
2033 don't want to reset all targets at once.
2034 Such a handler might write to chip registers to force a reset,
2035 use a JRC to do that (preferable -- the target may be wedged!),
2036 or force a watchdog timer to trigger.
2037 (For Cortex-M targets, this is not necessary. The target
2038 driver knows how to use trigger an NVIC reset when SRST is
2039 not available.)
2041 Some chips need special attention during reset handling if
2042 they're going to be used with JTAG.
2043 An example might be needing to send some commands right
2044 after the target's TAP has been reset, providing a
2045 @code{reset-deassert-post} event handler that writes a chip
2046 register to report that JTAG debugging is being done.
2047 Another would be reconfiguring the watchdog so that it stops
2048 counting while the core is halted in the debugger.
2050 JTAG clocking constraints often change during reset, and in
2051 some cases target config files (rather than board config files)
2052 are the right places to handle some of those issues.
2053 For example, immediately after reset most chips run using a
2054 slower clock than they will use later.
2055 That means that after reset (and potentially, as OpenOCD
2056 first starts up) they must use a slower JTAG clock rate
2057 than they will use later.
2058 @xref{jtagspeed,,JTAG Speed}.
2060 @quotation Important
2061 When you are debugging code that runs right after chip
2062 reset, getting these issues right is critical.
2063 In particular, if you see intermittent failures when
2064 OpenOCD verifies the scan chain after reset,
2065 look at how you are setting up JTAG clocking.
2066 @end quotation
2068 @anchor{theinittargetsprocedure}
2069 @subsection The init_targets procedure
2070 @cindex init_targets procedure
2072 Target config files can either be ``linear'' (script executed line-by-line when parsed in
2073 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
2074 procedure called @code{init_targets}, which will be executed when entering run stage
2075 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
2076 Such procedure can be overriden by ``next level'' script (which sources the original).
2077 This concept faciliates code reuse when basic target config files provide generic configuration
2078 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
2079 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
2080 because sourcing them executes every initialization commands they provide.
2082 @example
2083 ### generic_file.cfg ###
2085 proc setup_my_chip @{chip_name flash_size ram_size@} @{
2086 # basic initialization procedure ...
2087 @}
2089 proc init_targets @{@} @{
2090 # initializes generic chip with 4kB of flash and 1kB of RAM
2091 setup_my_chip MY_GENERIC_CHIP 4096 1024
2092 @}
2094 ### specific_file.cfg ###
2096 source [find target/generic_file.cfg]
2098 proc init_targets @{@} @{
2099 # initializes specific chip with 128kB of flash and 64kB of RAM
2100 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
2101 @}
2102 @end example
2104 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
2105 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
2107 For an example of this scheme see LPC2000 target config files.
2109 The @code{init_boards} procedure is a similar concept concerning board config files
2110 (@xref{theinitboardprocedure,,The init_board procedure}.)
2112 @subsection ARM Core Specific Hacks
2114 If the chip has a DCC, enable it. If the chip is an ARM9 with some
2115 special high speed download features - enable it.
2117 If present, the MMU, the MPU and the CACHE should be disabled.
2119 Some ARM cores are equipped with trace support, which permits
2120 examination of the instruction and data bus activity. Trace
2121 activity is controlled through an ``Embedded Trace Module'' (ETM)
2122 on one of the core's scan chains. The ETM emits voluminous data
2123 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
2124 If you are using an external trace port,
2125 configure it in your board config file.
2126 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2127 configure it in your target config file.
2129 @example
2130 etm config $_TARGETNAME 16 normal full etb
2131 etb config $_TARGETNAME $_CHIPNAME.etb
2132 @end example
2134 @subsection Internal Flash Configuration
2136 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2138 @b{Never ever} in the ``target configuration file'' define any type of
2139 flash that is external to the chip. (For example a BOOT flash on
2140 Chip Select 0.) Such flash information goes in a board file - not
2141 the TARGET (chip) file.
2143 Examples:
2144 @itemize @bullet
2145 @item at91sam7x256 - has 256K flash YES enable it.
2146 @item str912 - has flash internal YES enable it.
2147 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2148 @item pxa270 - again - CS0 flash - it goes in the board file.
2149 @end itemize
2151 @anchor{translatingconfigurationfiles}
2152 @section Translating Configuration Files
2153 @cindex translation
2154 If you have a configuration file for another hardware debugger
2155 or toolset (Abatron, BDI2000, BDI3000, CCS,
2156 Lauterbach, Segger, Macraigor, etc.), translating
2157 it into OpenOCD syntax is often quite straightforward. The most tricky
2158 part of creating a configuration script is oftentimes the reset init
2159 sequence where e.g. PLLs, DRAM and the like is set up.
2161 One trick that you can use when translating is to write small
2162 Tcl procedures to translate the syntax into OpenOCD syntax. This
2163 can avoid manual translation errors and make it easier to
2164 convert other scripts later on.
2166 Example of transforming quirky arguments to a simple search and
2167 replace job:
2169 @example
2170 # Lauterbach syntax(?)
2171 #
2172 # Data.Set c15:0x042f %long 0x40000015
2173 #
2174 # OpenOCD syntax when using procedure below.
2175 #
2176 # setc15 0x01 0x00050078
2178 proc setc15 @{regs value@} @{
2179 global TARGETNAME
2181 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2183 arm mcr 15 [expr ($regs>>12)&0x7] \
2184 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2185 [expr ($regs>>8)&0x7] $value
2186 @}
2187 @end example
2191 @node Daemon Configuration
2192 @chapter Daemon Configuration
2193 @cindex initialization
2194 The commands here are commonly found in the openocd.cfg file and are
2195 used to specify what TCP/IP ports are used, and how GDB should be
2196 supported.
2198 @anchor{configurationstage}
2199 @section Configuration Stage
2200 @cindex configuration stage
2201 @cindex config command
2203 When the OpenOCD server process starts up, it enters a
2204 @emph{configuration stage} which is the only time that
2205 certain commands, @emph{configuration commands}, may be issued.
2206 Normally, configuration commands are only available
2207 inside startup scripts.
2209 In this manual, the definition of a configuration command is
2210 presented as a @emph{Config Command}, not as a @emph{Command}
2211 which may be issued interactively.
2212 The runtime @command{help} command also highlights configuration
2213 commands, and those which may be issued at any time.
2215 Those configuration commands include declaration of TAPs,
2216 flash banks,
2217 the interface used for JTAG communication,
2218 and other basic setup.
2219 The server must leave the configuration stage before it
2220 may access or activate TAPs.
2221 After it leaves this stage, configuration commands may no
2222 longer be issued.
2224 @anchor{enteringtherunstage}
2225 @section Entering the Run Stage
2227 The first thing OpenOCD does after leaving the configuration
2228 stage is to verify that it can talk to the scan chain
2229 (list of TAPs) which has been configured.
2230 It will warn if it doesn't find TAPs it expects to find,
2231 or finds TAPs that aren't supposed to be there.
2232 You should see no errors at this point.
2233 If you see errors, resolve them by correcting the
2234 commands you used to configure the server.
2235 Common errors include using an initial JTAG speed that's too
2236 fast, and not providing the right IDCODE values for the TAPs
2237 on the scan chain.
2239 Once OpenOCD has entered the run stage, a number of commands
2240 become available.
2241 A number of these relate to the debug targets you may have declared.
2242 For example, the @command{mww} command will not be available until
2243 a target has been successfuly instantiated.
2244 If you want to use those commands, you may need to force
2245 entry to the run stage.
2247 @deffn {Config Command} init
2248 This command terminates the configuration stage and
2249 enters the run stage. This helps when you need to have
2250 the startup scripts manage tasks such as resetting the target,
2251 programming flash, etc. To reset the CPU upon startup, add "init" and
2252 "reset" at the end of the config script or at the end of the OpenOCD
2253 command line using the @option{-c} command line switch.
2255 If this command does not appear in any startup/configuration file
2256 OpenOCD executes the command for you after processing all
2257 configuration files and/or command line options.
2259 @b{NOTE:} This command normally occurs at or near the end of your
2260 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2261 targets ready. For example: If your openocd.cfg file needs to
2262 read/write memory on your target, @command{init} must occur before
2263 the memory read/write commands. This includes @command{nand probe}.
2264 @end deffn
2266 @deffn {Overridable Procedure} jtag_init
2267 This is invoked at server startup to verify that it can talk
2268 to the scan chain (list of TAPs) which has been configured.
2270 The default implementation first tries @command{jtag arp_init},
2271 which uses only a lightweight JTAG reset before examining the
2272 scan chain.
2273 If that fails, it tries again, using a harder reset
2274 from the overridable procedure @command{init_reset}.
2276 Implementations must have verified the JTAG scan chain before
2277 they return.
2278 This is done by calling @command{jtag arp_init}
2279 (or @command{jtag arp_init-reset}).
2280 @end deffn
2282 @anchor{tcpipports}
2283 @section TCP/IP Ports
2284 @cindex TCP port
2285 @cindex server
2286 @cindex port
2287 @cindex security
2288 The OpenOCD server accepts remote commands in several syntaxes.
2289 Each syntax uses a different TCP/IP port, which you may specify
2290 only during configuration (before those ports are opened).
2292 For reasons including security, you may wish to prevent remote
2293 access using one or more of these ports.
2294 In such cases, just specify the relevant port number as zero.
2295 If you disable all access through TCP/IP, you will need to
2296 use the command line @option{-pipe} option.
2298 @deffn {Command} gdb_port [number]
2299 @cindex GDB server
2300 Normally gdb listens to a TCP/IP port, but GDB can also
2301 communicate via pipes(stdin/out or named pipes). The name
2302 "gdb_port" stuck because it covers probably more than 90% of
2303 the normal use cases.
2305 No arguments reports GDB port. "pipe" means listen to stdin
2306 output to stdout, an integer is base port number, "disable"
2307 disables the gdb server.
2309 When using "pipe", also use log_output to redirect the log
2310 output to a file so as not to flood the stdin/out pipes.
2312 The -p/--pipe option is deprecated and a warning is printed
2313 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2315 Any other string is interpreted as named pipe to listen to.
2316 Output pipe is the same name as input pipe, but with 'o' appended,
2317 e.g. /var/gdb, /var/gdbo.
2319 The GDB port for the first target will be the base port, the
2320 second target will listen on gdb_port + 1, and so on.
2321 When not specified during the configuration stage,
2322 the port @var{number} defaults to 3333.
2323 @end deffn
2325 @deffn {Command} tcl_port [number]
2326 Specify or query the port used for a simplified RPC
2327 connection that can be used by clients to issue TCL commands and get the
2328 output from the Tcl engine.
2329 Intended as a machine interface.
2330 When not specified during the configuration stage,
2331 the port @var{number} defaults to 6666.
2333 @end deffn
2335 @deffn {Command} telnet_port [number]
2336 Specify or query the
2337 port on which to listen for incoming telnet connections.
2338 This port is intended for interaction with one human through TCL commands.
2339 When not specified during the configuration stage,
2340 the port @var{number} defaults to 4444.
2341 When specified as zero, this port is not activated.
2342 @end deffn
2344 @anchor{gdbconfiguration}
2345 @section GDB Configuration
2346 @cindex GDB
2347 @cindex GDB configuration
2348 You can reconfigure some GDB behaviors if needed.
2349 The ones listed here are static and global.
2350 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2351 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2353 @anchor{gdbbreakpointoverride}
2354 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2355 Force breakpoint type for gdb @command{break} commands.
2356 This option supports GDB GUIs which don't
2357 distinguish hard versus soft breakpoints, if the default OpenOCD and
2358 GDB behaviour is not sufficient. GDB normally uses hardware
2359 breakpoints if the memory map has been set up for flash regions.
2360 @end deffn
2362 @anchor{gdbflashprogram}
2363 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2364 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2365 vFlash packet is received.
2366 The default behaviour is @option{enable}.
2367 @end deffn
2369 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2370 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2371 requested. GDB will then know when to set hardware breakpoints, and program flash
2372 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2373 for flash programming to work.
2374 Default behaviour is @option{enable}.
2375 @xref{gdbflashprogram,,gdb_flash_program}.
2376 @end deffn
2378 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2379 Specifies whether data aborts cause an error to be reported
2380 by GDB memory read packets.
2381 The default behaviour is @option{disable};
2382 use @option{enable} see these errors reported.
2383 @end deffn
2385 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2386 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2387 The default behaviour is @option{disable}.
2388 @end deffn
2390 @deffn {Command} gdb_save_tdesc
2391 Saves the target descripton file to the local file system.
2393 The file name is @i{target_name}.xml.
2394 @end deffn
2396 @anchor{eventpolling}
2397 @section Event Polling
2399 Hardware debuggers are parts of asynchronous systems,
2400 where significant events can happen at any time.
2401 The OpenOCD server needs to detect some of these events,
2402 so it can report them to through TCL command line
2403 or to GDB.
2405 Examples of such events include:
2407 @itemize
2408 @item One of the targets can stop running ... maybe it triggers
2409 a code breakpoint or data watchpoint, or halts itself.
2410 @item Messages may be sent over ``debug message'' channels ... many
2411 targets support such messages sent over JTAG,
2412 for receipt by the person debugging or tools.
2413 @item Loss of power ... some adapters can detect these events.
2414 @item Resets not issued through JTAG ... such reset sources
2415 can include button presses or other system hardware, sometimes
2416 including the target itself (perhaps through a watchdog).
2417 @item Debug instrumentation sometimes supports event triggering
2418 such as ``trace buffer full'' (so it can quickly be emptied)
2419 or other signals (to correlate with code behavior).
2420 @end itemize
2422 None of those events are signaled through standard JTAG signals.
2423 However, most conventions for JTAG connectors include voltage
2424 level and system reset (SRST) signal detection.
2425 Some connectors also include instrumentation signals, which
2426 can imply events when those signals are inputs.
2428 In general, OpenOCD needs to periodically check for those events,
2429 either by looking at the status of signals on the JTAG connector
2430 or by sending synchronous ``tell me your status'' JTAG requests
2431 to the various active targets.
2432 There is a command to manage and monitor that polling,
2433 which is normally done in the background.
2435 @deffn Command poll [@option{on}|@option{off}]
2436 Poll the current target for its current state.
2437 (Also, @pxref{targetcurstate,,target curstate}.)
2438 If that target is in debug mode, architecture
2439 specific information about the current state is printed.
2440 An optional parameter
2441 allows background polling to be enabled and disabled.
2443 You could use this from the TCL command shell, or
2444 from GDB using @command{monitor poll} command.
2445 Leave background polling enabled while you're using GDB.
2446 @example
2447 > poll
2448 background polling: on
2449 target state: halted
2450 target halted in ARM state due to debug-request, \
2451 current mode: Supervisor
2452 cpsr: 0x800000d3 pc: 0x11081bfc
2453 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2454 >
2455 @end example
2456 @end deffn
2458 @node Debug Adapter Configuration
2459 @chapter Debug Adapter Configuration
2460 @cindex config file, interface
2461 @cindex interface config file
2463 Correctly installing OpenOCD includes making your operating system give
2464 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2465 are used to select which one is used, and to configure how it is used.
2467 @quotation Note
2468 Because OpenOCD started out with a focus purely on JTAG, you may find
2469 places where it wrongly presumes JTAG is the only transport protocol
2470 in use. Be aware that recent versions of OpenOCD are removing that
2471 limitation. JTAG remains more functional than most other transports.
2472 Other transports do not support boundary scan operations, or may be
2473 specific to a given chip vendor. Some might be usable only for
2474 programming flash memory, instead of also for debugging.
2475 @end quotation
2477 Debug Adapters/Interfaces/Dongles are normally configured
2478 through commands in an interface configuration
2479 file which is sourced by your @file{openocd.cfg} file, or
2480 through a command line @option{-f interface/....cfg} option.
2482 @example
2483 source [find interface/olimex-jtag-tiny.cfg]
2484 @end example
2486 These commands tell
2487 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2488 A few cases are so simple that you only need to say what driver to use:
2490 @example
2491 # jlink interface
2492 interface jlink
2493 @end example
2495 Most adapters need a bit more configuration than that.
2498 @section Interface Configuration
2500 The interface command tells OpenOCD what type of debug adapter you are
2501 using. Depending on the type of adapter, you may need to use one or
2502 more additional commands to further identify or configure the adapter.
2504 @deffn {Config Command} {interface} name
2505 Use the interface driver @var{name} to connect to the
2506 target.
2507 @end deffn
2509 @deffn Command {interface_list}
2510 List the debug adapter drivers that have been built into
2511 the running copy of OpenOCD.
2512 @end deffn
2513 @deffn Command {interface transports} transport_name+
2514 Specifies the transports supported by this debug adapter.
2515 The adapter driver builds-in similar knowledge; use this only
2516 when external configuration (such as jumpering) changes what
2517 the hardware can support.
2518 @end deffn
2522 @deffn Command {adapter_name}
2523 Returns the name of the debug adapter driver being used.
2524 @end deffn
2526 @section Interface Drivers
2528 Each of the interface drivers listed here must be explicitly
2529 enabled when OpenOCD is configured, in order to be made
2530 available at run time.
2532 @deffn {Interface Driver} {amt_jtagaccel}
2533 Amontec Chameleon in its JTAG Accelerator configuration,
2534 connected to a PC's EPP mode parallel port.
2535 This defines some driver-specific commands:
2537 @deffn {Config Command} {parport_port} number
2538 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2539 the number of the @file{/dev/parport} device.
2540 @end deffn
2542 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2543 Displays status of RTCK option.
2544 Optionally sets that option first.
2545 @end deffn
2546 @end deffn
2548 @deffn {Interface Driver} {arm-jtag-ew}
2549 Olimex ARM-JTAG-EW USB adapter
2550 This has one driver-specific command:
2552 @deffn Command {armjtagew_info}
2553 Logs some status
2554 @end deffn
2555 @end deffn
2557 @deffn {Interface Driver} {at91rm9200}
2558 Supports bitbanged JTAG from the local system,
2559 presuming that system is an Atmel AT91rm9200
2560 and a specific set of GPIOs is used.
2561 @c command: at91rm9200_device NAME
2562 @c chooses among list of bit configs ... only one option
2563 @end deffn
2565 @deffn {Interface Driver} {cmsis-dap}
2566 ARM CMSIS-DAP compliant based adapter.
2568 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2569 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2570 the driver will attempt to auto detect the CMSIS-DAP device.
2571 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2572 @example
2573 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2574 @end example
2575 @end deffn
2577 @deffn {Command} {cmsis-dap info}
2578 Display various device information, like hardware version, firmware version, current bus status.
2579 @end deffn
2580 @end deffn
2582 @deffn {Interface Driver} {dummy}
2583 A dummy software-only driver for debugging.
2584 @end deffn
2586 @deffn {Interface Driver} {ep93xx}
2587 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2588 @end deffn
2590 @deffn {Interface Driver} {ft2232}
2591 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2593 Note that this driver has several flaws and the @command{ftdi} driver is
2594 recommended as its replacement.
2596 These interfaces have several commands, used to configure the driver
2597 before initializing the JTAG scan chain:
2599 @deffn {Config Command} {ft2232_device_desc} description
2600 Provides the USB device description (the @emph{iProduct string})
2601 of the FTDI FT2232 device. If not
2602 specified, the FTDI default value is used. This setting is only valid
2603 if compiled with FTD2XX support.
2604 @end deffn
2606 @deffn {Config Command} {ft2232_serial} serial-number
2607 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2608 in case the vendor provides unique IDs and more than one FT2232 device
2609 is connected to the host.
2610 If not specified, serial numbers are not considered.
2611 (Note that USB serial numbers can be arbitrary Unicode strings,
2612 and are not restricted to containing only decimal digits.)
2613 @end deffn
2615 @deffn {Config Command} {ft2232_layout} name
2616 Each vendor's FT2232 device can use different GPIO signals
2617 to control output-enables, reset signals, and LEDs.
2618 Currently valid layout @var{name} values include:
2619 @itemize @minus
2620 @item @b{axm0432_jtag} Axiom AXM-0432
2621 @item @b{comstick} Hitex STR9 comstick
2622 @item @b{cortino} Hitex Cortino JTAG interface
2623 @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
2624 either for the local Cortex-M3 (SRST only)
2625 or in a passthrough mode (neither SRST nor TRST)
2626 This layout can not support the SWO trace mechanism, and should be
2627 used only for older boards (before rev C).
2628 @item @b{luminary_icdi} This layout should be used with most TI/Luminary
2629 eval boards, including Rev C LM3S811 eval boards and the eponymous
2630 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2631 to debug some other target. It can support the SWO trace mechanism.
2632 @item @b{flyswatter} Tin Can Tools Flyswatter
2633 @item @b{icebear} ICEbear JTAG adapter from Section 5
2634 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2635 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2636 @item @b{m5960} American Microsystems M5960
2637 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2638 @item @b{oocdlink} OOCDLink
2639 @c oocdlink ~= jtagkey_prototype_v1
2640 @item @b{redbee-econotag} Integrated with a Redbee development board.
2641 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2642 @item @b{sheevaplug} Marvell Sheevaplug development kit
2643 @item @b{signalyzer} Xverve Signalyzer
2644 @item @b{stm32stick} Hitex STM32 Performance Stick
2645 @item @b{turtelizer2} egnite Software turtelizer2
2646 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2647 @end itemize
2648 @end deffn
2650 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2651 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2652 default values are used.
2653 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2654 @example
2655 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2656 @end example
2657 @end deffn
2659 @deffn {Config Command} {ft2232_latency} ms
2660 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2661 ft2232_read() fails to return the expected number of bytes. This can be caused by
2662 USB communication delays and has proved hard to reproduce and debug. Setting the
2663 FT2232 latency timer to a larger value increases delays for short USB packets but it
2664 also reduces the risk of timeouts before receiving the expected number of bytes.
2665 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2666 @end deffn
2668 @deffn {Config Command} {ft2232_channel} channel
2669 Used to select the channel of the ft2232 chip to use (between 1 and 4).
2670 The default value is 1.
2671 @end deffn
2673 For example, the interface config file for a
2674 Turtelizer JTAG Adapter looks something like this:
2676 @example
2677 interface ft2232
2678 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2679 ft2232_layout turtelizer2
2680 ft2232_vid_pid 0x0403 0xbdc8
2681 @end example
2682 @end deffn
2684 @deffn {Interface Driver} {ftdi}
2685 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2686 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2687 It is a complete rewrite to address a large number of problems with the ft2232
2688 interface driver.
2690 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2691 bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
2692 consistently faster than the ft2232 driver, sometimes several times faster.
2694 A major improvement of this driver is that support for new FTDI based adapters
2695 can be added competely through configuration files, without the need to patch
2696 and rebuild OpenOCD.
2698 The driver uses a signal abstraction to enable Tcl configuration files to
2699 define outputs for one or several FTDI GPIO. These outputs can then be
2700 controlled using the @command{ftdi_set_signal} command. Special signal names
2701 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2702 will be used for their customary purpose.
2704 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2705 be controlled differently. In order to support tristateable signals such as
2706 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2707 signal. The following output buffer configurations are supported:
2709 @itemize @minus
2710 @item Push-pull with one FTDI output as (non-)inverted data line
2711 @item Open drain with one FTDI output as (non-)inverted output-enable
2712 @item Tristate with one FTDI output as (non-)inverted data line and another
2713 FTDI output as (non-)inverted output-enable
2714 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2715 switching data and direction as necessary
2716 @end itemize
2718 These interfaces have several commands, used to configure the driver
2719 before initializing the JTAG scan chain:
2721 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2722 The vendor ID and product ID of the adapter. If not specified, the FTDI
2723 default values are used.
2724 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2725 @example
2726 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2727 @end example
2728 @end deffn
2730 @deffn {Config Command} {ftdi_device_desc} description
2731 Provides the USB device description (the @emph{iProduct string})
2732 of the adapter. If not specified, the device description is ignored
2733 during device selection.
2734 @end deffn
2736 @deffn {Config Command} {ftdi_serial} serial-number
2737 Specifies the @var{serial-number} of the adapter to use,
2738 in case the vendor provides unique IDs and more than one adapter
2739 is connected to the host.
2740 If not specified, serial numbers are not considered.
2741 (Note that USB serial numbers can be arbitrary Unicode strings,
2742 and are not restricted to containing only decimal digits.)
2743 @end deffn
2745 @deffn {Config Command} {ftdi_channel} channel
2746 Selects the channel of the FTDI device to use for MPSSE operations. Most
2747 adapters use the default, channel 0, but there are exceptions.
2748 @end deffn
2750 @deffn {Config Command} {ftdi_layout_init} data direction
2751 Specifies the initial values of the FTDI GPIO data and direction registers.
2752 Each value is a 16-bit number corresponding to the concatenation of the high
2753 and low FTDI GPIO registers. The values should be selected based on the
2754 schematics of the adapter, such that all signals are set to safe levels with
2755 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2756 and initially asserted reset signals.
2757 @end deffn
2759 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask]
2760 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2761 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2762 register bitmasks to tell the driver the connection and type of the output
2763 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2764 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2765 used with inverting data inputs and @option{-data} with non-inverting inputs.
2766 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2767 not-output-enable) input to the output buffer is connected.
2769 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2770 simple open-collector transistor driver would be specified with @option{-oe}
2771 only. In that case the signal can only be set to drive low or to Hi-Z and the
2772 driver will complain if the signal is set to drive high. Which means that if
2773 it's a reset signal, @command{reset_config} must be specified as
2774 @option{srst_open_drain}, not @option{srst_push_pull}.
2776 A special case is provided when @option{-data} and @option{-oe} is set to the
2777 same bitmask. Then the FTDI pin is considered being connected straight to the
2778 target without any buffer. The FTDI pin is then switched between output and
2779 input as necessary to provide the full set of low, high and Hi-Z
2780 characteristics. In all other cases, the pins specified in a signal definition
2781 are always driven by the FTDI.
2782 @end deffn
2784 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2785 Set a previously defined signal to the specified level.
2786 @itemize @minus
2787 @item @option{0}, drive low
2788 @item @option{1}, drive high
2789 @item @option{z}, set to high-impedance
2790 @end itemize
2791 @end deffn
2793 For example adapter definitions, see the configuration files shipped in the
2794 @file{interface/ftdi} directory.
2795 @end deffn
2797 @deffn {Interface Driver} {remote_bitbang}
2798 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2799 with a remote process and sends ASCII encoded bitbang requests to that process
2800 instead of directly driving JTAG.
2802 The remote_bitbang driver is useful for debugging software running on
2803 processors which are being simulated.
2805 @deffn {Config Command} {remote_bitbang_port} number
2806 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2807 sockets instead of TCP.
2808 @end deffn
2810 @deffn {Config Command} {remote_bitbang_host} hostname
2811 Specifies the hostname of the remote process to connect to using TCP, or the
2812 name of the UNIX socket to use if remote_bitbang_port is 0.
2813 @end deffn
2815 For example, to connect remotely via TCP to the host foobar you might have
2816 something like:
2818 @example
2819 interface remote_bitbang
2820 remote_bitbang_port 3335
2821 remote_bitbang_host foobar
2822 @end example
2824 To connect to another process running locally via UNIX sockets with socket
2825 named mysocket:
2827 @example
2828 interface remote_bitbang
2829 remote_bitbang_port 0
2830 remote_bitbang_host mysocket
2831 @end example
2832 @end deffn
2834 @deffn {Interface Driver} {usb_blaster}
2835 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2836 for FTDI chips. These interfaces have several commands, used to
2837 configure the driver before initializing the JTAG scan chain:
2839 @deffn {Config Command} {usb_blaster_device_desc} description
2840 Provides the USB device description (the @emph{iProduct string})
2841 of the FTDI FT245 device. If not
2842 specified, the FTDI default value is used. This setting is only valid
2843 if compiled with FTD2XX support.
2844 @end deffn
2846 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2847 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2848 default values are used.
2849 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2850 Altera USB-Blaster (default):
2851 @example
2852 usb_blaster_vid_pid 0x09FB 0x6001
2853 @end example
2854 The following VID/PID is for Kolja Waschk's USB JTAG:
2855 @example
2856 usb_blaster_vid_pid 0x16C0 0x06AD
2857 @end example
2858 @end deffn
2860 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2861 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2862 female JTAG header). These pins can be used as SRST and/or TRST provided the
2863 appropriate connections are made on the target board.
2865 For example, to use pin 6 as SRST (as with an AVR board):
2866 @example
2867 $_TARGETNAME configure -event reset-assert \
2868 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2869 @end example
2870 @end deffn
2872 @end deffn
2874 @deffn {Interface Driver} {gw16012}
2875 Gateworks GW16012 JTAG programmer.
2876 This has one driver-specific command:
2878 @deffn {Config Command} {parport_port} [port_number]
2879 Display either the address of the I/O port
2880 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2881 If a parameter is provided, first switch to use that port.
2882 This is a write-once setting.
2883 @end deffn
2884 @end deffn
2886 @deffn {Interface Driver} {jlink}
2887 Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
2889 @quotation Compatibility Note
2890 Segger released many firmware versions for the many harware versions they
2891 produced. OpenOCD was extensively tested and intended to run on all of them,
2892 but some combinations were reported as incompatible. As a general
2893 recommendation, it is advisable to use the latest firmware version
2894 available for each hardware version. However the current V8 is a moving
2895 target, and Segger firmware versions released after the OpenOCD was
2896 released may not be compatible. In such cases it is recommended to
2897 revert to the last known functional version. For 0.5.0, this is from
2898 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2899 version is from "May 3 2012 18:36:22", packed with 4.46f.
2900 @end quotation
2902 @deffn {Command} {jlink caps}
2903 Display the device firmware capabilities.
2904 @end deffn
2905 @deffn {Command} {jlink info}
2906 Display various device information, like hardware version, firmware version, current bus status.
2907 @end deffn
2908 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2909 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2910 @end deffn
2911 @deffn {Command} {jlink config}
2912 Display the J-Link configuration.
2913 @end deffn
2914 @deffn {Command} {jlink config kickstart} [val]
2915 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2916 @end deffn
2917 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2918 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2919 @end deffn
2920 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2921 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2922 E the bit of the subnet mask and
2923 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2924 @end deffn
2925 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2926 Set the USB address; this will also change the product id. Without argument, show the USB address.
2927 @end deffn
2928 @deffn {Command} {jlink config reset}
2929 Reset the current configuration.
2930 @end deffn
2931 @deffn {Command} {jlink config save}
2932 Save the current configuration to the internal persistent storage.
2933 @end deffn
2934 @deffn {Config} {jlink pid} val
2935 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2936 @end deffn
2937 @end deffn
2939 @deffn {Interface Driver} {parport}
2940 Supports PC parallel port bit-banging cables:
2941 Wigglers, PLD download cable, and more.
2942 These interfaces have several commands, used to configure the driver
2943 before initializing the JTAG scan chain:
2945 @deffn {Config Command} {parport_cable} name
2946 Set the layout of the parallel port cable used to connect to the target.
2947 This is a write-once setting.
2948 Currently valid cable @var{name} values include:
2950 @itemize @minus
2951 @item @b{altium} Altium Universal JTAG cable.
2952 @item @b{arm-jtag} Same as original wiggler except SRST and
2953 TRST connections reversed and TRST is also inverted.
2954 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2955 in configuration mode. This is only used to
2956 program the Chameleon itself, not a connected target.
2957 @item @b{dlc5} The Xilinx Parallel cable III.
2958 @item @b{flashlink} The ST Parallel cable.
2959 @item @b{lattice} Lattice ispDOWNLOAD Cable
2960 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2961 some versions of
2962 Amontec's Chameleon Programmer. The new version available from
2963 the website uses the original Wiggler layout ('@var{wiggler}')
2964 @item @b{triton} The parallel port adapter found on the
2965 ``Karo Triton 1 Development Board''.
2966 This is also the layout used by the HollyGates design
2967 (see @uref{}).
2968 @item @b{wiggler} The original Wiggler layout, also supported by
2969 several clones, such as the Olimex ARM-JTAG
2970 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2971 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2972 @end itemize
2973 @end deffn
2975 @deffn {Config Command} {parport_port} [port_number]
2976 Display either the address of the I/O port
2977 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2978 If a parameter is provided, first switch to use that port.
2979 This is a write-once setting.
2981 When using PPDEV to access the parallel port, use the number of the parallel port:
2982 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2983 you may encounter a problem.
2984 @end deffn
2986 @deffn Command {parport_toggling_time} [nanoseconds]
2987 Displays how many nanoseconds the hardware needs to toggle TCK;
2988 the parport driver uses this value to obey the
2989 @command{adapter_khz} configuration.
2990 When the optional @var{nanoseconds} parameter is given,
2991 that setting is changed before displaying the current value.
2993 The default setting should work reasonably well on commodity PC hardware.
2994 However, you may want to calibrate for your specific hardware.
2995 @quotation Tip
2996 To measure the toggling time with a logic analyzer or a digital storage
2997 oscilloscope, follow the procedure below:
2998 @example
2999 > parport_toggling_time 1000
3000 > adapter_khz 500
3001 @end example
3002 This sets the maximum JTAG clock speed of the hardware, but
3003 the actual speed probably deviates from the requested 500 kHz.
3004 Now, measure the time between the two closest spaced TCK transitions.
3005 You can use @command{runtest 1000} or something similar to generate a
3006 large set of samples.
3007 Update the setting to match your measurement:
3008 @example
3009 > parport_toggling_time <measured nanoseconds>
3010 @end example
3011 Now the clock speed will be a better match for @command{adapter_khz rate}
3012 commands given in OpenOCD scripts and event handlers.
3014 You can do something similar with many digital multimeters, but note
3015 that you'll probably need to run the clock continuously for several
3016 seconds before it decides what clock rate to show. Adjust the
3017 toggling time up or down until the measured clock rate is a good
3018 match for the adapter_khz rate you specified; be conservative.
3019 @end quotation
3020 @end deffn
3022 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
3023 This will configure the parallel driver to write a known
3024 cable-specific value to the parallel interface on exiting OpenOCD.
3025 @end deffn
3027 For example, the interface configuration file for a
3028 classic ``Wiggler'' cable on LPT2 might look something like this:
3030 @example
3031 interface parport
3032 parport_port 0x278
3033 parport_cable wiggler
3034 @end example
3035 @end deffn
3037 @deffn {Interface Driver} {presto}
3038 ASIX PRESTO USB JTAG programmer.
3039 @deffn {Config Command} {presto_serial} serial_string
3040 Configures the USB serial number of the Presto device to use.
3041 @end deffn
3042 @end deffn
3044 @deffn {Interface Driver} {rlink}
3045 Raisonance RLink USB adapter
3046 @end deffn
3048 @deffn {Interface Driver} {usbprog}
3049 usbprog is a freely programmable USB adapter.
3050 @end deffn
3052 @deffn {Interface Driver} {vsllink}
3053 vsllink is part of Versaloon which is a versatile USB programmer.
3055 @quotation Note
3056 This defines quite a few driver-specific commands,
3057 which are not currently documented here.
3058 @end quotation
3059 @end deffn
3061 @deffn {Interface Driver} {hla}
3062 This is a driver that supports multiple High Level Adapters.
3063 This type of adapter does not expose some of the lower level api's
3064 that OpenOCD would normally use to access the target.
3066 Currently supported adapters include the ST STLINK and TI ICDI.
3068 @deffn {Config Command} {hla_device_desc} description
3069 Currently Not Supported.
3070 @end deffn
3072 @deffn {Config Command} {hla_serial} serial
3073 Currently Not Supported.
3074 @end deffn
3076 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
3077 Specifies the adapter layout to use.
3078 @end deffn
3080 @deffn {Config Command} {hla_vid_pid} vid pid
3081 The vendor ID and product ID of the device.
3082 @end deffn
3084 @deffn {Config Command} {trace} source_clock_hz [output_file_path]
3085 Enable SWO tracing (if supported). The source clock rate for the
3086 trace port must be specified, this is typically the CPU clock rate. If
3087 the optional output file is specified then raw trace data is appended
3088 to the file, and the file is created if it does not exist.
3089 @end deffn
3090 @end deffn
3092 @deffn {Interface Driver} {opendous}
3093 opendous-jtag is a freely programmable USB adapter.
3094 @end deffn
3096 @deffn {Interface Driver} {ulink}
3097 This is the Keil ULINK v1 JTAG debugger.
3098 @end deffn
3100 @deffn {Interface Driver} {ZY1000}
3101 This is the Zylin ZY1000 JTAG debugger.
3102 @end deffn
3104 @quotation Note
3105 This defines some driver-specific commands,
3106 which are not currently documented here.
3107 @end quotation
3109 @deffn Command power [@option{on}|@option{off}]
3110 Turn power switch to target on/off.
3111 No arguments: print status.
3112 @end deffn
3114 @deffn {Interface Driver} {bcm2835gpio}
3115 This SoC is present in Raspberry Pi which is a cheap single-board computer
3116 exposing some GPIOs on its expansion header.
3118 The driver accesses memory-mapped GPIO peripheral registers directly
3119 for maximum performance, but the only possible race condition is for
3120 the pins' modes/muxing (which is highly unlikely), so it should be
3121 able to coexist nicely with both sysfs bitbanging and various
3122 peripherals' kernel drivers. The driver restores the previous
3123 configuration on exit.
3125 See @file{interface/raspberrypi-native.cfg} for a sample config and
3126 pinout.
3128 @end deffn
3130 @section Transport Configuration
3131 @cindex Transport
3132 As noted earlier, depending on the version of OpenOCD you use,
3133 and the debug adapter you are using,
3134 several transports may be available to
3135 communicate with debug targets (or perhaps to program flash memory).
3136 @deffn Command {transport list}
3137 displays the names of the transports supported by this
3138 version of OpenOCD.
3139 @end deffn
3141 @deffn Command {transport select} transport_name
3142 Select which of the supported transports to use in this OpenOCD session.
3143 The transport must be supported by the debug adapter hardware and by the
3144 version of OpenOCD you are using (including the adapter's driver).
3145 No arguments: returns name of session's selected transport.
3146 @end deffn
3148 @subsection JTAG Transport
3149 @cindex JTAG
3150 JTAG is the original transport supported by OpenOCD, and most
3151 of the OpenOCD commands support it.
3152 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3153 each of which must be explicitly declared.
3154 JTAG supports both debugging and boundary scan testing.
3155 Flash programming support is built on top of debug support.
3156 @subsection SWD Transport
3157 @cindex SWD
3158 @cindex Serial Wire Debug
3159 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3160 Debug Access Point (DAP, which must be explicitly declared.
3161 (SWD uses fewer signal wires than JTAG.)
3162 SWD is debug-oriented, and does not support boundary scan testing.
3163 Flash programming support is built on top of debug support.
3164 (Some processors support both JTAG and SWD.)
3165 @deffn Command {swd newdap} ...
3166 Declares a single DAP which uses SWD transport.
3167 Parameters are currently the same as "jtag newtap" but this is
3168 expected to change.
3169 @end deffn
3170 @deffn Command {swd wcr trn prescale}
3171 Updates TRN (turnaraound delay) and prescaling.fields of the
3172 Wire Control Register (WCR).
3173 No parameters: displays current settings.
3174 @end deffn
3176 @subsection CMSIS-DAP Transport
3177 @cindex CMSIS-DAP
3178 CMSIS-DAP is an ARM-specific transport that is used to connect to
3179 compilant debuggers.
3181 @subsection SPI Transport
3182 @cindex SPI
3183 @cindex Serial Peripheral Interface
3184 The Serial Peripheral Interface (SPI) is a general purpose transport
3185 which uses four wire signaling. Some processors use it as part of a
3186 solution for flash programming.
3188 @anchor{jtagspeed}
3189 @section JTAG Speed
3190 JTAG clock setup is part of system setup.
3191 It @emph{does not belong with interface setup} since any interface
3192 only knows a few of the constraints for the JTAG clock speed.
3193 Sometimes the JTAG speed is
3194 changed during the target initialization process: (1) slow at
3195 reset, (2) program the CPU clocks, (3) run fast.
3196 Both the "slow" and "fast" clock rates are functions of the
3197 oscillators used, the chip, the board design, and sometimes
3198 power management software that may be active.
3200 The speed used during reset, and the scan chain verification which
3201 follows reset, can be adjusted using a @code{reset-start}
3202 target event handler.
3203 It can then be reconfigured to a faster speed by a
3204 @code{reset-init} target event handler after it reprograms those
3205 CPU clocks, or manually (if something else, such as a boot loader,
3206 sets up those clocks).
3207 @xref{targetevents,,Target Events}.
3208 When the initial low JTAG speed is a chip characteristic, perhaps
3209 because of a required oscillator speed, provide such a handler
3210 in the target config file.
3211 When that speed is a function of a board-specific characteristic
3212 such as which speed oscillator is used, it belongs in the board
3213 config file instead.
3214 In both cases it's safest to also set the initial JTAG clock rate
3215 to that same slow speed, so that OpenOCD never starts up using a
3216 clock speed that's faster than the scan chain can support.
3218 @example
3219 jtag_rclk 3000
3220 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3221 @end example
3223 If your system supports adaptive clocking (RTCK), configuring
3224 JTAG to use that is probably the most robust approach.
3225 However, it introduces delays to synchronize clocks; so it
3226 may not be the fastest solution.
3228 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3229 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3230 which support adaptive clocking.
3232 @deffn {Command} adapter_khz max_speed_kHz
3233 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3234 JTAG interfaces usually support a limited number of
3235 speeds. The speed actually used won't be faster
3236 than the speed specified.
3238 Chip data sheets generally include a top JTAG clock rate.
3239 The actual rate is often a function of a CPU core clock,
3240 and is normally less than that peak rate.
3241 For example, most ARM cores accept at most one sixth of the CPU clock.
3243 Speed 0 (khz) selects RTCK method.
3244 @xref{faqrtck,,FAQ RTCK}.
3245 If your system uses RTCK, you won't need to change the
3246 JTAG clocking after setup.
3247 Not all interfaces, boards, or targets support ``rtck''.
3248 If the interface device can not
3249 support it, an error is returned when you try to use RTCK.
3250 @end deffn
3252 @defun jtag_rclk fallback_speed_kHz
3253 @cindex adaptive clocking
3254 @cindex RTCK
3255 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3256 If that fails (maybe the interface, board, or target doesn't
3257 support it), falls back to the specified frequency.
3258 @example
3259 # Fall back to 3mhz if RTCK is not supported
3260 jtag_rclk 3000
3261 @end example
3262 @end defun
3264 @node Reset Configuration
3265 @chapter Reset Configuration
3266 @cindex Reset Configuration
3268 Every system configuration may require a different reset
3269 configuration. This can also be quite confusing.
3270 Resets also interact with @var{reset-init} event handlers,
3271 which do things like setting up clocks and DRAM, and
3272 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3273 They can also interact with JTAG routers.
3274 Please see the various board files for examples.
3276 @quotation Note
3277 To maintainers and integrators:
3278 Reset configuration touches several things at once.
3279 Normally the board configuration file
3280 should define it and assume that the JTAG adapter supports
3281 everything that's wired up to the board's JTAG connector.
3283 However, the target configuration file could also make note
3284 of something the silicon vendor has done inside the chip,
3285 which will be true for most (or all) boards using that chip.
3286 And when the JTAG adapter doesn't support everything, the
3287 user configuration file will need to override parts of
3288 the reset configuration provided by other files.
3289 @end quotation
3291 @section Types of Reset
3293 There are many kinds of reset possible through JTAG, but
3294 they may not all work with a given board and adapter.
3295 That's part of why reset configuration can be error prone.
3297 @itemize @bullet
3298 @item
3299 @emph{System Reset} ... the @emph{SRST} hardware signal
3300 resets all chips connected to the JTAG adapter, such as processors,
3301 power management chips, and I/O controllers. Normally resets triggered
3302 with this signal behave exactly like pressing a RESET button.
3303 @item
3304 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3305 just the TAP controllers connected to the JTAG adapter.
3306 Such resets should not be visible to the rest of the system; resetting a
3307 device's TAP controller just puts that controller into a known state.
3308 @item
3309 @emph{Emulation Reset} ... many devices can be reset through JTAG
3310 commands. These resets are often distinguishable from system
3311 resets, either explicitly (a "reset reason" register says so)
3312 or implicitly (not all parts of the chip get reset).
3313 @item
3314 @emph{Other Resets} ... system-on-chip devices often support
3315 several other types of reset.
3316 You may need to arrange that a watchdog timer stops
3317 while debugging, preventing a watchdog reset.
3318 There may be individual module resets.
3319 @end itemize
3321 In the best case, OpenOCD can hold SRST, then reset
3322 the TAPs via TRST and send commands through JTAG to halt the
3323 CPU at the reset vector before the 1st instruction is executed.
3324 Then when it finally releases the SRST signal, the system is
3325 halted under debugger control before any code has executed.
3326 This is the behavior required to support the @command{reset halt}
3327 and @command{reset init} commands; after @command{reset init} a
3328 board-specific script might do things like setting up DRAM.
3329 (@xref{resetcommand,,Reset Command}.)
3331 @anchor{srstandtrstissues}
3332 @section SRST and TRST Issues
3334 Because SRST and TRST are hardware signals, they can have a
3335 variety of system-specific constraints. Some of the most
3336 common issues are:
3338 @itemize @bullet
3340 @item @emph{Signal not available} ... Some boards don't wire
3341 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3342 support such signals even if they are wired up.
3343 Use the @command{reset_config} @var{signals} options to say
3344 when either of those signals is not connected.
3345 When SRST is not available, your code might not be able to rely
3346 on controllers having been fully reset during code startup.
3347 Missing TRST is not a problem, since JTAG-level resets can
3348 be triggered using with TMS signaling.
3350 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3351 adapter will connect SRST to TRST, instead of keeping them separate.
3352 Use the @command{reset_config} @var{combination} options to say
3353 when those signals aren't properly independent.
3355 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3356 delay circuit, reset supervisor, or on-chip features can extend
3357 the effect of a JTAG adapter's reset for some time after the adapter
3358 stops issuing the reset. For example, there may be chip or board
3359 requirements that all reset pulses last for at least a
3360 certain amount of time; and reset buttons commonly have
3361 hardware debouncing.
3362 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3363 commands to say when extra delays are needed.
3365 @item @emph{Drive type} ... Reset lines often have a pullup
3366 resistor, letting the JTAG interface treat them as open-drain
3367 signals. But that's not a requirement, so the adapter may need
3368 to use push/pull output drivers.
3369 Also, with weak pullups it may be advisable to drive
3370 signals to both levels (push/pull) to minimize rise times.
3371 Use the @command{reset_config} @var{trst_type} and
3372 @var{srst_type} parameters to say how to drive reset signals.
3374 @item @emph{Special initialization} ... Targets sometimes need
3375 special JTAG initialization sequences to handle chip-specific
3376 issues (not limited to errata).
3377 For example, certain JTAG commands might need to be issued while
3378 the system as a whole is in a reset state (SRST active)
3379 but the JTAG scan chain is usable (TRST inactive).
3380 Many systems treat combined assertion of SRST and TRST as a
3381 trigger for a harder reset than SRST alone.
3382 Such custom reset handling is discussed later in this chapter.
3383 @end itemize
3385 There can also be other issues.
3386 Some devices don't fully conform to the JTAG specifications.
3387 Trivial system-specific differences are common, such as
3388 SRST and TRST using slightly different names.
3389 There are also vendors who distribute key JTAG documentation for
3390 their chips only to developers who have signed a Non-Disclosure
3391 Agreement (NDA).
3393 Sometimes there are chip-specific extensions like a requirement to use
3394 the normally-optional TRST signal (precluding use of JTAG adapters which
3395 don't pass TRST through), or needing extra steps to complete a TAP reset.
3397 In short, SRST and especially TRST handling may be very finicky,
3398 needing to cope with both architecture and board specific constraints.
3400 @section Commands for Handling Resets
3402 @deffn {Command} adapter_nsrst_assert_width milliseconds
3403 Minimum amount of time (in milliseconds) OpenOCD should wait
3404 after asserting nSRST (active-low system reset) before
3405 allowing it to be deasserted.
3406 @end deffn
3408 @deffn {Command} adapter_nsrst_delay milliseconds
3409 How long (in milliseconds) OpenOCD should wait after deasserting
3410 nSRST (active-low system reset) before starting new JTAG operations.
3411 When a board has a reset button connected to SRST line it will
3412 probably have hardware debouncing, implying you should use this.
3413 @end deffn
3415 @deffn {Command} jtag_ntrst_assert_width milliseconds
3416 Minimum amount of time (in milliseconds) OpenOCD should wait
3417 after asserting nTRST (active-low JTAG TAP reset) before
3418 allowing it to be deasserted.
3419 @end deffn
3421 @deffn {Command} jtag_ntrst_delay milliseconds
3422 How long (in milliseconds) OpenOCD should wait after deasserting
3423 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3424 @end deffn
3426 @deffn {Command} reset_config mode_flag ...
3427 This command displays or modifies the reset configuration
3428 of your combination of JTAG board and target in target
3429 configuration scripts.
3431 Information earlier in this section describes the kind of problems
3432 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3433 As a rule this command belongs only in board config files,
3434 describing issues like @emph{board doesn't connect TRST};
3435 or in user config files, addressing limitations derived
3436 from a particular combination of interface and board.
3437 (An unlikely example would be using a TRST-only adapter
3438 with a board that only wires up SRST.)
3440 The @var{mode_flag} options can be specified in any order, but only one
3441 of each type -- @var{signals}, @var{combination}, @var{gates},
3442 @var{trst_type}, @var{srst_type} and @var{connect_type}
3443 -- may be specified at a time.
3444 If you don't provide a new value for a given type, its previous
3445 value (perhaps the default) is unchanged.
3446 For example, this means that you don't need to say anything at all about
3447 TRST just to declare that if the JTAG adapter should want to drive SRST,
3448 it must explicitly be driven high (@option{srst_push_pull}).
3450 @itemize
3451 @item
3452 @var{signals} can specify which of the reset signals are connected.
3453 For example, If the JTAG interface provides SRST, but the board doesn't
3454 connect that signal properly, then OpenOCD can't use it.
3455 Possible values are @option{none} (the default), @option{trst_only},
3456 @option{srst_only} and @option{trst_and_srst}.
3458 @quotation Tip
3459 If your board provides SRST and/or TRST through the JTAG connector,
3460 you must declare that so those signals can be used.
3461 @end quotation
3463 @item
3464 The @var{combination} is an optional value specifying broken reset
3465 signal implementations.
3466 The default behaviour if no option given is @option{separate},
3467 indicating everything behaves normally.
3468 @option{srst_pulls_trst} states that the
3469 test logic is reset together with the reset of the system (e.g. NXP
3470 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3471 the system is reset together with the test logic (only hypothetical, I
3472 haven't seen hardware with such a bug, and can be worked around).
3473 @option{combined} implies both @option{srst_pulls_trst} and
3474 @option{trst_pulls_srst}.
3476 @item
3477 The @var{gates} tokens control flags that describe some cases where
3478 JTAG may be unvailable during reset.
3479 @option{srst_gates_jtag} (default)
3480 indicates that asserting SRST gates the
3481 JTAG clock. This means that no communication can happen on JTAG
3482 while SRST is asserted.
3483 Its converse is @option{srst_nogate}, indicating that JTAG commands
3484 can safely be issued while SRST is active.
3486 @item
3487 The @var{connect_type} tokens control flags that describe some cases where
3488 SRST is asserted while connecting to the target. @option{srst_nogate}
3489 is required to use this option.
3490 @option{connect_deassert_srst} (default)
3491 indicates that SRST will not be asserted while connecting to the target.
3492 Its converse is @option{connect_assert_srst}, indicating that SRST will
3493 be asserted before any target connection.
3494 Only some targets support this feature, STM32 and STR9 are examples.
3495 This feature is useful if you are unable to connect to your target due
3496 to incorrect options byte config or illegal program execution.
3497 @end itemize
3499 The optional @var{trst_type} and @var{srst_type} parameters allow the
3500 driver mode of each reset line to be specified. These values only affect
3501 JTAG interfaces with support for different driver modes, like the Amontec
3502 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3503 relevant signal (TRST or SRST) is not connected.
3505 @itemize
3506 @item
3507 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3508 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3509 Most boards connect this signal to a pulldown, so the JTAG TAPs
3510 never leave reset unless they are hooked up to a JTAG adapter.
3512 @item
3513 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3514 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3515 Most boards connect this signal to a pullup, and allow the
3516 signal to be pulled low by various events including system
3517 powerup and pressing a reset button.
3518 @end itemize
3519 @end deffn
3521 @section Custom Reset Handling
3522 @cindex events
3524 OpenOCD has several ways to help support the various reset
3525 mechanisms provided by chip and board vendors.
3526 The commands shown in the previous section give standard parameters.
3527 There are also @emph{event handlers} associated with TAPs or Targets.
3528 Those handlers are Tcl procedures you can provide, which are invoked
3529 at particular points in the reset sequence.
3531 @emph{When SRST is not an option} you must set
3532 up a @code{reset-assert} event handler for your target.
3533 For example, some JTAG adapters don't include the SRST signal;
3534 and some boards have multiple targets, and you won't always
3535 want to reset everything at once.
3537 After configuring those mechanisms, you might still
3538 find your board doesn't start up or reset correctly.
3539 For example, maybe it needs a slightly different sequence
3540 of SRST and/or TRST manipulations, because of quirks that
3541 the @command{reset_config} mechanism doesn't address;
3542 or asserting both might trigger a stronger reset, which
3543 needs special attention.
3545 Experiment with lower level operations, such as @command{jtag_reset}
3546 and the @command{jtag arp_*} operations shown here,
3547 to find a sequence of operations that works.
3548 @xref{JTAG Commands}.
3549 When you find a working sequence, it can be used to override
3550 @command{jtag_init}, which fires during OpenOCD startup
3551 (@pxref{configurationstage,,Configuration Stage});
3552 or @command{init_reset}, which fires during reset processing.
3554 You might also want to provide some project-specific reset
3555 schemes. For example, on a multi-target board the standard
3556 @command{reset} command would reset all targets, but you
3557 may need the ability to reset only one target at time and
3558 thus want to avoid using the board-wide SRST signal.
3560 @deffn {Overridable Procedure} init_reset mode
3561 This is invoked near the beginning of the @command{reset} command,
3562 usually to provide as much of a cold (power-up) reset as practical.
3563 By default it is also invoked from @command{jtag_init} if
3564 the scan chain does not respond to pure JTAG operations.
3565 The @var{mode} parameter is the parameter given to the
3566 low level reset command (@option{halt},
3567 @option{init}, or @option{run}), @option{setup},
3568 or potentially some other value.
3570 The default implementation just invokes @command{jtag arp_init-reset}.
3571 Replacements will normally build on low level JTAG
3572 operations such as @command{jtag_reset}.
3573 Operations here must not address individual TAPs
3574 (or their associated targets)
3575 until the JTAG scan chain has first been verified to work.
3577 Implementations must have verified the JTAG scan chain before
3578 they return.
3579 This is done by calling @command{jtag arp_init}
3580 (or @command{jtag arp_init-reset}).
3581 @end deffn
3583 @deffn Command {jtag arp_init}
3584 This validates the scan chain using just the four
3585 standard JTAG signals (TMS, TCK, TDI, TDO).
3586 It starts by issuing a JTAG-only reset.
3587 Then it performs checks to verify that the scan chain configuration
3588 matches the TAPs it can observe.
3589 Those checks include checking IDCODE values for each active TAP,
3590 and verifying the length of their instruction registers using
3591 TAP @code{-ircapture} and @code{-irmask} values.
3592 If these tests all pass, TAP @code{setup} events are
3593 issued to all TAPs with handlers for that event.
3594 @end deffn
3596 @deffn Command {jtag arp_init-reset}
3597 This uses TRST and SRST to try resetting
3598 everything on the JTAG scan chain
3599 (and anything else connected to SRST).
3600 It then invokes the logic of @command{jtag arp_init}.
3601 @end deffn
3604 @node TAP Declaration
3605 @chapter TAP Declaration
3606 @cindex TAP declaration
3607 @cindex TAP configuration
3609 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3610 TAPs serve many roles, including:
3612 @itemize @bullet
3613 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3614 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3615 Others do it indirectly, making a CPU do it.
3616 @item @b{Program Download} Using the same CPU support GDB uses,
3617 you can initialize a DRAM controller, download code to DRAM, and then
3618 start running that code.
3619 @item @b{Boundary Scan} Most chips support boundary scan, which
3620 helps test for board assembly problems like solder bridges
3621 and missing connections.
3622 @end itemize
3624 OpenOCD must know about the active TAPs on your board(s).
3625 Setting up the TAPs is the core task of your configuration files.
3626 Once those TAPs are set up, you can pass their names to code
3627 which sets up CPUs and exports them as GDB targets,
3628 probes flash memory, performs low-level JTAG operations, and more.
3630 @section Scan Chains
3631 @cindex scan chain
3633 TAPs are part of a hardware @dfn{scan chain},
3634 which is a daisy chain of TAPs.
3635 They also need to be added to
3636 OpenOCD's software mirror of that hardware list,
3637 giving each member a name and associating other data with it.
3638 Simple scan chains, with a single TAP, are common in
3639 systems with a single microcontroller or microprocessor.
3640 More complex chips may have several TAPs internally.
3641 Very complex scan chains might have a dozen or more TAPs:
3642 several in one chip, more in the next, and connecting
3643 to other boards with their own chips and TAPs.
3645 You can display the list with the @command{scan_chain} command.
3646 (Don't confuse this with the list displayed by the @command{targets}
3647 command, presented in the next chapter.
3648 That only displays TAPs for CPUs which are configured as
3649 debugging targets.)
3650 Here's what the scan chain might look like for a chip more than one TAP:
3652 @verbatim
3653 TapName Enabled IdCode Expected IrLen IrCap IrMask
3654 -- ------------------ ------- ---------- ---------- ----- ----- ------
3655 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3656 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3657 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3658 @end verbatim
3660 OpenOCD can detect some of that information, but not all
3661 of it. @xref{autoprobing,,Autoprobing}.
3662 Unfortunately, those TAPs can't always be autoconfigured,
3663 because not all devices provide good support for that.
3664 JTAG doesn't require supporting IDCODE instructions, and
3665 chips with JTAG routers may not link TAPs into the chain
3666 until they are told to do so.
3668 The configuration mechanism currently supported by OpenOCD
3669 requires explicit configuration of all TAP devices using
3670 @command{jtag newtap} commands, as detailed later in this chapter.
3671 A command like this would declare one tap and name it @code{chip1.cpu}:
3673 @example
3674 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3675 @end example
3677 Each target configuration file lists the TAPs provided
3678 by a given chip.
3679 Board configuration files combine all the targets on a board,
3680 and so forth.
3681 Note that @emph{the order in which TAPs are declared is very important.}
3682 That declaration order must match the order in the JTAG scan chain,
3683 both inside a single chip and between them.
3684 @xref{faqtaporder,,FAQ TAP Order}.
3686 For example, the ST Microsystems STR912 chip has
3687 three separate TAPs@footnote{See the ST
3688 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3689 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3690 @url{}}.
3691 To configure those taps, @file{target/str912.cfg}
3692 includes commands something like this:
3694 @example
3695 jtag newtap str912 flash ... params ...
3696 jtag newtap str912 cpu ... params ...
3697 jtag newtap str912 bs ... params ...
3698 @end example
3700 Actual config files typically use a variable such as @code{$_CHIPNAME}
3701 instead of literals like @option{str912}, to support more than one chip
3702 of each type. @xref{Config File Guidelines}.
3704 @deffn Command {jtag names}
3705 Returns the names of all current TAPs in the scan chain.
3706 Use @command{jtag cget} or @command{jtag tapisenabled}
3707 to examine attributes and state of each TAP.
3708 @example
3709 foreach t [jtag names] @{
3710 puts [format "TAP: %s\n" $t]
3711 @}
3712 @end example
3713 @end deffn
3715 @deffn Command {scan_chain}
3716 Displays the TAPs in the scan chain configuration,
3717 and their status.
3718 The set of TAPs listed by this command is fixed by
3719 exiting the OpenOCD configuration stage,
3720 but systems with a JTAG router can
3721 enable or disable TAPs dynamically.
3722 @end deffn
3724 @c FIXME! "jtag cget" should be able to return all TAP
3725 @c attributes, like "$target_name cget" does for targets.
3727 @c Probably want "jtag eventlist", and a "tap-reset" event
3728 @c (on entry to RESET state).
3730 @section TAP Names
3731 @cindex dotted name
3733 When TAP objects are declared with @command{jtag newtap},
3734 a @dfn{} is created for the TAP, combining the
3735 name of a module (usually a chip) and a label for the TAP.
3736 For example: @code{xilinx.tap}, @code{str912.flash},
3737 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3738 Many other commands use that to manipulate or
3739 refer to the TAP. For example, CPU configuration uses the
3740 name, as does declaration of NAND or NOR flash banks.
3742 The components of a dotted name should follow ``C'' symbol
3743 name rules: start with an alphabetic character, then numbers
3744 and underscores are OK; while others (including dots!) are not.
3746 @section TAP Declaration Commands
3748 @c shouldn't this be(come) a {Config Command}?
3749 @deffn Command {jtag newtap} chipname tapname configparams...
3750 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3751 and configured according to the various @var{configparams}.
3753 The @var{chipname} is a symbolic name for the chip.
3754 Conventionally target config files use @code{$_CHIPNAME},
3755 defaulting to the model name given by the chip vendor but
3756 overridable.
3758 @cindex TAP naming convention
3759 The @var{tapname} reflects the role of that TAP,
3760 and should follow this convention:
3762 @itemize @bullet
3763 @item @code{bs} -- For boundary scan if this is a separate TAP;
3764 @item @code{cpu} -- The main CPU of the chip, alternatively
3765 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3766 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3767 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3768 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3769 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3770 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3771 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3772 with a single TAP;
3773 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3774 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3775 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3776 a JTAG TAP; that TAP should be named @code{sdma}.
3777 @end itemize
3779 Every TAP requires at least the following @var{configparams}:
3781 @itemize @bullet
3782 @item @code{-irlen} @var{NUMBER}
3783 @*The length in bits of the
3784 instruction register, such as 4 or 5 bits.
3785 @end itemize
3787 A TAP may also provide optional @var{configparams}:
3789 @itemize @bullet
3790 @item @code{-disable} (or @code{-enable})
3791 @*Use the @code{-disable} parameter to flag a TAP which is not
3792 linked into the scan chain after a reset using either TRST
3793 or the JTAG state machine's @sc{reset} state.
3794 You may use @code{-enable} to highlight the default state
3795 (the TAP is linked in).
3796 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3797 @item @code{-expected-id} @var{NUMBER}
3798 @*A non-zero @var{number} represents a 32-bit IDCODE
3799 which you expect to find when the scan chain is examined.
3800 These codes are not required by all JTAG devices.
3801 @emph{Repeat the option} as many times as required if more than one
3802 ID code could appear (for example, multiple versions).
3803 Specify @var{number} as zero to suppress warnings about IDCODE
3804 values that were found but not included in the list.
3806 Provide this value if at all possible, since it lets OpenOCD
3807 tell when the scan chain it sees isn't right. These values
3808 are provided in vendors' chip documentation, usually a technical
3809 reference manual. Sometimes you may need to probe the JTAG
3810 hardware to find these values.
3811 @xref{autoprobing,,Autoprobing}.
3812 @item @code{-ignore-version}
3813 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3814 option. When vendors put out multiple versions of a chip, or use the same
3815 JTAG-level ID for several largely-compatible chips, it may be more practical
3816 to ignore the version field than to update config files to handle all of
3817 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3818 @item @code{-ircapture} @var{NUMBER}
3819 @*The bit pattern loaded by the TAP into the JTAG shift register
3820 on entry to the @sc{ircapture} state, such as 0x01.
3821 JTAG requires the two LSBs of this value to be 01.
3822 By default, @code{-ircapture} and @code{-irmask} are set
3823 up to verify that two-bit value. You may provide
3824 additional bits if you know them, or indicate that
3825 a TAP doesn't conform to the JTAG specification.
3826 @item @code{-irmask} @var{NUMBER}
3827 @*A mask used with @code{-ircapture}
3828 to verify that instruction scans work correctly.
3829 Such scans are not used by OpenOCD except to verify that
3830 there seems to be no problems with JTAG scan chain operations.
3831 @end itemize
3832 @end deffn
3834 @section Other TAP commands
3836 @deffn Command {jtag cget} @option{-event} event_name
3837 @deffnx Command {jtag configure} @option{-event} event_name handler
3838 At this writing this TAP attribute
3839 mechanism is used only for event handling.
3840 (It is not a direct analogue of the @code{cget}/@code{configure}
3841 mechanism for debugger targets.)
3842 See the next section for information about the available events.
3844 The @code{configure} subcommand assigns an event handler,
3845 a TCL string which is evaluated when the event is triggered.
3846 The @code{cget} subcommand returns that handler.
3847 @end deffn
3849 @section TAP Events
3850 @cindex events
3851 @cindex TAP events
3853 OpenOCD includes two event mechanisms.
3854 The one presented here applies to all JTAG TAPs.
3855 The other applies to debugger targets,
3856 which are associated with certain TAPs.
3858 The TAP events currently defined are:
3860 @itemize @bullet
3861 @item @b{post-reset}
3862 @* The TAP has just completed a JTAG reset.
3863 The tap may still be in the JTAG @sc{reset} state.
3864 Handlers for these events might perform initialization sequences
3865 such as issuing TCK cycles, TMS sequences to ensure
3866 exit from the ARM SWD mode, and more.
3868 Because the scan chain has not yet been verified, handlers for these events
3869 @emph{should not issue commands which scan the JTAG IR or DR registers}
3870 of any particular target.
3871 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3872 @item @b{setup}
3873 @* The scan chain has been reset and verified.
3874 This handler may enable TAPs as needed.
3875 @item @b{tap-disable}
3876 @* The TAP needs to be disabled. This handler should
3877 implement @command{jtag tapdisable}
3878 by issuing the relevant JTAG commands.
3879 @item @b{tap-enable}
3880 @* The TAP needs to be enabled. This handler should
3881 implement @command{jtag tapenable}
3882 by issuing the relevant JTAG commands.
3883 @end itemize
3885 If you need some action after each JTAG reset which isn't actually
3886 specific to any TAP (since you can't yet trust the scan chain's
3887 contents to be accurate), you might:
3889 @example
3890 jtag configure CHIP.jrc -event post-reset @{
3891 echo "JTAG Reset done"
3892 ... non-scan jtag operations to be done after reset
3893 @}
3894 @end example
3897 @anchor{enablinganddisablingtaps}
3898 @section Enabling and Disabling TAPs
3899 @cindex JTAG Route Controller
3900 @cindex jrc
3902 In some systems, a @dfn{JTAG Route Controller} (JRC)
3903 is used to enable and/or disable specific JTAG TAPs.
3904 Many ARM-based chips from Texas Instruments include
3905 an ``ICEPick'' module, which is a JRC.
3906 Such chips include DaVinci and OMAP3 processors.
3908 A given TAP may not be visible until the JRC has been
3909 told to link it into the scan chain; and if the JRC
3910 has been told to unlink that TAP, it will no longer
3911 be visible.
3912 Such routers address problems that JTAG ``bypass mode''
3913 ignores, such as:
3915 @itemize
3916 @item The scan chain can only go as fast as its slowest TAP.
3917 @item Having many TAPs slows instruction scans, since all
3918 TAPs receive new instructions.
3919 @item TAPs in the scan chain must be powered up, which wastes
3920 power and prevents debugging some power management mechanisms.
3921 @end itemize
3923 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3924 as implied by the existence of JTAG routers.
3925 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3926 does include a kind of JTAG router functionality.
3928 @c (a) currently the event handlers don't seem to be able to
3929 @c fail in a way that could lead to no-change-of-state.
3931 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3932 shown below, and is implemented using TAP event handlers.
3933 So for example, when defining a TAP for a CPU connected to
3934 a JTAG router, your @file{target.cfg} file
3935 should define TAP event handlers using
3936 code that looks something like this:
3938 @example
3939 jtag configure CHIP.cpu -event tap-enable @{
3940 ... jtag operations using CHIP.jrc
3941 @}
3942 jtag configure CHIP.cpu -event tap-disable @{
3943 ... jtag operations using CHIP.jrc
3944 @}
3945 @end example
3947 Then you might want that CPU's TAP enabled almost all the time:
3949 @example
3950 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3951 @end example
3953 Note how that particular setup event handler declaration
3954 uses quotes to evaluate @code{$CHIP} when the event is configured.
3955 Using brackets @{ @} would cause it to be evaluated later,
3956 at runtime, when it might have a different value.
3958 @deffn Command {jtag tapdisable}
3959 If necessary, disables the tap
3960 by sending it a @option{tap-disable} event.
3961 Returns the string "1" if the tap
3962 specified by @var{} is enabled,
3963 and "0" if it is disabled.
3964 @end deffn
3966 @deffn Command {jtag tapenable}
3967 If necessary, enables the tap
3968 by sending it a @option{tap-enable} event.
3969 Returns the string "1" if the tap
3970 specified by @var{} is enabled,
3971 and "0" if it is disabled.
3972 @end deffn
3974 @deffn Command {jtag tapisenabled}
3975 Returns the string "1" if the tap
3976 specified by @var{} is enabled,
3977 and "0" if it is disabled.
3979 @quotation Note
3980 Humans will find the @command{scan_chain} command more helpful
3981 for querying the state of the JTAG taps.
3982 @end quotation
3983 @end deffn
3985 @anchor{autoprobing}
3986 @section Autoprobing
3987 @cindex autoprobe
3988 @cindex JTAG autoprobe
3990 TAP configuration is the first thing that needs to be done
3991 after interface and reset configuration. Sometimes it's
3992 hard finding out what TAPs exist, or how they are identified.
3993 Vendor documentation is not always easy to find and use.
3995 To help you get past such problems, OpenOCD has a limited
3996 @emph{autoprobing} ability to look at the scan chain, doing
3997 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3998 To use this mechanism, start the OpenOCD server with only data
3999 that configures your JTAG interface, and arranges to come up
4000 with a slow clock (many devices don't support fast JTAG clocks
4001 right when they come out of reset).
4003 For example, your @file{openocd.cfg} file might have:
4005 @example
4006 source [find interface/olimex-arm-usb-tiny-h.cfg]
4007 reset_config trst_and_srst
4008 jtag_rclk 8
4009 @end example
4011 When you start the server without any TAPs configured, it will
4012 attempt to autoconfigure the TAPs. There are two parts to this:
4014 @enumerate
4015 @item @emph{TAP discovery} ...
4016 After a JTAG reset (sometimes a system reset may be needed too),
4017 each TAP's data registers will hold the contents of either the
4018 IDCODE or BYPASS register.
4019 If JTAG communication is working, OpenOCD will see each TAP,
4020 and report what @option{-expected-id} to use with it.
4021 @item @emph{IR Length discovery} ...
4022 Unfortunately JTAG does not provide a reliable way to find out
4023 the value of the @option{-irlen} parameter to use with a TAP
4024 that is discovered.
4025 If OpenOCD can discover the length of a TAP's instruction
4026 register, it will report it.
4027 Otherwise you may need to consult vendor documentation, such
4028 as chip data sheets or BSDL files.
4029 @end enumerate
4031 In many cases your board will have a simple scan chain with just
4032 a single device. Here's what OpenOCD reported with one board
4033 that's a bit more complex:
4035 @example
4036 clock speed 8 kHz
4037 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4038 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4039 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4040 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4041 AUTO auto0.tap - use "... -irlen 4"
4042 AUTO auto1.tap - use "... -irlen 4"
4043 AUTO auto2.tap - use "... -irlen 6"
4044 no gdb ports allocated as no target has been specified
4045 @end example
4047 Given that information, you should be able to either find some existing
4048 config files to use, or create your own. If you create your own, you
4049 would configure from the bottom up: first a @file{target.cfg} file
4050 with these TAPs, any targets associated with them, and any on-chip
4051 resources; then a @file{board.cfg} with off-chip resources, clocking,
4052 and so forth.
4054 @node CPU Configuration
4055 @chapter CPU Configuration
4056 @cindex GDB target
4058 This chapter discusses how to set up GDB debug targets for CPUs.
4059 You can also access these targets without GDB
4060 (@pxref{Architecture and Core Commands},
4061 and @ref{targetstatehandling,,Target State handling}) and
4062 through various kinds of NAND and NOR flash commands.
4063 If you have multiple CPUs you can have multiple such targets.
4065 We'll start by looking at how to examine the targets you have,
4066 then look at how to add one more target and how to configure it.
4068 @section Target List
4069 @cindex target, current
4070 @cindex target, list
4072 All targets that have been set up are part of a list,
4073 where each member has a name.
4074 That name should normally be the same as the TAP name.
4075 You can display the list with the @command{targets}
4076 (plural!) command.
4077 This display often has only one CPU; here's what it might
4078 look like with more than one:
4079 @verbatim
4080 TargetName Type Endian TapName State
4081 -- ------------------ ---------- ------ ------------------ ------------
4082 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4083 1 MyTarget cortex_m little tap-disabled
4084 @end verbatim
4086 One member of that list is the @dfn{current target}, which
4087 is implicitly referenced by many commands.
4088 It's the one marked with a @code{*} near the target name.
4089 In particular, memory addresses often refer to the address
4090 space seen by that current target.
4091 Commands like @command{mdw} (memory display words)
4092 and @command{flash erase_address} (erase NOR flash blocks)
4093 are examples; and there are many more.
4095 Several commands let you examine the list of targets:
4097 @deffn Command {target count}
4098 @emph{Note: target numbers are deprecated; don't use them.
4099 They will be removed shortly after August 2010, including this command.
4100 Iterate target using @command{target names}, not by counting.}
4102 Returns the number of targets, @math{N}.
4103 The highest numbered target is @math{N - 1}.
4104 @example
4105 set c [target count]
4106 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
4107 # Assuming you have created this function
4108 print_target_details $x
4109 @}
4110 @end example
4111 @end deffn
4113 @deffn Command {target current}
4114 Returns the name of the current target.
4115 @end deffn
4117 @deffn Command {target names}
4118 Lists the names of all current targets in the list.
4119 @example
4120 foreach t [target names] @{
4121 puts [format "Target: %s\n" $t]
4122 @}
4123 @end example
4124 @end deffn
4126 @deffn Command {target number} number
4127 @emph{Note: target numbers are deprecated; don't use them.
4128 They will be removed shortly after August 2010, including this command.}
4130 The list of targets is numbered starting at zero.
4131 This command returns the name of the target at index @var{number}.
4132 @example
4133 set thename [target number $x]
4134 puts [format "Target %d is: %s\n" $x $thename]
4135 @end example
4136 @end deffn
4138 @c yep, "target list" would have been better.
4139 @c plus maybe "target setdefault".
4141 @deffn Command targets [name]
4142 @emph{Note: the name of this command is plural. Other target
4143 command names are singular.}
4145 With no parameter, this command displays a table of all known
4146 targets in a user friendly form.
4148 With a parameter, this command sets the current target to
4149 the given target with the given @var{name}; this is
4150 only relevant on boards which have more than one target.
4151 @end deffn
4153 @section Target CPU Types and Variants
4154 @cindex target type
4155 @cindex CPU type
4156 @cindex CPU variant
4158 Each target has a @dfn{CPU type}, as shown in the output of
4159 the @command{targets} command. You need to specify that type
4160 when calling @command{target create}.
4161 The CPU type indicates more than just the instruction set.
4162 It also indicates how that instruction set is implemented,
4163 what kind of debug support it integrates,
4164 whether it has an MMU (and if so, what kind),
4165 what core-specific commands may be available
4166 (@pxref{Architecture and Core Commands}),
4167 and more.
4169 For some CPU types, OpenOCD also defines @dfn{variants} which
4170 indicate differences that affect their handling.
4171 For example, a particular implementation bug might need to be
4172 worked around in some chip versions.
4174 It's easy to see what target types are supported,
4175 since there's a command to list them.
4176 However, there is currently no way to list what target variants
4177 are supported (other than by reading the OpenOCD source code).
4179 @anchor{targettypes}
4180 @deffn Command {target types}
4181 Lists all supported target types.
4182 At this writing, the supported CPU types and variants are:
4184 @itemize @bullet
4185 @item @code{arm11} -- this is a generation of ARMv6 cores
4186 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4187 @item @code{arm7tdmi} -- this is an ARMv4 core
4188 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4189 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4190 @item @code{arm966e} -- this is an ARMv5 core
4191 @item @code{arm9tdmi} -- this is an ARMv4 core
4192 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4193 (Support for this is preliminary and incomplete.)
4194 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4195 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4196 compact Thumb2 instruction set.
4197 @item @code{dragonite} -- resembles arm966e
4198 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4199 (Support for this is still incomplete.)
4200 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4201 @item @code{feroceon} -- resembles arm926
4202 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
4203 @item @code{xscale} -- this is actually an architecture,
4204 not a CPU type. It is based on the ARMv5 architecture.
4205 There are several variants defined:
4206 @itemize @minus
4207 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
4208 @code{pxa27x} ... instruction register length is 7 bits
4209 @item @code{pxa250}, @code{pxa255},
4210 @code{pxa26x} ... instruction register length is 5 bits
4211 @item @code{pxa3xx} ... instruction register length is 11 bits
4212 @end itemize
4213 @item @code{openrisc} -- this is an OpenRISC 1000 core.
4214 The current implementation supports three JTAG TAP cores:
4215 @itemize @minus
4216 @item @code{OpenCores TAP} (See: @emph{,jtag})
4217 @item @code{Altera Virtual JTAG TAP} (See: @emph{})
4218 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @emph{})
4219 @end itemize
4220 And two debug interfaces cores:
4221 @itemize @minus
4222 @item @code{Advanced debug interface} (See: @emph{,adv_debug_sys})
4223 @item @code{SoC Debug Interface} (See: @emph{,dbg_interface})
4224 @end itemize
4225 @end itemize
4226 @end deffn
4228 To avoid being confused by the variety of ARM based cores, remember
4229 this key point: @emph{ARM is a technology licencing company}.
4230 (See: @url{}.)
4231 The CPU name used by OpenOCD will reflect the CPU design that was
4232 licenced, not a vendor brand which incorporates that design.
4233 Name prefixes like arm7, arm9, arm11, and cortex
4234 reflect design generations;
4235 while names like ARMv4, ARMv5, ARMv6, and ARMv7
4236 reflect an architecture version implemented by a CPU design.
4238 @anchor{targetconfiguration}
4239 @section Target Configuration
4241 Before creating a ``target'', you must have added its TAP to the scan chain.
4242 When you've added that TAP, you will have a @code{}
4243 which is used to set up the CPU support.
4244 The chip-specific configuration file will normally configure its CPU(s)
4245 right after it adds all of the chip's TAPs to the scan chain.
4247 Although you can set up a target in one step, it's often clearer if you
4248 use shorter commands and do it in two steps: create it, then configure
4249 optional parts.
4250 All operations on the target after it's created will use a new
4251 command, created as part of target creation.
4253 The two main things to configure after target creation are
4254 a work area, which usually has target-specific defaults even
4255 if the board setup code overrides them later;
4256 and event handlers (@pxref{targetevents,,Target Events}), which tend
4257 to be much more board-specific.
4258 The key steps you use might look something like this
4260 @example
4261 target create MyTarget cortex_m -chain-position mychip.cpu
4262 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4263 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4264 $MyTarget configure -event reset-init @{ myboard_reinit @}
4265 @end example
4267 You should specify a working area if you can; typically it uses some
4268 on-chip SRAM.
4269 Such a working area can speed up many things, including bulk
4270 writes to target memory;
4271 flash operations like checking to see if memory needs to be erased;
4272 GDB memory checksumming;
4273 and more.
4275 @quotation Warning
4276 On more complex chips, the work area can become
4277 inaccessible when application code
4278 (such as an operating system)
4279 enables or disables the MMU.
4280 For example, the particular MMU context used to acess the virtual
4281 address will probably matter ... and that context might not have
4282 easy access to other addresses needed.
4283 At this writing, OpenOCD doesn't have much MMU intelligence.
4284 @end quotation
4286 It's often very useful to define a @code{reset-init} event handler.
4287 For systems that are normally used with a boot loader,
4288 common tasks include updating clocks and initializing memory
4289 controllers.
4290 That may be needed to let you write the boot loader into flash,
4291 in order to ``de-brick'' your board; or to load programs into
4292 external DDR memory without having run the boot loader.
4294 @deffn Command {target create} target_name type configparams...
4295 This command creates a GDB debug target that refers to a specific JTAG tap.
4296 It enters that target into a list, and creates a new
4297 command (@command{@var{target_name}}) which is used for various
4298 purposes including additional configuration.
4300 @itemize @bullet
4301 @item @var{target_name} ... is the name of the debug target.
4302 By convention this should be the same as the @emph{}
4303 of the TAP associated with this target, which must be specified here
4304 using the @code{-chain-position @var{}} configparam.
4306 This name is also used to create the target object command,
4307 referred to here as @command{$target_name},
4308 and in other places the target needs to be identified.
4309 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4310 @item @var{configparams} ... all parameters accepted by
4311 @command{$target_name configure} are permitted.
4312 If the target is big-endian, set it here with @code{-endian big}.
4313 If the variant matters, set it here with @code{-variant}.
4315 You @emph{must} set the @code{-chain-position @var{}} here.
4316 @end itemize
4317 @end deffn
4319 @deffn Command {$target_name configure} configparams...
4320 The options accepted by this command may also be
4321 specified as parameters to @command{target create}.
4322 Their values can later be queried one at a time by
4323 using the @command{$target_name cget} command.
4325 @emph{Warning:} changing some of these after setup is dangerous.
4326 For example, moving a target from one TAP to another;
4327 and changing its endianness or variant.
4329 @itemize @bullet
4331 @item @code{-chain-position} @var{} -- names the TAP
4332 used to access this target.
4334 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4335 whether the CPU uses big or little endian conventions
4337 @item @code{-event} @var{event_name} @var{event_body} --
4338 @xref{targetevents,,Target Events}.
4339 Note that this updates a list of named event handlers.
4340 Calling this twice with two different event names assigns
4341 two different handlers, but calling it twice with the
4342 same event name assigns only one handler.
4344 @item @code{-variant} @var{name} -- specifies a variant of the target,
4345 which OpenOCD needs to know about.
4347 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4348 whether the work area gets backed up; by default,
4349 @emph{it is not backed up.}
4350 When possible, use a working_area that doesn't need to be backed up,
4351 since performing a backup slows down operations.
4352 For example, the beginning of an SRAM block is likely to
4353 be used by most build systems, but the end is often unused.
4355 @item @code{-work-area-size} @var{size} -- specify work are size,
4356 in bytes. The same size applies regardless of whether its physical
4357 or virtual address is being used.
4359 @item @code{-work-area-phys} @var{address} -- set the work area
4360 base @var{address} to be used when no MMU is active.
4362 @item @code{-work-area-virt} @var{address} -- set the work area
4363 base @var{address} to be used when an MMU is active.
4364 @emph{Do not specify a value for this except on targets with an MMU.}
4365 The value should normally correspond to a static mapping for the
4366 @code{-work-area-phys} address, set up by the current operating system.
4368 @anchor{rtostype}
4369 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4370 @var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}|
4371 @option{FreeRTOS}|@option{linux}|@option{ChibiOS}|@option{embKernel}
4372 @xref{gdbrtossupport,,RTOS Support}.
4374 @end itemize
4375 @end deffn
4377 @section Other $target_name Commands
4378 @cindex object command
4380 The Tcl/Tk language has the concept of object commands,
4381 and OpenOCD adopts that same model for targets.
4383 A good Tk example is a on screen button.
4384 Once a button is created a button
4385 has a name (a path in Tk terms) and that name is useable as a first
4386 class command. For example in Tk, one can create a button and later
4387 configure it like this:
4389 @example
4390 # Create
4391 button .foobar -background red -command @{ foo @}
4392 # Modify
4393 .foobar configure -foreground blue
4394 # Query
4395 set x [.foobar cget -background]
4396 # Report
4397 puts [format "The button is %s" $x]
4398 @end example
4400 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4401 button, and its object commands are invoked the same way.
4403 @example
4404 str912.cpu mww 0x1234 0x42
4405 omap3530.cpu mww 0x5555 123
4406 @end example
4408 The commands supported by OpenOCD target objects are:
4410 @deffn Command {$target_name arp_examine}
4411 @deffnx Command {$target_name arp_halt}
4412 @deffnx Command {$target_name arp_poll}
4413 @deffnx Command {$target_name arp_reset}
4414 @deffnx Command {$target_name arp_waitstate}
4415 Internal OpenOCD scripts (most notably @file{startup.tcl})
4416 use these to deal with specific reset cases.
4417 They are not otherwise documented here.
4418 @end deffn
4420 @deffn Command {$target_name array2mem} arrayname width address count
4421 @deffnx Command {$target_name mem2array} arrayname width address count
4422 These provide an efficient script-oriented interface to memory.
4423 The @code{array2mem} primitive writes bytes, halfwords, or words;
4424 while @code{mem2array} reads them.
4425 In both cases, the TCL side uses an array, and
4426 the target side uses raw memory.
4428 The efficiency comes from enabling the use of
4429 bulk JTAG data transfer operations.
4430 The script orientation comes from working with data
4431 values that are packaged for use by TCL scripts;
4432 @command{mdw} type primitives only print data they retrieve,
4433 and neither store nor return those values.
4435 @itemize
4436 @item @var{arrayname} ... is the name of an array variable
4437 @item @var{width} ... is 8/16/32 - indicating the memory access size
4438 @item @var{address} ... is the target memory address
4439 @item @var{count} ... is the number of elements to process
4440 @end itemize
4441 @end deffn
4443 @deffn Command {$target_name cget} queryparm
4444 Each configuration parameter accepted by
4445 @command{$target_name configure}
4446 can be individually queried, to return its current value.
4447 The @var{queryparm} is a parameter name
4448 accepted by that command, such as @code{-work-area-phys}.
4449 There are a few special cases:
4451 @itemize @bullet
4452 @item @code{-event} @var{event_name} -- returns the handler for the
4453 event named @var{event_name}.
4454 This is a special case because setting a handler requires
4455 two parameters.
4456 @item @code{-type} -- returns the target type.
4457 This is a special case because this is set using
4458 @command{target create} and can't be changed
4459 using @command{$target_name configure}.
4460 @end itemize
4462 For example, if you wanted to summarize information about
4463 all the targets you might use something like this:
4465 @example
4466 foreach name [target names] @{
4467 set y [$name cget -endian]
4468 set z [$name cget -type]
4469 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4470 $x $name $y $z]
4471 @}
4472 @end example
4473 @end deffn
4475 @anchor{targetcurstate}
4476 @deffn Command {$target_name curstate}
4477 Displays the current target state:
4478 @code{debug-running},
4479 @code{halted},
4480 @code{reset},
4481 @code{running}, or @code{unknown}.
4482 (Also, @pxref{eventpolling,,Event Polling}.)
4483 @end deffn
4485 @deffn Command {$target_name eventlist}
4486 Displays a table listing all event handlers
4487 currently associated with this target.
4488 @xref{targetevents,,Target Events}.
4489 @end deffn
4491 @deffn Command {$target_name invoke-event} event_name
4492 Invokes the handler for the event named @var{event_name}.
4493 (This is primarily intended for use by OpenOCD framework
4494 code, for example by the reset code in @file{startup.tcl}.)
4495 @end deffn
4497 @deffn Command {$target_name mdw} addr [count]
4498 @deffnx Command {$target_name mdh} addr [count]
4499 @deffnx Command {$target_name mdb} addr [count]
4500 Display contents of address @var{addr}, as
4501 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4502 or 8-bit bytes (@command{mdb}).
4503 If @var{count} is specified, displays that many units.
4504 (If you want to manipulate the data instead of displaying it,
4505 see the @code{mem2array} primitives.)
4506 @end deffn
4508 @deffn Command {$target_name mww} addr word
4509 @deffnx Command {$target_name mwh} addr halfword
4510 @deffnx Command {$target_name mwb} addr byte
4511 Writes the specified @var{word} (32 bits),
4512 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4513 at the specified address @var{addr}.
4514 @end deffn
4516 @anchor{targetevents}
4517 @section Target Events
4518 @cindex target events
4519 @cindex events
4520 At various times, certain things can happen, or you want them to happen.
4521 For example:
4522 @itemize @bullet
4523 @item What should happen when GDB connects? Should your target reset?
4524 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4525 @item Is using SRST appropriate (and possible) on your system?
4526 Or instead of that, do you need to issue JTAG commands to trigger reset?
4527 SRST usually resets everything on the scan chain, which can be inappropriate.
4528 @item During reset, do you need to write to certain memory locations
4529 to set up system clocks or
4530 to reconfigure the SDRAM?
4531 How about configuring the watchdog timer, or other peripherals,
4532 to stop running while you hold the core stopped for debugging?
4533 @end itemize
4535 All of the above items can be addressed by target event handlers.
4536 These are set up by @command{$target_name configure -event} or
4537 @command{target create ... -event}.
4539 The programmer's model matches the @code{-command} option used in Tcl/Tk
4540 buttons and events. The two examples below act the same, but one creates
4541 and invokes a small procedure while the other inlines it.
4543 @example
4544 proc my_attach_proc @{ @} @{
4545 echo "Reset..."
4546 reset halt
4547 @}
4548 mychip.cpu configure -event gdb-attach my_attach_proc
4549 mychip.cpu configure -event gdb-attach @{
4550 echo "Reset..."
4551 # To make flash probe and gdb load to flash work we need a reset init.
4552 reset init
4553 @}
4554 @end example
4556 The following target events are defined:
4558 @itemize @bullet
4559 @item @b{debug-halted}
4560 @* The target has halted for debug reasons (i.e.: breakpoint)
4561 @item @b{debug-resumed}
4562 @* The target has resumed (i.e.: gdb said run)
4563 @item @b{early-halted}
4564 @* Occurs early in the halt process
4565 @item @b{examine-start}
4566 @* Before target examine is called.
4567 @item @b{examine-end}
4568 @* After target examine is called with no errors.
4569 @item @b{gdb-attach}
4570 @* When GDB connects. This is before any communication with the target, so this
4571 can be used to set up the target so it is possible to probe flash. Probing flash
4572 is necessary during gdb connect if gdb load is to write the image to flash. Another
4573 use of the flash memory map is for GDB to automatically hardware/software breakpoints
4574 depending on whether the breakpoint is in RAM or read only memory.
4575 @item @b{gdb-detach}
4576 @* When GDB disconnects
4577 @item @b{gdb-end}
4578 @* When the target has halted and GDB is not doing anything (see early halt)
4579 @item @b{gdb-flash-erase-start}
4580 @* Before the GDB flash process tries to erase the flash
4581 @item @b{gdb-flash-erase-end}
4582 @* After the GDB flash process has finished erasing the flash
4583 @item @b{gdb-flash-write-start}
4584 @* Before GDB writes to the flash
4585 @item @b{gdb-flash-write-end}
4586 @* After GDB writes to the flash
4587 @item @b{gdb-start}
4588 @* Before the target steps, gdb is trying to start/resume the target
4589 @item @b{halted}
4590 @* The target has halted
4591 @item @b{reset-assert-pre}
4592 @* Issued as part of @command{reset} processing
4593 after @command{reset_init} was triggered
4594 but before either SRST alone is re-asserted on the scan chain,
4595 or @code{reset-assert} is triggered.
4596 @item @b{reset-assert}
4597 @* Issued as part of @command{reset} processing
4598 after @command{reset-assert-pre} was triggered.
4599 When such a handler is present, cores which support this event will use
4600 it instead of asserting SRST.
4601 This support is essential for debugging with JTAG interfaces which
4602 don't include an SRST line (JTAG doesn't require SRST), and for
4603 selective reset on scan chains that have multiple targets.
4604 @item @b{reset-assert-post}
4605 @* Issued as part of @command{reset} processing
4606 after @code{reset-assert} has been triggered.
4607 or the target asserted SRST on the entire scan chain.
4608 @item @b{reset-deassert-pre}
4609 @* Issued as part of @command{reset} processing
4610 after @code{reset-assert-post} has been triggered.
4611 @item @b{reset-deassert-post}
4612 @* Issued as part of @command{reset} processing
4613 after @code{reset-deassert-pre} has been triggered
4614 and (if the target is using it) after SRST has been
4615 released on the scan chain.
4616 @item @b{reset-end}
4617 @* Issued as the final step in @command{reset} processing.
4618 @ignore
4619 @item @b{reset-halt-post}
4620 @* Currently not used
4621 @item @b{reset-halt-pre}
4622 @* Currently not used
4623 @end ignore
4624 @item @b{reset-init}
4625 @* Used by @b{reset init} command for board-specific initialization.
4626 This event fires after @emph{reset-deassert-post}.
4628 This is where you would configure PLLs and clocking, set up DRAM so
4629 you can download programs that don't fit in on-chip SRAM, set up pin
4630 multiplexing, and so on.
4631 (You may be able to switch to a fast JTAG clock rate here, after
4632 the target clocks are fully set up.)
4633 @item @b{reset-start}
4634 @* Issued as part of @command{reset} processing
4635 before @command{reset_init} is called.
4637 This is the most robust place to use @command{jtag_rclk}
4638 or @command{adapter_khz} to switch to a low JTAG clock rate,
4639 when reset disables PLLs needed to use a fast clock.
4640 @ignore
4641 @item @b{reset-wait-pos}
4642 @* Currently not used
4643 @item @b{reset-wait-pre}
4644 @* Currently not used
4645 @end ignore
4646 @item @b{resume-start}
4647 @* Before any target is resumed
4648 @item @b{resume-end}
4649 @* After all targets have resumed
4650 @item @b{resumed}
4651 @* Target has resumed
4652 @end itemize
4654 @node Flash Commands
4655 @chapter Flash Commands
4657 OpenOCD has different commands for NOR and NAND flash;
4658 the ``flash'' command works with NOR flash, while
4659 the ``nand'' command works with NAND flash.
4660 This partially reflects different hardware technologies:
4661 NOR flash usually supports direct CPU instruction and data bus access,
4662 while data from a NAND flash must be copied to memory before it can be
4663 used. (SPI flash must also be copied to memory before use.)
4664 However, the documentation also uses ``flash'' as a generic term;
4665 for example, ``Put flash configuration in board-specific files''.
4667 Flash Steps:
4668 @enumerate
4669 @item Configure via the command @command{flash bank}
4670 @* Do this in a board-specific configuration file,
4671 passing parameters as needed by the driver.
4672 @item Operate on the flash via @command{flash subcommand}
4673 @* Often commands to manipulate the flash are typed by a human, or run
4674 via a script in some automated way. Common tasks include writing a
4675 boot loader, operating system, or other data.
4676 @item GDB Flashing
4677 @* Flashing via GDB requires the flash be configured via ``flash
4678 bank'', and the GDB flash features be enabled.
4679 @xref{gdbconfiguration,,GDB Configuration}.
4680 @end enumerate
4682 Many CPUs have the ablity to ``boot'' from the first flash bank.
4683 This means that misprogramming that bank can ``brick'' a system,
4684 so that it can't boot.
4685 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4686 board by (re)installing working boot firmware.
4688 @anchor{norconfiguration}
4689 @section Flash Configuration Commands
4690 @cindex flash configuration
4692 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4693 Configures a flash bank which provides persistent storage
4694 for addresses from @math{base} to @math{base + size - 1}.
4695 These banks will often be visible to GDB through the target's memory map.
4696 In some cases, configuring a flash bank will activate extra commands;
4697 see the driver-specific documentation.
4699 @itemize @bullet
4700 @item @var{name} ... may be used to reference the flash bank
4701 in other flash commands. A number is also available.
4702 @item @var{driver} ... identifies the controller driver
4703 associated with the flash bank being declared.
4704 This is usually @code{cfi} for external flash, or else
4705 the name of a microcontroller with embedded flash memory.
4706 @xref{flashdriverlist,,Flash Driver List}.
4707 @item @var{base} ... Base address of the flash chip.
4708 @item @var{size} ... Size of the chip, in bytes.
4709 For some drivers, this value is detected from the hardware.
4710 @item @var{chip_width} ... Width of the flash chip, in bytes;
4711 ignored for most microcontroller drivers.
4712 @item @var{bus_width} ... Width of the data bus used to access the
4713 chip, in bytes; ignored for most microcontroller drivers.
4714 @item @var{target} ... Names the target used to issue
4715 commands to the flash controller.
4716 @comment Actually, it's currently a controller-specific parameter...
4717 @item @var{driver_options} ... drivers may support, or require,
4718 additional parameters. See the driver-specific documentation
4719 for more information.
4720 @end itemize
4721 @quotation Note
4722 This command is not available after OpenOCD initialization has completed.
4723 Use it in board specific configuration files, not interactively.
4724 @end quotation
4725 @end deffn
4727 @comment the REAL name for this command is "ocd_flash_banks"
4728 @comment less confusing would be: "flash list" (like "nand list")
4729 @deffn Command {flash banks}
4730 Prints a one-line summary of each device that was
4731 declared using @command{flash bank}, numbered from zero.
4732 Note that this is the @emph{plural} form;
4733 the @emph{singular} form is a very different command.
4734 @end deffn
4736 @deffn Command {flash list}
4737 Retrieves a list of associative arrays for each device that was
4738 declared using @command{flash bank}, numbered from zero.
4739 This returned list can be manipulated easily from within scripts.
4740 @end deffn
4742 @deffn Command {flash probe} num
4743 Identify the flash, or validate the parameters of the configured flash. Operation
4744 depends on the flash type.
4745 The @var{num} parameter is a value shown by @command{flash banks}.
4746 Most flash commands will implicitly @emph{autoprobe} the bank;
4747 flash drivers can distinguish between probing and autoprobing,
4748 but most don't bother.
4749 @end deffn
4751 @section Erasing, Reading, Writing to Flash
4752 @cindex flash erasing
4753 @cindex flash reading
4754 @cindex flash writing
4755 @cindex flash programming
4756 @anchor{flashprogrammingcommands}
4758 One feature distinguishing NOR flash from NAND or serial flash technologies
4759 is that for read access, it acts exactly like any other addressible memory.
4760 This means you can use normal memory read commands like @command{mdw} or
4761 @command{dump_image} with it, with no special @command{flash} subcommands.
4762 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
4764 Write access works differently. Flash memory normally needs to be erased
4765 before it's written. Erasing a sector turns all of its bits to ones, and
4766 writing can turn ones into zeroes. This is why there are special commands
4767 for interactive erasing and writing, and why GDB needs to know which parts
4768 of the address space hold NOR flash memory.
4770 @quotation Note
4771 Most of these erase and write commands leverage the fact that NOR flash
4772 chips consume target address space. They implicitly refer to the current
4773 JTAG target, and map from an address in that target's address space
4774 back to a flash bank.
4775 @comment In May 2009, those mappings may fail if any bank associated
4776 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
4777 A few commands use abstract addressing based on bank and sector numbers,
4778 and don't depend on searching the current target and its address space.
4779 Avoid confusing the two command models.
4780 @end quotation
4782 Some flash chips implement software protection against accidental writes,
4783 since such buggy writes could in some cases ``brick'' a system.
4784 For such systems, erasing and writing may require sector protection to be
4785 disabled first.
4786 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4787 and AT91SAM7 on-chip flash.
4788 @xref{flashprotect,,flash protect}.
4790 @deffn Command {flash erase_sector} num first last
4791 Erase sectors in bank @var{num}, starting at sector @var{first}
4792 up to and including @var{last}.
4793 Sector numbering starts at 0.
4794 Providing a @var{last} sector of @option{last}
4795 specifies "to the end of the flash bank".
4796 The @var{num} parameter is a value shown by @command{flash banks}.
4797 @end deffn
4799 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4800 Erase sectors starting at @var{address} for @var{length} bytes.
4801 Unless @option{pad} is specified, @math{address} must begin a
4802 flash sector, and @math{address + length - 1} must end a sector.
4803 Specifying @option{pad} erases extra data at the beginning and/or
4804 end of the specified region, as needed to erase only full sectors.
4805 The flash bank to use is inferred from the @var{address}, and
4806 the specified length must stay within that bank.
4807 As a special case, when @var{length} is zero and @var{address} is
4808 the start of the bank, the whole flash is erased.
4809 If @option{unlock} is specified, then the flash is unprotected
4810 before erase starts.
4811 @end deffn
4813 @deffn Command {flash fillw} address word length
4814 @deffnx Command {flash fillh} address halfword length
4815 @deffnx Command {flash fillb} address byte length
4816 Fills flash memory with the specified @var{word} (32 bits),
4817 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4818 starting at @var{address} and continuing
4819 for @var{length} units (word/halfword/byte).
4820 No erasure is done before writing; when needed, that must be done
4821 before issuing this command.
4822 Writes are done in blocks of up to 1024 bytes, and each write is
4823 verified by reading back the data and comparing it to what was written.
4824 The flash bank to use is inferred from the @var{address} of
4825 each block, and the specified length must stay within that bank.
4826 @end deffn
4827 @comment no current checks for errors if fill blocks touch multiple banks!
4829 @deffn Command {flash write_bank} num filename offset
4830 Write the binary @file{filename} to flash bank @var{num},
4831 starting at @var{offset} bytes from the beginning of the bank.
4832 The @var{num} parameter is a value shown by @command{flash banks}.
4833 @end deffn
4835 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4836 Write the image @file{filename} to the current target's flash bank(s).
4837 A relocation @var{offset} may be specified, in which case it is added
4838 to the base address for each section in the image.
4839 The file [@var{type}] can be specified
4840 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4841 @option{elf} (ELF file), @option{s19} (Motorola s19).
4842 @option{mem}, or @option{builder}.
4843 The relevant flash sectors will be erased prior to programming
4844 if the @option{erase} parameter is given. If @option{unlock} is
4845 provided, then the flash banks are unlocked before erase and
4846 program. The flash bank to use is inferred from the address of
4847 each image section.
4849 @quotation Warning
4850 Be careful using the @option{erase} flag when the flash is holding
4851 data you want to preserve.
4852 Portions of the flash outside those described in the image's
4853 sections might be erased with no notice.
4854 @itemize
4855 @item
4856 When a section of the image being written does not fill out all the
4857 sectors it uses, the unwritten parts of those sectors are necessarily
4858 also erased, because sectors can't be partially erased.
4859 @item
4860 Data stored in sector "holes" between image sections are also affected.
4861 For example, "@command{flash write_image erase ...}" of an image with
4862 one byte at the beginning of a flash bank and one byte at the end
4863 erases the entire bank -- not just the two sectors being written.
4864 @end itemize
4865 Also, when flash protection is important, you must re-apply it after
4866 it has been removed by the @option{unlock} flag.
4867 @end quotation
4869 @end deffn
4871 @section Other Flash commands
4872 @cindex flash protection
4874 @deffn Command {flash erase_check} num
4875 Check erase state of sectors in flash bank @var{num},
4876 and display that status.
4877 The @var{num} parameter is a value shown by @command{flash banks}.
4878 @end deffn
4880 @deffn Command {flash info} num
4881 Print info about flash bank @var{num}
4882 The @var{num} parameter is a value shown by @command{flash banks}.
4883 This command will first query the hardware, it does not print cached
4884 and possibly stale information.
4885 @end deffn
4887 @anchor{flashprotect}
4888 @deffn Command {flash protect} num first last (@option{on}|@option{off})
4889 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
4890 in flash bank @var{num}, starting at sector @var{first}
4891 and continuing up to and including @var{last}.
4892 Providing a @var{last} sector of @option{last}
4893 specifies "to the end of the flash bank".
4894 The @var{num} parameter is a value shown by @command{flash banks}.
4895 @end deffn
4897 @deffn Command {flash padded_value} num value
4898 Sets the default value used for padding any image sections, This should
4899 normally match the flash bank erased value. If not specified by this
4900 comamnd or the flash driver then it defaults to 0xff.
4901 @end deffn
4903 @anchor{program}
4904 @deffn Command {program} filename [verify] [reset] [offset]
4905 This is a helper script that simplifies using OpenOCD as a standalone
4906 programmer. The only required parameter is @option{filename}, the others are optional.
4907 @xref{Flash Programming}.
4908 @end deffn
4910 @anchor{flashdriverlist}
4911 @section Flash Driver List
4912 As noted above, the @command{flash bank} command requires a driver name,
4913 and allows driver-specific options and behaviors.
4914 Some drivers also activate driver-specific commands.
4916 @subsection External Flash
4918 @deffn {Flash Driver} cfi
4919 @cindex Common Flash Interface
4920 @cindex CFI
4921 The ``Common Flash Interface'' (CFI) is the main standard for
4922 external NOR flash chips, each of which connects to a
4923 specific external chip select on the CPU.
4924 Frequently the first such chip is used to boot the system.
4925 Your board's @code{reset-init} handler might need to
4926 configure additional chip selects using other commands (like: @command{mww} to
4927 configure a bus and its timings), or
4928 perhaps configure a GPIO pin that controls the ``write protect'' pin
4929 on the flash chip.
4930 The CFI driver can use a target-specific working area to significantly
4931 speed up operation.
4933 The CFI driver can accept the following optional parameters, in any order:
4935 @itemize
4936 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
4937 like AM29LV010 and similar types.
4938 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
4939 @end itemize
4941 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
4942 wide on a sixteen bit bus:
4944 @example
4945 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
4946 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
4947 @end example
4949 To configure one bank of 32 MBytes
4950 built from two sixteen bit (two byte) wide parts wired in parallel
4951 to create a thirty-two bit (four byte) bus with doubled throughput:
4953 @example
4954 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
4955 @end example
4957 @c "cfi part_id" disabled
4958 @end deffn
4960 @deffn {Flash Driver} lpcspifi
4961 @cindex NXP SPI Flash Interface
4962 @cindex SPIFI
4963 @cindex lpcspifi
4964 NXP's LPC43xx and LPC18xx families include a proprietary SPI
4965 Flash Interface (SPIFI) peripheral that can drive and provide
4966 memory mapped access to external SPI flash devices.
4968 The lpcspifi driver initializes this interface and provides
4969 program and erase functionality for these serial flash devices.
4970 Use of this driver @b{requires} a working area of at least 1kB
4971 to be configured on the target device; more than this will
4972 significantly reduce flash programming times.
4974 The setup command only requires the @var{base} parameter. All
4975 other parameters are ignored, and the flash size and layout
4976 are configured by the driver.
4978 @example
4979 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
4980 @end example
4982 @end deffn
4984 @deffn {Flash Driver} stmsmi
4985 @cindex STMicroelectronics Serial Memory Interface
4986 @cindex SMI
4987 @cindex stmsmi
4988 Some devices form STMicroelectronics (e.g. STR75x MCU family,
4989 SPEAr MPU family) include a proprietary
4990 ``Serial Memory Interface'' (SMI) controller able to drive external
4991 SPI flash devices.
4992 Depending on specific device and board configuration, up to 4 external
4993 flash devices can be connected.
4995 SMI makes the flash content directly accessible in the CPU address
4996 space; each external device is mapped in a memory bank.
4997 CPU can directly read data, execute code and boot from SMI banks.
4998 Normal OpenOCD commands like @command{mdw} can be used to display
4999 the flash content.
5001 The setup command only requires the @var{base} parameter in order
5002 to identify the memory bank.
5003 All other parameters are ignored. Additional information, like
5004 flash size, are detected automatically.
5006 @example
5007 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
5008 @end example
5010 @end deffn
5012 @subsection Internal Flash (Microcontrollers)
5014 @deffn {Flash Driver} aduc702x
5015 The ADUC702x analog microcontrollers from Analog Devices
5016 include internal flash and use ARM7TDMI cores.
5017 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
5018 The setup command only requires the @var{target} argument
5019 since all devices in this family have the same memory layout.
5021 @example
5022 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
5023 @end example
5024 @end deffn
5026 @anchor{at91sam3}
5027 @deffn {Flash Driver} at91sam3
5028 @cindex at91sam3
5029 All members of the AT91SAM3 microcontroller family from
5030 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
5031 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
5032 that the driver was orginaly developed and tested using the
5033 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chip