doc: Update list of interfaces, targets and boards
[openocd.git] / doc / openocd.texi
1 \input texinfo @c -*-texinfo-*-
2 @c %**start of header
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
6 @direntry
7 * OpenOCD: (openocd). OpenOCD User's Guide
8 @end direntry
9 @paragraphindent 0
10 @c %**end of header
11
12 @include version.texi
13
14 @copying
15
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
20
21 @itemize @bullet
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
27 @end itemize
28
29 @quotation
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
36 @end quotation
37 @end copying
38
39 @titlepage
40 @titlefont{@emph{Open On-Chip Debugger:}}
41 @sp 1
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
45
46 @page
47 @vskip 0pt plus 1filll
48 @insertcopying
49 @end titlepage
50
51 @summarycontents
52 @contents
53
54 @ifnottex
55 @node Top
56 @top OpenOCD User's Guide
57
58 @insertcopying
59 @end ifnottex
60
61 @menu
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * NAND Flash Commands:: NAND Flash Commands
77 * PLD/FPGA Commands:: PLD/FPGA Commands
78 * General Commands:: General Commands
79 * Architecture and Core Commands:: Architecture and Core Commands
80 * JTAG Commands:: JTAG Commands
81 * Boundary Scan Commands:: Boundary Scan Commands
82 * TFTP:: TFTP
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
88
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
95 @end menu
96
97 @node About
98 @unnumbered About
99 @cindex about
100
101 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
102 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
105 around the world.
106
107 @section What is OpenOCD?
108 @cindex TAP
109 @cindex JTAG
110
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
113 devices.
114
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
121
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
127
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board can be directly connected to the debug
132 host over USB (and sometimes also to power it over USB).
133
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
140 scan operations.
141
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD only supports
145 debugging, whereas JTAG also supports boundary scan operations.
146
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
151
152
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
154 based, parallel port based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
156
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
159 Cortex-M3 (Stellaris LM3, ST STM32 and Energy Micro EFM32) based cores to be
160 debugged via the GDB protocol.
161
162 @b{Flash Programing:} Flash writing is supported for external CFI
163 compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) controller is included.
167
168 @section OpenOCD Web Site
169
170 The OpenOCD web site provides the latest public news from the community:
171
172 @uref{http://openocd.sourceforge.net/}
173
174 @section Latest User's Guide:
175
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
179
180 @uref{http://openocd.sourceforge.net/doc/html/index.html}
181
182 PDF form is likewise published at:
183
184 @uref{http://openocd.sourceforge.net/doc/pdf/openocd.pdf}
185
186 @section OpenOCD User's Forum
187
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
193
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
195
196 @section OpenOCD User's Mailing List
197
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
200
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
202
203 @section OpenOCD IRC
204
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
207
208 @node Developers
209 @chapter OpenOCD Developer Resources
210 @cindex developers
211
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
216
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
219
220 @section OpenOCD GIT Repository
221
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a GIT repository hosted at SourceForge. The repository URL is:
224
225 @uref{git://git.code.sf.net/p/openocd/code}
226
227 or via http
228
229 @uref{http://git.code.sf.net/p/openocd/code}
230
231 You may prefer to use a mirror and the HTTP protocol:
232
233 @uref{http://repo.or.cz/r/openocd.git}
234
235 With standard GIT tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a GIT client:
240
241 @uref{http://repo.or.cz/w/openocd.git}
242
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
245
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
250
251 @section Doxygen Developer Manual
252
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
257
258 @uref{http://openocd.sourceforge.net/doc/doxygen/html/index.html}
259
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration in the top of the source tree.
263
264 @section OpenOCD Developer Mailing List
265
266 The OpenOCD Developer Mailing List provides the primary means of
267 communication between developers:
268
269 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
270
271 Discuss and submit patches to this list.
272 The @file{HACKING} file contains basic information about how
273 to prepare patches.
274
275 @section OpenOCD Bug Database
276
277 During the 0.4.x release cycle the OpenOCD project team began
278 using Trac for its bug database:
279
280 @uref{https://sourceforge.net/apps/trac/openocd}
281
282
283 @node Debug Adapter Hardware
284 @chapter Debug Adapter Hardware
285 @cindex dongles
286 @cindex FTDI
287 @cindex wiggler
288 @cindex zy1000
289 @cindex printer port
290 @cindex USB Adapter
291 @cindex RTCK
292
293 Defined: @b{dongle}: A small device that plugins into a computer and serves as
294 an adapter .... [snip]
295
296 In the OpenOCD case, this generally refers to @b{a small adapter} that
297 attaches to your computer via USB or the Parallel Printer Port. One
298 exception is the Zylin ZY1000, packaged as a small box you attach via
299 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
300 require any drivers to be installed on the developer PC. It also has
301 a built in web interface. It supports RTCK/RCLK or adaptive clocking
302 and has a built in relay to power cycle targets remotely.
303
304
305 @section Choosing a Dongle
306
307 There are several things you should keep in mind when choosing a dongle.
308
309 @enumerate
310 @item @b{Transport} Does it support the kind of communication that you need?
311 OpenOCD focusses mostly on JTAG. Your version may also support
312 other ways to communicate with target devices.
313 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
314 Does your dongle support it? You might need a level converter.
315 @item @b{Pinout} What pinout does your target board use?
316 Does your dongle support it? You may be able to use jumper
317 wires, or an "octopus" connector, to convert pinouts.
318 @item @b{Connection} Does your computer have the USB, printer, or
319 Ethernet port needed?
320 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
321 RTCK support? Also known as ``adaptive clocking''
322 @end enumerate
323
324 @section Stand alone Systems
325
326 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/33-zylin-zy1000-jtag-probe}
327 Technically, not a dongle, but a standalone box. The ZY1000 has the advantage that it does
328 not require any drivers installed on the developer PC. It also has
329 a built in web interface. It supports RTCK/RCLK or adaptive clocking
330 and has a built in relay to power cycle targets remotely.
331
332 @section USB FT2232 Based
333
334 There are many USB JTAG dongles on the market, many of them are based
335 on a chip from ``Future Technology Devices International'' (FTDI)
336 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
337 See: @url{http://www.ftdichip.com} for more information.
338 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
339 chips are starting to become available in JTAG adapters. (Adapters
340 using those high speed FT2232H chips may support adaptive clocking.)
341
342 The FT2232 chips are flexible enough to support some other
343 transport options, such as SWD or the SPI variants used to
344 program some chips. They have two communications channels,
345 and one can be used for a UART adapter at the same time the
346 other one is used to provide a debug adapter.
347
348 Also, some development boards integrate an FT2232 chip to serve as
349 a built-in low cost debug adapter and usb-to-serial solution.
350
351 @itemize @bullet
352 @item @b{usbjtag}
353 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
354 @item @b{jtagkey}
355 @* See: @url{http://www.amontec.com/jtagkey.shtml}
356 @item @b{jtagkey2}
357 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
358 @item @b{oocdlink}
359 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
360 @item @b{signalyzer}
361 @* See: @url{http://www.signalyzer.com}
362 @item @b{Stellaris Eval Boards}
363 @* See: @url{http://www.ti.com} - The Stellaris eval boards
364 bundle FT2232-based JTAG and SWD support, which can be used to debug
365 the Stellaris chips. Using separate JTAG adapters is optional.
366 These boards can also be used in a "pass through" mode as JTAG adapters
367 to other target boards, disabling the Stellaris chip.
368 @item @b{TI/Luminary ICDI}
369 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
370 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
371 Evaluation Kits. Like the non-detachable FT2232 support on the other
372 Stellaris eval boards, they can be used to debug other target boards.
373 @item @b{olimex-jtag}
374 @* See: @url{http://www.olimex.com}
375 @item @b{Flyswatter/Flyswatter2}
376 @* See: @url{http://www.tincantools.com}
377 @item @b{turtelizer2}
378 @* See:
379 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
380 @url{http://www.ethernut.de}
381 @item @b{comstick}
382 @* Link: @url{http://www.hitex.com/index.php?id=383}
383 @item @b{stm32stick}
384 @* Link @url{http://www.hitex.com/stm32-stick}
385 @item @b{axm0432_jtag}
386 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
387 to be available anymore as of April 2012.
388 @item @b{cortino}
389 @* Link @url{http://www.hitex.com/index.php?id=cortino}
390 @item @b{dlp-usb1232h}
391 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
392 @item @b{digilent-hs1}
393 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
394 @item @b{opendous}
395 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
396 (OpenHardware).
397 @end itemize
398
399 @section USB-JTAG / Altera USB-Blaster compatibles
400
401 These devices also show up as FTDI devices, but are not
402 protocol-compatible with the FT2232 devices. They are, however,
403 protocol-compatible among themselves. USB-JTAG devices typically consist
404 of a FT245 followed by a CPLD that understands a particular protocol,
405 or emulate this protocol using some other hardware.
406
407 They may appear under different USB VID/PID depending on the particular
408 product. The driver can be configured to search for any VID/PID pair
409 (see the section on driver commands).
410
411 @itemize
412 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
413 @* Link: @url{http://ixo-jtag.sourceforge.net/}
414 @item @b{Altera USB-Blaster}
415 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
416 @end itemize
417
418 @section USB JLINK based
419 There are several OEM versions of the Segger @b{JLINK} adapter. It is
420 an example of a micro controller based JTAG adapter, it uses an
421 AT91SAM764 internally.
422
423 @itemize @bullet
424 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
425 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
426 @item @b{SEGGER JLINK}
427 @* Link: @url{http://www.segger.com/jlink.html}
428 @item @b{IAR J-Link}
429 @* Link: @url{http://www.iar.com/en/products/hardware-debug-probes/iar-j-link/}
430 @end itemize
431
432 @section USB RLINK based
433 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
434 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
435 SWD and not JTAG, thus not supported.
436
437 @itemize @bullet
438 @item @b{Raisonance RLink}
439 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
440 @item @b{STM32 Primer}
441 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
442 @item @b{STM32 Primer2}
443 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
444 @end itemize
445
446 @section USB ST-LINK based
447 ST Micro has an adapter called @b{ST-LINK}.
448 They only work with ST Micro chips, notably STM32 and STM8.
449
450 @itemize @bullet
451 @item @b{ST-LINK}
452 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
453 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
454 @item @b{ST-LINK/V2}
455 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
456 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
457 @end itemize
458
459 For info the original ST-LINK enumerates using the mass storage usb class, however
460 it's implementation is completely broken. The result is this causes issues under linux.
461 The simplest solution is to get linux to ignore the ST-LINK using one of the following methods:
462 @itemize @bullet
463 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
464 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
465 @end itemize
466
467 @section USB TI/Stellaris ICDI based
468 Texas Instruments has an adapter called @b{ICDI}.
469 It is not to be confused with the FTDI based adapters that were originally fitted to their
470 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
471
472 @section USB Other
473 @itemize @bullet
474 @item @b{USBprog}
475 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
476
477 @item @b{USB - Presto}
478 @* Link: @url{http://tools.asix.net/prg_presto.htm}
479
480 @item @b{Versaloon-Link}
481 @* Link: @url{http://www.versaloon.com}
482
483 @item @b{ARM-JTAG-EW}
484 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
485
486 @item @b{Buspirate}
487 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
488
489 @item @b{opendous}
490 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
491
492 @item @b{estick}
493 @* Link: @url{http://code.google.com/p/estick-jtag/}
494
495 @item @b{Keil ULINK v1}
496 @* Link: @url{http://www.keil.com/ulink1/}
497 @end itemize
498
499 @section IBM PC Parallel Printer Port Based
500
501 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
502 and the Macraigor Wiggler. There are many clones and variations of
503 these on the market.
504
505 Note that parallel ports are becoming much less common, so if you
506 have the choice you should probably avoid these adapters in favor
507 of USB-based ones.
508
509 @itemize @bullet
510
511 @item @b{Wiggler} - There are many clones of this.
512 @* Link: @url{http://www.macraigor.com/wiggler.htm}
513
514 @item @b{DLC5} - From XILINX - There are many clones of this
515 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
516 produced, PDF schematics are easily found and it is easy to make.
517
518 @item @b{Amontec - JTAG Accelerator}
519 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
520
521 @item @b{GW16402}
522 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
523
524 @item @b{Wiggler2}
525 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
526
527 @item @b{Wiggler_ntrst_inverted}
528 @* Yet another variation - See the source code, src/jtag/parport.c
529
530 @item @b{old_amt_wiggler}
531 @* Unknown - probably not on the market today
532
533 @item @b{arm-jtag}
534 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
535
536 @item @b{chameleon}
537 @* Link: @url{http://www.amontec.com/chameleon.shtml}
538
539 @item @b{Triton}
540 @* Unknown.
541
542 @item @b{Lattice}
543 @* ispDownload from Lattice Semiconductor
544 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
545
546 @item @b{flashlink}
547 @* From ST Microsystems;
548 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
549
550 @end itemize
551
552 @section Other...
553 @itemize @bullet
554
555 @item @b{ep93xx}
556 @* An EP93xx based Linux machine using the GPIO pins directly.
557
558 @item @b{at91rm9200}
559 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
560
561 @end itemize
562
563 @node About Jim-Tcl
564 @chapter About Jim-Tcl
565 @cindex Jim-Tcl
566 @cindex tcl
567
568 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
569 This programming language provides a simple and extensible
570 command interpreter.
571
572 All commands presented in this Guide are extensions to Jim-Tcl.
573 You can use them as simple commands, without needing to learn
574 much of anything about Tcl.
575 Alternatively, can write Tcl programs with them.
576
577 You can learn more about Jim at its website, @url{http://jim.berlios.de}.
578 There is an active and responsive community, get on the mailing list
579 if you have any questions. Jim-Tcl maintainers also lurk on the
580 OpenOCD mailing list.
581
582 @itemize @bullet
583 @item @b{Jim vs. Tcl}
584 @* Jim-Tcl is a stripped down version of the well known Tcl language,
585 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
586 fewer features. Jim-Tcl is several dozens of .C files and .H files and
587 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
588 4.2 MB .zip file containing 1540 files.
589
590 @item @b{Missing Features}
591 @* Our practice has been: Add/clone the real Tcl feature if/when
592 needed. We welcome Jim-Tcl improvements, not bloat. Also there
593 are a large number of optional Jim-Tcl features that are not
594 enabled in OpenOCD.
595
596 @item @b{Scripts}
597 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
598 command interpreter today is a mixture of (newer)
599 Jim-Tcl commands, and (older) the orginal command interpreter.
600
601 @item @b{Commands}
602 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
603 can type a Tcl for() loop, set variables, etc.
604 Some of the commands documented in this guide are implemented
605 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
606
607 @item @b{Historical Note}
608 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
609 before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
610 as a git submodule, which greatly simplified upgrading Jim Tcl
611 to benefit from new features and bugfixes in Jim Tcl.
612
613 @item @b{Need a crash course in Tcl?}
614 @*@xref{Tcl Crash Course}.
615 @end itemize
616
617 @node Running
618 @chapter Running
619 @cindex command line options
620 @cindex logfile
621 @cindex directory search
622
623 Properly installing OpenOCD sets up your operating system to grant it access
624 to the debug adapters. On Linux, this usually involves installing a file
625 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
626 complex and confusing driver configuration for every peripheral. Such issues
627 are unique to each operating system, and are not detailed in this User's Guide.
628
629 Then later you will invoke the OpenOCD server, with various options to
630 tell it how each debug session should work.
631 The @option{--help} option shows:
632 @verbatim
633 bash$ openocd --help
634
635 --help | -h display this help
636 --version | -v display OpenOCD version
637 --file | -f use configuration file <name>
638 --search | -s dir to search for config files and scripts
639 --debug | -d set debug level <0-3>
640 --log_output | -l redirect log output to file <name>
641 --command | -c run <command>
642 @end verbatim
643
644 If you don't give any @option{-f} or @option{-c} options,
645 OpenOCD tries to read the configuration file @file{openocd.cfg}.
646 To specify one or more different
647 configuration files, use @option{-f} options. For example:
648
649 @example
650 openocd -f config1.cfg -f config2.cfg -f config3.cfg
651 @end example
652
653 Configuration files and scripts are searched for in
654 @enumerate
655 @item the current directory,
656 @item any search dir specified on the command line using the @option{-s} option,
657 @item any search dir specified using the @command{add_script_search_dir} command,
658 @item @file{$HOME/.openocd} (not on Windows),
659 @item the site wide script library @file{$pkgdatadir/site} and
660 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
661 @end enumerate
662 The first found file with a matching file name will be used.
663
664 @quotation Note
665 Don't try to use configuration script names or paths which
666 include the "#" character. That character begins Tcl comments.
667 @end quotation
668
669 @section Simple setup, no customization
670
671 In the best case, you can use two scripts from one of the script
672 libraries, hook up your JTAG adapter, and start the server ... and
673 your JTAG setup will just work "out of the box". Always try to
674 start by reusing those scripts, but assume you'll need more
675 customization even if this works. @xref{OpenOCD Project Setup}.
676
677 If you find a script for your JTAG adapter, and for your board or
678 target, you may be able to hook up your JTAG adapter then start
679 the server like:
680
681 @example
682 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
683 @end example
684
685 You might also need to configure which reset signals are present,
686 using @option{-c 'reset_config trst_and_srst'} or something similar.
687 If all goes well you'll see output something like
688
689 @example
690 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
691 For bug reports, read
692 http://openocd.sourceforge.net/doc/doxygen/bugs.html
693 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
694 (mfg: 0x23b, part: 0xba00, ver: 0x3)
695 @end example
696
697 Seeing that "tap/device found" message, and no warnings, means
698 the JTAG communication is working. That's a key milestone, but
699 you'll probably need more project-specific setup.
700
701 @section What OpenOCD does as it starts
702
703 OpenOCD starts by processing the configuration commands provided
704 on the command line or, if there were no @option{-c command} or
705 @option{-f file.cfg} options given, in @file{openocd.cfg}.
706 @xref{configurationstage,,Configuration Stage}.
707 At the end of the configuration stage it verifies the JTAG scan
708 chain defined using those commands; your configuration should
709 ensure that this always succeeds.
710 Normally, OpenOCD then starts running as a daemon.
711 Alternatively, commands may be used to terminate the configuration
712 stage early, perform work (such as updating some flash memory),
713 and then shut down without acting as a daemon.
714
715 Once OpenOCD starts running as a daemon, it waits for connections from
716 clients (Telnet, GDB, Other) and processes the commands issued through
717 those channels.
718
719 If you are having problems, you can enable internal debug messages via
720 the @option{-d} option.
721
722 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
723 @option{-c} command line switch.
724
725 To enable debug output (when reporting problems or working on OpenOCD
726 itself), use the @option{-d} command line switch. This sets the
727 @option{debug_level} to "3", outputting the most information,
728 including debug messages. The default setting is "2", outputting only
729 informational messages, warnings and errors. You can also change this
730 setting from within a telnet or gdb session using @command{debug_level<n>}
731 (@pxref{debuglevel,,debug_level}).
732
733 You can redirect all output from the daemon to a file using the
734 @option{-l <logfile>} switch.
735
736 Note! OpenOCD will launch the GDB & telnet server even if it can not
737 establish a connection with the target. In general, it is possible for
738 the JTAG controller to be unresponsive until the target is set up
739 correctly via e.g. GDB monitor commands in a GDB init script.
740
741 @node OpenOCD Project Setup
742 @chapter OpenOCD Project Setup
743
744 To use OpenOCD with your development projects, you need to do more than
745 just connecting the JTAG adapter hardware (dongle) to your development board
746 and then starting the OpenOCD server.
747 You also need to configure that server so that it knows
748 about that adapter and board, and helps your work.
749 You may also want to connect OpenOCD to GDB, possibly
750 using Eclipse or some other GUI.
751
752 @section Hooking up the JTAG Adapter
753
754 Today's most common case is a dongle with a JTAG cable on one side
755 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
756 and a USB cable on the other.
757 Instead of USB, some cables use Ethernet;
758 older ones may use a PC parallel port, or even a serial port.
759
760 @enumerate
761 @item @emph{Start with power to your target board turned off},
762 and nothing connected to your JTAG adapter.
763 If you're particularly paranoid, unplug power to the board.
764 It's important to have the ground signal properly set up,
765 unless you are using a JTAG adapter which provides
766 galvanic isolation between the target board and the
767 debugging host.
768
769 @item @emph{Be sure it's the right kind of JTAG connector.}
770 If your dongle has a 20-pin ARM connector, you need some kind
771 of adapter (or octopus, see below) to hook it up to
772 boards using 14-pin or 10-pin connectors ... or to 20-pin
773 connectors which don't use ARM's pinout.
774
775 In the same vein, make sure the voltage levels are compatible.
776 Not all JTAG adapters have the level shifters needed to work
777 with 1.2 Volt boards.
778
779 @item @emph{Be certain the cable is properly oriented} or you might
780 damage your board. In most cases there are only two possible
781 ways to connect the cable.
782 Connect the JTAG cable from your adapter to the board.
783 Be sure it's firmly connected.
784
785 In the best case, the connector is keyed to physically
786 prevent you from inserting it wrong.
787 This is most often done using a slot on the board's male connector
788 housing, which must match a key on the JTAG cable's female connector.
789 If there's no housing, then you must look carefully and
790 make sure pin 1 on the cable hooks up to pin 1 on the board.
791 Ribbon cables are frequently all grey except for a wire on one
792 edge, which is red. The red wire is pin 1.
793
794 Sometimes dongles provide cables where one end is an ``octopus'' of
795 color coded single-wire connectors, instead of a connector block.
796 These are great when converting from one JTAG pinout to another,
797 but are tedious to set up.
798 Use these with connector pinout diagrams to help you match up the
799 adapter signals to the right board pins.
800
801 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
802 A USB, parallel, or serial port connector will go to the host which
803 you are using to run OpenOCD.
804 For Ethernet, consult the documentation and your network administrator.
805
806 For USB based JTAG adapters you have an easy sanity check at this point:
807 does the host operating system see the JTAG adapter? If that host is an
808 MS-Windows host, you'll need to install a driver before OpenOCD works.
809
810 @item @emph{Connect the adapter's power supply, if needed.}
811 This step is primarily for non-USB adapters,
812 but sometimes USB adapters need extra power.
813
814 @item @emph{Power up the target board.}
815 Unless you just let the magic smoke escape,
816 you're now ready to set up the OpenOCD server
817 so you can use JTAG to work with that board.
818
819 @end enumerate
820
821 Talk with the OpenOCD server using
822 telnet (@code{telnet localhost 4444} on many systems) or GDB.
823 @xref{GDB and OpenOCD}.
824
825 @section Project Directory
826
827 There are many ways you can configure OpenOCD and start it up.
828
829 A simple way to organize them all involves keeping a
830 single directory for your work with a given board.
831 When you start OpenOCD from that directory,
832 it searches there first for configuration files, scripts,
833 files accessed through semihosting,
834 and for code you upload to the target board.
835 It is also the natural place to write files,
836 such as log files and data you download from the board.
837
838 @section Configuration Basics
839
840 There are two basic ways of configuring OpenOCD, and
841 a variety of ways you can mix them.
842 Think of the difference as just being how you start the server:
843
844 @itemize
845 @item Many @option{-f file} or @option{-c command} options on the command line
846 @item No options, but a @dfn{user config file}
847 in the current directory named @file{openocd.cfg}
848 @end itemize
849
850 Here is an example @file{openocd.cfg} file for a setup
851 using a Signalyzer FT2232-based JTAG adapter to talk to
852 a board with an Atmel AT91SAM7X256 microcontroller:
853
854 @example
855 source [find interface/signalyzer.cfg]
856
857 # GDB can also flash my flash!
858 gdb_memory_map enable
859 gdb_flash_program enable
860
861 source [find target/sam7x256.cfg]
862 @end example
863
864 Here is the command line equivalent of that configuration:
865
866 @example
867 openocd -f interface/signalyzer.cfg \
868 -c "gdb_memory_map enable" \
869 -c "gdb_flash_program enable" \
870 -f target/sam7x256.cfg
871 @end example
872
873 You could wrap such long command lines in shell scripts,
874 each supporting a different development task.
875 One might re-flash the board with a specific firmware version.
876 Another might set up a particular debugging or run-time environment.
877
878 @quotation Important
879 At this writing (October 2009) the command line method has
880 problems with how it treats variables.
881 For example, after @option{-c "set VAR value"}, or doing the
882 same in a script, the variable @var{VAR} will have no value
883 that can be tested in a later script.
884 @end quotation
885
886 Here we will focus on the simpler solution: one user config
887 file, including basic configuration plus any TCL procedures
888 to simplify your work.
889
890 @section User Config Files
891 @cindex config file, user
892 @cindex user config file
893 @cindex config file, overview
894
895 A user configuration file ties together all the parts of a project
896 in one place.
897 One of the following will match your situation best:
898
899 @itemize
900 @item Ideally almost everything comes from configuration files
901 provided by someone else.
902 For example, OpenOCD distributes a @file{scripts} directory
903 (probably in @file{/usr/share/openocd/scripts} on Linux).
904 Board and tool vendors can provide these too, as can individual
905 user sites; the @option{-s} command line option lets you say
906 where to find these files. (@xref{Running}.)
907 The AT91SAM7X256 example above works this way.
908
909 Three main types of non-user configuration file each have their
910 own subdirectory in the @file{scripts} directory:
911
912 @enumerate
913 @item @b{interface} -- one for each different debug adapter;
914 @item @b{board} -- one for each different board
915 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
916 @end enumerate
917
918 Best case: include just two files, and they handle everything else.
919 The first is an interface config file.
920 The second is board-specific, and it sets up the JTAG TAPs and
921 their GDB targets (by deferring to some @file{target.cfg} file),
922 declares all flash memory, and leaves you nothing to do except
923 meet your deadline:
924
925 @example
926 source [find interface/olimex-jtag-tiny.cfg]
927 source [find board/csb337.cfg]
928 @end example
929
930 Boards with a single microcontroller often won't need more
931 than the target config file, as in the AT91SAM7X256 example.
932 That's because there is no external memory (flash, DDR RAM), and
933 the board differences are encapsulated by application code.
934
935 @item Maybe you don't know yet what your board looks like to JTAG.
936 Once you know the @file{interface.cfg} file to use, you may
937 need help from OpenOCD to discover what's on the board.
938 Once you find the JTAG TAPs, you can just search for appropriate
939 target and board
940 configuration files ... or write your own, from the bottom up.
941 @xref{autoprobing,,Autoprobing}.
942
943 @item You can often reuse some standard config files but
944 need to write a few new ones, probably a @file{board.cfg} file.
945 You will be using commands described later in this User's Guide,
946 and working with the guidelines in the next chapter.
947
948 For example, there may be configuration files for your JTAG adapter
949 and target chip, but you need a new board-specific config file
950 giving access to your particular flash chips.
951 Or you might need to write another target chip configuration file
952 for a new chip built around the Cortex M3 core.
953
954 @quotation Note
955 When you write new configuration files, please submit
956 them for inclusion in the next OpenOCD release.
957 For example, a @file{board/newboard.cfg} file will help the
958 next users of that board, and a @file{target/newcpu.cfg}
959 will help support users of any board using that chip.
960 @end quotation
961
962 @item
963 You may may need to write some C code.
964 It may be as simple as a supporting a new ft2232 or parport
965 based adapter; a bit more involved, like a NAND or NOR flash
966 controller driver; or a big piece of work like supporting
967 a new chip architecture.
968 @end itemize
969
970 Reuse the existing config files when you can.
971 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
972 You may find a board configuration that's a good example to follow.
973
974 When you write config files, separate the reusable parts
975 (things every user of that interface, chip, or board needs)
976 from ones specific to your environment and debugging approach.
977 @itemize
978
979 @item
980 For example, a @code{gdb-attach} event handler that invokes
981 the @command{reset init} command will interfere with debugging
982 early boot code, which performs some of the same actions
983 that the @code{reset-init} event handler does.
984
985 @item
986 Likewise, the @command{arm9 vector_catch} command (or
987 @cindex vector_catch
988 its siblings @command{xscale vector_catch}
989 and @command{cortex_m vector_catch}) can be a timesaver
990 during some debug sessions, but don't make everyone use that either.
991 Keep those kinds of debugging aids in your user config file,
992 along with messaging and tracing setup.
993 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
994
995 @item
996 You might need to override some defaults.
997 For example, you might need to move, shrink, or back up the target's
998 work area if your application needs much SRAM.
999
1000 @item
1001 TCP/IP port configuration is another example of something which
1002 is environment-specific, and should only appear in
1003 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1004 @end itemize
1005
1006 @section Project-Specific Utilities
1007
1008 A few project-specific utility
1009 routines may well speed up your work.
1010 Write them, and keep them in your project's user config file.
1011
1012 For example, if you are making a boot loader work on a
1013 board, it's nice to be able to debug the ``after it's
1014 loaded to RAM'' parts separately from the finicky early
1015 code which sets up the DDR RAM controller and clocks.
1016 A script like this one, or a more GDB-aware sibling,
1017 may help:
1018
1019 @example
1020 proc ramboot @{ @} @{
1021 # Reset, running the target's "reset-init" scripts
1022 # to initialize clocks and the DDR RAM controller.
1023 # Leave the CPU halted.
1024 reset init
1025
1026 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1027 load_image u-boot.bin 0x20000000
1028
1029 # Start running.
1030 resume 0x20000000
1031 @}
1032 @end example
1033
1034 Then once that code is working you will need to make it
1035 boot from NOR flash; a different utility would help.
1036 Alternatively, some developers write to flash using GDB.
1037 (You might use a similar script if you're working with a flash
1038 based microcontroller application instead of a boot loader.)
1039
1040 @example
1041 proc newboot @{ @} @{
1042 # Reset, leaving the CPU halted. The "reset-init" event
1043 # proc gives faster access to the CPU and to NOR flash;
1044 # "reset halt" would be slower.
1045 reset init
1046
1047 # Write standard version of U-Boot into the first two
1048 # sectors of NOR flash ... the standard version should
1049 # do the same lowlevel init as "reset-init".
1050 flash protect 0 0 1 off
1051 flash erase_sector 0 0 1
1052 flash write_bank 0 u-boot.bin 0x0
1053 flash protect 0 0 1 on
1054
1055 # Reboot from scratch using that new boot loader.
1056 reset run
1057 @}
1058 @end example
1059
1060 You may need more complicated utility procedures when booting
1061 from NAND.
1062 That often involves an extra bootloader stage,
1063 running from on-chip SRAM to perform DDR RAM setup so it can load
1064 the main bootloader code (which won't fit into that SRAM).
1065
1066 Other helper scripts might be used to write production system images,
1067 involving considerably more than just a three stage bootloader.
1068
1069 @section Target Software Changes
1070
1071 Sometimes you may want to make some small changes to the software
1072 you're developing, to help make JTAG debugging work better.
1073 For example, in C or assembly language code you might
1074 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1075 handling issues like:
1076
1077 @itemize @bullet
1078
1079 @item @b{Watchdog Timers}...
1080 Watchog timers are typically used to automatically reset systems if
1081 some application task doesn't periodically reset the timer. (The
1082 assumption is that the system has locked up if the task can't run.)
1083 When a JTAG debugger halts the system, that task won't be able to run
1084 and reset the timer ... potentially causing resets in the middle of
1085 your debug sessions.
1086
1087 It's rarely a good idea to disable such watchdogs, since their usage
1088 needs to be debugged just like all other parts of your firmware.
1089 That might however be your only option.
1090
1091 Look instead for chip-specific ways to stop the watchdog from counting
1092 while the system is in a debug halt state. It may be simplest to set
1093 that non-counting mode in your debugger startup scripts. You may however
1094 need a different approach when, for example, a motor could be physically
1095 damaged by firmware remaining inactive in a debug halt state. That might
1096 involve a type of firmware mode where that "non-counting" mode is disabled
1097 at the beginning then re-enabled at the end; a watchdog reset might fire
1098 and complicate the debug session, but hardware (or people) would be
1099 protected.@footnote{Note that many systems support a "monitor mode" debug
1100 that is a somewhat cleaner way to address such issues. You can think of
1101 it as only halting part of the system, maybe just one task,
1102 instead of the whole thing.
1103 At this writing, January 2010, OpenOCD based debugging does not support
1104 monitor mode debug, only "halt mode" debug.}
1105
1106 @item @b{ARM Semihosting}...
1107 @cindex ARM semihosting
1108 When linked with a special runtime library provided with many
1109 toolchains@footnote{See chapter 8 "Semihosting" in
1110 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1111 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1112 The CodeSourcery EABI toolchain also includes a semihosting library.},
1113 your target code can use I/O facilities on the debug host. That library
1114 provides a small set of system calls which are handled by OpenOCD.
1115 It can let the debugger provide your system console and a file system,
1116 helping with early debugging or providing a more capable environment
1117 for sometimes-complex tasks like installing system firmware onto
1118 NAND or SPI flash.
1119
1120 @item @b{ARM Wait-For-Interrupt}...
1121 Many ARM chips synchronize the JTAG clock using the core clock.
1122 Low power states which stop that core clock thus prevent JTAG access.
1123 Idle loops in tasking environments often enter those low power states
1124 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1125
1126 You may want to @emph{disable that instruction} in source code,
1127 or otherwise prevent using that state,
1128 to ensure you can get JTAG access at any time.@footnote{As a more
1129 polite alternative, some processors have special debug-oriented
1130 registers which can be used to change various features including
1131 how the low power states are clocked while debugging.
1132 The STM32 DBGMCU_CR register is an example; at the cost of extra
1133 power consumption, JTAG can be used during low power states.}
1134 For example, the OpenOCD @command{halt} command may not
1135 work for an idle processor otherwise.
1136
1137 @item @b{Delay after reset}...
1138 Not all chips have good support for debugger access
1139 right after reset; many LPC2xxx chips have issues here.
1140 Similarly, applications that reconfigure pins used for
1141 JTAG access as they start will also block debugger access.
1142
1143 To work with boards like this, @emph{enable a short delay loop}
1144 the first thing after reset, before "real" startup activities.
1145 For example, one second's delay is usually more than enough
1146 time for a JTAG debugger to attach, so that
1147 early code execution can be debugged
1148 or firmware can be replaced.
1149
1150 @item @b{Debug Communications Channel (DCC)}...
1151 Some processors include mechanisms to send messages over JTAG.
1152 Many ARM cores support these, as do some cores from other vendors.
1153 (OpenOCD may be able to use this DCC internally, speeding up some
1154 operations like writing to memory.)
1155
1156 Your application may want to deliver various debugging messages
1157 over JTAG, by @emph{linking with a small library of code}
1158 provided with OpenOCD and using the utilities there to send
1159 various kinds of message.
1160 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1161
1162 @end itemize
1163
1164 @section Target Hardware Setup
1165
1166 Chip vendors often provide software development boards which
1167 are highly configurable, so that they can support all options
1168 that product boards may require. @emph{Make sure that any
1169 jumpers or switches match the system configuration you are
1170 working with.}
1171
1172 Common issues include:
1173
1174 @itemize @bullet
1175
1176 @item @b{JTAG setup} ...
1177 Boards may support more than one JTAG configuration.
1178 Examples include jumpers controlling pullups versus pulldowns
1179 on the nTRST and/or nSRST signals, and choice of connectors
1180 (e.g. which of two headers on the base board,
1181 or one from a daughtercard).
1182 For some Texas Instruments boards, you may need to jumper the
1183 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1184
1185 @item @b{Boot Modes} ...
1186 Complex chips often support multiple boot modes, controlled
1187 by external jumpers. Make sure this is set up correctly.
1188 For example many i.MX boards from NXP need to be jumpered
1189 to "ATX mode" to start booting using the on-chip ROM, when
1190 using second stage bootloader code stored in a NAND flash chip.
1191
1192 Such explicit configuration is common, and not limited to
1193 booting from NAND. You might also need to set jumpers to
1194 start booting using code loaded from an MMC/SD card; external
1195 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1196 flash; some external host; or various other sources.
1197
1198
1199 @item @b{Memory Addressing} ...
1200 Boards which support multiple boot modes may also have jumpers
1201 to configure memory addressing. One board, for example, jumpers
1202 external chipselect 0 (used for booting) to address either
1203 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1204 or NAND flash. When it's jumpered to address NAND flash, that
1205 board must also be told to start booting from on-chip ROM.
1206
1207 Your @file{board.cfg} file may also need to be told this jumper
1208 configuration, so that it can know whether to declare NOR flash
1209 using @command{flash bank} or instead declare NAND flash with
1210 @command{nand device}; and likewise which probe to perform in
1211 its @code{reset-init} handler.
1212
1213 A closely related issue is bus width. Jumpers might need to
1214 distinguish between 8 bit or 16 bit bus access for the flash
1215 used to start booting.
1216
1217 @item @b{Peripheral Access} ...
1218 Development boards generally provide access to every peripheral
1219 on the chip, sometimes in multiple modes (such as by providing
1220 multiple audio codec chips).
1221 This interacts with software
1222 configuration of pin multiplexing, where for example a
1223 given pin may be routed either to the MMC/SD controller
1224 or the GPIO controller. It also often interacts with
1225 configuration jumpers. One jumper may be used to route
1226 signals to an MMC/SD card slot or an expansion bus (which
1227 might in turn affect booting); others might control which
1228 audio or video codecs are used.
1229
1230 @end itemize
1231
1232 Plus you should of course have @code{reset-init} event handlers
1233 which set up the hardware to match that jumper configuration.
1234 That includes in particular any oscillator or PLL used to clock
1235 the CPU, and any memory controllers needed to access external
1236 memory and peripherals. Without such handlers, you won't be
1237 able to access those resources without working target firmware
1238 which can do that setup ... this can be awkward when you're
1239 trying to debug that target firmware. Even if there's a ROM
1240 bootloader which handles a few issues, it rarely provides full
1241 access to all board-specific capabilities.
1242
1243
1244 @node Config File Guidelines
1245 @chapter Config File Guidelines
1246
1247 This chapter is aimed at any user who needs to write a config file,
1248 including developers and integrators of OpenOCD and any user who
1249 needs to get a new board working smoothly.
1250 It provides guidelines for creating those files.
1251
1252 You should find the following directories under @t{$(INSTALLDIR)/scripts},
1253 with files including the ones listed here.
1254 Use them as-is where you can; or as models for new files.
1255 @itemize @bullet
1256 @item @file{interface} ...
1257 These are for debug adapters.
1258 Files that configure JTAG adapters go here.
1259 @example
1260 $ ls interface -R
1261 interface/:
1262 altera-usb-blaster.cfg hilscher_nxhx50_re.cfg openocd-usb-hs.cfg
1263 arm-jtag-ew.cfg hitex_str9-comstick.cfg openrd.cfg
1264 at91rm9200.cfg icebear.cfg osbdm.cfg
1265 axm0432.cfg jlink.cfg parport.cfg
1266 busblaster.cfg jtagkey2.cfg parport_dlc5.cfg
1267 buspirate.cfg jtagkey2p.cfg redbee-econotag.cfg
1268 calao-usb-a9260-c01.cfg jtagkey.cfg redbee-usb.cfg
1269 calao-usb-a9260-c02.cfg jtagkey-tiny.cfg rlink.cfg
1270 calao-usb-a9260.cfg jtag-lock-pick_tiny_2.cfg sheevaplug.cfg
1271 chameleon.cfg kt-link.cfg signalyzer.cfg
1272 cortino.cfg lisa-l.cfg signalyzer-h2.cfg
1273 digilent-hs1.cfg luminary.cfg signalyzer-h4.cfg
1274 dlp-usb1232h.cfg luminary-icdi.cfg signalyzer-lite.cfg
1275 dummy.cfg luminary-lm3s811.cfg stlink-v1.cfg
1276 estick.cfg minimodule.cfg stlink-v2.cfg
1277 flashlink.cfg neodb.cfg stm32-stick.cfg
1278 flossjtag.cfg ngxtech.cfg sysfsgpio-raspberrypi.cfg
1279 flossjtag-noeeprom.cfg olimex-arm-usb-ocd.cfg ti-icdi.cfg
1280 flyswatter2.cfg olimex-arm-usb-ocd-h.cfg turtelizer2.cfg
1281 flyswatter.cfg olimex-arm-usb-tiny-h.cfg ulink.cfg
1282 ftdi olimex-jtag-tiny.cfg usb-jtag.cfg
1283 hilscher_nxhx10_etm.cfg oocdlink.cfg usbprog.cfg
1284 hilscher_nxhx500_etm.cfg opendous.cfg vpaclink.cfg
1285 hilscher_nxhx500_re.cfg opendous_ftdi.cfg vsllink.cfg
1286 hilscher_nxhx50_etm.cfg openocd-usb.cfg xds100v2.cfg
1287
1288 interface/ftdi:
1289 axm0432.cfg icebear.cfg oocdlink.cfg
1290 calao-usb-a9260-c01.cfg jtagkey2.cfg opendous_ftdi.cfg
1291 calao-usb-a9260-c02.cfg jtagkey2p.cfg openocd-usb.cfg
1292 cortino.cfg jtagkey.cfg openocd-usb-hs.cfg
1293 dlp-usb1232h.cfg jtag-lock-pick_tiny_2.cfg openrd.cfg
1294 dp_busblaster.cfg kt-link.cfg redbee-econotag.cfg
1295 flossjtag.cfg lisa-l.cfg redbee-usb.cfg
1296 flossjtag-noeeprom.cfg luminary.cfg sheevaplug.cfg
1297 flyswatter2.cfg luminary-icdi.cfg signalyzer.cfg
1298 flyswatter.cfg luminary-lm3s811.cfg signalyzer-lite.cfg
1299 hilscher_nxhx10_etm.cfg minimodule.cfg stm32-stick.cfg
1300 hilscher_nxhx500_etm.cfg neodb.cfg turtelizer2-revB.cfg
1301 hilscher_nxhx500_re.cfg ngxtech.cfg turtelizer2-revC.cfg
1302 hilscher_nxhx50_etm.cfg olimex-arm-usb-ocd.cfg vpaclink.cfg
1303 hilscher_nxhx50_re.cfg olimex-arm-usb-ocd-h.cfg xds100v2.cfg
1304 hitex_lpc1768stick.cfg olimex-arm-usb-tiny-h.cfg
1305 hitex_str9-comstick.cfg olimex-jtag-tiny.cfg
1306 $
1307 @end example
1308 @item @file{board} ...
1309 think Circuit Board, PWA, PCB, they go by many names. Board files
1310 contain initialization items that are specific to a board.
1311 They reuse target configuration files, since the same
1312 microprocessor chips are used on many boards,
1313 but support for external parts varies widely. For
1314 example, the SDRAM initialization sequence for the board, or the type
1315 of external flash and what address it uses. Any initialization
1316 sequence to enable that external flash or SDRAM should be found in the
1317 board file. Boards may also contain multiple targets: two CPUs; or
1318 a CPU and an FPGA.
1319 @example
1320 $ ls board
1321 actux3.cfg lpc1850_spifi_generic.cfg
1322 am3517evm.cfg lpc4350_spifi_generic.cfg
1323 arm_evaluator7t.cfg lubbock.cfg
1324 at91cap7a-stk-sdram.cfg mcb1700.cfg
1325 at91eb40a.cfg microchip_explorer16.cfg
1326 at91rm9200-dk.cfg mini2440.cfg
1327 at91rm9200-ek.cfg mini6410.cfg
1328 at91sam9261-ek.cfg netgear-dg834v3.cfg
1329 at91sam9263-ek.cfg olimex_LPC2378STK.cfg
1330 at91sam9g20-ek.cfg olimex_lpc_h2148.cfg
1331 atmel_at91sam7s-ek.cfg olimex_sam7_ex256.cfg
1332 atmel_at91sam9260-ek.cfg olimex_sam9_l9260.cfg
1333 atmel_at91sam9rl-ek.cfg olimex_stm32_h103.cfg
1334 atmel_sam3n_ek.cfg olimex_stm32_h107.cfg
1335 atmel_sam3s_ek.cfg olimex_stm32_p107.cfg
1336 atmel_sam3u_ek.cfg omap2420_h4.cfg
1337 atmel_sam3x_ek.cfg open-bldc.cfg
1338 atmel_sam4s_ek.cfg openrd.cfg
1339 balloon3-cpu.cfg osk5912.cfg
1340 colibri.cfg phone_se_j100i.cfg
1341 crossbow_tech_imote2.cfg phytec_lpc3250.cfg
1342 csb337.cfg pic-p32mx.cfg
1343 csb732.cfg propox_mmnet1001.cfg
1344 da850evm.cfg pxa255_sst.cfg
1345 digi_connectcore_wi-9c.cfg redbee.cfg
1346 diolan_lpc4350-db1.cfg rsc-w910.cfg
1347 dm355evm.cfg sheevaplug.cfg
1348 dm365evm.cfg smdk6410.cfg
1349 dm6446evm.cfg spear300evb.cfg
1350 efikamx.cfg spear300evb_mod.cfg
1351 eir.cfg spear310evb20.cfg
1352 ek-lm3s1968.cfg spear310evb20_mod.cfg
1353 ek-lm3s3748.cfg spear320cpu.cfg
1354 ek-lm3s6965.cfg spear320cpu_mod.cfg
1355 ek-lm3s811.cfg steval_pcc010.cfg
1356 ek-lm3s811-revb.cfg stm320518_eval_stlink.cfg
1357 ek-lm3s8962.cfg stm32100b_eval.cfg
1358 ek-lm3s9b9x.cfg stm3210b_eval.cfg
1359 ek-lm3s9d92.cfg stm3210c_eval.cfg
1360 ek-lm4f120xl.cfg stm3210e_eval.cfg
1361 ek-lm4f232.cfg stm3220g_eval.cfg
1362 embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
1363 ethernut3.cfg stm3241g_eval.cfg
1364 glyn_tonga2.cfg stm3241g_eval_stlink.cfg
1365 hammer.cfg stm32f0discovery.cfg
1366 hilscher_nxdb500sys.cfg stm32f3discovery.cfg
1367 hilscher_nxeb500hmi.cfg stm32f4discovery.cfg
1368 hilscher_nxhx10.cfg stm32ldiscovery.cfg
1369 hilscher_nxhx500.cfg stm32vldiscovery.cfg
1370 hilscher_nxhx50.cfg str910-eval.cfg
1371 hilscher_nxsb100.cfg telo.cfg
1372 hitex_lpc1768stick.cfg ti_am335xevm.cfg
1373 hitex_lpc2929.cfg ti_beagleboard.cfg
1374 hitex_stm32-performancestick.cfg ti_beagleboard_xm.cfg
1375 hitex_str9-comstick.cfg ti_beaglebone.cfg
1376 iar_lpc1768.cfg ti_blaze.cfg
1377 iar_str912_sk.cfg ti_pandaboard.cfg
1378 icnova_imx53_sodimm.cfg ti_pandaboard_es.cfg
1379 icnova_sam9g45_sodimm.cfg topas910.cfg
1380 imx27ads.cfg topasa900.cfg
1381 imx27lnst.cfg twr-k60f120m.cfg
1382 imx28evk.cfg twr-k60n512.cfg
1383 imx31pdk.cfg tx25_stk5.cfg
1384 imx35pdk.cfg tx27_stk5.cfg
1385 imx53loco.cfg unknown_at91sam9260.cfg
1386 keil_mcb1700.cfg uptech_2410.cfg
1387 keil_mcb2140.cfg verdex.cfg
1388 kwikstik.cfg voipac.cfg
1389 linksys_nslu2.cfg voltcraft_dso-3062c.cfg
1390 lisa-l.cfg x300t.cfg
1391 logicpd_imx27.cfg zy1000.cfg
1392 $
1393 @end example
1394 @item @file{target} ...
1395 think chip. The ``target'' directory represents the JTAG TAPs
1396 on a chip
1397 which OpenOCD should control, not a board. Two common types of targets
1398 are ARM chips and FPGA or CPLD chips.
1399 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1400 the target config file defines all of them.
1401 @example
1402 $ ls target
1403 aduc702x.cfg lpc1763.cfg
1404 am335x.cfg lpc1764.cfg
1405 amdm37x.cfg lpc1765.cfg
1406 ar71xx.cfg lpc1766.cfg
1407 at32ap7000.cfg lpc1767.cfg
1408 at91r40008.cfg lpc1768.cfg
1409 at91rm9200.cfg lpc1769.cfg
1410 at91sam3ax_4x.cfg lpc1788.cfg
1411 at91sam3ax_8x.cfg lpc17xx.cfg
1412 at91sam3ax_xx.cfg lpc1850.cfg
1413 at91sam3nXX.cfg lpc2103.cfg
1414 at91sam3sXX.cfg lpc2124.cfg
1415 at91sam3u1c.cfg lpc2129.cfg
1416 at91sam3u1e.cfg lpc2148.cfg
1417 at91sam3u2c.cfg lpc2294.cfg
1418 at91sam3u2e.cfg lpc2378.cfg
1419 at91sam3u4c.cfg lpc2460.cfg
1420 at91sam3u4e.cfg lpc2478.cfg
1421 at91sam3uxx.cfg lpc2900.cfg
1422 at91sam3XXX.cfg lpc2xxx.cfg
1423 at91sam4sd32x.cfg lpc3131.cfg
1424 at91sam4sXX.cfg lpc3250.cfg
1425 at91sam4XXX.cfg lpc4350.cfg
1426 at91sam7se512.cfg lpc4350.cfg.orig
1427 at91sam7sx.cfg mc13224v.cfg
1428 at91sam7x256.cfg nuc910.cfg
1429 at91sam7x512.cfg omap2420.cfg
1430 at91sam9260.cfg omap3530.cfg
1431 at91sam9260_ext_RAM_ext_flash.cfg omap4430.cfg
1432 at91sam9261.cfg omap4460.cfg
1433 at91sam9263.cfg omap5912.cfg
1434 at91sam9.cfg omapl138.cfg
1435 at91sam9g10.cfg pic32mx.cfg
1436 at91sam9g20.cfg pxa255.cfg
1437 at91sam9g45.cfg pxa270.cfg
1438 at91sam9rl.cfg pxa3xx.cfg
1439 atmega128.cfg readme.txt
1440 avr32.cfg samsung_s3c2410.cfg
1441 c100.cfg samsung_s3c2440.cfg
1442 c100config.tcl samsung_s3c2450.cfg
1443 c100helper.tcl samsung_s3c4510.cfg
1444 c100regs.tcl samsung_s3c6410.cfg
1445 cs351x.cfg sharp_lh79532.cfg
1446 davinci.cfg smp8634.cfg
1447 dragonite.cfg spear3xx.cfg
1448 dsp56321.cfg stellaris.cfg
1449 dsp568013.cfg stellaris_icdi.cfg
1450 dsp568037.cfg stm32f0x_stlink.cfg
1451 efm32_stlink.cfg stm32f1x.cfg
1452 epc9301.cfg stm32f1x_stlink.cfg
1453 faux.cfg stm32f2x.cfg
1454 feroceon.cfg stm32f2x_stlink.cfg
1455 fm3.cfg stm32f3x.cfg
1456 hilscher_netx10.cfg stm32f3x_stlink.cfg
1457 hilscher_netx500.cfg stm32f4x.cfg
1458 hilscher_netx50.cfg stm32f4x_stlink.cfg
1459 icepick.cfg stm32l.cfg
1460 imx21.cfg stm32lx_dual_bank.cfg
1461 imx25.cfg stm32lx_stlink.cfg
1462 imx27.cfg stm32_stlink.cfg
1463 imx28.cfg stm32w108_stlink.cfg
1464 imx31.cfg stm32xl.cfg
1465 imx35.cfg str710.cfg
1466 imx51.cfg str730.cfg
1467 imx53.cfg str750.cfg
1468 imx6.cfg str912.cfg
1469 imx.cfg swj-dp.tcl
1470 is5114.cfg test_reset_syntax_error.cfg
1471 ixp42x.cfg test_syntax_error.cfg
1472 k40.cfg ti-ar7.cfg
1473 k60.cfg ti_calypso.cfg
1474 lpc1751.cfg ti_dm355.cfg
1475 lpc1752.cfg ti_dm365.cfg
1476 lpc1754.cfg ti_dm6446.cfg
1477 lpc1756.cfg tmpa900.cfg
1478 lpc1758.cfg tmpa910.cfg
1479 lpc1759.cfg u8500.cfg
1480 @end example
1481 @item @emph{more} ... browse for other library files which may be useful.
1482 For example, there are various generic and CPU-specific utilities.
1483 @end itemize
1484
1485 The @file{openocd.cfg} user config
1486 file may override features in any of the above files by
1487 setting variables before sourcing the target file, or by adding
1488 commands specific to their situation.
1489
1490 @section Interface Config Files
1491
1492 The user config file
1493 should be able to source one of these files with a command like this:
1494
1495 @example
1496 source [find interface/FOOBAR.cfg]
1497 @end example
1498
1499 A preconfigured interface file should exist for every debug adapter
1500 in use today with OpenOCD.
1501 That said, perhaps some of these config files
1502 have only been used by the developer who created it.
1503
1504 A separate chapter gives information about how to set these up.
1505 @xref{Debug Adapter Configuration}.
1506 Read the OpenOCD source code (and Developer's Guide)
1507 if you have a new kind of hardware interface
1508 and need to provide a driver for it.
1509
1510 @section Board Config Files
1511 @cindex config file, board
1512 @cindex board config file
1513
1514 The user config file
1515 should be able to source one of these files with a command like this:
1516
1517 @example
1518 source [find board/FOOBAR.cfg]
1519 @end example
1520
1521 The point of a board config file is to package everything
1522 about a given board that user config files need to know.
1523 In summary the board files should contain (if present)
1524
1525 @enumerate
1526 @item One or more @command{source [target/...cfg]} statements
1527 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1528 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1529 @item Target @code{reset} handlers for SDRAM and I/O configuration
1530 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1531 @item All things that are not ``inside a chip''
1532 @end enumerate
1533
1534 Generic things inside target chips belong in target config files,
1535 not board config files. So for example a @code{reset-init} event
1536 handler should know board-specific oscillator and PLL parameters,
1537 which it passes to target-specific utility code.
1538
1539 The most complex task of a board config file is creating such a
1540 @code{reset-init} event handler.
1541 Define those handlers last, after you verify the rest of the board
1542 configuration works.
1543
1544 @subsection Communication Between Config files
1545
1546 In addition to target-specific utility code, another way that
1547 board and target config files communicate is by following a
1548 convention on how to use certain variables.
1549
1550 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1551 Thus the rule we follow in OpenOCD is this: Variables that begin with
1552 a leading underscore are temporary in nature, and can be modified and
1553 used at will within a target configuration file.
1554
1555 Complex board config files can do the things like this,
1556 for a board with three chips:
1557
1558 @example
1559 # Chip #1: PXA270 for network side, big endian
1560 set CHIPNAME network
1561 set ENDIAN big
1562 source [find target/pxa270.cfg]
1563 # on return: _TARGETNAME = network.cpu
1564 # other commands can refer to the "network.cpu" target.
1565 $_TARGETNAME configure .... events for this CPU..
1566
1567 # Chip #2: PXA270 for video side, little endian
1568 set CHIPNAME video
1569 set ENDIAN little
1570 source [find target/pxa270.cfg]
1571 # on return: _TARGETNAME = video.cpu
1572 # other commands can refer to the "video.cpu" target.
1573 $_TARGETNAME configure .... events for this CPU..
1574
1575 # Chip #3: Xilinx FPGA for glue logic
1576 set CHIPNAME xilinx
1577 unset ENDIAN
1578 source [find target/spartan3.cfg]
1579 @end example
1580
1581 That example is oversimplified because it doesn't show any flash memory,
1582 or the @code{reset-init} event handlers to initialize external DRAM
1583 or (assuming it needs it) load a configuration into the FPGA.
1584 Such features are usually needed for low-level work with many boards,
1585 where ``low level'' implies that the board initialization software may
1586 not be working. (That's a common reason to need JTAG tools. Another
1587 is to enable working with microcontroller-based systems, which often
1588 have no debugging support except a JTAG connector.)
1589
1590 Target config files may also export utility functions to board and user
1591 config files. Such functions should use name prefixes, to help avoid
1592 naming collisions.
1593
1594 Board files could also accept input variables from user config files.
1595 For example, there might be a @code{J4_JUMPER} setting used to identify
1596 what kind of flash memory a development board is using, or how to set
1597 up other clocks and peripherals.
1598
1599 @subsection Variable Naming Convention
1600 @cindex variable names
1601
1602 Most boards have only one instance of a chip.
1603 However, it should be easy to create a board with more than
1604 one such chip (as shown above).
1605 Accordingly, we encourage these conventions for naming
1606 variables associated with different @file{target.cfg} files,
1607 to promote consistency and
1608 so that board files can override target defaults.
1609
1610 Inputs to target config files include:
1611
1612 @itemize @bullet
1613 @item @code{CHIPNAME} ...
1614 This gives a name to the overall chip, and is used as part of
1615 tap identifier dotted names.
1616 While the default is normally provided by the chip manufacturer,
1617 board files may need to distinguish between instances of a chip.
1618 @item @code{ENDIAN} ...
1619 By default @option{little} - although chips may hard-wire @option{big}.
1620 Chips that can't change endianness don't need to use this variable.
1621 @item @code{CPUTAPID} ...
1622 When OpenOCD examines the JTAG chain, it can be told verify the
1623 chips against the JTAG IDCODE register.
1624 The target file will hold one or more defaults, but sometimes the
1625 chip in a board will use a different ID (perhaps a newer revision).
1626 @end itemize
1627
1628 Outputs from target config files include:
1629
1630 @itemize @bullet
1631 @item @code{_TARGETNAME} ...
1632 By convention, this variable is created by the target configuration
1633 script. The board configuration file may make use of this variable to
1634 configure things like a ``reset init'' script, or other things
1635 specific to that board and that target.
1636 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1637 @code{_TARGETNAME1}, ... etc.
1638 @end itemize
1639
1640 @subsection The reset-init Event Handler
1641 @cindex event, reset-init
1642 @cindex reset-init handler
1643
1644 Board config files run in the OpenOCD configuration stage;
1645 they can't use TAPs or targets, since they haven't been
1646 fully set up yet.
1647 This means you can't write memory or access chip registers;
1648 you can't even verify that a flash chip is present.
1649 That's done later in event handlers, of which the target @code{reset-init}
1650 handler is one of the most important.
1651
1652 Except on microcontrollers, the basic job of @code{reset-init} event
1653 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1654 Microcontrollers rarely use boot loaders; they run right out of their
1655 on-chip flash and SRAM memory. But they may want to use one of these
1656 handlers too, if just for developer convenience.
1657
1658 @quotation Note
1659 Because this is so very board-specific, and chip-specific, no examples
1660 are included here.
1661 Instead, look at the board config files distributed with OpenOCD.
1662 If you have a boot loader, its source code will help; so will
1663 configuration files for other JTAG tools
1664 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1665 @end quotation
1666
1667 Some of this code could probably be shared between different boards.
1668 For example, setting up a DRAM controller often doesn't differ by
1669 much except the bus width (16 bits or 32?) and memory timings, so a
1670 reusable TCL procedure loaded by the @file{target.cfg} file might take
1671 those as parameters.
1672 Similarly with oscillator, PLL, and clock setup;
1673 and disabling the watchdog.
1674 Structure the code cleanly, and provide comments to help
1675 the next developer doing such work.
1676 (@emph{You might be that next person} trying to reuse init code!)
1677
1678 The last thing normally done in a @code{reset-init} handler is probing
1679 whatever flash memory was configured. For most chips that needs to be
1680 done while the associated target is halted, either because JTAG memory
1681 access uses the CPU or to prevent conflicting CPU access.
1682
1683 @subsection JTAG Clock Rate
1684
1685 Before your @code{reset-init} handler has set up
1686 the PLLs and clocking, you may need to run with
1687 a low JTAG clock rate.
1688 @xref{jtagspeed,,JTAG Speed}.
1689 Then you'd increase that rate after your handler has
1690 made it possible to use the faster JTAG clock.
1691 When the initial low speed is board-specific, for example
1692 because it depends on a board-specific oscillator speed, then
1693 you should probably set it up in the board config file;
1694 if it's target-specific, it belongs in the target config file.
1695
1696 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1697 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1698 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1699 Consult chip documentation to determine the peak JTAG clock rate,
1700 which might be less than that.
1701
1702 @quotation Warning
1703 On most ARMs, JTAG clock detection is coupled to the core clock, so
1704 software using a @option{wait for interrupt} operation blocks JTAG access.
1705 Adaptive clocking provides a partial workaround, but a more complete
1706 solution just avoids using that instruction with JTAG debuggers.
1707 @end quotation
1708
1709 If both the chip and the board support adaptive clocking,
1710 use the @command{jtag_rclk}
1711 command, in case your board is used with JTAG adapter which
1712 also supports it. Otherwise use @command{adapter_khz}.
1713 Set the slow rate at the beginning of the reset sequence,
1714 and the faster rate as soon as the clocks are at full speed.
1715
1716 @anchor{theinitboardprocedure}
1717 @subsection The init_board procedure
1718 @cindex init_board procedure
1719
1720 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1721 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1722 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1723 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1724 spearate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1725 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1726 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1727 Additionally ``linear'' board config file will most likely fail when target config file uses
1728 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1729 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1730 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1731 need to override @code{init_targets} defined in target config files when they only need to to add some specifics.
1732
1733 Just as @code{init_targets}, the @code{init_board} procedure can be overriden by ``next level'' script (which sources
1734 the original), allowing greater code reuse.
1735
1736 @example
1737 ### board_file.cfg ###
1738
1739 # source target file that does most of the config in init_targets
1740 source [find target/target.cfg]
1741
1742 proc enable_fast_clock @{@} @{
1743 # enables fast on-board clock source
1744 # configures the chip to use it
1745 @}
1746
1747 # initialize only board specifics - reset, clock, adapter frequency
1748 proc init_board @{@} @{
1749 reset_config trst_and_srst trst_pulls_srst
1750
1751 $_TARGETNAME configure -event reset-init @{
1752 adapter_khz 1
1753 enable_fast_clock
1754 adapter_khz 10000
1755 @}
1756 @}
1757 @end example
1758
1759 @section Target Config Files
1760 @cindex config file, target
1761 @cindex target config file
1762
1763 Board config files communicate with target config files using
1764 naming conventions as described above, and may source one or
1765 more target config files like this:
1766
1767 @example
1768 source [find target/FOOBAR.cfg]
1769 @end example
1770
1771 The point of a target config file is to package everything
1772 about a given chip that board config files need to know.
1773 In summary the target files should contain
1774
1775 @enumerate
1776 @item Set defaults
1777 @item Add TAPs to the scan chain
1778 @item Add CPU targets (includes GDB support)
1779 @item CPU/Chip/CPU-Core specific features
1780 @item On-Chip flash
1781 @end enumerate
1782
1783 As a rule of thumb, a target file sets up only one chip.
1784 For a microcontroller, that will often include a single TAP,
1785 which is a CPU needing a GDB target, and its on-chip flash.
1786
1787 More complex chips may include multiple TAPs, and the target
1788 config file may need to define them all before OpenOCD
1789 can talk to the chip.
1790 For example, some phone chips have JTAG scan chains that include
1791 an ARM core for operating system use, a DSP,
1792 another ARM core embedded in an image processing engine,
1793 and other processing engines.
1794
1795 @subsection Default Value Boiler Plate Code
1796
1797 All target configuration files should start with code like this,
1798 letting board config files express environment-specific
1799 differences in how things should be set up.
1800
1801 @example
1802 # Boards may override chip names, perhaps based on role,
1803 # but the default should match what the vendor uses
1804 if @{ [info exists CHIPNAME] @} @{
1805 set _CHIPNAME $CHIPNAME
1806 @} else @{
1807 set _CHIPNAME sam7x256
1808 @}
1809
1810 # ONLY use ENDIAN with targets that can change it.
1811 if @{ [info exists ENDIAN] @} @{
1812 set _ENDIAN $ENDIAN
1813 @} else @{
1814 set _ENDIAN little
1815 @}
1816
1817 # TAP identifiers may change as chips mature, for example with
1818 # new revision fields (the "3" here). Pick a good default; you
1819 # can pass several such identifiers to the "jtag newtap" command.
1820 if @{ [info exists CPUTAPID ] @} @{
1821 set _CPUTAPID $CPUTAPID
1822 @} else @{
1823 set _CPUTAPID 0x3f0f0f0f
1824 @}
1825 @end example
1826 @c but 0x3f0f0f0f is for an str73x part ...
1827
1828 @emph{Remember:} Board config files may include multiple target
1829 config files, or the same target file multiple times
1830 (changing at least @code{CHIPNAME}).
1831
1832 Likewise, the target configuration file should define
1833 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1834 use it later on when defining debug targets:
1835
1836 @example
1837 set _TARGETNAME $_CHIPNAME.cpu
1838 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1839 @end example
1840
1841 @subsection Adding TAPs to the Scan Chain
1842 After the ``defaults'' are set up,
1843 add the TAPs on each chip to the JTAG scan chain.
1844 @xref{TAP Declaration}, and the naming convention
1845 for taps.
1846
1847 In the simplest case the chip has only one TAP,
1848 probably for a CPU or FPGA.
1849 The config file for the Atmel AT91SAM7X256
1850 looks (in part) like this:
1851
1852 @example
1853 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1854 @end example
1855
1856 A board with two such at91sam7 chips would be able
1857 to source such a config file twice, with different
1858 values for @code{CHIPNAME}, so
1859 it adds a different TAP each time.
1860
1861 If there are nonzero @option{-expected-id} values,
1862 OpenOCD attempts to verify the actual tap id against those values.
1863 It will issue error messages if there is mismatch, which
1864 can help to pinpoint problems in OpenOCD configurations.
1865
1866 @example
1867 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1868 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1869 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1870 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1871 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1872 @end example
1873
1874 There are more complex examples too, with chips that have
1875 multiple TAPs. Ones worth looking at include:
1876
1877 @itemize
1878 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1879 plus a JRC to enable them
1880 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1881 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1882 is not currently used)
1883 @end itemize
1884
1885 @subsection Add CPU targets
1886
1887 After adding a TAP for a CPU, you should set it up so that
1888 GDB and other commands can use it.
1889 @xref{CPU Configuration}.
1890 For the at91sam7 example above, the command can look like this;
1891 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1892 to little endian, and this chip doesn't support changing that.
1893
1894 @example
1895 set _TARGETNAME $_CHIPNAME.cpu
1896 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1897 @end example
1898
1899 Work areas are small RAM areas associated with CPU targets.
1900 They are used by OpenOCD to speed up downloads,
1901 and to download small snippets of code to program flash chips.
1902 If the chip includes a form of ``on-chip-ram'' - and many do - define
1903 a work area if you can.
1904 Again using the at91sam7 as an example, this can look like:
1905
1906 @example
1907 $_TARGETNAME configure -work-area-phys 0x00200000 \
1908 -work-area-size 0x4000 -work-area-backup 0
1909 @end example
1910
1911 @anchor{definecputargetsworkinginsmp}
1912 @subsection Define CPU targets working in SMP
1913 @cindex SMP
1914 After setting targets, you can define a list of targets working in SMP.
1915
1916 @example
1917 set _TARGETNAME_1 $_CHIPNAME.cpu1
1918 set _TARGETNAME_2 $_CHIPNAME.cpu2
1919 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1920 -coreid 0 -dbgbase $_DAP_DBG1
1921 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1922 -coreid 1 -dbgbase $_DAP_DBG2
1923 #define 2 targets working in smp.
1924 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1925 @end example
1926 In the above example on cortex_a, 2 cpus are working in SMP.
1927 In SMP only one GDB instance is created and :
1928 @itemize @bullet
1929 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1930 @item halt command triggers the halt of all targets in the list.
1931 @item resume command triggers the write context and the restart of all targets in the list.
1932 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1933 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1934 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1935 @end itemize
1936
1937 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1938 command have been implemented.
1939 @itemize @bullet
1940 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1941 @item cortex_a smp_off : disable SMP mode, the current target is the one
1942 displayed in the GDB session, only this target is now controlled by GDB
1943 session. This behaviour is useful during system boot up.
1944 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1945 following example.
1946 @end itemize
1947
1948 @example
1949 >cortex_a smp_gdb
1950 gdb coreid 0 -> -1
1951 #0 : coreid 0 is displayed to GDB ,
1952 #-> -1 : next resume triggers a real resume
1953 > cortex_a smp_gdb 1
1954 gdb coreid 0 -> 1
1955 #0 :coreid 0 is displayed to GDB ,
1956 #->1 : next resume displays coreid 1 to GDB
1957 > resume
1958 > cortex_a smp_gdb
1959 gdb coreid 1 -> 1
1960 #1 :coreid 1 is displayed to GDB ,
1961 #->1 : next resume displays coreid 1 to GDB
1962 > cortex_a smp_gdb -1
1963 gdb coreid 1 -> -1
1964 #1 :coreid 1 is displayed to GDB,
1965 #->-1 : next resume triggers a real resume
1966 @end example
1967
1968
1969 @subsection Chip Reset Setup
1970
1971 As a rule, you should put the @command{reset_config} command
1972 into the board file. Most things you think you know about a
1973 chip can be tweaked by the board.
1974
1975 Some chips have specific ways the TRST and SRST signals are
1976 managed. In the unusual case that these are @emph{chip specific}
1977 and can never be changed by board wiring, they could go here.
1978 For example, some chips can't support JTAG debugging without
1979 both signals.
1980
1981 Provide a @code{reset-assert} event handler if you can.
1982 Such a handler uses JTAG operations to reset the target,
1983 letting this target config be used in systems which don't
1984 provide the optional SRST signal, or on systems where you
1985 don't want to reset all targets at once.
1986 Such a handler might write to chip registers to force a reset,
1987 use a JRC to do that (preferable -- the target may be wedged!),
1988 or force a watchdog timer to trigger.
1989 (For Cortex-M targets, this is not necessary. The target
1990 driver knows how to use trigger an NVIC reset when SRST is
1991 not available.)
1992
1993 Some chips need special attention during reset handling if
1994 they're going to be used with JTAG.
1995 An example might be needing to send some commands right
1996 after the target's TAP has been reset, providing a
1997 @code{reset-deassert-post} event handler that writes a chip
1998 register to report that JTAG debugging is being done.
1999 Another would be reconfiguring the watchdog so that it stops
2000 counting while the core is halted in the debugger.
2001
2002 JTAG clocking constraints often change during reset, and in
2003 some cases target config files (rather than board config files)
2004 are the right places to handle some of those issues.
2005 For example, immediately after reset most chips run using a
2006 slower clock than they will use later.
2007 That means that after reset (and potentially, as OpenOCD
2008 first starts up) they must use a slower JTAG clock rate
2009 than they will use later.
2010 @xref{jtagspeed,,JTAG Speed}.
2011
2012 @quotation Important
2013 When you are debugging code that runs right after chip
2014 reset, getting these issues right is critical.
2015 In particular, if you see intermittent failures when
2016 OpenOCD verifies the scan chain after reset,
2017 look at how you are setting up JTAG clocking.
2018 @end quotation
2019
2020 @anchor{theinittargetsprocedure}
2021 @subsection The init_targets procedure
2022 @cindex init_targets procedure
2023
2024 Target config files can either be ``linear'' (script executed line-by-line when parsed in
2025 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
2026 procedure called @code{init_targets}, which will be executed when entering run stage
2027 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
2028 Such procedure can be overriden by ``next level'' script (which sources the original).
2029 This concept faciliates code reuse when basic target config files provide generic configuration
2030 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
2031 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
2032 because sourcing them executes every initialization commands they provide.
2033
2034 @example
2035 ### generic_file.cfg ###
2036
2037 proc setup_my_chip @{chip_name flash_size ram_size@} @{
2038 # basic initialization procedure ...
2039 @}
2040
2041 proc init_targets @{@} @{
2042 # initializes generic chip with 4kB of flash and 1kB of RAM
2043 setup_my_chip MY_GENERIC_CHIP 4096 1024
2044 @}
2045
2046 ### specific_file.cfg ###
2047
2048 source [find target/generic_file.cfg]
2049
2050 proc init_targets @{@} @{
2051 # initializes specific chip with 128kB of flash and 64kB of RAM
2052 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
2053 @}
2054 @end example
2055
2056 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
2057 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
2058
2059 For an example of this scheme see LPC2000 target config files.
2060
2061 The @code{init_boards} procedure is a similar concept concerning board config files
2062 (@xref{theinitboardprocedure,,The init_board procedure}.)
2063
2064 @subsection ARM Core Specific Hacks
2065
2066 If the chip has a DCC, enable it. If the chip is an ARM9 with some
2067 special high speed download features - enable it.
2068
2069 If present, the MMU, the MPU and the CACHE should be disabled.
2070
2071 Some ARM cores are equipped with trace support, which permits
2072 examination of the instruction and data bus activity. Trace
2073 activity is controlled through an ``Embedded Trace Module'' (ETM)
2074 on one of the core's scan chains. The ETM emits voluminous data
2075 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
2076 If you are using an external trace port,
2077 configure it in your board config file.
2078 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
2079 configure it in your target config file.
2080
2081 @example
2082 etm config $_TARGETNAME 16 normal full etb
2083 etb config $_TARGETNAME $_CHIPNAME.etb
2084 @end example
2085
2086 @subsection Internal Flash Configuration
2087
2088 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
2089
2090 @b{Never ever} in the ``target configuration file'' define any type of
2091 flash that is external to the chip. (For example a BOOT flash on
2092 Chip Select 0.) Such flash information goes in a board file - not
2093 the TARGET (chip) file.
2094
2095 Examples:
2096 @itemize @bullet
2097 @item at91sam7x256 - has 256K flash YES enable it.
2098 @item str912 - has flash internal YES enable it.
2099 @item imx27 - uses boot flash on CS0 - it goes in the board file.
2100 @item pxa270 - again - CS0 flash - it goes in the board file.
2101 @end itemize
2102
2103 @anchor{translatingconfigurationfiles}
2104 @section Translating Configuration Files
2105 @cindex translation
2106 If you have a configuration file for another hardware debugger
2107 or toolset (Abatron, BDI2000, BDI3000, CCS,
2108 Lauterbach, Segger, Macraigor, etc.), translating
2109 it into OpenOCD syntax is often quite straightforward. The most tricky
2110 part of creating a configuration script is oftentimes the reset init
2111 sequence where e.g. PLLs, DRAM and the like is set up.
2112
2113 One trick that you can use when translating is to write small
2114 Tcl procedures to translate the syntax into OpenOCD syntax. This
2115 can avoid manual translation errors and make it easier to
2116 convert other scripts later on.
2117
2118 Example of transforming quirky arguments to a simple search and
2119 replace job:
2120
2121 @example
2122 # Lauterbach syntax(?)
2123 #
2124 # Data.Set c15:0x042f %long 0x40000015
2125 #
2126 # OpenOCD syntax when using procedure below.
2127 #
2128 # setc15 0x01 0x00050078
2129
2130 proc setc15 @{regs value@} @{
2131 global TARGETNAME
2132
2133 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2134
2135 arm mcr 15 [expr ($regs>>12)&0x7] \
2136 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2137 [expr ($regs>>8)&0x7] $value
2138 @}
2139 @end example
2140
2141
2142
2143 @node Daemon Configuration
2144 @chapter Daemon Configuration
2145 @cindex initialization
2146 The commands here are commonly found in the openocd.cfg file and are
2147 used to specify what TCP/IP ports are used, and how GDB should be
2148 supported.
2149
2150 @anchor{configurationstage}
2151 @section Configuration Stage
2152 @cindex configuration stage
2153 @cindex config command
2154
2155 When the OpenOCD server process starts up, it enters a
2156 @emph{configuration stage} which is the only time that
2157 certain commands, @emph{configuration commands}, may be issued.
2158 Normally, configuration commands are only available
2159 inside startup scripts.
2160
2161 In this manual, the definition of a configuration command is
2162 presented as a @emph{Config Command}, not as a @emph{Command}
2163 which may be issued interactively.
2164 The runtime @command{help} command also highlights configuration
2165 commands, and those which may be issued at any time.
2166
2167 Those configuration commands include declaration of TAPs,
2168 flash banks,
2169 the interface used for JTAG communication,
2170 and other basic setup.
2171 The server must leave the configuration stage before it
2172 may access or activate TAPs.
2173 After it leaves this stage, configuration commands may no
2174 longer be issued.
2175
2176 @anchor{enteringtherunstage}
2177 @section Entering the Run Stage
2178
2179 The first thing OpenOCD does after leaving the configuration
2180 stage is to verify that it can talk to the scan chain
2181 (list of TAPs) which has been configured.
2182 It will warn if it doesn't find TAPs it expects to find,
2183 or finds TAPs that aren't supposed to be there.
2184 You should see no errors at this point.
2185 If you see errors, resolve them by correcting the
2186 commands you used to configure the server.
2187 Common errors include using an initial JTAG speed that's too
2188 fast, and not providing the right IDCODE values for the TAPs
2189 on the scan chain.
2190
2191 Once OpenOCD has entered the run stage, a number of commands
2192 become available.
2193 A number of these relate to the debug targets you may have declared.
2194 For example, the @command{mww} command will not be available until
2195 a target has been successfuly instantiated.
2196 If you want to use those commands, you may need to force
2197 entry to the run stage.
2198
2199 @deffn {Config Command} init
2200 This command terminates the configuration stage and
2201 enters the run stage. This helps when you need to have
2202 the startup scripts manage tasks such as resetting the target,
2203 programming flash, etc. To reset the CPU upon startup, add "init" and
2204 "reset" at the end of the config script or at the end of the OpenOCD
2205 command line using the @option{-c} command line switch.
2206
2207 If this command does not appear in any startup/configuration file
2208 OpenOCD executes the command for you after processing all
2209 configuration files and/or command line options.
2210
2211 @b{NOTE:} This command normally occurs at or near the end of your
2212 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2213 targets ready. For example: If your openocd.cfg file needs to
2214 read/write memory on your target, @command{init} must occur before
2215 the memory read/write commands. This includes @command{nand probe}.
2216 @end deffn
2217
2218 @deffn {Overridable Procedure} jtag_init
2219 This is invoked at server startup to verify that it can talk
2220 to the scan chain (list of TAPs) which has been configured.
2221
2222 The default implementation first tries @command{jtag arp_init},
2223 which uses only a lightweight JTAG reset before examining the
2224 scan chain.
2225 If that fails, it tries again, using a harder reset
2226 from the overridable procedure @command{init_reset}.
2227
2228 Implementations must have verified the JTAG scan chain before
2229 they return.
2230 This is done by calling @command{jtag arp_init}
2231 (or @command{jtag arp_init-reset}).
2232 @end deffn
2233
2234 @anchor{tcpipports}
2235 @section TCP/IP Ports
2236 @cindex TCP port
2237 @cindex server
2238 @cindex port
2239 @cindex security
2240 The OpenOCD server accepts remote commands in several syntaxes.
2241 Each syntax uses a different TCP/IP port, which you may specify
2242 only during configuration (before those ports are opened).
2243
2244 For reasons including security, you may wish to prevent remote
2245 access using one or more of these ports.
2246 In such cases, just specify the relevant port number as zero.
2247 If you disable all access through TCP/IP, you will need to
2248 use the command line @option{-pipe} option.
2249
2250 @deffn {Command} gdb_port [number]
2251 @cindex GDB server
2252 Normally gdb listens to a TCP/IP port, but GDB can also
2253 communicate via pipes(stdin/out or named pipes). The name
2254 "gdb_port" stuck because it covers probably more than 90% of
2255 the normal use cases.
2256
2257 No arguments reports GDB port. "pipe" means listen to stdin
2258 output to stdout, an integer is base port number, "disable"
2259 disables the gdb server.
2260
2261 When using "pipe", also use log_output to redirect the log
2262 output to a file so as not to flood the stdin/out pipes.
2263
2264 The -p/--pipe option is deprecated and a warning is printed
2265 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2266
2267 Any other string is interpreted as named pipe to listen to.
2268 Output pipe is the same name as input pipe, but with 'o' appended,
2269 e.g. /var/gdb, /var/gdbo.
2270
2271 The GDB port for the first target will be the base port, the
2272 second target will listen on gdb_port + 1, and so on.
2273 When not specified during the configuration stage,
2274 the port @var{number} defaults to 3333.
2275 @end deffn
2276
2277 @deffn {Command} tcl_port [number]
2278 Specify or query the port used for a simplified RPC
2279 connection that can be used by clients to issue TCL commands and get the
2280 output from the Tcl engine.
2281 Intended as a machine interface.
2282 When not specified during the configuration stage,
2283 the port @var{number} defaults to 6666.
2284
2285 @end deffn
2286
2287 @deffn {Command} telnet_port [number]
2288 Specify or query the
2289 port on which to listen for incoming telnet connections.
2290 This port is intended for interaction with one human through TCL commands.
2291 When not specified during the configuration stage,
2292 the port @var{number} defaults to 4444.
2293 When specified as zero, this port is not activated.
2294 @end deffn
2295
2296 @anchor{gdbconfiguration}
2297 @section GDB Configuration
2298 @cindex GDB
2299 @cindex GDB configuration
2300 You can reconfigure some GDB behaviors if needed.
2301 The ones listed here are static and global.
2302 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2303 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2304
2305 @anchor{gdbbreakpointoverride}
2306 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2307 Force breakpoint type for gdb @command{break} commands.
2308 This option supports GDB GUIs which don't
2309 distinguish hard versus soft breakpoints, if the default OpenOCD and
2310 GDB behaviour is not sufficient. GDB normally uses hardware
2311 breakpoints if the memory map has been set up for flash regions.
2312 @end deffn
2313
2314 @anchor{gdbflashprogram}
2315 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2316 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2317 vFlash packet is received.
2318 The default behaviour is @option{enable}.
2319 @end deffn
2320
2321 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2322 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2323 requested. GDB will then know when to set hardware breakpoints, and program flash
2324 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2325 for flash programming to work.
2326 Default behaviour is @option{enable}.
2327 @xref{gdbflashprogram,,gdb_flash_program}.
2328 @end deffn
2329
2330 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2331 Specifies whether data aborts cause an error to be reported
2332 by GDB memory read packets.
2333 The default behaviour is @option{disable};
2334 use @option{enable} see these errors reported.
2335 @end deffn
2336
2337 @anchor{eventpolling}
2338 @section Event Polling
2339
2340 Hardware debuggers are parts of asynchronous systems,
2341 where significant events can happen at any time.
2342 The OpenOCD server needs to detect some of these events,
2343 so it can report them to through TCL command line
2344 or to GDB.
2345
2346 Examples of such events include:
2347
2348 @itemize
2349 @item One of the targets can stop running ... maybe it triggers
2350 a code breakpoint or data watchpoint, or halts itself.
2351 @item Messages may be sent over ``debug message'' channels ... many
2352 targets support such messages sent over JTAG,
2353 for receipt by the person debugging or tools.
2354 @item Loss of power ... some adapters can detect these events.
2355 @item Resets not issued through JTAG ... such reset sources
2356 can include button presses or other system hardware, sometimes
2357 including the target itself (perhaps through a watchdog).
2358 @item Debug instrumentation sometimes supports event triggering
2359 such as ``trace buffer full'' (so it can quickly be emptied)
2360 or other signals (to correlate with code behavior).
2361 @end itemize
2362
2363 None of those events are signaled through standard JTAG signals.
2364 However, most conventions for JTAG connectors include voltage
2365 level and system reset (SRST) signal detection.
2366 Some connectors also include instrumentation signals, which
2367 can imply events when those signals are inputs.
2368
2369 In general, OpenOCD needs to periodically check for those events,
2370 either by looking at the status of signals on the JTAG connector
2371 or by sending synchronous ``tell me your status'' JTAG requests
2372 to the various active targets.
2373 There is a command to manage and monitor that polling,
2374 which is normally done in the background.
2375
2376 @deffn Command poll [@option{on}|@option{off}]
2377 Poll the current target for its current state.
2378 (Also, @pxref{targetcurstate,,target curstate}.)
2379 If that target is in debug mode, architecture
2380 specific information about the current state is printed.
2381 An optional parameter
2382 allows background polling to be enabled and disabled.
2383
2384 You could use this from the TCL command shell, or
2385 from GDB using @command{monitor poll} command.
2386 Leave background polling enabled while you're using GDB.
2387 @example
2388 > poll
2389 background polling: on
2390 target state: halted
2391 target halted in ARM state due to debug-request, \
2392 current mode: Supervisor
2393 cpsr: 0x800000d3 pc: 0x11081bfc
2394 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2395 >
2396 @end example
2397 @end deffn
2398
2399 @node Debug Adapter Configuration
2400 @chapter Debug Adapter Configuration
2401 @cindex config file, interface
2402 @cindex interface config file
2403
2404 Correctly installing OpenOCD includes making your operating system give
2405 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2406 are used to select which one is used, and to configure how it is used.
2407
2408 @quotation Note
2409 Because OpenOCD started out with a focus purely on JTAG, you may find
2410 places where it wrongly presumes JTAG is the only transport protocol
2411 in use. Be aware that recent versions of OpenOCD are removing that
2412 limitation. JTAG remains more functional than most other transports.
2413 Other transports do not support boundary scan operations, or may be
2414 specific to a given chip vendor. Some might be usable only for
2415 programming flash memory, instead of also for debugging.
2416 @end quotation
2417
2418 Debug Adapters/Interfaces/Dongles are normally configured
2419 through commands in an interface configuration
2420 file which is sourced by your @file{openocd.cfg} file, or
2421 through a command line @option{-f interface/....cfg} option.
2422
2423 @example
2424 source [find interface/olimex-jtag-tiny.cfg]
2425 @end example
2426
2427 These commands tell
2428 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2429 A few cases are so simple that you only need to say what driver to use:
2430
2431 @example
2432 # jlink interface
2433 interface jlink
2434 @end example
2435
2436 Most adapters need a bit more configuration than that.
2437
2438
2439 @section Interface Configuration
2440
2441 The interface command tells OpenOCD what type of debug adapter you are
2442 using. Depending on the type of adapter, you may need to use one or
2443 more additional commands to further identify or configure the adapter.
2444
2445 @deffn {Config Command} {interface} name
2446 Use the interface driver @var{name} to connect to the
2447 target.
2448 @end deffn
2449
2450 @deffn Command {interface_list}
2451 List the debug adapter drivers that have been built into
2452 the running copy of OpenOCD.
2453 @end deffn
2454 @deffn Command {interface transports} transport_name+
2455 Specifies the transports supported by this debug adapter.
2456 The adapter driver builds-in similar knowledge; use this only
2457 when external configuration (such as jumpering) changes what
2458 the hardware can support.
2459 @end deffn
2460
2461
2462
2463 @deffn Command {adapter_name}
2464 Returns the name of the debug adapter driver being used.
2465 @end deffn
2466
2467 @section Interface Drivers
2468
2469 Each of the interface drivers listed here must be explicitly
2470 enabled when OpenOCD is configured, in order to be made
2471 available at run time.
2472
2473 @deffn {Interface Driver} {amt_jtagaccel}
2474 Amontec Chameleon in its JTAG Accelerator configuration,
2475 connected to a PC's EPP mode parallel port.
2476 This defines some driver-specific commands:
2477
2478 @deffn {Config Command} {parport_port} number
2479 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2480 the number of the @file{/dev/parport} device.
2481 @end deffn
2482
2483 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2484 Displays status of RTCK option.
2485 Optionally sets that option first.
2486 @end deffn
2487 @end deffn
2488
2489 @deffn {Interface Driver} {arm-jtag-ew}
2490 Olimex ARM-JTAG-EW USB adapter
2491 This has one driver-specific command:
2492
2493 @deffn Command {armjtagew_info}
2494 Logs some status
2495 @end deffn
2496 @end deffn
2497
2498 @deffn {Interface Driver} {at91rm9200}
2499 Supports bitbanged JTAG from the local system,
2500 presuming that system is an Atmel AT91rm9200
2501 and a specific set of GPIOs is used.
2502 @c command: at91rm9200_device NAME
2503 @c chooses among list of bit configs ... only one option
2504 @end deffn
2505
2506 @deffn {Interface Driver} {dummy}
2507 A dummy software-only driver for debugging.
2508 @end deffn
2509
2510 @deffn {Interface Driver} {ep93xx}
2511 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2512 @end deffn
2513
2514 @deffn {Interface Driver} {ft2232}
2515 FTDI FT2232 (USB) based devices over one of the userspace libraries.
2516
2517 Note that this driver has several flaws and the @command{ftdi} driver is
2518 recommended as its replacement.
2519
2520 These interfaces have several commands, used to configure the driver
2521 before initializing the JTAG scan chain:
2522
2523 @deffn {Config Command} {ft2232_device_desc} description
2524 Provides the USB device description (the @emph{iProduct string})
2525 of the FTDI FT2232 device. If not
2526 specified, the FTDI default value is used. This setting is only valid
2527 if compiled with FTD2XX support.
2528 @end deffn
2529
2530 @deffn {Config Command} {ft2232_serial} serial-number
2531 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
2532 in case the vendor provides unique IDs and more than one FT2232 device
2533 is connected to the host.
2534 If not specified, serial numbers are not considered.
2535 (Note that USB serial numbers can be arbitrary Unicode strings,
2536 and are not restricted to containing only decimal digits.)
2537 @end deffn
2538
2539 @deffn {Config Command} {ft2232_layout} name
2540 Each vendor's FT2232 device can use different GPIO signals
2541 to control output-enables, reset signals, and LEDs.
2542 Currently valid layout @var{name} values include:
2543 @itemize @minus
2544 @item @b{axm0432_jtag} Axiom AXM-0432
2545 @item @b{comstick} Hitex STR9 comstick
2546 @item @b{cortino} Hitex Cortino JTAG interface
2547 @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
2548 either for the local Cortex-M3 (SRST only)
2549 or in a passthrough mode (neither SRST nor TRST)
2550 This layout can not support the SWO trace mechanism, and should be
2551 used only for older boards (before rev C).
2552 @item @b{luminary_icdi} This layout should be used with most TI/Luminary
2553 eval boards, including Rev C LM3S811 eval boards and the eponymous
2554 ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
2555 to debug some other target. It can support the SWO trace mechanism.
2556 @item @b{flyswatter} Tin Can Tools Flyswatter
2557 @item @b{icebear} ICEbear JTAG adapter from Section 5
2558 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
2559 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
2560 @item @b{m5960} American Microsystems M5960
2561 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
2562 @item @b{oocdlink} OOCDLink
2563 @c oocdlink ~= jtagkey_prototype_v1
2564 @item @b{redbee-econotag} Integrated with a Redbee development board.
2565 @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
2566 @item @b{sheevaplug} Marvell Sheevaplug development kit
2567 @item @b{signalyzer} Xverve Signalyzer
2568 @item @b{stm32stick} Hitex STM32 Performance Stick
2569 @item @b{turtelizer2} egnite Software turtelizer2
2570 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
2571 @end itemize
2572 @end deffn
2573
2574 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
2575 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
2576 default values are used.
2577 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2578 @example
2579 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2580 @end example
2581 @end deffn
2582
2583 @deffn {Config Command} {ft2232_latency} ms
2584 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
2585 ft2232_read() fails to return the expected number of bytes. This can be caused by
2586 USB communication delays and has proved hard to reproduce and debug. Setting the
2587 FT2232 latency timer to a larger value increases delays for short USB packets but it
2588 also reduces the risk of timeouts before receiving the expected number of bytes.
2589 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
2590 @end deffn
2591
2592 @deffn {Config Command} {ft2232_channel} channel
2593 Used to select the channel of the ft2232 chip to use (between 1 and 4).
2594 The default value is 1.
2595 @end deffn
2596
2597 For example, the interface config file for a
2598 Turtelizer JTAG Adapter looks something like this:
2599
2600 @example
2601 interface ft2232
2602 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
2603 ft2232_layout turtelizer2
2604 ft2232_vid_pid 0x0403 0xbdc8
2605 @end example
2606 @end deffn
2607
2608 @deffn {Interface Driver} {ftdi}
2609 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2610 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2611 It is a complete rewrite to address a large number of problems with the ft2232
2612 interface driver.
2613
2614 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2615 bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
2616 consistently faster than the ft2232 driver, sometimes several times faster.
2617
2618 A major improvement of this driver is that support for new FTDI based adapters
2619 can be added competely through configuration files, without the need to patch
2620 and rebuild OpenOCD.
2621
2622 The driver uses a signal abstraction to enable Tcl configuration files to
2623 define outputs for one or several FTDI GPIO. These outputs can then be
2624 controlled using the @command{ftdi_set_signal} command. Special signal names
2625 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2626 will be used for their customary purpose.
2627
2628 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2629 be controlled differently. In order to support tristateable signals such as
2630 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2631 signal. The following output buffer configurations are supported:
2632
2633 @itemize @minus
2634 @item Push-pull with one FTDI output as (non-)inverted data line
2635 @item Open drain with one FTDI output as (non-)inverted output-enable
2636 @item Tristate with one FTDI output as (non-)inverted data line and another
2637 FTDI output as (non-)inverted output-enable
2638 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2639 switching data and direction as necessary
2640 @end itemize
2641
2642 These interfaces have several commands, used to configure the driver
2643 before initializing the JTAG scan chain:
2644
2645 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2646 The vendor ID and product ID of the adapter. If not specified, the FTDI
2647 default values are used.
2648 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2649 @example
2650 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2651 @end example
2652 @end deffn
2653
2654 @deffn {Config Command} {ftdi_device_desc} description
2655 Provides the USB device description (the @emph{iProduct string})
2656 of the adapter. If not specified, the device description is ignored
2657 during device selection.
2658 @end deffn
2659
2660 @deffn {Config Command} {ftdi_serial} serial-number
2661 Specifies the @var{serial-number} of the adapter to use,
2662 in case the vendor provides unique IDs and more than one adapter
2663 is connected to the host.
2664 If not specified, serial numbers are not considered.
2665 (Note that USB serial numbers can be arbitrary Unicode strings,
2666 and are not restricted to containing only decimal digits.)
2667 @end deffn
2668
2669 @deffn {Config Command} {ftdi_channel} channel
2670 Selects the channel of the FTDI device to use for MPSSE operations. Most
2671 adapters use the default, channel 0, but there are exceptions.
2672 @end deffn
2673
2674 @deffn {Config Command} {ftdi_layout_init} data direction
2675 Specifies the initial values of the FTDI GPIO data and direction registers.
2676 Each value is a 16-bit number corresponding to the concatenation of the high
2677 and low FTDI GPIO registers. The values should be selected based on the
2678 schematics of the adapter, such that all signals are set to safe levels with
2679 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2680 and initially asserted reset signals.
2681 @end deffn
2682
2683 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask]
2684 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2685 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2686 register bitmasks to tell the driver the connection and type of the output
2687 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2688 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2689 used with inverting data inputs and @option{-data} with non-inverting inputs.
2690 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2691 not-output-enable) input to the output buffer is connected.
2692
2693 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2694 simple open-collector transistor driver would be specified with @option{-oe}
2695 only. In that case the signal can only be set to drive low or to Hi-Z and the
2696 driver will complain if the signal is set to drive high. Which means that if
2697 it's a reset signal, @command{reset_config} must be specified as
2698 @option{srst_open_drain}, not @option{srst_push_pull}.
2699
2700 A special case is provided when @option{-data} and @option{-oe} is set to the
2701 same bitmask. Then the FTDI pin is considered being connected straight to the
2702 target without any buffer. The FTDI pin is then switched between output and
2703 input as necessary to provide the full set of low, high and Hi-Z
2704 characteristics. In all other cases, the pins specified in a signal definition
2705 are always driven by the FTDI.
2706 @end deffn
2707
2708 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2709 Set a previously defined signal to the specified level.
2710 @itemize @minus
2711 @item @option{0}, drive low
2712 @item @option{1}, drive high
2713 @item @option{z}, set to high-impedance
2714 @end itemize
2715 @end deffn
2716
2717 For example adapter definitions, see the configuration files shipped in the
2718 @file{interface/ftdi} directory.
2719 @end deffn
2720
2721 @deffn {Interface Driver} {remote_bitbang}
2722 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2723 with a remote process and sends ASCII encoded bitbang requests to that process
2724 instead of directly driving JTAG.
2725
2726 The remote_bitbang driver is useful for debugging software running on
2727 processors which are being simulated.
2728
2729 @deffn {Config Command} {remote_bitbang_port} number
2730 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2731 sockets instead of TCP.
2732 @end deffn
2733
2734 @deffn {Config Command} {remote_bitbang_host} hostname
2735 Specifies the hostname of the remote process to connect to using TCP, or the
2736 name of the UNIX socket to use if remote_bitbang_port is 0.
2737 @end deffn
2738
2739 For example, to connect remotely via TCP to the host foobar you might have
2740 something like:
2741
2742 @example
2743 interface remote_bitbang
2744 remote_bitbang_port 3335
2745 remote_bitbang_host foobar
2746 @end example
2747
2748 To connect to another process running locally via UNIX sockets with socket
2749 named mysocket:
2750
2751 @example
2752 interface remote_bitbang
2753 remote_bitbang_port 0
2754 remote_bitbang_host mysocket
2755 @end example
2756 @end deffn
2757
2758 @deffn {Interface Driver} {usb_blaster}
2759 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2760 for FTDI chips. These interfaces have several commands, used to
2761 configure the driver before initializing the JTAG scan chain:
2762
2763 @deffn {Config Command} {usb_blaster_device_desc} description
2764 Provides the USB device description (the @emph{iProduct string})
2765 of the FTDI FT245 device. If not
2766 specified, the FTDI default value is used. This setting is only valid
2767 if compiled with FTD2XX support.
2768 @end deffn
2769
2770 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2771 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2772 default values are used.
2773 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2774 Altera USB-Blaster (default):
2775 @example
2776 usb_blaster_vid_pid 0x09FB 0x6001
2777 @end example
2778 The following VID/PID is for Kolja Waschk's USB JTAG:
2779 @example
2780 usb_blaster_vid_pid 0x16C0 0x06AD
2781 @end example
2782 @end deffn
2783
2784 @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
2785 Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
2786 female JTAG header). These pins can be used as SRST and/or TRST provided the
2787 appropriate connections are made on the target board.
2788
2789 For example, to use pin 6 as SRST (as with an AVR board):
2790 @example
2791 $_TARGETNAME configure -event reset-assert \
2792 "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
2793 @end example
2794 @end deffn
2795
2796 @end deffn
2797
2798 @deffn {Interface Driver} {gw16012}
2799 Gateworks GW16012 JTAG programmer.
2800 This has one driver-specific command:
2801
2802 @deffn {Config Command} {parport_port} [port_number]
2803 Display either the address of the I/O port
2804 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2805 If a parameter is provided, first switch to use that port.
2806 This is a write-once setting.
2807 @end deffn
2808 @end deffn
2809
2810 @deffn {Interface Driver} {jlink}
2811 Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
2812
2813 @quotation Compatibility Note
2814 Segger released many firmware versions for the many harware versions they
2815 produced. OpenOCD was extensively tested and intended to run on all of them,
2816 but some combinations were reported as incompatible. As a general
2817 recommendation, it is advisable to use the latest firmware version
2818 available for each hardware version. However the current V8 is a moving
2819 target, and Segger firmware versions released after the OpenOCD was
2820 released may not be compatible. In such cases it is recommended to
2821 revert to the last known functional version. For 0.5.0, this is from
2822 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2823 version is from "May 3 2012 18:36:22", packed with 4.46f.
2824 @end quotation
2825
2826 @deffn {Command} {jlink caps}
2827 Display the device firmware capabilities.
2828 @end deffn
2829 @deffn {Command} {jlink info}
2830 Display various device information, like hardware version, firmware version, current bus status.
2831 @end deffn
2832 @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
2833 Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
2834 @end deffn
2835 @deffn {Command} {jlink config}
2836 Display the J-Link configuration.
2837 @end deffn
2838 @deffn {Command} {jlink config kickstart} [val]
2839 Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
2840 @end deffn
2841 @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
2842 Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
2843 @end deffn
2844 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2845 Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
2846 E the bit of the subnet mask and
2847 F.G.H.I the subnet mask. Without arguments, show the IP configuration.
2848 @end deffn
2849 @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
2850 Set the USB address; this will also change the product id. Without argument, show the USB address.
2851 @end deffn
2852 @deffn {Command} {jlink config reset}
2853 Reset the current configuration.
2854 @end deffn
2855 @deffn {Command} {jlink config save}
2856 Save the current configuration to the internal persistent storage.
2857 @end deffn
2858 @deffn {Config} {jlink pid} val
2859 Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
2860 @end deffn
2861 @end deffn
2862
2863 @deffn {Interface Driver} {parport}
2864 Supports PC parallel port bit-banging cables:
2865 Wigglers, PLD download cable, and more.
2866 These interfaces have several commands, used to configure the driver
2867 before initializing the JTAG scan chain:
2868
2869 @deffn {Config Command} {parport_cable} name
2870 Set the layout of the parallel port cable used to connect to the target.
2871 This is a write-once setting.
2872 Currently valid cable @var{name} values include:
2873
2874 @itemize @minus
2875 @item @b{altium} Altium Universal JTAG cable.
2876 @item @b{arm-jtag} Same as original wiggler except SRST and
2877 TRST connections reversed and TRST is also inverted.
2878 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2879 in configuration mode. This is only used to
2880 program the Chameleon itself, not a connected target.
2881 @item @b{dlc5} The Xilinx Parallel cable III.
2882 @item @b{flashlink} The ST Parallel cable.
2883 @item @b{lattice} Lattice ispDOWNLOAD Cable
2884 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2885 some versions of
2886 Amontec's Chameleon Programmer. The new version available from
2887 the website uses the original Wiggler layout ('@var{wiggler}')
2888 @item @b{triton} The parallel port adapter found on the
2889 ``Karo Triton 1 Development Board''.
2890 This is also the layout used by the HollyGates design
2891 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2892 @item @b{wiggler} The original Wiggler layout, also supported by
2893 several clones, such as the Olimex ARM-JTAG
2894 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2895 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2896 @end itemize
2897 @end deffn
2898
2899 @deffn {Config Command} {parport_port} [port_number]
2900 Display either the address of the I/O port
2901 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2902 If a parameter is provided, first switch to use that port.
2903 This is a write-once setting.
2904
2905 When using PPDEV to access the parallel port, use the number of the parallel port:
2906 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2907 you may encounter a problem.
2908 @end deffn
2909
2910 @deffn Command {parport_toggling_time} [nanoseconds]
2911 Displays how many nanoseconds the hardware needs to toggle TCK;
2912 the parport driver uses this value to obey the
2913 @command{adapter_khz} configuration.
2914 When the optional @var{nanoseconds} parameter is given,
2915 that setting is changed before displaying the current value.
2916
2917 The default setting should work reasonably well on commodity PC hardware.
2918 However, you may want to calibrate for your specific hardware.
2919 @quotation Tip
2920 To measure the toggling time with a logic analyzer or a digital storage
2921 oscilloscope, follow the procedure below:
2922 @example
2923 > parport_toggling_time 1000
2924 > adapter_khz 500
2925 @end example
2926 This sets the maximum JTAG clock speed of the hardware, but
2927 the actual speed probably deviates from the requested 500 kHz.
2928 Now, measure the time between the two closest spaced TCK transitions.
2929 You can use @command{runtest 1000} or something similar to generate a
2930 large set of samples.
2931 Update the setting to match your measurement:
2932 @example
2933 > parport_toggling_time <measured nanoseconds>
2934 @end example
2935 Now the clock speed will be a better match for @command{adapter_khz rate}
2936 commands given in OpenOCD scripts and event handlers.
2937
2938 You can do something similar with many digital multimeters, but note
2939 that you'll probably need to run the clock continuously for several
2940 seconds before it decides what clock rate to show. Adjust the
2941 toggling time up or down until the measured clock rate is a good
2942 match for the adapter_khz rate you specified; be conservative.
2943 @end quotation
2944 @end deffn
2945
2946 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2947 This will configure the parallel driver to write a known
2948 cable-specific value to the parallel interface on exiting OpenOCD.
2949 @end deffn
2950
2951 For example, the interface configuration file for a
2952 classic ``Wiggler'' cable on LPT2 might look something like this:
2953
2954 @example
2955 interface parport
2956 parport_port 0x278
2957 parport_cable wiggler
2958 @end example
2959 @end deffn
2960
2961 @deffn {Interface Driver} {presto}
2962 ASIX PRESTO USB JTAG programmer.
2963 @deffn {Config Command} {presto_serial} serial_string
2964 Configures the USB serial number of the Presto device to use.
2965 @end deffn
2966 @end deffn
2967
2968 @deffn {Interface Driver} {rlink}
2969 Raisonance RLink USB adapter
2970 @end deffn
2971
2972 @deffn {Interface Driver} {usbprog}
2973 usbprog is a freely programmable USB adapter.
2974 @end deffn
2975
2976 @deffn {Interface Driver} {vsllink}
2977 vsllink is part of Versaloon which is a versatile USB programmer.
2978
2979 @quotation Note
2980 This defines quite a few driver-specific commands,
2981 which are not currently documented here.
2982 @end quotation
2983 @end deffn
2984
2985 @deffn {Interface Driver} {hla}
2986 This is a driver that supports multiple High Level Adapters.
2987 This type of adapter does not expose some of the lower level api's
2988 that OpenOCD would normally use to access the target.
2989
2990 Currently supported adapters include the ST STLINK and TI ICDI.
2991
2992 @deffn {Config Command} {hla_device_desc} description
2993 Currently Not Supported.
2994 @end deffn
2995
2996 @deffn {Config Command} {hla_serial} serial
2997 Currently Not Supported.
2998 @end deffn
2999
3000 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
3001 Specifies the adapter layout to use.
3002 @end deffn
3003
3004 @deffn {Config Command} {hla_vid_pid} vid pid
3005 The vendor ID and product ID of the device.
3006 @end deffn
3007
3008 @deffn {Config Command} {stlink_api} api_level
3009 Manually sets the stlink api used, valid options are 1 or 2. (@b{STLINK Only}).
3010 @end deffn
3011 @end deffn
3012
3013 @deffn {Interface Driver} {opendous}
3014 opendous-jtag is a freely programmable USB adapter.
3015 @end deffn
3016
3017 @deffn {Interface Driver} {ulink}
3018 This is the Keil ULINK v1 JTAG debugger.
3019 @end deffn
3020
3021 @deffn {Interface Driver} {ZY1000}
3022 This is the Zylin ZY1000 JTAG debugger.
3023 @end deffn
3024
3025 @quotation Note
3026 This defines some driver-specific commands,
3027 which are not currently documented here.
3028 @end quotation
3029
3030 @deffn Command power [@option{on}|@option{off}]
3031 Turn power switch to target on/off.
3032 No arguments: print status.
3033 @end deffn
3034
3035 @section Transport Configuration
3036 @cindex Transport
3037 As noted earlier, depending on the version of OpenOCD you use,
3038 and the debug adapter you are using,
3039 several transports may be available to
3040 communicate with debug targets (or perhaps to program flash memory).
3041 @deffn Command {transport list}
3042 displays the names of the transports supported by this
3043 version of OpenOCD.
3044 @end deffn
3045
3046 @deffn Command {transport select} transport_name
3047 Select which of the supported transports to use in this OpenOCD session.
3048 The transport must be supported by the debug adapter hardware and by the
3049 version of OPenOCD you are using (including the adapter's driver).
3050 No arguments: returns name of session's selected transport.
3051 @end deffn
3052
3053 @subsection JTAG Transport
3054 @cindex JTAG
3055 JTAG is the original transport supported by OpenOCD, and most
3056 of the OpenOCD commands support it.
3057 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3058 each of which must be explicitly declared.
3059 JTAG supports both debugging and boundary scan testing.
3060 Flash programming support is built on top of debug support.
3061 @subsection SWD Transport
3062 @cindex SWD
3063 @cindex Serial Wire Debug
3064 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3065 Debug Access Point (DAP, which must be explicitly declared.
3066 (SWD uses fewer signal wires than JTAG.)
3067 SWD is debug-oriented, and does not support boundary scan testing.
3068 Flash programming support is built on top of debug support.
3069 (Some processors support both JTAG and SWD.)
3070 @deffn Command {swd newdap} ...
3071 Declares a single DAP which uses SWD transport.
3072 Parameters are currently the same as "jtag newtap" but this is
3073 expected to change.
3074 @end deffn
3075 @deffn Command {swd wcr trn prescale}
3076 Updates TRN (turnaraound delay) and prescaling.fields of the
3077 Wire Control Register (WCR).
3078 No parameters: displays current settings.
3079 @end deffn
3080
3081 @subsection SPI Transport
3082 @cindex SPI
3083 @cindex Serial Peripheral Interface
3084 The Serial Peripheral Interface (SPI) is a general purpose transport
3085 which uses four wire signaling. Some processors use it as part of a
3086 solution for flash programming.
3087
3088 @anchor{jtagspeed}
3089 @section JTAG Speed
3090 JTAG clock setup is part of system setup.
3091 It @emph{does not belong with interface setup} since any interface
3092 only knows a few of the constraints for the JTAG clock speed.
3093 Sometimes the JTAG speed is
3094 changed during the target initialization process: (1) slow at
3095 reset, (2) program the CPU clocks, (3) run fast.
3096 Both the "slow" and "fast" clock rates are functions of the
3097 oscillators used, the chip, the board design, and sometimes
3098 power management software that may be active.
3099
3100 The speed used during reset, and the scan chain verification which
3101 follows reset, can be adjusted using a @code{reset-start}
3102 target event handler.
3103 It can then be reconfigured to a faster speed by a
3104 @code{reset-init} target event handler after it reprograms those
3105 CPU clocks, or manually (if something else, such as a boot loader,
3106 sets up those clocks).
3107 @xref{targetevents,,Target Events}.
3108 When the initial low JTAG speed is a chip characteristic, perhaps
3109 because of a required oscillator speed, provide such a handler
3110 in the target config file.
3111 When that speed is a function of a board-specific characteristic
3112 such as which speed oscillator is used, it belongs in the board
3113 config file instead.
3114 In both cases it's safest to also set the initial JTAG clock rate
3115 to that same slow speed, so that OpenOCD never starts up using a
3116 clock speed that's faster than the scan chain can support.
3117
3118 @example
3119 jtag_rclk 3000
3120 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3121 @end example
3122
3123 If your system supports adaptive clocking (RTCK), configuring
3124 JTAG to use that is probably the most robust approach.
3125 However, it introduces delays to synchronize clocks; so it
3126 may not be the fastest solution.
3127
3128 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3129 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3130 which support adaptive clocking.
3131
3132 @deffn {Command} adapter_khz max_speed_kHz
3133 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3134 JTAG interfaces usually support a limited number of
3135 speeds. The speed actually used won't be faster
3136 than the speed specified.
3137
3138 Chip data sheets generally include a top JTAG clock rate.
3139 The actual rate is often a function of a CPU core clock,
3140 and is normally less than that peak rate.
3141 For example, most ARM cores accept at most one sixth of the CPU clock.
3142
3143 Speed 0 (khz) selects RTCK method.
3144 @xref{faqrtck,,FAQ RTCK}.
3145 If your system uses RTCK, you won't need to change the
3146 JTAG clocking after setup.
3147 Not all interfaces, boards, or targets support ``rtck''.
3148 If the interface device can not
3149 support it, an error is returned when you try to use RTCK.
3150 @end deffn
3151
3152 @defun jtag_rclk fallback_speed_kHz
3153 @cindex adaptive clocking
3154 @cindex RTCK
3155 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3156 If that fails (maybe the interface, board, or target doesn't
3157 support it), falls back to the specified frequency.
3158 @example
3159 # Fall back to 3mhz if RTCK is not supported
3160 jtag_rclk 3000
3161 @end example
3162 @end defun
3163
3164 @node Reset Configuration
3165 @chapter Reset Configuration
3166 @cindex Reset Configuration
3167
3168 Every system configuration may require a different reset
3169 configuration. This can also be quite confusing.
3170 Resets also interact with @var{reset-init} event handlers,
3171 which do things like setting up clocks and DRAM, and
3172 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3173 They can also interact with JTAG routers.
3174 Please see the various board files for examples.
3175
3176 @quotation Note
3177 To maintainers and integrators:
3178 Reset configuration touches several things at once.
3179 Normally the board configuration file
3180 should define it and assume that the JTAG adapter supports
3181 everything that's wired up to the board's JTAG connector.
3182
3183 However, the target configuration file could also make note
3184 of something the silicon vendor has done inside the chip,
3185 which will be true for most (or all) boards using that chip.
3186 And when the JTAG adapter doesn't support everything, the
3187 user configuration file will need to override parts of
3188 the reset configuration provided by other files.
3189 @end quotation
3190
3191 @section Types of Reset
3192
3193 There are many kinds of reset possible through JTAG, but
3194 they may not all work with a given board and adapter.
3195 That's part of why reset configuration can be error prone.
3196
3197 @itemize @bullet
3198 @item
3199 @emph{System Reset} ... the @emph{SRST} hardware signal
3200 resets all chips connected to the JTAG adapter, such as processors,
3201 power management chips, and I/O controllers. Normally resets triggered
3202 with this signal behave exactly like pressing a RESET button.
3203 @item
3204 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3205 just the TAP controllers connected to the JTAG adapter.
3206 Such resets should not be visible to the rest of the system; resetting a
3207 device's TAP controller just puts that controller into a known state.
3208 @item
3209 @emph{Emulation Reset} ... many devices can be reset through JTAG
3210 commands. These resets are often distinguishable from system
3211 resets, either explicitly (a "reset reason" register says so)
3212 or implicitly (not all parts of the chip get reset).
3213 @item
3214 @emph{Other Resets} ... system-on-chip devices often support
3215 several other types of reset.
3216 You may need to arrange that a watchdog timer stops
3217 while debugging, preventing a watchdog reset.
3218 There may be individual module resets.
3219 @end itemize
3220
3221 In the best case, OpenOCD can hold SRST, then reset
3222 the TAPs via TRST and send commands through JTAG to halt the
3223 CPU at the reset vector before the 1st instruction is executed.
3224 Then when it finally releases the SRST signal, the system is
3225 halted under debugger control before any code has executed.
3226 This is the behavior required to support the @command{reset halt}
3227 and @command{reset init} commands; after @command{reset init} a
3228 board-specific script might do things like setting up DRAM.
3229 (@xref{resetcommand,,Reset Command}.)
3230
3231 @anchor{srstandtrstissues}
3232 @section SRST and TRST Issues
3233
3234 Because SRST and TRST are hardware signals, they can have a
3235 variety of system-specific constraints. Some of the most
3236 common issues are:
3237
3238 @itemize @bullet
3239
3240 @item @emph{Signal not available} ... Some boards don't wire
3241 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3242 support such signals even if they are wired up.
3243 Use the @command{reset_config} @var{signals} options to say
3244 when either of those signals is not connected.
3245 When SRST is not available, your code might not be able to rely
3246 on controllers having been fully reset during code startup.
3247 Missing TRST is not a problem, since JTAG-level resets can
3248 be triggered using with TMS signaling.
3249
3250 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3251 adapter will connect SRST to TRST, instead of keeping them separate.
3252 Use the @command{reset_config} @var{combination} options to say
3253 when those signals aren't properly independent.
3254
3255 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3256 delay circuit, reset supervisor, or on-chip features can extend
3257 the effect of a JTAG adapter's reset for some time after the adapter
3258 stops issuing the reset. For example, there may be chip or board
3259 requirements that all reset pulses last for at least a
3260 certain amount of time; and reset buttons commonly have
3261 hardware debouncing.
3262 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3263 commands to say when extra delays are needed.
3264
3265 @item @emph{Drive type} ... Reset lines often have a pullup
3266 resistor, letting the JTAG interface treat them as open-drain
3267 signals. But that's not a requirement, so the adapter may need
3268 to use push/pull output drivers.
3269 Also, with weak pullups it may be advisable to drive
3270 signals to both levels (push/pull) to minimize rise times.
3271 Use the @command{reset_config} @var{trst_type} and
3272 @var{srst_type} parameters to say how to drive reset signals.
3273
3274 @item @emph{Special initialization} ... Targets sometimes need
3275 special JTAG initialization sequences to handle chip-specific
3276 issues (not limited to errata).
3277 For example, certain JTAG commands might need to be issued while
3278 the system as a whole is in a reset state (SRST active)
3279 but the JTAG scan chain is usable (TRST inactive).
3280 Many systems treat combined assertion of SRST and TRST as a
3281 trigger for a harder reset than SRST alone.
3282 Such custom reset handling is discussed later in this chapter.
3283 @end itemize
3284
3285 There can also be other issues.
3286 Some devices don't fully conform to the JTAG specifications.
3287 Trivial system-specific differences are common, such as
3288 SRST and TRST using slightly different names.
3289 There are also vendors who distribute key JTAG documentation for
3290 their chips only to developers who have signed a Non-Disclosure
3291 Agreement (NDA).
3292
3293 Sometimes there are chip-specific extensions like a requirement to use
3294 the normally-optional TRST signal (precluding use of JTAG adapters which
3295 don't pass TRST through), or needing extra steps to complete a TAP reset.
3296
3297 In short, SRST and especially TRST handling may be very finicky,
3298 needing to cope with both architecture and board specific constraints.
3299
3300 @section Commands for Handling Resets
3301
3302 @deffn {Command} adapter_nsrst_assert_width milliseconds
3303 Minimum amount of time (in milliseconds) OpenOCD should wait
3304 after asserting nSRST (active-low system reset) before
3305 allowing it to be deasserted.
3306 @end deffn
3307
3308 @deffn {Command} adapter_nsrst_delay milliseconds
3309 How long (in milliseconds) OpenOCD should wait after deasserting
3310 nSRST (active-low system reset) before starting new JTAG operations.
3311 When a board has a reset button connected to SRST line it will
3312 probably have hardware debouncing, implying you should use this.
3313 @end deffn
3314
3315 @deffn {Command} jtag_ntrst_assert_width milliseconds
3316 Minimum amount of time (in milliseconds) OpenOCD should wait
3317 after asserting nTRST (active-low JTAG TAP reset) before
3318 allowing it to be deasserted.
3319 @end deffn
3320
3321 @deffn {Command} jtag_ntrst_delay milliseconds
3322 How long (in milliseconds) OpenOCD should wait after deasserting
3323 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3324 @end deffn
3325
3326 @deffn {Command} reset_config mode_flag ...
3327 This command displays or modifies the reset configuration
3328 of your combination of JTAG board and target in target
3329 configuration scripts.
3330
3331 Information earlier in this section describes the kind of problems
3332 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3333 As a rule this command belongs only in board config files,
3334 describing issues like @emph{board doesn't connect TRST};
3335 or in user config files, addressing limitations derived
3336 from a particular combination of interface and board.
3337 (An unlikely example would be using a TRST-only adapter
3338 with a board that only wires up SRST.)
3339
3340 The @var{mode_flag} options can be specified in any order, but only one
3341 of each type -- @var{signals}, @var{combination}, @var{gates},
3342 @var{trst_type}, @var{srst_type} and @var{connect_type}
3343 -- may be specified at a time.
3344 If you don't provide a new value for a given type, its previous
3345 value (perhaps the default) is unchanged.
3346 For example, this means that you don't need to say anything at all about
3347 TRST just to declare that if the JTAG adapter should want to drive SRST,
3348 it must explicitly be driven high (@option{srst_push_pull}).
3349
3350 @itemize
3351 @item
3352 @var{signals} can specify which of the reset signals are connected.
3353 For example, If the JTAG interface provides SRST, but the board doesn't
3354 connect that signal properly, then OpenOCD can't use it.
3355 Possible values are @option{none} (the default), @option{trst_only},
3356 @option{srst_only} and @option{trst_and_srst}.
3357
3358 @quotation Tip
3359 If your board provides SRST and/or TRST through the JTAG connector,
3360 you must declare that so those signals can be used.
3361 @end quotation
3362
3363 @item
3364 The @var{combination} is an optional value specifying broken reset
3365 signal implementations.
3366 The default behaviour if no option given is @option{separate},
3367 indicating everything behaves normally.
3368 @option{srst_pulls_trst} states that the
3369 test logic is reset together with the reset of the system (e.g. NXP
3370 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3371 the system is reset together with the test logic (only hypothetical, I
3372 haven't seen hardware with such a bug, and can be worked around).
3373 @option{combined} implies both @option{srst_pulls_trst} and
3374 @option{trst_pulls_srst}.
3375
3376 @item
3377 The @var{gates} tokens control flags that describe some cases where
3378 JTAG may be unvailable during reset.
3379 @option{srst_gates_jtag} (default)
3380 indicates that asserting SRST gates the
3381 JTAG clock. This means that no communication can happen on JTAG
3382 while SRST is asserted.
3383 Its converse is @option{srst_nogate}, indicating that JTAG commands
3384 can safely be issued while SRST is active.
3385
3386 @item
3387 The @var{connect_type} tokens control flags that describe some cases where
3388 SRST is asserted while connecting to the target. @option{srst_nogate}
3389 is required to use this option.
3390 @option{connect_deassert_srst} (default)
3391 indicates that SRST will not be asserted while connecting to the target.
3392 Its converse is @option{connect_assert_srst}, indicating that SRST will
3393 be asserted before any target connection.
3394 Only some targets support this feature, STM32 and STR9 are examples.
3395 This feature is useful if you are unable to connect to your target due
3396 to incorrect options byte config or illegal program execution.
3397 @end itemize
3398
3399 The optional @var{trst_type} and @var{srst_type} parameters allow the
3400 driver mode of each reset line to be specified. These values only affect
3401 JTAG interfaces with support for different driver modes, like the Amontec
3402 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3403 relevant signal (TRST or SRST) is not connected.
3404
3405 @itemize
3406 @item
3407 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3408 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3409 Most boards connect this signal to a pulldown, so the JTAG TAPs
3410 never leave reset unless they are hooked up to a JTAG adapter.
3411
3412 @item
3413 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3414 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3415 Most boards connect this signal to a pullup, and allow the
3416 signal to be pulled low by various events including system
3417 powerup and pressing a reset button.
3418 @end itemize
3419 @end deffn
3420
3421 @section Custom Reset Handling
3422 @cindex events
3423
3424 OpenOCD has several ways to help support the various reset
3425 mechanisms provided by chip and board vendors.
3426 The commands shown in the previous section give standard parameters.
3427 There are also @emph{event handlers} associated with TAPs or Targets.
3428 Those handlers are Tcl procedures you can provide, which are invoked
3429 at particular points in the reset sequence.
3430
3431 @emph{When SRST is not an option} you must set
3432 up a @code{reset-assert} event handler for your target.
3433 For example, some JTAG adapters don't include the SRST signal;
3434 and some boards have multiple targets, and you won't always
3435 want to reset everything at once.
3436
3437 After configuring those mechanisms, you might still
3438 find your board doesn't start up or reset correctly.
3439 For example, maybe it needs a slightly different sequence
3440 of SRST and/or TRST manipulations, because of quirks that
3441 the @command{reset_config} mechanism doesn't address;
3442 or asserting both might trigger a stronger reset, which
3443 needs special attention.
3444
3445 Experiment with lower level operations, such as @command{jtag_reset}
3446 and the @command{jtag arp_*} operations shown here,
3447 to find a sequence of operations that works.
3448 @xref{JTAG Commands}.
3449 When you find a working sequence, it can be used to override
3450 @command{jtag_init}, which fires during OpenOCD startup
3451 (@pxref{configurationstage,,Configuration Stage});
3452 or @command{init_reset}, which fires during reset processing.
3453
3454 You might also want to provide some project-specific reset
3455 schemes. For example, on a multi-target board the standard
3456 @command{reset} command would reset all targets, but you
3457 may need the ability to reset only one target at time and
3458 thus want to avoid using the board-wide SRST signal.
3459
3460 @deffn {Overridable Procedure} init_reset mode
3461 This is invoked near the beginning of the @command{reset} command,
3462 usually to provide as much of a cold (power-up) reset as practical.
3463 By default it is also invoked from @command{jtag_init} if
3464 the scan chain does not respond to pure JTAG operations.
3465 The @var{mode} parameter is the parameter given to the
3466 low level reset command (@option{halt},
3467 @option{init}, or @option{run}), @option{setup},
3468 or potentially some other value.
3469
3470 The default implementation just invokes @command{jtag arp_init-reset}.
3471 Replacements will normally build on low level JTAG
3472 operations such as @command{jtag_reset}.
3473 Operations here must not address individual TAPs
3474 (or their associated targets)
3475 until the JTAG scan chain has first been verified to work.
3476
3477 Implementations must have verified the JTAG scan chain before
3478 they return.
3479 This is done by calling @command{jtag arp_init}
3480 (or @command{jtag arp_init-reset}).
3481 @end deffn
3482
3483 @deffn Command {jtag arp_init}
3484 This validates the scan chain using just the four
3485 standard JTAG signals (TMS, TCK, TDI, TDO).
3486 It starts by issuing a JTAG-only reset.
3487 Then it performs checks to verify that the scan chain configuration
3488 matches the TAPs it can observe.
3489 Those checks include checking IDCODE values for each active TAP,
3490 and verifying the length of their instruction registers using
3491 TAP @code{-ircapture} and @code{-irmask} values.
3492 If these tests all pass, TAP @code{setup} events are
3493 issued to all TAPs with handlers for that event.
3494 @end deffn
3495
3496 @deffn Command {jtag arp_init-reset}
3497 This uses TRST and SRST to try resetting
3498 everything on the JTAG scan chain
3499 (and anything else connected to SRST).
3500 It then invokes the logic of @command{jtag arp_init}.
3501 @end deffn
3502
3503
3504 @node TAP Declaration
3505 @chapter TAP Declaration
3506 @cindex TAP declaration
3507 @cindex TAP configuration
3508
3509 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3510 TAPs serve many roles, including:
3511
3512 @itemize @bullet
3513 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
3514 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
3515 Others do it indirectly, making a CPU do it.
3516 @item @b{Program Download} Using the same CPU support GDB uses,
3517 you can initialize a DRAM controller, download code to DRAM, and then
3518 start running that code.
3519 @item @b{Boundary Scan} Most chips support boundary scan, which
3520 helps test for board assembly problems like solder bridges
3521 and missing connections
3522 @end itemize
3523
3524 OpenOCD must know about the active TAPs on your board(s).
3525 Setting up the TAPs is the core task of your configuration files.
3526 Once those TAPs are set up, you can pass their names to code
3527 which sets up CPUs and exports them as GDB targets,
3528 probes flash memory, performs low-level JTAG operations, and more.
3529
3530 @section Scan Chains
3531 @cindex scan chain
3532
3533 TAPs are part of a hardware @dfn{scan chain},
3534 which is daisy chain of TAPs.
3535 They also need to be added to
3536 OpenOCD's software mirror of that hardware list,
3537 giving each member a name and associating other data with it.
3538 Simple scan chains, with a single TAP, are common in
3539 systems with a single microcontroller or microprocessor.
3540 More complex chips may have several TAPs internally.
3541 Very complex scan chains might have a dozen or more TAPs:
3542 several in one chip, more in the next, and connecting
3543 to other boards with their own chips and TAPs.
3544
3545 You can display the list with the @command{scan_chain} command.
3546 (Don't confuse this with the list displayed by the @command{targets}
3547 command, presented in the next chapter.
3548 That only displays TAPs for CPUs which are configured as
3549 debugging targets.)
3550 Here's what the scan chain might look like for a chip more than one TAP:
3551
3552 @verbatim
3553 TapName Enabled IdCode Expected IrLen IrCap IrMask
3554 -- ------------------ ------- ---------- ---------- ----- ----- ------
3555 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3556 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3557 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3558 @end verbatim
3559
3560 OpenOCD can detect some of that information, but not all
3561 of it. @xref{autoprobing,,Autoprobing}.
3562 Unfortunately those TAPs can't always be autoconfigured,
3563 because not all devices provide good support for that.
3564 JTAG doesn't require supporting IDCODE instructions, and
3565 chips with JTAG routers may not link TAPs into the chain
3566 until they are told to do so.
3567
3568 The configuration mechanism currently supported by OpenOCD
3569 requires explicit configuration of all TAP devices using
3570 @command{jtag newtap} commands, as detailed later in this chapter.
3571 A command like this would declare one tap and name it @code{chip1.cpu}:
3572
3573 @example
3574 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3575 @end example
3576
3577 Each target configuration file lists the TAPs provided
3578 by a given chip.
3579 Board configuration files combine all the targets on a board,
3580 and so forth.
3581 Note that @emph{the order in which TAPs are declared is very important.}
3582 It must match the order in the JTAG scan chain, both inside
3583 a single chip and between them.
3584 @xref{faqtaporder,,FAQ TAP Order}.
3585
3586 For example, the ST Microsystems STR912 chip has
3587 three separate TAPs@footnote{See the ST
3588 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3589 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3590 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3591 To configure those taps, @file{target/str912.cfg}
3592 includes commands something like this:
3593
3594 @example
3595 jtag newtap str912 flash ... params ...
3596 jtag newtap str912 cpu ... params ...
3597 jtag newtap str912 bs ... params ...
3598 @end example
3599
3600 Actual config files use a variable instead of literals like
3601 @option{str912}, to support more than one chip of each type.
3602 @xref{Config File Guidelines}.
3603
3604 @deffn Command {jtag names}
3605 Returns the names of all current TAPs in the scan chain.
3606 Use @command{jtag cget} or @command{jtag tapisenabled}
3607 to examine attributes and state of each TAP.
3608 @example
3609 foreach t [jtag names] @{
3610 puts [format "TAP: %s\n" $t]
3611 @}
3612 @end example
3613 @end deffn
3614
3615 @deffn Command {scan_chain}
3616 Displays the TAPs in the scan chain configuration,
3617 and their status.
3618 The set of TAPs listed by this command is fixed by
3619 exiting the OpenOCD configuration stage,
3620 but systems with a JTAG router can
3621 enable or disable TAPs dynamically.
3622 @end deffn
3623
3624 @c FIXME! "jtag cget" should be able to return all TAP
3625 @c attributes, like "$target_name cget" does for targets.
3626
3627 @c Probably want "jtag eventlist", and a "tap-reset" event
3628 @c (on entry to RESET state).
3629
3630 @section TAP Names
3631 @cindex dotted name
3632
3633 When TAP objects are declared with @command{jtag newtap},
3634 a @dfn{dotted.name} is created for the TAP, combining the
3635 name of a module (usually a chip) and a label for the TAP.
3636 For example: @code{xilinx.tap}, @code{str912.flash},
3637 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3638 Many other commands use that dotted.name to manipulate or
3639 refer to the TAP. For example, CPU configuration uses the
3640 name, as does declaration of NAND or NOR flash banks.
3641
3642 The components of a dotted name should follow ``C'' symbol
3643 name rules: start with an alphabetic character, then numbers
3644 and underscores are OK; while others (including dots!) are not.
3645
3646 @quotation Tip
3647 In older code, JTAG TAPs were numbered from 0..N.
3648 This feature is still present.
3649 However its use is highly discouraged, and
3650 should not be relied on; it will be removed by mid-2010.
3651 Update all of your scripts to use TAP names rather than numbers,
3652 by paying attention to the runtime warnings they trigger.
3653 Using TAP numbers in target configuration scripts prevents
3654 reusing those scripts on boards with multiple targets.
3655 @end quotation
3656
3657 @section TAP Declaration Commands
3658
3659 @c shouldn't this be(come) a {Config Command}?
3660 @deffn Command {jtag newtap} chipname tapname configparams...
3661 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3662 and configured according to the various @var{configparams}.
3663
3664 The @var{chipname} is a symbolic name for the chip.
3665 Conventionally target config files use @code{$_CHIPNAME},
3666 defaulting to the model name given by the chip vendor but
3667 overridable.
3668
3669 @cindex TAP naming convention
3670 The @var{tapname} reflects the role of that TAP,
3671 and should follow this convention:
3672
3673 @itemize @bullet
3674 @item @code{bs} -- For boundary scan if this is a seperate TAP;
3675 @item @code{cpu} -- The main CPU of the chip, alternatively
3676 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3677 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
3678 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3679 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3680 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
3681 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3682 @item @code{tap} -- Should be used only FPGA or CPLD like devices
3683 with a single TAP;
3684 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3685 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3686 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
3687 a JTAG TAP; that TAP should be named @code{sdma}.
3688 @end itemize
3689
3690 Every TAP requires at least the following @var{configparams}:
3691
3692 @itemize @bullet
3693 @item @code{-irlen} @var{NUMBER}
3694 @*The length in bits of the
3695 instruction register, such as 4 or 5 bits.
3696 @end itemize
3697
3698 A TAP may also provide optional @var{configparams}:
3699
3700 @itemize @bullet
3701 @item @code{-disable} (or @code{-enable})
3702 @*Use the @code{-disable} parameter to flag a TAP which is not
3703 linked in to the scan chain after a reset using either TRST
3704 or the JTAG state machine's @sc{reset} state.
3705 You may use @code{-enable} to highlight the default state
3706 (the TAP is linked in).
3707 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3708 @item @code{-expected-id} @var{number}
3709 @*A non-zero @var{number} represents a 32-bit IDCODE
3710 which you expect to find when the scan chain is examined.
3711 These codes are not required by all JTAG devices.
3712 @emph{Repeat the option} as many times as required if more than one
3713 ID code could appear (for example, multiple versions).
3714 Specify @var{number} as zero to suppress warnings about IDCODE
3715 values that were found but not included in the list.
3716
3717 Provide this value if at all possible, since it lets OpenOCD
3718 tell when the scan chain it sees isn't right. These values
3719 are provided in vendors' chip documentation, usually a technical
3720 reference manual. Sometimes you may need to probe the JTAG
3721 hardware to find these values.
3722 @xref{autoprobing,,Autoprobing}.
3723 @item @code{-ignore-version}
3724 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3725 option. When vendors put out multiple versions of a chip, or use the same
3726 JTAG-level ID for several largely-compatible chips, it may be more practical
3727 to ignore the version field than to update config files to handle all of
3728 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3729 @item @code{-ircapture} @var{NUMBER}
3730 @*The bit pattern loaded by the TAP into the JTAG shift register
3731 on entry to the @sc{ircapture} state, such as 0x01.
3732 JTAG requires the two LSBs of this value to be 01.
3733 By default, @code{-ircapture} and @code{-irmask} are set
3734 up to verify that two-bit value. You may provide
3735 additional bits, if you know them, or indicate that
3736 a TAP doesn't conform to the JTAG specification.
3737 @item @code{-irmask} @var{NUMBER}
3738 @*A mask used with @code{-ircapture}
3739 to verify that instruction scans work correctly.
3740 Such scans are not used by OpenOCD except to verify that
3741 there seems to be no problems with JTAG scan chain operations.
3742 @end itemize
3743 @end deffn
3744
3745 @section Other TAP commands
3746
3747 @deffn Command {jtag cget} dotted.name @option{-event} name
3748 @deffnx Command {jtag configure} dotted.name @option{-event} name string
3749 At this writing this TAP attribute
3750 mechanism is used only for event handling.
3751 (It is not a direct analogue of the @code{cget}/@code{configure}
3752 mechanism for debugger targets.)
3753 See the next section for information about the available events.
3754
3755 The @code{configure} subcommand assigns an event handler,
3756 a TCL string which is evaluated when the event is triggered.
3757 The @code{cget} subcommand returns that handler.
3758 @end deffn
3759
3760 @section TAP Events
3761 @cindex events
3762 @cindex TAP events
3763
3764 OpenOCD includes two event mechanisms.
3765 The one presented here applies to all JTAG TAPs.
3766 The other applies to debugger targets,
3767 which are associated with certain TAPs.
3768
3769 The TAP events currently defined are:
3770
3771 @itemize @bullet
3772 @item @b{post-reset}
3773 @* The TAP has just completed a JTAG reset.
3774 The tap may still be in the JTAG @sc{reset} state.
3775 Handlers for these events might perform initialization sequences
3776 such as issuing TCK cycles, TMS sequences to ensure
3777 exit from the ARM SWD mode, and more.
3778
3779 Because the scan chain has not yet been verified, handlers for these events
3780 @emph{should not issue commands which scan the JTAG IR or DR registers}
3781 of any particular target.
3782 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3783 @item @b{setup}
3784 @* The scan chain has been reset and verified.
3785 This handler may enable TAPs as needed.
3786 @item @b{tap-disable}
3787 @* The TAP needs to be disabled. This handler should
3788 implement @command{jtag tapdisable}
3789 by issuing the relevant JTAG commands.
3790 @item @b{tap-enable}
3791 @* The TAP needs to be enabled. This handler should
3792 implement @command{jtag tapenable}
3793 by issuing the relevant JTAG commands.
3794 @end itemize
3795
3796 If you need some action after each JTAG reset, which isn't actually
3797 specific to any TAP (since you can't yet trust the scan chain's
3798 contents to be accurate), you might:
3799
3800 @example
3801 jtag configure CHIP.jrc -event post-reset @{
3802 echo "JTAG Reset done"
3803 ... non-scan jtag operations to be done after reset
3804 @}
3805 @end example
3806
3807
3808 @anchor{enablinganddisablingtaps}
3809 @section Enabling and Disabling TAPs
3810 @cindex JTAG Route Controller
3811 @cindex jrc
3812
3813 In some systems, a @dfn{JTAG Route Controller} (JRC)
3814 is used to enable and/or disable specific JTAG TAPs.
3815 Many ARM based chips from Texas Instruments include
3816 an ``ICEpick'' module, which is a JRC.
3817 Such chips include DaVinci and OMAP3 processors.
3818
3819 A given TAP may not be visible until the JRC has been
3820 told to link it into the scan chain; and if the JRC
3821 has been told to unlink that TAP, it will no longer
3822 be visible.
3823 Such routers address problems that JTAG ``bypass mode''
3824 ignores, such as:
3825
3826 @itemize
3827 @item The scan chain can only go as fast as its slowest TAP.
3828 @item Having many TAPs slows instruction scans, since all
3829 TAPs receive new instructions.
3830 @item TAPs in the scan chain must be powered up, which wastes
3831 power and prevents debugging some power management mechanisms.
3832 @end itemize
3833
3834 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3835 as implied by the existence of JTAG routers.
3836 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3837 does include a kind of JTAG router functionality.
3838
3839 @c (a) currently the event handlers don't seem to be able to
3840 @c fail in a way that could lead to no-change-of-state.
3841
3842 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3843 shown below, and is implemented using TAP event handlers.
3844 So for example, when defining a TAP for a CPU connected to
3845 a JTAG router, your @file{target.cfg} file
3846 should define TAP event handlers using
3847 code that looks something like this:
3848
3849 @example
3850 jtag configure CHIP.cpu -event tap-enable @{
3851 ... jtag operations using CHIP.jrc
3852 @}
3853 jtag configure CHIP.cpu -event tap-disable @{
3854 ... jtag operations using CHIP.jrc
3855 @}
3856 @end example
3857
3858 Then you might want that CPU's TAP enabled almost all the time:
3859
3860 @example
3861 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3862 @end example
3863
3864 Note how that particular setup event handler declaration
3865 uses quotes to evaluate @code{$CHIP} when the event is configured.
3866 Using brackets @{ @} would cause it to be evaluated later,
3867 at runtime, when it might have a different value.
3868
3869 @deffn Command {jtag tapdisable} dotted.name
3870 If necessary, disables the tap
3871 by sending it a @option{tap-disable} event.
3872 Returns the string "1" if the tap
3873 specified by @var{dotted.name} is enabled,
3874 and "0" if it is disabled.
3875 @end deffn
3876
3877 @deffn Command {jtag tapenable} dotted.name
3878 If necessary, enables the tap
3879 by sending it a @option{tap-enable} event.
3880 Returns the string "1" if the tap
3881 specified by @var{dotted.name} is enabled,
3882 and "0" if it is disabled.
3883 @end deffn
3884
3885 @deffn Command {jtag tapisenabled} dotted.name
3886 Returns the string "1" if the tap
3887 specified by @var{dotted.name} is enabled,
3888 and "0" if it is disabled.
3889
3890 @quotation Note
3891 Humans will find the @command{scan_chain} command more helpful
3892 for querying the state of the JTAG taps.
3893 @end quotation
3894 @end deffn
3895
3896 @anchor{autoprobing}
3897 @section Autoprobing
3898 @cindex autoprobe
3899 @cindex JTAG autoprobe
3900
3901 TAP configuration is the first thing that needs to be done
3902 after interface and reset configuration. Sometimes it's
3903 hard finding out what TAPs exist, or how they are identified.
3904 Vendor documentation is not always easy to find and use.
3905
3906 To help you get past such problems, OpenOCD has a limited
3907 @emph{autoprobing} ability to look at the scan chain, doing
3908 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3909 To use this mechanism, start the OpenOCD server with only data
3910 that configures your JTAG interface, and arranges to come up
3911 with a slow clock (many devices don't support fast JTAG clocks
3912 right when they come out of reset).
3913
3914 For example, your @file{openocd.cfg} file might have:
3915
3916 @example
3917 source [find interface/olimex-arm-usb-tiny-h.cfg]
3918 reset_config trst_and_srst
3919 jtag_rclk 8
3920 @end example
3921
3922 When you start the server without any TAPs configured, it will
3923 attempt to autoconfigure the TAPs. There are two parts to this:
3924
3925 @enumerate
3926 @item @emph{TAP discovery} ...
3927 After a JTAG reset (sometimes a system reset may be needed too),
3928 each TAP's data registers will hold the contents of either the
3929 IDCODE or BYPASS register.
3930 If JTAG communication is working, OpenOCD will see each TAP,
3931 and report what @option{-expected-id} to use with it.
3932 @item @emph{IR Length discovery} ...
3933 Unfortunately JTAG does not provide a reliable way to find out
3934 the value of the @option{-irlen} parameter to use with a TAP
3935 that is discovered.
3936 If OpenOCD can discover the length of a TAP's instruction
3937 register, it will report it.
3938 Otherwise you may need to consult vendor documentation, such
3939 as chip data sheets or BSDL files.
3940 @end enumerate
3941
3942 In many cases your board will have a simple scan chain with just
3943 a single device. Here's what OpenOCD reported with one board
3944 that's a bit more complex:
3945
3946 @example
3947 clock speed 8 kHz
3948 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3949 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3950 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3951 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3952 AUTO auto0.tap - use "... -irlen 4"
3953 AUTO auto1.tap - use "... -irlen 4"
3954 AUTO auto2.tap - use "... -irlen 6"
3955 no gdb ports allocated as no target has been specified
3956 @end example
3957
3958 Given that information, you should be able to either find some existing
3959 config files to use, or create your own. If you create your own, you
3960 would configure from the bottom up: first a @file{target.cfg} file
3961 with these TAPs, any targets associated with them, and any on-chip
3962 resources; then a @file{board.cfg} with off-chip resources, clocking,
3963 and so forth.
3964
3965 @node CPU Configuration
3966 @chapter CPU Configuration
3967 @cindex GDB target
3968
3969 This chapter discusses how to set up GDB debug targets for CPUs.
3970 You can also access these targets without GDB
3971 (@pxref{Architecture and Core Commands},
3972 and @ref{targetstatehandling,,Target State handling}) and
3973 through various kinds of NAND and NOR flash commands.
3974 If you have multiple CPUs you can have multiple such targets.
3975
3976 We'll start by looking at how to examine the targets you have,
3977 then look at how to add one more target and how to configure it.
3978
3979 @section Target List
3980 @cindex target, current
3981 @cindex target, list
3982
3983 All targets that have been set up are part of a list,
3984 where each member has a name.
3985 That name should normally be the same as the TAP name.
3986 You can display the list with the @command{targets}
3987 (plural!) command.
3988 This display often has only one CPU; here's what it might
3989 look like with more than one:
3990 @verbatim
3991 TargetName Type Endian TapName State
3992 -- ------------------ ---------- ------ ------------------ ------------
3993 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
3994 1 MyTarget cortex_m little mychip.foo tap-disabled
3995 @end verbatim
3996
3997 One member of that list is the @dfn{current target}, which
3998 is implicitly referenced by many commands.
3999 It's the one marked with a @code{*} near the target name.
4000 In particular, memory addresses often refer to the address
4001 space seen by that current target.
4002 Commands like @command{mdw} (memory display words)
4003 and @command{flash erase_address} (erase NOR flash blocks)
4004 are examples; and there are many more.
4005
4006 Several commands let you examine the list of targets:
4007
4008 @deffn Command {target count}
4009 @emph{Note: target numbers are deprecated; don't use them.
4010 They will be removed shortly after August 2010, including this command.
4011 Iterate target using @command{target names}, not by counting.}
4012
4013 Returns the number of targets, @math{N}.
4014 The highest numbered target is @math{N - 1}.
4015 @example
4016 set c [target count]
4017 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
4018 # Assuming you have created this function
4019 print_target_details $x
4020 @}
4021 @end example
4022 @end deffn
4023
4024 @deffn Command {target current}
4025 Returns the name of the current target.
4026 @end deffn
4027
4028 @deffn Command {target names}
4029 Lists the names of all current targets in the list.
4030 @example
4031 foreach t [target names] @{
4032 puts [format "Target: %s\n" $t]
4033 @}
4034 @end example
4035 @end deffn
4036
4037 @deffn Command {target number} number
4038 @emph{Note: target numbers are deprecated; don't use them.
4039 They will be removed shortly after August 2010, including this command.}
4040
4041 The list of targets is numbered starting at zero.
4042 This command returns the name of the target at index @var{number}.
4043 @example
4044 set thename [target number $x]
4045 puts [format "Target %d is: %s\n" $x $thename]
4046 @end example
4047 @end deffn
4048
4049 @c yep, "target list" would have been better.
4050 @c plus maybe "target setdefault".
4051
4052 @deffn Command targets [name]
4053 @emph{Note: the name of this command is plural. Other target
4054 command names are singular.}
4055
4056 With no parameter, this command displays a table of all known
4057 targets in a user friendly form.
4058
4059 With a parameter, this command sets the current target to
4060 the given target with the given @var{name}; this is
4061 only relevant on boards which have more than one target.
4062 @end deffn
4063
4064 @section Target CPU Types and Variants
4065 @cindex target type
4066 @cindex CPU type
4067 @cindex CPU variant
4068
4069 Each target has a @dfn{CPU type}, as shown in the output of
4070 the @command{targets} command. You need to specify that type
4071 when calling @command{target create}.
4072 The CPU type indicates more than just the instruction set.
4073 It also indicates how that instruction set is implemented,
4074 what kind of debug support it integrates,
4075 whether it has an MMU (and if so, what kind),
4076 what core-specific commands may be available
4077 (@pxref{Architecture and Core Commands}),
4078 and more.
4079
4080 For some CPU types, OpenOCD also defines @dfn{variants} which
4081 indicate differences that affect their handling.
4082 For example, a particular implementation bug might need to be
4083 worked around in some chip versions.
4084
4085 It's easy to see what target types are supported,
4086 since there's a command to list them.
4087 However, there is currently no way to list what target variants
4088 are supported (other than by reading the OpenOCD source code).
4089
4090 @anchor{targettypes}
4091 @deffn Command {target types}
4092 Lists all supported target types.
4093 At this writing, the supported CPU types and variants are:
4094
4095 @itemize @bullet
4096 @item @code{arm11} -- this is a generation of ARMv6 cores
4097 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4098 @item @code{arm7tdmi} -- this is an ARMv4 core
4099 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4100 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4101 @item @code{arm966e} -- this is an ARMv5 core
4102 @item @code{arm9tdmi} -- this is an ARMv4 core
4103 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4104 (Support for this is preliminary and incomplete.)
4105 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4106 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4107 compact Thumb2 instruction set.
4108 @item @code{dragonite} -- resembles arm966e
4109 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4110 (Support for this is still incomplete.)
4111 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4112 @item @code{feroceon} -- resembles arm926
4113 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
4114 @item @code{xscale} -- this is actually an architecture,
4115 not a CPU type. It is based on the ARMv5 architecture.
4116 There are several variants defined:
4117 @itemize @minus
4118 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
4119 @code{pxa27x} ... instruction register length is 7 bits
4120 @item @code{pxa250}, @code{pxa255},
4121 @code{pxa26x} ... instruction register length is 5 bits
4122 @item @code{pxa3xx} ... instruction register length is 11 bits
4123 @end itemize
4124 @end itemize
4125 @end deffn
4126
4127 To avoid being confused by the variety of ARM based cores, remember
4128 this key point: @emph{ARM is a technology licencing company}.
4129 (See: @url{http://www.arm.com}.)
4130 The CPU name used by OpenOCD will reflect the CPU design that was
4131 licenced, not a vendor brand which incorporates that design.
4132 Name prefixes like arm7, arm9, arm11, and cortex
4133 reflect design generations;
4134 while names like ARMv4, ARMv5, ARMv6, and ARMv7
4135 reflect an architecture version implemented by a CPU design.
4136
4137 @anchor{targetconfiguration}
4138 @section Target Configuration
4139
4140 Before creating a ``target'', you must have added its TAP to the scan chain.
4141 When you've added that TAP, you will have a @code{dotted.name}
4142 which is used to set up the CPU support.
4143 The chip-specific configuration file will normally configure its CPU(s)
4144 right after it adds all of the chip's TAPs to the scan chain.
4145
4146 Although you can set up a target in one step, it's often clearer if you
4147 use shorter commands and do it in two steps: create it, then configure
4148 optional parts.
4149 All operations on the target after it's created will use a new
4150 command, created as part of target creation.
4151
4152 The two main things to configure after target creation are
4153 a work area, which usually has target-specific defaults even
4154 if the board setup code overrides them later;
4155 and event handlers (@pxref{targetevents,,Target Events}), which tend
4156 to be much more board-specific.
4157 The key steps you use might look something like this
4158
4159 @example
4160 target create MyTarget cortex_m -chain-position mychip.cpu
4161 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4162 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4163 $MyTarget configure -event reset-init @{ myboard_reinit @}
4164 @end example
4165
4166 You should specify a working area if you can; typically it uses some
4167 on-chip SRAM.
4168 Such a working area can speed up many things, including bulk
4169 writes to target memory;
4170 flash operations like checking to see if memory needs to be erased;
4171 GDB memory checksumming;
4172 and more.
4173
4174 @quotation Warning
4175 On more complex chips, the work area can become
4176 inaccessible when application code
4177 (such as an operating system)
4178 enables or disables the MMU.
4179 For example, the particular MMU context used to acess the virtual
4180 address will probably matter ... and that context might not have
4181 easy access to other addresses needed.
4182 At this writing, OpenOCD doesn't have much MMU intelligence.
4183 @end quotation
4184
4185 It's often very useful to define a @code{reset-init} event handler.
4186 For systems that are normally used with a boot loader,
4187 common tasks include updating clocks and initializing memory
4188 controllers.
4189 That may be needed to let you write the boot loader into flash,
4190 in order to ``de-brick'' your board; or to load programs into
4191 external DDR memory without having run the boot loader.
4192
4193 @deffn Command {target create} target_name type configparams...
4194 This command creates a GDB debug target that refers to a specific JTAG tap.
4195 It enters that target into a list, and creates a new
4196 command (@command{@var{target_name}}) which is used for various
4197 purposes including additional configuration.
4198
4199 @itemize @bullet
4200 @item @var{target_name} ... is the name of the debug target.
4201 By convention this should be the same as the @emph{dotted.name}
4202 of the TAP associated with this target, which must be specified here
4203 using the @code{-chain-position @var{dotted.name}} configparam.
4204
4205 This name is also used to create the target object command,
4206 referred to here as @command{$target_name},
4207 and in other places the target needs to be identified.
4208 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4209 @item @var{configparams} ... all parameters accepted by
4210 @command{$target_name configure} are permitted.
4211 If the target is big-endian, set it here with @code{-endian big}.
4212 If the variant matters, set it here with @code{-variant}.
4213
4214 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
4215 @end itemize
4216 @end deffn
4217
4218 @deffn Command {$target_name configure} configparams...
4219 The options accepted by this command may also be
4220 specified as parameters to @command{target create}.
4221 Their values can later be queried one at a time by
4222 using the @command{$target_name cget} command.
4223
4224 @emph{Warning:} changing some of these after setup is dangerous.
4225 For example, moving a target from one TAP to another;
4226 and changing its endianness or variant.
4227
4228 @itemize @bullet
4229
4230 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4231 used to access this target.
4232
4233 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4234 whether the CPU uses big or little endian conventions
4235
4236 @item @code{-event} @var{event_name} @var{event_body} --
4237 @xref{targetevents,,Target Events}.
4238 Note that this updates a list of named event handlers.
4239 Calling this twice with two different event names assigns
4240 two different handlers, but calling it twice with the
4241 same event name assigns only one handler.
4242
4243 @item @code{-variant} @var{name} -- specifies a variant of the target,
4244 which OpenOCD needs to know about.
4245
4246 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4247 whether the work area gets backed up; by default,
4248 @emph{it is not backed up.}
4249 When possible, use a working_area that doesn't need to be backed up,
4250 since performing a backup slows down operations.
4251 For example, the beginning of an SRAM block is likely to
4252 be used by most build systems, but the end is often unused.
4253
4254 @item @code{-work-area-size} @var{size} -- specify work are size,
4255 in bytes. The same size applies regardless of whether its physical
4256 or virtual address is being used.
4257
4258 @item @code{-work-area-phys} @var{address} -- set the work area
4259 base @var{address} to be used when no MMU is active.
4260
4261 @item @code{-work-area-virt} @var{address} -- set the work area
4262 base @var{address} to be used when an MMU is active.
4263 @emph{Do not specify a value for this except on targets with an MMU.}
4264 The value should normally correspond to a static mapping for the
4265 @code{-work-area-phys} address, set up by the current operating system.
4266
4267 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4268 @var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}|
4269 @option{FreeRTOS}|@option{linux}|@option{ChibiOS}.
4270
4271 @end itemize
4272 @end deffn
4273
4274 @section Other $target_name Commands
4275 @cindex object command
4276
4277 The Tcl/Tk language has the concept of object commands,
4278 and OpenOCD adopts that same model for targets.
4279
4280 A good Tk example is a on screen button.
4281 Once a button is created a button
4282 has a name (a path in Tk terms) and that name is useable as a first
4283 class command. For example in Tk, one can create a button and later
4284 configure it like this:
4285
4286 @example
4287 # Create
4288 button .foobar -background red -command @{ foo @}
4289 # Modify
4290 .foobar configure -foreground blue
4291 # Query
4292 set x [.foobar cget -background]
4293 # Report
4294 puts [format "The button is %s" $x]
4295 @end example
4296
4297 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4298 button, and its object commands are invoked the same way.
4299
4300 @example
4301 str912.cpu mww 0x1234 0x42
4302 omap3530.cpu mww 0x5555 123
4303 @end example
4304
4305 The commands supported by OpenOCD target objects are:
4306
4307 @deffn Command {$target_name arp_examine}
4308 @deffnx Command {$target_name arp_halt}
4309 @deffnx Command {$target_name arp_poll}
4310 @deffnx Command {$target_name arp_reset}
4311 @deffnx Command {$target_name arp_waitstate}
4312 Internal OpenOCD scripts (most notably @file{startup.tcl})
4313 use these to deal with specific reset cases.
4314 They are not otherwise documented here.
4315 @end deffn
4316
4317 @deffn Command {$target_name array2mem} arrayname width address count
4318 @deffnx Command {$target_name mem2array} arrayname width address count
4319 These provide an efficient script-oriented interface to memory.
4320 The @code{array2mem} primitive writes bytes, halfwords, or words;
4321 while @code{mem2array} reads them.
4322 In both cases, the TCL side uses an array, and
4323 the target side uses raw memory.
4324
4325 The efficiency comes from enabling the use of
4326 bulk JTAG data transfer operations.
4327 The script orientation comes from working with data
4328 values that are packaged for use by TCL scripts;
4329 @command{mdw} type primitives only print data they retrieve,
4330 and neither store nor return those values.
4331
4332 @itemize
4333 @item @var{arrayname} ... is the name of an array variable
4334 @item @var{width} ... is 8/16/32 - indicating the memory access size
4335 @item @var{address} ... is the target memory address
4336 @item @var{count} ... is the number of elements to process
4337 @end itemize
4338 @end deffn
4339
4340 @deffn Command {$target_name cget} queryparm
4341 Each configuration parameter accepted by
4342 @command{$target_name configure}
4343 can be individually queried, to return its current value.
4344 The @var{queryparm} is a parameter name
4345 accepted by that command, such as @code{-work-area-phys}.
4346 There are a few special cases:
4347
4348 @itemize @bullet
4349 @item @code{-event} @var{event_name} -- returns the handler for the
4350 event named @var{event_name}.
4351 This is a special case because setting a handler requires
4352 two parameters.
4353 @item @code{-type} -- returns the target type.
4354 This is a special case because this is set using
4355 @command{target create} and can't be changed
4356 using @command{$target_name configure}.
4357 @end itemize
4358
4359 For example, if you wanted to summarize information about
4360 all the targets you might use something like this:
4361
4362 @example
4363 foreach name [target names] @{
4364 set y [$name cget -endian]
4365 set z [$name cget -type]
4366 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4367 $x $name $y $z]
4368 @}
4369 @end example
4370 @end deffn
4371
4372 @anchor{targetcurstate}
4373 @deffn Command {$target_name curstate}
4374 Displays the current target state:
4375 @code{debug-running},
4376 @code{halted},
4377 @code{reset},
4378 @code{running}, or @code{unknown}.
4379 (Also, @pxref{eventpolling,,Event Polling}.)
4380 @end deffn
4381
4382 @deffn Command {$target_name eventlist}
4383 Displays a table listing all event handlers
4384 currently associated with this target.
4385 @xref{targetevents,,Target Events}.
4386 @end deffn
4387
4388 @deffn Command {$target_name invoke-event} event_name
4389 Invokes the handler for the event named @var{event_name}.
4390 (This is primarily intended for use by OpenOCD framework
4391 code, for example by the reset code in @file{startup.tcl}.)
4392 @end deffn
4393
4394 @deffn Command {$target_name mdw} addr [count]
4395 @deffnx Command {$target_name mdh} addr [count]
4396 @deffnx Command {$target_name mdb} addr [count]
4397 Display contents of address @var{addr}, as
4398 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4399 or 8-bit bytes (@command{mdb}).
4400 If @var{count} is specified, displays that many units.
4401 (If you want to manipulate the data instead of displaying it,
4402 see the @code{mem2array} primitives.)
4403 @end deffn
4404
4405 @deffn Command {$target_name mww} addr word
4406 @deffnx Command {$target_name mwh} addr halfword
4407 @deffnx Command {$target_name mwb} addr byte
4408 Writes the specified @var{word} (32 bits),
4409 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4410 at the specified address @var{addr}.
4411 @end deffn
4412
4413 @anchor{targetevents}
4414 @section Target Events
4415 @cindex target events
4416 @cindex events
4417 At various times, certain things can happen, or you want them to happen.
4418 For example:
4419 @itemize @bullet
4420 @item What should happen when GDB connects? Should your target reset?
4421 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4422 @item Is using SRST appropriate (and possible) on your system?
4423 Or instead of that, do you need to issue JTAG commands to trigger reset?
4424 SRST usually resets everything on the scan chain, which can be inappropriate.
4425 @item During reset, do you need to write to certain memory locations
4426 to set up system clocks or
4427 to reconfigure the SDRAM?
4428 How about configuring the watchdog timer, or other peripherals,
4429 to stop running while you hold the core stopped for debugging?
4430 @end itemize
4431
4432 All of the above items can be addressed by target event handlers.
4433 These are set up by @command{$target_name configure -event} or
4434 @command{target create ... -event}.
4435
4436 The programmer's model matches the @code{-command} option used in Tcl/Tk
4437 buttons and events. The two examples below act the same, but one creates
4438 and invokes a small procedure while the other inlines it.
4439
4440 @example
4441 proc my_attach_proc @{ @} @{
4442 echo "Reset..."
4443 reset halt
4444 @}
4445 mychip.cpu configure -event gdb-attach my_attach_proc
4446 mychip.cpu configure -event gdb-attach @{
4447 echo "Reset..."
4448 # To make flash probe and gdb load to flash work we need a reset init.
4449 reset init
4450 @}
4451 @end example
4452
4453 The following target events are defined:
4454
4455 @itemize @bullet
4456 @item @b{debug-halted}
4457 @* The target has halted for debug reasons (i.e.: breakpoint)
4458 @item @b{debug-resumed}
4459 @* The target has resumed (i.e.: gdb said run)
4460 @item @b{early-halted}
4461 @* Occurs early in the halt process
4462 @item @b{examine-start}
4463 @* Before target examine is called.
4464 @item @b{examine-end}
4465 @* After target examine is called with no errors.
4466 @item @b{gdb-attach}
4467 @* When GDB connects. This is before any communication with the target, so this
4468 can be used to set up the target so it is possible to probe flash. Probing flash
4469 is necessary during gdb connect if gdb load is to write the image to flash. Another
4470 use of the flash memory map is for GDB to automatically hardware/software breakpoints
4471 depending on whether the breakpoint is in RAM or read only memory.
4472 @item @b{gdb-detach}
4473 @* When GDB disconnects
4474 @item @b{gdb-end}
4475 @* When the target has halted and GDB is not doing anything (see early halt)
4476 @item @b{gdb-flash-erase-start}
4477 @* Before the GDB flash process tries to erase the flash
4478 @item @b{gdb-flash-erase-end}
4479 @* After the GDB flash process has finished erasing the flash
4480 @item @b{gdb-flash-write-start}
4481 @* Before GDB writes to the flash
4482 @item @b{gdb-flash-write-end}
4483 @* After GDB writes to the flash
4484 @item @b{gdb-start}
4485 @* Before the target steps, gdb is trying to start/resume the target
4486 @item @b{halted}
4487 @* The target has halted
4488 @item @b{reset-assert-pre}
4489 @* Issued as part of @command{reset} processing
4490 after @command{reset_init} was triggered
4491 but before either SRST alone is re-asserted on the scan chain,
4492 or @code{reset-assert} is triggered.
4493 @item @b{reset-assert}
4494 @* Issued as part of @command{reset} processing
4495 after @command{reset-assert-pre} was triggered.
4496 When such a handler is present, cores which support this event will use
4497 it instead of asserting SRST.
4498 This support is essential for debugging with JTAG interfaces which
4499 don't include an SRST line (JTAG doesn't require SRST), and for
4500 selective reset on scan chains that have multiple targets.
4501 @item @b{reset-assert-post}
4502 @* Issued as part of @command{reset} processing
4503 after @code{reset-assert} has been triggered.
4504 or the target asserted SRST on the entire scan chain.
4505 @item @b{reset-deassert-pre}
4506 @* Issued as part of @command{reset} processing
4507 after @code{reset-assert-post} has been triggered.
4508 @item @b{reset-deassert-post}
4509 @* Issued as part of @command{reset} processing
4510 after @code{reset-deassert-pre} has been triggered
4511 and (if the target is using it) after SRST has been
4512 released on the scan chain.
4513 @item @b{reset-end}
4514 @* Issued as the final step in @command{reset} processing.
4515 @ignore
4516 @item @b{reset-halt-post}
4517 @* Currently not used
4518 @item @b{reset-halt-pre}
4519 @* Currently not used
4520 @end ignore
4521 @item @b{reset-init}
4522 @* Used by @b{reset init} command for board-specific initialization.
4523 This event fires after @emph{reset-deassert-post}.
4524
4525 This is where you would configure PLLs and clocking, set up DRAM so
4526 you can download programs that don't fit in on-chip SRAM, set up pin
4527 multiplexing, and so on.
4528 (You may be able to switch to a fast JTAG clock rate here, after
4529 the target clocks are fully set up.)
4530 @item @b{reset-start}
4531 @* Issued as part of @command{reset} processing
4532 before @command{reset_init} is called.
4533
4534 This is the most robust place to use @command{jtag_rclk}
4535 or @command{adapter_khz} to switch to a low JTAG clock rate,
4536 when reset disables PLLs needed to use a fast clock.
4537 @ignore
4538 @item @b{reset-wait-pos}
4539 @* Currently not used
4540 @item @b{reset-wait-pre}
4541 @* Currently not used
4542 @end ignore
4543 @item @b{resume-start}
4544 @* Before any target is resumed
4545 @item @b{resume-end}
4546 @* After all targets have resumed
4547 @item @b{resumed}
4548 @* Target has resumed
4549 @end itemize
4550
4551 @node Flash Commands
4552 @chapter Flash Commands
4553
4554 OpenOCD has different commands for NOR and NAND flash;
4555 the ``flash'' command works with NOR flash, while
4556 the ``nand'' command works with NAND flash.
4557 This partially reflects different hardware technologies:
4558 NOR flash usually supports direct CPU instruction and data bus access,
4559 while data from a NAND flash must be copied to memory before it can be
4560 used. (SPI flash must also be copied to memory before use.)
4561 However, the documentation also uses ``flash'' as a generic term;
4562 for example, ``Put flash configuration in board-specific files''.
4563
4564 Flash Steps:
4565 @enumerate
4566 @item Configure via the command @command{flash bank}
4567 @* Do this in a board-specific configuration file,
4568 passing parameters as needed by the driver.
4569 @item Operate on the flash via @command{flash subcommand}
4570 @* Often commands to manipulate the flash are typed by a human, or run
4571 via a script in some automated way. Common tasks include writing a
4572 boot loader, operating system, or other data.
4573 @item GDB Flashing
4574 @* Flashing via GDB requires the flash be configured via ``flash
4575 bank'', and the GDB flash features be enabled.
4576 @xref{gdbconfiguration,,GDB Configuration}.
4577 @end enumerate
4578
4579 Many CPUs have the ablity to ``boot'' from the first flash bank.
4580 This means that misprogramming that bank can ``brick'' a system,
4581 so that it can't boot.
4582 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4583 board by (re)installing working boot firmware.
4584
4585 @anchor{norconfiguration}
4586 @section Flash Configuration Commands
4587 @cindex flash configuration
4588
4589 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4590 Configures a flash bank which provides persistent storage
4591 for addresses from @math{base} to @math{base + size - 1}.
4592 These banks will often be visible to GDB through the target's memory map.
4593 In some cases, configuring a flash bank will activate extra commands;
4594 see the driver-specific documentation.
4595
4596 @itemize @bullet
4597 @item @var{name} ... may be used to reference the flash bank
4598 in other flash commands. A number is also available.
4599 @item @var{driver} ... identifies the controller driver
4600 associated with the flash bank being declared.
4601 This is usually @code{cfi} for external flash, or else
4602 the name of a microcontroller with embedded flash memory.
4603 @xref{flashdriverlist,,Flash Driver List}.
4604 @item @var{base} ... Base address of the flash chip.
4605 @item @var{size} ... Size of the chip, in bytes.
4606 For some drivers, this value is detected from the hardware.
4607 @item @var{chip_width} ... Width of the flash chip, in bytes;
4608 ignored for most microcontroller drivers.
4609 @item @var{bus_width} ... Width of the data bus used to access the
4610 chip, in bytes; ignored for most microcontroller drivers.
4611 @item @var{target} ... Names the target used to issue
4612 commands to the flash controller.
4613 @comment Actually, it's currently a controller-specific parameter...
4614 @item @var{driver_options} ... drivers may support, or require,
4615 additional parameters. See the driver-specific documentation
4616 for more information.
4617 @end itemize
4618 @quotation Note
4619 This command is not available after OpenOCD initialization has completed.
4620 Use it in board specific configuration files, not interactively.
4621 @end quotation
4622 @end deffn
4623
4624 @comment the REAL name for this command is "ocd_flash_banks"
4625 @comment less confusing would be: "flash list" (like "nand list")
4626 @deffn Command {flash banks}
4627 Prints a one-line summary of each device that was
4628 declared using @command{flash bank}, numbered from zero.
4629 Note that this is the @emph{plural} form;
4630 the @emph{singular} form is a very different command.
4631 @end deffn
4632
4633 @deffn Command {flash list}
4634 Retrieves a list of associative arrays for each device that was
4635 declared using @command{flash bank}, numbered from zero.
4636 This returned list can be manipulated easily from within scripts.
4637 @end deffn
4638
4639 @deffn Command {flash probe} num
4640 Identify the flash, or validate the parameters of the configured flash. Operation
4641 depends on the flash type.
4642 The @var{num} parameter is a value shown by @command{flash banks}.
4643 Most flash commands will implicitly @emph{autoprobe} the bank;
4644 flash drivers can distinguish between probing and autoprobing,
4645 but most don't bother.
4646 @end deffn
4647
4648 @section Erasing, Reading, Writing to Flash
4649 @cindex flash erasing
4650 @cindex flash reading
4651 @cindex flash writing
4652 @cindex flash programming
4653 @anchor{flashprogrammingcommands}
4654
4655 One feature distinguishing NOR flash from NAND or serial flash technologies
4656 is that for read access, it acts exactly like any other addressible memory.
4657 This means you can use normal memory read commands like @command{mdw} or
4658 @command{dump_image} with it, with no special @command{flash} subcommands.
4659 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
4660
4661 Write access works differently. Flash memory normally needs to be erased
4662 before it's written. Erasing a sector turns all of its bits to ones, and
4663 writing can turn ones into zeroes. This is why there are special commands
4664 for interactive erasing and writing, and why GDB needs to know which parts
4665 of the address space hold NOR flash memory.
4666
4667 @quotation Note
4668 Most of these erase and write commands leverage the fact that NOR flash
4669 chips consume target address space. They implicitly refer to the current
4670 JTAG target, and map from an address in that target's address space
4671 back to a flash bank.
4672 @comment In May 2009, those mappings may fail if any bank associated
4673 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
4674 A few commands use abstract addressing based on bank and sector numbers,
4675 and don't depend on searching the current target and its address space.
4676 Avoid confusing the two command models.
4677 @end quotation
4678
4679 Some flash chips implement software protection against accidental writes,
4680 since such buggy writes could in some cases ``brick'' a system.
4681 For such systems, erasing and writing may require sector protection to be
4682 disabled first.
4683 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4684 and AT91SAM7 on-chip flash.
4685 @xref{flashprotect,,flash protect}.
4686
4687 @deffn Command {flash erase_sector} num first last
4688 Erase sectors in bank @var{num}, starting at sector @var{first}
4689 up to and including @var{last}.
4690 Sector numbering starts at 0.
4691 Providing a @var{last} sector of @option{last}
4692 specifies "to the end of the flash bank".
4693 The @var{num} parameter is a value shown by @command{flash banks}.
4694 @end deffn
4695
4696 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4697 Erase sectors starting at @var{address} for @var{length} bytes.
4698 Unless @option{pad} is specified, @math{address} must begin a
4699 flash sector, and @math{address + length - 1} must end a sector.
4700 Specifying @option{pad} erases extra data at the beginning and/or
4701 end of the specified region, as needed to erase only full sectors.
4702 The flash bank to use is inferred from the @var{address}, and
4703 the specified length must stay within that bank.
4704 As a special case, when @var{length} is zero and @var{address} is
4705 the start of the bank, the whole flash is erased.
4706 If @option{unlock} is specified, then the flash is unprotected
4707 before erase starts.
4708 @end deffn
4709
4710 @deffn Command {flash fillw} address word length
4711 @deffnx Command {flash fillh} address halfword length
4712 @deffnx Command {flash fillb} address byte length
4713 Fills flash memory with the specified @var{word} (32 bits),
4714 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4715 starting at @var{address} and continuing
4716 for @var{length} units (word/halfword/byte).
4717 No erasure is done before writing; when needed, that must be done
4718 before issuing this command.
4719 Writes are done in blocks of up to 1024 bytes, and each write is
4720 verified by reading back the data and comparing it to what was written.
4721 The flash bank to use is inferred from the @var{address} of
4722 each block, and the specified length must stay within that bank.
4723 @end deffn
4724 @comment no current checks for errors if fill blocks touch multiple banks!
4725
4726 @deffn Command {flash write_bank} num filename offset
4727 Write the binary @file{filename} to flash bank @var{num},
4728 starting at @var{offset} bytes from the beginning of the bank.
4729 The @var{num} parameter is a value shown by @command{flash banks}.
4730 @end deffn
4731
4732 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4733 Write the image @file{filename} to the current target's flash bank(s).
4734 A relocation @var{offset} may be specified, in which case it is added
4735 to the base address for each section in the image.
4736 The file [@var{type}] can be specified
4737 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4738 @option{elf} (ELF file), @option{s19} (Motorola s19).
4739 @option{mem}, or @option{builder}.
4740 The relevant flash sectors will be erased prior to programming
4741 if the @option{erase} parameter is given. If @option{unlock} is
4742 provided, then the flash banks are unlocked before erase and
4743 program. The flash bank to use is inferred from the address of
4744 each image section.
4745
4746 @quotation Warning
4747 Be careful using the @option{erase} flag when the flash is holding
4748 data you want to preserve.
4749 Portions of the flash outside those described in the image's
4750 sections might be erased with no notice.
4751 @itemize
4752 @item
4753 When a section of the image being written does not fill out all the
4754 sectors it uses, the unwritten parts of those sectors are necessarily
4755 also erased, because sectors can't be partially erased.
4756 @item
4757 Data stored in sector "holes" between image sections are also affected.
4758 For example, "@command{flash write_image erase ...}" of an image with
4759 one byte at the beginning of a flash bank and one byte at the end
4760 erases the entire bank -- not just the two sectors being written.
4761 @end itemize
4762 Also, when flash protection is important, you must re-apply it after
4763 it has been removed by the @option{unlock} flag.
4764 @end quotation
4765
4766 @end deffn
4767
4768 @section Other Flash commands
4769 @cindex flash protection
4770
4771 @deffn Command {flash erase_check} num
4772 Check erase state of sectors in flash bank @var{num},
4773 and display that status.
4774 The @var{num} parameter is a value shown by @command{flash banks}.
4775 @end deffn
4776
4777 @deffn Command {flash info} num
4778 Print info about flash bank @var{num}
4779 The @var{num} parameter is a value shown by @command{flash banks}.
4780 This command will first query the hardware, it does not print cached
4781 and possibly stale information.
4782 @end deffn
4783
4784 @anchor{flashprotect}
4785 @deffn Command {flash protect} num first last (@option{on}|@option{off})
4786 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
4787 in flash bank @var{num}, starting at sector @var{first}
4788 and continuing up to and including @var{last}.
4789 Providing a @var{last} sector of @option{last}
4790 specifies "to the end of the flash bank".
4791 The @var{num} parameter is a value shown by @command{flash banks}.
4792 @end deffn
4793
4794 @anchor{program}
4795 @deffn Command {program} filename [verify] [reset] [offset]
4796 This is a helper script that simplifies using OpenOCD as a standalone
4797 programmer. The only required parameter is @option{filename}, the others are optional.
4798 @xref{Flash Programming}.
4799 @end deffn
4800
4801 @anchor{flashdriverlist}
4802 @section Flash Driver List
4803 As noted above, the @command{flash bank} command requires a driver name,
4804 and allows driver-specific options and behaviors.
4805 Some drivers also activate driver-specific commands.
4806
4807 @subsection External Flash
4808
4809 @deffn {Flash Driver} cfi
4810 @cindex Common Flash Interface
4811 @cindex CFI
4812 The ``Common Flash Interface'' (CFI) is the main standard for
4813 external NOR flash chips, each of which connects to a
4814 specific external chip select on the CPU.
4815 Frequently the first such chip is used to boot the system.
4816 Your board's @code{reset-init} handler might need to
4817 configure additional chip selects using other commands (like: @command{mww} to
4818 configure a bus and its timings), or
4819 perhaps configure a GPIO pin that controls the ``write protect'' pin
4820 on the flash chip.
4821 The CFI driver can use a target-specific working area to significantly
4822 speed up operation.
4823
4824 The CFI driver can accept the following optional parameters, in any order:
4825
4826 @itemize
4827 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
4828 like AM29LV010 and similar types.
4829 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
4830 @end itemize
4831
4832 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
4833 wide on a sixteen bit bus:
4834
4835 @example
4836 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
4837 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
4838 @end example
4839
4840 To configure one bank of 32 MBytes
4841 built from two sixteen bit (two byte) wide parts wired in parallel
4842 to create a thirty-two bit (four byte) bus with doubled throughput:
4843
4844 @example
4845 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
4846 @end example
4847
4848 @c "cfi part_id" disabled
4849 @end deffn
4850
4851 @deffn {Flash Driver} lpcspifi
4852 @cindex NXP SPI Flash Interface
4853 @cindex SPIFI
4854 @cindex lpcspifi
4855 NXP's LPC43xx and LPC18xx families include a proprietary SPI
4856 Flash Interface (SPIFI) peripheral that can drive and provide
4857 memory mapped access to external SPI flash devices.
4858
4859 The lpcspifi driver initializes this interface and provides
4860 program and erase functionality for these serial flash devices.
4861 Use of this driver @b{requires} a working area of at least 1kB
4862 to be configured on the target device; more than this will
4863 significantly reduce flash programming times.
4864
4865 The setup command only requires the @var{base} parameter. All
4866 other parameters are ignored, and the flash size and layout
4867 are configured by the driver.
4868
4869 @example
4870 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
4871 @end example
4872
4873 @end deffn
4874
4875 @deffn {Flash Driver} stmsmi
4876 @cindex STMicroelectronics Serial Memory Interface
4877 @cindex SMI
4878 @cindex stmsmi
4879 Some devices form STMicroelectronics (e.g. STR75x MCU family,
4880 SPEAr MPU family) include a proprietary
4881 ``Serial Memory Interface'' (SMI) controller able to drive external
4882 SPI flash devices.
4883 Depending on specific device and board configuration, up to 4 external
4884 flash devices can be connected.
4885
4886 SMI makes the flash content directly accessible in the CPU address
4887 space; each external device is mapped in a memory bank.
4888 CPU can directly read data, execute code and boot from SMI banks.
4889 Normal OpenOCD commands like @command{mdw} can be used to display
4890 the flash content.
4891
4892 The setup command only requires the @var{base} parameter in order
4893 to identify the memory bank.
4894 All other parameters are ignored. Additional information, like
4895 flash size, are detected automatically.
4896
4897 @example
4898 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
4899 @end example
4900
4901 @end deffn
4902
4903 @subsection Internal Flash (Microcontrollers)
4904
4905 @deffn {Flash Driver} aduc702x
4906 The ADUC702x analog microcontrollers from Analog Devices
4907 include internal flash and use ARM7TDMI cores.
4908 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
4909 The setup command only requires the @var{target} argument
4910 since all devices in this family have the same memory layout.
4911
4912 @example
4913 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
4914 @end example
4915 @end deffn
4916
4917 @anchor{at91sam3}
4918 @deffn {Flash Driver} at91sam3
4919 @cindex at91sam3
4920 All members of the AT91SAM3 microcontroller family from
4921 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
4922 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
4923 that the driver was orginaly developed and tested using the
4924 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
4925 the family was cribbed from the data sheet. @emph{Note to future
4926 readers/updaters: Please remove this worrysome comment after other
4927 chips are confirmed.}
4928
4929 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
4930 have one flash bank. In all cases the flash banks are at
4931 the following fixed locations:
4932
4933 @example
4934 # Flash bank 0 - all chips
4935 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
4936 # Flash bank 1 - only 256K chips
4937 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
4938 @end example
4939
4940 Internally, the AT91SAM3 flash memory is organized as follows.
4941 Unlike the AT91SAM7 chips, these are not used as parameters
4942 to the @command{flash bank} command:
4943
4944 @itemize
4945 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
4946 @item @emph{Bank Size:} 128K/64K Per flash bank
4947 @item @emph{Sectors:} 16 or 8 per bank
4948 @item @emph{SectorSize:} 8K Per Sector
4949 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
4950 @end itemize
4951
4952 The AT91SAM3 driver adds some additional commands:
4953
4954 @deffn Command {at91sam3 gpnvm}
4955 @deffnx Command {at91sam3 gpnvm clear} number
4956 @deffnx Command {at91sam3 gpnvm set} number
4957 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
4958 With no parameters, @command{show} or @command{show all},
4959 shows the status of all GPNVM bits.
4960 With @command{show} @var{number}, displays that bit.
4961
4962 With @command{set} @var{number} or @command{clear} @var{number},
4963 modifies that GPNVM bit.
4964 @end deffn
4965
4966 @deffn Command {at91sam3 info}
4967 This command attempts to display information about the AT91SAM3
4968 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
4969 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
4970 document id: doc6430A] and decodes the values. @emph{Second} it reads the
4971 various clock configuration registers and attempts to display how it
4972 believes the chip is configured. By default, the SLOWCLK is assumed to
4973 be 32768 Hz, see the command @command{at91sam3 slowclk}.
4974 @end deffn
4975
4976 @deffn Command {at91sam3 slowclk} [value]
4977 This command shows/sets the slow clock frequency used in the
4978 @command{at91sam3 info} command calculations above.
4979 @end deffn
4980 @end deffn
4981
4982 @deffn {Flash Driver} at91sam4
4983 @cindex at91sam4
4984 All members of the AT91SAM4 microcontroller family from
4985 Atmel include internal flash and use ARM's Cortex-M4 core.
4986 This driver uses the same cmd names/syntax as @xref{at91sam3}.
4987 @end deffn
4988
4989 @deffn {Flash Driver} at91sam7
4990 All members of the AT91SAM7 microcontroller family from Atmel include
4991 internal flash and use ARM7TDMI cores. The driver automatically
4992 recognizes a number of these chips using the chip identification
4993 register, and autoconfigures itself.
4994
4995 @example
4996 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
4997 @end example
4998
4999 For chips which are not recognized by the controller driver, you must
5000 provide additional parameters in the following order:
5001
5002 @itemize
5003 @item @var{chip_model} ... label used with @command{flash info}
5004 @item @var{banks}
5005 @item @var{sectors_per_bank}
5006 @item @var{pages_per_sector}
5007 @item @var{pages_size}
5008 @item @var{num_nvm_bits}
5009 @item @var{freq_khz} ... required if an external clock is provided,
5010 optional (but recommended) when the oscillator frequency is known
5011 @end itemize
5012
5013 It is recommended that you provide zeroes for all of those values
5014 except the clock frequency, so that everything except that frequency
5015 will be autoconfigured.
5016 Knowing the frequency helps ensure correct timings for flash access.
5017
5018 The flash controller handles erases automatically on a page (128/256 byte)
5019 basis, so explicit erase commands are not necessary for flash programming.
5020 However, there is an ``EraseAll`` command that can erase an entire flash
5021 plane (of up to 256KB), and it will be used automatically when you issue
5022 @command{flash erase_sector} or @command{flash erase_address} commands.
5023
5024 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
5025 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
5026 bit for the processor. Each processor has a number of such bits,
5027 used for controlling features such as brownout detection (so they
5028 are not truly general purpose).
5029 @quotation Note
5030 This assumes that the first flash bank (number 0) is associated with
5031 the appropriate at91sam7 target.
5032 @end quotation
5033 @end deffn
5034 @end deffn
5035
5036 @deffn {Flash Driver} avr