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target: less implicit inclusion of "command.h"
[openocd.git] / src / flash / at91sam3.c
1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
13 * GNU General public License for more details. *
14 * *
15 * You should have received a copy of the GNU General public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ****************************************************************************/
20
21 /* Some of the the lower level code was based on code supplied by
22 * ATMEL under this copyright. */
23
24 /* BEGIN ATMEL COPYRIGHT */
25 /* ----------------------------------------------------------------------------
26 * ATMEL Microcontroller Software Support
27 * ----------------------------------------------------------------------------
28 * Copyright (c) 2009, Atmel Corporation
29 *
30 * All rights reserved.
31 *
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions are met:
34 *
35 * - Redistributions of source code must retain the above copyright notice,
36 * this list of conditions and the disclaimer below.
37 *
38 * Atmel's name may not be used to endorse or promote products derived from
39 * this software without specific prior written permission.
40 *
41 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
43 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
44 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
47 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
48 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
49 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
50 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 * ----------------------------------------------------------------------------
52 */
53 /* END ATMEL COPYRIGHT */
54
55 #ifdef HAVE_CONFIG_H
56 #include "config.h"
57 #endif
58
59
60 #include <stdio.h>
61 #include <string.h>
62 #include <stddef.h>
63 #include "types.h"
64 #include "flash.h"
65 #include "target.h"
66 #include "membuf.h"
67 #include "at91sam3.h"
68 #include "time_support.h"
69
70 #define REG_NAME_WIDTH (12)
71
72
73 #define FLASH_BANK0_BASE 0x00080000
74 #define FLASH_BANK1_BASE 0x00100000
75
76 #define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor
77 #define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page
78 #define AT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page and Lock
79 #define AT91C_EFC_FCMD_EWP (0x3) // (EFC) Erase Page and Write Page
80 #define AT91C_EFC_FCMD_EWPL (0x4) // (EFC) Erase Page and Write Page then Lock
81 #define AT91C_EFC_FCMD_EA (0x5) // (EFC) Erase All
82 // cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2
83 // #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane?
84 // cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2
85 // #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages?
86 #define AT91C_EFC_FCMD_SLB (0x8) // (EFC) Set Lock Bit
87 #define AT91C_EFC_FCMD_CLB (0x9) // (EFC) Clear Lock Bit
88 #define AT91C_EFC_FCMD_GLB (0xA) // (EFC) Get Lock Bit
89 #define AT91C_EFC_FCMD_SFB (0xB) // (EFC) Set Fuse Bit
90 #define AT91C_EFC_FCMD_CFB (0xC) // (EFC) Clear Fuse Bit
91 #define AT91C_EFC_FCMD_GFB (0xD) // (EFC) Get Fuse Bit
92 #define AT91C_EFC_FCMD_STUI (0xE) // (EFC) Start Read Unique ID
93 #define AT91C_EFC_FCMD_SPUI (0xF) // (EFC) Stop Read Unique ID
94
95 #define offset_EFC_FMR 0
96 #define offset_EFC_FCR 4
97 #define offset_EFC_FSR 8
98 #define offset_EFC_FRR 12
99
100
101 static float
102 _tomhz(uint32_t freq_hz)
103 {
104 float f;
105
106 f = ((float)(freq_hz)) / 1000000.0;
107 return f;
108 }
109
110 // How the chip is configured.
111 struct sam3_cfg {
112 uint32_t unique_id[4];
113
114 uint32_t slow_freq;
115 uint32_t rc_freq;
116 uint32_t mainosc_freq;
117 uint32_t plla_freq;
118 uint32_t mclk_freq;
119 uint32_t cpu_freq;
120 uint32_t fclk_freq;
121 uint32_t pclk0_freq;
122 uint32_t pclk1_freq;
123 uint32_t pclk2_freq;
124
125
126 #define SAM3_CHIPID_CIDR (0x400E0740)
127 uint32_t CHIPID_CIDR;
128 #define SAM3_CHIPID_EXID (0x400E0744)
129 uint32_t CHIPID_EXID;
130
131 #define SAM3_SUPC_CR (0x400E1210)
132 uint32_t SUPC_CR;
133
134 #define SAM3_PMC_BASE (0x400E0400)
135 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
136 uint32_t PMC_SCSR;
137 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
138 uint32_t PMC_PCSR;
139 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
140 uint32_t CKGR_UCKR;
141 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
142 uint32_t CKGR_MOR;
143 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
144 uint32_t CKGR_MCFR;
145 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
146 uint32_t CKGR_PLLAR;
147 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
148 uint32_t PMC_MCKR;
149 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
150 uint32_t PMC_PCK0;
151 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
152 uint32_t PMC_PCK1;
153 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
154 uint32_t PMC_PCK2;
155 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
156 uint32_t PMC_SR;
157 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
158 uint32_t PMC_IMR;
159 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
160 uint32_t PMC_FSMR;
161 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
162 uint32_t PMC_FSPR;
163 };
164
165
166 struct sam3_bank_private {
167 int probed;
168 // DANGER: THERE ARE DRAGONS HERE..
169 // NOTE: If you add more 'ghost' pointers
170 // be aware that you must *manually* update
171 // these pointers in the function sam3_GetDetails()
172 // See the comment "Here there be dragons"
173
174 // so we can find the chip we belong to
175 struct sam3_chip *pChip;
176 // so we can find the orginal bank pointer
177 struct flash_bank *pBank;
178 unsigned bank_number;
179 uint32_t controller_address;
180 uint32_t base_address;
181 bool present;
182 unsigned size_bytes;
183 unsigned nsectors;
184 unsigned sector_size;
185 unsigned page_size;
186 };
187
188 struct sam3_chip_details {
189 // THERE ARE DRAGONS HERE..
190 // note: If you add pointers here
191 // becareful about them as they
192 // may need to be updated inside
193 // the function: "sam3_GetDetails()
194 // which copy/overwrites the
195 // 'runtime' copy of this structure
196 uint32_t chipid_cidr;
197 const char *name;
198
199 unsigned n_gpnvms;
200 #define SAM3_N_NVM_BITS 3
201 unsigned gpnvm[SAM3_N_NVM_BITS];
202 unsigned total_flash_size;
203 unsigned total_sram_size;
204 unsigned n_banks;
205 #define SAM3_MAX_FLASH_BANKS 2
206 // these are "initialized" from the global const data
207 struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
208 };
209
210
211 struct sam3_chip {
212 struct sam3_chip *next;
213 int probed;
214
215 // this is "initialized" from the global const structure
216 struct sam3_chip_details details;
217 struct target *target;
218 struct sam3_cfg cfg;
219
220 struct membuf *mbuf;
221 };
222
223
224 struct sam3_reg_list {
225 uint32_t address; size_t struct_offset; const char *name;
226 void (*explain_func)(struct sam3_chip *pInfo);
227 };
228
229
230 static struct sam3_chip *all_sam3_chips;
231
232 static struct sam3_chip *
233 get_current_sam3(struct command_context *cmd_ctx)
234 {
235 struct target *t;
236 static struct sam3_chip *p;
237
238 t = get_current_target(cmd_ctx);
239 if (!t) {
240 command_print(cmd_ctx, "No current target?");
241 return NULL;
242 }
243
244 p = all_sam3_chips;
245 if (!p) {
246 // this should not happen
247 // the command is not registered until the chip is created?
248 command_print(cmd_ctx, "No SAM3 chips exist?");
249 return NULL;
250 }
251
252 while (p) {
253 if (p->target == t) {
254 return p;
255 }
256 p = p->next;
257 }
258 command_print(cmd_ctx, "Cannot find SAM3 chip?");
259 return NULL;
260 }
261
262
263 // these are used to *initialize* the "pChip->details" structure.
264 static const struct sam3_chip_details all_sam3_details[] = {
265 {
266 .chipid_cidr = 0x28100960,
267 .name = "at91sam3u4e",
268 .total_flash_size = 256 * 1024,
269 .total_sram_size = 52 * 1024,
270 .n_gpnvms = 3,
271 .n_banks = 2,
272
273 // System boots at address 0x0
274 // gpnvm[1] = selects boot code
275 // if gpnvm[1] == 0
276 // boot is via "SAMBA" (rom)
277 // else
278 // boot is via FLASH
279 // Selection is via gpnvm[2]
280 // endif
281 //
282 // NOTE: banks 0 & 1 switch places
283 // if gpnvm[2] == 0
284 // Bank0 is the boot rom
285 // else
286 // Bank1 is the boot rom
287 // endif
288 // .bank[0] = {
289 {
290 {
291 .probed = 0,
292 .pChip = NULL,
293 .pBank = NULL,
294 .bank_number = 0,
295 .base_address = FLASH_BANK0_BASE,
296 .controller_address = 0x400e0800,
297 .present = 1,
298 .size_bytes = 128 * 1024,
299 .nsectors = 16,
300 .sector_size = 8192,
301 .page_size = 256,
302 },
303
304 // .bank[1] = {
305 {
306 .probed = 0,
307 .pChip = NULL,
308 .pBank = NULL,
309 .bank_number = 1,
310 .base_address = FLASH_BANK1_BASE,
311 .controller_address = 0x400e0a00,
312 .present = 1,
313 .size_bytes = 128 * 1024,
314 .nsectors = 16,
315 .sector_size = 8192,
316 .page_size = 256,
317 },
318 },
319 },
320
321 {
322 .chipid_cidr = 0x281a0760,
323 .name = "at91sam3u2e",
324 .total_flash_size = 128 * 1024,
325 .total_sram_size = 36 * 1024,
326 .n_gpnvms = 2,
327 .n_banks = 1,
328
329 // System boots at address 0x0
330 // gpnvm[1] = selects boot code
331 // if gpnvm[1] == 0
332 // boot is via "SAMBA" (rom)
333 // else
334 // boot is via FLASH
335 // Selection is via gpnvm[2]
336 // endif
337 // .bank[0] = {
338 {
339 {
340 .probed = 0,
341 .pChip = NULL,
342 .pBank = NULL,
343 .bank_number = 0,
344 .base_address = FLASH_BANK0_BASE,
345 .controller_address = 0x400e0800,
346 .present = 1,
347 .size_bytes = 128 * 1024,
348 .nsectors = 16,
349 .sector_size = 8192,
350 .page_size = 256,
351 },
352 // .bank[1] = {
353 {
354 .present = 0,
355 .probed = 0,
356 .bank_number = 1,
357 },
358 },
359 },
360 {
361 .chipid_cidr = 0x28190560,
362 .name = "at91sam3u1e",
363 .total_flash_size = 64 * 1024,
364 .total_sram_size = 20 * 1024,
365 .n_gpnvms = 2,
366 .n_banks = 1,
367
368 // System boots at address 0x0
369 // gpnvm[1] = selects boot code
370 // if gpnvm[1] == 0
371 // boot is via "SAMBA" (rom)
372 // else
373 // boot is via FLASH
374 // Selection is via gpnvm[2]
375 // endif
376 //
377
378 // .bank[0] = {
379 {
380 {
381 .probed = 0,
382 .pChip = NULL,
383 .pBank = NULL,
384 .bank_number = 0,
385 .base_address = FLASH_BANK0_BASE,
386 .controller_address = 0x400e0800,
387 .present = 1,
388 .size_bytes = 64 * 1024,
389 .nsectors = 8,
390 .sector_size = 8192,
391 .page_size = 256,
392 },
393
394 // .bank[1] = {
395 {
396 .present = 0,
397 .probed = 0,
398 .bank_number = 1,
399 },
400 },
401 },
402
403 {
404 .chipid_cidr = 0x28000960,
405 .name = "at91sam3u4c",
406 .total_flash_size = 256 * 1024,
407 .total_sram_size = 52 * 1024,
408 .n_gpnvms = 3,
409 .n_banks = 2,
410
411 // System boots at address 0x0
412 // gpnvm[1] = selects boot code
413 // if gpnvm[1] == 0
414 // boot is via "SAMBA" (rom)
415 // else
416 // boot is via FLASH
417 // Selection is via gpnvm[2]
418 // endif
419 //
420 // NOTE: banks 0 & 1 switch places
421 // if gpnvm[2] == 0
422 // Bank0 is the boot rom
423 // else
424 // Bank1 is the boot rom
425 // endif
426 {
427 {
428 // .bank[0] = {
429 .probed = 0,
430 .pChip = NULL,
431 .pBank = NULL,
432 .bank_number = 0,
433 .base_address = FLASH_BANK0_BASE,
434 .controller_address = 0x400e0800,
435 .present = 1,
436 .size_bytes = 128 * 1024,
437 .nsectors = 16,
438 .sector_size = 8192,
439 .page_size = 256,
440 },
441 // .bank[1] = {
442 {
443 .probed = 0,
444 .pChip = NULL,
445 .pBank = NULL,
446 .bank_number = 1,
447 .base_address = FLASH_BANK1_BASE,
448 .controller_address = 0x400e0a00,
449 .present = 1,
450 .size_bytes = 128 * 1024,
451 .nsectors = 16,
452 .sector_size = 8192,
453 .page_size = 256,
454 },
455 },
456 },
457
458 {
459 .chipid_cidr = 0x280a0760,
460 .name = "at91sam3u2c",
461 .total_flash_size = 128 * 1024,
462 .total_sram_size = 36 * 1024,
463 .n_gpnvms = 2,
464 .n_banks = 1,
465
466 // System boots at address 0x0
467 // gpnvm[1] = selects boot code
468 // if gpnvm[1] == 0
469 // boot is via "SAMBA" (rom)
470 // else
471 // boot is via FLASH
472 // Selection is via gpnvm[2]
473 // endif
474 {
475 // .bank[0] = {
476 {
477 .probed = 0,
478 .pChip = NULL,
479 .pBank = NULL,
480 .bank_number = 0,
481 .base_address = FLASH_BANK0_BASE,
482 .controller_address = 0x400e0800,
483 .present = 1,
484 .size_bytes = 128 * 1024,
485 .nsectors = 16,
486 .sector_size = 8192,
487 .page_size = 256,
488 },
489 // .bank[1] = {
490 {
491 .present = 0,
492 .probed = 0,
493 .bank_number = 1,
494 },
495 },
496 },
497 {
498 .chipid_cidr = 0x28090560,
499 .name = "at91sam3u1c",
500 .total_flash_size = 64 * 1024,
501 .total_sram_size = 20 * 1024,
502 .n_gpnvms = 2,
503 .n_banks = 1,
504
505 // System boots at address 0x0
506 // gpnvm[1] = selects boot code
507 // if gpnvm[1] == 0
508 // boot is via "SAMBA" (rom)
509 // else
510 // boot is via FLASH
511 // Selection is via gpnvm[2]
512 // endif
513 //
514
515 {
516 // .bank[0] = {
517 {
518 .probed = 0,
519 .pChip = NULL,
520 .pBank = NULL,
521 .bank_number = 0,
522 .base_address = FLASH_BANK0_BASE,
523 .controller_address = 0x400e0800,
524 .present = 1,
525 .size_bytes = 64 * 1024,
526 .nsectors = 8,
527 .sector_size = 8192,
528 .page_size = 256,
529 },
530 // .bank[1] = {
531 {
532 .present = 0,
533 .probed = 0,
534 .bank_number = 1,
535
536 },
537 },
538 },
539
540 // terminate
541 {
542 .chipid_cidr = 0,
543 .name = NULL,
544 }
545 };
546
547 /* Globals above */
548 /***********************************************************************
549 **********************************************************************
550 **********************************************************************
551 **********************************************************************
552 **********************************************************************
553 **********************************************************************/
554 /* *ATMEL* style code - from the SAM3 driver code */
555
556 /**
557 * Get the current status of the EEFC and
558 * the value of some status bits (LOCKE, PROGE).
559 * @param pPrivate - info about the bank
560 * @param v - result goes here
561 */
562 static int
563 EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
564 {
565 int r;
566 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address + offset_EFC_FSR, v);
567 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
568 (unsigned int)(*v),
569 ((unsigned int)((*v >> 2) & 1)),
570 ((unsigned int)((*v >> 1) & 1)),
571 ((unsigned int)((*v >> 0) & 1)));
572
573 return r;
574 }
575
576 /**
577 * Get the result of the last executed command.
578 * @param pPrivate - info about the bank
579 * @param v - result goes here
580 */
581 static int
582 EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
583 {
584 int r;
585 uint32_t rv;
586 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address + offset_EFC_FRR, &rv);
587 if (v) {
588 *v = rv;
589 }
590 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
591 return r;
592 }
593
594 static int
595 EFC_StartCommand(struct sam3_bank_private *pPrivate,
596 unsigned command, unsigned argument)
597 {
598 uint32_t n,v;
599 int r;
600 int retry;
601
602 retry = 0;
603 do_retry:
604
605 // Check command & argument
606 switch (command) {
607
608 case AT91C_EFC_FCMD_WP:
609 case AT91C_EFC_FCMD_WPL:
610 case AT91C_EFC_FCMD_EWP:
611 case AT91C_EFC_FCMD_EWPL:
612 // case AT91C_EFC_FCMD_EPL:
613 // case AT91C_EFC_FCMD_EPA:
614 case AT91C_EFC_FCMD_SLB:
615 case AT91C_EFC_FCMD_CLB:
616 n = (pPrivate->size_bytes / pPrivate->page_size);
617 if (argument >= n) {
618 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
619 }
620 break;
621
622 case AT91C_EFC_FCMD_SFB:
623 case AT91C_EFC_FCMD_CFB:
624 if (argument >= pPrivate->pChip->details.n_gpnvms) {
625 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
626 pPrivate->pChip->details.n_gpnvms);
627 }
628 break;
629
630 case AT91C_EFC_FCMD_GETD:
631 case AT91C_EFC_FCMD_EA:
632 case AT91C_EFC_FCMD_GLB:
633 case AT91C_EFC_FCMD_GFB:
634 case AT91C_EFC_FCMD_STUI:
635 case AT91C_EFC_FCMD_SPUI:
636 if (argument != 0) {
637 LOG_ERROR("Argument is meaningless for cmd: %d", command);
638 }
639 break;
640 default:
641 LOG_ERROR("Unknown command %d", command);
642 break;
643 }
644
645 if (command == AT91C_EFC_FCMD_SPUI) {
646 // this is a very special situation.
647 // Situation (1) - error/retry - see below
648 // And we are being called recursively
649 // Situation (2) - normal, finished reading unique id
650 } else {
651 // it should be "ready"
652 EFC_GetStatus(pPrivate, &v);
653 if (v & 1) {
654 // then it is ready
655 // we go on
656 } else {
657 if (retry) {
658 // we have done this before
659 // the controller is not responding.
660 LOG_ERROR("flash controller(%d) is not ready! Error", pPrivate->bank_number);
661 return ERROR_FAIL;
662 } else {
663 retry++;
664 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
665 pPrivate->bank_number);
666 // we do that by issuing the *STOP* command
667 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
668 // above is recursive, and further recursion is blocked by
669 // if (command == AT91C_EFC_FCMD_SPUI) above
670 goto do_retry;
671 }
672 }
673 }
674
675 v = (0x5A << 24) | (argument << 8) | command;
676 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
677 r = target_write_u32(pPrivate->pBank->target,
678 pPrivate->controller_address + offset_EFC_FCR,
679 v);
680 if (r != ERROR_OK) {
681 LOG_DEBUG("Error Write failed");
682 }
683 return r;
684 }
685
686 /**
687 * Performs the given command and wait until its completion (or an error).
688 * @param pPrivate - info about the bank
689 * @param command - Command to perform.
690 * @param argument - Optional command argument.
691 * @param status - put command status bits here
692 */
693 static int
694 EFC_PerformCommand(struct sam3_bank_private *pPrivate,
695 unsigned command,
696 unsigned argument,
697 uint32_t *status)
698 {
699
700 int r;
701 uint32_t v;
702 long long ms_now, ms_end;
703
704 // default
705 if (status) {
706 *status = 0;
707 }
708
709 r = EFC_StartCommand(pPrivate, command, argument);
710 if (r != ERROR_OK) {
711 return r;
712 }
713
714 ms_end = 500 + timeval_ms();
715
716
717 do {
718 r = EFC_GetStatus(pPrivate, &v);
719 if (r != ERROR_OK) {
720 return r;
721 }
722 ms_now = timeval_ms();
723 if (ms_now > ms_end) {
724 // error
725 LOG_ERROR("Command timeout");
726 return ERROR_FAIL;
727 }
728 }
729 while ((v & 1) == 0)
730 ;
731
732 // error bits..
733 if (status) {
734 *status = (v & 0x6);
735 }
736 return ERROR_OK;
737
738 }
739
740
741
742
743
744 /**
745 * Read the unique ID.
746 * @param pPrivate - info about the bank
747 * The unique ID is stored in the 'pPrivate' structure.
748 */
749 static int
750 FLASHD_ReadUniqueID (struct sam3_bank_private *pPrivate)
751 {
752 int r;
753 uint32_t v;
754 int x;
755 // assume 0
756 pPrivate->pChip->cfg.unique_id[0] = 0;
757 pPrivate->pChip->cfg.unique_id[1] = 0;
758 pPrivate->pChip->cfg.unique_id[2] = 0;
759 pPrivate->pChip->cfg.unique_id[3] = 0;
760
761 LOG_DEBUG("Begin");
762 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
763 if (r < 0) {
764 return r;
765 }
766
767 for (x = 0 ; x < 4 ; x++) {
768 r = target_read_u32(pPrivate->pChip->target,
769 pPrivate->pBank->base + (x * 4),
770 &v);
771 if (r < 0) {
772 return r;
773 }
774 pPrivate->pChip->cfg.unique_id[x] = v;
775 }
776
777 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
778 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
779 r,
780 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
781 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
782 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
783 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
784 return r;
785
786 }
787
788 /**
789 * Erases the entire flash.
790 * @param pPrivate - the info about the bank.
791 */
792 static int
793 FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
794 {
795 LOG_DEBUG("Here");
796 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
797 }
798
799
800
801 /**
802 * Gets current GPNVM state.
803 * @param pPrivate - info about the bank.
804 * @param gpnvm - GPNVM bit index.
805 * @param puthere - result stored here.
806 */
807 //------------------------------------------------------------------------------
808 static int
809 FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
810 {
811 uint32_t v;
812 int r;
813
814 LOG_DEBUG("Here");
815 if (pPrivate->bank_number != 0) {
816 LOG_ERROR("GPNVM only works with Bank0");
817 return ERROR_FAIL;
818 }
819
820 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
821 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
822 gpnvm,pPrivate->pChip->details.n_gpnvms);
823 return ERROR_FAIL;
824 }
825
826 // Get GPNVMs status
827 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
828 if (r != ERROR_OK) {
829 LOG_ERROR("Failed");
830 return r;
831 }
832
833 r = EFC_GetResult(pPrivate, &v);
834
835 if (puthere) {
836 // Check if GPNVM is set
837 // get the bit and make it a 0/1
838 *puthere = (v >> gpnvm) & 1;
839 }
840
841 return r;
842 }
843
844
845
846
847 /**
848 * Clears the selected GPNVM bit.
849 * @param pPrivate info about the bank
850 * @param gpnvm GPNVM index.
851 * @returns 0 if successful; otherwise returns an error code.
852 */
853 static int
854 FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
855 {
856 int r;
857 unsigned v;
858
859 LOG_DEBUG("Here");
860 if (pPrivate->bank_number != 0) {
861 LOG_ERROR("GPNVM only works with Bank0");
862 return ERROR_FAIL;
863 }
864
865 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
866 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
867 gpnvm,pPrivate->pChip->details.n_gpnvms);
868 return ERROR_FAIL;
869 }
870
871 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
872 if (r != ERROR_OK) {
873 LOG_DEBUG("Failed: %d",r);
874 return r;
875 }
876 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
877 LOG_DEBUG("End: %d",r);
878 return r;
879 }
880
881
882
883 /**
884 * Sets the selected GPNVM bit.
885 * @param pPrivate info about the bank
886 * @param gpnvm GPNVM index.
887 */
888 static int
889 FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
890 {
891 int r;
892 unsigned v;
893
894 if (pPrivate->bank_number != 0) {
895 LOG_ERROR("GPNVM only works with Bank0");
896 return ERROR_FAIL;
897 }
898
899 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
900 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
901 gpnvm,pPrivate->pChip->details.n_gpnvms);
902 return ERROR_FAIL;
903 }
904
905 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
906 if (r != ERROR_OK) {
907 return r;
908 }
909 if (v) {
910 // already set
911 r = ERROR_OK;
912 } else {
913 // set it
914 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
915 }
916 return r;
917 }
918
919
920 /**
921 * Returns a bit field (at most 64) of locked regions within a page.
922 * @param pPrivate info about the bank
923 * @param v where to store locked bits
924 */
925 static int
926 FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
927 {
928 int r;
929 LOG_DEBUG("Here");
930 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
931 if (r == ERROR_OK) {
932 r = EFC_GetResult(pPrivate, v);
933 }
934 LOG_DEBUG("End: %d",r);
935 return r;
936 }
937
938
939 /**
940 * Unlocks all the regions in the given address range.
941 * @param pPrivate info about the bank
942 * @param start_sector first sector to unlock
943 * @param end_sector last (inclusive) to unlock
944 */
945
946 static int
947 FLASHD_Unlock(struct sam3_bank_private *pPrivate,
948 unsigned start_sector,
949 unsigned end_sector)
950 {
951 int r;
952 uint32_t status;
953 uint32_t pg;
954 uint32_t pages_per_sector;
955
956 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
957
958 /* Unlock all pages */
959 while (start_sector <= end_sector) {
960 pg = start_sector * pages_per_sector;
961
962 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
963 if (r != ERROR_OK) {
964 return r;
965 }
966 start_sector++;
967 }
968
969 return ERROR_OK;
970 }
971
972
973 /**
974 * Locks regions
975 * @param pPrivate - info about the bank
976 * @param start_sector - first sector to lock
977 * @param end_sector - last sector (inclusive) to lock
978 */
979 static int
980 FLASHD_Lock(struct sam3_bank_private *pPrivate,
981 unsigned start_sector,
982 unsigned end_sector)
983 {
984 uint32_t status;
985 uint32_t pg;
986 uint32_t pages_per_sector;
987 int r;
988
989 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
990
991 /* Lock all pages */
992 while (start_sector <= end_sector) {
993 pg = start_sector * pages_per_sector;
994
995 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
996 if (r != ERROR_OK) {
997 return r;
998 }
999 start_sector++;
1000 }
1001 return ERROR_OK;
1002 }
1003
1004
1005 /****** END SAM3 CODE ********/
1006
1007 /* begin helpful debug code */
1008
1009 static void
1010 sam3_sprintf(struct sam3_chip *pChip , const char *fmt, ...)
1011 {
1012 va_list ap;
1013 va_start(ap,fmt);
1014 if (pChip->mbuf == NULL) {
1015 return;
1016 }
1017
1018 membuf_vsprintf(pChip->mbuf, fmt, ap);
1019 va_end(ap);
1020 }
1021
1022 // print the fieldname, the field value, in dec & hex, and return field value
1023 static uint32_t
1024 sam3_reg_fieldname(struct sam3_chip *pChip,
1025 const char *regname,
1026 uint32_t value,
1027 unsigned shift,
1028 unsigned width)
1029 {
1030 uint32_t v;
1031 int hwidth, dwidth;
1032
1033
1034 // extract the field
1035 v = value >> shift;
1036 v = v & ((1 << width)-1);
1037 if (width <= 16) {
1038 hwidth = 4;
1039 dwidth = 5;
1040 } else {
1041 hwidth = 8;
1042 dwidth = 12;
1043 }
1044
1045 // show the basics
1046 sam3_sprintf(pChip, "\t%*s: %*d [0x%0*x] ",
1047 REG_NAME_WIDTH, regname,
1048 dwidth, v,
1049 hwidth, v);
1050 return v;
1051 }
1052
1053
1054 static const char _unknown[] = "unknown";
1055 static const char * const eproc_names[] = {
1056 _unknown, // 0
1057 "arm946es", // 1
1058 "arm7tdmi", // 2
1059 "cortex-m3", // 3
1060 "arm920t", // 4
1061 "arm926ejs", // 5
1062 _unknown, // 6
1063 _unknown, // 7
1064 _unknown, // 8
1065 _unknown, // 9
1066 _unknown, // 10
1067 _unknown, // 11
1068 _unknown, // 12
1069 _unknown, // 13
1070 _unknown, // 14
1071 _unknown, // 15
1072 };
1073
1074 #define nvpsize2 nvpsize // these two tables are identical
1075 static const char * const nvpsize[] = {
1076 "none", // 0
1077 "8K bytes", // 1
1078 "16K bytes", // 2
1079 "32K bytes", // 3
1080 _unknown, // 4
1081 "64K bytes", // 5
1082 _unknown, // 6
1083 "128K bytes", // 7
1084 _unknown, // 8
1085 "256K bytes", // 9
1086 "512K bytes", // 10
1087 _unknown, // 11
1088 "1024K bytes", // 12
1089 _unknown, // 13
1090 "2048K bytes", // 14
1091 _unknown, // 15
1092 };
1093
1094
1095 static const char * const sramsize[] = {
1096 "48K Bytes", // 0
1097 "1K Bytes", // 1
1098 "2K Bytes", // 2
1099 "6K Bytes", // 3
1100 "112K Bytes", // 4
1101 "4K Bytes", // 5
1102 "80K Bytes", // 6
1103 "160K Bytes", // 7
1104 "8K Bytes", // 8
1105 "16K Bytes", // 9
1106 "32K Bytes", // 10
1107 "64K Bytes", // 11
1108 "128K Bytes", // 12
1109 "256K Bytes", // 13
1110 "96K Bytes", // 14
1111 "512K Bytes", // 15
1112
1113 };
1114
1115 static const struct archnames { unsigned value; const char *name; } archnames[] = {
1116 { 0x19, "AT91SAM9xx Series" },
1117 { 0x29, "AT91SAM9XExx Series" },
1118 { 0x34, "AT91x34 Series" },
1119 { 0x37, "CAP7 Series" },
1120 { 0x39, "CAP9 Series" },
1121 { 0x3B, "CAP11 Series" },
1122 { 0x40, "AT91x40 Series" },
1123 { 0x42, "AT91x42 Series" },
1124 { 0x55, "AT91x55 Series" },
1125 { 0x60, "AT91SAM7Axx Series" },
1126 { 0x61, "AT91SAM7AQxx Series" },
1127 { 0x63, "AT91x63 Series" },
1128 { 0x70, "AT91SAM7Sxx Series" },
1129 { 0x71, "AT91SAM7XCxx Series" },
1130 { 0x72, "AT91SAM7SExx Series" },
1131 { 0x73, "AT91SAM7Lxx Series" },
1132 { 0x75, "AT91SAM7Xxx Series" },
1133 { 0x76, "AT91SAM7SLxx Series" },
1134 { 0x80, "ATSAM3UxC Series (100-pin version)" },
1135 { 0x81, "ATSAM3UxE Series (144-pin version)" },
1136 { 0x83, "ATSAM3AxC Series (100-pin version)" },
1137 { 0x84, "ATSAM3XxC Series (100-pin version)" },
1138 { 0x85, "ATSAM3XxE Series (144-pin version)" },
1139 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
1140 { 0x88, "ATSAM3SxA Series (48-pin version)" },
1141 { 0x89, "ATSAM3SxB Series (64-pin version)" },
1142 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
1143 { 0x92, "AT91x92 Series" },
1144 { 0xF0, "AT75Cxx Series" },
1145 { -1, NULL },
1146
1147 };
1148
1149 static const char * const nvptype[] = {
1150 "rom", // 0
1151 "romless or onchip flash", // 1
1152 "embedded flash memory", // 2
1153 "rom(nvpsiz) + embedded flash (nvpsiz2)", //3
1154 "sram emulating flash", // 4
1155 _unknown, // 5
1156 _unknown, // 6
1157 _unknown, // 7
1158
1159 };
1160
1161 static const char *_yes_or_no(uint32_t v)
1162 {
1163 if (v) {
1164 return "YES";
1165 } else {
1166 return "NO";
1167 }
1168 }
1169
1170 static const char * const _rc_freq[] = {
1171 "4 MHz", "8 MHz", "12 MHz", "reserved"
1172 };
1173
1174 static void
1175 sam3_explain_ckgr_mor(struct sam3_chip *pChip)
1176 {
1177 uint32_t v;
1178 uint32_t rcen;
1179
1180 v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
1181 sam3_sprintf(pChip, "(main xtal enabled: %s)\n",
1182 _yes_or_no(v));
1183 v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
1184 sam3_sprintf(pChip, "(main osc bypass: %s)\n",
1185 _yes_or_no(v));
1186 rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 2, 1);
1187 sam3_sprintf(pChip, "(onchip RC-OSC enabled: %s)\n",
1188 _yes_or_no(rcen));
1189 v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
1190 sam3_sprintf(pChip, "(onchip RC-OSC freq: %s)\n",
1191 _rc_freq[v]);
1192
1193 pChip->cfg.rc_freq = 0;
1194 if (rcen) {
1195 switch (v) {
1196 default:
1197 pChip->cfg.rc_freq = 0;
1198 case 0:
1199 pChip->cfg.rc_freq = 4 * 1000 * 1000;
1200 break;
1201 case 1:
1202 pChip->cfg.rc_freq = 8 * 1000 * 1000;
1203 break;
1204 case 2:
1205 pChip->cfg.rc_freq = 12* 1000 * 1000;
1206 break;
1207 }
1208 }
1209
1210 v = sam3_reg_fieldname(pChip,"MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
1211 sam3_sprintf(pChip, "(startup clks, time= %f uSecs)\n",
1212 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
1213 v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
1214 sam3_sprintf(pChip, "(mainosc source: %s)\n",
1215 v ? "external xtal" : "internal RC");
1216
1217 v = sam3_reg_fieldname(pChip,"CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
1218 sam3_sprintf(pChip, "(clock failure enabled: %s)\n",
1219 _yes_or_no(v));
1220 }
1221
1222
1223
1224 static void
1225 sam3_explain_chipid_cidr(struct sam3_chip *pChip)
1226 {
1227 int x;
1228 uint32_t v;
1229 const char *cp;
1230
1231 sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
1232 sam3_sprintf(pChip,"\n");
1233
1234 v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
1235 sam3_sprintf(pChip, "%s\n", eproc_names[v]);
1236
1237 v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
1238 sam3_sprintf(pChip, "%s\n", nvpsize[v]);
1239
1240 v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
1241 sam3_sprintf(pChip, "%s\n", nvpsize2[v]);
1242
1243 v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16,4);
1244 sam3_sprintf(pChip, "%s\n", sramsize[ v ]);
1245
1246 v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
1247 cp = _unknown;
1248 for (x = 0 ; archnames[x].name ; x++) {
1249 if (v == archnames[x].value) {
1250 cp = archnames[x].name;
1251 break;
1252 }
1253 }
1254
1255 sam3_sprintf(pChip, "%s\n", cp);
1256
1257 v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
1258 sam3_sprintf(pChip, "%s\n", nvptype[ v ]);
1259
1260 v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
1261 sam3_sprintf(pChip, "(exists: %s)\n", _yes_or_no(v));
1262 }
1263
1264 static void
1265 sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
1266 {
1267 uint32_t v;
1268
1269
1270 v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
1271 sam3_sprintf(pChip, "(main ready: %s)\n", _yes_or_no(v));
1272
1273 v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
1274
1275 v = (v * pChip->cfg.slow_freq) / 16;
1276 pChip->cfg.mainosc_freq = v;
1277
1278 sam3_sprintf(pChip, "(%3.03f Mhz (%d.%03dkhz slowclk)\n",
1279 _tomhz(v),
1280 pChip->cfg.slow_freq / 1000,
1281 pChip->cfg.slow_freq % 1000);
1282
1283 }
1284
1285 static void
1286 sam3_explain_ckgr_plla(struct sam3_chip *pChip)
1287 {
1288 uint32_t mula,diva;
1289
1290 diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
1291 sam3_sprintf(pChip,"\n");
1292 mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
1293 sam3_sprintf(pChip,"\n");
1294 pChip->cfg.plla_freq = 0;
1295 if (mula == 0) {
1296 sam3_sprintf(pChip,"\tPLLA Freq: (Disabled,mula = 0)\n");
1297 } else if (diva == 0) {
1298 sam3_sprintf(pChip,"\tPLLA Freq: (Disabled,diva = 0)\n");
1299 } else if (diva == 1) {
1300 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
1301 sam3_sprintf(pChip,"\tPLLA Freq: %3.03f MHz\n",
1302 _tomhz(pChip->cfg.plla_freq));
1303 }
1304 }
1305
1306
1307 static void
1308 sam3_explain_mckr(struct sam3_chip *pChip)
1309 {
1310 uint32_t css, pres, fin = 0;
1311 int pdiv = 0;
1312 const char *cp = NULL;
1313
1314 css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
1315 switch (css & 3) {
1316 case 0:
1317 fin = pChip->cfg.slow_freq;
1318 cp = "slowclk";
1319 break;
1320 case 1:
1321 fin = pChip->cfg.mainosc_freq;
1322 cp = "mainosc";
1323 break;
1324 case 2:
1325 fin = pChip->cfg.plla_freq;
1326 cp = "plla";
1327 break;
1328 case 3:
1329 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
1330 fin = 480 * 1000 * 1000;
1331 cp = "upll";
1332 } else {
1333 fin = 0;
1334 cp = "upll (*ERROR* UPLL is disabled)";
1335 }
1336 break;
1337 default:
1338 assert(0);
1339 break;
1340 }
1341
1342 sam3_sprintf(pChip, "%s (%3.03f Mhz)\n",
1343 cp,
1344 _tomhz(fin));
1345 pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
1346 switch (pres & 0x07) {
1347 case 0:
1348 pdiv = 1;
1349 cp = "selected clock";
1350 case 1:
1351 pdiv = 2;
1352 cp = "clock/2";
1353 break;
1354 case 2:
1355 pdiv = 4;
1356 cp = "clock/4";
1357 break;
1358 case 3:
1359 pdiv = 8;
1360 cp = "clock/8";
1361 break;
1362 case 4:
1363 pdiv = 16;
1364 cp = "clock/16";
1365 break;
1366 case 5:
1367 pdiv = 32;
1368 cp = "clock/32";
1369 break;
1370 case 6:
1371 pdiv = 64;
1372 cp = "clock/64";
1373 break;
1374 case 7:
1375 pdiv = 6;
1376 cp = "clock/6";
1377 break;
1378 default:
1379 assert(0);
1380 break;
1381 }
1382 sam3_sprintf(pChip, "(%s)\n", cp);
1383 fin = fin / pdiv;
1384 // sam3 has a *SINGLE* clock -
1385 // other at91 series parts have divisors for these.
1386 pChip->cfg.cpu_freq = fin;
1387 pChip->cfg.mclk_freq = fin;
1388 pChip->cfg.fclk_freq = fin;
1389 sam3_sprintf(pChip, "\t\tResult CPU Freq: %3.03f\n",
1390 _tomhz(fin));
1391 }
1392
1393 #if 0
1394 static struct sam3_chip *
1395 target2sam3(struct target *pTarget)
1396 {
1397 struct sam3_chip *pChip;
1398
1399 if (pTarget == NULL) {
1400 return NULL;
1401 }
1402
1403 pChip = all_sam3_chips;
1404 while (pChip) {
1405 if (pChip->target == pTarget) {
1406 break; // return below
1407 } else {
1408 pChip = pChip->next;
1409 }
1410 }
1411 return pChip;
1412 }
1413 #endif
1414
1415 static uint32_t *
1416 sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
1417 {
1418 // this function exists to help
1419 // keep funky offsetof() errors
1420 // and casting from causing bugs
1421
1422 // By using prototypes - we can detect what would
1423 // be casting errors.
1424
1425 return ((uint32_t *)(((char *)(pCfg)) + pList->struct_offset));
1426 }
1427
1428
1429 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof(struct sam3_cfg, NAME), #NAME, FUNC }
1430 static const struct sam3_reg_list sam3_all_regs[] = {
1431 SAM3_ENTRY(CKGR_MOR , sam3_explain_ckgr_mor),
1432 SAM3_ENTRY(CKGR_MCFR , sam3_explain_ckgr_mcfr),
1433 SAM3_ENTRY(CKGR_PLLAR , sam3_explain_ckgr_plla),
1434 SAM3_ENTRY(CKGR_UCKR , NULL),
1435 SAM3_ENTRY(PMC_FSMR , NULL),
1436 SAM3_ENTRY(PMC_FSPR , NULL),
1437 SAM3_ENTRY(PMC_IMR , NULL),
1438 SAM3_ENTRY(PMC_MCKR , sam3_explain_mckr),
1439 SAM3_ENTRY(PMC_PCK0 , NULL),
1440 SAM3_ENTRY(PMC_PCK1 , NULL),
1441 SAM3_ENTRY(PMC_PCK2 , NULL),
1442 SAM3_ENTRY(PMC_PCSR , NULL),
1443 SAM3_ENTRY(PMC_SCSR , NULL),
1444 SAM3_ENTRY(PMC_SR , NULL),
1445 SAM3_ENTRY(CHIPID_CIDR , sam3_explain_chipid_cidr),
1446 SAM3_ENTRY(CHIPID_EXID , NULL),
1447 SAM3_ENTRY(SUPC_CR, NULL),
1448
1449 // TERMINATE THE LIST
1450 { .name = NULL }
1451 };
1452 #undef SAM3_ENTRY
1453
1454
1455
1456
1457 static struct sam3_bank_private *
1458 get_sam3_bank_private(struct flash_bank *bank)
1459 {
1460 return (struct sam3_bank_private *)(bank->driver_priv);
1461 }
1462
1463 /**
1464 * Given a pointer to where it goes in the structure,
1465 * determine the register name, address from the all registers table.
1466 */
1467 static const struct sam3_reg_list *
1468 sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
1469 {
1470 const struct sam3_reg_list *pReg;
1471
1472 pReg = &(sam3_all_regs[0]);
1473 while (pReg->name) {
1474 uint32_t *pPossible;
1475
1476 // calculate where this one go..
1477 // it is "possibly" this register.
1478
1479 pPossible = ((uint32_t *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
1480
1481 // well? Is it this register
1482 if (pPossible == goes_here) {
1483 // Jump for joy!
1484 return pReg;
1485 }
1486
1487 // next...
1488 pReg++;
1489 }
1490 // This is *TOTAL*PANIC* - we are totally screwed.
1491 LOG_ERROR("INVALID SAM3 REGISTER");
1492 return NULL;
1493 }
1494
1495
1496 static int
1497 sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
1498 {
1499 const struct sam3_reg_list *pReg;
1500 int r;
1501
1502 pReg = sam3_GetReg(pChip, goes_here);
1503 if (!pReg) {
1504 return ERROR_FAIL;
1505 }
1506
1507 r = target_read_u32(pChip->target, pReg->address, goes_here);
1508 if (r != ERROR_OK) {
1509 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d\n",
1510 pReg->name, (unsigned)(pReg->address), r);
1511 }
1512 return r;
1513 }
1514
1515
1516
1517 static int
1518 sam3_ReadAllRegs(struct sam3_chip *pChip)
1519 {
1520 int r;
1521 const struct sam3_reg_list *pReg;
1522
1523 pReg = &(sam3_all_regs[0]);
1524 while (pReg->name) {
1525 r = sam3_ReadThisReg(pChip,
1526 sam3_get_reg_ptr(&(pChip->cfg), pReg));
1527 if (r != ERROR_OK) {
1528 LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d\n",
1529 pReg->name, ((unsigned)(pReg->address)), r);
1530 return r;
1531 }
1532
1533 pReg++;
1534 }
1535
1536 return ERROR_OK;
1537 }
1538
1539
1540 static int
1541 sam3_GetInfo(struct sam3_chip *pChip)
1542 {
1543 const struct sam3_reg_list *pReg;
1544 uint32_t regval;
1545
1546 membuf_reset(pChip->mbuf);
1547
1548
1549 pReg = &(sam3_all_regs[0]);
1550 while (pReg->name) {
1551 // display all regs
1552 LOG_DEBUG("Start: %s", pReg->name);
1553 regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
1554 sam3_sprintf(pChip, "%*s: [0x%08x] -> 0x%08x\n",
1555 REG_NAME_WIDTH,
1556 pReg->name,
1557 pReg->address,
1558 regval);
1559 if (pReg->explain_func) {
1560 (*(pReg->explain_func))(pChip);
1561 }
1562 LOG_DEBUG("End: %s", pReg->name);
1563 pReg++;
1564 }
1565 sam3_sprintf(pChip," rc-osc: %3.03f MHz\n", _tomhz(pChip->cfg.rc_freq));
1566 sam3_sprintf(pChip," mainosc: %3.03f MHz\n", _tomhz(pChip->cfg.mainosc_freq));
1567 sam3_sprintf(pChip," plla: %3.03f MHz\n", _tomhz(pChip->cfg.plla_freq));
1568 sam3_sprintf(pChip," cpu-freq: %3.03f MHz\n", _tomhz(pChip->cfg.cpu_freq));
1569 sam3_sprintf(pChip,"mclk-freq: %3.03f MHz\n", _tomhz(pChip->cfg.mclk_freq));
1570
1571
1572 sam3_sprintf(pChip, " UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1573 pChip->cfg.unique_id[0],
1574 pChip->cfg.unique_id[1],
1575 pChip->cfg.unique_id[2],
1576 pChip->cfg.unique_id[3]);
1577
1578
1579 return ERROR_OK;
1580 }
1581
1582
1583 static int
1584 sam3_erase_check(struct flash_bank *bank)
1585 {
1586 int x;
1587
1588 LOG_DEBUG("Here");
1589 if (bank->target->state != TARGET_HALTED) {
1590 LOG_ERROR("Target not halted");
1591 return ERROR_TARGET_NOT_HALTED;
1592 }
1593 if (0 == bank->num_sectors) {
1594 LOG_ERROR("Target: not supported/not probed\n");
1595 return ERROR_FAIL;
1596 }
1597
1598 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
1599 for (x = 0 ; x < bank->num_sectors ; x++) {
1600 bank->sectors[x].is_erased = 1;
1601 }
1602
1603 LOG_DEBUG("Done");
1604 return ERROR_OK;
1605 }
1606
1607 static int
1608 sam3_protect_check(struct flash_bank *bank)
1609 {
1610 int r;
1611 uint32_t v=0;
1612 unsigned x;
1613 struct sam3_bank_private *pPrivate;
1614
1615 LOG_DEBUG("Begin");
1616 if (bank->target->state != TARGET_HALTED) {
1617 LOG_ERROR("Target not halted");
1618 return ERROR_TARGET_NOT_HALTED;
1619 }
1620
1621 pPrivate = get_sam3_bank_private(bank);
1622 if (!pPrivate) {
1623 LOG_ERROR("no private for this bank?");
1624 return ERROR_FAIL;
1625 }
1626 if (!(pPrivate->probed)) {
1627 return ERROR_FLASH_BANK_NOT_PROBED;
1628 }
1629
1630 r = FLASHD_GetLockBits(pPrivate , &v);
1631 if (r != ERROR_OK) {
1632 LOG_DEBUG("Failed: %d",r);
1633 return r;
1634 }
1635
1636 for (x = 0 ; x < pPrivate->nsectors ; x++) {
1637 bank->sectors[x].is_protected = (!!(v & (1 << x)));
1638 }
1639 LOG_DEBUG("Done");
1640 return ERROR_OK;
1641 }
1642
1643 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
1644 {
1645 struct sam3_chip *pChip;
1646
1647 pChip = all_sam3_chips;
1648
1649 // is this an existing chip?
1650 while (pChip) {
1651 if (pChip->target == bank->target) {
1652 break;
1653 }
1654 pChip = pChip->next;
1655 }
1656
1657 if (!pChip) {
1658 // this is a *NEW* chip
1659 pChip = calloc(1, sizeof(struct sam3_chip));
1660 if (!pChip) {
1661 LOG_ERROR("NO RAM!");
1662 return ERROR_FAIL;
1663 }
1664 pChip->target = bank->target;
1665 // insert at head
1666 pChip->next = all_sam3_chips;
1667 all_sam3_chips = pChip;
1668 pChip->target = bank->target;
1669 // assumption is this runs at 32khz
1670 pChip->cfg.slow_freq = 32768;
1671 pChip->probed = 0;
1672 pChip->mbuf = membuf_new();
1673 if (!(pChip->mbuf)) {
1674 LOG_ERROR("no memory");
1675 return ERROR_FAIL;
1676 }
1677 }
1678
1679 switch (bank->base) {
1680 default:
1681 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x)",
1682 ((unsigned int)(bank->base)),
1683 ((unsigned int)(FLASH_BANK0_BASE)),
1684 ((unsigned int)(FLASH_BANK1_BASE)));
1685 return ERROR_FAIL;
1686 break;
1687 case FLASH_BANK0_BASE:
1688 bank->driver_priv = &(pChip->details.bank[0]);
1689 bank->bank_number = 0;
1690 pChip->details.bank[0].pChip = pChip;
1691 pChip->details.bank[0].pBank = bank;
1692 break;
1693 case FLASH_BANK1_BASE:
1694 bank->driver_priv = &(pChip->details.bank[1]);
1695 bank->bank_number = 1;
1696 pChip->details.bank[1].pChip = pChip;
1697 pChip->details.bank[1].pBank = bank;
1698 break;
1699 }
1700
1701 // we initialize after probing.
1702 return ERROR_OK;
1703 }
1704
1705 static int
1706 sam3_GetDetails(struct sam3_bank_private *pPrivate)
1707 {
1708 const struct sam3_chip_details *pDetails;
1709 struct sam3_chip *pChip;
1710 void *vp;
1711 struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
1712
1713 unsigned x;
1714 const char *cp;
1715
1716 LOG_DEBUG("Begin");
1717 pDetails = all_sam3_details;
1718 while (pDetails->name) {
1719 if (pDetails->chipid_cidr == pPrivate->pChip->cfg.CHIPID_CIDR) {
1720 break;
1721 } else {
1722 pDetails++;
1723 }
1724 }
1725 if (pDetails->name == NULL) {
1726 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)",
1727 (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
1728 // Help the victim, print details about the chip
1729 membuf_reset(pPrivate->pChip->mbuf);
1730 membuf_sprintf(pPrivate->pChip->mbuf,
1731 "SAM3 CHIPID_CIDR: 0x%08x decodes as follows\n",
1732 pPrivate->pChip->cfg.CHIPID_CIDR);
1733 sam3_explain_chipid_cidr(pPrivate->pChip);
1734 cp = membuf_strtok(pPrivate->pChip->mbuf, "\n", &vp);
1735 while (cp) {
1736 LOG_INFO("%s", cp);
1737 cp = membuf_strtok(NULL, "\n", &vp);
1738 }
1739 return ERROR_FAIL;
1740 }
1741
1742 // DANGER: THERE ARE DRAGONS HERE
1743
1744 // get our pChip - it is going
1745 // to be over-written shortly
1746 pChip = pPrivate->pChip;
1747
1748 // Note that, in reality:
1749 //
1750 // pPrivate = &(pChip->details.bank[0])
1751 // or pPrivate = &(pChip->details.bank[1])
1752 //
1753
1754 // save the "bank" pointers
1755 for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
1756 saved_banks[ x ] = pChip->details.bank[x].pBank;
1757 }
1758
1759 // Overwrite the "details" structure.
1760 memcpy(&(pPrivate->pChip->details),
1761 pDetails,
1762 sizeof(pPrivate->pChip->details));
1763
1764 // now fix the ghosted pointers
1765 for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
1766 pChip->details.bank[x].pChip = pChip;
1767 pChip->details.bank[x].pBank = saved_banks[x];
1768 }
1769
1770 // update the *BANK*SIZE*
1771
1772 LOG_DEBUG("End");
1773 return ERROR_OK;
1774 }
1775
1776
1777
1778 static int
1779 _sam3_probe(struct flash_bank *bank, int noise)
1780 {
1781 unsigned x;
1782 int r;
1783 struct sam3_bank_private *pPrivate;
1784
1785
1786 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
1787 if (bank->target->state != TARGET_HALTED)
1788 {
1789 LOG_ERROR("Target not halted");
1790 return ERROR_TARGET_NOT_HALTED;
1791 }
1792
1793 pPrivate = get_sam3_bank_private(bank);
1794 if (!pPrivate) {
1795 LOG_ERROR("Invalid/unknown bank number\n");
1796 return ERROR_FAIL;
1797 }
1798
1799 r = sam3_ReadAllRegs(pPrivate->pChip);
1800 if (r != ERROR_OK) {
1801 return r;
1802 }
1803
1804
1805 LOG_DEBUG("Here");
1806 r = sam3_GetInfo(pPrivate->pChip);
1807 if (r != ERROR_OK) {
1808 return r;
1809 }
1810 if (!(pPrivate->pChip->probed)) {
1811 pPrivate->pChip->probed = 1;
1812 LOG_DEBUG("Here");
1813 r = sam3_GetDetails(pPrivate);
1814 if (r != ERROR_OK) {
1815 return r;
1816 }
1817 }
1818
1819 // update the flash bank size
1820 for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
1821 if (bank->base == pPrivate->pChip->details.bank[0].base_address) {
1822 bank->size = pPrivate->pChip->details.bank[0].size_bytes;
1823 break;
1824 }
1825 }
1826
1827 if (bank->sectors == NULL) {
1828 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
1829 if (bank->sectors == NULL) {
1830 LOG_ERROR("No memory!");
1831 return ERROR_FAIL;
1832 }
1833 bank->num_sectors = pPrivate->nsectors;
1834
1835 for (x = 0 ; ((int)(x)) < bank->num_sectors ; x++) {
1836 bank->sectors[x].size = pPrivate->sector_size;
1837 bank->sectors[x].offset = x * (pPrivate->sector_size);
1838 // mark as unknown
1839 bank->sectors[x].is_erased = -1;
1840 bank->sectors[x].is_protected = -1;
1841 }
1842 }
1843
1844 pPrivate->probed = 1;
1845
1846 r = sam3_protect_check(bank);
1847 if (r != ERROR_OK) {
1848 return r;
1849 }
1850
1851 LOG_DEBUG("Bank = %d, nbanks = %d",
1852 pPrivate->bank_number , pPrivate->pChip->details.n_banks);
1853 if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
1854 // read unique id,
1855 // it appears to be associated with the *last* flash bank.
1856 FLASHD_ReadUniqueID(pPrivate);
1857 }
1858
1859 return r;
1860 }
1861
1862 static int
1863 sam3_probe(struct flash_bank *bank)
1864 {
1865 return _sam3_probe(bank, 1);
1866 }
1867
1868 static int
1869 sam3_auto_probe(struct flash_bank *bank)
1870 {
1871 return _sam3_probe(bank, 0);
1872 }
1873
1874
1875
1876 static int
1877 sam3_erase(struct flash_bank *bank, int first, int last)
1878 {
1879 struct sam3_bank_private *pPrivate;
1880 int r;
1881
1882 LOG_DEBUG("Here");
1883 if (bank->target->state != TARGET_HALTED) {
1884 LOG_ERROR("Target not halted");
1885 return ERROR_TARGET_NOT_HALTED;
1886 }
1887
1888 r = sam3_auto_probe(bank);
1889 if (r != ERROR_OK) {
1890 LOG_DEBUG("Here,r=%d",r);
1891 return r;
1892 }
1893
1894 pPrivate = get_sam3_bank_private(bank);
1895 if (!(pPrivate->probed)) {
1896 return ERROR_FLASH_BANK_NOT_PROBED;
1897 }
1898
1899 if ((first == 0) && ((last + 1)== ((int)(pPrivate->nsectors)))) {
1900 // whole chip
1901 LOG_DEBUG("Here");
1902 return FLASHD_EraseEntireBank(pPrivate);
1903 }
1904 LOG_INFO("sam3 auto-erases while programing (request ignored)");
1905 return ERROR_OK;
1906 }
1907
1908 static int
1909 sam3_protect(struct flash_bank *bank, int set, int first, int last)
1910 {
1911 struct sam3_bank_private *pPrivate;
1912 int r;
1913
1914 LOG_DEBUG("Here");
1915 if (bank->target->state != TARGET_HALTED) {
1916 LOG_ERROR("Target not halted");
1917 return ERROR_TARGET_NOT_HALTED;
1918 }
1919
1920 pPrivate = get_sam3_bank_private(bank);
1921 if (!(pPrivate->probed)) {
1922 return ERROR_FLASH_BANK_NOT_PROBED;
1923 }
1924
1925 if (set) {
1926 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
1927 } else {
1928 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
1929 }
1930 LOG_DEBUG("End: r=%d",r);
1931
1932 return r;
1933
1934 }
1935
1936
1937 static int
1938 sam3_info(struct flash_bank *bank, char *buf, int buf_size)
1939 {
1940 if (bank->target->state != TARGET_HALTED) {
1941 LOG_ERROR("Target not halted");
1942 return ERROR_TARGET_NOT_HALTED;
1943 }
1944 buf[ 0 ] = 0;
1945 return ERROR_OK;
1946 }
1947
1948 static int
1949 sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
1950 {
1951 uint32_t adr;
1952 int r;
1953
1954 adr = pagenum * pPrivate->page_size;
1955 adr += adr + pPrivate->base_address;
1956
1957 r = target_read_memory(pPrivate->pChip->target,
1958 adr,
1959 4, /* THIS*MUST*BE* in 32bit values */
1960 pPrivate->page_size / 4,
1961 buf);
1962 if (r != ERROR_OK) {
1963 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x", (unsigned int)(adr));
1964 }
1965 return r;
1966 }
1967
1968 // The code below is basically this:
1969 // compiled with
1970 // arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s
1971 //
1972 // Only the *CPU* can write to the flash buffer.
1973 // the DAP cannot... so - we download this 28byte thing
1974 // Run the algorithm - (below)
1975 // to program the device
1976 //
1977 // ========================================
1978 // #include <stdint.h>
1979 //
1980 // struct foo {
1981 // uint32_t *dst;
1982 // const uint32_t *src;
1983 // int n;
1984 // volatile uint32_t *base;
1985 // uint32_t cmd;
1986 // };
1987 //
1988 //
1989 // uint32_t sam3_function(struct foo *p)
1990 // {
1991 // volatile uint32_t *v;
1992 // uint32_t *d;
1993 // const uint32_t *s;
1994 // int n;
1995 // uint32_t r;
1996 //
1997 // d = p->dst;
1998 // s = p->src;
1999 // n = p->n;
2000 //
2001 // do {
2002 // *d++ = *s++;
2003 // } while (--n)
2004 // ;
2005 //
2006 // v = p->base;
2007 //
2008 // v[ 1 ] = p->cmd;
2009 // do {
2010 // r = v[8/4];
2011 // } while (!(r&1))
2012 // ;
2013 // return r;
2014 // }
2015 // ========================================
2016
2017
2018
2019 static const uint8_t
2020 sam3_page_write_opcodes[] = {
2021 // 24 0000 0446 mov r4, r0
2022 0x04,0x46,
2023 // 25 0002 6168 ldr r1, [r4, #4]
2024 0x61,0x68,
2025 // 26 0004 0068 ldr r0, [r0, #0]
2026 0x00,0x68,
2027 // 27 0006 A268 ldr r2, [r4, #8]
2028 0xa2,0x68,
2029 // 28 @ lr needed for prologue
2030 // 29 .L2:
2031 // 30 0008 51F8043B ldr r3, [r1], #4
2032 0x51,0xf8,0x04,0x3b,
2033 // 31 000c 12F1FF32 adds r2, r2, #-1
2034 0x12,0xf1,0xff,0x32,
2035 // 32 0010 40F8043B str r3, [r0], #4
2036 0x40,0xf8,0x04,0x3b,
2037 // 33 0014 F8D1 bne .L2
2038 0xf8,0xd1,
2039 // 34 0016 E268 ldr r2, [r4, #12]
2040 0xe2,0x68,
2041 // 35 0018 2369 ldr r3, [r4, #16]
2042 0x23,0x69,
2043 // 36 001a 5360 str r3, [r2, #4]
2044 0x53,0x60,
2045 // 37 001c 0832 adds r2, r2, #8
2046 0x08,0x32,
2047 // 38 .L4:
2048 // 39 001e 1068 ldr r0, [r2, #0]
2049 0x10,0x68,
2050 // 40 0020 10F0010F tst r0, #1
2051 0x10,0xf0,0x01,0x0f,
2052 // 41 0024 FBD0 beq .L4
2053 0xfb,0xd0,
2054 // 42 .done:
2055 // 43 0026 FEE7 b .done
2056 0xfe,0xe7
2057 };
2058
2059
2060 static int
2061 sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2062 {
2063 uint32_t adr;
2064 uint32_t status;
2065 int r;
2066
2067 adr = pagenum * pPrivate->page_size;
2068 adr += (adr + pPrivate->base_address);
2069
2070 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
2071 r = target_write_memory(pPrivate->pChip->target,
2072 adr,
2073 4, /* THIS*MUST*BE* in 32bit values */
2074 pPrivate->page_size / 4,
2075 buf);
2076 if (r != ERROR_OK) {
2077 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x", (unsigned int)(adr));
2078 return r;
2079 }
2080
2081 r = EFC_PerformCommand(pPrivate,
2082 // send Erase & Write Page
2083 AT91C_EFC_FCMD_EWP,
2084 pagenum,
2085 &status);
2086
2087 if (r != ERROR_OK) {
2088 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x", (unsigned int)(adr));
2089 }
2090 if (status & (1 << 2)) {
2091 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
2092 return ERROR_FAIL;
2093 }
2094 if (status & (1 << 1)) {
2095 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
2096 return ERROR_FAIL;
2097 }
2098 return ERROR_OK;
2099 }
2100
2101
2102
2103
2104
2105 static int
2106 sam3_write(struct flash_bank *bank,
2107 uint8_t *buffer,
2108 uint32_t offset,
2109 uint32_t count)
2110 {
2111 int n;
2112 unsigned page_cur;
2113 unsigned page_end;
2114 int r;
2115 unsigned page_offset;
2116 struct sam3_bank_private *pPrivate;
2117 uint8_t *pagebuffer;
2118
2119 // incase we bail further below, set this to null
2120 pagebuffer = NULL;
2121
2122 // ignore dumb requests
2123 if (count == 0) {
2124 r = ERROR_OK;
2125 goto done;
2126 }
2127
2128 if (bank->target->state != TARGET_HALTED) {
2129 LOG_ERROR("Target not halted");
2130 r = ERROR_TARGET_NOT_HALTED;
2131 goto done;
2132 }
2133
2134 pPrivate = get_sam3_bank_private(bank);
2135 if (!(pPrivate->probed)) {
2136 r = ERROR_FLASH_BANK_NOT_PROBED;
2137 goto done;
2138 }
2139
2140
2141 if ((offset + count) > pPrivate->size_bytes) {
2142 LOG_ERROR("Flash write error - past end of bank");
2143 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2144 (unsigned int)(offset),
2145 (unsigned int)(count),
2146 (unsigned int)(pPrivate->size_bytes));
2147 r = ERROR_FAIL;
2148 goto done;
2149 }
2150
2151 pagebuffer = malloc(pPrivate->page_size);
2152 if( !pagebuffer ){
2153 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
2154 r = ERROR_FAIL;
2155 goto done;
2156 }
2157
2158 // what page do we start & end in?
2159 page_cur = offset / pPrivate->page_size;
2160 page_end = (offset + count - 1) / pPrivate->page_size;
2161
2162 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
2163 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
2164
2165 // Special case: all one page
2166 //
2167 // Otherwise:
2168 // (1) non-aligned start
2169 // (2) body pages
2170 // (3) non-aligned end.
2171
2172 // Handle special case - all one page.
2173 if (page_cur == page_end) {
2174 LOG_DEBUG("Special case, all in one page");
2175 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2176 if (r != ERROR_OK) {
2177 goto done;
2178 }
2179
2180 page_offset = (offset & (pPrivate->page_size-1));
2181 memcpy(pagebuffer + page_offset,
2182 buffer,
2183 count);
2184
2185 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2186 if (r != ERROR_OK) {
2187 goto done;
2188 }
2189 r = ERROR_OK;
2190 goto done;
2191 }
2192
2193 // non-aligned start
2194 page_offset = offset & (pPrivate->page_size - 1);
2195 if (page_offset) {
2196 LOG_DEBUG("Not-Aligned start");
2197 // read the partial
2198 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2199 if (r != ERROR_OK) {
2200 goto done;
2201 }
2202
2203 // over-write with new data
2204 n = (pPrivate->page_size - page_offset);
2205 memcpy(pagebuffer + page_offset,
2206 buffer,
2207 n);
2208
2209 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2210 if (r != ERROR_OK) {
2211 goto done;
2212 }
2213
2214 count -= n;
2215 offset += n;
2216 buffer += n;
2217 page_cur++;
2218 }
2219
2220 // intermediate large pages
2221 // also - the final *terminal*
2222 // if that terminal page is a full page
2223 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2224 (int)page_cur, (int)page_end, (unsigned int)(count));
2225
2226 while ((page_cur < page_end) &&
2227 (count >= pPrivate->page_size)) {
2228 r = sam3_page_write(pPrivate, page_cur, buffer);
2229 if (r != ERROR_OK) {
2230 goto done;
2231 }
2232 count -= pPrivate->page_size;
2233 buffer += pPrivate->page_size;
2234 page_cur += 1;
2235 }
2236
2237 // terminal partial page?
2238 if (count) {
2239 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
2240 // we have a partial page
2241 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2242 if (r != ERROR_OK) {
2243 goto done;
2244 }
2245 // data goes at start
2246 memcpy(pagebuffer, buffer, count);
2247 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2248 if (r != ERROR_OK) {
2249 goto done;
2250 }
2251 buffer += count;
2252 count -= count;
2253 }
2254 LOG_DEBUG("Done!");
2255 r = ERROR_OK;
2256 done:
2257 if( pagebuffer ){
2258 free(pagebuffer);
2259 }
2260 return r;
2261 }
2262
2263 COMMAND_HANDLER(sam3_handle_info_command)
2264 {
2265 struct sam3_chip *pChip;
2266 void *vp;
2267 const char *cp;
2268 unsigned x;
2269 int r;
2270
2271 pChip = get_current_sam3(cmd_ctx);
2272 if (!pChip) {
2273 return ERROR_OK;
2274 }
2275
2276 r = 0;
2277
2278 // bank0 must exist before we can do anything
2279 if (pChip->details.bank[0].pBank == NULL) {
2280 x = 0;
2281 need_define:
2282 command_print(cmd_ctx,
2283 "Please define bank %d via command: flash bank %s ... ",
2284 x,
2285 at91sam3_flash.name);
2286 return ERROR_FAIL;
2287 }
2288
2289 // if bank 0 is not probed, then probe it
2290 if (!(pChip->details.bank[0].probed)) {
2291 r = sam3_auto_probe(pChip->details.bank[0].pBank);
2292 if (r != ERROR_OK) {
2293 return ERROR_FAIL;
2294 }
2295 }
2296 // above garentees the "chip details" structure is valid
2297 // and thus, bank private areas are valid
2298 // and we have a SAM3 chip, what a concept!
2299
2300
2301 // auto-probe other banks, 0 done above
2302 for (x = 1 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
2303 // skip banks not present
2304 if (!(pChip->details.bank[x].present)) {
2305 continue;
2306 }
2307
2308 if (pChip->details.bank[x].pBank == NULL) {
2309 goto need_define;
2310 }
2311
2312 if (pChip->details.bank[x].probed) {
2313 continue;
2314 }
2315
2316 r = sam3_auto_probe(pChip->details.bank[x].pBank);
2317 if (r != ERROR_OK) {
2318 return r;
2319 }
2320 }
2321
2322
2323 r = sam3_GetInfo(pChip);
2324 if (r != ERROR_OK) {
2325 LOG_DEBUG("Sam3Info, Failed %d\n",r);
2326 return r;
2327 }
2328
2329
2330 // print results
2331 cp = membuf_strtok(pChip->mbuf, "\n", &vp);
2332 while (cp) {
2333 command_print(cmd_ctx,"%s", cp);
2334 cp = membuf_strtok(NULL, "\n", &vp);
2335 }
2336 return ERROR_OK;
2337 }
2338
2339 COMMAND_HANDLER(sam3_handle_gpnvm_command)
2340 {
2341 unsigned x,v;
2342 int r,who;
2343 struct sam3_chip *pChip;
2344
2345 pChip = get_current_sam3(cmd_ctx);
2346 if (!pChip) {
2347 return ERROR_OK;
2348 }
2349
2350 if (pChip->target->state != TARGET_HALTED) {
2351 LOG_ERROR("sam3 - target not halted");
2352 return ERROR_TARGET_NOT_HALTED;
2353 }
2354
2355
2356 if (pChip->details.bank[0].pBank == NULL) {
2357 command_print(cmd_ctx, "Bank0 must be defined first via: flash bank %s ...",
2358 at91sam3_flash.name);
2359 return ERROR_FAIL;
2360 }
2361 if (!pChip->details.bank[0].probed) {
2362 r = sam3_auto_probe(pChip->details.bank[0].pBank);
2363 if (r != ERROR_OK) {
2364 return r;
2365 }
2366 }
2367
2368
2369 switch (argc) {
2370 default:
2371 command_print(cmd_ctx,"Too many parameters\n");
2372 return ERROR_COMMAND_SYNTAX_ERROR;
2373 break;
2374 case 0:
2375 who = -1;
2376 goto showall;
2377 break;
2378 case 1:
2379 who = -1;
2380 break;
2381 case 2:
2382 if ((0 == strcmp(args[0], "show")) && (0 == strcmp(args[1], "all"))) {
2383 who = -1;
2384 } else {
2385 uint32_t v32;
2386 COMMAND_PARSE_NUMBER(u32, args[1], v32);
2387 who = v32;
2388 }
2389 break;
2390 }
2391
2392 if (0 == strcmp("show", args[0])) {
2393 if (who == -1) {
2394 showall:
2395 r = ERROR_OK;
2396 for (x = 0 ; x < pChip->details.n_gpnvms ; x++) {
2397 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
2398 if (r != ERROR_OK) {
2399 break;
2400 }
2401 command_print(cmd_ctx, "sam3-gpnvm%u: %u", x, v);
2402 }
2403 return r;
2404 }
2405 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
2406 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
2407 command_print(cmd_ctx, "sam3-gpnvm%u: %u", who, v);
2408 return r;
2409 } else {
2410 command_print(cmd_ctx, "sam3-gpnvm invalid GPNVM: %u", who);
2411 return ERROR_COMMAND_SYNTAX_ERROR;
2412 }
2413 }
2414
2415 if (who == -1) {
2416 command_print(cmd_ctx, "Missing GPNVM number");
2417 return ERROR_COMMAND_SYNTAX_ERROR;
2418 }
2419
2420 if (0 == strcmp("set", args[0])) {
2421 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
2422 } else if ((0 == strcmp("clr", args[0])) ||
2423 (0 == strcmp("clear", args[0]))) { // quietly accept both
2424 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
2425 } else {
2426 command_print(cmd_ctx, "Unkown command: %s", args[0]);
2427 r = ERROR_COMMAND_SYNTAX_ERROR;
2428 }
2429 return r;
2430 }
2431
2432 COMMAND_HANDLER(sam3_handle_slowclk_command)
2433 {
2434 struct sam3_chip *pChip;
2435
2436 pChip = get_current_sam3(cmd_ctx);
2437 if (!pChip) {
2438 return ERROR_OK;
2439 }
2440
2441
2442 switch (argc) {
2443 case 0:
2444 // show
2445 break;
2446 case 1:
2447 {
2448 // set
2449 uint32_t v;
2450 COMMAND_PARSE_NUMBER(u32, args[0], v);
2451 if (v > 200000) {
2452 // absurd slow clock of 200Khz?
2453 command_print(cmd_ctx,"Absurd/illegal slow clock freq: %d\n", (int)(v));
2454 return ERROR_COMMAND_SYNTAX_ERROR;
2455 }
2456 pChip->cfg.slow_freq = v;
2457 break;
2458 }
2459 default:
2460 // error
2461 command_print(cmd_ctx,"Too many parameters");
2462 return ERROR_COMMAND_SYNTAX_ERROR;
2463 break;
2464 }
2465 command_print(cmd_ctx, "Slowclk freq: %d.%03dkhz",
2466 (int)(pChip->cfg.slow_freq/ 1000),
2467 (int)(pChip->cfg.slow_freq% 1000));
2468 return ERROR_OK;
2469 }
2470
2471
2472 static int sam3_registered;
2473 static int
2474 sam3_register_commands(struct command_context *cmd_ctx)
2475 {
2476 struct command *pCmd;
2477
2478 // only register once
2479 if (!sam3_registered) {
2480 sam3_registered++;
2481
2482 pCmd = register_command(cmd_ctx, NULL, "at91sam3", NULL, COMMAND_ANY, NULL);
2483 register_command(cmd_ctx, pCmd,
2484 "gpnvm",
2485 sam3_handle_gpnvm_command,
2486 COMMAND_EXEC,
2487 "at91sam3 gpnvm [action [<BIT>], by default 'show', otherwise set | clear BIT");
2488 register_command(cmd_ctx, pCmd,
2489 "info",
2490 sam3_handle_info_command,
2491 COMMAND_EXEC,
2492 "at91sam3 info - print information about the current sam3 chip");
2493 register_command(cmd_ctx, pCmd,
2494 "slowclk",
2495 sam3_handle_slowclk_command,
2496 COMMAND_EXEC,
2497 "at91sam3 slowclk [VALUE] set the slowclock frequency (default 32768hz)");
2498 }
2499 return ERROR_OK;
2500 }
2501
2502 struct flash_driver at91sam3_flash = {
2503 .name = "at91sam3",
2504 .register_commands = &sam3_register_commands,
2505 .flash_bank_command = &sam3_flash_bank_command,
2506 .erase = &sam3_erase,
2507 .protect = &sam3_protect,
2508 .write = &sam3_write,
2509 .probe = &sam3_probe,
2510 .auto_probe = &sam3_auto_probe,
2511 .erase_check = &sam3_erase_check,
2512 .protect_check = &sam3_protect_check,
2513 .info = &sam3_info,
2514 };
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